imply BITREVERSE
select BLOBLIST
imply CMD_DM
+ imply CMD_EXCEPTION
imply CMD_GETTIME
imply CMD_HASH
imply CMD_IO
};
/* Information about a GPIO bank */
-struct hikey_gpio_platdata {
+struct hikey_gpio_plat {
int bank_index;
ulong base; /* address of registers in physical memory */
};
#include <asm/arch/sci/types.h>
-struct imx8_power_domain_platdata {
+struct imx8_power_domain_plat {
sc_rsrc_t resource_id;
};
#ifndef _ASM_ARCH_IMX8M_POWER_DOMAIN_H
#define _ASM_ARCH_IMX8M_POWER_DOMAIN_H
-struct imx8m_power_domain_platdata {
+struct imx8m_power_domain_plat {
int resource_id;
int has_pd;
struct power_domain pd;
u32 gpio_pdir;
};
-struct vybrid_gpio_platdata {
+struct vybrid_gpio_plat {
unsigned int chip;
u32 base;
const char *port_name;
#if CONFIG_IS_ENABLED(DM_GPIO)
/* Information about a GPIO bank */
-struct omap_gpio_platdata {
+struct omap_gpio_plat {
int bank_index;
ulong base; /* address of registers in physical memory */
const char *port_name;
#ifdef CONFIG_DM_I2C
/* Information about a GPIO bank */
-struct omap_i2c_platdata {
+struct omap_i2c_plat {
ulong base; /* address of registers in physical memory */
int speed;
int ip_rev;
enum musb_interface {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI};
-struct ti_musb_platdata {
+struct ti_musb_plat {
void *base;
void *ctrl_mod_base;
struct musb_hdrc_platform_data plat;
}
/* Platform data for the GPIOs */
-static const struct at91_port_platdata at91sam9260_plat[] = {
+static const struct at91_port_plat at91sam9260_plat[] = {
{ ATMEL_BASE_PIOA, "PA" },
{ ATMEL_BASE_PIOB, "PB" },
{ ATMEL_BASE_PIOC, "PC" },
#endif
/* Platform data for the GPIOs */
-static const struct at91_port_platdata at91sam9260_plat[] = {
+static const struct at91_port_plat at91sam9260_plat[] = {
{ ATMEL_BASE_PIOA, "PA" },
{ ATMEL_BASE_PIOB, "PB" },
{ ATMEL_BASE_PIOC, "PC" },
#define _ATMEL_SERIAL_H
/* Information about a serial port */
-struct atmel_serial_platdata {
+struct atmel_serial_plat {
uint32_t base_addr;
};
}
/* Platform data for each GPIO port */
-struct at91_port_platdata {
+struct at91_port_plat {
uint32_t base_addr;
const char *bank_name;
};
};
/**
- * struct bcm2835_gpio_platdata - GPIO platform description
+ * struct bcm2835_gpio_plat - GPIO platform description
*
* @base: Base address of GPIO controller
*/
-struct bcm2835_gpio_platdata {
+struct bcm2835_gpio_plat {
unsigned long base;
};
U_BOOT_DEVICE(imx6_thermal) = {
.name = "imx_thermal",
- .platdata = &imx6_thermal_plat,
+ .plat = &imx6_thermal_plat,
};
#endif
U_BOOT_DEVICE(imx7_thermal) = {
.name = "imx_thermal",
- .platdata = &imx7_thermal_plat,
+ .plat = &imx7_thermal_plat,
};
#endif
.id = UCLASS_CLK,
.of_match = msm_clk_ids,
.ops = &msm_clk_ops,
- .priv_auto_alloc_size = sizeof(struct msm_clk_priv),
+ .priv_auto = sizeof(struct msm_clk_priv),
.probe = msm_clk_probe,
};
.name = "pinctrl_msm",
.id = UCLASS_PINCTRL,
.of_match = msm_pinctrl_ids,
- .priv_auto_alloc_size = sizeof(struct msm_pinctrl_priv),
+ .priv_auto = sizeof(struct msm_pinctrl_priv),
.ops = &msm_pinctrl_ops,
.probe = msm_pinctrl_probe,
};
}
#if !CONFIG_IS_ENABLED(OF_CONTROL)
-static const struct ns16550_platdata lpc32xx_uart[] = {
+static const struct ns16550_plat lpc32xx_uart[] = {
{ .base = UART3_BASE, .reg_shift = 2,
.clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
{ .base = UART4_BASE, .reg_shift = 2,
};
#if defined(CONFIG_LPC32XX_HSUART)
-static const struct lpc32xx_hsuart_platdata lpc32xx_hsuart[] = {
+static const struct lpc32xx_hsuart_plat lpc32xx_hsuart[] = {
{ HS_UART1_BASE, },
{ HS_UART2_BASE, },
{ HS_UART7_BASE, },
};
/* platform data for the driver model */
-struct nx_display_platdata {
+struct nx_display_plat {
int module;
struct dp_sync_info sync;
struct dp_ctrl_info ctrl;
#if defined CONFIG_SPL_BUILD || \
(!defined(CONFIG_DM) && !defined(CONFIG_OF_CONTROL))
-int nx_display_probe(struct nx_display_platdata *plat);
+int nx_display_probe(struct nx_display_plat *plat);
#endif
#endif
}
#if !CONFIG_IS_ENABLED(OF_CONTROL)
-static const struct ns16550_platdata am33xx_serial[] = {
+static const struct ns16550_plat am33xx_serial[] = {
{ .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2,
.clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
# ifdef CONFIG_SYS_NS16550_COM2
};
#ifdef CONFIG_DM_I2C
-static const struct omap_i2c_platdata am33xx_i2c[] = {
+static const struct omap_i2c_plat am33xx_i2c[] = {
{ I2C_BASE1, 100000, OMAP_I2C_REV_V2},
{ I2C_BASE2, 100000, OMAP_I2C_REV_V2},
{ I2C_BASE3, 100000, OMAP_I2C_REV_V2},
#endif
#if CONFIG_IS_ENABLED(DM_GPIO)
-static const struct omap_gpio_platdata am33xx_gpio[] = {
+static const struct omap_gpio_plat am33xx_gpio[] = {
{ 0, AM33XX_GPIO0_BASE },
{ 1, AM33XX_GPIO1_BASE },
{ 2, AM33XX_GPIO2_BASE },
U_BOOT_DEVICE(am33xx_spi) = {
.name = "omap3_spi",
- .platdata = &omap3_spi_pdata,
+ .plat = &omap3_spi_pdata,
};
#endif
#endif
};
#if CONFIG_IS_ENABLED(DM_USB) && !CONFIG_IS_ENABLED(OF_CONTROL)
-static struct ti_musb_platdata usb0 = {
+static struct ti_musb_plat usb0 = {
.base = (void *)USB0_OTG_BASE,
.ctrl_mod_base = &((struct ctrl_dev *)CTRL_DEVICE_BASE)->usb_ctrl0,
.plat = {
},
};
-static struct ti_musb_platdata usb1 = {
+static struct ti_musb_plat usb1 = {
.base = (void *)USB1_OTG_BASE,
.ctrl_mod_base = &((struct ctrl_dev *)CTRL_DEVICE_BASE)->usb_ctrl1,
.plat = {
#if CONFIG_IS_ENABLED(DM_GPIO)
#if !CONFIG_IS_ENABLED(OF_CONTROL)
/* Manually initialize GPIO banks when OF_CONTROL doesn't */
-static const struct omap_gpio_platdata omap34xx_gpio[] = {
+static const struct omap_gpio_plat omap34xx_gpio[] = {
{ 0, OMAP34XX_GPIO1_BASE },
{ 1, OMAP34XX_GPIO2_BASE },
{ 2, OMAP34XX_GPIO3_BASE },
};
#if CONFIG_IS_ENABLED(OF_PLATDATA)
-static int px30_syscon_bind_of_platdata(struct udevice *dev)
+static int px30_syscon_bind_of_plat(struct udevice *dev)
{
dev->driver_data = dev->driver->of_match->data;
debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
.name = "rockchip_px30_pmu",
.id = UCLASS_SYSCON,
.of_match = px30_syscon_ids,
- .bind = px30_syscon_bind_of_platdata,
+ .bind = px30_syscon_bind_of_plat,
};
U_BOOT_DRIVER(rockchip_px30_pmugrf) = {
.name = "rockchip_px30_pmugrf",
.id = UCLASS_SYSCON,
.of_match = px30_syscon_ids + 1,
- .bind = px30_syscon_bind_of_platdata,
+ .bind = px30_syscon_bind_of_plat,
};
U_BOOT_DRIVER(rockchip_px30_grf) = {
.name = "rockchip_px30_grf",
.id = UCLASS_SYSCON,
.of_match = px30_syscon_ids + 2,
- .bind = px30_syscon_bind_of_platdata,
+ .bind = px30_syscon_bind_of_plat,
};
#endif
};
#if CONFIG_IS_ENABLED(OF_PLATDATA)
-static int rk3188_syscon_bind_of_platdata(struct udevice *dev)
+static int rk3188_syscon_bind_of_plat(struct udevice *dev)
{
dev->driver_data = dev->driver->of_match->data;
debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
.name = "rockchip_rk3188_noc",
.id = UCLASS_SYSCON,
.of_match = rk3188_syscon_ids,
- .bind = rk3188_syscon_bind_of_platdata,
+ .bind = rk3188_syscon_bind_of_plat,
};
U_BOOT_DRIVER(rockchip_rk3188_grf) = {
.name = "rockchip_rk3188_grf",
.id = UCLASS_SYSCON,
.of_match = rk3188_syscon_ids + 1,
- .bind = rk3188_syscon_bind_of_platdata,
+ .bind = rk3188_syscon_bind_of_plat,
};
U_BOOT_DRIVER(rockchip_rk3188_pmu) = {
.name = "rockchip_rk3188_pmu",
.id = UCLASS_SYSCON,
.of_match = rk3188_syscon_ids + 2,
- .bind = rk3188_syscon_bind_of_platdata,
+ .bind = rk3188_syscon_bind_of_plat,
};
#endif
};
#if CONFIG_IS_ENABLED(OF_PLATDATA)
-static int rk3288_syscon_bind_of_platdata(struct udevice *dev)
+static int rk3288_syscon_bind_of_plat(struct udevice *dev)
{
dev->driver_data = dev->driver->of_match->data;
debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
.name = "rockchip_rk3288_noc",
.id = UCLASS_SYSCON,
.of_match = rk3288_syscon_ids,
- .bind = rk3288_syscon_bind_of_platdata,
+ .bind = rk3288_syscon_bind_of_plat,
};
U_BOOT_DRIVER(rockchip_rk3288_grf) = {
.name = "rockchip_rk3288_grf",
.id = UCLASS_SYSCON,
.of_match = rk3288_syscon_ids + 1,
- .bind = rk3288_syscon_bind_of_platdata,
+ .bind = rk3288_syscon_bind_of_plat,
};
U_BOOT_DRIVER(rockchip_rk3288_sgrf) = {
.name = "rockchip_rk3288_sgrf",
.id = UCLASS_SYSCON,
.of_match = rk3288_syscon_ids + 2,
- .bind = rk3288_syscon_bind_of_platdata,
+ .bind = rk3288_syscon_bind_of_plat,
};
U_BOOT_DRIVER(rockchip_rk3288_pmu) = {
.name = "rockchip_rk3288_pmu",
.id = UCLASS_SYSCON,
.of_match = rk3288_syscon_ids + 3,
- .bind = rk3288_syscon_bind_of_platdata,
+ .bind = rk3288_syscon_bind_of_plat,
};
#endif
};
#if CONFIG_IS_ENABLED(OF_PLATDATA)
-static int rk3368_syscon_bind_of_platdata(struct udevice *dev)
+static int rk3368_syscon_bind_of_plat(struct udevice *dev)
{
dev->driver_data = dev->driver->of_match->data;
debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
.name = "rockchip_rk3368_grf",
.id = UCLASS_SYSCON,
.of_match = rk3368_syscon_ids,
- .bind = rk3368_syscon_bind_of_platdata,
+ .bind = rk3368_syscon_bind_of_plat,
};
U_BOOT_DRIVER(rockchip_rk3368_pmugrf) = {
.name = "rockchip_rk3368_pmugrf",
.id = UCLASS_SYSCON,
.of_match = rk3368_syscon_ids + 1,
- .bind = rk3368_syscon_bind_of_platdata,
+ .bind = rk3368_syscon_bind_of_plat,
};
U_BOOT_DRIVER(rockchip_rk3368_msch) = {
.name = "rockchip_rk3368_msch",
.id = UCLASS_SYSCON,
.of_match = rk3368_syscon_ids + 2,
- .bind = rk3368_syscon_bind_of_platdata,
+ .bind = rk3368_syscon_bind_of_plat,
};
U_BOOT_DRIVER(rockchip_rk3368_sgrf) = {
.name = "rockchip_rk3368_sgrf",
.id = UCLASS_SYSCON,
.of_match = rk3368_syscon_ids + 3,
- .bind = rk3368_syscon_bind_of_platdata,
+ .bind = rk3368_syscon_bind_of_plat,
};
#endif
};
#if CONFIG_IS_ENABLED(OF_PLATDATA)
-static int rk3399_syscon_bind_of_platdata(struct udevice *dev)
+static int rk3399_syscon_bind_of_plat(struct udevice *dev)
{
dev->driver_data = dev->driver->of_match->data;
debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
.name = "rockchip_rk3399_grf",
.id = UCLASS_SYSCON,
.of_match = rk3399_syscon_ids,
- .bind = rk3399_syscon_bind_of_platdata,
+ .bind = rk3399_syscon_bind_of_plat,
};
U_BOOT_DRIVER(rockchip_rk3399_pmugrf) = {
.name = "rockchip_rk3399_pmugrf",
.id = UCLASS_SYSCON,
.of_match = rk3399_syscon_ids + 1,
- .bind = rk3399_syscon_bind_of_platdata,
+ .bind = rk3399_syscon_bind_of_plat,
};
U_BOOT_DRIVER(rockchip_rk3399_pmusgrf) = {
.name = "rockchip_rk3399_pmusgrf",
.id = UCLASS_SYSCON,
.of_match = rk3399_syscon_ids + 2,
- .bind = rk3399_syscon_bind_of_platdata,
+ .bind = rk3399_syscon_bind_of_plat,
};
U_BOOT_DRIVER(rockchip_rk3399_cic) = {
.name = "rockchip_rk3399_cic",
.id = UCLASS_SYSCON,
.of_match = rk3399_syscon_ids + 3,
- .bind = rk3399_syscon_bind_of_platdata,
+ .bind = rk3399_syscon_bind_of_plat,
};
U_BOOT_DRIVER(rockchip_rk3399_pmu) = {
.name = "rockchip_rk3399_pmu",
.id = UCLASS_SYSCON,
.of_match = rk3399_syscon_ids + 4,
- .bind = rk3399_syscon_bind_of_platdata,
+ .bind = rk3399_syscon_bind_of_plat,
};
#endif
dev;
device_find_next_child(&dev)) {
if (device_get_uclass_id(dev) == UCLASS_BLK) {
- desc = dev_get_uclass_platdata(dev);
+ desc = dev_get_uclass_plat(dev);
break;
}
}
void board_boot_order(u32 *spl_boot_list)
{
- /* In case of no fdt (or only platdata), use spl_boot_device() */
+ /* In case of no fdt (or only plat), use spl_boot_device() */
if (!CONFIG_IS_ENABLED(OF_CONTROL) || CONFIG_IS_ENABLED(OF_PLATDATA)) {
spl_boot_list[0] = spl_boot_device();
return;
.id = UCLASS_CLK,
.of_match = msm_clk_ids,
.ops = &msm_clk_ops,
- .priv_auto_alloc_size = sizeof(struct msm_clk_priv),
+ .priv_auto = sizeof(struct msm_clk_priv),
.probe = msm_clk_probe,
};
.name = "pinctrl_msm",
.id = UCLASS_PINCTRL,
.of_match = msm_pinctrl_ids,
- .priv_auto_alloc_size = sizeof(struct msm_pinctrl_priv),
+ .priv_auto = sizeof(struct msm_pinctrl_priv),
.ops = &msm_pinctrl_ops,
.probe = msm_pinctrl_probe,
};
}
/* BSEC MISC driver *******************************************************/
-struct stm32mp_bsec_platdata {
+struct stm32mp_bsec_plat {
u32 base;
};
static int stm32mp_bsec_read_otp(struct udevice *dev, u32 *val, u32 otp)
{
- struct stm32mp_bsec_platdata *plat;
+ struct stm32mp_bsec_plat *plat;
u32 tmp_data = 0;
int ret;
STM32_SMC_READ_OTP,
otp, 0, val);
- plat = dev_get_platdata(dev);
+ plat = dev_get_plat(dev);
/* read current shadow value */
ret = bsec_read_shadow(plat->base, &tmp_data, otp);
static int stm32mp_bsec_read_shadow(struct udevice *dev, u32 *val, u32 otp)
{
- struct stm32mp_bsec_platdata *plat;
+ struct stm32mp_bsec_plat *plat;
if (IS_ENABLED(CONFIG_TFABOOT))
return stm32_smc(STM32_SMC_BSEC,
STM32_SMC_READ_SHADOW,
otp, 0, val);
- plat = dev_get_platdata(dev);
+ plat = dev_get_plat(dev);
return bsec_read_shadow(plat->base, val, otp);
}
static int stm32mp_bsec_read_lock(struct udevice *dev, u32 *val, u32 otp)
{
- struct stm32mp_bsec_platdata *plat = dev_get_platdata(dev);
+ struct stm32mp_bsec_plat *plat = dev_get_plat(dev);
/* return OTP permanent write lock status */
*val = bsec_read_lock(plat->base + BSEC_WRLOCK_OFF, otp);
static int stm32mp_bsec_write_otp(struct udevice *dev, u32 val, u32 otp)
{
- struct stm32mp_bsec_platdata *plat;
+ struct stm32mp_bsec_plat *plat;
if (IS_ENABLED(CONFIG_TFABOOT))
return stm32_smc_exec(STM32_SMC_BSEC,
STM32_SMC_PROG_OTP,
otp, val);
- plat = dev_get_platdata(dev);
+ plat = dev_get_plat(dev);
return bsec_program_otp(plat->base, val, otp);
static int stm32mp_bsec_write_shadow(struct udevice *dev, u32 val, u32 otp)
{
- struct stm32mp_bsec_platdata *plat;
+ struct stm32mp_bsec_plat *plat;
if (IS_ENABLED(CONFIG_TFABOOT))
return stm32_smc_exec(STM32_SMC_BSEC,
STM32_SMC_WRITE_SHADOW,
otp, val);
- plat = dev_get_platdata(dev);
+ plat = dev_get_plat(dev);
return bsec_write_shadow(plat->base, val, otp);
}
.write = stm32mp_bsec_write,
};
-static int stm32mp_bsec_ofdata_to_platdata(struct udevice *dev)
+static int stm32mp_bsec_of_to_plat(struct udevice *dev)
{
- struct stm32mp_bsec_platdata *plat = dev_get_platdata(dev);
+ struct stm32mp_bsec_plat *plat = dev_get_plat(dev);
plat->base = (u32)dev_read_addr_ptr(dev);
static int stm32mp_bsec_probe(struct udevice *dev)
{
int otp;
- struct stm32mp_bsec_platdata *plat;
+ struct stm32mp_bsec_plat *plat;
/*
* update unlocked shadow for OTP cleared by the rom code
*/
if (!IS_ENABLED(CONFIG_TFABOOT) && !IS_ENABLED(CONFIG_SPL_BUILD)) {
- plat = dev_get_platdata(dev);
+ plat = dev_get_plat(dev);
for (otp = 57; otp <= BSEC_OTP_MAX_VALUE; otp++)
if (!bsec_read_SR_lock(plat->base, otp))
.name = "stm32mp_bsec",
.id = UCLASS_MISC,
.of_match = stm32mp_bsec_ids,
- .ofdata_to_platdata = stm32mp_bsec_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct stm32mp_bsec_platdata),
+ .of_to_plat = stm32mp_bsec_of_to_plat,
+ .plat_auto = sizeof(struct stm32mp_bsec_plat),
.ops = &stm32mp_bsec_ops,
.probe = stm32mp_bsec_probe,
};
bool bsec_dbgswenable(void)
{
struct udevice *dev;
- struct stm32mp_bsec_platdata *plat;
+ struct stm32mp_bsec_plat *plat;
int ret;
ret = uclass_get_device_by_driver(UCLASS_MISC,
return false;
}
- plat = dev_get_platdata(dev);
+ plat = dev_get_plat(dev);
if (readl(plat->base + BSEC_DENABLE_OFF) & BSEC_DENABLE_DBGSWENABLE)
return true;
return 0;
}
-static int stm32mp_pwr_ofdata_to_platdata(struct udevice *dev)
+static int stm32mp_pwr_of_to_plat(struct udevice *dev)
{
struct stm32mp_pwr_priv *priv = dev_get_priv(dev);
.of_match = stm32mp_pwr_ids,
.bind = stm32mp_pwr_bind,
.ops = &stm32mp_pwr_ops,
- .ofdata_to_platdata = stm32mp_pwr_ofdata_to_platdata,
- .priv_auto_alloc_size = sizeof(struct stm32mp_pwr_priv),
+ .of_to_plat = stm32mp_pwr_of_to_plat,
+ .priv_auto = sizeof(struct stm32mp_pwr_priv),
};
static const struct stm32mp_pwr_reg_info stm32mp_pwr_reg11 = {
static int stm32mp_pwr_regulator_probe(struct udevice *dev)
{
const struct stm32mp_pwr_reg_info **p = stm32mp_pwr_reg_infos;
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
while (*p) {
int rc;
static int stm32mp_pwr_regulator_set_value(struct udevice *dev, int uV)
{
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
if (!uc_pdata)
return -ENXIO;
static int stm32mp_pwr_regulator_get_value(struct udevice *dev)
{
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
if (!uc_pdata)
return -ENXIO;
}
#if !CONFIG_IS_ENABLED(OF_CONTROL)
-static struct ns16550_platdata ns16550_com1_pdata = {
+static struct ns16550_plat ns16550_com1_pdata = {
.base = CONFIG_SYS_NS16550_COM1,
.reg_shift = 2,
.clock = CONFIG_SYS_NS16550_CLK,
};
/* Details about a GPIO bank */
-struct sifive_gpio_platdata {
+struct sifive_gpio_plat {
void *base; /* address of registers in physical memory */
};
};
/* Details about a GPIO bank */
-struct sifive_gpio_platdata {
+struct sifive_gpio_plat {
void *base; /* address of registers in physical memory */
};
endchoice
+config SANDBOX_CRASH_RESET
+ bool "Reset on crash"
+ help
+ If an illegal instruction or an illegal memory access occurs, the
+ sandbox by default writes a crash dump and exits. If you set this
+ flag, the sandbox is reset instead. This may be useful when running
+ test suites like the UEFI self certification test which continue
+ with the next test after a crash.
+
config SANDBOX_BITS_PER_LONG
int
default 32 if HOST_32BIT
* Copyright (c) 2011 The Chromium OS Authors.
*/
+#define _GNU_SOURCE
+
#include <dirent.h>
#include <errno.h>
#include <fcntl.h>
#include <string.h>
#include <termios.h>
#include <time.h>
+#include <ucontext.h>
#include <unistd.h>
#include <sys/mman.h>
#include <sys/stat.h>
#include <sys/time.h>
#include <sys/types.h>
+#include <linux/compiler_attributes.h>
#include <linux/types.h>
#include <asm/getopt.h>
raise(SIGINT);
}
+static void os_signal_handler(int sig, siginfo_t *info, void *con)
+{
+ ucontext_t __maybe_unused *context = con;
+ unsigned long pc;
+
+#if defined(__x86_64__)
+ pc = context->uc_mcontext.gregs[REG_RIP];
+#elif defined(__aarch64__)
+ pc = context->uc_mcontext.pc;
+#elif defined(__riscv)
+ pc = context->uc_mcontext.__gregs[REG_PC];
+#else
+ const char msg[] =
+ "\nUnsupported architecture, cannot read program counter\n";
+
+ os_write(1, msg, sizeof(msg));
+ pc = 0;
+#endif
+
+ os_signal_action(sig, pc);
+}
+
+int os_setup_signal_handlers(void)
+{
+ struct sigaction act;
+
+ act.sa_sigaction = os_signal_handler;
+ sigemptyset(&act.sa_mask);
+ act.sa_flags = SA_SIGINFO | SA_NODEFER;
+ if (sigaction(SIGILL, &act, NULL) ||
+ sigaction(SIGBUS, &act, NULL) ||
+ sigaction(SIGSEGV, &act, NULL))
+ return -1;
+ return 0;
+}
+
/* Put tty into raw mode so <tab> and <ctrl+c> work */
void os_tty_raw(int fd, bool allow_sigs)
{
if (ret)
goto err;
+ ret = os_setup_signal_handlers();
+ if (ret)
+ goto err;
+
#if CONFIG_VAL(SYS_MALLOC_F_LEN)
gd->malloc_base = CONFIG_MALLOC_F_ADDR;
#endif
*/
#include <common.h>
+#include <efi_loader.h>
#include <irq_func.h>
+#include <os.h>
+#include <asm-generic/signal.h>
+#include <asm/u-boot-sandbox.h>
+
+DECLARE_GLOBAL_DATA_PTR;
int interrupt_init(void)
{
{
return 0;
}
+
+void os_signal_action(int sig, unsigned long pc)
+{
+ efi_restore_gd();
+
+ switch (sig) {
+ case SIGILL:
+ printf("\nIllegal instruction\n");
+ break;
+ case SIGBUS:
+ printf("\nBus error\n");
+ break;
+ case SIGSEGV:
+ printf("\nSegmentation violation\n");
+ break;
+ default:
+ break;
+ }
+ printf("pc = 0x%lx, ", pc);
+ printf("pc_reloc = 0x%lx\n\n", pc - gd->reloc_off);
+ efi_print_image_infos((void *)pc);
+
+ if (IS_ENABLED(CONFIG_SANDBOX_CRASH_RESET)) {
+ printf("resetting ...\n\n");
+ sandbox_reset();
+ } else {
+ sandbox_exit();
+ }
+}
return ret;
}
-static int acpi_gpe_ofdata_to_platdata(struct udevice *dev)
+static int acpi_gpe_of_to_plat(struct udevice *dev)
{
struct acpi_gpe_priv *priv = dev_get_priv(dev);
.id = UCLASS_IRQ,
.of_match = acpi_gpe_ids,
.ops = &acpi_gpe_ops,
- .ofdata_to_platdata = acpi_gpe_ofdata_to_platdata,
- .priv_auto_alloc_size = sizeof(struct acpi_gpe_priv),
+ .of_to_plat = acpi_gpe_of_to_plat,
+ .priv_auto = sizeof(struct acpi_gpe_priv),
};
};
/**
- * struct apl_hostbridge_platdata - platform data for hostbridge
+ * struct apl_hostbridge_plat - platform data for hostbridge
*
* @dtplat: Platform data for of-platdata
* @early_pads: Early pad data to set up, each (pad, cfg0, cfg1)
* @pciex_region_size: BAR length in bytes
* @bdf: Bus/device/function of hostbridge
*/
-struct apl_hostbridge_platdata {
+struct apl_hostbridge_plat {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct dtd_intel_apl_hostbridge dtplat;
#endif
static int apl_hostbridge_early_init_pinctrl(struct udevice *dev)
{
- struct apl_hostbridge_platdata *plat = dev_get_platdata(dev);
+ struct apl_hostbridge_plat *plat = dev_get_plat(dev);
struct udevice *pinctrl;
int ret;
static int apl_hostbridge_early_init(struct udevice *dev)
{
- struct apl_hostbridge_platdata *plat = dev_get_platdata(dev);
+ struct apl_hostbridge_plat *plat = dev_get_plat(dev);
u32 region_size;
ulong base;
u32 reg;
return 0;
}
-static int apl_hostbridge_ofdata_to_platdata(struct udevice *dev)
+static int apl_hostbridge_of_to_plat(struct udevice *dev)
{
- struct apl_hostbridge_platdata *plat = dev_get_platdata(dev);
+ struct apl_hostbridge_plat *plat = dev_get_plat(dev);
struct udevice *pinctrl;
int ret;
.name = "intel_apl_hostbridge",
.id = UCLASS_NORTHBRIDGE,
.of_match = apl_hostbridge_ids,
- .ofdata_to_platdata = apl_hostbridge_ofdata_to_platdata,
+ .of_to_plat = apl_hostbridge_of_to_plat,
.probe = apl_hostbridge_probe,
.remove = apl_hostbridge_remove,
- .platdata_auto_alloc_size = sizeof(struct apl_hostbridge_platdata),
+ .plat_auto = sizeof(struct apl_hostbridge_plat),
ACPI_OPS_PTR(&apl_hostbridge_acpi_ops)
.flags = DM_FLAG_OS_PREPARE,
};
CF9_GLB_RST = 1 << 20,
};
-struct apl_pmc_platdata {
+struct apl_pmc_plat {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct dtd_intel_apl_pmc dtplat;
#endif
return 0;
}
-int apl_pmc_ofdata_to_uc_platdata(struct udevice *dev)
+int apl_pmc_ofdata_to_uc_plat(struct udevice *dev)
{
struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
- struct apl_pmc_platdata *plat = dev_get_platdata(dev);
+ struct apl_pmc_plat *plat = dev_get_plat(dev);
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
u32 base[6];
if (ret)
return log_msg_ret("Bad gpe0-dw", ret);
- return pmc_ofdata_to_uc_platdata(dev);
+ return pmc_ofdata_to_uc_plat(dev);
#else
struct dtd_intel_apl_pmc *dtplat = &plat->dtplat;
static int enable_pmcbar(struct udevice *dev)
{
struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
- struct apl_pmc_platdata *priv = dev_get_platdata(dev);
+ struct apl_pmc_plat *priv = dev_get_plat(dev);
pci_dev_t pmc = priv->bdf;
/*
.name = "intel_apl_pmc",
.id = UCLASS_ACPI_PMC,
.of_match = apl_pmc_ids,
- .ofdata_to_platdata = apl_pmc_ofdata_to_uc_platdata,
+ .of_to_plat = apl_pmc_ofdata_to_uc_plat,
.probe = apl_pmc_probe,
.ops = &apl_pmc_ops,
- .platdata_auto_alloc_size = sizeof(struct apl_pmc_platdata),
+ .plat_auto = sizeof(struct apl_pmc_plat),
};
/*
* Manually set the parent of the SPI flash to SPI, since dtoc doesn't. We also
- * need to allocate the parent_platdata since by the time this function is
+ * need to allocate the parent_plat since by the time this function is
* called device_bind() has already gone past that step.
*/
static int apl_flash_bind(struct udevice *dev)
{
if (CONFIG_IS_ENABLED(OF_PLATDATA) &&
!CONFIG_IS_ENABLED(OF_PLATDATA_PARENT)) {
- struct dm_spi_slave_platdata *plat;
+ struct dm_spi_slave_plat *plat;
struct udevice *spi;
int ret;
plat = calloc(sizeof(*plat), 1);
if (!plat)
return -ENOMEM;
- dev->parent_platdata = plat;
+ dev->parent_plat = plat;
}
return 0;
.of_match = apl_flash_ids,
.bind = apl_flash_bind,
.probe = apl_flash_probe,
- .priv_auto_alloc_size = sizeof(struct spi_flash),
+ .priv_auto = sizeof(struct spi_flash),
.ops = &apl_flash_ops,
};
* This driver uses its own compatible string but almost everything else from
* the standard ns16550 driver. This allows us to provide an of-platdata
* implementation, since the platdata produced by of-platdata does not match
- * struct ns16550_platdata.
+ * struct ns16550_plat.
*
* When running with of-platdata (generally TPL), the platdata is converted to
* something that ns16550 expects. When running withoutof-platdata (SPL, U-Boot
- * proper), we use ns16550's ofdata_to_platdata routine.
+ * proper), we use ns16550's of_to_plat routine.
*/
static int apl_ns16550_probe(struct udevice *dev)
{
- struct ns16550_platdata *plat = dev_get_platdata(dev);
+ struct ns16550_plat *plat = dev_get_plat(dev);
if (!CONFIG_IS_ENABLED(PCI))
apl_uart_init(plat->bdf, plat->base);
return ns16550_serial_probe(dev);
}
-static int apl_ns16550_ofdata_to_platdata(struct udevice *dev)
+static int apl_ns16550_of_to_plat(struct udevice *dev)
{
#if CONFIG_IS_ENABLED(OF_PLATDATA)
- struct dtd_intel_apl_ns16550 *dtplat = dev_get_platdata(dev);
- struct ns16550_platdata *plat;
+ struct dtd_intel_apl_ns16550 *dtplat = dev_get_plat(dev);
+ struct ns16550_plat *plat;
/*
- * Convert our platdata to the ns16550's platdata, so we can just use
+ * Convert our plat to the ns16550's plat, so we can just use
* that driver
*/
plat = malloc(sizeof(*plat));
plat->clock = dtplat->clock_frequency;
plat->fcr = UART_FCR_DEFVAL;
plat->bdf = pci_ofplat_get_devfn(dtplat->reg[0]);
- dev->platdata = plat;
+ dev->plat = plat;
#else
int ret;
- ret = ns16550_serial_ofdata_to_platdata(dev);
+ ret = ns16550_serial_of_to_plat(dev);
if (ret)
return ret;
#endif /* OF_PLATDATA */
.name = "intel_apl_ns16550",
.id = UCLASS_SERIAL,
.of_match = apl_ns16550_serial_ids,
- .platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
- .priv_auto_alloc_size = sizeof(struct NS16550),
+ .plat_auto = sizeof(struct ns16550_plat),
+ .priv_auto = sizeof(struct NS16550),
.ops = &ns16550_serial_ops,
- .ofdata_to_platdata = apl_ns16550_ofdata_to_platdata,
+ .of_to_plat = apl_ns16550_of_to_plat,
.probe = apl_ns16550_probe,
};
return 0;
}
-static int broadwell_adsp_ofdata_to_platdata(struct udevice *dev)
+static int broadwell_adsp_of_to_plat(struct udevice *dev)
{
struct broadwell_adsp_priv *priv = dev_get_priv(dev);
U_BOOT_DRIVER(broadwell_adsp_drv) = {
.name = "adsp",
.id = UCLASS_SYSCON,
- .ofdata_to_platdata = broadwell_adsp_ofdata_to_platdata,
+ .of_to_plat = broadwell_adsp_of_to_plat,
.of_match = broadwell_adsp_ids,
.bind = dm_scan_fdt_dev,
.probe = broadwell_adsp_probe,
.bind = cpu_x86_bind,
.probe = cpu_x86_broadwell_probe,
.ops = &cpu_x86_broadwell_ops,
- .priv_auto_alloc_size = sizeof(struct cpu_broadwell_priv),
+ .priv_auto = sizeof(struct cpu_broadwell_priv),
.flags = DM_FLAG_PRE_RELOC,
};
#include <asm/arch/pch.h>
#include <linux/delay.h>
-struct sata_platdata {
+struct sata_plat {
int port_map;
uint port0_gen3_tx;
uint port1_gen3_tx;
static void broadwell_sata_init(struct udevice *dev)
{
- struct sata_platdata *plat = dev_get_platdata(dev);
+ struct sata_plat *plat = dev_get_plat(dev);
u32 reg32;
u8 *abar;
u16 reg16;
static int broadwell_sata_enable(struct udevice *dev)
{
- struct sata_platdata *plat = dev_get_platdata(dev);
+ struct sata_plat *plat = dev_get_plat(dev);
struct gpio_desc desc;
u16 map;
int ret;
return 0;
}
-static int broadwell_sata_ofdata_to_platdata(struct udevice *dev)
+static int broadwell_sata_of_to_plat(struct udevice *dev)
{
- struct sata_platdata *plat = dev_get_platdata(dev);
+ struct sata_plat *plat = dev_get_plat(dev);
const void *blob = gd->fdt_blob;
int node = dev_of_offset(dev);
.name = "ahci_broadwell",
.id = UCLASS_AHCI,
.of_match = broadwell_ahci_ids,
- .ofdata_to_platdata = broadwell_sata_ofdata_to_platdata,
+ .of_to_plat = broadwell_sata_of_to_plat,
.probe = broadwell_sata_probe,
- .platdata_auto_alloc_size = sizeof(struct sata_platdata),
+ .plat_auto = sizeof(struct sata_plat),
};
int cpu_x86_bind(struct udevice *dev)
{
- struct cpu_platdata *plat = dev_get_parent_platdata(dev);
+ struct cpu_plat *plat = dev_get_parent_plat(dev);
struct cpuid_result res;
plat->cpu_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
#include <spl.h>
#include <asm/itss.h>
-struct itss_platdata {
+struct itss_plat {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
/* Put this first since driver model will copy the data here */
struct dtd_intel_itss dtplat;
return 0;
}
-static int itss_ofdata_to_platdata(struct udevice *dev)
+static int itss_of_to_plat(struct udevice *dev)
{
struct itss_priv *priv = dev_get_priv(dev);
int ret;
#if CONFIG_IS_ENABLED(OF_PLATDATA)
- struct itss_platdata *plat = dev_get_platdata(dev);
+ struct itss_plat *plat = dev_get_plat(dev);
struct dtd_intel_itss *dtplat = &plat->dtplat;
/*
.of_match = itss_ids,
.ops = &itss_ops,
.bind = itss_bind,
- .ofdata_to_platdata = itss_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct itss_platdata),
- .priv_auto_alloc_size = sizeof(struct itss_priv),
+ .of_to_plat = itss_of_to_plat,
+ .plat_auto = sizeof(struct itss_plat),
+ .priv_auto = sizeof(struct itss_priv),
};
#define PCH_P2SB_E0 0xe0
#define HIDE_BIT BIT(0)
-struct p2sb_platdata {
+struct p2sb_plat {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct dtd_intel_p2sb dtplat;
#endif
*/
static int p2sb_early_init(struct udevice *dev)
{
- struct p2sb_platdata *plat = dev_get_platdata(dev);
+ struct p2sb_plat *plat = dev_get_plat(dev);
pci_dev_t pdev = plat->bdf;
/*
return 0;
}
-int p2sb_ofdata_to_platdata(struct udevice *dev)
+int p2sb_of_to_plat(struct udevice *dev)
{
struct p2sb_uc_priv *upriv = dev_get_uclass_priv(dev);
- struct p2sb_platdata *plat = dev_get_platdata(dev);
+ struct p2sb_plat *plat = dev_get_plat(dev);
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
int ret;
static int p2sb_child_post_bind(struct udevice *dev)
{
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
- struct p2sb_child_platdata *pplat = dev_get_parent_platdata(dev);
+ struct p2sb_child_plat *pplat = dev_get_parent_plat(dev);
int ret;
u32 pid;
.probe = p2sb_probe,
.remove = p2sb_remove,
.ops = &p2sb_ops,
- .ofdata_to_platdata = p2sb_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct p2sb_platdata),
- .per_child_platdata_auto_alloc_size =
- sizeof(struct p2sb_child_platdata),
+ .of_to_plat = p2sb_of_to_plat,
+ .plat_auto = sizeof(struct p2sb_plat),
+ .per_child_plat_auto = sizeof(struct p2sb_child_plat),
.child_post_bind = p2sb_child_post_bind,
.flags = DM_FLAG_OS_PREPARE,
};
.id = UCLASS_IRQ,
.of_match = irq_router_ids,
.probe = irq_router_probe,
- .priv_auto_alloc_size = sizeof(struct irq_router),
+ .priv_auto = sizeof(struct irq_router),
};
for (uclass_find_first_device(UCLASS_CPU, &dev);
dev;
uclass_find_next_device(&dev)) {
- struct cpu_platdata *plat = dev_get_parent_platdata(dev);
+ struct cpu_plat *plat = dev_get_parent_plat(dev);
if (plat->cpu_id == apic_id) {
*devp = dev;
static int mp_init_cpu(struct udevice *cpu, void *unused)
{
- struct cpu_platdata *plat = dev_get_parent_platdata(cpu);
+ struct cpu_plat *plat = dev_get_parent_plat(cpu);
plat->ucode_version = microcode_read_rev();
plat->device_id = gd->arch.x86_device;
int cpu_num;
int cpu_online;
struct udevice *dev, *pdev;
- struct cpu_platdata *plat;
+ struct cpu_plat *plat;
char *cpu;
/* first we need to find '/cpus' */
printf("binding cpu@%d failed: %d\n", cpu_num, ret);
return ret;
}
- plat = dev_get_parent_platdata(dev);
+ plat = dev_get_parent_plat(dev);
plat->cpu_id = cpu_num;
}
return 0;
* The serial port info hob is generated by Slim Bootloader, so eligible for
* Slim Bootloader based boards only.
*/
-static int slimbootloader_serial_ofdata_to_platdata(struct udevice *dev)
+static int slimbootloader_serial_of_to_plat(struct udevice *dev)
{
const efi_guid_t guid = SBL_SERIAL_PORT_INFO_GUID;
struct sbl_serial_port_info *data;
- struct ns16550_platdata *plat = dev->platdata;
+ struct ns16550_plat *plat = dev->plat;
if (!gd->arch.hob_list)
panic("hob list not found!");
.name = "serial_slimbootloader",
.id = UCLASS_SERIAL,
.of_match = slimbootloader_serial_ids,
- .ofdata_to_platdata = slimbootloader_serial_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
- .priv_auto_alloc_size = sizeof(struct NS16550),
+ .of_to_plat = slimbootloader_serial_of_to_plat,
+ .plat_auto = sizeof(struct ns16550_plat),
+ .priv_auto = sizeof(struct NS16550),
.probe = ns16550_serial_probe,
.ops = &ns16550_serial_ops,
};
.id = UCLASS_SYSCON,
.of_match = tangier_pinctrl_match,
.probe = tangier_pinctrl_probe,
- .priv_auto_alloc_size = sizeof(struct mrfld_pinctrl),
+ .priv_auto = sizeof(struct mrfld_pinctrl),
};
#define GPIO_PER_BANK 32
#define GPIO_BANKS 3
-struct broadwell_bank_platdata {
+struct broadwell_bank_plat {
uint16_t base_addr;
const char *bank_name;
int bank;
#include <asm-generic/gpio.h>
-struct ich6_bank_platdata {
+struct ich6_bank_plat {
uint16_t base_addr;
const char *bank_name;
int offset;
int intel_pinctrl_probe(struct udevice *dev);
/**
- * intel_pinctrl_ofdata_to_platdata() - Handle common platdata setup
+ * intel_pinctrl_of_to_plat() - Handle common plat setup
*
* @dev: Pinctrl device
* @comm: Pad community for this device
* @num_cfgs: Number of configuration words for each pad
* @return 0 if OK, -EDOM if @comm is NULL, other -ve value on other error
*/
-int intel_pinctrl_ofdata_to_platdata(struct udevice *dev,
- const struct pad_community *comm,
- int num_cfgs);
+int intel_pinctrl_of_to_plat(struct udevice *dev,
+ const struct pad_community *comm, int num_cfgs);
/**
* pinctrl_route_gpe() - set GPIO groups for the general-purpose-event blocks
for (uclass_find_first_device(UCLASS_CPU, &dev);
dev;
uclass_find_next_device(&dev)) {
- struct cpu_platdata *plat = dev_get_parent_platdata(dev);
+ struct cpu_plat *plat = dev_get_parent_plat(dev);
int length;
length = acpi_create_madt_lapic(
static int fsp_video_probe(struct udevice *dev)
{
- struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
struct vesa_mode_info *vesa = &mode_info.vesa;
int ret;
static int fsp_video_bind(struct udevice *dev)
{
- struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
/* Set the maximum supported resolution */
plat->size = 2560 * 1600 * 4;
for (uclass_find_first_device(UCLASS_CPU, &dev);
dev;
uclass_find_next_device(&dev)) {
- struct cpu_platdata *plat = dev_get_parent_platdata(dev);
+ struct cpu_plat *plat = dev_get_parent_plat(dev);
u8 cpuflag = MPC_CPU_EN;
if (!device_active(dev))
.id = UCLASS_SYSCON,
.of_match = pmu_mid_match,
.probe = pmu_mid_probe,
- .priv_auto_alloc_size = sizeof(struct pmu_mid),
+ .priv_auto = sizeof(struct pmu_mid),
};
.id = UCLASS_SYSCON,
.of_match = scu_ipc_match,
.probe = scu_ipc_probe,
- .priv_auto_alloc_size = sizeof(struct scu),
+ .priv_auto = sizeof(struct scu),
};
for (uclass_find_first_device(UCLASS_CPU, &dev);
dev;
uclass_find_next_device(&dev)) {
- struct cpu_platdata *plat = dev_get_parent_platdata(dev);
+ struct cpu_plat *plat = dev_get_parent_plat(dev);
if (!device_active(dev))
continue;
DECLARE_GLOBAL_DATA_PTR;
-static const struct pl01x_serial_platdata serial_platdata = {
+static const struct pl01x_serial_plat serial_plat = {
.base = 0x16000000,
#ifdef CONFIG_ARCH_CINTEGRATOR
.type = TYPE_PL011,
U_BOOT_DEVICE(integrator_serials) = {
.name = "serial_pl01x",
- .platdata = &serial_platdata,
+ .plat = &serial_plat,
};
void peripheral_power_enable (void);
#include <dm/platform_data/serial_pl01x.h>
#include <asm/armv8/mmu.h>
-static const struct pl01x_serial_platdata serial_platdata = {
+static const struct pl01x_serial_plat serial_plat = {
.base = UART0_BASE,
.type = TYPE_PL011,
.clock = CONFIG_PL011_CLOCK,
U_BOOT_DEVICE(total_compute_serials) = {
.name = "serial_pl01x",
- .platdata = &serial_platdata,
+ .plat = &serial_plat,
};
static struct mm_region total_compute_mem_map[] = {
DECLARE_GLOBAL_DATA_PTR;
-static const struct pl01x_serial_platdata serial_platdata = {
+static const struct pl01x_serial_plat serial_plat = {
.base = V2M_UART0,
.type = TYPE_PL011,
.clock = CONFIG_PL011_CLOCK,
U_BOOT_DEVICE(vexpress_serials) = {
.name = "serial_pl01x",
- .platdata = &serial_platdata,
+ .plat = &serial_plat,
};
static struct mm_region vexpress64_mem_map[] = {
uclass_find_first_device(UCLASS_VIDEO, &dev);
if (dev) {
- struct atmel_lcd_platdata *plat = dev_get_platdata(dev);
+ struct atmel_lcd_plat *plat = dev_get_plat(dev);
plat->timing_index = 1;
}
{
}
-static struct atmel_serial_platdata at91sam9260_serial_plat = {
+static struct atmel_serial_plat at91sam9260_serial_plat = {
.base_addr = ATMEL_BASE_DBGU,
};
U_BOOT_DEVICE(at91sam9260_serial) = {
.name = "serial_atmel",
- .platdata = &at91sam9260_serial_plat,
+ .plat = &at91sam9260_serial_plat,
};
{
}
-static struct atmel_serial_platdata at91sam9260_serial_plat = {
+static struct atmel_serial_plat at91sam9260_serial_plat = {
.base_addr = ATMEL_BASE_DBGU,
};
U_BOOT_DEVICE(at91sam9260_serial) = {
.name = "serial_atmel",
- .platdata = &at91sam9260_serial_plat,
+ .plat = &at91sam9260_serial_plat,
};
U_BOOT_DEVICE(ethoc) = {
.name = "ethoc",
- .platdata = ðoc_pdata,
+ .plat = ðoc_pdata,
};
#if !CONFIG_IS_ENABLED(OF_CONTROL)
#include <dm/platform_data/serial_pl01x.h>
-static const struct pl01x_serial_platdata serial0 = {
+static const struct pl01x_serial_plat serial0 = {
.base = CONFIG_SYS_SERIAL0,
.type = TYPE_PL011,
.clock = 0,
U_BOOT_DEVICE(thunderx_serial0) = {
.name = "serial_pl01x",
- .platdata = &serial0,
+ .plat = &serial0,
};
-static const struct pl01x_serial_platdata serial1 = {
+static const struct pl01x_serial_plat serial1 = {
.base = CONFIG_SYS_SERIAL1,
.type = TYPE_PL011,
.clock = 0,
U_BOOT_DEVICE(thunderx_serial1) = {
.name = "serial_pl01x",
- .platdata = &serial1,
+ .plat = &serial1,
};
#endif
return cl_eeprom_get_board_rev(CONFIG_SYS_I2C_EEPROM_BUS);
}
-static struct mxc_serial_platdata cm_fx6_mxc_serial_plat = {
+static struct mxc_serial_plat cm_fx6_mxc_serial_plat = {
.reg = (struct mxc_uart *)UART4_BASE,
};
U_BOOT_DEVICE(cm_fx6_serial) = {
.name = "serial_mxc",
- .platdata = &cm_fx6_mxc_serial_plat,
+ .plat = &cm_fx6_mxc_serial_plat,
};
#if CONFIG_IS_ENABLED(AHCI)
#endif
#ifdef CONFIG_SPL_BUILD
-static const struct ns16550_platdata serial_pdata = {
+static const struct ns16550_plat serial_pdata = {
.base = DAVINCI_UART2_BASE,
.reg_shift = 2,
.clock = 228000000,
U_BOOT_DEVICE(omapl138_uart) = {
.name = "ns16550_serial",
- .platdata = &serial_pdata,
+ .plat = &serial_pdata,
};
-static const struct davinci_mmc_plat mmc_platdata = {
+static const struct davinci_mmc_plat mmc_plat = {
.reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
.cfg = {
.f_min = 200000,
};
U_BOOT_DEVICE(omapl138_mmc) = {
.name = "ti_da830_mmc",
- .platdata = &mmc_platdata,
+ .plat = &mmc_plat,
};
void spl_board_init(void)
U_BOOT_DEVICE(ls1012a_pfe0) = {
.name = "pfe_eth",
- .platdata = &pfe_pdata0,
+ .plat = &pfe_pdata0,
};
U_BOOT_DEVICE(ls1012a_pfe1) = {
.name = "pfe_eth",
- .platdata = &pfe_pdata1,
+ .plat = &pfe_pdata1,
};
U_BOOT_DEVICE(ls1012a_pfe0) = {
.name = "pfe_eth",
- .platdata = &pfe_pdata0,
+ .plat = &pfe_pdata0,
};
U_BOOT_DEVICE(ls1012a_pfe1) = {
.name = "pfe_eth",
- .platdata = &pfe_pdata1,
+ .plat = &pfe_pdata1,
};
U_BOOT_DEVICE(ls1012a_pfe0) = {
.name = "pfe_eth",
- .platdata = &pfe_pdata0,
+ .plat = &pfe_pdata0,
};
U_BOOT_DEVICE(ls1012a_pfe1) = {
.name = "pfe_eth",
- .platdata = &pfe_pdata1,
+ .plat = &pfe_pdata1,
};
DECLARE_GLOBAL_DATA_PTR;
-static struct pl01x_serial_platdata serial0 = {
+static struct pl01x_serial_plat serial0 = {
#if CONFIG_CONS_INDEX == 0
.base = CONFIG_SYS_SERIAL0,
#elif CONFIG_CONS_INDEX == 1
U_BOOT_DEVICE(nxp_serial0) = {
.name = "serial_pl01x",
- .platdata = &serial0,
+ .plat = &serial0,
};
-static struct pl01x_serial_platdata serial1 = {
+static struct pl01x_serial_plat serial1 = {
.base = CONFIG_SYS_SERIAL1,
.type = TYPE_PL011,
};
U_BOOT_DEVICE(nxp_serial1) = {
.name = "serial_pl01x",
- .platdata = &serial1,
+ .plat = &serial1,
};
int select_i2c_ch_pca9547(u8 ch)
}
#endif /* CONFIG_OF_BOARD_SETUP */
-static struct mxc_serial_platdata ventana_mxc_serial_plat = {
+static struct mxc_serial_plat ventana_mxc_serial_plat = {
.reg = (struct mxc_uart *)UART2_BASE,
};
U_BOOT_DEVICE(ventana_serial) = {
.name = "serial_mxc",
- .platdata = &ventana_mxc_serial_plat,
+ .plat = &ventana_mxc_serial_plat,
};
#include <asm/armv8/mmu.h>
/*TODO drop this table in favour of device tree */
-static const struct hikey_gpio_platdata hi6220_gpio[] = {
+static const struct hikey_gpio_plat hi6220_gpio[] = {
{ 0, HI6220_GPIO_BASE(0)},
{ 1, HI6220_GPIO_BASE(1)},
{ 2, HI6220_GPIO_BASE(2)},
#if !CONFIG_IS_ENABLED(OF_CONTROL)
-static const struct pl01x_serial_platdata serial_platdata = {
+static const struct pl01x_serial_plat serial_plat = {
#if CONFIG_CONS_INDEX == 1
.base = HI6220_UART0_BASE,
#elif CONFIG_CONS_INDEX == 4
U_BOOT_DEVICE(hikey_seriala) = {
.name = "serial_pl01x",
- .platdata = &serial_platdata,
+ .plat = &serial_plat,
};
#endif
#if !CONFIG_IS_ENABLED(OF_CONTROL)
#include <dm/platform_data/serial_pl01x.h>
-static const struct pl01x_serial_platdata serial_platdata = {
+static const struct pl01x_serial_plat serial_plat = {
.base = HI3660_UART6_BASE,
.type = TYPE_PL011,
.clock = 19200000
U_BOOT_DEVICE(hikey960_serial0) = {
.name = "serial_pl01x",
- .platdata = &serial_platdata,
+ .plat = &serial_plat,
};
#endif
struct mm_region *mem_map = poplar_mem_map;
#if !CONFIG_IS_ENABLED(OF_CONTROL)
-static const struct pl01x_serial_platdata serial_platdata = {
+static const struct pl01x_serial_plat serial_plat = {
.base = REG_BASE_UART0,
.type = TYPE_PL010,
.clock = 75000000,
U_BOOT_DEVICE(poplar_serial) = {
.name = "serial_pl01x",
- .platdata = &serial_platdata,
+ .plat = &serial_plat,
};
#endif
* Intel Galileo gen2 board uses GPIO Resume Well bank pin0 as the PERST# pin.
*
* We cannot use any public GPIO APIs in <asm-generic/gpio.h> to control this
- * pin, as these APIs will eventually call into gpio_ich6_ofdata_to_platdata()
+ * pin, as these APIs will eventually call into gpio_ich6_of_to_plat()
* in the Intel ICH6 GPIO driver where it calls PCI configuration space access
* APIs which will trigger PCI enumeration process.
*
#include <fdt_support.h>
#include "igep00x0.h"
-static const struct ns16550_platdata igep_serial = {
+static const struct ns16550_plat igep_serial = {
.base = OMAP34XX_UART3,
.reg_shift = 2,
.clock = V_NS16550_CLK,
.nand_string = "MMC"
};
-static const struct ns16550_platdata serial_omap_platdata = {
+static const struct ns16550_plat serial_omap_plat = {
.base = OMAP34XX_UART3,
.reg_shift = 2,
.clock = V_NS16550_CLK,
U_BOOT_DEVICE(sniper_serial) = {
.name = "ns16550_serial",
- .platdata = &serial_omap_platdata
+ .plat = &serial_omap_plat
};
static struct musb_hdrc_config musb_config = {
twl4030_power_mmc_init(1);
}
-static const struct omap_i2c_platdata rx51_i2c[] = {
+static const struct omap_i2c_plat rx51_i2c[] = {
{ I2C_BASE1, 2200000, OMAP_I2C_REV_V1 },
{ I2C_BASE2, 100000, OMAP_I2C_REV_V1 },
{ I2C_BASE3, 400000, OMAP_I2C_REV_V1 },
.ops = &renesas_ulcb_sysreset,
.probe = renesas_ulcb_sysreset_probe,
.of_match = renesas_ulcb_sysreset_ids,
- .priv_auto_alloc_size = sizeof(struct renesas_ulcb_sysreset_priv),
+ .priv_auto = sizeof(struct renesas_ulcb_sysreset_priv),
};
}
}
-static struct atmel_serial_platdata at91sam9260_serial_plat = {
+static struct atmel_serial_plat at91sam9260_serial_plat = {
.base_addr = ATMEL_BASE_DBGU,
};
U_BOOT_DEVICE(at91sam9260_serial) = {
.name = "serial_atmel",
- .platdata = &at91sam9260_serial_plat,
+ .plat = &at91sam9260_serial_plat,
};
(struct gpio_regs *) GPIOA_BASE_ADDR;
#ifndef CONFIG_OF_CONTROL
-static const struct pl01x_serial_platdata serial_platdata = {
+static const struct pl01x_serial_plat serial_plat = {
.base = 0x80406000,
.type = TYPE_PL011,
.clock = 2700 * 1000,
U_BOOT_DEVICE(stv09911_serials) = {
.name = "serial_pl01x",
- .platdata = &serial_platdata,
+ .plat = &serial_plat,
};
#endif
return 0;
}
-static struct coldfire_serial_platdata mcf5307_serial_plat = {
+static struct coldfire_serial_plat mcf5307_serial_plat = {
.base = CONFIG_SYS_UART_BASE,
.port = 0,
.baudrate = CONFIG_BAUDRATE,
U_BOOT_DEVICE(coldfire_serial) = {
.name = "serial_coldfire",
- .platdata = &mcf5307_serial_plat,
+ .plat = &mcf5307_serial_plat,
};
}
#endif
-/* CPSW platdata */
+/* CPSW plat */
#if !CONFIG_IS_ENABLED(OF_CONTROL)
struct cpsw_slave_data slave_data[] = {
{
U_BOOT_DEVICE(am335x_eth) = {
.name = "eth_cpsw",
- .platdata = &cpsw_pdata,
+ .plat = &cpsw_pdata,
};
#endif
#endif
#if !CONFIG_IS_ENABLED(OF_CONTROL)
-static const struct omap_hsmmc_plat am335x_mmc0_platdata = {
+static const struct omap_hsmmc_plat am335x_mmc0_plat = {
.base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE,
.cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_4BIT,
.cfg.f_min = 400000,
U_BOOT_DEVICE(am335x_mmc0) = {
.name = "omap_hsmmc",
- .platdata = &am335x_mmc0_platdata,
+ .plat = &am335x_mmc0_plat,
};
-static const struct omap_hsmmc_plat am335x_mmc1_platdata = {
+static const struct omap_hsmmc_plat am335x_mmc1_plat = {
.base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE,
.cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_8BIT,
.cfg.f_min = 400000,
U_BOOT_DEVICE(am335x_mmc1) = {
.name = "omap_hsmmc",
- .platdata = &am335x_mmc1_platdata,
+ .plat = &am335x_mmc1_plat,
};
#endif
0
};
-static const struct ns16550_platdata devkit8000_serial = {
+static const struct ns16550_plat devkit8000_serial = {
.base = OMAP34XX_UART3,
.reg_shift = 2,
.clock = V_NS16550_CLK,
#endif /* CONFIG_SPL_BUILD */
-static struct mxc_serial_platdata mxc_serial_plat = {
+static struct mxc_serial_plat mxc_serial_plat = {
.reg = (struct mxc_uart *)UART1_BASE,
.use_dte = true,
};
U_BOOT_DEVICE(mxc_serial) = {
.name = "serial_mxc",
- .platdata = &mxc_serial_plat,
+ .plat = &mxc_serial_plat,
};
}
#endif
-static struct mxc_serial_platdata mxc_serial_plat = {
+static struct mxc_serial_plat mxc_serial_plat = {
.reg = (struct mxc_uart *)UART1_BASE,
.use_dte = 1,
};
U_BOOT_DEVICE(mxc_serial) = {
.name = "serial_mxc",
- .platdata = &mxc_serial_plat,
+ .plat = &mxc_serial_plat,
};
#endif /* CONFIG_SPL_BUILD */
-static struct mxc_serial_platdata mxc_serial_plat = {
+static struct mxc_serial_plat mxc_serial_plat = {
.reg = (struct mxc_uart *)UART1_BASE,
.use_dte = true,
};
U_BOOT_DEVICE(mxc_serial) = {
.name = "serial_mxc",
- .platdata = &mxc_serial_plat,
+ .plat = &mxc_serial_plat,
};
return 0;
}
#else /* !CONFIG_IS_ENABLED(DM_MMC) */
-static const struct pxa_mmc_plat mmc_platdata = {
+static const struct pxa_mmc_plat mmc_plat = {
.base = (struct pxa_mmc_regs *)MMC0_BASE,
};
U_BOOT_DEVICE(pxa_mmcs) = {
.name = "pxa_mmc",
- .platdata = &mmc_platdata,
+ .plat = &mmc_plat,
};
#endif /* !CONFIG_IS_ENABLED(DM_MMC) */
#endif
-static const struct pxa_serial_platdata serial_platdata = {
+static const struct pxa_serial_plat serial_plat = {
.base = (struct pxa_uart_regs *)FFUART_BASE,
.port = FFUART_INDEX,
.baudrate = CONFIG_BAUDRATE,
U_BOOT_DEVICE(pxa_serials) = {
.name = "serial_pxa",
- .platdata = &serial_platdata,
+ .plat = &serial_plat,
};
config CMD_EXCEPTION
bool "exception - raise exception"
- depends on ARM || RISCV || X86
+ depends on ARM || RISCV || SANDBOX || X86
help
Enable the 'exception' command which allows to raise an exception.
The '-f' (force) option can be used for set the value which exceeds
the limits, which are found in device-tree and are kept in regulator's
- uclass platdata structure.
+ uclass plat structure.
endmenu
obj-$(CONFIG_ARM) += arm/
obj-$(CONFIG_RISCV) += riscv/
+obj-$(CONFIG_SANDBOX) += sandbox/
obj-$(CONFIG_X86) += x86/
obj-$(CONFIG_ARCH_MVEBU) += mvebu/
for (uclass_find_first_device(UCLASS_BUTTON, &dev);
dev;
uclass_find_next_device(&dev)) {
- struct button_uc_plat *plat = dev_get_uclass_platdata(dev);
+ struct button_uc_plat *plat = dev_get_uclass_plat(dev);
if (!plat->label)
continue;
for (uclass_first_device(UCLASS_CPU, &dev);
dev;
uclass_next_device(&dev)) {
- struct cpu_platdata *plat = dev_get_parent_platdata(dev);
+ struct cpu_plat *plat = dev_get_parent_plat(dev);
struct cpu_info info;
bool first = true;
int ret, i;
for (i = 0, ret = uclass_first_device(UCLASS_DEMO, &dev);
dev;
ret = uclass_next_device(&dev)) {
- printf("entry %d - instance %08x, ops %08x, platdata %08x\n",
+ printf("entry %d - instance %08x, ops %08x, plat %08x\n",
i++, (uint)map_to_sysmem(dev),
(uint)map_to_sysmem(dev->driver->ops),
- (uint)map_to_sysmem(dev_get_platdata(dev)));
+ (uint)map_to_sysmem(dev_get_plat(dev)));
}
return cmd_process_error(cmdtp, ret);
struct host_block_dev *host_dev;
#ifdef CONFIG_BLK
- host_dev = dev_get_platdata(blk_dev->bdev);
+ host_dev = dev_get_plat(blk_dev->bdev);
#else
host_dev = blk_dev->priv;
#endif
ret = i2c_set_chip_offset_len(dev, alen);
if (ret)
return i2c_report_err(ret, I2C_ERR_WRITE);
- i2c_chip = dev_get_parent_platdata(dev);
+ i2c_chip = dev_get_parent_plat(dev);
if (!i2c_chip)
return i2c_report_err(ret, I2C_ERR_WRITE);
#endif
for (device_find_first_child(bus, &dev);
dev;
device_find_next_child(&dev)) {
- struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
+ struct dm_i2c_chip *chip = dev_get_parent_plat(dev);
printf(" %02x: %s, offset len %x, flags %x\n",
chip->chip_addr, dev->name, chip->offset_len,
for (uclass_find_first_device(UCLASS_LED, &dev);
dev;
uclass_find_next_device(&dev)) {
- struct led_uc_plat *plat = dev_get_uclass_platdata(dev);
+ struct led_uc_plat *plat = dev_get_uclass_plat(dev);
if (!plat->label)
continue;
uclass_foreach_dev(udev, uc) {
if (udev->driver != entry)
continue;
- desc = dev_get_uclass_platdata(udev);
+ desc = dev_get_uclass_plat(udev);
printf("%c %s %u", i ? ',' : ':',
blk_get_if_type_name(desc->if_type),
desc->devnum);
for (device_find_first_child(bus, &dev);
dev;
device_find_next_child(&dev)) {
- struct pci_child_platdata *pplat;
+ struct pci_child_plat *pplat;
- pplat = dev_get_parent_platdata(dev);
+ pplat = dev_get_parent_plat(dev);
if (short_listing) {
printf("%02x.%02x.%02x ", bus->seq,
PCI_DEV(pplat->devfn), PCI_FUNC(pplat->devfn));
static int do_dev(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
const char *name;
int ret = -ENXIO;
return CMD_RET_USAGE;
}
- uc_pdata = dev_get_uclass_platdata(currdev);
+ uc_pdata = dev_get_uclass_plat(currdev);
if (!uc_pdata) {
printf("%s: no regulator platform data!\n", currdev->name);
return failure(ret);
return CMD_RET_SUCCESS;
}
-static int curr_dev_and_platdata(struct udevice **devp,
- struct dm_regulator_uclass_platdata **uc_pdata,
- bool allow_type_fixed)
+static int curr_dev_and_plat(struct udevice **devp,
+ struct dm_regulator_uclass_plat **uc_pdata,
+ bool allow_type_fixed)
{
*devp = NULL;
*uc_pdata = NULL;
*devp = currdev;
- *uc_pdata = dev_get_uclass_platdata(*devp);
+ *uc_pdata = dev_get_uclass_plat(*devp);
if (!*uc_pdata) {
pr_err("Regulator: %s - missing platform data!\n", currdev->name);
return CMD_RET_FAILURE;
static int do_list(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
struct udevice *dev;
int ret;
if (ret)
continue;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
printf("| %-*.*s| %-*.*s| %s\n",
LIMIT_DEVNAME, LIMIT_DEVNAME, dev->name,
LIMIT_OFNAME, LIMIT_OFNAME, uc_pdata->name,
char *const argv[])
{
struct udevice *dev;
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
struct dm_regulator_mode *modes;
const char *parent_uc;
int mode_count;
int ret;
int i;
- ret = curr_dev_and_platdata(&dev, &uc_pdata, true);
+ ret = curr_dev_and_plat(&dev, &uc_pdata, true);
if (ret)
return ret;
}
static void do_status_detail(struct udevice *dev,
- struct dm_regulator_uclass_platdata *uc_pdata)
+ struct dm_regulator_uclass_plat *uc_pdata)
{
int current, value, mode;
const char *mode_name;
static void do_status_line(struct udevice *dev)
{
- struct dm_regulator_uclass_platdata *pdata;
+ struct dm_regulator_uclass_plat *pdata;
int current, value, mode;
const char *mode_name;
bool enabled;
- pdata = dev_get_uclass_platdata(dev);
+ pdata = dev_get_uclass_plat(dev);
enabled = regulator_get_enable(dev);
value = regulator_get_value(dev);
current = regulator_get_current(dev);
static int do_status(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
struct udevice *dev;
int ret;
if (currdev && (argc < 2 || strcmp(argv[1], "-a"))) {
- ret = curr_dev_and_platdata(&dev, &uc_pdata, true);
+ ret = curr_dev_and_plat(&dev, &uc_pdata, true);
if (ret)
return CMD_RET_FAILURE;
do_status_detail(dev, uc_pdata);
char *const argv[])
{
struct udevice *dev;
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
int value;
int force;
int ret;
- ret = curr_dev_and_platdata(&dev, &uc_pdata, argc == 1);
+ ret = curr_dev_and_plat(&dev, &uc_pdata, argc == 1);
if (ret)
return ret;
char *const argv[])
{
struct udevice *dev;
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
int current;
int ret;
- ret = curr_dev_and_platdata(&dev, &uc_pdata, argc == 1);
+ ret = curr_dev_and_plat(&dev, &uc_pdata, argc == 1);
if (ret)
return ret;
char *const argv[])
{
struct udevice *dev;
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
int mode;
int ret;
- ret = curr_dev_and_platdata(&dev, &uc_pdata, false);
+ ret = curr_dev_and_plat(&dev, &uc_pdata, false);
if (ret)
return ret;
char *const argv[])
{
struct udevice *dev;
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
int ret;
- ret = curr_dev_and_platdata(&dev, &uc_pdata, true);
+ ret = curr_dev_and_plat(&dev, &uc_pdata, true);
if (ret)
return ret;
char *const argv[])
{
struct udevice *dev;
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
int ret;
- ret = curr_dev_and_platdata(&dev, &uc_pdata, true);
+ ret = curr_dev_and_plat(&dev, &uc_pdata, true);
if (ret)
return ret;
struct dm_rproc_uclass_pdata *uc_pdata;
const struct dm_rproc_ops *ops = rproc_get_ops(dev);
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
/* Do not print if rproc is not probed */
if (!(dev->flags & DM_FLAG_ACTIVATED))
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-$(CONFIG_CMD_EXCEPTION) += exception.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * The 'exception' command can be used for testing exception handling.
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+
+static int do_sigsegv(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ u8 *ptr = NULL;
+
+ *ptr = 0;
+ return CMD_RET_FAILURE;
+}
+
+static int do_undefined(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ asm volatile (".word 0xffff\n");
+ return CMD_RET_FAILURE;
+}
+
+static struct cmd_tbl cmd_sub[] = {
+ U_BOOT_CMD_MKENT(sigsegv, CONFIG_SYS_MAXARGS, 1, do_sigsegv,
+ "", ""),
+ U_BOOT_CMD_MKENT(undefined, CONFIG_SYS_MAXARGS, 1, do_undefined,
+ "", ""),
+};
+
+static char exception_help_text[] =
+ "<ex>\n"
+ " The following exceptions are available:\n"
+ " undefined - undefined instruction\n"
+ " sigsegv - illegal memory access\n"
+ ;
+
+#include <exception.h>
const char *name;
ulong fb_base;
#ifdef CONFIG_DM_VIDEO
- struct video_uc_platdata *plat;
+ struct video_uc_plat *plat;
struct video_priv *uc_priv;
struct udevice *dev;
int ret;
if (ret)
return ret;
uc_priv = dev_get_uclass_priv(dev);
- plat = dev_get_uclass_platdata(dev);
+ plat = dev_get_uclass_plat(dev);
xsize = uc_priv->xsize;
ysize = uc_priv->ysize;
bpix = uc_priv->bpix;
.post_bind = dm_scan_fdt_dev,
.post_probe = usb_hub_post_probe,
.child_pre_probe = usb_child_pre_probe,
- .per_child_auto_alloc_size = sizeof(struct usb_device),
- .per_child_platdata_auto_alloc_size = sizeof(struct usb_dev_platdata),
- .per_device_auto_alloc_size = sizeof(struct usb_hub_device),
+ .per_child_auto = sizeof(struct usb_device),
+ .per_child_plat_auto = sizeof(struct usb_dev_plat),
+ .per_device_auto = sizeof(struct usb_hub_device),
};
static const struct usb_device_id hub_id_table[] = {
for (blk_first_device(IF_TYPE_USB, &dev);
dev;
blk_next_device(&dev)) {
- struct blk_desc *desc = dev_get_uclass_platdata(dev);
+ struct blk_desc *desc = dev_get_uclass_plat(dev);
printf(" Device %d: ", desc->devnum);
dev_print(desc);
debug("\n\nProbing for storage\n");
#if CONFIG_IS_ENABLED(BLK)
/*
- * We store the us_data in the mass storage device's platdata. It
+ * We store the us_data in the mass storage device's plat. It
* is shared by all LUNs (block devices) attached to this mass storage
* device.
*/
- data = dev_get_platdata(udev->dev);
+ data = dev_get_plat(udev->dev);
if (!usb_storage_probe(udev, 0, data))
return 0;
max_lun = usb_get_max_lun(data);
return ret;
}
- blkdev = dev_get_uclass_platdata(dev);
+ blkdev = dev_get_uclass_plat(dev);
blkdev->target = 0xff;
blkdev->lun = lun;
return 0;
/* Setup device */
#if CONFIG_IS_ENABLED(BLK)
- block_dev = dev_get_uclass_platdata(dev);
+ block_dev = dev_get_uclass_plat(dev);
udev = dev_get_parent_priv(dev_get_parent(dev));
debug("\nusb_read: udev %d\n", block_dev->devnum);
#else
/* Setup device */
#if CONFIG_IS_ENABLED(BLK)
- block_dev = dev_get_uclass_platdata(dev);
+ block_dev = dev_get_uclass_plat(dev);
udev = dev_get_parent_priv(dev_get_parent(dev));
debug("\nusb_read: udev %d\n", block_dev->devnum);
#else
.of_match = usb_mass_storage_ids,
.probe = usb_mass_storage_probe,
#if CONFIG_IS_ENABLED(BLK)
- .platdata_auto_alloc_size = sizeof(struct us_data),
+ .plat_auto = sizeof(struct us_data),
#endif
};
going.
- -EINVAL which typically indicates that something was missing or wrong in
the device tree node. Check that everything is correct and look at the
- ofdata_to_platdata() method in the driver.
+ of_to_plat() method in the driver.
If there is no error, you should check if the device is actually bound. Call
dm_dump_all() just before you locate the device to make sure it exists.
The demo class is pretty simple, but not trivial. The intention is that it
can be used for testing, so it will implement all driver model features and
provide good code coverage of them. It does have multiple drivers, it
-handles parameter data and platdata (data which tells the driver how
+handles parameter data and plat (data which tells the driver how
to operate on a particular platform) and it uses private driver data.
To try it, see the example session below::
static int simple_hello(struct udevice *dev, int ch)
{
- const struct dm_demo_pdata *pdata = dev_get_platdata(dev);
+ const struct dm_demo_pdata *pdata = dev_get_plat(dev);
printf("Hello from %08x: %s %d\n", map_to_sysmem(dev),
pdata->colour, pdata->sides);
* bind - make the driver model aware of a device (bind it to its driver)
* unbind - make the driver model forget the device
- * ofdata_to_platdata - convert device tree data to platdata - see later
+ * of_to_plat - convert device tree data to plat - see later
* probe - make a device ready for use
* remove - remove a device so it cannot be used until probed again
-The sequence to get a device to work is bind, ofdata_to_platdata (if using
+The sequence to get a device to work is bind, of_to_plat (if using
device tree) and probe.
basically a communication scheme between the board-specific code and
the generic drivers, which are intended to work on any board.
-Drivers can access their data via dev->info->platdata. Here is
+Drivers can access their data via dev->info->plat. Here is
the declaration for the platform data, which would normally appear
in the board file.
static const struct driver_info info[] = {
{
.name = "demo_shape_drv",
- .platdata = &red_square,
+ .plat = &red_square,
},
};
Device Tree
-----------
-While platdata is useful, a more flexible way of providing device data is
+While plat is useful, a more flexible way of providing device data is
by using device tree. In U-Boot you should use this where possible. Avoid
sending patches which make use of the U_BOOT_DEVICE() macro unless strictly
necessary.
.. code-block:: c
- .platdata_auto_alloc_size = sizeof(struct dm_test_pdata),
- .ofdata_to_platdata = testfdt_ofdata_to_platdata,
+ .plat_auto = sizeof(struct dm_test_pdata),
+ .of_to_plat = testfdt_of_to_plat,
-The 'auto_alloc' feature allowed space for the platdata to be allocated
-and zeroed before the driver's ofdata_to_platdata() method is called. The
-ofdata_to_platdata() method, which the driver write supplies, should parse
-the device tree node for this device and place it in dev->platdata. Thus
+The 'auto' feature allowed space for the plat to be allocated
+and zeroed before the driver's of_to_plat() method is called. The
+of_to_plat() method, which the driver write supplies, should parse
+the device tree node for this device and place it in dev->plat. Thus
when the probe method is called later (to set up the device ready for use)
the platform data will be present.
-Note that both methods are optional. If you provide an ofdata_to_platdata
+Note that both methods are optional. If you provide an of_to_plat
method then it will be called first (during activation). If you provide a
probe method it will be called next. See Driver Lifecycle below for more
details.
-If you don't want to have the platdata automatically allocated then you
-can leave out platdata_auto_alloc_size. In this case you can use malloc
-in your ofdata_to_platdata (or probe) method to allocate the required memory,
+If you don't want to have the plat automatically allocated then you
+can leave out plat_auto. In this case you can use malloc
+in your of_to_plat (or probe) method to allocate the required memory,
and you should free it in the remove method.
The driver model tree is intended to mirror that of the device tree. The
The bus device wants to store this address and some other information such
as the bus speed for each device.
-To achieve this, the bus device can use dev->parent_platdata in each of its
+To achieve this, the bus device can use dev->parent_plat in each of its
three children. This can be auto-allocated if the bus driver (or bus uclass)
-has a non-zero value for per_child_platdata_auto_alloc_size. If not, then
+has a non-zero value for per_child_plat_auto. If not, then
the bus device or uclass can allocate the space itself before the child
device is probed.
- Scan the U_BOOT_DEVICE() definitions. U-Boot looks up the name specified
by each, to find the appropriate U_BOOT_DRIVER() definition. In this case,
there is no path by which driver_data may be provided, but the U_BOOT_DEVICE()
- may provide platdata.
+ may provide plat.
- Scan through the device tree definitions. U-Boot looks at top-level
nodes in the the device tree. It looks at the compatible string in each node
and uses the of_match table of the U_BOOT_DRIVER() structure to find the
right driver for each node. In this case, the of_match table may provide a
- driver_data value, but platdata cannot be provided until later.
+ driver_data value, but plat cannot be provided until later.
For each device that is discovered, U-Boot then calls device_bind() to create a
new device, initializes various core fields of the device object such as name,
uclass & driver, initializes any optional fields of the device object that are
-applicable such as of_offset, driver_data & platdata, and finally calls the
+applicable such as of_offset, driver_data & plat, and finally calls the
driver's bind() method if one is defined.
At this point all the devices are known, and bound to their drivers. There
is a 'struct udevice' allocated for all devices. However, nothing has been
activated (except for the root device). Each bound device that was created
-from a U_BOOT_DEVICE() declaration will hold the platdata pointer specified
+from a U_BOOT_DEVICE() declaration will hold the plat pointer specified
in that declaration. For a bound device created from the device tree,
-platdata will be NULL, but of_offset will be the offset of the device tree
+plat will be NULL, but of_offset will be the offset of the device tree
node that caused the device to be created. The uclass is set correctly for
the device.
base address of hardware registers and parameters relating to driver
operation. This is called 'ofdata' (Open-Firmware data).
-The device's_ofdata_to_platdata() implemnents allocation and reading of
-platdata. A parent's ofdata is always read before a child.
+The device's of_to_plat() implemnents allocation and reading of
+plat. A parent's ofdata is always read before a child.
The steps are:
- 1. If priv_auto_alloc_size is non-zero, then the device-private space
+ 1. If priv_auto is non-zero, then the device-private space
is allocated for the device and zeroed. It will be accessible as
dev->priv. The driver can put anything it likes in there, but should use
it for run-time information, not platform data (which should be static
and known before the device is probed).
- 2. If platdata_auto_alloc_size is non-zero, then the platform data space
+ 2. If plat_auto is non-zero, then the platform data space
is allocated. This is only useful for device tree operation, since
otherwise you would have to specific the platform data in the
U_BOOT_DEVICE() declaration. The space is allocated for the device and
- zeroed. It will be accessible as dev->platdata.
+ zeroed. It will be accessible as dev->plat.
- 3. If the device's uclass specifies a non-zero per_device_auto_alloc_size,
+ 3. If the device's uclass specifies a non-zero per_device_auto,
then this space is allocated and zeroed also. It is allocated for and
stored in the device, but it is uclass data. owned by the uclass driver.
It is possible for the device to access it.
- 4. If the device's immediate parent specifies a per_child_auto_alloc_size
+ 4. If the device's immediate parent specifies a per_child_auto
then this space is allocated. This is intended for use by the parent
device to keep track of things related to the child. For example a USB
flash stick attached to a USB host controller would likely use this
space. The controller can hold information about the USB state of each
of its children.
- 5. If the driver provides an ofdata_to_platdata() method, then this is
+ 5. If the driver provides an of_to_plat() method, then this is
called to convert the device tree data into platform data. This should
do various calls like dev_read_u32(dev, ...) to access the node and store
- the resulting information into dev->platdata. After this point, the device
+ the resulting information into dev->plat. After this point, the device
works the same way whether it was bound using a device tree node or
U_BOOT_DEVICE() structure. In either case, the platform data is now stored
- in the platdata structure. Typically you will use the
- platdata_auto_alloc_size feature to specify the size of the platform data
+ in the plat structure. Typically you will use the
+ plat_auto feature to specify the size of the platform data
structure, and U-Boot will automatically allocate and zero it for you before
- entry to ofdata_to_platdata(). But if not, you can allocate it yourself in
- ofdata_to_platdata(). Note that it is preferable to do all the device tree
- decoding in ofdata_to_platdata() rather than in probe(). (Apart from the
+ entry to of_to_plat(). But if not, you can allocate it yourself in
+ of_to_plat(). Note that it is preferable to do all the device tree
+ decoding in of_to_plat() rather than in probe(). (Apart from the
ugliness of mixing configuration and run-time data, one day it is possible
that U-Boot will cache platform data for devices which are regularly
de/activated).
- 5. The device is marked 'platdata valid'.
+ 6. The device is marked 'plat valid'.
Note that ofdata reading is always done (for a child and all its parents)
before probing starts. Thus devices go through two distinct states when
Having probing separate from ofdata-reading helps deal with of-platdata, where
the probe() method is common to both DT/of-platdata operation, but the
-ofdata_to_platdata() method is implemented differently.
+of_to_plat() method is implemented differently.
Another case has come up where this separate is useful. Generation of ACPI
tables uses the of-platdata but does not want to probe the device. Probing
present will cause an error on probe, yet we still must tell Linux about
the SD card connector in case it is used while Linux is running.
-It is important that the ofdata_to_platdata() method does not actually probe
+It is important that the of_to_plat() method does not actually probe
the device itself. However there are cases where other devices must be probed
-in the ofdata_to_platdata() method. An example is where a device requires a
+in the of_to_plat() method. An example is where a device requires a
GPIO for it to operate. To select a GPIO obviously requires that the GPIO
device is probed. This is OK when used by common, core devices such as GPIO,
clock, interrupts, reset and the like.
If your device relies on its parent setting up a suitable address space, so
that dev_read_addr() works correctly, then make sure that the parent device
-has its setup code in ofdata_to_platdata(). If it has it in the probe method,
+has its setup code in of_to_plat(). If it has it in the probe method,
then you cannot call dev_read_addr() from the child device's
-ofdata_to_platdata() method. Move it to probe() instead. Buses like PCI can
+of_to_plat() method. Move it to probe() instead. Buses like PCI can
fall afoul of this rule.
Activation/probe
hardware and setting up hardware registers to initial values. The code
in probe() can access:
- - platform data in dev->platdata (for configuration)
+ - platform data in dev->plat (for configuration)
- private data in dev->priv (for run-time state)
- uclass data in dev->uclass_priv (for things the uclass stores
about this device)
- Note: If you don't use priv_auto_alloc_size then you will need to
+ Note: If you don't use priv_auto then you will need to
allocate the priv space here yourself. The same applies also to
- platdata_auto_alloc_size. Remember to free them in the remove() method.
+ plat_auto. Remember to free them in the remove() method.
5. The device is marked 'activated'
be dynamically allocated, and thus needs to be deallocated during the
remove() method, either:
- - if the platdata_auto_alloc_size is non-zero, the deallocation
+ - if the plat_auto is non-zero, the deallocation
happens automatically within the driver model core; or
- - when platdata_auto_alloc_size is 0, both the allocation (in probe()
- or preferably ofdata_to_platdata()) and the deallocation in remove()
+ - when plat_auto is 0, both the allocation (in probe()
+ or preferably of_to_plat()) and the deallocation in remove()
are the responsibility of the driver author.
5. The device sequence number is set to -1, meaning that it no longer
the driver operations structure in the driver, rather than passing it
to the driver bind function.
- Rename some structures to make them more similar to Linux (struct udevice
- instead of struct instance, struct platdata, etc.)
+ instead of struct instance, struct plat, etc.)
- Change the name 'core' to 'uclass', meaning U-Boot class. It seems that
this concept relates to a class of drivers (or a subsystem). We shouldn't
use 'class' since it is a C++ reserved word, so U-Boot class (uclass) seems
better than 'core'.
- Remove 'struct driver_instance' and just use a single 'struct udevice'.
This removes a level of indirection that doesn't seem necessary.
-- Built in device tree support, to avoid the need for platdata
+- Built in device tree support, to avoid the need for plat
- Removed the concept of driver relocation, and just make it possible for
the new driver (created after relocation) to access the old driver data.
I feel that relocation is a very special case and will only apply to a few
.name = "eth_ape",
.id = UCLASS_ETH,
.of_match = eth_ape_ids,
- .ofdata_to_platdata = eth_ape_ofdata_to_platdata,
+ .of_to_plat = eth_ape_of_to_plat,
.probe = eth_ape_probe,
.ops = ð_ape_ops,
- .priv_auto_alloc_size = sizeof(struct eth_ape_priv),
- .platdata_auto_alloc_size = sizeof(struct eth_ape_pdata),
+ .priv_auto = sizeof(struct eth_ape_priv),
+ .plat_auto = sizeof(struct eth_ape_pdata),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
struct eth_ape_priv contains runtime per-instance data, like buffers, pointers
to current descriptors, current speed settings, pointers to PHY related data
-(like struct mii_dev) and so on. Declaring its size in .priv_auto_alloc_size
+(like struct mii_dev) and so on. Declaring its size in .priv_auto
will let the driver framework allocate it at the right time.
It can be retrieved using a dev_get_priv(dev) call.
a hardware variant, the MAC address. ``struct eth_pdata eth_pdata``
as the first member of this struct helps to avoid duplicated code.
If you don't need any more platform data beside the standard member,
-just use sizeof(struct eth_pdata) for the platdata_auto_alloc_size.
+just use sizeof(struct eth_pdata) for the plat_auto.
PCI devices add a line pointing to supported vendor/device ID pairs:
and/or PHY, and waiting for the link to autonegotiate. You should also take
the opportunity to program the device's MAC address with the enetaddr member
of the generic struct eth_pdata (which would be the first member of your
-own platdata struct). This allows the rest of U-Boot to dynamically change
+own plat struct). This allows the rest of U-Boot to dynamically change
the MAC address and have the new settings be respected.
The **send** function does what you think -- transmit the specified packet
U_BOOT_DEVICE(dwmmc_at_ff0c0000) = {
.name = "rockchip_rk3288_dw_mshc",
- .platdata = &dtv_dwmmc_at_ff0c0000,
- .platdata_size = sizeof(dtv_dwmmc_at_ff0c0000),
+ .plat = &dtv_dwmmc_at_ff0c0000,
+ .plat_size = sizeof(dtv_dwmmc_at_ff0c0000),
.parent_idx = -1,
};
.. code-block:: c
struct udevice *dev;
- struct dtd_rockchip_rk3288_dw_mshc *plat = dev_get_platdata(dev);
+ struct dtd_rockchip_rk3288_dw_mshc *plat = dev_get_plat(dev);
This avoids the code overhead of converting the device tree data to
-platform data in the driver. The ofdata_to_platdata() method should
+platform data in the driver. The of_to_plat() method should
therefore do nothing in such a driver.
Note that for the platform data to be matched with a driver, the 'name'
Therefore it is recommended that the of-platdata structure should be used
only in the probe() method of your driver. It cannot be used in the
-ofdata_to_platdata() method since this is not called when platform data is
+of_to_plat() method since this is not called when platform data is
already present.
Drivers should always support device tree as an option. The of-platdata
feature is intended as a add-on to existing drivers.
-Your driver should convert the platdata struct in its probe() method. The
+Your driver should convert the plat struct in its probe() method. The
existing device tree decoding logic should be kept in the
-ofdata_to_platdata() method and wrapped with #if.
+of_to_plat() method and wrapped with #if.
For example:
#include <dt-structs.h>
- struct mmc_platdata {
+ struct mmc_plat {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
/* Put this first since driver model will copy the data here */
struct dtd_mmc dtplat;
int fifo_depth;
};
- static int mmc_ofdata_to_platdata(struct udevice *dev)
+ static int mmc_of_to_plat(struct udevice *dev)
{
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
/* Decode the device tree data */
- struct mmc_platdata *plat = dev_get_platdata(dev);
+ struct mmc_plat *plat = dev_get_plat(dev);
const void *blob = gd->fdt_blob;
int node = dev_of_offset(dev);
static int mmc_probe(struct udevice *dev)
{
- struct mmc_platdata *plat = dev_get_platdata(dev);
+ struct mmc_plat *plat = dev_get_plat(dev);
#if CONFIG_IS_ENABLED(OF_PLATDATA)
/* Decode the of-platdata from the C structures */
.name = "mmc_drv",
.id = UCLASS_MMC,
.of_match = mmc_ids,
- .ofdata_to_platdata = mmc_ofdata_to_platdata,
+ .of_to_plat = mmc_of_to_plat,
.probe = mmc_probe,
- .priv_auto_alloc_size = sizeof(struct mmc_priv),
- .platdata_auto_alloc_size = sizeof(struct mmc_platdata),
+ .priv_auto = sizeof(struct mmc_priv),
+ .plat_auto = sizeof(struct mmc_plat),
};
U_BOOT_DRIVER_ALIAS(mmc_drv, vendor_mmc) /* matches compatible string */
-Note that struct mmc_platdata is defined in the C file, not in a header. This
+Note that struct mmc_plat is defined in the C file, not in a header. This
is to avoid needing to include dt-structs.h in a header file. The idea is to
keep the use of each of-platdata struct to the smallest possible code area.
There is just one driver C file for each struct, that can convert from the
of-platdata struct to the standard one used by the driver.
-In the case where SPL_OF_PLATDATA is enabled, platdata_auto_alloc_size is
+In the case where SPL_OF_PLATDATA is enabled, plat_auto is
still used to allocate space for the platform data. This is different from
the normal behaviour and is triggered by the use of of-platdata (strictly
-speaking it is a non-zero platdata_size which triggers this).
+speaking it is a non-zero plat_size which triggers this).
The of-platdata struct contents is copied from the C structure data to the
start of the newly allocated area. In the case where device tree is used,
the platform data is allocated, and starts zeroed. In this case the
-ofdata_to_platdata() method should still set up the platform data (and the
+of_to_plat() method should still set up the platform data (and the
of-platdata struct will not be present).
SPL must use either of-platdata or device tree. Drivers cannot use both at
prevents them being used inadvertently. All usage must be bracketed with
#if CONFIG_IS_ENABLED(OF_PLATDATA).
-The dt-platdata.c file contains the device declarations and is is built in
-spl/dt-platdata.c. It additionally contains the definition of
+The dt-plat.c file contains the device declarations and is is built in
+spl/dt-plat.c. It additionally contains the definition of
dm_populate_phandle_data() which is responsible of filling the phandle
information by adding references to U_BOOT_DEVICE by using DM_GET_DEVICE
U_BOOT_DEVICE(proc_3_demo) = {
.name = "sandbox_test_proc",
- .platdata = &proc_3_test,
+ .plat = &proc_3_test,
};
There can be additional data that may be desired depending on the
return NULL;
}
- static int exynos_spi_ofdata_to_platdata(struct udevice *dev)
+ static int exynos_spi_of_to_plat(struct udevice *dev)
{
return -ENODEV;
}
.id = UCLASS_SPI,
.of_match = exynos_spi_ids,
.ops = &exynos_spi_ops,
- .ofdata_to_platdata = exynos_spi_ofdata_to_platdata,
+ .of_to_plat = exynos_spi_of_to_plat,
.probe = exynos_spi_probe,
.remove = exynos_spi_remove,
};
.. code-block:: c
- struct exynos_spi_platdata {
+ struct exynos_spi_plat {
enum periph_id periph_id;
s32 frequency; /* Default clock frequency, -1 for none */
struct exynos_spi *regs;
};
-Write ofdata_to_platdata() [for device tree only]
+Write of_to_plat() [for device tree only]
-------------------------------------------------
This method will convert information in the device tree node into a C
U_BOOT_DRIVER(spi_exynos) = {
...
- .platdata_auto_alloc_size = sizeof(struct exynos_spi_platdata),
+ .plat_auto = sizeof(struct exynos_spi_plat),
Here is a sample function. It gets a pointer to the platform data and
.. code-block:: c
- static int exynos_spi_ofdata_to_platdata(struct udevice *bus)
+ static int exynos_spi_of_to_plat(struct udevice *bus)
{
- struct exynos_spi_platdata *plat = bus->platdata;
+ struct exynos_spi_plat *plat = bus->plat;
const void *blob = gd->fdt_blob;
int node = dev_of_offset(bus);
.. code-block:: c
- struct exynos_spi_platdata platdata_spi0 = {
+ struct exynos_spi_plat platdata_spi0 = {
.periph_id = ...
.frequency = ...
.regs = ...
U_BOOT_DEVICE(board_spi0) = {
.name = "exynos_spi",
- .platdata = &platdata_spi0,
+ .plat = &platdata_spi0,
};
You will unfortunately need to put the struct definition into a header file
U_BOOT_DRIVER(spi_exynos) = {
...
- .priv_auto_alloc_size = sizeof(struct exynos_spi_priv),
+ .priv_auto = sizeof(struct exynos_spi_priv),
Note that this is created before the probe method is called, and destroyed
static int exynos_spi_probe(struct udevice *bus)
{
- struct exynos_spi_platdata *plat = dev_get_platdata(bus);
+ struct exynos_spi_plat *plat = dev_get_plat(bus);
struct exynos_spi_priv *priv = dev_get_priv(bus);
priv->regs = plat->regs;
static int exynos_spi_set_speed(struct udevice *bus, uint speed)
{
- struct exynos_spi_platdata *plat = bus->platdata;
+ struct exynos_spi_plat *plat = bus->plat;
struct exynos_spi_priv *priv = dev_get_priv(bus);
int ret;
static void spi_cs_activate(struct udevice *dev)
{
struct udevice *bus = dev->parent;
- struct exynos_spi_platdata *pdata = dev_get_platdata(bus);
+ struct exynos_spi_plat *pdata = dev_get_plat(bus);
struct exynos_spi_priv *priv = dev_get_priv(bus);
/* If it's too soon to do another transaction, wait */
U_BOOT_DRIVER(exynos_spi) = {
...
- .per_child_auto_alloc_size = sizeof(struct spi_slave),
+ .per_child_auto = sizeof(struct spi_slave),
}
The SPI uclass keeps some information about each device 'dev' on the bus:
- struct dm_spi_slave_platdata:
- This is device_get_parent_platdata(dev).
+ struct dm_spi_slave_plat:
+ This is device_get_parent_plat(dev).
This is where the chip select number is stored, along with
the default bus speed and mode. It is automatically read
from the device tree in spi_child_post_bind(). It must not
.name = "ehci_tegra",
.id = UCLASS_USB,
.of_match = ehci_usb_ids,
- .ofdata_to_platdata = ehci_usb_ofdata_to_platdata,
+ .of_to_plat = ehci_usb_of_to_plat,
.probe = tegra_ehci_usb_probe,
.remove = tegra_ehci_usb_remove,
.ops = &ehci_usb_ops,
- .platdata_auto_alloc_size = sizeof(struct usb_platdata),
- .priv_auto_alloc_size = sizeof(struct fdt_usb),
+ .plat_auto = sizeof(struct usb_plat),
+ .priv_auto = sizeof(struct fdt_usb),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
Here ehci_usb_ids is used to list the controllers that the driver supports.
Each has its own data value. Controllers must be in the UCLASS_USB uclass.
-The ofdata_to_platdata() method allows the controller driver to grab any
+The of_to_plat() method allows the controller driver to grab any
necessary settings from the device tree.
The ops here are ehci_usb_ops. All EHCI drivers will use these same ops in
most cases, since they are all EHCI-compatible. For EHCI there are also some
special operations that can be overridden when calling ehci_register().
-The driver can use priv_auto_alloc_size to set the size of its private data.
+The driver can use priv_auto to set the size of its private data.
This can hold run-time information needed by the driver for operation. It
exists when the device is probed (not when it is bound) and is removed when
the driver is removed.
-Note that usb_platdata is currently only used to deal with setting up a bus
+Note that usb_plat is currently only used to deal with setting up a bus
in USB device mode (OTG operation). It can be omitted if that is not
supported.
handles that). Once the device is set up, you can find the device
descriptor and current configuration descriptor in this structure.
-- struct usb_platdata:
+- struct usb_plat:
This holds platform data for a controller. So far this is only used
as a work-around for controllers which can act as USB devices in OTG
mode, since the gadget framework does not use driver model.
-- struct usb_dev_platdata:
+- struct usb_dev_plat:
This holds platform data for a device. You can access it for a
- device 'dev' with dev_get_parent_platdata(dev). It holds the device
+ device 'dev' with dev_get_parent_plat(dev). It holds the device
address and speed - anything that can be determined before the device
driver is actually set up. When probing the bus this structure is
used to provide essential information to the device driver.
modify clk-uclass.c file and add there struct uc_clk_priv, which would have
clock related members (like pointer to clk). As of this writing there is no
such need, so to avoid extra allocations (as it can be auto allocated by
- setting .per_device_auto_alloc_size = sizeof(struct uc_clk_priv)) the
+ setting .per_device_auto = sizeof(struct uc_clk_priv)) the
uclass_priv stores the pointer to struct clk.
* Non-CCF clocks do not have a pointer to a clock in clk->dev->priv. In the case
#include <linux/delay.h>
#include <power/regulator.h>
-#define ADC_UCLASS_PLATDATA_SIZE sizeof(struct adc_uclass_platdata)
+#define ADC_UCLASS_PLATDATA_SIZE sizeof(struct adc_uclass_plat)
#define CHECK_NUMBER true
#define CHECK_MASK (!CHECK_NUMBER)
static int check_channel(struct udevice *dev, int value, bool number_or_mask,
const char *caller_function)
{
- struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);
+ struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
unsigned mask = number_or_mask ? (1 << value) : value;
/* For the real ADC hardware, some ADC channels can be inactive.
static int adc_supply_enable(struct udevice *dev)
{
- struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);
+ struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
const char *supply_type;
int ret = 0;
int adc_data_mask(struct udevice *dev, unsigned int *data_mask)
{
- struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);
+ struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
if (!uc_pdata)
return -ENOSYS;
int adc_channel_mask(struct udevice *dev, unsigned int *channel_mask)
{
- struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);
+ struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
if (!uc_pdata)
return -ENOSYS;
int adc_channel_data(struct udevice *dev, int channel, unsigned int *data)
{
- struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);
+ struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
const struct adc_ops *ops = dev_get_driver_ops(dev);
unsigned int timeout_us = uc_pdata->data_timeout_us;
int ret;
int adc_channels_data(struct udevice *dev, unsigned int channel_mask,
struct adc_channel *channels)
{
- struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);
+ struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
unsigned int timeout_us = uc_pdata->multidata_timeout_us;
const struct adc_ops *ops = dev_get_driver_ops(dev);
int ret;
return _adc_channels_single_shot(dev, channel_mask, channels);
}
-static int adc_vdd_platdata_update(struct udevice *dev)
+static int adc_vdd_plat_update(struct udevice *dev)
{
- struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);
+ struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
int ret;
/* Warning!
return 0;
}
-static int adc_vss_platdata_update(struct udevice *dev)
+static int adc_vss_plat_update(struct udevice *dev)
{
- struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);
+ struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
int ret;
if (!uc_pdata->vss_supply)
int adc_vdd_value(struct udevice *dev, int *uV)
{
- struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);
+ struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
int ret, value_sign = uc_pdata->vdd_polarity_negative ? -1 : 1;
/* Update the regulator Value. */
- ret = adc_vdd_platdata_update(dev);
+ ret = adc_vdd_plat_update(dev);
if (ret)
return ret;
int adc_vss_value(struct udevice *dev, int *uV)
{
- struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);
+ struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
int ret, value_sign = uc_pdata->vss_polarity_negative ? -1 : 1;
/* Update the regulator Value. */
- ret = adc_vss_platdata_update(dev);
+ ret = adc_vss_plat_update(dev);
if (ret)
return ret;
return 0;
}
-static int adc_vdd_platdata_set(struct udevice *dev)
+static int adc_vdd_plat_set(struct udevice *dev)
{
- struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);
+ struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
int ret;
char *prop;
ret = device_get_supply_regulator(dev, "vdd-supply",
&uc_pdata->vdd_supply);
if (!ret)
- return adc_vdd_platdata_update(dev);
+ return adc_vdd_plat_update(dev);
if (ret != -ENOENT)
return ret;
return 0;
}
-static int adc_vss_platdata_set(struct udevice *dev)
+static int adc_vss_plat_set(struct udevice *dev)
{
- struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);
+ struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
int ret;
char *prop;
ret = device_get_supply_regulator(dev, "vss-supply",
&uc_pdata->vss_supply);
if (!ret)
- return adc_vss_platdata_update(dev);
+ return adc_vss_plat_update(dev);
if (ret != -ENOENT)
return ret;
{
int ret;
- /* Set ADC VDD platdata: polarity, uV, regulator (phandle). */
- ret = adc_vdd_platdata_set(dev);
+ /* Set ADC VDD plat: polarity, uV, regulator (phandle). */
+ ret = adc_vdd_plat_set(dev);
if (ret)
pr_err("%s: Can't update Vdd. Error: %d", dev->name, ret);
- /* Set ADC VSS platdata: polarity, uV, regulator (phandle). */
- ret = adc_vss_platdata_set(dev);
+ /* Set ADC VSS plat: polarity, uV, regulator (phandle). */
+ ret = adc_vss_plat_set(dev);
if (ret)
pr_err("%s: Can't update Vss. Error: %d", dev->name, ret);
.id = UCLASS_ADC,
.name = "adc",
.pre_probe = adc_pre_probe,
- .per_device_platdata_auto_alloc_size = ADC_UCLASS_PLATDATA_SIZE,
+ .per_device_plat_auto = ADC_UCLASS_PLATDATA_SIZE,
};
return 0;
}
-int exynos_adc_ofdata_to_platdata(struct udevice *dev)
+int exynos_adc_of_to_plat(struct udevice *dev)
{
- struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);
+ struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
struct exynos_adc_priv *priv = dev_get_priv(dev);
priv->regs = dev_read_addr_ptr(dev);
.of_match = exynos_adc_ids,
.ops = &exynos_adc_ops,
.probe = exynos_adc_probe,
- .ofdata_to_platdata = exynos_adc_ofdata_to_platdata,
- .priv_auto_alloc_size = sizeof(struct exynos_adc_priv),
+ .of_to_plat = exynos_adc_of_to_plat,
+ .priv_auto = sizeof(struct exynos_adc_priv),
};
return 0;
}
-int meson_saradc_ofdata_to_platdata(struct udevice *dev)
+int meson_saradc_of_to_plat(struct udevice *dev)
{
- struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);
+ struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
struct meson_saradc_priv *priv = dev_get_priv(dev);
priv->data = (struct meson_saradc_data *)dev_get_driver_data(dev);
.of_match = meson_saradc_ids,
.ops = &meson_saradc_ops,
.probe = meson_saradc_probe,
- .ofdata_to_platdata = meson_saradc_ofdata_to_platdata,
- .priv_auto_alloc_size = sizeof(struct meson_saradc_priv),
+ .of_to_plat = meson_saradc_of_to_plat,
+ .priv_auto = sizeof(struct meson_saradc_priv),
};
unsigned int *data)
{
struct rockchip_saradc_priv *priv = dev_get_priv(dev);
- struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);
+ struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
if (channel != priv->active_channel) {
pr_err("Requested channel is not active!");
return 0;
}
-int rockchip_saradc_ofdata_to_platdata(struct udevice *dev)
+int rockchip_saradc_of_to_plat(struct udevice *dev)
{
- struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);
+ struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
struct rockchip_saradc_priv *priv = dev_get_priv(dev);
struct rockchip_saradc_data *data;
.of_match = rockchip_saradc_ids,
.ops = &rockchip_saradc_ops,
.probe = rockchip_saradc_probe,
- .ofdata_to_platdata = rockchip_saradc_ofdata_to_platdata,
- .priv_auto_alloc_size = sizeof(struct rockchip_saradc_priv),
+ .of_to_plat = rockchip_saradc_of_to_plat,
+ .priv_auto = sizeof(struct rockchip_saradc_priv),
};
return 0;
}
-int sandbox_adc_ofdata_to_platdata(struct udevice *dev)
+int sandbox_adc_of_to_plat(struct udevice *dev)
{
- struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);
+ struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
uc_pdata->data_mask = SANDBOX_ADC_DATA_MASK;
uc_pdata->data_format = ADC_DATA_FORMAT_BIN;
.of_match = sandbox_adc_ids,
.ops = &sandbox_adc_ops,
.probe = sandbox_adc_probe,
- .ofdata_to_platdata = sandbox_adc_ofdata_to_platdata,
- .priv_auto_alloc_size = sizeof(struct sandbox_adc_priv),
+ .of_to_plat = sandbox_adc_of_to_plat,
+ .priv_auto = sizeof(struct sandbox_adc_priv),
};
.id = UCLASS_SIMPLE_BUS,
.of_match = stm32_adc_core_ids,
.probe = stm32_adc_core_probe,
- .priv_auto_alloc_size = sizeof(struct stm32_adc_common),
+ .priv_auto = sizeof(struct stm32_adc_common),
};
static int stm32_adc_start_channel(struct udevice *dev, int channel)
{
- struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);
+ struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
struct stm32_adc_common *common = dev_get_priv(dev_get_parent(dev));
struct stm32_adc *adc = dev_get_priv(dev);
int ret;
static int stm32_adc_chan_of_init(struct udevice *dev)
{
- struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);
+ struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
struct stm32_adc *adc = dev_get_priv(dev);
u32 chans[STM32_ADC_CH_MAX];
unsigned int i, num_channels;
static int stm32_adc_probe(struct udevice *dev)
{
- struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);
+ struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
struct stm32_adc_common *common = dev_get_priv(dev_get_parent(dev));
struct stm32_adc *adc = dev_get_priv(dev);
int offset;
.of_match = stm32_adc_ids,
.probe = stm32_adc_probe,
.ops = &stm32_adc_ops,
- .priv_auto_alloc_size = sizeof(struct stm32_adc),
+ .priv_auto = sizeof(struct stm32_adc),
};
UCLASS_DRIVER(ahci) = {
.id = UCLASS_AHCI,
.name = "ahci",
- .per_device_auto_alloc_size = sizeof(struct ahci_uc_priv),
+ .per_device_auto = sizeof(struct ahci_uc_priv),
};
#if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
# ifdef CONFIG_DM_PCI
struct udevice *dev = uc_priv->dev;
- struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
+ struct pci_child_plat *pplat = dev_get_parent_plat(dev);
# else
pci_dev_t pdev = uc_priv->dev;
unsigned short vendor;
pci_write_config_byte(dev, 0x41, 0xa1);
#endif
#else
- struct scsi_platdata *plat = dev_get_uclass_platdata(dev);
+ struct scsi_plat *plat = dev_get_uclass_plat(dev);
uc_priv->mmio_base = (void *)plat->base;
#endif
int ahci_probe_scsi(struct udevice *ahci_dev, ulong base)
{
struct ahci_uc_priv *uc_priv;
- struct scsi_platdata *uc_plat;
+ struct scsi_plat *uc_plat;
struct udevice *dev;
int ret;
device_find_first_child(ahci_dev, &dev);
if (!dev)
return -ENODEV;
- uc_plat = dev_get_uclass_platdata(dev);
+ uc_plat = dev_get_uclass_plat(dev);
uc_plat->base = base;
uc_plat->max_lun = 1;
uc_plat->max_id = 2;
return ahci_bind_scsi(dev, &scsi_dev);
}
-static int dwc_ahci_ofdata_to_platdata(struct udevice *dev)
+static int dwc_ahci_of_to_plat(struct udevice *dev)
{
struct dwc_ahci_priv *priv = dev_get_priv(dev);
fdt_addr_t addr;
.id = UCLASS_AHCI,
.of_match = dwc_ahci_ids,
.bind = dwc_ahci_bind,
- .ofdata_to_platdata = dwc_ahci_ofdata_to_platdata,
+ .of_to_plat = dwc_ahci_of_to_plat,
.ops = &scsi_ops,
.probe = dwc_ahci_probe,
- .priv_auto_alloc_size = sizeof(struct dwc_ahci_priv),
+ .priv_auto = sizeof(struct dwc_ahci_priv),
};
}
}
- desc = dev_get_uclass_platdata(blk);
+ desc = dev_get_uclass_plat(blk);
ret = dwc_ahsata_scan_common(uc_priv, desc);
if (ret) {
debug("%s: Failed to scan bus\n", __func__);
static ulong dwc_ahsata_read(struct udevice *blk, lbaint_t blknr,
lbaint_t blkcnt, void *buffer)
{
- struct blk_desc *desc = dev_get_uclass_platdata(blk);
+ struct blk_desc *desc = dev_get_uclass_plat(blk);
struct udevice *dev = dev_get_parent(blk);
struct ahci_uc_priv *uc_priv;
static ulong dwc_ahsata_write(struct udevice *blk, lbaint_t blknr,
lbaint_t blkcnt, const void *buffer)
{
- struct blk_desc *desc = dev_get_uclass_platdata(blk);
+ struct blk_desc *desc = dev_get_uclass_plat(blk);
struct udevice *dev = dev_get_parent(blk);
struct ahci_uc_priv *uc_priv;
static ulong sata_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
void *buffer)
{
- struct fsl_ata_priv *priv = dev_get_platdata(dev);
+ struct fsl_ata_priv *priv = dev_get_plat(dev);
fsl_sata_t *sata = priv->fsl_sata;
#endif
u32 rc;
static ulong sata_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
const void *buffer)
{
- struct fsl_ata_priv *priv = dev_get_platdata(dev);
+ struct fsl_ata_priv *priv = dev_get_plat(dev);
fsl_sata_t *sata = priv->fsl_sata;
#endif
u32 rc;
#else
static int scan_sata(struct udevice *dev)
{
- struct blk_desc *desc = dev_get_uclass_platdata(dev);
- struct fsl_ata_priv *priv = dev_get_platdata(dev);
+ struct blk_desc *desc = dev_get_uclass_plat(dev);
+ struct fsl_ata_priv *priv = dev_get_plat(dev);
fsl_sata_t *sata = priv->fsl_sata;
#endif
.name = "sata_fsl_blk",
.id = UCLASS_BLK,
.ops = &sata_fsl_blk_ops,
- .platdata_auto_alloc_size = sizeof(struct fsl_ata_priv),
+ .plat_auto = sizeof(struct fsl_ata_priv),
};
-static int fsl_ata_ofdata_to_platdata(struct udevice *dev)
+static int fsl_ata_of_to_plat(struct udevice *dev)
{
struct fsl_ata_priv *priv = dev_get_priv(dev);
continue;
}
- blk_priv = dev_get_platdata(blk);
+ blk_priv = dev_get_plat(blk);
blk_priv->fsl_sata = priv->fsl_sata;
/* Scan SATA port */
ret = scan_sata(blk);
.id = UCLASS_AHCI,
.of_match = fsl_ata_ids,
.ops = &sata_fsl_ahci_ops,
- .ofdata_to_platdata = fsl_ata_ofdata_to_platdata,
+ .of_to_plat = fsl_ata_of_to_plat,
.probe = fsl_ata_probe,
.remove = fsl_ata_remove,
- .priv_auto_alloc_size = sizeof(struct fsl_ata_priv),
+ .priv_auto = sizeof(struct fsl_ata_priv),
};
#endif
return ahci_bind_scsi(dev, &scsi_dev);
}
-static int mtk_ahci_ofdata_to_platdata(struct udevice *dev)
+static int mtk_ahci_of_to_plat(struct udevice *dev)
{
struct mtk_ahci_priv *priv = dev_get_priv(dev);
.id = UCLASS_AHCI,
.of_match = mtk_ahci_ids,
.bind = mtk_ahci_bind,
- .ofdata_to_platdata = mtk_ahci_ofdata_to_platdata,
+ .of_to_plat = mtk_ahci_of_to_plat,
.ops = &scsi_ops,
.probe = mtk_ahci_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_ahci_priv),
+ .priv_auto = sizeof(struct mtk_ahci_priv),
};
{ }
};
-static int sata_ceva_ofdata_to_platdata(struct udevice *dev)
+static int sata_ceva_of_to_plat(struct udevice *dev)
{
struct ceva_sata_priv *priv = dev_get_priv(dev);
struct resource res_regs;
.of_match = sata_ceva_ids,
.bind = sata_ceva_bind,
.ops = &scsi_ops,
- .priv_auto_alloc_size = sizeof(struct ceva_sata_priv),
+ .priv_auto = sizeof(struct ceva_sata_priv),
.probe = sata_ceva_probe,
- .ofdata_to_platdata = sata_ceva_ofdata_to_platdata,
+ .of_to_plat = sata_ceva_of_to_plat,
};
/* Cut from sata_mv in linux kernel */
static int mv_stop_edma_engine(struct udevice *dev, int port)
{
- struct mv_priv *priv = dev_get_platdata(dev);
+ struct mv_priv *priv = dev_get_plat(dev);
int i;
/* Disable eDMA. The disable bit auto clears. */
static int mv_start_edma_engine(struct udevice *dev, int port)
{
- struct mv_priv *priv = dev_get_platdata(dev);
+ struct mv_priv *priv = dev_get_plat(dev);
u32 tmp;
/* Check preconditions */
static int mv_reset_channel(struct udevice *dev, int port)
{
- struct mv_priv *priv = dev_get_platdata(dev);
+ struct mv_priv *priv = dev_get_plat(dev);
/* Make sure edma is stopped */
mv_stop_edma_engine(dev, port);
static void mv_reset_port(struct udevice *dev, int port)
{
- struct mv_priv *priv = dev_get_platdata(dev);
+ struct mv_priv *priv = dev_get_plat(dev);
mv_reset_channel(dev, port);
static int probe_port(struct udevice *dev, int port)
{
- struct mv_priv *priv = dev_get_platdata(dev);
+ struct mv_priv *priv = dev_get_plat(dev);
int tries, tries2, set15 = 0;
u32 tmp;
/* Get request queue in pointer */
static int get_reqip(struct udevice *dev, int port)
{
- struct mv_priv *priv = dev_get_platdata(dev);
+ struct mv_priv *priv = dev_get_plat(dev);
u32 tmp;
tmp = in_le32(priv->regbase + EDMA_RQIPR) & EDMA_RQIPR_IPMASK;
static void set_reqip(struct udevice *dev, int port, int reqin)
{
- struct mv_priv *priv = dev_get_platdata(dev);
+ struct mv_priv *priv = dev_get_plat(dev);
u32 tmp;
tmp = in_le32(priv->regbase + EDMA_RQIPR) & ~EDMA_RQIPR_IPMASK;
/* Get response queue in pointer */
static int get_rspip(struct udevice *dev, int port)
{
- struct mv_priv *priv = dev_get_platdata(dev);
+ struct mv_priv *priv = dev_get_plat(dev);
u32 tmp;
tmp = in_le32(priv->regbase + EDMA_RSIPR) & EDMA_RSIPR_IPMASK;
/* Get response queue out pointer */
static int get_rspop(struct udevice *dev, int port)
{
- struct mv_priv *priv = dev_get_platdata(dev);
+ struct mv_priv *priv = dev_get_plat(dev);
u32 tmp;
tmp = in_le32(priv->regbase + EDMA_RSOPR) & EDMA_RSOPR_OPMASK;
/* Set response queue pointer */
static void set_rspop(struct udevice *dev, int port, int reqin)
{
- struct mv_priv *priv = dev_get_platdata(dev);
+ struct mv_priv *priv = dev_get_plat(dev);
u32 tmp;
tmp = in_le32(priv->regbase + EDMA_RSOPR) & ~EDMA_RSOPR_OPMASK;
static void process_responses(struct udevice *dev, int port)
{
#ifdef DEBUG
- struct mv_priv *priv = dev_get_platdata(dev);
+ struct mv_priv *priv = dev_get_plat(dev);
#endif
u32 tmp;
u32 outind = get_rspop(dev, port);
struct sata_fis_h2d *cfis,
u8 *buffer, u32 len, u32 iswrite)
{
- struct mv_priv *priv = dev_get_platdata(dev);
+ struct mv_priv *priv = dev_get_plat(dev);
struct crqb *req;
int slot;
u32 start;
static u32 ata_low_level_rw(struct udevice *dev, int port, lbaint_t blknr,
lbaint_t blkcnt, void *buffer, int is_write)
{
- struct blk_desc *desc = dev_get_uclass_platdata(dev);
+ struct blk_desc *desc = dev_get_uclass_plat(dev);
lbaint_t start, blks;
u8 *addr;
int max_blks;
struct sata_fis_h2d *cfis, u8 *buffer,
u32 len, u32 iswrite)
{
- struct mv_priv *priv = dev_get_platdata(dev);
+ struct mv_priv *priv = dev_get_plat(dev);
int i;
u16 *tp;
static void mv_sata_xfer_mode(struct udevice *dev, int port, u16 *id)
{
- struct mv_priv *priv = dev_get_platdata(dev);
+ struct mv_priv *priv = dev_get_plat(dev);
priv->pio = id[ATA_ID_PIO_MODES];
priv->mwdma = id[ATA_ID_MWDMA_MODES];
static void mv_sata_set_features(struct udevice *dev, int port)
{
- struct mv_priv *priv = dev_get_platdata(dev);
+ struct mv_priv *priv = dev_get_plat(dev);
struct sata_fis_h2d cfis;
u8 udma_cap;
static int sata_mv_init_sata(struct udevice *dev, int port)
{
- struct mv_priv *priv = dev_get_platdata(dev);
+ struct mv_priv *priv = dev_get_plat(dev);
debug("Initialize sata dev: %d\n", port);
static int sata_mv_scan_sata(struct udevice *dev, int port)
{
- struct blk_desc *desc = dev_get_uclass_platdata(dev);
- struct mv_priv *priv = dev_get_platdata(dev);
+ struct blk_desc *desc = dev_get_uclass_plat(dev);
+ struct mv_priv *priv = dev_get_plat(dev);
unsigned char serial[ATA_ID_SERNO_LEN + 1];
unsigned char firmware[ATA_ID_FW_REV_LEN + 1];
unsigned char product[ATA_ID_PROD_LEN + 1];
static ulong sata_mv_read(struct udevice *blk, lbaint_t blknr,
lbaint_t blkcnt, void *buffer)
{
- struct mv_priv *priv = dev_get_platdata(blk);
+ struct mv_priv *priv = dev_get_plat(blk);
return ata_low_level_rw(blk, priv->dev_nr, blknr, blkcnt,
buffer, READ_CMD);
static ulong sata_mv_write(struct udevice *blk, lbaint_t blknr,
lbaint_t blkcnt, const void *buffer)
{
- struct mv_priv *priv = dev_get_platdata(blk);
+ struct mv_priv *priv = dev_get_plat(blk);
return ata_low_level_rw(blk, priv->dev_nr, blknr, blkcnt,
(void *)buffer, WRITE_CMD);
.name = "sata_mv_blk",
.id = UCLASS_BLK,
.ops = &sata_mv_blk_ops,
- .platdata_auto_alloc_size = sizeof(struct mv_priv),
+ .plat_auto = sizeof(struct mv_priv),
};
static int sata_mv_probe(struct udevice *dev)
return ret;
}
- priv = dev_get_platdata(blk);
+ priv = dev_get_plat(blk);
priv->dev_nr = i;
/* Init SATA port */
static ulong sata_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
void *buffer)
{
- struct sil_sata_priv *priv = dev_get_platdata(dev);
+ struct sil_sata_priv *priv = dev_get_plat(dev);
int port_number = priv->port_num;
struct sil_sata *sata = priv->sil_sata_desc[port_number];
#endif
ulong sata_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
const void *buffer)
{
- struct sil_sata_priv *priv = dev_get_platdata(dev);
+ struct sil_sata_priv *priv = dev_get_plat(dev);
int port_number = priv->port_num;
struct sil_sata *sata = priv->sil_sata_desc[port_number];
#endif
#else
static int sil_init_sata(struct udevice *uc_dev, int dev)
{
- struct sil_sata_priv *priv = dev_get_platdata(uc_dev);
+ struct sil_sata_priv *priv = dev_get_plat(uc_dev);
#endif
struct sil_sata *sata;
void *port;
#else
static int scan_sata(struct udevice *blk_dev, int dev)
{
- struct blk_desc *desc = dev_get_uclass_platdata(blk_dev);
- struct sil_sata_priv *priv = dev_get_platdata(blk_dev);
+ struct blk_desc *desc = dev_get_uclass_plat(blk_dev);
+ struct sil_sata_priv *priv = dev_get_plat(blk_dev);
struct sil_sata *sata = priv->sil_sata_desc[dev];
#endif
unsigned char serial[ATA_ID_SERNO_LEN + 1];
.name = "sata_sil_blk",
.id = UCLASS_BLK,
.ops = &sata_sil_blk_ops,
- .platdata_auto_alloc_size = sizeof(struct sil_sata_priv),
+ .plat_auto = sizeof(struct sil_sata_priv),
};
static int sil_unbind_device(struct udevice *dev)
.ops = &sata_sil_ops,
.probe = sil_pci_probe,
.remove = sil_pci_remove,
- .priv_auto_alloc_size = sizeof(struct sil_sata_priv),
+ .priv_auto = sizeof(struct sil_sata_priv),
};
U_BOOT_PCI_DEVICE(sil_ahci_pci, supported);
.id = UCLASS_AXI,
.of_match = ihs_axi_ids,
.ops = &ihs_axi_ops,
- .priv_auto_alloc_size = sizeof(struct ihs_axi_priv),
+ .priv_auto = sizeof(struct ihs_axi_priv),
.probe = ihs_axi_probe,
};
.id = UCLASS_AXI_EMUL,
.of_match = sandbox_store_ids,
.ops = &sandbox_store_ops,
- .priv_auto_alloc_size = sizeof(struct sandbox_store_priv),
+ .priv_auto = sizeof(struct sandbox_store_priv),
.probe = sandbox_store_probe,
.remove = sandbox_store_remove,
};
ret = blk_get_device(if_type, devnum, &dev);
if (ret)
return NULL;
- desc = dev_get_uclass_platdata(dev);
+ desc = dev_get_uclass_plat(dev);
return desc;
}
if (ret)
return NULL;
uclass_foreach_dev(dev, uc) {
- struct blk_desc *desc = dev_get_uclass_platdata(dev);
+ struct blk_desc *desc = dev_get_uclass_plat(dev);
debug("%s: if_type=%d, devnum=%d: %s, %d, %d\n", __func__,
if_type, devnum, dev->name, desc->if_type, desc->devnum);
if (device_get_uclass_id(child_dev) != UCLASS_BLK)
continue;
- return dev_get_uclass_platdata(child_dev);
+ return dev_get_uclass_plat(child_dev);
}
debug("%s: No block device found\n", __func__);
if (ret)
return ret;
uclass_foreach_dev(dev, uc) {
- struct blk_desc *desc = dev_get_uclass_platdata(dev);
+ struct blk_desc *desc = dev_get_uclass_plat(dev);
debug("%s: if_type=%d, devnum=%d: %s, %d, %d\n", __func__,
if_type, devnum, dev->name, desc->if_type, desc->devnum);
if (!*devp)
return -ENODEV;
do {
- desc = dev_get_uclass_platdata(*devp);
+ desc = dev_get_uclass_plat(*devp);
if (desc->if_type == if_type)
return 0;
ret = uclass_find_next_device(devp);
struct blk_desc *desc;
int ret, if_type;
- desc = dev_get_uclass_platdata(*devp);
+ desc = dev_get_uclass_plat(*devp);
if_type = desc->if_type;
do {
ret = uclass_find_next_device(devp);
return ret;
if (!*devp)
return -ENODEV;
- desc = dev_get_uclass_platdata(*devp);
+ desc = dev_get_uclass_plat(*devp);
if (desc->if_type == if_type)
return 0;
} while (1);
if (ret)
return ret;
uclass_foreach_dev(dev, uc) {
- struct blk_desc *desc = dev_get_uclass_platdata(dev);
+ struct blk_desc *desc = dev_get_uclass_plat(dev);
debug("%s: if_type=%d, devnum=%d: %s, %d, %d\n", __func__,
if_type, devnum, dev->name, desc->if_type, desc->devnum);
if (ret)
return ret;
uclass_foreach_dev(dev, uc) {
- struct blk_desc *desc = dev_get_uclass_platdata(dev);
+ struct blk_desc *desc = dev_get_uclass_plat(dev);
if (desc->if_type == if_type && desc->devnum > max_devnum)
max_devnum = desc->devnum;
if (ret)
return ret;
uclass_foreach_dev(dev, uc) {
- struct blk_desc *desc = dev_get_uclass_platdata(dev);
+ struct blk_desc *desc = dev_get_uclass_plat(dev);
if (desc->if_type == if_type && desc->devnum == devnum) {
int next = blk_next_free_devnum(if_type);
ret = device_bind_driver(parent, drv_name, name, &dev);
if (ret)
return ret;
- desc = dev_get_uclass_platdata(dev);
+ desc = dev_get_uclass_plat(dev);
desc->if_type = if_type;
desc->blksz = blksz;
desc->log2blksz = LOG2(desc->blksz);
if (ret)
return ret;
uclass_foreach_dev_safe(dev, next, uc) {
- struct blk_desc *desc = dev_get_uclass_platdata(dev);
+ struct blk_desc *desc = dev_get_uclass_plat(dev);
if (desc->if_type == if_type) {
ret = device_remove(dev, DM_REMOVE_NORMAL);
{
if (IS_ENABLED(CONFIG_PARTITIONS) &&
IS_ENABLED(CONFIG_HAVE_BLOCK_DEVICE)) {
- struct blk_desc *desc = dev_get_uclass_platdata(dev);
+ struct blk_desc *desc = dev_get_uclass_plat(dev);
part_init(desc);
}
.id = UCLASS_BLK,
.name = "blk",
.post_probe = blk_post_probe,
- .per_device_platdata_auto_alloc_size = sizeof(struct blk_desc),
+ .per_device_plat_auto = sizeof(struct blk_desc),
};
#endif
{
#ifdef CONFIG_BLK
- struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
+ struct blk_desc *block_dev = dev_get_uclass_plat(dev);
#endif
int device = block_dev->devnum;
ulong n = 0;
#endif
{
#ifdef CONFIG_BLK
- struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
+ struct blk_desc *block_dev = dev_get_uclass_plat(dev);
#endif
int device = block_dev->devnum;
ulong n = 0;
#ifdef CONFIG_BLK
static int ide_blk_probe(struct udevice *udev)
{
- struct blk_desc *desc = dev_get_uclass_platdata(udev);
+ struct blk_desc *desc = dev_get_uclass_plat(udev);
/* fill in device vendor/product/rev strings */
strncpy(desc->vendor, ide_dev_desc[desc->devnum].vendor,
unsigned long start, lbaint_t blkcnt,
void *buffer)
{
- struct host_block_dev *host_dev = dev_get_platdata(dev);
- struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
+ struct host_block_dev *host_dev = dev_get_plat(dev);
+ struct blk_desc *block_dev = dev_get_uclass_plat(dev);
#else
static unsigned long host_block_read(struct blk_desc *block_dev,
unsigned long start, lbaint_t blkcnt,
const void *buffer)
{
- struct host_block_dev *host_dev = dev_get_platdata(dev);
- struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
+ struct host_block_dev *host_dev = dev_get_plat(dev);
+ struct blk_desc *block_dev = dev_get_uclass_plat(dev);
#else
static unsigned long host_block_write(struct blk_desc *block_dev,
unsigned long start, lbaint_t blkcnt,
if (ret)
goto err_file;
- host_dev = dev_get_platdata(dev);
+ host_dev = dev_get_plat(dev);
host_dev->fd = fd;
host_dev->filename = fname;
ret = blk_get_device(IF_TYPE_HOST, devnum, &dev);
if (ret)
return ret;
- *blk_devp = dev_get_uclass_platdata(dev);
+ *blk_devp = dev_get_uclass_plat(dev);
#else
struct host_block_dev *host_dev = find_host_device(devnum);
.name = "sandbox_host_blk",
.id = UCLASS_BLK,
.ops = &sandbox_host_blk_ops,
- .platdata_auto_alloc_size = sizeof(struct host_block_dev),
+ .plat_auto = sizeof(struct host_block_dev),
};
#else
U_BOOT_LEGACY_BLK(sandbox_host) = {
U_BOOT_DRIVER(bootcount_mem) = {
.name = "bootcount-mem",
.id = UCLASS_BOOTCOUNT,
- .priv_auto_alloc_size = sizeof(struct bootcount_mem_priv),
+ .priv_auto = sizeof(struct bootcount_mem_priv),
.probe = bootcount_mem_probe,
.of_match = bootcount_mem_ids,
.ops = &bootcount_mem_ops,
U_BOOT_DRIVER(bootcount_spi_flash) = {
.name = "bootcount-i2c-eeprom",
.id = UCLASS_BOOTCOUNT,
- .priv_auto_alloc_size = sizeof(struct bootcount_i2c_eeprom_priv),
+ .priv_auto = sizeof(struct bootcount_i2c_eeprom_priv),
.probe = bootcount_i2c_eeprom_probe,
.of_match = bootcount_i2c_eeprom_ids,
.ops = &bootcount_i2c_eeprom_ops,
U_BOOT_DRIVER(bootcount_rtc) = {
.name = "bootcount-rtc",
.id = UCLASS_BOOTCOUNT,
- .priv_auto_alloc_size = sizeof(struct bootcount_rtc_priv),
+ .priv_auto = sizeof(struct bootcount_rtc_priv),
.probe = bootcount_rtc_probe,
.of_match = bootcount_rtc_ids,
.ops = &bootcount_rtc_ops,
U_BOOT_DRIVER(bootcount_spi_flash) = {
.name = "bootcount-spi-flash",
.id = UCLASS_BOOTCOUNT,
- .priv_auto_alloc_size = sizeof(struct bootcount_spi_flash_priv),
+ .priv_auto = sizeof(struct bootcount_spi_flash_priv),
.probe = bootcount_spi_flash_probe,
.of_match = bootcount_spi_flash_ids,
.ops = &bootcount_spi_flash_ops,
static int button_gpio_probe(struct udevice *dev)
{
- struct button_uc_plat *uc_plat = dev_get_uclass_platdata(dev);
+ struct button_uc_plat *uc_plat = dev_get_uclass_plat(dev);
struct button_gpio_priv *priv = dev_get_priv(dev);
int ret;
node, &dev);
if (ret)
return ret;
- uc_plat = dev_get_uclass_platdata(dev);
+ uc_plat = dev_get_uclass_plat(dev);
uc_plat->label = label;
}
.id = UCLASS_BUTTON,
.of_match = button_gpio_ids,
.ops = &button_gpio_ops,
- .priv_auto_alloc_size = sizeof(struct button_gpio_priv),
+ .priv_auto = sizeof(struct button_gpio_priv),
.bind = button_gpio_bind,
.probe = button_gpio_probe,
.remove = button_gpio_remove,
struct uclass *uc;
uclass_id_foreach_dev(UCLASS_BUTTON, dev, uc) {
- struct button_uc_plat *uc_plat = dev_get_uclass_platdata(dev);
+ struct button_uc_plat *uc_plat = dev_get_uclass_plat(dev);
/* Ignore the top-level button node */
if (uc_plat->label && !strcmp(label, uc_plat->label))
UCLASS_DRIVER(button) = {
.id = UCLASS_BUTTON,
.name = "button",
- .per_device_platdata_auto_alloc_size = sizeof(struct button_uc_plat),
+ .per_device_plat_auto = sizeof(struct button_uc_plat),
};
static int v5l2_enable(struct udevice *dev)
{
- struct v5l2_plat *plat = dev_get_platdata(dev);
+ struct v5l2_plat *plat = dev_get_plat(dev);
volatile struct l2cache *regs = plat->regs;
if (regs)
static int v5l2_disable(struct udevice *dev)
{
- struct v5l2_plat *plat = dev_get_platdata(dev);
+ struct v5l2_plat *plat = dev_get_plat(dev);
volatile struct l2cache *regs = plat->regs;
u8 hart = gd->arch.boot_hart;
void __iomem *cctlcmd = (void __iomem *)CCTL_CMD_REG(regs, hart);
return 0;
}
-static int v5l2_ofdata_to_platdata(struct udevice *dev)
+static int v5l2_of_to_plat(struct udevice *dev)
{
- struct v5l2_plat *plat = dev_get_platdata(dev);
+ struct v5l2_plat *plat = dev_get_plat(dev);
struct l2cache *regs;
regs = (struct l2cache *)dev_read_addr(dev);
static int v5l2_probe(struct udevice *dev)
{
- struct v5l2_plat *plat = dev_get_platdata(dev);
+ struct v5l2_plat *plat = dev_get_plat(dev);
struct l2cache *regs = plat->regs;
u32 ctl_val;
.name = "v5l2_cache",
.id = UCLASS_CACHE,
.of_match = v5l2_cache_ids,
- .ofdata_to_platdata = v5l2_ofdata_to_platdata,
+ .of_to_plat = v5l2_of_to_plat,
.probe = v5l2_probe,
- .platdata_auto_alloc_size = sizeof(struct v5l2_plat),
+ .plat_auto = sizeof(struct v5l2_plat),
.ops = &v5l2_cache_ops,
.flags = DM_FLAG_PRE_RELOC,
};
DECLARE_GLOBAL_DATA_PTR;
-struct socfpga_clk_platdata {
+struct socfpga_clk_plat {
void __iomem *regs;
};
* function to write the bypass register which requires a poll of the
* busy bit
*/
-static void clk_write_bypass_mainpll(struct socfpga_clk_platdata *plat, u32 val)
+static void clk_write_bypass_mainpll(struct socfpga_clk_plat *plat, u32 val)
{
CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_BYPASS);
cm_wait_for_fsm();
}
-static void clk_write_bypass_perpll(struct socfpga_clk_platdata *plat, u32 val)
+static void clk_write_bypass_perpll(struct socfpga_clk_plat *plat, u32 val)
{
CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_BYPASS);
cm_wait_for_fsm();
}
/* function to write the ctrl register which requires a poll of the busy bit */
-static void clk_write_ctrl(struct socfpga_clk_platdata *plat, u32 val)
+static void clk_write_ctrl(struct socfpga_clk_plat *plat, u32 val)
{
CM_REG_WRITEL(plat, val, CLKMGR_CTRL);
cm_wait_for_fsm();
},
};
-static int membus_wait_for_req(struct socfpga_clk_platdata *plat, u32 pll,
+static int membus_wait_for_req(struct socfpga_clk_plat *plat, u32 pll,
int timeout)
{
int cnt = 0;
return 0;
}
-static int membus_write_pll(struct socfpga_clk_platdata *plat, u32 pll,
+static int membus_write_pll(struct socfpga_clk_plat *plat, u32 pll,
u32 addr_offset, u32 wdat, int timeout)
{
u32 addr;
return membus_wait_for_req(plat, pll, timeout);
}
-static int membus_read_pll(struct socfpga_clk_platdata *plat, u32 pll,
+static int membus_read_pll(struct socfpga_clk_plat *plat, u32 pll,
u32 addr_offset, u32 *rdata, int timeout)
{
u32 addr;
return 0;
}
-static void membus_pll_configs(struct socfpga_clk_platdata *plat, u32 pll)
+static void membus_pll_configs(struct socfpga_clk_plat *plat, u32 pll)
{
int i;
u32 rdata;
static void clk_basic_init(struct udevice *dev,
const struct cm_config * const cfg)
{
- struct socfpga_clk_platdata *plat = dev_get_platdata(dev);
+ struct socfpga_clk_plat *plat = dev_get_plat(dev);
u32 vcocalib;
if (!cfg)
CM_REG_READL(plat, CLKMGR_CTRL) & ~CLKMGR_CTRL_BOOTMODE);
}
-static u64 clk_get_vco_clk_hz(struct socfpga_clk_platdata *plat,
+static u64 clk_get_vco_clk_hz(struct socfpga_clk_plat *plat,
u32 pllglob_reg, u32 pllm_reg)
{
u64 fref, arefdiv, mdiv, reg, vco;
return vco;
}
-static u64 clk_get_main_vco_clk_hz(struct socfpga_clk_platdata *plat)
+static u64 clk_get_main_vco_clk_hz(struct socfpga_clk_plat *plat)
{
return clk_get_vco_clk_hz(plat, CLKMGR_MAINPLL_PLLGLOB,
CLKMGR_MAINPLL_PLLM);
}
-static u64 clk_get_per_vco_clk_hz(struct socfpga_clk_platdata *plat)
+static u64 clk_get_per_vco_clk_hz(struct socfpga_clk_plat *plat)
{
return clk_get_vco_clk_hz(plat, CLKMGR_PERPLL_PLLGLOB,
CLKMGR_PERPLL_PLLM);
}
-static u32 clk_get_5_1_clk_src(struct socfpga_clk_platdata *plat, u64 reg)
+static u32 clk_get_5_1_clk_src(struct socfpga_clk_plat *plat, u64 reg)
{
u32 clksrc = CM_REG_READL(plat, reg);
return (clksrc & CLKMGR_CLKSRC_MASK) >> CLKMGR_CLKSRC_OFFSET;
}
-static u64 clk_get_clksrc_hz(struct socfpga_clk_platdata *plat, u32 clksrc_reg,
+static u64 clk_get_clksrc_hz(struct socfpga_clk_plat *plat, u32 clksrc_reg,
u32 main_reg, u32 per_reg)
{
u64 clock;
return clock;
}
-static u64 clk_get_mpu_clk_hz(struct socfpga_clk_platdata *plat)
+static u64 clk_get_mpu_clk_hz(struct socfpga_clk_plat *plat)
{
u64 clock = clk_get_clksrc_hz(plat, CLKMGR_MAINPLL_MPUCLK,
CLKMGR_MAINPLL_PLLC0,
return clock;
}
-static u32 clk_get_l3_main_clk_hz(struct socfpga_clk_platdata *plat)
+static u32 clk_get_l3_main_clk_hz(struct socfpga_clk_plat *plat)
{
return clk_get_clksrc_hz(plat, CLKMGR_MAINPLL_NOCCLK,
CLKMGR_MAINPLL_PLLC1,
CLKMGR_PERPLL_PLLC1);
}
-static u32 clk_get_l4_main_clk_hz(struct socfpga_clk_platdata *plat)
+static u32 clk_get_l4_main_clk_hz(struct socfpga_clk_plat *plat)
{
u64 clock = clk_get_l3_main_clk_hz(plat);
return clock;
}
-static u32 clk_get_sdmmc_clk_hz(struct socfpga_clk_platdata *plat)
+static u32 clk_get_sdmmc_clk_hz(struct socfpga_clk_plat *plat)
{
u64 clock = clk_get_clksrc_hz(plat, CLKMGR_ALTR_SDMMCCTR,
CLKMGR_MAINPLL_PLLC3,
return clock / 4;
}
-static u32 clk_get_l4_sp_clk_hz(struct socfpga_clk_platdata *plat)
+static u32 clk_get_l4_sp_clk_hz(struct socfpga_clk_plat *plat)
{
u64 clock = clk_get_l3_main_clk_hz(plat);
return clock;
}
-static u32 clk_get_l4_mp_clk_hz(struct socfpga_clk_platdata *plat)
+static u32 clk_get_l4_mp_clk_hz(struct socfpga_clk_plat *plat)
{
u64 clock = clk_get_l3_main_clk_hz(plat);
return clock;
}
-static u32 clk_get_l4_sys_free_clk_hz(struct socfpga_clk_platdata *plat)
+static u32 clk_get_l4_sys_free_clk_hz(struct socfpga_clk_plat *plat)
{
if (CM_REG_READL(plat, CLKMGR_STAT) & CLKMGR_STAT_BOOTMODE)
return clk_get_l3_main_clk_hz(plat) / 2;
return clk_get_l3_main_clk_hz(plat) / 4;
}
-static u32 clk_get_emac_clk_hz(struct socfpga_clk_platdata *plat, u32 emac_id)
+static u32 clk_get_emac_clk_hz(struct socfpga_clk_plat *plat, u32 emac_id)
{
bool emacsel_a;
u32 ctl;
static ulong socfpga_clk_get_rate(struct clk *clk)
{
- struct socfpga_clk_platdata *plat = dev_get_platdata(clk->dev);
+ struct socfpga_clk_plat *plat = dev_get_plat(clk->dev);
switch (clk->id) {
case AGILEX_MPU_CLK:
return 0;
}
-static int socfpga_clk_ofdata_to_platdata(struct udevice *dev)
+static int socfpga_clk_of_to_plat(struct udevice *dev)
{
- struct socfpga_clk_platdata *plat = dev_get_platdata(dev);
+ struct socfpga_clk_plat *plat = dev_get_plat(dev);
fdt_addr_t addr;
addr = dev_read_addr(dev);
.of_match = socfpga_clk_match,
.ops = &socfpga_clk_ops,
.probe = socfpga_clk_probe,
- .ofdata_to_platdata = socfpga_clk_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct socfpga_clk_platdata),
+ .of_to_plat = socfpga_clk_of_to_plat,
+ .plat_auto = sizeof(struct socfpga_clk_plat),
};
SOCFPGA_A10_CLK_UNKNOWN_CLK,
};
-struct socfpga_a10_clk_platdata {
+struct socfpga_a10_clk_plat {
enum socfpga_a10_clk_type type;
struct clk_bulk clks;
u32 regs;
static int socfpga_a10_clk_get_upstream(struct clk *clk, struct clk **upclk)
{
- struct socfpga_a10_clk_platdata *plat = dev_get_platdata(clk->dev);
+ struct socfpga_a10_clk_plat *plat = dev_get_plat(clk->dev);
u32 reg, maxval;
if (plat->clks.count == 0)
static int socfpga_a10_clk_endisable(struct clk *clk, bool enable)
{
- struct socfpga_a10_clk_platdata *plat = dev_get_platdata(clk->dev);
+ struct socfpga_a10_clk_plat *plat = dev_get_plat(clk->dev);
struct clk *upclk = NULL;
int ret;
static ulong socfpga_a10_clk_get_rate(struct clk *clk)
{
- struct socfpga_a10_clk_platdata *plat = dev_get_platdata(clk->dev);
+ struct socfpga_a10_clk_plat *plat = dev_get_plat(clk->dev);
struct clk *upclk = NULL;
ulong rate = 0, reg, numer, denom;
int ret;
*/
static void socfpga_a10_handoff_workaround(struct udevice *dev)
{
- struct socfpga_a10_clk_platdata *plat = dev_get_platdata(dev);
+ struct socfpga_a10_clk_plat *plat = dev_get_plat(dev);
const void *fdt = gd->fdt_blob;
struct clk_bulk *bulk = &plat->clks;
int i, ret, offset = dev_of_offset(dev);
static int socfpga_a10_clk_probe(struct udevice *dev)
{
- struct socfpga_a10_clk_platdata *plat = dev_get_platdata(dev);
- struct socfpga_a10_clk_platdata *pplat;
+ struct socfpga_a10_clk_plat *plat = dev_get_plat(dev);
+ struct socfpga_a10_clk_plat *pplat;
struct udevice *pdev;
const void *fdt = gd->fdt_blob;
int offset = dev_of_offset(dev);
if (!pdev)
return -ENODEV;
- pplat = dev_get_platdata(pdev);
+ pplat = dev_get_plat(pdev);
if (!pplat)
return -EINVAL;
return 0;
}
-static int socfpga_a10_ofdata_to_platdata(struct udevice *dev)
+static int socfpga_a10_of_to_plat(struct udevice *dev)
{
- struct socfpga_a10_clk_platdata *plat = dev_get_platdata(dev);
+ struct socfpga_a10_clk_plat *plat = dev_get_plat(dev);
unsigned int divreg[3], gatereg[2];
int ret;
.ops = &socfpga_a10_clk_ops,
.bind = socfpga_a10_clk_bind,
.probe = socfpga_a10_clk_probe,
- .ofdata_to_platdata = socfpga_a10_ofdata_to_platdata,
+ .of_to_plat = socfpga_a10_of_to_plat,
- .platdata_auto_alloc_size = sizeof(struct socfpga_a10_clk_platdata),
+ .plat_auto = sizeof(struct socfpga_a10_clk_plat),
};
.enable = ast2500_clk_enable,
};
-static int ast2500_clk_ofdata_to_platdata(struct udevice *dev)
+static int ast2500_clk_of_to_plat(struct udevice *dev)
{
struct ast2500_clk_priv *priv = dev_get_priv(dev);
.name = "aspeed_ast2500_scu",
.id = UCLASS_CLK,
.of_match = ast2500_clk_ids,
- .priv_auto_alloc_size = sizeof(struct ast2500_clk_priv),
+ .priv_auto = sizeof(struct ast2500_clk_priv),
.ops = &ast2500_clk_ops,
.bind = ast2500_clk_bind,
- .ofdata_to_platdata = ast2500_clk_ofdata_to_platdata,
+ .of_to_plat = ast2500_clk_of_to_plat,
};
DECLARE_GLOBAL_DATA_PTR;
-struct pmc_platdata {
+struct pmc_plat {
struct at91_pmc *reg_base;
struct regmap *regmap_sfr;
};
static int at91_pmc_core_probe(struct udevice *dev)
{
- struct pmc_platdata *plat = dev_get_platdata(dev);
+ struct pmc_plat *plat = dev_get_plat(dev);
dev = dev_get_parent(dev);
*/
int at91_clk_sub_device_bind(struct udevice *dev, const char *drv_name)
{
- const void *fdt = gd->fdt_blob;
- int offset = dev_of_offset(dev);
+ ofnode parent = dev_ofnode(dev);
+ ofnode node;
bool pre_reloc_only = !(gd->flags & GD_FLG_RELOC);
const char *name;
int ret;
- for (offset = fdt_first_subnode(fdt, offset);
- offset > 0;
- offset = fdt_next_subnode(fdt, offset)) {
- if (pre_reloc_only &&
- !ofnode_pre_reloc(offset_to_ofnode(offset)))
+ ofnode_for_each_subnode(node, parent) {
+ if (pre_reloc_only && !ofnode_pre_reloc(node))
continue;
/*
* If this node has "compatible" property, this is not
* a clock sub-node, but a normal device. skip.
*/
- fdt_get_property(fdt, offset, "compatible", &ret);
- if (ret >= 0)
+ if (ofnode_read_prop(node, "compatible", NULL))
continue;
if (ret != -FDT_ERR_NOTFOUND)
return ret;
- name = fdt_get_name(fdt, offset, NULL);
+ name = ofnode_get_name(node);
if (!name)
return -EINVAL;
- ret = device_bind_driver_to_node(dev, drv_name, name,
- offset_to_ofnode(offset), NULL);
+ ret = device_bind_driver_to_node(dev, drv_name, name, node,
+ NULL);
if (ret)
return ret;
}
int at91_clk_probe(struct udevice *dev)
{
struct udevice *dev_periph_container, *dev_pmc;
- struct pmc_platdata *plat = dev_get_platdata(dev);
+ struct pmc_plat *plat = dev_get_plat(dev);
dev_periph_container = dev_get_parent(dev);
dev_pmc = dev_get_parent(dev_periph_container);
/* Main osc clock specific code. */
static int main_osc_clk_enable(struct clk *clk)
{
- struct pmc_platdata *plat = dev_get_platdata(clk->dev);
+ struct pmc_plat *plat = dev_get_plat(clk->dev);
struct at91_pmc *pmc = plat->reg_base;
if (readl(&pmc->sr) & AT91_PMC_MOSCSELS)
.id = UCLASS_CLK,
.of_match = main_osc_clk_match,
.probe = main_osc_clk_probe,
- .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
+ .plat_auto = sizeof(struct pmc_plat),
.ops = &main_osc_clk_ops,
};
/* PLLA clock specific code. */
static int plla_clk_enable(struct clk *clk)
{
- struct pmc_platdata *plat = dev_get_platdata(clk->dev);
+ struct pmc_plat *plat = dev_get_plat(clk->dev);
struct at91_pmc *pmc = plat->reg_base;
if (readl(&pmc->sr) & AT91_PMC_LOCKA)
.id = UCLASS_CLK,
.of_match = plla_clk_match,
.probe = plla_clk_probe,
- .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
+ .plat_auto = sizeof(struct pmc_plat),
.ops = &plla_clk_ops,
};
static ulong at91_plladiv_clk_get_rate(struct clk *clk)
{
- struct pmc_platdata *plat = dev_get_platdata(clk->dev);
+ struct pmc_plat *plat = dev_get_plat(clk->dev);
struct at91_pmc *pmc = plat->reg_base;
struct clk source;
ulong clk_rate;
static ulong at91_plladiv_clk_set_rate(struct clk *clk, ulong rate)
{
- struct pmc_platdata *plat = dev_get_platdata(clk->dev);
+ struct pmc_plat *plat = dev_get_plat(clk->dev);
struct at91_pmc *pmc = plat->reg_base;
struct clk source;
ulong parent_rate;
.id = UCLASS_CLK,
.of_match = at91_plladiv_clk_match,
.probe = at91_plladiv_clk_probe,
- .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
+ .plat_auto = sizeof(struct pmc_plat),
.ops = &at91_plladiv_clk_ops,
};
static int system_clk_enable(struct clk *clk)
{
- struct pmc_platdata *plat = dev_get_platdata(clk->dev);
+ struct pmc_plat *plat = dev_get_plat(clk->dev);
struct at91_pmc *pmc = plat->reg_base;
u32 mask;
.name = "system-clk",
.id = UCLASS_CLK,
.probe = at91_clk_probe,
- .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
+ .plat_auto = sizeof(struct pmc_plat),
.ops = &system_clk_ops,
};
static int periph_clk_enable(struct clk *clk)
{
- struct pmc_platdata *plat = dev_get_platdata(clk->dev);
+ struct pmc_plat *plat = dev_get_plat(clk->dev);
struct at91_pmc *pmc = plat->reg_base;
enum periph_clk_type clk_type;
void *addr;
U_BOOT_DRIVER(clk_periph) = {
.name = "periph-clk",
.id = UCLASS_CLK,
- .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
+ .plat_auto = sizeof(struct pmc_plat),
.probe = at91_clk_probe,
.ops = &periph_clk_ops,
};
static int utmi_clk_enable(struct clk *clk)
{
- struct pmc_platdata *plat = dev_get_platdata(clk->dev);
+ struct pmc_plat *plat = dev_get_plat(clk->dev);
struct at91_pmc *pmc = plat->reg_base;
struct clk clk_dev;
ulong clk_rate;
.get_rate = utmi_clk_get_rate,
};
-static int utmi_clk_ofdata_to_platdata(struct udevice *dev)
+static int utmi_clk_of_to_plat(struct udevice *dev)
{
- struct pmc_platdata *plat = dev_get_platdata(dev);
+ struct pmc_plat *plat = dev_get_plat(dev);
struct udevice *syscon;
uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
.id = UCLASS_CLK,
.of_match = utmi_clk_match,
.probe = utmi_clk_probe,
- .ofdata_to_platdata = utmi_clk_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
+ .of_to_plat = utmi_clk_of_to_plat,
+ .plat_auto = sizeof(struct pmc_plat),
.ops = &utmi_clk_ops,
};
static ulong sama5d4_h32mx_clk_get_rate(struct clk *clk)
{
- struct pmc_platdata *plat = dev_get_platdata(clk->dev);
+ struct pmc_plat *plat = dev_get_plat(clk->dev);
struct at91_pmc *pmc = plat->reg_base;
ulong rate = gd->arch.mck_rate_hz;
.id = UCLASS_CLK,
.of_match = sama5d4_h32mx_clk_match,
.probe = sama5d4_h32mx_clk_probe,
- .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
+ .plat_auto = sizeof(struct pmc_plat),
.ops = &sama5d4_h32mx_clk_ops,
};
static ulong generic_clk_get_rate(struct clk *clk)
{
- struct pmc_platdata *plat = dev_get_platdata(clk->dev);
+ struct pmc_plat *plat = dev_get_plat(clk->dev);
struct at91_pmc *pmc = plat->reg_base;
struct clk parent;
ulong clk_rate;
static ulong generic_clk_set_rate(struct clk *clk, ulong rate)
{
- struct pmc_platdata *plat = dev_get_platdata(clk->dev);
+ struct pmc_plat *plat = dev_get_plat(clk->dev);
struct at91_pmc *pmc = plat->reg_base;
struct generic_clk_priv *priv = dev_get_priv(clk->dev);
struct clk parent, best_parent;
.set_rate = generic_clk_set_rate,
};
-static int generic_clk_ofdata_to_platdata(struct udevice *dev)
+static int generic_clk_of_to_plat(struct udevice *dev)
{
struct generic_clk_priv *priv = dev_get_priv(dev);
u32 cells[GENERATED_SOURCE_MAX];
.name = "generic-clk",
.id = UCLASS_CLK,
.probe = at91_clk_probe,
- .ofdata_to_platdata = generic_clk_ofdata_to_platdata,
- .priv_auto_alloc_size = sizeof(struct generic_clk_priv),
- .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
+ .of_to_plat = generic_clk_of_to_plat,
+ .priv_auto = sizeof(struct generic_clk_priv),
+ .plat_auto = sizeof(struct pmc_plat),
.ops = &generic_clk_ops,
};
static ulong at91_usb_clk_get_rate(struct clk *clk)
{
- struct pmc_platdata *plat = dev_get_platdata(clk->dev);
+ struct pmc_plat *plat = dev_get_plat(clk->dev);
struct at91_pmc *pmc = plat->reg_base;
struct clk source;
u32 tmp, usbdiv;
static ulong at91_usb_clk_set_rate(struct clk *clk, ulong rate)
{
- struct pmc_platdata *plat = dev_get_platdata(clk->dev);
+ struct pmc_plat *plat = dev_get_plat(clk->dev);
struct at91_pmc *pmc = plat->reg_base;
struct at91_usb_clk_priv *priv = dev_get_priv(clk->dev);
struct clk source, best_source;
.set_rate = at91_usb_clk_set_rate,
};
-static int at91_usb_clk_ofdata_to_platdata(struct udevice *dev)
+static int at91_usb_clk_of_to_plat(struct udevice *dev)
{
struct at91_usb_clk_priv *priv = dev_get_priv(dev);
u32 cells[AT91_USB_CLK_SOURCE_MAX];
.id = UCLASS_CLK,
.of_match = at91_usb_clk_match,
.probe = at91_usb_clk_probe,
- .ofdata_to_platdata = at91_usb_clk_ofdata_to_platdata,
- .priv_auto_alloc_size = sizeof(struct at91_usb_clk_priv),
- .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
+ .of_to_plat = at91_usb_clk_of_to_plat,
+ .priv_auto = sizeof(struct at91_usb_clk_priv),
+ .plat_auto = sizeof(struct pmc_plat),
.ops = &at91_usb_clk_ops,
};
.name = UBOOT_DM_CLK_AT91_SCKC,
.id = UCLASS_CLK,
.of_match = sam9x60_sckc_ids,
- .priv_auto_alloc_size = sizeof(struct sam9x60_sckc) * 2,
+ .priv_auto = sizeof(struct sam9x60_sckc) * 2,
.ops = &sam9x60_sckc_ops,
.probe = at91_sam9x60_sckc_probe,
.flags = DM_FLAG_PRE_RELOC,
.id = UCLASS_CLK,
.of_match = cdce9xx_clk_of_match,
.probe = cdce9xx_clk_probe,
- .priv_auto_alloc_size = sizeof(struct cdce9xx_clk_data),
+ .priv_auto = sizeof(struct cdce9xx_clk_data),
.ops = &cdce9xx_clk_ops,
};
.id = UCLASS_CLK,
.of_match = hsdk_cgu_clk_id,
.probe = hsdk_cgu_clk_probe,
- .priv_auto_alloc_size = sizeof(struct hsdk_cgu_clk),
+ .priv_auto = sizeof(struct hsdk_cgu_clk),
.ops = &hsdk_cgu_ops,
};
.id = UCLASS_CLK,
.of_match = ti_sci_clk_of_match,
.probe = ti_sci_clk_probe,
- .priv_auto_alloc_size = sizeof(struct ti_sci_clk_data),
+ .priv_auto = sizeof(struct ti_sci_clk_data),
.ops = &ti_sci_clk_ops,
};
return -ENOENT;
}
- ret = device_bind(parent, drv, name, NULL, -1, &clk->dev);
+ ret = device_bind(parent, drv, name, NULL, ofnode_null(), &clk->dev);
if (ret) {
printf("%s: CLK: %s driver bind error [%d]!\n", __func__, name,
ret);
.of_match = bcm6345_clk_ids,
.ops = &bcm6345_clk_ops,
.probe = bcm63xx_clk_probe,
- .priv_auto_alloc_size = sizeof(struct bcm6345_clk_priv),
+ .priv_auto = sizeof(struct bcm6345_clk_priv),
};
static ulong clk_boston_get_rate(struct clk *clk)
{
- struct clk_boston *state = dev_get_platdata(clk->dev);
+ struct clk_boston *state = dev_get_plat(clk->dev);
uint32_t in_rate, mul, div;
uint mmcmdiv;
int err;
.get_rate = clk_boston_get_rate,
};
-static int clk_boston_ofdata_to_platdata(struct udevice *dev)
+static int clk_boston_of_to_plat(struct udevice *dev)
{
- struct clk_boston *state = dev_get_platdata(dev);
+ struct clk_boston *state = dev_get_plat(dev);
struct udevice *syscon;
int err;
.name = "boston_clock",
.id = UCLASS_CLK,
.of_match = clk_boston_match,
- .ofdata_to_platdata = clk_boston_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct clk_boston),
+ .of_to_plat = clk_boston_of_to_plat,
+ .plat_auto = sizeof(struct clk_boston),
.ops = &clk_boston_ops,
};
};
#define to_clk_fixed_factor(dev) \
- ((struct clk_fixed_factor *)dev_get_platdata(dev))
+ ((struct clk_fixed_factor *)dev_get_plat(dev))
static ulong clk_fixed_factor_get_rate(struct clk *clk)
{
.get_rate = clk_fixed_factor_get_rate,
};
-static int clk_fixed_factor_ofdata_to_platdata(struct udevice *dev)
+static int clk_fixed_factor_of_to_plat(struct udevice *dev)
{
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
int err;
.name = "fixed_factor_clock",
.id = UCLASS_CLK,
.of_match = clk_fixed_factor_match,
- .ofdata_to_platdata = clk_fixed_factor_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct clk_fixed_factor),
+ .of_to_plat = clk_fixed_factor_of_to_plat,
+ .plat_auto = sizeof(struct clk_fixed_factor),
.ops = &clk_fixed_factor_ops,
};
.enable = dummy_enable,
};
-static int clk_fixed_rate_ofdata_to_platdata(struct udevice *dev)
+static int clk_fixed_rate_of_to_plat(struct udevice *dev)
{
struct clk *clk = &to_clk_fixed_rate(dev)->clk;
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
.name = "fixed_clock",
.id = UCLASS_CLK,
.of_match = clk_fixed_rate_match,
- .ofdata_to_platdata = clk_fixed_rate_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct clk_fixed_rate),
+ .of_to_plat = clk_fixed_rate_of_to_plat,
+ .plat_auto = sizeof(struct clk_fixed_rate),
.ops = &clk_fixed_rate_ops,
.flags = DM_FLAG_PRE_RELOC,
};
.of_match = octeon_clk_ids,
.ops = &octeon_clk_ops,
.probe = octeon_clk_probe,
- .priv_auto_alloc_size = sizeof(struct octeon_clk_priv),
+ .priv_auto = sizeof(struct octeon_clk_priv),
};
.of_match = pic32_clk_ids,
.ops = &pic32_pic32_clk_ops,
.probe = pic32_clk_probe,
- .priv_auto_alloc_size = sizeof(struct pic32_clk_priv),
+ .priv_auto = sizeof(struct pic32_clk_priv),
};
.of_match = sandbox_clk_ids,
.ops = &sandbox_clk_ops,
.probe = sandbox_clk_probe,
- .priv_auto_alloc_size = sizeof(struct sandbox_clk_priv),
+ .priv_auto = sizeof(struct sandbox_clk_priv),
};
ulong sandbox_clk_query_rate(struct udevice *dev, int id)
.id = UCLASS_MISC,
.of_match = sandbox_clk_test_ids,
.probe = sandbox_clk_test_probe,
- .priv_auto_alloc_size = sizeof(struct sandbox_clk_test),
+ .priv_auto = sizeof(struct sandbox_clk_test),
};
.id = UCLASS_CLK,
.ops = &stm32_clk_ops,
.probe = stm32_clk_probe,
- .priv_auto_alloc_size = sizeof(struct stm32_clk),
+ .priv_auto = sizeof(struct stm32_clk),
.flags = DM_FLAG_PRE_RELOC,
};
.id = UCLASS_CLK,
.ops = &stm32_clk_ops,
.probe = stm32_clk_probe,
- .priv_auto_alloc_size = sizeof(struct stm32_clk),
+ .priv_auto = sizeof(struct stm32_clk),
.flags = DM_FLAG_PRE_RELOC,
};
.name = "stm32mp1_clk",
.id = UCLASS_CLK,
.ops = &stm32mp1_clk_ops,
- .priv_auto_alloc_size = sizeof(struct stm32mp1_clk_priv),
+ .priv_auto = sizeof(struct stm32mp1_clk_priv),
.probe = stm32mp1_clk_probe,
};
.of_match = versal_clk_ids,
.probe = versal_clk_probe,
.ops = &versal_clk_ops,
- .priv_auto_alloc_size = sizeof(struct versal_clk_priv),
+ .priv_auto = sizeof(struct versal_clk_priv),
};
.id = UCLASS_CLK,
.of_match = vexpress_osc_clk_ids,
.ops = &vexpress_osc_clk_ops,
- .priv_auto_alloc_size = sizeof(struct vexpress_osc_clk_priv),
+ .priv_auto = sizeof(struct vexpress_osc_clk_priv),
.probe = vexpress_osc_clk_probe,
};
.id = UCLASS_CLK,
.of_match = zynq_clk_ids,
.ops = &zynq_clk_ops,
- .priv_auto_alloc_size = sizeof(struct zynq_clk_priv),
+ .priv_auto = sizeof(struct zynq_clk_priv),
.probe = zynq_clk_probe,
};
.of_match = zynqmp_clk_ids,
.probe = zynqmp_clk_probe,
.ops = &zynqmp_clk_ops,
- .priv_auto_alloc_size = sizeof(struct zynqmp_clk_priv),
+ .priv_auto = sizeof(struct zynqmp_clk_priv),
};
.id = UCLASS_CLK,
.of_match = exynos7420_clk_topc_compat,
.probe = exynos7420_clk_topc_probe,
- .priv_auto_alloc_size = sizeof(struct exynos7420_clk_topc_priv),
+ .priv_auto = sizeof(struct exynos7420_clk_topc_priv),
.ops = &exynos7420_clk_topc_ops,
};
.id = UCLASS_CLK,
.of_match = exynos7420_clk_top0_compat,
.probe = exynos7420_clk_top0_probe,
- .priv_auto_alloc_size = sizeof(struct exynos7420_clk_top0_priv),
+ .priv_auto = sizeof(struct exynos7420_clk_top0_priv),
.ops = &exynos7420_clk_top0_ops,
};
.ops = &ics8n3qv01_ops,
.of_match = ics8n3qv01_ids,
.probe = ics8n3qv01_probe,
- .priv_auto_alloc_size = sizeof(struct ics8n3qv01_priv),
+ .priv_auto = sizeof(struct ics8n3qv01_priv),
};
.id = UCLASS_CLK,
.of_match = mt7622_apmixed_compat,
.probe = mt7622_apmixedsys_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
+ .priv_auto = sizeof(struct mtk_clk_priv),
.ops = &mtk_clk_apmixedsys_ops,
.flags = DM_FLAG_PRE_RELOC,
};
.id = UCLASS_CLK,
.of_match = mt7622_topckgen_compat,
.probe = mt7622_topckgen_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
+ .priv_auto = sizeof(struct mtk_clk_priv),
.ops = &mtk_clk_topckgen_ops,
.flags = DM_FLAG_PRE_RELOC,
};
.id = UCLASS_CLK,
.of_match = mt7622_infracfg_compat,
.probe = mt7622_infracfg_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .priv_auto = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
.flags = DM_FLAG_PRE_RELOC,
};
.id = UCLASS_CLK,
.of_match = mt7622_pericfg_compat,
.probe = mt7622_pericfg_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .priv_auto = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
.flags = DM_FLAG_PRE_RELOC,
};
.of_match = mt7622_pciesys_compat,
.probe = mt7622_pciesys_probe,
.bind = mt7622_pciesys_bind,
- .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .priv_auto = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
};
.of_match = mt7622_ethsys_compat,
.probe = mt7622_ethsys_probe,
.bind = mt7622_ethsys_bind,
- .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .priv_auto = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
};
.id = UCLASS_CLK,
.of_match = mt7622_sgmiisys_compat,
.probe = mt7622_sgmiisys_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .priv_auto = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
};
.id = UCLASS_CLK,
.of_match = mt7622_ssusbsys_compat,
.probe = mt7622_ssusbsys_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .priv_auto = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
};
.id = UCLASS_CLK,
.of_match = mt7623_apmixed_compat,
.probe = mt7623_apmixedsys_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
+ .priv_auto = sizeof(struct mtk_clk_priv),
.ops = &mtk_clk_apmixedsys_ops,
.flags = DM_FLAG_PRE_RELOC,
};
.id = UCLASS_CLK,
.of_match = mt7623_topckgen_compat,
.probe = mt7623_topckgen_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
+ .priv_auto = sizeof(struct mtk_clk_priv),
.ops = &mtk_clk_topckgen_ops,
.flags = DM_FLAG_PRE_RELOC,
};
.id = UCLASS_CLK,
.of_match = mt7623_infracfg_compat,
.probe = mt7623_infracfg_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .priv_auto = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
.flags = DM_FLAG_PRE_RELOC,
};
.id = UCLASS_CLK,
.of_match = mt7623_pericfg_compat,
.probe = mt7623_pericfg_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .priv_auto = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
.flags = DM_FLAG_PRE_RELOC,
};
.of_match = mt7623_hifsys_compat,
.probe = mt7623_hifsys_probe,
.bind = mt7623_ethsys_hifsys_bind,
- .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .priv_auto = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
};
.of_match = mt7623_ethsys_compat,
.probe = mt7623_ethsys_probe,
.bind = mt7623_ethsys_hifsys_bind,
- .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .priv_auto = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
};
.id = UCLASS_CLK,
.of_match = mt7629_apmixed_compat,
.probe = mt7629_apmixedsys_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
+ .priv_auto = sizeof(struct mtk_clk_priv),
.ops = &mtk_clk_apmixedsys_ops,
.flags = DM_FLAG_PRE_RELOC,
};
.id = UCLASS_CLK,
.of_match = mt7629_topckgen_compat,
.probe = mt7629_topckgen_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
+ .priv_auto = sizeof(struct mtk_clk_priv),
.ops = &mtk_clk_topckgen_ops,
.flags = DM_FLAG_PRE_RELOC,
};
.id = UCLASS_CLK,
.of_match = mt7629_infracfg_compat,
.probe = mt7629_infracfg_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .priv_auto = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
.flags = DM_FLAG_PRE_RELOC,
};
.id = UCLASS_CLK,
.of_match = mt7629_pericfg_compat,
.probe = mt7629_pericfg_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .priv_auto = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
.flags = DM_FLAG_PRE_RELOC,
};
.of_match = mt7629_ethsys_compat,
.probe = mt7629_ethsys_probe,
.bind = mt7629_ethsys_bind,
- .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .priv_auto = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
};
.id = UCLASS_CLK,
.of_match = mt7629_sgmiisys_compat,
.probe = mt7629_sgmiisys_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .priv_auto = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
};
.id = UCLASS_CLK,
.of_match = mt7629_ssusbsys_compat,
.probe = mt7629_ssusbsys_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .priv_auto = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
};
.id = UCLASS_CLK,
.of_match = mt8512_apmixed_compat,
.probe = mt8512_apmixedsys_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
+ .priv_auto = sizeof(struct mtk_clk_priv),
.ops = &mtk_clk_apmixedsys_ops,
.flags = DM_FLAG_PRE_RELOC,
};
.id = UCLASS_CLK,
.of_match = mt8512_topckgen_compat,
.probe = mt8512_topckgen_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
+ .priv_auto = sizeof(struct mtk_clk_priv),
.ops = &mtk_clk_topckgen_ops,
.flags = DM_FLAG_PRE_RELOC,
};
.id = UCLASS_CLK,
.of_match = mt8512_topckgen_cg_compat,
.probe = mt8512_topckgen_cg_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .priv_auto = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
.flags = DM_FLAG_PRE_RELOC,
};
.id = UCLASS_CLK,
.of_match = mt8512_infracfg_compat,
.probe = mt8512_infracfg_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .priv_auto = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
.flags = DM_FLAG_PRE_RELOC,
};
.id = UCLASS_CLK,
.of_match = mt8516_apmixed_compat,
.probe = mt8516_apmixedsys_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
+ .priv_auto = sizeof(struct mtk_clk_priv),
.ops = &mtk_clk_apmixedsys_ops,
.flags = DM_FLAG_PRE_RELOC,
};
.id = UCLASS_CLK,
.of_match = mt8516_topckgen_compat,
.probe = mt8516_topckgen_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
+ .priv_auto = sizeof(struct mtk_clk_priv),
.ops = &mtk_clk_topckgen_ops,
.flags = DM_FLAG_PRE_RELOC,
};
.id = UCLASS_CLK,
.of_match = mt8516_topckgen_cg_compat,
.probe = mt8516_topckgen_cg_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .priv_auto = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
.flags = DM_FLAG_PRE_RELOC,
};
.id = UCLASS_CLK,
.of_match = mt8518_apmixed_compat,
.probe = mt8518_apmixedsys_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
+ .priv_auto = sizeof(struct mtk_clk_priv),
.ops = &mtk_clk_apmixedsys_ops,
.flags = DM_FLAG_PRE_RELOC,
};
.id = UCLASS_CLK,
.of_match = mt8518_topckgen_compat,
.probe = mt8518_topckgen_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
+ .priv_auto = sizeof(struct mtk_clk_priv),
.ops = &mtk_clk_topckgen_ops,
.flags = DM_FLAG_PRE_RELOC,
};
.id = UCLASS_CLK,
.of_match = mt8518_topckgen_cg_compat,
.probe = mt8518_topckgen_cg_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .priv_auto = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
.flags = DM_FLAG_PRE_RELOC,
};
.name = "meson_clk_axg",
.id = UCLASS_CLK,
.of_match = meson_clk_ids,
- .priv_auto_alloc_size = sizeof(struct meson_clk),
+ .priv_auto = sizeof(struct meson_clk),
.ops = &meson_clk_ops,
.probe = meson_clk_probe,
};
.name = "meson_clk_g12a",
.id = UCLASS_CLK,
.of_match = meson_clk_ids,
- .priv_auto_alloc_size = sizeof(struct meson_clk),
+ .priv_auto = sizeof(struct meson_clk),
.ops = &meson_clk_ops,
.probe = meson_clk_probe,
};
.name = "meson_clk",
.id = UCLASS_CLK,
.of_match = meson_clk_ids,
- .priv_auto_alloc_size = sizeof(struct meson_clk),
+ .priv_auto = sizeof(struct meson_clk),
.ops = &meson_clk_ops,
.probe = meson_clk_probe,
};
.of_match = mpc83xx_clk_match,
.ops = &mpc83xx_clk_ops,
.probe = mpc83xx_clk_probe,
- .priv_auto_alloc_size = sizeof(struct mpc83xx_clk_priv),
+ .priv_auto = sizeof(struct mpc83xx_clk_priv),
.bind = mpc83xx_clk_bind,
};
.id = UCLASS_CLK,
.of_match = mt7628_clk_ids,
.probe = mt7628_clk_probe,
- .priv_auto_alloc_size = sizeof(struct mt7628_clk_priv),
+ .priv_auto = sizeof(struct mt7628_clk_priv),
.ops = &mt7628_clk_ops,
};
.id = UCLASS_CLK,
.of_match = armada_37xx_periph_clk_ids,
.ops = &armada_37xx_periph_clk_ops,
- .priv_auto_alloc_size = sizeof(struct a37xx_periphclk),
+ .priv_auto = sizeof(struct a37xx_periphclk),
.probe = armada_37xx_periph_clk_probe,
};
.id = UCLASS_CLK,
.of_match = armada_37xx_tbg_clk_ids,
.ops = &armada_37xx_tbg_clk_ops,
- .priv_auto_alloc_size = sizeof(struct a37xx_tbgclk),
+ .priv_auto = sizeof(struct a37xx_tbgclk),
.probe = armada_37xx_tbg_clk_probe,
};
.id = UCLASS_CLK,
.of_match = owl_clk_ids,
.ops = &owl_clk_ops,
- .priv_auto_alloc_size = sizeof(struct owl_clk_priv),
+ .priv_auto = sizeof(struct owl_clk_priv),
.probe = owl_clk_probe,
};
.name = "clk_r8a774a1",
.id = UCLASS_CLK,
.of_match = r8a774a1_clk_ids,
- .priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
+ .priv_auto = sizeof(struct gen3_clk_priv),
.ops = &gen3_clk_ops,
.probe = gen3_clk_probe,
.remove = gen3_clk_remove,
.name = "clk_r8a774b1",
.id = UCLASS_CLK,
.of_match = r8a774b1_clk_ids,
- .priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
+ .priv_auto = sizeof(struct gen3_clk_priv),
.ops = &gen3_clk_ops,
.probe = gen3_clk_probe,
.remove = gen3_clk_remove,
.name = "clk_r8a774c0",
.id = UCLASS_CLK,
.of_match = r8a774c0_clk_ids,
- .priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
+ .priv_auto = sizeof(struct gen3_clk_priv),
.ops = &gen3_clk_ops,
.probe = gen3_clk_probe,
.remove = gen3_clk_remove,
.name = "clk_r8a774e1",
.id = UCLASS_CLK,
.of_match = r8a774e1_clk_ids,
- .priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
+ .priv_auto = sizeof(struct gen3_clk_priv),
.ops = &gen3_clk_ops,
.probe = gen3_clk_probe,
.remove = gen3_clk_remove,
.name = "clk_r8a7790",
.id = UCLASS_CLK,
.of_match = r8a7790_clk_ids,
- .priv_auto_alloc_size = sizeof(struct gen2_clk_priv),
+ .priv_auto = sizeof(struct gen2_clk_priv),
.ops = &gen2_clk_ops,
.probe = gen2_clk_probe,
.remove = gen2_clk_remove,
.name = "clk_r8a7791",
.id = UCLASS_CLK,
.of_match = r8a7791_clk_ids,
- .priv_auto_alloc_size = sizeof(struct gen2_clk_priv),
+ .priv_auto = sizeof(struct gen2_clk_priv),
.ops = &gen2_clk_ops,
.probe = gen2_clk_probe,
.remove = gen2_clk_remove,
.name = "clk_r8a7792",
.id = UCLASS_CLK,
.of_match = r8a7792_clk_ids,
- .priv_auto_alloc_size = sizeof(struct gen2_clk_priv),
+ .priv_auto = sizeof(struct gen2_clk_priv),
.ops = &gen2_clk_ops,
.probe = gen2_clk_probe,
.remove = gen2_clk_remove,
.name = "clk_r8a7794",
.id = UCLASS_CLK,
.of_match = r8a7794_clk_ids,
- .priv_auto_alloc_size = sizeof(struct gen2_clk_priv),
+ .priv_auto = sizeof(struct gen2_clk_priv),
.ops = &gen2_clk_ops,
.probe = gen2_clk_probe,
.remove = gen2_clk_remove,
.name = "clk_r8a7795",
.id = UCLASS_CLK,
.of_match = r8a7795_clk_ids,
- .priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
+ .priv_auto = sizeof(struct gen3_clk_priv),
.ops = &gen3_clk_ops,
.probe = gen3_clk_probe,
.remove = gen3_clk_remove,
.name = "clk_r8a7796",
.id = UCLASS_CLK,
.of_match = r8a7796_clk_ids,
- .priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
+ .priv_auto = sizeof(struct gen3_clk_priv),
.ops = &gen3_clk_ops,
.probe = gen3_clk_probe,
.remove = gen3_clk_remove,
.name = "clk_r8a77965",
.id = UCLASS_CLK,
.of_match = r8a77965_clk_ids,
- .priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
+ .priv_auto = sizeof(struct gen3_clk_priv),
.ops = &gen3_clk_ops,
.probe = gen3_clk_probe,
.remove = gen3_clk_remove,
.name = "clk_r8a77970",
.id = UCLASS_CLK,
.of_match = r8a77970_clk_ids,
- .priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
+ .priv_auto = sizeof(struct gen3_clk_priv),
.ops = &gen3_clk_ops,
.probe = gen3_clk_probe,
.remove = gen3_clk_remove,
.name = "clk_r8a77980",
.id = UCLASS_CLK,
.of_match = r8a77980_clk_ids,
- .priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
+ .priv_auto = sizeof(struct gen3_clk_priv),
.ops = &gen3_clk_ops,
.probe = gen3_clk_probe,
.remove = gen3_clk_remove,
.name = "clk_r8a77990",
.id = UCLASS_CLK,
.of_match = r8a77990_clk_ids,
- .priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
+ .priv_auto = sizeof(struct gen3_clk_priv),
.ops = &gen3_clk_ops,
.probe = gen3_clk_probe,
.remove = gen3_clk_remove,
.name = "clk_r8a77995",
.id = UCLASS_CLK,
.of_match = r8a77995_clk_ids,
- .priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
+ .priv_auto = sizeof(struct gen3_clk_priv),
.ops = &gen3_clk_ops,
.probe = gen3_clk_probe,
.remove = gen3_clk_remove,
return 0;
}
-static int px30_clk_ofdata_to_platdata(struct udevice *dev)
+static int px30_clk_of_to_plat(struct udevice *dev)
{
struct px30_clk_priv *priv = dev_get_priv(dev);
.name = "rockchip_px30_cru",
.id = UCLASS_CLK,
.of_match = px30_clk_ids,
- .priv_auto_alloc_size = sizeof(struct px30_clk_priv),
- .ofdata_to_platdata = px30_clk_ofdata_to_platdata,
+ .priv_auto = sizeof(struct px30_clk_priv),
+ .of_to_plat = px30_clk_of_to_plat,
.ops = &px30_clk_ops,
.bind = px30_clk_bind,
.probe = px30_clk_probe,
return 0;
}
-static int px30_pmuclk_ofdata_to_platdata(struct udevice *dev)
+static int px30_pmuclk_of_to_plat(struct udevice *dev)
{
struct px30_pmuclk_priv *priv = dev_get_priv(dev);
.name = "rockchip_px30_pmucru",
.id = UCLASS_CLK,
.of_match = px30_pmuclk_ids,
- .priv_auto_alloc_size = sizeof(struct px30_pmuclk_priv),
- .ofdata_to_platdata = px30_pmuclk_ofdata_to_platdata,
+ .priv_auto = sizeof(struct px30_pmuclk_priv),
+ .of_to_plat = px30_pmuclk_of_to_plat,
.ops = &px30_pmuclk_ops,
.probe = px30_pmuclk_probe,
};
.set_rate = rk3036_clk_set_rate,
};
-static int rk3036_clk_ofdata_to_platdata(struct udevice *dev)
+static int rk3036_clk_of_to_plat(struct udevice *dev)
{
struct rk3036_clk_priv *priv = dev_get_priv(dev);
.name = "clk_rk3036",
.id = UCLASS_CLK,
.of_match = rk3036_clk_ids,
- .priv_auto_alloc_size = sizeof(struct rk3036_clk_priv),
- .ofdata_to_platdata = rk3036_clk_ofdata_to_platdata,
+ .priv_auto = sizeof(struct rk3036_clk_priv),
+ .of_to_plat = rk3036_clk_of_to_plat,
.ops = &rk3036_clk_ops,
.bind = rk3036_clk_bind,
.probe = rk3036_clk_probe,
.set_rate = rk3128_clk_set_rate,
};
-static int rk3128_clk_ofdata_to_platdata(struct udevice *dev)
+static int rk3128_clk_of_to_plat(struct udevice *dev)
{
struct rk3128_clk_priv *priv = dev_get_priv(dev);
.name = "clk_rk3128",
.id = UCLASS_CLK,
.of_match = rk3128_clk_ids,
- .priv_auto_alloc_size = sizeof(struct rk3128_clk_priv),
- .ofdata_to_platdata = rk3128_clk_ofdata_to_platdata,
+ .priv_auto = sizeof(struct rk3128_clk_priv),
+ .of_to_plat = rk3128_clk_of_to_plat,
.ops = &rk3128_clk_ops,
.bind = rk3128_clk_bind,
.probe = rk3128_clk_probe,
.set_rate = rk3188_clk_set_rate,
};
-static int rk3188_clk_ofdata_to_platdata(struct udevice *dev)
+static int rk3188_clk_of_to_plat(struct udevice *dev)
{
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct rk3188_clk_priv *priv = dev_get_priv(dev);
#ifdef CONFIG_SPL_BUILD
#if CONFIG_IS_ENABLED(OF_PLATDATA)
- struct rk3188_clk_plat *plat = dev_get_platdata(dev);
+ struct rk3188_clk_plat *plat = dev_get_plat(dev);
priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
#endif
.name = "rockchip_rk3188_cru",
.id = UCLASS_CLK,
.of_match = rk3188_clk_ids,
- .priv_auto_alloc_size = sizeof(struct rk3188_clk_priv),
- .platdata_auto_alloc_size = sizeof(struct rk3188_clk_plat),
+ .priv_auto = sizeof(struct rk3188_clk_priv),
+ .plat_auto = sizeof(struct rk3188_clk_plat),
.ops = &rk3188_clk_ops,
.bind = rk3188_clk_bind,
- .ofdata_to_platdata = rk3188_clk_ofdata_to_platdata,
+ .of_to_plat = rk3188_clk_of_to_plat,
.probe = rk3188_clk_probe,
};
.set_parent = rk322x_clk_set_parent,
};
-static int rk322x_clk_ofdata_to_platdata(struct udevice *dev)
+static int rk322x_clk_of_to_plat(struct udevice *dev)
{
struct rk322x_clk_priv *priv = dev_get_priv(dev);
.name = "clk_rk322x",
.id = UCLASS_CLK,
.of_match = rk322x_clk_ids,
- .priv_auto_alloc_size = sizeof(struct rk322x_clk_priv),
- .ofdata_to_platdata = rk322x_clk_ofdata_to_platdata,
+ .priv_auto = sizeof(struct rk322x_clk_priv),
+ .of_to_plat = rk322x_clk_of_to_plat,
.ops = &rk322x_clk_ops,
.bind = rk322x_clk_bind,
.probe = rk322x_clk_probe,
#endif
};
-static int rk3288_clk_ofdata_to_platdata(struct udevice *dev)
+static int rk3288_clk_of_to_plat(struct udevice *dev)
{
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct rk3288_clk_priv *priv = dev_get_priv(dev);
return PTR_ERR(priv->grf);
#ifdef CONFIG_SPL_BUILD
#if CONFIG_IS_ENABLED(OF_PLATDATA)
- struct rk3288_clk_plat *plat = dev_get_platdata(dev);
+ struct rk3288_clk_plat *plat = dev_get_plat(dev);
priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
#endif
.name = "rockchip_rk3288_cru",
.id = UCLASS_CLK,
.of_match = rk3288_clk_ids,
- .priv_auto_alloc_size = sizeof(struct rk3288_clk_priv),
- .platdata_auto_alloc_size = sizeof(struct rk3288_clk_plat),
+ .priv_auto = sizeof(struct rk3288_clk_priv),
+ .plat_auto = sizeof(struct rk3288_clk_plat),
.ops = &rk3288_clk_ops,
.bind = rk3288_clk_bind,
- .ofdata_to_platdata = rk3288_clk_ofdata_to_platdata,
+ .of_to_plat = rk3288_clk_of_to_plat,
.probe = rk3288_clk_probe,
};
return ret;
}
-static int rk3308_clk_ofdata_to_platdata(struct udevice *dev)
+static int rk3308_clk_of_to_plat(struct udevice *dev)
{
struct rk3308_clk_priv *priv = dev_get_priv(dev);
.name = "rockchip_rk3308_cru",
.id = UCLASS_CLK,
.of_match = rk3308_clk_ids,
- .priv_auto_alloc_size = sizeof(struct rk3308_clk_priv),
- .ofdata_to_platdata = rk3308_clk_ofdata_to_platdata,
+ .priv_auto = sizeof(struct rk3308_clk_priv),
+ .of_to_plat = rk3308_clk_of_to_plat,
.ops = &rk3308_clk_ops,
.bind = rk3308_clk_bind,
.probe = rk3308_clk_probe,
return 0;
}
-static int rk3328_clk_ofdata_to_platdata(struct udevice *dev)
+static int rk3328_clk_of_to_plat(struct udevice *dev)
{
struct rk3328_clk_priv *priv = dev_get_priv(dev);
.name = "rockchip_rk3328_cru",
.id = UCLASS_CLK,
.of_match = rk3328_clk_ids,
- .priv_auto_alloc_size = sizeof(struct rk3328_clk_priv),
- .ofdata_to_platdata = rk3328_clk_ofdata_to_platdata,
+ .priv_auto = sizeof(struct rk3328_clk_priv),
+ .of_to_plat = rk3328_clk_of_to_plat,
.ops = &rk3328_clk_ops,
.bind = rk3328_clk_bind,
.probe = rk3328_clk_probe,
{
struct rk3368_clk_priv __maybe_unused *priv = dev_get_priv(dev);
#if CONFIG_IS_ENABLED(OF_PLATDATA)
- struct rk3368_clk_plat *plat = dev_get_platdata(dev);
+ struct rk3368_clk_plat *plat = dev_get_plat(dev);
priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
#endif
return 0;
}
-static int rk3368_clk_ofdata_to_platdata(struct udevice *dev)
+static int rk3368_clk_of_to_plat(struct udevice *dev)
{
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct rk3368_clk_priv *priv = dev_get_priv(dev);
.name = "rockchip_rk3368_cru",
.id = UCLASS_CLK,
.of_match = rk3368_clk_ids,
- .priv_auto_alloc_size = sizeof(struct rk3368_clk_priv),
+ .priv_auto = sizeof(struct rk3368_clk_priv),
#if CONFIG_IS_ENABLED(OF_PLATDATA)
- .platdata_auto_alloc_size = sizeof(struct rk3368_clk_plat),
+ .plat_auto = sizeof(struct rk3368_clk_plat),
#endif
- .ofdata_to_platdata = rk3368_clk_ofdata_to_platdata,
+ .of_to_plat = rk3368_clk_of_to_plat,
.ops = &rk3368_clk_ops,
.bind = rk3368_clk_bind,
.probe = rk3368_clk_probe,
bool init_clocks = false;
#if CONFIG_IS_ENABLED(OF_PLATDATA)
- struct rk3399_clk_plat *plat = dev_get_platdata(dev);
+ struct rk3399_clk_plat *plat = dev_get_plat(dev);
priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
#endif
return 0;
}
-static int rk3399_clk_ofdata_to_platdata(struct udevice *dev)
+static int rk3399_clk_of_to_plat(struct udevice *dev)
{
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct rk3399_clk_priv *priv = dev_get_priv(dev);
.name = "rockchip_rk3399_cru",
.id = UCLASS_CLK,
.of_match = rk3399_clk_ids,
- .priv_auto_alloc_size = sizeof(struct rk3399_clk_priv),
- .ofdata_to_platdata = rk3399_clk_ofdata_to_platdata,
+ .priv_auto = sizeof(struct rk3399_clk_priv),
+ .of_to_plat = rk3399_clk_of_to_plat,
.ops = &rk3399_clk_ops,
.bind = rk3399_clk_bind,
.probe = rk3399_clk_probe,
#if CONFIG_IS_ENABLED(OF_PLATDATA)
- .platdata_auto_alloc_size = sizeof(struct rk3399_clk_plat),
+ .plat_auto = sizeof(struct rk3399_clk_plat),
#endif
};
#endif
#if CONFIG_IS_ENABLED(OF_PLATDATA)
- struct rk3399_pmuclk_plat *plat = dev_get_platdata(dev);
+ struct rk3399_pmuclk_plat *plat = dev_get_plat(dev);
priv->pmucru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
#endif
return 0;
}
-static int rk3399_pmuclk_ofdata_to_platdata(struct udevice *dev)
+static int rk3399_pmuclk_of_to_plat(struct udevice *dev)
{
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct rk3399_pmuclk_priv *priv = dev_get_priv(dev);
.name = "rockchip_rk3399_pmucru",
.id = UCLASS_CLK,
.of_match = rk3399_pmuclk_ids,
- .priv_auto_alloc_size = sizeof(struct rk3399_pmuclk_priv),
- .ofdata_to_platdata = rk3399_pmuclk_ofdata_to_platdata,
+ .priv_auto = sizeof(struct rk3399_pmuclk_priv),
+ .of_to_plat = rk3399_pmuclk_of_to_plat,
.ops = &rk3399_pmuclk_ops,
.probe = rk3399_pmuclk_probe,
.bind = rk3399_pmuclk_bind,
#if CONFIG_IS_ENABLED(OF_PLATDATA)
- .platdata_auto_alloc_size = sizeof(struct rk3399_pmuclk_plat),
+ .plat_auto = sizeof(struct rk3399_pmuclk_plat),
#endif
};
aclk_bus, aclk_peri, hclk_peri, pclk_peri);
}
-static int rv1108_clk_ofdata_to_platdata(struct udevice *dev)
+static int rv1108_clk_of_to_plat(struct udevice *dev)
{
struct rv1108_clk_priv *priv = dev_get_priv(dev);
.name = "clk_rv1108",
.id = UCLASS_CLK,
.of_match = rv1108_clk_ids,
- .priv_auto_alloc_size = sizeof(struct rv1108_clk_priv),
+ .priv_auto = sizeof(struct rv1108_clk_priv),
.ops = &rv1108_clk_ops,
.bind = rv1108_clk_bind,
- .ofdata_to_platdata = rv1108_clk_ofdata_to_platdata,
+ .of_to_plat = rv1108_clk_of_to_plat,
.probe = rv1108_clk_probe,
};
.of_match = sifive_fu540_prci_ids,
.probe = sifive_fu540_prci_probe,
.ops = &sifive_fu540_prci_ops,
- .priv_auto_alloc_size = sizeof(struct __prci_data),
+ .priv_auto = sizeof(struct __prci_data),
.bind = sifive_fu540_clk_bind,
};
.name = "sun4i_a10_ccu",
.id = UCLASS_CLK,
.of_match = a10_ccu_ids,
- .priv_auto_alloc_size = sizeof(struct ccu_priv),
+ .priv_auto = sizeof(struct ccu_priv),
.ops = &sunxi_clk_ops,
.probe = sunxi_clk_probe,
.bind = a10_clk_bind,
.name = "sun5i_a10s_ccu",
.id = UCLASS_CLK,
.of_match = a10s_ccu_ids,
- .priv_auto_alloc_size = sizeof(struct ccu_priv),
+ .priv_auto = sizeof(struct ccu_priv),
.ops = &sunxi_clk_ops,
.probe = sunxi_clk_probe,
.bind = a10s_clk_bind,
.name = "sun8i_a23_ccu",
.id = UCLASS_CLK,
.of_match = a23_clk_ids,
- .priv_auto_alloc_size = sizeof(struct ccu_priv),
+ .priv_auto = sizeof(struct ccu_priv),
.ops = &sunxi_clk_ops,
.probe = sunxi_clk_probe,
.bind = a23_clk_bind,
.name = "sun6i_a31_ccu",
.id = UCLASS_CLK,
.of_match = a31_clk_ids,
- .priv_auto_alloc_size = sizeof(struct ccu_priv),
+ .priv_auto = sizeof(struct ccu_priv),
.ops = &sunxi_clk_ops,
.probe = sunxi_clk_probe,
.bind = a31_clk_bind,
.name = "sun50i_a64_ccu",
.id = UCLASS_CLK,
.of_match = a64_ccu_ids,
- .priv_auto_alloc_size = sizeof(struct ccu_priv),
+ .priv_auto = sizeof(struct ccu_priv),
.ops = &sunxi_clk_ops,
.probe = sunxi_clk_probe,
.bind = a64_clk_bind,
.name = "sun9i_a80_ccu",
.id = UCLASS_CLK,
.of_match = a80_ccu_ids,
- .priv_auto_alloc_size = sizeof(struct ccu_priv),
+ .priv_auto = sizeof(struct ccu_priv),
.ops = &sunxi_clk_ops,
.probe = sunxi_clk_probe,
.bind = a80_clk_bind,
.name = "sun8i_a83t_ccu",
.id = UCLASS_CLK,
.of_match = a83t_clk_ids,
- .priv_auto_alloc_size = sizeof(struct ccu_priv),
+ .priv_auto = sizeof(struct ccu_priv),
.ops = &sunxi_clk_ops,
.probe = sunxi_clk_probe,
.bind = a83t_clk_bind,
.name = "sun8i_h3_ccu",
.id = UCLASS_CLK,
.of_match = h3_ccu_ids,
- .priv_auto_alloc_size = sizeof(struct ccu_priv),
+ .priv_auto = sizeof(struct ccu_priv),
.ops = &sunxi_clk_ops,
.probe = sunxi_clk_probe,
.bind = h3_clk_bind,
.name = "sun50i_h6_ccu",
.id = UCLASS_CLK,
.of_match = h6_ccu_ids,
- .priv_auto_alloc_size = sizeof(struct ccu_priv),
+ .priv_auto = sizeof(struct ccu_priv),
.ops = &sunxi_clk_ops,
.probe = sunxi_clk_probe,
.bind = h6_clk_bind,
.name = "sun8i_r40_ccu",
.id = UCLASS_CLK,
.of_match = r40_clk_ids,
- .priv_auto_alloc_size = sizeof(struct ccu_priv),
+ .priv_auto = sizeof(struct ccu_priv),
.ops = &sunxi_clk_ops,
.probe = sunxi_clk_probe,
.bind = r40_clk_bind,
.name = "sun8i_v3s_ccu",
.id = UCLASS_CLK,
.of_match = v3s_clk_ids,
- .priv_auto_alloc_size = sizeof(struct ccu_priv),
+ .priv_auto = sizeof(struct ccu_priv),
.ops = &sunxi_clk_ops,
.probe = sunxi_clk_probe,
.bind = v3s_clk_bind,
.id = UCLASS_CLK,
.of_match = uniphier_clk_match,
.probe = uniphier_clk_probe,
- .priv_auto_alloc_size = sizeof(struct uniphier_clk_priv),
+ .priv_auto = sizeof(struct uniphier_clk_priv),
.ops = &uniphier_clk_ops,
};
void *start = ctx->current;
log_debug("- method %d, %s %p\n", method, parent->name, func);
- ret = device_ofdata_to_platdata(parent);
+ ret = device_of_to_plat(parent);
if (ret)
return log_msg_ret("ofdata", ret);
ret = func(parent, ctx);
return log_msg_ret("child unbind", ret);
if (dev->flags & DM_FLAG_ALLOC_PDATA) {
- free(dev->platdata);
- dev->platdata = NULL;
+ free(dev->plat);
+ dev->plat = NULL;
}
if (dev->flags & DM_FLAG_ALLOC_UCLASS_PDATA) {
- free(dev->uclass_platdata);
- dev->uclass_platdata = NULL;
+ free(dev->uclass_plat);
+ dev->uclass_plat = NULL;
}
if (dev->flags & DM_FLAG_ALLOC_PARENT_PDATA) {
- free(dev->parent_platdata);
- dev->parent_platdata = NULL;
+ free(dev->parent_plat);
+ dev->parent_plat = NULL;
}
ret = uclass_unbind_device(dev);
if (ret)
{
int size;
- if (dev->driver->priv_auto_alloc_size) {
+ if (dev->driver->priv_auto) {
free(dev->priv);
dev->priv = NULL;
}
- size = dev->uclass->uc_drv->per_device_auto_alloc_size;
+ size = dev->uclass->uc_drv->per_device_auto;
if (size) {
free(dev->uclass_priv);
dev->uclass_priv = NULL;
}
if (dev->parent) {
- size = dev->parent->driver->per_child_auto_alloc_size;
+ size = dev->parent->driver->per_child_auto;
if (!size) {
size = dev->parent->uclass->uc_drv->
- per_child_auto_alloc_size;
+ per_child_auto;
}
if (size) {
free(dev->parent_priv);
DECLARE_GLOBAL_DATA_PTR;
static int device_bind_common(struct udevice *parent, const struct driver *drv,
- const char *name, void *platdata,
+ const char *name, void *plat,
ulong driver_data, ofnode node,
- uint of_platdata_size, struct udevice **devp)
+ uint of_plat_size, struct udevice **devp)
{
struct udevice *dev;
struct uclass *uc;
#ifdef CONFIG_DEVRES
INIT_LIST_HEAD(&dev->devres_head);
#endif
- dev->platdata = platdata;
+ dev->plat = plat;
dev->driver_data = driver_data;
dev->name = name;
dev->node = node;
}
}
- if (drv->platdata_auto_alloc_size) {
- bool alloc = !platdata;
+ if (drv->plat_auto) {
+ bool alloc = !plat;
if (CONFIG_IS_ENABLED(OF_PLATDATA)) {
- if (of_platdata_size) {
+ if (of_plat_size) {
dev->flags |= DM_FLAG_OF_PLATDATA;
- if (of_platdata_size <
- drv->platdata_auto_alloc_size)
+ if (of_plat_size < drv->plat_auto)
alloc = true;
}
}
if (alloc) {
dev->flags |= DM_FLAG_ALLOC_PDATA;
- dev->platdata = calloc(1,
- drv->platdata_auto_alloc_size);
- if (!dev->platdata) {
+ dev->plat = calloc(1, drv->plat_auto);
+ if (!dev->plat) {
ret = -ENOMEM;
goto fail_alloc1;
}
- if (CONFIG_IS_ENABLED(OF_PLATDATA) && platdata) {
- memcpy(dev->platdata, platdata,
- of_platdata_size);
+ if (CONFIG_IS_ENABLED(OF_PLATDATA) && plat) {
+ memcpy(dev->plat, plat, of_plat_size);
}
}
}
- size = uc->uc_drv->per_device_platdata_auto_alloc_size;
+ size = uc->uc_drv->per_device_plat_auto;
if (size) {
dev->flags |= DM_FLAG_ALLOC_UCLASS_PDATA;
- dev->uclass_platdata = calloc(1, size);
- if (!dev->uclass_platdata) {
+ dev->uclass_plat = calloc(1, size);
+ if (!dev->uclass_plat) {
ret = -ENOMEM;
goto fail_alloc2;
}
}
if (parent) {
- size = parent->driver->per_child_platdata_auto_alloc_size;
+ size = parent->driver->per_child_plat_auto;
if (!size) {
- size = parent->uclass->uc_drv->
- per_child_platdata_auto_alloc_size;
+ size = parent->uclass->uc_drv->per_child_plat_auto;
}
if (size) {
dev->flags |= DM_FLAG_ALLOC_PARENT_PDATA;
- dev->parent_platdata = calloc(1, size);
- if (!dev->parent_platdata) {
+ dev->parent_plat = calloc(1, size);
+ if (!dev->parent_plat) {
ret = -ENOMEM;
goto fail_alloc3;
}
if (CONFIG_IS_ENABLED(DM_DEVICE_REMOVE)) {
list_del(&dev->sibling_node);
if (dev->flags & DM_FLAG_ALLOC_PARENT_PDATA) {
- free(dev->parent_platdata);
- dev->parent_platdata = NULL;
+ free(dev->parent_plat);
+ dev->parent_plat = NULL;
}
}
fail_alloc3:
if (dev->flags & DM_FLAG_ALLOC_UCLASS_PDATA) {
- free(dev->uclass_platdata);
- dev->uclass_platdata = NULL;
+ free(dev->uclass_plat);
+ dev->uclass_plat = NULL;
}
fail_alloc2:
if (dev->flags & DM_FLAG_ALLOC_PDATA) {
- free(dev->platdata);
- dev->platdata = NULL;
+ free(dev->plat);
+ dev->plat = NULL;
}
fail_alloc1:
devres_release_all(dev);
}
int device_bind(struct udevice *parent, const struct driver *drv,
- const char *name, void *platdata, int of_offset,
+ const char *name, void *plat, ofnode node,
struct udevice **devp)
{
- return device_bind_common(parent, drv, name, platdata, 0,
- offset_to_ofnode(of_offset), 0, devp);
-}
-
-int device_bind_ofnode(struct udevice *parent, const struct driver *drv,
- const char *name, void *platdata, ofnode node,
- struct udevice **devp)
-{
- return device_bind_common(parent, drv, name, platdata, 0, node, 0,
+ return device_bind_common(parent, drv, name, plat, 0, node, 0,
devp);
}
const struct driver_info *info, struct udevice **devp)
{
struct driver *drv;
- uint platdata_size = 0;
+ uint plat_size = 0;
int ret;
drv = lists_driver_lookup_name(info->name);
return -EPERM;
#if CONFIG_IS_ENABLED(OF_PLATDATA)
- platdata_size = info->platdata_size;
+ plat_size = info->plat_size;
#endif
- ret = device_bind_common(parent, drv, info->name,
- (void *)info->platdata, 0, ofnode_null(),
- platdata_size, devp);
+ ret = device_bind_common(parent, drv, info->name, (void *)info->plat, 0,
+ ofnode_null(), plat_size, devp);
if (ret)
return ret;
return priv;
}
-int device_ofdata_to_platdata(struct udevice *dev)
+int device_of_to_plat(struct udevice *dev)
{
const struct driver *drv;
int size = 0;
/* Ensure all parents have ofdata */
if (dev->parent) {
- ret = device_ofdata_to_platdata(dev->parent);
+ ret = device_of_to_plat(dev->parent);
if (ret)
goto fail;
assert(drv);
/* Allocate private data if requested and not reentered */
- if (drv->priv_auto_alloc_size && !dev->priv) {
- dev->priv = alloc_priv(drv->priv_auto_alloc_size, drv->flags);
+ if (drv->priv_auto && !dev->priv) {
+ dev->priv = alloc_priv(drv->priv_auto, drv->flags);
if (!dev->priv) {
ret = -ENOMEM;
goto fail;
}
}
/* Allocate private data if requested and not reentered */
- size = dev->uclass->uc_drv->per_device_auto_alloc_size;
+ size = dev->uclass->uc_drv->per_device_auto;
if (size && !dev->uclass_priv) {
dev->uclass_priv = alloc_priv(size,
dev->uclass->uc_drv->flags);
/* Allocate parent data for this child */
if (dev->parent) {
- size = dev->parent->driver->per_child_auto_alloc_size;
+ size = dev->parent->driver->per_child_auto;
if (!size) {
- size = dev->parent->uclass->uc_drv->
- per_child_auto_alloc_size;
+ size = dev->parent->uclass->uc_drv->per_child_auto;
}
if (size && !dev->parent_priv) {
dev->parent_priv = alloc_priv(size, drv->flags);
}
}
- if (drv->ofdata_to_platdata &&
+ if (drv->of_to_plat &&
(CONFIG_IS_ENABLED(OF_PLATDATA) || dev_has_of_node(dev))) {
- ret = drv->ofdata_to_platdata(dev);
+ ret = drv->of_to_plat(dev);
if (ret)
goto fail;
}
drv = dev->driver;
assert(drv);
- ret = device_ofdata_to_platdata(dev);
+ ret = device_of_to_plat(dev);
if (ret)
goto fail;
return ret;
}
-void *dev_get_platdata(const struct udevice *dev)
+void *dev_get_plat(const struct udevice *dev)
{
if (!dev) {
dm_warn("%s: null device\n", __func__);
return NULL;
}
- return dev->platdata;
+ return dev->plat;
}
-void *dev_get_parent_platdata(const struct udevice *dev)
+void *dev_get_parent_plat(const struct udevice *dev)
{
if (!dev) {
dm_warn("%s: null device\n", __func__);
return NULL;
}
- return dev->parent_platdata;
+ return dev->parent_plat;
}
-void *dev_get_uclass_platdata(const struct udevice *dev)
+void *dev_get_uclass_plat(const struct udevice *dev)
{
if (!dev) {
dm_warn("%s: null device\n", __func__);
return NULL;
}
- return dev->uclass_platdata;
+ return dev->uclass_plat;
}
void *dev_get_priv(const struct udevice *dev)
if (!dev)
return -ENODEV;
- ret = device_ofdata_to_platdata(dev);
+ ret = device_of_to_plat(dev);
if (ret)
return ret;
if (!dev)
return -ENODEV;
- ret = device_ofdata_to_platdata(dev);
+ ret = device_of_to_plat(dev);
if (ret)
return ret;
/** enum devres_phase - Shows where resource was allocated
*
* DEVRES_PHASE_BIND: In the bind() method
- * DEVRES_PHASE_OFDATA: In the ofdata_to_platdata() method
+ * DEVRES_PHASE_OFDATA: In the of_to_plat() method
* DEVRES_PHASE_PROBE: In the probe() method
*/
enum devres_phase {
puts("---------------------------------\n");
for (entry = drv; entry != drv + n_ents; entry++) {
printf("%-25.25s @%08lx\n", entry->name,
- (ulong)map_to_sysmem(entry->platdata));
+ (ulong)map_to_sysmem(entry->plat));
}
}
}
}
+bool ofnode_is_enabled(ofnode node)
+{
+ if (ofnode_is_np(node)) {
+ return of_device_is_available(ofnode_to_np(node));
+ } else {
+ return fdtdec_get_is_enabled(gd->fdt_blob,
+ ofnode_to_offset(node));
+ }
+}
+
ofnode ofnode_first_subnode(ofnode node)
{
assert(ofnode_valid(node));
}
#if CONFIG_IS_ENABLED(OF_PLATDATA)
-int regmap_init_mem_platdata(struct udevice *dev, fdt_val_t *reg, int count,
- struct regmap **mapp)
+int regmap_init_mem_plat(struct udevice *dev, fdt_val_t *reg, int count,
+ struct regmap **mapp)
{
struct regmap_range *range;
struct regmap *map;
entry->remove += gd->reloc_off;
if (entry->unbind)
entry->unbind += gd->reloc_off;
- if (entry->ofdata_to_platdata)
- entry->ofdata_to_platdata += gd->reloc_off;
+ if (entry->of_to_plat)
+ entry->of_to_plat += gd->reloc_off;
if (entry->child_post_bind)
entry->child_post_bind += gd->reloc_off;
if (entry->child_pre_probe)
struct driver_info *entry;
for (entry = dev; entry != dev + n_ents; entry++) {
- if (entry->platdata)
- entry->platdata += gd->reloc_off;
+ if (entry->plat)
+ entry->plat += gd->reloc_off;
}
}
ret = device_bind_by_name(NULL, false, &root_info, &DM_ROOT_NON_CONST);
if (ret)
return ret;
-#if CONFIG_IS_ENABLED(OF_CONTROL)
- if (CONFIG_IS_ENABLED(OF_LIVE) && of_live)
- DM_ROOT_NON_CONST->node = np_to_ofnode(gd_of_root());
- else
- DM_ROOT_NON_CONST->node = offset_to_ofnode(0);
-#endif
+ if (CONFIG_IS_ENABLED(OF_CONTROL))
+ DM_ROOT_NON_CONST->node = ofnode_root();
ret = device_probe(DM_ROOT_NON_CONST);
if (ret)
return ret;
}
#endif
-int dm_scan_platdata(bool pre_reloc_only)
+int dm_scan_plat(bool pre_reloc_only)
{
int ret;
}
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
-static int dm_scan_fdt_live(struct udevice *parent,
- const struct device_node *node_parent,
- bool pre_reloc_only)
-{
- struct device_node *np;
- int ret = 0, err;
-
- for (np = node_parent->child; np; np = np->sibling) {
-
- if (!of_device_is_available(np)) {
- pr_debug(" - ignoring disabled device\n");
- continue;
- }
- err = lists_bind_fdt(parent, np_to_ofnode(np), NULL,
- pre_reloc_only);
- if (err && !ret) {
- ret = err;
- debug("%s: ret=%d\n", np->name, ret);
- }
- }
-
- if (ret)
- dm_warn("Some drivers failed to bind\n");
-
- return ret;
-}
-
/**
* dm_scan_fdt_node() - Scan the device tree and bind drivers for a node
*
* for each one.
*
* @parent: Parent device for the devices that will be created
- * @blob: Pointer to device tree blob
- * @offset: Offset of node to scan
+ * @node: Node to scan
* @pre_reloc_only: If true, bind only drivers with the DM_FLAG_PRE_RELOC
* flag. If false bind all drivers.
* @return 0 if OK, -ve on error
*/
-static int dm_scan_fdt_node(struct udevice *parent, const void *blob,
- int offset, bool pre_reloc_only)
+static int dm_scan_fdt_node(struct udevice *parent, ofnode parent_node,
+ bool pre_reloc_only)
{
int ret = 0, err;
+ ofnode node;
+
+ if (!ofnode_valid(parent_node))
+ return 0;
- for (offset = fdt_first_subnode(blob, offset);
- offset > 0;
- offset = fdt_next_subnode(blob, offset)) {
- const char *node_name = fdt_get_name(blob, offset, NULL);
+ for (node = ofnode_first_subnode(parent_node);
+ ofnode_valid(node);
+ node = ofnode_next_subnode(node)) {
+ const char *node_name = ofnode_get_name(node);
- if (!fdtdec_get_is_enabled(blob, offset)) {
+ if (!ofnode_is_enabled(node)) {
pr_debug(" - ignoring disabled device\n");
continue;
}
- err = lists_bind_fdt(parent, offset_to_ofnode(offset), NULL,
- pre_reloc_only);
+ err = lists_bind_fdt(parent, node, NULL, pre_reloc_only);
if (err && !ret) {
ret = err;
debug("%s: ret=%d\n", node_name, ret);
int dm_scan_fdt_dev(struct udevice *dev)
{
- if (!dev_of_valid(dev))
- return 0;
-
- if (of_live_active())
- return dm_scan_fdt_live(dev, dev_np(dev),
- gd->flags & GD_FLG_RELOC ? false : true);
-
- return dm_scan_fdt_node(dev, gd->fdt_blob, dev_of_offset(dev),
+ return dm_scan_fdt_node(dev, dev_ofnode(dev),
gd->flags & GD_FLG_RELOC ? false : true);
}
-int dm_scan_fdt(const void *blob, bool pre_reloc_only)
+int dm_scan_fdt(bool pre_reloc_only)
{
- if (of_live_active())
- return dm_scan_fdt_live(gd->dm_root, gd_of_root(),
- pre_reloc_only);
-
- return dm_scan_fdt_node(gd->dm_root, blob, 0, pre_reloc_only);
+ return dm_scan_fdt_node(gd->dm_root, ofnode_root(), pre_reloc_only);
}
-static int dm_scan_fdt_ofnode_path(const void *blob, const char *path,
- bool pre_reloc_only)
+static int dm_scan_fdt_ofnode_path(const char *path, bool pre_reloc_only)
{
ofnode node;
node = ofnode_path(path);
- if (!ofnode_valid(node))
- return 0;
-
- if (of_live_active())
- return dm_scan_fdt_live(gd->dm_root, node.np, pre_reloc_only);
- return dm_scan_fdt_node(gd->dm_root, blob, node.of_offset,
- pre_reloc_only);
+ return dm_scan_fdt_node(gd->dm_root, node, pre_reloc_only);
}
-int dm_extended_scan_fdt(const void *blob, bool pre_reloc_only)
+int dm_extended_scan(bool pre_reloc_only)
{
int ret, i;
const char * const nodes[] = {
"/firmware"
};
- ret = dm_scan_fdt(blob, pre_reloc_only);
+ ret = dm_scan_fdt(pre_reloc_only);
if (ret) {
debug("dm_scan_fdt() failed: %d\n", ret);
return ret;
/* Some nodes aren't devices themselves but may contain some */
for (i = 0; i < ARRAY_SIZE(nodes); i++) {
- ret = dm_scan_fdt_ofnode_path(blob, nodes[i], pre_reloc_only);
+ ret = dm_scan_fdt_ofnode_path(nodes[i], pre_reloc_only);
if (ret) {
debug("dm_scan_fdt() scan for %s failed: %d\n",
nodes[i], ret);
debug("dm_init() failed: %d\n", ret);
return ret;
}
- ret = dm_scan_platdata(pre_reloc_only);
+ ret = dm_scan_plat(pre_reloc_only);
if (ret) {
- debug("dm_scan_platdata() failed: %d\n", ret);
+ debug("dm_scan_plat() failed: %d\n", ret);
return ret;
}
if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)) {
- ret = dm_extended_scan_fdt(gd->fdt_blob, pre_reloc_only);
+ ret = dm_extended_scan(pre_reloc_only);
if (ret) {
- debug("dm_extended_scan_dt() failed: %d\n", ret);
+ debug("dm_extended_scan() failed: %d\n", ret);
return ret;
}
}
fdt_addr_t simple_bus_translate(struct udevice *dev, fdt_addr_t addr)
{
- struct simple_bus_plat *plat = dev_get_uclass_platdata(dev);
+ struct simple_bus_plat *plat = dev_get_uclass_plat(dev);
if (addr >= plat->base && addr < plat->base + plat->size)
addr = (addr - plat->base) + plat->target;
ret = dev_read_u32_array(dev, "ranges", cell, ARRAY_SIZE(cell));
if (!ret) {
- struct simple_bus_plat *plat = dev_get_uclass_platdata(dev);
+ struct simple_bus_plat *plat = dev_get_uclass_plat(dev);
plat->base = cell[0];
plat->target = cell[1];
.id = UCLASS_SIMPLE_BUS,
.name = "simple_bus",
.post_bind = simple_bus_post_bind,
- .per_device_platdata_auto_alloc_size = sizeof(struct simple_bus_plat),
+ .per_device_plat_auto = sizeof(struct simple_bus_plat),
};
static const struct udevice_id generic_simple_bus_ids[] = {
.of_match = simple_pm_bus_ids,
.probe = simple_pm_bus_probe,
.remove = simple_pm_bus_remove,
- .priv_auto_alloc_size = sizeof(struct clk_bulk),
+ .priv_auto = sizeof(struct clk_bulk),
.flags = DM_FLAG_PRE_RELOC,
};
* using OF_PLATDATA will need to ensure that this is true.
*/
#if CONFIG_IS_ENABLED(OF_PLATDATA)
- struct syscon_base_platdata *plat = dev_get_platdata(dev);
+ struct syscon_base_plat *plat = dev_get_plat(dev);
- return regmap_init_mem_platdata(dev, plat->reg, ARRAY_SIZE(plat->reg),
+ return regmap_init_mem_plat(dev, plat->reg, ARRAY_SIZE(plat->reg),
&priv->regmap);
#else
return regmap_init_mem(dev_ofnode(dev), &priv->regmap);
UCLASS_DRIVER(syscon) = {
.id = UCLASS_SYSCON,
.name = "syscon",
- .per_device_auto_alloc_size = sizeof(struct syscon_uc_info),
+ .per_device_auto = sizeof(struct syscon_uc_info),
.pre_probe = syscon_pre_probe,
};
uc = calloc(1, sizeof(*uc));
if (!uc)
return -ENOMEM;
- if (uc_drv->priv_auto_alloc_size) {
- uc->priv = calloc(1, uc_drv->priv_auto_alloc_size);
+ if (uc_drv->priv_auto) {
+ uc->priv = calloc(1, uc_drv->priv_auto);
if (!uc->priv) {
ret = -ENOMEM;
goto fail_mem;
return 0;
fail:
- if (uc_drv->priv_auto_alloc_size) {
+ if (uc_drv->priv_auto) {
free(uc->priv);
uc->priv = NULL;
}
if (uc_drv->destroy)
uc_drv->destroy(uc);
list_del(&uc->sibling_node);
- if (uc_drv->priv_auto_alloc_size)
+ if (uc_drv->priv_auto)
free(uc->priv);
free(uc);
#include <div64.h>
#include <linux/clk-provider.h>
-struct at91_cpu_platdata {
+struct at91_cpu_plat {
const char *name;
ulong cpufreq_mhz;
ulong mckfreq_mhz;
int at91_cpu_get_desc(const struct udevice *dev, char *buf, int size)
{
- struct at91_cpu_platdata *plat = dev_get_platdata(dev);
+ struct at91_cpu_plat *plat = dev_get_plat(dev);
snprintf(buf, size, "%s\n"
"Crystal frequency: %8lu MHz\n"
static int at91_cpu_get_info(const struct udevice *dev, struct cpu_info *info)
{
- struct at91_cpu_platdata *plat = dev_get_platdata(dev);
+ struct at91_cpu_plat *plat = dev_get_plat(dev);
info->cpu_freq = plat->cpufreq_mhz * 1000000;
info->features = BIT(CPU_FEAT_L1_CACHE);
static int at91_cpu_probe(struct udevice *dev)
{
- struct at91_cpu_platdata *plat = dev_get_platdata(dev);
+ struct at91_cpu_plat *plat = dev_get_plat(dev);
struct clk clk;
ulong rate;
int ret;
.of_match = at91_cpu_ids,
.ops = &at91_cpu_ops,
.probe = at91_cpu_probe,
- .platdata_auto_alloc_size = sizeof(struct at91_cpu_platdata),
+ .plat_auto = sizeof(struct at91_cpu_plat),
.flags = DM_FLAG_PRE_RELOC,
};
/* BMIPS CPU driver */
int bmips_cpu_bind(struct udevice *dev)
{
- struct cpu_platdata *plat = dev_get_parent_platdata(dev);
+ struct cpu_plat *plat = dev_get_parent_plat(dev);
plat->cpu_id = dev_read_u32_default(dev, "reg", -1);
plat->device_id = read_c0_prid();
.of_match = bmips_cpu_ids,
.bind = bmips_cpu_bind,
.probe = bmips_cpu_probe,
- .priv_auto_alloc_size = sizeof(struct bmips_cpu_priv),
+ .priv_auto = sizeof(struct bmips_cpu_priv),
.ops = &bmips_cpu_ops,
.flags = DM_FLAG_PRE_RELOC,
};
U_BOOT_DRIVER(cpu_bus) = {
.name = "cpu_bus",
.id = UCLASS_SIMPLE_BUS,
- .per_child_platdata_auto_alloc_size = sizeof(struct cpu_platdata),
+ .per_child_plat_auto = sizeof(struct cpu_plat),
};
static int uclass_cpu_init(struct uclass *uc)
static int cpu_sandbox_bind(struct udevice *dev)
{
int ret;
- struct cpu_platdata *plat = dev_get_parent_platdata(dev);
+ struct cpu_plat *plat = dev_get_parent_plat(dev);
/* first examine the property in current cpu node */
ret = dev_read_u32(dev, "timebase-frequency", &plat->timebase_freq);
DECLARE_GLOBAL_DATA_PTR;
-struct cpu_imx_platdata {
+struct cpu_imx_plat {
const char *name;
const char *rev;
const char *type;
static void set_core_data(struct udevice *dev)
{
- struct cpu_imx_platdata *plat = dev_get_platdata(dev);
+ struct cpu_imx_plat *plat = dev_get_plat(dev);
if (device_is_compatible(dev, "arm,cortex-a35")) {
plat->cpu_rsrc = SC_R_A35;
}
#if IS_ENABLED(CONFIG_IMX_SCU_THERMAL)
-static int cpu_imx_get_temp(struct cpu_imx_platdata *plat)
+static int cpu_imx_get_temp(struct cpu_imx_plat *plat)
{
struct udevice *thermal_dev;
int cpu_tmp, ret;
return cpu_tmp;
}
#else
-static int cpu_imx_get_temp(struct cpu_imx_platdata *plat)
+static int cpu_imx_get_temp(struct cpu_imx_plat *plat)
{
return 0;
}
int cpu_imx_get_desc(const struct udevice *dev, char *buf, int size)
{
- struct cpu_imx_platdata *plat = dev_get_platdata(dev);
+ struct cpu_imx_plat *plat = dev_get_plat(dev);
int ret, temp;
if (size < 100)
static int cpu_imx_get_info(const struct udevice *dev, struct cpu_info *info)
{
- struct cpu_imx_platdata *plat = dev_get_platdata(dev);
+ struct cpu_imx_plat *plat = dev_get_plat(dev);
info->cpu_freq = plat->freq_mhz * 1000;
info->features = BIT(CPU_FEAT_L1_CACHE) | BIT(CPU_FEAT_MMU);
static int cpu_imx_is_current(struct udevice *dev)
{
- struct cpu_imx_platdata *plat = dev_get_platdata(dev);
+ struct cpu_imx_plat *plat = dev_get_plat(dev);
if (plat->mpidr == (read_mpidr() & 0xffff))
return 1;
static ulong imx8_get_cpu_rate(struct udevice *dev)
{
- struct cpu_imx_platdata *plat = dev_get_platdata(dev);
+ struct cpu_imx_plat *plat = dev_get_plat(dev);
ulong rate;
int ret;
static int imx8_cpu_probe(struct udevice *dev)
{
- struct cpu_imx_platdata *plat = dev_get_platdata(dev);
+ struct cpu_imx_plat *plat = dev_get_plat(dev);
u32 cpurev;
set_core_data(dev);
.of_match = cpu_imx8_ids,
.ops = &cpu_imx8_ops,
.probe = imx8_cpu_probe,
- .platdata_auto_alloc_size = sizeof(struct cpu_imx_platdata),
+ .plat_auto = sizeof(struct cpu_imx_plat),
.flags = DM_FLAG_PRE_RELOC,
};
.id = UCLASS_CPU,
.of_match = mpc83xx_cpu_ids,
.probe = mpc83xx_cpu_probe,
- .priv_auto_alloc_size = sizeof(struct mpc83xx_cpu_priv),
+ .priv_auto = sizeof(struct mpc83xx_cpu_priv),
.ops = &mpc83xx_cpu_ops,
.flags = DM_FLAG_PRE_RELOC,
};
static int riscv_cpu_bind(struct udevice *dev)
{
- struct cpu_platdata *plat = dev_get_parent_platdata(dev);
+ struct cpu_plat *plat = dev_get_parent_plat(dev);
struct driver *drv;
int ret;
.id = UCLASS_RNG,
.ops = &caam_rng_ops,
.probe = caam_rng_probe,
- .priv_auto_alloc_size = sizeof(struct caam_rng_priv),
+ .priv_auto = sizeof(struct caam_rng_priv),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
int sdram_mmr_init_full(struct udevice *dev)
{
- struct altera_sdram_platdata *plat = dev->platdata;
+ struct altera_sdram_plat *plat = dev->plat;
struct altera_sdram_priv *priv = dev_get_priv(dev);
u32 i;
int ret;
struct ram_info info;
};
-struct altera_gen5_sdram_platdata {
+struct altera_gen5_sdram_plat {
struct socfpga_sdr *sdr;
};
return temp;
}
-static int altera_gen5_sdram_ofdata_to_platdata(struct udevice *dev)
+static int altera_gen5_sdram_of_to_plat(struct udevice *dev)
{
- struct altera_gen5_sdram_platdata *plat = dev->platdata;
+ struct altera_gen5_sdram_plat *plat = dev->plat;
plat->sdr = (struct socfpga_sdr *)devfdt_get_addr_index(dev, 0);
if (!plat->sdr)
{
int ret;
unsigned long sdram_size;
- struct altera_gen5_sdram_platdata *plat = dev->platdata;
+ struct altera_gen5_sdram_plat *plat = dev->plat;
struct altera_gen5_sdram_priv *priv = dev_get_priv(dev);
struct socfpga_sdr_ctrl *sdr_ctrl = &plat->sdr->sdr_ctrl;
struct reset_ctl_bulk resets;
.id = UCLASS_RAM,
.of_match = altera_gen5_sdram_ids,
.ops = &altera_gen5_sdram_ops,
- .ofdata_to_platdata = altera_gen5_sdram_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct altera_gen5_sdram_platdata),
+ .of_to_plat = altera_gen5_sdram_of_to_plat,
+ .plat_auto = sizeof(struct altera_gen5_sdram_plat),
.probe = altera_gen5_sdram_probe,
- .priv_auto_alloc_size = sizeof(struct altera_gen5_sdram_priv),
+ .priv_auto = sizeof(struct altera_gen5_sdram_priv),
};
#endif /* CONFIG_SPL_BUILD */
*/
int sdram_mmr_init_full(struct udevice *dev)
{
- struct altera_sdram_platdata *plat = dev->platdata;
+ struct altera_sdram_plat *plat = dev->plat;
struct altera_sdram_priv *priv = dev_get_priv(dev);
u32 update_value, io48_value, ddrioctl;
u32 i;
#define PGTABLE_OFF 0x4000
-u32 hmc_readl(struct altera_sdram_platdata *plat, u32 reg)
+u32 hmc_readl(struct altera_sdram_plat *plat, u32 reg)
{
return readl(plat->iomhc + reg);
}
-u32 hmc_ecc_readl(struct altera_sdram_platdata *plat, u32 reg)
+u32 hmc_ecc_readl(struct altera_sdram_plat *plat, u32 reg)
{
return readl(plat->hmc + reg);
}
-u32 hmc_ecc_writel(struct altera_sdram_platdata *plat,
+u32 hmc_ecc_writel(struct altera_sdram_plat *plat,
u32 data, u32 reg)
{
return writel(data, plat->hmc + reg);
}
-u32 ddr_sch_writel(struct altera_sdram_platdata *plat, u32 data,
+u32 ddr_sch_writel(struct altera_sdram_plat *plat, u32 data,
u32 reg)
{
return writel(data, plat->ddr_sch + reg);
}
-int emif_clear(struct altera_sdram_platdata *plat)
+int emif_clear(struct altera_sdram_plat *plat)
{
hmc_ecc_writel(plat, 0, RSTHANDSHAKECTRL);
false, 1000, false);
}
-int emif_reset(struct altera_sdram_platdata *plat)
+int emif_reset(struct altera_sdram_plat *plat)
{
u32 c2s, s2c, ret;
* Calculate SDRAM device size based on SDRAM controller parameters.
* Size is specified in bytes.
*/
-phys_size_t sdram_calculate_size(struct altera_sdram_platdata *plat)
+phys_size_t sdram_calculate_size(struct altera_sdram_plat *plat)
{
u32 dramaddrw = hmc_readl(plat, DRAMADDRW);
return size;
}
-static int altera_sdram_ofdata_to_platdata(struct udevice *dev)
+static int altera_sdram_of_to_plat(struct udevice *dev)
{
- struct altera_sdram_platdata *plat = dev->platdata;
+ struct altera_sdram_plat *plat = dev->plat;
fdt_addr_t addr;
addr = dev_read_addr_index(dev, 0);
.id = UCLASS_RAM,
.of_match = altera_sdram_ids,
.ops = &altera_sdram_ops,
- .ofdata_to_platdata = altera_sdram_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct altera_sdram_platdata),
+ .of_to_plat = altera_sdram_of_to_plat,
+ .plat_auto = sizeof(struct altera_sdram_plat),
.probe = altera_sdram_probe,
- .priv_auto_alloc_size = sizeof(struct altera_sdram_priv),
+ .priv_auto = sizeof(struct altera_sdram_priv),
};
struct reset_ctl_bulk resets;
};
-struct altera_sdram_platdata {
+struct altera_sdram_plat {
void __iomem *hmc;
void __iomem *ddr_sch;
void __iomem *iomhc;
#define FW_HMC_ADAPTOR_REG_ADDR 0xf8020004
#define FW_HMC_ADAPTOR_MPU_MASK BIT(0)
-u32 hmc_readl(struct altera_sdram_platdata *plat, u32 reg);
-u32 hmc_ecc_readl(struct altera_sdram_platdata *plat, u32 reg);
-u32 hmc_ecc_writel(struct altera_sdram_platdata *plat,
+u32 hmc_readl(struct altera_sdram_plat *plat, u32 reg);
+u32 hmc_ecc_readl(struct altera_sdram_plat *plat, u32 reg);
+u32 hmc_ecc_writel(struct altera_sdram_plat *plat,
u32 data, u32 reg);
-u32 ddr_sch_writel(struct altera_sdram_platdata *plat, u32 data,
+u32 ddr_sch_writel(struct altera_sdram_plat *plat, u32 data,
u32 reg);
-int emif_clear(struct altera_sdram_platdata *plat);
-int emif_reset(struct altera_sdram_platdata *plat);
+int emif_clear(struct altera_sdram_plat *plat);
+int emif_reset(struct altera_sdram_plat *plat);
int poll_hmc_clock_status(void);
void sdram_clear_mem(phys_addr_t addr, phys_size_t size);
void sdram_init_ecc_bits(struct bd_info *bd);
void sdram_size_check(struct bd_info *bd);
-phys_size_t sdram_calculate_size(struct altera_sdram_platdata *plat);
+phys_size_t sdram_calculate_size(struct altera_sdram_plat *plat);
int sdram_mmr_init_full(struct udevice *dev);
#endif /* _SDRAM_SOC64_H_ */
U_BOOT_DEVICE(demo0) = {
.name = "demo_shape_drv",
- .platdata = &red_square,
+ .plat = &red_square,
};
U_BOOT_DEVICE(demo1) = {
.name = "demo_simple_drv",
- .platdata = &red_square,
+ .plat = &red_square,
};
U_BOOT_DEVICE(demo2) = {
.name = "demo_shape_drv",
- .platdata = &green_triangle,
+ .plat = &green_triangle,
};
U_BOOT_DEVICE(demo3) = {
.name = "demo_simple_drv",
- .platdata = &yellow_hexagon,
+ .plat = &yellow_hexagon,
};
U_BOOT_DEVICE(demo4) = {
.name = "demo_shape_drv",
- .platdata = &yellow_hexagon,
+ .plat = &yellow_hexagon,
};
/* Crazy little function to draw shapes on the console */
static int shape_hello(struct udevice *dev, int ch)
{
- const struct dm_demo_pdata *pdata = dev_get_platdata(dev);
+ const struct dm_demo_pdata *pdata = dev_get_plat(dev);
struct shape_data *data = dev_get_priv(dev);
static const struct shape {
int start;
.set_light = set_light,
};
-static int shape_ofdata_to_platdata(struct udevice *dev)
+static int shape_of_to_plat(struct udevice *dev)
{
- struct dm_demo_pdata *pdata = dev_get_platdata(dev);
+ struct dm_demo_pdata *pdata = dev_get_plat(dev);
int ret;
/* Parse the data that is common with all demo devices */
.name = "demo_shape_drv",
.of_match = demo_shape_id,
.id = UCLASS_DEMO,
- .ofdata_to_platdata = shape_ofdata_to_platdata,
+ .of_to_plat = shape_of_to_plat,
.ops = &shape_ops,
.probe = dm_shape_probe,
.remove = dm_shape_remove,
- .priv_auto_alloc_size = sizeof(struct shape_data),
- .platdata_auto_alloc_size = sizeof(struct dm_demo_pdata),
+ .priv_auto = sizeof(struct shape_data),
+ .plat_auto = sizeof(struct dm_demo_pdata),
};
static int simple_hello(struct udevice *dev, int ch)
{
- const struct dm_demo_pdata *pdata = dev_get_platdata(dev);
+ const struct dm_demo_pdata *pdata = dev_get_plat(dev);
printf("Hello from %08x: %s %d\n", (uint)map_to_sysmem(dev), pdata->colour,
pdata->sides);
.hello = simple_hello,
};
-static int demo_shape_ofdata_to_platdata(struct udevice *dev)
+static int demo_shape_of_to_plat(struct udevice *dev)
{
/* Parse the data that is common with all demo devices */
return demo_parse_dt(dev);
.name = "demo_simple_drv",
.of_match = demo_shape_id,
.id = UCLASS_DEMO,
- .ofdata_to_platdata = demo_shape_ofdata_to_platdata,
+ .of_to_plat = demo_shape_of_to_plat,
.ops = &simple_ops,
- .platdata_auto_alloc_size = sizeof(struct dm_demo_pdata),
+ .plat_auto = sizeof(struct dm_demo_pdata),
};
int demo_parse_dt(struct udevice *dev)
{
- struct dm_demo_pdata *pdata = dev_get_platdata(dev);
+ struct dm_demo_pdata *pdata = dev_get_plat(dev);
int dn = dev_of_offset(dev);
pdata->sides = fdtdec_get_int(gd->fdt_blob, dn, "sides", 0);
.id = UCLASS_DMA,
.of_match = bcm6348_iudma_ids,
.ops = &bcm6348_iudma_ops,
- .priv_auto_alloc_size = sizeof(struct bcm6348_iudma_priv),
+ .priv_auto = sizeof(struct bcm6348_iudma_priv),
.probe = bcm6348_iudma_probe,
};
.id = UCLASS_DMA,
.name = "dma",
.flags = DM_UC_FLAG_SEQ_ALIAS,
- .per_device_auto_alloc_size = sizeof(struct dma_dev_priv),
+ .per_device_auto = sizeof(struct dma_dev_priv),
};
.of_match = sandbox_dma_ids,
.ops = &sandbox_dma_ops,
.probe = sandbox_dma_probe,
- .priv_auto_alloc_size = sizeof(struct sandbox_dma_dev),
+ .priv_auto = sizeof(struct sandbox_dma_dev),
};
return 0;
}
-static int ti_edma3_ofdata_to_platdata(struct udevice *dev)
+static int ti_edma3_of_to_plat(struct udevice *dev)
{
struct ti_edma3_priv *priv = dev_get_priv(dev);
.id = UCLASS_DMA,
.of_match = ti_edma3_ids,
.ops = &ti_edma3_ops,
- .ofdata_to_platdata = ti_edma3_ofdata_to_platdata,
+ .of_to_plat = ti_edma3_of_to_plat,
.probe = ti_edma3_probe,
- .priv_auto_alloc_size = sizeof(struct ti_edma3_priv),
+ .priv_auto = sizeof(struct ti_edma3_priv),
};
#endif /* CONFIG_DMA */
.of_match = udma_ids,
.ops = &udma_ops,
.probe = udma_probe,
- .priv_auto_alloc_size = sizeof(struct udma_dev),
+ .priv_auto = sizeof(struct udma_dev),
};
.name = "scmi-over-mailbox",
.id = UCLASS_SCMI_AGENT,
.of_match = scmi_mbox_ids,
- .priv_auto_alloc_size = sizeof(struct scmi_mbox_channel),
+ .priv_auto = sizeof(struct scmi_mbox_channel),
.probe = scmi_mbox_probe,
.ops = &scmi_mbox_ops,
};
.name = "sandbox-scmi_agent",
.id = UCLASS_SCMI_AGENT,
.of_match = sandbox_scmi_test_ids,
- .priv_auto_alloc_size = sizeof(struct sandbox_scmi_agent),
+ .priv_auto = sizeof(struct sandbox_scmi_agent),
.probe = sandbox_scmi_test_probe,
.remove = sandbox_scmi_test_remove,
.ops = &sandbox_scmi_test_ops,
.name = "sandbox-scmi_devices",
.id = UCLASS_MISC,
.of_match = sandbox_scmi_devices_ids,
- .priv_auto_alloc_size = sizeof(struct sandbox_scmi_device_priv),
+ .priv_auto = sizeof(struct sandbox_scmi_device_priv),
.remove = sandbox_scmi_devices_remove,
.probe = sandbox_scmi_devices_probe,
};
continue;
}
- ret = device_bind_ofnode(dev, drv, ofnode_get_name(node),
- NULL, node, NULL);
+ ret = device_bind(dev, drv, ofnode_get_name(node), NULL, node,
+ NULL);
if (ret)
break;
}
.name = "scmi-over-smccc",
.id = UCLASS_SCMI_AGENT,
.of_match = scmi_smccc_ids,
- .priv_auto_alloc_size = sizeof(struct scmi_smccc_channel),
+ .priv_auto = sizeof(struct scmi_smccc_channel),
.probe = scmi_smccc_probe,
.ops = &scmi_smccc_ops,
};
.id = UCLASS_FIRMWARE,
.of_match = ti_sci_ids,
.probe = ti_sci_probe,
- .priv_auto_alloc_size = sizeof(struct ti_sci_info),
+ .priv_auto = sizeof(struct ti_sci_info),
};
.id = UCLASS_GPIO,
.ops = &gen_74x164_ops,
.probe = gen_74x164_probe,
- .priv_auto_alloc_size = sizeof(struct gen_74x164_priv),
+ .priv_auto = sizeof(struct gen_74x164_priv),
.of_match = gen_74x164_ids,
};
u32 direction; /* Direction register */
};
-struct altera_pio_platdata {
+struct altera_pio_plat {
struct altera_pio_regs *regs;
int gpio_count;
const char *bank_name;
static int altera_pio_direction_input(struct udevice *dev, unsigned pin)
{
- struct altera_pio_platdata *plat = dev_get_platdata(dev);
+ struct altera_pio_plat *plat = dev_get_plat(dev);
struct altera_pio_regs *const regs = plat->regs;
clrbits_le32(®s->direction, 1 << pin);
static int altera_pio_direction_output(struct udevice *dev, unsigned pin,
int val)
{
- struct altera_pio_platdata *plat = dev_get_platdata(dev);
+ struct altera_pio_plat *plat = dev_get_plat(dev);
struct altera_pio_regs *const regs = plat->regs;
if (val)
static int altera_pio_get_value(struct udevice *dev, unsigned pin)
{
- struct altera_pio_platdata *plat = dev_get_platdata(dev);
+ struct altera_pio_plat *plat = dev_get_plat(dev);
struct altera_pio_regs *const regs = plat->regs;
return !!(readl(®s->data) & (1 << pin));
static int altera_pio_set_value(struct udevice *dev, unsigned pin, int val)
{
- struct altera_pio_platdata *plat = dev_get_platdata(dev);
+ struct altera_pio_plat *plat = dev_get_plat(dev);
struct altera_pio_regs *const regs = plat->regs;
if (val)
static int altera_pio_probe(struct udevice *dev)
{
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
- struct altera_pio_platdata *plat = dev_get_platdata(dev);
+ struct altera_pio_plat *plat = dev_get_plat(dev);
uc_priv->gpio_count = plat->gpio_count;
uc_priv->bank_name = plat->bank_name;
return 0;
}
-static int altera_pio_ofdata_to_platdata(struct udevice *dev)
+static int altera_pio_of_to_plat(struct udevice *dev)
{
- struct altera_pio_platdata *plat = dev_get_platdata(dev);
+ struct altera_pio_plat *plat = dev_get_plat(dev);
plat->regs = map_physmem(dev_read_addr(dev),
sizeof(struct altera_pio_regs),
.id = UCLASS_GPIO,
.of_match = altera_pio_ids,
.ops = &altera_pio_ops,
- .ofdata_to_platdata = altera_pio_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct altera_pio_platdata),
+ .of_to_plat = altera_pio_of_to_plat,
+ .plat_auto = sizeof(struct altera_pio_plat),
.probe = altera_pio_probe,
};
static int at91_gpio_probe(struct udevice *dev)
{
struct at91_port_priv *port = dev_get_priv(dev);
- struct at91_port_platdata *plat = dev_get_platdata(dev);
+ struct at91_port_plat *plat = dev_get_plat(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct clk clk;
int ret;
.id = UCLASS_GPIO,
#if CONFIG_IS_ENABLED(OF_CONTROL)
.of_match = at91_gpio_ids,
- .platdata_auto_alloc_size = sizeof(struct at91_port_platdata),
+ .plat_auto = sizeof(struct at91_port_plat),
#endif
.ops = &gpio_at91_ops,
.probe = at91_gpio_probe,
- .priv_auto_alloc_size = sizeof(struct at91_port_priv),
+ .priv_auto = sizeof(struct at91_port_priv),
};
#endif
u32 nbanks;
};
-struct atmel_pio4_platdata {
+struct atmel_pio4_plat {
struct atmel_pio4_port *reg_base;
};
static struct atmel_pio4_port *atmel_pio4_bank_base(struct udevice *dev,
u32 bank)
{
- struct atmel_pio4_platdata *plat = dev_get_platdata(dev);
+ struct atmel_pio4_plat *plat = dev_get_plat(dev);
struct atmel_pio4_port *port_base =
(struct atmel_pio4_port *)((u32)plat->reg_base +
ATMEL_PIO_BANK_OFFSET * bank);
static int atmel_pio4_probe(struct udevice *dev)
{
- struct atmel_pio4_platdata *plat = dev_get_platdata(dev);
+ struct atmel_pio4_plat *plat = dev_get_plat(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct atmel_pioctrl_data *pioctrl_data;
struct clk clk;
.probe = atmel_pio4_probe,
.bind = atmel_pio4_bind,
.of_match = atmel_pio4_ids,
- .platdata_auto_alloc_size = sizeof(struct atmel_pio4_platdata),
+ .plat_auto = sizeof(struct atmel_pio4_plat),
};
#endif
static int bcm2835_gpio_probe(struct udevice *dev)
{
struct bcm2835_gpios *gpios = dev_get_priv(dev);
- struct bcm2835_gpio_platdata *plat = dev_get_platdata(dev);
+ struct bcm2835_gpio_plat *plat = dev_get_plat(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
uc_priv->bank_name = "GPIO";
}
#if CONFIG_IS_ENABLED(OF_CONTROL)
-static int bcm2835_gpio_ofdata_to_platdata(struct udevice *dev)
+static int bcm2835_gpio_of_to_plat(struct udevice *dev)
{
- struct bcm2835_gpio_platdata *plat = dev_get_platdata(dev);
+ struct bcm2835_gpio_plat *plat = dev_get_plat(dev);
fdt_addr_t addr;
addr = dev_read_addr(dev);
U_BOOT_DRIVER(gpio_bcm2835) = {
.name = "gpio_bcm2835",
.id = UCLASS_GPIO,
- .ofdata_to_platdata = of_match_ptr(bcm2835_gpio_ofdata_to_platdata),
- .platdata_auto_alloc_size = sizeof(struct bcm2835_gpio_platdata),
+ .of_to_plat = of_match_ptr(bcm2835_gpio_of_to_plat),
+ .plat_auto = sizeof(struct bcm2835_gpio_plat),
.ops = &gpio_bcm2835_ops,
.probe = bcm2835_gpio_probe,
.flags = DM_FLAG_PRE_RELOC,
- .priv_auto_alloc_size = sizeof(struct bcm2835_gpios),
+ .priv_auto = sizeof(struct bcm2835_gpios),
};
.id = UCLASS_GPIO,
.of_match = bcm6345_gpio_ids,
.ops = &bcm6345_gpio_ops,
- .priv_auto_alloc_size = sizeof(struct bcm6345_gpio_priv),
+ .priv_auto = sizeof(struct bcm6345_gpio_priv),
.probe = bcm6345_gpio_probe,
};
.id = UCLASS_GPIO,
.ops = &gpio_cortina_ops,
.probe = ca_gpio_probe,
- .priv_auto_alloc_size = sizeof(struct cortina_gpio_bank),
+ .priv_auto = sizeof(struct cortina_gpio_bank),
.of_match = ca_gpio_ids,
};
#endif /* CONFIG_DM_GPIO */
static int davinci_gpio_probe(struct udevice *dev)
{
struct davinci_gpio_bank *bank = dev_get_priv(dev);
- struct davinci_gpio_platdata *plat = dev_get_platdata(dev);
+ struct davinci_gpio_plat *plat = dev_get_plat(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
const void *fdt = gd->fdt_blob;
int node = dev_of_offset(dev);
{ }
};
-static int davinci_gpio_ofdata_to_platdata(struct udevice *dev)
+static int davinci_gpio_of_to_plat(struct udevice *dev)
{
- struct davinci_gpio_platdata *plat = dev_get_platdata(dev);
+ struct davinci_gpio_plat *plat = dev_get_plat(dev);
fdt_addr_t addr;
addr = dev_read_addr(dev);
.name = "ti_dm6441_gpio",
.id = UCLASS_GPIO,
.ops = &gpio_davinci_ops,
- .ofdata_to_platdata = of_match_ptr(davinci_gpio_ofdata_to_platdata),
+ .of_to_plat = of_match_ptr(davinci_gpio_of_to_plat),
.of_match = davinci_gpio_ids,
.bind = dm_scan_fdt_dev,
- .platdata_auto_alloc_size = sizeof(struct davinci_gpio_platdata),
+ .plat_auto = sizeof(struct davinci_gpio_plat),
.probe = davinci_gpio_probe,
- .priv_auto_alloc_size = sizeof(struct davinci_gpio_bank),
+ .priv_auto = sizeof(struct davinci_gpio_bank),
};
#endif
#if CONFIG_IS_ENABLED(DM_GPIO)
/* Information about a GPIO bank */
-struct davinci_gpio_platdata {
+struct davinci_gpio_plat {
int bank_index;
ulong base; /* address of registers in physical memory */
const char *port_name;
struct reset_ctl_bulk resets;
};
-struct gpio_dwapb_platdata {
+struct gpio_dwapb_plat {
const char *name;
int bank;
int pins;
static int dwapb_gpio_direction_input(struct udevice *dev, unsigned pin)
{
- struct gpio_dwapb_platdata *plat = dev_get_platdata(dev);
+ struct gpio_dwapb_plat *plat = dev_get_plat(dev);
clrbits_le32(plat->base + GPIO_SWPORT_DDR(plat->bank), 1 << pin);
return 0;
static int dwapb_gpio_direction_output(struct udevice *dev, unsigned pin,
int val)
{
- struct gpio_dwapb_platdata *plat = dev_get_platdata(dev);
+ struct gpio_dwapb_plat *plat = dev_get_plat(dev);
setbits_le32(plat->base + GPIO_SWPORT_DDR(plat->bank), 1 << pin);
static int dwapb_gpio_set_value(struct udevice *dev, unsigned pin, int val)
{
- struct gpio_dwapb_platdata *plat = dev_get_platdata(dev);
+ struct gpio_dwapb_plat *plat = dev_get_plat(dev);
if (val)
setbits_le32(plat->base + GPIO_SWPORT_DR(plat->bank), 1 << pin);
static int dwapb_gpio_get_function(struct udevice *dev, unsigned offset)
{
- struct gpio_dwapb_platdata *plat = dev_get_platdata(dev);
+ struct gpio_dwapb_plat *plat = dev_get_plat(dev);
u32 gpio;
gpio = readl(plat->base + GPIO_SWPORT_DDR(plat->bank));
static int dwapb_gpio_get_value(struct udevice *dev, unsigned pin)
{
- struct gpio_dwapb_platdata *plat = dev_get_platdata(dev);
+ struct gpio_dwapb_plat *plat = dev_get_plat(dev);
u32 value;
if (dwapb_gpio_get_function(dev, pin) == GPIOF_OUTPUT)
static int gpio_dwapb_probe(struct udevice *dev)
{
struct gpio_dev_priv *priv = dev_get_uclass_priv(dev);
- struct gpio_dwapb_platdata *plat = dev->platdata;
+ struct gpio_dwapb_plat *plat = dev->plat;
if (!plat) {
/* Reset on parent device only */
static int gpio_dwapb_bind(struct udevice *dev)
{
- struct gpio_dwapb_platdata *plat = dev_get_platdata(dev);
+ struct gpio_dwapb_plat *plat = dev_get_plat(dev);
struct udevice *subdev;
fdt_addr_t base;
int ret, bank = 0;
}
}
- ret = device_bind_ofnode(dev, dev->driver, plat->name,
- plat, node, &subdev);
+ ret = device_bind(dev, dev->driver, plat->name, plat, node,
+ &subdev);
if (ret)
return ret;
static int gpio_dwapb_remove(struct udevice *dev)
{
- struct gpio_dwapb_platdata *plat = dev_get_platdata(dev);
+ struct gpio_dwapb_plat *plat = dev_get_plat(dev);
struct gpio_dwapb_priv *priv = dev_get_priv(dev);
if (!plat && priv)
.bind = gpio_dwapb_bind,
.probe = gpio_dwapb_probe,
.remove = gpio_dwapb_remove,
- .priv_auto_alloc_size = sizeof(struct gpio_dwapb_priv),
+ .priv_auto = sizeof(struct gpio_dwapb_priv),
};
.id = UCLASS_GPIO,
.of_match = rcar_gpio_ids,
.ops = &rcar_gpio_ops,
- .priv_auto_alloc_size = sizeof(struct rcar_gpio_priv),
+ .priv_auto = sizeof(struct rcar_gpio_priv),
.probe = rcar_gpio_probe,
};
.name = "r7s72100-gpio",
.id = UCLASS_GPIO,
.ops = &r7s72100_gpio_ops,
- .priv_auto_alloc_size = sizeof(struct r7s72100_gpio_priv),
+ .priv_auto = sizeof(struct r7s72100_gpio_priv),
.probe = r7s72100_gpio_probe,
};
u32 val[2];
};
-static int gpio_hog_ofdata_to_platdata(struct udevice *dev)
+static int gpio_hog_of_to_plat(struct udevice *dev)
{
- struct gpio_hog_data *plat = dev_get_platdata(dev);
+ struct gpio_hog_data *plat = dev_get_plat(dev);
const char *nodename;
int ret;
static int gpio_hog_probe(struct udevice *dev)
{
- struct gpio_hog_data *plat = dev_get_platdata(dev);
+ struct gpio_hog_data *plat = dev_get_plat(dev);
struct gpio_hog_priv *priv = dev_get_priv(dev);
int ret;
U_BOOT_DRIVER(gpio_hog) = {
.name = "gpio_hog",
.id = UCLASS_NOP,
- .ofdata_to_platdata = gpio_hog_ofdata_to_platdata,
+ .of_to_plat = gpio_hog_of_to_plat,
.probe = gpio_hog_probe,
- .priv_auto_alloc_size = sizeof(struct gpio_hog_priv),
- .platdata_auto_alloc_size = sizeof(struct gpio_hog_data),
+ .priv_auto = sizeof(struct gpio_hog_priv),
+ .plat_auto = sizeof(struct gpio_hog_data),
};
#else
int gpio_hog_lookup_name(const char *name, struct gpio_desc **desc)
.post_probe = gpio_post_probe,
.post_bind = gpio_post_bind,
.pre_remove = gpio_pre_remove,
- .per_device_auto_alloc_size = sizeof(struct gpio_dev_priv),
+ .per_device_auto = sizeof(struct gpio_dev_priv),
};
.id = UCLASS_GPIO,
.of_match = uniphier_gpio_match,
.probe = uniphier_gpio_probe,
- .priv_auto_alloc_size = sizeof(struct uniphier_gpio_priv),
+ .priv_auto = sizeof(struct uniphier_gpio_priv),
.ops = &uniphier_gpio_ops,
};
static int hi6220_gpio_probe(struct udevice *dev)
{
struct gpio_bank *bank = dev_get_priv(dev);
- struct hikey_gpio_platdata *plat = dev_get_platdata(dev);
+ struct hikey_gpio_plat *plat = dev_get_plat(dev);
struct gpio_dev_priv *uc_priv = dev->uclass_priv;
char name[18], *str;
.id = UCLASS_GPIO,
.ops = &gpio_hi6220_ops,
.probe = hi6220_gpio_probe,
- .priv_auto_alloc_size = sizeof(struct gpio_bank),
+ .priv_auto = sizeof(struct gpio_bank),
};
.ops = &hsdk_creg_gpio_ops,
.probe = hsdk_creg_gpio_probe,
.of_match = hsdk_creg_gpio_ids,
- .platdata_auto_alloc_size = sizeof(struct hsdk_creg_gpio),
+ .plat_auto = sizeof(struct hsdk_creg_gpio),
};
static int imx_rgpio2p_probe(struct udevice *dev)
{
struct imx_rgpio2p_data *bank = dev_get_priv(dev);
- struct imx_rgpio2p_plat *plat = dev_get_platdata(dev);
+ struct imx_rgpio2p_plat *plat = dev_get_plat(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
int banknum;
char name[18], *str;
static int imx_rgpio2p_bind(struct udevice *dev)
{
- struct imx_rgpio2p_plat *plat = dev->platdata;
+ struct imx_rgpio2p_plat *plat = dev->plat;
fdt_addr_t addr;
/*
- * If platdata already exsits, directly return.
- * Actually only when DT is not supported, platdata
+ * If plat already exsits, directly return.
+ * Actually only when DT is not supported, plat
* is statically initialized in U_BOOT_DEVICES.Here
* will return.
*/
* TODO:
* When every board is converted to driver model and DT is supported,
* this can be done by auto-alloc feature, but not using calloc
- * to alloc memory for platdata.
+ * to alloc memory for plat.
*
* For example imx_rgpio2p_plat uses platform data rather than device
* tree.
plat->regs = (struct gpio_regs *)addr;
plat->bank_index = dev->req_seq;
- dev->platdata = plat;
+ dev->plat = plat;
return 0;
}
.id = UCLASS_GPIO,
.ops = &imx_rgpio2p_ops,
.probe = imx_rgpio2p_probe,
- .priv_auto_alloc_size = sizeof(struct imx_rgpio2p_plat),
+ .priv_auto = sizeof(struct imx_rgpio2p_plat),
.of_match = imx_rgpio2p_ids,
.bind = imx_rgpio2p_bind,
};
static int broadwell_gpio_probe(struct udevice *dev)
{
- struct broadwell_bank_platdata *plat = dev_get_platdata(dev);
+ struct broadwell_bank_plat *plat = dev_get_plat(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct broadwell_bank_priv *priv = dev_get_priv(dev);
struct udevice *pinctrl;
return 0;
}
-static int broadwell_gpio_ofdata_to_platdata(struct udevice *dev)
+static int broadwell_gpio_of_to_plat(struct udevice *dev)
{
- struct broadwell_bank_platdata *plat = dev_get_platdata(dev);
+ struct broadwell_bank_plat *plat = dev_get_plat(dev);
u32 gpiobase;
int bank;
int ret;
.id = UCLASS_GPIO,
.of_match = intel_broadwell_gpio_ids,
.ops = &gpio_broadwell_ops,
- .ofdata_to_platdata = broadwell_gpio_ofdata_to_platdata,
+ .of_to_plat = broadwell_gpio_of_to_plat,
.probe = broadwell_gpio_probe,
- .priv_auto_alloc_size = sizeof(struct broadwell_bank_priv),
- .platdata_auto_alloc_size = sizeof(struct broadwell_bank_platdata),
+ .priv_auto = sizeof(struct broadwell_bank_priv),
+ .plat_auto = sizeof(struct broadwell_bank_plat),
};
return 0;
}
-static int intel_gpio_ofdata_to_platdata(struct udevice *dev)
+static int intel_gpio_of_to_plat(struct udevice *dev)
{
struct gpio_dev_priv *upriv = dev_get_uclass_priv(dev);
struct intel_pinctrl_priv *pinctrl_priv = dev_get_priv(dev->parent);
.id = UCLASS_GPIO,
.of_match = intel_intel_gpio_ids,
.ops = &gpio_intel_ops,
- .ofdata_to_platdata = intel_gpio_ofdata_to_platdata,
+ .of_to_plat = intel_gpio_of_to_plat,
.probe = intel_gpio_probe,
};
return 0;
}
-static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
+static int gpio_ich6_of_to_plat(struct udevice *dev)
{
- struct ich6_bank_platdata *plat = dev_get_platdata(dev);
+ struct ich6_bank_plat *plat = dev_get_plat(dev);
u32 gpiobase;
int offset;
int ret;
static int ich6_gpio_probe(struct udevice *dev)
{
- struct ich6_bank_platdata *plat = dev_get_platdata(dev);
+ struct ich6_bank_plat *plat = dev_get_plat(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct ich6_bank_priv *bank = dev_get_priv(dev);
const void *prop;
.id = UCLASS_GPIO,
.of_match = intel_ich6_gpio_ids,
.ops = &gpio_ich6_ops,
- .ofdata_to_platdata = gpio_ich6_ofdata_to_platdata,
+ .of_to_plat = gpio_ich6_of_to_plat,
.probe = ich6_gpio_probe,
- .priv_auto_alloc_size = sizeof(struct ich6_bank_priv),
- .platdata_auto_alloc_size = sizeof(struct ich6_bank_platdata),
+ .priv_auto = sizeof(struct ich6_bank_priv),
+ .plat_auto = sizeof(struct ich6_bank_plat),
};
* @name: gpio device name, ex GPIO0, GPIO1
* @ngpios: total number of gpios
*/
-struct iproc_gpio_platdata {
+struct iproc_gpio_plat {
struct udevice *pinctrl_dev;
struct list_head gpiomap;
void __iomem *base;
* @gpio: GPIO pin
* @set: set or clear
*/
-static inline void iproc_gpio_set_bit(struct iproc_gpio_platdata *plat,
+static inline void iproc_gpio_set_bit(struct iproc_gpio_plat *plat,
u32 reg, u32 gpio, bool set)
{
u32 offset = GPIO_REG(gpio, reg);
(set ? BIT(shift) : 0));
}
-static inline bool iproc_gpio_get_bit(struct iproc_gpio_platdata *plat,
+static inline bool iproc_gpio_get_bit(struct iproc_gpio_plat *plat,
u32 reg, u32 gpio)
{
u32 offset = GPIO_REG(gpio, reg);
* @plat: iproc GPIO device
* @gpio: GPIO pin
*/
-static u32 iproc_get_pctrl_from_gpio(struct iproc_gpio_platdata *plat, u32 gpio)
+static u32 iproc_get_pctrl_from_gpio(struct iproc_gpio_plat *plat, u32 gpio)
{
struct iproc_gpio_pctrl_map *range = NULL;
struct list_head *pos, *tmp;
*/
static int iproc_get_gpio_pctrl_mapping(struct udevice *dev)
{
- struct iproc_gpio_platdata *plat = dev_get_platdata(dev);
+ struct iproc_gpio_plat *plat = dev_get_plat(dev);
struct iproc_gpio_pctrl_map *range = NULL;
struct ofnode_phandle_args args;
int index = 0, ret;
static int iproc_gpio_request(struct udevice *dev, u32 gpio, const char *label)
{
- struct iproc_gpio_platdata *plat = dev_get_platdata(dev);
+ struct iproc_gpio_plat *plat = dev_get_plat(dev);
u32 pctrl;
/* nothing to do if there is no corresponding pinctrl device */
static int iproc_gpio_direction_input(struct udevice *dev, u32 gpio)
{
- struct iproc_gpio_platdata *plat = dev_get_platdata(dev);
+ struct iproc_gpio_plat *plat = dev_get_plat(dev);
iproc_gpio_set_bit(plat, OUT_EN_OFFSET, gpio, false);
dev_dbg(dev, "gpio:%u set input\n", gpio);
static int iproc_gpio_direction_output(struct udevice *dev, u32 gpio, int value)
{
- struct iproc_gpio_platdata *plat = dev_get_platdata(dev);
+ struct iproc_gpio_plat *plat = dev_get_plat(dev);
iproc_gpio_set_bit(plat, OUT_EN_OFFSET, gpio, true);
iproc_gpio_set_bit(plat, DATA_OUT_OFFSET, gpio, value);
static int iproc_gpio_get_value(struct udevice *dev, u32 gpio)
{
- struct iproc_gpio_platdata *plat = dev_get_platdata(dev);
+ struct iproc_gpio_plat *plat = dev_get_plat(dev);
int value;
value = iproc_gpio_get_bit(plat, DATA_IN_OFFSET, gpio);
static int iproc_gpio_set_value(struct udevice *dev, u32 gpio, int value)
{
- struct iproc_gpio_platdata *plat = dev_get_platdata(dev);
+ struct iproc_gpio_plat *plat = dev_get_plat(dev);
if (iproc_gpio_get_bit(plat, OUT_EN_OFFSET, gpio))
iproc_gpio_set_bit(plat, DATA_OUT_OFFSET, gpio, value);
static int iproc_gpio_get_function(struct udevice *dev, u32 gpio)
{
- struct iproc_gpio_platdata *plat = dev_get_platdata(dev);
+ struct iproc_gpio_plat *plat = dev_get_plat(dev);
if (iproc_gpio_get_bit(plat, OUT_EN_OFFSET, gpio))
return GPIOF_OUTPUT;
return GPIOF_INPUT;
}
-static int iproc_gpio_ofdata_to_platdata(struct udevice *dev)
+static int iproc_gpio_of_to_plat(struct udevice *dev)
{
- struct iproc_gpio_platdata *plat = dev_get_platdata(dev);
+ struct iproc_gpio_plat *plat = dev_get_plat(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
int ret;
char name[10];
.id = UCLASS_GPIO,
.of_match = iproc_gpio_ids,
.ops = &iproc_gpio_ops,
- .ofdata_to_platdata = iproc_gpio_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct iproc_gpio_platdata),
+ .of_to_plat = iproc_gpio_of_to_plat,
+ .plat_auto = sizeof(struct iproc_gpio_plat),
};
.id = UCLASS_GPIO,
.ops = &gpio_lpc32xx_ops,
.probe = lpc32xx_gpio_probe,
- .priv_auto_alloc_size = sizeof(struct lpc32xx_gpio_priv),
+ .priv_auto = sizeof(struct lpc32xx_gpio_priv),
};
}
#if CONFIG_IS_ENABLED(OF_CONTROL)
-static int mpc83xx_spisel_boot_ofdata_to_platdata(struct udevice *dev)
+static int mpc83xx_spisel_boot_of_to_plat(struct udevice *dev)
{
- struct mpc8xxx_gpio_plat *plat = dev_get_platdata(dev);
+ struct mpc8xxx_gpio_plat *plat = dev_get_plat(dev);
fdt_addr_t addr;
u32 reg[2];
}
#endif
-static int mpc83xx_spisel_boot_platdata_to_priv(struct udevice *dev)
+static int mpc83xx_spisel_boot_plat_to_priv(struct udevice *dev)
{
struct mpc83xx_spisel_boot *priv = dev_get_priv(dev);
- struct mpc8xxx_gpio_plat *plat = dev_get_platdata(dev);
+ struct mpc8xxx_gpio_plat *plat = dev_get_plat(dev);
unsigned long size = plat->size;
ulong driver_data = dev_get_driver_data(dev);
struct mpc83xx_spisel_boot *data = dev_get_priv(dev);
char name[32], *str;
- mpc83xx_spisel_boot_platdata_to_priv(dev);
+ mpc83xx_spisel_boot_plat_to_priv(dev);
snprintf(name, sizeof(name), "MPC@%lx_", data->addr);
str = strdup(name);
.id = UCLASS_GPIO,
.ops = &mpc83xx_spisel_boot_ops,
#if CONFIG_IS_ENABLED(OF_CONTROL)
- .ofdata_to_platdata = mpc83xx_spisel_boot_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct mpc8xxx_gpio_plat),
+ .of_to_plat = mpc83xx_spisel_boot_of_to_plat,
+ .plat_auto = sizeof(struct mpc8xxx_gpio_plat),
.of_match = mpc83xx_spisel_boot_ids,
#endif
.probe = mpc83xx_spisel_boot_probe,
- .priv_auto_alloc_size = sizeof(struct mpc83xx_spisel_boot),
+ .priv_auto = sizeof(struct mpc83xx_spisel_boot),
};
}
#if CONFIG_IS_ENABLED(OF_CONTROL)
-static int mpc8xxx_gpio_ofdata_to_platdata(struct udevice *dev)
+static int mpc8xxx_gpio_of_to_plat(struct udevice *dev)
{
- struct mpc8xxx_gpio_plat *plat = dev_get_platdata(dev);
+ struct mpc8xxx_gpio_plat *plat = dev_get_plat(dev);
struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
fdt_addr_t addr;
u32 i;
}
#endif
-static int mpc8xxx_gpio_platdata_to_priv(struct udevice *dev)
+static int mpc8xxx_gpio_plat_to_priv(struct udevice *dev)
{
struct mpc8xxx_gpio_data *priv = dev_get_priv(dev);
- struct mpc8xxx_gpio_plat *plat = dev_get_platdata(dev);
+ struct mpc8xxx_gpio_plat *plat = dev_get_plat(dev);
unsigned long size = plat->size;
ulong driver_data = dev_get_driver_data(dev);
struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
char name[32], *str;
- mpc8xxx_gpio_platdata_to_priv(dev);
+ mpc8xxx_gpio_plat_to_priv(dev);
snprintf(name, sizeof(name), "MPC@%lx_", data->addr);
str = strdup(name);
.id = UCLASS_GPIO,
.ops = &gpio_mpc8xxx_ops,
#if CONFIG_IS_ENABLED(OF_CONTROL)
- .ofdata_to_platdata = mpc8xxx_gpio_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct mpc8xxx_gpio_plat),
+ .of_to_plat = mpc8xxx_gpio_of_to_plat,
+ .plat_auto = sizeof(struct mpc8xxx_gpio_plat),
.of_match = mpc8xxx_gpio_ids,
#endif
.probe = mpc8xxx_gpio_probe,
- .priv_auto_alloc_size = sizeof(struct mpc8xxx_gpio_data),
+ .priv_auto = sizeof(struct mpc8xxx_gpio_data),
};
.of_match = mscc_sgpio_ids,
.ops = &mscc_sgpio_ops,
.probe = mscc_sgpio_probe,
- .priv_auto_alloc_size = sizeof(struct mscc_sgpio_priv),
+ .priv_auto = sizeof(struct mscc_sgpio_priv),
};
return priv->base == FDT_ADDR_T_NONE ? -EINVAL : 0;
}
-static int msm_gpio_ofdata_to_platdata(struct udevice *dev)
+static int msm_gpio_of_to_plat(struct udevice *dev)
{
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
.name = "gpio_msm",
.id = UCLASS_GPIO,
.of_match = msm_gpio_ids,
- .ofdata_to_platdata = msm_gpio_ofdata_to_platdata,
+ .of_to_plat = msm_gpio_of_to_plat,
.probe = msm_gpio_probe,
.ops = &gpio_msm_ops,
- .priv_auto_alloc_size = sizeof(struct msm_gpio_bank),
+ .priv_auto = sizeof(struct msm_gpio_bank),
};
static void __iomem *mediatek_gpio_membase;
-struct mediatek_gpio_platdata {
+struct mediatek_gpio_plat {
char bank_name[3]; /* Name of bank, e.g. "PA", "PB" etc */
int gpio_count;
int bank;
};
-static u32 reg_offs(struct mediatek_gpio_platdata *plat, int reg)
+static u32 reg_offs(struct mediatek_gpio_plat *plat, int reg)
{
return (reg * 0x10) + (plat->bank * 0x4);
}
static int mediatek_gpio_get_value(struct udevice *dev, unsigned int offset)
{
- struct mediatek_gpio_platdata *plat = dev_get_platdata(dev);
+ struct mediatek_gpio_plat *plat = dev_get_plat(dev);
return !!(ioread32(mediatek_gpio_membase +
reg_offs(plat, GPIO_REG_DATA)) & BIT(offset));
static int mediatek_gpio_set_value(struct udevice *dev, unsigned int offset,
int value)
{
- struct mediatek_gpio_platdata *plat = dev_get_platdata(dev);
+ struct mediatek_gpio_plat *plat = dev_get_plat(dev);
iowrite32(BIT(offset), mediatek_gpio_membase +
reg_offs(plat, value ? GPIO_REG_DSET : GPIO_REG_DCLR));
static int mediatek_gpio_direction_input(struct udevice *dev, unsigned int offset)
{
- struct mediatek_gpio_platdata *plat = dev_get_platdata(dev);
+ struct mediatek_gpio_plat *plat = dev_get_plat(dev);
clrbits_le32(mediatek_gpio_membase + reg_offs(plat, GPIO_REG_CTRL),
BIT(offset));
static int mediatek_gpio_direction_output(struct udevice *dev, unsigned int offset,
int value)
{
- struct mediatek_gpio_platdata *plat = dev_get_platdata(dev);
+ struct mediatek_gpio_plat *plat = dev_get_plat(dev);
setbits_le32(mediatek_gpio_membase + reg_offs(plat, GPIO_REG_CTRL),
BIT(offset));
static int mediatek_gpio_get_function(struct udevice *dev, unsigned int offset)
{
- struct mediatek_gpio_platdata *plat = dev_get_platdata(dev);
+ struct mediatek_gpio_plat *plat = dev_get_plat(dev);
u32 t;
t = ioread32(mediatek_gpio_membase + reg_offs(plat, GPIO_REG_CTRL));
static int gpio_mediatek_probe(struct udevice *dev)
{
- struct mediatek_gpio_platdata *plat = dev_get_platdata(dev);
+ struct mediatek_gpio_plat *plat = dev_get_plat(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
/* Tell the uclass how many GPIOs we have */
*/
static int gpio_mediatek_bind(struct udevice *parent)
{
- struct mediatek_gpio_platdata *plat = parent->platdata;
+ struct mediatek_gpio_plat *plat = parent->plat;
ofnode node;
int bank = 0;
int ret;
for (node = dev_read_first_subnode(parent); ofnode_valid(node);
node = dev_read_next_subnode(node)) {
- struct mediatek_gpio_platdata *plat;
+ struct mediatek_gpio_plat *plat;
struct udevice *dev;
plat = calloc(1, sizeof(*plat));
plat->gpio_count = MTK_BANK_WIDTH;
plat->bank = bank;
- ret = device_bind(parent, parent->driver,
- plat->bank_name, plat, -1, &dev);
+ ret = device_bind(parent, parent->driver, plat->bank_name, plat,
+ node, &dev);
if (ret)
return ret;
- dev->node = node;
bank++;
}
.of_match = mvebu_gpio_ids,
.ops = &mvebu_gpio_ops,
.probe = mvebu_gpio_probe,
- .priv_auto_alloc_size = sizeof(struct mvebu_gpio_priv),
+ .priv_auto = sizeof(struct mvebu_gpio_priv),
};
static int mxc_gpio_probe(struct udevice *dev)
{
struct mxc_bank_info *bank = dev_get_priv(dev);
- struct mxc_gpio_plat *plat = dev_get_platdata(dev);
+ struct mxc_gpio_plat *plat = dev_get_plat(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
int banknum;
char name[18], *str;
return 0;
}
-static int mxc_gpio_ofdata_to_platdata(struct udevice *dev)
+static int mxc_gpio_of_to_plat(struct udevice *dev)
{
- struct mxc_gpio_plat *plat = dev_get_platdata(dev);
+ struct mxc_gpio_plat *plat = dev_get_plat(dev);
if (!CONFIG_IS_ENABLED(OF_PLATDATA)) {
fdt_addr_t addr;
addr = dev_read_addr(dev);
.id = UCLASS_GPIO,
.ops = &gpio_mxc_ops,
.probe = mxc_gpio_probe,
- .ofdata_to_platdata = mxc_gpio_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct mxc_gpio_plat),
- .priv_auto_alloc_size = sizeof(struct mxc_bank_info),
+ .of_to_plat = mxc_gpio_of_to_plat,
+ .plat_auto = sizeof(struct mxc_gpio_plat),
+ .priv_auto = sizeof(struct mxc_bank_info),
.of_match = mxc_gpio_ids,
.bind = mxc_gpio_bind,
};
* Bank 4: 0-20 -> 21 PINS
*/
-struct mxs_gpio_platdata {
+struct mxs_gpio_plat {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct dtd_fsl_imx23_gpio dtplat;
#endif
static int mxs_gpio_probe(struct udevice *dev)
{
- struct mxs_gpio_platdata *plat = dev_get_platdata(dev);
+ struct mxs_gpio_plat *plat = dev_get_plat(dev);
struct mxs_gpio_priv *priv = dev_get_priv(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
char name[16], *str;
}
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
-static int mxs_ofdata_to_platdata(struct udevice *dev)
+static int mxs_of_to_plat(struct udevice *dev)
{
- struct mxs_gpio_platdata *plat = dev->platdata;
+ struct mxs_gpio_plat *plat = dev->plat;
struct fdtdec_phandle_args args;
int node = dev_of_offset(dev);
int ret;
.id = UCLASS_GPIO,
.ops = &gpio_mxs_ops,
.probe = mxs_gpio_probe,
- .priv_auto_alloc_size = sizeof(struct mxs_gpio_priv),
- .platdata_auto_alloc_size = sizeof(struct mxs_gpio_platdata),
+ .priv_auto = sizeof(struct mxs_gpio_priv),
+ .plat_auto = sizeof(struct mxs_gpio_plat),
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
.of_match = mxs_gpio_ids,
- .ofdata_to_platdata = mxs_ofdata_to_platdata,
+ .of_to_plat = mxs_of_to_plat,
#endif
};
u32 pad; /* Alive GPIO Input Value Register */
};
-struct nx_gpio_platdata {
+struct nx_gpio_plat {
void *regs;
int gpio_count;
const char *bank_name;
static int nx_alive_gpio_is_check(struct udevice *dev)
{
- struct nx_gpio_platdata *plat = dev_get_platdata(dev);
+ struct nx_gpio_plat *plat = dev_get_plat(dev);
const char *bank_name = plat->bank_name;
if (!strcmp(bank_name, "gpio_alv"))
static int nx_alive_gpio_direction_input(struct udevice *dev, unsigned int pin)
{
- struct nx_gpio_platdata *plat = dev_get_platdata(dev);
+ struct nx_gpio_plat *plat = dev_get_plat(dev);
struct nx_alive_gpio_regs *const regs = plat->regs;
setbits_le32(®s->outputenb_reset, 1 << pin);
static int nx_alive_gpio_direction_output(struct udevice *dev, unsigned int pin,
int val)
{
- struct nx_gpio_platdata *plat = dev_get_platdata(dev);
+ struct nx_gpio_plat *plat = dev_get_plat(dev);
struct nx_alive_gpio_regs *const regs = plat->regs;
if (val)
static int nx_alive_gpio_get_value(struct udevice *dev, unsigned int pin)
{
- struct nx_gpio_platdata *plat = dev_get_platdata(dev);
+ struct nx_gpio_plat *plat = dev_get_plat(dev);
struct nx_alive_gpio_regs *const regs = plat->regs;
unsigned int mask = 1UL << pin;
unsigned int value;
static int nx_alive_gpio_set_value(struct udevice *dev, unsigned int pin,
int val)
{
- struct nx_gpio_platdata *plat = dev_get_platdata(dev);
+ struct nx_gpio_plat *plat = dev_get_plat(dev);
struct nx_alive_gpio_regs *const regs = plat->regs;
if (val)
static int nx_alive_gpio_get_function(struct udevice *dev, unsigned int pin)
{
- struct nx_gpio_platdata *plat = dev_get_platdata(dev);
+ struct nx_gpio_plat *plat = dev_get_plat(dev);
struct nx_alive_gpio_regs *const regs = plat->regs;
unsigned int mask = (1UL << pin);
unsigned int output;
static int nx_gpio_direction_input(struct udevice *dev, unsigned int pin)
{
- struct nx_gpio_platdata *plat = dev_get_platdata(dev);
+ struct nx_gpio_plat *plat = dev_get_plat(dev);
struct nx_gpio_regs *const regs = plat->regs;
if (nx_alive_gpio_is_check(dev))
static int nx_gpio_direction_output(struct udevice *dev, unsigned int pin,
int val)
{
- struct nx_gpio_platdata *plat = dev_get_platdata(dev);
+ struct nx_gpio_plat *plat = dev_get_plat(dev);
struct nx_gpio_regs *const regs = plat->regs;
if (nx_alive_gpio_is_check(dev))
static int nx_gpio_get_value(struct udevice *dev, unsigned int pin)
{
- struct nx_gpio_platdata *plat = dev_get_platdata(dev);
+ struct nx_gpio_plat *plat = dev_get_plat(dev);
struct nx_gpio_regs *const regs = plat->regs;
unsigned int mask = 1UL << pin;
unsigned int value;
static int nx_gpio_set_value(struct udevice *dev, unsigned int pin, int val)
{
- struct nx_gpio_platdata *plat = dev_get_platdata(dev);
+ struct nx_gpio_plat *plat = dev_get_plat(dev);
struct nx_gpio_regs *const regs = plat->regs;
if (nx_alive_gpio_is_check(dev))
static int nx_gpio_get_function(struct udevice *dev, unsigned int pin)
{
- struct nx_gpio_platdata *plat = dev_get_platdata(dev);
+ struct nx_gpio_plat *plat = dev_get_plat(dev);
struct nx_gpio_regs *const regs = plat->regs;
unsigned int mask = (1UL << pin);
unsigned int output;
static int nx_gpio_probe(struct udevice *dev)
{
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
- struct nx_gpio_platdata *plat = dev_get_platdata(dev);
+ struct nx_gpio_plat *plat = dev_get_plat(dev);
uc_priv->gpio_count = plat->gpio_count;
uc_priv->bank_name = plat->bank_name;
return 0;
}
-static int nx_gpio_ofdata_to_platdata(struct udevice *dev)
+static int nx_gpio_of_to_plat(struct udevice *dev)
{
- struct nx_gpio_platdata *plat = dev_get_platdata(dev);
+ struct nx_gpio_plat *plat = dev_get_plat(dev);
plat->regs = map_physmem(devfdt_get_addr(dev),
sizeof(struct nx_gpio_regs),
.id = UCLASS_GPIO,
.of_match = nx_gpio_ids,
.ops = &nx_gpio_ops,
- .ofdata_to_platdata = nx_gpio_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct nx_gpio_platdata),
+ .of_to_plat = nx_gpio_of_to_plat,
+ .plat_auto = sizeof(struct nx_gpio_plat),
.probe = nx_gpio_probe,
};
.id = UCLASS_GPIO,
.of_match = of_match_ptr(octeon_gpio_ids),
.probe = octeon_gpio_probe,
- .priv_auto_alloc_size = sizeof(struct octeon_gpio),
+ .priv_auto = sizeof(struct octeon_gpio),
.ops = &octeon_gpio_ops,
.flags = DM_FLAG_PRE_RELOC,
};
static int omap_gpio_probe(struct udevice *dev)
{
struct gpio_bank *bank = dev_get_priv(dev);
- struct omap_gpio_platdata *plat = dev_get_platdata(dev);
+ struct omap_gpio_plat *plat = dev_get_plat(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
char name[18], *str;
#if !CONFIG_IS_ENABLED(OF_CONTROL)
static int omap_gpio_bind(struct udevice *dev)
{
- struct omap_gpio_platdata *plat = dev_get_platdata(dev);
+ struct omap_gpio_plat *plat = dev_get_plat(dev);
fdt_addr_t base_addr;
if (plat)
* TODO:
* When every board is converted to driver model and DT is
* supported, this can be done by auto-alloc feature, but
- * not using calloc to alloc memory for platdata.
+ * not using calloc to alloc memory for plat.
*
* For example am33xx_gpio uses platform data rather than device tree.
*
plat->base = base_addr;
plat->port_name = fdt_get_name(gd->fdt_blob, dev_of_offset(dev), NULL);
- dev->platdata = plat;
+ dev->plat = plat;
return 0;
}
{ }
};
-static int omap_gpio_ofdata_to_platdata(struct udevice *dev)
+static int omap_gpio_of_to_plat(struct udevice *dev)
{
- struct omap_gpio_platdata *plat = dev_get_platdata(dev);
+ struct omap_gpio_plat *plat = dev_get_plat(dev);
fdt_addr_t addr;
addr = dev_read_addr(dev);
#if CONFIG_IS_ENABLED(OF_CONTROL)
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
.of_match = omap_gpio_ids,
- .ofdata_to_platdata = of_match_ptr(omap_gpio_ofdata_to_platdata),
- .platdata_auto_alloc_size = sizeof(struct omap_gpio_platdata),
+ .of_to_plat = of_match_ptr(omap_gpio_of_to_plat),
+ .plat_auto = sizeof(struct omap_gpio_plat),
#endif
#else
.bind = omap_gpio_bind,
#endif
.ops = &gpio_omap_ops,
.probe = omap_gpio_probe,
- .priv_auto_alloc_size = sizeof(struct gpio_bank),
+ .priv_auto = sizeof(struct gpio_bank),
#if !CONFIG_IS_ENABLED(OF_CONTROL)
.flags = DM_FLAG_PRE_RELOC,
#endif
static int pca953x_write_single(struct udevice *dev, int reg, u8 val,
int offset)
{
- struct pca953x_info *info = dev_get_platdata(dev);
+ struct pca953x_info *info = dev_get_plat(dev);
int bank_shift = fls((info->gpio_count - 1) / BANK_SZ);
int off = offset / BANK_SZ;
int ret = 0;
static int pca953x_read_single(struct udevice *dev, int reg, u8 *val,
int offset)
{
- struct pca953x_info *info = dev_get_platdata(dev);
+ struct pca953x_info *info = dev_get_plat(dev);
int bank_shift = fls((info->gpio_count - 1) / BANK_SZ);
int off = offset / BANK_SZ;
int ret;
static int pca953x_read_regs(struct udevice *dev, int reg, u8 *val)
{
- struct pca953x_info *info = dev_get_platdata(dev);
+ struct pca953x_info *info = dev_get_plat(dev);
int ret = 0;
if (info->gpio_count <= 8) {
static int pca953x_write_regs(struct udevice *dev, int reg, u8 *val)
{
- struct pca953x_info *info = dev_get_platdata(dev);
+ struct pca953x_info *info = dev_get_plat(dev);
int ret = 0;
if (info->gpio_count <= 8) {
static int pca953x_is_output(struct udevice *dev, int offset)
{
- struct pca953x_info *info = dev_get_platdata(dev);
+ struct pca953x_info *info = dev_get_plat(dev);
int bank = offset / BANK_SZ;
int off = offset % BANK_SZ;
static int pca953x_set_value(struct udevice *dev, uint offset, int value)
{
- struct pca953x_info *info = dev_get_platdata(dev);
+ struct pca953x_info *info = dev_get_plat(dev);
int bank = offset / BANK_SZ;
int off = offset % BANK_SZ;
u8 val;
static int pca953x_set_direction(struct udevice *dev, uint offset, int dir)
{
- struct pca953x_info *info = dev_get_platdata(dev);
+ struct pca953x_info *info = dev_get_plat(dev);
int bank = offset / BANK_SZ;
int off = offset % BANK_SZ;
u8 val;
static int pca953x_probe(struct udevice *dev)
{
- struct pca953x_info *info = dev_get_platdata(dev);
+ struct pca953x_info *info = dev_get_plat(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
char name[32], label[8], *str;
int addr;
.id = UCLASS_GPIO,
.ops = &pca953x_ops,
.probe = pca953x_probe,
- .platdata_auto_alloc_size = sizeof(struct pca953x_info),
+ .plat_auto = sizeof(struct pca953x_info),
.of_match = pca953x_ids,
};
static int pcf8575_i2c_write_le16(struct udevice *dev, unsigned int word)
{
- struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
+ struct dm_i2c_chip *chip = dev_get_parent_plat(dev);
u8 buf[2] = { word & 0xff, word >> 8, };
int ret;
static int pcf8575_i2c_read_le16(struct udevice *dev)
{
- struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
+ struct dm_i2c_chip *chip = dev_get_parent_plat(dev);
u8 buf[2];
int ret;
static int pcf8575_direction_input(struct udevice *dev, unsigned offset)
{
- struct pcf8575_chip *plat = dev_get_platdata(dev);
+ struct pcf8575_chip *plat = dev_get_plat(dev);
int status;
plat->out |= BIT(offset);
static int pcf8575_direction_output(struct udevice *dev,
unsigned int offset, int value)
{
- struct pcf8575_chip *plat = dev_get_platdata(dev);
+ struct pcf8575_chip *plat = dev_get_plat(dev);
int ret;
if (value)
return pcf8575_direction_output(dev, offset, value);
}
-static int pcf8575_ofdata_platdata(struct udevice *dev)
+static int pcf8575_ofdata_plat(struct udevice *dev)
{
- struct pcf8575_chip *plat = dev_get_platdata(dev);
+ struct pcf8575_chip *plat = dev_get_plat(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
int n_latch;
.id = UCLASS_GPIO,
.ops = &pcf8575_gpio_ops,
.of_match = pcf8575_gpio_ids,
- .ofdata_to_platdata = pcf8575_ofdata_platdata,
+ .of_to_plat = pcf8575_ofdata_plat,
.probe = pcf8575_gpio_probe,
- .platdata_auto_alloc_size = sizeof(struct pcf8575_chip),
+ .plat_auto = sizeof(struct pcf8575_chip),
};
.of_match = pic32_gpio_ids,
.ops = &gpio_pic32_ops,
.probe = pic32_gpio_probe,
- .priv_auto_alloc_size = sizeof(struct pic32_gpio_priv),
+ .priv_auto = sizeof(struct pic32_gpio_priv),
};
return 0;
}
-static int pm8916_gpio_ofdata_to_platdata(struct udevice *dev)
+static int pm8916_gpio_of_to_plat(struct udevice *dev)
{
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
.name = "gpio_pm8916",
.id = UCLASS_GPIO,
.of_match = pm8916_gpio_ids,
- .ofdata_to_platdata = pm8916_gpio_ofdata_to_platdata,
+ .of_to_plat = pm8916_gpio_of_to_plat,
.probe = pm8916_gpio_probe,
.ops = &pm8916_gpio_ops,
- .priv_auto_alloc_size = sizeof(struct pm8916_gpio_bank),
+ .priv_auto = sizeof(struct pm8916_gpio_bank),
};
return 0;
}
-static int pm8941_pwrkey_ofdata_to_platdata(struct udevice *dev)
+static int pm8941_pwrkey_of_to_plat(struct udevice *dev)
{
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
.name = "pwrkey_pm8916",
.id = UCLASS_GPIO,
.of_match = pm8941_pwrkey_ids,
- .ofdata_to_platdata = pm8941_pwrkey_ofdata_to_platdata,
+ .of_to_plat = pm8941_pwrkey_of_to_plat,
.probe = pm8941_pwrkey_probe,
.ops = &pm8941_pwrkey_ops,
- .priv_auto_alloc_size = sizeof(struct pm8916_gpio_bank),
+ .priv_auto = sizeof(struct pm8916_gpio_bank),
};
.id = UCLASS_GPIO,
.of_match = rockchip_gpio_ids,
.ops = &gpio_rockchip_ops,
- .priv_auto_alloc_size = sizeof(struct rockchip_gpio_priv),
+ .priv_auto = sizeof(struct rockchip_gpio_priv),
.probe = rockchip_gpio_probe,
};
#define RATE_SET(gpio) (0x1 << (gpio + 16))
/* Platform data for each bank */
-struct exynos_gpio_platdata {
+struct exynos_gpio_plat {
struct s5p_gpio_bank *bank;
const char *bank_name; /* Name of port, e.g. 'gpa0" */
};
{
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct exynos_bank_info *priv = dev->priv;
- struct exynos_gpio_platdata *plat = dev->platdata;
+ struct exynos_gpio_plat *plat = dev->plat;
/* Only child devices have ports */
if (!plat)
*/
static int gpio_exynos_bind(struct udevice *parent)
{
- struct exynos_gpio_platdata *plat = parent->platdata;
+ struct exynos_gpio_plat *plat = parent->plat;
struct s5p_gpio_bank *bank, *base;
const void *blob = gd->fdt_blob;
int node;
for (node = fdt_first_subnode(blob, dev_of_offset(parent)), bank = base;
node > 0;
node = fdt_next_subnode(blob, node), bank++) {
- struct exynos_gpio_platdata *plat;
+ struct exynos_gpio_plat *plat;
struct udevice *dev;
fdt_addr_t reg;
int ret;
return -ENOMEM;
plat->bank_name = fdt_get_name(blob, node, NULL);
- ret = device_bind(parent, parent->driver,
- plat->bank_name, plat, -1, &dev);
+ ret = device_bind(parent, parent->driver, plat->bank_name, plat,
+ offset_to_ofnode(node), &dev);
if (ret)
return ret;
- dev_set_of_offset(dev, node);
-
reg = dev_read_addr(dev);
if (reg != FDT_ADDR_T_NONE)
bank = (struct s5p_gpio_bank *)((ulong)base + reg);
.of_match = exynos_gpio_ids,
.bind = gpio_exynos_bind,
.probe = gpio_exynos_probe,
- .priv_auto_alloc_size = sizeof(struct exynos_bank_info),
+ .priv_auto = sizeof(struct exynos_bank_info),
.ops = &gpio_exynos_ops,
};
#endif
#endif
};
-static int sandbox_gpio_ofdata_to_platdata(struct udevice *dev)
+static int sandbox_gpio_of_to_plat(struct udevice *dev)
{
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
.name = "sandbox_gpio",
.id = UCLASS_GPIO,
.of_match = sandbox_gpio_ids,
- .ofdata_to_platdata = sandbox_gpio_ofdata_to_platdata,
+ .of_to_plat = sandbox_gpio_of_to_plat,
.probe = gpio_sandbox_probe,
.remove = gpio_sandbox_remove,
.ops = &gpio_sandbox_ops,
.ops = &sandbox_pinctrl_gpio_ops,
.bind = dm_scan_fdt_dev,
.probe = sandbox_pinctrl_probe,
- .priv_auto_alloc_size = sizeof(struct sb_pinctrl_priv),
+ .priv_auto = sizeof(struct sb_pinctrl_priv),
ACPI_OPS_PTR(&pinctrl_sandbox_acpi_ops)
};
static int sifive_gpio_probe(struct udevice *dev)
{
- struct sifive_gpio_platdata *plat = dev_get_platdata(dev);
+ struct sifive_gpio_plat *plat = dev_get_plat(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
char name[18], *str;
static int sifive_gpio_direction_input(struct udevice *dev, u32 offset)
{
- struct sifive_gpio_platdata *plat = dev_get_platdata(dev);
+ struct sifive_gpio_plat *plat = dev_get_plat(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
if (offset > uc_priv->gpio_count)
static int sifive_gpio_direction_output(struct udevice *dev, u32 offset,
int value)
{
- struct sifive_gpio_platdata *plat = dev_get_platdata(dev);
+ struct sifive_gpio_plat *plat = dev_get_plat(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
if (offset > uc_priv->gpio_count)
static int sifive_gpio_get_value(struct udevice *dev, u32 offset)
{
- struct sifive_gpio_platdata *plat = dev_get_platdata(dev);
+ struct sifive_gpio_plat *plat = dev_get_plat(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
int val;
int dir;
static int sifive_gpio_set_value(struct udevice *dev, u32 offset, int value)
{
- struct sifive_gpio_platdata *plat = dev_get_platdata(dev);
+ struct sifive_gpio_plat *plat = dev_get_plat(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
if (offset > uc_priv->gpio_count)
static int sifive_gpio_get_function(struct udevice *dev, unsigned int offset)
{
- struct sifive_gpio_platdata *plat = dev_get_platdata(dev);
+ struct sifive_gpio_plat *plat = dev_get_plat(dev);
u32 outdir, indir, val;
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
.get_function = sifive_gpio_get_function,
};
-static int sifive_gpio_ofdata_to_platdata(struct udevice *dev)
+static int sifive_gpio_of_to_plat(struct udevice *dev)
{
- struct sifive_gpio_platdata *plat = dev_get_platdata(dev);
+ struct sifive_gpio_plat *plat = dev_get_plat(dev);
fdt_addr_t addr;
addr = dev_read_addr(dev);
.name = "gpio_sifive",
.id = UCLASS_GPIO,
.of_match = sifive_gpio_match,
- .ofdata_to_platdata = of_match_ptr(sifive_gpio_ofdata_to_platdata),
- .platdata_auto_alloc_size = sizeof(struct sifive_gpio_platdata),
+ .of_to_plat = of_match_ptr(sifive_gpio_of_to_plat),
+ .plat_auto = sizeof(struct sifive_gpio_plat),
.ops = &sifive_gpio_ops,
.probe = sifive_gpio_probe,
};
.probe = gpio_stm32_probe,
.ops = &gpio_stm32_ops,
.flags = DM_UC_FLAG_SEQ_ALIAS,
- .priv_auto_alloc_size = sizeof(struct stm32_gpio_priv),
+ .priv_auto = sizeof(struct stm32_gpio_priv),
};
#define SUNXI_GPIOS_PER_BANK SUNXI_GPIO_A_NR
-struct sunxi_gpio_platdata {
+struct sunxi_gpio_plat {
struct sunxi_gpio *regs;
const char *bank_name; /* Name of bank, e.g. "B" */
int gpio_count;
static int sunxi_gpio_direction_input(struct udevice *dev, unsigned offset)
{
- struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
+ struct sunxi_gpio_plat *plat = dev_get_plat(dev);
sunxi_gpio_set_cfgbank(plat->regs, offset, SUNXI_GPIO_INPUT);
static int sunxi_gpio_direction_output(struct udevice *dev, unsigned offset,
int value)
{
- struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
+ struct sunxi_gpio_plat *plat = dev_get_plat(dev);
u32 num = GPIO_NUM(offset);
sunxi_gpio_set_cfgbank(plat->regs, offset, SUNXI_GPIO_OUTPUT);
static int sunxi_gpio_get_value(struct udevice *dev, unsigned offset)
{
- struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
+ struct sunxi_gpio_plat *plat = dev_get_plat(dev);
u32 num = GPIO_NUM(offset);
unsigned dat;
static int sunxi_gpio_set_value(struct udevice *dev, unsigned offset,
int value)
{
- struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
+ struct sunxi_gpio_plat *plat = dev_get_plat(dev);
u32 num = GPIO_NUM(offset);
clrsetbits_le32(&plat->regs->dat, 1 << num, value ? (1 << num) : 0);
static int sunxi_gpio_get_function(struct udevice *dev, unsigned offset)
{
- struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
+ struct sunxi_gpio_plat *plat = dev_get_plat(dev);
int func;
func = sunxi_gpio_get_cfgbank(plat->regs, offset);
static int gpio_sunxi_probe(struct udevice *dev)
{
- struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
+ struct sunxi_gpio_plat *plat = dev_get_plat(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
/* Tell the uclass how many GPIOs we have */
{
struct sunxi_gpio_soc_data *soc_data =
(struct sunxi_gpio_soc_data *)dev_get_driver_data(parent);
- struct sunxi_gpio_platdata *plat = parent->platdata;
+ struct sunxi_gpio_plat *plat = parent->plat;
struct sunxi_gpio_reg *ctlr;
int bank, ret;
ctlr = dev_read_addr_ptr(parent);
for (bank = 0; bank < soc_data->no_banks; bank++) {
- struct sunxi_gpio_platdata *plat;
+ struct sunxi_gpio_plat *plat;
struct udevice *dev;
plat = calloc(1, sizeof(*plat));
plat->bank_name = gpio_bank_name(soc_data->start + bank);
plat->gpio_count = SUNXI_GPIOS_PER_BANK;
- ret = device_bind(parent, parent->driver,
- plat->bank_name, plat, -1, &dev);
+ ret = device_bind(parent, parent->driver, plat->bank_name, plat,
+ dev_ofnode(parent), &dev);
if (ret)
return ret;
- dev_set_of_offset(dev, dev_of_offset(parent));
}
return 0;
uint32_t port_count;
};
-struct tegra186_gpio_platdata {
+struct tegra186_gpio_plat {
const char *name;
uint32_t *regs;
};
static uint32_t *tegra186_gpio_reg(struct udevice *dev, uint32_t reg,
uint32_t gpio)
{
- struct tegra186_gpio_platdata *plat = dev->platdata;
+ struct tegra186_gpio_plat *plat = dev->plat;
uint32_t index = (reg + (gpio * TEGRA186_GPIO_PER_GPIO_STRIDE)) / 4;
return &(plat->regs[index]);
*/
static int tegra186_gpio_bind(struct udevice *parent)
{
- struct tegra186_gpio_platdata *parent_plat = parent->platdata;
+ struct tegra186_gpio_plat *parent_plat = parent->plat;
struct tegra186_gpio_ctlr_data *ctlr_data =
(struct tegra186_gpio_ctlr_data *)dev_get_driver_data(parent);
uint32_t *regs;
return -EINVAL;
for (port = 0; port < ctlr_data->port_count; port++) {
- struct tegra186_gpio_platdata *plat;
+ struct tegra186_gpio_plat *plat;
struct udevice *dev;
plat = calloc(1, sizeof(*plat));
plat->regs = &(regs[ctlr_data->ports[port].offset / 4]);
ret = device_bind(parent, parent->driver, plat->name, plat,
- -1, &dev);
+ dev_ofnode(parent), &dev);
if (ret)
return ret;
- dev_set_of_offset(dev, dev_of_offset(parent));
}
return 0;
static int tegra186_gpio_probe(struct udevice *dev)
{
- struct tegra186_gpio_platdata *plat = dev->platdata;
+ struct tegra186_gpio_plat *plat = dev->plat;
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
/* Only child devices have ports */
static const int DIRECTION_INPUT = 0;
static const int DIRECTION_OUTPUT = 1;
-struct tegra_gpio_platdata {
+struct tegra_gpio_plat {
struct gpio_ctlr_bank *bank;
const char *port_name; /* Name of port, e.g. "B" */
int base_gpio; /* Port number for this port (0, 1,.., n-1) */
{
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct tegra_port_info *priv = dev->priv;
- struct tegra_gpio_platdata *plat = dev->platdata;
+ struct tegra_gpio_plat *plat = dev->plat;
/* Only child devices have ports */
if (!plat)
*/
static int gpio_tegra_bind(struct udevice *parent)
{
- struct tegra_gpio_platdata *plat = parent->platdata;
+ struct tegra_gpio_plat *plat = parent->plat;
struct gpio_ctlr *ctlr;
int bank_count;
int bank;
int port;
for (port = 0; port < TEGRA_PORTS_PER_BANK; port++) {
- struct tegra_gpio_platdata *plat;
+ struct tegra_gpio_plat *plat;
struct udevice *dev;
int base_port;
plat->port_name = gpio_port_name(base_port);
ret = device_bind(parent, parent->driver,
- plat->port_name, plat, -1, &dev);
+ plat->port_name, plat,
+ dev_ofnode(parent), &dev);
if (ret)
return ret;
- dev_set_of_offset(dev, dev_of_offset(parent));
}
}
.of_match = tegra_gpio_ids,
.bind = gpio_tegra_bind,
.probe = gpio_tegra_probe,
- .priv_auto_alloc_size = sizeof(struct tegra_port_info),
+ .priv_auto = sizeof(struct tegra_port_info),
.ops = &gpio_tegra_ops,
};
static int vybrid_gpio_probe(struct udevice *dev)
{
struct vybrid_gpios *gpios = dev_get_priv(dev);
- struct vybrid_gpio_platdata *plat = dev_get_platdata(dev);
+ struct vybrid_gpio_plat *plat = dev_get_plat(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
uc_priv->bank_name = plat->port_name;
return 0;
}
-static int vybrid_gpio_odata_to_platdata(struct udevice *dev)
+static int vybrid_gpio_odata_to_plat(struct udevice *dev)
{
- struct vybrid_gpio_platdata *plat = dev_get_platdata(dev);
+ struct vybrid_gpio_plat *plat = dev_get_plat(dev);
fdt_addr_t base_addr;
base_addr = dev_read_addr(dev);
.id = UCLASS_GPIO,
.ops = &gpio_vybrid_ops,
.of_match = vybrid_gpio_ids,
- .ofdata_to_platdata = vybrid_gpio_odata_to_platdata,
+ .of_to_plat = vybrid_gpio_odata_to_plat,
.probe = vybrid_gpio_probe,
- .priv_auto_alloc_size = sizeof(struct vybrid_gpios),
- .platdata_auto_alloc_size = sizeof(struct vybrid_gpio_platdata),
+ .priv_auto = sizeof(struct vybrid_gpios),
+ .plat_auto = sizeof(struct vybrid_gpio_plat),
};
u32 gpiodir;
};
-struct xilinx_gpio_platdata {
+struct xilinx_gpio_plat {
struct gpio_regs *regs;
int bank_max[XILINX_GPIO_MAX_BANK];
int bank_input[XILINX_GPIO_MAX_BANK];
static int xilinx_gpio_get_bank_pin(unsigned offset, u32 *bank_num,
u32 *bank_pin_num, struct udevice *dev)
{
- struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
+ struct xilinx_gpio_plat *plat = dev_get_plat(dev);
u32 bank, max_pins;
/* the first gpio is 0 not 1 */
u32 pin_num = offset;
for (bank = 0; bank < XILINX_GPIO_MAX_BANK; bank++) {
- max_pins = platdata->bank_max[bank];
+ max_pins = plat->bank_max[bank];
if (pin_num < max_pins) {
debug("%s: found at bank 0x%x pin 0x%x\n", __func__,
bank, pin_num);
static int xilinx_gpio_set_value(struct udevice *dev, unsigned offset,
int value)
{
- struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
+ struct xilinx_gpio_plat *plat = dev_get_plat(dev);
struct xilinx_gpio_privdata *priv = dev_get_priv(dev);
int val, ret;
u32 bank, pin;
val = priv->output_val[bank];
debug("%s: regs: %lx, value: %x, gpio: %x, bank %x, pin %x, out %x\n",
- __func__, (ulong)platdata->regs, value, offset, bank, pin, val);
+ __func__, (ulong)plat->regs, value, offset, bank, pin, val);
if (value)
val = val | (1 << pin);
else
val = val & ~(1 << pin);
- writel(val, &platdata->regs->gpiodata + bank * 2);
+ writel(val, &plat->regs->gpiodata + bank * 2);
priv->output_val[bank] = val;
static int xilinx_gpio_get_value(struct udevice *dev, unsigned offset)
{
- struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
+ struct xilinx_gpio_plat *plat = dev_get_plat(dev);
struct xilinx_gpio_privdata *priv = dev_get_priv(dev);
int val, ret;
u32 bank, pin;
return ret;
debug("%s: regs: %lx, gpio: %x, bank %x, pin %x\n", __func__,
- (ulong)platdata->regs, offset, bank, pin);
+ (ulong)plat->regs, offset, bank, pin);
- if (platdata->bank_output[bank]) {
+ if (plat->bank_output[bank]) {
debug("%s: Read saved output value\n", __func__);
val = priv->output_val[bank];
} else {
debug("%s: Read input value from reg\n", __func__);
- val = readl(&platdata->regs->gpiodata + bank * 2);
+ val = readl(&plat->regs->gpiodata + bank * 2);
}
val = !!(val & (1 << pin));
static int xilinx_gpio_get_function(struct udevice *dev, unsigned offset)
{
- struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
+ struct xilinx_gpio_plat *plat = dev_get_plat(dev);
int val, ret;
u32 bank, pin;
return ret;
/* Check if all pins are inputs */
- if (platdata->bank_input[bank])
+ if (plat->bank_input[bank])
return GPIOF_INPUT;
/* Check if all pins are outputs */
- if (platdata->bank_output[bank])
+ if (plat->bank_output[bank])
return GPIOF_OUTPUT;
/* FIXME test on dual */
- val = readl(&platdata->regs->gpiodir + bank * 2);
+ val = readl(&plat->regs->gpiodir + bank * 2);
val = !(val & (1 << pin));
/* input is 1 in reg but GPIOF_INPUT is 0 */
static int xilinx_gpio_direction_output(struct udevice *dev, unsigned offset,
int value)
{
- struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
+ struct xilinx_gpio_plat *plat = dev_get_plat(dev);
int val, ret;
u32 bank, pin;
return ret;
/* can't change it if all is input by default */
- if (platdata->bank_input[bank])
+ if (plat->bank_input[bank])
return -EINVAL;
xilinx_gpio_set_value(dev, offset, value);
- if (!platdata->bank_output[bank]) {
- val = readl(&platdata->regs->gpiodir + bank * 2);
+ if (!plat->bank_output[bank]) {
+ val = readl(&plat->regs->gpiodir + bank * 2);
val = val & ~(1 << pin);
- writel(val, &platdata->regs->gpiodir + bank * 2);
+ writel(val, &plat->regs->gpiodir + bank * 2);
}
return 0;
static int xilinx_gpio_direction_input(struct udevice *dev, unsigned offset)
{
- struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
+ struct xilinx_gpio_plat *plat = dev_get_plat(dev);
int val, ret;
u32 bank, pin;
return ret;
/* Already input */
- if (platdata->bank_input[bank])
+ if (plat->bank_input[bank])
return 0;
/* can't change it if all is output by default */
- if (platdata->bank_output[bank])
+ if (plat->bank_output[bank])
return -EINVAL;
- val = readl(&platdata->regs->gpiodir + bank * 2);
+ val = readl(&plat->regs->gpiodir + bank * 2);
val = val | (1 << pin);
- writel(val, &platdata->regs->gpiodir + bank * 2);
+ writel(val, &plat->regs->gpiodir + bank * 2);
return 0;
}
static int xilinx_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
struct ofnode_phandle_args *args)
{
- struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
+ struct xilinx_gpio_plat *plat = dev_get_plat(dev);
desc->offset = args->args[0];
* add amount of pins in second channel if present.
*/
if (args->args[1]) {
- if (!platdata->bank_max[1]) {
+ if (!plat->bank_max[1]) {
printf("%s: %s has no second channel\n",
__func__, dev->name);
return -EINVAL;
}
- desc->offset += platdata->bank_max[0];
+ desc->offset += plat->bank_max[0];
}
/* The third cell is optional */
static int xilinx_gpio_probe(struct udevice *dev)
{
- struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
+ struct xilinx_gpio_plat *plat = dev_get_plat(dev);
struct xilinx_gpio_privdata *priv = dev_get_priv(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
const void *label_ptr;
uc_priv->bank_name = dev->name;
}
- uc_priv->gpio_count = platdata->bank_max[0] + platdata->bank_max[1];
+ uc_priv->gpio_count = plat->bank_max[0] + plat->bank_max[1];
- priv->output_val[0] = platdata->dout_default[0];
+ priv->output_val[0] = plat->dout_default[0];
- if (platdata->bank_max[1])
- priv->output_val[1] = platdata->dout_default[1];
+ if (plat->bank_max[1])
+ priv->output_val[1] = plat->dout_default[1];
return 0;
}
-static int xilinx_gpio_ofdata_to_platdata(struct udevice *dev)
+static int xilinx_gpio_of_to_plat(struct udevice *dev)
{
- struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
+ struct xilinx_gpio_plat *plat = dev_get_plat(dev);
int is_dual;
- platdata->regs = (struct gpio_regs *)dev_read_addr(dev);
+ plat->regs = (struct gpio_regs *)dev_read_addr(dev);
- platdata->bank_max[0] = dev_read_u32_default(dev,
- "xlnx,gpio-width", 0);
- platdata->bank_input[0] = dev_read_u32_default(dev,
- "xlnx,all-inputs", 0);
- platdata->bank_output[0] = dev_read_u32_default(dev,
- "xlnx,all-outputs", 0);
- platdata->dout_default[0] = dev_read_u32_default(dev,
- "xlnx,dout-default",
- 0);
+ plat->bank_max[0] = dev_read_u32_default(dev, "xlnx,gpio-width", 0);
+ plat->bank_input[0] = dev_read_u32_default(dev, "xlnx,all-inputs", 0);
+ plat->bank_output[0] = dev_read_u32_default(dev, "xlnx,all-outputs", 0);
+ plat->dout_default[0] = dev_read_u32_default(dev, "xlnx,dout-default",
+ 0);
is_dual = dev_read_u32_default(dev, "xlnx,is-dual", 0);
if (is_dual) {
- platdata->bank_max[1] = dev_read_u32_default(dev,
- "xlnx,gpio2-width", 0);
- platdata->bank_input[1] = dev_read_u32_default(dev,
+ plat->bank_max[1] = dev_read_u32_default(dev,
+ "xlnx,gpio2-width", 0);
+ plat->bank_input[1] = dev_read_u32_default(dev,
"xlnx,all-inputs-2", 0);
- platdata->bank_output[1] = dev_read_u32_default(dev,
+ plat->bank_output[1] = dev_read_u32_default(dev,
"xlnx,all-outputs-2", 0);
- platdata->dout_default[1] = dev_read_u32_default(dev,
+ plat->dout_default[1] = dev_read_u32_default(dev,
"xlnx,dout-default-2", 0);
}
.id = UCLASS_GPIO,
.ops = &xilinx_gpio_ops,
.of_match = xilinx_gpio_ids,
- .ofdata_to_platdata = xilinx_gpio_ofdata_to_platdata,
+ .of_to_plat = xilinx_gpio_of_to_plat,
.probe = xilinx_gpio_probe,
- .platdata_auto_alloc_size = sizeof(struct xilinx_gpio_platdata),
- .priv_auto_alloc_size = sizeof(struct xilinx_gpio_privdata),
+ .plat_auto = sizeof(struct xilinx_gpio_plat),
+ .priv_auto = sizeof(struct xilinx_gpio_privdata),
};
#define PMC_GPIO_NR_GPIOS 116
#define PMC_GPIO_MAX_BANK 5
-struct zynq_gpio_platdata {
+struct zynq_gpio_plat {
phys_addr_t base;
const struct zynq_platform_data *p_data;
};
unsigned int *bank_pin_num,
struct udevice *dev)
{
- struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
+ struct zynq_gpio_plat *plat = dev_get_plat(dev);
u32 bank;
- for (bank = 0; bank < platdata->p_data->max_bank; bank++) {
- if (pin_num >= platdata->p_data->bank_min[bank] &&
- pin_num <= platdata->p_data->bank_max[bank]) {
+ for (bank = 0; bank < plat->p_data->max_bank; bank++) {
+ if (pin_num >= plat->p_data->bank_min[bank] &&
+ pin_num <= plat->p_data->bank_max[bank]) {
*bank_num = bank;
*bank_pin_num = pin_num -
- platdata->p_data->bank_min[bank];
+ plat->p_data->bank_min[bank];
return;
}
}
- if (bank >= platdata->p_data->max_bank) {
+ if (bank >= plat->p_data->max_bank) {
printf("Invalid bank and pin num\n");
*bank_num = 0;
*bank_pin_num = 0;
static int gpio_is_valid(unsigned gpio, struct udevice *dev)
{
- struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
+ struct zynq_gpio_plat *plat = dev_get_plat(dev);
- return gpio < platdata->p_data->ngpio;
+ return gpio < plat->p_data->ngpio;
}
static int check_gpio(unsigned gpio, struct udevice *dev)
{
u32 data;
unsigned int bank_num, bank_pin_num;
- struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
+ struct zynq_gpio_plat *plat = dev_get_plat(dev);
if (check_gpio(gpio, dev) < 0)
return -1;
zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev);
- data = readl(platdata->base +
+ data = readl(plat->base +
ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
return (data >> bank_pin_num) & 1;
static int zynq_gpio_set_value(struct udevice *dev, unsigned gpio, int value)
{
unsigned int reg_offset, bank_num, bank_pin_num;
- struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
+ struct zynq_gpio_plat *plat = dev_get_plat(dev);
if (check_gpio(gpio, dev) < 0)
return -1;
value = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) &
((value << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK);
- writel(value, platdata->base + reg_offset);
+ writel(value, plat->base + reg_offset);
return 0;
}
{
u32 reg;
unsigned int bank_num, bank_pin_num;
- struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
+ struct zynq_gpio_plat *plat = dev_get_plat(dev);
if (check_gpio(gpio, dev) < 0)
return -1;
return -1;
/* clear the bit in direction mode reg to set the pin as input */
- reg = readl(platdata->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
+ reg = readl(plat->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
reg &= ~BIT(bank_pin_num);
- writel(reg, platdata->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
+ writel(reg, plat->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
return 0;
}
{
u32 reg;
unsigned int bank_num, bank_pin_num;
- struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
+ struct zynq_gpio_plat *plat = dev_get_plat(dev);
if (check_gpio(gpio, dev) < 0)
return -1;
zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev);
/* set the GPIO pin as output */
- reg = readl(platdata->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
+ reg = readl(plat->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
reg |= BIT(bank_pin_num);
- writel(reg, platdata->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
+ writel(reg, plat->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
/* configure the output enable reg for the pin */
- reg = readl(platdata->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
+ reg = readl(plat->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
reg |= BIT(bank_pin_num);
- writel(reg, platdata->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
+ writel(reg, plat->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
/* set the state of the pin */
zynq_gpio_set_value(dev, gpio, value);
{
u32 reg;
unsigned int bank_num, bank_pin_num;
- struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
+ struct zynq_gpio_plat *plat = dev_get_plat(dev);
if (check_gpio(offset, dev) < 0)
return -1;
zynq_gpio_get_bank_pin(offset, &bank_num, &bank_pin_num, dev);
/* set the GPIO pin as output */
- reg = readl(platdata->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
+ reg = readl(plat->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
reg &= BIT(bank_pin_num);
if (reg)
return GPIOF_OUTPUT;
static int zynq_gpio_probe(struct udevice *dev)
{
- struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
+ struct zynq_gpio_plat *plat = dev_get_plat(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
const void *label_ptr;
uc_priv->bank_name = dev->name;
}
- if (platdata->p_data)
- uc_priv->gpio_count = platdata->p_data->ngpio;
+ if (plat->p_data)
+ uc_priv->gpio_count = plat->p_data->ngpio;
return 0;
}
-static int zynq_gpio_ofdata_to_platdata(struct udevice *dev)
+static int zynq_gpio_of_to_plat(struct udevice *dev)
{
- struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
+ struct zynq_gpio_plat *plat = dev_get_plat(dev);
- platdata->base = (phys_addr_t)dev_read_addr(dev);
+ plat->base = (phys_addr_t)dev_read_addr(dev);
- platdata->p_data =
+ plat->p_data =
(struct zynq_platform_data *)dev_get_driver_data(dev);
return 0;
.id = UCLASS_GPIO,
.ops = &gpio_zynq_ops,
.of_match = zynq_gpio_ids,
- .ofdata_to_platdata = zynq_gpio_ofdata_to_platdata,
+ .of_to_plat = zynq_gpio_of_to_plat,
.probe = zynq_gpio_probe,
- .platdata_auto_alloc_size = sizeof(struct zynq_gpio_platdata),
+ .plat_auto = sizeof(struct zynq_gpio_plat),
};
.of_match = stm32mp1_hwspinlock_ids,
.ops = &stm32mp1_hwspinlock_ops,
.probe = stm32mp1_hwspinlock_probe,
- .priv_auto_alloc_size = sizeof(struct stm32mp1_hws_priv),
+ .priv_auto = sizeof(struct stm32mp1_hws_priv),
};
Enable driver model for I2C. The I2C uclass interface: probe, read,
write and speed, is implemented with the bus drivers operations,
which provide methods for bus setting and data transfer. Each chip
- device (bus child) info is kept as parent platdata. The interface
+ device (bus child) info is kept as parent plat. The interface
is defined in include/i2c.h.
config I2C_CROS_EC_TUNNEL
return 0;
}
-int acpi_i2c_ofdata_to_platdata(struct udevice *dev)
+int acpi_i2c_of_to_plat(struct udevice *dev)
{
struct acpi_i2c_priv *priv = dev_get_priv(dev);
/* Use name specified in priv or build one from I2C address */
static int acpi_i2c_get_name(const struct udevice *dev, char *out_name)
{
- struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
+ struct dm_i2c_chip *chip = dev_get_parent_plat(dev);
struct acpi_i2c_priv *priv = dev_get_priv(dev);
snprintf(out_name, ACPI_NAME_MAX,
extern struct acpi_ops acpi_i2c_ops;
-int acpi_i2c_ofdata_to_platdata(struct udevice *dev);
+int acpi_i2c_of_to_plat(struct udevice *dev);
#endif
| I2CD_INTR_ABNORMAL, &priv->regs->icr);
}
-static int ast_i2c_ofdata_to_platdata(struct udevice *dev)
+static int ast_i2c_of_to_plat(struct udevice *dev)
{
struct ast_i2c_priv *priv = dev_get_priv(dev);
int ret;
.id = UCLASS_I2C,
.of_match = ast_i2c_ids,
.probe = ast_i2c_probe,
- .ofdata_to_platdata = ast_i2c_ofdata_to_platdata,
- .priv_auto_alloc_size = sizeof(struct ast_i2c_priv),
+ .of_to_plat = ast_i2c_of_to_plat,
+ .priv_auto = sizeof(struct ast_i2c_priv),
.ops = &ast_i2c_ops,
};
return bus->speed;
}
-static int at91_i2c_ofdata_to_platdata(struct udevice *dev)
+static int at91_i2c_of_to_plat(struct udevice *dev)
{
const void *blob = gd->fdt_blob;
struct at91_i2c_bus *bus = dev_get_priv(dev);
.id = UCLASS_I2C,
.of_match = at91_i2c_ids,
.probe = at91_i2c_probe,
- .ofdata_to_platdata = at91_i2c_ofdata_to_platdata,
- .per_child_auto_alloc_size = sizeof(struct dm_i2c_chip),
- .priv_auto_alloc_size = sizeof(struct at91_i2c_bus),
+ .of_to_plat = at91_i2c_of_to_plat,
+ .per_child_auto = sizeof(struct dm_i2c_chip),
+ .priv_auto = sizeof(struct at91_i2c_bus),
.ops = &at91_i2c_ops,
};
return cros_ec_i2c_tunnel(dev->parent, i2c_bus->remote_bus, msg, nmsgs);
}
-static int cros_ec_i2c_ofdata_to_platdata(struct udevice *dev)
+static int cros_ec_i2c_of_to_plat(struct udevice *dev)
{
struct cros_ec_i2c_bus *i2c_bus = dev_get_priv(dev);
const void *blob = gd->fdt_blob;
.name = "cros_ec_tunnel",
.id = UCLASS_I2C,
.of_match = cros_ec_i2c_ids,
- .ofdata_to_platdata = cros_ec_i2c_ofdata_to_platdata,
- .priv_auto_alloc_size = sizeof(struct cros_ec_i2c_bus),
+ .of_to_plat = cros_ec_i2c_of_to_plat,
+ .priv_auto = sizeof(struct cros_ec_i2c_bus),
.ops = &cros_ec_i2c_ops,
};
.id = UCLASS_I2C,
.of_match = davinci_i2c_ids,
.probe = davinci_i2c_probe,
- .priv_auto_alloc_size = sizeof(struct i2c_bus),
+ .priv_auto = sizeof(struct i2c_bus),
.ops = &davinci_i2c_ops,
};
return ret;
}
-int designware_i2c_ofdata_to_platdata(struct udevice *bus)
+int designware_i2c_of_to_plat(struct udevice *bus)
{
struct dw_i2c *priv = dev_get_priv(bus);
int ret;
.name = "i2c_designware",
.id = UCLASS_I2C,
.of_match = designware_i2c_ids,
- .ofdata_to_platdata = designware_i2c_ofdata_to_platdata,
+ .of_to_plat = designware_i2c_of_to_plat,
.probe = designware_i2c_probe,
- .priv_auto_alloc_size = sizeof(struct dw_i2c),
+ .priv_auto = sizeof(struct dw_i2c),
.remove = designware_i2c_remove,
.flags = DM_FLAG_OS_PREPARE,
.ops = &designware_i2c_ops,
int designware_i2c_probe(struct udevice *bus);
int designware_i2c_remove(struct udevice *dev);
-int designware_i2c_ofdata_to_platdata(struct udevice *bus);
+int designware_i2c_of_to_plat(struct udevice *bus);
/**
* dw_i2c_gen_speed_config() - Calculate config info from requested speed
/* Have a weak function for now - possibly should be a new uclass */
__weak void lpss_reset_release(void *regs);
-static int designware_i2c_pci_ofdata_to_platdata(struct udevice *dev)
+static int designware_i2c_pci_of_to_plat(struct udevice *dev)
{
struct dw_i2c *priv = dev_get_priv(dev);
if (dev_get_driver_data(dev) == INTEL_APL)
priv->has_spk_cnt = true;
- return designware_i2c_ofdata_to_platdata(dev);
+ return designware_i2c_of_to_plat(dev);
}
static int designware_i2c_pci_probe(struct udevice *dev)
.id = UCLASS_I2C,
.of_match = designware_i2c_pci_ids,
.bind = designware_i2c_pci_bind,
- .ofdata_to_platdata = designware_i2c_pci_ofdata_to_platdata,
+ .of_to_plat = designware_i2c_pci_of_to_plat,
.probe = designware_i2c_pci_probe,
- .priv_auto_alloc_size = sizeof(struct dw_i2c),
+ .priv_auto = sizeof(struct dw_i2c),
.remove = designware_i2c_remove,
.flags = DM_FLAG_OS_PREPARE,
.ops = &designware_i2c_ops,
return ret != I2C_OK;
}
-static int s3c_i2c_ofdata_to_platdata(struct udevice *dev)
+static int s3c_i2c_of_to_plat(struct udevice *dev)
{
const void *blob = gd->fdt_blob;
struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
.name = "i2c_s3c_hs",
.id = UCLASS_I2C,
.of_match = exynos_hs_i2c_ids,
- .ofdata_to_platdata = s3c_i2c_ofdata_to_platdata,
- .priv_auto_alloc_size = sizeof(struct s3c24x0_i2c_bus),
+ .of_to_plat = s3c_i2c_of_to_plat,
+ .priv_auto = sizeof(struct s3c24x0_i2c_bus),
.ops = &exynos_hs_i2c_ops,
};
return __i2c_set_bus_speed(dev->base, speed, dev->i2c_clk);
}
-static int fsl_i2c_ofdata_to_platdata(struct udevice *bus)
+static int fsl_i2c_of_to_plat(struct udevice *bus)
{
struct fsl_i2c_dev *dev = dev_get_priv(bus);
struct clk clock;
.id = UCLASS_I2C,
.of_match = fsl_i2c_ids,
.probe = fsl_i2c_probe,
- .ofdata_to_platdata = fsl_i2c_ofdata_to_platdata,
- .priv_auto_alloc_size = sizeof(struct fsl_i2c_dev),
+ .of_to_plat = fsl_i2c_of_to_plat,
+ .priv_auto = sizeof(struct fsl_i2c_dev),
.ops = &fsl_i2c_ops,
};
return ret;
}
-static int cdns_i2c_ofdata_to_platdata(struct udevice *dev)
+static int cdns_i2c_of_to_plat(struct udevice *dev)
{
struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
struct cdns_i2c_platform_data *pdata =
.name = "i2c_cdns",
.id = UCLASS_I2C,
.of_match = cdns_i2c_of_match,
- .ofdata_to_platdata = cdns_i2c_ofdata_to_platdata,
- .priv_auto_alloc_size = sizeof(struct i2c_cdns_bus),
+ .of_to_plat = cdns_i2c_of_to_plat,
+ .priv_auto = sizeof(struct i2c_cdns_bus),
.ops = &cdns_i2c_ops,
};
return 0;
}
-static int ca_i2c_ofdata_to_platdata(struct udevice *bus)
+static int ca_i2c_of_to_plat(struct udevice *bus)
{
struct ca_i2c *priv = dev_get_priv(bus);
.name = "i2c_cortina",
.id = UCLASS_I2C,
.of_match = ca_i2c_ids,
- .ofdata_to_platdata = ca_i2c_ofdata_to_platdata,
+ .of_to_plat = ca_i2c_of_to_plat,
.probe = ca_i2c_probe,
- .priv_auto_alloc_size = sizeof(struct ca_i2c),
+ .priv_auto = sizeof(struct ca_i2c),
.ops = &ca_i2c_ops,
.flags = DM_FLAG_PRE_RELOC,
};
* i2c emulation works using an 'emul' node at the bus level. Each device in
* that node is in the UCLASS_I2C_EMUL uclass, and emulates one i2c device. A
* pointer to the device it emulates is in the 'dev' property of the emul device
- * uclass platdata (struct i2c_emul_platdata), put there by i2c_emul_find().
+ * uclass plat (struct i2c_emul_plat), put there by i2c_emul_find().
* When sandbox wants an emulator for a device, it calls i2c_emul_find() which
* searches for the emulator with the correct address. To find the device for an
* emulator, call i2c_emul_get_device().
*/
/**
- * struct i2c_emul_uc_platdata - information about the emulator for this device
+ * struct i2c_emul_uc_plat - information about the emulator for this device
*
* This is used by devices in UCLASS_I2C_EMUL to record information about the
- * device being emulated. It is accessible with dev_get_uclass_platdata()
+ * device being emulated. It is accessible with dev_get_uclass_plat()
*
* @dev: Device being emulated
*/
-struct i2c_emul_uc_platdata {
+struct i2c_emul_uc_plat {
struct udevice *dev;
};
struct udevice *i2c_emul_get_device(struct udevice *emul)
{
- struct i2c_emul_uc_platdata *uc_plat = dev_get_uclass_platdata(emul);
+ struct i2c_emul_uc_plat *uc_plat = dev_get_uclass_plat(emul);
return uc_plat->dev;
}
int i2c_emul_find(struct udevice *dev, struct udevice **emulp)
{
- struct i2c_emul_uc_platdata *uc_plat;
+ struct i2c_emul_uc_plat *uc_plat;
struct udevice *emul;
int ret;
log_err("No emulators for device '%s'\n", dev->name);
return ret;
}
- uc_plat = dev_get_uclass_platdata(emul);
+ uc_plat = dev_get_uclass_plat(emul);
uc_plat->dev = dev;
*emulp = emul;
UCLASS_DRIVER(i2c_emul) = {
.id = UCLASS_I2C_EMUL,
.name = "i2c_emul",
- .per_device_platdata_auto_alloc_size =
- sizeof(struct i2c_emul_uc_platdata),
+ .per_device_plat_auto = sizeof(struct i2c_emul_uc_plat),
};
/*
- * This uclass is a child of the i2c bus. Its platdata is not defined here so
+ * This uclass is a child of the i2c bus. Its plat is not defined here so
* is defined by its parent, UCLASS_I2C, which uses struct dm_i2c_chip. See
- * per_child_platdata_auto_alloc_size in UCLASS_DRIVER(i2c).
+ * per_child_plat_auto in UCLASS_DRIVER(i2c).
*/
UCLASS_DRIVER(i2c_emul_parent) = {
.id = UCLASS_I2C_EMUL_PARENT,
return 0;
}
-static int i2c_gpio_ofdata_to_platdata(struct udevice *dev)
+static int i2c_gpio_of_to_plat(struct udevice *dev)
{
struct i2c_gpio_bus *bus = dev_get_priv(dev);
int ret;
.id = UCLASS_I2C,
.of_match = i2c_gpio_ids,
.probe = i2c_gpio_drv_probe,
- .ofdata_to_platdata = i2c_gpio_ofdata_to_platdata,
- .priv_auto_alloc_size = sizeof(struct i2c_gpio_bus),
+ .of_to_plat = i2c_gpio_of_to_plat,
+ .priv_auto = sizeof(struct i2c_gpio_bus),
.ops = &i2c_gpio_ops,
};
static int i2c_read_bytewise(struct udevice *dev, uint offset,
uint8_t *buffer, int len)
{
- struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
+ struct dm_i2c_chip *chip = dev_get_parent_plat(dev);
struct udevice *bus = dev_get_parent(dev);
struct dm_i2c_ops *ops = i2c_get_ops(bus);
struct i2c_msg msg[2], *ptr;
static int i2c_write_bytewise(struct udevice *dev, uint offset,
const uint8_t *buffer, int len)
{
- struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
+ struct dm_i2c_chip *chip = dev_get_parent_plat(dev);
struct udevice *bus = dev_get_parent(dev);
struct dm_i2c_ops *ops = i2c_get_ops(bus);
struct i2c_msg msg[1];
int dm_i2c_read(struct udevice *dev, uint offset, uint8_t *buffer, int len)
{
- struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
+ struct dm_i2c_chip *chip = dev_get_parent_plat(dev);
struct udevice *bus = dev_get_parent(dev);
struct dm_i2c_ops *ops = i2c_get_ops(bus);
struct i2c_msg msg[2], *ptr;
int dm_i2c_write(struct udevice *dev, uint offset, const uint8_t *buffer,
int len)
{
- struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
+ struct dm_i2c_chip *chip = dev_get_parent_plat(dev);
struct udevice *bus = dev_get_parent(dev);
struct dm_i2c_ops *ops = i2c_get_ops(bus);
struct i2c_msg msg[1];
goto err_bind;
/* Tell the device what we know about it */
- chip = dev_get_parent_platdata(dev);
+ chip = dev_get_parent_plat(dev);
chip->chip_addr = chip_addr;
chip->offset_len = offset_len;
ret = device_probe(dev);
bus->name, chip_addr);
for (device_find_first_child(bus, &dev); dev;
device_find_next_child(&dev)) {
- struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
+ struct dm_i2c_chip *chip = dev_get_parent_plat(dev);
int ret;
if (chip->chip_addr == (chip_addr &
int i2c_set_chip_flags(struct udevice *dev, uint flags)
{
struct udevice *bus = dev->parent;
- struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
+ struct dm_i2c_chip *chip = dev_get_parent_plat(dev);
struct dm_i2c_ops *ops = i2c_get_ops(bus);
int ret;
int i2c_get_chip_flags(struct udevice *dev, uint *flagsp)
{
- struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
+ struct dm_i2c_chip *chip = dev_get_parent_plat(dev);
*flagsp = chip->flags;
int i2c_set_chip_offset_len(struct udevice *dev, uint offset_len)
{
- struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
+ struct dm_i2c_chip *chip = dev_get_parent_plat(dev);
if (offset_len > I2C_MAX_OFFSET_LEN)
return log_ret(-EINVAL);
int i2c_get_chip_offset_len(struct udevice *dev)
{
- struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
+ struct dm_i2c_chip *chip = dev_get_parent_plat(dev);
return chip->offset_len;
}
int i2c_set_chip_addr_offset_mask(struct udevice *dev, uint mask)
{
- struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
+ struct dm_i2c_chip *chip = dev_get_parent_plat(dev);
chip->chip_addr_offset_mask = mask;
uint i2c_get_chip_addr_offset_mask(struct udevice *dev)
{
- struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
+ struct dm_i2c_chip *chip = dev_get_parent_plat(dev);
return chip->chip_addr_offset_mask;
}
}
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
-int i2c_chip_ofdata_to_platdata(struct udevice *dev, struct dm_i2c_chip *chip)
+int i2c_chip_of_to_plat(struct udevice *dev, struct dm_i2c_chip *chip)
{
int addr;
static int i2c_child_post_bind(struct udevice *dev)
{
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
- struct dm_i2c_chip *plat = dev_get_parent_platdata(dev);
+ struct dm_i2c_chip *plat = dev_get_parent_plat(dev);
if (!dev_of_valid(dev))
return 0;
- return i2c_chip_ofdata_to_platdata(dev, plat);
+ return i2c_chip_of_to_plat(dev, plat);
#else
return 0;
#endif
.flags = DM_UC_FLAG_SEQ_ALIAS,
.post_bind = i2c_post_bind,
.init = i2c_uclass_init,
- .priv_auto_alloc_size = sizeof(struct i2c_priv),
+ .priv_auto = sizeof(struct i2c_priv),
.pre_probe = i2c_pre_probe,
.post_probe = i2c_post_probe,
- .per_device_auto_alloc_size = sizeof(struct dm_i2c_bus),
- .per_child_platdata_auto_alloc_size = sizeof(struct dm_i2c_chip),
+ .per_device_auto = sizeof(struct dm_i2c_bus),
+ .per_child_plat_auto = sizeof(struct dm_i2c_chip),
.child_post_bind = i2c_child_post_bind,
};
.id = UCLASS_I2C_GENERIC,
.of_match = generic_chip_i2c_ids,
#if CONFIG_IS_ENABLED(ACPIGEN)
- .ofdata_to_platdata = acpi_i2c_ofdata_to_platdata,
- .priv_auto_alloc_size = sizeof(struct acpi_i2c_priv),
+ .of_to_plat = acpi_i2c_of_to_plat,
+ .priv_auto = sizeof(struct acpi_i2c_priv),
#endif
ACPI_OPS_PTR(&acpi_i2c_ops)
};
.id = UCLASS_I2C,
.of_match = uniphier_fi2c_of_match,
.probe = uniphier_fi2c_probe,
- .priv_auto_alloc_size = sizeof(struct uniphier_fi2c_priv),
+ .priv_auto = sizeof(struct uniphier_fi2c_priv),
.ops = &uniphier_fi2c_ops,
};
.id = UCLASS_I2C,
.of_match = uniphier_i2c_of_match,
.probe = uniphier_i2c_probe,
- .priv_auto_alloc_size = sizeof(struct uniphier_i2c_priv),
+ .priv_auto = sizeof(struct uniphier_i2c_priv),
.ops = &uniphier_i2c_ops,
};
.id = UCLASS_I2C,
.of_match = versatile_i2c_of_match,
.probe = versatile_i2c_probe,
- .priv_auto_alloc_size = sizeof(struct versatile_i2c_priv),
+ .priv_auto = sizeof(struct versatile_i2c_priv),
.ops = &versatile_i2c_ops,
};
.id = UCLASS_I2C,
.of_match = ihs_i2c_ids,
.probe = ihs_i2c_probe,
- .priv_auto_alloc_size = sizeof(struct ihs_i2c_priv),
+ .priv_auto = sizeof(struct ihs_i2c_priv),
.ops = &ihs_i2c_ops,
};
.id = UCLASS_I2C,
.of_match = imx_lpi2c_ids,
.probe = imx_lpi2c_probe,
- .priv_auto_alloc_size = sizeof(struct imx_lpi2c_bus),
+ .priv_auto = sizeof(struct imx_lpi2c_bus),
.ops = &imx_lpi2c_ops,
};
.id = UCLASS_I2C,
.of_match = intel_i2c_ids,
.ops = &intel_i2c_ops,
- .priv_auto_alloc_size = sizeof(struct intel_i2c),
+ .priv_auto = sizeof(struct intel_i2c),
.bind = intel_i2c_bind,
.probe = intel_i2c_probe,
};
return iproc_i2c_init(bus);
}
-static int iproc_i2c_ofdata_to_platdata(struct udevice *bus)
+static int iproc_i2c_of_to_plat(struct udevice *bus)
{
struct iproc_i2c *bus_prvdata = dev_get_priv(bus);
int node = dev_of_offset(bus);
.name = "iproc_i2c",
.id = UCLASS_I2C,
.of_match = iproc_i2c_ids,
- .ofdata_to_platdata = iproc_i2c_ofdata_to_platdata,
+ .of_to_plat = iproc_i2c_of_to_plat,
.probe = iproc_i2c_probe,
- .priv_auto_alloc_size = sizeof(struct iproc_i2c),
+ .priv_auto = sizeof(struct iproc_i2c),
.ops = &iproc_i2c_ops,
.flags = DM_FLAG_PRE_RELOC,
};
#else /* CONFIG_DM_I2C */
static int lpc32xx_i2c_probe(struct udevice *bus)
{
- struct lpc32xx_i2c_dev *dev = dev_get_platdata(bus);
+ struct lpc32xx_i2c_dev *dev = dev_get_plat(bus);
bus->seq = dev->index;
__i2c_init(dev->base, dev->speed, 0, dev->index);
static int lpc32xx_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
u32 chip_flags)
{
- struct lpc32xx_i2c_dev *dev = dev_get_platdata(bus);
+ struct lpc32xx_i2c_dev *dev = dev_get_plat(bus);
return __i2c_probe_chip(dev->base, chip_addr);
}
static int lpc32xx_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
int nmsgs)
{
- struct lpc32xx_i2c_dev *dev = dev_get_platdata(bus);
+ struct lpc32xx_i2c_dev *dev = dev_get_plat(bus);
struct i2c_msg *dmsg, *omsg, dummy;
uint i = 0, address = 0;
static int lpc32xx_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
{
- struct lpc32xx_i2c_dev *dev = dev_get_platdata(bus);
+ struct lpc32xx_i2c_dev *dev = dev_get_plat(bus);
return __i2c_set_bus_speed(dev->base, speed, dev->index);
}
static int lpc32xx_i2c_reset(struct udevice *bus)
{
- struct lpc32xx_i2c_dev *dev = dev_get_platdata(bus);
+ struct lpc32xx_i2c_dev *dev = dev_get_plat(bus);
__i2c_init(dev->base, dev->speed, 0, dev->index);
return 0;
.id = UCLASS_I2C,
.of_match = meson_i2c_ids,
.probe = meson_i2c_probe,
- .priv_auto_alloc_size = sizeof(struct meson_i2c),
+ .priv_auto = sizeof(struct meson_i2c),
.ops = &meson_i2c_ops,
};
.probe = i2c_arbitrator_probe,
.remove = i2c_arbitrator_remove,
.ops = &i2c_arbitrator_ops,
- .priv_auto_alloc_size = sizeof(struct i2c_arbitrator_priv),
+ .priv_auto = sizeof(struct i2c_arbitrator_priv),
};
.of_match = i2c_mux_gpio_ids,
.ops = &i2c_mux_gpio_ops,
.probe = i2c_mux_gpio_probe,
- .priv_auto_alloc_size = sizeof(struct i2c_mux_gpio_priv),
+ .priv_auto = sizeof(struct i2c_mux_gpio_priv),
};
/* Find out the mux channel number */
static int i2c_mux_child_post_bind(struct udevice *dev)
{
- struct i2c_mux_bus *plat = dev_get_parent_platdata(dev);
+ struct i2c_mux_bus *plat = dev_get_parent_plat(dev);
int channel;
channel = dev_read_u32_default(dev, "reg", -1);
int i2c_mux_select(struct udevice *dev)
{
- struct i2c_mux_bus *plat = dev_get_parent_platdata(dev);
+ struct i2c_mux_bus *plat = dev_get_parent_plat(dev);
struct udevice *mux = dev->parent;
struct i2c_mux_ops *ops = i2c_mux_get_ops(mux);
int i2c_mux_deselect(struct udevice *dev)
{
- struct i2c_mux_bus *plat = dev_get_parent_platdata(dev);
+ struct i2c_mux_bus *plat = dev_get_parent_plat(dev);
struct udevice *mux = dev->parent;
struct i2c_mux_ops *ops = i2c_mux_get_ops(mux);
.name = "i2c_mux",
.post_bind = i2c_mux_post_bind,
.post_probe = i2c_mux_post_probe,
- .per_device_auto_alloc_size = sizeof(struct i2c_mux),
- .per_child_platdata_auto_alloc_size = sizeof(struct i2c_mux_bus),
+ .per_device_auto = sizeof(struct i2c_mux),
+ .per_child_plat_auto = sizeof(struct i2c_mux_bus),
.child_post_bind = i2c_mux_child_post_bind,
};
{ }
};
-static int pca954x_ofdata_to_platdata(struct udevice *dev)
+static int pca954x_of_to_plat(struct udevice *dev)
{
struct pca954x_priv *priv = dev_get_priv(dev);
const struct chip_desc *chip = &chips[dev_get_driver_data(dev)];
.probe = pca954x_probe,
.remove = pca954x_remove,
.ops = &pca954x_ops,
- .ofdata_to_platdata = pca954x_ofdata_to_platdata,
- .priv_auto_alloc_size = sizeof(struct pca954x_priv),
+ .of_to_plat = pca954x_of_to_plat,
+ .priv_auto = sizeof(struct pca954x_priv),
};
.id = UCLASS_I2C,
.of_match = mv_i2c_ids,
.probe = mv_i2c_probe,
- .priv_auto_alloc_size = sizeof(struct mv_i2c_priv),
+ .priv_auto = sizeof(struct mv_i2c_priv),
.ops = &mv_i2c_ops,
};
#endif /* CONFIG_DM_I2C */
return 0;
}
-static int mvtwsi_i2c_ofdata_to_platdata(struct udevice *bus)
+static int mvtwsi_i2c_of_to_plat(struct udevice *bus)
{
struct mvtwsi_i2c_dev *dev = dev_get_priv(bus);
.of_match = mvtwsi_i2c_ids,
.bind = mvtwsi_i2c_bind,
.probe = mvtwsi_i2c_probe,
- .ofdata_to_platdata = mvtwsi_i2c_ofdata_to_platdata,
- .priv_auto_alloc_size = sizeof(struct mvtwsi_i2c_dev),
+ .of_to_plat = mvtwsi_i2c_of_to_plat,
+ .priv_auto = sizeof(struct mvtwsi_i2c_dev),
.ops = &mvtwsi_i2c_ops,
};
#endif /* CONFIG_DM_I2C */
.id = UCLASS_I2C,
.of_match = mxc_i2c_ids,
.probe = mxc_i2c_probe,
- .priv_auto_alloc_size = sizeof(struct mxc_i2c_bus),
+ .priv_auto = sizeof(struct mxc_i2c_bus),
.ops = &mxc_i2c_ops,
.flags = DM_FLAG_PRE_RELOC,
};
.id = UCLASS_I2C,
.of_match = nx_i2c_ids,
.probe = nx_i2c_probe,
- .priv_auto_alloc_size = sizeof(struct nx_i2c_bus),
+ .priv_auto = sizeof(struct nx_i2c_bus),
.ops = &nx_i2c_ops,
};
.id = UCLASS_I2C,
.of_match = ocores_i2c_ids,
.probe = ocores_i2c_probe,
- .priv_auto_alloc_size = sizeof(struct ocores_i2c_bus),
+ .priv_auto = sizeof(struct ocores_i2c_bus),
.ops = &ocores_i2c_ops,
};
.id = UCLASS_I2C,
.of_match = octeon_i2c_ids,
.probe = octeon_i2c_probe,
- .priv_auto_alloc_size = sizeof(struct octeon_twsi),
+ .priv_auto = sizeof(struct octeon_twsi),
.ops = &octeon_i2c_ops,
};
static int omap_i2c_probe(struct udevice *bus)
{
struct omap_i2c *priv = dev_get_priv(bus);
- struct omap_i2c_platdata *plat = dev_get_platdata(bus);
+ struct omap_i2c_plat *plat = dev_get_plat(bus);
priv->speed = plat->speed;
priv->regs = map_physmem(plat->base, sizeof(void *),
}
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
-static int omap_i2c_ofdata_to_platdata(struct udevice *bus)
+static int omap_i2c_of_to_plat(struct udevice *bus)
{
- struct omap_i2c_platdata *plat = dev_get_platdata(bus);
+ struct omap_i2c_plat *plat = dev_get_plat(bus);
plat->base = dev_read_addr(bus);
plat->speed = dev_read_u32_default(bus, "clock-frequency",
.id = UCLASS_I2C,
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
.of_match = omap_i2c_ids,
- .ofdata_to_platdata = omap_i2c_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct omap_i2c_platdata),
+ .of_to_plat = omap_i2c_of_to_plat,
+ .plat_auto = sizeof(struct omap_i2c_plat),
#endif
.probe = omap_i2c_probe,
- .priv_auto_alloc_size = sizeof(struct omap_i2c),
+ .priv_auto = sizeof(struct omap_i2c),
.ops = &omap_i2c_ops,
#if !CONFIG_IS_ENABLED(OF_CONTROL)
.flags = DM_FLAG_PRE_RELOC,
.id = UCLASS_I2C,
.of_match = rcar_i2c_ids,
.probe = rcar_i2c_probe,
- .priv_auto_alloc_size = sizeof(struct rcar_i2c_priv),
+ .priv_auto = sizeof(struct rcar_i2c_priv),
.ops = &rcar_i2c_ops,
};
.id = UCLASS_I2C,
.of_match = rcar_iic_ids,
.probe = rcar_iic_probe,
- .priv_auto_alloc_size = sizeof(struct rcar_iic_priv),
+ .priv_auto = sizeof(struct rcar_iic_priv),
.ops = &rcar_iic_ops,
};
return 0;
}
-static int rockchip_i2c_ofdata_to_platdata(struct udevice *bus)
+static int rockchip_i2c_of_to_plat(struct udevice *bus)
{
struct rk_i2c *priv = dev_get_priv(bus);
int ret;
.name = "rockchip_rk3066_i2c",
.id = UCLASS_I2C,
.of_match = rockchip_i2c_ids,
- .ofdata_to_platdata = rockchip_i2c_ofdata_to_platdata,
+ .of_to_plat = rockchip_i2c_of_to_plat,
.probe = rockchip_i2c_probe,
- .priv_auto_alloc_size = sizeof(struct rk_i2c),
+ .priv_auto = sizeof(struct rk_i2c),
.ops = &rockchip_i2c_ops,
};
return ret ? -EREMOTEIO : 0;
}
-static int s3c_i2c_ofdata_to_platdata(struct udevice *dev)
+static int s3c_i2c_of_to_plat(struct udevice *dev)
{
const void *blob = gd->fdt_blob;
struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
.name = "i2c_s3c",
.id = UCLASS_I2C,
.of_match = s3c_i2c_ids,
- .ofdata_to_platdata = s3c_i2c_ofdata_to_platdata,
- .priv_auto_alloc_size = sizeof(struct s3c24x0_i2c_bus),
+ .of_to_plat = s3c_i2c_of_to_plat,
+ .priv_auto = sizeof(struct s3c24x0_i2c_bus),
.ops = &s3c_i2c_ops,
};
*devp = NULL;
*opsp = NULL;
- plat = dev_get_parent_platdata(dev);
+ plat = dev_get_parent_plat(dev);
if (!plat->emul) {
ret = i2c_emul_find(dev, &plat->emul);
if (ret)
.id = UCLASS_I2C,
.of_match = sandbox_i2c_ids,
.ops = &sandbox_i2c_ops,
- .priv_auto_alloc_size = sizeof(struct sandbox_i2c_priv),
+ .priv_auto = sizeof(struct sandbox_i2c_priv),
};
return ret;
}
-static int stm32_ofdata_to_platdata(struct udevice *dev)
+static int stm32_of_to_plat(struct udevice *dev)
{
struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev);
u32 rise_time, fall_time;
.name = "stm32f7-i2c",
.id = UCLASS_I2C,
.of_match = stm32_i2c_of_match,
- .ofdata_to_platdata = stm32_ofdata_to_platdata,
+ .of_to_plat = stm32_of_to_plat,
.probe = stm32_i2c_probe,
- .priv_auto_alloc_size = sizeof(struct stm32_i2c_priv),
+ .priv_auto = sizeof(struct stm32_i2c_priv),
.ops = &stm32_i2c_ops,
};
.id = UCLASS_I2C,
.of_match = tegra186_bpmp_i2c_ids,
.probe = tegra186_bpmp_i2c_probe,
- .priv_auto_alloc_size = sizeof(struct tegra186_bpmp_i2c),
+ .priv_auto = sizeof(struct tegra186_bpmp_i2c),
.ops = &tegra186_bpmp_i2c_ops,
};
.id = UCLASS_I2C,
.of_match = tegra_i2c_ids,
.probe = tegra_i2c_probe,
- .priv_auto_alloc_size = sizeof(struct i2c_bus),
+ .priv_auto = sizeof(struct i2c_bus),
.ops = &tegra_i2c_ops,
};
.id = UCLASS_I2C,
.of_match = xilinx_xiic_ids,
.probe = xilinx_xiic_probe,
- .priv_auto_alloc_size = sizeof(struct xilinx_xiic_priv),
+ .priv_auto = sizeof(struct xilinx_xiic_priv),
.ops = &xilinx_xiic_ops,
};
.of_match = cros_ec_kbd_ids,
.probe = cros_ec_kbd_probe,
.ops = &cros_ec_kbd_ops,
- .priv_auto_alloc_size = sizeof(struct cros_ec_keyb_priv),
+ .priv_auto = sizeof(struct cros_ec_keyb_priv),
};
.probe = i8042_kbd_probe,
.remove = i8042_kbd_remove,
.ops = &i8042_kbd_ops,
- .priv_auto_alloc_size = sizeof(struct i8042_kbd_priv),
+ .priv_auto = sizeof(struct i8042_kbd_priv),
};
.id = UCLASS_KEYBOARD,
.name = "keyboard",
.pre_probe = keyboard_pre_probe,
- .per_device_auto_alloc_size = sizeof(struct keyboard_priv),
+ .per_device_auto = sizeof(struct keyboard_priv),
};
.of_match = tegra_kbd_ids,
.probe = tegra_kbd_probe,
.ops = &tegra_kbd_ops,
- .priv_auto_alloc_size = sizeof(struct tegra_kbd_priv),
+ .priv_auto = sizeof(struct tegra_kbd_priv),
};
if (ret)
return ret;
uclass_foreach_dev(dev, uc) {
- struct led_uc_plat *uc_plat = dev_get_uclass_platdata(dev);
+ struct led_uc_plat *uc_plat = dev_get_uclass_plat(dev);
/* Ignore the top-level LED node */
if (uc_plat->label && !strcmp(label, uc_plat->label))
UCLASS_DRIVER(led) = {
.id = UCLASS_LED,
.name = "led",
- .per_device_platdata_auto_alloc_size = sizeof(struct led_uc_plat),
+ .per_device_plat_auto = sizeof(struct led_uc_plat),
};
static int bcm6328_led_probe(struct udevice *dev)
{
- struct led_uc_plat *uc_plat = dev_get_uclass_platdata(dev);
+ struct led_uc_plat *uc_plat = dev_get_uclass_plat(dev);
/* Top-level LED node */
if (!uc_plat->label) {
if (ret)
return ret;
- uc_plat = dev_get_uclass_platdata(dev);
+ uc_plat = dev_get_uclass_plat(dev);
uc_plat->label = label;
}
.ops = &bcm6328_led_ops,
.bind = bcm6328_led_bind,
.probe = bcm6328_led_probe,
- .priv_auto_alloc_size = sizeof(struct bcm6328_led_priv),
+ .priv_auto = sizeof(struct bcm6328_led_priv),
};
static int bcm6358_led_probe(struct udevice *dev)
{
- struct led_uc_plat *uc_plat = dev_get_uclass_platdata(dev);
+ struct led_uc_plat *uc_plat = dev_get_uclass_plat(dev);
/* Top-level LED node */
if (!uc_plat->label) {
if (ret)
return ret;
- uc_plat = dev_get_uclass_platdata(dev);
+ uc_plat = dev_get_uclass_plat(dev);
uc_plat->label = label;
}
.of_match = bcm6358_led_ids,
.bind = bcm6358_led_bind,
.probe = bcm6358_led_probe,
- .priv_auto_alloc_size = sizeof(struct bcm6358_led_priv),
+ .priv_auto = sizeof(struct bcm6358_led_priv),
.ops = &bcm6358_led_ops,
};
static int bcm6858_led_probe(struct udevice *dev)
{
- struct led_uc_plat *uc_plat = dev_get_uclass_platdata(dev);
+ struct led_uc_plat *uc_plat = dev_get_uclass_plat(dev);
/* Top-level LED node */
if (!uc_plat->label) {
if (ret)
return ret;
- uc_plat = dev_get_uclass_platdata(dev);
+ uc_plat = dev_get_uclass_plat(dev);
uc_plat->label = label;
}
.of_match = bcm6858_led_ids,
.bind = bcm6858_led_bind,
.probe = bcm6858_led_probe,
- .priv_auto_alloc_size = sizeof(struct bcm6858_led_priv),
+ .priv_auto = sizeof(struct bcm6858_led_priv),
.ops = &bcm6858_led_ops,
};
};
/* LED_control structures */
-struct cortina_led_platdata {
+struct cortina_led_plat {
void __iomem *ctrl_regs;
u16 rate1; /* blink rate setting 0 */
u16 rate2; /* blink rate setting 1 */
.set_state = cortina_led_set_state,
};
-static int ca_led_ofdata_to_platdata(struct udevice *dev)
+static int ca_led_of_to_plat(struct udevice *dev)
{
- struct led_uc_plat *uc_plat = dev_get_uclass_platdata(dev);
+ struct led_uc_plat *uc_plat = dev_get_uclass_plat(dev);
/* Top-level LED node */
if (!uc_plat->label) {
- struct cortina_led_platdata *plt = dev_get_platdata(dev);
+ struct cortina_led_plat *plt = dev_get_plat(dev);
plt->rate1 =
dev_read_u32_default(dev, "Cortina,blink-rate1", 256);
static int cortina_led_probe(struct udevice *dev)
{
- struct led_uc_plat *uc_plat = dev_get_uclass_platdata(dev);
+ struct led_uc_plat *uc_plat = dev_get_uclass_plat(dev);
/* Top-level LED node */
if (!uc_plat->label) {
- struct cortina_led_platdata *platdata = dev_get_platdata(dev);
+ struct cortina_led_plat *plat = dev_get_plat(dev);
u32 reg_value, val;
u16 rate1, rate2;
- if (!platdata->ctrl_regs)
+ if (!plat->ctrl_regs)
return -EINVAL;
reg_value = 0;
reg_value |= LED_CLK_POLARITY;
- rate1 = platdata->rate1;
- rate2 = platdata->rate2;
+ rate1 = plat->rate1;
+ rate2 = plat->rate2;
val = rate1 / 16 - 1;
rate1 = val > LED_MAX_HW_BLINK ?
reg_value |= (rate2 & LED_BLINK_RATE2_MASK) <<
LED_BLINK_RATE2_SHIFT;
- cortina_led_write(platdata->ctrl_regs, reg_value);
+ cortina_led_write(plat->ctrl_regs, reg_value);
} else {
struct cortina_led_cfg *priv = dev_get_priv(dev);
node, &dev);
if (ret)
return ret;
- uc_plat = dev_get_uclass_platdata(dev);
+ uc_plat = dev_get_uclass_plat(dev);
uc_plat->label = label;
}
.name = "ca-leds",
.id = UCLASS_LED,
.of_match = ca_led_ids,
- .ofdata_to_platdata = ca_led_ofdata_to_platdata,
+ .of_to_plat = ca_led_of_to_plat,
.bind = cortina_led_bind,
.probe = cortina_led_probe,
- .platdata_auto_alloc_size = sizeof(struct cortina_led_platdata),
- .priv_auto_alloc_size = sizeof(struct cortina_led_cfg),
+ .plat_auto = sizeof(struct cortina_led_plat),
+ .priv_auto = sizeof(struct cortina_led_cfg),
.ops = &cortina_led_ops,
};
static int led_gpio_probe(struct udevice *dev)
{
- struct led_uc_plat *uc_plat = dev_get_uclass_platdata(dev);
+ struct led_uc_plat *uc_plat = dev_get_uclass_plat(dev);
struct led_gpio_priv *priv = dev_get_priv(dev);
int ret;
node, &dev);
if (ret)
return ret;
- uc_plat = dev_get_uclass_platdata(dev);
+ uc_plat = dev_get_uclass_plat(dev);
uc_plat->label = label;
}
.id = UCLASS_LED,
.of_match = led_gpio_ids,
.ops = &gpio_led_ops,
- .priv_auto_alloc_size = sizeof(struct led_gpio_priv),
+ .priv_auto = sizeof(struct led_gpio_priv),
.bind = led_gpio_bind,
.probe = led_gpio_probe,
.remove = led_gpio_remove,
.of_match = k3_sec_proxy_ids,
.probe = k3_sec_proxy_probe,
.remove = k3_sec_proxy_remove,
- .priv_auto_alloc_size = sizeof(struct k3_sec_proxy_mbox),
+ .priv_auto = sizeof(struct k3_sec_proxy_mbox),
.ops = &k3_sec_proxy_mbox_ops,
};
.name = "sandbox_mbox_test",
.id = UCLASS_MISC,
.of_match = sandbox_mbox_test_ids,
- .priv_auto_alloc_size = sizeof(struct sandbox_mbox_test),
+ .priv_auto = sizeof(struct sandbox_mbox_test),
};
.of_match = sandbox_mbox_ids,
.bind = sandbox_mbox_bind,
.probe = sandbox_mbox_probe,
- .priv_auto_alloc_size = sizeof(struct sandbox_mbox),
+ .priv_auto = sizeof(struct sandbox_mbox),
.ops = &sandbox_mbox_mbox_ops,
};
.id = UCLASS_MAILBOX,
.of_match = stm32_ipcc_ids,
.probe = stm32_ipcc_probe,
- .priv_auto_alloc_size = sizeof(struct stm32_ipcc),
+ .priv_auto = sizeof(struct stm32_ipcc),
.ops = &stm32_ipcc_mbox_ops,
};
.of_match = tegra_hsp_ids,
.bind = tegra_hsp_bind,
.probe = tegra_hsp_probe,
- .priv_auto_alloc_size = sizeof(struct tegra_hsp),
+ .priv_auto = sizeof(struct tegra_hsp),
.ops = &tegra_hsp_mbox_ops,
};
.id = UCLASS_MAILBOX,
.of_match = zynqmp_ipi_ids,
.probe = zynqmp_ipi_probe,
- .priv_auto_alloc_size = sizeof(struct zynqmp_ipi),
+ .priv_auto = sizeof(struct zynqmp_ipi),
.ops = &zynqmp_ipi_mbox_ops,
};
.id = UCLASS_NOP,
.of_match = stm32_fmc2_ebi_match,
.probe = stm32_fmc2_ebi_probe,
- .priv_auto_alloc_size = sizeof(struct stm32_fmc2_ebi),
+ .priv_auto = sizeof(struct stm32_fmc2_ebi),
.bind = dm_scan_fdt_dev,
};
u32 timestamp; /* Timestamp */
};
-struct altera_sysid_platdata {
+struct altera_sysid_plat {
struct altera_sysid_regs *regs;
};
static int altera_sysid_read(struct udevice *dev,
int offset, void *buf, int size)
{
- struct altera_sysid_platdata *plat = dev->platdata;
+ struct altera_sysid_plat *plat = dev->plat;
struct altera_sysid_regs *const regs = plat->regs;
u32 *sysid = buf;
return 0;
}
-static int altera_sysid_ofdata_to_platdata(struct udevice *dev)
+static int altera_sysid_of_to_plat(struct udevice *dev)
{
- struct altera_sysid_platdata *plat = dev_get_platdata(dev);
+ struct altera_sysid_plat *plat = dev_get_plat(dev);
plat->regs = map_physmem(dev_read_addr(dev),
sizeof(struct altera_sysid_regs),
.name = "altera_sysid",
.id = UCLASS_MISC,
.of_match = altera_sysid_ids,
- .ofdata_to_platdata = altera_sysid_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct altera_sysid_platdata),
+ .of_to_plat = altera_sysid_of_to_plat,
+ .plat_auto = sizeof(struct altera_sysid_plat),
.ops = &altera_sysid_ops,
};
return 0;
}
-static int atsha204a_ofdata_to_platdata(struct udevice *dev)
+static int atsha204a_of_to_plat(struct udevice *dev)
{
fdt_addr_t *priv = dev_get_priv(dev);
fdt_addr_t addr;
.name = "atsha204",
.id = UCLASS_MISC,
.of_match = atsha204a_ids,
- .ofdata_to_platdata = atsha204a_ofdata_to_platdata,
- .priv_auto_alloc_size = sizeof(fdt_addr_t),
+ .of_to_plat = atsha204a_of_to_plat,
+ .priv_auto = sizeof(fdt_addr_t),
};
UCLASS_DRIVER(cros_ec) = {
.id = UCLASS_CROS_EC,
.name = "cros-ec",
- .per_device_auto_alloc_size = sizeof(struct cros_ec_dev),
+ .per_device_auto = sizeof(struct cros_ec_dev),
.post_bind = dm_scan_fdt_dev,
.flags = DM_UC_FLAG_ALLOC_PRIV_DMA,
};
static int cros_ec_i2c_packet(struct udevice *udev, int out_bytes, int in_bytes)
{
struct cros_ec_dev *dev = dev_get_uclass_priv(udev);
- struct dm_i2c_chip *chip = dev_get_parent_platdata(udev);
+ struct dm_i2c_chip *chip = dev_get_parent_plat(udev);
struct ec_host_request_i2c *ec_request_i2c =
(struct ec_host_request_i2c *)dev->dout;
struct ec_host_response_i2c *ec_response_i2c =
int dout_len, uint8_t **dinp, int din_len)
{
struct cros_ec_dev *dev = dev_get_uclass_priv(udev);
- struct dm_i2c_chip *chip = dev_get_parent_platdata(udev);
+ struct dm_i2c_chip *chip = dev_get_parent_plat(udev);
struct i2c_msg i2c_msg[2];
/* version8, cmd8, arglen8, out8[dout_len], csum8 */
int out_bytes = dout_len + 4;
.id = UCLASS_CROS_EC,
.of_match = cros_ec_ids,
.probe = cros_ec_probe,
- .priv_auto_alloc_size = sizeof(struct ec_state),
+ .priv_auto = sizeof(struct ec_state),
.ops = &cros_ec_ops,
};
}
#endif
-static int select_fs_dev(struct device_platdata *plat)
+static int select_fs_dev(struct device_plat *plat)
{
int ret;
else
ret = -ENODEV;
} else {
- ret = select_fs_dev(dev->platdata);
+ ret = select_fs_dev(dev->plat);
}
if (ret)
return ret;
}
-static int fs_loader_ofdata_to_platdata(struct udevice *dev)
+static int fs_loader_of_to_plat(struct udevice *dev)
{
u32 phandlepart[2];
ofnode fs_loader_node = dev_ofnode(dev);
if (ofnode_valid(fs_loader_node)) {
- struct device_platdata *plat;
+ struct device_plat *plat;
- plat = dev->platdata;
+ plat = dev->plat;
if (!ofnode_read_u32_array(fs_loader_node,
"phandlepart",
phandlepart, 2)) {
{
#if CONFIG_IS_ENABLED(DM) && CONFIG_IS_ENABLED(BLK)
int ret;
- struct device_platdata *plat = dev->platdata;
+ struct device_plat *plat = dev->plat;
if (plat->phandlepart.phandle) {
ofnode node = ofnode_get_by_phandle(plat->phandlepart.phandle);
.id = UCLASS_FS_FIRMWARE_LOADER,
.of_match = fs_loader_ids,
.probe = fs_loader_probe,
- .ofdata_to_platdata = fs_loader_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct device_platdata),
- .priv_auto_alloc_size = sizeof(struct firmware),
+ .of_to_plat = fs_loader_of_to_plat,
+ .plat_auto = sizeof(struct device_plat),
+ .priv_auto = sizeof(struct firmware),
};
UCLASS_DRIVER(fs_loader) = {
.flags = DM_UC_FLAG_SEQ_ALIAS,
.of_match = gdsys_ioep_ids,
.probe = gdsys_ioep_probe,
- .priv_auto_alloc_size = sizeof(struct gdsys_ioep_priv),
+ .priv_auto = sizeof(struct gdsys_ioep_priv),
};
.ops = &gdsys_rxaui_ctrl_ops,
.of_match = gdsys_rxaui_ctrl_ids,
.probe = gdsys_rxaui_ctrl_probe,
- .priv_auto_alloc_size = sizeof(struct gdsys_rxaui_ctrl_priv),
+ .priv_auto = sizeof(struct gdsys_rxaui_ctrl_priv),
};
.id = UCLASS_SIMPLE_BUS,
.of_match = gdsys_soc_ids,
.probe = gdsys_soc_probe,
- .priv_auto_alloc_size = sizeof(struct gdsys_soc_priv),
+ .priv_auto = sizeof(struct gdsys_soc_priv),
};
.size = i2c_eeprom_std_size,
};
-static int i2c_eeprom_std_ofdata_to_platdata(struct udevice *dev)
+static int i2c_eeprom_std_of_to_plat(struct udevice *dev)
{
struct i2c_eeprom *priv = dev_get_priv(dev);
struct i2c_eeprom_drv_data *data =
if (!name)
continue;
- device_bind_ofnode(dev, DM_GET_DRIVER(i2c_eeprom_partition),
- name, NULL, partition, NULL);
+ device_bind(dev, DM_GET_DRIVER(i2c_eeprom_partition), name,
+ NULL, partition, NULL);
}
return 0;
.of_match = i2c_eeprom_std_ids,
.bind = i2c_eeprom_std_bind,
.probe = i2c_eeprom_std_probe,
- .ofdata_to_platdata = i2c_eeprom_std_ofdata_to_platdata,
- .priv_auto_alloc_size = sizeof(struct i2c_eeprom),
+ .of_to_plat = i2c_eeprom_std_of_to_plat,
+ .priv_auto = sizeof(struct i2c_eeprom),
.ops = &i2c_eeprom_std_ops,
};
return 0;
}
-static int i2c_eeprom_partition_ofdata_to_platdata(struct udevice *dev)
+static int i2c_eeprom_partition_of_to_plat(struct udevice *dev)
{
struct i2c_eeprom_partition *priv = dev_get_priv(dev);
u32 reg[2];
.name = "i2c_eeprom_partition",
.id = UCLASS_I2C_EEPROM,
.probe = i2c_eeprom_partition_probe,
- .ofdata_to_platdata = i2c_eeprom_partition_ofdata_to_platdata,
- .priv_auto_alloc_size = sizeof(struct i2c_eeprom_partition),
+ .of_to_plat = i2c_eeprom_partition_of_to_plat,
+ .priv_auto = sizeof(struct i2c_eeprom_partition),
.ops = &i2c_eeprom_partition_ops,
};
void sandbox_i2c_eeprom_set_test_mode(struct udevice *dev,
enum sandbox_i2c_eeprom_test_mode mode)
{
- struct sandbox_i2c_flash_plat_data *plat = dev_get_platdata(dev);
+ struct sandbox_i2c_flash_plat_data *plat = dev_get_plat(dev);
plat->test_mode = mode;
}
void sandbox_i2c_eeprom_set_offset_len(struct udevice *dev, int offset_len)
{
- struct sandbox_i2c_flash_plat_data *plat = dev_get_platdata(dev);
+ struct sandbox_i2c_flash_plat_data *plat = dev_get_plat(dev);
plat->offset_len = offset_len;
}
void sandbox_i2c_eeprom_set_chip_addr_offset_mask(struct udevice *dev,
uint mask)
{
- struct sandbox_i2c_flash_plat_data *plat = dev_get_platdata(dev);
+ struct sandbox_i2c_flash_plat_data *plat = dev_get_plat(dev);
plat->chip_addr_offset_mask = mask;
}
int nmsgs)
{
struct sandbox_i2c_flash *priv = dev_get_priv(emul);
- struct sandbox_i2c_flash_plat_data *plat = dev_get_platdata(emul);
+ struct sandbox_i2c_flash_plat_data *plat = dev_get_plat(emul);
uint offset = msg->addr & plat->chip_addr_offset_mask;
debug("\n%s\n", __func__);
.xfer = sandbox_i2c_eeprom_xfer,
};
-static int sandbox_i2c_eeprom_ofdata_to_platdata(struct udevice *dev)
+static int sandbox_i2c_eeprom_of_to_plat(struct udevice *dev)
{
- struct sandbox_i2c_flash_plat_data *plat = dev_get_platdata(dev);
+ struct sandbox_i2c_flash_plat_data *plat = dev_get_plat(dev);
plat->size = dev_read_u32_default(dev, "sandbox,size", 32);
plat->filename = dev_read_string(dev, "sandbox,filename");
static int sandbox_i2c_eeprom_probe(struct udevice *dev)
{
- struct sandbox_i2c_flash_plat_data *plat = dev_get_platdata(dev);
+ struct sandbox_i2c_flash_plat_data *plat = dev_get_plat(dev);
struct sandbox_i2c_flash *priv = dev_get_priv(dev);
priv->data = calloc(1, plat->size);
.name = "sandbox_i2c_eeprom_emul",
.id = UCLASS_I2C_EMUL,
.of_match = sandbox_i2c_ids,
- .ofdata_to_platdata = sandbox_i2c_eeprom_ofdata_to_platdata,
+ .of_to_plat = sandbox_i2c_eeprom_of_to_plat,
.probe = sandbox_i2c_eeprom_probe,
.remove = sandbox_i2c_eeprom_remove,
- .priv_auto_alloc_size = sizeof(struct sandbox_i2c_flash),
- .platdata_auto_alloc_size = sizeof(struct sandbox_i2c_flash_plat_data),
+ .priv_auto = sizeof(struct sandbox_i2c_flash),
+ .plat_auto = sizeof(struct sandbox_i2c_flash_plat_data),
.ops = &sandbox_i2c_emul_ops,
};
.id = UCLASS_MISC,
.of_match = ihs_fpga_ids,
.probe = ihs_fpga_probe,
- .priv_auto_alloc_size = sizeof(struct ihs_fpga_priv),
+ .priv_auto = sizeof(struct ihs_fpga_priv),
};
static int imx8_scu_call(struct udevice *dev, int no_resp, void *tx_msg,
int tx_size, void *rx_msg, int rx_size)
{
- struct imx8_scu *plat = dev_get_platdata(dev);
+ struct imx8_scu *plat = dev_get_plat(dev);
sc_err_t result;
int ret;
static int imx8_scu_probe(struct udevice *dev)
{
- struct imx8_scu *plat = dev_get_platdata(dev);
+ struct imx8_scu *plat = dev_get_plat(dev);
fdt_addr_t addr;
debug("%s(dev=%p) (plat=%p)\n", __func__, dev, plat);
.bind = imx8_scu_bind,
.remove = imx8_scu_remove,
.ops = &imx8_scu_ops,
- .platdata_auto_alloc_size = sizeof(struct imx8_scu),
+ .plat_auto = sizeof(struct imx8_scu),
.flags = DM_FLAG_PRE_RELOC,
};
.id = UCLASS_IRQ,
.of_match = sandbox_irq_ids,
.ops = &sandbox_irq_ops,
- .priv_auto_alloc_size = sizeof(struct sandbox_irq_priv),
+ .priv_auto = sizeof(struct sandbox_irq_priv),
};
.of_match = k3_avs_ids,
.id = UCLASS_MISC,
.probe = k3_avs_probe,
- .priv_auto_alloc_size = sizeof(struct k3_avs_privdata),
+ .priv_auto = sizeof(struct k3_avs_privdata),
};
u32 cr;
};
-struct microchip_flexcom_platdata {
+struct microchip_flexcom_plat {
struct microchip_flexcom_regs *regs;
u32 flexcom_mode;
};
-static int microchip_flexcom_ofdata_to_platdata(struct udevice *dev)
+static int microchip_flexcom_of_to_plat(struct udevice *dev)
{
- struct microchip_flexcom_platdata *plat = dev_get_platdata(dev);
+ struct microchip_flexcom_plat *plat = dev_get_plat(dev);
int ret;
plat->regs = map_physmem(dev_read_addr(dev),
.name = "microchip_flexcom",
.id = UCLASS_MISC,
.of_match = microchip_flexcom_ids,
- .ofdata_to_platdata = microchip_flexcom_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct microchip_flexcom_platdata),
+ .of_to_plat = microchip_flexcom_of_to_plat,
+ .plat_auto = sizeof(struct microchip_flexcom_plat),
};
.ops = &misc_sandbox_ops,
.of_match = misc_sandbox_ids,
.probe = misc_sandbox_probe,
- .priv_auto_alloc_size = sizeof(struct misc_sandbox_priv),
+ .priv_auto = sizeof(struct misc_sandbox_priv),
};
.id = UCLASS_MISC,
.of_match = mpc83xx_serdes_ids,
.probe = mpc83xx_serdes_probe,
- .priv_auto_alloc_size = sizeof(struct mpc83xx_serdes_priv),
+ .priv_auto = sizeof(struct mpc83xx_serdes_priv),
};
void *pcr_reg_address(struct udevice *dev, uint offset)
{
- struct p2sb_child_platdata *pplat = dev_get_parent_platdata(dev);
+ struct p2sb_child_plat *pplat = dev_get_parent_plat(dev);
struct udevice *p2sb = dev_get_parent(dev);
struct p2sb_uc_priv *upriv = dev_get_uclass_priv(p2sb);
uintptr_t reg_addr;
int p2sb_get_port_id(struct udevice *dev)
{
- struct p2sb_child_platdata *pplat = dev_get_parent_platdata(dev);
+ struct p2sb_child_plat *pplat = dev_get_parent_plat(dev);
return pplat->pid;
}
int p2sb_set_port_id(struct udevice *dev, int portid)
{
struct udevice *ps2b;
- struct p2sb_child_platdata *pplat;
+ struct p2sb_child_plat *pplat;
if (!CONFIG_IS_ENABLED(OF_PLATDATA))
return -ENOSYS;
* We must allocate this, since when the device was bound it did
* not have a parent.
*/
- dev->parent_platdata = malloc(sizeof(*pplat));
- if (!dev->parent_platdata)
+ dev->parent_plat = malloc(sizeof(*pplat));
+ if (!dev->parent_plat)
return -ENOMEM;
}
- pplat = dev_get_parent_platdata(dev);
+ pplat = dev_get_parent_plat(dev);
pplat->pid = portid;
return 0;
static int p2sb_child_post_bind(struct udevice *dev)
{
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
- struct p2sb_child_platdata *pplat = dev_get_parent_platdata(dev);
+ struct p2sb_child_plat *pplat = dev_get_parent_plat(dev);
int ret;
u32 pid;
UCLASS_DRIVER(p2sb) = {
.id = UCLASS_P2SB,
.name = "p2sb",
- .per_device_auto_alloc_size = sizeof(struct p2sb_uc_priv),
+ .per_device_auto = sizeof(struct p2sb_uc_priv),
.post_bind = p2sb_post_bind,
.child_post_bind = p2sb_child_post_bind,
- .per_child_platdata_auto_alloc_size =
- sizeof(struct p2sb_child_platdata),
+ .per_child_plat_auto = sizeof(struct p2sb_child_plat),
};
#include <p2sb.h>
/**
- * struct p2sb_emul_platdata - platform data for this device
+ * struct p2sb_emul_plat - platform data for this device
*
* @command: Current PCI command value
* @bar: Current base address values
*/
-struct p2sb_emul_platdata {
+struct p2sb_emul_plat {
u16 command;
u32 bar[6];
};
uint offset, ulong *valuep,
enum pci_size_t size)
{
- struct p2sb_emul_platdata *plat = dev_get_platdata(emul);
+ struct p2sb_emul_plat *plat = dev_get_plat(emul);
switch (offset) {
case PCI_COMMAND:
static int sandbox_p2sb_emul_write_config(struct udevice *emul, uint offset,
ulong value, enum pci_size_t size)
{
- struct p2sb_emul_platdata *plat = dev_get_platdata(emul);
+ struct p2sb_emul_plat *plat = dev_get_plat(emul);
switch (offset) {
case PCI_COMMAND:
static int sandbox_p2sb_emul_find_bar(struct udevice *emul, unsigned int addr,
int *barnump, unsigned int *offsetp)
{
- struct p2sb_emul_platdata *plat = dev_get_platdata(emul);
+ struct p2sb_emul_plat *plat = dev_get_plat(emul);
int barnum;
for (barnum = 0; barnum < ARRAY_SIZE(barinfo); barnum++) {
return log_msg_ret("No client", ret);
device_foreach_child(dev, p2sb) {
- struct p2sb_child_platdata *pplat =
- dev_get_parent_platdata(dev);
+ struct p2sb_child_plat *pplat =
+ dev_get_parent_plat(dev);
log_debug(" - child %s, pid %d, want %d\n", dev->name,
pplat->pid, pid);
.id = UCLASS_PCI_EMUL,
.of_match = sandbox_p2sb_emul_ids,
.ops = &sandbox_p2sb_emul_emul_ops,
- .priv_auto_alloc_size = sizeof(struct p2sb_emul_priv),
- .platdata_auto_alloc_size = sizeof(struct p2sb_emul_platdata),
+ .priv_auto = sizeof(struct p2sb_emul_priv),
+ .plat_auto = sizeof(struct p2sb_emul_plat),
};
static struct pci_device_id sandbox_p2sb_emul_supported[] = {
.id = UCLASS_P2SB,
.of_match = sandbox_p2sb_ids,
.probe = sandbox_p2sb_probe,
- .priv_auto_alloc_size = sizeof(struct sandbox_p2sb_priv),
+ .priv_auto = sizeof(struct sandbox_p2sb_priv),
};
/* 0x14 efuse strobe finish control register */
};
-struct rockchip_efuse_platdata {
+struct rockchip_efuse_plat {
void __iomem *base;
struct clk *clk;
};
static int rockchip_rk3399_efuse_read(struct udevice *dev, int offset,
void *buf, int size)
{
- struct rockchip_efuse_platdata *plat = dev_get_platdata(dev);
+ struct rockchip_efuse_plat *plat = dev_get_plat(dev);
struct rockchip_efuse_regs *efuse =
(struct rockchip_efuse_regs *)plat->base;
.read = rockchip_efuse_read,
};
-static int rockchip_efuse_ofdata_to_platdata(struct udevice *dev)
+static int rockchip_efuse_of_to_plat(struct udevice *dev)
{
- struct rockchip_efuse_platdata *plat = dev_get_platdata(dev);
+ struct rockchip_efuse_plat *plat = dev_get_plat(dev);
plat->base = dev_read_addr_ptr(dev);
return 0;
.name = "rockchip_efuse",
.id = UCLASS_MISC,
.of_match = rockchip_efuse_ids,
- .ofdata_to_platdata = rockchip_efuse_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct rockchip_efuse_platdata),
+ .of_to_plat = rockchip_efuse_of_to_plat,
+ .plat_auto = sizeof(struct rockchip_efuse_plat),
.ops = &rockchip_efuse_ops,
};
#define OTPC_TIMEOUT 10000
-struct rockchip_otp_platdata {
+struct rockchip_otp_plat {
void __iomem *base;
unsigned long secure_conf_base;
unsigned long otp_mask_base;
};
-static int rockchip_otp_wait_status(struct rockchip_otp_platdata *otp,
+static int rockchip_otp_wait_status(struct rockchip_otp_plat *otp,
u32 flag)
{
int delay = OTPC_TIMEOUT;
return 0;
}
-static int rockchip_otp_ecc_enable(struct rockchip_otp_platdata *otp,
+static int rockchip_otp_ecc_enable(struct rockchip_otp_plat *otp,
bool enable)
{
int ret = 0;
static int rockchip_px30_otp_read(struct udevice *dev, int offset,
void *buf, int size)
{
- struct rockchip_otp_platdata *otp = dev_get_platdata(dev);
+ struct rockchip_otp_plat *otp = dev_get_plat(dev);
u8 *buffer = buf;
int ret = 0;
.read = rockchip_otp_read,
};
-static int rockchip_otp_ofdata_to_platdata(struct udevice *dev)
+static int rockchip_otp_of_to_plat(struct udevice *dev)
{
- struct rockchip_otp_platdata *otp = dev_get_platdata(dev);
+ struct rockchip_otp_plat *otp = dev_get_plat(dev);
otp->base = dev_read_addr_ptr(dev);
.id = UCLASS_MISC,
.of_match = rockchip_otp_ids,
.ops = &rockchip_otp_ops,
- .ofdata_to_platdata = rockchip_otp_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct rockchip_otp_platdata),
+ .of_to_plat = rockchip_otp_of_to_plat,
+ .plat_auto = sizeof(struct rockchip_otp_plat),
};
int sandbox_adder_read(struct udevice *dev, ulong address, void *data,
enum axi_size_t size)
{
- struct p2sb_child_platdata *pplat = dev_get_parent_platdata(dev);
+ struct p2sb_child_plat *pplat = dev_get_parent_plat(dev);
u32 *val = data;
*val = pplat->pid << 24 | address;
.of_match = sandbox_adder_ids,
.probe = sandbox_adder_probe,
.ops = &sandbox_adder_ops,
- .priv_auto_alloc_size = sizeof(struct sandbox_adder_priv),
+ .priv_auto = sizeof(struct sandbox_adder_priv),
};
u32 pwe; /* Write enable input (defines program cycle) */
};
-struct sifive_otp_platdata {
+struct sifive_otp_plat {
struct sifive_otp_regs __iomem *regs;
u32 total_fuses;
};
static int sifive_otp_read(struct udevice *dev, int offset,
void *buf, int size)
{
- struct sifive_otp_platdata *plat = dev_get_platdata(dev);
+ struct sifive_otp_plat *plat = dev_get_plat(dev);
struct sifive_otp_regs *regs = (struct sifive_otp_regs *)plat->regs;
/* Check if offset and size are multiple of BYTES_PER_FUSE */
static int sifive_otp_write(struct udevice *dev, int offset,
const void *buf, int size)
{
- struct sifive_otp_platdata *plat = dev_get_platdata(dev);
+ struct sifive_otp_plat *plat = dev_get_plat(dev);
struct sifive_otp_regs *regs = (struct sifive_otp_regs *)plat->regs;
/* Check if offset and size are multiple of BYTES_PER_FUSE */
return size;
}
-static int sifive_otp_ofdata_to_platdata(struct udevice *dev)
+static int sifive_otp_of_to_plat(struct udevice *dev)
{
- struct sifive_otp_platdata *plat = dev_get_platdata(dev);
+ struct sifive_otp_plat *plat = dev_get_plat(dev);
int ret;
plat->regs = dev_read_addr_ptr(dev);
.name = "sifive_otp",
.id = UCLASS_MISC,
.of_match = sifive_otp_ids,
- .ofdata_to_platdata = sifive_otp_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct sifive_otp_platdata),
+ .of_to_plat = sifive_otp_of_to_plat,
+ .plat_auto = sizeof(struct sifive_otp_plat),
.ops = &sifive_otp_ops,
};
#include <linux/ctype.h>
/**
- * struct swap_case_platdata - platform data for this device
+ * struct swap_case_plat - platform data for this device
*
* @command: Current PCI command value
* @bar: Current base address values
*/
-struct swap_case_platdata {
+struct swap_case_plat {
u16 command;
u32 bar[6];
};
uint offset, ulong *valuep,
enum pci_size_t size)
{
- struct swap_case_platdata *plat = dev_get_platdata(emul);
+ struct swap_case_plat *plat = dev_get_plat(emul);
/*
* The content of the EA capability structure is handled elsewhere to
static int sandbox_swap_case_write_config(struct udevice *emul, uint offset,
ulong value, enum pci_size_t size)
{
- struct swap_case_platdata *plat = dev_get_platdata(emul);
+ struct swap_case_plat *plat = dev_get_plat(emul);
switch (offset) {
case PCI_COMMAND:
static int sandbox_swap_case_find_bar(struct udevice *emul, unsigned int addr,
int *barnump, unsigned int *offsetp)
{
- struct swap_case_platdata *plat = dev_get_platdata(emul);
+ struct swap_case_plat *plat = dev_get_plat(emul);
int barnum;
for (barnum = 0; barnum < ARRAY_SIZE(barinfo); barnum++) {
.id = UCLASS_PCI_EMUL,
.of_match = sandbox_swap_case_ids,
.ops = &sandbox_swap_case_emul_ops,
- .priv_auto_alloc_size = sizeof(struct swap_case_priv),
- .platdata_auto_alloc_size = sizeof(struct swap_case_platdata),
+ .priv_auto = sizeof(struct swap_case_priv),
+ .plat_auto = sizeof(struct swap_case_plat),
};
static struct pci_device_id sandbox_swap_case_supported[] = {
.probe = tegra186_bpmp_probe,
.remove = tegra186_bpmp_remove,
.ops = &tegra186_bpmp_ops,
- .priv_auto_alloc_size = sizeof(struct tegra186_bpmp),
+ .priv_auto = sizeof(struct tegra186_bpmp),
};
static int am654_sdhci_set_ios_post(struct sdhci_host *host)
{
struct udevice *dev = host->mmc->dev;
- struct am654_sdhci_plat *plat = dev_get_platdata(dev);
+ struct am654_sdhci_plat *plat = dev_get_plat(dev);
unsigned int speed = host->mmc->clock;
int sel50, sel100, freqsel;
u32 otap_del_sel;
static int am654_sdhci_deferred_probe(struct sdhci_host *host)
{
struct udevice *dev = host->mmc->dev;
- struct am654_sdhci_plat *plat = dev_get_platdata(dev);
+ struct am654_sdhci_plat *plat = dev_get_plat(dev);
unsigned long start;
int val;
static int j721e_4bit_sdhci_set_ios_post(struct sdhci_host *host)
{
struct udevice *dev = host->mmc->dev;
- struct am654_sdhci_plat *plat = dev_get_platdata(dev);
+ struct am654_sdhci_plat *plat = dev_get_plat(dev);
u32 otap_del_sel, mask, val;
otap_del_sel = plat->otap_del_sel[host->mmc->selected_mode];
static int sdhci_am654_get_otap_delay(struct udevice *dev,
struct mmc_config *cfg)
{
- struct am654_sdhci_plat *plat = dev_get_platdata(dev);
+ struct am654_sdhci_plat *plat = dev_get_plat(dev);
int ret;
int i;
{
struct am654_driver_data *drv_data =
(struct am654_driver_data *)dev_get_driver_data(dev);
- struct am654_sdhci_plat *plat = dev_get_platdata(dev);
+ struct am654_sdhci_plat *plat = dev_get_plat(dev);
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct sdhci_host *host = dev_get_priv(dev);
struct mmc_config *cfg = &plat->cfg;
return 0;
}
-static int am654_sdhci_ofdata_to_platdata(struct udevice *dev)
+static int am654_sdhci_of_to_plat(struct udevice *dev)
{
- struct am654_sdhci_plat *plat = dev_get_platdata(dev);
+ struct am654_sdhci_plat *plat = dev_get_plat(dev);
struct sdhci_host *host = dev_get_priv(dev);
struct mmc_config *cfg = &plat->cfg;
u32 drv_strength;
{
struct am654_driver_data *drv_data =
(struct am654_driver_data *)dev_get_driver_data(dev);
- struct am654_sdhci_plat *plat = dev_get_platdata(dev);
+ struct am654_sdhci_plat *plat = dev_get_plat(dev);
plat->flags = drv_data->flags;
.name = "am654_sdhci",
.id = UCLASS_MMC,
.of_match = am654_sdhci_ids,
- .ofdata_to_platdata = am654_sdhci_ofdata_to_platdata,
+ .of_to_plat = am654_sdhci_of_to_plat,
.ops = &sdhci_ops,
.bind = am654_sdhci_bind,
.probe = am654_sdhci_probe,
- .priv_auto_alloc_size = sizeof(struct sdhci_host),
- .platdata_auto_alloc_size = sizeof(struct am654_sdhci_plat),
+ .priv_auto = sizeof(struct sdhci_host),
+ .plat_auto = sizeof(struct am654_sdhci_plat),
};
static int arm_pl180_mmc_probe(struct udevice *dev)
{
- struct arm_pl180_mmc_plat *pdata = dev_get_platdata(dev);
+ struct arm_pl180_mmc_plat *pdata = dev_get_plat(dev);
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct mmc *mmc = &pdata->mmc;
struct pl180_mmc_host *host = dev->priv;
int arm_pl180_mmc_bind(struct udevice *dev)
{
- struct arm_pl180_mmc_plat *plat = dev_get_platdata(dev);
+ struct arm_pl180_mmc_plat *plat = dev_get_plat(dev);
return mmc_bind(dev, &plat->mmc, &plat->cfg);
}
.get_cd = dm_mmc_getcd,
};
-static int arm_pl180_mmc_ofdata_to_platdata(struct udevice *dev)
+static int arm_pl180_mmc_of_to_plat(struct udevice *dev)
{
struct pl180_mmc_host *host = dev->priv;
fdt_addr_t addr;
.of_match = arm_pl180_mmc_match,
.ops = &arm_pl180_dm_mmc_ops,
.probe = arm_pl180_mmc_probe,
- .ofdata_to_platdata = arm_pl180_mmc_ofdata_to_platdata,
+ .of_to_plat = arm_pl180_mmc_of_to_plat,
.bind = arm_pl180_mmc_bind,
- .priv_auto_alloc_size = sizeof(struct pl180_mmc_host),
- .platdata_auto_alloc_size = sizeof(struct arm_pl180_mmc_plat),
+ .priv_auto = sizeof(struct pl180_mmc_host),
+ .plat_auto = sizeof(struct arm_pl180_mmc_plat),
};
#endif
static int aspeed_sdhci_probe(struct udevice *dev)
{
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
- struct aspeed_sdhci_plat *plat = dev_get_platdata(dev);
+ struct aspeed_sdhci_plat *plat = dev_get_plat(dev);
struct sdhci_host *host = dev_get_priv(dev);
u32 max_clk;
struct clk clk;
static int aspeed_sdhci_bind(struct udevice *dev)
{
- struct aspeed_sdhci_plat *plat = dev_get_platdata(dev);
+ struct aspeed_sdhci_plat *plat = dev_get_plat(dev);
return sdhci_bind(dev, &plat->mmc, &plat->cfg);
}
.ops = &sdhci_ops,
.bind = aspeed_sdhci_bind,
.probe = aspeed_sdhci_probe,
- .priv_auto_alloc_size = sizeof(struct sdhci_host),
- .platdata_auto_alloc_size = sizeof(struct aspeed_sdhci_plat),
+ .priv_auto = sizeof(struct sdhci_host),
+ .plat_auto = sizeof(struct aspeed_sdhci_plat),
};
static int atmel_sdhci_probe(struct udevice *dev)
{
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
- struct atmel_sdhci_plat *plat = dev_get_platdata(dev);
+ struct atmel_sdhci_plat *plat = dev_get_plat(dev);
struct sdhci_host *host = dev_get_priv(dev);
u32 max_clk;
struct clk clk;
static int atmel_sdhci_bind(struct udevice *dev)
{
- struct atmel_sdhci_plat *plat = dev_get_platdata(dev);
+ struct atmel_sdhci_plat *plat = dev_get_plat(dev);
return sdhci_bind(dev, &plat->mmc, &plat->cfg);
}
.ops = &sdhci_ops,
.bind = atmel_sdhci_bind,
.probe = atmel_sdhci_probe,
- .priv_auto_alloc_size = sizeof(struct sdhci_host),
- .platdata_auto_alloc_size = sizeof(struct atmel_sdhci_plat),
+ .priv_auto = sizeof(struct sdhci_host),
+ .plat_auto = sizeof(struct atmel_sdhci_plat),
};
#endif
static int bcm2835_sdhci_bind(struct udevice *dev)
{
- struct bcm2835_sdhci_plat *plat = dev_get_platdata(dev);
+ struct bcm2835_sdhci_plat *plat = dev_get_plat(dev);
return sdhci_bind(dev, &plat->mmc, &plat->cfg);
}
static int bcm2835_sdhci_probe(struct udevice *dev)
{
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
- struct bcm2835_sdhci_plat *plat = dev_get_platdata(dev);
+ struct bcm2835_sdhci_plat *plat = dev_get_plat(dev);
struct bcm2835_sdhci_host *priv = dev_get_priv(dev);
struct sdhci_host *host = &priv->host;
fdt_addr_t base;
.of_match = bcm2835_sdhci_match,
.bind = bcm2835_sdhci_bind,
.probe = bcm2835_sdhci_probe,
- .priv_auto_alloc_size = sizeof(struct bcm2835_sdhci_host),
- .platdata_auto_alloc_size = sizeof(struct bcm2835_sdhci_plat),
+ .priv_auto = sizeof(struct bcm2835_sdhci_host),
+ .plat_auto = sizeof(struct bcm2835_sdhci_plat),
.ops = &sdhci_ops,
};
static int bcm2835_probe(struct udevice *dev)
{
- struct bcm2835_plat *plat = dev_get_platdata(dev);
+ struct bcm2835_plat *plat = dev_get_plat(dev);
struct bcm2835_host *host = dev_get_priv(dev);
struct mmc *mmc = mmc_get_mmc_dev(dev);
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
static int bcm2835_bind(struct udevice *dev)
{
- struct bcm2835_plat *plat = dev_get_platdata(dev);
+ struct bcm2835_plat *plat = dev_get_plat(dev);
return mmc_bind(dev, &plat->mmc, &plat->cfg);
}
.of_match = bcm2835_match,
.bind = bcm2835_bind,
.probe = bcm2835_probe,
- .priv_auto_alloc_size = sizeof(struct bcm2835_host),
- .platdata_auto_alloc_size = sizeof(struct bcm2835_plat),
+ .priv_auto = sizeof(struct bcm2835_host),
+ .plat_auto = sizeof(struct bcm2835_plat),
.ops = &bcm2835_ops,
};
static int sdhci_bcmstb_bind(struct udevice *dev)
{
- struct sdhci_bcmstb_plat *plat = dev_get_platdata(dev);
+ struct sdhci_bcmstb_plat *plat = dev_get_plat(dev);
return sdhci_bind(dev, &plat->mmc, &plat->cfg);
}
static int sdhci_bcmstb_probe(struct udevice *dev)
{
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
- struct sdhci_bcmstb_plat *plat = dev_get_platdata(dev);
+ struct sdhci_bcmstb_plat *plat = dev_get_plat(dev);
struct sdhci_host *host = dev_get_priv(dev);
fdt_addr_t base;
int ret;
.ops = &sdhci_ops,
.bind = sdhci_bcmstb_bind,
.probe = sdhci_bcmstb_probe,
- .priv_auto_alloc_size = sizeof(struct sdhci_host),
- .platdata_auto_alloc_size = sizeof(struct sdhci_bcmstb_plat),
+ .priv_auto = sizeof(struct sdhci_host),
+ .plat_auto = sizeof(struct sdhci_bcmstb_plat),
};
return SD_SCLK_MAX / clk_div / (host->div + 1);
}
-static int ca_dwmmc_ofdata_to_platdata(struct udevice *dev)
+static int ca_dwmmc_of_to_plat(struct udevice *dev)
{
struct ca_dwmmc_priv_data *priv = dev_get_priv(dev);
struct dwmci_host *host = &priv->host;
static int ca_dwmmc_probe(struct udevice *dev)
{
- struct ca_mmc_plat *plat = dev_get_platdata(dev);
+ struct ca_mmc_plat *plat = dev_get_plat(dev);
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct ca_dwmmc_priv_data *priv = dev_get_priv(dev);
struct dwmci_host *host = &priv->host;
static int ca_dwmmc_bind(struct udevice *dev)
{
- struct ca_mmc_plat *plat = dev_get_platdata(dev);
+ struct ca_mmc_plat *plat = dev_get_plat(dev);
return dwmci_bind(dev, &plat->mmc, &plat->cfg);
}
.name = "cortina_dwmmc",
.id = UCLASS_MMC,
.of_match = ca_dwmmc_ids,
- .ofdata_to_platdata = ca_dwmmc_ofdata_to_platdata,
+ .of_to_plat = ca_dwmmc_of_to_plat,
.bind = ca_dwmmc_bind,
.ops = &ca_dwmci_dm_ops,
.probe = ca_dwmmc_probe,
- .priv_auto_alloc_size = sizeof(struct ca_dwmmc_priv_data),
- .platdata_auto_alloc_size = sizeof(struct ca_mmc_plat),
+ .priv_auto = sizeof(struct ca_dwmmc_priv_data),
+ .plat_auto = sizeof(struct ca_mmc_plat),
};
static int davinci_mmc_probe(struct udevice *dev)
{
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
- struct davinci_mmc_plat *plat = dev_get_platdata(dev);
+ struct davinci_mmc_plat *plat = dev_get_plat(dev);
struct davinci_mmc_priv *priv = dev_get_priv(dev);
priv->reg_base = plat->reg_base;
static int davinci_mmc_bind(struct udevice *dev)
{
- struct davinci_mmc_plat *plat = dev_get_platdata(dev);
+ struct davinci_mmc_plat *plat = dev_get_plat(dev);
return mmc_bind(dev, &plat->mmc, &plat->cfg);
}
#if CONFIG_IS_ENABLED(OF_CONTROL)
-static int davinci_mmc_ofdata_to_platdata(struct udevice *dev)
+static int davinci_mmc_of_to_plat(struct udevice *dev)
{
- struct davinci_mmc_plat *plat = dev_get_platdata(dev);
+ struct davinci_mmc_plat *plat = dev_get_plat(dev);
struct mmc_config *cfg = &plat->cfg;
plat->reg_base = (struct davinci_mmc_regs *)dev_read_addr(dev);
.id = UCLASS_MMC,
#if CONFIG_IS_ENABLED(OF_CONTROL)
.of_match = davinci_mmc_ids,
- .platdata_auto_alloc_size = sizeof(struct davinci_mmc_plat),
- .ofdata_to_platdata = davinci_mmc_ofdata_to_platdata,
+ .plat_auto = sizeof(struct davinci_mmc_plat),
+ .of_to_plat = davinci_mmc_of_to_plat,
#endif
#if CONFIG_BLK
.bind = davinci_mmc_bind,
#endif
.probe = davinci_mmc_probe,
.ops = &davinci_mmc_ops,
- .priv_auto_alloc_size = sizeof(struct davinci_mmc_priv),
+ .priv_auto = sizeof(struct davinci_mmc_priv),
#if !CONFIG_IS_ENABLED(OF_CONTROL)
.flags = DM_FLAG_PRE_RELOC,
#endif
#ifdef CONFIG_DM_MMC
static int exynos_dwmmc_probe(struct udevice *dev)
{
- struct exynos_mmc_plat *plat = dev_get_platdata(dev);
+ struct exynos_mmc_plat *plat = dev_get_plat(dev);
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct dwmci_exynos_priv_data *priv = dev_get_priv(dev);
struct dwmci_host *host = &priv->host;
static int exynos_dwmmc_bind(struct udevice *dev)
{
- struct exynos_mmc_plat *plat = dev_get_platdata(dev);
+ struct exynos_mmc_plat *plat = dev_get_plat(dev);
return dwmci_bind(dev, &plat->mmc, &plat->cfg);
}
.bind = exynos_dwmmc_bind,
.ops = &dm_dwmci_ops,
.probe = exynos_dwmmc_probe,
- .priv_auto_alloc_size = sizeof(struct dwmci_exynos_priv_data),
- .platdata_auto_alloc_size = sizeof(struct exynos_mmc_plat),
+ .priv_auto = sizeof(struct dwmci_exynos_priv_data),
+ .plat_auto = sizeof(struct exynos_mmc_plat),
};
#endif
static int fsl_esdhc_probe(struct udevice *dev)
{
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
- struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
+ struct fsl_esdhc_plat *plat = dev_get_plat(dev);
struct fsl_esdhc_priv *priv = dev_get_priv(dev);
u32 caps, hostver;
fdt_addr_t addr;
static int fsl_esdhc_get_cd(struct udevice *dev)
{
- struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
+ struct fsl_esdhc_plat *plat = dev_get_plat(dev);
struct fsl_esdhc_priv *priv = dev_get_priv(dev);
if (plat->cfg.host_caps & MMC_CAP_NONREMOVABLE)
static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
struct mmc_data *data)
{
- struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
+ struct fsl_esdhc_plat *plat = dev_get_plat(dev);
struct fsl_esdhc_priv *priv = dev_get_priv(dev);
return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data);
static int fsl_esdhc_set_ios(struct udevice *dev)
{
- struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
+ struct fsl_esdhc_plat *plat = dev_get_plat(dev);
struct fsl_esdhc_priv *priv = dev_get_priv(dev);
return esdhc_set_ios_common(priv, &plat->mmc);
static int fsl_esdhc_reinit(struct udevice *dev)
{
- struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
+ struct fsl_esdhc_plat *plat = dev_get_plat(dev);
struct fsl_esdhc_priv *priv = dev_get_priv(dev);
return esdhc_init_common(priv, &plat->mmc);
#ifdef MMC_SUPPORTS_TUNING
static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode)
{
- struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
+ struct fsl_esdhc_plat *plat = dev_get_plat(dev);
struct fsl_esdhc_priv *priv = dev_get_priv(dev);
struct fsl_esdhc *regs = priv->esdhc_regs;
u32 val, irqstaten;
static int fsl_esdhc_bind(struct udevice *dev)
{
- struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
+ struct fsl_esdhc_plat *plat = dev_get_plat(dev);
return mmc_bind(dev, &plat->mmc, &plat->cfg);
}
.ops = &fsl_esdhc_ops,
.bind = fsl_esdhc_bind,
.probe = fsl_esdhc_probe,
- .platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat),
- .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),
+ .plat_auto = sizeof(struct fsl_esdhc_plat),
+ .priv_auto = sizeof(struct fsl_esdhc_priv),
};
#endif
static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode)
{
- struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
+ struct fsl_esdhc_plat *plat = dev_get_plat(dev);
struct fsl_esdhc_priv *priv = dev_get_priv(dev);
struct fsl_esdhc *regs = priv->esdhc_regs;
struct mmc *mmc = &plat->mmc;
{
}
-static int fsl_esdhc_ofdata_to_platdata(struct udevice *dev)
+static int fsl_esdhc_of_to_plat(struct udevice *dev)
{
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct fsl_esdhc_priv *priv = dev_get_priv(dev);
static int fsl_esdhc_probe(struct udevice *dev)
{
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
- struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
+ struct fsl_esdhc_plat *plat = dev_get_plat(dev);
struct fsl_esdhc_priv *priv = dev_get_priv(dev);
struct esdhc_soc_data *data =
(struct esdhc_soc_data *)dev_get_driver_data(dev);
static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
struct mmc_data *data)
{
- struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
+ struct fsl_esdhc_plat *plat = dev_get_plat(dev);
struct fsl_esdhc_priv *priv = dev_get_priv(dev);
return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data);
static int fsl_esdhc_set_ios(struct udevice *dev)
{
- struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
+ struct fsl_esdhc_plat *plat = dev_get_plat(dev);
struct fsl_esdhc_priv *priv = dev_get_priv(dev);
return esdhc_set_ios_common(priv, &plat->mmc);
#if CONFIG_IS_ENABLED(BLK)
static int fsl_esdhc_bind(struct udevice *dev)
{
- struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
+ struct fsl_esdhc_plat *plat = dev_get_plat(dev);
return mmc_bind(dev, &plat->mmc, &plat->cfg);
}
.name = "fsl_esdhc",
.id = UCLASS_MMC,
.of_match = fsl_esdhc_ids,
- .ofdata_to_platdata = fsl_esdhc_ofdata_to_platdata,
+ .of_to_plat = fsl_esdhc_of_to_plat,
.ops = &fsl_esdhc_ops,
#if CONFIG_IS_ENABLED(BLK)
.bind = fsl_esdhc_bind,
#endif
.probe = fsl_esdhc_probe,
- .platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat),
- .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),
+ .plat_auto = sizeof(struct fsl_esdhc_plat),
+ .priv_auto = sizeof(struct fsl_esdhc_priv),
};
U_BOOT_DRIVER_ALIAS(fsl_esdhc, fsl_imx6q_usdhc)
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
}
-static int ftsdc010_mmc_ofdata_to_platdata(struct udevice *dev)
+static int ftsdc010_mmc_of_to_plat(struct udevice *dev)
{
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct ftsdc_priv *priv = dev_get_priv(dev);
static int ftsdc010_mmc_probe(struct udevice *dev)
{
- struct ftsdc010_plat *plat = dev_get_platdata(dev);
+ struct ftsdc010_plat *plat = dev_get_plat(dev);
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct ftsdc_priv *priv = dev_get_priv(dev);
struct ftsdc010_chip *chip = &priv->chip;
int ftsdc010_mmc_bind(struct udevice *dev)
{
- struct ftsdc010_plat *plat = dev_get_platdata(dev);
+ struct ftsdc010_plat *plat = dev_get_plat(dev);
return mmc_bind(dev, &plat->mmc, &plat->cfg);
}
.name = "ftsdc010_mmc",
.id = UCLASS_MMC,
.of_match = ftsdc010_mmc_ids,
- .ofdata_to_platdata = ftsdc010_mmc_ofdata_to_platdata,
+ .of_to_plat = ftsdc010_mmc_of_to_plat,
.ops = &dm_ftsdc010_mmc_ops,
.bind = ftsdc010_mmc_bind,
.probe = ftsdc010_mmc_probe,
- .priv_auto_alloc_size = sizeof(struct ftsdc_priv),
- .platdata_auto_alloc_size = sizeof(struct ftsdc010_plat),
+ .priv_auto = sizeof(struct ftsdc_priv),
+ .plat_auto = sizeof(struct ftsdc010_plat),
};
#ifdef CONFIG_DM_MMC
static void mci_set_mode(struct udevice *dev, u32 hz, u32 blklen)
{
- struct atmel_mci_plat *plat = dev_get_platdata(dev);
+ struct atmel_mci_plat *plat = dev_get_plat(dev);
struct atmel_mci_priv *priv = dev_get_priv(dev);
struct mmc *mmc = &plat->mmc;
u32 bus_hz = priv->bus_clk_rate;
static int atmel_mci_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
struct mmc_data *data)
{
- struct atmel_mci_plat *plat = dev_get_platdata(dev);
+ struct atmel_mci_plat *plat = dev_get_plat(dev);
struct atmel_mci_priv *priv = dev_get_priv(dev);
atmel_mci_t *mci = plat->mci;
#else
#ifdef CONFIG_DM_MMC
static int atmel_mci_set_ios(struct udevice *dev)
{
- struct atmel_mci_plat *plat = dev_get_platdata(dev);
+ struct atmel_mci_plat *plat = dev_get_plat(dev);
struct mmc *mmc = mmc_get_mmc_dev(dev);
atmel_mci_t *mci = plat->mci;
#else
#ifdef CONFIG_DM_MMC
static int atmel_mci_hw_init(struct udevice *dev)
{
- struct atmel_mci_plat *plat = dev_get_platdata(dev);
+ struct atmel_mci_plat *plat = dev_get_plat(dev);
atmel_mci_t *mci = plat->mci;
#else
/* Entered into mmc structure during driver init */
static void atmel_mci_setup_cfg(struct udevice *dev)
{
- struct atmel_mci_plat *plat = dev_get_platdata(dev);
+ struct atmel_mci_plat *plat = dev_get_plat(dev);
struct atmel_mci_priv *priv = dev_get_priv(dev);
struct mmc_config *cfg;
u32 version;
static int atmel_mci_probe(struct udevice *dev)
{
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
- struct atmel_mci_plat *plat = dev_get_platdata(dev);
+ struct atmel_mci_plat *plat = dev_get_plat(dev);
struct mmc *mmc;
int ret;
static int atmel_mci_bind(struct udevice *dev)
{
- struct atmel_mci_plat *plat = dev_get_platdata(dev);
+ struct atmel_mci_plat *plat = dev_get_plat(dev);
return mmc_bind(dev, &plat->mmc, &plat->cfg);
}
.of_match = atmel_mci_ids,
.bind = atmel_mci_bind,
.probe = atmel_mci_probe,
- .platdata_auto_alloc_size = sizeof(struct atmel_mci_plat),
- .priv_auto_alloc_size = sizeof(struct atmel_mci_priv),
+ .plat_auto = sizeof(struct atmel_mci_plat),
+ .priv_auto = sizeof(struct atmel_mci_priv),
.ops = &atmel_mci_mmc_ops,
};
#endif
bool use_fifo;
};
-static int hi6220_dwmmc_ofdata_to_platdata(struct udevice *dev)
+static int hi6220_dwmmc_of_to_plat(struct udevice *dev)
{
struct hi6220_dwmmc_priv_data *priv = dev_get_priv(dev);
struct dwmci_host *host = &priv->host;
static int hi6220_dwmmc_probe(struct udevice *dev)
{
- struct hi6220_dwmmc_plat *plat = dev_get_platdata(dev);
+ struct hi6220_dwmmc_plat *plat = dev_get_plat(dev);
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct hi6220_dwmmc_priv_data *priv = dev_get_priv(dev);
struct dwmci_host *host = &priv->host;
static int hi6220_dwmmc_bind(struct udevice *dev)
{
- struct hi6220_dwmmc_plat *plat = dev_get_platdata(dev);
+ struct hi6220_dwmmc_plat *plat = dev_get_plat(dev);
int ret;
ret = dwmci_bind(dev, &plat->mmc, &plat->cfg);
.name = "hi6220_dwmmc",
.id = UCLASS_MMC,
.of_match = hi6220_dwmmc_ids,
- .ofdata_to_platdata = hi6220_dwmmc_ofdata_to_platdata,
+ .of_to_plat = hi6220_dwmmc_of_to_plat,
.ops = &dm_dwmci_ops,
.bind = hi6220_dwmmc_bind,
.probe = hi6220_dwmmc_probe,
- .priv_auto_alloc_size = sizeof(struct hi6220_dwmmc_priv_data),
- .platdata_auto_alloc_size = sizeof(struct hi6220_dwmmc_plat),
+ .priv_auto = sizeof(struct hi6220_dwmmc_priv_data),
+ .plat_auto = sizeof(struct hi6220_dwmmc_plat),
};
static int iproc_sdhci_probe(struct udevice *dev)
{
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
- struct iproc_sdhci_plat *plat = dev_get_platdata(dev);
+ struct iproc_sdhci_plat *plat = dev_get_plat(dev);
struct sdhci_host *host = dev_get_priv(dev);
struct sdhci_iproc_host *iproc_host;
int node = dev_of_offset(dev);
static int iproc_sdhci_bind(struct udevice *dev)
{
- struct iproc_sdhci_plat *plat = dev_get_platdata(dev);
+ struct iproc_sdhci_plat *plat = dev_get_plat(dev);
return sdhci_bind(dev, &plat->mmc, &plat->cfg);
}
.ops = &sdhci_ops,
.bind = iproc_sdhci_bind,
.probe = iproc_sdhci_probe,
- .priv_auto_alloc_size = sizeof(struct sdhci_host),
- .platdata_auto_alloc_size = sizeof(struct iproc_sdhci_plat),
+ .priv_auto = sizeof(struct sdhci_host),
+ .plat_auto = sizeof(struct iproc_sdhci_plat),
};
.set_ios = jz_mmc_dm_set_ios,
};
-static int jz_mmc_ofdata_to_platdata(struct udevice *dev)
+static int jz_mmc_of_to_plat(struct udevice *dev)
{
struct jz_mmc_priv *priv = dev_get_priv(dev);
- struct jz_mmc_plat *plat = dev_get_platdata(dev);
+ struct jz_mmc_plat *plat = dev_get_plat(dev);
struct mmc_config *cfg;
int ret;
static int jz_mmc_bind(struct udevice *dev)
{
- struct jz_mmc_plat *plat = dev_get_platdata(dev);
+ struct jz_mmc_plat *plat = dev_get_plat(dev);
return mmc_bind(dev, &plat->mmc, &plat->cfg);
}
{
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct jz_mmc_priv *priv = dev_get_priv(dev);
- struct jz_mmc_plat *plat = dev_get_platdata(dev);
+ struct jz_mmc_plat *plat = dev_get_plat(dev);
plat->mmc.priv = priv;
upriv->mmc = &plat->mmc;
.name = "jz_mmc",
.id = UCLASS_MMC,
.of_match = jz_mmc_ids,
- .ofdata_to_platdata = jz_mmc_ofdata_to_platdata,
+ .of_to_plat = jz_mmc_of_to_plat,
.bind = jz_mmc_bind,
.probe = jz_mmc_probe,
- .priv_auto_alloc_size = sizeof(struct jz_mmc_priv),
- .platdata_auto_alloc_size = sizeof(struct jz_mmc_plat),
+ .priv_auto = sizeof(struct jz_mmc_priv),
+ .plat_auto = sizeof(struct jz_mmc_plat),
.ops = &jz_msc_ops,
};
#endif /* CONFIG_DM_MMC */
static inline void *get_regbase(const struct mmc *mmc)
{
- struct meson_mmc_platdata *pdata = mmc->priv;
+ struct meson_mmc_plat *pdata = mmc->priv;
return pdata->regbase;
}
static void meson_mmc_setup_addr(struct mmc *mmc, struct mmc_data *data)
{
- struct meson_mmc_platdata *pdata = mmc->priv;
+ struct meson_mmc_plat *pdata = mmc->priv;
unsigned int data_size;
uint32_t data_addr = 0;
struct mmc_data *data)
{
struct mmc *mmc = mmc_get_mmc_dev(dev);
- struct meson_mmc_platdata *pdata = mmc->priv;
+ struct meson_mmc_plat *pdata = mmc->priv;
uint32_t status;
ulong start;
int ret = 0;
.set_ios = meson_dm_mmc_set_ios,
};
-static int meson_mmc_ofdata_to_platdata(struct udevice *dev)
+static int meson_mmc_of_to_plat(struct udevice *dev)
{
- struct meson_mmc_platdata *pdata = dev_get_platdata(dev);
+ struct meson_mmc_plat *pdata = dev_get_plat(dev);
fdt_addr_t addr;
addr = dev_read_addr(dev);
static int meson_mmc_probe(struct udevice *dev)
{
- struct meson_mmc_platdata *pdata = dev_get_platdata(dev);
+ struct meson_mmc_plat *pdata = dev_get_plat(dev);
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct mmc *mmc = &pdata->mmc;
struct mmc_config *cfg = &pdata->cfg;
int meson_mmc_bind(struct udevice *dev)
{
- struct meson_mmc_platdata *pdata = dev_get_platdata(dev);
+ struct meson_mmc_plat *pdata = dev_get_plat(dev);
return mmc_bind(dev, &pdata->mmc, &pdata->cfg);
}
.ops = &meson_dm_mmc_ops,
.probe = meson_mmc_probe,
.bind = meson_mmc_bind,
- .ofdata_to_platdata = meson_mmc_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct meson_mmc_platdata),
+ .of_to_plat = meson_mmc_of_to_plat,
+ .plat_auto = sizeof(struct meson_mmc_plat),
};
#ifdef CONFIG_PWRSEQ
#define MESON_SD_EMMC_CMD_RSP2 0x64
#define MESON_SD_EMMC_CMD_RSP3 0x68
-struct meson_mmc_platdata {
+struct meson_mmc_plat {
struct mmc_config cfg;
struct mmc mmc;
void *regbase;
device_find_first_child(mmc->dev, &dev);
if (!dev)
return NULL;
- desc = dev_get_uclass_platdata(dev);
+ desc = dev_get_uclass_plat(dev);
return desc;
}
debug("Cannot create block device\n");
return ret;
}
- bdesc = dev_get_uclass_platdata(bdev);
+ bdesc = dev_get_uclass_plat(bdev);
mmc->cfg = cfg;
mmc->priv = dev;
{
struct udevice *mmc_dev = dev_get_parent(bdev);
struct mmc *mmc = mmc_get_mmc_dev(mmc_dev);
- struct blk_desc *desc = dev_get_uclass_platdata(bdev);
+ struct blk_desc *desc = dev_get_uclass_plat(bdev);
int ret;
if (desc->hwpart == hwpart)
.id = UCLASS_MMC,
.name = "mmc",
.flags = DM_UC_FLAG_SEQ_ALIAS,
- .per_device_auto_alloc_size = sizeof(struct mmc_uclass_priv),
+ .per_device_auto = sizeof(struct mmc_uclass_priv),
};
#endif
{
#if CONFIG_IS_ENABLED(BLK)
- struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
+ struct blk_desc *block_dev = dev_get_uclass_plat(dev);
#endif
int dev_num = block_dev->devnum;
int err;
static int mmc_spi_probe(struct udevice *dev)
{
struct mmc_spi_priv *priv = dev_get_priv(dev);
- struct mmc_spi_plat *plat = dev_get_platdata(dev);
+ struct mmc_spi_plat *plat = dev_get_plat(dev);
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
char *name;
static int mmc_spi_bind(struct udevice *dev)
{
- struct mmc_spi_plat *plat = dev_get_platdata(dev);
+ struct mmc_spi_plat *plat = dev_get_plat(dev);
return mmc_bind(dev, &plat->mmc, &plat->cfg);
}
.ops = &mmc_spi_ops,
.probe = mmc_spi_probe,
.bind = mmc_spi_bind,
- .platdata_auto_alloc_size = sizeof(struct mmc_spi_plat),
- .priv_auto_alloc_size = sizeof(struct mmc_spi_priv),
+ .plat_auto = sizeof(struct mmc_spi_plat),
+ .priv_auto = sizeof(struct mmc_spi_priv),
};
#endif
{
#if CONFIG_IS_ENABLED(BLK)
- struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
+ struct blk_desc *block_dev = dev_get_uclass_plat(dev);
#endif
int dev_num = block_dev->devnum;
int err = 0;
#endif
{
#if CONFIG_IS_ENABLED(BLK)
- struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
+ struct blk_desc *block_dev = dev_get_uclass_plat(dev);
#endif
int dev_num = block_dev->devnum;
lbaint_t cur, blocks_todo = blkcnt;
static int msm_sdc_probe(struct udevice *dev)
{
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
- struct msm_sdhc_plat *plat = dev_get_platdata(dev);
+ struct msm_sdhc_plat *plat = dev_get_plat(dev);
struct msm_sdhc *prv = dev_get_priv(dev);
struct sdhci_host *host = &prv->host;
u32 core_version, core_minor, core_major;
return 0;
}
-static int msm_ofdata_to_platdata(struct udevice *dev)
+static int msm_of_to_plat(struct udevice *dev)
{
struct udevice *parent = dev->parent;
struct msm_sdhc *priv = dev_get_priv(dev);
static int msm_sdc_bind(struct udevice *dev)
{
- struct msm_sdhc_plat *plat = dev_get_platdata(dev);
+ struct msm_sdhc_plat *plat = dev_get_plat(dev);
return sdhci_bind(dev, &plat->mmc, &plat->cfg);
}
.name = "msm_sdc",
.id = UCLASS_MMC,
.of_match = msm_mmc_ids,
- .ofdata_to_platdata = msm_ofdata_to_platdata,
+ .of_to_plat = msm_of_to_plat,
.ops = &sdhci_ops,
.bind = msm_sdc_bind,
.probe = msm_sdc_probe,
.remove = msm_sdc_remove,
- .priv_auto_alloc_size = sizeof(struct msm_sdhc),
- .platdata_auto_alloc_size = sizeof(struct msm_sdhc_plat),
+ .priv_auto = sizeof(struct msm_sdhc),
+ .plat_auto = sizeof(struct msm_sdhc_plat),
};
static int msdc_ops_set_ios(struct udevice *dev)
{
- struct msdc_plat *plat = dev_get_platdata(dev);
+ struct msdc_plat *plat = dev_get_plat(dev);
struct msdc_host *host = dev_get_priv(dev);
struct mmc *mmc = &plat->mmc;
uint clock = mmc->clock;
static int hs400_tune_response(struct udevice *dev, u32 opcode)
{
- struct msdc_plat *plat = dev_get_platdata(dev);
+ struct msdc_plat *plat = dev_get_plat(dev);
struct msdc_host *host = dev_get_priv(dev);
struct mmc *mmc = &plat->mmc;
u32 cmd_delay = 0;
static int msdc_tune_response(struct udevice *dev, u32 opcode)
{
- struct msdc_plat *plat = dev_get_platdata(dev);
+ struct msdc_plat *plat = dev_get_plat(dev);
struct msdc_host *host = dev_get_priv(dev);
struct mmc *mmc = &plat->mmc;
u32 rise_delay = 0, fall_delay = 0;
static int msdc_tune_data(struct udevice *dev, u32 opcode)
{
- struct msdc_plat *plat = dev_get_platdata(dev);
+ struct msdc_plat *plat = dev_get_plat(dev);
struct msdc_host *host = dev_get_priv(dev);
struct mmc *mmc = &plat->mmc;
u32 rise_delay = 0, fall_delay = 0;
*/
static int msdc_tune_together(struct udevice *dev, u32 opcode)
{
- struct msdc_plat *plat = dev_get_platdata(dev);
+ struct msdc_plat *plat = dev_get_plat(dev);
struct msdc_host *host = dev_get_priv(dev);
struct mmc *mmc = &plat->mmc;
u32 rise_delay = 0, fall_delay = 0;
static int msdc_execute_tuning(struct udevice *dev, uint opcode)
{
- struct msdc_plat *plat = dev_get_platdata(dev);
+ struct msdc_plat *plat = dev_get_plat(dev);
struct msdc_host *host = dev_get_priv(dev);
struct mmc *mmc = &plat->mmc;
int ret = 0;
static int msdc_drv_probe(struct udevice *dev)
{
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
- struct msdc_plat *plat = dev_get_platdata(dev);
+ struct msdc_plat *plat = dev_get_plat(dev);
struct msdc_host *host = dev_get_priv(dev);
struct mmc_config *cfg = &plat->cfg;
return 0;
}
-static int msdc_ofdata_to_platdata(struct udevice *dev)
+static int msdc_of_to_plat(struct udevice *dev)
{
- struct msdc_plat *plat = dev_get_platdata(dev);
+ struct msdc_plat *plat = dev_get_plat(dev);
struct msdc_host *host = dev_get_priv(dev);
struct mmc_config *cfg = &plat->cfg;
fdt_addr_t base, top_base;
static int msdc_drv_bind(struct udevice *dev)
{
- struct msdc_plat *plat = dev_get_platdata(dev);
+ struct msdc_plat *plat = dev_get_plat(dev);
return mmc_bind(dev, &plat->mmc, &plat->cfg);
}
.name = "mtk_sd",
.id = UCLASS_MMC,
.of_match = msdc_ids,
- .ofdata_to_platdata = msdc_ofdata_to_platdata,
+ .of_to_plat = msdc_of_to_plat,
.bind = msdc_drv_bind,
.probe = msdc_drv_probe,
.ops = &msdc_ops,
- .platdata_auto_alloc_size = sizeof(struct msdc_plat),
- .priv_auto_alloc_size = sizeof(struct msdc_host),
+ .plat_auto = sizeof(struct msdc_plat),
+ .priv_auto = sizeof(struct msdc_host),
};
static int mv_sdhci_probe(struct udevice *dev)
{
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
- struct mv_sdhci_plat *plat = dev_get_platdata(dev);
+ struct mv_sdhci_plat *plat = dev_get_plat(dev);
struct sdhci_host *host = dev_get_priv(dev);
int ret;
static int mv_sdhci_bind(struct udevice *dev)
{
- struct mv_sdhci_plat *plat = dev_get_platdata(dev);
+ struct mv_sdhci_plat *plat = dev_get_plat(dev);
return sdhci_bind(dev, &plat->mmc, &plat->cfg);
}
.bind = mv_sdhci_bind,
.probe = mv_sdhci_probe,
.ops = &sdhci_ops,
- .priv_auto_alloc_size = sizeof(struct sdhci_host),
- .platdata_auto_alloc_size = sizeof(struct mv_sdhci_plat),
+ .priv_auto = sizeof(struct sdhci_host),
+ .plat_auto = sizeof(struct mv_sdhci_plat),
};
#endif /* CONFIG_DM_MMC */
#include <dm/read.h>
#include <dt-structs.h>
-struct mxsmmc_platdata {
+struct mxsmmc_plat {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct dtd_fsl_imx23_mmc dtplat;
#endif
static int
mxsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, struct mmc_data *data)
{
- struct mxsmmc_platdata *plat = dev_get_platdata(dev);
+ struct mxsmmc_plat *plat = dev_get_plat(dev);
struct mxsmmc_priv *priv = dev_get_priv(dev);
struct mxs_ssp_regs *ssp_regs = priv->regs;
struct mmc *mmc = &plat->mmc;
static int mxsmmc_get_cd(struct udevice *dev)
{
- struct mxsmmc_platdata *plat = dev_get_platdata(dev);
+ struct mxsmmc_plat *plat = dev_get_plat(dev);
struct mxsmmc_priv *priv = dev_get_priv(dev);
struct mxs_ssp_regs *ssp_regs = priv->regs;
static int mxsmmc_set_ios(struct udevice *dev)
{
- struct mxsmmc_platdata *plat = dev_get_platdata(dev);
+ struct mxsmmc_plat *plat = dev_get_plat(dev);
struct mxsmmc_priv *priv = dev_get_priv(dev);
struct mxs_ssp_regs *ssp_regs = priv->regs;
struct mmc *mmc = &plat->mmc;
static int mxsmmc_probe(struct udevice *dev)
{
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
- struct mxsmmc_platdata *plat = dev_get_platdata(dev);
+ struct mxsmmc_plat *plat = dev_get_plat(dev);
struct mxsmmc_priv *priv = dev_get_priv(dev);
struct blk_desc *bdesc;
struct mmc *mmc;
#if CONFIG_IS_ENABLED(BLK)
static int mxsmmc_bind(struct udevice *dev)
{
- struct mxsmmc_platdata *plat = dev_get_platdata(dev);
+ struct mxsmmc_plat *plat = dev_get_plat(dev);
return mmc_bind(dev, &plat->mmc, &plat->cfg);
}
};
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
-static int mxsmmc_ofdata_to_platdata(struct udevice *bus)
+static int mxsmmc_of_to_plat(struct udevice *bus)
{
- struct mxsmmc_platdata *plat = bus->platdata;
+ struct mxsmmc_plat *plat = bus->plat;
u32 prop[2];
int ret;
.id = UCLASS_MMC,
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
.of_match = mxsmmc_ids,
- .ofdata_to_platdata = mxsmmc_ofdata_to_platdata,
+ .of_to_plat = mxsmmc_of_to_plat,
#endif
.ops = &mxsmmc_ops,
#if CONFIG_IS_ENABLED(BLK)
.bind = mxsmmc_bind,
#endif
.probe = mxsmmc_probe,
- .priv_auto_alloc_size = sizeof(struct mxsmmc_priv),
- .platdata_auto_alloc_size = sizeof(struct mxsmmc_platdata),
+ .priv_auto = sizeof(struct mxsmmc_priv),
+ .plat_auto = sizeof(struct mxsmmc_plat),
};
U_BOOT_DRIVER_ALIAS(fsl_imx23_mmc, fsl_imx28_mmc)
return rate;
}
-static int nexell_dwmmc_ofdata_to_platdata(struct udevice *dev)
+static int nexell_dwmmc_of_to_plat(struct udevice *dev)
{
struct nexell_dwmmc_priv *priv = dev_get_priv(dev);
struct dwmci_host *host = &priv->host;
static int nexell_dwmmc_probe(struct udevice *dev)
{
- struct nexell_mmc_plat *plat = dev_get_platdata(dev);
+ struct nexell_mmc_plat *plat = dev_get_plat(dev);
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct nexell_dwmmc_priv *priv = dev_get_priv(dev);
struct dwmci_host *host = &priv->host;
static int nexell_dwmmc_bind(struct udevice *dev)
{
- struct nexell_mmc_plat *plat = dev_get_platdata(dev);
+ struct nexell_mmc_plat *plat = dev_get_plat(dev);
return dwmci_bind(dev, &plat->mmc, &plat->cfg);
}
.name = "nexell_dwmmc",
.id = UCLASS_MMC,
.of_match = nexell_dwmmc_ids,
- .ofdata_to_platdata = nexell_dwmmc_ofdata_to_platdata,
+ .of_to_plat = nexell_dwmmc_of_to_plat,
.ops = &dm_dwmci_ops,
.bind = nexell_dwmmc_bind,
.probe = nexell_dwmmc_probe,
- .priv_auto_alloc_size = sizeof(struct nexell_dwmmc_priv),
- .platdata_auto_alloc_size = sizeof(struct nexell_mmc_plat),
+ .priv_auto = sizeof(struct nexell_dwmmc_priv),
+ .plat_auto = sizeof(struct nexell_mmc_plat),
};
.id = UCLASS_MISC,
.of_match = of_match_ptr(octeontx_hsmmc_host_ids),
.probe = octeontx_mmc_host_probe,
- .priv_auto_alloc_size = sizeof(struct octeontx_mmc_host),
+ .priv_auto = sizeof(struct octeontx_mmc_host),
.child_pre_probe = octeontx_mmc_host_child_pre_probe,
.flags = DM_FLAG_PRE_RELOC,
};
static inline struct mmc_config *omap_hsmmc_get_cfg(struct mmc *mmc)
{
#if CONFIG_IS_ENABLED(DM_MMC)
- struct omap_hsmmc_plat *plat = dev_get_platdata(mmc->dev);
+ struct omap_hsmmc_plat *plat = dev_get_plat(mmc->dev);
return &plat->cfg;
#else
return &((struct omap_hsmmc_data *)mmc->priv)->cfg;
}
#endif
-static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
+static int omap_hsmmc_of_to_plat(struct udevice *dev)
{
- struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
+ struct omap_hsmmc_plat *plat = dev_get_plat(dev);
struct omap_mmc_of_data *of_data = (void *)dev_get_driver_data(dev);
struct mmc_config *cfg = &plat->cfg;
static int omap_hsmmc_bind(struct udevice *dev)
{
- struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
+ struct omap_hsmmc_plat *plat = dev_get_plat(dev);
plat->mmc = calloc(1, sizeof(struct mmc));
return mmc_bind(dev, plat->mmc, &plat->cfg);
}
#endif
static int omap_hsmmc_probe(struct udevice *dev)
{
- struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
+ struct omap_hsmmc_plat *plat = dev_get_plat(dev);
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct omap_hsmmc_data *priv = dev_get_priv(dev);
struct mmc_config *cfg = &plat->cfg;
.id = UCLASS_MMC,
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
.of_match = omap_hsmmc_ids,
- .ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct omap_hsmmc_plat),
+ .of_to_plat = omap_hsmmc_of_to_plat,
+ .plat_auto = sizeof(struct omap_hsmmc_plat),
#endif
#ifdef CONFIG_BLK
.bind = omap_hsmmc_bind,
#endif
.ops = &omap_hsmmc_ops,
.probe = omap_hsmmc_probe,
- .priv_auto_alloc_size = sizeof(struct omap_hsmmc_data),
+ .priv_auto = sizeof(struct omap_hsmmc_data),
#if !CONFIG_IS_ENABLED(OF_CONTROL)
.flags = DM_FLAG_PRE_RELOC,
#endif
static int pci_mmc_probe(struct udevice *dev)
{
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
- struct pci_mmc_plat *plat = dev_get_platdata(dev);
+ struct pci_mmc_plat *plat = dev_get_plat(dev);
struct pci_mmc_priv *priv = dev_get_priv(dev);
struct sdhci_host *host = &priv->host;
int ret;
return sdhci_probe(dev);
}
-static int pci_mmc_ofdata_to_platdata(struct udevice *dev)
+static int pci_mmc_of_to_plat(struct udevice *dev)
{
struct pci_mmc_priv *priv = dev_get_priv(dev);
static int pci_mmc_bind(struct udevice *dev)
{
- struct pci_mmc_plat *plat = dev_get_platdata(dev);
+ struct pci_mmc_plat *plat = dev_get_plat(dev);
return sdhci_bind(dev, &plat->mmc, &plat->cfg);
}
.id = UCLASS_MMC,
.of_match = pci_mmc_match,
.bind = pci_mmc_bind,
- .ofdata_to_platdata = pci_mmc_ofdata_to_platdata,
+ .of_to_plat = pci_mmc_of_to_plat,
.probe = pci_mmc_probe,
.ops = &sdhci_ops,
- .priv_auto_alloc_size = sizeof(struct pci_mmc_priv),
- .platdata_auto_alloc_size = sizeof(struct pci_mmc_plat),
+ .priv_auto = sizeof(struct pci_mmc_priv),
+ .plat_auto = sizeof(struct pci_mmc_plat),
ACPI_OPS_PTR(&pci_mmc_acpi_ops)
};
static int pic32_sdhci_probe(struct udevice *dev)
{
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
- struct pic32_sdhci_plat *plat = dev_get_platdata(dev);
+ struct pic32_sdhci_plat *plat = dev_get_plat(dev);
struct sdhci_host *host = dev_get_priv(dev);
struct clk clk;
static int pic32_sdhci_bind(struct udevice *dev)
{
- struct pic32_sdhci_plat *plat = dev_get_platdata(dev);
+ struct pic32_sdhci_plat *plat = dev_get_plat(dev);
return sdhci_bind(dev, &plat->mmc, &plat->cfg);
}
.ops = &sdhci_ops,
.bind = pic32_sdhci_bind,
.probe = pic32_sdhci_probe,
- .priv_auto_alloc_size = sizeof(struct sdhci_host),
- .platdata_auto_alloc_size = sizeof(struct pic32_sdhci_plat)
+ .priv_auto = sizeof(struct sdhci_host),
+ .plat_auto = sizeof(struct pic32_sdhci_plat)
};
static int pxa_mmc_probe(struct udevice *dev)
{
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
- struct pxa_mmc_plat *plat = dev_get_platdata(dev);
+ struct pxa_mmc_plat *plat = dev_get_plat(dev);
struct mmc_config *cfg = &plat->cfg;
struct mmc *mmc = &plat->mmc;
struct pxa_mmc_priv *priv = dev_get_priv(dev);
static int pxa_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
struct mmc_data *data)
{
- struct pxa_mmc_plat *plat = dev_get_platdata(dev);
+ struct pxa_mmc_plat *plat = dev_get_plat(dev);
struct pxa_mmc_priv *priv = dev_get_priv(dev);
return pxa_mmc_send_cmd_common(priv, &plat->mmc, cmd, data);
static int pxa_mmc_set_ios(struct udevice *dev)
{
- struct pxa_mmc_plat *plat = dev_get_platdata(dev);
+ struct pxa_mmc_plat *plat = dev_get_plat(dev);
struct pxa_mmc_priv *priv = dev_get_priv(dev);
return pxa_mmc_set_ios_common(priv, &plat->mmc);
#if CONFIG_IS_ENABLED(BLK)
static int pxa_mmc_bind(struct udevice *dev)
{
- struct pxa_mmc_plat *plat = dev_get_platdata(dev);
+ struct pxa_mmc_plat *plat = dev_get_plat(dev);
return mmc_bind(dev, &plat->mmc, &plat->cfg);
}
.id = UCLASS_MMC,
.name = "pxa_mmc",
.ops = &pxa_mmc_ops,
- .priv_auto_alloc_size = sizeof(struct pxa_mmc_priv),
+ .priv_auto = sizeof(struct pxa_mmc_priv),
.probe = pxa_mmc_probe,
};
#endif /* !CONFIG_IS_ENABLED(DM_MMC) */
#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
- struct tmio_sd_plat *plat = dev_get_platdata(dev);
+ struct tmio_sd_plat *plat = dev_get_plat(dev);
/* HS400 is not supported on H3 ES1.x and M3W ES1.0, ES1.1 */
if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
.of_match = renesas_sdhi_match,
.bind = tmio_sd_bind,
.probe = renesas_sdhi_probe,
- .priv_auto_alloc_size = sizeof(struct tmio_sd_priv),
- .platdata_auto_alloc_size = sizeof(struct tmio_sd_plat),
+ .priv_auto = sizeof(struct tmio_sd_priv),
+ .plat_auto = sizeof(struct tmio_sd_plat),
.ops = &renesas_sdhi_ops,
};
return freq;
}
-static int rockchip_dwmmc_ofdata_to_platdata(struct udevice *dev)
+static int rockchip_dwmmc_of_to_plat(struct udevice *dev)
{
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
static int rockchip_dwmmc_probe(struct udevice *dev)
{
- struct rockchip_mmc_plat *plat = dev_get_platdata(dev);
+ struct rockchip_mmc_plat *plat = dev_get_plat(dev);
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
struct dwmci_host *host = &priv->host;
static int rockchip_dwmmc_bind(struct udevice *dev)
{
- struct rockchip_mmc_plat *plat = dev_get_platdata(dev);
+ struct rockchip_mmc_plat *plat = dev_get_plat(dev);
return dwmci_bind(dev, &plat->mmc, &plat->cfg);
}
.name = "rockchip_rk3288_dw_mshc",
.id = UCLASS_MMC,
.of_match = rockchip_dwmmc_ids,
- .ofdata_to_platdata = rockchip_dwmmc_ofdata_to_platdata,
+ .of_to_plat = rockchip_dwmmc_of_to_plat,
.ops = &dm_dwmci_ops,
.bind = rockchip_dwmmc_bind,
.probe = rockchip_dwmmc_probe,
- .priv_auto_alloc_size = sizeof(struct rockchip_dwmmc_priv),
- .platdata_auto_alloc_size = sizeof(struct rockchip_mmc_plat),
+ .priv_auto = sizeof(struct rockchip_dwmmc_priv),
+ .plat_auto = sizeof(struct rockchip_mmc_plat),
};
U_BOOT_DRIVER_ALIAS(rockchip_rk3288_dw_mshc, rockchip_rk3328_dw_mshc)
static int arasan_sdhci_probe(struct udevice *dev)
{
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
- struct rockchip_sdhc_plat *plat = dev_get_platdata(dev);
+ struct rockchip_sdhc_plat *plat = dev_get_plat(dev);
struct rockchip_sdhc *prv = dev_get_priv(dev);
struct sdhci_host *host = &prv->host;
int max_frequency, ret;
return sdhci_probe(dev);
}
-static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
+static int arasan_sdhci_of_to_plat(struct udevice *dev)
{
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct sdhci_host *host = dev_get_priv(dev);
static int rockchip_sdhci_bind(struct udevice *dev)
{
- struct rockchip_sdhc_plat *plat = dev_get_platdata(dev);
+ struct rockchip_sdhc_plat *plat = dev_get_plat(dev);
return sdhci_bind(dev, &plat->mmc, &plat->cfg);
}
.name = "rockchip_rk3399_sdhci_5_1",
.id = UCLASS_MMC,
.of_match = arasan_sdhci_ids,
- .ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata,
+ .of_to_plat = arasan_sdhci_of_to_plat,
.ops = &sdhci_ops,
.bind = rockchip_sdhci_bind,
.probe = arasan_sdhci_probe,
- .priv_auto_alloc_size = sizeof(struct rockchip_sdhc),
- .platdata_auto_alloc_size = sizeof(struct rockchip_sdhc_plat),
+ .priv_auto = sizeof(struct rockchip_sdhc),
+ .plat_auto = sizeof(struct rockchip_sdhc_plat),
};
#ifdef CONFIG_DM_MMC
static int s5p_sdhci_probe(struct udevice *dev)
{
- struct s5p_sdhci_plat *plat = dev_get_platdata(dev);
+ struct s5p_sdhci_plat *plat = dev_get_plat(dev);
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct sdhci_host *host = dev_get_priv(dev);
int ret;
static int s5p_sdhci_bind(struct udevice *dev)
{
- struct s5p_sdhci_plat *plat = dev_get_platdata(dev);
+ struct s5p_sdhci_plat *plat = dev_get_plat(dev);
int ret;
ret = sdhci_bind(dev, &plat->mmc, &plat->cfg);
.bind = s5p_sdhci_bind,
.ops = &sdhci_ops,
.probe = s5p_sdhci_probe,
- .priv_auto_alloc_size = sizeof(struct sdhci_host),
- .platdata_auto_alloc_size = sizeof(struct s5p_sdhci_plat),
+ .priv_auto = sizeof(struct sdhci_host),
+ .plat_auto = sizeof(struct s5p_sdhci_plat),
};
#endif /* CONFIG_DM_MMC */
int sandbox_mmc_probe(struct udevice *dev)
{
- struct sandbox_mmc_plat *plat = dev_get_platdata(dev);
+ struct sandbox_mmc_plat *plat = dev_get_plat(dev);
return mmc_init(&plat->mmc);
}
int sandbox_mmc_bind(struct udevice *dev)
{
- struct sandbox_mmc_plat *plat = dev_get_platdata(dev);
+ struct sandbox_mmc_plat *plat = dev_get_plat(dev);
struct mmc_config *cfg = &plat->cfg;
cfg->name = dev->name;
.bind = sandbox_mmc_bind,
.unbind = sandbox_mmc_unbind,
.probe = sandbox_mmc_probe,
- .platdata_auto_alloc_size = sizeof(struct sandbox_mmc_plat),
+ .plat_auto = sizeof(struct sandbox_mmc_plat),
};
static void sdhci_cdns_set_control_reg(struct sdhci_host *host)
{
struct mmc *mmc = host->mmc;
- struct sdhci_cdns_plat *plat = dev_get_platdata(mmc->dev);
+ struct sdhci_cdns_plat *plat = dev_get_plat(mmc->dev);
unsigned int clock = mmc->clock;
u32 mode, tmp;
static int __maybe_unused sdhci_cdns_execute_tuning(struct udevice *dev,
unsigned int opcode)
{
- struct sdhci_cdns_plat *plat = dev_get_platdata(dev);
+ struct sdhci_cdns_plat *plat = dev_get_plat(dev);
struct mmc *mmc = &plat->mmc;
int cur_streak = 0;
int max_streak = 0;
static int sdhci_cdns_bind(struct udevice *dev)
{
- struct sdhci_cdns_plat *plat = dev_get_platdata(dev);
+ struct sdhci_cdns_plat *plat = dev_get_plat(dev);
return sdhci_bind(dev, &plat->mmc, &plat->cfg);
}
{
DECLARE_GLOBAL_DATA_PTR;
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
- struct sdhci_cdns_plat *plat = dev_get_platdata(dev);
+ struct sdhci_cdns_plat *plat = dev_get_plat(dev);
struct sdhci_host *host = dev_get_priv(dev);
fdt_addr_t base;
int ret;
.of_match = sdhci_cdns_match,
.bind = sdhci_cdns_bind,
.probe = sdhci_cdns_probe,
- .priv_auto_alloc_size = sizeof(struct sdhci_host),
- .platdata_auto_alloc_size = sizeof(struct sdhci_cdns_plat),
+ .priv_auto = sizeof(struct sdhci_host),
+ .plat_auto = sizeof(struct sdhci_cdns_plat),
.ops = &sdhci_cdns_mmc_ops,
};
static int sh_mmcif_dm_bind(struct udevice *dev)
{
- struct sh_mmcif_plat *plat = dev_get_platdata(dev);
+ struct sh_mmcif_plat *plat = dev_get_plat(dev);
return mmc_bind(dev, &plat->mmc, &plat->cfg);
}
static int sh_mmcif_dm_probe(struct udevice *dev)
{
- struct sh_mmcif_plat *plat = dev_get_platdata(dev);
+ struct sh_mmcif_plat *plat = dev_get_plat(dev);
struct sh_mmcif_host *host = dev_get_priv(dev);
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct clk sh_mmcif_clk;
.of_match = sh_mmcif_sd_match,
.bind = sh_mmcif_dm_bind,
.probe = sh_mmcif_dm_probe,
- .priv_auto_alloc_size = sizeof(struct sh_mmcif_host),
- .platdata_auto_alloc_size = sizeof(struct sh_mmcif_plat),
+ .priv_auto = sizeof(struct sh_mmcif_host),
+ .plat_auto = sizeof(struct sh_mmcif_plat),
.ops = &sh_mmcif_dm_ops,
};
#endif
static int sh_sdhi_dm_bind(struct udevice *dev)
{
- struct sh_sdhi_plat *plat = dev_get_platdata(dev);
+ struct sh_sdhi_plat *plat = dev_get_plat(dev);
return mmc_bind(dev, &plat->mmc, &plat->cfg);
}
static int sh_sdhi_dm_probe(struct udevice *dev)
{
- struct sh_sdhi_plat *plat = dev_get_platdata(dev);
+ struct sh_sdhi_plat *plat = dev_get_plat(dev);
struct sh_sdhi_host *host = dev_get_priv(dev);
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct clk sh_sdhi_clk;
.of_match = sh_sdhi_sd_match,
.bind = sh_sdhi_dm_bind,
.probe = sh_sdhi_dm_probe,
- .priv_auto_alloc_size = sizeof(struct sh_sdhi_host),
- .platdata_auto_alloc_size = sizeof(struct sh_sdhi_plat),
+ .priv_auto = sizeof(struct sh_sdhi_host),
+ .plat_auto = sizeof(struct sh_sdhi_plat),
.ops = &sh_sdhi_dm_ops,
};
#endif
return ret;
}
-static int snps_dwmmc_ofdata_to_platdata(struct udevice *dev)
+static int snps_dwmmc_of_to_plat(struct udevice *dev)
{
struct snps_dwmci_priv_data *priv = dev_get_priv(dev);
struct dwmci_host *host = &priv->host;
static int snps_dwmmc_probe(struct udevice *dev)
{
#ifdef CONFIG_BLK
- struct snps_dwmci_plat *plat = dev_get_platdata(dev);
+ struct snps_dwmci_plat *plat = dev_get_plat(dev);
#endif
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct snps_dwmci_priv_data *priv = dev_get_priv(dev);
static int snps_dwmmc_bind(struct udevice *dev)
{
#ifdef CONFIG_BLK
- struct snps_dwmci_plat *plat = dev_get_platdata(dev);
+ struct snps_dwmci_plat *plat = dev_get_plat(dev);
int ret;
ret = dwmci_bind(dev, &plat->mmc, &plat->cfg);
.name = "snps_dw_mmc",
.id = UCLASS_MMC,
.of_match = snps_dwmmc_ids,
- .ofdata_to_platdata = snps_dwmmc_ofdata_to_platdata,
+ .of_to_plat = snps_dwmmc_of_to_plat,
.ops = &snps_dwmci_dm_ops,
.bind = snps_dwmmc_bind,
.probe = snps_dwmmc_probe,
- .priv_auto_alloc_size = sizeof(struct snps_dwmci_priv_data),
- .platdata_auto_alloc_size = sizeof(struct snps_dwmci_plat),
+ .priv_auto = sizeof(struct snps_dwmci_priv_data),
+ .plat_auto = sizeof(struct snps_dwmci_plat),
};
return 0;
}
-static int socfpga_dwmmc_ofdata_to_platdata(struct udevice *dev)
+static int socfpga_dwmmc_of_to_plat(struct udevice *dev)
{
struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
struct dwmci_host *host = &priv->host;
static int socfpga_dwmmc_probe(struct udevice *dev)
{
#ifdef CONFIG_BLK
- struct socfpga_dwmci_plat *plat = dev_get_platdata(dev);
+ struct socfpga_dwmci_plat *plat = dev_get_plat(dev);
#endif
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
static int socfpga_dwmmc_bind(struct udevice *dev)
{
#ifdef CONFIG_BLK
- struct socfpga_dwmci_plat *plat = dev_get_platdata(dev);
+ struct socfpga_dwmci_plat *plat = dev_get_plat(dev);
int ret;
ret = dwmci_bind(dev, &plat->mmc, &plat->cfg);
.name = "socfpga_dwmmc",
.id = UCLASS_MMC,
.of_match = socfpga_dwmmc_ids,
- .ofdata_to_platdata = socfpga_dwmmc_ofdata_to_platdata,
+ .of_to_plat = socfpga_dwmmc_of_to_plat,
.ops = &dm_dwmci_ops,
.bind = socfpga_dwmmc_bind,
.probe = socfpga_dwmmc_probe,
- .priv_auto_alloc_size = sizeof(struct dwmci_socfpga_priv_data),
- .platdata_auto_alloc_size = sizeof(struct socfpga_dwmci_plat),
+ .priv_auto = sizeof(struct dwmci_socfpga_priv_data),
+ .plat_auto = sizeof(struct socfpga_dwmci_plat),
};
*/
static int sti_mmc_core_config(struct udevice *dev)
{
- struct sti_sdhci_plat *plat = dev_get_platdata(dev);
+ struct sti_sdhci_plat *plat = dev_get_plat(dev);
struct sdhci_host *host = dev_get_priv(dev);
int ret;
static int sti_sdhci_probe(struct udevice *dev)
{
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
- struct sti_sdhci_plat *plat = dev_get_platdata(dev);
+ struct sti_sdhci_plat *plat = dev_get_plat(dev);
struct sdhci_host *host = dev_get_priv(dev);
int ret;
return sdhci_probe(dev);
}
-static int sti_sdhci_ofdata_to_platdata(struct udevice *dev)
+static int sti_sdhci_of_to_plat(struct udevice *dev)
{
struct sdhci_host *host = dev_get_priv(dev);
static int sti_sdhci_bind(struct udevice *dev)
{
- struct sti_sdhci_plat *plat = dev_get_platdata(dev);
+ struct sti_sdhci_plat *plat = dev_get_plat(dev);
return sdhci_bind(dev, &plat->mmc, &plat->cfg);
}
.of_match = sti_sdhci_ids,
.bind = sti_sdhci_bind,
.ops = &sdhci_ops,
- .ofdata_to_platdata = sti_sdhci_ofdata_to_platdata,
+ .of_to_plat = sti_sdhci_of_to_plat,
.probe = sti_sdhci_probe,
- .priv_auto_alloc_size = sizeof(struct sdhci_host),
- .platdata_auto_alloc_size = sizeof(struct sti_sdhci_plat),
+ .priv_auto = sizeof(struct sdhci_host),
+ .plat_auto = sizeof(struct sti_sdhci_plat),
};
static int stm32_sdmmc2_probe(struct udevice *dev)
{
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
- struct stm32_sdmmc2_plat *plat = dev_get_platdata(dev);
+ struct stm32_sdmmc2_plat *plat = dev_get_plat(dev);
struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
struct mmc_config *cfg = &plat->cfg;
int ret;
static int stm32_sdmmc_bind(struct udevice *dev)
{
- struct stm32_sdmmc2_plat *plat = dev_get_platdata(dev);
+ struct stm32_sdmmc2_plat *plat = dev_get_plat(dev);
return mmc_bind(dev, &plat->mmc, &plat->cfg);
}
.ops = &stm32_sdmmc2_ops,
.probe = stm32_sdmmc2_probe,
.bind = stm32_sdmmc_bind,
- .priv_auto_alloc_size = sizeof(struct stm32_sdmmc2_priv),
- .platdata_auto_alloc_size = sizeof(struct stm32_sdmmc2_plat),
+ .priv_auto = sizeof(struct stm32_sdmmc2_priv),
+ .plat_auto = sizeof(struct stm32_sdmmc2_plat),
};
static int sunxi_mmc_set_ios(struct udevice *dev)
{
- struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
+ struct sunxi_mmc_plat *plat = dev_get_plat(dev);
struct sunxi_mmc_priv *priv = dev_get_priv(dev);
return sunxi_mmc_set_ios_common(priv, &plat->mmc);
static int sunxi_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
struct mmc_data *data)
{
- struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
+ struct sunxi_mmc_plat *plat = dev_get_plat(dev);
struct sunxi_mmc_priv *priv = dev_get_priv(dev);
return sunxi_mmc_send_cmd_common(priv, &plat->mmc, cmd, data);
static int sunxi_mmc_probe(struct udevice *dev)
{
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
- struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
+ struct sunxi_mmc_plat *plat = dev_get_plat(dev);
struct sunxi_mmc_priv *priv = dev_get_priv(dev);
struct reset_ctl_bulk reset_bulk;
struct clk gate_clk;
static int sunxi_mmc_bind(struct udevice *dev)
{
- struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
+ struct sunxi_mmc_plat *plat = dev_get_plat(dev);
return mmc_bind(dev, &plat->mmc, &plat->cfg);
}
.bind = sunxi_mmc_bind,
.probe = sunxi_mmc_probe,
.ops = &sunxi_mmc_ops,
- .platdata_auto_alloc_size = sizeof(struct sunxi_mmc_plat),
- .priv_auto_alloc_size = sizeof(struct sunxi_mmc_priv),
+ .plat_auto = sizeof(struct sunxi_mmc_plat),
+ .priv_auto = sizeof(struct sunxi_mmc_priv),
};
#endif
static int sdhci_tangier_bind(struct udevice *dev)
{
- struct sdhci_tangier_plat *plat = dev_get_platdata(dev);
+ struct sdhci_tangier_plat *plat = dev_get_plat(dev);
return sdhci_bind(dev, &plat->mmc, &plat->cfg);
}
static int sdhci_tangier_probe(struct udevice *dev)
{
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
- struct sdhci_tangier_plat *plat = dev_get_platdata(dev);
+ struct sdhci_tangier_plat *plat = dev_get_plat(dev);
struct sdhci_host *host = dev_get_priv(dev);
fdt_addr_t base;
int ret;
.bind = sdhci_tangier_bind,
.probe = sdhci_tangier_probe,
.ops = &sdhci_ops,
- .priv_auto_alloc_size = sizeof(struct sdhci_host),
- .platdata_auto_alloc_size = sizeof(struct sdhci_tangier_plat),
+ .priv_auto = sizeof(struct sdhci_host),
+ .plat_auto = sizeof(struct sdhci_tangier_plat),
};
static int tegra_mmc_probe(struct udevice *dev)
{
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
- struct tegra_mmc_plat *plat = dev_get_platdata(dev);
+ struct tegra_mmc_plat *plat = dev_get_plat(dev);
struct tegra_mmc_priv *priv = dev_get_priv(dev);
struct mmc_config *cfg = &plat->cfg;
int bus_width, ret;
static int tegra_mmc_bind(struct udevice *dev)
{
- struct tegra_mmc_plat *plat = dev_get_platdata(dev);
+ struct tegra_mmc_plat *plat = dev_get_plat(dev);
return mmc_bind(dev, &plat->mmc, &plat->cfg);
}
.bind = tegra_mmc_bind,
.probe = tegra_mmc_probe,
.ops = &tegra_mmc_ops,
- .platdata_auto_alloc_size = sizeof(struct tegra_mmc_plat),
- .priv_auto_alloc_size = sizeof(struct tegra_mmc_priv),
+ .plat_auto = sizeof(struct tegra_mmc_plat),
+ .priv_auto = sizeof(struct tegra_mmc_priv),
};
int tmio_sd_bind(struct udevice *dev)
{
- struct tmio_sd_plat *plat = dev_get_platdata(dev);
+ struct tmio_sd_plat *plat = dev_get_plat(dev);
return mmc_bind(dev, &plat->mmc, &plat->cfg);
}
int tmio_sd_probe(struct udevice *dev, u32 quirks)
{
- struct tmio_sd_plat *plat = dev_get_platdata(dev);
+ struct tmio_sd_plat *plat = dev_get_plat(dev);
struct tmio_sd_priv *priv = dev_get_priv(dev);
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
fdt_addr_t base;
.of_match = uniphier_sd_match,
.bind = tmio_sd_bind,
.probe = uniphier_sd_probe,
- .priv_auto_alloc_size = sizeof(struct tmio_sd_priv),
- .platdata_auto_alloc_size = sizeof(struct tmio_sd_plat),
+ .priv_auto = sizeof(struct tmio_sd_priv),
+ .plat_auto = sizeof(struct tmio_sd_plat),
.ops = &uniphier_sd_ops,
};
static int xenon_sdhci_probe(struct udevice *dev)
{
- struct xenon_sdhci_plat *plat = dev_get_platdata(dev);
+ struct xenon_sdhci_plat *plat = dev_get_plat(dev);
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct xenon_sdhci_priv *priv = dev_get_priv(dev);
struct sdhci_host *host = dev_get_priv(dev);
return ret;
}
-static int xenon_sdhci_ofdata_to_platdata(struct udevice *dev)
+static int xenon_sdhci_of_to_plat(struct udevice *dev)
{
struct sdhci_host *host = dev_get_priv(dev);
struct xenon_sdhci_priv *priv = dev_get_priv(dev);
static int xenon_sdhci_bind(struct udevice *dev)
{
- struct xenon_sdhci_plat *plat = dev_get_platdata(dev);
+ struct xenon_sdhci_plat *plat = dev_get_plat(dev);
return sdhci_bind(dev, &plat->mmc, &plat->cfg);
}
.name = "xenon_sdhci",
.id = UCLASS_MMC,
.of_match = xenon_sdhci_ids,
- .ofdata_to_platdata = xenon_sdhci_ofdata_to_platdata,
+ .of_to_plat = xenon_sdhci_of_to_plat,
.ops = &sdhci_ops,
.bind = xenon_sdhci_bind,
.probe = xenon_sdhci_probe,
- .priv_auto_alloc_size = sizeof(struct xenon_sdhci_priv),
- .platdata_auto_alloc_size = sizeof(struct xenon_sdhci_plat),
+ .priv_auto = sizeof(struct xenon_sdhci_priv),
+ .plat_auto = sizeof(struct xenon_sdhci_plat),
};
static int arasan_sdhci_probe(struct udevice *dev)
{
- struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
+ struct arasan_sdhci_plat *plat = dev_get_plat(dev);
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct arasan_sdhci_priv *priv = dev_get_priv(dev);
struct sdhci_host *host;
return sdhci_probe(dev);
}
-static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
+static int arasan_sdhci_of_to_plat(struct udevice *dev)
{
struct arasan_sdhci_priv *priv = dev_get_priv(dev);
static int arasan_sdhci_bind(struct udevice *dev)
{
- struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
+ struct arasan_sdhci_plat *plat = dev_get_plat(dev);
return sdhci_bind(dev, &plat->mmc, &plat->cfg);
}
.name = "arasan_sdhci",
.id = UCLASS_MMC,
.of_match = arasan_sdhci_ids,
- .ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata,
+ .of_to_plat = arasan_sdhci_of_to_plat,
.ops = &sdhci_ops,
.bind = arasan_sdhci_bind,
.probe = arasan_sdhci_probe,
- .priv_auto_alloc_size = sizeof(struct arasan_sdhci_priv),
- .platdata_auto_alloc_size = sizeof(struct arasan_sdhci_plat),
+ .priv_auto = sizeof(struct arasan_sdhci_priv),
+ .plat_auto = sizeof(struct arasan_sdhci_plat),
};
u32 chip_select;
};
-struct altera_qspi_platdata {
+struct altera_qspi_plat {
struct altera_qspi_regs *regs;
void *base;
unsigned long size;
{
struct mtd_info *mtd = info->mtd;
struct udevice *dev = mtd->dev;
- struct altera_qspi_platdata *pdata = dev_get_platdata(dev);
+ struct altera_qspi_plat *pdata = dev_get_plat(dev);
ulong base = (ulong)pdata->base;
loff_t to = addr - base;
size_t retlen;
static int altera_qspi_erase(struct mtd_info *mtd, struct erase_info *instr)
{
struct udevice *dev = mtd->dev;
- struct altera_qspi_platdata *pdata = dev_get_platdata(dev);
+ struct altera_qspi_plat *pdata = dev_get_plat(dev);
struct altera_qspi_regs *regs = pdata->regs;
size_t addr = instr->addr;
size_t len = instr->len;
size_t *retlen, u_char *buf)
{
struct udevice *dev = mtd->dev;
- struct altera_qspi_platdata *pdata = dev_get_platdata(dev);
+ struct altera_qspi_plat *pdata = dev_get_plat(dev);
memcpy_fromio(buf, pdata->base + from, len);
*retlen = len;
size_t *retlen, const u_char *buf)
{
struct udevice *dev = mtd->dev;
- struct altera_qspi_platdata *pdata = dev_get_platdata(dev);
+ struct altera_qspi_plat *pdata = dev_get_plat(dev);
struct altera_qspi_regs *regs = pdata->regs;
u32 stat;
uint64_t *len)
{
struct udevice *dev = mtd->dev;
- struct altera_qspi_platdata *pdata = dev_get_platdata(dev);
+ struct altera_qspi_plat *pdata = dev_get_plat(dev);
struct altera_qspi_regs *regs = pdata->regs;
int shift0 = ffs(QUADSPI_SR_BP2_0) - 1;
int shift3 = ffs(QUADSPI_SR_BP3) - 1 - 3;
static int altera_qspi_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
{
struct udevice *dev = mtd->dev;
- struct altera_qspi_platdata *pdata = dev_get_platdata(dev);
+ struct altera_qspi_plat *pdata = dev_get_plat(dev);
struct altera_qspi_regs *regs = pdata->regs;
u32 sector_start, sector_end;
u32 num_sectors;
static int altera_qspi_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
{
struct udevice *dev = mtd->dev;
- struct altera_qspi_platdata *pdata = dev_get_platdata(dev);
+ struct altera_qspi_plat *pdata = dev_get_plat(dev);
struct altera_qspi_regs *regs = pdata->regs;
u32 mem_op;
static int altera_qspi_probe(struct udevice *dev)
{
- struct altera_qspi_platdata *pdata = dev_get_platdata(dev);
+ struct altera_qspi_plat *pdata = dev_get_plat(dev);
struct altera_qspi_regs *regs = pdata->regs;
unsigned long base = (unsigned long)pdata->base;
struct mtd_info *mtd;
return 0;
}
-static int altera_qspi_ofdata_to_platdata(struct udevice *dev)
+static int altera_qspi_of_to_plat(struct udevice *dev)
{
- struct altera_qspi_platdata *pdata = dev_get_platdata(dev);
+ struct altera_qspi_plat *pdata = dev_get_plat(dev);
void *blob = (void *)gd->fdt_blob;
int node = dev_of_offset(dev);
const char *list, *end;
.name = "altera_qspi",
.id = UCLASS_MTD,
.of_match = altera_qspi_ids,
- .ofdata_to_platdata = altera_qspi_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct altera_qspi_platdata),
+ .of_to_plat = altera_qspi_of_to_plat,
+ .plat_auto = sizeof(struct altera_qspi_plat),
.probe = altera_qspi_probe,
};
.of_match = am654_hbmc_dt_ids,
.probe = am654_hbmc_probe,
.bind = am654_hbmc_bind,
- .priv_auto_alloc_size = sizeof(struct am654_hbmc_priv),
+ .priv_auto = sizeof(struct am654_hbmc_priv),
};
UCLASS_DRIVER(mtd) = {
.id = UCLASS_MTD,
.name = "mtd",
- .per_device_auto_alloc_size = sizeof(struct mtd_info),
+ .per_device_auto = sizeof(struct mtd_info),
};
.id = UCLASS_MTD,
.of_match = arasan_nand_dt_ids,
.probe = arasan_probe,
- .priv_auto_alloc_size = sizeof(struct arasan_nand_info),
+ .priv_auto = sizeof(struct arasan_nand_info),
};
void board_nand_init(void)
.id = UCLASS_MTD,
.of_match = bcm63158_nand_dt_ids,
.probe = bcm63158_nand_probe,
- .priv_auto_alloc_size = sizeof(struct bcm63158_nand_soc),
+ .priv_auto = sizeof(struct bcm63158_nand_soc),
};
void board_nand_init(void)
.id = UCLASS_MTD,
.of_match = bcm6368_nand_dt_ids,
.probe = bcm6368_nand_probe,
- .priv_auto_alloc_size = sizeof(struct bcm6368_nand_soc),
+ .priv_auto = sizeof(struct bcm6368_nand_soc),
};
void board_nand_init(void)
.id = UCLASS_MTD,
.of_match = bcm68360_nand_dt_ids,
.probe = bcm68360_nand_probe,
- .priv_auto_alloc_size = sizeof(struct bcm68360_nand_soc),
+ .priv_auto = sizeof(struct bcm68360_nand_soc),
};
void board_nand_init(void)
.id = UCLASS_MTD,
.of_match = bcm6838_nand_dt_ids,
.probe = bcm6838_nand_probe,
- .priv_auto_alloc_size = sizeof(struct bcm6838_nand_soc),
+ .priv_auto = sizeof(struct bcm6838_nand_soc),
};
void board_nand_init(void)
.id = UCLASS_MTD,
.of_match = bcm6858_nand_dt_ids,
.probe = bcm6858_nand_probe,
- .priv_auto_alloc_size = sizeof(struct bcm6858_nand_soc),
+ .priv_auto = sizeof(struct bcm6858_nand_soc),
};
void board_nand_init(void)
.id = UCLASS_MTD,
.of_match = davinci_nand_ids,
.probe = davinci_nand_probe,
- .priv_auto_alloc_size = sizeof(struct nand_chip),
+ .priv_auto = sizeof(struct nand_chip),
};
void board_nand_init(void)
.id = UCLASS_MTD,
.of_match = denali_nand_dt_ids,
.probe = denali_dt_probe,
- .priv_auto_alloc_size = sizeof(struct denali_nand_info),
+ .priv_auto = sizeof(struct denali_nand_info),
};
void board_nand_init(void)
.id = UCLASS_MTD,
.of_match = mxs_nand_dt_ids,
.probe = mxs_nand_dt_probe,
- .priv_auto_alloc_size = sizeof(struct mxs_nand_info),
+ .priv_auto = sizeof(struct mxs_nand_info),
};
void board_nand_init(void)
.id = UCLASS_MISC,
.probe = octeontx_pci_bchpf_probe,
.remove = octeontx_pci_bchpf_remove,
- .priv_auto_alloc_size = sizeof(struct bch_device),
+ .priv_auto = sizeof(struct bch_device),
.flags = DM_FLAG_OS_PREPARE,
};
.name = BCHVF_DRIVER_NAME,
.id = UCLASS_MISC,
.probe = octeontx_pci_bchvf_probe,
- .priv_auto_alloc_size = sizeof(struct bch_vf),
+ .priv_auto = sizeof(struct bch_vf),
};
U_BOOT_PCI_DEVICE(octeontx_pci_bchpf, octeontx_bchpf_pci_id_table);
{}
};
-static int octeontx_nand_ofdata_to_platdata(struct udevice *dev)
+static int octeontx_nand_of_to_plat(struct udevice *dev)
{
return 0;
}
.name = OCTEONTX_NAND_DRIVER_NAME,
.id = UCLASS_MTD,
.of_match = of_match_ptr(octeontx_nand_ids),
- .ofdata_to_platdata = octeontx_nand_ofdata_to_platdata,
+ .of_to_plat = octeontx_nand_of_to_plat,
.probe = octeontx_pci_nand_probe,
- .priv_auto_alloc_size = sizeof(struct octeontx_nfc),
+ .priv_auto = sizeof(struct octeontx_nfc),
.remove = octeontx_pci_nand_disable,
.flags = DM_FLAG_OS_PREPARE,
};
.id = UCLASS_MTD,
.of_match = pxa3xx_nand_dt_ids,
.probe = pxa3xx_nand_probe,
- .priv_auto_alloc_size = sizeof(struct pxa3xx_nand_info) +
+ .priv_auto = sizeof(struct pxa3xx_nand_info) +
sizeof(struct pxa3xx_nand_host) * CONFIG_SYS_MAX_NAND_DEVICE,
};
.id = UCLASS_MTD,
.of_match = stm32_fmc2_nfc_match,
.probe = stm32_fmc2_nfc_probe,
- .priv_auto_alloc_size = sizeof(struct stm32_fmc2_nfc),
+ .priv_auto = sizeof(struct stm32_fmc2_nfc),
};
void board_nand_init(void)
.id = UCLASS_MTD,
.of_match = tegra_nand_dt_ids,
.probe = tegra_probe,
- .priv_auto_alloc_size = sizeof(struct tegra_nand_info),
+ .priv_auto = sizeof(struct tegra_nand_info),
};
void board_nand_init(void)
.name = "vf610-nfc-dt",
.id = UCLASS_MTD,
.of_match = vf610_nfc_dt_ids,
- .priv_auto_alloc_size = sizeof(struct vf610_nfc),
+ .priv_auto = sizeof(struct vf610_nfc),
.probe = vf610_nfc_dt_probe,
};
.id = UCLASS_MTD,
.of_match = zynq_nand_dt_ids,
.probe = zynq_nand_probe,
- .priv_auto_alloc_size = sizeof(struct zynq_nand_info),
+ .priv_auto = sizeof(struct zynq_nand_info),
};
void board_nand_init(void)
.name = "spi_nand",
.id = UCLASS_MTD,
.of_match = spinand_ids,
- .priv_auto_alloc_size = sizeof(struct spinand_device),
+ .priv_auto = sizeof(struct spinand_device),
.probe = spinand_probe,
};
to handle the common case when only a single serial
flash is present on the system.
Not used for boot with device tree; the SPI driver reads
- speed and mode from platdata values computed from
+ speed and mode from plat values computed from
available node.
config SF_DEFAULT_SPEED
to handle the common case when only a single serial
flash is present on the system.
Not used for boot with device tree; the SPI driver reads
- speed and mode from platdata values computed from
+ speed and mode from plat values computed from
available node.
if SPI_FLASH
struct sandbox_spi_flash *sbsf = dev_get_priv(dev);
size_t len, idname_len;
const struct flash_info *data;
- struct sandbox_spi_flash_plat_data *pdata = dev_get_platdata(dev);
+ struct sandbox_spi_flash_plat_data *pdata = dev_get_plat(dev);
struct sandbox_state *state = state_get_current();
- struct dm_spi_slave_platdata *slave_plat;
+ struct dm_spi_slave_plat *slave_plat;
struct udevice *bus = dev->parent;
const char *spec = NULL;
struct udevice *emul;
dev->name);
return ret;
}
- slave_plat = dev_get_parent_platdata(dev);
+ slave_plat = dev_get_parent_plat(dev);
cs = slave_plat->cs;
debug("found at cs %d\n", cs);
return pos == bytes ? 0 : -EIO;
}
-int sandbox_sf_ofdata_to_platdata(struct udevice *dev)
+int sandbox_sf_of_to_plat(struct udevice *dev)
{
- struct sandbox_spi_flash_plat_data *pdata = dev_get_platdata(dev);
+ struct sandbox_spi_flash_plat_data *pdata = dev_get_plat(dev);
pdata->filename = dev_read_string(dev, "sandbox,filename");
pdata->device_name = dev_read_string(dev, "compatible");
str = strdup(name);
if (!str)
return -ENOMEM;
- ret = device_bind_ofnode(bus, drv, str, NULL, node, &emul);
+ ret = device_bind(bus, drv, str, NULL, node, &emul);
if (ret) {
free(str);
printf("Cannot create emul device for spec '%s' (err=%d)\n",
.name = "sandbox_sf_emul",
.id = UCLASS_SPI_EMUL,
.of_match = sandbox_sf_ids,
- .ofdata_to_platdata = sandbox_sf_ofdata_to_platdata,
+ .of_to_plat = sandbox_sf_of_to_plat,
.probe = sandbox_sf_probe,
.remove = sandbox_sf_remove,
- .priv_auto_alloc_size = sizeof(struct sandbox_spi_flash),
- .platdata_auto_alloc_size = sizeof(struct sandbox_spi_flash_plat_data),
+ .priv_auto = sizeof(struct sandbox_spi_flash),
+ .plat_auto = sizeof(struct sandbox_spi_flash_plat_data),
.ops = &sandbox_sf_emul_ops,
};
.id = UCLASS_SPI_FLASH,
.name = "spi_flash",
.post_bind = spi_flash_post_bind,
- .per_device_auto_alloc_size = sizeof(struct spi_flash),
+ .per_device_auto = sizeof(struct spi_flash),
};
.id = UCLASS_SPI_FLASH,
.of_match = spi_dataflash_ids,
.probe = spi_dataflash_probe,
- .priv_auto_alloc_size = sizeof(struct dataflash),
+ .priv_auto = sizeof(struct dataflash),
.ops = &spi_dataflash_ops,
};
.of_match = spi_flash_std_ids,
.probe = spi_flash_std_probe,
.remove = spi_flash_std_remove,
- .priv_auto_alloc_size = sizeof(struct spi_flash),
+ .priv_auto = sizeof(struct spi_flash),
.ops = &spi_flash_std_ops,
};
.id = UCLASS_MUX,
.name = "mux",
.post_probe = mux_uclass_post_probe,
- .per_device_auto_alloc_size = sizeof(struct mux_chip),
+ .per_device_auto = sizeof(struct mux_chip),
};
*/
static int ag7xxx_eth_write_hwaddr(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
unsigned char *mac = pdata->enetaddr;
u32 macid_lo, macid_hi;
static int ag7xxx_eth_probe(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
void __iomem *iobase, *phyiobase;
int ret, phyreg;
.write_hwaddr = ag7xxx_eth_write_hwaddr,
};
-static int ag7xxx_eth_ofdata_to_platdata(struct udevice *dev)
+static int ag7xxx_eth_of_to_plat(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
const char *phy_mode;
int ret;
.name = "eth_ag7xxx",
.id = UCLASS_ETH,
.of_match = ag7xxx_eth_ids,
- .ofdata_to_platdata = ag7xxx_eth_ofdata_to_platdata,
+ .of_to_plat = ag7xxx_eth_of_to_plat,
.probe = ag7xxx_eth_probe,
.remove = ag7xxx_eth_remove,
.ops = &ag7xxx_eth_ops,
- .priv_auto_alloc_size = sizeof(struct ar7xxx_eth_priv),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct ar7xxx_eth_priv),
+ .plat_auto = sizeof(struct eth_pdata),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
{
struct altera_tse_priv *priv = dev_get_priv(dev);
struct alt_tse_mac *mac_dev = priv->mac_dev;
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
u8 *hwaddr = pdata->enetaddr;
u32 mac_lo, mac_hi;
static int altera_tse_probe(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct altera_tse_priv *priv = dev_get_priv(dev);
void *blob = (void *)gd->fdt_blob;
int node = dev_of_offset(dev);
return ret;
}
-static int altera_tse_ofdata_to_platdata(struct udevice *dev)
+static int altera_tse_of_to_plat(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
const char *phy_mode;
pdata->phy_interface = -1;
.id = UCLASS_ETH,
.of_match = altera_tse_ids,
.ops = &altera_tse_ops,
- .ofdata_to_platdata = altera_tse_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
- .priv_auto_alloc_size = sizeof(struct altera_tse_priv),
+ .of_to_plat = altera_tse_of_to_plat,
+ .plat_auto = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct altera_tse_priv),
.probe = altera_tse_probe,
};
static int bcm6348_eth_write_hwaddr(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct bcm6348_eth_priv *priv = dev_get_priv(dev);
bool running = false;
static int bcm6348_phy_init(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct bcm6348_eth_priv *priv = dev_get_priv(dev);
struct mii_dev *bus;
static int bcm6348_eth_probe(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct bcm6348_eth_priv *priv = dev_get_priv(dev);
struct ofnode_phandle_args phy;
const char *phy_mode;
.id = UCLASS_ETH,
.of_match = bcm6348_eth_ids,
.ops = &bcm6348_eth_ops,
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
- .priv_auto_alloc_size = sizeof(struct bcm6348_eth_priv),
+ .plat_auto = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct bcm6348_eth_priv),
.probe = bcm6348_eth_probe,
};
static int bcm6368_eth_probe(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct bcm6368_eth_priv *priv = dev_get_priv(dev);
int num_ports, ret, i;
ofnode node;
.id = UCLASS_ETH,
.of_match = bcm6368_eth_ids,
.ops = &bcm6368_eth_ops,
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
- .priv_auto_alloc_size = sizeof(struct bcm6368_eth_priv),
+ .plat_auto = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct bcm6368_eth_priv),
.probe = bcm6368_eth_probe,
};
static int bcmgenet_gmac_write_hwaddr(struct udevice *dev)
{
struct bcmgenet_eth_priv *priv = dev_get_priv(dev);
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
uchar *addr = pdata->enetaddr;
u32 reg;
static int bcmgenet_eth_probe(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct bcmgenet_eth_priv *priv = dev_get_priv(dev);
ofnode mdio_node;
const char *name;
.stop = bcmgenet_gmac_eth_stop,
};
-static int bcmgenet_eth_ofdata_to_platdata(struct udevice *dev)
+static int bcmgenet_eth_of_to_plat(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct bcmgenet_eth_priv *priv = dev_get_priv(dev);
struct ofnode_phandle_args phy_node;
const char *phy_mode;
.name = "eth_bcmgenet",
.id = UCLASS_ETH,
.of_match = bcmgenet_eth_ids,
- .ofdata_to_platdata = bcmgenet_eth_ofdata_to_platdata,
+ .of_to_plat = bcmgenet_eth_of_to_plat,
.probe = bcmgenet_eth_probe,
.ops = &bcmgenet_gmac_eth_ops,
- .priv_auto_alloc_size = sizeof(struct bcmgenet_eth_priv),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct bcmgenet_eth_priv),
+ .plat_auto = sizeof(struct eth_pdata),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
#else /* DM_ETH */
static int dc2114x_start(struct udevice *dev)
{
- struct eth_pdata *plat = dev_get_platdata(dev);
+ struct eth_pdata *plat = dev_get_plat(dev);
struct dc2114x_priv *priv = dev_get_priv(dev);
memcpy(priv->enetaddr, plat->enetaddr, sizeof(plat->enetaddr));
static int dc2114x_probe(struct udevice *dev)
{
- struct eth_pdata *plat = dev_get_platdata(dev);
+ struct eth_pdata *plat = dev_get_plat(dev);
struct dc2114x_priv *priv = dev_get_priv(dev);
u16 command, status;
u32 iobase;
.bind = dc2114x_bind,
.probe = dc2114x_probe,
.ops = &dc2114x_ops,
- .priv_auto_alloc_size = sizeof(struct dc2114x_priv),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct dc2114x_priv),
+ .plat_auto = sizeof(struct eth_pdata),
};
U_BOOT_PCI_DEVICE(eth_dc2114x, supported);
{
struct udevice *dev = bus->priv;
struct dw_eth_dev *priv = dev_get_priv(dev);
- struct dw_eth_pdata *pdata = dev_get_platdata(dev);
+ struct dw_eth_pdata *pdata = dev_get_plat(dev);
int ret;
if (!dm_gpio_is_valid(&priv->reset_gpio))
#ifdef CONFIG_DM_ETH
static int designware_eth_start(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct dw_eth_dev *priv = dev_get_priv(dev);
int ret;
int designware_eth_write_hwaddr(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct dw_eth_dev *priv = dev_get_priv(dev);
return _dw_write_hwaddr(priv, pdata->enetaddr);
int designware_eth_probe(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct dw_eth_dev *priv = dev_get_priv(dev);
u32 iobase = pdata->iobase;
ulong ioaddr;
#ifdef CONFIG_DM_PCI
/*
* If we are on PCI bus, either directly attached to a PCI root port,
- * or via a PCI bridge, fill in platdata before we probe the hardware.
+ * or via a PCI bridge, fill in plat before we probe the hardware.
*/
if (device_is_on_pci_bus(dev)) {
dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase);
.write_hwaddr = designware_eth_write_hwaddr,
};
-int designware_eth_ofdata_to_platdata(struct udevice *dev)
+int designware_eth_of_to_plat(struct udevice *dev)
{
- struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev);
+ struct dw_eth_pdata *dw_pdata = dev_get_plat(dev);
#if CONFIG_IS_ENABLED(DM_GPIO)
struct dw_eth_dev *priv = dev_get_priv(dev);
#endif
.name = "eth_designware",
.id = UCLASS_ETH,
.of_match = designware_eth_ids,
- .ofdata_to_platdata = designware_eth_ofdata_to_platdata,
+ .of_to_plat = designware_eth_of_to_plat,
.bind = designware_eth_bind,
.probe = designware_eth_probe,
.remove = designware_eth_remove,
.ops = &designware_eth_ops,
- .priv_auto_alloc_size = sizeof(struct dw_eth_dev),
- .platdata_auto_alloc_size = sizeof(struct dw_eth_pdata),
+ .priv_auto = sizeof(struct dw_eth_dev),
+ .plat_auto = sizeof(struct dw_eth_pdata),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
};
#ifdef CONFIG_DM_ETH
-int designware_eth_ofdata_to_platdata(struct udevice *dev);
+int designware_eth_of_to_plat(struct udevice *dev);
int designware_eth_probe(struct udevice *dev);
extern const struct eth_ops designware_eth_ops;
static int eqos_write_hwaddr(struct udevice *dev)
{
- struct eth_pdata *plat = dev_get_platdata(dev);
+ struct eth_pdata *plat = dev_get_plat(dev);
struct eqos_priv *eqos = dev_get_priv(dev);
uint32_t val;
static int eqos_read_rom_hwaddr(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
#ifdef CONFIG_ARCH_IMX8M
imx_get_mac_from_fuse(dev->req_seq, pdata->enetaddr);
.probe = eqos_probe,
.remove = eqos_remove,
.ops = &eqos_ops,
- .priv_auto_alloc_size = sizeof(struct eqos_priv),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct eqos_priv),
+ .plat_auto = sizeof(struct eth_pdata),
};
return designware_eth_probe(dev);
}
-static int dwmac_s700_ofdata_to_platdata(struct udevice *dev)
+static int dwmac_s700_of_to_plat(struct udevice *dev)
{
- return designware_eth_ofdata_to_platdata(dev);
+ return designware_eth_of_to_plat(dev);
}
static const struct udevice_id dwmac_s700_ids[] = {
.name = "dwmac_s700",
.id = UCLASS_ETH,
.of_match = dwmac_s700_ids,
- .ofdata_to_platdata = dwmac_s700_ofdata_to_platdata,
+ .of_to_plat = dwmac_s700_of_to_plat,
.probe = dwmac_s700_probe,
.ops = &designware_eth_ops,
- .priv_auto_alloc_size = sizeof(struct dw_eth_dev),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct dw_eth_dev),
+ .plat_auto = sizeof(struct eth_pdata),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
#include <asm/arch/system_manager.h>
-struct dwmac_socfpga_platdata {
+struct dwmac_socfpga_plat {
struct dw_eth_pdata dw_eth_pdata;
void *phy_intf;
u32 reg_shift;
};
-static int dwmac_socfpga_ofdata_to_platdata(struct udevice *dev)
+static int dwmac_socfpga_of_to_plat(struct udevice *dev)
{
- struct dwmac_socfpga_platdata *pdata = dev_get_platdata(dev);
+ struct dwmac_socfpga_plat *pdata = dev_get_plat(dev);
struct regmap *regmap;
struct ofnode_phandle_args args;
void *range;
pdata->phy_intf = range + args.args[0];
pdata->reg_shift = args.args[1];
- return designware_eth_ofdata_to_platdata(dev);
+ return designware_eth_of_to_plat(dev);
}
static int dwmac_socfpga_probe(struct udevice *dev)
{
- struct dwmac_socfpga_platdata *pdata = dev_get_platdata(dev);
+ struct dwmac_socfpga_plat *pdata = dev_get_plat(dev);
struct eth_pdata *edata = &pdata->dw_eth_pdata.eth_pdata;
struct reset_ctl_bulk reset_bulk;
int ret;
.name = "dwmac_socfpga",
.id = UCLASS_ETH,
.of_match = dwmac_socfpga_ids,
- .ofdata_to_platdata = dwmac_socfpga_ofdata_to_platdata,
+ .of_to_plat = dwmac_socfpga_of_to_plat,
.probe = dwmac_socfpga_probe,
.ops = &designware_eth_ops,
- .priv_auto_alloc_size = sizeof(struct dw_eth_dev),
- .platdata_auto_alloc_size = sizeof(struct dwmac_socfpga_platdata),
+ .priv_auto = sizeof(struct dw_eth_dev),
+ .plat_auto = sizeof(struct dwmac_socfpga_plat),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
e1000_name(name, cardnum);
ret = uclass_get_device_by_name(UCLASS_ETH, name, &dev);
if (!ret) {
- plat = dev_get_platdata(dev);
+ plat = dev_get_plat(dev);
mac = plat->enetaddr;
}
#else
#ifdef CONFIG_DM_ETH
static int e1000_eth_start(struct udevice *dev)
{
- struct eth_pdata *plat = dev_get_platdata(dev);
+ struct eth_pdata *plat = dev_get_plat(dev);
struct e1000_hw *hw = dev_get_priv(dev);
return _e1000_init(hw, plat->enetaddr);
static int e1000_eth_probe(struct udevice *dev)
{
- struct eth_pdata *plat = dev_get_platdata(dev);
+ struct eth_pdata *plat = dev_get_plat(dev);
struct e1000_hw *hw = dev_get_priv(dev);
int ret;
.bind = e1000_eth_bind,
.probe = e1000_eth_probe,
.ops = &e1000_eth_ops,
- .priv_auto_alloc_size = sizeof(struct e1000_hw),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct e1000_hw),
+ .plat_auto = sizeof(struct eth_pdata),
};
U_BOOT_PCI_DEVICE(eth_e1000, e1000_supported);
#else /* DM_ETH */
static int eepro100_start(struct udevice *dev)
{
- struct eth_pdata *plat = dev_get_platdata(dev);
+ struct eth_pdata *plat = dev_get_plat(dev);
struct eepro100_priv *priv = dev_get_priv(dev);
memcpy(priv->enetaddr, plat->enetaddr, sizeof(plat->enetaddr));
static int eepro100_probe(struct udevice *dev)
{
- struct eth_pdata *plat = dev_get_platdata(dev);
+ struct eth_pdata *plat = dev_get_plat(dev);
struct eepro100_priv *priv = dev_get_priv(dev);
u16 command, status;
u32 iobase;
.bind = eepro100_bind,
.probe = eepro100_probe,
.ops = &eepro100_ops,
- .priv_auto_alloc_size = sizeof(struct eepro100_priv),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct eepro100_priv),
+ .plat_auto = sizeof(struct eth_pdata),
};
U_BOOT_PCI_DEVICE(eth_eepro100, supported);
UCLASS_DRIVER(eth_phy_generic) = {
.id = UCLASS_ETH_PHY,
.name = "eth_phy_generic",
- .per_device_auto_alloc_size = sizeof(struct eth_phy_device_priv),
+ .per_device_auto = sizeof(struct eth_phy_device_priv),
};
U_BOOT_DRIVER(eth_phy_generic_drv) = {
static int ethoc_write_hwaddr(struct udevice *dev)
{
- struct ethoc_eth_pdata *pdata = dev_get_platdata(dev);
+ struct ethoc_eth_pdata *pdata = dev_get_plat(dev);
struct ethoc *priv = dev_get_priv(dev);
u8 *mac = pdata->eth_pdata.enetaddr;
ethoc_stop_common(dev_get_priv(dev));
}
-static int ethoc_ofdata_to_platdata(struct udevice *dev)
+static int ethoc_of_to_plat(struct udevice *dev)
{
- struct ethoc_eth_pdata *pdata = dev_get_platdata(dev);
+ struct ethoc_eth_pdata *pdata = dev_get_plat(dev);
fdt_addr_t addr;
pdata->eth_pdata.iobase = dev_read_addr(dev);
static int ethoc_probe(struct udevice *dev)
{
- struct ethoc_eth_pdata *pdata = dev_get_platdata(dev);
+ struct ethoc_eth_pdata *pdata = dev_get_plat(dev);
struct ethoc *priv = dev_get_priv(dev);
priv->iobase = ioremap(pdata->eth_pdata.iobase, ETHOC_IOSIZE);
.name = "ethoc",
.id = UCLASS_ETH,
.of_match = ethoc_ids,
- .ofdata_to_platdata = ethoc_ofdata_to_platdata,
+ .of_to_plat = ethoc_of_to_plat,
.probe = ethoc_probe,
.remove = ethoc_remove,
.ops = ðoc_ops,
- .priv_auto_alloc_size = sizeof(struct ethoc),
- .platdata_auto_alloc_size = sizeof(struct ethoc_eth_pdata),
+ .priv_auto = sizeof(struct ethoc),
+ .plat_auto = sizeof(struct ethoc_eth_pdata),
};
#else
{
#ifdef CONFIG_DM_ETH
struct fec_priv *fec = dev_get_priv(dev);
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
uchar *mac = pdata->enetaddr;
#else
uchar *mac = dev->enetaddr;
static int fecmxc_read_rom_hwaddr(struct udevice *dev)
{
struct fec_priv *priv = dev_get_priv(dev);
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
return fec_get_hwaddr(priv->dev_id, pdata->enetaddr);
}
static int fecmxc_probe(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct fec_priv *priv = dev_get_priv(dev);
struct mii_dev *bus = NULL;
uint32_t start;
return 0;
}
-static int fecmxc_ofdata_to_platdata(struct udevice *dev)
+static int fecmxc_of_to_plat(struct udevice *dev)
{
int ret = 0;
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct fec_priv *priv = dev_get_priv(dev);
const char *phy_mode;
.name = "fecmxc",
.id = UCLASS_ETH,
.of_match = fecmxc_ids,
- .ofdata_to_platdata = fecmxc_ofdata_to_platdata,
+ .of_to_plat = fecmxc_of_to_plat,
.probe = fecmxc_probe,
.remove = fecmxc_remove,
.ops = &fecmxc_ops,
- .priv_auto_alloc_size = sizeof(struct fec_priv),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct fec_priv),
+ .plat_auto = sizeof(struct eth_pdata),
};
#endif
#ifndef CONFIG_DM_ETH
struct fm_eth *fm_eth = dev->priv;
#else
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct fm_eth *fm_eth = dev_get_priv(dev);
#endif
unsigned char *enetaddr;
.probe = fm_eth_probe,
.remove = fm_eth_remove,
.ops = &fm_eth_ops,
- .priv_auto_alloc_size = sizeof(struct fm_eth),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct fm_eth),
+ .plat_auto = sizeof(struct eth_pdata),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
#endif /* CONFIG_DM_ETH */
.of_match = fman_ids,
.probe = fman_probe,
.remove = fman_remove,
- .priv_auto_alloc_size = sizeof(struct fman_priv),
+ .priv_auto = sizeof(struct fman_priv),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
#endif /* CONFIG_DM_ETH */
.probe = fm_mdio_probe,
.remove = fm_mdio_remove,
.ops = &fm_mdio_ops,
- .priv_auto_alloc_size = sizeof(struct fm_mdio_priv),
- .platdata_auto_alloc_size = sizeof(struct mdio_perdev_priv),
+ .priv_auto = sizeof(struct fm_mdio_priv),
+ .plat_auto = sizeof(struct mdio_perdev_priv),
};
#endif /* CONFIG_PHYLIB && CONFIG_DM_MDIO */
#endif /* CONFIG_DM_ETH */
enum mc_fixup_type type)
{
#ifdef CONFIG_DM_ETH
- struct eth_pdata *plat = dev_get_platdata(eth_dev);
+ struct eth_pdata *plat = dev_get_plat(eth_dev);
unsigned char *enetaddr = plat->enetaddr;
int eth_index = eth_dev->seq;
#else
/* sets up primary MAC addresses in DT/IERB */
void fdt_fixup_enetc_mac(void *blob)
{
- struct pci_child_platdata *ppdata;
+ struct pci_child_plat *ppdata;
struct eth_pdata *pdata;
struct udevice *dev;
struct uclass *uc;
strcmp(dev->driver->name, ENETC_DRIVER_NAME))
continue;
- pdata = dev_get_platdata(dev);
- ppdata = dev_get_parent_platdata(dev);
+ pdata = dev_get_plat(dev);
+ ppdata = dev_get_parent_plat(dev);
devfn = PCI_FUNC(ppdata->devfn);
enetc_set_ierb_primary_mac(dev, devfn, pdata->enetaddr);
static int enetc_ls1028a_write_hwaddr(struct udevice *dev)
{
- struct pci_child_platdata *ppdata = dev_get_parent_platdata(dev);
+ struct pci_child_plat *ppdata = dev_get_parent_plat(dev);
const int devfn_to_pf[] = {0, 1, 2, -1, -1, -1, 3};
- struct eth_pdata *plat = dev_get_platdata(dev);
+ struct eth_pdata *plat = dev_get_plat(dev);
int devfn = PCI_FUNC(ppdata->devfn);
u8 *addr = plat->enetaddr;
u32 lower, upper;
static int enetc_write_hwaddr(struct udevice *dev)
{
- struct eth_pdata *plat = dev_get_platdata(dev);
+ struct eth_pdata *plat = dev_get_plat(dev);
struct enetc_priv *priv = dev_get_priv(dev);
u8 *addr = plat->enetaddr;
.probe = enetc_probe,
.remove = enetc_remove,
.ops = &enetc_ops,
- .priv_auto_alloc_size = sizeof(struct enetc_priv),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct enetc_priv),
+ .plat_auto = sizeof(struct eth_pdata),
};
static struct pci_device_id enetc_ids[] = {
.bind = enetc_mdio_bind,
.probe = enetc_mdio_probe,
.ops = &enetc_mdio_ops,
- .priv_auto_alloc_size = sizeof(struct enetc_mdio_priv),
+ .priv_auto = sizeof(struct enetc_mdio_priv),
};
static struct pci_device_id enetc_mdio_ids[] = {
.of_match = fsl_ls_mdio_of_ids,
.probe = fsl_ls_mdio_probe,
.ops = &fsl_ls_mdio_ops,
- .priv_auto_alloc_size = sizeof(struct fsl_ls_mdio_priv),
+ .priv_auto = sizeof(struct fsl_ls_mdio_priv),
};
};
/*
- * Boot sequence, called just after mcffec_ofdata_to_platdata,
+ * Boot sequence, called just after mcffec_of_to_plat,
* as DM way, it replaces old mcffec_initialize.
*/
static int mcdmafec_probe(struct udevice *dev)
{
struct fec_info_dma *info = dev->priv;
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
int node = dev_of_offset(dev);
int retval;
const u32 *val;
/*
* Boot sequence, called 1st
*/
-static int mcdmafec_ofdata_to_platdata(struct udevice *dev)
+static int mcdmafec_of_to_plat(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
const u32 *val;
pdata->iobase = dev_read_addr(dev);
.name = "mcdmafec",
.id = UCLASS_ETH,
.of_match = mcdmafec_ids,
- .ofdata_to_platdata = mcdmafec_ofdata_to_platdata,
+ .of_to_plat = mcdmafec_of_to_plat,
.probe = mcdmafec_probe,
.remove = mcdmafec_remove,
.ops = &mcdmafec_ops,
- .priv_auto_alloc_size = sizeof(struct fec_info_dma),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct fec_info_dma),
+ .plat_auto = sizeof(struct eth_pdata),
};
.probe = tsec_mdio_probe,
.remove = tsec_mdio_remove,
.ops = &tsec_mdio_ops,
- .priv_auto_alloc_size = sizeof(struct tsec_mdio_priv),
- .platdata_auto_alloc_size = sizeof(struct mdio_perdev_priv),
+ .priv_auto = sizeof(struct tsec_mdio_priv),
+ .plat_auto = sizeof(struct mdio_perdev_priv),
};
#endif /* CONFIG_PHYLIB */
#endif /* CONFIG_DM_MDIO */
static int ftgmac100_start(struct udevice *dev)
{
- struct eth_pdata *plat = dev_get_platdata(dev);
+ struct eth_pdata *plat = dev_get_plat(dev);
struct ftgmac100_data *priv = dev_get_priv(dev);
struct ftgmac100 *ftgmac100 = priv->iobase;
struct phy_device *phydev = priv->phydev;
static int ftgmac100_write_hwaddr(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct ftgmac100_data *priv = dev_get_priv(dev);
return ftgmac100_set_mac(priv, pdata->enetaddr);
}
-static int ftgmac100_ofdata_to_platdata(struct udevice *dev)
+static int ftgmac100_of_to_plat(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct ftgmac100_data *priv = dev_get_priv(dev);
const char *phy_mode;
static int ftgmac100_probe(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct ftgmac100_data *priv = dev_get_priv(dev);
int ret;
.name = "ftgmac100",
.id = UCLASS_ETH,
.of_match = ftgmac100_ids,
- .ofdata_to_platdata = ftgmac100_ofdata_to_platdata,
+ .of_to_plat = ftgmac100_of_to_plat,
.probe = ftgmac100_probe,
.remove = ftgmac100_remove,
.ops = &ftgmac100_ops,
- .priv_auto_alloc_size = sizeof(struct ftgmac100_data),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct ftgmac100_data),
+ .plat_auto = sizeof(struct eth_pdata),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
#ifdef CONFIG_DM_ETH
static int ftmac100_start(struct udevice *dev)
{
- struct eth_pdata *plat = dev_get_platdata(dev);
+ struct eth_pdata *plat = dev_get_plat(dev);
struct ftmac100_data *priv = dev_get_priv(dev);
return _ftmac100_init(priv, plat->enetaddr);
int ftmac100_read_rom_hwaddr(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
eth_env_get_enetaddr("ethaddr", pdata->enetaddr);
return 0;
}
return NULL;
}
-static int ftmac100_ofdata_to_platdata(struct udevice *dev)
+static int ftmac100_of_to_plat(struct udevice *dev)
{
struct ftmac100_data *priv = dev_get_priv(dev);
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
const char *mac;
pdata->iobase = dev_read_addr(dev);
priv->iobase = pdata->iobase;
.id = UCLASS_ETH,
.of_match = ftmac100_ids,
.bind = ftmac100_bind,
- .ofdata_to_platdata = ftmac100_ofdata_to_platdata,
+ .of_to_plat = ftmac100_of_to_plat,
.probe = ftmac100_probe,
.ops = &ftmac100_ops,
- .priv_auto_alloc_size = sizeof(struct ftmac100_data),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct ftmac100_data),
+ .plat_auto = sizeof(struct eth_pdata),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
#endif
*
* dw_eth_pdata: Required platform data for designware driver (must be first)
*/
-struct gmac_rockchip_platdata {
+struct gmac_rockchip_plat {
struct dw_eth_pdata dw_eth_pdata;
bool clock_input;
int tx_delay;
struct rk_gmac_ops {
int (*fix_mac_speed)(struct dw_eth_dev *priv);
- void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata);
- void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata);
+ void (*set_to_rmii)(struct gmac_rockchip_plat *pdata);
+ void (*set_to_rgmii)(struct gmac_rockchip_plat *pdata);
};
-static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev)
+static int gmac_rockchip_of_to_plat(struct udevice *dev)
{
- struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
+ struct gmac_rockchip_plat *pdata = dev_get_plat(dev);
const char *string;
string = dev_read_string(dev, "clock_in_out");
if (pdata->rx_delay == -ENOENT)
pdata->rx_delay = dev_read_u32_default(dev, "rx-delay", 0x10);
- return designware_eth_ofdata_to_platdata(dev);
+ return designware_eth_of_to_plat(dev);
}
static int px30_gmac_fix_mac_speed(struct dw_eth_dev *priv)
return 0;
}
-static void px30_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
+static void px30_gmac_set_to_rmii(struct gmac_rockchip_plat *pdata)
{
struct px30_grf *grf;
enum {
PX30_GMAC_PHY_INTF_SEL_RMII);
}
-static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
+static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_plat *pdata)
{
struct rk322x_grf *grf;
enum {
pdata->tx_delay << RK3228_CLK_TX_DL_CFG_GMAC_SHIFT);
}
-static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
+static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_plat *pdata)
{
struct rk3288_grf *grf;
pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT);
}
-static void rk3308_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
+static void rk3308_gmac_set_to_rmii(struct gmac_rockchip_plat *pdata)
{
struct rk3308_grf *grf;
enum {
RK3308_GMAC_PHY_INTF_SEL_RMII);
}
-static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
+static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_plat *pdata)
{
struct rk3328_grf_regs *grf;
enum {
pdata->tx_delay << RK3328_CLK_TX_DL_CFG_GMAC_SHIFT);
}
-static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
+static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_plat *pdata)
{
struct rk3368_grf *grf;
enum {
pdata->tx_delay << RK3368_CLK_TX_DL_CFG_GMAC_SHIFT);
}
-static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
+static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_plat *pdata)
{
struct rk3399_grf_regs *grf;
pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT);
}
-static void rv1108_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
+static void rv1108_gmac_set_to_rmii(struct gmac_rockchip_plat *pdata)
{
struct rv1108_grf *grf;
static int gmac_rockchip_probe(struct udevice *dev)
{
- struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
+ struct gmac_rockchip_plat *pdata = dev_get_plat(dev);
struct rk_gmac_ops *ops =
(struct rk_gmac_ops *)dev_get_driver_data(dev);
- struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev);
+ struct dw_eth_pdata *dw_pdata = dev_get_plat(dev);
struct eth_pdata *eth_pdata = &dw_pdata->eth_pdata;
struct clk clk;
ulong rate;
static int gmac_rockchip_eth_start(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct dw_eth_dev *priv = dev_get_priv(dev);
struct rk_gmac_ops *ops =
(struct rk_gmac_ops *)dev_get_driver_data(dev);
.name = "gmac_rockchip",
.id = UCLASS_ETH,
.of_match = rockchip_gmac_ids,
- .ofdata_to_platdata = gmac_rockchip_ofdata_to_platdata,
+ .of_to_plat = gmac_rockchip_of_to_plat,
.probe = gmac_rockchip_probe,
.ops = &gmac_rockchip_eth_ops,
- .priv_auto_alloc_size = sizeof(struct dw_eth_dev),
- .platdata_auto_alloc_size = sizeof(struct gmac_rockchip_platdata),
+ .priv_auto = sizeof(struct dw_eth_dev),
+ .plat_auto = sizeof(struct gmac_rockchip_plat),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
static int higmac_write_hwaddr(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct higmac_priv *priv = dev_get_priv(dev);
unsigned char *mac = pdata->enetaddr;
u32 val;
return 0;
}
-static int higmac_ofdata_to_platdata(struct udevice *dev)
+static int higmac_of_to_plat(struct udevice *dev)
{
struct higmac_priv *priv = dev_get_priv(dev);
int phyintf = PHY_INTERFACE_MODE_NONE;
.name = "eth_higmac",
.id = UCLASS_ETH,
.of_match = higmac_ids,
- .ofdata_to_platdata = higmac_ofdata_to_platdata,
+ .of_to_plat = higmac_of_to_plat,
.probe = higmac_probe,
.remove = higmac_remove,
.ops = &higmac_ops,
- .priv_auto_alloc_size = sizeof(struct higmac_priv),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct higmac_priv),
+ .plat_auto = sizeof(struct eth_pdata),
};
static int ks8851_write_hwaddr(struct udevice *dev)
{
struct ks_net *ks = dev_get_priv(dev);
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
ks8851_mll_write_hwaddr_common(ks, pdata->enetaddr);
static int ks8851_read_rom_hwaddr(struct udevice *dev)
{
struct ks_net *ks = dev_get_priv(dev);
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
u16 addrl, addrm, addrh;
/* No EEPROM means no valid MAC address. */
return 0;
}
-static int ks8851_ofdata_to_platdata(struct udevice *dev)
+static int ks8851_of_to_plat(struct udevice *dev)
{
struct ks_net *ks = dev_get_priv(dev);
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
pdata->iobase = dev_read_addr(dev);
ks->iobase = pdata->iobase;
.id = UCLASS_ETH,
.of_match = ks8851_ids,
.bind = ks8851_bind,
- .ofdata_to_platdata = ks8851_ofdata_to_platdata,
+ .of_to_plat = ks8851_of_to_plat,
.probe = ks8851_probe,
.ops = &ks8851_ops,
- .priv_auto_alloc_size = sizeof(struct ks_net),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct ks_net),
+ .plat_auto = sizeof(struct eth_pdata),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
#endif
#ifdef CONFIG_DM_ETH
static int ldpaa_eth_open(struct udevice *dev)
{
- struct eth_pdata *plat = dev_get_platdata(dev);
+ struct eth_pdata *plat = dev_get_plat(dev);
struct ldpaa_eth_priv *priv = dev_get_priv(dev);
#else
static int ldpaa_eth_open(struct eth_device *net_dev, struct bd_info *bd)
return 0;
}
-static int ldpaa_eth_ofdata_to_platdata(struct udevice *dev)
+static int ldpaa_eth_of_to_plat(struct udevice *dev)
{
struct ldpaa_eth_priv *priv = dev_get_priv(dev);
const char *phy_mode_str;
.name = "ldpaa_eth",
.id = UCLASS_ETH,
.of_match = ldpaa_eth_of_ids,
- .ofdata_to_platdata = ldpaa_eth_ofdata_to_platdata,
+ .of_to_plat = ldpaa_eth_of_to_plat,
.bind = ldpaa_eth_bind,
.probe = ldpaa_eth_probe,
.ops = &ldpaa_eth_ops,
- .priv_auto_alloc_size = sizeof(struct ldpaa_eth_priv),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct ldpaa_eth_priv),
+ .plat_auto = sizeof(struct eth_pdata),
};
#else
static int macb_write_hwaddr(struct udevice *dev)
{
- struct eth_pdata *plat = dev_get_platdata(dev);
+ struct eth_pdata *plat = dev_get_plat(dev);
struct macb_device *macb = dev_get_priv(dev);
return _macb_write_hwaddr(macb, plat->enetaddr);
static int macb_eth_probe(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct macb_device *macb = dev_get_priv(dev);
const char *phy_mode;
int ret;
}
/**
- * macb_late_eth_ofdata_to_platdata
+ * macb_late_eth_of_to_plat
* @dev: udevice struct
* Returns 0 when operation success and negative errno number
* when operation failed.
*/
-int __weak macb_late_eth_ofdata_to_platdata(struct udevice *dev)
+int __weak macb_late_eth_of_to_plat(struct udevice *dev)
{
return 0;
}
-static int macb_eth_ofdata_to_platdata(struct udevice *dev)
+static int macb_eth_of_to_plat(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
pdata->iobase = (phys_addr_t)dev_remap_addr(dev);
if (!pdata->iobase)
return -EINVAL;
- return macb_late_eth_ofdata_to_platdata(dev);
+ return macb_late_eth_of_to_plat(dev);
}
static const struct macb_config sama5d4_config = {
.name = "eth_macb",
.id = UCLASS_ETH,
.of_match = macb_eth_ids,
- .ofdata_to_platdata = macb_eth_ofdata_to_platdata,
+ .of_to_plat = macb_eth_of_to_plat,
.probe = macb_eth_probe,
.remove = macb_eth_remove,
.ops = &macb_eth_ops,
- .priv_auto_alloc_size = sizeof(struct macb_device),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct macb_device),
+ .plat_auto = sizeof(struct eth_pdata),
};
#endif
};
/*
- * Boot sequence, called just after mcffec_ofdata_to_platdata,
+ * Boot sequence, called just after mcffec_of_to_plat,
* as DM way, it replaces old mcffec_initialize.
*/
static int mcffec_probe(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct fec_info_s *info = dev->priv;
int node = dev_of_offset(dev);
int retval, fec_idx;
/*
* Boot sequence, called 1st
*/
-static int mcffec_ofdata_to_platdata(struct udevice *dev)
+static int mcffec_of_to_plat(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
const u32 *val;
pdata->iobase = dev_read_addr(dev);
.name = "mcffec",
.id = UCLASS_ETH,
.of_match = mcffec_ids,
- .ofdata_to_platdata = mcffec_ofdata_to_platdata,
+ .of_to_plat = mcffec_of_to_plat,
.probe = mcffec_probe,
.remove = mcffec_remove,
.ops = &mcffec_ops,
- .priv_auto_alloc_size = sizeof(struct fec_info_s),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct fec_info_s),
+ .plat_auto = sizeof(struct eth_pdata),
};
.bind = ipq4019_mdio_bind,
.probe = ipq4019_mdio_probe,
.ops = &ipq4019_mdio_ops,
- .priv_auto_alloc_size = sizeof(struct ipq4019_mdio_priv),
+ .priv_auto = sizeof(struct ipq4019_mdio_priv),
};
.of_match = mdio_mux_i2creg_ids,
.probe = mdio_mux_i2creg_probe,
.ops = &mdio_mux_i2creg_ops,
- .priv_auto_alloc_size = sizeof(struct mdio_mux_i2creg_priv),
+ .priv_auto = sizeof(struct mdio_mux_i2creg_priv),
};
.of_match = mdio_mux_sandbox_ids,
.probe = mdio_mux_sandbox_probe,
.ops = &mdio_mux_sandbox_ops,
- .priv_auto_alloc_size = sizeof(struct mdio_mux_sandbox_priv),
+ .priv_auto = sizeof(struct mdio_mux_sandbox_priv),
};
.of_match = mdio_sandbox_ids,
.probe = mdio_sandbox_probe,
.ops = &mdio_sandbox_ops,
- .priv_auto_alloc_size = sizeof(struct mdio_sandbox_priv),
+ .priv_auto = sizeof(struct mdio_sandbox_priv),
};
static int jr2_write_hwaddr(struct udevice *dev)
{
struct jr2_private *priv = dev_get_priv(dev);
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
return jr2_mac_table_add(priv, pdata->enetaddr, PGID_UNICAST);
}
static int jr2_start(struct udevice *dev)
{
struct jr2_private *priv = dev_get_priv(dev);
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
const unsigned char mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff,
0xff };
int ret;
.probe = jr2_probe,
.remove = jr2_remove,
.ops = &jr2_ops,
- .priv_auto_alloc_size = sizeof(struct jr2_private),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct jr2_private),
+ .plat_auto = sizeof(struct eth_pdata),
};
static int luton_write_hwaddr(struct udevice *dev)
{
struct luton_private *priv = dev_get_priv(dev);
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
mscc_mac_table_add(priv->regs[ANA], luton_regs_ana_table,
pdata->enetaddr, PGID_UNICAST);
static int luton_start(struct udevice *dev)
{
struct luton_private *priv = dev_get_priv(dev);
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
const unsigned char mac[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff,
0xff };
int ret;
.probe = luton_probe,
.remove = luton_remove,
.ops = &luton_ops,
- .priv_auto_alloc_size = sizeof(struct luton_private),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct luton_private),
+ .plat_auto = sizeof(struct eth_pdata),
};
static int ocelot_write_hwaddr(struct udevice *dev)
{
struct ocelot_private *priv = dev_get_priv(dev);
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
mscc_mac_table_add(priv->regs[ANA], ocelot_regs_ana_table,
pdata->enetaddr, PGID_UNICAST);
static int ocelot_start(struct udevice *dev)
{
struct ocelot_private *priv = dev_get_priv(dev);
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
const unsigned char mac[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff,
0xff };
int ret;
.probe = ocelot_probe,
.remove = ocelot_remove,
.ops = &ocelot_ops,
- .priv_auto_alloc_size = sizeof(struct ocelot_private),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct ocelot_private),
+ .plat_auto = sizeof(struct eth_pdata),
};
static int serval_write_hwaddr(struct udevice *dev)
{
struct serval_private *priv = dev_get_priv(dev);
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
mscc_mac_table_add(priv->regs[ANA], serval_regs_ana_table,
pdata->enetaddr, PGID_UNICAST);
static int serval_start(struct udevice *dev)
{
struct serval_private *priv = dev_get_priv(dev);
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
const unsigned char mac[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff,
0xff };
int ret;
.probe = serval_probe,
.remove = serval_remove,
.ops = &serval_ops,
- .priv_auto_alloc_size = sizeof(struct serval_private),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct serval_private),
+ .plat_auto = sizeof(struct eth_pdata),
};
static int servalt_write_hwaddr(struct udevice *dev)
{
struct servalt_private *priv = dev_get_priv(dev);
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
return servalt_mac_table_add(priv, pdata->enetaddr, PGID_UNICAST);
}
static int servalt_start(struct udevice *dev)
{
struct servalt_private *priv = dev_get_priv(dev);
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
const unsigned char mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff,
0xff };
int ret;
.probe = servalt_probe,
.remove = servalt_remove,
.ops = &servalt_ops,
- .priv_auto_alloc_size = sizeof(struct servalt_private),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct servalt_private),
+ .plat_auto = sizeof(struct eth_pdata),
};
{
struct mt7628_eth_dev *priv = dev_get_priv(dev);
void __iomem *base = priv->base;
- u8 *addr = ((struct eth_pdata *)dev_get_platdata(dev))->enetaddr;
+ u8 *addr = ((struct eth_pdata *)dev_get_plat(dev))->enetaddr;
u32 val;
/* Set MAC address. */
.of_match = mt7628_eth_ids,
.probe = mt7628_eth_probe,
.ops = &mt7628_eth_ops,
- .priv_auto_alloc_size = sizeof(struct mt7628_eth_dev),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct mt7628_eth_dev),
+ .plat_auto = sizeof(struct eth_pdata),
};
static int mtk_eth_write_hwaddr(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct mtk_eth_priv *priv = dev_get_priv(dev);
unsigned char *mac = pdata->enetaddr;
u32 macaddr_lsb, macaddr_msb;
static int mtk_eth_probe(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct mtk_eth_priv *priv = dev_get_priv(dev);
ulong iobase = pdata->iobase;
int ret;
return 0;
}
-static int mtk_eth_ofdata_to_platdata(struct udevice *dev)
+static int mtk_eth_of_to_plat(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct mtk_eth_priv *priv = dev_get_priv(dev);
struct ofnode_phandle_args args;
struct regmap *regmap;
.name = "mtk-eth",
.id = UCLASS_ETH,
.of_match = mtk_eth_ids,
- .ofdata_to_platdata = mtk_eth_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .of_to_plat = mtk_eth_of_to_plat,
+ .plat_auto = sizeof(struct eth_pdata),
.probe = mtk_eth_probe,
.remove = mtk_eth_remove,
.ops = &mtk_eth_ops,
- .priv_auto_alloc_size = sizeof(struct mtk_eth_priv),
+ .priv_auto = sizeof(struct mtk_eth_priv),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
#ifdef CONFIG_DM_ETH
static int mvgbe_write_hwaddr(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
port_uc_addr_set(dev_get_priv(dev), pdata->enetaddr);
static int mvgbe_start(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct mvgbe_device *dmvgbe = dev_get_priv(dev);
int ret;
static int mvgbe_probe(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct mvgbe_device *dmvgbe = dev_get_priv(dev);
struct mii_dev *bus;
int ret;
.write_hwaddr = mvgbe_write_hwaddr,
};
-static int mvgbe_ofdata_to_platdata(struct udevice *dev)
+static int mvgbe_of_to_plat(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct mvgbe_device *dmvgbe = dev_get_priv(dev);
void *blob = (void *)gd->fdt_blob;
int node = dev_of_offset(dev);
.name = "mvgbe",
.id = UCLASS_ETH,
.of_match = mvgbe_ids,
- .ofdata_to_platdata = mvgbe_ofdata_to_platdata,
+ .of_to_plat = mvgbe_of_to_plat,
.probe = mvgbe_probe,
.ops = &mvgbe_ops,
- .priv_auto_alloc_size = sizeof(struct mvgbe_device),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct mvgbe_device),
+ .plat_auto = sizeof(struct eth_pdata),
};
#endif /* CONFIG_DM_ETH */
.bind = mvmdio_bind,
.probe = mvmdio_probe,
.ops = &mvmdio_ops,
- .priv_auto_alloc_size = sizeof(struct mvmdio_priv),
+ .priv_auto = sizeof(struct mvmdio_priv),
};
static int mvneta_write_hwaddr(struct udevice *dev)
{
mvneta_mac_addr_set(dev_get_priv(dev),
- ((struct eth_pdata *)dev_get_platdata(dev))->enetaddr,
+ ((struct eth_pdata *)dev_get_plat(dev))->enetaddr,
rxq_def);
return 0;
/* Device initialization routine */
static int mvneta_init(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct mvneta_port *pp = dev_get_priv(dev);
int err;
static int mvneta_probe(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct mvneta_port *pp = dev_get_priv(dev);
void *blob = (void *)gd->fdt_blob;
int node = dev_of_offset(dev);
else
mvneta_conf_mbus_windows(pp);
- /* PHY interface is already decoded in mvneta_ofdata_to_platdata() */
+ /* PHY interface is already decoded in mvneta_of_to_plat() */
pp->phy_interface = pdata->phy_interface;
/* fetch 'fixed-link' property from 'neta' node */
.write_hwaddr = mvneta_write_hwaddr,
};
-static int mvneta_ofdata_to_platdata(struct udevice *dev)
+static int mvneta_of_to_plat(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
const char *phy_mode;
pdata->iobase = dev_read_addr(dev);
.name = "mvneta",
.id = UCLASS_ETH,
.of_match = mvneta_ids,
- .ofdata_to_platdata = mvneta_ofdata_to_platdata,
+ .of_to_plat = mvneta_of_to_plat,
.probe = mvneta_probe,
.ops = &mvneta_ops,
- .priv_auto_alloc_size = sizeof(struct mvneta_port),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct mvneta_port),
+ .plat_auto = sizeof(struct eth_pdata),
};
static int mvpp2_start(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct mvpp2_port *port = dev_get_priv(dev);
/* Load current MAC address */
.probe = mvpp2_probe,
.remove = mvpp2_remove,
.ops = &mvpp2_ops,
- .priv_auto_alloc_size = sizeof(struct mvpp2_port),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct mvpp2_port),
+ .plat_auto = sizeof(struct eth_pdata),
.flags = DM_FLAG_ACTIVE_DMA,
};
sprintf(name, "mvpp2-%d", id);
/* Create child device UCLASS_ETH and bind it */
- device_bind(parent, &mvpp2_driver, name, plat, subnode, &dev);
- dev_set_of_offset(dev, subnode);
+ device_bind(parent, &mvpp2_driver, name, plat,
+ offset_to_ofnode(subnode), &dev);
}
return 0;
.id = UCLASS_MISC,
.of_match = mvpp2_ids,
.bind = mvpp2_base_bind,
- .priv_auto_alloc_size = sizeof(struct mvpp2),
+ .priv_auto = sizeof(struct mvpp2),
};
.id = UCLASS_MISC,
.probe = octeontx_bgx_probe,
.remove = octeontx_bgx_remove,
- .priv_auto_alloc_size = sizeof(struct bgx),
+ .priv_auto = sizeof(struct bgx),
.flags = DM_FLAG_OS_PREPARE,
};
.name = "octeontx_nic",
.id = UCLASS_MISC,
.probe = octeontx_nic_probe,
- .priv_auto_alloc_size = sizeof(struct nicpf),
+ .priv_auto = sizeof(struct nicpf),
};
static struct pci_device_id octeontx_nic_supported[] = {
static void nicvf_handle_mbx_intr(struct nicvf *nic)
{
union nic_mbx mbx = {};
- struct eth_pdata *pdata = dev_get_platdata(nic->dev);
+ struct eth_pdata *pdata = dev_get_plat(nic->dev);
u64 *mbx_data;
u64 mbx_addr;
int i;
static int nicvf_hw_set_mac_addr(struct nicvf *nic, struct udevice *dev)
{
union nic_mbx mbx = {};
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
mbx.mac.msg = NIC_MBOX_MSG_SET_MAC;
mbx.mac.vf_id = nic->vf_id;
int nicvf_write_hwaddr(struct udevice *dev)
{
unsigned char ethaddr[ARP_HLEN];
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct nicvf *nic = dev_get_priv(dev);
/* If lower level firmware fails to set proper MAC
int nicvf_initialize(struct udevice *dev)
{
struct nicvf *nicvf = dev_get_priv(dev);
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
int ret = 0, bgx, lmac;
char name[16];
unsigned char ethaddr[ARP_HLEN];
.id = UCLASS_ETH,
.probe = octeontx_vnic_probe,
.ops = &octeontx_vnic_ops,
- .priv_auto_alloc_size = sizeof(struct nicvf),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct nicvf),
+ .plat_auto = sizeof(struct eth_pdata),
};
static struct pci_device_id octeontx_vnic_supported[] = {
.id = UCLASS_MISC,
.probe = cgx_probe,
.remove = cgx_remove,
- .priv_auto_alloc_size = sizeof(struct cgx),
+ .priv_auto = sizeof(struct cgx),
};
static struct pci_device_id cgx_supported[] = {
{
struct rvu_pf *rvu = dev_get_priv(dev);
struct nix *nix = rvu->nix;
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
/* If lower level firmware fails to set proper MAC
* u-boot framework updates MAC to random address.
.id = UCLASS_MISC,
.probe = rvu_af_probe,
.remove = rvu_af_remove,
- .priv_auto_alloc_size = sizeof(struct rvu_af),
+ .priv_auto = sizeof(struct rvu_af),
};
static struct pci_device_id rvu_af_supported[] = {
int rvu_pf_init(struct rvu_pf *rvu)
{
struct nix *nix;
- struct eth_pdata *pdata = dev_get_platdata(rvu->dev);
+ struct eth_pdata *pdata = dev_get_plat(rvu->dev);
debug("%s: Allocating nix lf\n", __func__);
nix = nix_lf_alloc(rvu->dev);
.probe = rvu_pf_probe,
.remove = rvu_pf_remove,
.ops = &nix_eth_ops,
- .priv_auto_alloc_size = sizeof(struct rvu_pf),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct rvu_pf),
+ .plat_auto = sizeof(struct eth_pdata),
};
static struct pci_device_id rvu_pf_supported[] = {
static int pch_gbe_reset(struct udevice *dev)
{
struct pch_gbe_priv *priv = dev_get_priv(dev);
- struct eth_pdata *plat = dev_get_platdata(dev);
+ struct eth_pdata *plat = dev_get_plat(dev);
struct pch_gbe_regs *mac_regs = priv->mac_regs;
ulong start;
static int pch_gbe_phy_init(struct udevice *dev)
{
struct pch_gbe_priv *priv = dev_get_priv(dev);
- struct eth_pdata *plat = dev_get_platdata(dev);
+ struct eth_pdata *plat = dev_get_plat(dev);
struct phy_device *phydev;
int mask = 0xffffffff;
static int pch_gbe_probe(struct udevice *dev)
{
struct pch_gbe_priv *priv;
- struct eth_pdata *plat = dev_get_platdata(dev);
+ struct eth_pdata *plat = dev_get_plat(dev);
void *iobase;
int err;
.probe = pch_gbe_probe,
.remove = pch_gbe_remove,
.ops = &pch_gbe_ops,
- .priv_auto_alloc_size = sizeof(struct pch_gbe_priv),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct pch_gbe_priv),
+ .plat_auto = sizeof(struct eth_pdata),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
#else /* DM_ETH */
static int pcnet_start(struct udevice *dev)
{
- struct eth_pdata *plat = dev_get_platdata(dev);
+ struct eth_pdata *plat = dev_get_plat(dev);
struct pcnet_priv *priv = dev_get_priv(dev);
memcpy(priv->enetaddr, plat->enetaddr, sizeof(plat->enetaddr));
static int pcnet_probe(struct udevice *dev)
{
- struct eth_pdata *plat = dev_get_platdata(dev);
+ struct eth_pdata *plat = dev_get_plat(dev);
struct pcnet_priv *lp = dev_get_priv(dev);
u16 command, status;
u32 iobase;
.bind = pcnet_bind,
.probe = pcnet_probe,
.ops = &pcnet_ops,
- .priv_auto_alloc_size = sizeof(struct pcnet_priv),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct pcnet_priv),
+ .plat_auto = sizeof(struct eth_pdata),
.flags = DM_UC_FLAG_ALLOC_PRIV_DMA,
};
{
struct pfe_eth_dev *priv = dev_get_priv(dev);
struct gemac_s *gem = priv->gem;
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
uchar *mac = pdata->enetaddr;
writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
{
struct pfe_eth_dev *priv = dev_get_priv(dev);
struct pfe_ddr_address pfe_addr;
- struct pfe_eth_pdata *pdata = dev_get_platdata(dev);
+ struct pfe_eth_pdata *pdata = dev_get_plat(dev);
int ret = 0;
static int init_done;
static int pfe_eth_bind(struct udevice *dev)
{
- struct pfe_eth_pdata *pdata = dev_get_platdata(dev);
+ struct pfe_eth_pdata *pdata = dev_get_plat(dev);
char name[20];
sprintf(name, "pfe_eth%u", pdata->pfe_eth_pdata_mac.phy_interface);
.probe = pfe_eth_probe,
.remove = pfe_eth_remove,
.ops = &pfe_eth_ops,
- .priv_auto_alloc_size = sizeof(struct pfe_eth_dev),
- .platdata_auto_alloc_size = sizeof(struct pfe_eth_pdata)
+ .priv_auto = sizeof(struct pfe_eth_dev),
+ .plat_auto = sizeof(struct pfe_eth_pdata)
};
static int pic32_eth_start(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct pic32eth_dev *priv = dev_get_priv(dev);
/* controller */
static int pic32_eth_probe(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct pic32eth_dev *priv = dev_get_priv(dev);
const char *phy_mode;
void __iomem *iobase;
.probe = pic32_eth_probe,
.remove = pic32_eth_remove,
.ops = &pic32_eth_ops,
- .priv_auto_alloc_size = sizeof(struct pic32eth_dev),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct pic32eth_dev),
+ .plat_auto = sizeof(struct eth_pdata),
};
static int qe_uec_set_hwaddr(struct udevice *dev)
{
struct qe_uec_priv *priv = dev_get_priv(dev);
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct uec_priv *uec = priv->uec;
uec_t *uec_regs = uec->uec_regs;
uchar *mac = pdata->enetaddr;
static int qe_uec_set_uec_info(struct udevice *dev)
{
struct qe_uec_priv *priv = dev_get_priv(dev);
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct uec_priv *uec = priv->uec;
struct uec_inf *uec_info;
struct ucc_fast_inf *uf_info;
static int qe_uec_probe(struct udevice *dev)
{
struct qe_uec_priv *priv = dev_get_priv(dev);
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct uec_priv *uec;
int ret;
return 0;
}
-static int qe_uec_ofdata_to_platdata(struct udevice *dev)
+static int qe_uec_of_to_plat(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
const char *phy_mode;
pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
.name = QE_UEC_DRIVER_NAME,
.id = UCLASS_ETH,
.of_match = qe_uec_ids,
- .ofdata_to_platdata = qe_uec_ofdata_to_platdata,
+ .of_to_plat = qe_uec_of_to_plat,
.probe = qe_uec_probe,
.remove = qe_uec_remove,
.ops = &qe_uec_eth_ops,
- .priv_auto_alloc_size = sizeof(struct qe_uec_priv),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct qe_uec_priv),
+ .plat_auto = sizeof(struct eth_pdata),
};
.of_match = qe_uec_mdio_ids,
.probe = qe_uec_mdio_probe,
.ops = &qe_uec_mdio_ops,
- .priv_auto_alloc_size = sizeof(struct qe_uec_mdio_priv),
+ .priv_auto = sizeof(struct qe_uec_mdio_priv),
};
static int ravb_phy_config(struct udevice *dev)
{
struct ravb_priv *eth = dev_get_priv(dev);
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct phy_device *phydev;
int mask = 0xffffffff, reg;
static int ravb_write_hwaddr(struct udevice *dev)
{
struct ravb_priv *eth = dev_get_priv(dev);
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
unsigned char *mac = pdata->enetaddr;
writel((mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3],
static int ravb_dmac_init(struct udevice *dev)
{
struct ravb_priv *eth = dev_get_priv(dev);
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
int ret = 0;
/* Set CONFIG mode */
static int ravb_probe(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct ravb_priv *eth = dev_get_priv(dev);
struct ofnode_phandle_args phandle_args;
struct mii_dev *mdiodev;
.write_hwaddr = ravb_write_hwaddr,
};
-int ravb_ofdata_to_platdata(struct udevice *dev)
+int ravb_of_to_plat(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
const char *phy_mode;
const fdt32_t *cell;
int ret = 0;
.name = "ravb",
.id = UCLASS_ETH,
.of_match = ravb_ids,
- .ofdata_to_platdata = ravb_ofdata_to_platdata,
+ .of_to_plat = ravb_of_to_plat,
.probe = ravb_probe,
.remove = ravb_remove,
.ops = &ravb_ops,
- .priv_auto_alloc_size = sizeof(struct ravb_priv),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct ravb_priv),
+ .plat_auto = sizeof(struct eth_pdata),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
#else /* DM_ETH */
static int rtl8139_start(struct udevice *dev)
{
- struct eth_pdata *plat = dev_get_platdata(dev);
+ struct eth_pdata *plat = dev_get_plat(dev);
struct rtl8139_priv *priv = dev_get_priv(dev);
memcpy(priv->enetaddr, plat->enetaddr, sizeof(plat->enetaddr));
static int rtl8139_write_hwaddr(struct udevice *dev)
{
- struct eth_pdata *plat = dev_get_platdata(dev);
+ struct eth_pdata *plat = dev_get_plat(dev);
struct rtl8139_priv *priv = dev_get_priv(dev);
memcpy(priv->enetaddr, plat->enetaddr, sizeof(plat->enetaddr));
static int rtl8139_probe(struct udevice *dev)
{
- struct eth_pdata *plat = dev_get_platdata(dev);
+ struct eth_pdata *plat = dev_get_plat(dev);
struct rtl8139_priv *priv = dev_get_priv(dev);
u32 iobase;
.bind = rtl8139_bind,
.probe = rtl8139_probe,
.ops = &rtl8139_ops,
- .priv_auto_alloc_size = sizeof(struct rtl8139_priv),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct rtl8139_priv),
+ .plat_auto = sizeof(struct eth_pdata),
};
U_BOOT_PCI_DEVICE(eth_rtl8139, supported);
#ifdef CONFIG_DM_ETH
static int rtl8169_eth_start(struct udevice *dev)
{
- struct eth_pdata *plat = dev_get_platdata(dev);
+ struct eth_pdata *plat = dev_get_plat(dev);
struct rtl8169_private *priv = dev_get_priv(dev);
rtl8169_common_start(dev, plat->enetaddr, priv->iobase);
#ifdef CONFIG_DM_ETH
static int rtl8169_write_hwaddr(struct udevice *dev)
{
- struct eth_pdata *plat = dev_get_platdata(dev);
+ struct eth_pdata *plat = dev_get_plat(dev);
unsigned int i;
RTL_W8(Cfg9346, Cfg9346_Unlock);
#ifdef CONFIG_DM_ETH
static int rtl8169_eth_probe(struct udevice *dev)
{
- struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
+ struct pci_child_plat *pplat = dev_get_parent_plat(dev);
struct rtl8169_private *priv = dev_get_priv(dev);
- struct eth_pdata *plat = dev_get_platdata(dev);
+ struct eth_pdata *plat = dev_get_plat(dev);
u32 iobase;
int region;
int ret;
.of_match = rtl8169_eth_ids,
.probe = rtl8169_eth_probe,
.ops = &rtl8169_eth_ops,
- .priv_auto_alloc_size = sizeof(struct rtl8169_private),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct rtl8169_private),
+ .plat_auto = sizeof(struct eth_pdata),
};
U_BOOT_PCI_DEVICE(eth_rtl8169, supported);
static int sb_eth_raw_start(struct udevice *dev)
{
struct eth_sandbox_raw_priv *priv = dev_get_priv(dev);
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
int ret;
debug("eth_sandbox_raw: Start\n");
static int sb_eth_raw_recv(struct udevice *dev, int flags, uchar **packetp)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct eth_sandbox_raw_priv *priv = dev_get_priv(dev);
int retval = 0;
int length;
static int sb_eth_raw_read_rom_hwaddr(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
net_random_ethaddr(pdata->enetaddr);
.read_rom_hwaddr = sb_eth_raw_read_rom_hwaddr,
};
-static int sb_eth_raw_ofdata_to_platdata(struct udevice *dev)
+static int sb_eth_raw_of_to_plat(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct eth_sandbox_raw_priv *priv = dev_get_priv(dev);
const char *ifname;
int ret;
.name = "eth_sandbox_raw",
.id = UCLASS_ETH,
.of_match = sb_eth_raw_ids,
- .ofdata_to_platdata = sb_eth_raw_ofdata_to_platdata,
+ .of_to_plat = sb_eth_raw_of_to_plat,
.ops = &sb_eth_raw_ops,
- .priv_auto_alloc_size = sizeof(struct eth_sandbox_raw_priv),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct eth_sandbox_raw_priv),
+ .plat_auto = sizeof(struct eth_pdata),
};
static int sb_eth_write_hwaddr(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
debug("eth_sandbox %s: Write HW ADDR - %pM\n", dev->name,
pdata->enetaddr);
return 0;
}
-static int sb_eth_ofdata_to_platdata(struct udevice *dev)
+static int sb_eth_of_to_plat(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct eth_sandbox_priv *priv = dev_get_priv(dev);
const u8 *mac;
.name = "eth_sandbox",
.id = UCLASS_ETH,
.of_match = sb_eth_ids,
- .ofdata_to_platdata = sb_eth_ofdata_to_platdata,
+ .of_to_plat = sb_eth_of_to_plat,
.remove = sb_eth_remove,
.ops = &sb_eth_ops,
- .priv_auto_alloc_size = sizeof(struct eth_sandbox_priv),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct eth_sandbox_priv),
+ .plat_auto = sizeof(struct eth_pdata),
};
struct sh_ether_priv *priv = dev_get_priv(dev);
struct sh_eth_dev *eth = &priv->shdev;
struct sh_eth_info *port_info = ð->port_info[eth->port];
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
sh_eth_write_hwaddr(port_info, pdata->enetaddr);
static int sh_eth_phy_config(struct udevice *dev)
{
struct sh_ether_priv *priv = dev_get_priv(dev);
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct sh_eth_dev *eth = &priv->shdev;
int ret = 0;
struct sh_eth_info *port_info = ð->port_info[eth->port];
static int sh_ether_start(struct udevice *dev)
{
struct sh_ether_priv *priv = dev_get_priv(dev);
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct sh_eth_dev *eth = &priv->shdev;
int ret;
static int sh_ether_probe(struct udevice *udev)
{
- struct eth_pdata *pdata = dev_get_platdata(udev);
+ struct eth_pdata *pdata = dev_get_plat(udev);
struct sh_ether_priv *priv = dev_get_priv(udev);
struct sh_eth_dev *eth = &priv->shdev;
struct ofnode_phandle_args phandle_args;
.write_hwaddr = sh_ether_write_hwaddr,
};
-int sh_ether_ofdata_to_platdata(struct udevice *dev)
+int sh_ether_of_to_plat(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
const char *phy_mode;
const fdt32_t *cell;
int ret = 0;
.name = "sh_ether",
.id = UCLASS_ETH,
.of_match = sh_ether_ids,
- .ofdata_to_platdata = sh_ether_ofdata_to_platdata,
+ .of_to_plat = sh_ether_of_to_plat,
.probe = sh_ether_probe,
.remove = sh_ether_remove,
.ops = &sh_ether_ops,
- .priv_auto_alloc_size = sizeof(struct sh_ether_priv),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct sh_ether_priv),
+ .plat_auto = sizeof(struct eth_pdata),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
#endif
static int smc911x_start(struct udevice *dev)
{
- struct eth_pdata *plat = dev_get_platdata(dev);
+ struct eth_pdata *plat = dev_get_plat(dev);
struct smc911x_priv *priv = dev_get_priv(dev);
memcpy(priv->enetaddr, plat->enetaddr, sizeof(plat->enetaddr));
static int smc911x_read_rom_hwaddr(struct udevice *dev)
{
struct smc911x_priv *priv = dev_get_priv(dev);
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
if (!smc911x_read_mac_address(priv))
return -ENODEV;
return 0;
}
-static int smc911x_ofdata_to_platdata(struct udevice *dev)
+static int smc911x_of_to_plat(struct udevice *dev)
{
struct smc911x_priv *priv = dev_get_priv(dev);
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
pdata->iobase = dev_read_addr(dev);
priv->iobase = pdata->iobase;
.id = UCLASS_ETH,
.of_match = smc911x_ids,
.bind = smc911x_bind,
- .ofdata_to_platdata = smc911x_ofdata_to_platdata,
+ .of_to_plat = smc911x_of_to_plat,
.probe = smc911x_probe,
.ops = &smc911x_ops,
- .priv_auto_alloc_size = sizeof(struct smc911x_priv),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct smc911x_priv),
+ .plat_auto = sizeof(struct eth_pdata),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
#endif
static int ave_adjust_link(struct ave_private *priv)
{
struct phy_device *phydev = priv->phydev;
- struct eth_pdata *pdata = dev_get_platdata(phydev->dev);
+ struct eth_pdata *pdata = dev_get_plat(phydev->dev);
u32 val, txcr, rxcr, rxcr_org;
u16 rmt_adv = 0, lcl_adv = 0;
u8 cap;
static int ave_write_hwaddr(struct udevice *dev)
{
struct ave_private *priv = dev_get_priv(dev);
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
u8 *mac = pdata->enetaddr;
writel(mac[0] | mac[1] << 8 | mac[2] << 16 | mac[3] << 24,
return 0;
}
-static int ave_ofdata_to_platdata(struct udevice *dev)
+static int ave_of_to_plat(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct ave_private *priv = dev_get_priv(dev);
struct ofnode_phandle_args args;
const char *phy_mode;
static int ave_probe(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct ave_private *priv = dev_get_priv(dev);
int ret, nc, nr;
.of_match = ave_ids,
.probe = ave_probe,
.remove = ave_remove,
- .ofdata_to_platdata = ave_ofdata_to_platdata,
+ .of_to_plat = ave_of_to_plat,
.ops = &ave_ops,
- .priv_auto_alloc_size = sizeof(struct ave_private),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct ave_private),
+ .plat_auto = sizeof(struct eth_pdata),
};
static int sun8i_eth_write_hwaddr(struct udevice *dev)
{
struct emac_eth_dev *priv = dev_get_priv(dev);
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
uchar *mac_id = pdata->enetaddr;
u32 macid_lo, macid_hi;
{
struct udevice *dev = bus->priv;
struct emac_eth_dev *priv = dev_get_priv(dev);
- struct sun8i_eth_pdata *pdata = dev_get_platdata(dev);
+ struct sun8i_eth_pdata *pdata = dev_get_plat(dev);
int ret;
if (!dm_gpio_is_valid(&priv->reset_gpio))
static int sun8i_emac_eth_probe(struct udevice *dev)
{
- struct sun8i_eth_pdata *sun8i_pdata = dev_get_platdata(dev);
+ struct sun8i_eth_pdata *sun8i_pdata = dev_get_plat(dev);
struct eth_pdata *pdata = &sun8i_pdata->eth_pdata;
struct emac_eth_dev *priv = dev_get_priv(dev);
int ret;
return 0;
}
-static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev)
+static int sun8i_emac_eth_of_to_plat(struct udevice *dev)
{
- struct sun8i_eth_pdata *sun8i_pdata = dev_get_platdata(dev);
+ struct sun8i_eth_pdata *sun8i_pdata = dev_get_plat(dev);
struct eth_pdata *pdata = &sun8i_pdata->eth_pdata;
struct emac_eth_dev *priv = dev_get_priv(dev);
const char *phy_mode;
.name = "eth_sun8i_emac",
.id = UCLASS_ETH,
.of_match = sun8i_emac_eth_ids,
- .ofdata_to_platdata = sun8i_emac_eth_ofdata_to_platdata,
+ .of_to_plat = sun8i_emac_eth_of_to_plat,
.probe = sun8i_emac_eth_probe,
.ops = &sun8i_emac_eth_ops,
- .priv_auto_alloc_size = sizeof(struct emac_eth_dev),
- .platdata_auto_alloc_size = sizeof(struct sun8i_eth_pdata),
+ .priv_auto = sizeof(struct emac_eth_dev),
+ .plat_auto = sizeof(struct sun8i_eth_pdata),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
static int sunxi_emac_eth_start(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
return _sunxi_emac_eth_init(dev->priv, pdata->enetaddr);
}
static int sunxi_emac_eth_probe(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct emac_eth_dev *priv = dev_get_priv(dev);
int ret;
.stop = sunxi_emac_eth_stop,
};
-static int sunxi_emac_eth_ofdata_to_platdata(struct udevice *dev)
+static int sunxi_emac_eth_of_to_plat(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
pdata->iobase = dev_read_addr(dev);
.name = "eth_sunxi_emac",
.id = UCLASS_ETH,
.of_match = sunxi_emac_eth_ids,
- .ofdata_to_platdata = sunxi_emac_eth_ofdata_to_platdata,
+ .of_to_plat = sunxi_emac_eth_of_to_plat,
.probe = sunxi_emac_eth_probe,
.ops = &sunxi_emac_eth_ops,
- .priv_auto_alloc_size = sizeof(struct emac_eth_dev),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct emac_eth_dev),
+ .plat_auto = sizeof(struct eth_pdata),
};
static int am65_cpsw_start(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct am65_cpsw_priv *priv = dev_get_priv(dev);
struct am65_cpsw_common *common = priv->cpsw_common;
struct am65_cpsw_port *port = &common->ports[priv->port_id];
{
struct am65_cpsw_priv *priv = dev_get_priv(dev);
struct am65_cpsw_common *common = priv->cpsw_common;
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
u32 mac_hi, mac_lo;
if (common->mac_efuse == FDT_ADDR_T_NONE)
{
struct am65_cpsw_priv *priv = dev_get_priv(dev);
struct am65_cpsw_common *cpsw_common = priv->cpsw_common;
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct phy_device *phydev;
u32 supported = PHY_GBIT_FEATURES;
int ret;
static int am65_cpsw_ofdata_parse_phy(struct udevice *dev, ofnode port_np)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct am65_cpsw_priv *priv = dev_get_priv(dev);
struct ofnode_phandle_args out_args;
const char *phy_mode;
static int am65_cpsw_probe_cpsw(struct udevice *dev)
{
struct am65_cpsw_priv *priv = dev_get_priv(dev);
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct am65_cpsw_common *cpsw_common;
ofnode ports_np, node;
int ret, i;
.of_match = am65_cpsw_nuss_ids,
.probe = am65_cpsw_probe_cpsw,
.ops = &am65_cpsw_ops,
- .priv_auto_alloc_size = sizeof(struct am65_cpsw_priv),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct am65_cpsw_priv),
+ .plat_auto = sizeof(struct eth_pdata),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
struct cpsw_priv *priv)
{
#ifdef CONFIG_DM_ETH
- struct eth_pdata *pdata = dev_get_platdata(priv->dev);
+ struct eth_pdata *pdata = dev_get_plat(priv->dev);
writel(mac_hi(pdata->enetaddr), &slave->regs->sa_hi);
writel(mac_lo(pdata->enetaddr), &slave->regs->sa_lo);
#else
static int cpsw_eth_start(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct cpsw_priv *priv = dev_get_priv(dev);
return _cpsw_init(priv, pdata->enetaddr);
static int cpsw_eth_probe(struct udevice *dev)
{
struct cpsw_priv *priv = dev_get_priv(dev);
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
priv->dev = dev;
priv->data = pdata->priv_pdata;
"max-speed", 0);
}
-static int cpsw_eth_ofdata_to_platdata(struct udevice *dev)
+static int cpsw_eth_of_to_plat(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct cpsw_platform_data *data;
struct gpio_desc *mode_gpios;
int slave_index = 0;
.id = UCLASS_ETH,
#if CONFIG_IS_ENABLED(OF_CONTROL)
.of_match = cpsw_eth_ids,
- .ofdata_to_platdata = cpsw_eth_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .of_to_plat = cpsw_eth_of_to_plat,
+ .plat_auto = sizeof(struct eth_pdata),
#endif
.probe = cpsw_eth_probe,
.ops = &cpsw_eth_ops,
- .priv_auto_alloc_size = sizeof(struct cpsw_priv),
+ .priv_auto = sizeof(struct cpsw_priv),
.flags = DM_FLAG_ALLOC_PRIV_DMA | DM_FLAG_PRE_RELOC,
};
#endif /* CONFIG_DM_ETH */
static int davinci_emac_write_hwaddr(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
unsigned long mac_hi;
unsigned long mac_lo;
.of_match = davinci_emac_ids,
.probe = davinci_emac_probe,
.ops = &davinci_emac_ops,
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .plat_auto = sizeof(struct eth_pdata),
};
int ks2_eth_read_rom_hwaddr(struct udevice *dev)
{
struct ks2_eth_priv *priv = dev_get_priv(dev);
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
u32 maca = 0;
u32 macb = 0;
int ks2_eth_write_hwaddr(struct udevice *dev)
{
struct ks2_eth_priv *priv = dev_get_priv(dev);
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
writel(mac_hi(pdata->enetaddr),
DEVICE_EMACSW_BASE(pdata->iobase, priv->slave_port - 1) +
return 0;
}
-static int ks2_sl_eth_ofdata_to_platdata(struct udevice *dev)
+static int ks2_sl_eth_of_to_plat(struct udevice *dev)
{
struct ks2_eth_priv *priv = dev_get_priv(dev);
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
const void *fdt = gd->fdt_blob;
int slave = dev_of_offset(dev);
int interfaces;
return 0;
}
-static int ks2_eth_ofdata_to_platdata(struct udevice *dev)
+static int ks2_eth_of_to_plat(struct udevice *dev)
{
struct ks2_eth_priv *priv = dev_get_priv(dev);
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
const void *fdt = gd->fdt_blob;
int gbe_0 = -ENODEV;
int netcp_devices;
U_BOOT_DRIVER(eth_ks2_slave) = {
.name = "eth_ks2_sl",
.id = UCLASS_ETH,
- .ofdata_to_platdata = ks2_sl_eth_ofdata_to_platdata,
+ .of_to_plat = ks2_sl_eth_of_to_plat,
.probe = ks2_eth_probe,
.remove = ks2_eth_remove,
.ops = &ks2_eth_ops,
- .priv_auto_alloc_size = sizeof(struct ks2_eth_priv),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct ks2_eth_priv),
+ .plat_auto = sizeof(struct eth_pdata),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
.name = "eth_ks2",
.id = UCLASS_ETH,
.of_match = ks2_eth_ids,
- .ofdata_to_platdata = ks2_eth_ofdata_to_platdata,
+ .of_to_plat = ks2_eth_of_to_plat,
.probe = ks2_eth_probe,
.remove = ks2_eth_remove,
.ops = &ks2_eth_ops,
- .priv_auto_alloc_size = sizeof(struct ks2_eth_priv),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct ks2_eth_priv),
+ .plat_auto = sizeof(struct eth_pdata),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
{
struct tsec_private *priv = (struct tsec_private *)dev->priv;
#ifdef CONFIG_DM_ETH
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
#else
struct eth_device *pdata = dev;
#endif
#else /* CONFIG_DM_ETH */
int tsec_probe(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct tsec_private *priv = dev_get_priv(dev);
struct ofnode_phandle_args phandle_args;
u32 tbiaddr = CONFIG_SYS_TBIPA_VALUE;
.probe = tsec_probe,
.remove = tsec_remove,
.ops = &tsec_ops,
- .priv_auto_alloc_size = sizeof(struct tsec_private),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct tsec_private),
+ .plat_auto = sizeof(struct eth_pdata),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
#endif /* CONFIG_DM_ETH */
static int axiemac_write_hwaddr(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct axidma_priv *priv = dev_get_priv(dev);
struct axi_regs *regs = priv->iobase;
.write_hwaddr = axiemac_write_hwaddr,
};
-static int axi_emac_ofdata_to_platdata(struct udevice *dev)
+static int axi_emac_of_to_plat(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct axidma_priv *priv = dev_get_priv(dev);
int node = dev_of_offset(dev);
int offset = 0;
.name = "axi_emac",
.id = UCLASS_ETH,
.of_match = axi_emac_ids,
- .ofdata_to_platdata = axi_emac_ofdata_to_platdata,
+ .of_to_plat = axi_emac_of_to_plat,
.probe = axi_emac_probe,
.remove = axi_emac_remove,
.ops = &axi_emac_ops,
- .priv_auto_alloc_size = sizeof(struct axidma_priv),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct axidma_priv),
+ .plat_auto = sizeof(struct eth_pdata),
};
static int emaclite_start(struct udevice *dev)
{
struct xemaclite *emaclite = dev_get_priv(dev);
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct emaclite_regs *regs = emaclite->regs;
debug("EmacLite Initialization Started\n");
.stop = emaclite_stop,
};
-static int emaclite_ofdata_to_platdata(struct udevice *dev)
+static int emaclite_of_to_plat(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct xemaclite *emaclite = dev_get_priv(dev);
int offset = 0;
.name = "emaclite",
.id = UCLASS_ETH,
.of_match = emaclite_ids,
- .ofdata_to_platdata = emaclite_ofdata_to_platdata,
+ .of_to_plat = emaclite_of_to_plat,
.probe = emaclite_probe,
.remove = emaclite_remove,
.ops = &emaclite_ops,
- .priv_auto_alloc_size = sizeof(struct xemaclite),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct xemaclite),
+ .plat_auto = sizeof(struct eth_pdata),
};
static int zynq_gem_setup_mac(struct udevice *dev)
{
u32 i, macaddrlow, macaddrhigh;
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct zynq_gem_priv *priv = dev_get_priv(dev);
struct zynq_gem_regs *regs = priv->iobase;
static int zynq_gem_read_rom_mac(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
if (!pdata)
return -ENOSYS;
.read_rom_hwaddr = zynq_gem_read_rom_mac,
};
-static int zynq_gem_ofdata_to_platdata(struct udevice *dev)
+static int zynq_gem_of_to_plat(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct zynq_gem_priv *priv = dev_get_priv(dev);
struct ofnode_phandle_args phandle_args;
const char *phy_mode;
.name = "zynq_gem",
.id = UCLASS_ETH,
.of_match = zynq_gem_ids,
- .ofdata_to_platdata = zynq_gem_ofdata_to_platdata,
+ .of_to_plat = zynq_gem_of_to_plat,
.probe = zynq_gem_probe,
.remove = zynq_gem_remove,
.ops = &zynq_gem_ops,
- .priv_auto_alloc_size = sizeof(struct zynq_gem_priv),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct zynq_gem_priv),
+ .plat_auto = sizeof(struct eth_pdata),
};
static int nvme_blk_probe(struct udevice *udev)
{
struct nvme_dev *ndev = dev_get_priv(udev->parent);
- struct blk_desc *desc = dev_get_uclass_platdata(udev);
+ struct blk_desc *desc = dev_get_uclass_plat(udev);
struct nvme_ns *ns = dev_get_priv(udev);
u8 flbas;
- struct pci_child_platdata *pplat;
+ struct pci_child_plat *pplat;
struct nvme_id_ns *id;
id = memalign(ndev->page_size, sizeof(struct nvme_id_ns));
desc->log2blksz = ns->lba_shift;
desc->blksz = 1 << ns->lba_shift;
desc->bdev = udev;
- pplat = dev_get_parent_platdata(udev->parent);
+ pplat = dev_get_parent_plat(udev->parent);
sprintf(desc->vendor, "0x%.4x", pplat->vendor);
memcpy(desc->product, ndev->serial, sizeof(ndev->serial));
memcpy(desc->revision, ndev->firmware_rev, sizeof(ndev->firmware_rev));
struct nvme_ns *ns = dev_get_priv(udev);
struct nvme_dev *dev = ns->dev;
struct nvme_command c;
- struct blk_desc *desc = dev_get_uclass_platdata(udev);
+ struct blk_desc *desc = dev_get_uclass_plat(udev);
int status;
u64 prp2;
u64 total_len = blkcnt << desc->log2blksz;
.id = UCLASS_BLK,
.probe = nvme_blk_probe,
.ops = &nvme_blk_ops,
- .priv_auto_alloc_size = sizeof(struct nvme_ns),
+ .priv_auto = sizeof(struct nvme_ns),
};
static int nvme_bind(struct udevice *udev)
.id = UCLASS_NVME,
.bind = nvme_bind,
.probe = nvme_probe,
- .priv_auto_alloc_size = sizeof(struct nvme_dev),
+ .priv_auto = sizeof(struct nvme_dev),
};
struct pci_device_id nvme_supported[] = {
.id = UCLASS_PCH,
.of_match = sandbox_pch_ids,
.ops = &sandbox_pch_ops,
- .priv_auto_alloc_size = sizeof(struct sandbox_pch_priv),
+ .priv_auto = sizeof(struct sandbox_pch_priv),
};
}
/**
- * pcie_advk_ofdata_to_platdata() - Translate from DT to device state
+ * pcie_advk_of_to_plat() - Translate from DT to device state
*
* @dev: A pointer to the device being operated on
*
*
* Return: 0 on success, else -EINVAL
*/
-static int pcie_advk_ofdata_to_platdata(struct udevice *dev)
+static int pcie_advk_of_to_plat(struct udevice *dev)
{
struct pcie_advk *pcie = dev_get_priv(dev);
.id = UCLASS_PCI,
.of_match = pcie_advk_ids,
.ops = &pcie_advk_ops,
- .ofdata_to_platdata = pcie_advk_ofdata_to_platdata,
+ .of_to_plat = pcie_advk_of_to_plat,
.probe = pcie_advk_probe,
.remove = pcie_advk_remove,
.flags = DM_FLAG_OS_PREPARE,
- .priv_auto_alloc_size = sizeof(struct pcie_advk),
+ .priv_auto = sizeof(struct pcie_advk),
};
.name = "pci_emul",
.post_probe = sandbox_pci_emul_post_probe,
.pre_remove = sandbox_pci_emul_pre_remove,
- .priv_auto_alloc_size = sizeof(struct sandbox_pci_emul_priv),
- .per_device_auto_alloc_size = sizeof(struct pci_emul_uc_priv),
+ .priv_auto = sizeof(struct sandbox_pci_emul_priv),
+ .per_device_auto = sizeof(struct pci_emul_uc_priv),
};
/*
- * This uclass is a child of the pci bus. Its platdata is not defined here so
- * is defined by its parent, UCLASS_PCI, which uses struct pci_child_platdata.
- * See per_child_platdata_auto_alloc_size in UCLASS_DRIVER(pci).
+ * This uclass is a child of the pci bus. Its plat is not defined here so
+ * is defined by its parent, UCLASS_PCI, which uses struct pci_child_plat.
+ * See per_child_plat_auto in UCLASS_DRIVER(pci).
*/
UCLASS_DRIVER(pci_emul_parent) = {
.id = UCLASS_PCI_EMUL_PARENT,
return 0;
}
-static int rcar_gen2_pci_ofdata_to_platdata(struct udevice *dev)
+static int rcar_gen2_pci_of_to_plat(struct udevice *dev)
{
struct rcar_gen2_pci_priv *priv = dev_get_priv(dev);
.of_match = rcar_gen2_pci_ids,
.ops = &rcar_gen2_pci_ops,
.probe = rcar_gen2_pci_probe,
- .ofdata_to_platdata = rcar_gen2_pci_ofdata_to_platdata,
- .priv_auto_alloc_size = sizeof(struct rcar_gen2_pci_priv),
+ .of_to_plat = rcar_gen2_pci_of_to_plat,
+ .priv_auto = sizeof(struct rcar_gen2_pci_priv),
};
static void rcar_rmw32(struct udevice *dev, int where, u32 mask, u32 data)
{
- struct rcar_gen3_pcie_priv *priv = dev_get_platdata(dev);
+ struct rcar_gen3_pcie_priv *priv = dev_get_plat(dev);
int shift = 8 * (where & 3);
clrsetbits_le32(priv->regs + (where & ~3),
static u32 rcar_read_conf(const struct udevice *dev, int where)
{
- struct rcar_gen3_pcie_priv *priv = dev_get_platdata(dev);
+ struct rcar_gen3_pcie_priv *priv = dev_get_plat(dev);
int shift = 8 * (where & 3);
return readl(priv->regs + (where & ~3)) >> shift;
unsigned char access_type,
pci_dev_t bdf, int where, ulong *data)
{
- struct rcar_gen3_pcie_priv *priv = dev_get_platdata(udev);
+ struct rcar_gen3_pcie_priv *priv = dev_get_plat(udev);
u32 reg = where & ~3;
/* Clear errors */
static int rcar_gen3_pcie_wait_for_phyrdy(struct udevice *dev)
{
- struct rcar_gen3_pcie_priv *priv = dev_get_platdata(dev);
+ struct rcar_gen3_pcie_priv *priv = dev_get_plat(dev);
return wait_for_bit_le32((void *)priv->regs + PCIEPHYSR, PHYRDY,
true, 50, false);
static int rcar_gen3_pcie_wait_for_dl(struct udevice *dev)
{
- struct rcar_gen3_pcie_priv *priv = dev_get_platdata(dev);
+ struct rcar_gen3_pcie_priv *priv = dev_get_plat(dev);
return wait_for_bit_le32((void *)priv->regs + PCIETSTR,
DATA_LINK_ACTIVE, true, 50, false);
static int rcar_gen3_pcie_hw_init(struct udevice *dev)
{
- struct rcar_gen3_pcie_priv *priv = dev_get_platdata(dev);
+ struct rcar_gen3_pcie_priv *priv = dev_get_plat(dev);
int ret;
/* Begin initialization */
static int rcar_gen3_pcie_probe(struct udevice *dev)
{
- struct rcar_gen3_pcie_priv *priv = dev_get_platdata(dev);
+ struct rcar_gen3_pcie_priv *priv = dev_get_plat(dev);
struct pci_controller *hose = dev_get_uclass_priv(dev);
struct clk pci_clk;
u32 mask;
return 0;
}
-static int rcar_gen3_pcie_ofdata_to_platdata(struct udevice *dev)
+static int rcar_gen3_pcie_of_to_plat(struct udevice *dev)
{
- struct rcar_gen3_pcie_priv *priv = dev_get_platdata(dev);
+ struct rcar_gen3_pcie_priv *priv = dev_get_plat(dev);
priv->regs = devfdt_get_addr_index(dev, 0);
if (!priv->regs)
.of_match = rcar_gen3_pcie_ids,
.ops = &rcar_gen3_pcie_ops,
.probe = rcar_gen3_pcie_probe,
- .ofdata_to_platdata = rcar_gen3_pcie_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct rcar_gen3_pcie_priv),
+ .of_to_plat = rcar_gen3_pcie_of_to_plat,
+ .plat_auto = sizeof(struct rcar_gen3_pcie_priv),
};
pci_dev_t dm_pci_get_bdf(const struct udevice *dev)
{
- struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
+ struct pci_child_plat *pplat = dev_get_parent_plat(dev);
struct udevice *bus = dev->parent;
/*
* will produce a bad BDF>
*
* A common cause of this problem is that this function is called in the
- * ofdata_to_platdata() method of @dev. Accessing the PCI bus in that
+ * of_to_plat() method of @dev. Accessing the PCI bus in that
* method is not allowed, since it has not yet been probed. To fix this,
* move that access to the probe() method of @dev instead.
*/
for (device_find_first_child(bus, &dev);
dev;
device_find_next_child(&dev)) {
- struct pci_child_platdata *pplat;
+ struct pci_child_plat *pplat;
- pplat = dev_get_parent_platdata(dev);
+ pplat = dev_get_parent_plat(dev);
if (pplat && pplat->devfn == find_devfn) {
*devp = dev;
return 0;
static int pci_device_matches_ids(struct udevice *dev,
struct pci_device_id *ids)
{
- struct pci_child_platdata *pplat;
+ struct pci_child_plat *pplat;
int i;
- pplat = dev_get_parent_platdata(dev);
+ pplat = dev_get_parent_plat(dev);
if (!pplat)
return -EINVAL;
for (i = 0; ids[i].vendor != 0; i++) {
unsigned int device, int *indexp,
struct udevice **devp)
{
- struct pci_child_platdata *pplat;
+ struct pci_child_plat *pplat;
struct udevice *dev;
for (device_find_first_child(bus, &dev);
dev;
device_find_next_child(&dev)) {
- pplat = dev_get_parent_platdata(dev);
+ pplat = dev_get_parent_plat(dev);
if (pplat->vendor == vendor && pplat->device == device) {
if (!(*indexp)--) {
*devp = dev;
for (pci_find_first_device(&dev);
dev;
pci_find_next_device(&dev)) {
- struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
+ struct pci_child_plat *pplat = dev_get_parent_plat(dev);
if (pplat->class == find_class && !index--) {
*devp = dev;
int pci_auto_config_devices(struct udevice *bus)
{
struct pci_controller *hose = bus->uclass_priv;
- struct pci_child_platdata *pplat;
+ struct pci_child_plat *pplat;
unsigned int sub_bus;
struct udevice *dev;
int ret;
max_bus = ret;
sub_bus = max(sub_bus, max_bus);
- pplat = dev_get_parent_platdata(dev);
+ pplat = dev_get_parent_plat(dev);
if (pplat->class == (PCI_CLASS_DISPLAY_VGA << 8))
set_vga_bridge_bits(dev);
}
/*
* We could pass the descriptor to the driver as
- * platdata (instead of NULL) and allow its bind()
+ * plat (instead of NULL) and allow its bind()
* method to return -ENOENT if it doesn't support this
* device. That way we could continue the search to
* find another driver. For now this doesn't seem
* necesssary, so just bind the first match.
*/
- ret = device_bind_ofnode(parent, drv, drv->name, NULL,
- node, &dev);
+ ret = device_bind(parent, drv, drv->name, NULL, node,
+ &dev);
if (ret)
goto error;
debug("%s: Match found: %s\n", __func__, drv->name);
PCI_MAX_PCI_FUNCTIONS - 1);
for (bdf = PCI_BDF(bus->seq, 0, 0); bdf <= end;
bdf += PCI_BDF(0, 0, 1)) {
- struct pci_child_platdata *pplat;
+ struct pci_child_plat *pplat;
struct udevice *dev;
ulong class;
return ret;
/* Update the platform data */
- pplat = dev_get_parent_platdata(dev);
+ pplat = dev_get_parent_plat(dev);
pplat->devfn = PCI_MASK_BUS(bdf);
pplat->vendor = vendor;
pplat->device = device;
static int pci_uclass_child_post_bind(struct udevice *dev)
{
- struct pci_child_platdata *pplat;
+ struct pci_child_plat *pplat;
if (!dev_of_valid(dev))
return 0;
- pplat = dev_get_parent_platdata(dev);
+ pplat = dev_get_parent_plat(dev);
/* Extract vendor id and device id if available */
ofnode_read_pci_vendev(dev_ofnode(dev), &pplat->vendor, &pplat->device);
}
static phys_addr_t dm_pci_map_ea_virt(struct udevice *dev, int ea_off,
- struct pci_child_platdata *pdata)
+ struct pci_child_plat *pdata)
{
phys_addr_t addr = 0;
}
static void *dm_pci_map_ea_bar(struct udevice *dev, int bar, int flags,
- int ea_off, struct pci_child_platdata *pdata)
+ int ea_off, struct pci_child_plat *pdata)
{
int ea_cnt, i, entry_size;
int bar_id = (bar - PCI_BASE_ADDRESS_0) >> 2;
void *dm_pci_map_bar(struct udevice *dev, int bar, int flags)
{
- struct pci_child_platdata *pdata = dev_get_parent_platdata(dev);
+ struct pci_child_plat *pdata = dev_get_parent_plat(dev);
struct udevice *udev = dev;
pci_addr_t pci_bus_addr;
u32 bar_response;
bdf += PCI_BDF(0, 0, vf_offset);
for (vf = 0; vf < num_vfs; vf++) {
- struct pci_child_platdata *pplat;
+ struct pci_child_plat *pplat;
ulong class;
pci_bus_read_config(bus, bdf, PCI_CLASS_DEVICE,
}
/* Update the platform data */
- pplat = dev_get_parent_platdata(dev);
+ pplat = dev_get_parent_plat(dev);
pplat->devfn = PCI_MASK_BUS(bdf);
pplat->vendor = vendor;
pplat->device = device;
.pre_probe = pci_uclass_pre_probe,
.post_probe = pci_uclass_post_probe,
.child_post_bind = pci_uclass_child_post_bind,
- .per_device_auto_alloc_size = sizeof(struct pci_controller),
- .per_child_platdata_auto_alloc_size =
- sizeof(struct pci_child_platdata),
+ .per_device_auto = sizeof(struct pci_controller),
+ .per_child_plat_auto = sizeof(struct pci_child_plat),
};
static const struct dm_pci_ops pci_bridge_ops = {
return 0;
}
-static int mpc85xx_pci_ofdata_to_platdata(struct udevice *dev)
+static int mpc85xx_pci_of_to_plat(struct udevice *dev)
{
struct mpc85xx_pci_priv *priv = dev_get_priv(dev);
fdt_addr_t addr;
.ops = &mpc85xx_pci_ops,
.probe = mpc85xx_pci_dm_probe,
.remove = mpc85xx_pci_dm_remove,
- .ofdata_to_platdata = mpc85xx_pci_ofdata_to_platdata,
- .priv_auto_alloc_size = sizeof(struct mpc85xx_pci_priv),
+ .of_to_plat = mpc85xx_pci_of_to_plat,
+ .priv_auto = sizeof(struct mpc85xx_pci_priv),
};
uint offset, ulong *valuep,
enum pci_size_t size)
{
- struct mvebu_pcie *pcie = dev_get_platdata(bus);
+ struct mvebu_pcie *pcie = dev_get_plat(bus);
int local_bus = PCI_BUS(pcie->dev);
int local_dev = PCI_DEV(pcie->dev);
u32 reg;
uint offset, ulong value,
enum pci_size_t size)
{
- struct mvebu_pcie *pcie = dev_get_platdata(bus);
+ struct mvebu_pcie *pcie = dev_get_plat(bus);
int local_bus = PCI_BUS(pcie->dev);
int local_dev = PCI_DEV(pcie->dev);
u32 data;
static int mvebu_pcie_probe(struct udevice *dev)
{
- struct mvebu_pcie *pcie = dev_get_platdata(dev);
+ struct mvebu_pcie *pcie = dev_get_plat(dev);
struct udevice *ctlr = pci_get_controller(dev);
struct pci_controller *hose = dev_get_uclass_priv(ctlr);
static int bus;
return -ENOENT;
}
-static int mvebu_pcie_ofdata_to_platdata(struct udevice *dev)
+static int mvebu_pcie_of_to_plat(struct udevice *dev)
{
- struct mvebu_pcie *pcie = dev_get_platdata(dev);
+ struct mvebu_pcie *pcie = dev_get_plat(dev);
int ret = 0;
/* Get port number, lane number and memory target / attr */
.id = UCLASS_PCI,
.ops = &mvebu_pcie_ops,
.probe = mvebu_pcie_probe,
- .ofdata_to_platdata = mvebu_pcie_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct mvebu_pcie),
+ .of_to_plat = mvebu_pcie_of_to_plat,
+ .plat_auto = sizeof(struct mvebu_pcie),
};
/*
return -ENOMEM;
/* Create child device UCLASS_PCI and bind it */
- device_bind_ofnode(parent, &pcie_mvebu_drv, pcie->name, pcie,
- subnode, &dev);
+ device_bind(parent, &pcie_mvebu_drv, pcie->name, pcie, subnode,
+ &dev);
}
return 0;
return ret;
}
-static int pci_octeontx_ofdata_to_platdata(struct udevice *dev)
+static int pci_octeontx_of_to_plat(struct udevice *dev)
{
return 0;
}
.id = UCLASS_PCI,
.of_match = pci_octeontx_ids,
.ops = &pci_octeontx_ops,
- .ofdata_to_platdata = pci_octeontx_ofdata_to_platdata,
+ .of_to_plat = pci_octeontx_of_to_plat,
.probe = pci_octeontx_probe,
- .priv_auto_alloc_size = sizeof(struct octeontx_pci),
+ .priv_auto = sizeof(struct octeontx_pci),
.flags = DM_FLAG_PRE_RELOC,
};
static int pci_rom_probe(struct udevice *dev, struct pci_rom_header **hdrp)
{
- struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
+ struct pci_child_plat *pplat = dev_get_parent_plat(dev);
struct pci_rom_header *rom_header;
struct pci_rom_data *rom_data;
u16 rom_vendor, rom_device;
int dm_pci_run_vga_bios(struct udevice *dev, int (*int15_handler)(void),
int exec_method)
{
- struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
+ struct pci_child_plat *pplat = dev_get_parent_plat(dev);
struct pci_rom_header *rom = NULL, *ram = NULL;
int vesa_mode = -1;
bool emulate, alloced;
#ifdef CONFIG_DM_VIDEO
int vbe_setup_video_priv(struct vesa_mode_info *vesa,
struct video_priv *uc_priv,
- struct video_uc_platdata *plat)
+ struct video_uc_plat *plat)
{
if (!vesa->x_resolution)
return log_msg_ret("No x resolution", -ENXIO);
int vbe_setup_video(struct udevice *dev, int (*int15_handler)(void))
{
- struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
int ret;
.of_match = sandbox_pci_ids,
.ops = &sandbox_pci_ops,
.probe = sandbox_pci_probe,
- .priv_auto_alloc_size = sizeof(struct sandbox_pci_priv),
+ .priv_auto = sizeof(struct sandbox_pci_priv),
/* Attach an emulator if we can */
.child_post_bind = dm_scan_fdt_dev,
- .per_child_platdata_auto_alloc_size =
- sizeof(struct pci_child_platdata),
+ .per_child_plat_auto = sizeof(struct pci_child_plat),
};
},
};
-static int pci_tegra_ofdata_to_platdata(struct udevice *dev)
+static int pci_tegra_of_to_plat(struct udevice *dev)
{
struct tegra_pcie *pcie = dev_get_priv(dev);
enum tegra_pci_id id;
.id = UCLASS_PCI,
.of_match = pci_tegra_ids,
.ops = &pci_tegra_ops,
- .ofdata_to_platdata = pci_tegra_ofdata_to_platdata,
+ .of_to_plat = pci_tegra_of_to_plat,
.probe = pci_tegra_probe,
- .priv_auto_alloc_size = sizeof(struct tegra_pcie),
+ .priv_auto = sizeof(struct tegra_pcie),
};
return 0;
}
-static int brcm_pcie_ofdata_to_platdata(struct udevice *dev)
+static int brcm_pcie_of_to_plat(struct udevice *dev)
{
struct brcm_pcie *pcie = dev_get_priv(dev);
ofnode dn = dev_ofnode(dev);
.ops = &brcm_pcie_ops,
.of_match = brcm_pcie_ids,
.probe = brcm_pcie_probe,
- .ofdata_to_platdata = brcm_pcie_ofdata_to_platdata,
- .priv_auto_alloc_size = sizeof(struct brcm_pcie),
+ .of_to_plat = brcm_pcie_of_to_plat,
+ .priv_auto = sizeof(struct brcm_pcie),
};
}
/**
- * pcie_dw_mvebu_ofdata_to_platdata() - Translate from DT to device state
+ * pcie_dw_mvebu_of_to_plat() - Translate from DT to device state
*
* @dev: A pointer to the device being operated on
*
*
* Return: 0 on success, else -EINVAL
*/
-static int pcie_dw_mvebu_ofdata_to_platdata(struct udevice *dev)
+static int pcie_dw_mvebu_of_to_plat(struct udevice *dev)
{
struct pcie_dw_mvebu *pcie = dev_get_priv(dev);
.id = UCLASS_PCI,
.of_match = pcie_dw_mvebu_ids,
.ops = &pcie_dw_mvebu_ops,
- .ofdata_to_platdata = pcie_dw_mvebu_ofdata_to_platdata,
+ .of_to_plat = pcie_dw_mvebu_of_to_plat,
.probe = pcie_dw_mvebu_probe,
- .priv_auto_alloc_size = sizeof(struct pcie_dw_mvebu),
+ .priv_auto = sizeof(struct pcie_dw_mvebu),
};
}
/**
- * pcie_dw_ti_ofdata_to_platdata() - Translate from DT to device state
+ * pcie_dw_ti_of_to_plat() - Translate from DT to device state
*
* @dev: A pointer to the device being operated on
*
*
* Return: 0 on success, else -EINVAL
*/
-static int pcie_dw_ti_ofdata_to_platdata(struct udevice *dev)
+static int pcie_dw_ti_of_to_plat(struct udevice *dev)
{
struct pcie_dw_ti *pcie = dev_get_priv(dev);
.id = UCLASS_PCI,
.of_match = pcie_dw_ti_ids,
.ops = &pcie_dw_ti_ops,
- .ofdata_to_platdata = pcie_dw_ti_ofdata_to_platdata,
+ .of_to_plat = pcie_dw_ti_of_to_plat,
.probe = pcie_dw_ti_probe,
- .priv_auto_alloc_size = sizeof(struct pcie_dw_ti),
+ .priv_auto = sizeof(struct pcie_dw_ti),
};
}
/**
- * pci_generic_ecam_ofdata_to_platdata() - Translate from DT to device state
+ * pci_generic_ecam_of_to_plat() - Translate from DT to device state
* @dev: A pointer to the device being operated on
*
* Translate relevant data from the device tree pertaining to device @dev into
*
* Return: 0 on success, else -EINVAL
*/
-static int pci_generic_ecam_ofdata_to_platdata(struct udevice *dev)
+static int pci_generic_ecam_of_to_plat(struct udevice *dev)
{
struct generic_ecam_pcie *pcie = dev_get_priv(dev);
struct fdt_resource reg_res;
.of_match = pci_generic_ecam_ids,
.ops = &pci_generic_ecam_ops,
.probe = pci_generic_ecam_probe,
- .ofdata_to_platdata = pci_generic_ecam_ofdata_to_platdata,
- .priv_auto_alloc_size = sizeof(struct generic_ecam_pcie),
+ .of_to_plat = pci_generic_ecam_of_to_plat,
+ .priv_auto = sizeof(struct generic_ecam_pcie),
};
return 0;
}
-static int fsl_pcie_ofdata_to_platdata(struct udevice *dev)
+static int fsl_pcie_of_to_plat(struct udevice *dev)
{
struct fsl_pcie *pcie = dev_get_priv(dev);
struct fsl_pcie_data *info;
.id = UCLASS_PCI,
.of_match = fsl_pcie_ids,
.ops = &fsl_pcie_ops,
- .ofdata_to_platdata = fsl_pcie_ofdata_to_platdata,
+ .of_to_plat = fsl_pcie_of_to_plat,
.probe = fsl_pcie_probe,
- .priv_auto_alloc_size = sizeof(struct fsl_pcie),
+ .priv_auto = sizeof(struct fsl_pcie),
};
return 0;
}
-static int imx_pcie_ofdata_to_platdata(struct udevice *dev)
+static int imx_pcie_of_to_plat(struct udevice *dev)
{
struct imx_pcie_priv *priv = dev_get_priv(dev);
.ops = &imx_pcie_ops,
.probe = imx_pcie_dm_probe,
.remove = imx_pcie_dm_remove,
- .ofdata_to_platdata = imx_pcie_ofdata_to_platdata,
- .priv_auto_alloc_size = sizeof(struct imx_pcie_priv),
+ .of_to_plat = imx_pcie_of_to_plat,
+ .priv_auto = sizeof(struct imx_pcie_priv),
.flags = DM_FLAG_OS_PREPARE,
};
#endif
return 0;
}
-static int pcie_intel_fpga_ofdata_to_platdata(struct udevice *dev)
+static int pcie_intel_fpga_of_to_plat(struct udevice *dev)
{
struct intel_fpga_pcie *pcie = dev_get_priv(dev);
struct fdt_resource reg_res;
.id = UCLASS_PCI,
.of_match = pcie_intel_fpga_ids,
.ops = &pcie_intel_fpga_ops,
- .ofdata_to_platdata = pcie_intel_fpga_ofdata_to_platdata,
+ .of_to_plat = pcie_intel_fpga_of_to_plat,
.probe = pcie_intel_fpga_probe,
- .priv_auto_alloc_size = sizeof(struct intel_fpga_pcie),
+ .priv_auto = sizeof(struct intel_fpga_pcie),
};
.ops = &iproc_pcie_ops,
.probe = iproc_pcie_probe,
.remove = iproc_pcie_remove,
- .priv_auto_alloc_size = sizeof(struct iproc_pcie),
+ .priv_auto = sizeof(struct iproc_pcie),
.flags = DM_REMOVE_OS_PREPARE,
};
.ops = &ls_pcie_ep_ops,
.probe = ls_pcie_ep_probe,
.remove = ls_pcie_ep_remove,
- .priv_auto_alloc_size = sizeof(struct ls_pcie_ep),
+ .priv_auto = sizeof(struct ls_pcie_ep),
};
.of_match = ls_pcie_g4_ids,
.ops = &ls_pcie_g4_ops,
.probe = ls_pcie_g4_probe,
- .priv_auto_alloc_size = sizeof(struct ls_pcie_g4),
+ .priv_auto = sizeof(struct ls_pcie_g4),
};
.of_match = ls_pcie_ids,
.ops = &ls_pcie_ops,
.probe = ls_pcie_probe,
- .priv_auto_alloc_size = sizeof(struct ls_pcie_rc),
+ .priv_auto = sizeof(struct ls_pcie_rc),
};
struct mtk_pcie *pcie = dev_get_priv(bus);
struct mtk_pcie_port *port;
struct udevice *dev;
- struct pci_child_platdata *pplat = NULL;
+ struct pci_child_plat *pplat = NULL;
int ret = 0;
if (PCI_BUS(bdf) != 0) {
while (dev->parent->seq != 0)
dev = dev->parent;
- pplat = dev_get_parent_platdata(dev);
+ pplat = dev_get_parent_plat(dev);
}
list_for_each_entry(port, &pcie->ports, list) {
.of_match = mtk_pcie_ids,
.ops = &mtk_pcie_ops,
.probe = mtk_pcie_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_pcie),
+ .priv_auto = sizeof(struct mtk_pcie),
};
static const struct udevice_id mtk_pcie_ids_v2[] = {
.of_match = mtk_pcie_ids_v2,
.ops = &mtk_pcie_ops_v2,
.probe = mtk_pcie_probe_v2,
- .priv_auto_alloc_size = sizeof(struct mtk_pcie),
+ .priv_auto = sizeof(struct mtk_pcie),
};
}
/**
- * pci_phytium_ofdata_to_platdata() - Translate from DT to device state
+ * pci_phytium_of_to_plat() - Translate from DT to device state
* @dev: A pointer to the device being operated on
*
* Translate relevant data from the device tree pertaining to device @dev into
*
* Return: 0 on success, else -EINVAL
*/
-static int pci_phytium_ofdata_to_platdata(struct udevice *dev)
+static int pci_phytium_of_to_plat(struct udevice *dev)
{
struct phytium_pcie *pcie = dev_get_priv(dev);
struct fdt_resource reg_res;
.id = UCLASS_PCI,
.of_match = pci_phytium_ids,
.ops = &pci_phytium_ops,
- .ofdata_to_platdata = pci_phytium_ofdata_to_platdata,
- .priv_auto_alloc_size = sizeof(struct phytium_pcie),
+ .of_to_plat = pci_phytium_of_to_plat,
+ .priv_auto = sizeof(struct phytium_pcie),
};
.of_match = rockchip_pcie_ids,
.ops = &rockchip_pcie_ops,
.probe = rockchip_pcie_probe,
- .priv_auto_alloc_size = sizeof(struct rockchip_pcie),
+ .priv_auto = sizeof(struct rockchip_pcie),
};
}
/**
- * pcie_xilinx_ofdata_to_platdata() - Translate from DT to device state
+ * pcie_xilinx_of_to_plat() - Translate from DT to device state
* @dev: A pointer to the device being operated on
*
* Translate relevant data from the device tree pertaining to device @dev into
*
* Return: 0 on success, else -EINVAL
*/
-static int pcie_xilinx_ofdata_to_platdata(struct udevice *dev)
+static int pcie_xilinx_of_to_plat(struct udevice *dev)
{
struct xilinx_pcie *pcie = dev_get_priv(dev);
struct fdt_resource reg_res;
.id = UCLASS_PCI,
.of_match = pcie_xilinx_ids,
.ops = &pcie_xilinx_ops,
- .ofdata_to_platdata = pcie_xilinx_ofdata_to_platdata,
- .priv_auto_alloc_size = sizeof(struct xilinx_pcie),
+ .of_to_plat = pcie_xilinx_of_to_plat,
+ .priv_auto = sizeof(struct xilinx_pcie),
};
.ops = &cdns_pci_ep_ops,
.probe = cdns_pci_ep_probe,
.remove = cdns_pci_ep_remove,
- .priv_auto_alloc_size = sizeof(struct cdns_pcie),
+ .priv_auto = sizeof(struct cdns_pcie),
};
.of_match = sandbox_pci_ep_ids,
.probe = sandbox_pci_ep_probe,
.ops = &sandbox_pci_ep_ops,
- .priv_auto_alloc_size = sizeof(struct sandbox_pci_ep_priv),
+ .priv_auto = sizeof(struct sandbox_pci_ep_priv),
};
static int sun4i_usb_phy_probe(struct udevice *dev)
{
- struct sun4i_usb_phy_plat *plat = dev_get_platdata(dev);
+ struct sun4i_usb_phy_plat *plat = dev_get_plat(dev);
struct sun4i_usb_phy_data *data = dev_get_priv(dev);
int i, ret;
.of_match = sun4i_usb_phy_ids,
.ops = &sun4i_usb_phy_ops,
.probe = sun4i_usb_phy_probe,
- .platdata_auto_alloc_size = sizeof(struct sun4i_usb_phy_plat[MAX_PHYS]),
- .priv_auto_alloc_size = sizeof(struct sun4i_usb_phy_data),
+ .plat_auto = sizeof(struct sun4i_usb_phy_plat[MAX_PHYS]),
+ .priv_auto = sizeof(struct sun4i_usb_phy_data),
};
.id = UCLASS_PHY,
.of_match = bcm6318_usbh_ids,
.ops = &bcm6318_usbh_ops,
- .priv_auto_alloc_size = sizeof(struct bcm6318_usbh_priv),
+ .priv_auto = sizeof(struct bcm6318_usbh_priv),
.probe = bcm6318_usbh_probe,
};
.id = UCLASS_PHY,
.of_match = bcm6348_usbh_ids,
.ops = &bcm6348_usbh_ops,
- .priv_auto_alloc_size = sizeof(struct bcm6348_usbh_priv),
+ .priv_auto = sizeof(struct bcm6348_usbh_priv),
.probe = bcm6348_usbh_probe,
};
.id = UCLASS_PHY,
.of_match = bcm6358_usbh_ids,
.ops = &bcm6358_usbh_ops,
- .priv_auto_alloc_size = sizeof(struct bcm6358_usbh_priv),
+ .priv_auto = sizeof(struct bcm6358_usbh_priv),
.probe = bcm6358_usbh_probe,
};
.id = UCLASS_PHY,
.of_match = bcm6368_usbh_ids,
.ops = &bcm6368_usbh_ops,
- .priv_auto_alloc_size = sizeof(struct bcm6368_usbh_priv),
+ .priv_auto = sizeof(struct bcm6368_usbh_priv),
.probe = bcm6368_usbh_probe,
};
.of_match = keystone_usb_phy_ids,
.ops = &keystone_usb_phy_ops,
.probe = keystone_usb_phy_probe,
- .priv_auto_alloc_size = sizeof(struct keystone_usb_phy),
+ .priv_auto = sizeof(struct keystone_usb_phy),
};
.id = UCLASS_MISC,
.of_match = comphy_ids,
.probe = comphy_probe,
- .priv_auto_alloc_size = sizeof(struct chip_serdes_phy_config),
+ .priv_auto = sizeof(struct chip_serdes_phy_config),
};
.of_match = meson_g12a_usb2_phy_ids,
.probe = meson_g12a_usb2_phy_probe,
.ops = &meson_g12a_usb2_phy_ops,
- .priv_auto_alloc_size = sizeof(struct phy_meson_g12a_usb2_priv),
+ .priv_auto = sizeof(struct phy_meson_g12a_usb2_priv),
};
.of_match = meson_g12a_usb3_pcie_phy_ids,
.probe = meson_g12a_usb3_pcie_phy_probe,
.ops = &meson_g12a_usb3_pcie_phy_ops,
- .priv_auto_alloc_size = sizeof(struct phy_g12a_usb3_pcie_priv),
+ .priv_auto = sizeof(struct phy_g12a_usb3_pcie_priv),
};
.probe = meson_gxbb_usb2_phy_probe,
.remove = meson_gxbb_usb2_phy_remove,
.ops = &meson_gxbb_usb2_phy_ops,
- .priv_auto_alloc_size = sizeof(struct phy_meson_gxbb_usb2_priv),
+ .priv_auto = sizeof(struct phy_meson_gxbb_usb2_priv),
};
.of_match = meson_gxl_usb2_phy_ids,
.probe = meson_gxl_usb2_phy_probe,
.ops = &meson_gxl_usb2_phy_ops,
- .priv_auto_alloc_size = sizeof(struct phy_meson_gxl_usb2_priv),
+ .priv_auto = sizeof(struct phy_meson_gxl_usb2_priv),
};
.of_match = msm_phy_ids,
.ops = &msm_phy_ops,
.probe = msm_phy_probe,
- .priv_auto_alloc_size = sizeof(struct msm_phy_priv),
+ .priv_auto = sizeof(struct msm_phy_priv),
};
.of_match = mt76x8_usb_phy_ids,
.ops = &mt76x8_usb_phy_ops,
.probe = mt76x8_usb_phy_probe,
- .priv_auto_alloc_size = sizeof(struct mt76x8_usb_phy),
+ .priv_auto = sizeof(struct mt76x8_usb_phy),
};
.of_match = nop_phy_ids,
.ops = &nop_phy_ops,
.probe = nop_phy_probe,
- .priv_auto_alloc_size = sizeof(struct nop_phy_priv),
+ .priv_auto = sizeof(struct nop_phy_priv),
};
.of_match = omap_usb2_id_table,
.probe = omap_usb2_phy_probe,
.ops = &omap_usb2_phy_ops,
- .priv_auto_alloc_size = sizeof(struct omap_usb2_phy),
+ .priv_auto = sizeof(struct omap_usb2_phy),
};
.probe = sr_pcie_phy_probe,
.of_match = sr_pcie_phy_match_table,
.ops = &sr_pcie_phy_ops,
- .platdata_auto_alloc_size = sizeof(struct sr_pcie_phy_core),
- .priv_auto_alloc_size = sizeof(struct sr_pcie_phy_core),
+ .plat_auto = sizeof(struct sr_pcie_phy_core),
+ .priv_auto = sizeof(struct sr_pcie_phy_core),
};
.of_match = mtk_tphy_id_table,
.ops = &mtk_tphy_ops,
.probe = mtk_tphy_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_tphy),
+ .priv_auto = sizeof(struct mtk_tphy),
};
.of_match = ipq4019_usb_ss_phy_ids,
.ops = &ipq4019_usb_ss_phy_ops,
.probe = ipq4019_usb_ss_phy_probe,
- .priv_auto_alloc_size = sizeof(struct ipq4019_usb_phy),
+ .priv_auto = sizeof(struct ipq4019_usb_phy),
};
static int ipq4019_hs_phy_power_off(struct phy *_phy)
.of_match = ipq4019_usb_hs_phy_ids,
.ops = &ipq4019_usb_hs_phy_ops,
.probe = ipq4019_usb_hs_phy_probe,
- .priv_auto_alloc_size = sizeof(struct ipq4019_usb_phy),
+ .priv_auto = sizeof(struct ipq4019_usb_phy),
};
.ops = &rcar_gen2_phy_phy_ops,
.probe = rcar_gen2_phy_probe,
.remove = rcar_gen2_phy_remove,
- .priv_auto_alloc_size = sizeof(struct rcar_gen2_phy),
+ .priv_auto = sizeof(struct rcar_gen2_phy),
};
.ops = &rcar_gen3_phy_phy_ops,
.probe = rcar_gen3_phy_probe,
.remove = rcar_gen3_phy_remove,
- .priv_auto_alloc_size = sizeof(struct rcar_gen3_phy),
+ .priv_auto = sizeof(struct rcar_gen3_phy),
};
.of_match = stm32_usbphyc_of_match,
.ops = &stm32_usbphyc_phy_ops,
.probe = stm32_usbphyc_probe,
- .priv_auto_alloc_size = sizeof(struct stm32_usbphyc),
+ .priv_auto = sizeof(struct stm32_usbphyc),
};
.name = "ti-serdes-am654-mux-clk",
.id = UCLASS_CLK,
.probe = serdes_am654_mux_clk_probe,
- .priv_auto_alloc_size = sizeof(struct serdes_am654_mux_clk_data),
+ .priv_auto = sizeof(struct serdes_am654_mux_clk_data),
.ops = &serdes_am654_mux_clk_ops,
};
.bind = serdes_am654_bind,
.ops = &serdes_am654_phy_ops,
.probe = serdes_am654_probe,
- .priv_auto_alloc_size = sizeof(struct serdes_am654),
+ .priv_auto = sizeof(struct serdes_am654),
};
.of_match = rockchip_usb2phy_ids,
.probe = rockchip_usb2phy_probe,
.bind = rockchip_usb2phy_bind,
- .priv_auto_alloc_size = sizeof(struct rockchip_usb2phy),
+ .priv_auto = sizeof(struct rockchip_usb2phy),
};
.of_match = rockchip_pcie_phy_ids,
.ops = &rockchip_pcie_phy_ops,
.probe = rockchip_pcie_phy_probe,
- .priv_auto_alloc_size = sizeof(struct rockchip_pcie_phy),
+ .priv_auto = sizeof(struct rockchip_pcie_phy),
};
.of_match = rockchip_typec_phy_ids,
.probe = rockchip_tcphy_probe,
.bind = rockchip_tcphy_bind,
- .priv_auto_alloc_size = sizeof(struct rockchip_tcphy),
+ .priv_auto = sizeof(struct rockchip_tcphy),
};
.of_match = sandbox_phy_ids,
.ops = &sandbox_phy_ops,
.probe = sandbox_phy_probe,
- .priv_auto_alloc_size = sizeof(struct sandbox_phy_priv),
+ .priv_auto = sizeof(struct sandbox_phy_priv),
};
.of_match = sti_usb_phy_ids,
.probe = sti_usb_phy_probe,
.ops = &sti_usb_phy_ops,
- .priv_auto_alloc_size = sizeof(struct sti_usb_phy),
+ .priv_auto = sizeof(struct sti_usb_phy),
};
.of_match = pipe3_phy_ids,
.ops = &pipe3_phy_ops,
.probe = pipe3_phy_probe,
- .priv_auto_alloc_size = sizeof(struct omap_pipe3),
+ .priv_auto = sizeof(struct omap_pipe3),
};
.name = "aspeed_ast2500_pinctrl",
.id = UCLASS_PINCTRL,
.of_match = ast2500_pinctrl_ids,
- .priv_auto_alloc_size = sizeof(struct ast2500_pinctrl_priv),
+ .priv_auto = sizeof(struct ast2500_pinctrl_priv),
.ops = &ast2500_pinctrl_ops,
.probe = ast2500_pinctrl_probe,
};
.name = "pinctrl_ar933x",
.id = UCLASS_PINCTRL,
.of_match = ar933x_pinctrl_ids,
- .priv_auto_alloc_size = sizeof(struct ar933x_pinctrl_priv),
+ .priv_auto = sizeof(struct ar933x_pinctrl_priv),
.ops = &ar933x_pinctrl_ops,
.probe = ar933x_pinctrl_probe,
};
.name = "pinctrl_qca953x",
.id = UCLASS_PINCTRL,
.of_match = qca953x_pinctrl_ids,
- .priv_auto_alloc_size = sizeof(struct qca953x_pinctrl_priv),
+ .priv_auto = sizeof(struct qca953x_pinctrl_priv),
.ops = &qca953x_pinctrl_ops,
.probe = qca953x_pinctrl_probe,
};
{}
};
-int bcm283x_pinctl_ofdata_to_platdata(struct udevice *dev)
+int bcm283x_pinctl_of_to_plat(struct udevice *dev)
{
struct bcm283x_pinctrl_priv *priv;
/* Create GPIO device as well */
ret = device_bind(dev, lists_driver_lookup_name("gpio_bcm2835"),
- "gpio_bcm2835", NULL, dev_of_offset(dev), &pdev);
+ "gpio_bcm2835", NULL, dev_ofnode(dev), &pdev);
if (ret) {
/*
* While we really want the pinctrl driver to work to make
.name = "bcm283x_pinctrl",
.id = UCLASS_PINCTRL,
.of_match = of_match_ptr(bcm2835_pinctrl_id),
- .ofdata_to_platdata = bcm283x_pinctl_ofdata_to_platdata,
- .priv_auto_alloc_size = sizeof(struct bcm283x_pinctrl_priv),
+ .of_to_plat = bcm283x_pinctl_of_to_plat,
+ .priv_auto = sizeof(struct bcm283x_pinctrl_priv),
.ops = &bcm283x_pinctrl_ops,
.probe = bcm283x_pinctl_probe,
#if CONFIG_IS_ENABLED(OF_BOARD)
.id = UCLASS_PINCTRL,
.of_match = bcm6838_pinctrl_match,
.ops = &bcm6838_pinctrl_ops,
- .priv_auto_alloc_size = sizeof(struct bcm6838_pinctrl_priv),
+ .priv_auto = sizeof(struct bcm6838_pinctrl_priv),
.probe = bcm6838_pinctrl_probe,
};
.name = "pinctrl_exynos7420",
.id = UCLASS_PINCTRL,
.of_match = exynos7420_pinctrl_ids,
- .priv_auto_alloc_size = sizeof(struct exynos_pinctrl_priv),
+ .priv_auto = sizeof(struct exynos_pinctrl_priv),
.ops = &exynos7420_pinctrl_ops,
.probe = exynos_pinctrl_probe,
};
/*
* We have to probe each one of these since the community link is only
- * attached in intel_pinctrl_ofdata_to_platdata().
+ * attached in intel_pinctrl_of_to_plat().
*/
uclass_foreach_dev_probe(UCLASS_PINCTRL, dev) {
struct intel_pinctrl_priv *priv = dev_get_priv(dev);
return 0;
}
-int intel_pinctrl_ofdata_to_platdata(struct udevice *dev,
- const struct pad_community *comm,
- int num_cfgs)
+int intel_pinctrl_of_to_plat(struct udevice *dev,
+ const struct pad_community *comm, int num_cfgs)
{
- struct p2sb_child_platdata *pplat = dev_get_parent_platdata(dev);
+ struct p2sb_child_plat *pplat = dev_get_parent_plat(dev);
struct intel_pinctrl_priv *priv = dev_get_priv(dev);
if (!comm) {
#include <asm/intel_pinctrl_defs.h>
/**
- * struct apl_gpio_platdata - platform data for each device
+ * struct apl_gpio_plat - platform data for each device
*
* @dtplat: of-platdata data from C struct
*/
-struct apl_gpio_platdata {
+struct apl_gpio_plat {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
/* Put this first since driver model will copy the data here */
struct dtd_intel_apl_pinctrl dtplat;
},
};
-static int apl_pinctrl_ofdata_to_platdata(struct udevice *dev)
+static int apl_pinctrl_of_to_plat(struct udevice *dev)
{
- struct p2sb_child_platdata *pplat;
+ struct p2sb_child_plat *pplat;
const struct pad_community *comm = NULL;
int i;
#if CONFIG_IS_ENABLED(OF_PLATDATA)
- struct apl_gpio_platdata *plat = dev_get_platdata(dev);
+ struct apl_gpio_plat *plat = dev_get_plat(dev);
int ret;
/*
return log_msg_ret("Could not set port id", ret);
#endif
/* Attach this device to its community structure */
- pplat = dev_get_parent_platdata(dev);
+ pplat = dev_get_parent_plat(dev);
for (i = 0; i < ARRAY_SIZE(apl_gpio_communities); i++) {
if (apl_gpio_communities[i].port == pplat->pid)
comm = &apl_gpio_communities[i];
}
- return intel_pinctrl_ofdata_to_platdata(dev, comm, 2);
+ return intel_pinctrl_of_to_plat(dev, comm, 2);
}
static const struct udevice_id apl_gpio_ids[] = {
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
.bind = dm_scan_fdt_dev,
#endif
- .ofdata_to_platdata = apl_pinctrl_ofdata_to_platdata,
- .priv_auto_alloc_size = sizeof(struct intel_pinctrl_priv),
- .platdata_auto_alloc_size = sizeof(struct apl_gpio_platdata),
+ .of_to_plat = apl_pinctrl_of_to_plat,
+ .priv_auto = sizeof(struct intel_pinctrl_priv),
+ .plat_auto = sizeof(struct apl_gpio_plat),
};
.of_match = mt7622_pctrl_match,
.ops = &mtk_pinctrl_ops,
.probe = mtk_pinctrl_mt7622_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_pinctrl_priv),
+ .priv_auto = sizeof(struct mtk_pinctrl_priv),
};
.of_match = mt7623_pctrl_match,
.ops = &mtk_pinctrl_ops,
.probe = mtk_pinctrl_mt7623_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_pinctrl_priv),
+ .priv_auto = sizeof(struct mtk_pinctrl_priv),
};
.of_match = mt7629_pctrl_match,
.ops = &mtk_pinctrl_ops,
.probe = mtk_pinctrl_mt7629_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_pinctrl_priv),
+ .priv_auto = sizeof(struct mtk_pinctrl_priv),
};
.of_match = mt8512_pctrl_match,
.ops = &mtk_pinctrl_ops,
.probe = mtk_pinctrl_mt8512_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_pinctrl_priv),
+ .priv_auto = sizeof(struct mtk_pinctrl_priv),
};
.of_match = mt8516_pctrl_match,
.ops = &mtk_pinctrl_ops,
.probe = mtk_pinctrl_mt8516_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_pinctrl_priv),
+ .priv_auto = sizeof(struct mtk_pinctrl_priv),
};
.of_match = mt8518_pctrl_match,
.ops = &mtk_pinctrl_ops,
.probe = mtk_pinctrl_mt8518_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_pinctrl_priv),
+ .priv_auto = sizeof(struct mtk_pinctrl_priv),
};
.id = UCLASS_PINCTRL,
.of_match = of_match_ptr(meson_axg_pinctrl_match),
.probe = meson_pinctrl_probe,
- .priv_auto_alloc_size = sizeof(struct meson_pinctrl),
+ .priv_auto = sizeof(struct meson_pinctrl),
.ops = &meson_axg_pinctrl_ops,
};
.id = UCLASS_PINCTRL,
.of_match = of_match_ptr(meson_g12a_pinctrl_match),
.probe = meson_pinctrl_probe,
- .priv_auto_alloc_size = sizeof(struct meson_pinctrl),
+ .priv_auto = sizeof(struct meson_pinctrl),
.ops = &meson_axg_pinctrl_ops,
};
.id = UCLASS_PINCTRL,
.of_match = of_match_ptr(meson_gxbb_pinctrl_match),
.probe = meson_pinctrl_probe,
- .priv_auto_alloc_size = sizeof(struct meson_pinctrl),
+ .priv_auto = sizeof(struct meson_pinctrl),
.ops = &meson_gx_pinctrl_ops,
};
.id = UCLASS_PINCTRL,
.of_match = of_match_ptr(meson_gxl_pinctrl_match),
.probe = meson_pinctrl_probe,
- .priv_auto_alloc_size = sizeof(struct meson_pinctrl),
+ .priv_auto = sizeof(struct meson_pinctrl),
.ops = &meson_gx_pinctrl_ops,
};
int na, ns;
char *name;
+ /* FIXME: Should use livetree */
na = fdt_address_cells(gd->fdt_blob, dev_of_offset(dev->parent));
if (na < 1) {
debug("bad #address-cells\n");
sprintf(name, "meson-gpio");
/* Create child device UCLASS_GPIO and bind it */
- device_bind(dev, priv->data->gpio_driver, name, NULL, gpio, &gpio_dev);
- dev_set_of_offset(gpio_dev, gpio);
+ device_bind(dev, priv->data->gpio_driver, name, NULL,
+ offset_to_ofnode(gpio), &gpio_dev);
return 0;
}
return ret;
ret = device_bind(dev, &jr2_gpio_driver, "jr2-gpio", NULL,
- dev_of_offset(dev), NULL);
+ dev_ofnode(dev), NULL);
if (ret)
return ret;
.id = UCLASS_PINCTRL,
.of_match = of_match_ptr(jr2_pinctrl_of_match),
.probe = jr2_pinctrl_probe,
- .priv_auto_alloc_size = sizeof(struct mscc_pinctrl),
+ .priv_auto = sizeof(struct mscc_pinctrl),
.ops = &mscc_pinctrl_ops,
};
return ret;
ret = device_bind(dev, &luton_gpio_driver, "luton-gpio", NULL,
- dev_of_offset(dev), NULL);
+ dev_ofnode(dev), NULL);
return 0;
}
.id = UCLASS_PINCTRL,
.of_match = of_match_ptr(luton_pinctrl_of_match),
.probe = luton_pinctrl_probe,
- .priv_auto_alloc_size = sizeof(struct mscc_pinctrl),
+ .priv_auto = sizeof(struct mscc_pinctrl),
.ops = &mscc_pinctrl_ops,
};
return ret;
ret = device_bind(dev, &ocelot_gpio_driver, "ocelot-gpio", NULL,
- dev_of_offset(dev), NULL);
+ dev_ofnode(dev), NULL);
return ret;
}
.id = UCLASS_PINCTRL,
.of_match = of_match_ptr(ocelot_pinctrl_of_match),
.probe = ocelot_pinctrl_probe,
- .priv_auto_alloc_size = sizeof(struct mscc_pinctrl),
+ .priv_auto = sizeof(struct mscc_pinctrl),
.ops = &mscc_pinctrl_ops,
};
return ret;
ret = device_bind(dev, &serval_gpio_driver, "serval-gpio", NULL,
- dev_of_offset(dev), NULL);
+ dev_ofnode(dev), NULL);
if (ret)
return ret;
.id = UCLASS_PINCTRL,
.of_match = of_match_ptr(serval_pinctrl_of_match),
.probe = serval_pinctrl_probe,
- .priv_auto_alloc_size = sizeof(struct mscc_pinctrl),
+ .priv_auto = sizeof(struct mscc_pinctrl),
.ops = &mscc_pinctrl_ops,
};
return ret;
ret = device_bind(dev, &servalt_gpio_driver, "servalt-gpio", NULL,
- dev_of_offset(dev), NULL);
+ dev_ofnode(dev), NULL);
if (ret)
return ret;
.id = UCLASS_PINCTRL,
.of_match = of_match_ptr(servalt_pinctrl_of_match),
.probe = servalt_pinctrl_probe,
- .priv_auto_alloc_size = sizeof(struct mscc_pinctrl),
+ .priv_auto = sizeof(struct mscc_pinctrl),
.ops = &mscc_pinctrl_ops,
};
return ret;
}
-static int mt7628_pinctrl_ofdata_to_platdata(struct udevice *dev)
+static int mt7628_pinctrl_of_to_plat(struct udevice *dev)
{
struct mt7628_pinctrl_priv *priv = dev_get_priv(dev);
.name = "mt7628-pinctrl",
.id = UCLASS_PINCTRL,
.of_match = mt7628_pinctrl_ids,
- .ofdata_to_platdata = mt7628_pinctrl_ofdata_to_platdata,
+ .of_to_plat = mt7628_pinctrl_of_to_plat,
.ops = &mt7628_pinctrl_ops,
.probe = mt7628_pinctrl_probe,
- .priv_auto_alloc_size = sizeof(struct mt7628_pinctrl_priv),
+ .priv_auto = sizeof(struct mt7628_pinctrl_priv),
};
int subnode;
char *name;
- /* Lookup GPIO driver */
+ /* FIXME: Should not need to lookup GPIO uclass */
drv = lists_uclass_lookup(UCLASS_GPIO);
if (!drv) {
puts("Cannot find GPIO driver\n");
return -ENOENT;
}
+ /* FIXME: Use livtree and check the result of device_bind() below */
fdt_for_each_subnode(subnode, blob, node) {
if (fdtdec_get_bool(blob, subnode, "gpio-controller")) {
ret = 0;
sprintf(name, "armada-37xx-gpio");
/* Create child device UCLASS_GPIO and bind it */
- device_bind(parent, &armada_37xx_gpio_driver, name, NULL, subnode,
- &dev);
- dev_set_of_offset(dev, subnode);
+ device_bind(parent, &armada_37xx_gpio_driver, name, NULL,
+ offset_to_ofnode(subnode), &dev);
return 0;
}
.id = UCLASS_PINCTRL,
.of_match = of_match_ptr(armada_37xx_pinctrl_of_match),
.probe = armada_37xx_pinctrl_probe,
- .priv_auto_alloc_size = sizeof(struct armada_37xx_pinctrl),
+ .priv_auto = sizeof(struct armada_37xx_pinctrl),
.ops = &armada_37xx_pinctrl_ops,
};
.name = "mvebu_pinctrl",
.id = UCLASS_PINCTRL,
.of_match = mvebu_pinctrl_ids,
- .priv_auto_alloc_size = sizeof(struct mvebu_pinctrl_priv),
+ .priv_auto = sizeof(struct mvebu_pinctrl_priv),
.ops = &mvebu_pinctrl_ops,
.probe = mvebu_pinctl_probe
};
.name = "pinctrl_s5pxx18",
.id = UCLASS_PINCTRL,
.of_match = s5pxx18_pinctrl_ids,
- .priv_auto_alloc_size = sizeof(struct nexell_pinctrl_priv),
+ .priv_auto = sizeof(struct nexell_pinctrl_priv),
.ops = &s5pxx18_pinctrl_ops,
.probe = nexell_pinctrl_probe,
.flags = DM_FLAG_PRE_RELOC
.of_match = of_match_ptr(imx5_pinctrl_match),
.probe = imx5_pinctrl_probe,
.remove = imx_pinctrl_remove,
- .priv_auto_alloc_size = sizeof(struct imx_pinctrl_priv),
+ .priv_auto = sizeof(struct imx_pinctrl_priv),
.ops = &imx_pinctrl_ops,
.flags = DM_FLAG_PRE_RELOC,
};
.of_match = of_match_ptr(imx6_pinctrl_match),
.probe = imx6_pinctrl_probe,
.remove = imx_pinctrl_remove,
- .priv_auto_alloc_size = sizeof(struct imx_pinctrl_priv),
+ .priv_auto = sizeof(struct imx_pinctrl_priv),
.ops = &imx_pinctrl_ops,
.flags = DM_FLAG_PRE_RELOC,
};
.of_match = of_match_ptr(imx7_pinctrl_match),
.probe = imx7_pinctrl_probe,
.remove = imx_pinctrl_remove,
- .priv_auto_alloc_size = sizeof(struct imx_pinctrl_priv),
+ .priv_auto = sizeof(struct imx_pinctrl_priv),
.ops = &imx_pinctrl_ops,
.flags = DM_FLAG_PRE_RELOC,
};
.of_match = of_match_ptr(imx7ulp_pinctrl_match),
.probe = imx7ulp_pinctrl_probe,
.remove = imx_pinctrl_remove,
- .priv_auto_alloc_size = sizeof(struct imx_pinctrl_priv),
+ .priv_auto = sizeof(struct imx_pinctrl_priv),
.ops = &imx_pinctrl_ops,
.flags = DM_FLAG_PRE_RELOC,
};
.of_match = of_match_ptr(imx8_pinctrl_match),
.probe = imx8_pinctrl_probe,
.remove = imx_pinctrl_remove,
- .priv_auto_alloc_size = sizeof(struct imx_pinctrl_priv),
+ .priv_auto = sizeof(struct imx_pinctrl_priv),
.ops = &imx_pinctrl_ops,
.flags = DM_FLAG_PRE_RELOC,
};
.of_match = of_match_ptr(imx8m_pinctrl_match),
.probe = imx8mq_pinctrl_probe,
.remove = imx_pinctrl_remove,
- .priv_auto_alloc_size = sizeof(struct imx_pinctrl_priv),
+ .priv_auto = sizeof(struct imx_pinctrl_priv),
.ops = &imx_pinctrl_ops,
.flags = DM_FLAG_PRE_RELOC,
};
.of_match = of_match_ptr(imxrt_pinctrl_match),
.probe = imxrt_pinctrl_probe,
.remove = imx_pinctrl_remove,
- .priv_auto_alloc_size = sizeof(struct imx_pinctrl_priv),
+ .priv_auto = sizeof(struct imx_pinctrl_priv),
.ops = &imx_pinctrl_ops,
.flags = DM_FLAG_PRE_RELOC,
};
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
.bind = dm_scan_fdt_dev,
#endif
- .priv_auto_alloc_size = sizeof(struct mxs_pinctrl_priv),
+ .priv_auto = sizeof(struct mxs_pinctrl_priv),
.ops = &mxs_pinctrl_ops,
};
.of_match = of_match_ptr(vf610_pinctrl_match),
.probe = vf610_pinctrl_probe,
.remove = imx_pinctrl_remove,
- .priv_auto_alloc_size = sizeof(struct imx_pinctrl_priv),
+ .priv_auto = sizeof(struct imx_pinctrl_priv),
.ops = &imx_pinctrl_ops,
.flags = DM_FLAG_PRE_RELOC,
};
* framework groups, Atmel PIO groups will be called banks.
*/
-struct atmel_pio4_platdata {
+struct atmel_pio4_plat {
struct atmel_pio4_port *reg_base;
};
static inline struct atmel_pio4_port *atmel_pio4_bank_base(struct udevice *dev,
u32 bank)
{
- struct atmel_pio4_platdata *plat = dev_get_platdata(dev);
+ struct atmel_pio4_plat *plat = dev_get_plat(dev);
struct atmel_pio4_port *bank_base =
(struct atmel_pio4_port *)((u32)plat->reg_base +
ATMEL_PIO_BANK_OFFSET * bank);
static int atmel_pinctrl_probe(struct udevice *dev)
{
- struct atmel_pio4_platdata *plat = dev_get_platdata(dev);
+ struct atmel_pio4_plat *plat = dev_get_plat(dev);
fdt_addr_t addr_base;
dev = dev_get_parent(dev);
.id = UCLASS_PINCTRL,
.of_match = atmel_pinctrl_match,
.probe = atmel_pinctrl_probe,
- .platdata_auto_alloc_size = sizeof(struct atmel_pio4_platdata),
+ .plat_auto = sizeof(struct atmel_pio4_plat),
.ops = &atmel_pinctrl_ops,
};
.id = UCLASS_PINCTRL,
.of_match = at91_pinctrl_match,
.probe = at91_pinctrl_probe,
- .priv_auto_alloc_size = sizeof(struct at91_pinctrl_priv),
+ .priv_auto = sizeof(struct at91_pinctrl_priv),
.ops = &at91_pinctrl_ops,
};
.id = UCLASS_PINCTRL,
.of_match = k210_pc_ids,
.probe = k210_pc_probe,
- .priv_auto_alloc_size = sizeof(struct k210_pc_priv),
+ .priv_auto = sizeof(struct k210_pc_priv),
.ops = &k210_pc_pinctrl_ops,
};
#include <linux/ioport.h>
/**
- * struct qe_io_platdata
+ * struct qe_io_plat
*
* @base: Base register address
* @num_par_io_ports number of io ports
*/
-struct qe_io_platdata {
+struct qe_io_plat {
qepio83xx_t *base;
u32 num_io_ports;
};
qe_cfg_iopin(par_io, port, pin, dir, open_drain, assign);
}
#else
-static int qe_io_ofdata_to_platdata(struct udevice *dev)
+static int qe_io_of_to_plat(struct udevice *dev)
{
- struct qe_io_platdata *plat = dev->platdata;
+ struct qe_io_plat *plat = dev->plat;
fdt_addr_t addr;
addr = dev_read_addr(dev);
*/
static int par_io_of_config_node(struct udevice *dev, ofnode pio)
{
- struct qe_io_platdata *plat = dev->platdata;
+ struct qe_io_plat *plat = dev->plat;
qepio83xx_t *par_io = plat->base;
const unsigned int *pio_map;
int pio_map_len;
.id = UCLASS_PINCTRL,
.of_match = of_match_ptr(par_io_pinctrl_match),
.probe = par_io_pinctrl_probe,
- .ofdata_to_platdata = qe_io_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct qe_io_platdata),
+ .of_to_plat = qe_io_of_to_plat,
+ .plat_auto = sizeof(struct qe_io_plat),
.ops = &par_io_pinctrl_ops,
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
.flags = DM_FLAG_PRE_RELOC,
.name = "sandbox_pinctrl",
.id = UCLASS_PINCTRL,
.of_match = sandbox_pinctrl_match,
- .priv_auto_alloc_size = sizeof(struct sandbox_pinctrl_priv),
+ .priv_auto = sizeof(struct sandbox_pinctrl_priv),
.ops = &sandbox_pinctrl_ops,
};
const struct single_fdt_pin_cfg *pins,
int size)
{
- struct single_pdata *pdata = dev->platdata;
+ struct single_pdata *pdata = dev->plat;
int count = size / sizeof(struct single_fdt_pin_cfg);
phys_addr_t n, reg;
u32 val;
const struct single_fdt_bits_cfg *pins,
int size)
{
- struct single_pdata *pdata = dev->platdata;
+ struct single_pdata *pdata = dev->plat;
int count = size / sizeof(struct single_fdt_bits_cfg);
phys_addr_t n, reg;
u32 val, mask;
return len;
}
-static int single_ofdata_to_platdata(struct udevice *dev)
+static int single_of_to_plat(struct udevice *dev)
{
fdt_addr_t addr;
u32 of_reg[2];
int res;
- struct single_pdata *pdata = dev->platdata;
+ struct single_pdata *pdata = dev->plat;
pdata->width =
dev_read_u32_default(dev, "pinctrl-single,register-width", 0);
.id = UCLASS_PINCTRL,
.of_match = single_pinctrl_match,
.ops = &single_pinctrl_ops,
- .platdata_auto_alloc_size = sizeof(struct single_pdata),
- .ofdata_to_platdata = single_ofdata_to_platdata,
+ .plat_auto = sizeof(struct single_pdata),
+ .of_to_plat = single_of_to_plat,
};
/* oe = 1, pu = 1, od = 1 */
#define BIDIR_PU (OE | PU | OD)
-struct sti_pinctrl_platdata {
+struct sti_pinctrl_plat {
struct regmap *regmap;
};
*/
void sti_alternate_select(struct udevice *dev, struct sti_pin_desc *pin_desc)
{
- struct sti_pinctrl_platdata *plat = dev_get_platdata(dev);
+ struct sti_pinctrl_plat *plat = dev_get_plat(dev);
unsigned long sysconf, *sysconfreg;
int alt = pin_desc->alt;
int bank = pin_desc->bank;
/* pin configuration */
void sti_pin_configure(struct udevice *dev, struct sti_pin_desc *pin_desc)
{
- struct sti_pinctrl_platdata *plat = dev_get_platdata(dev);
+ struct sti_pinctrl_plat *plat = dev_get_plat(dev);
int bit;
int oe = 0, pu = 0, od = 0;
unsigned long *sysconfreg;
static int sti_pinctrl_probe(struct udevice *dev)
{
- struct sti_pinctrl_platdata *plat = dev_get_platdata(dev);
+ struct sti_pinctrl_plat *plat = dev_get_plat(dev);
struct udevice *syscon;
int err;
.of_match = sti_pinctrl_ids,
.ops = &sti_pinctrl_ops,
.probe = sti_pinctrl_probe,
- .platdata_auto_alloc_size = sizeof(struct sti_pinctrl_platdata),
+ .plat_auto = sizeof(struct sti_pinctrl_plat),
.ops = &sti_pinctrl_ops,
};
unsigned int param, unsigned int arg)
{
int ret, dir;
- struct stmfx_pinctrl *plat = dev_get_platdata(dev);
+ struct stmfx_pinctrl *plat = dev_get_plat(dev);
dir = stmfx_gpio_get_function(plat->gpio, pin);
static int stmfx_pinctrl_get_pins_count(struct udevice *dev)
{
- struct stmfx_pinctrl *plat = dev_get_platdata(dev);
+ struct stmfx_pinctrl *plat = dev_get_plat(dev);
struct gpio_dev_priv *uc_priv;
uc_priv = dev_get_uclass_priv(plat->gpio);
unsigned int selector,
char *buf, int size)
{
- struct stmfx_pinctrl *plat = dev_get_platdata(dev);
+ struct stmfx_pinctrl *plat = dev_get_plat(dev);
int func;
func = stmfx_gpio_get_function(plat->gpio, selector);
static int stmfx_pinctrl_bind(struct udevice *dev)
{
- struct stmfx_pinctrl *plat = dev_get_platdata(dev);
+ struct stmfx_pinctrl *plat = dev_get_plat(dev);
/* subnode name is not explicit: use father name */
device_set_name(dev, dev->parent->name);
static int stmfx_pinctrl_probe(struct udevice *dev)
{
- struct stmfx_pinctrl *plat = dev_get_platdata(dev);
+ struct stmfx_pinctrl *plat = dev_get_plat(dev);
return device_probe(plat->gpio);
};
.bind = stmfx_pinctrl_bind,
.probe = stmfx_pinctrl_probe,
.ops = &stmfx_pinctrl_ops,
- .platdata_auto_alloc_size = sizeof(struct stmfx_pinctrl),
+ .plat_auto = sizeof(struct stmfx_pinctrl),
};
static int stmfx_chip_init(struct udevice *dev)
u8 id;
u8 version[2];
int ret;
- struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
+ struct dm_i2c_chip *chip = dev_get_parent_plat(dev);
ret = dm_i2c_reg_read(dev, STMFX_REG_CHIP_ID);
if (ret < 0) {
.ops = &pic32_pinctrl_ops,
.probe = pic32_pinctrl_probe,
.bind = dm_scan_fdt_dev,
- .priv_auto_alloc_size = sizeof(struct pic32_pinctrl_priv),
+ .priv_auto = sizeof(struct pic32_pinctrl_priv),
};
.ops = &stm32_pinctrl_ops,
.bind = stm32_pinctrl_bind,
.probe = stm32_pinctrl_probe,
- .priv_auto_alloc_size = sizeof(struct stm32_pinctrl_priv),
+ .priv_auto = sizeof(struct stm32_pinctrl_priv),
};
DECLARE_GLOBAL_DATA_PTR;
-struct r7s72100_pfc_platdata {
+struct r7s72100_pfc_plat {
void __iomem *base;
};
static void r7s72100_pfc_set_function(struct udevice *dev, u16 bank, u16 line,
u16 func, u16 inbuf, u16 bidir)
{
- struct r7s72100_pfc_platdata *plat = dev_get_platdata(dev);
+ struct r7s72100_pfc_plat *plat = dev_get_plat(dev);
clrsetbits_le16(plat->base + PFCAE(bank), BIT(line),
(func & BIT(2)) ? BIT(line) : 0);
static int r7s72100_pfc_probe(struct udevice *dev)
{
- struct r7s72100_pfc_platdata *plat = dev_get_platdata(dev);
+ struct r7s72100_pfc_plat *plat = dev_get_plat(dev);
fdt_addr_t addr_base;
ofnode node;
.id = UCLASS_PINCTRL,
.of_match = r7s72100_pfc_match,
.probe = r7s72100_pfc_probe,
- .platdata_auto_alloc_size = sizeof(struct r7s72100_pfc_platdata),
+ .plat_auto = sizeof(struct r7s72100_pfc_plat),
.ops = &r7s72100_pfc_ops,
};
.name = "sh_pfc_pinctrl",
.id = UCLASS_PINCTRL,
.of_match = sh_pfc_pinctrl_ids,
- .priv_auto_alloc_size = sizeof(struct sh_pfc_pinctrl_priv),
+ .priv_auto = sizeof(struct sh_pfc_pinctrl_priv),
.ops = &sh_pfc_pinctrl_ops,
.probe = sh_pfc_pinctrl_probe,
};
.name = "rockchip_px30_pinctrl",
.id = UCLASS_PINCTRL,
.of_match = px30_pinctrl_ids,
- .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv),
+ .priv_auto = sizeof(struct rockchip_pinctrl_priv),
.ops = &rockchip_pinctrl_ops,
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
.bind = dm_scan_fdt_dev,
.name = "rk3036-pinctrl",
.id = UCLASS_PINCTRL,
.of_match = rk3036_pinctrl_ids,
- .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv),
+ .priv_auto = sizeof(struct rockchip_pinctrl_priv),
.ops = &rockchip_pinctrl_ops,
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
.bind = dm_scan_fdt_dev,
.name = "pinctrl_rk3128",
.id = UCLASS_PINCTRL,
.of_match = rk3128_pinctrl_ids,
- .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv),
+ .priv_auto = sizeof(struct rockchip_pinctrl_priv),
.ops = &rockchip_pinctrl_ops,
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
.bind = dm_scan_fdt_dev,
.name = "rockchip_rk3188_pinctrl",
.id = UCLASS_PINCTRL,
.of_match = rk3188_pinctrl_ids,
- .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv),
+ .priv_auto = sizeof(struct rockchip_pinctrl_priv),
.ops = &rockchip_pinctrl_ops,
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
.bind = dm_scan_fdt_dev,
.name = "rockchip_rk3228_pinctrl",
.id = UCLASS_PINCTRL,
.of_match = rk3228_pinctrl_ids,
- .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv),
+ .priv_auto = sizeof(struct rockchip_pinctrl_priv),
.ops = &rockchip_pinctrl_ops,
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
.bind = dm_scan_fdt_dev,
.name = "rockchip_rk3288_pinctrl",
.id = UCLASS_PINCTRL,
.of_match = rk3288_pinctrl_ids,
- .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv),
+ .priv_auto = sizeof(struct rockchip_pinctrl_priv),
.ops = &rockchip_pinctrl_ops,
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
.bind = dm_scan_fdt_dev,
.name = "rockchip_rk3308_pinctrl",
.id = UCLASS_PINCTRL,
.of_match = rk3308_pinctrl_ids,
- .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv),
+ .priv_auto = sizeof(struct rockchip_pinctrl_priv),
.ops = &rockchip_pinctrl_ops,
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
.bind = dm_scan_fdt_dev,
.name = "rockchip_rk3328_pinctrl",
.id = UCLASS_PINCTRL,
.of_match = rk3328_pinctrl_ids,
- .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv),
+ .priv_auto = sizeof(struct rockchip_pinctrl_priv),
.ops = &rockchip_pinctrl_ops,
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
.bind = dm_scan_fdt_dev,
.name = "rockchip_rk3368_pinctrl",
.id = UCLASS_PINCTRL,
.of_match = rk3368_pinctrl_ids,
- .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv),
+ .priv_auto = sizeof(struct rockchip_pinctrl_priv),
.ops = &rockchip_pinctrl_ops,
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
.bind = dm_scan_fdt_dev,
.name = "rockchip_rk3399_pinctrl",
.id = UCLASS_PINCTRL,
.of_match = rk3399_pinctrl_ids,
- .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv),
+ .priv_auto = sizeof(struct rockchip_pinctrl_priv),
.ops = &rockchip_pinctrl_ops,
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
.bind = dm_scan_fdt_dev,
.name = "pinctrl_rv1108",
.id = UCLASS_PINCTRL,
.of_match = rv1108_pinctrl_ids,
- .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv),
+ .priv_auto = sizeof(struct rockchip_pinctrl_priv),
.ops = &rockchip_pinctrl_ops,
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
.bind = dm_scan_fdt_dev,
.id = UCLASS_PINCTRL,
.of_match = of_match_ptr(uniphier_ld11_pinctrl_match),
.probe = uniphier_ld11_pinctrl_probe,
- .priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv),
+ .priv_auto = sizeof(struct uniphier_pinctrl_priv),
.ops = &uniphier_pinctrl_ops,
};
.id = UCLASS_PINCTRL,
.of_match = of_match_ptr(uniphier_ld20_pinctrl_match),
.probe = uniphier_ld20_pinctrl_probe,
- .priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv),
+ .priv_auto = sizeof(struct uniphier_pinctrl_priv),
.ops = &uniphier_pinctrl_ops,
};
.id = UCLASS_PINCTRL,
.of_match = of_match_ptr(uniphier_ld4_pinctrl_match),
.probe = uniphier_ld4_pinctrl_probe,
- .priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv),
+ .priv_auto = sizeof(struct uniphier_pinctrl_priv),
.ops = &uniphier_pinctrl_ops,
};
.id = UCLASS_PINCTRL,
.of_match = of_match_ptr(uniphier_ld6b_pinctrl_match),
.probe = uniphier_ld6b_pinctrl_probe,
- .priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv),
+ .priv_auto = sizeof(struct uniphier_pinctrl_priv),
.ops = &uniphier_pinctrl_ops,
};
.id = UCLASS_PINCTRL,
.of_match = of_match_ptr(uniphier_pro4_pinctrl_match),
.probe = uniphier_pro4_pinctrl_probe,
- .priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv),
+ .priv_auto = sizeof(struct uniphier_pinctrl_priv),
.ops = &uniphier_pinctrl_ops,
#if !CONFIG_IS_ENABLED(OF_CONTROL)
.flags = DM_FLAG_PRE_RELOC,
.id = UCLASS_PINCTRL,
.of_match = of_match_ptr(uniphier_pro5_pinctrl_match),
.probe = uniphier_pro5_pinctrl_probe,
- .priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv),
+ .priv_auto = sizeof(struct uniphier_pinctrl_priv),
.ops = &uniphier_pinctrl_ops,
#if !CONFIG_IS_ENABLED(OF_CONTROL)
.flags = DM_FLAG_PRE_RELOC,
.id = UCLASS_PINCTRL,
.of_match = of_match_ptr(uniphier_pxs2_pinctrl_match),
.probe = uniphier_pxs2_pinctrl_probe,
- .priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv),
+ .priv_auto = sizeof(struct uniphier_pinctrl_priv),
.ops = &uniphier_pinctrl_ops,
};
.id = UCLASS_PINCTRL,
.of_match = of_match_ptr(uniphier_pxs3_pinctrl_match),
.probe = uniphier_pxs3_pinctrl_probe,
- .priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv),
+ .priv_auto = sizeof(struct uniphier_pinctrl_priv),
.ops = &uniphier_pinctrl_ops,
};
.id = UCLASS_PINCTRL,
.of_match = of_match_ptr(uniphier_sld8_pinctrl_match),
.probe = uniphier_sld8_pinctrl_probe,
- .priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv),
+ .priv_auto = sizeof(struct uniphier_pinctrl_priv),
.ops = &uniphier_pinctrl_ops,
};
upriv->gen_pmcon1, upriv->gen_pmcon2, upriv->gen_pmcon3);
}
-int pmc_ofdata_to_uc_platdata(struct udevice *dev)
+int pmc_ofdata_to_uc_plat(struct udevice *dev)
{
struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
int ret;
UCLASS_DRIVER(acpi_pmc) = {
.id = UCLASS_ACPI_PMC,
.name = "power-mgr",
- .per_device_auto_alloc_size = sizeof(struct acpi_pmc_upriv),
+ .per_device_auto = sizeof(struct acpi_pmc_upriv),
};
#include <power/acpi_pmc.h>
/**
- * struct pmc_emul_platdata - platform data for this device
+ * struct pmc_emul_plat - platform data for this device
*
* @command: Current PCI command value
* @bar: Current base address values
*/
-struct pmc_emul_platdata {
+struct pmc_emul_plat {
u16 command;
u32 bar[6];
};
static int sandbox_pmc_emul_read_config(const struct udevice *emul, uint offset,
ulong *valuep, enum pci_size_t size)
{
- struct pmc_emul_platdata *plat = dev_get_platdata(emul);
+ struct pmc_emul_plat *plat = dev_get_plat(emul);
switch (offset) {
case PCI_COMMAND:
static int sandbox_pmc_emul_write_config(struct udevice *emul, uint offset,
ulong value, enum pci_size_t size)
{
- struct pmc_emul_platdata *plat = dev_get_platdata(emul);
+ struct pmc_emul_plat *plat = dev_get_plat(emul);
switch (offset) {
case PCI_COMMAND:
static int sandbox_pmc_emul_find_bar(struct udevice *emul, unsigned int addr,
int *barnump, unsigned int *offsetp)
{
- struct pmc_emul_platdata *plat = dev_get_platdata(emul);
+ struct pmc_emul_plat *plat = dev_get_plat(emul);
int barnum;
for (barnum = 0; barnum < ARRAY_SIZE(barinfo); barnum++) {
.of_match = sandbox_pmc_emul_ids,
.ops = &sandbox_pmc_emul_emul_ops,
.probe = sandbox_pmc_probe,
- .priv_auto_alloc_size = sizeof(struct pmc_emul_priv),
- .platdata_auto_alloc_size = sizeof(struct pmc_emul_platdata),
+ .priv_auto = sizeof(struct pmc_emul_priv),
+ .plat_auto = sizeof(struct pmc_emul_plat),
};
static struct pci_device_id sandbox_pmc_emul_supported[] = {
upriv->pmc_bar0 = map_sysmem(base, 0x2000);
upriv->gpe_cfg = (u32 *)(upriv->pmc_bar0 + GPIO_GPE_CFG);
- return pmc_ofdata_to_uc_platdata(dev);
+ return pmc_ofdata_to_uc_plat(dev);
}
static struct acpi_pmc_ops sandbox_pmc_ops = {
.of_match = sandbox_pmc_ids,
.probe = sandbox_pmc_probe,
.ops = &sandbox_pmc_ops,
- .priv_auto_alloc_size = sizeof(struct sandbox_pmc_priv),
+ .priv_auto = sizeof(struct sandbox_pmc_priv),
};
.id = UCLASS_POWER_DOMAIN,
.of_match = bcm6328_power_domain_ids,
.ops = &bcm6328_power_domain_ops,
- .priv_auto_alloc_size = sizeof(struct bcm6328_power_domain),
+ .priv_auto = sizeof(struct bcm6328_power_domain),
.probe = bcm6328_power_domain_probe,
};
static int imx8_power_domain_on(struct power_domain *power_domain)
{
struct udevice *dev = power_domain->dev;
- struct imx8_power_domain_platdata *pdata;
+ struct imx8_power_domain_plat *pdata;
struct imx8_power_domain_priv *ppriv;
sc_err_t ret;
int err;
return err;
}
- pdata = (struct imx8_power_domain_platdata *)dev_get_platdata(dev);
+ pdata = (struct imx8_power_domain_plat *)dev_get_plat(dev);
ppriv = (struct imx8_power_domain_priv *)dev_get_priv(dev);
debug("%s(power_domain=%s) resource_id %d\n", __func__, dev->name,
struct udevice *child;
struct imx8_power_domain_priv *ppriv;
struct imx8_power_domain_priv *child_ppriv;
- struct imx8_power_domain_platdata *pdata;
+ struct imx8_power_domain_plat *pdata;
sc_err_t ret;
ppriv = dev_get_priv(dev);
- pdata = dev_get_platdata(dev);
+ pdata = dev_get_plat(dev);
debug("%s, %s, state_on %d\n", __func__, dev->name, ppriv->state_on);
struct udevice *child;
struct imx8_power_domain_priv *ppriv;
struct imx8_power_domain_priv *child_ppriv;
- struct imx8_power_domain_platdata *pdata;
+ struct imx8_power_domain_plat *pdata;
sc_err_t ret;
struct power_domain parent_pd;
if (device_get_uclass_id(parent) == UCLASS_POWER_DOMAIN) {
pdata =
- (struct imx8_power_domain_platdata *)dev_get_platdata(parent);
+ (struct imx8_power_domain_plat *)dev_get_plat(parent);
ppriv = (struct imx8_power_domain_priv *)dev_get_priv(parent);
debug("%s, %s, state_on %d\n", __func__, parent->name,
return 0;
}
-static int imx8_power_domain_ofdata_to_platdata(struct udevice *dev)
+static int imx8_power_domain_of_to_plat(struct udevice *dev)
{
int reg;
- struct imx8_power_domain_platdata *pdata = dev_get_platdata(dev);
+ struct imx8_power_domain_plat *pdata = dev_get_plat(dev);
reg = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "reg", -1);
if (reg == -1) {
.of_match = imx8_power_domain_ids,
.bind = imx8_power_domain_bind,
.probe = imx8_power_domain_probe,
- .ofdata_to_platdata = imx8_power_domain_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct imx8_power_domain_platdata),
- .priv_auto_alloc_size = sizeof(struct imx8_power_domain_priv),
+ .of_to_plat = imx8_power_domain_of_to_plat,
+ .plat_auto = sizeof(struct imx8_power_domain_plat),
+ .priv_auto = sizeof(struct imx8_power_domain_priv),
.ops = &imx8_power_domain_ops,
.flags = DM_FLAG_DEFAULT_PD_CTRL_OFF,
};
static int imx8m_power_domain_on(struct power_domain *power_domain)
{
struct udevice *dev = power_domain->dev;
- struct imx8m_power_domain_platdata *pdata;
+ struct imx8m_power_domain_plat *pdata;
- pdata = dev_get_platdata(dev);
+ pdata = dev_get_plat(dev);
if (pdata->resource_id < 0)
return -EINVAL;
static int imx8m_power_domain_off(struct power_domain *power_domain)
{
struct udevice *dev = power_domain->dev;
- struct imx8m_power_domain_platdata *pdata;
- pdata = dev_get_platdata(dev);
+ struct imx8m_power_domain_plat *pdata;
+ pdata = dev_get_plat(dev);
if (pdata->resource_id < 0)
return -EINVAL;
return 0;
}
-static int imx8m_power_domain_ofdata_to_platdata(struct udevice *dev)
+static int imx8m_power_domain_of_to_plat(struct udevice *dev)
{
- struct imx8m_power_domain_platdata *pdata = dev_get_platdata(dev);
+ struct imx8m_power_domain_plat *pdata = dev_get_plat(dev);
pdata->resource_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"reg", -1);
.of_match = imx8m_power_domain_ids,
.bind = imx8m_power_domain_bind,
.probe = imx8m_power_domain_probe,
- .ofdata_to_platdata = imx8m_power_domain_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct imx8m_power_domain_platdata),
+ .of_to_plat = imx8m_power_domain_of_to_plat,
+ .plat_auto = sizeof(struct imx8m_power_domain_plat),
.ops = &imx8m_power_domain_ops,
};
.of_match = meson_ee_pwrc_ids,
.probe = meson_ee_pwrc_probe,
.ops = &meson_ee_pwrc_ops,
- .priv_auto_alloc_size = sizeof(struct meson_ee_pwrc_priv),
+ .priv_auto = sizeof(struct meson_ee_pwrc_priv),
};
.of_match = meson_gx_pwrc_vpu_ids,
.probe = meson_gx_pwrc_vpu_probe,
.ops = &meson_gx_pwrc_vpu_ops,
- .priv_auto_alloc_size = sizeof(struct meson_gx_pwrc_vpu_priv),
+ .priv_auto = sizeof(struct meson_gx_pwrc_vpu_priv),
};
.ops = &mtk_power_domain_ops,
.probe = mtk_power_domain_probe,
.of_match = mtk_power_domain_ids,
- .priv_auto_alloc_size = sizeof(struct scp_domain),
+ .priv_auto = sizeof(struct scp_domain),
};
.name = "sandbox_power_domain_test",
.id = UCLASS_MISC,
.of_match = sandbox_power_domain_test_ids,
- .priv_auto_alloc_size = sizeof(struct sandbox_power_domain_test),
+ .priv_auto = sizeof(struct sandbox_power_domain_test),
};
.of_match = sandbox_power_domain_ids,
.bind = sandbox_power_domain_bind,
.probe = sandbox_power_domain_probe,
- .priv_auto_alloc_size = sizeof(struct sandbox_power_domain),
+ .priv_auto = sizeof(struct sandbox_power_domain),
.ops = &sandbox_power_domain_ops,
};
.id = UCLASS_POWER_DOMAIN,
.of_match = ti_sci_power_domain_of_match,
.probe = ti_sci_power_domain_probe,
- .priv_auto_alloc_size = sizeof(struct ti_sci_power_domain_data),
+ .priv_auto = sizeof(struct ti_sci_power_domain_data),
.ops = &ti_sci_power_domain_ops,
};
static int sandbox_i2c_pmic_read_data(struct udevice *emul, uchar chip,
uchar *buffer, int len)
{
- struct sandbox_i2c_pmic_plat_data *plat = dev_get_platdata(emul);
+ struct sandbox_i2c_pmic_plat_data *plat = dev_get_plat(emul);
if (plat->rw_idx + len > plat->buf_size) {
pr_err("Request exceeds PMIC register range! Max register: %#x",
uchar *buffer, int len,
bool next_is_read)
{
- struct sandbox_i2c_pmic_plat_data *plat = dev_get_platdata(emul);
+ struct sandbox_i2c_pmic_plat_data *plat = dev_get_plat(emul);
/* Probe only */
if (!len)
return ret;
}
-static int sandbox_i2c_pmic_ofdata_to_platdata(struct udevice *emul)
+static int sandbox_i2c_pmic_of_to_plat(struct udevice *emul)
{
- struct sandbox_i2c_pmic_plat_data *plat = dev_get_platdata(emul);
+ struct sandbox_i2c_pmic_plat_data *plat = dev_get_plat(emul);
struct udevice *pmic_dev = i2c_emul_get_device(emul);
debug("%s:%d Setting PMIC default registers\n", __func__, __LINE__);
static int sandbox_i2c_pmic_probe(struct udevice *emul)
{
- struct sandbox_i2c_pmic_plat_data *plat = dev_get_platdata(emul);
+ struct sandbox_i2c_pmic_plat_data *plat = dev_get_plat(emul);
struct udevice *pmic_dev = i2c_emul_get_device(emul);
struct uc_pmic_priv *upriv = dev_get_uclass_priv(pmic_dev);
const u8 *reg_defaults;
.name = "sandbox_i2c_pmic_emul",
.id = UCLASS_I2C_EMUL,
.of_match = sandbox_i2c_pmic_ids,
- .ofdata_to_platdata = sandbox_i2c_pmic_ofdata_to_platdata,
+ .of_to_plat = sandbox_i2c_pmic_of_to_plat,
.probe = sandbox_i2c_pmic_probe,
- .platdata_auto_alloc_size = sizeof(struct sandbox_i2c_pmic_plat_data),
+ .plat_auto = sizeof(struct sandbox_i2c_pmic_plat_data),
.ops = &sandbox_i2c_pmic_emul_ops,
};
.bind = dm_scan_fdt_dev,
.probe = pm8916_probe,
.ops = &pm8916_ops,
- .priv_auto_alloc_size = sizeof(struct pm8916_priv),
+ .priv_auto = sizeof(struct pm8916_priv),
};
.id = UCLASS_PMIC,
.name = "pmic",
.pre_probe = pmic_pre_probe,
- .per_device_auto_alloc_size = sizeof(struct uc_pmic_priv),
+ .per_device_auto = sizeof(struct uc_pmic_priv),
};
#if CONFIG_IS_ENABLED(PMIC_CHILDREN)
.bind = rk8xx_bind,
#endif
- .priv_auto_alloc_size = sizeof(struct rk8xx_priv),
+ .priv_auto = sizeof(struct rk8xx_priv),
.probe = rk8xx_probe,
.ops = &rk8xx_ops,
};
static int act8846_reg_probe(struct udevice *dev)
{
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
int reg = dev->driver_data;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
uc_pdata->type = reg <= 4 ? REGULATOR_TYPE_BUCK : REGULATOR_TYPE_LDO;
uc_pdata->mode_count = 0;
static int as3722_stepdown_probe(struct udevice *dev)
{
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
uc_pdata->type = REGULATOR_TYPE_BUCK;
static int as3722_ldo_probe(struct udevice *dev)
{
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
uc_pdata->type = REGULATOR_TYPE_LDO;
};
/**
- * struct bd71837_platdata - describe regulator control registers
+ * struct bd71837_plat - describe regulator control registers
*
* @name: name of the regulator. Used for matching the dt-entry
* @enable_reg: register address used to enable/disable regulator
* @sel_mask: bit to toggle in order to transfer the register control to SW
* @dvs: whether the voltage can be changed when regulator is enabled
*/
-struct bd71837_platdata {
+struct bd71837_plat {
const char *name;
u8 enable_reg;
u8 enablemask;
* is powering NXP i.MX8. In this use-case we (for now) only allow control
* for BUCK3 and BUCK4 which are not boot critical.
*/
-static struct bd71837_platdata bd71837_reg_data[] = {
+static struct bd71837_plat bd71837_reg_data[] = {
/* Bucks 1-4 which support dynamic voltage scaling */
BD_DATA("BUCK1", BD718XX_BUCK1_CTRL, HW_STATE_CONTROL,
BD718XX_BUCK1_VOLT_RUN, DVS_BUCK_RUN_MASK, dvs_buck_vranges, 0,
BD71837_LDO7_MASK, ldo7_vranges, 0, false, BD718XX_LDO_SEL),
};
-static struct bd71837_platdata bd71847_reg_data[] = {
+static struct bd71837_plat bd71847_reg_data[] = {
/* Bucks 1 and 2 which support dynamic voltage scaling */
BD_DATA("BUCK1", BD718XX_BUCK1_CTRL, HW_STATE_CONTROL,
BD718XX_BUCK1_VOLT_RUN, DVS_BUCK_RUN_MASK, dvs_buck_vranges, 0,
static int bd71837_get_enable(struct udevice *dev)
{
int val;
- struct bd71837_platdata *plat = dev_get_platdata(dev);
+ struct bd71837_plat *plat = dev_get_plat(dev);
/*
* boot critical regulators on bd71837 must not be controlled by sw
static int bd71837_set_enable(struct udevice *dev, bool enable)
{
int val = 0;
- struct bd71837_platdata *plat = dev_get_platdata(dev);
+ struct bd71837_plat *plat = dev_get_plat(dev);
/*
* boot critical regulators on bd71837 must not be controlled by sw
unsigned int range;
int i;
int found = 0;
- struct bd71837_platdata *plat = dev_get_platdata(dev);
+ struct bd71837_plat *plat = dev_get_plat(dev);
/*
* An under/overshooting may occur if voltage is changed for other
{
unsigned int reg, range;
unsigned int tmp;
- struct bd71837_platdata *plat = dev_get_platdata(dev);
+ struct bd71837_plat *plat = dev_get_plat(dev);
int i;
reg = pmic_reg_read(dev->parent, plat->volt_reg);
static int bd71837_regulator_probe(struct udevice *dev)
{
- struct bd71837_platdata *plat = dev_get_platdata(dev);
+ struct bd71837_plat *plat = dev_get_plat(dev);
int i, ret;
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
int type;
- struct bd71837_platdata *init_data;
+ struct bd71837_plat *init_data;
int data_amnt;
type = dev_get_driver_data(dev_get_parent(dev));
* the initial state matches dt flags and then
* write the SEL bit
*/
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
ret = bd71837_set_enable(dev,
!!(uc_pdata->boot_on ||
uc_pdata->always_on));
.id = UCLASS_REGULATOR,
.ops = &bd71837_regulator_ops,
.probe = bd71837_regulator_probe,
- .platdata_auto_alloc_size = sizeof(struct bd71837_platdata),
+ .plat_auto = sizeof(struct bd71837_plat),
};
static int da9063_ldo_probe(struct udevice *dev)
{
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
struct da9063_priv *priv = dev->priv;
/* LDOs are named numerically in DT so can directly index */
return -EINVAL;
priv->reg_info = &da9063_ldo_info[dev->driver_data - 1];
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
uc_pdata->type = REGULATOR_TYPE_LDO;
uc_pdata->mode = da9063_ldo_modes;
uc_pdata->mode_count = ARRAY_SIZE(da9063_ldo_modes);
static int da9063_buck_probe(struct udevice *dev)
{
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
struct da9063_priv *priv = dev->priv;
int i;
if (!priv->reg_info)
return -ENODEV;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
uc_pdata->type = REGULATOR_TYPE_BUCK;
uc_pdata->mode = da9063_buck_modes;
uc_pdata->mode_count = ARRAY_SIZE(da9063_buck_modes);
.id = UCLASS_REGULATOR,
.ops = &da9063_ldo_ops,
.probe = da9063_ldo_probe,
- .priv_auto_alloc_size = sizeof(struct da9063_priv),
+ .priv_auto = sizeof(struct da9063_priv),
};
static const struct dm_regulator_ops da9063_buck_ops = {
.id = UCLASS_REGULATOR,
.ops = &da9063_buck_ops,
.probe = da9063_buck_probe,
- .priv_auto_alloc_size = sizeof(struct da9063_priv),
+ .priv_auto = sizeof(struct da9063_priv),
};
FAN53555_MONITOR,
};
-struct fan53555_platdata {
+struct fan53555_plat {
/* Voltage setting register */
unsigned int vol_reg;
unsigned int sleep_reg;
unsigned int sleep_vol_cache;
};
-static int fan53555_regulator_ofdata_to_platdata(struct udevice *dev)
+static int fan53555_regulator_of_to_plat(struct udevice *dev)
{
- struct fan53555_platdata *dev_pdata = dev_get_platdata(dev);
- struct dm_regulator_uclass_platdata *uc_pdata =
- dev_get_uclass_platdata(dev);
+ struct fan53555_plat *dev_pdata = dev_get_plat(dev);
+ struct dm_regulator_uclass_plat *uc_pdata =
+ dev_get_uclass_plat(dev);
u32 sleep_vsel;
/* This is a buck regulator */
static int fan53555_regulator_get_value(struct udevice *dev)
{
- struct fan53555_platdata *pdata = dev_get_platdata(dev);
+ struct fan53555_plat *pdata = dev_get_plat(dev);
struct fan53555_priv *priv = dev_get_priv(dev);
int reg;
int voltage;
static int fan53555_regulator_set_value(struct udevice *dev, int uV)
{
- struct fan53555_platdata *pdata = dev_get_platdata(dev);
+ struct fan53555_plat *pdata = dev_get_plat(dev);
struct fan53555_priv *priv = dev_get_priv(dev);
u8 vol;
.name = "fan53555_regulator",
.id = UCLASS_REGULATOR,
.ops = &fan53555_regulator_ops,
- .ofdata_to_platdata = fan53555_regulator_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct fan53555_platdata),
- .priv_auto_alloc_size = sizeof(struct fan53555_priv),
+ .of_to_plat = fan53555_regulator_of_to_plat,
+ .plat_auto = sizeof(struct fan53555_plat),
+ .priv_auto = sizeof(struct fan53555_priv),
.probe = fan53555_probe,
};
#include "regulator_common.h"
-static int fixed_regulator_ofdata_to_platdata(struct udevice *dev)
+static int fixed_regulator_of_to_plat(struct udevice *dev)
{
- struct dm_regulator_uclass_platdata *uc_pdata;
- struct regulator_common_platdata *dev_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
+ struct regulator_common_plat *dev_pdata;
- dev_pdata = dev_get_platdata(dev);
- uc_pdata = dev_get_uclass_platdata(dev);
+ dev_pdata = dev_get_plat(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
if (!uc_pdata)
return -ENXIO;
uc_pdata->type = REGULATOR_TYPE_FIXED;
- return regulator_common_ofdata_to_platdata(dev, dev_pdata, "gpio");
+ return regulator_common_of_to_plat(dev, dev_pdata, "gpio");
}
static int fixed_regulator_get_value(struct udevice *dev)
{
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
if (!uc_pdata)
return -ENXIO;
static int fixed_regulator_get_current(struct udevice *dev)
{
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
if (!uc_pdata)
return -ENXIO;
static int fixed_regulator_get_enable(struct udevice *dev)
{
- return regulator_common_get_enable(dev, dev_get_platdata(dev));
+ return regulator_common_get_enable(dev, dev_get_plat(dev));
}
static int fixed_regulator_set_enable(struct udevice *dev, bool enable)
{
- return regulator_common_set_enable(dev, dev_get_platdata(dev), enable);
+ return regulator_common_set_enable(dev, dev_get_plat(dev), enable);
}
static const struct dm_regulator_ops fixed_regulator_ops = {
.id = UCLASS_REGULATOR,
.ops = &fixed_regulator_ops,
.of_match = fixed_regulator_ids,
- .ofdata_to_platdata = fixed_regulator_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct regulator_common_platdata),
+ .of_to_plat = fixed_regulator_of_to_plat,
+ .plat_auto = sizeof(struct regulator_common_plat),
};
#define GPIO_REGULATOR_MAX_STATES 2
-struct gpio_regulator_platdata {
- struct regulator_common_platdata common;
+struct gpio_regulator_plat {
+ struct regulator_common_plat common;
struct gpio_desc gpio; /* GPIO for regulator voltage control */
int states[GPIO_REGULATOR_MAX_STATES];
int voltages[GPIO_REGULATOR_MAX_STATES];
};
-static int gpio_regulator_ofdata_to_platdata(struct udevice *dev)
+static int gpio_regulator_of_to_plat(struct udevice *dev)
{
- struct dm_regulator_uclass_platdata *uc_pdata;
- struct gpio_regulator_platdata *dev_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
+ struct gpio_regulator_plat *dev_pdata;
struct gpio_desc *gpio;
int ret, count, i, j;
u32 states_array[GPIO_REGULATOR_MAX_STATES * 2];
- dev_pdata = dev_get_platdata(dev);
- uc_pdata = dev_get_uclass_platdata(dev);
+ dev_pdata = dev_get_plat(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
if (!uc_pdata)
return -ENXIO;
j++;
}
- return regulator_common_ofdata_to_platdata(dev, &dev_pdata->common, "enable-gpios");
+ return regulator_common_of_to_plat(dev, &dev_pdata->common, "enable-gpios");
}
static int gpio_regulator_get_value(struct udevice *dev)
{
- struct dm_regulator_uclass_platdata *uc_pdata;
- struct gpio_regulator_platdata *dev_pdata = dev_get_platdata(dev);
+ struct dm_regulator_uclass_plat *uc_pdata;
+ struct gpio_regulator_plat *dev_pdata = dev_get_plat(dev);
int enable;
if (!dev_pdata->gpio.dev)
return -ENOSYS;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
if (uc_pdata->min_uV > uc_pdata->max_uV) {
debug("Invalid constraints for: %s\n", uc_pdata->name);
return -EINVAL;
static int gpio_regulator_set_value(struct udevice *dev, int uV)
{
- struct gpio_regulator_platdata *dev_pdata = dev_get_platdata(dev);
+ struct gpio_regulator_plat *dev_pdata = dev_get_plat(dev);
int ret;
bool enable;
static int gpio_regulator_get_enable(struct udevice *dev)
{
- struct gpio_regulator_platdata *dev_pdata = dev_get_platdata(dev);
+ struct gpio_regulator_plat *dev_pdata = dev_get_plat(dev);
return regulator_common_get_enable(dev, &dev_pdata->common);
}
static int gpio_regulator_set_enable(struct udevice *dev, bool enable)
{
- struct gpio_regulator_platdata *dev_pdata = dev_get_platdata(dev);
+ struct gpio_regulator_plat *dev_pdata = dev_get_plat(dev);
return regulator_common_set_enable(dev, &dev_pdata->common, enable);
}
.id = UCLASS_REGULATOR,
.ops = &gpio_regulator_ops,
.of_match = gpio_regulator_ids,
- .ofdata_to_platdata = gpio_regulator_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct gpio_regulator_platdata),
+ .of_to_plat = gpio_regulator_of_to_plat,
+ .plat_auto = sizeof(struct gpio_regulator_plat),
};
{
int ret;
unsigned int adr;
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
adr = uc_pdata->ctrl_reg;
ret = pmic_reg_read(dev->parent, adr);
{
unsigned int hex, adr;
int ret;
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
if (op == PMIC_OP_GET)
*uV = 0;
{
int ret;
unsigned int adr;
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
adr = uc_pdata->ctrl_reg;
ret = pmic_reg_read(dev->parent, adr);
unsigned int hex, adr;
int ret;
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
if (op == PMIC_OP_GET)
*uV = 0;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
adr = uc_pdata->volt_reg;
static int lp873x_ldo_probe(struct udevice *dev)
{
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
uc_pdata->type = REGULATOR_TYPE_LDO;
int idx = dev->driver_data;
static int lp873x_buck_probe(struct udevice *dev)
{
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
int idx;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
uc_pdata->type = REGULATOR_TYPE_BUCK;
idx = dev->driver_data;
{
int ret;
unsigned int adr;
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
adr = uc_pdata->ctrl_reg;
ret = pmic_reg_read(dev->parent, adr);
{
unsigned int hex, adr;
int ret;
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
if (op == PMIC_OP_GET)
*uV = 0;
static int lp87565_buck_probe(struct udevice *dev)
{
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
int idx;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
uc_pdata->type = REGULATOR_TYPE_BUCK;
idx = dev->driver_data;
static int max77686_ldo_probe(struct udevice *dev)
{
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
uc_pdata->type = REGULATOR_TYPE_LDO;
uc_pdata->mode_count = max77686_ldo_modes(dev->driver_data,
static int max77686_buck_probe(struct udevice *dev)
{
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
uc_pdata->type = REGULATOR_TYPE_BUCK;
uc_pdata->mode_count = max77686_buck_modes(dev->driver_data,
{
int ret;
unsigned int adr;
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
adr = uc_pdata->ctrl_reg;
ret = pmic_reg_read(dev->parent, adr);
unsigned int hex, adr;
int ret;
bool range;
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
if (op == PMIC_OP_GET)
*uV = 0;
static int palmas_ldo_bypass_enable(struct udevice *dev, bool enabled)
{
int type = dev_get_driver_data(dev_get_parent(dev));
- struct dm_regulator_uclass_platdata *p;
+ struct dm_regulator_uclass_plat *p;
unsigned int adr;
int reg;
return -ENOTSUPP;
}
- p = dev_get_uclass_platdata(dev);
+ p = dev_get_uclass_plat(dev);
adr = p->ctrl_reg;
reg = pmic_reg_read(dev->parent, adr);
{
int ret;
unsigned int adr;
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
adr = uc_pdata->ctrl_reg;
ret = pmic_reg_read(dev->parent, adr);
unsigned int hex, adr;
int ret;
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
if (op == PMIC_OP_GET)
*uV = 0;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
adr = uc_pdata->volt_reg;
static int palmas_ldo_probe(struct udevice *dev)
{
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
struct udevice *parent;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
parent = dev_get_parent(dev);
int type = dev_get_driver_data(parent);
static int palmas_smps_probe(struct udevice *dev)
{
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
struct udevice *parent;
int idx;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
parent = dev_get_parent(dev);
int type = dev_get_driver_data(parent);
return regmap_read(priv->regmap, priv->offset, (u32 *)buff);
}
-static int pbias_ofdata_to_platdata(struct udevice *dev)
+static int pbias_of_to_plat(struct udevice *dev)
{
struct pbias_priv *priv = dev_get_priv(dev);
struct udevice *syscon;
.of_match = pbias_ids,
.bind = pbias_bind,
.ops = &pbias_ops,
- .ofdata_to_platdata = pbias_ofdata_to_platdata,
- .priv_auto_alloc_size = sizeof(struct pbias_priv),
+ .of_to_plat = pbias_of_to_plat,
+ .priv_auto = sizeof(struct pbias_priv),
};
static const struct pbias_reg_info pbias_mmc_omap2430 = {
static int pbias_regulator_probe(struct udevice *dev)
{
const struct pbias_reg_info **p = pbias_reg_infos;
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
while (*p) {
int rc;
};
/**
- * struct pfuze100_regulator_platdata - platform data for pfuze100
+ * struct pfuze100_regulator_plat - platform data for pfuze100
*
* @desc: Points the description entry of one regulator of pfuze100
*/
-struct pfuze100_regulator_platdata {
+struct pfuze100_regulator_plat {
struct pfuze100_regulator_desc *desc;
};
static int pfuze100_regulator_probe(struct udevice *dev)
{
- struct dm_regulator_uclass_platdata *uc_pdata;
- struct pfuze100_regulator_platdata *plat = dev_get_platdata(dev);
+ struct dm_regulator_uclass_plat *uc_pdata;
+ struct pfuze100_regulator_plat *plat = dev_get_plat(dev);
struct pfuze100_regulator_desc *desc;
switch (dev_get_driver_data(dev_get_parent(dev))) {
}
plat->desc = desc;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
uc_pdata->type = desc->type;
if (uc_pdata->type == REGULATOR_TYPE_BUCK) {
static int pfuze100_regulator_mode(struct udevice *dev, int op, int *opmode)
{
int val;
- struct pfuze100_regulator_platdata *plat = dev_get_platdata(dev);
+ struct pfuze100_regulator_plat *plat = dev_get_plat(dev);
struct pfuze100_regulator_desc *desc = plat->desc;
if (op == PMIC_OP_GET) {
{
int val;
int ret, on_off;
- struct dm_regulator_uclass_platdata *uc_pdata =
- dev_get_uclass_platdata(dev);
+ struct dm_regulator_uclass_plat *uc_pdata =
+ dev_get_uclass_plat(dev);
if (op == PMIC_OP_GET) {
if (!strcmp(dev->name, "vrefddr")) {
{
int i;
int val;
- struct pfuze100_regulator_platdata *plat = dev_get_platdata(dev);
+ struct pfuze100_regulator_plat *plat = dev_get_plat(dev);
struct pfuze100_regulator_desc *desc = plat->desc;
- struct dm_regulator_uclass_platdata *uc_pdata =
- dev_get_uclass_platdata(dev);
+ struct dm_regulator_uclass_plat *uc_pdata =
+ dev_get_uclass_plat(dev);
if (op == PMIC_OP_GET) {
*uV = 0;
.id = UCLASS_REGULATOR,
.ops = &pfuze100_regulator_ops,
.probe = pfuze100_regulator_probe,
- .platdata_auto_alloc_size = sizeof(struct pfuze100_regulator_platdata),
+ .plat_auto = sizeof(struct pfuze100_regulator_plat),
};
return ret;
}
-static int pwm_regulator_ofdata_to_platdata(struct udevice *dev)
+static int pwm_regulator_of_to_plat(struct udevice *dev)
{
struct pwm_regulator_info *priv = dev_get_priv(dev);
struct ofnode_phandle_args args;
static int pwm_regulator_probe(struct udevice *dev)
{
struct pwm_regulator_info *priv = dev_get_priv(dev);
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
uc_pdata->type = REGULATOR_TYPE_BUCK;
uc_pdata->mode_count = 0;
.ops = &pwm_regulator_ops,
.probe = pwm_regulator_probe,
.of_match = pwm_regulator_ids,
- .ofdata_to_platdata = pwm_regulator_ofdata_to_platdata,
- .priv_auto_alloc_size = sizeof(struct pwm_regulator_info),
+ .of_to_plat = pwm_regulator_of_to_plat,
+ .priv_auto = sizeof(struct pwm_regulator_info),
};
int regulator_mode(struct udevice *dev, struct dm_regulator_mode **modep)
{
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
*modep = NULL;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
if (!uc_pdata)
return -ENXIO;
int regulator_set_value(struct udevice *dev, int uV)
{
const struct dm_regulator_ops *ops = dev_get_driver_ops(dev);
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
int ret, old_uV = uV, is_enabled = 0;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
if (uc_pdata->min_uV != -ENODATA && uV < uc_pdata->min_uV)
return -EINVAL;
if (uc_pdata->max_uV != -ENODATA && uV > uc_pdata->max_uV)
int regulator_set_suspend_value(struct udevice *dev, int uV)
{
const struct dm_regulator_ops *ops = dev_get_driver_ops(dev);
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
if (uc_pdata->min_uV != -ENODATA && uV < uc_pdata->min_uV)
return -EINVAL;
if (uc_pdata->max_uV != -ENODATA && uV > uc_pdata->max_uV)
int regulator_set_current(struct udevice *dev, int uA)
{
const struct dm_regulator_ops *ops = dev_get_driver_ops(dev);
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
if (uc_pdata->min_uA != -ENODATA && uA < uc_pdata->min_uA)
return -EINVAL;
if (uc_pdata->max_uA != -ENODATA && uA > uc_pdata->max_uA)
int regulator_set_enable(struct udevice *dev, bool enable)
{
const struct dm_regulator_ops *ops = dev_get_driver_ops(dev);
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
int ret, old_enable = 0;
if (!ops || !ops->set_enable)
return -ENOSYS;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
if (!enable && uc_pdata->always_on)
return -EACCES;
int regulator_get_by_platname(const char *plat_name, struct udevice **devp)
{
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
struct udevice *dev;
int ret;
continue;
}
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
if (!uc_pdata || strcmp(plat_name, uc_pdata->name))
continue;
int regulator_autoset(struct udevice *dev)
{
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
int ret = 0;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
ret = regulator_set_suspend_enable(dev, uc_pdata->suspend_on);
if (!ret && uc_pdata->suspend_on) {
static void regulator_show(struct udevice *dev, int ret)
{
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
printf("%s@%s: ", dev->name, uc_pdata->name);
if (uc_pdata->flags & REGULATOR_FLAG_AUTOSET_UV)
static bool regulator_name_is_unique(struct udevice *check_dev,
const char *check_name)
{
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
struct udevice *dev;
int check_len = strlen(check_name);
int ret;
if (ret || dev == check_dev)
continue;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
len = strlen(uc_pdata->name);
if (len != check_len)
continue;
static int regulator_post_bind(struct udevice *dev)
{
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
const char *property = "regulator-name";
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
/* Regulator's mandatory constraint */
uc_pdata->name = dev_read_string(dev, property);
static int regulator_pre_probe(struct udevice *dev)
{
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
ofnode node;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
if (!uc_pdata)
return -ENXIO;
.name = "regulator",
.post_bind = regulator_post_bind,
.pre_probe = regulator_pre_probe,
- .per_device_platdata_auto_alloc_size =
- sizeof(struct dm_regulator_uclass_platdata),
+ .per_device_plat_auto = sizeof(struct dm_regulator_uclass_plat),
};
#include "regulator_common.h"
-int regulator_common_ofdata_to_platdata(struct udevice *dev,
- struct regulator_common_platdata *dev_pdata, const char *enable_gpio_name)
+int regulator_common_of_to_plat(struct udevice *dev,
+ struct regulator_common_plat *dev_pdata,
+ const char *enable_gpio_name)
{
struct gpio_desc *gpio;
int flags = GPIOD_IS_OUT;
}
int regulator_common_get_enable(const struct udevice *dev,
- struct regulator_common_platdata *dev_pdata)
+ struct regulator_common_plat *dev_pdata)
{
/* Enable GPIO is optional */
if (!dev_pdata->gpio.dev)
}
int regulator_common_set_enable(const struct udevice *dev,
- struct regulator_common_platdata *dev_pdata, bool enable)
+ struct regulator_common_plat *dev_pdata, bool enable)
{
int ret;
#include <asm/gpio.h>
-struct regulator_common_platdata {
+struct regulator_common_plat {
struct gpio_desc gpio; /* GPIO for regulator enable control */
unsigned int startup_delay_us;
unsigned int off_on_delay_us;
};
-int regulator_common_ofdata_to_platdata(struct udevice *dev,
- struct regulator_common_platdata *dev_pdata, const char *enable_gpio_name);
+int regulator_common_of_to_plat(struct udevice *dev,
+ struct regulator_common_plat *dev_pdata, const
+ char *enable_gpio_name);
int regulator_common_get_enable(const struct udevice *dev,
- struct regulator_common_platdata *dev_pdata);
+ struct regulator_common_plat *dev_pdata);
int regulator_common_set_enable(const struct udevice *dev,
- struct regulator_common_platdata *dev_pdata, bool enable);
+ struct regulator_common_plat *dev_pdata, bool enable);
#endif /* _REGULATOR_COMMON_H */
static int rk8xx_buck_probe(struct udevice *dev)
{
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
uc_pdata->type = REGULATOR_TYPE_BUCK;
uc_pdata->mode_count = 0;
static int rk8xx_ldo_probe(struct udevice *dev)
{
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
uc_pdata->type = REGULATOR_TYPE_LDO;
uc_pdata->mode_count = 0;
static int rk8xx_switch_probe(struct udevice *dev)
{
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
uc_pdata->type = REGULATOR_TYPE_FIXED;
uc_pdata->mode_count = 0;
static int s2mps11_buck_probe(struct udevice *dev)
{
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
uc_pdata->type = REGULATOR_TYPE_BUCK;
uc_pdata->mode = s2mps11_buck_modes;
static int s2mps11_ldo_probe(struct udevice *dev)
{
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
uc_pdata->type = REGULATOR_TYPE_LDO;
uc_pdata->mode = s2mps11_ldo_modes;
uc_pdata->mode_count = ARRAY_SIZE(s2mps11_ldo_modes);
static int s5m8767_ldo_probe(struct udevice *dev)
{
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
uc_pdata->type = REGULATOR_TYPE_LDO;
uc_pdata->mode_count = 0;
static int s5m8767_buck_probe(struct udevice *dev)
{
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
uc_pdata->type = REGULATOR_TYPE_BUCK;
uc_pdata->mode_count = 0;
static int out_get_mode(struct udevice *dev)
{
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
uint8_t reg_val;
uint reg;
int ret;
int i;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
reg = (dev->driver_data - 1) * OUT_REG_COUNT + OUT_REG_OM;
ret = pmic_read(dev->parent, reg, ®_val, 1);
static int out_set_mode(struct udevice *dev, int mode)
{
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
int reg_val = -1;
uint reg;
int ret;
int i;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
if (mode >= uc_pdata->mode_count)
return -EINVAL;
static int sandbox_buck_probe(struct udevice *dev)
{
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
uc_pdata->type = REGULATOR_TYPE_BUCK;
uc_pdata->mode = sandbox_buck_modes;
static int sandbox_ldo_probe(struct udevice *dev)
{
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
uc_pdata->type = REGULATOR_TYPE_LDO;
uc_pdata->mode = sandbox_ldo_modes;
.of_match = stm32_vrefbuf_ids,
.probe = stm32_vrefbuf_probe,
.ops = &stm32_vrefbuf_ops,
- .priv_auto_alloc_size = sizeof(struct stm32_vrefbuf),
+ .priv_auto = sizeof(struct stm32_vrefbuf),
};
static int stpmic1_buck_set_enable(struct udevice *dev, bool enable)
{
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
int delay = enable ? STPMIC1_DEFAULT_START_UP_DELAY_MS :
STPMIC1_DEFAULT_STOP_DELAY_MS;
int ret, uv;
return 0;
if (enable) {
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
uv = stpmic1_buck_get_value(dev);
if (uv < uc_pdata->min_uV || uv > uc_pdata->max_uV)
stpmic1_buck_set_value(dev, uc_pdata->min_uV);
static int stpmic1_buck_probe(struct udevice *dev)
{
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
if (!dev->driver_data || dev->driver_data > STPMIC1_MAX_BUCK)
return -EINVAL;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
uc_pdata->type = REGULATOR_TYPE_BUCK;
uc_pdata->mode = (struct dm_regulator_mode *)buck_modes;
static int stpmic1_ldo_set_enable(struct udevice *dev, bool enable)
{
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
int delay = enable ? STPMIC1_DEFAULT_START_UP_DELAY_MS :
STPMIC1_DEFAULT_STOP_DELAY_MS;
int ret, uv;
return 0;
if (enable) {
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
uv = stpmic1_ldo_get_value(dev);
if (uv < uc_pdata->min_uV || uv > uc_pdata->max_uV)
stpmic1_ldo_set_value(dev, uc_pdata->min_uV);
static int stpmic1_ldo_probe(struct udevice *dev)
{
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
if (!dev->driver_data || dev->driver_data > STPMIC1_MAX_LDO)
return -EINVAL;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
uc_pdata->type = REGULATOR_TYPE_LDO;
if (dev->driver_data - 1 == STPMIC1_LDO3) {
static int stpmic1_vref_ddr_probe(struct udevice *dev)
{
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
uc_pdata->type = REGULATOR_TYPE_FIXED;
uc_pdata->mode_count = 0;
static int stpmic1_boost_probe(struct udevice *dev)
{
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
uc_pdata->type = REGULATOR_TYPE_FIXED;
uc_pdata->mode_count = 0;
static int stpmic1_pwr_sw_probe(struct udevice *dev)
{
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
if (!dev->driver_data || dev->driver_data > STPMIC1_MAX_PWR_SW)
return -EINVAL;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
uc_pdata->type = REGULATOR_TYPE_FIXED;
uc_pdata->mode_count = 0;
static int tps62360_regulator_set_value(struct udevice *dev, int uV)
{
- struct tps62360_regulator_pdata *pdata = dev_get_platdata(dev);
+ struct tps62360_regulator_pdata *pdata = dev_get_plat(dev);
u8 regval;
if (uV < pdata->config->vmin || uV > pdata->config->vmax)
{
u8 regval;
int ret;
- struct tps62360_regulator_pdata *pdata = dev_get_platdata(dev);
+ struct tps62360_regulator_pdata *pdata = dev_get_plat(dev);
ret = dm_i2c_read(pdata->i2c, TPS62360_REG_SET0 + pdata->vsel_offset,
®val, 1);
static int tps62360_regulator_probe(struct udevice *dev)
{
- struct tps62360_regulator_pdata *pdata = dev_get_platdata(dev);
+ struct tps62360_regulator_pdata *pdata = dev_get_plat(dev);
u8 vsel0;
u8 vsel1;
int ret;
.id = UCLASS_REGULATOR,
.ops = &tps62360_regulator_ops,
.of_match = tps62360_regulator_ids,
- .platdata_auto_alloc_size = sizeof(struct tps62360_regulator_pdata),
+ .plat_auto = sizeof(struct tps62360_regulator_pdata),
.probe = tps62360_regulator_probe,
};
static int tps65090_fet_probe(struct udevice *dev)
{
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
uc_pdata->type = REGULATOR_TYPE_OTHER;
uc_pdata->mode_count = 0;
const struct regulator_props *rgp)
{
int sel, val, vout;
- struct tps65910_regulator_pdata *pdata = dev_get_platdata(dev);
+ struct tps65910_regulator_pdata *pdata = dev_get_plat(dev);
int vin = pdata->supply;
val = pmic_reg_read(dev->parent, rgp->reg);
static int tps65910_ldo_get_value(struct udevice *dev)
{
- struct tps65910_regulator_pdata *pdata = dev_get_platdata(dev);
+ struct tps65910_regulator_pdata *pdata = dev_get_plat(dev);
int vin;
if (!pdata)
{
int val;
int sel = 0;
- struct tps65910_regulator_pdata *pdata = dev_get_platdata(dev);
+ struct tps65910_regulator_pdata *pdata = dev_get_plat(dev);
do {
/* we only allow exact voltage matches */
static int tps65910_ldo_set_value(struct udevice *dev, int uV)
{
- struct tps65910_regulator_pdata *pdata = dev_get_platdata(dev);
+ struct tps65910_regulator_pdata *pdata = dev_get_plat(dev);
int vin = pdata->supply;
switch (pdata->unit) {
static int tps65910_get_enable(struct udevice *dev)
{
int reg, val;
- struct tps65910_regulator_pdata *pdata = dev_get_platdata(dev);
+ struct tps65910_regulator_pdata *pdata = dev_get_plat(dev);
reg = get_ctrl_reg_from_unit_addr(pdata->unit);
if (reg < 0)
{
int reg;
uint clr, set;
- struct tps65910_regulator_pdata *pdata = dev_get_platdata(dev);
+ struct tps65910_regulator_pdata *pdata = dev_get_plat(dev);
reg = get_ctrl_reg_from_unit_addr(pdata->unit);
if (reg < 0)
static int tps65910_buck_get_value(struct udevice *dev)
{
- struct tps65910_regulator_pdata *pdata = dev_get_platdata(dev);
+ struct tps65910_regulator_pdata *pdata = dev_get_plat(dev);
switch (pdata->unit) {
case TPS65910_UNIT_VIO:
{
int ret, reg_vdd, gain;
int val;
- struct dm_regulator_uclass_platdata *uc_pdata;
- struct tps65910_regulator_pdata *pdata = dev_get_platdata(dev);
+ struct dm_regulator_uclass_plat *uc_pdata;
+ struct tps65910_regulator_pdata *pdata = dev_get_plat(dev);
switch (pdata->unit) {
case TPS65910_UNIT_VDD1:
default:
return -EINVAL;
}
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
/* check setpoint is within limits */
if (uV < uc_pdata->min_uV) {
static int tps65910_buck_set_value(struct udevice *dev, int uV)
{
- struct tps65910_regulator_pdata *pdata = dev_get_platdata(dev);
+ struct tps65910_regulator_pdata *pdata = dev_get_plat(dev);
if (pdata->unit == TPS65910_UNIT_VIO)
return tps65910_regulator_set_value(dev, &smps_props_vio, uV);
static int tps65910_boost_get_value(struct udevice *dev)
{
int vout;
- struct tps65910_regulator_pdata *pdata = dev_get_platdata(dev);
+ struct tps65910_regulator_pdata *pdata = dev_get_plat(dev);
vout = (pdata->supply >= 3000000) ? 5000000 : 0;
return vout;
}
-static int tps65910_regulator_ofdata_to_platdata(struct udevice *dev)
+static int tps65910_regulator_of_to_plat(struct udevice *dev)
{
struct udevice *supply;
int ret;
const char *supply_name;
- struct tps65910_regulator_pdata *pdata = dev_get_platdata(dev);
+ struct tps65910_regulator_pdata *pdata = dev_get_plat(dev);
pdata->unit = dev_get_driver_data(dev);
if (pdata->unit > TPS65910_UNIT_VMMC)
.name = TPS65910_BOOST_DRIVER,
.id = UCLASS_REGULATOR,
.ops = &tps65910_boost_ops,
- .platdata_auto_alloc_size = sizeof(struct tps65910_regulator_pdata),
- .ofdata_to_platdata = tps65910_regulator_ofdata_to_platdata,
+ .plat_auto = sizeof(struct tps65910_regulator_pdata),
+ .of_to_plat = tps65910_regulator_of_to_plat,
};
static const struct dm_regulator_ops tps65910_buck_ops = {
.name = TPS65910_BUCK_DRIVER,
.id = UCLASS_REGULATOR,
.ops = &tps65910_buck_ops,
- .platdata_auto_alloc_size = sizeof(struct tps65910_regulator_pdata),
- .ofdata_to_platdata = tps65910_regulator_ofdata_to_platdata,
+ .plat_auto = sizeof(struct tps65910_regulator_pdata),
+ .of_to_plat = tps65910_regulator_of_to_plat,
};
static const struct dm_regulator_ops tps65910_ldo_ops = {
.name = TPS65910_LDO_DRIVER,
.id = UCLASS_REGULATOR,
.ops = &tps65910_ldo_ops,
- .platdata_auto_alloc_size = sizeof(struct tps65910_regulator_pdata),
- .ofdata_to_platdata = tps65910_regulator_ofdata_to_platdata,
+ .plat_auto = sizeof(struct tps65910_regulator_pdata),
+ .of_to_plat = tps65910_regulator_of_to_plat,
};
{
int ret;
unsigned int adr;
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
adr = uc_pdata->ctrl_reg;
ret = pmic_reg_read(dev->parent, adr);
{
unsigned int hex, adr;
int ret, delta, uwait, slew;
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
if (op == PMIC_OP_GET)
*uV = 0;
{
int ret;
unsigned int adr;
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
adr = uc_pdata->ctrl_reg;
ret = pmic_reg_read(dev->parent, adr);
{
unsigned int hex, adr;
int ret;
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
if (op == PMIC_OP_GET)
*uV = 0;
static int tps65941_ldo_probe(struct udevice *dev)
{
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
int idx;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
uc_pdata->type = REGULATOR_TYPE_LDO;
idx = dev->driver_data;
static int tps65941_buck_probe(struct udevice *dev)
{
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
int idx;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
uc_pdata->type = REGULATOR_TYPE_BUCK;
idx = dev->driver_data;
return 0;
}
-static int exynos_pwm_ofdata_to_platdata(struct udevice *dev)
+static int exynos_pwm_of_to_plat(struct udevice *dev)
{
struct exynos_pwm_priv *priv = dev_get_priv(dev);
.of_match = exynos_channels,
.ops = &exynos_pwm_ops,
.probe = exynos_pwm_probe,
- .ofdata_to_platdata = exynos_pwm_ofdata_to_platdata,
- .priv_auto_alloc_size = sizeof(struct exynos_pwm_priv),
+ .of_to_plat = exynos_pwm_of_to_plat,
+ .priv_auto = sizeof(struct exynos_pwm_priv),
};
return 0;
};
-static int imx_pwm_ofdata_to_platdata(struct udevice *dev)
+static int imx_pwm_of_to_plat(struct udevice *dev)
{
struct imx_pwm_priv *priv = dev_get_priv(dev);
.id = UCLASS_PWM,
.of_match = imx_pwm_ids,
.ops = &imx_pwm_ops,
- .ofdata_to_platdata = imx_pwm_ofdata_to_platdata,
+ .of_to_plat = imx_pwm_of_to_plat,
.probe = imx_pwm_probe,
- .priv_auto_alloc_size = sizeof(struct imx_pwm_priv),
+ .priv_auto = sizeof(struct imx_pwm_priv),
};
#endif
return meson_pwm_set_config(dev, channeln, channel->period_ns, channel->duty_ns);
}
-static int meson_pwm_ofdata_to_platdata(struct udevice *dev)
+static int meson_pwm_of_to_plat(struct udevice *dev)
{
struct meson_pwm *priv = dev_get_priv(dev);
.id = UCLASS_PWM,
.of_match = meson_pwm_ids,
.ops = &meson_pwm_ops,
- .ofdata_to_platdata = meson_pwm_ofdata_to_platdata,
+ .of_to_plat = meson_pwm_of_to_plat,
.probe = meson_pwm_probe,
- .priv_auto_alloc_size = sizeof(struct meson_pwm),
+ .priv_auto = sizeof(struct meson_pwm),
};
.of_match = mtk_pwm_ids,
.ops = &mtk_pwm_ops,
.probe = mtk_pwm_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_pwm_priv),
+ .priv_auto = sizeof(struct mtk_pwm_priv),
};
return 0;
}
-static int pwm_sifive_ofdata_to_platdata(struct udevice *dev)
+static int pwm_sifive_of_to_plat(struct udevice *dev)
{
struct pwm_sifive_priv *priv = dev_get_priv(dev);
.id = UCLASS_PWM,
.of_match = pwm_sifive_ids,
.ops = &pwm_sifive_ops,
- .ofdata_to_platdata = pwm_sifive_ofdata_to_platdata,
+ .of_to_plat = pwm_sifive_of_to_plat,
.probe = pwm_sifive_probe,
- .priv_auto_alloc_size = sizeof(struct pwm_sifive_priv),
+ .priv_auto = sizeof(struct pwm_sifive_priv),
};
return 0;
}
-static int rk_pwm_ofdata_to_platdata(struct udevice *dev)
+static int rk_pwm_of_to_plat(struct udevice *dev)
{
struct rk_pwm_priv *priv = dev_get_priv(dev);
.id = UCLASS_PWM,
.of_match = rk_pwm_ids,
.ops = &rk_pwm_ops,
- .ofdata_to_platdata = rk_pwm_ofdata_to_platdata,
+ .of_to_plat = rk_pwm_of_to_plat,
.probe = rk_pwm_probe,
- .priv_auto_alloc_size = sizeof(struct rk_pwm_priv),
+ .priv_auto = sizeof(struct rk_pwm_priv),
};
.id = UCLASS_PWM,
.of_match = sandbox_pwm_ids,
.ops = &sandbox_pwm_ops,
- .priv_auto_alloc_size = sizeof(struct sandbox_pwm_priv),
+ .priv_auto = sizeof(struct sandbox_pwm_priv),
};
return 0;
}
-static int sunxi_pwm_ofdata_to_platdata(struct udevice *dev)
+static int sunxi_pwm_of_to_plat(struct udevice *dev)
{
struct sunxi_pwm_priv *priv = dev_get_priv(dev);
.id = UCLASS_PWM,
.of_match = sunxi_pwm_ids,
.ops = &sunxi_pwm_ops,
- .ofdata_to_platdata = sunxi_pwm_ofdata_to_platdata,
+ .of_to_plat = sunxi_pwm_of_to_plat,
.probe = sunxi_pwm_probe,
- .priv_auto_alloc_size = sizeof(struct sunxi_pwm_priv),
+ .priv_auto = sizeof(struct sunxi_pwm_priv),
};
return 0;
}
-static int tegra_pwm_ofdata_to_platdata(struct udevice *dev)
+static int tegra_pwm_of_to_plat(struct udevice *dev)
{
struct tegra_pwm_priv *priv = dev_get_priv(dev);
.id = UCLASS_PWM,
.of_match = tegra_pwm_ids,
.ops = &tegra_pwm_ops,
- .ofdata_to_platdata = tegra_pwm_ofdata_to_platdata,
- .priv_auto_alloc_size = sizeof(struct tegra_pwm_priv),
+ .of_to_plat = tegra_pwm_of_to_plat,
+ .priv_auto = sizeof(struct tegra_pwm_priv),
};
return 0;
}
-static int ast2500_sdrammc_ofdata_to_platdata(struct udevice *dev)
+static int ast2500_sdrammc_of_to_plat(struct udevice *dev)
{
struct dram_info *priv = dev_get_priv(dev);
struct regmap *map;
.id = UCLASS_RAM,
.of_match = ast2500_sdrammc_ids,
.ops = &ast2500_sdrammc_ops,
- .ofdata_to_platdata = ast2500_sdrammc_ofdata_to_platdata,
+ .of_to_plat = ast2500_sdrammc_of_to_plat,
.probe = ast2500_sdrammc_probe,
- .priv_auto_alloc_size = sizeof(struct dram_info),
+ .priv_auto = sizeof(struct dram_info),
};
.id = UCLASS_RAM,
.of_match = bmips_ram_ids,
.probe = bmips_ram_probe,
- .priv_auto_alloc_size = sizeof(struct bmips_ram_priv),
+ .priv_auto = sizeof(struct bmips_ram_priv),
.ops = &bmips_ram_ops,
};
int imxrt_sdram_init(struct udevice *dev)
{
- struct imxrt_sdram_params *params = dev_get_platdata(dev);
+ struct imxrt_sdram_params *params = dev_get_plat(dev);
struct imxrt_sdram_mux *mux = params->sdram_mux;
struct imxrt_sdram_control *ctrl = params->sdram_control;
struct imxrt_sdram_timing *time = params->sdram_timing;
return 0;
}
-static int imxrt_semc_ofdata_to_platdata(struct udevice *dev)
+static int imxrt_semc_of_to_plat(struct udevice *dev)
{
- struct imxrt_sdram_params *params = dev_get_platdata(dev);
+ struct imxrt_sdram_params *params = dev_get_plat(dev);
ofnode bank_node;
u8 bank = 0;
static int imxrt_semc_probe(struct udevice *dev)
{
- struct imxrt_sdram_params *params = dev_get_platdata(dev);
+ struct imxrt_sdram_params *params = dev_get_plat(dev);
int ret;
fdt_addr_t addr;
.id = UCLASS_RAM,
.of_match = imxrt_semc_ids,
.ops = &imxrt_semc_ops,
- .ofdata_to_platdata = imxrt_semc_ofdata_to_platdata,
+ .of_to_plat = imxrt_semc_of_to_plat,
.probe = imxrt_semc_probe,
- .platdata_auto_alloc_size = sizeof(struct imxrt_sdram_params),
+ .plat_auto = sizeof(struct imxrt_sdram_params),
};
.of_match = am654_ddrss_ids,
.ops = &am654_ddrss_ops,
.probe = am654_ddrss_probe,
- .priv_auto_alloc_size = sizeof(struct am654_ddrss_desc),
+ .priv_auto = sizeof(struct am654_ddrss_desc),
};
.of_match = j721e_ddrss_ids,
.ops = &j721e_ddrss_ops,
.probe = j721e_ddrss_probe,
- .priv_auto_alloc_size = sizeof(struct j721e_ddrss_desc),
+ .priv_auto = sizeof(struct j721e_ddrss_desc),
};
.of_match = mtk_ddr3_ids,
.ops = &mtk_ddr3_ops,
.probe = mtk_ddr3_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_ddr3_priv),
+ .priv_auto = sizeof(struct mtk_ddr3_priv),
};
return 0;
}
-static int mpc83xx_sdram_ofdata_to_platdata(struct udevice *dev)
+static int mpc83xx_sdram_of_to_plat(struct udevice *dev)
{
return 0;
}
.id = UCLASS_RAM,
.of_match = mpc83xx_sdram_ids,
.ops = &mpc83xx_sdram_ops,
- .ofdata_to_platdata = mpc83xx_sdram_ofdata_to_platdata,
+ .of_to_plat = mpc83xx_sdram_of_to_plat,
.probe = mpc83xx_sdram_probe,
- .priv_auto_alloc_size = sizeof(struct mpc83xx_sdram_priv),
+ .priv_auto = sizeof(struct mpc83xx_sdram_priv),
};
.of_match = octeon_ids,
.ops = &octeon_ops,
.probe = octeon_ddr_probe,
- .platdata_auto_alloc_size = sizeof(struct ddr_priv),
+ .plat_auto = sizeof(struct ddr_priv),
};
static int sdram_col_row_detect(struct udevice *dev)
{
struct dram_info *priv = dev_get_priv(dev);
- struct rk3368_sdram_params *params = dev_get_platdata(dev);
+ struct rk3368_sdram_params *params = dev_get_plat(dev);
struct rk3368_ddr_pctl *pctl = priv->pctl;
struct rk3368_msch *msch = priv->msch;
const u32 test_pattern = 0x5aa5f00f;
{
struct dram_info *priv = dev_get_priv(dev);
struct rk3368_pmu_grf *pmugrf = priv->pmugrf;
- struct rk3368_sdram_params *params = dev_get_platdata(dev);
+ struct rk3368_sdram_params *params = dev_get_plat(dev);
const struct rk3288_sdram_channel *info = ¶ms->chan;
u32 sys_reg = 0;
const int chan = 0;
static int setup_sdram(struct udevice *dev)
{
struct dram_info *priv = dev_get_priv(dev);
- struct rk3368_sdram_params *params = dev_get_platdata(dev);
+ struct rk3368_sdram_params *params = dev_get_plat(dev);
struct rk3368_ddr_pctl *pctl = priv->pctl;
struct rk3368_ddrphy *ddrphy = priv->phy;
}
#endif
-static int rk3368_dmc_ofdata_to_platdata(struct udevice *dev)
+static int rk3368_dmc_of_to_plat(struct udevice *dev)
{
int ret = 0;
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
- struct rk3368_sdram_params *plat = dev_get_platdata(dev);
+ struct rk3368_sdram_params *plat = dev_get_plat(dev);
ret = regmap_init_mem(dev_ofnode(dev), &plat->map);
if (ret)
}
#if CONFIG_IS_ENABLED(OF_PLATDATA)
-static int conv_of_platdata(struct udevice *dev)
+static int conv_of_plat(struct udevice *dev)
{
- struct rk3368_sdram_params *plat = dev_get_platdata(dev);
+ struct rk3368_sdram_params *plat = dev_get_plat(dev);
struct dtd_rockchip_rk3368_dmc *of_plat = &plat->of_plat;
plat->ddr_freq = of_plat->rockchip_ddr_frequency;
static int rk3368_dmc_probe(struct udevice *dev)
{
#ifdef CONFIG_TPL_BUILD
- struct rk3368_sdram_params *plat = dev_get_platdata(dev);
+ struct rk3368_sdram_params *plat = dev_get_plat(dev);
struct rk3368_ddr_pctl *pctl;
struct rk3368_ddrphy *ddrphy;
struct rk3368_cru *cru;
struct dram_info *priv = dev_get_priv(dev);
#if CONFIG_IS_ENABLED(OF_PLATDATA)
- ret = conv_of_platdata(dev);
+ ret = conv_of_plat(dev);
if (ret)
return ret;
#endif
.of_match = rk3368_dmc_ids,
.ops = &rk3368_dmc_ops,
.probe = rk3368_dmc_probe,
- .priv_auto_alloc_size = sizeof(struct dram_info),
- .ofdata_to_platdata = rk3368_dmc_ofdata_to_platdata,
+ .priv_auto = sizeof(struct dram_info),
+ .of_to_plat = rk3368_dmc_of_to_plat,
.probe = rk3368_dmc_probe,
- .priv_auto_alloc_size = sizeof(struct dram_info),
- .platdata_auto_alloc_size = sizeof(struct rk3368_sdram_params),
+ .priv_auto = sizeof(struct dram_info),
+ .plat_auto = sizeof(struct rk3368_sdram_params),
};
.of_match = px30_dmc_ids,
.ops = &px30_dmc_ops,
.probe = px30_dmc_probe,
- .priv_auto_alloc_size = sizeof(struct dram_info),
+ .priv_auto = sizeof(struct dram_info),
};
#endif /* CONFIG_TPL_BUILD */
.of_match = rk3128_dmc_ids,
.ops = &rk3128_dmc_ops,
.probe = rk3128_dmc_probe,
- .priv_auto_alloc_size = sizeof(struct dram_info),
+ .priv_auto = sizeof(struct dram_info),
};
static int setup_sdram(struct udevice *dev)
{
struct dram_info *priv = dev_get_priv(dev);
- struct rk3188_sdram_params *params = dev_get_platdata(dev);
+ struct rk3188_sdram_params *params = dev_get_plat(dev);
return sdram_init(priv, params);
}
-static int rk3188_dmc_ofdata_to_platdata(struct udevice *dev)
+static int rk3188_dmc_of_to_plat(struct udevice *dev)
{
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
- struct rk3188_sdram_params *params = dev_get_platdata(dev);
+ struct rk3188_sdram_params *params = dev_get_plat(dev);
int ret;
/* rk3188 supports only one-channel */
#endif /* CONFIG_SPL_BUILD */
#if CONFIG_IS_ENABLED(OF_PLATDATA)
-static int conv_of_platdata(struct udevice *dev)
+static int conv_of_plat(struct udevice *dev)
{
- struct rk3188_sdram_params *plat = dev_get_platdata(dev);
+ struct rk3188_sdram_params *plat = dev_get_plat(dev);
struct dtd_rockchip_rk3188_dmc *of_plat = &plat->of_plat;
int ret;
memcpy(&plat->base, of_plat->rockchip_sdram_params, sizeof(plat->base));
/* rk3188 supports dual-channel, set default channel num to 2 */
plat->num_channels = 1;
- ret = regmap_init_mem_platdata(dev, of_plat->reg,
- ARRAY_SIZE(of_plat->reg) / 2,
- &plat->map);
+ ret = regmap_init_mem_plat(dev, of_plat->reg,
+ ARRAY_SIZE(of_plat->reg) / 2, &plat->map);
if (ret)
return ret;
static int rk3188_dmc_probe(struct udevice *dev)
{
#ifdef CONFIG_SPL_BUILD
- struct rk3188_sdram_params *plat = dev_get_platdata(dev);
+ struct rk3188_sdram_params *plat = dev_get_plat(dev);
struct regmap *map;
struct udevice *dev_clk;
int ret;
#ifdef CONFIG_SPL_BUILD
#if CONFIG_IS_ENABLED(OF_PLATDATA)
- ret = conv_of_platdata(dev);
+ ret = conv_of_plat(dev);
if (ret)
return ret;
#endif
.of_match = rk3188_dmc_ids,
.ops = &rk3188_dmc_ops,
#ifdef CONFIG_SPL_BUILD
- .ofdata_to_platdata = rk3188_dmc_ofdata_to_platdata,
+ .of_to_plat = rk3188_dmc_of_to_plat,
#endif
.probe = rk3188_dmc_probe,
- .priv_auto_alloc_size = sizeof(struct dram_info),
+ .priv_auto = sizeof(struct dram_info),
#ifdef CONFIG_SPL_BUILD
- .platdata_auto_alloc_size = sizeof(struct rk3188_sdram_params),
+ .plat_auto = sizeof(struct rk3188_sdram_params),
#endif
};
return ret;
}
-static int rk322x_dmc_ofdata_to_platdata(struct udevice *dev)
+static int rk322x_dmc_of_to_plat(struct udevice *dev)
{
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
- struct rk322x_sdram_params *params = dev_get_platdata(dev);
+ struct rk322x_sdram_params *params = dev_get_plat(dev);
const void *blob = gd->fdt_blob;
int node = dev_of_offset(dev);
int ret;
#endif /* CONFIG_TPL_BUILD */
#if CONFIG_IS_ENABLED(OF_PLATDATA)
-static int conv_of_platdata(struct udevice *dev)
+static int conv_of_plat(struct udevice *dev)
{
- struct rk322x_sdram_params *plat = dev_get_platdata(dev);
+ struct rk322x_sdram_params *plat = dev_get_plat(dev);
struct dtd_rockchip_rk322x_dmc *of_plat = &plat->of_plat;
int ret;
memcpy(&plat->base, of_plat->rockchip_sdram_params, sizeof(plat->base));
plat->num_channels = 1;
- ret = regmap_init_mem_platdata(dev, of_plat->reg,
- ARRAY_SIZE(of_plat->reg) / 2,
- &plat->map);
+ ret = regmap_init_mem_plat(dev, of_plat->reg,
+ ARRAY_SIZE(of_plat->reg) / 2, &plat->map);
if (ret)
return ret;
static int rk322x_dmc_probe(struct udevice *dev)
{
#ifdef CONFIG_TPL_BUILD
- struct rk322x_sdram_params *plat = dev_get_platdata(dev);
+ struct rk322x_sdram_params *plat = dev_get_plat(dev);
int ret;
struct udevice *dev_clk;
#endif
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
#ifdef CONFIG_TPL_BUILD
#if CONFIG_IS_ENABLED(OF_PLATDATA)
- ret = conv_of_platdata(dev);
+ ret = conv_of_plat(dev);
if (ret)
return ret;
#endif
.of_match = rk322x_dmc_ids,
.ops = &rk322x_dmc_ops,
#ifdef CONFIG_TPL_BUILD
- .ofdata_to_platdata = rk322x_dmc_ofdata_to_platdata,
+ .of_to_plat = rk322x_dmc_of_to_plat,
#endif
.probe = rk322x_dmc_probe,
- .priv_auto_alloc_size = sizeof(struct dram_info),
+ .priv_auto = sizeof(struct dram_info),
#ifdef CONFIG_TPL_BUILD
- .platdata_auto_alloc_size = sizeof(struct rk322x_sdram_params),
+ .plat_auto = sizeof(struct rk322x_sdram_params),
#endif
};
static int setup_sdram(struct udevice *dev)
{
struct dram_info *priv = dev_get_priv(dev);
- struct rk3288_sdram_params *params = dev_get_platdata(dev);
+ struct rk3288_sdram_params *params = dev_get_plat(dev);
# ifdef CONFIG_ROCKCHIP_FAST_SPL
if (priv->is_veyron) {
return sdram_init(priv, params);
}
-static int rk3288_dmc_ofdata_to_platdata(struct udevice *dev)
+static int rk3288_dmc_of_to_plat(struct udevice *dev)
{
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
- struct rk3288_sdram_params *params = dev_get_platdata(dev);
+ struct rk3288_sdram_params *params = dev_get_plat(dev);
int ret;
/* Rk3288 supports dual-channel, set default channel num to 2 */
#endif /* CONFIG_SPL_BUILD */
#if CONFIG_IS_ENABLED(OF_PLATDATA)
-static int conv_of_platdata(struct udevice *dev)
+static int conv_of_plat(struct udevice *dev)
{
- struct rk3288_sdram_params *plat = dev_get_platdata(dev);
+ struct rk3288_sdram_params *plat = dev_get_plat(dev);
struct dtd_rockchip_rk3288_dmc *of_plat = &plat->of_plat;
int ret;
memcpy(&plat->base, of_plat->rockchip_sdram_params, sizeof(plat->base));
/* Rk3288 supports dual-channel, set default channel num to 2 */
plat->num_channels = 2;
- ret = regmap_init_mem_platdata(dev, of_plat->reg,
- ARRAY_SIZE(of_plat->reg) / 2,
- &plat->map);
+ ret = regmap_init_mem_plat(dev, of_plat->reg,
+ ARRAY_SIZE(of_plat->reg) / 2, &plat->map);
if (ret)
return ret;
{
#if defined(CONFIG_TPL_BUILD) || \
(!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
- struct rk3288_sdram_params *plat = dev_get_platdata(dev);
+ struct rk3288_sdram_params *plat = dev_get_plat(dev);
struct udevice *dev_clk;
struct regmap *map;
int ret;
#if defined(CONFIG_TPL_BUILD) || \
(!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
#if CONFIG_IS_ENABLED(OF_PLATDATA)
- ret = conv_of_platdata(dev);
+ ret = conv_of_plat(dev);
if (ret)
return ret;
#endif
.ops = &rk3288_dmc_ops,
#if defined(CONFIG_TPL_BUILD) || \
(!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
- .ofdata_to_platdata = rk3288_dmc_ofdata_to_platdata,
+ .of_to_plat = rk3288_dmc_of_to_plat,
#endif
.probe = rk3288_dmc_probe,
- .priv_auto_alloc_size = sizeof(struct dram_info),
+ .priv_auto = sizeof(struct dram_info),
#if defined(CONFIG_TPL_BUILD) || \
(!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
- .platdata_auto_alloc_size = sizeof(struct rk3288_sdram_params),
+ .plat_auto = sizeof(struct rk3288_sdram_params),
#endif
};
.of_match = rk3308_dmc_ids,
.ops = &rk3308_dmc_ops,
.probe = rk3308_dmc_probe,
- .priv_auto_alloc_size = sizeof(struct dram_info),
+ .priv_auto = sizeof(struct dram_info),
};
};
#if CONFIG_IS_ENABLED(OF_PLATDATA)
-static int conv_of_platdata(struct udevice *dev)
+static int conv_of_plat(struct udevice *dev)
{
- struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
+ struct rockchip_dmc_plat *plat = dev_get_plat(dev);
struct dtd_rockchip_rk3328_dmc *dtplat = &plat->dtplat;
int ret;
- ret = regmap_init_mem_platdata(dev, dtplat->reg,
- ARRAY_SIZE(dtplat->reg) / 2,
- &plat->map);
+ ret = regmap_init_mem_plat(dev, dtplat->reg,
+ ARRAY_SIZE(dtplat->reg) / 2, &plat->map);
if (ret)
return ret;
static int rk3328_dmc_init(struct udevice *dev)
{
struct dram_info *priv = dev_get_priv(dev);
- struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
+ struct rockchip_dmc_plat *plat = dev_get_plat(dev);
int ret;
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct rk3328_sdram_params *params =
(void *)dtplat->rockchip_sdram_params;
- ret = conv_of_platdata(dev);
+ ret = conv_of_plat(dev);
if (ret)
return ret;
#endif
return 0;
}
-static int rk3328_dmc_ofdata_to_platdata(struct udevice *dev)
+static int rk3328_dmc_of_to_plat(struct udevice *dev)
{
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
- struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
+ struct rockchip_dmc_plat *plat = dev_get_plat(dev);
int ret;
ret = dev_read_u32_array(dev, "rockchip,sdram-params",
.of_match = rk3328_dmc_ids,
.ops = &rk3328_dmc_ops,
#ifdef CONFIG_TPL_BUILD
- .ofdata_to_platdata = rk3328_dmc_ofdata_to_platdata,
+ .of_to_plat = rk3328_dmc_of_to_plat,
#endif
.probe = rk3328_dmc_probe,
- .priv_auto_alloc_size = sizeof(struct dram_info),
+ .priv_auto = sizeof(struct dram_info),
#ifdef CONFIG_TPL_BUILD
- .platdata_auto_alloc_size = sizeof(struct rockchip_dmc_plat),
+ .plat_auto = sizeof(struct rockchip_dmc_plat),
#endif
};
return 0;
}
-static int rk3399_dmc_ofdata_to_platdata(struct udevice *dev)
+static int rk3399_dmc_of_to_plat(struct udevice *dev)
{
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
- struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
+ struct rockchip_dmc_plat *plat = dev_get_plat(dev);
int ret;
ret = dev_read_u32_array(dev, "rockchip,sdram-params",
}
#if CONFIG_IS_ENABLED(OF_PLATDATA)
-static int conv_of_platdata(struct udevice *dev)
+static int conv_of_plat(struct udevice *dev)
{
- struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
+ struct rockchip_dmc_plat *plat = dev_get_plat(dev);
struct dtd_rockchip_rk3399_dmc *dtplat = &plat->dtplat;
int ret;
- ret = regmap_init_mem_platdata(dev, dtplat->reg,
- ARRAY_SIZE(dtplat->reg) / 2,
- &plat->map);
+ ret = regmap_init_mem_plat(dev, dtplat->reg,
+ ARRAY_SIZE(dtplat->reg) / 2, &plat->map);
if (ret)
return ret;
static int rk3399_dmc_init(struct udevice *dev)
{
struct dram_info *priv = dev_get_priv(dev);
- struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
+ struct rockchip_dmc_plat *plat = dev_get_plat(dev);
int ret;
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct rk3399_sdram_params *params = &plat->sdram_params;
struct rk3399_sdram_params *params =
(void *)dtplat->rockchip_sdram_params;
- ret = conv_of_platdata(dev);
+ ret = conv_of_plat(dev);
if (ret)
return ret;
#endif
.ops = &rk3399_dmc_ops,
#if defined(CONFIG_TPL_BUILD) || \
(!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
- .ofdata_to_platdata = rk3399_dmc_ofdata_to_platdata,
+ .of_to_plat = rk3399_dmc_of_to_plat,
#endif
.probe = rk3399_dmc_probe,
- .priv_auto_alloc_size = sizeof(struct dram_info),
+ .priv_auto = sizeof(struct dram_info),
#if defined(CONFIG_TPL_BUILD) || \
(!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
- .platdata_auto_alloc_size = sizeof(struct rockchip_dmc_plat),
+ .plat_auto = sizeof(struct rockchip_dmc_plat),
#endif
};
static int fu540_ddr_setup(struct udevice *dev)
{
struct fu540_ddr_info *priv = dev_get_priv(dev);
- struct sifive_dmc_plat *plat = dev_get_platdata(dev);
+ struct sifive_dmc_plat *plat = dev_get_plat(dev);
struct fu540_ddr_params *params = &plat->ddr_params;
volatile u32 *denali_ctl = priv->ctl->denali_ctl;
volatile u32 *denali_phy = priv->phy->denali_phy;
.of_match = fu540_ddr_ids,
.ops = &fu540_ddr_ops,
.probe = fu540_ddr_probe,
- .priv_auto_alloc_size = sizeof(struct fu540_ddr_info),
+ .priv_auto = sizeof(struct fu540_ddr_info),
#if defined(CONFIG_SPL_BUILD)
- .platdata_auto_alloc_size = sizeof(struct sifive_dmc_plat),
+ .plat_auto = sizeof(struct sifive_dmc_plat),
#endif
};
int stm32_sdram_init(struct udevice *dev)
{
- struct stm32_sdram_params *params = dev_get_platdata(dev);
+ struct stm32_sdram_params *params = dev_get_plat(dev);
struct stm32_sdram_control *control;
struct stm32_sdram_timing *timing;
struct stm32_fmc_regs *regs = params->base;
return 0;
}
-static int stm32_fmc_ofdata_to_platdata(struct udevice *dev)
+static int stm32_fmc_of_to_plat(struct udevice *dev)
{
- struct stm32_sdram_params *params = dev_get_platdata(dev);
+ struct stm32_sdram_params *params = dev_get_plat(dev);
struct bank_params *bank_params;
struct ofnode_phandle_args args;
u32 *syscfg_base;
static int stm32_fmc_probe(struct udevice *dev)
{
- struct stm32_sdram_params *params = dev_get_platdata(dev);
+ struct stm32_sdram_params *params = dev_get_plat(dev);
int ret;
fdt_addr_t addr;
.id = UCLASS_RAM,
.of_match = stm32_fmc_ids,
.ops = &stm32_fmc_ops,
- .ofdata_to_platdata = stm32_fmc_ofdata_to_platdata,
+ .of_to_plat = stm32_fmc_of_to_plat,
.probe = stm32_fmc_probe,
- .platdata_auto_alloc_size = sizeof(struct stm32_sdram_params),
+ .plat_auto = sizeof(struct stm32_sdram_params),
};
.of_match = stm32mp1_ddr_ids,
.ops = &stm32mp1_ddr_ops,
.probe = stm32mp1_ddr_probe,
- .priv_auto_alloc_size = sizeof(struct ddr_info),
+ .priv_auto = sizeof(struct ddr_info),
};
.id = UCLASS_REMOTEPROC,
.ops = &k3_sysctrler_ops,
.probe = k3_sysctrler_probe,
- .priv_auto_alloc_size = sizeof(struct k3_sysctrler_privdata),
+ .priv_auto = sizeof(struct k3_sysctrler_privdata),
};
ret = uclass_find_next_device(&dev)) {
if (ret || dev == skip_dev)
continue;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
ret = fn(dev, uc_pdata, data);
if (ret)
return ret;
struct dm_rproc_uclass_pdata *uc_pdata;
const struct dm_rproc_ops *ops;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
/* See if we need to populate via fdt */
- if (!dev->platdata) {
+ if (!dev->plat) {
#if CONFIG_IS_ENABLED(OF_CONTROL)
int node = dev_of_offset(dev);
const void *blob = gd->fdt_blob;
#endif
} else {
- struct dm_rproc_uclass_pdata *pdata = dev->platdata;
+ struct dm_rproc_uclass_pdata *pdata = dev->plat;
debug("'%s': using legacy data\n", dev->name);
if (pdata->name)
.flags = DM_UC_FLAG_SEQ_ALIAS,
.pre_probe = rproc_pre_probe,
.post_probe = rproc_post_probe,
- .per_device_platdata_auto_alloc_size =
- sizeof(struct dm_rproc_uclass_pdata),
+ .per_device_plat_auto = sizeof(struct dm_rproc_uclass_pdata),
};
/* Remoteproc subsystem access functions */
return ret;
}
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
ops = rproc_get_ops(dev);
if (!ops) {
return ret;
}
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
ops = rproc_get_ops(dev);
if (!ops) {
struct sandbox_test_devdata *ddata;
int ret;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
ddata = dev_get_priv(dev);
if (!ddata) {
debug("%s: platform private data missing\n", uc_pdata->name);
struct dm_rproc_uclass_pdata *uc_pdata;
int ret;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
ret = sandbox_dev_move_to_state(dev, sb_init);
struct dm_rproc_uclass_pdata *uc_pdata;
int ret;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
ret = sandbox_dev_move_to_state(dev, sb_reset);
struct dm_rproc_uclass_pdata *uc_pdata;
int ret;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
ret = sandbox_dev_move_to_state(dev, sb_loaded);
struct dm_rproc_uclass_pdata *uc_pdata;
int ret;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
ret = sandbox_dev_move_to_state(dev, sb_running);
struct dm_rproc_uclass_pdata *uc_pdata;
int ret;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
ret = sandbox_dev_move_to_state(dev, sb_init);
struct sandbox_test_devdata *ddata;
int ret = 1;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
ddata = dev_get_priv(dev);
if (ddata->current_state == sb_running)
struct sandbox_test_devdata *ddata;
int ret;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
ddata = dev_get_priv(dev);
if (ddata->current_state == sb_running)
.id = UCLASS_REMOTEPROC,
.ops = &sandbox_testproc_ops,
.probe = sandbox_testproc_probe,
- .priv_auto_alloc_size = sizeof(struct sandbox_test_devdata),
+ .priv_auto = sizeof(struct sandbox_test_devdata),
};
U_BOOT_DEVICE(proc_3_demo) = {
.name = "sandbox_test_proc",
- .platdata = &proc_3_test,
+ .plat = &proc_3_test,
};
.id = UCLASS_REMOTEPROC,
.ops = &stm32_copro_ops,
.probe = stm32_copro_probe,
- .priv_auto_alloc_size = sizeof(struct stm32_copro_privdata),
+ .priv_auto = sizeof(struct stm32_copro_privdata),
};
.id = UCLASS_REMOTEPROC,
.ops = &k3_arm64_ops,
.probe = k3_arm64_probe,
- .priv_auto_alloc_size = sizeof(struct k3_arm64_privdata),
+ .priv_auto = sizeof(struct k3_arm64_privdata),
.flags = DM_FLAG_DEFAULT_PD_CTRL_OFF,
};
.ops = &k3_dsp_ops,
.probe = k3_dsp_probe,
.remove = k3_dsp_remove,
- .priv_auto_alloc_size = sizeof(struct k3_dsp_privdata),
+ .priv_auto = sizeof(struct k3_dsp_privdata),
};
.ops = &k3_r5f_rproc_ops,
.probe = k3_r5f_probe,
.remove = k3_r5f_remove,
- .priv_auto_alloc_size = sizeof(struct k3_r5f_core),
+ .priv_auto = sizeof(struct k3_r5f_core),
};
static int k3_r5f_cluster_probe(struct udevice *dev)
.of_match = k3_r5fss_ids,
.id = UCLASS_MISC,
.probe = k3_r5f_cluster_probe,
- .priv_auto_alloc_size = sizeof(struct k3_r5f_cluster),
+ .priv_auto = sizeof(struct k3_r5f_cluster),
.flags = DM_FLAG_DEFAULT_PD_CTRL_OFF,
};
struct ti_powerproc_privdata *priv;
int ret;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
priv = dev_get_priv(dev);
ret = ti_of_to_priv(dev, priv);
struct ti_powerproc_privdata *priv;
int ret;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
if (!uc_pdata) {
debug("%s: no uc pdata!\n", dev->name);
return -EINVAL;
struct ti_powerproc_privdata *priv;
int ret;
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
if (!uc_pdata) {
debug("%s: no uc pdata!\n", dev->name);
return -EINVAL;
.id = UCLASS_REMOTEPROC,
.ops = &ti_powerproc_ops,
.probe = ti_powerproc_probe,
- .priv_auto_alloc_size = sizeof(struct ti_powerproc_privdata),
+ .priv_auto = sizeof(struct ti_powerproc_privdata),
};
.of_match = ast2500_reset_ids,
.probe = ast2500_reset_probe,
.ops = &ast2500_reset_ops,
- .priv_auto_alloc_size = sizeof(struct ast2500_reset_priv),
+ .priv_auto = sizeof(struct ast2500_reset_priv),
};
.of_match = bcm6345_reset_ids,
.ops = &bcm6345_reset_reset_ops,
.probe = bcm6345_reset_probe,
- .priv_auto_alloc_size = sizeof(struct bcm6345_reset_priv),
+ .priv_auto = sizeof(struct bcm6345_reset_priv),
};
.of_match = hisi_reset_ids,
.ops = &hisi_reset_reset_ops,
.probe = hisi_reset_probe,
- .priv_auto_alloc_size = sizeof(struct hisi_reset_priv),
+ .priv_auto = sizeof(struct hisi_reset_priv),
};
.of_match = hsdk_reset_dt_match,
.ops = &hsdk_reset_ops,
.probe = hsdk_reset_probe,
- .priv_auto_alloc_size = sizeof(struct hsdk_rst),
+ .priv_auto = sizeof(struct hsdk_rst),
};
.of_match = imx7_reset_ids,
.ops = &imx7_reset_reset_ops,
.probe = imx7_reset_probe,
- .priv_auto_alloc_size = sizeof(struct imx7_reset_priv),
+ .priv_auto = sizeof(struct imx7_reset_priv),
};
.of_match = ipq4019_reset_ids,
.ops = &ipq4019_reset_ops,
.probe = ipq4019_reset_probe,
- .priv_auto_alloc_size = sizeof(struct ipq4019_reset_priv),
+ .priv_auto = sizeof(struct ipq4019_reset_priv),
};
.id = UCLASS_RESET,
.probe = mediatek_reset_probe,
.ops = &mediatek_reset_ops,
- .priv_auto_alloc_size = sizeof(struct mediatek_reset_priv),
+ .priv_auto = sizeof(struct mediatek_reset_priv),
};
.of_match = meson_reset_ids,
.probe = meson_reset_probe,
.ops = &meson_reset_ops,
- .priv_auto_alloc_size = sizeof(struct meson_reset_priv),
+ .priv_auto = sizeof(struct meson_reset_priv),
};
return 0;
}
-static int mtmips_reset_ofdata_to_platdata(struct udevice *dev)
+static int mtmips_reset_of_to_plat(struct udevice *dev)
{
struct mtmips_reset_priv *priv = dev_get_priv(dev);
.name = "mtmips-reset",
.id = UCLASS_RESET,
.of_match = mtmips_reset_ids,
- .ofdata_to_platdata = mtmips_reset_ofdata_to_platdata,
+ .of_to_plat = mtmips_reset_of_to_plat,
.probe = mtmips_reset_probe,
- .priv_auto_alloc_size = sizeof(struct mtmips_reset_priv),
+ .priv_auto = sizeof(struct mtmips_reset_priv),
.ops = &mtmips_reset_ops,
};
.id = UCLASS_RESET,
.probe = rockchip_reset_probe,
.ops = &rockchip_reset_ops,
- .priv_auto_alloc_size = sizeof(struct rockchip_reset_priv),
+ .priv_auto = sizeof(struct rockchip_reset_priv),
};
.id = UCLASS_RESET,
.ops = &sifive_reset_ops,
.probe = sifive_reset_probe,
- .priv_auto_alloc_size = sizeof(struct sifive_reset_priv),
+ .priv_auto = sizeof(struct sifive_reset_priv),
};
.of_match = socfpga_reset_match,
.bind = socfpga_reset_bind,
.probe = socfpga_reset_probe,
- .priv_auto_alloc_size = sizeof(struct socfpga_reset_data),
+ .priv_auto = sizeof(struct socfpga_reset_data),
.ops = &socfpga_reset_ops,
.remove = socfpga_reset_remove,
.flags = DM_FLAG_OS_PREPARE,
.id = UCLASS_RESET,
.ops = &sunxi_reset_ops,
.probe = sunxi_reset_probe,
- .priv_auto_alloc_size = sizeof(struct sunxi_reset_priv),
+ .priv_auto = sizeof(struct sunxi_reset_priv),
};
.id = UCLASS_RESET,
.of_match = syscon_reset_ids,
.probe = syscon_reset_probe,
- .priv_auto_alloc_size = sizeof(struct syscon_reset_priv),
+ .priv_auto = sizeof(struct syscon_reset_priv),
.ops = &syscon_reset_ops,
};
.id = UCLASS_RESET,
.of_match = ti_sci_reset_of_match,
.probe = ti_sci_reset_probe,
- .priv_auto_alloc_size = sizeof(struct ti_sci_reset_data),
+ .priv_auto = sizeof(struct ti_sci_reset_data),
.ops = &ti_sci_reset_ops,
};
.id = UCLASS_RESET,
.of_match = uniphier_reset_match,
.probe = uniphier_reset_probe,
- .priv_auto_alloc_size = sizeof(struct uniphier_reset_priv),
+ .priv_auto = sizeof(struct uniphier_reset_priv),
.ops = &uniphier_reset_ops,
};
.name = "sandbox_reset_test",
.id = UCLASS_MISC,
.of_match = sandbox_reset_test_ids,
- .priv_auto_alloc_size = sizeof(struct sandbox_reset_test),
+ .priv_auto = sizeof(struct sandbox_reset_test),
};
.of_match = sandbox_reset_ids,
.bind = sandbox_reset_bind,
.probe = sandbox_reset_probe,
- .priv_auto_alloc_size = sizeof(struct sandbox_reset),
+ .priv_auto = sizeof(struct sandbox_reset),
.ops = &sandbox_reset_reset_ops,
};
.id = UCLASS_RESET,
.of_match = sti_reset_ids,
.probe = sti_reset_probe,
- .priv_auto_alloc_size = sizeof(struct sti_reset),
+ .priv_auto = sizeof(struct sti_reset),
.ops = &sti_reset_ops,
};
.name = "stm32_rcc_reset",
.id = UCLASS_RESET,
.probe = stm32_reset_probe,
- .priv_auto_alloc_size = sizeof(struct stm32_reset_priv),
+ .priv_auto = sizeof(struct stm32_reset_priv),
.ops = &stm32_reset_ops,
};
#include <rng.h>
#include <asm/io.h>
-struct meson_rng_platdata {
+struct meson_rng_plat {
fdt_addr_t base;
struct clk clk;
};
*/
static int meson_rng_read(struct udevice *dev, void *data, size_t len)
{
- struct meson_rng_platdata *pdata = dev_get_platdata(dev);
+ struct meson_rng_plat *pdata = dev_get_plat(dev);
char *buffer = (char *)data;
while (len) {
*/
static int meson_rng_probe(struct udevice *dev)
{
- struct meson_rng_platdata *pdata = dev_get_platdata(dev);
+ struct meson_rng_plat *pdata = dev_get_plat(dev);
int err;
err = clk_enable(&pdata->clk);
*/
static int meson_rng_remove(struct udevice *dev)
{
- struct meson_rng_platdata *pdata = dev_get_platdata(dev);
+ struct meson_rng_plat *pdata = dev_get_plat(dev);
return clk_disable(&pdata->clk);
}
/**
- * meson_rng_ofdata_to_platdata() - transfer device tree data to plaform data
+ * meson_rng_of_to_plat() - transfer device tree data to plaform data
*
* @dev: device
* Return: 0 if ok
*/
-static int meson_rng_ofdata_to_platdata(struct udevice *dev)
+static int meson_rng_of_to_plat(struct udevice *dev)
{
- struct meson_rng_platdata *pdata = dev_get_platdata(dev);
+ struct meson_rng_plat *pdata = dev_get_plat(dev);
int err;
pdata->base = dev_read_addr(dev);
.ops = &meson_rng_ops,
.probe = meson_rng_probe,
.remove = meson_rng_remove,
- .platdata_auto_alloc_size = sizeof(struct meson_rng_platdata),
- .ofdata_to_platdata = meson_rng_ofdata_to_platdata,
+ .plat_auto = sizeof(struct meson_rng_plat),
+ .of_to_plat = meson_rng_of_to_plat,
};
.ops = &msm_rng_ops,
.probe = msm_rng_probe,
.remove = msm_rng_remove,
- .priv_auto_alloc_size = sizeof(struct msm_rng_priv),
+ .priv_auto = sizeof(struct msm_rng_priv),
};
int (*rk_rng_read)(struct udevice *dev, void *data, size_t len);
};
-struct rk_rng_platdata {
+struct rk_rng_plat {
fdt_addr_t base;
struct rk_rng_soc_data *soc_data;
};
static int rk_v1_rng_read(struct udevice *dev, void *data, size_t len)
{
- struct rk_rng_platdata *pdata = dev_get_priv(dev);
+ struct rk_rng_plat *pdata = dev_get_priv(dev);
u32 reg = 0;
int retval;
static int rk_v2_rng_read(struct udevice *dev, void *data, size_t len)
{
- struct rk_rng_platdata *pdata = dev_get_priv(dev);
+ struct rk_rng_plat *pdata = dev_get_priv(dev);
u32 reg = 0;
int retval;
unsigned int i;
int ret = -EIO;
- struct rk_rng_platdata *pdata = dev_get_priv(dev);
+ struct rk_rng_plat *pdata = dev_get_priv(dev);
if (!len)
return 0;
return ret;
}
-static int rockchip_rng_ofdata_to_platdata(struct udevice *dev)
+static int rockchip_rng_of_to_plat(struct udevice *dev)
{
- struct rk_rng_platdata *pdata = dev_get_priv(dev);
+ struct rk_rng_plat *pdata = dev_get_priv(dev);
memset(pdata, 0x00, sizeof(*pdata));
static int rockchip_rng_probe(struct udevice *dev)
{
- struct rk_rng_platdata *pdata = dev_get_priv(dev);
+ struct rk_rng_plat *pdata = dev_get_priv(dev);
pdata->soc_data = (struct rk_rng_soc_data *)dev_get_driver_data(dev);
.of_match = rockchip_rng_match,
.ops = &rockchip_rng_ops,
.probe = rockchip_rng_probe,
- .ofdata_to_platdata = rockchip_rng_ofdata_to_platdata,
- .priv_auto_alloc_size = sizeof(struct rk_rng_platdata),
+ .of_to_plat = rockchip_rng_of_to_plat,
+ .priv_auto = sizeof(struct rk_rng_plat),
};
#define RNG_DR 0x08
-struct stm32_rng_platdata {
+struct stm32_rng_plat {
fdt_addr_t base;
struct clk clk;
struct reset_ctl rst;
int retval, i;
u32 sr, count, reg;
size_t increment;
- struct stm32_rng_platdata *pdata = dev_get_platdata(dev);
+ struct stm32_rng_plat *pdata = dev_get_plat(dev);
while (len > 0) {
retval = readl_poll_timeout(pdata->base + RNG_SR, sr,
return 0;
}
-static int stm32_rng_init(struct stm32_rng_platdata *pdata)
+static int stm32_rng_init(struct stm32_rng_plat *pdata)
{
int err;
return 0;
}
-static int stm32_rng_cleanup(struct stm32_rng_platdata *pdata)
+static int stm32_rng_cleanup(struct stm32_rng_plat *pdata)
{
writel(0, pdata->base + RNG_CR);
static int stm32_rng_probe(struct udevice *dev)
{
- struct stm32_rng_platdata *pdata = dev_get_platdata(dev);
+ struct stm32_rng_plat *pdata = dev_get_plat(dev);
reset_assert(&pdata->rst);
udelay(20);
static int stm32_rng_remove(struct udevice *dev)
{
- struct stm32_rng_platdata *pdata = dev_get_platdata(dev);
+ struct stm32_rng_plat *pdata = dev_get_plat(dev);
return stm32_rng_cleanup(pdata);
}
-static int stm32_rng_ofdata_to_platdata(struct udevice *dev)
+static int stm32_rng_of_to_plat(struct udevice *dev)
{
- struct stm32_rng_platdata *pdata = dev_get_platdata(dev);
+ struct stm32_rng_plat *pdata = dev_get_plat(dev);
int err;
pdata->base = dev_read_addr(dev);
.ops = &stm32_rng_ops,
.probe = stm32_rng_probe,
.remove = stm32_rng_remove,
- .platdata_auto_alloc_size = sizeof(struct stm32_rng_platdata),
- .ofdata_to_platdata = stm32_rng_ofdata_to_platdata,
+ .plat_auto = sizeof(struct stm32_rng_plat),
+ .of_to_plat = stm32_rng_of_to_plat,
};
.probe = ds3232_probe,
.of_match = ds3232_rtc_ids,
.ops = &ds3232_rtc_ops,
- .priv_auto_alloc_size = sizeof(struct ds3232_priv_data),
+ .priv_auto = sizeof(struct ds3232_priv_data),
};
.id = UCLASS_RTC,
.ops = &emul_rtc_ops,
.probe = emul_rtc_probe,
- .priv_auto_alloc_size = sizeof(struct emul_rtc),
+ .priv_auto = sizeof(struct emul_rtc),
};
U_BOOT_DEVICE(rtc_emul) = {
long sandbox_i2c_rtc_set_offset(struct udevice *dev, bool use_system_time,
int offset)
{
- struct sandbox_i2c_rtc_plat_data *plat = dev_get_platdata(dev);
+ struct sandbox_i2c_rtc_plat_data *plat = dev_get_plat(dev);
long old_offset;
old_offset = plat->offset;
long sandbox_i2c_rtc_get_set_base_time(struct udevice *dev, long base_time)
{
- struct sandbox_i2c_rtc_plat_data *plat = dev_get_platdata(dev);
+ struct sandbox_i2c_rtc_plat_data *plat = dev_get_plat(dev);
long old_base_time;
old_base_time = plat->base_time;
static void reset_time(struct udevice *dev)
{
- struct sandbox_i2c_rtc_plat_data *plat = dev_get_platdata(dev);
+ struct sandbox_i2c_rtc_plat_data *plat = dev_get_plat(dev);
struct rtc_time now;
os_localtime(&now);
static int sandbox_i2c_rtc_get(struct udevice *dev, struct rtc_time *time)
{
- struct sandbox_i2c_rtc_plat_data *plat = dev_get_platdata(dev);
+ struct sandbox_i2c_rtc_plat_data *plat = dev_get_plat(dev);
struct rtc_time tm_now;
long now;
static int sandbox_i2c_rtc_set(struct udevice *dev, const struct rtc_time *time)
{
- struct sandbox_i2c_rtc_plat_data *plat = dev_get_platdata(dev);
+ struct sandbox_i2c_rtc_plat_data *plat = dev_get_plat(dev);
struct rtc_time tm_now;
long now;
/* Update the current time in the registers */
static int sandbox_i2c_rtc_prepare_read(struct udevice *emul)
{
- struct sandbox_i2c_rtc_plat_data *plat = dev_get_platdata(emul);
+ struct sandbox_i2c_rtc_plat_data *plat = dev_get_plat(emul);
struct rtc_time time;
int ret;
static int sandbox_i2c_rtc_complete_write(struct udevice *emul)
{
- struct sandbox_i2c_rtc_plat_data *plat = dev_get_platdata(emul);
+ struct sandbox_i2c_rtc_plat_data *plat = dev_get_plat(emul);
struct rtc_time time;
int ret;
static int sandbox_i2c_rtc_xfer(struct udevice *emul, struct i2c_msg *msg,
int nmsgs)
{
- struct sandbox_i2c_rtc_plat_data *plat = dev_get_platdata(emul);
+ struct sandbox_i2c_rtc_plat_data *plat = dev_get_plat(emul);
uint offset = 0;
int ret;
.id = UCLASS_I2C_EMUL,
.of_match = sandbox_i2c_rtc_ids,
.bind = sandbox_i2c_rtc_bind,
- .priv_auto_alloc_size = sizeof(struct sandbox_i2c_rtc),
- .platdata_auto_alloc_size = sizeof(struct sandbox_i2c_rtc_plat_data),
+ .priv_auto = sizeof(struct sandbox_i2c_rtc),
+ .plat_auto = sizeof(struct sandbox_i2c_rtc_plat_data),
.ops = &sandbox_i2c_rtc_emul_ops,
};
#ifdef CONFIG_DM_RTC
static int mv_rtc_get(struct udevice *dev, struct rtc_time *tm)
{
- struct mvrtc_pdata *pdata = dev_get_platdata(dev);
+ struct mvrtc_pdata *pdata = dev_get_plat(dev);
struct mvrtc_registers *regs = (struct mvrtc_registers *)pdata->iobase;
return __mv_rtc_get(regs, tm);
static int mv_rtc_set(struct udevice *dev, const struct rtc_time *tm)
{
- struct mvrtc_pdata *pdata = dev_get_platdata(dev);
+ struct mvrtc_pdata *pdata = dev_get_plat(dev);
struct mvrtc_registers *regs = (struct mvrtc_registers *)pdata->iobase;
return __mv_rtc_set(regs, tm);
static int mv_rtc_reset(struct udevice *dev)
{
- struct mvrtc_pdata *pdata = dev_get_platdata(dev);
+ struct mvrtc_pdata *pdata = dev_get_plat(dev);
struct mvrtc_registers *regs = (struct mvrtc_registers *)pdata->iobase;
__mv_rtc_reset(regs);
{ }
};
-static int mv_rtc_ofdata_to_platdata(struct udevice *dev)
+static int mv_rtc_of_to_plat(struct udevice *dev)
{
- struct mvrtc_pdata *pdata = dev_get_platdata(dev);
+ struct mvrtc_pdata *pdata = dev_get_plat(dev);
pdata->iobase = dev_read_addr(dev);
return 0;
U_BOOT_DRIVER(rtc_mv) = {
.name = "rtc-mv",
.id = UCLASS_RTC,
- .ofdata_to_platdata = mv_rtc_ofdata_to_platdata,
+ .of_to_plat = mv_rtc_of_to_plat,
.of_match = mv_rtc_ids,
.ops = &mv_rtc_ops,
};
static int pcf2127_rtc_read(struct udevice *dev, uint offset, u8 *buffer, uint len)
{
- struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
+ struct dm_i2c_chip *chip = dev_get_parent_plat(dev);
struct i2c_msg msg;
int ret;
#define RTC_CR_START (1 << 0)
-struct pl031_platdata {
+struct pl031_plat {
phys_addr_t base;
};
static inline u32 pl031_read_reg(struct udevice *dev, int reg)
{
- struct pl031_platdata *pdata = dev_get_platdata(dev);
+ struct pl031_plat *pdata = dev_get_plat(dev);
return readl(pdata->base + reg);
}
static inline u32 pl031_write_reg(struct udevice *dev, int reg, u32 value)
{
- struct pl031_platdata *pdata = dev_get_platdata(dev);
+ struct pl031_plat *pdata = dev_get_plat(dev);
return writel(value, pdata->base + reg);
}
{ }
};
-static int pl031_ofdata_to_platdata(struct udevice *dev)
+static int pl031_of_to_plat(struct udevice *dev)
{
- struct pl031_platdata *pdata = dev_get_platdata(dev);
+ struct pl031_plat *pdata = dev_get_plat(dev);
pdata->base = dev_read_addr(dev);
.id = UCLASS_RTC,
.of_match = pl031_ids,
.probe = pl031_probe,
- .ofdata_to_platdata = pl031_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct pl031_platdata),
+ .of_to_plat = pl031_of_to_plat,
+ .plat_auto = sizeof(struct pl031_plat),
.ops = &pl031_ops,
};
.probe = stm32_rtc_probe,
.of_match = stm32_rtc_ids,
.ops = &stm32_rtc_ops,
- .priv_auto_alloc_size = sizeof(struct stm32_rtc_priv),
+ .priv_auto = sizeof(struct stm32_rtc_priv),
};
UCLASS_DRIVER(scsi) = {
.id = UCLASS_SCSI,
.name = "scsi",
- .per_device_platdata_auto_alloc_size = sizeof(struct scsi_platdata),
+ .per_device_plat_auto = sizeof(struct scsi_plat),
};
static ulong scsi_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
void *buffer)
{
- struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
+ struct blk_desc *block_dev = dev_get_uclass_plat(dev);
struct udevice *bdev = dev->parent;
- struct scsi_platdata *uc_plat = dev_get_uclass_platdata(bdev);
+ struct scsi_plat *uc_plat = dev_get_uclass_plat(bdev);
lbaint_t start, blks, max_blks;
uintptr_t buf_addr;
unsigned short smallblks = 0;
static ulong scsi_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
const void *buffer)
{
- struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
+ struct blk_desc *block_dev = dev_get_uclass_plat(dev);
struct udevice *bdev = dev->parent;
- struct scsi_platdata *uc_plat = dev_get_uclass_platdata(bdev);
+ struct scsi_plat *uc_plat = dev_get_uclass_plat(bdev);
lbaint_t start, blks, max_blks;
uintptr_t buf_addr;
unsigned short smallblks;
return ret;
}
- bdesc = dev_get_uclass_platdata(bdev);
+ bdesc = dev_get_uclass_plat(bdev);
bdesc->target = id;
bdesc->lun = lun;
bdesc->removable = bd.removable;
int scsi_scan_dev(struct udevice *dev, bool verbose)
{
- struct scsi_platdata *uc_plat; /* scsi controller platdata */
+ struct scsi_plat *uc_plat; /* scsi controller plat */
int ret;
int i;
int lun;
if (ret)
return ret;
- /* Get controller platdata */
- uc_plat = dev_get_uclass_platdata(dev);
+ /* Get controller plat */
+ uc_plat = dev_get_uclass_plat(dev);
for (i = 0; i < uc_plat->max_id; i++)
for (lun = 0; lun < uc_plat->max_lun; lun++)
u32 control; /* Control register */
};
-struct altera_jtaguart_platdata {
+struct altera_jtaguart_plat {
struct altera_jtaguart_regs *regs;
};
static int altera_jtaguart_putc(struct udevice *dev, const char ch)
{
- struct altera_jtaguart_platdata *plat = dev->platdata;
+ struct altera_jtaguart_plat *plat = dev->plat;
struct altera_jtaguart_regs *const regs = plat->regs;
u32 st = readl(®s->control);
static int altera_jtaguart_pending(struct udevice *dev, bool input)
{
- struct altera_jtaguart_platdata *plat = dev->platdata;
+ struct altera_jtaguart_plat *plat = dev->plat;
struct altera_jtaguart_regs *const regs = plat->regs;
u32 st = readl(®s->control);
static int altera_jtaguart_getc(struct udevice *dev)
{
- struct altera_jtaguart_platdata *plat = dev->platdata;
+ struct altera_jtaguart_plat *plat = dev->plat;
struct altera_jtaguart_regs *const regs = plat->regs;
u32 val;
static int altera_jtaguart_probe(struct udevice *dev)
{
#ifdef CONFIG_ALTERA_JTAG_UART_BYPASS
- struct altera_jtaguart_platdata *plat = dev->platdata;
+ struct altera_jtaguart_plat *plat = dev->plat;
struct altera_jtaguart_regs *const regs = plat->regs;
writel(ALTERA_JTAG_AC, ®s->control); /* clear AC flag */
return 0;
}
-static int altera_jtaguart_ofdata_to_platdata(struct udevice *dev)
+static int altera_jtaguart_of_to_plat(struct udevice *dev)
{
- struct altera_jtaguart_platdata *plat = dev_get_platdata(dev);
+ struct altera_jtaguart_plat *plat = dev_get_plat(dev);
plat->regs = map_physmem(dev_read_addr(dev),
sizeof(struct altera_jtaguart_regs),
.name = "altera_jtaguart",
.id = UCLASS_SERIAL,
.of_match = altera_jtaguart_ids,
- .ofdata_to_platdata = altera_jtaguart_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct altera_jtaguart_platdata),
+ .of_to_plat = altera_jtaguart_of_to_plat,
+ .plat_auto = sizeof(struct altera_jtaguart_plat),
.probe = altera_jtaguart_probe,
.ops = &altera_jtaguart_ops,
};
u32 endofpacket; /* End-of-packet reg */
};
-struct altera_uart_platdata {
+struct altera_uart_plat {
struct altera_uart_regs *regs;
unsigned int uartclk;
};
static int altera_uart_setbrg(struct udevice *dev, int baudrate)
{
- struct altera_uart_platdata *plat = dev->platdata;
+ struct altera_uart_plat *plat = dev->plat;
struct altera_uart_regs *const regs = plat->regs;
u32 div;
static int altera_uart_putc(struct udevice *dev, const char ch)
{
- struct altera_uart_platdata *plat = dev->platdata;
+ struct altera_uart_plat *plat = dev->plat;
struct altera_uart_regs *const regs = plat->regs;
if (!(readl(®s->status) & ALTERA_UART_TRDY))
static int altera_uart_pending(struct udevice *dev, bool input)
{
- struct altera_uart_platdata *plat = dev->platdata;
+ struct altera_uart_plat *plat = dev->plat;
struct altera_uart_regs *const regs = plat->regs;
u32 st = readl(®s->status);
static int altera_uart_getc(struct udevice *dev)
{
- struct altera_uart_platdata *plat = dev->platdata;
+ struct altera_uart_plat *plat = dev->plat;
struct altera_uart_regs *const regs = plat->regs;
if (!(readl(®s->status) & ALTERA_UART_RRDY))
return 0;
}
-static int altera_uart_ofdata_to_platdata(struct udevice *dev)
+static int altera_uart_of_to_plat(struct udevice *dev)
{
- struct altera_uart_platdata *plat = dev_get_platdata(dev);
+ struct altera_uart_plat *plat = dev_get_plat(dev);
plat->regs = map_physmem(dev_read_addr(dev),
sizeof(struct altera_uart_regs),
.name = "altera_uart",
.id = UCLASS_SERIAL,
.of_match = altera_uart_ids,
- .ofdata_to_platdata = altera_uart_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct altera_uart_platdata),
+ .of_to_plat = altera_uart_of_to_plat,
+ .plat_auto = sizeof(struct altera_uart_plat),
.probe = altera_uart_probe,
.ops = &altera_uart_ops,
};
static int atmel_serial_probe(struct udevice *dev)
{
- struct atmel_serial_platdata *plat = dev->platdata;
+ struct atmel_serial_plat *plat = dev->plat;
struct atmel_serial_priv *priv = dev_get_priv(dev);
int ret;
#if CONFIG_IS_ENABLED(OF_CONTROL)
.id = UCLASS_SERIAL,
#if CONFIG_IS_ENABLED(OF_CONTROL)
.of_match = atmel_serial_ids,
- .platdata_auto_alloc_size = sizeof(struct atmel_serial_platdata),
+ .plat_auto = sizeof(struct atmel_serial_plat),
#endif
.probe = atmel_serial_probe,
.ops = &atmel_serial_ops,
#if !CONFIG_IS_ENABLED(OF_CONTROL)
.flags = DM_FLAG_PRE_RELOC,
#endif
- .priv_auto_alloc_size = sizeof(struct atmel_serial_priv),
+ .priv_auto = sizeof(struct atmel_serial_priv),
};
#endif
static int lpc32xx_hsuart_probe(struct udevice *dev)
{
- struct lpc32xx_hsuart_platdata *platdata = dev_get_platdata(dev);
+ struct lpc32xx_hsuart_plat *plat = dev_get_plat(dev);
struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev);
- priv->hsuart = (struct hsuart_regs *)platdata->base;
+ priv->hsuart = (struct hsuart_regs *)plat->base;
lpc32xx_serial_init(priv->hsuart);
.id = UCLASS_SERIAL,
.probe = lpc32xx_hsuart_probe,
.ops = &lpc32xx_hsuart_ops,
- .priv_auto_alloc_size = sizeof(struct lpc32xx_hsuart_priv),
+ .priv_auto = sizeof(struct lpc32xx_hsuart_priv),
.flags = DM_FLAG_PRE_RELOC,
};
* on a platform
*/
#ifdef CONFIG_NS16550_DYNAMIC
-static void serial_out_dynamic(struct ns16550_platdata *plat, u8 *addr,
+static void serial_out_dynamic(struct ns16550_plat *plat, u8 *addr,
int value)
{
if (plat->flags & NS16550_FLAG_IO) {
}
}
-static int serial_in_dynamic(struct ns16550_platdata *plat, u8 *addr)
+static int serial_in_dynamic(struct ns16550_plat *plat, u8 *addr)
{
if (plat->flags & NS16550_FLAG_IO) {
return inb(addr);
}
}
#else
-static inline void serial_out_dynamic(struct ns16550_platdata *plat, u8 *addr,
+static inline void serial_out_dynamic(struct ns16550_plat *plat, u8 *addr,
int value)
{
}
-static inline int serial_in_dynamic(struct ns16550_platdata *plat, u8 *addr)
+static inline int serial_in_dynamic(struct ns16550_plat *plat, u8 *addr)
{
return 0;
}
static void ns16550_writeb(NS16550_t port, int offset, int value)
{
- struct ns16550_platdata *plat = port->plat;
+ struct ns16550_plat *plat = port->plat;
unsigned char *addr;
offset *= 1 << plat->reg_shift;
static int ns16550_readb(NS16550_t port, int offset)
{
- struct ns16550_platdata *plat = port->plat;
+ struct ns16550_plat *plat = port->plat;
unsigned char *addr;
offset *= 1 << plat->reg_shift;
static u32 ns16550_getfcr(NS16550_t port)
{
- struct ns16550_platdata *plat = port->plat;
+ struct ns16550_plat *plat = port->plat;
return plat->fcr;
}
static int ns16550_serial_setbrg(struct udevice *dev, int baudrate)
{
struct NS16550 *const com_port = dev_get_priv(dev);
- struct ns16550_platdata *plat = com_port->plat;
+ struct ns16550_plat *plat = com_port->plat;
int clock_divisor;
clock_divisor = ns16550_calc_divisor(com_port, plat->clock, baudrate);
struct serial_device_info *info)
{
struct NS16550 *const com_port = dev_get_priv(dev);
- struct ns16550_platdata *plat = com_port->plat;
+ struct ns16550_plat *plat = com_port->plat;
info->type = SERIAL_CHIP_16550_COMPATIBLE;
#ifdef CONFIG_SYS_NS16550_PORT_MAPPED
return 0;
}
-static int ns16550_serial_assign_base(struct ns16550_platdata *plat, ulong base)
+static int ns16550_serial_assign_base(struct ns16550_plat *plat, ulong base)
{
if (base == FDT_ADDR_T_NONE)
return -EINVAL;
int ns16550_serial_probe(struct udevice *dev)
{
- struct ns16550_platdata *plat = dev->platdata;
+ struct ns16550_plat *plat = dev->plat;
struct NS16550 *const com_port = dev_get_priv(dev);
struct reset_ctl_bulk reset_bulk;
fdt_addr_t addr;
/*
* If we are on PCI bus, either directly attached to a PCI root port,
- * or via a PCI bridge, assign platdata->base before probing hardware.
+ * or via a PCI bridge, assign plat->base before probing hardware.
*/
if (device_is_on_pci_bus(dev)) {
addr = devfdt_get_addr_pci(dev);
if (!ret)
reset_deassert_bulk(&reset_bulk);
- com_port->plat = dev_get_platdata(dev);
+ com_port->plat = dev_get_plat(dev);
NS16550_init(com_port, -1);
return 0;
#endif
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
-int ns16550_serial_ofdata_to_platdata(struct udevice *dev)
+int ns16550_serial_of_to_plat(struct udevice *dev)
{
- struct ns16550_platdata *plat = dev->platdata;
+ struct ns16550_plat *plat = dev->plat;
const u32 port_type = dev_get_driver_data(dev);
fdt_addr_t addr;
struct clk clk;
.id = UCLASS_SERIAL,
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
.of_match = ns16550_serial_ids,
- .ofdata_to_platdata = ns16550_serial_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
+ .of_to_plat = ns16550_serial_of_to_plat,
+ .plat_auto = sizeof(struct ns16550_plat),
#endif
- .priv_auto_alloc_size = sizeof(struct NS16550),
+ .priv_auto = sizeof(struct NS16550),
.probe = ns16550_serial_probe,
.ops = &ns16550_serial_ops,
#if !CONFIG_IS_ENABLED(OF_CONTROL)
#include <common.h>
#include <console.h>
#include <dm.h>
-#include <fdtdec.h>
#include <lcd.h>
#include <os.h>
#include <serial.h>
DECLARE_GLOBAL_DATA_PTR;
-#if CONFIG_IS_ENABLED(OF_CONTROL)
-
-/*
- *
- * serial_buf: A buffer that holds keyboard characters for the
- * Sandbox U-Boot.
- *
- * invariants:
- * serial_buf_write == serial_buf_read -> empty buffer
- * (serial_buf_write + 1) % 16 == serial_buf_read -> full buffer
- */
-static unsigned char serial_buf[16];
-static unsigned int serial_buf_write;
-static unsigned int serial_buf_read;
-
-struct sandbox_serial_platdata {
+struct sandbox_serial_plat {
int colour; /* Text colour to use for output, -1 for none */
};
+/**
+ * struct sandbox_serial_priv - Private data for this driver
+ *
+ * @buf: holds input characters available to be read by this driver
+ */
struct sandbox_serial_priv {
+ struct membuff buf;
+ char serial_buf[16];
bool start_of_line;
};
if (state->term_raw != STATE_TERM_RAW)
disable_ctrlc(1);
+ membuff_init(&priv->buf, priv->serial_buf, sizeof(priv->serial_buf));
return 0;
}
static int sandbox_serial_remove(struct udevice *dev)
{
- struct sandbox_serial_platdata *plat = dev->platdata;
+ struct sandbox_serial_plat *plat = dev->plat;
if (plat->colour != -1)
output_ansi_reset();
static int sandbox_serial_putc(struct udevice *dev, const char ch)
{
struct sandbox_serial_priv *priv = dev_get_priv(dev);
- struct sandbox_serial_platdata *plat = dev->platdata;
+ struct sandbox_serial_plat *plat = dev->plat;
/* With of-platdata we don't real the colour correctly, so disable it */
if (!CONFIG_IS_ENABLED(OF_PLATDATA) && priv->start_of_line &&
return 0;
}
-static unsigned int increment_buffer_index(unsigned int index)
-{
- return (index + 1) % ARRAY_SIZE(serial_buf);
-}
-
static int sandbox_serial_pending(struct udevice *dev, bool input)
{
- const unsigned int next_index =
- increment_buffer_index(serial_buf_write);
+ struct sandbox_serial_priv *priv = dev_get_priv(dev);
ssize_t count;
+ char *data;
+ int avail;
if (!input)
return 0;
os_usleep(100);
-#ifndef CONFIG_SPL_BUILD
- video_sync_all();
-#endif
- if (next_index == serial_buf_read)
+ if (!IS_ENABLED(CONFIG_SPL_BUILD))
+ video_sync_all();
+ avail = membuff_putraw(&priv->buf, 100, false, &data);
+ if (!avail)
return 1; /* buffer full */
- count = os_read(0, &serial_buf[serial_buf_write], 1);
- if (count == 1)
- serial_buf_write = next_index;
+ count = os_read(0, data, avail);
+ if (count > 0)
+ membuff_putraw(&priv->buf, count, true, &data);
- return serial_buf_write != serial_buf_read;
+ return membuff_avail(&priv->buf);
}
static int sandbox_serial_getc(struct udevice *dev)
{
- int result;
+ struct sandbox_serial_priv *priv = dev_get_priv(dev);
if (!sandbox_serial_pending(dev, true))
return -EAGAIN; /* buffer empty */
- result = serial_buf[serial_buf_read];
- serial_buf_read = increment_buffer_index(serial_buf_read);
- return result;
+ return membuff_getbyte(&priv->buf);
}
-#endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
#ifdef CONFIG_DEBUG_UART_SANDBOX
return 0;
}
-#if CONFIG_IS_ENABLED(OF_CONTROL)
static const char * const ansi_colour[] = {
"black", "red", "green", "yellow", "blue", "megenta", "cyan",
"white",
};
-static int sandbox_serial_ofdata_to_platdata(struct udevice *dev)
+static int sandbox_serial_of_to_plat(struct udevice *dev)
{
- struct sandbox_serial_platdata *plat = dev->platdata;
+ struct sandbox_serial_plat *plat = dev->plat;
const char *colour;
int i;
if (CONFIG_IS_ENABLED(OF_PLATDATA))
return 0;
plat->colour = -1;
- colour = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
- "sandbox,text-colour", NULL);
+ colour = dev_read_string(dev, "sandbox,text-colour");
if (colour) {
for (i = 0; i < ARRAY_SIZE(ansi_colour); i++) {
if (!strcmp(colour, ansi_colour[i])) {
.name = "sandbox_serial",
.id = UCLASS_SERIAL,
.of_match = sandbox_serial_ids,
- .ofdata_to_platdata = sandbox_serial_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct sandbox_serial_platdata),
- .priv_auto_alloc_size = sizeof(struct sandbox_serial_priv),
+ .of_to_plat = sandbox_serial_of_to_plat,
+ .plat_auto = sizeof(struct sandbox_serial_plat),
+ .priv_auto = sizeof(struct sandbox_serial_priv),
.probe = sandbox_serial_probe,
.remove = sandbox_serial_remove,
.ops = &sandbox_serial_ops,
};
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
-static const struct sandbox_serial_platdata platdata_non_fdt = {
+static const struct sandbox_serial_plat platdata_non_fdt = {
.colour = -1,
};
U_BOOT_DEVICE(serial_sandbox_non_fdt) = {
.name = "sandbox_serial",
- .platdata = &platdata_non_fdt,
+ .plat = &platdata_non_fdt,
};
#endif
-
-#endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
.flags = DM_UC_FLAG_SEQ_ALIAS,
.post_probe = serial_post_probe,
.pre_remove = serial_pre_remove,
- .per_device_auto_alloc_size = sizeof(struct serial_dev_priv),
+ .per_device_auto = sizeof(struct serial_dev_priv),
};
#endif
.name = "serial_ar933x",
.id = UCLASS_SERIAL,
.of_match = ar933x_serial_ids,
- .priv_auto_alloc_size = sizeof(struct ar933x_serial_priv),
+ .priv_auto = sizeof(struct ar933x_serial_priv),
.probe = ar933x_serial_probe,
.ops = &ar933x_serial_ops,
};
};
-struct arc_serial_platdata {
+struct arc_serial_plat {
struct arc_serial_regs *reg;
unsigned int uartclk;
};
static int arc_serial_setbrg(struct udevice *dev, int baudrate)
{
- struct arc_serial_platdata *plat = dev->platdata;
+ struct arc_serial_plat *plat = dev->plat;
struct arc_serial_regs *const regs = plat->reg;
int arc_console_baud = gd->cpu_clk / (baudrate * 4) - 1;
static int arc_serial_putc(struct udevice *dev, const char c)
{
- struct arc_serial_platdata *plat = dev->platdata;
+ struct arc_serial_plat *plat = dev->plat;
struct arc_serial_regs *const regs = plat->reg;
while (!(readb(®s->status) & UART_TXEMPTY))
static int arc_serial_pending(struct udevice *dev, bool input)
{
- struct arc_serial_platdata *plat = dev->platdata;
+ struct arc_serial_plat *plat = dev->plat;
struct arc_serial_regs *const regs = plat->reg;
uint32_t status = readb(®s->status);
static int arc_serial_getc(struct udevice *dev)
{
- struct arc_serial_platdata *plat = dev->platdata;
+ struct arc_serial_plat *plat = dev->plat;
struct arc_serial_regs *const regs = plat->reg;
while (!arc_serial_tstc(regs))
{ }
};
-static int arc_serial_ofdata_to_platdata(struct udevice *dev)
+static int arc_serial_of_to_plat(struct udevice *dev)
{
- struct arc_serial_platdata *plat = dev_get_platdata(dev);
+ struct arc_serial_plat *plat = dev_get_plat(dev);
DECLARE_GLOBAL_DATA_PTR;
plat->reg = dev_read_addr_ptr(dev);
.name = "serial_arc",
.id = UCLASS_SERIAL,
.of_match = arc_serial_ids,
- .ofdata_to_platdata = arc_serial_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct arc_serial_platdata),
+ .of_to_plat = arc_serial_of_to_plat,
+ .plat_auto = sizeof(struct arc_serial_plat),
.probe = arc_serial_probe,
.ops = &arc_serial_ops,
};
static int bcm283x_mu_serial_setbrg(struct udevice *dev, int baudrate)
{
- struct bcm283x_mu_serial_platdata *plat = dev_get_platdata(dev);
+ struct bcm283x_mu_serial_plat *plat = dev_get_plat(dev);
struct bcm283x_mu_priv *priv = dev_get_priv(dev);
struct bcm283x_mu_regs *regs = priv->regs;
u32 divider;
static int bcm283x_mu_serial_probe(struct udevice *dev)
{
- struct bcm283x_mu_serial_platdata *plat = dev_get_platdata(dev);
+ struct bcm283x_mu_serial_plat *plat = dev_get_plat(dev);
struct bcm283x_mu_priv *priv = dev_get_priv(dev);
fdt_addr_t addr;
return -ENODEV;
/*
- * Read the ofdata here rather than in an ofdata_to_platdata() method
+ * Read the ofdata here rather than in an of_to_plat() method
* since we need the soc simple-bus to be probed so that the 'ranges'
* property is used.
*/
.name = "serial_bcm283x_mu",
.id = UCLASS_SERIAL,
.of_match = of_match_ptr(bcm283x_mu_serial_id),
- .platdata_auto_alloc_size = sizeof(struct bcm283x_mu_serial_platdata),
+ .plat_auto = sizeof(struct bcm283x_mu_serial_plat),
.probe = bcm283x_mu_serial_probe,
.ops = &bcm283x_mu_serial_ops,
#if !CONFIG_IS_ENABLED(OF_CONTROL) || CONFIG_IS_ENABLED(OF_BOARD)
.flags = DM_FLAG_PRE_RELOC,
#endif
- .priv_auto_alloc_size = sizeof(struct bcm283x_mu_priv),
+ .priv_auto = sizeof(struct bcm283x_mu_priv),
};
static int bcm283x_pl011_serial_probe(struct udevice *dev)
{
- struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
+ struct pl01x_serial_plat *plat = dev_get_plat(dev);
int ret;
/* Don't spawn the device if it's not muxed */
return -ENODEV;
/*
- * Read the ofdata here rather than in an ofdata_to_platdata() method
+ * Read the ofdata here rather than in an of_to_plat() method
* since we need the soc simple-bus to be probed so that the 'ranges'
* property is used.
*/
- ret = pl01x_serial_ofdata_to_platdata(dev);
+ ret = pl01x_serial_of_to_plat(dev);
if (ret)
return ret;
.id = UCLASS_SERIAL,
.of_match = of_match_ptr(bcm283x_pl011_serial_id),
.probe = bcm283x_pl011_serial_probe,
- .platdata_auto_alloc_size = sizeof(struct pl01x_serial_platdata),
+ .plat_auto = sizeof(struct pl01x_serial_plat),
.ops = &bcm283x_pl011_serial_ops,
#if !CONFIG_IS_ENABLED(OF_CONTROL) || CONFIG_IS_ENABLED(OF_BOARD)
.flags = DM_FLAG_PRE_RELOC,
#endif
- .priv_auto_alloc_size = sizeof(struct pl01x_priv),
+ .priv_auto = sizeof(struct pl01x_priv),
};
.id = UCLASS_SERIAL,
.of_match = bcm6345_serial_ids,
.probe = bcm6345_serial_probe,
- .priv_auto_alloc_size = sizeof(struct bcm6345_serial_priv),
+ .priv_auto = sizeof(struct bcm6345_serial_priv),
.ops = &bcm6345_serial_ops,
};
#include <serial.h>
#include <asm/arch/sysinfo.h>
-static int coreboot_ofdata_to_platdata(struct udevice *dev)
+static int coreboot_of_to_plat(struct udevice *dev)
{
- struct ns16550_platdata *plat = dev_get_platdata(dev);
+ struct ns16550_plat *plat = dev_get_plat(dev);
struct cb_serial *cb_info = lib_sysinfo.serial;
plat->base = cb_info->baseaddr;
.name = "coreboot_uart",
.id = UCLASS_SERIAL,
.of_match = coreboot_serial_ids,
- .priv_auto_alloc_size = sizeof(struct NS16550),
- .platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
- .ofdata_to_platdata = coreboot_ofdata_to_platdata,
+ .priv_auto = sizeof(struct NS16550),
+ .plat_auto = sizeof(struct ns16550_plat),
+ .of_to_plat = coreboot_of_to_plat,
.probe = ns16550_serial_probe,
.ops = &ns16550_serial_ops,
.flags = DM_FLAG_PRE_RELOC,
return 0;
}
-static int ca_serial_ofdata_to_platdata(struct udevice *dev)
+static int ca_serial_of_to_plat(struct udevice *dev)
{
struct ca_uart_priv *priv = dev_get_priv(dev);
.name = "serial_cortina",
.id = UCLASS_SERIAL,
.of_match = ca_serial_ids,
- .ofdata_to_platdata = ca_serial_ofdata_to_platdata,
- .priv_auto_alloc_size = sizeof(struct ca_uart_priv),
+ .of_to_plat = ca_serial_of_to_plat,
+ .priv_auto = sizeof(struct ca_uart_priv),
.probe = ca_serial_probe,
.ops = &ca_serial_ops
};
.name = "serial_efi",
.id = UCLASS_SERIAL,
.of_match = serial_efi_ids,
- .priv_auto_alloc_size = sizeof(struct serial_efi_priv),
+ .priv_auto = sizeof(struct serial_efi_priv),
.probe = serial_efi_probe,
.ops = &serial_efi_ops,
};
#define UART_MUL 0x34
#define UART_DIV 0x38
-static void mid_writel(struct ns16550_platdata *plat, int offset, int value)
+static void mid_writel(struct ns16550_plat *plat, int offset, int value)
{
unsigned char *addr;
static int mid_serial_probe(struct udevice *dev)
{
- struct ns16550_platdata *plat = dev_get_platdata(dev);
+ struct ns16550_plat *plat = dev_get_plat(dev);
/*
* Initialize fractional divider correctly for Intel Edison
.name = "serial_intel_mid",
.id = UCLASS_SERIAL,
.of_match = mid_serial_ids,
- .ofdata_to_platdata = ns16550_serial_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
- .priv_auto_alloc_size = sizeof(struct NS16550),
+ .of_to_plat = ns16550_serial_of_to_plat,
+ .plat_auto = sizeof(struct ns16550_plat),
+ .priv_auto = sizeof(struct NS16550),
.probe = mid_serial_probe,
.ops = &ns16550_serial_ops,
};
return 0;
}
-struct linflex_serial_platdata {
+struct linflex_serial_plat {
struct linflex_fsl *base_addr;
u8 port_id; /* do we need this? */
};
static int linflex_serial_probe(struct udevice *dev)
{
- struct linflex_serial_platdata *plat = dev->platdata;
+ struct linflex_serial_plat *plat = dev->plat;
struct linflex_serial_priv *priv = dev_get_priv(dev);
priv->lfuart = (struct linflex_fsl *)plat->base_addr;
.probe = linflex_serial_probe,
.ops = &linflex_serial_ops,
.flags = DM_FLAG_PRE_RELOC,
- .priv_auto_alloc_size = sizeof(struct linflex_serial_priv),
+ .priv_auto = sizeof(struct linflex_serial_priv),
};
#ifdef CONFIG_DEBUG_UART_LINFLEXUART
DEV_IMXRT,
};
-struct lpuart_serial_platdata {
+struct lpuart_serial_plat {
void *reg;
enum lpuart_devtype devtype;
ulong flags;
static bool is_lpuart32(struct udevice *dev)
{
- struct lpuart_serial_platdata *plat = dev->platdata;
+ struct lpuart_serial_plat *plat = dev->plat;
return plat->flags & LPUART_FLAG_REGMAP_32BIT_REG;
}
static void _lpuart_serial_setbrg(struct udevice *dev,
int baudrate)
{
- struct lpuart_serial_platdata *plat = dev_get_platdata(dev);
+ struct lpuart_serial_plat *plat = dev_get_plat(dev);
struct lpuart_fsl *base = plat->reg;
u32 clk;
u16 sbr;
__raw_writeb(sbr & 0xff, &base->ubdl);
}
-static int _lpuart_serial_getc(struct lpuart_serial_platdata *plat)
+static int _lpuart_serial_getc(struct lpuart_serial_plat *plat)
{
struct lpuart_fsl *base = plat->reg;
while (!(__raw_readb(&base->us1) & (US1_RDRF | US1_OR)))
return __raw_readb(&base->ud);
}
-static void _lpuart_serial_putc(struct lpuart_serial_platdata *plat,
+static void _lpuart_serial_putc(struct lpuart_serial_plat *plat,
const char c)
{
struct lpuart_fsl *base = plat->reg;
}
/* Test whether a character is in the RX buffer */
-static int _lpuart_serial_tstc(struct lpuart_serial_platdata *plat)
+static int _lpuart_serial_tstc(struct lpuart_serial_plat *plat)
{
struct lpuart_fsl *base = plat->reg;
*/
static int _lpuart_serial_init(struct udevice *dev)
{
- struct lpuart_serial_platdata *plat = dev_get_platdata(dev);
+ struct lpuart_serial_plat *plat = dev_get_plat(dev);
struct lpuart_fsl *base = (struct lpuart_fsl *)plat->reg;
u8 ctrl;
static void _lpuart32_serial_setbrg_7ulp(struct udevice *dev,
int baudrate)
{
- struct lpuart_serial_platdata *plat = dev_get_platdata(dev);
+ struct lpuart_serial_plat *plat = dev_get_plat(dev);
struct lpuart_fsl_reg32 *base = plat->reg;
u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp;
u32 clk;
static void _lpuart32_serial_setbrg(struct udevice *dev,
int baudrate)
{
- struct lpuart_serial_platdata *plat = dev_get_platdata(dev);
+ struct lpuart_serial_plat *plat = dev_get_plat(dev);
struct lpuart_fsl_reg32 *base = plat->reg;
u32 clk;
u32 sbr;
lpuart_write32(plat->flags, &base->baud, sbr);
}
-static int _lpuart32_serial_getc(struct lpuart_serial_platdata *plat)
+static int _lpuart32_serial_getc(struct lpuart_serial_plat *plat)
{
struct lpuart_fsl_reg32 *base = plat->reg;
u32 stat, val;
return val & 0x3ff;
}
-static void _lpuart32_serial_putc(struct lpuart_serial_platdata *plat,
+static void _lpuart32_serial_putc(struct lpuart_serial_plat *plat,
const char c)
{
struct lpuart_fsl_reg32 *base = plat->reg;
}
/* Test whether a character is in the RX buffer */
-static int _lpuart32_serial_tstc(struct lpuart_serial_platdata *plat)
+static int _lpuart32_serial_tstc(struct lpuart_serial_plat *plat)
{
struct lpuart_fsl_reg32 *base = plat->reg;
u32 water;
*/
static int _lpuart32_serial_init(struct udevice *dev)
{
- struct lpuart_serial_platdata *plat = dev_get_platdata(dev);
+ struct lpuart_serial_plat *plat = dev_get_plat(dev);
struct lpuart_fsl_reg32 *base = (struct lpuart_fsl_reg32 *)plat->reg;
u32 val, tx_fifo_size;
static int lpuart_serial_setbrg(struct udevice *dev, int baudrate)
{
- struct lpuart_serial_platdata *plat = dev_get_platdata(dev);
+ struct lpuart_serial_plat *plat = dev_get_plat(dev);
if (is_lpuart32(dev)) {
if (plat->devtype == DEV_MX7ULP || plat->devtype == DEV_IMX8 ||
static int lpuart_serial_getc(struct udevice *dev)
{
- struct lpuart_serial_platdata *plat = dev->platdata;
+ struct lpuart_serial_plat *plat = dev->plat;
if (is_lpuart32(dev))
return _lpuart32_serial_getc(plat);
static int lpuart_serial_putc(struct udevice *dev, const char c)
{
- struct lpuart_serial_platdata *plat = dev->platdata;
+ struct lpuart_serial_plat *plat = dev->plat;
if (is_lpuart32(dev))
_lpuart32_serial_putc(plat, c);
static int lpuart_serial_pending(struct udevice *dev, bool input)
{
- struct lpuart_serial_platdata *plat = dev->platdata;
+ struct lpuart_serial_plat *plat = dev->plat;
struct lpuart_fsl *reg = plat->reg;
struct lpuart_fsl_reg32 *reg32 = plat->reg;
u32 stat;
return _lpuart_serial_init(dev);
}
-static int lpuart_serial_ofdata_to_platdata(struct udevice *dev)
+static int lpuart_serial_of_to_plat(struct udevice *dev)
{
- struct lpuart_serial_platdata *plat = dev->platdata;
+ struct lpuart_serial_plat *plat = dev->plat;
const void *blob = gd->fdt_blob;
int node = dev_of_offset(dev);
fdt_addr_t addr;
.name = "serial_lpuart",
.id = UCLASS_SERIAL,
.of_match = lpuart_serial_ids,
- .ofdata_to_platdata = lpuart_serial_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct lpuart_serial_platdata),
+ .of_to_plat = lpuart_serial_of_to_plat,
+ .plat_auto = sizeof(struct lpuart_serial_plat),
.probe = lpuart_serial_probe,
.ops = &lpuart_serial_ops,
};
static int coldfire_serial_probe(struct udevice *dev)
{
- struct coldfire_serial_platdata *plat = dev->platdata;
+ struct coldfire_serial_plat *plat = dev->plat;
plat->port = dev->seq;
static int coldfire_serial_putc(struct udevice *dev, const char ch)
{
- struct coldfire_serial_platdata *plat = dev->platdata;
+ struct coldfire_serial_plat *plat = dev->plat;
uart_t *uart = (uart_t *)plat->base;
/* Wait for last character to go. */
static int coldfire_serial_getc(struct udevice *dev)
{
- struct coldfire_serial_platdata *plat = dev->platdata;
+ struct coldfire_serial_plat *plat = dev->plat;
uart_t *uart = (uart_t *)(plat->base);
/* Wait for a character to arrive. */
int coldfire_serial_setbrg(struct udevice *dev, int baudrate)
{
- struct coldfire_serial_platdata *plat = dev->platdata;
+ struct coldfire_serial_plat *plat = dev->plat;
uart_t *uart = (uart_t *)(plat->base);
mcf_serial_setbrg_common(uart, baudrate);
static int coldfire_serial_pending(struct udevice *dev, bool input)
{
- struct coldfire_serial_platdata *plat = dev->platdata;
+ struct coldfire_serial_plat *plat = dev->plat;
uart_t *uart = (uart_t *)(plat->base);
if (input)
return 0;
}
-static int coldfire_ofdata_to_platdata(struct udevice *dev)
+static int coldfire_of_to_plat(struct udevice *dev)
{
- struct coldfire_serial_platdata *plat = dev_get_platdata(dev);
+ struct coldfire_serial_plat *plat = dev_get_plat(dev);
fdt_addr_t addr_base;
addr_base = dev_read_addr(dev);
.name = "serial_coldfire",
.id = UCLASS_SERIAL,
.of_match = coldfire_serial_ids,
- .ofdata_to_platdata = coldfire_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct coldfire_serial_platdata),
+ .of_to_plat = coldfire_of_to_plat,
+ .plat_auto = sizeof(struct coldfire_serial_plat),
.probe = coldfire_serial_probe,
.ops = &coldfire_serial_ops,
.flags = DM_FLAG_PRE_RELOC,
u32 misc;
};
-struct meson_serial_platdata {
+struct meson_serial_plat {
struct meson_uart *reg;
};
static int meson_serial_probe(struct udevice *dev)
{
- struct meson_serial_platdata *plat = dev->platdata;
+ struct meson_serial_plat *plat = dev->plat;
struct meson_uart *const uart = plat->reg;
meson_serial_init(uart);
static void meson_serial_rx_error(struct udevice *dev)
{
- struct meson_serial_platdata *plat = dev->platdata;
+ struct meson_serial_plat *plat = dev->plat;
struct meson_uart *const uart = plat->reg;
u32 val = readl(&uart->control);
static int meson_serial_getc(struct udevice *dev)
{
- struct meson_serial_platdata *plat = dev->platdata;
+ struct meson_serial_plat *plat = dev->plat;
struct meson_uart *const uart = plat->reg;
uint32_t status = readl(&uart->status);
static int meson_serial_putc(struct udevice *dev, const char ch)
{
- struct meson_serial_platdata *plat = dev->platdata;
+ struct meson_serial_plat *plat = dev->plat;
struct meson_uart *const uart = plat->reg;
if (readl(&uart->status) & AML_UART_TX_FULL)
static int meson_serial_pending(struct udevice *dev, bool input)
{
- struct meson_serial_platdata *plat = dev->platdata;
+ struct meson_serial_plat *plat = dev->plat;
struct meson_uart *const uart = plat->reg;
uint32_t status = readl(&uart->status);
}
}
-static int meson_serial_ofdata_to_platdata(struct udevice *dev)
+static int meson_serial_of_to_plat(struct udevice *dev)
{
- struct meson_serial_platdata *plat = dev->platdata;
+ struct meson_serial_plat *plat = dev->plat;
fdt_addr_t addr;
addr = dev_read_addr(dev);
.of_match = meson_serial_ids,
.probe = meson_serial_probe,
.ops = &meson_serial_ops,
- .ofdata_to_platdata = meson_serial_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct meson_serial_platdata),
+ .of_to_plat = meson_serial_of_to_plat,
+ .plat_auto = sizeof(struct meson_serial_plat),
};
#ifdef CONFIG_DEBUG_UART_MESON
return 0;
}
-static int msm_serial_ofdata_to_platdata(struct udevice *dev)
+static int msm_serial_of_to_plat(struct udevice *dev)
{
struct msm_serial_data *priv = dev_get_priv(dev);
.name = "serial_msm",
.id = UCLASS_SERIAL,
.of_match = msm_serial_ids,
- .ofdata_to_platdata = msm_serial_ofdata_to_platdata,
- .priv_auto_alloc_size = sizeof(struct msm_serial_data),
+ .of_to_plat = msm_serial_of_to_plat,
+ .priv_auto = sizeof(struct msm_serial_data),
.probe = msm_serial_probe,
.ops = &msm_serial_ops,
};
return 0;
}
-static int mtk_serial_ofdata_to_platdata(struct udevice *dev)
+static int mtk_serial_of_to_plat(struct udevice *dev)
{
struct mtk_serial_priv *priv = dev_get_priv(dev);
fdt_addr_t addr;
.name = "serial_mtk",
.id = UCLASS_SERIAL,
.of_match = mtk_serial_ids,
- .ofdata_to_platdata = mtk_serial_ofdata_to_platdata,
- .priv_auto_alloc_size = sizeof(struct mtk_serial_priv),
+ .of_to_plat = mtk_serial_of_to_plat,
+ .priv_auto = sizeof(struct mtk_serial_priv),
.probe = mtk_serial_probe,
.ops = &mtk_serial_ops,
.flags = DM_FLAG_PRE_RELOC,
#include <serial.h>
#include <asm/io.h>
-struct mvebu_platdata {
+struct mvebu_plat {
void __iomem *base;
};
static int mvebu_serial_putc(struct udevice *dev, const char ch)
{
- struct mvebu_platdata *plat = dev_get_platdata(dev);
+ struct mvebu_plat *plat = dev_get_plat(dev);
void __iomem *base = plat->base;
while (readl(base + UART_STATUS_REG) & UART_STATUS_TXFIFO_FULL)
static int mvebu_serial_getc(struct udevice *dev)
{
- struct mvebu_platdata *plat = dev_get_platdata(dev);
+ struct mvebu_plat *plat = dev_get_plat(dev);
void __iomem *base = plat->base;
while (!(readl(base + UART_STATUS_REG) & UART_STATUS_RX_RDY))
static int mvebu_serial_pending(struct udevice *dev, bool input)
{
- struct mvebu_platdata *plat = dev_get_platdata(dev);
+ struct mvebu_plat *plat = dev_get_plat(dev);
void __iomem *base = plat->base;
if (readl(base + UART_STATUS_REG) & UART_STATUS_RX_RDY)
static int mvebu_serial_setbrg(struct udevice *dev, int baudrate)
{
- struct mvebu_platdata *plat = dev_get_platdata(dev);
+ struct mvebu_plat *plat = dev_get_plat(dev);
void __iomem *base = plat->base;
/*
static int mvebu_serial_probe(struct udevice *dev)
{
- struct mvebu_platdata *plat = dev_get_platdata(dev);
+ struct mvebu_plat *plat = dev_get_plat(dev);
void __iomem *base = plat->base;
/* reset FIFOs */
return 0;
}
-static int mvebu_serial_ofdata_to_platdata(struct udevice *dev)
+static int mvebu_serial_of_to_plat(struct udevice *dev)
{
- struct mvebu_platdata *plat = dev_get_platdata(dev);
+ struct mvebu_plat *plat = dev_get_plat(dev);
plat->base = dev_read_addr_ptr(dev);
.name = "serial_mvebu",
.id = UCLASS_SERIAL,
.of_match = mvebu_serial_ids,
- .ofdata_to_platdata = mvebu_serial_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct mvebu_platdata),
+ .of_to_plat = mvebu_serial_of_to_plat,
+ .plat_auto = sizeof(struct mvebu_plat),
.probe = mvebu_serial_probe,
.ops = &mvebu_serial_ops,
};
int mxc_serial_setbrg(struct udevice *dev, int baudrate)
{
- struct mxc_serial_platdata *plat = dev->platdata;
+ struct mxc_serial_plat *plat = dev->plat;
u32 clk = imx_get_uartclk();
_mxc_serial_setbrg(plat->reg, clk, baudrate, plat->use_dte);
static int mxc_serial_probe(struct udevice *dev)
{
- struct mxc_serial_platdata *plat = dev->platdata;
+ struct mxc_serial_plat *plat = dev->plat;
_mxc_serial_init(plat->reg, plat->use_dte);
static int mxc_serial_getc(struct udevice *dev)
{
- struct mxc_serial_platdata *plat = dev->platdata;
+ struct mxc_serial_plat *plat = dev->plat;
struct mxc_uart *const uart = plat->reg;
if (readl(&uart->ts) & UTS_RXEMPTY)
static int mxc_serial_putc(struct udevice *dev, const char ch)
{
- struct mxc_serial_platdata *plat = dev->platdata;
+ struct mxc_serial_plat *plat = dev->plat;
struct mxc_uart *const uart = plat->reg;
if (!(readl(&uart->ts) & UTS_TXEMPTY))
static int mxc_serial_pending(struct udevice *dev, bool input)
{
- struct mxc_serial_platdata *plat = dev->platdata;
+ struct mxc_serial_plat *plat = dev->plat;
struct mxc_uart *const uart = plat->reg;
uint32_t sr2 = readl(&uart->sr2);
};
#if CONFIG_IS_ENABLED(OF_CONTROL)
-static int mxc_serial_ofdata_to_platdata(struct udevice *dev)
+static int mxc_serial_of_to_plat(struct udevice *dev)
{
- struct mxc_serial_platdata *plat = dev->platdata;
+ struct mxc_serial_plat *plat = dev->plat;
fdt_addr_t addr;
addr = dev_read_addr(dev);
.id = UCLASS_SERIAL,
#if CONFIG_IS_ENABLED(OF_CONTROL)
.of_match = mxc_serial_ids,
- .ofdata_to_platdata = mxc_serial_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct mxc_serial_platdata),
+ .of_to_plat = mxc_serial_of_to_plat,
+ .plat_auto = sizeof(struct mxc_serial_plat),
#endif
.probe = mxc_serial_probe,
.ops = &mxc_serial_ops,
#if CONFIG_IS_ENABLED(DM_SERIAL)
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
-static int omap_serial_ofdata_to_platdata(struct udevice *dev)
+static int omap_serial_of_to_plat(struct udevice *dev)
{
- struct ns16550_platdata *plat = dev->platdata;
+ struct ns16550_plat *plat = dev->plat;
fdt_addr_t addr;
struct clk clk;
int err;
.id = UCLASS_SERIAL,
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
.of_match = omap_serial_ids,
- .ofdata_to_platdata = omap_serial_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
+ .of_to_plat = omap_serial_of_to_plat,
+ .plat_auto = sizeof(struct ns16550_plat),
#endif
- .priv_auto_alloc_size = sizeof(struct NS16550),
+ .priv_auto = sizeof(struct NS16550),
.probe = ns16550_serial_probe,
.ops = &ns16550_serial_ops,
#if !CONFIG_IS_ENABLED(OF_CONTROL)
return 0;
}
-static int owl_serial_ofdata_to_platdata(struct udevice *dev)
+static int owl_serial_of_to_plat(struct udevice *dev)
{
struct owl_serial_priv *priv = dev_get_priv(dev);
.name = "serial_owl",
.id = UCLASS_SERIAL,
.of_match = owl_serial_ids,
- .ofdata_to_platdata = owl_serial_ofdata_to_platdata,
- .priv_auto_alloc_size = sizeof(struct owl_serial_priv),
+ .of_to_plat = owl_serial_of_to_plat,
+ .priv_auto = sizeof(struct owl_serial_priv),
.probe = owl_serial_probe,
.ops = &owl_serial_ops,
};
.of_match = pic32_uart_ids,
.probe = pic32_uart_probe,
.ops = &pic32_uart_ops,
- .priv_auto_alloc_size = sizeof(struct pic32_uart_priv),
+ .priv_auto = sizeof(struct pic32_uart_priv),
};
#ifdef CONFIG_DEBUG_UART_PIC32
int pl01x_serial_setbrg(struct udevice *dev, int baudrate)
{
- struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
+ struct pl01x_serial_plat *plat = dev_get_plat(dev);
struct pl01x_priv *priv = dev_get_priv(dev);
if (!plat->skip_init) {
int pl01x_serial_probe(struct udevice *dev)
{
- struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
+ struct pl01x_serial_plat *plat = dev_get_plat(dev);
struct pl01x_priv *priv = dev_get_priv(dev);
priv->regs = (struct pl01x_regs *)plat->base;
#define CONFIG_PL011_CLOCK 0
#endif
-int pl01x_serial_ofdata_to_platdata(struct udevice *dev)
+int pl01x_serial_of_to_plat(struct udevice *dev)
{
- struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
+ struct pl01x_serial_plat *plat = dev_get_plat(dev);
struct clk clk;
fdt_addr_t addr;
int ret;
.name = "serial_pl01x",
.id = UCLASS_SERIAL,
.of_match = of_match_ptr(pl01x_serial_id),
- .ofdata_to_platdata = of_match_ptr(pl01x_serial_ofdata_to_platdata),
- .platdata_auto_alloc_size = sizeof(struct pl01x_serial_platdata),
+ .of_to_plat = of_match_ptr(pl01x_serial_of_to_plat),
+ .plat_auto = sizeof(struct pl01x_serial_plat),
.probe = pl01x_serial_probe,
.ops = &pl01x_serial_ops,
.flags = DM_FLAG_PRE_RELOC,
- .priv_auto_alloc_size = sizeof(struct pl01x_priv),
+ .priv_auto = sizeof(struct pl01x_priv),
};
#endif
#ifdef CONFIG_DM_SERIAL
-int pl01x_serial_ofdata_to_platdata(struct udevice *dev);
+int pl01x_serial_of_to_plat(struct udevice *dev);
int pl01x_serial_probe(struct udevice *dev);
/* Needed for external pl01x_serial_ops drivers */
#ifdef CONFIG_DM_SERIAL
static int pxa_serial_probe(struct udevice *dev)
{
- struct pxa_serial_platdata *plat = dev->platdata;
+ struct pxa_serial_plat *plat = dev->plat;
pxa_setbrg_common((struct pxa_uart_regs *)plat->base, plat->port,
plat->baudrate);
static int pxa_serial_putc(struct udevice *dev, const char ch)
{
- struct pxa_serial_platdata *plat = dev->platdata;
+ struct pxa_serial_plat *plat = dev->plat;
struct pxa_uart_regs *uart_regs = (struct pxa_uart_regs *)plat->base;
/* Wait for last character to go. */
static int pxa_serial_getc(struct udevice *dev)
{
- struct pxa_serial_platdata *plat = dev->platdata;
+ struct pxa_serial_plat *plat = dev->plat;
struct pxa_uart_regs *uart_regs = (struct pxa_uart_regs *)plat->base;
/* Wait for a character to arrive. */
int pxa_serial_setbrg(struct udevice *dev, int baudrate)
{
- struct pxa_serial_platdata *plat = dev->platdata;
+ struct pxa_serial_plat *plat = dev->plat;
struct pxa_uart_regs *uart_regs = (struct pxa_uart_regs *)plat->base;
int port = plat->port;
static int pxa_serial_pending(struct udevice *dev, bool input)
{
- struct pxa_serial_platdata *plat = dev->platdata;
+ struct pxa_serial_plat *plat = dev->plat;
struct pxa_uart_regs *uart_regs = (struct pxa_uart_regs *)plat->base;
if (input)
#include <asm/arch-rockchip/clock.h>
#if defined(CONFIG_ROCKCHIP_RK3188)
-struct rockchip_uart_platdata {
+struct rockchip_uart_plat {
struct dtd_rockchip_rk3188_uart dtplat;
- struct ns16550_platdata plat;
+ struct ns16550_plat plat;
};
struct dtd_rockchip_rk3188_uart *dtplat, s_dtplat;
#elif defined(CONFIG_ROCKCHIP_RK3288)
-struct rockchip_uart_platdata {
+struct rockchip_uart_plat {
struct dtd_rockchip_rk3288_uart dtplat;
- struct ns16550_platdata plat;
+ struct ns16550_plat plat;
};
struct dtd_rockchip_rk3288_uart *dtplat, s_dtplat;
#endif
static int rockchip_serial_probe(struct udevice *dev)
{
- struct rockchip_uart_platdata *plat = dev_get_platdata(dev);
+ struct rockchip_uart_plat *plat = dev_get_plat(dev);
/* Create some new platform data for the standard driver */
plat->plat.base = plat->dtplat.reg[0];
plat->plat.reg_shift = plat->dtplat.reg_shift;
plat->plat.clock = plat->dtplat.clock_frequency;
plat->plat.fcr = UART_FCR_DEFVAL;
- dev->platdata = &plat->plat;
+ dev->plat = &plat->plat;
return ns16550_serial_probe(dev);
}
U_BOOT_DRIVER(rockchip_rk3188_uart) = {
.name = "rockchip_rk3188_uart",
.id = UCLASS_SERIAL,
- .priv_auto_alloc_size = sizeof(struct NS16550),
- .platdata_auto_alloc_size = sizeof(struct rockchip_uart_platdata),
+ .priv_auto = sizeof(struct NS16550),
+ .plat_auto = sizeof(struct rockchip_uart_plat),
.probe = rockchip_serial_probe,
.ops = &ns16550_serial_ops,
.flags = DM_FLAG_PRE_RELOC,
U_BOOT_DRIVER(rockchip_rk3288_uart) = {
.name = "rockchip_rk3288_uart",
.id = UCLASS_SERIAL,
- .priv_auto_alloc_size = sizeof(struct NS16550),
- .platdata_auto_alloc_size = sizeof(struct rockchip_uart_platdata),
+ .priv_auto = sizeof(struct NS16550),
+ .plat_auto = sizeof(struct rockchip_uart_plat),
.probe = rockchip_serial_probe,
.ops = &ns16550_serial_ops,
.flags = DM_FLAG_PRE_RELOC,
#define TX_FIFO_FULL (1 << 24)
/* Information about a serial port */
-struct s5p_serial_platdata {
+struct s5p_serial_plat {
struct s5p_uart *reg; /* address of registers in physical memory */
u8 port_id; /* uart port number */
};
#ifndef CONFIG_SPL_BUILD
int s5p_serial_setbrg(struct udevice *dev, int baudrate)
{
- struct s5p_serial_platdata *plat = dev->platdata;
+ struct s5p_serial_plat *plat = dev->plat;
struct s5p_uart *const uart = plat->reg;
u32 uclk;
static int s5p_serial_probe(struct udevice *dev)
{
- struct s5p_serial_platdata *plat = dev->platdata;
+ struct s5p_serial_plat *plat = dev->plat;
struct s5p_uart *const uart = plat->reg;
s5p_serial_init(uart);
static int s5p_serial_getc(struct udevice *dev)
{
- struct s5p_serial_platdata *plat = dev->platdata;
+ struct s5p_serial_plat *plat = dev->plat;
struct s5p_uart *const uart = plat->reg;
if (!(readl(&uart->ufstat) & RX_FIFO_COUNT_MASK))
static int s5p_serial_putc(struct udevice *dev, const char ch)
{
- struct s5p_serial_platdata *plat = dev->platdata;
+ struct s5p_serial_plat *plat = dev->plat;
struct s5p_uart *const uart = plat->reg;
if (readl(&uart->ufstat) & TX_FIFO_FULL)
static int s5p_serial_pending(struct udevice *dev, bool input)
{
- struct s5p_serial_platdata *plat = dev->platdata;
+ struct s5p_serial_plat *plat = dev->plat;
struct s5p_uart *const uart = plat->reg;
uint32_t ufstat = readl(&uart->ufstat);
return (ufstat & TX_FIFO_COUNT_MASK) >> TX_FIFO_COUNT_SHIFT;
}
-static int s5p_serial_ofdata_to_platdata(struct udevice *dev)
+static int s5p_serial_of_to_plat(struct udevice *dev)
{
- struct s5p_serial_platdata *plat = dev->platdata;
+ struct s5p_serial_plat *plat = dev->plat;
fdt_addr_t addr;
addr = dev_read_addr(dev);
.name = "serial_s5p",
.id = UCLASS_SERIAL,
.of_match = s5p_serial_ids,
- .ofdata_to_platdata = s5p_serial_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct s5p_serial_platdata),
+ .of_to_plat = s5p_serial_of_to_plat,
+ .plat_auto = sizeof(struct s5p_serial_plat),
.probe = s5p_serial_probe,
.ops = &s5p_serial_ops,
};
static int sh_serial_setbrg(struct udevice *dev, int baudrate)
{
- struct sh_serial_platdata *plat = dev_get_platdata(dev);
+ struct sh_serial_plat *plat = dev_get_plat(dev);
struct uart_port *priv = dev_get_priv(dev);
sh_serial_setbrg_generic(priv, plat->clk, baudrate);
static int sh_serial_probe(struct udevice *dev)
{
- struct sh_serial_platdata *plat = dev_get_platdata(dev);
+ struct sh_serial_plat *plat = dev_get_plat(dev);
struct uart_port *priv = dev_get_priv(dev);
priv->membase = (unsigned char *)plat->base;
{}
};
-static int sh_serial_ofdata_to_platdata(struct udevice *dev)
+static int sh_serial_of_to_plat(struct udevice *dev)
{
- struct sh_serial_platdata *plat = dev_get_platdata(dev);
+ struct sh_serial_plat *plat = dev_get_plat(dev);
struct clk sh_serial_clk;
fdt_addr_t addr;
int ret;
.name = "serial_sh",
.id = UCLASS_SERIAL,
.of_match = of_match_ptr(sh_serial_id),
- .ofdata_to_platdata = of_match_ptr(sh_serial_ofdata_to_platdata),
- .platdata_auto_alloc_size = sizeof(struct sh_serial_platdata),
+ .of_to_plat = of_match_ptr(sh_serial_of_to_plat),
+ .plat_auto = sizeof(struct sh_serial_plat),
.probe = sh_serial_probe,
.ops = &sh_serial_ops,
#if !CONFIG_IS_ENABLED(OF_CONTROL)
.flags = DM_FLAG_PRE_RELOC,
#endif
- .priv_auto_alloc_size = sizeof(struct uart_port),
+ .priv_auto = sizeof(struct uart_port),
};
#else /* CONFIG_DM_SERIAL */
u32 div;
};
-struct sifive_uart_platdata {
+struct sifive_uart_plat {
unsigned long clock;
struct uart_sifive *regs;
};
{
int ret;
struct clk clk;
- struct sifive_uart_platdata *platdata = dev_get_platdata(dev);
+ struct sifive_uart_plat *plat = dev_get_plat(dev);
u32 clock = 0;
ret = clk_get_by_index(dev, 0, &clk);
return 0;
}
}
- platdata->clock = clock;
- _sifive_serial_setbrg(platdata->regs, platdata->clock, baudrate);
+ plat->clock = clock;
+ _sifive_serial_setbrg(plat->regs, plat->clock, baudrate);
return 0;
}
static int sifive_serial_probe(struct udevice *dev)
{
- struct sifive_uart_platdata *platdata = dev_get_platdata(dev);
+ struct sifive_uart_plat *plat = dev_get_plat(dev);
/* No need to reinitialize the UART after relocation */
if (gd->flags & GD_FLG_RELOC)
return 0;
- _sifive_serial_init(platdata->regs);
+ _sifive_serial_init(plat->regs);
return 0;
}
static int sifive_serial_getc(struct udevice *dev)
{
int c;
- struct sifive_uart_platdata *platdata = dev_get_platdata(dev);
- struct uart_sifive *regs = platdata->regs;
+ struct sifive_uart_plat *plat = dev_get_plat(dev);
+ struct uart_sifive *regs = plat->regs;
while ((c = _sifive_serial_getc(regs)) == -EAGAIN) ;
static int sifive_serial_putc(struct udevice *dev, const char ch)
{
int rc;
- struct sifive_uart_platdata *platdata = dev_get_platdata(dev);
+ struct sifive_uart_plat *plat = dev_get_plat(dev);
- while ((rc = _sifive_serial_putc(platdata->regs, ch)) == -EAGAIN) ;
+ while ((rc = _sifive_serial_putc(plat->regs, ch)) == -EAGAIN) ;
return rc;
}
static int sifive_serial_pending(struct udevice *dev, bool input)
{
- struct sifive_uart_platdata *platdata = dev_get_platdata(dev);
- struct uart_sifive *regs = platdata->regs;
+ struct sifive_uart_plat *plat = dev_get_plat(dev);
+ struct uart_sifive *regs = plat->regs;
if (input)
return (readl(®s->ip) & UART_IP_RXWM);
return !!(readl(®s->txfifo) & UART_TXFIFO_FULL);
}
-static int sifive_serial_ofdata_to_platdata(struct udevice *dev)
+static int sifive_serial_of_to_plat(struct udevice *dev)
{
- struct sifive_uart_platdata *platdata = dev_get_platdata(dev);
+ struct sifive_uart_plat *plat = dev_get_plat(dev);
- platdata->regs = (struct uart_sifive *)dev_read_addr(dev);
- if (IS_ERR(platdata->regs))
- return PTR_ERR(platdata->regs);
+ plat->regs = (struct uart_sifive *)dev_read_addr(dev);
+ if (IS_ERR(plat->regs))
+ return PTR_ERR(plat->regs);
return 0;
}
.name = "serial_sifive",
.id = UCLASS_SERIAL,
.of_match = sifive_serial_ids,
- .ofdata_to_platdata = sifive_serial_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct sifive_uart_platdata),
+ .of_to_plat = sifive_serial_of_to_plat,
+ .plat_auto = sizeof(struct sifive_uart_plat),
.probe = sifive_serial_probe,
.ops = &sifive_serial_ops,
};
.of_match = sti_serial_of_match,
.ops = &sti_asc_serial_ops,
.probe = sti_asc_serial_probe,
- .priv_auto_alloc_size = sizeof(struct sti_asc_serial),
+ .priv_auto = sizeof(struct sti_asc_serial),
};
static int stm32_serial_setbrg(struct udevice *dev, int baudrate)
{
- struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
+ struct stm32x7_serial_plat *plat = dev_get_plat(dev);
_stm32_serial_setbrg(plat->base, plat->uart_info,
plat->clock_rate, baudrate);
static int stm32_serial_setconfig(struct udevice *dev, uint serial_config)
{
- struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
+ struct stm32x7_serial_plat *plat = dev_get_plat(dev);
bool stm32f4 = plat->uart_info->stm32f4;
u8 uart_enable_bit = plat->uart_info->uart_enable_bit;
u32 cr1 = plat->base + CR1_OFFSET(stm32f4);
static int stm32_serial_getc(struct udevice *dev)
{
- struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
+ struct stm32x7_serial_plat *plat = dev_get_plat(dev);
bool stm32f4 = plat->uart_info->stm32f4;
fdt_addr_t base = plat->base;
u32 isr = readl(base + ISR_OFFSET(stm32f4));
static int stm32_serial_putc(struct udevice *dev, const char c)
{
- struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
+ struct stm32x7_serial_plat *plat = dev_get_plat(dev);
return _stm32_serial_putc(plat->base, plat->uart_info, c);
}
static int stm32_serial_pending(struct udevice *dev, bool input)
{
- struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
+ struct stm32x7_serial_plat *plat = dev_get_plat(dev);
bool stm32f4 = plat->uart_info->stm32f4;
fdt_addr_t base = plat->base;
static int stm32_serial_probe(struct udevice *dev)
{
- struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
+ struct stm32x7_serial_plat *plat = dev_get_plat(dev);
struct clk clk;
struct reset_ctl reset;
int ret;
{}
};
-static int stm32_serial_ofdata_to_platdata(struct udevice *dev)
+static int stm32_serial_of_to_plat(struct udevice *dev)
{
- struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
+ struct stm32x7_serial_plat *plat = dev_get_plat(dev);
plat->base = dev_read_addr(dev);
if (plat->base == FDT_ADDR_T_NONE)
.name = "serial_stm32",
.id = UCLASS_SERIAL,
.of_match = of_match_ptr(stm32_serial_id),
- .ofdata_to_platdata = of_match_ptr(stm32_serial_ofdata_to_platdata),
- .platdata_auto_alloc_size = sizeof(struct stm32x7_serial_platdata),
+ .of_to_plat = of_match_ptr(stm32_serial_of_to_plat),
+ .plat_auto = sizeof(struct stm32x7_serial_plat),
.ops = &stm32_serial_ops,
.probe = stm32_serial_probe,
#if !CONFIG_IS_ENABLED(OF_CONTROL)
};
/* Information about a serial port */
-struct stm32x7_serial_platdata {
+struct stm32x7_serial_plat {
fdt_addr_t base; /* address of registers in physical memory */
struct stm32_uart_info *uart_info;
unsigned long int clock_rate;
.id = UCLASS_SERIAL,
.of_match = uniphier_uart_of_match,
.probe = uniphier_serial_probe,
- .priv_auto_alloc_size = sizeof(struct uniphier_serial_priv),
+ .priv_auto = sizeof(struct uniphier_serial_priv),
.ops = &uniphier_serial_ops,
};
#if CONFIG_IS_ENABLED(OF_CONTROL)
.of_match = xen_serial_ids,
#endif
- .priv_auto_alloc_size = sizeof(struct xen_uart_priv),
+ .priv_auto = sizeof(struct xen_uart_priv),
.probe = xen_serial_probe,
.ops = &xen_serial_ops,
#if !CONFIG_IS_ENABLED(OF_CONTROL)
unsigned int control;
};
-struct uartlite_platdata {
+struct uartlite_plat {
struct uartlite *regs;
};
static int uartlite_serial_putc(struct udevice *dev, const char ch)
{
- struct uartlite_platdata *plat = dev_get_platdata(dev);
+ struct uartlite_plat *plat = dev_get_plat(dev);
struct uartlite *regs = plat->regs;
if (uart_in32(®s->status) & SR_TX_FIFO_FULL)
static int uartlite_serial_getc(struct udevice *dev)
{
- struct uartlite_platdata *plat = dev_get_platdata(dev);
+ struct uartlite_plat *plat = dev_get_plat(dev);
struct uartlite *regs = plat->regs;
if (!(uart_in32(®s->status) & SR_RX_FIFO_VALID_DATA))
static int uartlite_serial_pending(struct udevice *dev, bool input)
{
- struct uartlite_platdata *plat = dev_get_platdata(dev);
+ struct uartlite_plat *plat = dev_get_plat(dev);
struct uartlite *regs = plat->regs;
if (input)
static int uartlite_serial_probe(struct udevice *dev)
{
- struct uartlite_platdata *plat = dev_get_platdata(dev);
+ struct uartlite_plat *plat = dev_get_plat(dev);
struct uartlite *regs = plat->regs;
int ret;
return 0;
}
-static int uartlite_serial_ofdata_to_platdata(struct udevice *dev)
+static int uartlite_serial_of_to_plat(struct udevice *dev)
{
- struct uartlite_platdata *plat = dev_get_platdata(dev);
+ struct uartlite_plat *plat = dev_get_plat(dev);
plat->regs = dev_read_addr_ptr(dev);
.name = "serial_uartlite",
.id = UCLASS_SERIAL,
.of_match = uartlite_serial_ids,
- .ofdata_to_platdata = uartlite_serial_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct uartlite_platdata),
+ .of_to_plat = uartlite_serial_of_to_plat,
+ .plat_auto = sizeof(struct uartlite_plat),
.probe = uartlite_serial_probe,
.ops = &uartlite_serial_ops,
};
u32 baud_rate_divider; /* 0x34 - Baud Rate Divider [7:0] */
};
-struct zynq_uart_platdata {
+struct zynq_uart_plat {
struct uart_zynq *regs;
};
static int zynq_serial_setbrg(struct udevice *dev, int baudrate)
{
- struct zynq_uart_platdata *platdata = dev_get_platdata(dev);
+ struct zynq_uart_plat *plat = dev_get_plat(dev);
unsigned long clock;
int ret;
return ret;
}
- _uart_zynq_serial_setbrg(platdata->regs, clock, baudrate);
+ _uart_zynq_serial_setbrg(plat->regs, clock, baudrate);
return 0;
}
static int zynq_serial_probe(struct udevice *dev)
{
- struct zynq_uart_platdata *platdata = dev_get_platdata(dev);
- struct uart_zynq *regs = platdata->regs;
+ struct zynq_uart_plat *plat = dev_get_plat(dev);
+ struct uart_zynq *regs = plat->regs;
u32 val;
/* No need to reinitialize the UART if TX already enabled */
if (val & ZYNQ_UART_CR_TX_EN)
return 0;
- _uart_zynq_serial_init(platdata->regs);
+ _uart_zynq_serial_init(plat->regs);
return 0;
}
static int zynq_serial_getc(struct udevice *dev)
{
- struct zynq_uart_platdata *platdata = dev_get_platdata(dev);
- struct uart_zynq *regs = platdata->regs;
+ struct zynq_uart_plat *plat = dev_get_plat(dev);
+ struct uart_zynq *regs = plat->regs;
if (readl(®s->channel_sts) & ZYNQ_UART_SR_RXEMPTY)
return -EAGAIN;
static int zynq_serial_putc(struct udevice *dev, const char ch)
{
- struct zynq_uart_platdata *platdata = dev_get_platdata(dev);
+ struct zynq_uart_plat *plat = dev_get_plat(dev);
- return _uart_zynq_serial_putc(platdata->regs, ch);
+ return _uart_zynq_serial_putc(plat->regs, ch);
}
static int zynq_serial_pending(struct udevice *dev, bool input)
{
- struct zynq_uart_platdata *platdata = dev_get_platdata(dev);
- struct uart_zynq *regs = platdata->regs;
+ struct zynq_uart_plat *plat = dev_get_plat(dev);
+ struct uart_zynq *regs = plat->regs;
if (input)
return !(readl(®s->channel_sts) & ZYNQ_UART_SR_RXEMPTY);
return !!(readl(®s->channel_sts) & ZYNQ_UART_SR_TXACTIVE);
}
-static int zynq_serial_ofdata_to_platdata(struct udevice *dev)
+static int zynq_serial_of_to_plat(struct udevice *dev)
{
- struct zynq_uart_platdata *platdata = dev_get_platdata(dev);
+ struct zynq_uart_plat *plat = dev_get_plat(dev);
- platdata->regs = (struct uart_zynq *)dev_read_addr(dev);
- if (IS_ERR(platdata->regs))
- return PTR_ERR(platdata->regs);
+ plat->regs = (struct uart_zynq *)dev_read_addr(dev);
+ if (IS_ERR(plat->regs))
+ return PTR_ERR(plat->regs);
return 0;
}
.name = "serial_zynq",
.id = UCLASS_SERIAL,
.of_match = zynq_serial_ids,
- .ofdata_to_platdata = zynq_serial_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct zynq_uart_platdata),
+ .of_to_plat = zynq_serial_of_to_plat,
+ .plat_auto = sizeof(struct zynq_uart_plat),
.probe = zynq_serial_probe,
.ops = &zynq_serial_ops,
};
#define JTAG_ID_PARTNO_SHIFT 12
#define JTAG_ID_PARTNO_MASK (0xffff << 12)
-struct soc_ti_k3_platdata {
+struct soc_ti_k3_plat {
const char *family;
const char *revision;
};
static int soc_ti_k3_get_family(struct udevice *dev, char *buf, int size)
{
- struct soc_ti_k3_platdata *plat = dev_get_platdata(dev);
+ struct soc_ti_k3_plat *plat = dev_get_plat(dev);
snprintf(buf, size, "%s", plat->family);
static int soc_ti_k3_get_revision(struct udevice *dev, char *buf, int size)
{
- struct soc_ti_k3_platdata *plat = dev_get_platdata(dev);
+ struct soc_ti_k3_plat *plat = dev_get_plat(dev);
snprintf(buf, size, "SR%s", plat->revision);
int soc_ti_k3_probe(struct udevice *dev)
{
- struct soc_ti_k3_platdata *plat = dev_get_platdata(dev);
+ struct soc_ti_k3_plat *plat = dev_get_plat(dev);
u32 idreg;
void *idreg_addr;
.ops = &soc_ti_k3_ops,
.of_match = soc_ti_k3_ids,
.probe = soc_ti_k3_probe,
- .platdata_auto_alloc_size = sizeof(struct soc_ti_k3_platdata),
+ .plat_auto = sizeof(struct soc_ti_k3_plat),
};
.id = UCLASS_MISC,
.of_match = knav_ringacc_ids,
.probe = k3_nav_ringacc_probe,
- .priv_auto_alloc_size = sizeof(struct k3_nav_ringacc),
+ .priv_auto = sizeof(struct k3_nav_ringacc),
};
.of_match = broadwell_i2s_ids,
.probe = broadwell_i2s_probe,
.ops = &broadwell_i2s_ops,
- .priv_auto_alloc_size = sizeof(struct broadwell_i2s_priv),
+ .priv_auto = sizeof(struct broadwell_i2s_priv),
};
.name = "hda_codec",
.id = UCLASS_SOUND,
.ops = &hda_codec_ops,
- .priv_auto_alloc_size = sizeof(struct hda_codec_priv),
+ .priv_auto = sizeof(struct hda_codec_priv),
.probe = hda_codec_init,
};
UCLASS_DRIVER(i2s) = {
.id = UCLASS_I2S,
.name = "i2s",
- .per_device_auto_alloc_size = sizeof(struct i2s_uc_priv),
+ .per_device_auto = sizeof(struct i2s_uc_priv),
};
static int bd82x6x_azalia_probe(struct udevice *dev)
{
- struct pci_child_platdata *plat;
+ struct pci_child_plat *plat;
struct hda_codec_priv *priv;
struct udevice *pch;
u32 codec_mask;
dm_pci_clrset_config32(dev, 0xd0, 1U << 31, 0);
/* Additional step on Panther Point */
- plat = dev_get_parent_platdata(dev);
+ plat = dev_get_parent_plat(dev);
if (plat->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_HDA)
dm_pci_clrset_config32(dev, 0xc4, 0, 1 << 17);
.of_match = bd82x6x_azalia_ids,
.probe = bd82x6x_azalia_probe,
.ops = &bd82x6x_azalia_ops,
- .priv_auto_alloc_size = sizeof(struct hda_codec_priv),
+ .priv_auto = sizeof(struct hda_codec_priv),
};
.of_match = max98088_ids,
.probe = max98088_probe,
.ops = &max98088_ops,
- .priv_auto_alloc_size = sizeof(struct maxim_priv),
+ .priv_auto = sizeof(struct maxim_priv),
};
.of_match = max98090_ids,
.probe = max98090_probe,
.ops = &max98090_ops,
- .priv_auto_alloc_size = sizeof(struct maxim_priv),
+ .priv_auto = sizeof(struct maxim_priv),
};
.of_match = max98095_ids,
.probe = max98095_probe,
.ops = &max98095_ops,
- .priv_auto_alloc_size = sizeof(struct maxim_priv),
+ .priv_auto = sizeof(struct maxim_priv),
};
struct gpio_desc sdmode_gpio;
};
-static int max98357a_ofdata_to_platdata(struct udevice *dev)
+static int max98357a_of_to_plat(struct udevice *dev)
{
struct max98357a_priv *priv = dev_get_priv(dev);
int ret;
.name = "max98357a",
.id = UCLASS_AUDIO_CODEC,
.of_match = max98357a_ids,
- .ofdata_to_platdata = max98357a_ofdata_to_platdata,
+ .of_to_plat = max98357a_of_to_plat,
.ops = &max98357a_ops,
ACPI_OPS_PTR(&max98357a_acpi_ops)
};
.of_match = rt5677_ids,
.ops = &rt5677_ops,
.probe = rt5677_probe,
- .priv_auto_alloc_size = sizeof(struct rt5677_priv),
+ .priv_auto = sizeof(struct rt5677_priv),
};
return i2s_tx_init(priv);
}
-static int samsung_i2s_ofdata_to_platdata(struct udevice *dev)
+static int samsung_i2s_of_to_plat(struct udevice *dev)
{
struct i2s_uc_priv *priv = dev_get_uclass_priv(dev);
ulong base;
.id = UCLASS_I2S,
.of_match = samsung_i2s_ids,
.probe = samsung_i2s_probe,
- .ofdata_to_platdata = samsung_i2s_ofdata_to_platdata,
+ .of_to_plat = samsung_i2s_of_to_plat,
.ops = &samsung_i2s_ops,
};
.id = UCLASS_AUDIO_CODEC,
.of_match = sandbox_codec_ids,
.ops = &sandbox_codec_ops,
- .priv_auto_alloc_size = sizeof(struct sandbox_codec_priv),
+ .priv_auto = sizeof(struct sandbox_codec_priv),
};
static const struct i2s_ops sandbox_i2s_ops = {
.of_match = sandbox_i2s_ids,
.ops = &sandbox_i2s_ops,
.probe = sandbox_i2s_probe,
- .priv_auto_alloc_size = sizeof(struct sandbox_i2s_priv),
+ .priv_auto = sizeof(struct sandbox_i2s_priv),
};
static const struct sound_ops sandbox_sound_ops = {
.id = UCLASS_SOUND,
.of_match = sandbox_sound_ids,
.ops = &sandbox_sound_ops,
- .priv_auto_alloc_size = sizeof(struct sandbox_sound_priv),
+ .priv_auto = sizeof(struct sandbox_sound_priv),
.probe = sandbox_sound_probe,
};
UCLASS_DRIVER(sound) = {
.id = UCLASS_SOUND,
.name = "sound",
- .per_device_auto_alloc_size = sizeof(struct sound_uc_priv),
+ .per_device_auto = sizeof(struct sound_uc_priv),
};
.of_match = tegra_ahub_ids,
.ops = &tegra_ahub_ops,
.probe = tegra_ahub_probe,
- .priv_auto_alloc_size = sizeof(struct tegra_ahub_priv),
+ .priv_auto = sizeof(struct tegra_ahub_priv),
};
.of_match = wm8994_ids,
.probe = wm8994_probe,
.ops = &wm8994_ops,
- .priv_auto_alloc_size = sizeof(struct wm8994_priv),
+ .priv_auto = sizeof(struct wm8994_priv),
};
u32 slave_sel;
};
-struct altera_spi_platdata {
+struct altera_spi_plat {
struct altera_spi_regs *regs;
};
struct udevice *bus = dev->parent;
struct altera_spi_priv *priv = dev_get_priv(bus);
struct altera_spi_regs *const regs = priv->regs;
- struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
/* assume spi core configured to do 8 bit transfers */
unsigned int bytes = bitlen / 8;
static int altera_spi_probe(struct udevice *bus)
{
- struct altera_spi_platdata *plat = dev_get_platdata(bus);
+ struct altera_spi_plat *plat = dev_get_plat(bus);
struct altera_spi_priv *priv = dev_get_priv(bus);
priv->regs = plat->regs;
return 0;
}
-static int altera_spi_ofdata_to_platdata(struct udevice *bus)
+static int altera_spi_of_to_plat(struct udevice *bus)
{
- struct altera_spi_platdata *plat = dev_get_platdata(bus);
+ struct altera_spi_plat *plat = dev_get_plat(bus);
plat->regs = map_physmem(dev_read_addr(bus),
sizeof(struct altera_spi_regs),
.id = UCLASS_SPI,
.of_match = altera_spi_ids,
.ops = &altera_spi_ops,
- .ofdata_to_platdata = altera_spi_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct altera_spi_platdata),
- .priv_auto_alloc_size = sizeof(struct altera_spi_priv),
+ .of_to_plat = altera_spi_of_to_plat,
+ .plat_auto = sizeof(struct altera_spi_plat),
+ .priv_auto = sizeof(struct altera_spi_priv),
.probe = altera_spi_probe,
};
static int atcspi200_spi_claim_bus(struct udevice *dev)
{
- struct dm_spi_slave_platdata *slave_plat =
- dev_get_parent_platdata(dev);
+ struct dm_spi_slave_plat *slave_plat =
+ dev_get_parent_plat(dev);
struct udevice *bus = dev->parent;
struct nds_spi_slave *ns = dev_get_priv(bus);
.id = UCLASS_SPI,
.of_match = atcspi200_spi_ids,
.ops = &atcspi200_spi_ops,
- .ofdata_to_platdata = atcspi200_ofdata_to_platadata,
- .priv_auto_alloc_size = sizeof(struct nds_spi_slave),
+ .of_to_plat = atcspi200_ofdata_to_platadata,
+ .priv_auto = sizeof(struct nds_spi_slave),
.probe = atcspi200_spi_probe,
};
{
struct udevice *bus = dev_get_parent(dev);
struct ath79_spi_priv *priv = dev_get_priv(bus);
- struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
+ struct dm_spi_slave_plat *slave = dev_get_parent_plat(dev);
u8 *rx = din;
const u8 *tx = dout;
u8 curbyte, curbitlen, restbits;
.id = UCLASS_SPI,
.of_match = ath79_spi_ids,
.ops = &ath79_spi_ops,
- .priv_auto_alloc_size = sizeof(struct ath79_spi_priv),
+ .priv_auto = sizeof(struct ath79_spi_priv),
.probe = ath79_spi_probe,
};
.id = UCLASS_SPI,
.of_match = atmel_qspi_ids,
.ops = &atmel_qspi_ops,
- .priv_auto_alloc_size = sizeof(struct atmel_qspi),
+ .priv_auto = sizeof(struct atmel_qspi),
.probe = atmel_qspi_probe,
};
#define spi_writel(as, reg, value) \
writel(value, as->regs + ATMEL_SPI_##reg)
-struct atmel_spi_platdata {
+struct atmel_spi_plat {
struct at91_spi *regs;
};
static int atmel_spi_claim_bus(struct udevice *dev)
{
struct udevice *bus = dev_get_parent(dev);
- struct atmel_spi_platdata *bus_plat = dev_get_platdata(bus);
+ struct atmel_spi_plat *bus_plat = dev_get_plat(bus);
struct atmel_spi_priv *priv = dev_get_priv(bus);
- struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
struct at91_spi *reg_base = bus_plat->regs;
u32 cs = slave_plat->cs;
u32 freq = priv->freq;
static int atmel_spi_release_bus(struct udevice *dev)
{
struct udevice *bus = dev_get_parent(dev);
- struct atmel_spi_platdata *bus_plat = dev_get_platdata(bus);
+ struct atmel_spi_plat *bus_plat = dev_get_plat(bus);
writel(ATMEL_SPI_CR_SPIDIS, &bus_plat->regs->cr);
#if CONFIG_IS_ENABLED(DM_GPIO)
struct udevice *bus = dev_get_parent(dev);
struct atmel_spi_priv *priv = dev_get_priv(bus);
- struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
u32 cs = slave_plat->cs;
if (!dm_gpio_is_valid(&priv->cs_gpios[cs]))
#if CONFIG_IS_ENABLED(DM_GPIO)
struct udevice *bus = dev_get_parent(dev);
struct atmel_spi_priv *priv = dev_get_priv(bus);
- struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
u32 cs = slave_plat->cs;
if (!dm_gpio_is_valid(&priv->cs_gpios[cs]))
const void *dout, void *din, unsigned long flags)
{
struct udevice *bus = dev_get_parent(dev);
- struct atmel_spi_platdata *bus_plat = dev_get_platdata(bus);
+ struct atmel_spi_plat *bus_plat = dev_get_plat(bus);
struct at91_spi *reg_base = bus_plat->regs;
u32 len_tx, len_rx, len;
static int atmel_spi_probe(struct udevice *bus)
{
- struct atmel_spi_platdata *bus_plat = dev_get_platdata(bus);
+ struct atmel_spi_plat *bus_plat = dev_get_plat(bus);
int ret;
ret = atmel_spi_enable_clk(bus);
.id = UCLASS_SPI,
.of_match = atmel_spi_ids,
.ops = &atmel_spi_ops,
- .platdata_auto_alloc_size = sizeof(struct atmel_spi_platdata),
- .priv_auto_alloc_size = sizeof(struct atmel_spi_priv),
+ .plat_auto = sizeof(struct atmel_spi_plat),
+ .priv_auto = sizeof(struct atmel_spi_priv),
.probe = atmel_spi_probe,
};
}
static void bcm63xx_hsspi_activate_cs(struct bcm63xx_hsspi_priv *priv,
- struct dm_spi_slave_platdata *plat)
+ struct dm_spi_slave_plat *plat)
{
uint32_t clr, set;
const void *dout, void *din, unsigned long flags)
{
struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev->parent);
- struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev);
+ struct dm_spi_slave_plat *plat = dev_get_parent_plat(dev);
size_t data_bytes = bitlen / 8;
size_t step_size = HSSPI_FIFO_SIZE;
uint16_t opcode = 0;
static int bcm63xx_hsspi_child_pre_probe(struct udevice *dev)
{
struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev->parent);
- struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev);
+ struct dm_spi_slave_plat *plat = dev_get_parent_plat(dev);
/* check cs */
if (plat->cs >= priv->num_cs) {
.id = UCLASS_SPI,
.of_match = bcm63xx_hsspi_ids,
.ops = &bcm63xx_hsspi_ops,
- .priv_auto_alloc_size = sizeof(struct bcm63xx_hsspi_priv),
+ .priv_auto = sizeof(struct bcm63xx_hsspi_priv),
.child_pre_probe = bcm63xx_hsspi_child_pre_probe,
.probe = bcm63xx_hsspi_probe,
};
}
if (flags & SPI_XFER_END) {
- struct dm_spi_slave_platdata *plat =
- dev_get_parent_platdata(dev);
+ struct dm_spi_slave_plat *plat =
+ dev_get_parent_plat(dev);
uint16_t val, cmd;
int ret;
struct bcm63xx_spi_priv *priv = dev_get_priv(dev->parent);
const unsigned long *regs = priv->regs;
struct spi_slave *slave = dev_get_parent_priv(dev);
- struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev);
+ struct dm_spi_slave_plat *plat = dev_get_parent_plat(dev);
/* check cs */
if (plat->cs >= priv->num_cs) {
.id = UCLASS_SPI,
.of_match = bcm63xx_spi_ids,
.ops = &bcm63xx_spi_ops,
- .priv_auto_alloc_size = sizeof(struct bcm63xx_spi_priv),
+ .priv_auto = sizeof(struct bcm63xx_spi_priv),
.child_pre_probe = bcm63xx_spi_child_pre_probe,
.probe = bcm63xx_spi_probe,
};
BASE_LAST,
};
-struct bcmstb_spi_platdata {
+struct bcmstb_spi_plat {
void *base[4];
};
void *saved_din_addr;
};
-static int bcmstb_spi_ofdata_to_platdata(struct udevice *bus)
+static int bcmstb_spi_of_to_plat(struct udevice *bus)
{
- struct bcmstb_spi_platdata *plat = dev_get_platdata(bus);
+ struct bcmstb_spi_plat *plat = dev_get_plat(bus);
const void *fdt = gd->fdt_blob;
int node = dev_of_offset(bus);
int ret = 0;
static int bcmstb_spi_probe(struct udevice *bus)
{
- struct bcmstb_spi_platdata *plat = dev_get_platdata(bus);
+ struct bcmstb_spi_plat *plat = dev_get_plat(bus);
struct bcmstb_spi_priv *priv = dev_get_priv(bus);
priv->regs = plat->base[HIF_MSPI];
.id = UCLASS_SPI,
.of_match = bcmstb_spi_id,
.ops = &bcmstb_spi_ops,
- .ofdata_to_platdata = bcmstb_spi_ofdata_to_platdata,
+ .of_to_plat = bcmstb_spi_of_to_plat,
.probe = bcmstb_spi_probe,
- .platdata_auto_alloc_size = sizeof(struct bcmstb_spi_platdata),
- .priv_auto_alloc_size = sizeof(struct bcmstb_spi_priv),
+ .plat_auto = sizeof(struct bcmstb_spi_plat),
+ .priv_auto = sizeof(struct bcmstb_spi_priv),
};
static int cadence_spi_write_speed(struct udevice *bus, uint hz)
{
- struct cadence_spi_platdata *plat = bus->platdata;
+ struct cadence_spi_plat *plat = bus->plat;
struct cadence_spi_priv *priv = dev_get_priv(bus);
cadence_qspi_apb_config_baudrate_div(priv->regbase,
static int cadence_spi_set_speed(struct udevice *bus, uint hz)
{
- struct cadence_spi_platdata *plat = bus->platdata;
+ struct cadence_spi_plat *plat = bus->plat;
struct cadence_spi_priv *priv = dev_get_priv(bus);
int err;
static int cadence_spi_probe(struct udevice *bus)
{
- struct cadence_spi_platdata *plat = bus->platdata;
+ struct cadence_spi_plat *plat = bus->plat;
struct cadence_spi_priv *priv = dev_get_priv(bus);
struct clk clk;
int ret;
static int cadence_spi_set_mode(struct udevice *bus, uint mode)
{
- struct cadence_spi_platdata *plat = bus->platdata;
+ struct cadence_spi_plat *plat = bus->plat;
struct cadence_spi_priv *priv = dev_get_priv(bus);
/* Disable QSPI */
const struct spi_mem_op *op)
{
struct udevice *bus = spi->dev->parent;
- struct cadence_spi_platdata *plat = bus->platdata;
+ struct cadence_spi_plat *plat = bus->plat;
struct cadence_spi_priv *priv = dev_get_priv(bus);
void *base = priv->regbase;
int err = 0;
return err;
}
-static int cadence_spi_ofdata_to_platdata(struct udevice *bus)
+static int cadence_spi_of_to_plat(struct udevice *bus)
{
- struct cadence_spi_platdata *plat = bus->platdata;
+ struct cadence_spi_plat *plat = bus->plat;
ofnode subnode;
plat->regbase = (void *)devfdt_get_addr_index(bus, 0);
.id = UCLASS_SPI,
.of_match = cadence_spi_ids,
.ops = &cadence_spi_ops,
- .ofdata_to_platdata = cadence_spi_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct cadence_spi_platdata),
- .priv_auto_alloc_size = sizeof(struct cadence_spi_priv),
+ .of_to_plat = cadence_spi_of_to_plat,
+ .plat_auto = sizeof(struct cadence_spi_plat),
+ .priv_auto = sizeof(struct cadence_spi_priv),
.probe = cadence_spi_probe,
.remove = cadence_spi_remove,
.flags = DM_FLAG_OS_PREPARE,
#define CQSPI_DECODER_MAX_CS 16
#define CQSPI_READ_CAPTURE_MAX_DELAY 16
-struct cadence_spi_platdata {
+struct cadence_spi_plat {
unsigned int ref_clk_hz;
unsigned int max_hz;
void *regbase;
};
/* Functions call declaration */
-void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat);
+void cadence_qspi_apb_controller_init(struct cadence_spi_plat *plat);
void cadence_qspi_apb_controller_enable(void *reg_base_addr);
void cadence_qspi_apb_controller_disable(void *reg_base_addr);
void cadence_qspi_apb_dac_mode_enable(void *reg_base);
int cadence_qspi_apb_command_write(void *reg_base_addr,
const struct spi_mem_op *op);
-int cadence_qspi_apb_read_setup(struct cadence_spi_platdata *plat,
+int cadence_qspi_apb_read_setup(struct cadence_spi_plat *plat,
const struct spi_mem_op *op);
-int cadence_qspi_apb_read_execute(struct cadence_spi_platdata *plat,
+int cadence_qspi_apb_read_execute(struct cadence_spi_plat *plat,
const struct spi_mem_op *op);
-int cadence_qspi_apb_write_setup(struct cadence_spi_platdata *plat,
+int cadence_qspi_apb_write_setup(struct cadence_spi_plat *plat,
const struct spi_mem_op *op);
-int cadence_qspi_apb_write_execute(struct cadence_spi_platdata *plat,
+int cadence_qspi_apb_write_execute(struct cadence_spi_plat *plat,
const struct spi_mem_op *op);
void cadence_qspi_apb_chipselect(void *reg_base,
cadence_qspi_apb_controller_enable(reg_base);
}
-void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat)
+void cadence_qspi_apb_controller_init(struct cadence_spi_plat *plat)
{
unsigned reg;
}
/* Opcode + Address (3/4 bytes) + dummy bytes (0-4 bytes) */
-int cadence_qspi_apb_read_setup(struct cadence_spi_platdata *plat,
+int cadence_qspi_apb_read_setup(struct cadence_spi_plat *plat,
const struct spi_mem_op *op)
{
unsigned int reg;
return 0;
}
-static u32 cadence_qspi_get_rd_sram_level(struct cadence_spi_platdata *plat)
+static u32 cadence_qspi_get_rd_sram_level(struct cadence_spi_plat *plat)
{
u32 reg = readl(plat->regbase + CQSPI_REG_SDRAMLEVEL);
reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB;
return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK;
}
-static int cadence_qspi_wait_for_data(struct cadence_spi_platdata *plat)
+static int cadence_qspi_wait_for_data(struct cadence_spi_plat *plat)
{
unsigned int timeout = 10000;
u32 reg;
}
static int
-cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
+cadence_qspi_apb_indirect_read_execute(struct cadence_spi_plat *plat,
unsigned int n_rx, u8 *rxbuf)
{
unsigned int remaining = n_rx;
return ret;
}
-int cadence_qspi_apb_read_execute(struct cadence_spi_platdata *plat,
+int cadence_qspi_apb_read_execute(struct cadence_spi_plat *plat,
const struct spi_mem_op *op)
{
u64 from = op->addr.val;
}
/* Opcode + Address (3/4 bytes) */
-int cadence_qspi_apb_write_setup(struct cadence_spi_platdata *plat,
+int cadence_qspi_apb_write_setup(struct cadence_spi_plat *plat,
const struct spi_mem_op *op)
{
unsigned int reg;
}
static int
-cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
+cadence_qspi_apb_indirect_write_execute(struct cadence_spi_plat *plat,
unsigned int n_tx, const u8 *txbuf)
{
unsigned int page_size = plat->page_size;
return ret;
}
-int cadence_qspi_apb_write_execute(struct cadence_spi_platdata *plat,
+int cadence_qspi_apb_write_execute(struct cadence_spi_plat *plat,
const struct spi_mem_op *op)
{
u32 to = op->addr.val;
struct udevice *bus = dev->parent;
struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
struct dspi *dspi = cfspi->regs;
- struct dm_spi_slave_platdata *slave_plat =
- dev_get_parent_platdata(dev);
+ struct dm_spi_slave_plat *slave_plat =
+ dev_get_parent_plat(dev);
if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
return -1;
struct udevice *bus = dev->parent;
struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
struct dspi *dspi = cfspi->regs;
- struct dm_spi_slave_platdata *slave_plat =
- dev_get_parent_platdata(dev);
+ struct dm_spi_slave_plat *slave_plat =
+ dev_get_parent_plat(dev);
/* Clear FIFO */
clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
{
struct udevice *bus = dev_get_parent(dev);
struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
- struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
u16 *spi_rd16 = NULL, *spi_wr16 = NULL;
u8 *spi_rd = NULL, *spi_wr = NULL;
static u32 ctrl;
static int coldfire_spi_probe(struct udevice *bus)
{
- struct coldfire_spi_platdata *plat = dev_get_platdata(bus);
+ struct coldfire_spi_plat *plat = dev_get_plat(bus);
struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
struct dspi *dspi = cfspi->regs;
int i;
}
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
-static int coldfire_dspi_ofdata_to_platdata(struct udevice *bus)
+static int coldfire_dspi_of_to_plat(struct udevice *bus)
{
fdt_addr_t addr;
- struct coldfire_spi_platdata *plat = bus->platdata;
+ struct coldfire_spi_plat *plat = bus->plat;
const void *blob = gd->fdt_blob;
int node = dev_of_offset(bus);
int *ctar, len;
.id = UCLASS_SPI,
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
.of_match = coldfire_spi_ids,
- .ofdata_to_platdata = coldfire_dspi_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct coldfire_spi_platdata),
+ .of_to_plat = coldfire_dspi_of_to_plat,
+ .plat_auto = sizeof(struct coldfire_spi_plat),
#endif
.probe = coldfire_spi_probe,
.ops = &coldfire_spi_ops,
- .priv_auto_alloc_size = sizeof(struct coldfire_spi_priv),
+ .priv_auto = sizeof(struct coldfire_spi_priv),
};
static int davinci_spi_claim_bus(struct udevice *dev)
{
- struct dm_spi_slave_platdata *slave_plat =
- dev_get_parent_platdata(dev);
+ struct dm_spi_slave_plat *slave_plat =
+ dev_get_parent_plat(dev);
struct udevice *bus = dev->parent;
struct davinci_spi_slave *ds = dev_get_priv(bus);
const void *dout, void *din,
unsigned long flags)
{
- struct dm_spi_slave_platdata *slave =
- dev_get_parent_platdata(dev);
+ struct dm_spi_slave_plat *slave =
+ dev_get_parent_plat(dev);
struct udevice *bus = dev->parent;
struct davinci_spi_slave *ds = dev_get_priv(bus);
static int davinci_spi_probe(struct udevice *bus)
{
struct davinci_spi_slave *ds = dev_get_priv(bus);
- struct davinci_spi_platdata *plat = bus->platdata;
+ struct davinci_spi_plat *plat = bus->plat;
ds->regs = plat->regs;
ds->num_cs = plat->num_cs;
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
static int davinci_ofdata_to_platadata(struct udevice *bus)
{
- struct davinci_spi_platdata *plat = bus->platdata;
+ struct davinci_spi_plat *plat = bus->plat;
fdt_addr_t addr;
addr = dev_read_addr(bus);
.id = UCLASS_SPI,
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
.of_match = davinci_spi_ids,
- .ofdata_to_platdata = davinci_ofdata_to_platadata,
- .platdata_auto_alloc_size = sizeof(struct davinci_spi_platdata),
+ .of_to_plat = davinci_ofdata_to_platadata,
+ .plat_auto = sizeof(struct davinci_spi_plat),
#endif
.probe = davinci_spi_probe,
.ops = &davinci_spi_ops,
- .priv_auto_alloc_size = sizeof(struct davinci_spi_slave),
+ .priv_auto = sizeof(struct davinci_spi_slave),
};
#define RX_TIMEOUT 1000 /* timeout in ms */
-struct dw_spi_platdata {
+struct dw_spi_plat {
s32 frequency; /* Default clock frequency, -1 for none */
void __iomem *regs;
};
return 0;
}
-static int dw_spi_ofdata_to_platdata(struct udevice *bus)
+static int dw_spi_of_to_plat(struct udevice *bus)
{
- struct dw_spi_platdata *plat = bus->platdata;
+ struct dw_spi_plat *plat = bus->plat;
plat->regs = dev_read_addr_ptr(bus);
static int dw_spi_probe(struct udevice *bus)
{
- struct dw_spi_platdata *plat = dev_get_platdata(bus);
+ struct dw_spi_plat *plat = dev_get_plat(bus);
struct dw_spi_priv *priv = dev_get_priv(bus);
int ret;
static int dw_spi_set_speed(struct udevice *bus, uint speed)
{
- struct dw_spi_platdata *plat = bus->platdata;
+ struct dw_spi_plat *plat = bus->plat;
struct dw_spi_priv *priv = dev_get_priv(bus);
u16 clk_div;
.id = UCLASS_SPI,
.of_match = dw_spi_ids,
.ops = &dw_spi_ops,
- .ofdata_to_platdata = dw_spi_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct dw_spi_platdata),
- .priv_auto_alloc_size = sizeof(struct dw_spi_priv),
+ .of_to_plat = dw_spi_of_to_plat,
+ .plat_auto = sizeof(struct dw_spi_plat),
+ .priv_auto = sizeof(struct dw_spi_priv),
.probe = dw_spi_probe,
.remove = dw_spi_remove,
};
DECLARE_GLOBAL_DATA_PTR;
-struct exynos_spi_platdata {
+struct exynos_spi_plat {
enum periph_id periph_id;
s32 frequency; /* Default clock frequency, -1 for none */
struct exynos_spi *regs;
static void spi_cs_activate(struct udevice *dev)
{
struct udevice *bus = dev->parent;
- struct exynos_spi_platdata *pdata = dev_get_platdata(bus);
+ struct exynos_spi_plat *pdata = dev_get_plat(bus);
struct exynos_spi_priv *priv = dev_get_priv(bus);
/* If it's too soon to do another transaction, wait */
static void spi_cs_deactivate(struct udevice *dev)
{
struct udevice *bus = dev->parent;
- struct exynos_spi_platdata *pdata = dev_get_platdata(bus);
+ struct exynos_spi_plat *pdata = dev_get_plat(bus);
struct exynos_spi_priv *priv = dev_get_priv(bus);
setbits_le32(&priv->regs->cs_reg, SPI_SLAVE_SIG_INACT);
debug("Deactivate CS, bus '%s'\n", bus->name);
}
-static int exynos_spi_ofdata_to_platdata(struct udevice *bus)
+static int exynos_spi_of_to_plat(struct udevice *bus)
{
- struct exynos_spi_platdata *plat = bus->platdata;
+ struct exynos_spi_plat *plat = bus->plat;
const void *blob = gd->fdt_blob;
int node = dev_of_offset(bus);
static int exynos_spi_probe(struct udevice *bus)
{
- struct exynos_spi_platdata *plat = dev_get_platdata(bus);
+ struct exynos_spi_plat *plat = dev_get_plat(bus);
struct exynos_spi_priv *priv = dev_get_priv(bus);
priv->regs = plat->regs;
static int exynos_spi_set_speed(struct udevice *bus, uint speed)
{
- struct exynos_spi_platdata *plat = bus->platdata;
+ struct exynos_spi_plat *plat = bus->plat;
struct exynos_spi_priv *priv = dev_get_priv(bus);
int ret;
.id = UCLASS_SPI,
.of_match = exynos_spi_ids,
.ops = &exynos_spi_ops,
- .ofdata_to_platdata = exynos_spi_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct exynos_spi_platdata),
- .priv_auto_alloc_size = sizeof(struct exynos_spi_priv),
+ .of_to_plat = exynos_spi_of_to_plat,
+ .plat_auto = sizeof(struct exynos_spi_plat),
+ .priv_auto = sizeof(struct exynos_spi_priv),
.probe = exynos_spi_probe,
};
DECLARE_GLOBAL_DATA_PTR;
-/* fsl_dspi_platdata flags */
+/* fsl_dspi_plat flags */
#define DSPI_FLAG_REGMAP_ENDIAN_BIG BIT(0)
/* idle data value */
DSPI_CTAR_DT(15))
/**
- * struct fsl_dspi_platdata - platform data for Freescale DSPI
+ * struct fsl_dspi_plat - platform data for Freescale DSPI
*
* @flags: Flags for DSPI DSPI_FLAG_...
* @speed_hz: Default SCK frequency
* @num_chipselect: Number of DSPI chipselect signals
* @regs_addr: Base address of DSPI registers
*/
-struct fsl_dspi_platdata {
+struct fsl_dspi_plat {
uint flags;
uint speed_hz;
uint num_chipselect;
static int fsl_dspi_child_pre_probe(struct udevice *dev)
{
- struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
struct fsl_dspi_priv *priv = dev_get_priv(dev->parent);
u32 cs_sck_delay = 0, sck_cs_delay = 0;
unsigned char pcssck = 0, cssck = 0;
static int fsl_dspi_probe(struct udevice *bus)
{
- struct fsl_dspi_platdata *plat = dev_get_platdata(bus);
+ struct fsl_dspi_plat *plat = dev_get_plat(bus);
struct fsl_dspi_priv *priv = dev_get_priv(bus);
struct dm_spi_bus *dm_spi_bus;
uint mcr_cfg_val;
uint sr_val;
struct fsl_dspi_priv *priv;
struct udevice *bus = dev->parent;
- struct dm_spi_slave_platdata *slave_plat =
- dev_get_parent_platdata(dev);
+ struct dm_spi_slave_plat *slave_plat =
+ dev_get_parent_plat(dev);
priv = dev_get_priv(bus);
{
struct udevice *bus = dev->parent;
struct fsl_dspi_priv *priv = dev_get_priv(bus);
- struct dm_spi_slave_platdata *slave_plat =
- dev_get_parent_platdata(dev);
+ struct dm_spi_slave_plat *slave_plat =
+ dev_get_parent_plat(dev);
/* halt module */
dspi_halt(priv, 1);
return 0;
}
-static int fsl_dspi_ofdata_to_platdata(struct udevice *bus)
+static int fsl_dspi_of_to_plat(struct udevice *bus)
{
fdt_addr_t addr;
- struct fsl_dspi_platdata *plat = bus->platdata;
+ struct fsl_dspi_plat *plat = bus->plat;
const void *blob = gd->fdt_blob;
int node = dev_of_offset(bus);
const void *dout, void *din, unsigned long flags)
{
struct fsl_dspi_priv *priv;
- struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
struct udevice *bus;
bus = dev->parent;
.id = UCLASS_SPI,
.of_match = fsl_dspi_ids,
.ops = &fsl_dspi_ops,
- .ofdata_to_platdata = fsl_dspi_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct fsl_dspi_platdata),
- .priv_auto_alloc_size = sizeof(struct fsl_dspi_priv),
+ .of_to_plat = fsl_dspi_of_to_plat,
+ .plat_auto = sizeof(struct fsl_dspi_plat),
+ .priv_auto = sizeof(struct fsl_dspi_priv),
.probe = fsl_dspi_probe,
.child_pre_probe = fsl_dspi_child_pre_probe,
.bind = fsl_dspi_bind,
static int fsl_espi_child_pre_probe(struct udevice *dev)
{
- struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
struct udevice *bus = dev->parent;
struct fsl_spi_slave *fsl = dev_get_priv(bus);
static int fsl_espi_probe(struct udevice *bus)
{
- struct fsl_espi_platdata *plat = dev_get_platdata(bus);
+ struct fsl_espi_plat *plat = dev_get_plat(bus);
struct fsl_spi_slave *fsl = dev_get_priv(bus);
fsl->espi = (ccsr_espi_t *)((u32)plat->regs_addr);
};
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
-static int fsl_espi_ofdata_to_platdata(struct udevice *bus)
+static int fsl_espi_of_to_plat(struct udevice *bus)
{
fdt_addr_t addr;
- struct fsl_espi_platdata *plat = bus->platdata;
+ struct fsl_espi_plat *plat = bus->plat;
const void *blob = gd->fdt_blob;
int node = dev_of_offset(bus);
.id = UCLASS_SPI,
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
.of_match = fsl_espi_ids,
- .ofdata_to_platdata = fsl_espi_ofdata_to_platdata,
+ .of_to_plat = fsl_espi_of_to_plat,
#endif
.ops = &fsl_espi_ops,
- .platdata_auto_alloc_size = sizeof(struct fsl_espi_platdata),
- .priv_auto_alloc_size = sizeof(struct fsl_spi_slave),
+ .plat_auto = sizeof(struct fsl_espi_plat),
+ .priv_auto = sizeof(struct fsl_spi_slave),
.probe = fsl_espi_probe,
.child_pre_probe = fsl_espi_child_pre_probe,
};
static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_slave *slave)
{
- struct dm_spi_slave_platdata *plat =
- dev_get_parent_platdata(slave->dev);
+ struct dm_spi_slave_plat *plat =
+ dev_get_parent_plat(slave->dev);
if (q->selected == plat->cs)
return;
.id = UCLASS_SPI,
.of_match = fsl_qspi_ids,
.ops = &fsl_qspi_ops,
- .priv_auto_alloc_size = sizeof(struct fsl_qspi),
+ .priv_auto = sizeof(struct fsl_qspi),
.probe = fsl_qspi_probe,
};
#define debug_trace(x, args...)
#endif
-struct ich_spi_platdata {
+struct ich_spi_plat {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct dtd_intel_fast_spi dtplat;
#endif
return speed == 1;
}
-static void spi_lock_down(struct ich_spi_platdata *plat, void *sbase)
+static void spi_lock_down(struct ich_spi_plat *plat, void *sbase)
{
if (plat->ich_version == ICHV_7) {
struct ich7_spi_regs *ich7_spi = sbase;
}
}
-static bool spi_lock_status(struct ich_spi_platdata *plat, void *sbase)
+static bool spi_lock_status(struct ich_spi_plat *plat, void *sbase)
{
int lock = 0;
const struct spi_mem_op *op)
{
struct udevice *bus = dev_get_parent(slave->dev);
- struct ich_spi_platdata *plat = dev_get_platdata(bus);
+ struct ich_spi_plat *plat = dev_get_plat(bus);
struct ich_spi_priv *ctlr = dev_get_priv(bus);
uint16_t control;
int16_t opcode_index;
static int ich_spi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op)
{
struct udevice *bus = dev_get_parent(slave->dev);
- struct ich_spi_platdata *plat = dev_get_platdata(bus);
+ struct ich_spi_plat *plat = dev_get_plat(bus);
int ret;
bootstage_start(BOOTSTAGE_ID_ACCUM_SPI, "fast_spi");
* 1. Using of-platdata, in which case we have the BDF and can access the
* registers by reading the BAR
* 2. Not using of-platdata, but still with a SPI controller that is on its own
- * PCI PDF. In this case we read the BDF from the parent platdata and again get
+ * PCI PDF. In this case we read the BDF from the parent plat and again get
* the registers by reading the BAR
* 3. Using a SPI controller that is a child of the PCH, in which case we try
* to find the registers by asking the PCH. This only works if the PCH has
pci_dev_t spi_bdf;
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
if (device_is_on_pci_bus(bus)) {
- struct pci_child_platdata *pplat;
+ struct pci_child_plat *pplat;
- pplat = dev_get_parent_platdata(bus);
+ pplat = dev_get_parent_plat(bus);
spi_bdf = pplat->devfn;
} else {
enum ich_version ich_version;
offsetp);
}
#else
- struct ich_spi_platdata *plat = dev_get_platdata(bus);
+ struct ich_spi_plat *plat = dev_get_plat(bus);
/*
* We cannot rely on plat->bdf being set up yet since this method can
static int ich_protect_lockdown(struct udevice *dev)
{
- struct ich_spi_platdata *plat = dev_get_platdata(dev);
+ struct ich_spi_plat *plat = dev_get_plat(dev);
struct ich_spi_priv *priv = dev_get_priv(dev);
int ret = -ENOSYS;
}
static int ich_init_controller(struct udevice *dev,
- struct ich_spi_platdata *plat,
+ struct ich_spi_plat *plat,
struct ich_spi_priv *ctlr)
{
if (spl_phase() == PHASE_TPL) {
- struct ich_spi_platdata *plat = dev_get_platdata(dev);
+ struct ich_spi_plat *plat = dev_get_plat(dev);
int ret;
ret = fast_spi_early_init(plat->bdf, plat->mmio_base);
static int ich_spi_probe(struct udevice *dev)
{
- struct ich_spi_platdata *plat = dev_get_platdata(dev);
+ struct ich_spi_plat *plat = dev_get_plat(dev);
struct ich_spi_priv *priv = dev_get_priv(dev);
int ret;
static int ich_spi_child_pre_probe(struct udevice *dev)
{
struct udevice *bus = dev_get_parent(dev);
- struct ich_spi_platdata *plat = dev_get_platdata(bus);
+ struct ich_spi_plat *plat = dev_get_plat(bus);
struct ich_spi_priv *priv = dev_get_priv(bus);
struct spi_slave *slave = dev_get_parent_priv(dev);
return 0;
}
-static int ich_spi_ofdata_to_platdata(struct udevice *dev)
+static int ich_spi_of_to_plat(struct udevice *dev)
{
- struct ich_spi_platdata *plat = dev_get_platdata(dev);
+ struct ich_spi_plat *plat = dev_get_plat(dev);
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct ich_spi_priv *priv = dev_get_priv(dev);
.id = UCLASS_SPI,
.of_match = ich_spi_ids,
.ops = &ich_spi_ops,
- .ofdata_to_platdata = ich_spi_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct ich_spi_platdata),
- .priv_auto_alloc_size = sizeof(struct ich_spi_priv),
+ .of_to_plat = ich_spi_of_to_plat,
+ .plat_auto = sizeof(struct ich_spi_plat),
+ .priv_auto = sizeof(struct ich_spi_priv),
.child_pre_probe = ich_spi_child_pre_probe,
.probe = ich_spi_probe,
.remove = ich_spi_remove,
bool is_errata_50mhz_ac;
};
-struct mvebu_spi_platdata {
+struct mvebu_spi_plat {
struct kwspi_registers *spireg;
bool is_errata_50mhz_ac;
};
static int mvebu_spi_set_speed(struct udevice *bus, uint hz)
{
- struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
+ struct mvebu_spi_plat *plat = dev_get_plat(bus);
struct kwspi_registers *reg = plat->spireg;
u32 data;
static void mvebu_spi_50mhz_ac_timing_erratum(struct udevice *bus, uint mode)
{
- struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
+ struct mvebu_spi_plat *plat = dev_get_plat(bus);
struct kwspi_registers *reg = plat->spireg;
u32 data;
static int mvebu_spi_set_mode(struct udevice *bus, uint mode)
{
- struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
+ struct mvebu_spi_plat *plat = dev_get_plat(bus);
struct kwspi_registers *reg = plat->spireg;
u32 data = readl(®->cfg);
const void *dout, void *din, unsigned long flags)
{
struct udevice *bus = dev->parent;
- struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
+ struct mvebu_spi_plat *plat = dev_get_plat(bus);
return _spi_xfer(plat->spireg, bitlen, dout, din, flags);
}
static int mvebu_spi_claim_bus(struct udevice *dev)
{
struct udevice *bus = dev->parent;
- struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
+ struct mvebu_spi_plat *plat = dev_get_plat(bus);
/* Configure the chip-select in the CTRL register */
clrsetbits_le32(&plat->spireg->ctrl,
static int mvebu_spi_probe(struct udevice *bus)
{
- struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
+ struct mvebu_spi_plat *plat = dev_get_plat(bus);
struct kwspi_registers *reg = plat->spireg;
writel(KWSPI_SMEMRDY, ®->ctrl);
return 0;
}
-static int mvebu_spi_ofdata_to_platdata(struct udevice *bus)
+static int mvebu_spi_of_to_plat(struct udevice *bus)
{
- struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
+ struct mvebu_spi_plat *plat = dev_get_plat(bus);
const struct mvebu_spi_dev *drvdata =
(struct mvebu_spi_dev *)dev_get_driver_data(bus);
.id = UCLASS_SPI,
.of_match = mvebu_spi_ids,
.ops = &mvebu_spi_ops,
- .ofdata_to_platdata = mvebu_spi_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct mvebu_spi_platdata),
- .priv_auto_alloc_size = sizeof(struct mvebu_spi_priv),
+ .of_to_plat = mvebu_spi_of_to_plat,
+ .plat_auto = sizeof(struct mvebu_spi_plat),
+ .priv_auto = sizeof(struct mvebu_spi_priv),
.probe = mvebu_spi_probe,
};
.of_match = meson_spifc_ids,
.ops = &meson_spifc_ops,
.probe = meson_spifc_probe,
- .priv_auto_alloc_size = sizeof(struct meson_spifc_priv),
+ .priv_auto = sizeof(struct meson_spifc_priv),
};
#define SPI_TIMEOUT 1000
-static int mpc8xxx_spi_ofdata_to_platdata(struct udevice *dev)
+static int mpc8xxx_spi_of_to_plat(struct udevice *dev)
{
struct mpc8xxx_priv *priv = dev_get_priv(dev);
struct clk clk;
static void mpc8xxx_spi_cs_activate(struct udevice *dev)
{
struct mpc8xxx_priv *priv = dev_get_priv(dev->parent);
- struct dm_spi_slave_platdata *platdata = dev_get_parent_platdata(dev);
+ struct dm_spi_slave_plat *plat = dev_get_parent_plat(dev);
- dm_gpio_set_value(&priv->gpios[platdata->cs], 1);
+ dm_gpio_set_value(&priv->gpios[plat->cs], 1);
}
static void mpc8xxx_spi_cs_deactivate(struct udevice *dev)
{
struct mpc8xxx_priv *priv = dev_get_priv(dev->parent);
- struct dm_spi_slave_platdata *platdata = dev_get_parent_platdata(dev);
+ struct dm_spi_slave_plat *plat = dev_get_parent_plat(dev);
- dm_gpio_set_value(&priv->gpios[platdata->cs], 0);
+ dm_gpio_set_value(&priv->gpios[plat->cs], 0);
}
static int mpc8xxx_spi_xfer(struct udevice *dev, uint bitlen,
struct udevice *bus = dev->parent;
struct mpc8xxx_priv *priv = dev_get_priv(bus);
spi8xxx_t *spi = priv->spi;
- struct dm_spi_slave_platdata *platdata = dev_get_parent_platdata(dev);
+ struct dm_spi_slave_plat *plat = dev_get_parent_plat(dev);
u32 tmpdin = 0, tmpdout = 0, n;
const u8 *cout = dout;
u8 *cin = din;
debug("%s: slave %s:%u dout %08X din %08X bitlen %u\n", __func__,
- bus->name, platdata->cs, (uint)dout, (uint)din, bitlen);
- if (platdata->cs >= priv->cs_count) {
+ bus->name, plat->cs, (uint)dout, (uint)din, bitlen);
+ if (plat->cs >= priv->cs_count) {
dev_err(dev, "chip select index %d too large (cs_count=%d)\n",
- platdata->cs, priv->cs_count);
+ plat->cs, priv->cs_count);
return -EINVAL;
}
if (bitlen % 8) {
.id = UCLASS_SPI,
.of_match = mpc8xxx_spi_ids,
.ops = &mpc8xxx_spi_ops,
- .ofdata_to_platdata = mpc8xxx_spi_ofdata_to_platdata,
+ .of_to_plat = mpc8xxx_spi_of_to_plat,
.probe = mpc8xxx_spi_probe,
- .priv_auto_alloc_size = sizeof(struct mpc8xxx_priv),
+ .priv_auto = sizeof(struct mpc8xxx_priv),
};
const void *dout, void *din, unsigned long flags)
{
struct udevice *bus = dev_get_parent(dev);
- struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev);
+ struct dm_spi_slave_plat *plat = dev_get_parent_plat(dev);
struct mscc_bb_priv *priv = dev_get_priv(bus);
u32 i, count;
const u8 *txd = dout;
.id = UCLASS_SPI,
.of_match = mscc_bb_ids,
.ops = &mscc_bb_ops,
- .priv_auto_alloc_size = sizeof(struct mscc_bb_priv),
+ .priv_auto = sizeof(struct mscc_bb_priv),
.probe = mscc_bb_spi_probe,
};
.id = UCLASS_SPI,
.of_match = mt7621_spi_ids,
.ops = &mt7621_spi_ops,
- .priv_auto_alloc_size = sizeof(struct mt7621_spi),
+ .priv_auto = sizeof(struct mt7621_spi),
.probe = mt7621_spi_probe,
};
.id = UCLASS_SPI,
.of_match = mtk_snfi_spi_ids,
.ops = &mtk_snfi_spi_ops,
- .priv_auto_alloc_size = sizeof(struct mtk_snfi_priv),
+ .priv_auto = sizeof(struct mtk_snfi_priv),
.probe = mtk_snfi_spi_probe,
};
u32 din; /* 0x1060c */
};
-struct mvebu_spi_platdata {
+struct mvebu_spi_plat {
struct spi_reg *spireg;
struct clk clk;
struct gpio_desc cs_gpios[MAX_CS_COUNT];
};
-static void spi_cs_activate(struct mvebu_spi_platdata *plat, int cs)
+static void spi_cs_activate(struct mvebu_spi_plat *plat, int cs)
{
if (CONFIG_IS_ENABLED(DM_GPIO) && dm_gpio_is_valid(&plat->cs_gpios[cs]))
dm_gpio_set_value(&plat->cs_gpios[cs], 1);
setbits_le32(&plat->spireg->ctrl, MVEBU_SPI_A3700_SPI_EN_0 << cs);
}
-static void spi_cs_deactivate(struct mvebu_spi_platdata *plat, int cs)
+static void spi_cs_deactivate(struct mvebu_spi_plat *plat, int cs)
{
if (CONFIG_IS_ENABLED(DM_GPIO) && dm_gpio_is_valid(&plat->cs_gpios[cs]))
dm_gpio_set_value(&plat->cs_gpios[cs], 0);
const void *dout, void *din, unsigned long flags)
{
struct udevice *bus = dev->parent;
- struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
+ struct mvebu_spi_plat *plat = dev_get_plat(bus);
struct spi_reg *reg = plat->spireg;
unsigned int bytelen;
int ret;
static int mvebu_spi_set_speed(struct udevice *bus, uint hz)
{
- struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
+ struct mvebu_spi_plat *plat = dev_get_plat(bus);
struct spi_reg *reg = plat->spireg;
u32 data, prescale;
static int mvebu_spi_set_mode(struct udevice *bus, uint mode)
{
- struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
+ struct mvebu_spi_plat *plat = dev_get_plat(bus);
struct spi_reg *reg = plat->spireg;
/*
static int mvebu_spi_probe(struct udevice *bus)
{
- struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
+ struct mvebu_spi_plat *plat = dev_get_plat(bus);
struct spi_reg *reg = plat->spireg;
u32 data;
int ret;
return 0;
}
-static int mvebu_spi_ofdata_to_platdata(struct udevice *bus)
+static int mvebu_spi_of_to_plat(struct udevice *bus)
{
- struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
+ struct mvebu_spi_plat *plat = dev_get_plat(bus);
int ret;
plat->spireg = dev_read_addr_ptr(bus);
static int mvebu_spi_remove(struct udevice *bus)
{
- struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
+ struct mvebu_spi_plat *plat = dev_get_plat(bus);
clk_free(&plat->clk);
.id = UCLASS_SPI,
.of_match = mvebu_spi_ids,
.ops = &mvebu_spi_ops,
- .ofdata_to_platdata = mvebu_spi_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct mvebu_spi_platdata),
+ .of_to_plat = mvebu_spi_of_to_plat,
+ .plat_auto = sizeof(struct mvebu_spi_plat),
.probe = mvebu_spi_probe,
.remove = mvebu_spi_remove,
};
{
#if CONFIG_IS_ENABLED(DM_SPI)
struct udevice *dev = mxcs->dev;
- struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
u32 cs = slave_plat->cs;
{
#if CONFIG_IS_ENABLED(DM_SPI)
struct udevice *dev = mxcs->dev;
- struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
u32 cs = slave_plat->cs;
static int mxc_spi_probe(struct udevice *bus)
{
- struct mxc_spi_slave *mxcs = dev_get_platdata(bus);
+ struct mxc_spi_slave *mxcs = dev_get_plat(bus);
int node = dev_of_offset(bus);
const void *blob = gd->fdt_blob;
int ret;
static int mxc_spi_xfer(struct udevice *dev, unsigned int bitlen,
const void *dout, void *din, unsigned long flags)
{
- struct mxc_spi_slave *mxcs = dev_get_platdata(dev->parent);
+ struct mxc_spi_slave *mxcs = dev_get_plat(dev->parent);
return mxc_spi_xfer_internal(mxcs, bitlen, dout, din, flags);
static int mxc_spi_claim_bus(struct udevice *dev)
{
- struct mxc_spi_slave *mxcs = dev_get_platdata(dev->parent);
- struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+ struct mxc_spi_slave *mxcs = dev_get_plat(dev->parent);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
mxcs->dev = dev;
static int mxc_spi_set_mode(struct udevice *bus, uint mode)
{
- struct mxc_spi_slave *mxcs = dev_get_platdata(bus);
+ struct mxc_spi_slave *mxcs = dev_get_plat(bus);
mxcs->mode = mode;
mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;
.id = UCLASS_SPI,
.of_match = mxc_spi_ids,
.ops = &mxc_spi_ops,
- .platdata_auto_alloc_size = sizeof(struct mxc_spi_slave),
+ .plat_auto = sizeof(struct mxc_spi_slave),
.probe = mxc_spi_probe,
};
#endif
#define MXS_SSP_IMX23_CLKID_SSP0 33
#define MXS_SSP_IMX28_CLKID_SSP0 46
-struct mxs_spi_platdata {
+struct mxs_spi_plat {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct dtd_fsl_imx23_spi dtplat;
#endif
static int mxs_spi_probe(struct udevice *bus)
{
- struct mxs_spi_platdata *plat = dev_get_platdata(bus);
+ struct mxs_spi_plat *plat = dev_get_plat(bus);
struct mxs_spi_priv *priv = dev_get_priv(bus);
int ret;
};
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
-static int mxs_ofdata_to_platdata(struct udevice *bus)
+static int mxs_of_to_plat(struct udevice *bus)
{
- struct mxs_spi_platdata *plat = bus->platdata;
+ struct mxs_spi_plat *plat = bus->plat;
u32 prop[2];
int ret;
.id = UCLASS_SPI,
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
.of_match = mxs_spi_ids,
- .ofdata_to_platdata = mxs_ofdata_to_platdata,
+ .of_to_plat = mxs_of_to_plat,
#endif
- .platdata_auto_alloc_size = sizeof(struct mxs_spi_platdata),
+ .plat_auto = sizeof(struct mxs_spi_plat),
.ops = &mxs_spi_ops,
- .priv_auto_alloc_size = sizeof(struct mxs_spi_priv),
+ .priv_auto = sizeof(struct mxs_spi_priv),
.probe = mxs_spi_probe,
};
{
struct nxp_fspi *f;
struct udevice *bus;
- struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
bus = dev->parent;
f = dev_get_priv(bus);
return 0;
}
-static int nxp_fspi_ofdata_to_platdata(struct udevice *bus)
+static int nxp_fspi_of_to_plat(struct udevice *bus)
{
struct nxp_fspi *f = dev_get_priv(bus);
#if CONFIG_IS_ENABLED(CLK)
.id = UCLASS_SPI,
.of_match = nxp_fspi_ids,
.ops = &nxp_fspi_ops,
- .ofdata_to_platdata = nxp_fspi_ofdata_to_platdata,
- .priv_auto_alloc_size = sizeof(struct nxp_fspi),
+ .of_to_plat = nxp_fspi_of_to_plat,
+ .priv_auto = sizeof(struct nxp_fspi),
.probe = nxp_fspi_probe,
};
static u64 octeon_spi_set_mpicfg(struct udevice *dev)
{
- struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
+ struct dm_spi_slave_plat *slave = dev_get_parent_plat(dev);
struct udevice *bus = dev_get_parent(dev);
struct octeon_spi *priv = dev_get_priv(bus);
u64 mpi_cfg;
.id = UCLASS_SPI,
.of_match = octeon_spi_ids,
.probe = octeon_spi_probe,
- .priv_auto_alloc_size = sizeof(struct octeon_spi),
+ .priv_auto = sizeof(struct octeon_spi),
.ops = &octeon_spi_ops,
};
{
struct udevice *bus = dev->parent;
struct omap3_spi_priv *priv = dev_get_priv(bus);
- struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
priv->cs = slave_plat->cs;
priv->freq = slave_plat->max_hz;
{
struct udevice *bus = dev->parent;
struct omap3_spi_priv *priv = dev_get_priv(bus);
- struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
priv->cs = slave_plat->cs;
priv->wordlen = wordlen;
static int omap3_spi_probe(struct udevice *dev)
{
struct omap3_spi_priv *priv = dev_get_priv(dev);
- struct omap3_spi_plat *plat = dev_get_platdata(dev);
+ struct omap3_spi_plat *plat = dev_get_plat(dev);
priv->regs = plat->regs;
priv->pin_dir = plat->pin_dir;
.regs_offset = OMAP4_MCSPI_REG_OFFSET,
};
-static int omap3_spi_ofdata_to_platdata(struct udevice *dev)
+static int omap3_spi_of_to_plat(struct udevice *dev)
{
struct omap2_mcspi_platform_config *data =
(struct omap2_mcspi_platform_config *)dev_get_driver_data(dev);
- struct omap3_spi_plat *plat = dev_get_platdata(dev);
+ struct omap3_spi_plat *plat = dev_get_plat(dev);
plat->regs = (struct mcspi *)(dev_read_addr(dev) + data->regs_offset);
.flags = DM_FLAG_PRE_RELOC,
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
.of_match = omap3_spi_ids,
- .ofdata_to_platdata = omap3_spi_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct omap3_spi_plat),
+ .of_to_plat = omap3_spi_of_to_plat,
+ .plat_auto = sizeof(struct omap3_spi_plat),
#endif
.probe = omap3_spi_probe,
.ops = &omap3_spi_ops,
- .priv_auto_alloc_size = sizeof(struct omap3_spi_priv),
+ .priv_auto = sizeof(struct omap3_spi_priv),
};
const void *tx_buf, void *rx_buf,
unsigned long flags)
{
- struct dm_spi_slave_platdata *slave_plat;
+ struct dm_spi_slave_plat *slave_plat;
struct udevice *bus = slave->parent;
struct pic32_spi_priv *priv;
int len = bitlen / 8;
ulong tbase;
priv = dev_get_priv(bus);
- slave_plat = dev_get_parent_platdata(slave);
+ slave_plat = dev_get_parent_plat(slave);
debug("spi_xfer: bus:%i cs:%i flags:%lx\n",
bus->seq, slave_plat->cs, flags);
.id = UCLASS_SPI,
.of_match = pic32_spi_ids,
.ops = &pic32_spi_ops,
- .priv_auto_alloc_size = sizeof(struct pic32_spi_priv),
+ .priv_auto = sizeof(struct pic32_spi_priv),
.probe = pic32_spi_probe,
};
static int pl022_spi_probe(struct udevice *bus)
{
- struct pl022_spi_pdata *plat = dev_get_platdata(bus);
+ struct pl022_spi_pdata *plat = dev_get_plat(bus);
struct pl022_spi_slave *ps = dev_get_priv(bus);
ps->base = ioremap(plat->addr, plat->size);
};
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
-static int pl022_spi_ofdata_to_platdata(struct udevice *bus)
+static int pl022_spi_of_to_plat(struct udevice *bus)
{
- struct pl022_spi_pdata *plat = bus->platdata;
+ struct pl022_spi_pdata *plat = bus->plat;
const void *fdt = gd->fdt_blob;
int node = dev_of_offset(bus);
struct clk clkdev;
.id = UCLASS_SPI,
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
.of_match = pl022_spi_ids,
- .ofdata_to_platdata = pl022_spi_ofdata_to_platdata,
+ .of_to_plat = pl022_spi_of_to_plat,
#endif
.ops = &pl022_spi_ops,
- .platdata_auto_alloc_size = sizeof(struct pl022_spi_pdata),
- .priv_auto_alloc_size = sizeof(struct pl022_spi_slave),
+ .plat_auto = sizeof(struct pl022_spi_pdata),
+ .priv_auto = sizeof(struct pl022_spi_slave),
.probe = pl022_spi_probe,
};
DECLARE_GLOBAL_DATA_PTR;
-struct rpc_spi_platdata {
+struct rpc_spi_plat {
fdt_addr_t regs;
fdt_addr_t extr;
s32 freq; /* Default clock freq, -1 for none */
static int rpc_spi_probe(struct udevice *dev)
{
- struct rpc_spi_platdata *plat = dev_get_platdata(dev);
+ struct rpc_spi_plat *plat = dev_get_plat(dev);
struct rpc_spi_priv *priv = dev_get_priv(dev);
priv->regs = plat->regs;
return 0;
}
-static int rpc_spi_ofdata_to_platdata(struct udevice *bus)
+static int rpc_spi_of_to_plat(struct udevice *bus)
{
- struct rpc_spi_platdata *plat = dev_get_platdata(bus);
+ struct rpc_spi_plat *plat = dev_get_plat(bus);
plat->regs = dev_read_addr_index(bus, 0);
plat->extr = dev_read_addr_index(bus, 1);
.id = UCLASS_SPI,
.of_match = rpc_spi_ids,
.ops = &rpc_spi_ops,
- .ofdata_to_platdata = rpc_spi_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct rpc_spi_platdata),
- .priv_auto_alloc_size = sizeof(struct rpc_spi_priv),
+ .of_to_plat = rpc_spi_of_to_plat,
+ .plat_auto = sizeof(struct rpc_spi_plat),
+ .priv_auto = sizeof(struct rpc_spi_priv),
.bind = rpc_spi_bind,
.probe = rpc_spi_probe,
};
bool master_manages_fifo;
};
-struct rockchip_spi_platdata {
+struct rockchip_spi_plat {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct dtd_rockchip_rk3288_spi of_plat;
#endif
static void spi_cs_activate(struct udevice *dev, uint cs)
{
struct udevice *bus = dev->parent;
- struct rockchip_spi_platdata *plat = bus->platdata;
+ struct rockchip_spi_plat *plat = bus->plat;
struct rockchip_spi_priv *priv = dev_get_priv(bus);
struct rockchip_spi *regs = priv->regs;
static void spi_cs_deactivate(struct udevice *dev, uint cs)
{
struct udevice *bus = dev->parent;
- struct rockchip_spi_platdata *plat = bus->platdata;
+ struct rockchip_spi_plat *plat = bus->plat;
struct rockchip_spi_priv *priv = dev_get_priv(bus);
struct rockchip_spi *regs = priv->regs;
}
#if CONFIG_IS_ENABLED(OF_PLATDATA)
-static int conv_of_platdata(struct udevice *dev)
+static int conv_of_plat(struct udevice *dev)
{
- struct rockchip_spi_platdata *plat = dev->platdata;
+ struct rockchip_spi_plat *plat = dev->plat;
struct dtd_rockchip_rk3288_spi *dtplat = &plat->of_plat;
struct rockchip_spi_priv *priv = dev_get_priv(dev);
int ret;
}
#endif
-static int rockchip_spi_ofdata_to_platdata(struct udevice *bus)
+static int rockchip_spi_of_to_plat(struct udevice *bus)
{
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
- struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
+ struct rockchip_spi_plat *plat = dev_get_plat(bus);
struct rockchip_spi_priv *priv = dev_get_priv(bus);
int ret;
static int rockchip_spi_probe(struct udevice *bus)
{
- struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
+ struct rockchip_spi_plat *plat = dev_get_plat(bus);
struct rockchip_spi_priv *priv = dev_get_priv(bus);
int ret;
debug("%s: probe\n", __func__);
#if CONFIG_IS_ENABLED(OF_PLATDATA)
- ret = conv_of_platdata(bus);
+ ret = conv_of_plat(bus);
if (ret)
return ret;
#endif
struct udevice *bus = dev->parent;
struct rockchip_spi_priv *priv = dev_get_priv(bus);
struct rockchip_spi *regs = priv->regs;
- struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
int len = bitlen >> 3;
const u8 *out = dout;
u8 *in = din;
.id = UCLASS_SPI,
.of_match = rockchip_spi_ids,
.ops = &rockchip_spi_ops,
- .ofdata_to_platdata = rockchip_spi_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct rockchip_spi_platdata),
- .priv_auto_alloc_size = sizeof(struct rockchip_spi_priv),
+ .of_to_plat = rockchip_spi_of_to_plat,
+ .plat_auto = sizeof(struct rockchip_spi_plat),
+ .priv_auto = sizeof(struct rockchip_spi_priv),
.probe = rockchip_spi_probe,
};
const void *dout, void *din, unsigned long flags)
{
struct udevice *bus = dev->parent;
- struct sh_qspi_slave *ss = dev_get_platdata(bus);
+ struct sh_qspi_slave *ss = dev_get_plat(bus);
return sh_qspi_xfer_common(ss, bitlen, dout, din, flags);
}
static int sh_qspi_probe(struct udevice *dev)
{
- struct sh_qspi_slave *ss = dev_get_platdata(dev);
+ struct sh_qspi_slave *ss = dev_get_plat(dev);
sh_qspi_init(ss);
return 0;
}
-static int sh_qspi_ofdata_to_platdata(struct udevice *dev)
+static int sh_qspi_of_to_plat(struct udevice *dev)
{
- struct sh_qspi_slave *plat = dev_get_platdata(dev);
+ struct sh_qspi_slave *plat = dev_get_plat(dev);
plat->regs = (struct sh_qspi_regs *)dev_read_addr(dev);
.id = UCLASS_SPI,
.of_match = sh_qspi_ids,
.ops = &sh_qspi_ops,
- .ofdata_to_platdata = sh_qspi_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct sh_qspi_slave),
+ .of_to_plat = sh_qspi_of_to_plat,
+ .plat_auto = sizeof(struct sh_qspi_slave),
.probe = sh_qspi_probe,
};
#endif
DECLARE_GLOBAL_DATA_PTR;
-struct soft_spi_platdata {
+struct soft_spi_plat {
struct gpio_desc cs;
struct gpio_desc sclk;
struct gpio_desc mosi;
static int soft_spi_scl(struct udevice *dev, int bit)
{
struct udevice *bus = dev_get_parent(dev);
- struct soft_spi_platdata *plat = dev_get_platdata(bus);
+ struct soft_spi_plat *plat = dev_get_plat(bus);
dm_gpio_set_value(&plat->sclk, bit);
static int soft_spi_sda(struct udevice *dev, int bit)
{
struct udevice *bus = dev_get_parent(dev);
- struct soft_spi_platdata *plat = dev_get_platdata(bus);
+ struct soft_spi_plat *plat = dev_get_plat(bus);
dm_gpio_set_value(&plat->mosi, bit);
{
struct udevice *bus = dev_get_parent(dev);
struct soft_spi_priv *priv = dev_get_priv(bus);
- struct soft_spi_platdata *plat = dev_get_platdata(bus);
+ struct soft_spi_plat *plat = dev_get_plat(bus);
int cidle = !!(priv->mode & SPI_CPOL);
dm_gpio_set_value(&plat->cs, 0);
static int soft_spi_cs_deactivate(struct udevice *dev)
{
struct udevice *bus = dev_get_parent(dev);
- struct soft_spi_platdata *plat = dev_get_platdata(bus);
+ struct soft_spi_plat *plat = dev_get_plat(bus);
dm_gpio_set_value(&plat->cs, 0);
{
struct udevice *bus = dev_get_parent(dev);
struct soft_spi_priv *priv = dev_get_priv(bus);
- struct soft_spi_platdata *plat = dev_get_platdata(bus);
+ struct soft_spi_plat *plat = dev_get_plat(bus);
uchar tmpdin = 0;
uchar tmpdout = 0;
const u8 *txd = dout;
.set_mode = soft_spi_set_mode,
};
-static int soft_spi_ofdata_to_platdata(struct udevice *dev)
+static int soft_spi_of_to_plat(struct udevice *dev)
{
- struct soft_spi_platdata *plat = dev->platdata;
+ struct soft_spi_plat *plat = dev->plat;
const void *blob = gd->fdt_blob;
int node = dev_of_offset(dev);
static int soft_spi_probe(struct udevice *dev)
{
struct spi_slave *slave = dev_get_parent_priv(dev);
- struct soft_spi_platdata *plat = dev->platdata;
+ struct soft_spi_plat *plat = dev->plat;
int cs_flags, clk_flags;
int ret;
.id = UCLASS_SPI,
.of_match = soft_spi_ids,
.ops = &soft_spi_ops,
- .ofdata_to_platdata = soft_spi_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct soft_spi_platdata),
- .priv_auto_alloc_size = sizeof(struct soft_spi_priv),
+ .of_to_plat = soft_spi_of_to_plat,
+ .plat_auto = sizeof(struct soft_spi_plat),
+ .priv_auto = sizeof(struct soft_spi_priv),
.probe = soft_spi_probe,
};
const void *dout, void *din, unsigned long flags)
{
struct udevice *bus = dev_get_parent(dev);
- struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
unsigned int len;
const u8 *txp = dout;
u8 *rxp = din;
.id = UCLASS_SPI,
.of_match = qup_spi_ids,
.ops = &qup_spi_ops,
- .priv_auto_alloc_size = sizeof(struct qup_spi_priv),
+ .priv_auto = sizeof(struct qup_spi_priv),
.probe = qup_spi_probe,
};
};
static void sifive_spi_prep_device(struct sifive_spi *spi,
- struct dm_spi_slave_platdata *slave_plat)
+ struct dm_spi_slave_plat *slave_plat)
{
/* Update the chip select polarity */
if (slave_plat->mode & SPI_CS_HIGH)
}
static int sifive_spi_set_cs(struct sifive_spi *spi,
- struct dm_spi_slave_platdata *slave_plat)
+ struct dm_spi_slave_plat *slave_plat)
{
u32 cs_mode = SIFIVE_SPI_CSMODE_MODE_HOLD;
}
static void sifive_spi_prep_transfer(struct sifive_spi *spi,
- struct dm_spi_slave_platdata *slave_plat,
+ struct dm_spi_slave_plat *slave_plat,
u8 *rx_ptr)
{
u32 cr;
{
struct udevice *bus = dev->parent;
struct sifive_spi *spi = dev_get_priv(bus);
- struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
const u8 *tx_ptr = dout;
u8 *rx_ptr = din;
u32 remaining_len;
.id = UCLASS_SPI,
.of_match = sifive_spi_ids,
.ops = &sifive_spi_ops,
- .priv_auto_alloc_size = sizeof(struct sifive_spi),
+ .priv_auto = sizeof(struct sifive_spi),
.probe = sifive_spi_probe,
};
bool has_burst_ctl;
};
-struct sun4i_spi_platdata {
+struct sun4i_spi_plat {
struct sun4i_spi_variant *variant;
u32 base;
u32 max_hz;
{
struct udevice *bus = dev->parent;
struct sun4i_spi_priv *priv = dev_get_priv(bus);
- struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
u32 len = bitlen / 8;
u32 rx_fifocnt;
static int sun4i_spi_set_speed(struct udevice *dev, uint speed)
{
- struct sun4i_spi_platdata *plat = dev_get_platdata(dev);
+ struct sun4i_spi_plat *plat = dev_get_plat(dev);
struct sun4i_spi_priv *priv = dev_get_priv(dev);
unsigned int div;
u32 reg;
static int sun4i_spi_probe(struct udevice *bus)
{
- struct sun4i_spi_platdata *plat = dev_get_platdata(bus);
+ struct sun4i_spi_plat *plat = dev_get_plat(bus);
struct sun4i_spi_priv *priv = dev_get_priv(bus);
int ret;
return 0;
}
-static int sun4i_spi_ofdata_to_platdata(struct udevice *bus)
+static int sun4i_spi_of_to_plat(struct udevice *bus)
{
- struct sun4i_spi_platdata *plat = dev_get_platdata(bus);
+ struct sun4i_spi_plat *plat = dev_get_plat(bus);
int node = dev_of_offset(bus);
plat->base = dev_read_addr(bus);
.id = UCLASS_SPI,
.of_match = sun4i_spi_ids,
.ops = &sun4i_spi_ops,
- .ofdata_to_platdata = sun4i_spi_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct sun4i_spi_platdata),
- .priv_auto_alloc_size = sizeof(struct sun4i_spi_priv),
+ .of_to_plat = sun4i_spi_of_to_plat,
+ .plat_auto = sizeof(struct sun4i_spi_plat),
+ .priv_auto = sizeof(struct sun4i_spi_priv),
.probe = sun4i_spi_probe,
};
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
static int spi_child_post_bind(struct udevice *dev)
{
- struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev);
+ struct dm_spi_slave_plat *plat = dev_get_parent_plat(dev);
if (!dev_of_valid(dev))
return 0;
- return spi_slave_ofdata_to_platdata(dev, plat);
+ return spi_slave_of_to_plat(dev, plat);
}
#endif
static int spi_child_pre_probe(struct udevice *dev)
{
- struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev);
+ struct dm_spi_slave_plat *plat = dev_get_parent_plat(dev);
struct spi_slave *slave = dev_get_parent_priv(dev);
/*
int spi_chip_select(struct udevice *dev)
{
- struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev);
+ struct dm_spi_slave_plat *plat = dev_get_parent_plat(dev);
return plat ? plat->cs : -ENOENT;
}
for (device_find_first_child(bus, &dev); dev;
device_find_next_child(&dev)) {
- struct dm_spi_slave_platdata *plat;
+ struct dm_spi_slave_plat *plat;
- plat = dev_get_parent_platdata(dev);
+ plat = dev_get_parent_plat(dev);
debug("%s: plat=%p, cs=%d\n", __func__, plat, plat->cs);
if (plat->cs == cs) {
*devp = dev;
struct udevice **busp, struct spi_slave **devp)
{
struct udevice *bus, *dev;
- struct dm_spi_slave_platdata *plat;
+ struct dm_spi_slave_plat *plat;
struct spi_slave *slave;
bool created = false;
int ret;
ret);
return ret;
}
- plat = dev_get_parent_platdata(dev);
+ plat = dev_get_parent_plat(dev);
plat->cs = cs;
if (speed) {
plat->max_hz = speed;
slave->dev = NULL;
}
-int spi_slave_ofdata_to_platdata(struct udevice *dev,
- struct dm_spi_slave_platdata *plat)
+int spi_slave_of_to_plat(struct udevice *dev, struct dm_spi_slave_plat *plat)
{
int mode = 0;
int value;
#endif
.post_probe = spi_post_probe,
.child_pre_probe = spi_child_pre_probe,
- .per_device_auto_alloc_size = sizeof(struct dm_spi_bus),
- .per_child_auto_alloc_size = sizeof(struct spi_slave),
- .per_child_platdata_auto_alloc_size =
- sizeof(struct dm_spi_slave_platdata),
+ .per_device_auto = sizeof(struct dm_spi_bus),
+ .per_child_auto = sizeof(struct spi_slave),
+ .per_child_plat_auto = sizeof(struct dm_spi_slave_plat),
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
.child_post_bind = spi_child_post_bind,
#endif
static int stm32_qspi_claim_bus(struct udevice *dev)
{
struct stm32_qspi_priv *priv = dev_get_priv(dev->parent);
- struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
int slave_cs = slave_plat->cs;
if (slave_cs >= STM32_QSPI_MAX_CHIP)
.id = UCLASS_SPI,
.of_match = stm32_qspi_ids,
.ops = &stm32_qspi_ops,
- .priv_auto_alloc_size = sizeof(struct stm32_qspi_priv),
+ .priv_auto = sizeof(struct stm32_qspi_priv),
.probe = stm32_qspi_probe,
};
const void *dout, void *din, unsigned long flags)
{
struct udevice *bus = dev_get_parent(slave);
- struct dm_spi_slave_platdata *slave_plat;
+ struct dm_spi_slave_plat *slave_plat;
struct stm32_spi_priv *priv = dev_get_priv(bus);
u32 sr;
u32 ifcr = 0;
debug("%s: priv->tx_len=%d priv->rx_len=%d\n", __func__,
priv->tx_len, priv->rx_len);
- slave_plat = dev_get_parent_platdata(slave);
+ slave_plat = dev_get_parent_plat(slave);
if (flags & SPI_XFER_BEGIN)
stm32_spi_set_cs(bus, slave_plat->cs, false);
.id = UCLASS_SPI,
.of_match = stm32_spi_ids,
.ops = &stm32_spi_ops,
- .priv_auto_alloc_size = sizeof(struct stm32_spi_priv),
+ .priv_auto = sizeof(struct stm32_spi_priv),
.probe = stm32_spi_probe,
.remove = stm32_spi_remove,
};
int last_transaction_us;
};
-static int tegra114_spi_ofdata_to_platdata(struct udevice *bus)
+static int tegra114_spi_of_to_plat(struct udevice *bus)
{
- struct tegra_spi_platdata *plat = bus->platdata;
+ struct tegra_spi_plat *plat = bus->plat;
plat->base = dev_read_addr(bus);
plat->periph_id = clock_decode_periph_id(bus);
static int tegra114_spi_probe(struct udevice *bus)
{
- struct tegra_spi_platdata *plat = dev_get_platdata(bus);
+ struct tegra_spi_plat *plat = dev_get_plat(bus);
struct tegra114_spi_priv *priv = dev_get_priv(bus);
struct spi_regs *regs;
ulong rate;
static void spi_cs_activate(struct udevice *dev)
{
struct udevice *bus = dev->parent;
- struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
+ struct tegra_spi_plat *pdata = dev_get_plat(bus);
struct tegra114_spi_priv *priv = dev_get_priv(bus);
/* If it's too soon to do another transaction, wait */
static void spi_cs_deactivate(struct udevice *dev)
{
struct udevice *bus = dev->parent;
- struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
+ struct tegra_spi_plat *pdata = dev_get_plat(bus);
struct tegra114_spi_priv *priv = dev_get_priv(bus);
setbits_le32(&priv->regs->command1, SPI_CMD1_CS_SW_VAL);
static int tegra114_spi_set_speed(struct udevice *bus, uint speed)
{
- struct tegra_spi_platdata *plat = bus->platdata;
+ struct tegra_spi_plat *plat = bus->plat;
struct tegra114_spi_priv *priv = dev_get_priv(bus);
if (speed > plat->frequency)
.id = UCLASS_SPI,
.of_match = tegra114_spi_ids,
.ops = &tegra114_spi_ops,
- .ofdata_to_platdata = tegra114_spi_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata),
- .priv_auto_alloc_size = sizeof(struct tegra114_spi_priv),
+ .of_to_plat = tegra114_spi_of_to_plat,
+ .plat_auto = sizeof(struct tegra_spi_plat),
+ .priv_auto = sizeof(struct tegra114_spi_priv),
.probe = tegra114_spi_probe,
};
return 0;
}
-static int tegra20_sflash_ofdata_to_platdata(struct udevice *bus)
+static int tegra20_sflash_of_to_plat(struct udevice *bus)
{
- struct tegra_spi_platdata *plat = bus->platdata;
+ struct tegra_spi_plat *plat = bus->plat;
const void *blob = gd->fdt_blob;
int node = dev_of_offset(bus);
static int tegra20_sflash_probe(struct udevice *bus)
{
- struct tegra_spi_platdata *plat = dev_get_platdata(bus);
+ struct tegra_spi_plat *plat = dev_get_plat(bus);
struct tegra20_sflash_priv *priv = dev_get_priv(bus);
priv->regs = (struct spi_regs *)plat->base;
static void spi_cs_activate(struct udevice *dev)
{
struct udevice *bus = dev->parent;
- struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
+ struct tegra_spi_plat *pdata = dev_get_plat(bus);
struct tegra20_sflash_priv *priv = dev_get_priv(bus);
/* If it's too soon to do another transaction, wait */
static void spi_cs_deactivate(struct udevice *dev)
{
struct udevice *bus = dev->parent;
- struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
+ struct tegra_spi_plat *pdata = dev_get_plat(bus);
struct tegra20_sflash_priv *priv = dev_get_priv(bus);
/* CS is negated on Tegra, so drive a 0 to get a 1 */
static int tegra20_sflash_set_speed(struct udevice *bus, uint speed)
{
- struct tegra_spi_platdata *plat = bus->platdata;
+ struct tegra_spi_plat *plat = bus->plat;
struct tegra20_sflash_priv *priv = dev_get_priv(bus);
if (speed > plat->frequency)
.id = UCLASS_SPI,
.of_match = tegra20_sflash_ids,
.ops = &tegra20_sflash_ops,
- .ofdata_to_platdata = tegra20_sflash_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata),
- .priv_auto_alloc_size = sizeof(struct tegra20_sflash_priv),
+ .of_to_plat = tegra20_sflash_of_to_plat,
+ .plat_auto = sizeof(struct tegra_spi_plat),
+ .priv_auto = sizeof(struct tegra20_sflash_priv),
.probe = tegra20_sflash_probe,
};
struct tegra30_spi_priv *ctrl;
};
-static int tegra30_spi_ofdata_to_platdata(struct udevice *bus)
+static int tegra30_spi_of_to_plat(struct udevice *bus)
{
- struct tegra_spi_platdata *plat = bus->platdata;
+ struct tegra_spi_plat *plat = bus->plat;
const void *blob = gd->fdt_blob;
int node = dev_of_offset(bus);
static int tegra30_spi_probe(struct udevice *bus)
{
- struct tegra_spi_platdata *plat = dev_get_platdata(bus);
+ struct tegra_spi_plat *plat = dev_get_plat(bus);
struct tegra30_spi_priv *priv = dev_get_priv(bus);
priv->regs = (struct spi_regs *)plat->base;
static void spi_cs_activate(struct udevice *dev)
{
struct udevice *bus = dev->parent;
- struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
+ struct tegra_spi_plat *pdata = dev_get_plat(bus);
struct tegra30_spi_priv *priv = dev_get_priv(bus);
/* If it's too soon to do another transaction, wait */
static void spi_cs_deactivate(struct udevice *dev)
{
struct udevice *bus = dev->parent;
- struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
+ struct tegra_spi_plat *pdata = dev_get_plat(bus);
struct tegra30_spi_priv *priv = dev_get_priv(bus);
/* CS is negated on Tegra, so drive a 0 to get a 1 */
static int tegra30_spi_set_speed(struct udevice *bus, uint speed)
{
- struct tegra_spi_platdata *plat = bus->platdata;
+ struct tegra_spi_plat *plat = bus->plat;
struct tegra30_spi_priv *priv = dev_get_priv(bus);
if (speed > plat->frequency)
.id = UCLASS_SPI,
.of_match = tegra30_spi_ids,
.ops = &tegra30_spi_ops,
- .ofdata_to_platdata = tegra30_spi_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata),
- .priv_auto_alloc_size = sizeof(struct tegra30_spi_priv),
+ .of_to_plat = tegra30_spi_of_to_plat,
+ .plat_auto = sizeof(struct tegra_spi_plat),
+ .priv_auto = sizeof(struct tegra30_spi_priv),
.probe = tegra30_spi_probe,
};
int last_transaction_us;
};
-static int tegra210_qspi_ofdata_to_platdata(struct udevice *bus)
+static int tegra210_qspi_of_to_plat(struct udevice *bus)
{
- struct tegra_spi_platdata *plat = bus->platdata;
+ struct tegra_spi_plat *plat = bus->plat;
plat->base = dev_read_addr(bus);
plat->periph_id = clock_decode_periph_id(bus);
static int tegra210_qspi_probe(struct udevice *bus)
{
- struct tegra_spi_platdata *plat = dev_get_platdata(bus);
+ struct tegra_spi_plat *plat = dev_get_plat(bus);
struct tegra210_qspi_priv *priv = dev_get_priv(bus);
priv->regs = (struct qspi_regs *)plat->base;
static void spi_cs_activate(struct udevice *dev)
{
struct udevice *bus = dev->parent;
- struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
+ struct tegra_spi_plat *pdata = dev_get_plat(bus);
struct tegra210_qspi_priv *priv = dev_get_priv(bus);
/* If it's too soon to do another transaction, wait */
static void spi_cs_deactivate(struct udevice *dev)
{
struct udevice *bus = dev->parent;
- struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
+ struct tegra_spi_plat *pdata = dev_get_plat(bus);
struct tegra210_qspi_priv *priv = dev_get_priv(bus);
setbits_le32(&priv->regs->command1, QSPI_CMD1_CS_SW_VAL);
static int tegra210_qspi_set_speed(struct udevice *bus, uint speed)
{
- struct tegra_spi_platdata *plat = bus->platdata;
+ struct tegra_spi_plat *plat = bus->plat;
struct tegra210_qspi_priv *priv = dev_get_priv(bus);
if (speed > plat->frequency)
.id = UCLASS_SPI,
.of_match = tegra210_qspi_ids,
.ops = &tegra210_qspi_ops,
- .ofdata_to_platdata = tegra210_qspi_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata),
- .priv_auto_alloc_size = sizeof(struct tegra210_qspi_priv),
- .per_child_auto_alloc_size = sizeof(struct spi_slave),
+ .of_to_plat = tegra210_qspi_of_to_plat,
+ .plat_auto = sizeof(struct tegra_spi_plat),
+ .priv_auto = sizeof(struct tegra210_qspi_priv),
+ .per_child_auto = sizeof(struct spi_slave),
.probe = tegra210_qspi_probe,
};
* (C) Copyright 2014 Google, Inc
*/
-struct tegra_spi_platdata {
+struct tegra_spi_plat {
enum periph_id periph_id;
int frequency; /* Default clock frequency, -1 for none */
ulong base;
static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen,
const void *dout, void *din, unsigned long flags)
{
- struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
+ struct dm_spi_slave_plat *slave = dev_get_parent_plat(dev);
struct ti_qspi_priv *priv;
struct udevice *bus;
uint words = bitlen >> 3; /* fixed 8-bit word length */
static int ti_qspi_exec_mem_op(struct spi_slave *slave,
const struct spi_mem_op *op)
{
- struct dm_spi_slave_platdata *slave_plat;
+ struct dm_spi_slave_plat *slave_plat;
struct ti_qspi_priv *priv;
struct udevice *bus;
u32 from = 0;
bus = slave->dev->parent;
priv = dev_get_priv(bus);
- slave_plat = dev_get_parent_platdata(slave->dev);
+ slave_plat = dev_get_parent_plat(slave->dev);
/* Only optimize read path. */
if (!op->data.nbytes || op->data.dir != SPI_MEM_DATA_IN ||
static int ti_qspi_claim_bus(struct udevice *dev)
{
- struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
struct ti_qspi_priv *priv;
struct udevice *bus;
static int ti_qspi_release_bus(struct udevice *dev)
{
- struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
struct ti_qspi_priv *priv;
struct udevice *bus;
#endif
}
-static int ti_qspi_ofdata_to_platdata(struct udevice *bus)
+static int ti_qspi_of_to_plat(struct udevice *bus)
{
struct ti_qspi_priv *priv = dev_get_priv(bus);
const void *blob = gd->fdt_blob;
.id = UCLASS_SPI,
.of_match = ti_qspi_ids,
.ops = &ti_qspi_ops,
- .ofdata_to_platdata = ti_qspi_ofdata_to_platdata,
- .priv_auto_alloc_size = sizeof(struct ti_qspi_priv),
+ .of_to_plat = ti_qspi_of_to_plat,
+ .priv_auto = sizeof(struct ti_qspi_priv),
.probe = ti_qspi_probe,
};
#define SSI_CLK 50000000 /* internal I/O clock: 50MHz */
-struct uniphier_spi_platdata {
+struct uniphier_spi_plat {
void __iomem *base;
u32 frequency; /* input frequency */
u32 speed_hz;
static void spi_cs_activate(struct udevice *dev)
{
struct udevice *bus = dev->parent;
- struct uniphier_spi_platdata *plat = bus->platdata;
+ struct uniphier_spi_plat *plat = bus->plat;
struct uniphier_spi_priv *priv = dev_get_priv(bus);
ulong delay_us; /* The delay completed so far */
u32 val;
static void spi_cs_deactivate(struct udevice *dev)
{
struct udevice *bus = dev->parent;
- struct uniphier_spi_platdata *plat = bus->platdata;
+ struct uniphier_spi_plat *plat = bus->plat;
struct uniphier_spi_priv *priv = dev_get_priv(bus);
u32 val;
static int uniphier_spi_set_speed(struct udevice *bus, uint speed)
{
- struct uniphier_spi_platdata *plat = bus->platdata;
+ struct uniphier_spi_plat *plat = bus->plat;
struct uniphier_spi_priv *priv = dev_get_priv(bus);
u32 val, ckdiv;
return 0;
}
-static int uniphier_spi_ofdata_to_platdata(struct udevice *bus)
+static int uniphier_spi_of_to_plat(struct udevice *bus)
{
- struct uniphier_spi_platdata *plat = bus->platdata;
+ struct uniphier_spi_plat *plat = bus->plat;
const void *blob = gd->fdt_blob;
int node = dev_of_offset(bus);
static int uniphier_spi_probe(struct udevice *bus)
{
- struct uniphier_spi_platdata *plat = dev_get_platdata(bus);
+ struct uniphier_spi_plat *plat = dev_get_plat(bus);
struct uniphier_spi_priv *priv = dev_get_priv(bus);
priv->base = plat->base;
.id = UCLASS_SPI,
.of_match = uniphier_spi_ids,
.ops = &uniphier_spi_ops,
- .ofdata_to_platdata = uniphier_spi_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct uniphier_spi_platdata),
- .priv_auto_alloc_size = sizeof(struct uniphier_spi_priv),
+ .of_to_plat = uniphier_spi_of_to_plat,
+ .plat_auto = sizeof(struct uniphier_spi_plat),
+ .priv_auto = sizeof(struct uniphier_spi_priv),
.probe = uniphier_spi_probe,
};
struct udevice *bus = dev_get_parent(dev);
struct xilinx_spi_priv *priv = dev_get_priv(bus);
struct xilinx_spi_regs *regs = priv->regs;
- struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
const unsigned char *txp = dout;
unsigned char *rxp = din;
u32 reg;
struct udevice *bus = dev_get_parent(dev);
struct xilinx_spi_priv *priv = dev_get_priv(bus);
struct xilinx_spi_regs *regs = priv->regs;
- struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
/* assume spi core configured to do 8 bit transfers */
unsigned int bytes = bitlen / XILSPI_MAX_XFER_BITS;
const unsigned char *txp = dout;
.id = UCLASS_SPI,
.of_match = xilinx_spi_ids,
.ops = &xilinx_spi_ops,
- .priv_auto_alloc_size = sizeof(struct xilinx_spi_priv),
+ .priv_auto = sizeof(struct xilinx_spi_priv),
.probe = xilinx_spi_probe,
};
};
/* zynq qspi platform data */
-struct zynq_qspi_platdata {
+struct zynq_qspi_plat {
struct zynq_qspi_regs *regs;
u32 frequency; /* input frequency */
u32 speed_hz;
unsigned cs_change:1;
};
-static int zynq_qspi_ofdata_to_platdata(struct udevice *bus)
+static int zynq_qspi_of_to_plat(struct udevice *bus)
{
- struct zynq_qspi_platdata *plat = bus->platdata;
+ struct zynq_qspi_plat *plat = bus->plat;
const void *blob = gd->fdt_blob;
int node = dev_of_offset(bus);
static int zynq_qspi_probe(struct udevice *bus)
{
- struct zynq_qspi_platdata *plat = dev_get_platdata(bus);
+ struct zynq_qspi_plat *plat = dev_get_plat(bus);
struct zynq_qspi_priv *priv = dev_get_priv(bus);
struct clk clk;
unsigned long clock;
{
struct udevice *bus = dev->parent;
struct zynq_qspi_priv *priv = dev_get_priv(bus);
- struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
priv->cs = slave_plat->cs;
priv->tx_buf = dout;
static int zynq_qspi_set_speed(struct udevice *bus, uint speed)
{
- struct zynq_qspi_platdata *plat = bus->platdata;
+ struct zynq_qspi_plat *plat = bus->plat;
struct zynq_qspi_priv *priv = dev_get_priv(bus);
struct zynq_qspi_regs *regs = priv->regs;
uint32_t confr;
.id = UCLASS_SPI,
.of_match = zynq_qspi_ids,
.ops = &zynq_qspi_ops,
- .ofdata_to_platdata = zynq_qspi_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct zynq_qspi_platdata),
- .priv_auto_alloc_size = sizeof(struct zynq_qspi_priv),
+ .of_to_plat = zynq_qspi_of_to_plat,
+ .plat_auto = sizeof(struct zynq_qspi_plat),
+ .priv_auto = sizeof(struct zynq_qspi_priv),
.probe = zynq_qspi_probe,
};
/* zynq spi platform data */
-struct zynq_spi_platdata {
+struct zynq_spi_plat {
struct zynq_spi_regs *regs;
u32 frequency; /* input frequency */
u32 speed_hz;
u32 freq; /* required frequency */
};
-static int zynq_spi_ofdata_to_platdata(struct udevice *bus)
+static int zynq_spi_of_to_plat(struct udevice *bus)
{
- struct zynq_spi_platdata *plat = bus->platdata;
+ struct zynq_spi_plat *plat = bus->plat;
const void *blob = gd->fdt_blob;
int node = dev_of_offset(bus);
static int zynq_spi_probe(struct udevice *bus)
{
- struct zynq_spi_platdata *plat = dev_get_platdata(bus);
+ struct zynq_spi_plat *plat = dev_get_plat(bus);
struct zynq_spi_priv *priv = dev_get_priv(bus);
struct clk clk;
unsigned long clock;
static void spi_cs_activate(struct udevice *dev)
{
struct udevice *bus = dev->parent;
- struct zynq_spi_platdata *plat = bus->platdata;
+ struct zynq_spi_plat *plat = bus->plat;
struct zynq_spi_priv *priv = dev_get_priv(bus);
struct zynq_spi_regs *regs = priv->regs;
u32 cr;
static void spi_cs_deactivate(struct udevice *dev)
{
struct udevice *bus = dev->parent;
- struct zynq_spi_platdata *plat = bus->platdata;
+ struct zynq_spi_plat *plat = bus->plat;
struct zynq_spi_priv *priv = dev_get_priv(bus);
struct zynq_spi_regs *regs = priv->regs;
struct udevice *bus = dev->parent;
struct zynq_spi_priv *priv = dev_get_priv(bus);
struct zynq_spi_regs *regs = priv->regs;
- struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
u32 len = bitlen / 8;
u32 tx_len = len, rx_len = len, tx_tvl;
const u8 *tx_buf = dout;
static int zynq_spi_set_speed(struct udevice *bus, uint speed)
{
- struct zynq_spi_platdata *plat = bus->platdata;
+ struct zynq_spi_plat *plat = bus->plat;
struct zynq_spi_priv *priv = dev_get_priv(bus);
struct zynq_spi_regs *regs = priv->regs;
uint32_t confr;
.id = UCLASS_SPI,
.of_match = zynq_spi_ids,
.ops = &zynq_spi_ops,
- .ofdata_to_platdata = zynq_spi_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct zynq_spi_platdata),
- .priv_auto_alloc_size = sizeof(struct zynq_spi_priv),
+ .of_to_plat = zynq_spi_of_to_plat,
+ .plat_auto = sizeof(struct zynq_spi_plat),
+ .priv_auto = sizeof(struct zynq_spi_priv),
.probe = zynq_spi_probe,
};
DECLARE_GLOBAL_DATA_PTR;
-struct zynqmp_qspi_platdata {
+struct zynqmp_qspi_plat {
struct zynqmp_qspi_regs *regs;
struct zynqmp_qspi_dma_regs *dma_regs;
u32 frequency;
unsigned int cs_change:1;
};
-static int zynqmp_qspi_ofdata_to_platdata(struct udevice *bus)
+static int zynqmp_qspi_of_to_plat(struct udevice *bus)
{
- struct zynqmp_qspi_platdata *plat = bus->platdata;
+ struct zynqmp_qspi_plat *plat = bus->plat;
debug("%s\n", __func__);
void zynqmp_qspi_set_tapdelay(struct udevice *bus, u32 baudrateval)
{
- struct zynqmp_qspi_platdata *plat = bus->platdata;
+ struct zynqmp_qspi_plat *plat = bus->plat;
struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
struct zynqmp_qspi_regs *regs = priv->regs;
u32 tapdlybypass = 0, lpbkdlyadj = 0, datadlyadj = 0, clk_rate;
static int zynqmp_qspi_set_speed(struct udevice *bus, uint speed)
{
- struct zynqmp_qspi_platdata *plat = bus->platdata;
+ struct zynqmp_qspi_plat *plat = bus->plat;
struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
struct zynqmp_qspi_regs *regs = priv->regs;
u32 confr;
static int zynqmp_qspi_probe(struct udevice *bus)
{
- struct zynqmp_qspi_platdata *plat = dev_get_platdata(bus);
+ struct zynqmp_qspi_plat *plat = dev_get_plat(bus);
struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
struct clk clk;
unsigned long clock;
.id = UCLASS_SPI,
.of_match = zynqmp_qspi_ids,
.ops = &zynqmp_qspi_ops,
- .ofdata_to_platdata = zynqmp_qspi_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct zynqmp_qspi_platdata),
- .priv_auto_alloc_size = sizeof(struct zynqmp_qspi_priv),
+ .of_to_plat = zynqmp_qspi_of_to_plat,
+ .plat_auto = sizeof(struct zynqmp_qspi_plat),
+ .priv_auto = sizeof(struct zynqmp_qspi_priv),
.probe = zynqmp_qspi_probe,
};
.of_match = msm_spmi_ids,
.ops = &msm_spmi_ops,
.probe = msm_spmi_probe,
- .priv_auto_alloc_size = sizeof(struct msm_spmi_priv),
+ .priv_auto = sizeof(struct msm_spmi_priv),
};
.of_match = sandbox_spmi_ids,
.ops = &sandbox_spmi_ops,
.probe = sandbox_spmi_probe,
- .priv_auto_alloc_size = sizeof(struct sandbox_spmi_priv),
+ .priv_auto = sizeof(struct sandbox_spmi_priv),
};
.id = UCLASS_SYSINFO,
.of_match = sysinfo_gazerbeam_ids,
.ops = &sysinfo_gazerbeam_ops,
- .priv_auto_alloc_size = sizeof(struct sysinfo_gazerbeam_priv),
+ .priv_auto = sizeof(struct sysinfo_gazerbeam_priv),
.probe = sysinfo_gazerbeam_probe,
};
.id = UCLASS_SYSINFO,
.of_match = sysinfo_sandbox_ids,
.ops = &sysinfo_sandbox_ops,
- .priv_auto_alloc_size = sizeof(struct sysinfo_sandbox_priv),
+ .priv_auto = sizeof(struct sysinfo_sandbox_priv),
.probe = sysinfo_sandbox_probe,
};
.id = UCLASS_SYSRESET,
.ops = &poweroff_gpio_ops,
.probe = poweroff_gpio_probe,
- .priv_auto_alloc_size = sizeof(struct poweroff_gpio_info),
+ .priv_auto = sizeof(struct poweroff_gpio_info),
.of_match = poweroff_gpio_ids,
};
.id = UCLASS_SYSRESET,
.of_match = ti_sci_sysreset_of_match,
.probe = ti_sci_sysreset_probe,
- .priv_auto_alloc_size = sizeof(struct ti_sci_sysreset_data),
+ .priv_auto = sizeof(struct ti_sci_sysreset_data),
.ops = &ti_sci_sysreset_ops,
};
.name = "gpio_restart",
.of_match = led_gpio_ids,
.ops = &gpio_reboot_ops,
- .priv_auto_alloc_size = sizeof(struct gpio_reboot_priv),
+ .priv_auto = sizeof(struct gpio_reboot_priv),
.probe = gpio_reboot_probe,
};
U_BOOT_DRIVER(sysreset_octeon) = {
.id = UCLASS_SYSRESET,
.name = "octeon_sysreset",
- .priv_auto_alloc_size = sizeof(struct octeon_sysreset_data),
+ .priv_auto = sizeof(struct octeon_sysreset_data),
.ops = &octeon_sysreset,
.probe = octeon_sysreset_probe,
.of_match = octeon_sysreset_ids,
.name = "resetctl_reboot",
.of_match = resetctl_reboot_ids,
.ops = &resetctl_reboot_ops,
- .priv_auto_alloc_size = sizeof(struct resetctl_reboot_priv),
+ .priv_auto = sizeof(struct resetctl_reboot_priv),
.probe = resetctl_reboot_probe,
};
U_BOOT_DRIVER(sysreset_socfpga) = {
.id = UCLASS_SYSRESET,
.name = "socfpga_sysreset",
- .priv_auto_alloc_size = sizeof(struct socfpga_sysreset_data),
+ .priv_auto = sizeof(struct socfpga_sysreset_data),
.ops = &socfpga_sysreset,
.probe = socfpga_sysreset_probe,
};
.ops = &sti_sysreset,
.probe = sti_sysreset_probe,
.of_match = sti_sysreset_ids,
- .priv_auto_alloc_size = sizeof(struct sti_sysreset_priv),
+ .priv_auto = sizeof(struct sti_sysreset_priv),
};
.id = UCLASS_SYSRESET,
.of_match = syscon_reboot_ids,
.probe = syscon_reboot_probe,
- .priv_auto_alloc_size = sizeof(struct syscon_reboot_priv),
+ .priv_auto = sizeof(struct syscon_reboot_priv),
.ops = &syscon_reboot_ops,
};
.id = UCLASS_SYSRESET,
.of_match = wdt_reboot_ids,
.ops = &wdt_reboot_ops,
- .priv_auto_alloc_size = sizeof(struct wdt_reboot_priv),
+ .priv_auto = sizeof(struct wdt_reboot_priv),
.probe = wdt_reboot_probe,
};
#include <asm/io.h>
#include <asm/processor.h>
-struct x86_sysreset_platdata {
+struct x86_sysreset_plat {
struct udevice *pch;
};
*/
int pch_sysreset_power_off(struct udevice *dev)
{
- struct x86_sysreset_platdata *plat = dev_get_platdata(dev);
+ struct x86_sysreset_plat *plat = dev_get_plat(dev);
struct pch_pmbase_info pm;
u32 reg32;
int ret;
static int x86_sysreset_probe(struct udevice *dev)
{
- struct x86_sysreset_platdata *plat = dev_get_platdata(dev);
+ struct x86_sysreset_plat *plat = dev_get_plat(dev);
/* Locate the PCH if there is one. It isn't essential */
uclass_first_device(UCLASS_PCH, &plat->pch);
.of_match = x86_sysreset_ids,
.ops = &x86_sysreset_ops,
.probe = x86_sysreset_probe,
- .platdata_auto_alloc_size = sizeof(struct x86_sysreset_platdata),
+ .plat_auto = sizeof(struct x86_sysreset_plat),
};
static u32 do_call_with_arg(struct udevice *dev, struct optee_msg_arg *arg)
{
- struct optee_pdata *pdata = dev_get_platdata(dev);
+ struct optee_pdata *pdata = dev_get_plat(dev);
struct rpc_param param = { .a0 = OPTEE_SMC_CALL_WITH_ARG };
void *page_list = NULL;
return ERR_PTR(-EINVAL);
}
-static int optee_ofdata_to_platdata(struct udevice *dev)
+static int optee_of_to_plat(struct udevice *dev)
{
- struct optee_pdata *pdata = dev_get_platdata(dev);
+ struct optee_pdata *pdata = dev_get_plat(dev);
pdata->invoke_fn = get_invoke_func(dev);
if (IS_ERR(pdata->invoke_fn))
static int optee_probe(struct udevice *dev)
{
- struct optee_pdata *pdata = dev_get_platdata(dev);
+ struct optee_pdata *pdata = dev_get_plat(dev);
u32 sec_caps;
if (!is_optee_api(pdata->invoke_fn)) {
.name = "optee",
.id = UCLASS_TEE,
.of_match = optee_match,
- .ofdata_to_platdata = optee_ofdata_to_platdata,
+ .of_to_plat = optee_of_to_plat,
.probe = optee_probe,
.ops = &optee_ops,
- .platdata_auto_alloc_size = sizeof(struct optee_pdata),
- .priv_auto_alloc_size = sizeof(struct optee_private),
+ .plat_auto = sizeof(struct optee_pdata),
+ .priv_auto = sizeof(struct optee_private),
};
.id = UCLASS_TEE,
.of_match = sandbox_tee_match,
.ops = &sandbox_tee_ops,
- .priv_auto_alloc_size = sizeof(struct sandbox_tee_state),
+ .priv_auto = sizeof(struct sandbox_tee_state),
.probe = sandbox_tee_probe,
.remove = sandbox_tee_remove,
};
UCLASS_DRIVER(tee) = {
.id = UCLASS_TEE,
.name = "tee",
- .per_device_auto_alloc_size = sizeof(struct tee_uclass_priv),
+ .per_device_auto = sizeof(struct tee_uclass_priv),
.pre_probe = tee_pre_probe,
.pre_remove = tee_pre_remove,
};
sc_rsrc_t *sensor_rsrc = (sc_rsrc_t *)dev_get_driver_data(dev);
- struct imx_sc_thermal_plat *pdata = dev_get_platdata(dev);
+ struct imx_sc_thermal_plat *pdata = dev_get_plat(dev);
if (!temp)
return -EINVAL;
int imx_sc_thermal_get_temp(struct udevice *dev, int *temp)
{
- struct imx_sc_thermal_plat *pdata = dev_get_platdata(dev);
+ struct imx_sc_thermal_plat *pdata = dev_get_plat(dev);
int cpu_temp = 0;
int ret;
static int imx_sc_thermal_bind(struct udevice *dev)
{
- struct imx_sc_thermal_plat *pdata = dev_get_platdata(dev);
+ struct imx_sc_thermal_plat *pdata = dev_get_plat(dev);
int reg, ret;
int offset;
const char *name;
return 0;
}
-static int imx_sc_thermal_ofdata_to_platdata(struct udevice *dev)
+static int imx_sc_thermal_of_to_plat(struct udevice *dev)
{
- struct imx_sc_thermal_plat *pdata = dev_get_platdata(dev);
+ struct imx_sc_thermal_plat *pdata = dev_get_plat(dev);
struct fdtdec_phandle_args args;
const char *type;
int ret;
.of_match = imx_sc_thermal_ids,
.bind = imx_sc_thermal_bind,
.probe = imx_sc_thermal_probe,
- .ofdata_to_platdata = imx_sc_thermal_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct imx_sc_thermal_plat),
+ .of_to_plat = imx_sc_thermal_of_to_plat,
+ .plat_auto = sizeof(struct imx_sc_thermal_plat),
.flags = DM_FLAG_PRE_RELOC,
};
{
int temperature;
unsigned int reg, n_meas;
- const struct imx_thermal_plat *pdata = dev_get_platdata(dev);
+ const struct imx_thermal_plat *pdata = dev_get_plat(dev);
struct anatop_regs *anatop = (struct anatop_regs *)pdata->regs;
struct thermal_data *priv = dev_get_priv(dev);
u32 fuse = priv->fuse;
{
unsigned int fuse = ~0;
- const struct imx_thermal_plat *pdata = dev_get_platdata(dev);
+ const struct imx_thermal_plat *pdata = dev_get_plat(dev);
struct thermal_data *priv = dev_get_priv(dev);
/* Read Temperature calibration data fuse */
.id = UCLASS_THERMAL,
.ops = &imx_thermal_ops,
.probe = imx_thermal_probe,
- .priv_auto_alloc_size = sizeof(struct thermal_data),
+ .priv_auto = sizeof(struct thermal_data),
.flags = DM_FLAG_PRE_RELOC,
};
static int read_temperature(struct udevice *dev, int *temp)
{
- struct imx_tmu_plat *pdata = dev_get_platdata(dev);
+ struct imx_tmu_plat *pdata = dev_get_plat(dev);
ulong drv_data = dev_get_driver_data(dev);
u32 val;
u32 retry = 10;
int imx_tmu_get_temp(struct udevice *dev, int *temp)
{
- struct imx_tmu_plat *pdata = dev_get_platdata(dev);
+ struct imx_tmu_plat *pdata = dev_get_plat(dev);
int cpu_tmp = 0;
int ret;
int i, val, len, ret;
u32 range[4];
const fdt32_t *calibration;
- struct imx_tmu_plat *pdata = dev_get_platdata(dev);
+ struct imx_tmu_plat *pdata = dev_get_plat(dev);
ulong drv_data = dev_get_driver_data(dev);
debug("%s\n", __func__);
static void imx_tmu_init(struct udevice *dev)
{
- struct imx_tmu_plat *pdata = dev_get_platdata(dev);
+ struct imx_tmu_plat *pdata = dev_get_plat(dev);
ulong drv_data = dev_get_driver_data(dev);
debug("%s\n", __func__);
static int imx_tmu_enable_msite(struct udevice *dev)
{
- struct imx_tmu_plat *pdata = dev_get_platdata(dev);
+ struct imx_tmu_plat *pdata = dev_get_plat(dev);
ulong drv_data = dev_get_driver_data(dev);
u32 reg;
static int imx_tmu_bind(struct udevice *dev)
{
- struct imx_tmu_plat *pdata = dev_get_platdata(dev);
+ struct imx_tmu_plat *pdata = dev_get_plat(dev);
int ret;
ofnode node, offset;
const char *name;
static int imx_tmu_parse_fdt(struct udevice *dev)
{
- struct imx_tmu_plat *pdata = dev_get_platdata(dev), *p_parent_data;
+ struct imx_tmu_plat *pdata = dev_get_plat(dev), *p_parent_data;
struct ofnode_phandle_args args;
ofnode trips_np;
int ret;
return 0;
}
- p_parent_data = dev_get_platdata(dev->parent);
+ p_parent_data = dev_get_plat(dev->parent);
if (p_parent_data->zone_node)
pdata->regs = p_parent_data->regs;
static int imx_tmu_probe(struct udevice *dev)
{
- struct imx_tmu_plat *pdata = dev_get_platdata(dev);
+ struct imx_tmu_plat *pdata = dev_get_plat(dev);
int ret;
ret = imx_tmu_parse_fdt(dev);
.of_match = imx_tmu_ids,
.bind = imx_tmu_bind,
.probe = imx_tmu_probe,
- .platdata_auto_alloc_size = sizeof(struct imx_tmu_plat),
+ .plat_auto = sizeof(struct imx_tmu_plat),
.flags = DM_FLAG_PRE_RELOC,
};
.ops = &ti_thermal_ops,
.probe = ti_bandgap_probe,
.of_match = of_ti_bandgap_match,
- .priv_auto_alloc_size = sizeof(struct ti_bandgap),
+ .priv_auto = sizeof(struct ti_bandgap),
};
u32 int_mask; /* 0x38 */
};
-struct atftmr_timer_platdata {
+struct atftmr_timer_plat {
struct atftmr_timer_regs *regs;
};
static u64 atftmr_timer_get_count(struct udevice *dev)
{
- struct atftmr_timer_platdata *plat = dev->platdata;
+ struct atftmr_timer_plat *plat = dev->plat;
struct atftmr_timer_regs *const regs = plat->regs;
u32 val;
val = readl(®s->t3_counter);
static int atftmr_timer_probe(struct udevice *dev)
{
- struct atftmr_timer_platdata *plat = dev->platdata;
+ struct atftmr_timer_plat *plat = dev->plat;
struct atftmr_timer_regs *const regs = plat->regs;
u32 cr;
writel(0, ®s->t3_load);
return 0;
}
-static int atftme_timer_ofdata_to_platdata(struct udevice *dev)
+static int atftme_timer_of_to_plat(struct udevice *dev)
{
- struct atftmr_timer_platdata *plat = dev_get_platdata(dev);
+ struct atftmr_timer_plat *plat = dev_get_plat(dev);
plat->regs = map_physmem(dev_read_addr(dev),
sizeof(struct atftmr_timer_regs),
MAP_NOCACHE);
.name = "ag101p_timer",
.id = UCLASS_TIMER,
.of_match = ag101p_timer_ids,
- .ofdata_to_platdata = atftme_timer_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct atftmr_timer_platdata),
+ .of_to_plat = atftme_timer_of_to_plat,
+ .plat_auto = sizeof(struct atftmr_timer_plat),
.probe = atftmr_timer_probe,
.ops = &ag101p_timer_ops,
};
u32 snaph; /* Snapshot high */
};
-struct altera_timer_platdata {
+struct altera_timer_plat {
struct altera_timer_regs *regs;
};
static u64 altera_timer_get_count(struct udevice *dev)
{
- struct altera_timer_platdata *plat = dev->platdata;
+ struct altera_timer_plat *plat = dev->plat;
struct altera_timer_regs *const regs = plat->regs;
u32 val;
static int altera_timer_probe(struct udevice *dev)
{
- struct altera_timer_platdata *plat = dev->platdata;
+ struct altera_timer_plat *plat = dev->plat;
struct altera_timer_regs *const regs = plat->regs;
writel(0, ®s->status);
return 0;
}
-static int altera_timer_ofdata_to_platdata(struct udevice *dev)
+static int altera_timer_of_to_plat(struct udevice *dev)
{
- struct altera_timer_platdata *plat = dev_get_platdata(dev);
+ struct altera_timer_plat *plat = dev_get_plat(dev);
plat->regs = map_physmem(dev_read_addr(dev),
sizeof(struct altera_timer_regs),
.name = "altera_timer",
.id = UCLASS_TIMER,
.of_match = altera_timer_ids,
- .ofdata_to_platdata = altera_timer_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct altera_timer_platdata),
+ .of_to_plat = altera_timer_of_to_plat,
+ .plat_auto = sizeof(struct altera_timer_plat),
.probe = altera_timer_probe,
.ops = &altera_timer_ops,
};
.of_match = arc_timer_ids,
.probe = arc_timer_probe,
.ops = &arc_timer_ops,
- .priv_auto_alloc_size = sizeof(struct arc_timer_priv),
+ .priv_auto = sizeof(struct arc_timer_priv),
};
return AST_TMC_RELOAD_VAL - readl(&priv->tmc->status);
}
-static int ast_timer_ofdata_to_platdata(struct udevice *dev)
+static int ast_timer_of_to_plat(struct udevice *dev)
{
struct ast_timer_priv *priv = dev_get_priv(dev);
.id = UCLASS_TIMER,
.of_match = ast_timer_ids,
.probe = ast_timer_probe,
- .priv_auto_alloc_size = sizeof(struct ast_timer_priv),
- .ofdata_to_platdata = ast_timer_ofdata_to_platdata,
+ .priv_auto = sizeof(struct ast_timer_priv),
+ .of_to_plat = ast_timer_of_to_plat,
.ops = &ast_timer_ops,
};
u32 int_mask; /* 0x38 */
};
-struct atcpit_timer_platdata {
+struct atcpit_timer_plat {
u32 *regs;
};
static u64 atcpit_timer_get_count(struct udevice *dev)
{
- struct atcpit_timer_platdata *plat = dev_get_platdata(dev);
+ struct atcpit_timer_plat *plat = dev_get_plat(dev);
u32 val;
val = ~(REG32_TMR(CH_CNT(1))+0xffffffff);
return timer_conv_64(val);
static int atcpit_timer_probe(struct udevice *dev)
{
- struct atcpit_timer_platdata *plat = dev_get_platdata(dev);
+ struct atcpit_timer_plat *plat = dev_get_plat(dev);
REG32_TMR(CH_REL(1)) = 0xffffffff;
REG32_TMR(CH_CTL(1)) = APB_CLK|TMR_32;
REG32_TMR(CH_EN) |= CH_TMR_EN(1 , 0);
return 0;
}
-static int atcpit_timer_ofdata_to_platdata(struct udevice *dev)
+static int atcpit_timer_of_to_plat(struct udevice *dev)
{
- struct atcpit_timer_platdata *plat = dev_get_platdata(dev);
+ struct atcpit_timer_plat *plat = dev_get_plat(dev);
plat->regs = map_physmem(dev_read_addr(dev), 0x100 , MAP_NOCACHE);
return 0;
}
.name = "atcpit100_timer",
.id = UCLASS_TIMER,
.of_match = atcpit_timer_ids,
- .ofdata_to_platdata = atcpit_timer_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct atcpit_timer_platdata),
+ .of_to_plat = atcpit_timer_of_to_plat,
+ .plat_auto = sizeof(struct atcpit_timer_plat),
.probe = atcpit_timer_probe,
.ops = &atcpit_timer_ops,
};
u32 value_image;
};
-struct atmel_pit_platdata {
+struct atmel_pit_plat {
struct atmel_pit_regs *regs;
};
static u64 atmel_pit_get_count(struct udevice *dev)
{
- struct atmel_pit_platdata *plat = dev_get_platdata(dev);
+ struct atmel_pit_plat *plat = dev_get_plat(dev);
struct atmel_pit_regs *const regs = plat->regs;
u32 val = readl(®s->value_image);
static int atmel_pit_probe(struct udevice *dev)
{
- struct atmel_pit_platdata *plat = dev_get_platdata(dev);
+ struct atmel_pit_plat *plat = dev_get_plat(dev);
struct atmel_pit_regs *const regs = plat->regs;
struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct clk clk;
return 0;
}
-static int atmel_pit_ofdata_to_platdata(struct udevice *dev)
+static int atmel_pit_of_to_plat(struct udevice *dev)
{
- struct atmel_pit_platdata *plat = dev_get_platdata(dev);
+ struct atmel_pit_plat *plat = dev_get_plat(dev);
plat->regs = dev_read_addr_ptr(dev);
.name = "atmel_pit",
.id = UCLASS_TIMER,
.of_match = atmel_pit_ids,
- .ofdata_to_platdata = atmel_pit_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct atmel_pit_platdata),
+ .of_to_plat = atmel_pit_of_to_plat,
+ .plat_auto = sizeof(struct atmel_pit_plat),
.probe = atmel_pit_probe,
.ops = &atmel_pit_ops,
};
return 0;
}
-static int cadence_ttc_ofdata_to_platdata(struct udevice *dev)
+static int cadence_ttc_of_to_plat(struct udevice *dev)
{
struct cadence_ttc_priv *priv = dev_get_priv(dev);
.name = "cadence_ttc",
.id = UCLASS_TIMER,
.of_match = cadence_ttc_ids,
- .ofdata_to_platdata = cadence_ttc_ofdata_to_platdata,
- .priv_auto_alloc_size = sizeof(struct cadence_ttc_priv),
+ .of_to_plat = cadence_ttc_of_to_plat,
+ .priv_auto = sizeof(struct cadence_ttc_priv),
.probe = cadence_ttc_probe,
.ops = &cadence_ttc_ops,
};
return 0;
}
-static int dw_apb_timer_ofdata_to_platdata(struct udevice *dev)
+static int dw_apb_timer_of_to_plat(struct udevice *dev)
{
struct dw_apb_timer_priv *priv = dev_get_priv(dev);
.ops = &dw_apb_timer_ops,
.probe = dw_apb_timer_probe,
.of_match = dw_apb_timer_ids,
- .ofdata_to_platdata = dw_apb_timer_ofdata_to_platdata,
+ .of_to_plat = dw_apb_timer_of_to_plat,
.remove = dw_apb_timer_remove,
- .priv_auto_alloc_size = sizeof(struct dw_apb_timer_priv),
+ .priv_auto = sizeof(struct dw_apb_timer_priv),
};
.name = "mchp-pit64b",
.id = UCLASS_TIMER,
.of_match = mchp_pit64b_ids,
- .priv_auto_alloc_size = sizeof(struct mchp_pit64b_priv),
+ .priv_auto = sizeof(struct mchp_pit64b_priv),
.probe = mchp_pit64b_probe,
.ops = &mchp_pit64b_ops,
.flags = DM_FLAG_PRE_RELOC,
.of_match = mpc83xx_timer_ids,
.probe = mpc83xx_timer_probe,
.ops = &mpc83xx_timer_ops,
- .priv_auto_alloc_size = sizeof(struct mpc83xx_timer_priv),
+ .priv_auto = sizeof(struct mpc83xx_timer_priv),
};
.name = "mtk_timer",
.id = UCLASS_TIMER,
.of_match = mtk_timer_ids,
- .priv_auto_alloc_size = sizeof(struct mtk_timer_priv),
+ .priv_auto = sizeof(struct mtk_timer_priv),
.probe = mtk_timer_probe,
.ops = &mtk_timer_ops,
.flags = DM_FLAG_PRE_RELOC,
.name = "nomadik_mtu",
.id = UCLASS_TIMER,
.of_match = nomadik_mtu_ids,
- .priv_auto_alloc_size = sizeof(struct nomadik_mtu_priv),
+ .priv_auto = sizeof(struct nomadik_mtu_priv),
.probe = nomadik_mtu_probe,
.ops = &nomadik_mtu_ops,
};
return 0;
}
-static int omap_timer_ofdata_to_platdata(struct udevice *dev)
+static int omap_timer_of_to_plat(struct udevice *dev)
{
struct omap_timer_priv *priv = dev_get_priv(dev);
.name = "omap_timer",
.id = UCLASS_TIMER,
.of_match = omap_timer_ids,
- .ofdata_to_platdata = omap_timer_ofdata_to_platdata,
- .priv_auto_alloc_size = sizeof(struct omap_timer_priv),
+ .of_to_plat = omap_timer_of_to_plat,
+ .priv_auto = sizeof(struct omap_timer_priv),
.probe = omap_timer_probe,
.ops = &omap_timer_ops,
};
return 0;
}
-static int ostm_ofdata_to_platdata(struct udevice *dev)
+static int ostm_of_to_plat(struct udevice *dev)
{
struct ostm_priv *priv = dev_get_priv(dev);
.ops = &ostm_ops,
.probe = ostm_probe,
.of_match = ostm_ids,
- .ofdata_to_platdata = ostm_ofdata_to_platdata,
- .priv_auto_alloc_size = sizeof(struct ostm_priv),
+ .of_to_plat = ostm_of_to_plat,
+ .priv_auto = sizeof(struct ostm_priv),
};
return ~0ull - cntr;
}
-static int rockchip_clk_ofdata_to_platdata(struct udevice *dev)
+static int rockchip_clk_of_to_plat(struct udevice *dev)
{
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct rockchip_timer_priv *priv = dev_get_priv(dev);
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct rockchip_timer_priv *priv = dev_get_priv(dev);
- struct rockchip_timer_plat *plat = dev_get_platdata(dev);
+ struct rockchip_timer_plat *plat = dev_get_plat(dev);
priv->timer = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
uc_priv->clock_rate = plat->dtd.clock_frequency;
.of_match = rockchip_timer_ids,
.probe = rockchip_timer_probe,
.ops = &rockchip_timer_ops,
- .priv_auto_alloc_size = sizeof(struct rockchip_timer_priv),
+ .priv_auto = sizeof(struct rockchip_timer_priv),
#if CONFIG_IS_ENABLED(OF_PLATDATA)
- .platdata_auto_alloc_size = sizeof(struct rockchip_timer_plat),
+ .plat_auto = sizeof(struct rockchip_timer_plat),
#endif
- .ofdata_to_platdata = rockchip_clk_ofdata_to_platdata,
+ .of_to_plat = rockchip_clk_of_to_plat,
};
.name = "sti_timer",
.id = UCLASS_TIMER,
.of_match = sti_timer_ids,
- .priv_auto_alloc_size = sizeof(struct sti_timer_priv),
+ .priv_auto = sizeof(struct sti_timer_priv),
.probe = sti_timer_probe,
.ops = &sti_timer_ops,
};
.name = "stm32_timer",
.id = UCLASS_TIMER,
.of_match = stm32_timer_ids,
- .priv_auto_alloc_size = sizeof(struct stm32_timer_priv),
+ .priv_auto = sizeof(struct stm32_timer_priv),
.probe = stm32_timer_probe,
.ops = &stm32_timer_ops,
};
int timer_timebase_fallback(struct udevice *dev)
{
struct udevice *cpu;
- struct cpu_platdata *cpu_plat;
+ struct cpu_plat *cpu_plat;
struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
/* Did we get our clock rate from the device tree? */
if (!cpu)
return -ENODEV;
- cpu_plat = dev_get_parent_platdata(cpu);
+ cpu_plat = dev_get_parent_plat(cpu);
if (!cpu_plat)
return -ENODEV;
.pre_probe = timer_pre_probe,
.flags = DM_UC_FLAG_SEQ_ALIAS,
.post_probe = timer_post_probe,
- .per_device_auto_alloc_size = sizeof(struct timer_dev_priv),
+ .per_device_auto = sizeof(struct timer_dev_priv),
};
static int cr50_i2c_get_desc(struct udevice *dev, char *buf, int size)
{
- struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
+ struct dm_i2c_chip *chip = dev_get_parent_plat(dev);
struct cr50_priv *priv = dev_get_priv(dev);
return snprintf(buf, size, "cr50 TPM 2.0 (i2c %02x id %x) irq=%d",
LONG_TIMEOUT_MS = 2000,
};
-static int cr50_i2c_ofdata_to_platdata(struct udevice *dev)
+static int cr50_i2c_of_to_plat(struct udevice *dev)
{
struct tpm_chip_priv *upriv = dev_get_uclass_priv(dev);
struct cr50_priv *priv = dev_get_priv(dev);
.id = UCLASS_TPM,
.of_match = cr50_i2c_ids,
.ops = &cr50_i2c_ops,
- .ofdata_to_platdata = cr50_i2c_ofdata_to_platdata,
+ .of_to_plat = cr50_i2c_of_to_plat,
.probe = cr50_i2c_probe,
.remove = cr50_i2c_cleanup,
- .priv_auto_alloc_size = sizeof(struct cr50_priv),
+ .priv_auto = sizeof(struct cr50_priv),
ACPI_OPS_PTR(&cr50_acpi_ops)
.flags = DM_FLAG_OS_PREPARE,
};
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
.post_bind = dm_scan_fdt_dev,
#endif
- .per_device_auto_alloc_size = sizeof(struct tpm_chip_priv),
+ .per_device_auto = sizeof(struct tpm_chip_priv),
};
.probe = ftpm_tee_probe,
.remove = ftpm_tee_remove,
.flags = DM_FLAG_OS_PREPARE,
- .priv_auto_alloc_size = sizeof(struct ftpm_tee_private),
+ .priv_auto = sizeof(struct ftpm_tee_private),
};
.of_match = sandbox_tpm2_ids,
.ops = &sandbox_tpm2_ops,
.probe = sandbox_tpm2_probe,
- .priv_auto_alloc_size = sizeof(struct sandbox_tpm2),
+ .priv_auto = sizeof(struct sandbox_tpm2),
};
.ops = &tpm_tis_spi_ops,
.probe = tpm_tis_spi_probe,
.remove = tpm_tis_spi_remove,
- .priv_auto_alloc_size = sizeof(struct tpm_chip),
+ .priv_auto = sizeof(struct tpm_chip),
};
.of_match = tpm_tis_i2c_ids,
.ops = &tpm_tis_i2c_ops,
.probe = tpm_tis_i2c_probe,
- .priv_auto_alloc_size = sizeof(struct tpm_chip),
+ .priv_auto = sizeof(struct tpm_chip),
};
.of_match = tpm_tis_lpc_ids,
.ops = &tpm_tis_lpc_ops,
.probe = tpm_tis_lpc_probe,
- .priv_auto_alloc_size = sizeof(struct tpm_tis_lpc_priv),
+ .priv_auto = sizeof(struct tpm_tis_lpc_priv),
};
.of_match = sandbox_tpm_ids,
.ops = &sandbox_tpm_ops,
.probe = sandbox_tpm_probe,
- .priv_auto_alloc_size = sizeof(struct tpm_state),
+ .priv_auto = sizeof(struct tpm_state),
};
.probe = st33zp24_i2c_probe,
.remove = st33zp24_i2c_remove,
.ops = &st33zp24_i2c_tpm_ops,
- .priv_auto_alloc_size = sizeof(struct tpm_chip),
+ .priv_auto = sizeof(struct tpm_chip),
};
{
int total_length = 0, ret;
struct spi_slave *slave = dev_get_parent_priv(dev);
- struct st33zp24_spi_phy *phy = dev_get_platdata(dev);
+ struct st33zp24_spi_phy *phy = dev_get_plat(dev);
u8 *tx_buf = (u8 *)phy->tx_buf;
u8 *rx_buf = phy->rx_buf;
{
int total_length = 0, ret;
struct spi_slave *slave = dev_get_parent_priv(dev);
- struct st33zp24_spi_phy *phy = dev_get_platdata(dev);
+ struct st33zp24_spi_phy *phy = dev_get_plat(dev);
u8 *tx_buf = (u8 *)phy->tx_buf;
u8 *rx_buf = phy->rx_buf;
{
int latency = 1, status = 0;
u8 data = 0;
- struct st33zp24_spi_phy *phy = dev_get_platdata(dev);
+ struct st33zp24_spi_phy *phy = dev_get_plat(dev);
while (!status && latency < MAX_SPI_LATENCY) {
phy->latency = latency;
static int st33zp24_spi_init(struct udevice *dev)
{
struct tpm_chip *chip = dev_get_priv(dev);
- struct st33zp24_spi_phy *phy = dev_get_platdata(dev);
+ struct st33zp24_spi_phy *phy = dev_get_plat(dev);
chip->is_open = 1;
.probe = st33zp24_spi_probe,
.remove = st33zp24_spi_remove,
.ops = &st33zp24_spi_tpm_ops,
- .priv_auto_alloc_size = sizeof(struct tpm_chip),
- .platdata_auto_alloc_size = sizeof(struct st33zp24_spi_phy),
+ .priv_auto = sizeof(struct tpm_chip),
+ .plat_auto = sizeof(struct st33zp24_spi_phy),
};
UCLASS_DRIVER(ufs) = {
.id = UCLASS_UFS,
.name = "ufs",
- .per_device_auto_alloc_size = sizeof(struct ufs_hba),
+ .per_device_auto = sizeof(struct ufs_hba),
};
int ufshcd_probe(struct udevice *ufs_dev, struct ufs_hba_ops *hba_ops)
{
struct ufs_hba *hba = dev_get_uclass_priv(ufs_dev);
- struct scsi_platdata *scsi_plat;
+ struct scsi_plat *scsi_plat;
struct udevice *scsi_dev;
int err;
if (!scsi_dev)
return -ENODEV;
- scsi_plat = dev_get_uclass_platdata(scsi_dev);
+ scsi_plat = dev_get_uclass_plat(scsi_dev);
scsi_plat->max_id = UFSHCD_MAX_ID;
scsi_plat->max_lun = UFS_MAX_LUNS;
scsi_plat->max_bytes_per_req = UFS_MAX_BYTES;
static int cdns_ti_probe(struct udevice *dev)
{
- struct cdns_ti *data = dev_get_platdata(dev);
+ struct cdns_ti *data = dev_get_plat(dev);
struct clk usb2_refclk;
int modestrap_mode;
unsigned long rate;
static int cdns_ti_remove(struct udevice *dev)
{
- struct cdns_ti *data = dev_get_platdata(dev);
+ struct cdns_ti *data = dev_get_plat(dev);
u32 reg;
/* put device back to RESET*/
.bind = cdns3_bind,
.probe = cdns_ti_probe,
.remove = cdns_ti_remove,
- .platdata_auto_alloc_size = sizeof(struct cdns_ti),
+ .plat_auto = sizeof(struct cdns_ti),
.flags = DM_FLAG_OS_PREPARE,
};
.of_match = cdns3_ids,
.probe = cdns3_gadget_probe,
.remove = cdns3_gadget_remove,
- .priv_auto_alloc_size = sizeof(struct cdns3_gadget_priv),
+ .priv_auto = sizeof(struct cdns3_gadget_priv),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
#endif
.of_match = cdns3_ids,
.probe = cdns3_host_probe,
.remove = cdns3_host_remove,
- .priv_auto_alloc_size = sizeof(struct cdns3_host_priv),
+ .priv_auto = sizeof(struct cdns3_host_priv),
.ops = &xhci_usb_ops,
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
struct dwc3_generic_priv *priv)
{
int rc;
- struct dwc3_generic_plat *plat = dev_get_platdata(dev);
+ struct dwc3_generic_plat *plat = dev_get_plat(dev);
struct dwc3 *dwc3 = &priv->dwc3;
- struct dwc3_glue_data *glue = dev_get_platdata(dev->parent);
+ struct dwc3_glue_data *glue = dev_get_plat(dev->parent);
dwc3->dev = dev;
dwc3->maximum_speed = plat->maximum_speed;
return 0;
}
-static int dwc3_generic_ofdata_to_platdata(struct udevice *dev)
+static int dwc3_generic_of_to_plat(struct udevice *dev)
{
- struct dwc3_generic_plat *plat = dev_get_platdata(dev);
+ struct dwc3_generic_plat *plat = dev_get_plat(dev);
ofnode node = dev->node;
plat->base = dev_read_addr(dev);
U_BOOT_DRIVER(dwc3_generic_peripheral) = {
.name = "dwc3-generic-peripheral",
.id = UCLASS_USB_GADGET_GENERIC,
- .ofdata_to_platdata = dwc3_generic_ofdata_to_platdata,
+ .of_to_plat = dwc3_generic_of_to_plat,
.probe = dwc3_generic_peripheral_probe,
.remove = dwc3_generic_peripheral_remove,
- .priv_auto_alloc_size = sizeof(struct dwc3_generic_priv),
- .platdata_auto_alloc_size = sizeof(struct dwc3_generic_plat),
+ .priv_auto = sizeof(struct dwc3_generic_priv),
+ .plat_auto = sizeof(struct dwc3_generic_plat),
};
#endif
U_BOOT_DRIVER(dwc3_generic_host) = {
.name = "dwc3-generic-host",
.id = UCLASS_USB,
- .ofdata_to_platdata = dwc3_generic_ofdata_to_platdata,
+ .of_to_plat = dwc3_generic_of_to_plat,
.probe = dwc3_generic_host_probe,
.remove = dwc3_generic_host_remove,
- .priv_auto_alloc_size = sizeof(struct dwc3_generic_host_priv),
- .platdata_auto_alloc_size = sizeof(struct dwc3_generic_plat),
+ .priv_auto = sizeof(struct dwc3_generic_host_priv),
+ .plat_auto = sizeof(struct dwc3_generic_plat),
.ops = &xhci_usb_ops,
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
u32 utmi_mode;
u32 utmi_status_offset = USBOTGSS_UTMI_OTG_STATUS;
- struct dwc3_glue_data *glue = dev_get_platdata(dev);
+ struct dwc3_glue_data *glue = dev_get_plat(dev);
void *base = map_physmem(glue->regs, 0x10000, MAP_NOCACHE);
if (device_is_compatible(dev, "ti,am437x-dwc3"))
static int dwc3_glue_probe(struct udevice *dev)
{
struct dwc3_glue_ops *ops = (struct dwc3_glue_ops *)dev_get_driver_data(dev);
- struct dwc3_glue_data *glue = dev_get_platdata(dev);
+ struct dwc3_glue_data *glue = dev_get_plat(dev);
struct udevice *child = NULL;
int index = 0;
int ret;
static int dwc3_glue_remove(struct udevice *dev)
{
- struct dwc3_glue_data *glue = dev_get_platdata(dev);
+ struct dwc3_glue_data *glue = dev_get_plat(dev);
reset_release_bulk(&glue->resets);
.bind = dwc3_glue_bind,
.probe = dwc3_glue_probe,
.remove = dwc3_glue_remove,
- .platdata_auto_alloc_size = sizeof(struct dwc3_glue_data),
+ .plat_auto = sizeof(struct dwc3_glue_data),
};
int dwc3_meson_g12a_force_mode(struct udevice *dev, enum usb_dr_mode mode)
{
- struct dwc3_meson_g12a *priv = dev_get_platdata(dev);
+ struct dwc3_meson_g12a *priv = dev_get_plat(dev);
if (!priv)
return -EINVAL;
static int dwc3_meson_g12a_probe(struct udevice *dev)
{
- struct dwc3_meson_g12a *priv = dev_get_platdata(dev);
+ struct dwc3_meson_g12a *priv = dev_get_plat(dev);
int ret, i;
priv->dev = dev;
static int dwc3_meson_g12a_remove(struct udevice *dev)
{
- struct dwc3_meson_g12a *priv = dev_get_platdata(dev);
+ struct dwc3_meson_g12a *priv = dev_get_plat(dev);
int i;
reset_release_all(&priv->reset, 1);
.of_match = dwc3_meson_g12a_ids,
.probe = dwc3_meson_g12a_probe,
.remove = dwc3_meson_g12a_remove,
- .platdata_auto_alloc_size = sizeof(struct dwc3_meson_g12a),
+ .plat_auto = sizeof(struct dwc3_meson_g12a),
};
int dwc3_meson_gxl_force_mode(struct udevice *dev, enum usb_dr_mode mode)
{
- struct dwc3_meson_gxl *priv = dev_get_platdata(dev);
+ struct dwc3_meson_gxl *priv = dev_get_plat(dev);
if (!priv)
return -EINVAL;
static int dwc3_meson_gxl_probe(struct udevice *dev)
{
- struct dwc3_meson_gxl *priv = dev_get_platdata(dev);
+ struct dwc3_meson_gxl *priv = dev_get_plat(dev);
int ret, i;
priv->dev = dev;
static int dwc3_meson_gxl_remove(struct udevice *dev)
{
- struct dwc3_meson_gxl *priv = dev_get_platdata(dev);
+ struct dwc3_meson_gxl *priv = dev_get_plat(dev);
int i;
reset_release_all(&priv->reset, 1);
.of_match = dwc3_meson_gxl_ids,
.probe = dwc3_meson_gxl_probe,
.remove = dwc3_meson_gxl_remove,
- .platdata_auto_alloc_size = sizeof(struct dwc3_meson_gxl),
+ .plat_auto = sizeof(struct dwc3_meson_gxl),
};
static int sandbox_flash_bulk(struct udevice *dev, struct usb_device *udev,
unsigned long pipe, void *buff, int len)
{
- struct sandbox_flash_plat *plat = dev_get_platdata(dev);
+ struct sandbox_flash_plat *plat = dev_get_plat(dev);
struct sandbox_flash_priv *priv = dev_get_priv(dev);
int ep = usb_pipeendpoint(pipe);
struct umass_bbb_cbw *cbw = buff;
return 0;
}
-static int sandbox_flash_ofdata_to_platdata(struct udevice *dev)
+static int sandbox_flash_of_to_plat(struct udevice *dev)
{
- struct sandbox_flash_plat *plat = dev_get_platdata(dev);
+ struct sandbox_flash_plat *plat = dev_get_plat(dev);
plat->pathname = dev_read_string(dev, "sandbox,filepath");
static int sandbox_flash_bind(struct udevice *dev)
{
- struct sandbox_flash_plat *plat = dev_get_platdata(dev);
+ struct sandbox_flash_plat *plat = dev_get_plat(dev);
struct usb_string *fs;
fs = plat->flash_strings;
static int sandbox_flash_probe(struct udevice *dev)
{
- struct sandbox_flash_plat *plat = dev_get_platdata(dev);
+ struct sandbox_flash_plat *plat = dev_get_plat(dev);
struct sandbox_flash_priv *priv = dev_get_priv(dev);
priv->fd = os_open(plat->pathname, OS_O_RDONLY);
.of_match = sandbox_usb_flash_ids,
.bind = sandbox_flash_bind,
.probe = sandbox_flash_probe,
- .ofdata_to_platdata = sandbox_flash_ofdata_to_platdata,
+ .of_to_plat = sandbox_flash_of_to_plat,
.ops = &sandbox_usb_flash_ops,
- .priv_auto_alloc_size = sizeof(struct sandbox_flash_priv),
- .platdata_auto_alloc_size = sizeof(struct sandbox_flash_plat),
+ .priv_auto = sizeof(struct sandbox_flash_priv),
+ .plat_auto = sizeof(struct sandbox_flash_plat),
};
/* We only support up to 8 */
#define SANDBOX_NUM_PORTS 4
-struct sandbox_hub_platdata {
- struct usb_dev_platdata plat;
+struct sandbox_hub_plat {
+ struct usb_dev_plat plat;
int port; /* Port number (numbered from 0) */
};
for (device_find_first_child(hub, &dev);
dev;
device_find_next_child(&dev)) {
- struct sandbox_hub_platdata *plat;
+ struct sandbox_hub_plat *plat;
- plat = dev_get_parent_platdata(dev);
+ plat = dev_get_parent_plat(dev);
if (plat->port == port) {
gen_desc = plat->plat.desc_list;
gen_desc = usb_emul_find_descriptor(gen_desc,
static int sandbox_child_post_bind(struct udevice *dev)
{
- struct sandbox_hub_platdata *plat = dev_get_parent_platdata(dev);
- struct usb_emul_platdata *emul = dev_get_uclass_platdata(dev);
+ struct sandbox_hub_plat *plat = dev_get_parent_plat(dev);
+ struct usb_emul_plat *emul = dev_get_uclass_plat(dev);
plat->port = dev_read_u32_default(dev, "reg", -1);
emul->port1 = plat->port + 1;
.of_match = sandbox_usb_hub_ids,
.bind = sandbox_hub_bind,
.ops = &sandbox_usb_hub_ops,
- .priv_auto_alloc_size = sizeof(struct sandbox_hub_priv),
- .per_child_platdata_auto_alloc_size =
- sizeof(struct sandbox_hub_platdata),
+ .priv_auto = sizeof(struct sandbox_hub_priv),
+ .per_child_plat_auto = sizeof(struct sandbox_hub_plat),
.child_post_bind = sandbox_child_post_bind,
};
static int sandbox_keyb_bind(struct udevice *dev)
{
- struct sandbox_keyb_plat *plat = dev_get_platdata(dev);
+ struct sandbox_keyb_plat *plat = dev_get_plat(dev);
struct usb_string *fs;
fs = plat->keyb_strings;
.bind = sandbox_keyb_bind,
.probe = sandbox_keyb_probe,
.ops = &sandbox_usb_keyb_ops,
- .priv_auto_alloc_size = sizeof(struct sandbox_keyb_priv),
- .platdata_auto_alloc_size = sizeof(struct sandbox_keyb_plat),
+ .priv_auto = sizeof(struct sandbox_keyb_priv),
+ .plat_auto = sizeof(struct sandbox_keyb_plat),
};
return ptr;
}
-static int usb_emul_get_descriptor(struct usb_dev_platdata *plat, int value,
+static int usb_emul_get_descriptor(struct usb_dev_plat *plat, int value,
void *buffer, int length)
{
struct usb_generic_descriptor **ptr;
if (ret)
return ret;
uclass_foreach_dev(dev, uc) {
- struct usb_dev_platdata *udev = dev_get_parent_platdata(dev);
+ struct usb_dev_plat *udev = dev_get_parent_plat(dev);
/*
* devnum is initialzied to zero at the beginning of the
* emulator device.
*/
if (!devnum) {
- struct usb_emul_platdata *plat;
+ struct usb_emul_plat *plat;
/*
* If the parent is sandbox USB controller, we are
return 0;
}
- plat = dev_get_uclass_platdata(dev);
+ plat = dev_get_uclass_plat(dev);
if (plat->port1 == port1) {
debug("%s: Found emulator '%s', port %d\n",
__func__, dev->name, port1);
int usb_emul_find_for_dev(struct udevice *dev, struct udevice **emulp)
{
- struct usb_dev_platdata *udev = dev_get_parent_platdata(dev);
+ struct usb_dev_plat *udev = dev_get_parent_plat(dev);
return usb_emul_find_devnum(udev->devnum, 0, emulp);
}
struct devrequest *setup)
{
struct dm_usb_ops *ops = usb_get_emul_ops(emul);
- struct usb_dev_platdata *plat;
+ struct usb_dev_plat *plat;
int ret;
/* We permit getting the descriptor before we are probed */
- plat = dev_get_parent_platdata(emul);
+ plat = dev_get_parent_plat(emul);
if (!ops->control)
return -ENOSYS;
debug("%s: dev=%s\n", __func__, emul->name);
int usb_emul_setup_device(struct udevice *dev, struct usb_string *strings,
void **desc_list)
{
- struct usb_dev_platdata *plat = dev_get_parent_platdata(dev);
+ struct usb_dev_plat *plat = dev_get_parent_plat(dev);
struct usb_generic_descriptor **ptr;
struct usb_config_descriptor *cdesc;
int upto;
.id = UCLASS_USB_EMUL,
.name = "usb_emul",
.post_bind = dm_scan_fdt_dev,
- .per_device_platdata_auto_alloc_size = sizeof(struct usb_emul_platdata),
- .per_child_auto_alloc_size = sizeof(struct usb_device),
- .per_child_platdata_auto_alloc_size = sizeof(struct usb_dev_platdata),
+ .per_device_plat_auto = sizeof(struct usb_emul_plat),
+ .per_child_auto = sizeof(struct usb_device),
+ .per_child_plat_auto = sizeof(struct usb_dev_plat),
};
#ifdef CONFIG_DM_ETH
static int asix_eth_start(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct asix_private *priv = dev_get_priv(dev);
return asix_init_common(&priv->ueth, pdata->enetaddr);
int asix_write_hwaddr(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct asix_private *priv = dev_get_priv(dev);
if (priv->flags & FLAG_TYPE_AX88172)
static int asix_eth_probe(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct asix_private *priv = dev_get_priv(dev);
struct ueth_data *ss = &priv->ueth;
int ret;
.id = UCLASS_ETH,
.probe = asix_eth_probe,
.ops = &asix_eth_ops,
- .priv_auto_alloc_size = sizeof(struct asix_private),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct asix_private),
+ .plat_auto = sizeof(struct eth_pdata),
};
static const struct usb_device_id asix_eth_id_table[] = {
int ax88179_write_hwaddr(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct asix_private *priv = dev_get_priv(dev);
struct ueth_data *ueth = &priv->ueth;
static int ax88179_eth_probe(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct asix_private *priv = dev_get_priv(dev);
struct usb_device *usb_dev;
int ret;
.id = UCLASS_ETH,
.probe = ax88179_eth_probe,
.ops = &ax88179_eth_ops,
- .priv_auto_alloc_size = sizeof(struct asix_private),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct asix_private),
+ .plat_auto = sizeof(struct eth_pdata),
};
static const struct usb_device_id ax88179_eth_id_table[] = {
int lan75xx_write_hwaddr(struct udevice *dev)
{
struct usb_device *udev = dev_get_parent_priv(dev);
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
unsigned char *enetaddr = pdata->enetaddr;
u32 addr_lo = get_unaligned_le32(&enetaddr[0]);
u32 addr_hi = (u32)get_unaligned_le16(&enetaddr[4]);
int lan75xx_read_rom_hwaddr(struct udevice *dev)
{
struct usb_device *udev = dev_get_parent_priv(dev);
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
int ret;
/*
struct usb_device *udev = dev_get_parent_priv(dev);
struct lan7x_private *priv = dev_get_priv(dev);
struct ueth_data *ueth = &priv->ueth;
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
int ret;
/* Do a reset in order to get the MAC address from HW */
.probe = lan75xx_eth_probe,
.remove = lan7x_eth_remove,
.ops = &lan75xx_eth_ops,
- .priv_auto_alloc_size = sizeof(struct lan7x_private),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct lan7x_private),
+ .plat_auto = sizeof(struct eth_pdata),
};
static const struct usb_device_id lan75xx_eth_id_table[] = {
int lan78xx_write_hwaddr(struct udevice *dev)
{
struct usb_device *udev = dev_get_parent_priv(dev);
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
unsigned char *enetaddr = pdata->enetaddr;
u32 addr_lo = get_unaligned_le32(&enetaddr[0]);
u32 addr_hi = (u32)get_unaligned_le16(&enetaddr[4]);
int lan78xx_read_rom_hwaddr(struct udevice *dev)
{
struct usb_device *udev = dev_get_parent_priv(dev);
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct lan7x_private *priv = dev_get_priv(dev);
int ret;
struct usb_device *udev = dev_get_parent_priv(dev);
struct lan7x_private *priv = dev_get_priv(dev);
struct ueth_data *ueth = &priv->ueth;
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
int ret;
/* Do a reset in order to get the MAC address from HW */
.probe = lan78xx_eth_probe,
.remove = lan7x_eth_remove,
.ops = &lan78xx_eth_ops,
- .priv_auto_alloc_size = sizeof(struct lan7x_private),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct lan7x_private),
+ .plat_auto = sizeof(struct eth_pdata),
};
static const struct usb_device_id lan78xx_eth_id_table[] = {
int mcs7830_write_hwaddr(struct udevice *dev)
{
struct usb_device *udev = dev_get_parent_priv(dev);
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
return mcs7830_write_mac_common(udev, pdata->enetaddr);
}
{
struct usb_device *udev = dev_get_parent_priv(dev);
struct mcs7830_private *priv = dev_get_priv(dev);
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct ueth_data *ueth = &priv->ueth;
if (mcs7830_basic_reset(udev, priv))
.id = UCLASS_ETH,
.probe = mcs7830_eth_probe,
.ops = &mcs7830_eth_ops,
- .priv_auto_alloc_size = sizeof(struct mcs7830_private),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct mcs7830_private),
+ .plat_auto = sizeof(struct eth_pdata),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
static int r8152_write_hwaddr(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct r8152 *tp = dev_get_priv(dev);
unsigned char enetaddr[8] = { 0 };
int r8152_read_rom_hwaddr(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct r8152 *tp = dev_get_priv(dev);
debug("** %s (%d)\n", __func__, __LINE__);
static int r8152_eth_probe(struct udevice *dev)
{
struct usb_device *udev = dev_get_parent_priv(dev);
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct r8152 *tp = dev_get_priv(dev);
struct ueth_data *ueth = &tp->ueth;
int ret;
.id = UCLASS_ETH,
.probe = r8152_eth_probe,
.ops = &r8152_eth_ops,
- .priv_auto_alloc_size = sizeof(struct r8152),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct r8152),
+ .plat_auto = sizeof(struct eth_pdata),
};
static const struct usb_device_id r8152_eth_id_table[] = {
{
struct usb_device *udev = dev_get_parent_priv(dev);
struct smsc95xx_private *priv = dev_get_priv(dev);
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
/* Driver-model Ethernet ensures we have this */
priv->have_hwaddr = 1;
int smsc95xx_write_hwaddr(struct udevice *dev)
{
struct usb_device *udev = dev_get_parent_priv(dev);
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
struct smsc95xx_private *priv = dev_get_priv(dev);
return smsc95xx_write_hwaddr_common(udev, priv, pdata->enetaddr);
int smsc95xx_read_rom_hwaddr(struct udevice *dev)
{
struct usb_device *udev = dev_get_parent_priv(dev);
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
int ret;
ret = smsc95xx_init_mac_address(pdata->enetaddr, udev);
.id = UCLASS_ETH,
.probe = smsc95xx_eth_probe,
.ops = &smsc95xx_eth_ops,
- .priv_auto_alloc_size = sizeof(struct smsc95xx_private),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct smsc95xx_private),
+ .plat_auto = sizeof(struct eth_pdata),
};
static const struct usb_device_id smsc95xx_eth_id_table[] = {
generic_phy_exit_bulk(phys);
}
-static int dwc2_udc_otg_ofdata_to_platdata(struct udevice *dev)
+static int dwc2_udc_otg_of_to_plat(struct udevice *dev)
{
- struct dwc2_plat_otg_data *platdata = dev_get_platdata(dev);
+ struct dwc2_plat_otg_data *plat = dev_get_plat(dev);
ulong drvdata;
void (*set_params)(struct dwc2_plat_otg_data *data);
int ret;
return -ENODEV;
}
- platdata->regs_otg = dev_read_addr(dev);
+ plat->regs_otg = dev_read_addr(dev);
- platdata->rx_fifo_sz = dev_read_u32_default(dev, "g-rx-fifo-size", 0);
- platdata->np_tx_fifo_sz = dev_read_u32_default(dev,
- "g-np-tx-fifo-size", 0);
+ plat->rx_fifo_sz = dev_read_u32_default(dev, "g-rx-fifo-size", 0);
+ plat->np_tx_fifo_sz = dev_read_u32_default(dev, "g-np-tx-fifo-size", 0);
- platdata->tx_fifo_sz_nb =
+ plat->tx_fifo_sz_nb =
dev_read_size(dev, "g-tx-fifo-size") / sizeof(u32);
- if (platdata->tx_fifo_sz_nb > DWC2_MAX_HW_ENDPOINTS)
- platdata->tx_fifo_sz_nb = DWC2_MAX_HW_ENDPOINTS;
- if (platdata->tx_fifo_sz_nb) {
+ if (plat->tx_fifo_sz_nb > DWC2_MAX_HW_ENDPOINTS)
+ plat->tx_fifo_sz_nb = DWC2_MAX_HW_ENDPOINTS;
+ if (plat->tx_fifo_sz_nb) {
ret = dev_read_u32_array(dev, "g-tx-fifo-size",
- platdata->tx_fifo_sz_array,
- platdata->tx_fifo_sz_nb);
+ plat->tx_fifo_sz_array,
+ plat->tx_fifo_sz_nb);
if (ret)
return ret;
}
- platdata->force_b_session_valid =
+ plat->force_b_session_valid =
dev_read_bool(dev, "u-boot,force-b-session-valid");
- platdata->force_vbus_detection =
+ plat->force_vbus_detection =
dev_read_bool(dev, "u-boot,force-vbus-detection");
- /* force platdata according compatible */
+ /* force plat according compatible */
drvdata = dev_get_driver_data(dev);
if (drvdata) {
set_params = (void *)drvdata;
- set_params(platdata);
+ set_params(plat);
}
return 0;
static int dwc2_udc_otg_probe(struct udevice *dev)
{
- struct dwc2_plat_otg_data *platdata = dev_get_platdata(dev);
+ struct dwc2_plat_otg_data *plat = dev_get_plat(dev);
struct dwc2_priv_data *priv = dev_get_priv(dev);
struct dwc2_usbotg_reg *usbotg_reg =
- (struct dwc2_usbotg_reg *)platdata->regs_otg;
+ (struct dwc2_usbotg_reg *)plat->regs_otg;
int ret;
ret = dwc2_udc_otg_clk_init(dev, &priv->clks);
if (ret)
return ret;
- if (platdata->activate_stm_id_vb_detection) {
+ if (plat->activate_stm_id_vb_detection) {
if (CONFIG_IS_ENABLED(DM_REGULATOR) &&
- (!platdata->force_b_session_valid ||
- platdata->force_vbus_detection)) {
+ (!plat->force_b_session_valid ||
+ plat->force_vbus_detection)) {
ret = device_get_supply_regulator(dev, "usb33d-supply",
&priv->usb33d_supply);
if (ret) {
}
}
- if (platdata->force_b_session_valid &&
- !platdata->force_vbus_detection) {
+ if (plat->force_b_session_valid &&
+ !plat->force_vbus_detection) {
/* Override VBUS detection: enable then value*/
setbits_le32(&usbotg_reg->gotgctl, VB_VALOEN);
setbits_le32(&usbotg_reg->gotgctl, VB_VALOVAL);
setbits_le32(&usbotg_reg->ggpio,
GGPIO_STM32_OTG_GCCFG_VBDEN);
}
- if (platdata->force_b_session_valid) {
+ if (plat->force_b_session_valid) {
/* Override B session bits: enable then value */
setbits_le32(&usbotg_reg->gotgctl, A_VALOEN | B_VALOEN);
setbits_le32(&usbotg_reg->gotgctl,
}
}
- ret = dwc2_udc_probe(platdata);
+ ret = dwc2_udc_probe(plat);
if (ret)
return ret;
.name = "dwc2-udc-otg",
.id = UCLASS_USB_GADGET_GENERIC,
.of_match = dwc2_udc_otg_ids,
- .ofdata_to_platdata = dwc2_udc_otg_ofdata_to_platdata,
+ .of_to_plat = dwc2_udc_otg_of_to_plat,
.probe = dwc2_udc_otg_probe,
.remove = dwc2_udc_otg_remove,
- .platdata_auto_alloc_size = sizeof(struct dwc2_plat_otg_data),
- .priv_auto_alloc_size = sizeof(struct dwc2_priv_data),
+ .plat_auto = sizeof(struct dwc2_plat_otg_data),
+ .priv_auto = sizeof(struct dwc2_priv_data),
};
int dwc2_udc_B_session_valid(struct udevice *dev)
{
- struct dwc2_plat_otg_data *platdata = dev_get_platdata(dev);
+ struct dwc2_plat_otg_data *plat = dev_get_plat(dev);
struct dwc2_usbotg_reg *usbotg_reg =
- (struct dwc2_usbotg_reg *)platdata->regs_otg;
+ (struct dwc2_usbotg_reg *)plat->regs_otg;
return readl(&usbotg_reg->gotgctl) & B_SESSION_VALID;
}
int gcnum;
u8 tmp[7];
#ifdef CONFIG_DM_ETH
- struct eth_pdata *pdata = dev_get_platdata(l_priv->netdev);
+ struct eth_pdata *pdata = dev_get_plat(l_priv->netdev);
#endif
/* these flags are only ever cleared; compiler take note */
static int usb_eth_probe(struct udevice *dev)
{
struct ether_priv *priv = dev_get_priv(dev);
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
priv->netdev = dev;
l_priv = priv;
.id = UCLASS_ETH,
.probe = usb_eth_probe,
.ops = &usb_eth_ops,
- .priv_auto_alloc_size = sizeof(struct ether_priv),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct ether_priv),
+ .plat_auto = sizeof(struct eth_pdata),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
#endif /* CONFIG_DM_ETH */
static int max3420_udc_probe(struct udevice *dev)
{
struct max3420_udc *udc = dev_get_priv(dev);
- struct dm_spi_slave_platdata *slave_pdata;
+ struct dm_spi_slave_plat *slave_pdata;
struct udevice *bus = dev->parent;
int busnum = bus->seq;
unsigned int cs;
uint speed, mode;
struct udevice *spid;
- slave_pdata = dev_get_parent_platdata(dev);
+ slave_pdata = dev_get_parent_plat(dev);
cs = slave_pdata->cs;
speed = slave_pdata->max_hz;
mode = slave_pdata->mode;
.of_match = max3420_ids,
.probe = max3420_udc_probe,
.remove = max3420_udc_remove,
- .priv_auto_alloc_size = sizeof(struct max3420_udc),
+ .priv_auto = sizeof(struct max3420_udc),
};
nonblock);
}
-static int dwc2_usb_ofdata_to_platdata(struct udevice *dev)
+static int dwc2_usb_of_to_plat(struct udevice *dev)
{
struct dwc2_priv *priv = dev_get_priv(dev);
.name = "dwc2_usb",
.id = UCLASS_USB,
.of_match = dwc2_usb_ids,
- .ofdata_to_platdata = dwc2_usb_ofdata_to_platdata,
+ .of_to_plat = dwc2_usb_of_to_plat,
.probe = dwc2_usb_probe,
.remove = dwc2_usb_remove,
.ops = &dwc2_usb_ops,
- .priv_auto_alloc_size = sizeof(struct dwc2_priv),
+ .priv_auto = sizeof(struct dwc2_priv),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
#endif
static int dwc3_of_simple_probe(struct udevice *dev)
{
- struct dwc3_of_simple *simple = dev_get_platdata(dev);
+ struct dwc3_of_simple *simple = dev_get_plat(dev);
int ret;
ret = dwc3_of_simple_clk_init(dev, simple);
static int dwc3_of_simple_remove(struct udevice *dev)
{
- struct dwc3_of_simple *simple = dev_get_platdata(dev);
+ struct dwc3_of_simple *simple = dev_get_plat(dev);
reset_release_bulk(&simple->resets);
.of_match = dwc3_of_simple_ids,
.probe = dwc3_of_simple_probe,
.remove = dwc3_of_simple_remove,
- .platdata_auto_alloc_size = sizeof(struct dwc3_of_simple),
+ .plat_auto = sizeof(struct dwc3_of_simple),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
DECLARE_GLOBAL_DATA_PTR;
/*
- * struct sti_dwc3_glue_platdata - dwc3 STi glue driver private structure
+ * struct sti_dwc3_glue_plat - dwc3 STi glue driver private structure
* @syscfg_base: addr for the glue syscfg
* @glue_base: addr for the glue registers
* @syscfg_offset: usb syscfg control offset
* @softreset_ctl: reset controller for softreset signal
* @mode: drd static host/device config
*/
-struct sti_dwc3_glue_platdata {
+struct sti_dwc3_glue_plat {
phys_addr_t syscfg_base;
phys_addr_t glue_base;
phys_addr_t syscfg_offset;
enum usb_dr_mode mode;
};
-static int sti_dwc3_glue_drd_init(struct sti_dwc3_glue_platdata *plat)
+static int sti_dwc3_glue_drd_init(struct sti_dwc3_glue_plat *plat)
{
unsigned long val;
return 0;
}
-static void sti_dwc3_glue_init(struct sti_dwc3_glue_platdata *plat)
+static void sti_dwc3_glue_init(struct sti_dwc3_glue_plat *plat)
{
unsigned long reg;
setbits_le32(plat->glue_base + CLKRST_CTRL, SW_PIPEW_RESET_N);
}
-static int sti_dwc3_glue_ofdata_to_platdata(struct udevice *dev)
+static int sti_dwc3_glue_of_to_plat(struct udevice *dev)
{
- struct sti_dwc3_glue_platdata *plat = dev_get_platdata(dev);
+ struct sti_dwc3_glue_plat *plat = dev_get_plat(dev);
struct udevice *syscon;
struct regmap *regmap;
int ret;
static int sti_dwc3_glue_bind(struct udevice *dev)
{
- struct sti_dwc3_glue_platdata *plat = dev_get_platdata(dev);
+ struct sti_dwc3_glue_plat *plat = dev_get_plat(dev);
ofnode node, dwc3_node;
/* Find snps,dwc3 node from subnode */
static int sti_dwc3_glue_probe(struct udevice *dev)
{
- struct sti_dwc3_glue_platdata *plat = dev_get_platdata(dev);
+ struct sti_dwc3_glue_plat *plat = dev_get_plat(dev);
int ret;
/* deassert both powerdown and softreset */
static int sti_dwc3_glue_remove(struct udevice *dev)
{
- struct sti_dwc3_glue_platdata *plat = dev_get_platdata(dev);
+ struct sti_dwc3_glue_plat *plat = dev_get_plat(dev);
int ret;
/* assert both powerdown and softreset */
.name = "dwc3_sti_glue",
.id = UCLASS_NOP,
.of_match = sti_dwc3_glue_ids,
- .ofdata_to_platdata = sti_dwc3_glue_ofdata_to_platdata,
+ .of_to_plat = sti_dwc3_glue_of_to_plat,
.probe = sti_dwc3_glue_probe,
.remove = sti_dwc3_glue_remove,
.bind = sti_dwc3_glue_bind,
- .platdata_auto_alloc_size = sizeof(struct sti_dwc3_glue_platdata),
+ .plat_auto = sizeof(struct sti_dwc3_glue_plat),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
.probe = ehci_atmel_probe,
.remove = ehci_deregister,
.ops = &ehci_usb_ops,
- .platdata_auto_alloc_size = sizeof(struct usb_platdata),
- .priv_auto_alloc_size = sizeof(struct ehci_atmel_priv),
+ .plat_auto = sizeof(struct usb_plat),
+ .priv_auto = sizeof(struct ehci_atmel_priv),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
/* Declare global data pointer */
DECLARE_GLOBAL_DATA_PTR;
-struct exynos_ehci_platdata {
- struct usb_platdata usb_plat;
+struct exynos_ehci_plat {
+ struct usb_plat usb_plat;
fdt_addr_t hcd_base;
fdt_addr_t phy_base;
struct gpio_desc vbus_gpio;
struct ehci_hccr *hcd;
};
-static int ehci_usb_ofdata_to_platdata(struct udevice *dev)
+static int ehci_usb_of_to_plat(struct udevice *dev)
{
- struct exynos_ehci_platdata *plat = dev_get_platdata(dev);
+ struct exynos_ehci_plat *plat = dev_get_plat(dev);
const void *blob = gd->fdt_blob;
unsigned int node;
int depth;
static int ehci_usb_probe(struct udevice *dev)
{
- struct exynos_ehci_platdata *plat = dev_get_platdata(dev);
+ struct exynos_ehci_plat *plat = dev_get_plat(dev);
struct exynos_ehci *ctx = dev_get_priv(dev);
struct ehci_hcor *hcor;
.name = "ehci_exynos",
.id = UCLASS_USB,
.of_match = ehci_usb_ids,
- .ofdata_to_platdata = ehci_usb_ofdata_to_platdata,
+ .of_to_plat = ehci_usb_of_to_plat,
.probe = ehci_usb_probe,
.remove = ehci_usb_remove,
.ops = &ehci_usb_ops,
- .priv_auto_alloc_size = sizeof(struct exynos_ehci),
- .platdata_auto_alloc_size = sizeof(struct exynos_ehci_platdata),
+ .priv_auto = sizeof(struct exynos_ehci),
+ .plat_auto = sizeof(struct exynos_ehci_plat),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
}
#if CONFIG_IS_ENABLED(DM_USB)
-static int ehci_fsl_ofdata_to_platdata(struct udevice *dev)
+static int ehci_fsl_of_to_plat(struct udevice *dev)
{
struct ehci_fsl_priv *priv = dev_get_priv(dev);
const void *prop;
.name = "ehci_fsl",
.id = UCLASS_USB,
.of_match = ehci_usb_ids,
- .ofdata_to_platdata = ehci_fsl_ofdata_to_platdata,
+ .of_to_plat = ehci_fsl_of_to_plat,
.probe = ehci_fsl_probe,
.remove = ehci_deregister,
.ops = &ehci_usb_ops,
- .platdata_auto_alloc_size = sizeof(struct usb_platdata),
- .priv_auto_alloc_size = sizeof(struct ehci_fsl_priv),
+ .plat_auto = sizeof(struct usb_plat),
+ .priv_auto = sizeof(struct ehci_fsl_priv),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
#else
.probe = ehci_usb_probe,
.remove = ehci_usb_remove,
.ops = &ehci_usb_ops,
- .priv_auto_alloc_size = sizeof(struct generic_ehci),
+ .priv_auto = sizeof(struct generic_ehci),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
.probe = ehci_mvebu_probe,
.remove = ehci_deregister,
.ops = &ehci_usb_ops,
- .platdata_auto_alloc_size = sizeof(struct usb_platdata),
- .priv_auto_alloc_size = sizeof(struct ehci_mvebu_priv),
+ .plat_auto = sizeof(struct usb_plat),
+ .priv_auto = sizeof(struct ehci_mvebu_priv),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
{
struct msm_ehci_priv *p = dev_get_priv(dev);
struct usb_ehci *ehci = p->ehci;
- struct usb_platdata *plat = dev_get_platdata(dev);
+ struct usb_plat *plat = dev_get_plat(dev);
struct ehci_hccr *hccr;
struct ehci_hcor *hcor;
int ret;
return 0;
}
-static int ehci_usb_ofdata_to_platdata(struct udevice *dev)
+static int ehci_usb_of_to_plat(struct udevice *dev)
{
struct msm_ehci_priv *priv = dev_get_priv(dev);
.name = "ehci_msm",
.id = UCLASS_USB,
.of_match = ehci_usb_ids,
- .ofdata_to_platdata = ehci_usb_ofdata_to_platdata,
+ .of_to_plat = ehci_usb_of_to_plat,
.probe = ehci_usb_probe,
.remove = ehci_usb_remove,
.ops = &ehci_usb_ops,
- .priv_auto_alloc_size = sizeof(struct msm_ehci_priv),
- .platdata_auto_alloc_size = sizeof(struct usb_platdata),
+ .priv_auto = sizeof(struct msm_ehci_priv),
+ .plat_auto = sizeof(struct usb_plat),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
.powerup_fixup = mx5_ehci_powerup_fixup,
};
-static int ehci_usb_ofdata_to_platdata(struct udevice *dev)
+static int ehci_usb_of_to_plat(struct udevice *dev)
{
- struct usb_platdata *plat = dev_get_platdata(dev);
+ struct usb_plat *plat = dev_get_plat(dev);
const char *mode;
mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "dr_mode", NULL);
static int ehci_usb_probe(struct udevice *dev)
{
- struct usb_platdata *plat = dev_get_platdata(dev);
+ struct usb_plat *plat = dev_get_plat(dev);
struct usb_ehci *ehci = dev_read_addr_ptr(dev);
struct ehci_mx5_priv_data *priv = dev_get_priv(dev);
enum usb_init_type type = plat->init_type;
.name = "ehci_mx5",
.id = UCLASS_USB,
.of_match = mx5_usb_ids,
- .ofdata_to_platdata = ehci_usb_ofdata_to_platdata,
+ .of_to_plat = ehci_usb_of_to_plat,
.probe = ehci_usb_probe,
.remove = ehci_deregister,
.ops = &ehci_usb_ops,
- .platdata_auto_alloc_size = sizeof(struct usb_platdata),
- .priv_auto_alloc_size = sizeof(struct ehci_mx5_priv_data),
+ .plat_auto = sizeof(struct usb_plat),
+ .priv_auto = sizeof(struct ehci_mx5_priv_data),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
#endif /* !CONFIG_IS_ENABLED(DM_USB) */
static int ehci_usb_phy_mode(struct udevice *dev)
{
- struct usb_platdata *plat = dev_get_platdata(dev);
+ struct usb_plat *plat = dev_get_plat(dev);
void *__iomem addr = dev_read_addr_ptr(dev);
void *__iomem phy_ctrl, *__iomem phy_status;
const void *blob = gd->fdt_blob;
return 0;
}
-static int ehci_usb_ofdata_to_platdata(struct udevice *dev)
+static int ehci_usb_of_to_plat(struct udevice *dev)
{
- struct usb_platdata *plat = dev_get_platdata(dev);
+ struct usb_plat *plat = dev_get_plat(dev);
enum usb_dr_mode dr_mode;
dr_mode = usb_get_dr_mode(dev->node);
static int ehci_usb_probe(struct udevice *dev)
{
- struct usb_platdata *plat = dev_get_platdata(dev);
+ struct usb_plat *plat = dev_get_plat(dev);
struct usb_ehci *ehci = dev_read_addr_ptr(dev);
struct ehci_mx6_priv_data *priv = dev_get_priv(dev);
enum usb_init_type type = plat->init_type;
.name = "ehci_mx6",
.id = UCLASS_USB,
.of_match = mx6_usb_ids,
- .ofdata_to_platdata = ehci_usb_ofdata_to_platdata,
+ .of_to_plat = ehci_usb_of_to_plat,
.bind = ehci_usb_bind,
.probe = ehci_usb_probe,
.remove = ehci_deregister,
.ops = &ehci_usb_ops,
- .platdata_auto_alloc_size = sizeof(struct usb_platdata),
- .priv_auto_alloc_size = sizeof(struct ehci_mx6_priv_data),
+ .plat_auto = sizeof(struct usb_plat),
+ .priv_auto = sizeof(struct ehci_mx6_priv_data),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
#endif
int nports;
};
-static int ehci_usb_ofdata_to_platdata(struct udevice *dev)
+static int ehci_usb_of_to_plat(struct udevice *dev)
{
- struct usb_platdata *plat = dev_get_platdata(dev);
+ struct usb_plat *plat = dev_get_plat(dev);
plat->init_type = USB_INIT_HOST;
static int omap_ehci_probe(struct udevice *dev)
{
- struct usb_platdata *plat = dev_get_platdata(dev);
+ struct usb_plat *plat = dev_get_plat(dev);
struct ehci_omap_priv_data *priv = dev_get_priv(dev);
struct ehci_hccr *hccr;
struct ehci_hcor *hcor;
.id = UCLASS_USB,
.of_match = omap_ehci_dt_ids,
.probe = omap_ehci_probe,
- .ofdata_to_platdata = ehci_usb_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct usb_platdata),
- .priv_auto_alloc_size = sizeof(struct ehci_omap_priv_data),
+ .of_to_plat = ehci_usb_of_to_plat,
+ .plat_auto = sizeof(struct usb_plat),
+ .priv_auto = sizeof(struct ehci_omap_priv_data),
.remove = ehci_deregister,
.ops = &ehci_usb_ops,
.flags = DM_FLAG_ALLOC_PRIV_DMA,
.remove = ehci_pci_remove,
.of_match = ehci_pci_ids,
.ops = &ehci_usb_ops,
- .platdata_auto_alloc_size = sizeof(struct usb_platdata),
- .priv_auto_alloc_size = sizeof(struct ehci_pci_priv),
+ .plat_auto = sizeof(struct usb_plat),
+ .priv_auto = sizeof(struct ehci_pci_priv),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
.powerup_fixup = tegra_ehci_powerup_fixup,
};
-static int ehci_usb_ofdata_to_platdata(struct udevice *dev)
+static int ehci_usb_of_to_plat(struct udevice *dev)
{
struct fdt_usb *priv = dev_get_priv(dev);
int ret;
static int ehci_usb_probe(struct udevice *dev)
{
- struct usb_platdata *plat = dev_get_platdata(dev);
+ struct usb_plat *plat = dev_get_plat(dev);
struct fdt_usb *priv = dev_get_priv(dev);
struct ehci_hccr *hccr;
struct ehci_hcor *hcor;
.name = "ehci_tegra",
.id = UCLASS_USB,
.of_match = ehci_usb_ids,
- .ofdata_to_platdata = ehci_usb_ofdata_to_platdata,
+ .of_to_plat = ehci_usb_of_to_plat,
.probe = ehci_usb_probe,
.remove = ehci_deregister,
.ops = &ehci_usb_ops,
- .platdata_auto_alloc_size = sizeof(struct usb_platdata),
- .priv_auto_alloc_size = sizeof(struct fdt_usb),
+ .plat_auto = sizeof(struct usb_plat),
+ .priv_auto = sizeof(struct fdt_usb),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
u32 portnr;
};
-static int vf_usb_ofdata_to_platdata(struct udevice *dev)
+static int vf_usb_of_to_plat(struct udevice *dev)
{
struct ehci_vf_priv_data *priv = dev_get_priv(dev);
const void *dt_blob = gd->fdt_blob;
static int ehci_usb_probe(struct udevice *dev)
{
- struct usb_platdata *plat = dev_get_platdata(dev);
+ struct usb_plat *plat = dev_get_plat(dev);
struct ehci_vf_priv_data *priv = dev_get_priv(dev);
struct usb_ehci *ehci = priv->ehci;
struct ehci_hccr *hccr;
.probe = ehci_usb_probe,
.remove = ehci_deregister,
.ops = &ehci_usb_ops,
- .ofdata_to_platdata = vf_usb_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct usb_platdata),
- .priv_auto_alloc_size = sizeof(struct ehci_vf_priv_data),
+ .of_to_plat = vf_usb_of_to_plat,
+ .plat_auto = sizeof(struct usb_plat),
+ .priv_auto = sizeof(struct ehci_vf_priv_data),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
#endif
struct usb_ehci *ehci;
};
-static int ehci_zynq_ofdata_to_platdata(struct udevice *dev)
+static int ehci_zynq_of_to_plat(struct udevice *dev)
{
struct zynq_ehci_priv *priv = dev_get_priv(dev);
static int ehci_zynq_probe(struct udevice *dev)
{
- struct usb_platdata *plat = dev_get_platdata(dev);
+ struct usb_plat *plat = dev_get_plat(dev);
struct zynq_ehci_priv *priv = dev_get_priv(dev);
struct ehci_hccr *hccr;
struct ehci_hcor *hcor;
.name = "ehci_zynq",
.id = UCLASS_USB,
.of_match = ehci_zynq_ids,
- .ofdata_to_platdata = ehci_zynq_ofdata_to_platdata,
+ .of_to_plat = ehci_zynq_of_to_plat,
.probe = ehci_zynq_probe,
.remove = ehci_deregister,
.ops = &ehci_usb_ops,
- .platdata_auto_alloc_size = sizeof(struct usb_platdata),
- .priv_auto_alloc_size = sizeof(struct zynq_ehci_priv),
+ .plat_auto = sizeof(struct usb_plat),
+ .priv_auto = sizeof(struct zynq_ehci_priv),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
.probe = ohci_da8xx_probe,
.remove = ohci_da8xx_remove,
.ops = &ohci_usb_ops,
- .priv_auto_alloc_size = sizeof(struct da8xx_ohci),
+ .priv_auto = sizeof(struct da8xx_ohci),
.flags = DM_FLAG_ALLOC_PRIV_DMA | DM_FLAG_OS_PREPARE,
};
#endif
.probe = ohci_usb_probe,
.remove = ohci_usb_remove,
.ops = &ohci_usb_ops,
- .priv_auto_alloc_size = sizeof(struct generic_ohci),
+ .priv_auto = sizeof(struct generic_ohci),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
.remove = ohci_pci_remove,
.of_match = ohci_pci_ids,
.ops = &ohci_usb_ops,
- .platdata_auto_alloc_size = sizeof(struct usb_platdata),
- .priv_auto_alloc_size = sizeof(ohci_t),
+ .plat_auto = sizeof(struct usb_plat),
+ .priv_auto = sizeof(ohci_t),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
return ret;
}
-static int r8a66597_usb_ofdata_to_platdata(struct udevice *dev)
+static int r8a66597_usb_of_to_plat(struct udevice *dev)
{
struct r8a66597 *priv = dev_get_priv(dev);
fdt_addr_t addr;
.name = "r8a66597_usb",
.id = UCLASS_USB,
.of_match = r8a66597_usb_ids,
- .ofdata_to_platdata = r8a66597_usb_ofdata_to_platdata,
+ .of_to_plat = r8a66597_usb_of_to_plat,
.probe = r8a66597_usb_probe,
.remove = r8a66597_usb_remove,
.ops = &r8a66597_usb_ops,
- .priv_auto_alloc_size = sizeof(struct r8a66597),
+ .priv_auto = sizeof(struct r8a66597),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
.of_match = sandbox_usb_ids,
.probe = sandbox_usb_probe,
.ops = &sandbox_usb_ops,
- .priv_auto_alloc_size = sizeof(struct sandbox_usb_ctrl),
+ .priv_auto = sizeof(struct sandbox_usb_ctrl),
};
int usb_setup_ehci_gadget(struct ehci_ctrl **ctlrp)
{
- struct usb_platdata *plat;
+ struct usb_plat *plat;
struct udevice *dev;
int ret;
if (ret)
return ret;
- plat = dev_get_platdata(dev);
+ plat = dev_get_plat(dev);
plat->init_type = USB_INIT_DEVICE;
ret = device_probe(dev);
if (ret)
const struct usb_device_id *id;
struct udevice *dev;
const struct driver *drv;
- struct usb_dev_platdata *plat;
+ struct usb_dev_plat *plat;
for (id = entry->match; id->match_flags; id++) {
if (!usb_match_one_id(desc, iface, id))
drv = entry->driver;
/*
* We could pass the descriptor to the driver as
- * platdata (instead of NULL) and allow its bind()
+ * plat (instead of NULL) and allow its bind()
* method to return -ENOENT if it doesn't support this
* device. That way we could continue the search to
* find another driver. For now this doesn't seem
* necesssary, so just bind the first match.
*/
- ret = device_bind_ofnode(parent, drv, drv->name, NULL,
- node, &dev);
+ ret = device_bind(parent, drv, drv->name, NULL, node,
+ &dev);
if (ret)
goto error;
debug("%s: Match found: %s\n", __func__, drv->name);
dev->driver_data = id->driver_info;
- plat = dev_get_parent_platdata(dev);
+ plat = dev_get_parent_plat(dev);
plat->id = *id;
*devp = dev;
return 0;
for (device_find_first_child(parent, &dev);
dev;
device_find_next_child(&dev)) {
- struct usb_dev_platdata *plat = dev_get_parent_platdata(dev);
+ struct usb_dev_plat *plat = dev_get_parent_plat(dev);
/* If this device is already in use, skip it */
if (device_active(dev))
{
struct udevice *dev;
bool created = false;
- struct usb_dev_platdata *plat;
+ struct usb_dev_plat *plat;
struct usb_bus_priv *priv;
struct usb_device *parent_udev;
int ret;
return ret;
created = true;
}
- plat = dev_get_parent_platdata(dev);
+ plat = dev_get_parent_plat(dev);
debug("%s: Probing '%s', plat=%p\n", __func__, dev->name, plat);
plat->devnum = udev->devnum;
plat->udev = udev;
static int usb_child_post_bind(struct udevice *dev)
{
- struct usb_dev_platdata *plat = dev_get_parent_platdata(dev);
+ struct usb_dev_plat *plat = dev_get_parent_plat(dev);
int val;
if (!dev_of_valid(dev))
int usb_child_pre_probe(struct udevice *dev)
{
struct usb_device *udev = dev_get_parent_priv(dev);
- struct usb_dev_platdata *plat = dev_get_parent_platdata(dev);
+ struct usb_dev_plat *plat = dev_get_parent_plat(dev);
int ret;
if (plat->udev) {
.name = "usb",
.flags = DM_UC_FLAG_SEQ_ALIAS,
.post_bind = dm_scan_fdt_dev,
- .priv_auto_alloc_size = sizeof(struct usb_uclass_priv),
- .per_child_auto_alloc_size = sizeof(struct usb_device),
- .per_device_auto_alloc_size = sizeof(struct usb_bus_priv),
+ .priv_auto = sizeof(struct usb_uclass_priv),
+ .per_child_auto = sizeof(struct usb_device),
+ .per_device_auto = sizeof(struct usb_bus_priv),
.child_post_bind = usb_child_post_bind,
.child_pre_probe = usb_child_pre_probe,
- .per_child_platdata_auto_alloc_size = sizeof(struct usb_dev_platdata),
+ .per_child_plat_auto = sizeof(struct usb_dev_plat),
};
UCLASS_DRIVER(usb_dev_generic) = {
#define USBAXI_SA_UA_MASK (USBAXI_UA_MASK | USBAXI_SA_MASK)
#define USBAXI_SA_UA_VAL (USBAXI_UA_VAL | USBAXI_SA_VAL)
-struct brcm_xhci_platdata {
+struct brcm_xhci_plat {
unsigned int arcache;
unsigned int awcache;
void __iomem *hc_base;
static int xhci_brcm_probe(struct udevice *dev)
{
- struct brcm_xhci_platdata *plat = dev_get_platdata(dev);
+ struct brcm_xhci_plat *plat = dev_get_plat(dev);
struct xhci_hcor *hcor;
struct xhci_hccr *hcd;
int len, ret = 0;
static int xhci_brcm_deregister(struct udevice *dev)
{
- struct brcm_xhci_platdata *plat = dev_get_platdata(dev);
+ struct brcm_xhci_plat *plat = dev_get_plat(dev);
/* Restore the default values for AXI read and write attributes */
writel(plat->awcache, plat->hc_base + DRD2U3H_XHC_REGS_AXIWRA);
.remove = xhci_brcm_deregister,
.ops = &xhci_usb_ops,
.of_match = xhci_brcm_ids,
- .platdata_auto_alloc_size = sizeof(struct brcm_xhci_platdata),
- .priv_auto_alloc_size = sizeof(struct xhci_ctrl),
+ .plat_auto = sizeof(struct brcm_xhci_plat),
+ .priv_auto = sizeof(struct xhci_ctrl),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
#include <linux/usb/dwc3.h>
#include <linux/usb/otg.h>
-struct xhci_dwc3_platdata {
+struct xhci_dwc3_plat {
struct phy_bulk phys;
};
struct xhci_hccr *hccr;
struct dwc3 *dwc3_reg;
enum usb_dr_mode dr_mode;
- struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
+ struct xhci_dwc3_plat *plat = dev_get_plat(dev);
const char *phy;
u32 reg;
int ret;
static int xhci_dwc3_remove(struct udevice *dev)
{
- struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
+ struct xhci_dwc3_plat *plat = dev_get_plat(dev);
dwc3_shutdown_phy(dev, &plat->phys);
.probe = xhci_dwc3_probe,
.remove = xhci_dwc3_remove,
.ops = &xhci_usb_ops,
- .priv_auto_alloc_size = sizeof(struct xhci_ctrl),
- .platdata_auto_alloc_size = sizeof(struct xhci_dwc3_platdata),
+ .priv_auto = sizeof(struct xhci_ctrl),
+ .plat_auto = sizeof(struct xhci_dwc3_plat),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
#endif
/* Declare global data pointer */
DECLARE_GLOBAL_DATA_PTR;
-struct exynos_xhci_platdata {
+struct exynos_xhci_plat {
fdt_addr_t hcd_base;
fdt_addr_t phy_base;
struct gpio_desc vbus_gpio;
* for the usb controller.
*/
struct exynos_xhci {
- struct usb_platdata usb_plat;
+ struct usb_plat usb_plat;
struct xhci_ctrl ctrl;
struct exynos_usb3_phy *usb3_phy;
struct xhci_hccr *hcd;
struct dwc3 *dwc3_reg;
};
-static int xhci_usb_ofdata_to_platdata(struct udevice *dev)
+static int xhci_usb_of_to_plat(struct udevice *dev)
{
- struct exynos_xhci_platdata *plat = dev_get_platdata(dev);
+ struct exynos_xhci_plat *plat = dev_get_plat(dev);
const void *blob = gd->fdt_blob;
unsigned int node;
int depth;
static int xhci_usb_probe(struct udevice *dev)
{
- struct exynos_xhci_platdata *plat = dev_get_platdata(dev);
+ struct exynos_xhci_plat *plat = dev_get_plat(dev);
struct exynos_xhci *ctx = dev_get_priv(dev);
struct xhci_hcor *hcor;
int ret;
.name = "xhci_exynos",
.id = UCLASS_USB,
.of_match = xhci_usb_ids,
- .ofdata_to_platdata = xhci_usb_ofdata_to_platdata,
+ .of_to_plat = xhci_usb_of_to_plat,
.probe = xhci_usb_probe,
.remove = xhci_usb_remove,
.ops = &xhci_usb_ops,
- .platdata_auto_alloc_size = sizeof(struct exynos_xhci_platdata),
- .priv_auto_alloc_size = sizeof(struct exynos_xhci),
+ .plat_auto = sizeof(struct exynos_xhci_plat),
+ .priv_auto = sizeof(struct exynos_xhci),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
.probe = xhci_fsl_probe,
.remove = xhci_fsl_remove,
.ops = &xhci_usb_ops,
- .platdata_auto_alloc_size = sizeof(struct usb_platdata),
- .priv_auto_alloc_size = sizeof(struct xhci_fsl_priv),
+ .plat_auto = sizeof(struct usb_plat),
+ .priv_auto = sizeof(struct xhci_fsl_priv),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
#else
.remove = xhci_mtk_remove,
.ops = &xhci_usb_ops,
.bind = dm_scan_fdt_dev,
- .priv_auto_alloc_size = sizeof(struct mtk_xhci),
+ .priv_auto = sizeof(struct mtk_xhci),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
#include <usb/xhci.h>
-struct mvebu_xhci_platdata {
+struct mvebu_xhci_plat {
fdt_addr_t hcd_base;
};
*/
struct mvebu_xhci {
struct xhci_ctrl ctrl; /* Needs to come first in this struct! */
- struct usb_platdata usb_plat;
+ struct usb_plat usb_plat;
struct xhci_hccr *hcd;
};
static int xhci_usb_probe(struct udevice *dev)
{
- struct mvebu_xhci_platdata *plat = dev_get_platdata(dev);
+ struct mvebu_xhci_plat *plat = dev_get_plat(dev);
struct mvebu_xhci *ctx = dev_get_priv(dev);
struct xhci_hcor *hcor;
int len, ret;
return xhci_register(dev, ctx->hcd, hcor);
}
-static int xhci_usb_ofdata_to_platdata(struct udevice *dev)
+static int xhci_usb_of_to_plat(struct udevice *dev)
{
- struct mvebu_xhci_platdata *plat = dev_get_platdata(dev);
+ struct mvebu_xhci_plat *plat = dev_get_plat(dev);
/*
* Get the base address for XHCI controller from the device node
.name = "xhci_mvebu",
.id = UCLASS_USB,
.of_match = xhci_usb_ids,
- .ofdata_to_platdata = xhci_usb_ofdata_to_platdata,
+ .of_to_plat = xhci_usb_of_to_plat,
.probe = xhci_usb_probe,
.remove = xhci_deregister,
.ops = &xhci_usb_ops,
- .platdata_auto_alloc_size = sizeof(struct mvebu_xhci_platdata),
- .priv_auto_alloc_size = sizeof(struct mvebu_xhci),
+ .plat_auto = sizeof(struct mvebu_xhci_plat),
+ .priv_auto = sizeof(struct mvebu_xhci),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
.remove = xhci_deregister,
.of_match = xhci_pci_ids,
.ops = &xhci_usb_ops,
- .platdata_auto_alloc_size = sizeof(struct usb_platdata),
- .priv_auto_alloc_size = sizeof(struct xhci_ctrl),
+ .plat_auto = sizeof(struct usb_plat),
+ .priv_auto = sizeof(struct xhci_ctrl),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
#define RCAR_USB3_DL_CTRL_FW_SUCCESS BIT(4)
#define RCAR_USB3_DL_CTRL_FW_SET_DATA0 BIT(8)
-struct rcar_xhci_platdata {
+struct rcar_xhci_plat {
fdt_addr_t hcd_base;
struct clk clk;
};
*/
struct rcar_xhci {
struct xhci_ctrl ctrl; /* Needs to come first in this struct! */
- struct usb_platdata usb_plat;
+ struct usb_plat usb_plat;
struct xhci_hccr *hcd;
};
static int xhci_rcar_probe(struct udevice *dev)
{
- struct rcar_xhci_platdata *plat = dev_get_platdata(dev);
+ struct rcar_xhci_plat *plat = dev_get_plat(dev);
struct rcar_xhci *ctx = dev_get_priv(dev);
struct xhci_hcor *hcor;
int len, ret;
static int xhci_rcar_deregister(struct udevice *dev)
{
int ret;
- struct rcar_xhci_platdata *plat = dev_get_platdata(dev);
+ struct rcar_xhci_plat *plat = dev_get_plat(dev);
ret = xhci_deregister(dev);
return ret;
}
-static int xhci_rcar_ofdata_to_platdata(struct udevice *dev)
+static int xhci_rcar_of_to_plat(struct udevice *dev)
{
- struct rcar_xhci_platdata *plat = dev_get_platdata(dev);
+ struct rcar_xhci_plat *plat = dev_get_plat(dev);
plat->hcd_base = dev_read_addr(dev);
if (plat->hcd_base == FDT_ADDR_T_NONE) {
.remove = xhci_rcar_deregister,
.ops = &xhci_usb_ops,
.of_match = xhci_rcar_ids,
- .ofdata_to_platdata = xhci_rcar_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct rcar_xhci_platdata),
- .priv_auto_alloc_size = sizeof(struct rcar_xhci),
+ .of_to_plat = xhci_rcar_of_to_plat,
+ .plat_auto = sizeof(struct rcar_xhci_plat),
+ .priv_auto = sizeof(struct rcar_xhci),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
.of_match = ssusb_of_match,
.probe = mtu3_gadget_probe,
.remove = mtu3_gadget_remove,
- .priv_auto_alloc_size = sizeof(struct mtu3),
+ .priv_auto = sizeof(struct mtu3),
};
#endif
.of_match = ssusb_of_match,
.probe = mtu3_host_probe,
.remove = mtu3_host_remove,
- .priv_auto_alloc_size = sizeof(struct mtu3_host),
+ .priv_auto = sizeof(struct mtu3_host),
.ops = &xhci_usb_ops,
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
.bind = mtu3_glue_bind,
.probe = mtu3_probe,
.remove = mtu3_remove,
- .priv_auto_alloc_size = sizeof(struct ssusb_mtk),
+ .priv_auto = sizeof(struct ssusb_mtk),
};
.disable = da8xx_musb_disable,
};
-struct da8xx_musb_platdata {
+struct da8xx_musb_plat {
void *base;
void *ctrl_mod_base;
struct musb_hdrc_platform_data plat;
struct phy phy;
};
-static int da8xx_musb_ofdata_to_platdata(struct udevice *dev)
+static int da8xx_musb_of_to_plat(struct udevice *dev)
{
- struct da8xx_musb_platdata *platdata = dev_get_platdata(dev);
+ struct da8xx_musb_plat *plat = dev_get_plat(dev);
const void *fdt = gd->fdt_blob;
int node = dev_of_offset(dev);
- platdata->base = (void *)dev_read_addr_ptr(dev);
- platdata->musb_config.multipoint = 1;
- platdata->musb_config.dyn_fifo = 1;
- platdata->musb_config.num_eps = 5;
- platdata->musb_config.ram_bits = 10;
- platdata->plat.power = fdtdec_get_int(fdt, node, "power", 50);
- platdata->otg_board_data.interface_type = MUSB_INTERFACE_UTMI;
- platdata->plat.mode = MUSB_HOST;
- platdata->otg_board_data.dev = dev;
- platdata->plat.config = &platdata->musb_config;
- platdata->plat.platform_ops = &da8xx_ops;
- platdata->plat.board_data = &platdata->otg_board_data;
- platdata->otg_board_data.clear_irq = da8xx_musb_clear_irq;
- platdata->otg_board_data.reset = da8xx_musb_reset;
+ plat->base = (void *)dev_read_addr_ptr(dev);
+ plat->musb_config.multipoint = 1;
+ plat->musb_config.dyn_fifo = 1;
+ plat->musb_config.num_eps = 5;
+ plat->musb_config.ram_bits = 10;
+ plat->plat.power = fdtdec_get_int(fdt, node, "power", 50);
+ plat->otg_board_data.interface_type = MUSB_INTERFACE_UTMI;
+ plat->plat.mode = MUSB_HOST;
+ plat->otg_board_data.dev = dev;
+ plat->plat.config = &plat->musb_config;
+ plat->plat.platform_ops = &da8xx_ops;
+ plat->plat.board_data = &plat->otg_board_data;
+ plat->otg_board_data.clear_irq = da8xx_musb_clear_irq;
+ plat->otg_board_data.reset = da8xx_musb_reset;
return 0;
}
static int da8xx_musb_probe(struct udevice *dev)
{
struct musb_host_data *host = dev_get_priv(dev);
- struct da8xx_musb_platdata *platdata = dev_get_platdata(dev);
+ struct da8xx_musb_plat *plat = dev_get_plat(dev);
struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
struct omap_musb_board_data *otg_board_data;
int ret;
void *base = dev_read_addr_ptr(dev);
/* Get the phy info from the device tree */
- ret = generic_phy_get_by_name(dev, "usb-phy", &platdata->phy);
+ ret = generic_phy_get_by_name(dev, "usb-phy", &plat->phy);
if (ret)
return ret;
/* Initialize the phy */
- ret = generic_phy_init(&platdata->phy);
+ ret = generic_phy_init(&plat->phy);
if (ret)
return ret;
lpsc_on(33);
/* Enable phy */
- generic_phy_power_on(&platdata->phy);
+ generic_phy_power_on(&plat->phy);
priv->desc_before_addr = true;
- otg_board_data = &platdata->otg_board_data;
+ otg_board_data = &plat->otg_board_data;
- host->host = musb_init_controller(&platdata->plat,
+ host->host = musb_init_controller(&plat->plat,
(struct device *)otg_board_data,
- platdata->base);
+ plat->base);
if (!host->host) {
ret = -ENODEV;
goto shutdown; /* Shutdown what we started */
return 0;
shutdown:
/* Turn off the phy if we fail */
- generic_phy_power_off(&platdata->phy);
+ generic_phy_power_off(&plat->phy);
lpsc_disable(33);
return ret;
}
.name = "da8xx-musb",
.id = UCLASS_USB,
.of_match = da8xx_musb_ids,
- .ofdata_to_platdata = da8xx_musb_ofdata_to_platdata,
+ .of_to_plat = da8xx_musb_of_to_plat,
.probe = da8xx_musb_probe,
.remove = da8xx_musb_remove,
.ops = &musb_usb_ops,
- .platdata_auto_alloc_size = sizeof(struct da8xx_musb_platdata),
- .priv_auto_alloc_size = sizeof(struct musb_host_data),
+ .plat_auto = sizeof(struct da8xx_musb_plat),
+ .priv_auto = sizeof(struct musb_host_data),
};
#ifdef CONFIG_USB_MUSB_HOST
.ops = &musb_usb_ops,
#endif
- .platdata_auto_alloc_size = sizeof(struct usb_platdata),
- .priv_auto_alloc_size = sizeof(struct mtk_musb_glue),
+ .plat_auto = sizeof(struct usb_plat),
+ .priv_auto = sizeof(struct mtk_musb_glue),
};
#if CONFIG_IS_ENABLED(DM_USB)
-struct omap2430_musb_platdata {
+struct omap2430_musb_plat {
void *base;
void *ctrl_mod_base;
struct musb_hdrc_platform_data plat;
struct omap_musb_board_data otg_board_data;
};
-static int omap2430_musb_ofdata_to_platdata(struct udevice *dev)
+static int omap2430_musb_of_to_plat(struct udevice *dev)
{
- struct omap2430_musb_platdata *platdata = dev_get_platdata(dev);
+ struct omap2430_musb_plat *plat = dev_get_plat(dev);
const void *fdt = gd->fdt_blob;
int node = dev_of_offset(dev);
- platdata->base = (void *)dev_read_addr_ptr(dev);
+ plat->base = (void *)dev_read_addr_ptr(dev);
- platdata->musb_config.multipoint = fdtdec_get_int(fdt, node,
- "multipoint",
- -1);
- if (platdata->musb_config.multipoint < 0) {
+ plat->musb_config.multipoint = fdtdec_get_int(fdt, node, "multipoint",
+ -1);
+ if (plat->musb_config.multipoint < 0) {
pr_err("MUSB multipoint DT entry missing\n");
return -ENOENT;
}
- platdata->musb_config.dyn_fifo = 1;
- platdata->musb_config.num_eps = fdtdec_get_int(fdt, node,
- "num-eps", -1);
- if (platdata->musb_config.num_eps < 0) {
+ plat->musb_config.dyn_fifo = 1;
+ plat->musb_config.num_eps = fdtdec_get_int(fdt, node, "num-eps", -1);
+ if (plat->musb_config.num_eps < 0) {
pr_err("MUSB num-eps DT entry missing\n");
return -ENOENT;
}
- platdata->musb_config.ram_bits = fdtdec_get_int(fdt, node,
- "ram-bits", -1);
- if (platdata->musb_config.ram_bits < 0) {
+ plat->musb_config.ram_bits = fdtdec_get_int(fdt, node, "ram-bits", -1);
+ if (plat->musb_config.ram_bits < 0) {
pr_err("MUSB ram-bits DT entry missing\n");
return -ENOENT;
}
- platdata->plat.power = fdtdec_get_int(fdt, node,
- "power", -1);
- if (platdata->plat.power < 0) {
+ plat->plat.power = fdtdec_get_int(fdt, node, "power", -1);
+ if (plat->plat.power < 0) {
pr_err("MUSB power DT entry missing\n");
return -ENOENT;
}
- platdata->otg_board_data.interface_type = fdtdec_get_int(fdt, node,
- "interface-type", -1);
- if (platdata->otg_board_data.interface_type < 0) {
+ plat->otg_board_data.interface_type = fdtdec_get_int(fdt, node,
+ "interface-type",
+ -1);
+ if (plat->otg_board_data.interface_type < 0) {
pr_err("MUSB interface-type DT entry missing\n");
return -ENOENT;
}
#if 0 /* In a perfect world, mode would be set to OTG, mode 3 from DT */
- platdata->plat.mode = fdtdec_get_int(fdt, node,
- "mode", -1);
- if (platdata->plat.mode < 0) {
+ plat->plat.mode = fdtdec_get_int(fdt, node, "mode", -1);
+ if (plat->plat.mode < 0) {
pr_err("MUSB mode DT entry missing\n");
return -ENOENT;
}
#else /* MUSB_OTG, it doesn't work */
#ifdef CONFIG_USB_MUSB_HOST /* Host seems to be the only option that works */
- platdata->plat.mode = MUSB_HOST;
+ plat->plat.mode = MUSB_HOST;
#else /* For that matter, MUSB_PERIPHERAL doesn't either */
- platdata->plat.mode = MUSB_PERIPHERAL;
+ plat->plat.mode = MUSB_PERIPHERAL;
#endif
#endif
- platdata->otg_board_data.dev = dev;
- platdata->plat.config = &platdata->musb_config;
- platdata->plat.platform_ops = &omap2430_ops;
- platdata->plat.board_data = &platdata->otg_board_data;
+ plat->otg_board_data.dev = dev;
+ plat->plat.config = &plat->musb_config;
+ plat->plat.platform_ops = &omap2430_ops;
+ plat->plat.board_data = &plat->otg_board_data;
return 0;
}
#else
struct musb *musbp;
#endif
- struct omap2430_musb_platdata *platdata = dev_get_platdata(dev);
+ struct omap2430_musb_plat *plat = dev_get_plat(dev);
struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
struct omap_musb_board_data *otg_board_data;
int ret = 0;
priv->desc_before_addr = true;
- otg_board_data = &platdata->otg_board_data;
+ otg_board_data = &plat->otg_board_data;
#ifdef CONFIG_USB_MUSB_HOST
- host->host = musb_init_controller(&platdata->plat,
+ host->host = musb_init_controller(&plat->plat,
(struct device *)otg_board_data,
- platdata->base);
+ plat->base);
if (!host->host) {
return -EIO;
}
ret = musb_lowlevel_init(host);
#else
- musbp = musb_register(&platdata->plat,
- (struct device *)otg_board_data,
- platdata->base);
+ musbp = musb_register(&plat->plat, (struct device *)otg_board_data,
+ plat->base);
if (IS_ERR_OR_NULL(musbp))
return -EINVAL;
#endif
.id = UCLASS_USB_GADGET_GENERIC,
#endif
.of_match = omap2430_musb_ids,
- .ofdata_to_platdata = omap2430_musb_ofdata_to_platdata,
+ .of_to_plat = omap2430_musb_of_to_plat,
.probe = omap2430_musb_probe,
.remove = omap2430_musb_remove,
#ifdef CONFIG_USB_MUSB_HOST
.ops = &musb_usb_ops,
#endif
- .platdata_auto_alloc_size = sizeof(struct omap2430_musb_platdata),
- .priv_auto_alloc_size = sizeof(struct musb_host_data),
+ .plat_auto = sizeof(struct omap2430_musb_plat),
+ .priv_auto = sizeof(struct musb_host_data),
};
#endif /* CONFIG_IS_ENABLED(DM_USB) */
#ifdef CONFIG_USB_MUSB_HOST
.ops = &musb_usb_ops,
#endif
- .platdata_auto_alloc_size = sizeof(struct usb_platdata),
- .priv_auto_alloc_size = sizeof(struct pic32_musb_data),
+ .plat_auto = sizeof(struct usb_plat),
+ .priv_auto = sizeof(struct pic32_musb_data),
};
#ifdef CONFIG_USB_MUSB_HOST
.ops = &musb_usb_ops,
#endif
- .platdata_auto_alloc_size = sizeof(struct usb_platdata),
- .priv_auto_alloc_size = sizeof(struct sunxi_glue),
+ .plat_auto = sizeof(struct usb_plat),
+ .priv_auto = sizeof(struct sunxi_glue),
};
static void ti_musb_set_phy_power(struct udevice *dev, u8 on)
{
- struct ti_musb_platdata *platdata = dev_get_platdata(dev);
+ struct ti_musb_plat *plat = dev_get_plat(dev);
- if (!platdata->ctrl_mod_base)
+ if (!plat->ctrl_mod_base)
return;
if (on) {
- clrsetbits_le32(platdata->ctrl_mod_base,
+ clrsetbits_le32(plat->ctrl_mod_base,
CM_PHY_PWRDN | CM_PHY_OTG_PWRDN,
OTGVDET_EN | OTGSESSENDEN);
} else {
- clrsetbits_le32(platdata->ctrl_mod_base, 0,
+ clrsetbits_le32(plat->ctrl_mod_base, 0,
CM_PHY_PWRDN | CM_PHY_OTG_PWRDN);
}
}
return -ENOENT;
}
-static int ti_musb_ofdata_to_platdata(struct udevice *dev)
+static int ti_musb_of_to_plat(struct udevice *dev)
{
- struct ti_musb_platdata *platdata = dev_get_platdata(dev);
+ struct ti_musb_plat *plat = dev_get_plat(dev);
const void *fdt = gd->fdt_blob;
int node = dev_of_offset(dev);
int phys;
int usb_index;
struct musb_hdrc_config *musb_config;
- platdata->base = (void *)devfdt_get_addr_index(dev, 1);
+ plat->base = (void *)devfdt_get_addr_index(dev, 1);
phys = fdtdec_lookup_phandle(fdt, node, "phys");
ctrl_mod = fdtdec_lookup_phandle(fdt, phys, "ti,ctrl_mod");
- platdata->ctrl_mod_base = (void *)fdtdec_get_addr(fdt, ctrl_mod, "reg");
+ plat->ctrl_mod_base = (void *)fdtdec_get_addr(fdt, ctrl_mod, "reg");
usb_index = ti_musb_get_usb_index(node);
switch (usb_index) {
case 1:
- platdata->ctrl_mod_base += AM335X_USB1_CTRL;
+ plat->ctrl_mod_base += AM335X_USB1_CTRL;
break;
case 0:
- platdata->ctrl_mod_base += AM335X_USB0_CTRL;
+ plat->ctrl_mod_base += AM335X_USB0_CTRL;
break;
default:
break;
return -ENOENT;
}
- platdata->plat.config = musb_config;
+ plat->plat.config = musb_config;
- platdata->plat.power = fdtdec_get_int(fdt, node, "mentor,power", -1);
- if (platdata->plat.power < 0) {
+ plat->plat.power = fdtdec_get_int(fdt, node, "mentor,power", -1);
+ if (plat->plat.power < 0) {
pr_err("MUSB mentor,power DT entry missing\n");
return -ENOENT;
}
- platdata->plat.platform_ops = &musb_dsps_ops;
+ plat->plat.platform_ops = &musb_dsps_ops;
return 0;
}
static int ti_musb_host_probe(struct udevice *dev)
{
struct musb_host_data *host = dev_get_priv(dev);
- struct ti_musb_platdata *platdata = dev_get_platdata(dev);
+ struct ti_musb_plat *plat = dev_get_plat(dev);
struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
int ret;
priv->desc_before_addr = true;
- host->host = musb_init_controller(&platdata->plat,
+ host->host = musb_init_controller(&plat->plat,
NULL,
- platdata->base);
+ plat->base);
if (!host->host)
return -EIO;
}
#if CONFIG_IS_ENABLED(OF_CONTROL)
-static int ti_musb_host_ofdata_to_platdata(struct udevice *dev)
+static int ti_musb_host_of_to_plat(struct udevice *dev)
{
- struct ti_musb_platdata *platdata = dev_get_platdata(dev);
+ struct ti_musb_plat *plat = dev_get_plat(dev);
const void *fdt = gd->fdt_blob;
int node = dev_of_offset(dev);
int ret;
- ret = ti_musb_ofdata_to_platdata(dev);
+ ret = ti_musb_of_to_plat(dev);
if (ret) {
- pr_err("platdata dt parse error\n");
+ pr_err("plat dt parse error\n");
return ret;
}
- platdata->plat.mode = MUSB_HOST;
+ plat->plat.mode = MUSB_HOST;
return 0;
}
.name = "ti-musb-host",
.id = UCLASS_USB,
#if CONFIG_IS_ENABLED(OF_CONTROL)
- .ofdata_to_platdata = ti_musb_host_ofdata_to_platdata,
+ .of_to_plat = ti_musb_host_of_to_plat,
#endif
.probe = ti_musb_host_probe,
.remove = ti_musb_host_remove,
.ops = &musb_usb_ops,
- .platdata_auto_alloc_size = sizeof(struct ti_musb_platdata),
- .priv_auto_alloc_size = sizeof(struct musb_host_data),
+ .plat_auto = sizeof(struct ti_musb_plat),
+ .priv_auto = sizeof(struct musb_host_data),
};
#if CONFIG_IS_ENABLED(DM_USB_GADGET)
};
#if CONFIG_IS_ENABLED(OF_CONTROL)
-static int ti_musb_peripheral_ofdata_to_platdata(struct udevice *dev)
+static int ti_musb_peripheral_of_to_plat(struct udevice *dev)
{
- struct ti_musb_platdata *platdata = dev_get_platdata(dev);
+ struct ti_musb_plat *plat = dev_get_plat(dev);
const void *fdt = gd->fdt_blob;
int node = dev_of_offset(dev);
int ret;
- ret = ti_musb_ofdata_to_platdata(dev);
+ ret = ti_musb_of_to_plat(dev);
if (ret) {
- pr_err("platdata dt parse error\n");
+ pr_err("plat dt parse error\n");
return ret;
}
- platdata->plat.mode = MUSB_PERIPHERAL;
+ plat->plat.mode = MUSB_PERIPHERAL;
return 0;
}
static int ti_musb_peripheral_probe(struct udevice *dev)
{
struct ti_musb_peripheral *priv = dev_get_priv(dev);
- struct ti_musb_platdata *platdata = dev_get_platdata(dev);
+ struct ti_musb_plat *plat = dev_get_plat(dev);
int ret;
- priv->periph = musb_init_controller(&platdata->plat,
+ priv->periph = musb_init_controller(&plat->plat,
NULL,
- platdata->base);
+ plat->base);
if (!priv->periph)
return -EIO;
.name = "ti-musb-peripheral",
.id = UCLASS_USB_GADGET_GENERIC,
#if CONFIG_IS_ENABLED(OF_CONTROL)
- .ofdata_to_platdata = ti_musb_peripheral_ofdata_to_platdata,
+ .of_to_plat = ti_musb_peripheral_of_to_plat,
#endif
.probe = ti_musb_peripheral_probe,
.remove = ti_musb_peripheral_remove,
.ops = &musb_usb_ops,
- .platdata_auto_alloc_size = sizeof(struct ti_musb_platdata),
- .priv_auto_alloc_size = sizeof(struct ti_musb_peripheral),
+ .plat_auto = sizeof(struct ti_musb_plat),
+ .priv_auto = sizeof(struct ti_musb_peripheral),
.flags = DM_FLAG_PRE_RELOC,
};
#endif
static int am335x_fb_remove(struct udevice *dev)
{
- struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
+ struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
uc_plat->base -= 0x20;
uc_plat->size += 0x20;
static int am335x_fb_probe(struct udevice *dev)
{
- struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
+ struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
struct am335x_fb_priv *priv = dev_get_priv(dev);
struct am335x_lcdhw *regs = priv->regs;
return 0;
}
-static int am335x_fb_ofdata_to_platdata(struct udevice *dev)
+static int am335x_fb_of_to_plat(struct udevice *dev)
{
struct am335x_fb_priv *priv = dev_get_priv(dev);
struct tilcdc_panel_info *panel = &priv->panel;
static int am335x_fb_bind(struct udevice *dev)
{
- struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
+ struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
uc_plat->size = ((LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
(1 << LCD_MAX_LOG2_BPP)) >> 3) + 0x20;
.id = UCLASS_VIDEO,
.of_match = am335x_fb_ids,
.bind = am335x_fb_bind,
- .ofdata_to_platdata = am335x_fb_ofdata_to_platdata,
+ .of_to_plat = am335x_fb_of_to_plat,
.probe = am335x_fb_probe,
.remove = am335x_fb_remove,
- .priv_auto_alloc_size = sizeof(struct am335x_fb_priv),
+ .priv_auto = sizeof(struct am335x_fb_priv),
};
#endif /* CONFIG_DM_VIDEO */
static void atmel_hlcdc_init(struct udevice *dev)
{
- struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
+ struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
struct atmel_hlcdc_priv *priv = dev_get_priv(dev);
struct atmel_hlcd_regs *regs = priv->regs;
struct display_timing *timing = &priv->timing;
return 0;
}
-static int atmel_hlcdc_ofdata_to_platdata(struct udevice *dev)
+static int atmel_hlcdc_of_to_plat(struct udevice *dev)
{
struct atmel_hlcdc_priv *priv = dev_get_priv(dev);
const void *blob = gd->fdt_blob;
static int atmel_hlcdc_bind(struct udevice *dev)
{
- struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
+ struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
uc_plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
(1 << LCD_MAX_LOG2_BPP) / 8;
.of_match = atmel_hlcdc_ids,
.bind = atmel_hlcdc_bind,
.probe = atmel_hlcdc_probe,
- .ofdata_to_platdata = atmel_hlcdc_ofdata_to_platdata,
- .priv_auto_alloc_size = sizeof(struct atmel_hlcdc_priv),
+ .of_to_plat = atmel_hlcdc_of_to_plat,
+ .priv_auto = sizeof(struct atmel_hlcdc_priv),
};
#endif
#ifdef CONFIG_DM_VIDEO
static int atmel_fb_lcd_probe(struct udevice *dev)
{
- struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
+ struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
struct atmel_fb_priv *priv = dev_get_priv(dev);
struct display_timing *timing = &priv->timing;
return 0;
}
-static int atmel_fb_ofdata_to_platdata(struct udevice *dev)
+static int atmel_fb_of_to_plat(struct udevice *dev)
{
- struct atmel_lcd_platdata *plat = dev_get_platdata(dev);
+ struct atmel_lcd_plat *plat = dev_get_plat(dev);
struct atmel_fb_priv *priv = dev_get_priv(dev);
struct display_timing *timing = &priv->timing;
const void *blob = gd->fdt_blob;
static int atmel_fb_lcd_bind(struct udevice *dev)
{
- struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
+ struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
uc_plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
(1 << VIDEO_BPP16) / 8;
.id = UCLASS_VIDEO,
.of_match = atmel_fb_lcd_ids,
.bind = atmel_fb_lcd_bind,
- .ofdata_to_platdata = atmel_fb_ofdata_to_platdata,
+ .of_to_plat = atmel_fb_of_to_plat,
.probe = atmel_fb_lcd_probe,
- .platdata_auto_alloc_size = sizeof(struct atmel_lcd_platdata),
- .priv_auto_alloc_size = sizeof(struct atmel_fb_priv),
+ .plat_auto = sizeof(struct atmel_lcd_plat),
+ .priv_auto = sizeof(struct atmel_fb_priv),
};
#endif
return 0;
}
-static int gpio_backlight_ofdata_to_platdata(struct udevice *dev)
+static int gpio_backlight_of_to_plat(struct udevice *dev)
{
struct gpio_backlight_priv *priv = dev_get_priv(dev);
int ret;
.id = UCLASS_PANEL_BACKLIGHT,
.of_match = gpio_backlight_ids,
.ops = &gpio_backlight_ops,
- .ofdata_to_platdata = gpio_backlight_ofdata_to_platdata,
+ .of_to_plat = gpio_backlight_of_to_plat,
.probe = gpio_backlight_probe,
- .priv_auto_alloc_size = sizeof(struct gpio_backlight_priv),
+ .priv_auto = sizeof(struct gpio_backlight_priv),
};
static int bcm2835_video_probe(struct udevice *dev)
{
- struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
int ret;
int w, h, pitch;
static int anx6345_write_r0(struct udevice *dev, unsigned char reg_addr,
unsigned char value)
{
- struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
+ struct dm_i2c_chip *chip = dev_get_parent_plat(dev);
return anx6345_write(dev, chip->chip_addr, reg_addr, value);
}
static int anx6345_read_r0(struct udevice *dev, unsigned char reg_addr,
unsigned char *value)
{
- struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
+ struct dm_i2c_chip *chip = dev_get_parent_plat(dev);
return anx6345_read(dev, chip->chip_addr, reg_addr, value);
}
static int anx6345_write_r1(struct udevice *dev, unsigned char reg_addr,
unsigned char value)
{
- struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
+ struct dm_i2c_chip *chip = dev_get_parent_plat(dev);
return anx6345_write(dev, chip->chip_addr + 1, reg_addr, value);
}
static int anx6345_read_r1(struct udevice *dev, unsigned char reg_addr,
unsigned char *value)
{
- struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
+ struct dm_i2c_chip *chip = dev_get_parent_plat(dev);
return anx6345_read(dev, chip->chip_addr + 1, reg_addr, value);
}
.of_match = anx6345_ids,
.probe = anx6345_probe,
.ops = &anx6345_ops,
- .priv_auto_alloc_size = sizeof(struct anx6345_priv),
+ .priv_auto = sizeof(struct anx6345_priv),
};
static int ps8622_write(struct udevice *dev, unsigned addr_off,
unsigned char reg_addr, unsigned char value)
{
- struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
+ struct dm_i2c_chip *chip = dev_get_parent_plat(dev);
uint8_t buf[2];
struct i2c_msg msg;
int ret;
UCLASS_DRIVER(video_bridge) = {
.id = UCLASS_VIDEO_BRIDGE,
.name = "video_bridge",
- .per_device_auto_alloc_size = sizeof(struct video_bridge_priv),
+ .per_device_auto = sizeof(struct video_bridge_priv),
.pre_probe = video_bridge_pre_probe,
};
static void igd_setup_panel(struct udevice *dev)
{
- struct broadwell_igd_plat *plat = dev_get_platdata(dev);
+ struct broadwell_igd_plat *plat = dev_get_plat(dev);
struct broadwell_igd_priv *priv = dev_get_priv(dev);
u32 reg32;
static int igd_cdclk_init_haswell(struct udevice *dev)
{
- struct broadwell_igd_plat *plat = dev_get_platdata(dev);
+ struct broadwell_igd_plat *plat = dev_get_plat(dev);
struct broadwell_igd_priv *priv = dev_get_priv(dev);
int cdclk = plat->cdclk;
u16 devid;
static int igd_cdclk_init_broadwell(struct udevice *dev)
{
- struct broadwell_igd_plat *plat = dev_get_platdata(dev);
+ struct broadwell_igd_plat *plat = dev_get_plat(dev);
struct broadwell_igd_priv *priv = dev_get_priv(dev);
int cdclk = plat->cdclk;
u32 dpdiv, lpcll, pwctl, cdset;
static int igd_pre_init(struct udevice *dev, bool is_broadwell)
{
- struct broadwell_igd_plat *plat = dev_get_platdata(dev);
+ struct broadwell_igd_plat *plat = dev_get_plat(dev);
struct broadwell_igd_priv *priv = dev_get_priv(dev);
u32 rp1_gfx_freq;
int ret;
static int broadwell_igd_probe(struct udevice *dev)
{
- struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
bool is_broadwell;
ulong fbbase;
return 0;
}
-static int broadwell_igd_ofdata_to_platdata(struct udevice *dev)
+static int broadwell_igd_of_to_plat(struct udevice *dev)
{
- struct broadwell_igd_plat *plat = dev_get_platdata(dev);
+ struct broadwell_igd_plat *plat = dev_get_plat(dev);
struct broadwell_igd_priv *priv = dev_get_priv(dev);
int node = dev_of_offset(dev);
const void *blob = gd->fdt_blob;
static int broadwell_igd_bind(struct udevice *dev)
{
- struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
+ struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
/* Set the maximum supported resolution */
uc_plat->size = 2560 * 1600 * 4;
.id = UCLASS_VIDEO,
.of_match = broadwell_igd_ids,
.ops = &broadwell_igd_ops,
- .ofdata_to_platdata = broadwell_igd_ofdata_to_platdata,
+ .of_to_plat = broadwell_igd_of_to_plat,
.bind = broadwell_igd_bind,
.probe = broadwell_igd_probe,
- .priv_auto_alloc_size = sizeof(struct broadwell_igd_priv),
- .platdata_auto_alloc_size = sizeof(struct broadwell_igd_plat),
+ .priv_auto = sizeof(struct broadwell_igd_priv),
+ .plat_auto = sizeof(struct broadwell_igd_plat),
};
.id = UCLASS_VIDEO_CONSOLE,
.ops = &console_truetype_ops,
.probe = console_truetype_probe,
- .priv_auto_alloc_size = sizeof(struct console_tt_priv),
+ .priv_auto = sizeof(struct console_tt_priv),
};
static int coreboot_video_probe(struct udevice *dev)
{
- struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
struct cb_framebuffer *fb = lib_sysinfo.framebuffer;
struct vesa_mode_info *vesa = &mode_info.vesa;
if (ret)
return ret;
- disp_uc_plat = dev_get_uclass_platdata(dev);
+ disp_uc_plat = dev_get_uclass_plat(dev);
disp_uc_plat->in_use = true;
return 0;
bool display_in_use(struct udevice *dev)
{
- struct display_plat *disp_uc_plat = dev_get_uclass_platdata(dev);
+ struct display_plat *disp_uc_plat = dev_get_uclass_plat(dev);
return disp_uc_plat->in_use;
}
UCLASS_DRIVER(display) = {
.id = UCLASS_DISPLAY,
.name = "display",
- .per_device_platdata_auto_alloc_size = sizeof(struct display_plat),
+ .per_device_plat_auto = sizeof(struct display_plat),
};
.id = UCLASS_DSI_HOST,
.probe = dw_mipi_dsi_probe,
.ops = &dw_mipi_dsi_ops,
- .priv_auto_alloc_size = sizeof(struct dw_mipi_dsi),
+ .priv_auto = sizeof(struct dw_mipi_dsi),
};
static int efi_video_probe(struct udevice *dev)
{
- struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
struct vesa_mode_info *vesa = &mode_info.vesa;
int ret;
return ret;
}
-static int exynos_dp_ofdata_to_platdata(struct udevice *dev)
+static int exynos_dp_of_to_plat(struct udevice *dev)
{
struct exynos_dp_priv *priv = dev_get_priv(dev);
const void *blob = gd->fdt_blob;
.id = UCLASS_DISPLAY,
.of_match = exynos_dp_ids,
.ops = &exynos_dp_ops,
- .ofdata_to_platdata = exynos_dp_ofdata_to_platdata,
- .priv_auto_alloc_size = sizeof(struct exynos_dp_priv),
+ .of_to_plat = exynos_dp_of_to_plat,
+ .priv_auto = sizeof(struct exynos_dp_priv),
};
void exynos_fimd_lcd_init(struct udevice *dev)
{
struct exynos_fb_priv *priv = dev_get_priv(dev);
- struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
struct exynos_fb *reg = priv->reg;
unsigned int cfg = 0, rgb_mode;
unsigned int offset;
return priv->vl_col * priv->vl_row * (VNBITS(priv->vl_bpix) / 8);
}
-int exynos_fb_ofdata_to_platdata(struct udevice *dev)
+int exynos_fb_of_to_plat(struct udevice *dev)
{
struct exynos_fb_priv *priv = dev_get_priv(dev);
unsigned int node = dev_of_offset(dev);
static int exynos_fb_bind(struct udevice *dev)
{
- struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
/* This is the maximum panel size we expect to see */
plat->size = 1920 * 1080 * 2;
.ops = &exynos_fb_ops,
.bind = exynos_fb_bind,
.probe = exynos_fb_probe,
- .ofdata_to_platdata = exynos_fb_ofdata_to_platdata,
- .priv_auto_alloc_size = sizeof(struct exynos_fb_priv),
+ .of_to_plat = exynos_fb_of_to_plat,
+ .priv_auto = sizeof(struct exynos_fb_priv),
};
static int fsl_dcu_video_probe(struct udevice *dev)
{
- struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
struct fb_info fbinfo = { 0 };
unsigned int win_x;
static int fsl_dcu_video_bind(struct udevice *dev)
{
- struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
unsigned int win_x;
unsigned int win_y;
unsigned int depth = 0, freq = 0;
.ops = &ihs_video_out_ops,
.of_match = ihs_video_out_ids,
.probe = ihs_video_out_probe,
- .priv_auto_alloc_size = sizeof(struct ihs_video_out_priv),
+ .priv_auto = sizeof(struct ihs_video_out_priv),
};
static int mxcfb_map_video_memory(struct fb_info *fbi)
{
struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par;
- struct video_uc_platdata *plat = dev_get_uclass_platdata(mxc_fbi->udev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(mxc_fbi->udev);
if (fbi->fix.smem_len < fbi->var.yres_virtual * fbi->fix.line_length) {
fbi->fix.smem_len = fbi->var.yres_virtual *
static int ipuv3_video_probe(struct udevice *dev)
{
- struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
#if defined(CONFIG_DISPLAY)
struct udevice *disp_dev;
static int ipuv3_video_bind(struct udevice *dev)
{
- struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
(1 << VIDEO_BPP32) / 8;
.of_match = ipuv3_video_ids,
.bind = ipuv3_video_bind,
.probe = ipuv3_video_probe,
- .priv_auto_alloc_size = sizeof(struct ipuv3_video_priv),
+ .priv_auto = sizeof(struct ipuv3_video_priv),
.flags = DM_FLAG_PRE_RELOC,
};
static int bd82x6x_video_probe(struct udevice *dev)
{
- struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
ulong fbbase;
void *gtt_bar;
int ret, rev;
static int bd82x6x_video_bind(struct udevice *dev)
{
- struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
+ struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
/* Set the maximum supported resolution */
uc_plat->size = 2560 * 1600 * 4;
.enable = lg4573_lcd_enable,
};
-static int lg4573_ofdata_to_platdata(struct udevice *dev)
+static int lg4573_of_to_plat(struct udevice *dev)
{
struct lg4573_lcd_priv *priv = dev_get_priv(dev);
int ret;
.name = "lg4573",
.id = UCLASS_DISPLAY,
.ops = &lg4573_lcd_ops,
- .ofdata_to_platdata = lg4573_ofdata_to_platdata,
+ .of_to_plat = lg4573_of_to_plat,
.of_match = lg4573_ids,
.bind = lg4573_bind,
.probe = lg4573_probe,
- .priv_auto_alloc_size = sizeof(struct lg4573_lcd_priv),
+ .priv_auto = sizeof(struct lg4573_lcd_priv),
};
.id = UCLASS_DISPLAY,
.of_match = logicore_dp_tx_ids,
.probe = logicore_dp_tx_probe,
- .priv_auto_alloc_size = sizeof(struct dp_tx),
+ .priv_auto = sizeof(struct dp_tx),
.ops = &logicore_dp_tx_ops,
};
static int malidp_probe(struct udevice *dev)
{
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
- struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
+ struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
ofnode framebuffer = ofnode_find_subnode(dev_ofnode(dev), "framebuffer");
struct malidp_priv *priv = dev_get_priv(dev);
struct display_timing timings;
static int malidp_bind(struct udevice *dev)
{
- struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
+ struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
/* choose max possible size: 2K x 2K, XRGB888 framebuffer */
uc_plat->size = 4 * 2048 * 2048;
.of_match = malidp_ids,
.bind = malidp_bind,
.probe = malidp_probe,
- .priv_auto_alloc_size = sizeof(struct malidp_priv),
+ .priv_auto = sizeof(struct malidp_priv),
.ops = &malidp_ops,
};
.of_match = meson_dw_hdmi_ids,
.ops = &meson_dw_hdmi_ops,
.probe = meson_dw_hdmi_probe,
- .priv_auto_alloc_size = sizeof(struct meson_dw_hdmi),
+ .priv_auto = sizeof(struct meson_dw_hdmi),
};
void meson_vpu_setup_plane(struct udevice *dev, bool is_interlaced)
{
- struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
+ struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
struct meson_vpu_priv *priv = dev_get_priv(dev);
u32 osd1_ctrl_stat;
static int meson_vpu_setup_mode(struct udevice *dev, struct udevice *disp)
{
- struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
+ struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
struct display_timing timing;
bool is_cvbs = false;
static int meson_vpu_bind(struct udevice *dev)
{
- struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
plat->size = VPU_MAX_WIDTH * VPU_MAX_HEIGHT *
(1 << VPU_MAX_LOG2_BPP) / 8;
.of_match = meson_vpu_ids,
.probe = meson_vpu_probe,
.bind = meson_vpu_bind,
- .priv_auto_alloc_size = sizeof(struct meson_vpu_priv),
+ .priv_auto = sizeof(struct meson_vpu_priv),
.flags = DM_FLAG_PRE_RELOC | DM_FLAG_REMOVE_WITH_PD_ON,
};
static int mvebu_video_probe(struct udevice *dev)
{
- struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
struct mvebu_video_priv *priv = dev_get_priv(dev);
struct mvebu_lcd_info lcd_info;
static int mvebu_video_bind(struct udevice *dev)
{
- struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
(1 << LCD_MAX_LOG2_BPP) / 8;
.of_match = mvebu_video_ids,
.bind = mvebu_video_bind,
.probe = mvebu_video_probe,
- .priv_auto_alloc_size = sizeof(struct mvebu_video_priv),
+ .priv_auto = sizeof(struct mvebu_video_priv),
};
static int mxs_video_probe(struct udevice *dev)
{
- struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
struct display_timing timings;
static int mxs_video_bind(struct udevice *dev)
{
- struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
struct display_timing timings;
u32 bpp = 0;
u32 bytes_pp = 0;
static int mxs_video_remove(struct udevice *dev)
{
- struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
mxs_remove_common(plat->base);
static void nx_display_parse_dp_planes(ofnode node,
struct nx_display_dev *dp,
- struct video_uc_platdata *plat)
+ struct video_uc_plat *plat)
{
const char *name;
ofnode subnode;
static int nx_display_parse_dt(struct udevice *dev,
struct nx_display_dev *dp,
- struct video_uc_platdata *plat)
+ struct video_uc_plat *plat)
{
const char *name, *dtype;
int ret = 0;
struct nx_display_dev *dp;
int i, ret;
int node = 0;
- struct video_uc_platdata *plat = NULL;
+ struct video_uc_plat *plat = NULL;
struct udevice *dev;
__func__);
return NULL;
}
- plat = dev_get_uclass_platdata(dev);
+ plat = dev_get_uclass_plat(dev);
if (!dev) {
- debug("%s(): dev_get_uclass_platdata(dev) == NULL --> return NULL\n",
+ debug("%s(): dev_get_uclass_plat(dev) == NULL --> return NULL\n",
__func__);
return NULL;
}
static int nx_display_probe(struct udevice *dev)
{
- struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
+ struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
- struct nx_display_platdata *plat = dev_get_platdata(dev);
+ struct nx_display_plat *plat = dev_get_plat(dev);
static GraphicDevice *graphic_device;
char addr[64];
return -EINVAL;
if (!uc_plat) {
- debug("%s(): video_uc_platdata *plat == NULL --> return -EINVAL\n",
+ debug("%s(): video_uc_plat *plat == NULL --> return -EINVAL\n",
__func__);
return -EINVAL;
}
}
if (!plat) {
- debug("%s(): nx_display_platdata *plat == NULL --> return -EINVAL\n",
+ debug("%s(): nx_display_plat *plat == NULL --> return -EINVAL\n",
__func__);
return -EINVAL;
}
static int nx_display_bind(struct udevice *dev)
{
- struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
debug("%s()\n", __func__);
.name = "nexell-display",
.id = UCLASS_VIDEO,
.of_match = nx_display_ids,
- .platdata_auto_alloc_size =
- sizeof(struct nx_display_platdata),
+ .plat_auto = sizeof(struct nx_display_plat),
.bind = nx_display_bind,
.probe = nx_display_probe,
- .priv_auto_alloc_size = sizeof(struct nx_display_dev),
+ .priv_auto = sizeof(struct nx_display_dev),
};
static void otm8009a_dcs_write_buf(struct udevice *dev, const void *data,
size_t len)
{
- struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
+ struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
struct mipi_dsi_device *device = plat->device;
if (mipi_dsi_dcs_write_buffer(device, data, len) < 0)
static void otm8009a_dcs_write_buf_hs(struct udevice *dev, const void *data,
size_t len)
{
- struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
+ struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
struct mipi_dsi_device *device = plat->device;
/* data will be sent in dsi hs mode (ie. no lpm) */
static int otm8009a_init_sequence(struct udevice *dev)
{
- struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
+ struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
struct mipi_dsi_device *device = plat->device;
int ret;
static int otm8009a_panel_enable_backlight(struct udevice *dev)
{
- struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
+ struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
struct mipi_dsi_device *device = plat->device;
int ret;
return 0;
}
-static int otm8009a_panel_ofdata_to_platdata(struct udevice *dev)
+static int otm8009a_panel_of_to_plat(struct udevice *dev)
{
struct otm8009a_panel_priv *priv = dev_get_priv(dev);
int ret;
static int otm8009a_panel_probe(struct udevice *dev)
{
struct otm8009a_panel_priv *priv = dev_get_priv(dev);
- struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
+ struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
int ret;
if (IS_ENABLED(CONFIG_DM_REGULATOR) && priv->reg) {
.id = UCLASS_PANEL,
.of_match = otm8009a_panel_ids,
.ops = &otm8009a_panel_ops,
- .ofdata_to_platdata = otm8009a_panel_ofdata_to_platdata,
+ .of_to_plat = otm8009a_panel_of_to_plat,
.probe = otm8009a_panel_probe,
- .platdata_auto_alloc_size = sizeof(struct mipi_dsi_panel_plat),
- .priv_auto_alloc_size = sizeof(struct otm8009a_panel_priv),
+ .plat_auto = sizeof(struct mipi_dsi_panel_plat),
+ .priv_auto = sizeof(struct otm8009a_panel_priv),
};
switch (seq) {
case 0:
if (priv->reg) {
- __maybe_unused struct dm_regulator_uclass_platdata
+ __maybe_unused struct dm_regulator_uclass_plat
*plat;
- plat = dev_get_uclass_platdata(priv->reg);
+ plat = dev_get_uclass_plat(priv->reg);
log_debug("Enable '%s', regulator '%s'/'%s'\n",
dev->name, priv->reg->name, plat->name);
ret = regulator_set_enable(priv->reg, true);
return 0;
}
-static int pwm_backlight_ofdata_to_platdata(struct udevice *dev)
+static int pwm_backlight_of_to_plat(struct udevice *dev)
{
struct pwm_backlight_priv *priv = dev_get_priv(dev);
struct ofnode_phandle_args args;
.id = UCLASS_PANEL_BACKLIGHT,
.of_match = pwm_backlight_ids,
.ops = &pwm_backlight_ops,
- .ofdata_to_platdata = pwm_backlight_ofdata_to_platdata,
+ .of_to_plat = pwm_backlight_of_to_plat,
.probe = pwm_backlight_probe,
- .priv_auto_alloc_size = sizeof(struct pwm_backlight_priv),
+ .priv_auto = sizeof(struct pwm_backlight_priv),
};
static void rm68200_dcs_write_buf(struct udevice *dev, const void *data,
size_t len)
{
- struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
+ struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
struct mipi_dsi_device *device = plat->device;
int err;
static void rm68200_dcs_write_cmd(struct udevice *dev, u8 cmd, u8 value)
{
- struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
+ struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
struct mipi_dsi_device *device = plat->device;
int err;
static int rm68200_panel_enable_backlight(struct udevice *dev)
{
- struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
+ struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
struct mipi_dsi_device *device = plat->device;
struct rm68200_panel_priv *priv = dev_get_priv(dev);
int ret;
return 0;
}
-static int rm68200_panel_ofdata_to_platdata(struct udevice *dev)
+static int rm68200_panel_of_to_plat(struct udevice *dev)
{
struct rm68200_panel_priv *priv = dev_get_priv(dev);
int ret;
static int rm68200_panel_probe(struct udevice *dev)
{
struct rm68200_panel_priv *priv = dev_get_priv(dev);
- struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
+ struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
int ret;
if (IS_ENABLED(CONFIG_DM_REGULATOR) && priv->reg) {
.id = UCLASS_PANEL,
.of_match = rm68200_panel_ids,
.ops = &rm68200_panel_ops,
- .ofdata_to_platdata = rm68200_panel_ofdata_to_platdata,
+ .of_to_plat = rm68200_panel_of_to_plat,
.probe = rm68200_panel_probe,
- .platdata_auto_alloc_size = sizeof(struct mipi_dsi_panel_plat),
- .priv_auto_alloc_size = sizeof(struct rm68200_panel_priv),
+ .plat_auto = sizeof(struct mipi_dsi_panel_plat),
+ .priv_auto = sizeof(struct rm68200_panel_priv),
};
const struct display_timing *edid)
{
struct rk_hdmi_priv *priv = dev_get_priv(dev);
- struct display_plat *uc_plat = dev_get_uclass_platdata(dev);
+ struct display_plat *uc_plat = dev_get_uclass_plat(dev);
int vop_id = uc_plat->source_id;
struct rk3288_grf *grf = priv->grf;
return dw_hdmi_enable(&priv->hdmi, edid);
}
-static int rk3288_hdmi_ofdata_to_platdata(struct udevice *dev)
+static int rk3288_hdmi_of_to_plat(struct udevice *dev)
{
struct rk_hdmi_priv *priv = dev_get_priv(dev);
struct dw_hdmi *hdmi = &priv->hdmi;
hdmi->i2c_clk_high = 0x0d;
hdmi->i2c_clk_low = 0x0d;
- return rk_hdmi_ofdata_to_platdata(dev);
+ return rk_hdmi_of_to_plat(dev);
}
static int rk3288_clk_config(struct udevice *dev)
{
- struct display_plat *uc_plat = dev_get_uclass_platdata(dev);
+ struct display_plat *uc_plat = dev_get_uclass_plat(dev);
struct clk clk;
int ret;
.id = UCLASS_DISPLAY,
.of_match = rk3288_hdmi_ids,
.ops = &rk3288_hdmi_ops,
- .ofdata_to_platdata = rk3288_hdmi_ofdata_to_platdata,
+ .of_to_plat = rk3288_hdmi_of_to_plat,
.probe = rk3288_hdmi_probe,
- .priv_auto_alloc_size = sizeof(struct rk_hdmi_priv),
+ .priv_auto = sizeof(struct rk_hdmi_priv),
};
{
struct rk_mipi_priv *priv = dev_get_priv(dev);
struct rk3288_grf *grf = priv->grf;
- struct display_plat *disp_uc_plat = dev_get_uclass_platdata(dev);
+ struct display_plat *disp_uc_plat = dev_get_uclass_plat(dev);
/* Select the video source */
switch (disp_uc_plat->source_id) {
return 0;
}
-static int rk_mipi_ofdata_to_platdata(struct udevice *dev)
+static int rk_mipi_of_to_plat(struct udevice *dev)
{
struct rk_mipi_priv *priv = dev_get_priv(dev);
.name = "rk_mipi_dsi",
.id = UCLASS_DISPLAY,
.of_match = rk_mipi_dsi_ids,
- .ofdata_to_platdata = rk_mipi_ofdata_to_platdata,
+ .of_to_plat = rk_mipi_of_to_plat,
.probe = rk_mipi_probe,
.ops = &rk_mipi_dsi_ops,
- .priv_auto_alloc_size = sizeof(struct rk_mipi_priv),
+ .priv_auto = sizeof(struct rk_mipi_priv),
};
.bind = rk_vop_bind,
.probe = rk3288_vop_probe,
.remove = rk_vop_remove,
- .priv_auto_alloc_size = sizeof(struct rk_vop_priv),
+ .priv_auto = sizeof(struct rk_vop_priv),
};
const struct display_timing *edid)
{
struct rk_hdmi_priv *priv = dev_get_priv(dev);
- struct display_plat *uc_plat = dev_get_uclass_platdata(dev);
+ struct display_plat *uc_plat = dev_get_uclass_plat(dev);
int vop_id = uc_plat->source_id;
struct rk3399_grf_regs *grf = priv->grf;
return dw_hdmi_enable(&priv->hdmi, edid);
}
-static int rk3399_hdmi_ofdata_to_platdata(struct udevice *dev)
+static int rk3399_hdmi_of_to_plat(struct udevice *dev)
{
struct rk_hdmi_priv *priv = dev_get_priv(dev);
struct dw_hdmi *hdmi = &priv->hdmi;
hdmi->i2c_clk_high = 0x7a;
hdmi->i2c_clk_low = 0x8d;
- return rk_hdmi_ofdata_to_platdata(dev);
+ return rk_hdmi_of_to_plat(dev);
}
static const char * const rk3399_regulator_names[] = {
.id = UCLASS_DISPLAY,
.of_match = rk3399_hdmi_ids,
.ops = &rk3399_hdmi_ops,
- .ofdata_to_platdata = rk3399_hdmi_ofdata_to_platdata,
+ .of_to_plat = rk3399_hdmi_of_to_plat,
.probe = rk3399_hdmi_probe,
- .priv_auto_alloc_size = sizeof(struct rk_hdmi_priv),
+ .priv_auto = sizeof(struct rk_hdmi_priv),
};
{
struct rk_mipi_priv *priv = dev_get_priv(dev);
struct rk3399_grf_regs *grf = priv->grf;
- struct display_plat *disp_uc_plat = dev_get_uclass_platdata(dev);
+ struct display_plat *disp_uc_plat = dev_get_uclass_plat(dev);
/* Select the video source */
switch (disp_uc_plat->source_id) {
return 0;
}
-static int rk_mipi_ofdata_to_platdata(struct udevice *dev)
+static int rk_mipi_of_to_plat(struct udevice *dev)
{
struct rk_mipi_priv *priv = dev_get_priv(dev);
.name = "rk_mipi_dsi",
.id = UCLASS_DISPLAY,
.of_match = rk_mipi_dsi_ids,
- .ofdata_to_platdata = rk_mipi_ofdata_to_platdata,
+ .of_to_plat = rk_mipi_of_to_plat,
.probe = rk_mipi_probe,
.ops = &rk_mipi_dsi_ops,
- .priv_auto_alloc_size = sizeof(struct rk_mipi_priv),
+ .priv_auto = sizeof(struct rk_mipi_priv),
};
.ops = &rk3399_vop_ops,
.bind = rk_vop_bind,
.probe = rk3399_vop_probe,
- .priv_auto_alloc_size = sizeof(struct rk_vop_priv),
+ .priv_auto = sizeof(struct rk_vop_priv),
};
return edid_size;
}
-static int rk_edp_ofdata_to_platdata(struct udevice *dev)
+static int rk_edp_of_to_plat(struct udevice *dev)
{
struct rk_edp_priv *priv = dev_get_priv(dev);
static int rk_edp_probe(struct udevice *dev)
{
- struct display_plat *uc_plat = dev_get_uclass_platdata(dev);
+ struct display_plat *uc_plat = dev_get_uclass_plat(dev);
struct rk_edp_priv *priv = dev_get_priv(dev);
struct rk3288_edp *regs = priv->regs;
struct clk clk;
.id = UCLASS_DISPLAY,
.of_match = rockchip_dp_ids,
.ops = &dp_rockchip_ops,
- .ofdata_to_platdata = rk_edp_ofdata_to_platdata,
+ .of_to_plat = rk_edp_of_to_plat,
.probe = rk_edp_probe,
.remove = rk_edp_remove,
- .priv_auto_alloc_size = sizeof(struct rk_edp_priv),
+ .priv_auto = sizeof(struct rk_edp_priv),
};
return dw_hdmi_read_edid(&priv->hdmi, buf, buf_size);
}
-int rk_hdmi_ofdata_to_platdata(struct udevice *dev)
+int rk_hdmi_of_to_plat(struct udevice *dev)
{
struct rk_hdmi_priv *priv = dev_get_priv(dev);
struct dw_hdmi *hdmi = &priv->hdmi;
void rk_hdmi_probe_regulators(struct udevice *dev,
const char * const *names, int cnt);
/**
- * rk_hdmi_ofdata_to_platdata() - common ofdata_to_platdata implementation
+ * rk_hdmi_of_to_plat() - common of_to_plat implementation
*
* @dev: device
* @return 0 if OK, -ve if something went wrong
*/
-int rk_hdmi_ofdata_to_platdata(struct udevice *dev);
+int rk_hdmi_of_to_plat(struct udevice *dev);
/**
* rk_hdmi_probe() - common probe implementation
const struct display_timing *edid)
{
struct rk_lvds_priv *priv = dev_get_priv(dev);
- struct display_plat *uc_plat = dev_get_uclass_platdata(dev);
+ struct display_plat *uc_plat = dev_get_uclass_plat(dev);
int ret = 0;
unsigned int val = 0;
return 0;
}
-static int rk_lvds_ofdata_to_platdata(struct udevice *dev)
+static int rk_lvds_of_to_plat(struct udevice *dev)
{
struct rk_lvds_priv *priv = dev_get_priv(dev);
int ret;
.id = UCLASS_DISPLAY,
.of_match = rockchip_lvds_ids,
.ops = &lvds_rockchip_ops,
- .ofdata_to_platdata = rk_lvds_ofdata_to_platdata,
+ .of_to_plat = rk_lvds_of_to_plat,
.probe = rk_lvds_probe,
- .priv_auto_alloc_size = sizeof(struct rk_lvds_priv),
+ .priv_auto = sizeof(struct rk_lvds_priv),
};
break;
};
- disp_uc_plat = dev_get_uclass_platdata(disp);
+ disp_uc_plat = dev_get_uclass_plat(disp);
debug("Found device '%s', disp_uc_priv=%p\n", disp->name, disp_uc_plat);
if (display_in_use(disp)) {
debug(" - device in use\n");
int rk_vop_probe(struct udevice *dev)
{
- struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
struct rk_vop_priv *priv = dev_get_priv(dev);
int ret = 0;
ofnode port, node;
int rk_vop_bind(struct udevice *dev)
{
- struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
plat->size = 4 * (CONFIG_VIDEO_ROCKCHIP_MAX_XRES *
CONFIG_VIDEO_ROCKCHIP_MAX_YRES);
.id = UCLASS_DSI_HOST,
.of_match = sandbox_dsi_host_ids,
.ops = &sandbox_dsi_host_ops,
- .priv_auto_alloc_size = sizeof(struct sandbox_dsi_host_priv),
+ .priv_auto = sizeof(struct sandbox_dsi_host_priv),
};
.ops = &sandbox_osd_ops,
.of_match = sandbox_osd_ids,
.probe = sandbox_osd_probe,
- .priv_auto_alloc_size = sizeof(struct sandbox_osd_priv),
+ .priv_auto = sizeof(struct sandbox_osd_priv),
};
static int sandbox_sdl_probe(struct udevice *dev)
{
- struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
- struct sandbox_sdl_plat *plat = dev_get_platdata(dev);
+ struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
+ struct sandbox_sdl_plat *plat = dev_get_plat(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
struct sandbox_state *state = state_get_current();
int ret;
static int sandbox_sdl_bind(struct udevice *dev)
{
- struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
- struct sandbox_sdl_plat *plat = dev_get_platdata(dev);
+ struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
+ struct sandbox_sdl_plat *plat = dev_get_plat(dev);
int ret = 0;
plat->xres = dev_read_u32_default(dev, "xres", LCD_MAX_WIDTH);
.of_match = sandbox_sdl_ids,
.bind = sandbox_sdl_bind,
.probe = sandbox_sdl_probe,
- .platdata_auto_alloc_size = sizeof(struct sandbox_sdl_plat),
+ .plat_auto = sizeof(struct sandbox_sdl_plat),
};
return 0;
}
-static int simple_panel_ofdata_to_platdata(struct udevice *dev)
+static int simple_panel_of_to_plat(struct udevice *dev)
{
struct simple_panel_priv *priv = dev_get_priv(dev);
int ret;
.id = UCLASS_PANEL,
.of_match = simple_panel_ids,
.ops = &simple_panel_ops,
- .ofdata_to_platdata = simple_panel_ofdata_to_platdata,
+ .of_to_plat = simple_panel_of_to_plat,
.probe = simple_panel_probe,
- .priv_auto_alloc_size = sizeof(struct simple_panel_priv),
+ .priv_auto = sizeof(struct simple_panel_priv),
};
static int simple_video_probe(struct udevice *dev)
{
- struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
const void *blob = gd->fdt_blob;
const int node = dev_of_offset(dev);
return ret;
}
- mplat = dev_get_platdata(priv->panel);
+ mplat = dev_get_plat(priv->panel);
mplat->device = &priv->device;
device->lanes = mplat->lanes;
device->format = mplat->format;
.bind = stm32_dsi_bind,
.probe = stm32_dsi_probe,
.ops = &stm32_dsi_ops,
- .priv_auto_alloc_size = sizeof(struct stm32_dsi_priv),
+ .priv_auto = sizeof(struct stm32_dsi_priv),
};
static int stm32_ltdc_probe(struct udevice *dev)
{
- struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
+ struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
struct stm32_ltdc_priv *priv = dev_get_priv(dev);
struct udevice *bridge = NULL;
static int stm32_ltdc_bind(struct udevice *dev)
{
- struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
+ struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
uc_plat->size = CONFIG_VIDEO_STM32_MAX_XRES *
CONFIG_VIDEO_STM32_MAX_YRES *
.of_match = stm32_ltdc_ids,
.probe = stm32_ltdc_probe,
.bind = stm32_ltdc_bind,
- .priv_auto_alloc_size = sizeof(struct stm32_ltdc_priv),
+ .priv_auto = sizeof(struct stm32_ltdc_priv),
};
struct display_plat *disp_uc_plat;
int ret;
- disp_uc_plat = dev_get_uclass_platdata(disp);
+ disp_uc_plat = dev_get_uclass_plat(disp);
debug("Using device '%s', disp_uc_priv=%p\n", disp->name, disp_uc_plat);
if (display_in_use(disp)) {
debug(" - device in use\n");
static int sunxi_de2_probe(struct udevice *dev)
{
- struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
struct udevice *disp;
int ret;
static int sunxi_de2_bind(struct udevice *dev)
{
- struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
(1 << LCD_MAX_LOG2_BPP) / 8;
{
struct udevice *de2, *hdmi, *lcd;
struct video_priv *de2_priv;
- struct video_uc_platdata *de2_plat;
+ struct video_uc_plat *de2_plat;
int mux;
int offset, ret;
u64 start, size;
}
de2_priv = dev_get_uclass_priv(de2);
- de2_plat = dev_get_uclass_platdata(de2);
+ de2_plat = dev_get_uclass_plat(de2);
offset = sunxi_simplefb_fdt_match(blob, pipeline);
if (offset < 0) {
static int sunxi_dw_hdmi_probe(struct udevice *dev)
{
- struct display_plat *uc_plat = dev_get_uclass_platdata(dev);
+ struct display_plat *uc_plat = dev_get_uclass_plat(dev);
struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
struct sunxi_ccm_reg * const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
.id = UCLASS_DISPLAY,
.ops = &sunxi_dw_hdmi_ops,
.probe = sunxi_dw_hdmi_probe,
- .priv_auto_alloc_size = sizeof(struct sunxi_dw_hdmi_priv),
+ .priv_auto = sizeof(struct sunxi_dw_hdmi_priv),
};
U_BOOT_DEVICE(sunxi_dw_hdmi) = {
.id = UCLASS_DISPLAY,
.ops = &sunxi_lcd_ops,
.probe = sunxi_lcd_probe,
- .priv_auto_alloc_size = sizeof(struct sunxi_lcd_priv),
+ .priv_auto = sizeof(struct sunxi_lcd_priv),
};
#ifdef CONFIG_MACH_SUN50I
.of_match = tda19988_ids,
.ops = &tda19988_ops,
.probe = tda19988_probe,
- .priv_auto_alloc_size = sizeof(struct tda19988_priv),
+ .priv_auto = sizeof(struct tda19988_priv),
};
static int tegra_lcd_probe(struct udevice *dev)
{
- struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
struct tegra_lcd_priv *priv = dev_get_priv(dev);
const void *blob = gd->fdt_blob;
return 0;
}
-static int tegra_lcd_ofdata_to_platdata(struct udevice *dev)
+static int tegra_lcd_of_to_plat(struct udevice *dev)
{
struct tegra_lcd_priv *priv = dev_get_priv(dev);
const void *blob = gd->fdt_blob;
static int tegra_lcd_bind(struct udevice *dev)
{
- struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
const void *blob = gd->fdt_blob;
int node = dev_of_offset(dev);
int rgb;
.ops = &tegra_lcd_ops,
.bind = tegra_lcd_bind,
.probe = tegra_lcd_probe,
- .ofdata_to_platdata = tegra_lcd_ofdata_to_platdata,
- .priv_auto_alloc_size = sizeof(struct tegra_lcd_priv),
+ .of_to_plat = tegra_lcd_of_to_plat,
+ .priv_auto = sizeof(struct tegra_lcd_priv),
};
return ret;
}
- disp_uc_plat = dev_get_uclass_platdata(dp_dev);
+ disp_uc_plat = dev_get_uclass_plat(dp_dev);
debug("Found device '%s', disp_uc_priv=%p\n", dp_dev->name,
disp_uc_plat);
disp_uc_plat->src_dev = dev;
static int tegra124_lcd_probe(struct udevice *dev)
{
- struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
ulong start;
int ret;
static int tegra124_lcd_bind(struct udevice *dev)
{
- struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
+ struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
uc_plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
(1 << VIDEO_BPP16) / 8;
return 0;
}
-static int tegra_dp_ofdata_to_platdata(struct udevice *dev)
+static int tegra_dp_of_to_plat(struct udevice *dev)
{
- struct tegra_dp_plat *plat = dev_get_platdata(dev);
+ struct tegra_dp_plat *plat = dev_get_plat(dev);
plat->base = dev_read_addr(dev);
static int dp_tegra_probe(struct udevice *dev)
{
- struct tegra_dp_plat *plat = dev_get_platdata(dev);
+ struct tegra_dp_plat *plat = dev_get_plat(dev);
struct tegra_dp_priv *priv = dev_get_priv(dev);
- struct display_plat *disp_uc_plat = dev_get_uclass_platdata(dev);
+ struct display_plat *disp_uc_plat = dev_get_uclass_plat(dev);
priv->regs = (struct dpaux_ctlr *)plat->base;
priv->enabled = false;
.name = "dpaux_tegra",
.id = UCLASS_DISPLAY,
.of_match = tegra_dp_ids,
- .ofdata_to_platdata = tegra_dp_ofdata_to_platdata,
+ .of_to_plat = tegra_dp_of_to_plat,
.probe = dp_tegra_probe,
.ops = &dp_tegra_ops,
- .priv_auto_alloc_size = sizeof(struct tegra_dp_priv),
- .platdata_auto_alloc_size = sizeof(struct tegra_dp_plat),
+ .priv_auto = sizeof(struct tegra_dp_priv),
+ .plat_auto = sizeof(struct tegra_dp_plat),
};
return 0;
}
-static int tegra_sor_ofdata_to_platdata(struct udevice *dev)
+static int tegra_sor_of_to_plat(struct udevice *dev)
{
struct tegra_dc_sor_data *priv = dev_get_priv(dev);
int ret;
.name = "sor_tegra",
.id = UCLASS_VIDEO_BRIDGE,
.of_match = tegra_sor_ids,
- .ofdata_to_platdata = tegra_sor_ofdata_to_platdata,
+ .of_to_plat = tegra_sor_of_to_plat,
.ops = &tegra_sor_ops,
- .priv_auto_alloc_size = sizeof(struct tegra_dc_sor_data),
+ .priv_auto = sizeof(struct tegra_dc_sor_data),
};
static int vesa_video_probe(struct udevice *dev)
{
- struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
ulong fbbase;
int ret;
static int vesa_video_bind(struct udevice *dev)
{
- struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
+ struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
/* Set the maximum supported resolution */
uc_plat->size = 2560 * 1600 * 4;
.name = "vidconsole0",
.pre_probe = vidconsole_pre_probe,
.post_probe = vidconsole_post_probe,
- .per_device_auto_alloc_size = sizeof(struct vidconsole_priv),
+ .per_device_auto = sizeof(struct vidconsole_priv),
};
#ifdef CONFIG_VIDEO_COPY
* Theory of operation:
*
* Before relocation each device is bound. The driver for each device must
- * set the @align and @size values in struct video_uc_platdata. This
+ * set the @align and @size values in struct video_uc_plat. This
* information represents the requires size and alignment of the frame buffer
* for the device. The values can be an over-estimate but cannot be too
* small. The actual values will be suppled (in the same manner) by the bind()
static ulong alloc_fb(struct udevice *dev, ulong *addrp)
{
- struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
ulong base, align, size;
if (!plat->size)
/* Set up the display ready for use */
static int video_post_probe(struct udevice *dev)
{
- struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
struct video_priv *priv = dev_get_uclass_priv(dev);
char name[30], drv[15], *str;
const char *drv_name = drv;
.pre_probe = video_pre_probe,
.post_probe = video_post_probe,
.pre_remove = video_pre_remove,
- .priv_auto_alloc_size = sizeof(struct video_uc_priv),
- .per_device_auto_alloc_size = sizeof(struct video_priv),
- .per_device_platdata_auto_alloc_size = sizeof(struct video_uc_platdata),
+ .priv_auto = sizeof(struct video_uc_priv),
+ .per_device_auto = sizeof(struct video_priv),
+ .per_device_plat_auto = sizeof(struct video_uc_plat),
};
.child_post_bind = virtio_uclass_child_post_bind,
.child_pre_probe = virtio_uclass_child_pre_probe,
.child_post_probe = virtio_uclass_child_post_probe,
- .per_device_auto_alloc_size = sizeof(struct virtio_dev_priv),
+ .per_device_auto = sizeof(struct virtio_dev_priv),
};
static int virtio_blk_bind(struct udevice *dev)
{
struct virtio_dev_priv *uc_priv = dev_get_uclass_priv(dev->parent);
- struct blk_desc *desc = dev_get_uclass_platdata(dev);
+ struct blk_desc *desc = dev_get_uclass_plat(dev);
int devnum;
desc->if_type = IF_TYPE_VIRTIO;
static int virtio_blk_probe(struct udevice *dev)
{
struct virtio_blk_priv *priv = dev_get_priv(dev);
- struct blk_desc *desc = dev_get_uclass_platdata(dev);
+ struct blk_desc *desc = dev_get_uclass_plat(dev);
u64 cap;
int ret;
.bind = virtio_blk_bind,
.probe = virtio_blk_probe,
.remove = virtio_reset,
- .priv_auto_alloc_size = sizeof(struct virtio_blk_priv),
+ .priv_auto = sizeof(struct virtio_blk_priv),
.flags = DM_FLAG_ACTIVE_DMA,
};
return 0;
}
-static int virtio_mmio_ofdata_to_platdata(struct udevice *udev)
+static int virtio_mmio_of_to_plat(struct udevice *udev)
{
struct virtio_mmio_priv *priv = dev_get_priv(udev);
.of_match = virtio_mmio_ids,
.ops = &virtio_mmio_ops,
.probe = virtio_mmio_probe,
- .ofdata_to_platdata = virtio_mmio_ofdata_to_platdata,
- .priv_auto_alloc_size = sizeof(struct virtio_mmio_priv),
+ .of_to_plat = virtio_mmio_of_to_plat,
+ .priv_auto = sizeof(struct virtio_mmio_priv),
};
static int virtio_net_write_hwaddr(struct udevice *dev)
{
struct virtio_dev_priv *uc_priv = dev_get_uclass_priv(dev->parent);
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
int i;
/*
static int virtio_net_read_rom_hwaddr(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
if (!pdata)
return -ENOSYS;
.probe = virtio_net_probe,
.remove = virtio_reset,
.ops = &virtio_net_ops,
- .priv_auto_alloc_size = sizeof(struct virtio_net_priv),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct virtio_net_priv),
+ .plat_auto = sizeof(struct eth_pdata),
.flags = DM_FLAG_ACTIVE_DMA,
};
static int virtio_pci_probe(struct udevice *udev)
{
- struct pci_child_platdata *pplat = dev_get_parent_platdata(udev);
+ struct pci_child_plat *pplat = dev_get_parent_plat(udev);
struct virtio_dev_priv *uc_priv = dev_get_uclass_priv(udev);
struct virtio_pci_priv *priv = dev_get_priv(udev);
u16 subvendor, subdevice;
.ops = &virtio_pci_ops,
.bind = virtio_pci_bind,
.probe = virtio_pci_probe,
- .priv_auto_alloc_size = sizeof(struct virtio_pci_priv),
+ .priv_auto = sizeof(struct virtio_pci_priv),
};
static struct pci_device_id virtio_pci_supported[] = {
static int virtio_pci_probe(struct udevice *udev)
{
- struct pci_child_platdata *pplat = dev_get_parent_platdata(udev);
+ struct pci_child_plat *pplat = dev_get_parent_plat(udev);
struct virtio_dev_priv *uc_priv = dev_get_uclass_priv(udev);
struct virtio_pci_priv *priv = dev_get_priv(udev);
u16 subvendor;
.ops = &virtio_pci_ops,
.bind = virtio_pci_bind,
.probe = virtio_pci_probe,
- .priv_auto_alloc_size = sizeof(struct virtio_pci_priv),
+ .priv_auto = sizeof(struct virtio_pci_priv),
};
static struct pci_device_id virtio_pci_supported[] = {
.probe = virtio_rng_probe,
.remove = virtio_reset,
.ops = &virtio_rng_ops,
- .priv_auto_alloc_size = sizeof(struct virtio_rng_priv),
+ .priv_auto = sizeof(struct virtio_rng_priv),
.flags = DM_FLAG_ACTIVE_DMA,
};
.ops = &virtio_sandbox1_ops,
.probe = virtio_sandbox_probe,
.child_post_remove = virtio_sandbox_child_post_remove,
- .priv_auto_alloc_size = sizeof(struct virtio_sandbox_priv),
+ .priv_auto = sizeof(struct virtio_sandbox_priv),
};
/* this one without notify op */
.of_match = virtio_sandbox2_ids,
.ops = &virtio_sandbox2_ops,
.probe = virtio_sandbox_probe,
- .priv_auto_alloc_size = sizeof(struct virtio_sandbox_priv),
+ .priv_auto = sizeof(struct virtio_sandbox_priv),
};
{
struct w1_device *w1;
- w1 = dev_get_parent_platdata(dev);
+ w1 = dev_get_parent_plat(dev);
w1->id = 0;
return 0;
}
{
struct w1_device *w1;
- w1 = dev_get_parent_platdata(dev);
+ w1 = dev_get_parent_plat(dev);
w1->id = 0;
return 0;
}
if (dev_get_driver_data(dev) == family) {
struct w1_device *w1;
- w1 = dev_get_parent_platdata(dev);
+ w1 = dev_get_parent_plat(dev);
if (w1->id) /* device already in use */
continue;
w1->id = id;
int w1_eeprom_get_id(struct udevice *dev, u64 *id)
{
- struct w1_device *w1 = dev_get_parent_platdata(dev);
+ struct w1_device *w1 = dev_get_parent_plat(dev);
if (!w1)
return -ENODEV;
static u8 mxc_w1_read_byte(struct udevice *dev)
{
- struct mxc_w1_pdata *pdata = dev_get_platdata(dev);
+ struct mxc_w1_pdata *pdata = dev_get_plat(dev);
struct mxc_w1_regs *regs = pdata->regs;
u16 status;
static void mxc_w1_write_byte(struct udevice *dev, u8 byte)
{
- struct mxc_w1_pdata *pdata = dev_get_platdata(dev);
+ struct mxc_w1_pdata *pdata = dev_get_plat(dev);
struct mxc_w1_regs *regs = pdata->regs;
u16 status;
static bool mxc_w1_reset(struct udevice *dev)
{
- struct mxc_w1_pdata *pdata = dev_get_platdata(dev);
+ struct mxc_w1_pdata *pdata = dev_get_plat(dev);
u16 reg_val;
writew(MXC_W1_CONTROL_RPP, &pdata->regs->control);
static u8 mxc_w1_triplet(struct udevice *dev, bool bdir)
{
- struct mxc_w1_pdata *pdata = dev_get_platdata(dev);
+ struct mxc_w1_pdata *pdata = dev_get_plat(dev);
u8 id_bit = mxc_w1_touch_bit(pdata, 1);
u8 comp_bit = mxc_w1_touch_bit(pdata, 1);
u8 retval;
return retval;
}
-static int mxc_w1_ofdata_to_platdata(struct udevice *dev)
+static int mxc_w1_of_to_plat(struct udevice *dev)
{
- struct mxc_w1_pdata *pdata = dev_get_platdata(dev);
+ struct mxc_w1_pdata *pdata = dev_get_plat(dev);
fdt_addr_t addr;
addr = dev_read_addr(dev);
static int mxc_w1_probe(struct udevice *dev)
{
- struct mxc_w1_pdata *pdata = dev_get_platdata(dev);
+ struct mxc_w1_pdata *pdata = dev_get_plat(dev);
unsigned int clkrate = mxc_get_clock(MXC_IPG_PERCLK);
unsigned int clkdiv;
.id = UCLASS_W1,
.name = "mxc_w1_drv",
.of_match = mxc_w1_id,
- .ofdata_to_platdata = mxc_w1_ofdata_to_platdata,
+ .of_to_plat = mxc_w1_of_to_plat,
.ops = &mxc_w1_ops,
- .platdata_auto_alloc_size = sizeof(struct mxc_w1_pdata),
+ .plat_auto = sizeof(struct mxc_w1_pdata),
.probe = mxc_w1_probe,
};
static bool w1_gpio_read_bit(struct udevice *dev)
{
- struct w1_gpio_pdata *pdata = dev_get_platdata(dev);
+ struct w1_gpio_pdata *pdata = dev_get_plat(dev);
int val;
dm_gpio_set_dir_flags(&pdata->gpio, GPIOD_IS_OUT);
static void w1_gpio_write_bit(struct udevice *dev, bool bit)
{
- struct w1_gpio_pdata *pdata = dev_get_platdata(dev);
+ struct w1_gpio_pdata *pdata = dev_get_plat(dev);
dm_gpio_set_dir_flags(&pdata->gpio, GPIOD_IS_OUT);
static bool w1_gpio_reset(struct udevice *dev)
{
- struct w1_gpio_pdata *pdata = dev_get_platdata(dev);
+ struct w1_gpio_pdata *pdata = dev_get_plat(dev);
int val;
/* initiate the reset pulse. first we must pull the bus to low */
.write_byte = w1_gpio_write_byte,
};
-static int w1_gpio_ofdata_to_platdata(struct udevice *dev)
+static int w1_gpio_of_to_plat(struct udevice *dev)
{
- struct w1_gpio_pdata *pdata = dev_get_platdata(dev);
+ struct w1_gpio_pdata *pdata = dev_get_plat(dev);
int ret;
ret = gpio_request_by_name(dev, "gpios", 0, &pdata->gpio, 0);
.id = UCLASS_W1,
.name = "w1_gpio_drv",
.of_match = w1_gpio_id,
- .ofdata_to_platdata = w1_gpio_ofdata_to_platdata,
+ .of_to_plat = w1_gpio_of_to_plat,
.ops = &w1_gpio_ops,
- .platdata_auto_alloc_size = sizeof(struct w1_gpio_pdata),
+ .plat_auto = sizeof(struct w1_gpio_pdata),
};
u8 w1_get_device_family(struct udevice *dev)
{
- struct w1_device *w1 = dev_get_parent_platdata(dev);
+ struct w1_device *w1 = dev_get_parent_plat(dev);
return w1->id & 0xff;
}
int w1_reset_select(struct udevice *dev)
{
- struct w1_device *w1 = dev_get_parent_platdata(dev);
+ struct w1_device *w1 = dev_get_parent_plat(dev);
struct udevice *bus = dev_get_parent(dev);
const struct w1_ops *ops = device_get_ops(bus);
int i;
.name = "w1",
.id = UCLASS_W1,
.flags = DM_UC_FLAG_SEQ_ALIAS,
- .per_device_auto_alloc_size = sizeof(struct w1_bus),
+ .per_device_auto = sizeof(struct w1_bus),
.post_probe = w1_post_probe,
#if CONFIG_IS_ENABLED(OF_CONTROL)
.post_bind = dm_scan_fdt_dev,
#endif
- .per_child_platdata_auto_alloc_size = sizeof(struct w1_device),
+ .per_child_plat_auto = sizeof(struct w1_device),
};
.id = UCLASS_WDT,
.of_match = a37xx_wdt_ids,
.probe = a37xx_wdt_probe,
- .priv_auto_alloc_size = sizeof(struct a37xx_wdt),
+ .priv_auto = sizeof(struct a37xx_wdt),
.ops = &a37xx_wdt_ops,
};
return ast_wdt_stop(dev);
}
-static int ast_wdt_ofdata_to_platdata(struct udevice *dev)
+static int ast_wdt_of_to_plat(struct udevice *dev)
{
struct ast_wdt_priv *priv = dev_get_priv(dev);
.id = UCLASS_WDT,
.of_match = ast_wdt_ids,
.probe = ast_wdt_probe,
- .priv_auto_alloc_size = sizeof(struct ast_wdt_priv),
- .ofdata_to_platdata = ast_wdt_ofdata_to_platdata,
+ .priv_auto = sizeof(struct ast_wdt_priv),
+ .of_to_plat = ast_wdt_of_to_plat,
.ops = &ast_wdt_ops,
};
.name = "atmel_at91sam9260_wdt",
.id = UCLASS_WDT,
.of_match = at91_wdt_ids,
- .priv_auto_alloc_size = sizeof(struct at91_wdt_priv),
+ .priv_auto = sizeof(struct at91_wdt_priv),
.ops = &at91_wdt_ops,
.probe = at91_wdt_probe,
};
.id = UCLASS_WDT,
.of_match = bcm6345_wdt_ids,
.ops = &bcm6345_wdt_ops,
- .priv_auto_alloc_size = sizeof(struct bcm6345_wdt_priv),
+ .priv_auto = sizeof(struct bcm6345_wdt_priv),
.probe = bcm6345_wdt_probe,
};
return 0;
}
-static int cdns_wdt_ofdata_to_platdata(struct udevice *dev)
+static int cdns_wdt_of_to_plat(struct udevice *dev)
{
struct cdns_wdt_priv *priv = dev_get_priv(dev);
.id = UCLASS_WDT,
.of_match = cdns_wdt_ids,
.probe = cdns_wdt_probe,
- .priv_auto_alloc_size = sizeof(struct cdns_wdt_priv),
- .ofdata_to_platdata = cdns_wdt_ofdata_to_platdata,
+ .priv_auto = sizeof(struct cdns_wdt_priv),
+ .of_to_plat = cdns_wdt_of_to_plat,
.ops = &cdns_wdt_ops,
};
.name = "designware_wdt",
.id = UCLASS_WDT,
.of_match = designware_wdt_ids,
- .priv_auto_alloc_size = sizeof(struct designware_wdt_priv),
+ .priv_auto = sizeof(struct designware_wdt_priv),
.probe = designware_wdt_probe,
.ops = &designware_wdt_ops,
.flags = DM_FLAG_PRE_RELOC,
.of_match = imx_wdt_ids,
.probe = imx_wdt_probe,
.ops = &imx_wdt_ops,
- .priv_auto_alloc_size = sizeof(struct imx_wdt_priv),
+ .priv_auto = sizeof(struct imx_wdt_priv),
.flags = DM_FLAG_PRE_RELOC,
};
#endif
.id = UCLASS_WDT,
.of_match = mt762x_wdt_ids,
.probe = mt762x_wdt_probe,
- .priv_auto_alloc_size = sizeof(struct mt762x_wdt),
+ .priv_auto = sizeof(struct mt762x_wdt),
.ops = &mt762x_wdt_ops,
};
.name = "mtk_wdt",
.id = UCLASS_WDT,
.of_match = mtk_wdt_ids,
- .priv_auto_alloc_size = sizeof(struct mtk_wdt_priv),
+ .priv_auto = sizeof(struct mtk_wdt_priv),
.probe = mtk_wdt_probe,
.ops = &mtk_wdt_ops,
.flags = DM_FLAG_PRE_RELOC,
.id = UCLASS_WDT,
.of_match = octeontx_wdt_ids,
.ops = &octeontx_wdt_ops,
- .priv_auto_alloc_size = sizeof(struct octeontx_wdt),
+ .priv_auto = sizeof(struct octeontx_wdt),
.probe = octeontx_wdt_probe,
.remove = octeontx_wdt_remove,
.flags = DM_FLAG_OS_PREPARE,
.of_match = omap3_wdt_ids,
.ops = &omap3_wdt_ops,
.probe = omap3_wdt_probe,
- .priv_auto_alloc_size = sizeof(struct omap3_wdt_priv),
+ .priv_auto = sizeof(struct omap3_wdt_priv),
};
#endif /* !CONFIG_IS_ENABLED(WDT) */
return true;
}
-static int orion_wdt_ofdata_to_platdata(struct udevice *dev)
+static int orion_wdt_of_to_plat(struct udevice *dev)
{
struct orion_wdt_priv *priv = dev_get_priv(dev);
.id = UCLASS_WDT,
.of_match = orion_wdt_ids,
.probe = orion_wdt_probe,
- .priv_auto_alloc_size = sizeof(struct orion_wdt_priv),
- .ofdata_to_platdata = orion_wdt_ofdata_to_platdata,
+ .priv_auto = sizeof(struct orion_wdt_priv),
+ .of_to_plat = orion_wdt_of_to_plat,
.ops = &orion_wdt_ops,
};
.of_match = rti_wdt_ids,
.ops = &rti_wdt_ops,
.probe = rti_wdt_probe,
- .priv_auto_alloc_size = sizeof(struct rti_wdt_priv),
+ .priv_auto = sizeof(struct rti_wdt_priv),
.flags = DM_FLAG_REMOVE_WITH_PD_ON,
};
return 0;
}
-static int sbsa_gwdt_ofdata_to_platdata(struct udevice *dev)
+static int sbsa_gwdt_of_to_plat(struct udevice *dev)
{
struct sbsa_gwdt_priv *priv = dev_get_priv(dev);
.id = UCLASS_WDT,
.of_match = sbsa_gwdt_ids,
.probe = sbsa_gwdt_probe,
- .priv_auto_alloc_size = sizeof(struct sbsa_gwdt_priv),
- .ofdata_to_platdata = sbsa_gwdt_ofdata_to_platdata,
+ .priv_auto = sizeof(struct sbsa_gwdt_priv),
+ .of_to_plat = sbsa_gwdt_of_to_plat,
.ops = &sbsa_gwdt_ops,
};
return 0;
}
-static int sp805_wdt_ofdata_to_platdata(struct udevice *dev)
+static int sp805_wdt_of_to_plat(struct udevice *dev)
{
struct sp805_wdt_priv *priv = dev_get_priv(dev);
struct clk clk;
.id = UCLASS_WDT,
.of_match = sp805_wdt_ids,
.probe = sp805_wdt_probe,
- .priv_auto_alloc_size = sizeof(struct sp805_wdt_priv),
- .ofdata_to_platdata = sp805_wdt_ofdata_to_platdata,
+ .priv_auto = sizeof(struct sp805_wdt_priv),
+ .of_to_plat = sp805_wdt_of_to_plat,
.ops = &sp805_wdt_ops,
};
.name = "stm32mp-wdt",
.id = UCLASS_WDT,
.of_match = stm32mp_wdt_match,
- .priv_auto_alloc_size = sizeof(struct stm32mp_wdt_priv),
+ .priv_auto = sizeof(struct stm32mp_wdt_priv),
.probe = stm32mp_wdt_probe,
.ops = &stm32mp_wdt_ops,
};
u32 tbr; /* 0x8 */
};
-struct xlnx_wdt_platdata {
+struct xlnx_wdt_plat {
bool enable_once;
struct watchdog_regs *regs;
};
static int xlnx_wdt_reset(struct udevice *dev)
{
u32 reg;
- struct xlnx_wdt_platdata *platdata = dev_get_platdata(dev);
+ struct xlnx_wdt_plat *plat = dev_get_plat(dev);
debug("%s ", __func__);
/* Read the current contents of TCSR0 */
- reg = readl(&platdata->regs->twcsr0);
+ reg = readl(&plat->regs->twcsr0);
/* Clear the watchdog WDS bit */
if (reg & (XWT_CSR0_EWDT1_MASK | XWT_CSRX_EWDT2_MASK))
- writel(reg | XWT_CSR0_WDS_MASK, &platdata->regs->twcsr0);
+ writel(reg | XWT_CSR0_WDS_MASK, &plat->regs->twcsr0);
return 0;
}
static int xlnx_wdt_stop(struct udevice *dev)
{
u32 reg;
- struct xlnx_wdt_platdata *platdata = dev_get_platdata(dev);
+ struct xlnx_wdt_plat *plat = dev_get_plat(dev);
- if (platdata->enable_once) {
+ if (plat->enable_once) {
debug("Can't stop Xilinx watchdog.\n");
return -EBUSY;
}
/* Read the current contents of TCSR0 */
- reg = readl(&platdata->regs->twcsr0);
+ reg = readl(&plat->regs->twcsr0);
- writel(reg & ~XWT_CSR0_EWDT1_MASK, &platdata->regs->twcsr0);
- writel(~XWT_CSRX_EWDT2_MASK, &platdata->regs->twcsr1);
+ writel(reg & ~XWT_CSR0_EWDT1_MASK, &plat->regs->twcsr0);
+ writel(~XWT_CSRX_EWDT2_MASK, &plat->regs->twcsr1);
debug("Watchdog disabled!\n");
static int xlnx_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
{
- struct xlnx_wdt_platdata *platdata = dev_get_platdata(dev);
+ struct xlnx_wdt_plat *plat = dev_get_plat(dev);
debug("%s:\n", __func__);
writel((XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK | XWT_CSR0_EWDT1_MASK),
- &platdata->regs->twcsr0);
+ &plat->regs->twcsr0);
- writel(XWT_CSRX_EWDT2_MASK, &platdata->regs->twcsr1);
+ writel(XWT_CSRX_EWDT2_MASK, &plat->regs->twcsr1);
return 0;
}
return 0;
}
-static int xlnx_wdt_ofdata_to_platdata(struct udevice *dev)
+static int xlnx_wdt_of_to_plat(struct udevice *dev)
{
- struct xlnx_wdt_platdata *platdata = dev_get_platdata(dev);
+ struct xlnx_wdt_plat *plat = dev_get_plat(dev);
- platdata->regs = (struct watchdog_regs *)dev_read_addr(dev);
- if (IS_ERR(platdata->regs))
- return PTR_ERR(platdata->regs);
+ plat->regs = (struct watchdog_regs *)dev_read_addr(dev);
+ if (IS_ERR(plat->regs))
+ return PTR_ERR(plat->regs);
- platdata->enable_once = dev_read_u32_default(dev,
- "xlnx,wdt-enable-once", 0);
+ plat->enable_once = dev_read_u32_default(dev, "xlnx,wdt-enable-once",
+ 0);
- debug("%s: wdt-enable-once %d\n", __func__, platdata->enable_once);
+ debug("%s: wdt-enable-once %d\n", __func__, plat->enable_once);
return 0;
}
.id = UCLASS_WDT,
.of_match = xlnx_wdt_ids,
.probe = xlnx_wdt_probe,
- .platdata_auto_alloc_size = sizeof(struct xlnx_wdt_platdata),
- .ofdata_to_platdata = xlnx_wdt_ofdata_to_platdata,
+ .plat_auto = sizeof(struct xlnx_wdt_plat),
+ .of_to_plat = xlnx_wdt_of_to_plat,
.ops = &xlnx_wdt_ops,
};
struct clk clk;
};
-struct xlnx_wwdt_platdata {
+struct xlnx_wwdt_plat {
bool enable_once;
};
static int xlnx_wwdt_probe(struct udevice *dev)
{
int ret;
- struct xlnx_wwdt_platdata *platdata = dev_get_platdata(dev);
+ struct xlnx_wwdt_plat *plat = dev_get_plat(dev);
struct xlnx_wwdt_priv *wdt = dev_get_priv(dev);
dev_dbg(dev, "%s: Probing wdt%u\n", __func__, dev->seq);
return ret;
}
- wdt->enable_once = platdata->enable_once;
+ wdt->enable_once = plat->enable_once;
ret = clk_get_by_index(dev, 0, &wdt->clk);
if (ret < 0)
return ret;
}
-static int xlnx_wwdt_ofdata_to_platdata(struct udevice *dev)
+static int xlnx_wwdt_of_to_plat(struct udevice *dev)
{
- struct xlnx_wwdt_platdata *platdata = dev_get_platdata(dev);
+ struct xlnx_wwdt_plat *plat = dev_get_plat(dev);
- platdata->enable_once = dev_read_u32_default(dev,
- "xlnx,wdt-enable-once", 0);
- dev_dbg(dev, "wdt-enable-once %d\n", platdata->enable_once);
+ plat->enable_once = dev_read_u32_default(dev, "xlnx,wdt-enable-once",
+ 0);
+ dev_dbg(dev, "wdt-enable-once %d\n", plat->enable_once);
return 0;
}
.id = UCLASS_WDT,
.of_match = xlnx_wwdt_ids,
.probe = xlnx_wwdt_probe,
- .priv_auto_alloc_size = sizeof(struct xlnx_wwdt_priv),
- .platdata_auto_alloc_size = sizeof(struct xlnx_wwdt_platdata),
- .ofdata_to_platdata = xlnx_wwdt_ofdata_to_platdata,
+ .priv_auto = sizeof(struct xlnx_wwdt_priv),
+ .plat_auto = sizeof(struct xlnx_wwdt_plat),
+ .of_to_plat = xlnx_wwdt_of_to_plat,
.ops = &xlnx_wwdt_ops,
};
u8 *bounce_buffer;
};
-struct blkfront_platdata {
+struct blkfront_plat {
unsigned int devid;
};
lbaint_t blkcnt, void *buffer, int write)
{
struct blkfront_dev *blk_dev = dev_get_priv(udev);
- struct blk_desc *desc = dev_get_uclass_platdata(udev);
+ struct blk_desc *desc = dev_get_uclass_plat(udev);
struct blkfront_aiocb aiocb;
lbaint_t blocks_todo;
bool unaligned;
static int pvblock_blk_bind(struct udevice *udev)
{
- struct blk_desc *desc = dev_get_uclass_platdata(udev);
+ struct blk_desc *desc = dev_get_uclass_plat(udev);
int devnum;
desc->if_type = IF_TYPE_PVBLOCK;
static int pvblock_blk_probe(struct udevice *udev)
{
struct blkfront_dev *blk_dev = dev_get_priv(udev);
- struct blkfront_platdata *platdata = dev_get_platdata(udev);
- struct blk_desc *desc = dev_get_uclass_platdata(udev);
+ struct blkfront_plat *plat = dev_get_plat(udev);
+ struct blk_desc *desc = dev_get_uclass_plat(udev);
int ret, devid;
- devid = platdata->devid;
- free(platdata);
+ devid = plat->devid;
+ free(plat);
ret = init_blkfront(devid, blk_dev);
if (ret < 0)
.bind = pvblock_blk_bind,
.probe = pvblock_blk_probe,
.remove = pvblock_blk_remove,
- .priv_auto_alloc_size = sizeof(struct blkfront_dev),
+ .priv_auto = sizeof(struct blkfront_dev),
.flags = DM_FLAG_OS_PREPARE,
};
{
struct driver_info info;
struct udevice *udev;
- struct blkfront_platdata *platdata;
+ struct blkfront_plat *plat;
int ret;
debug("New " DRV_NAME_BLK ", device ID %d\n", devid);
- platdata = malloc(sizeof(struct blkfront_platdata));
- if (!platdata) {
+ plat = malloc(sizeof(struct blkfront_plat));
+ if (!plat) {
printf("Failed to allocate platform data\n");
return -ENOMEM;
}
- platdata->devid = devid;
+ plat->devid = devid;
info.name = DRV_NAME_BLK;
- info.platdata = platdata;
+ info.plat = plat;
ret = device_bind_by_name(parent, false, &info, &udev);
if (ret < 0) {
printf("Failed to bind " DRV_NAME_BLK " to device with ID %d, ret: %d\n",
devid, ret);
- free(platdata);
+ free(plat);
}
return ret;
}
class_name = uclass_get_name(UCLASS_PVBLOCK);
for (blk_first_device(IF_TYPE_PVBLOCK, &udev); udev;
blk_next_device(&udev), first = false) {
- struct blk_desc *desc = dev_get_uclass_platdata(udev);
+ struct blk_desc *desc = dev_get_uclass_plat(udev);
if (!first)
puts(", ");
};
/**
- * struct adc_uclass_platdata - basic ADC info
+ * struct adc_uclass_plat - basic ADC info
*
* Note: The positive/negative reference Voltage is only a name and it doesn't
* provide an information about the value polarity. It is possible, for both
* @vdd_microvolts - positive reference Voltage value
* @vss_microvolts - negative reference Voltage value
*/
-struct adc_uclass_platdata {
+struct adc_uclass_plat {
int data_format;
unsigned int data_mask;
unsigned int data_timeout_us;
#define _ATMEL_LCD_H_
/**
- * struct atmel_lcd_platdata - platform data for Atmel LCDs with driver model
+ * struct atmel_lcd_plat - platform data for Atmel LCDs with driver model
*
* @timing_index: Index of LCD timing to use in device tree node
*/
-struct atmel_lcd_platdata {
+struct atmel_lcd_plat {
int timing_index;
};
/*
* With driver model (CONFIG_BLK) this is uclass platform data, accessible
- * with dev_get_uclass_platdata(dev)
+ * with dev_get_uclass_plat(dev)
*/
struct blk_desc {
/*
#define __CPU_H
/**
- * struct cpu_platdata - platform data for a CPU
+ * struct cpu_plat - platform data for a CPU
* @cpu_id: Platform-specific way of identifying the CPU.
* @ucode_version: Microcode version, if CPU_FEAT_UCODE is set
* @device_id: Driver-defined device identifier
* @timebase_freq: the current frequency at which the cpu timer timebase
* registers are updated (in Hz)
*
- * This can be accessed with dev_get_parent_platdata() for any UCLASS_CPU
+ * This can be accessed with dev_get_parent_plat() for any UCLASS_CPU
* device.
*/
-struct cpu_platdata {
+struct cpu_plat {
int cpu_id;
int ucode_version;
ulong device_id;
* device_bind() - Create a device and bind it to a driver
*
* Called to set up a new device attached to a driver. The device will either
- * have platdata, or a device tree node which can be used to create the
- * platdata.
+ * have plat, or a device tree node which can be used to create the
+ * plat.
*
* Once bound a device exists but is not yet active until device_probe() is
* called.
* @parent: Pointer to device's parent, under which this driver will exist
* @drv: Device's driver
* @name: Name of device (e.g. device tree node name)
- * @platdata: Pointer to data for this device - the structure is device-
+ * @plat: Pointer to data for this device - the structure is device-
* specific but may include the device's I/O address, etc.. This is NULL for
* devices which use device tree.
- * @of_offset: Offset of device tree node for this device. This is -1 for
- * devices which don't use device tree.
+ * @ofnode: Devicetree node for this device. This is ofnode_null() for
+ * devices which don't use devicetree or don't have a node.
* @devp: if non-NULL, returns a pointer to the bound device
* @return 0 if OK, -ve on error
*/
int device_bind(struct udevice *parent, const struct driver *drv,
- const char *name, void *platdata, int of_offset,
+ const char *name, void *plat, ofnode node,
struct udevice **devp);
-int device_bind_ofnode(struct udevice *parent, const struct driver *drv,
- const char *name, void *platdata, ofnode node,
- struct udevice **devp);
-
/**
* device_bind_with_driver_data() - Create a device and bind it to a driver
*
* @parent: Pointer to device's parent
* @pre_reloc_only: If true, bind the driver only if its DM_FLAG_PRE_RELOC flag
* is set. If false bind the driver always.
- * @info: Name and platdata for this device
+ * @info: Name and plat for this device
* @devp: if non-NULL, returns a pointer to the bound device
* @return 0 if OK, -ve on error
*/
int device_reparent(struct udevice *dev, struct udevice *new_parent);
/**
- * device_ofdata_to_platdata() - Read platform data for a device
+ * device_of_to_plat() - Read platform data for a device
*
* Read platform data for a device (typically from the device tree) so that
* the information needed to probe the device is present.
* @dev: Pointer to device to process
* @return 0 if OK, -ve on error
*/
-int device_ofdata_to_platdata(struct udevice *dev);
+int device_of_to_plat(struct udevice *dev);
/**
* device_probe() - Probe a device, activating it
/* Driver is active (probed). Cleared when it is removed */
#define DM_FLAG_ACTIVATED (1 << 0)
-/* DM is responsible for allocating and freeing platdata */
+/* DM is responsible for allocating and freeing plat */
#define DM_FLAG_ALLOC_PDATA (1 << 1)
/* DM should init this device prior to relocation */
#define DM_FLAG_PRE_RELOC (1 << 2)
-/* DM is responsible for allocating and freeing parent_platdata */
+/* DM is responsible for allocating and freeing parent_plat */
#define DM_FLAG_ALLOC_PARENT_PDATA (1 << 3)
-/* DM is responsible for allocating and freeing uclass_platdata */
+/* DM is responsible for allocating and freeing uclass_plat */
#define DM_FLAG_ALLOC_UCLASS_PDATA (1 << 4)
/* Allocate driver private data on a DMA boundary */
/* DM does not enable/disable the power domains corresponding to this device */
#define DM_FLAG_DEFAULT_PD_CTRL_OFF (1 << 11)
-/* Driver platdata has been read. Cleared when the device is removed */
+/* Driver plat has been read. Cleared when the device is removed */
#define DM_FLAG_PLATDATA_VALID (1 << 12)
/*
* particular port or peripheral (essentially a driver instance).
*
* A device will come into existence through a 'bind' call, either due to
- * a U_BOOT_DEVICE() macro (in which case platdata is non-NULL) or a node
+ * a U_BOOT_DEVICE() macro (in which case plat is non-NULL) or a node
* in the device tree (in which case of_offset is >= 0). In the latter case
- * we translate the device tree information into platdata in a function
- * implemented by the driver ofdata_to_platdata method (called just before the
+ * we translate the device tree information into plat in a function
+ * implemented by the driver of_to_plat method (called just before the
* probe method if the device has a device tree node.
*
- * All three of platdata, priv and uclass_priv can be allocated by the
+ * All three of plat, priv and uclass_priv can be allocated by the
* driver, or you can use the auto_alloc_size members of struct driver and
* struct uclass_driver to have driver model do this automatically.
*
* @driver: The driver used by this device
* @name: Name of device, typically the FDT node name
- * @platdata: Configuration data for this device
- * @parent_platdata: The parent bus's configuration data for this device
- * @uclass_platdata: The uclass's configuration data for this device
+ * @plat: Configuration data for this device
+ * @parent_plat: The parent bus's configuration data for this device
+ * @uclass_plat: The uclass's configuration data for this device
* @node: Reference to device tree node for this device
* @driver_data: Driver data word for the entry that matched this device with
* its driver
struct udevice {
const struct driver *driver;
const char *name;
- void *platdata;
- void *parent_platdata;
- void *uclass_platdata;
+ void *plat;
+ void *parent_plat;
+ void *uclass_plat;
ofnode node;
ulong driver_data;
struct udevice *parent;
return ofnode_to_offset(dev->node);
}
-static inline void dev_set_of_offset(struct udevice *dev, int of_offset)
-{
- dev->node = offset_to_ofnode(of_offset);
-}
-
static inline bool dev_has_of_node(struct udevice *dev)
{
return ofnode_valid(dev->node);
*
* This holds methods for setting up a new device, and also removing it.
* The device needs information to set itself up - this is provided either
- * by platdata or a device tree node (which we find by looking up
+ * by plat or a device tree node (which we find by looking up
* matching compatible strings with of_match).
*
* Drivers all belong to a uclass, representing a class of devices of the
* @probe: Called to probe a device, i.e. activate it
* @remove: Called to remove a device, i.e. de-activate it
* @unbind: Called to unbind a device from its driver
- * @ofdata_to_platdata: Called before probe to decode device tree data
+ * @of_to_plat: Called before probe to decode device tree data
* @child_post_bind: Called after a new child has been bound
* @child_pre_probe: Called before a child device is probed. The device has
* memory allocated but it has not yet been probed.
* @child_post_remove: Called after a child device is removed. The device
* has memory allocated but its device_remove() method has been called.
- * @priv_auto_alloc_size: If non-zero this is the size of the private data
+ * @priv_auto: If non-zero this is the size of the private data
* to be allocated in the device's ->priv pointer. If zero, then the driver
* is responsible for allocating any data required.
- * @platdata_auto_alloc_size: If non-zero this is the size of the
- * platform data to be allocated in the device's ->platdata pointer.
+ * @plat_auto: If non-zero this is the size of the
+ * platform data to be allocated in the device's ->plat pointer.
* This is typically only useful for device-tree-aware drivers (those with
- * an of_match), since drivers which use platdata will have the data
+ * an of_match), since drivers which use plat will have the data
* provided in the U_BOOT_DEVICE() instantiation.
- * @per_child_auto_alloc_size: Each device can hold private data owned by
+ * @per_child_auto: Each device can hold private data owned by
* its parent. If required this will be automatically allocated if this
* value is non-zero.
- * @per_child_platdata_auto_alloc_size: A bus likes to store information about
+ * @per_child_plat_auto: A bus likes to store information about
* its children. If non-zero this is the size of this data, to be allocated
- * in the child's parent_platdata pointer.
+ * in the child's parent_plat pointer.
* @ops: Driver-specific operations. This is typically a list of function
* pointers defined by the driver, to implement driver functions required by
* the uclass.
int (*probe)(struct udevice *dev);
int (*remove)(struct udevice *dev);
int (*unbind)(struct udevice *dev);
- int (*ofdata_to_platdata)(struct udevice *dev);
+ int (*of_to_plat)(struct udevice *dev);
int (*child_post_bind)(struct udevice *dev);
int (*child_pre_probe)(struct udevice *dev);
int (*child_post_remove)(struct udevice *dev);
- int priv_auto_alloc_size;
- int platdata_auto_alloc_size;
- int per_child_auto_alloc_size;
- int per_child_platdata_auto_alloc_size;
+ int priv_auto;
+ int plat_auto;
+ int per_child_auto;
+ int per_child_plat_auto;
const void *ops; /* driver-specific operations */
uint32_t flags;
#if CONFIG_IS_ENABLED(ACPIGEN)
#define U_BOOT_DRIVER_ALIAS(__name, __alias)
/**
- * dev_get_platdata() - Get the platform data for a device
+ * dev_get_plat() - Get the platform data for a device
*
* This checks that dev is not NULL, but no other checks for now
*
* @dev Device to check
* @return platform data, or NULL if none
*/
-void *dev_get_platdata(const struct udevice *dev);
+void *dev_get_plat(const struct udevice *dev);
/**
- * dev_get_parent_platdata() - Get the parent platform data for a device
+ * dev_get_parent_plat() - Get the parent platform data for a device
*
* This checks that dev is not NULL, but no other checks for now
*
* @dev Device to check
* @return parent's platform data, or NULL if none
*/
-void *dev_get_parent_platdata(const struct udevice *dev);
+void *dev_get_parent_plat(const struct udevice *dev);
/**
- * dev_get_uclass_platdata() - Get the uclass platform data for a device
+ * dev_get_uclass_plat() - Get the uclass platform data for a device
*
* This checks that dev is not NULL, but no other checks for now
*
* @dev Device to check
* @return uclass's platform data, or NULL if none
*/
-void *dev_get_uclass_platdata(const struct udevice *dev);
+void *dev_get_uclass_plat(const struct udevice *dev);
/**
* dev_get_priv() - Get the private data for a device
struct udevice **devp);
/**
- * device_first_child_ofdata_err() - Find the first child and reads its platdata
+ * device_first_child_ofdata_err() - Find the first child and reads its plat
*
- * The ofdata_to_platdata() method is called on the child before it is returned,
+ * The of_to_plat() method is called on the child before it is returned,
* but the child is not probed.
*
* @parent: Parent to check
struct udevice **devp);
/*
- * device_next_child_ofdata_err() - Find the next child and read its platdata
+ * device_next_child_ofdata_err() - Find the next child and read its plat
*
- * The ofdata_to_platdata() method is called on the child before it is returned,
+ * The of_to_plat() method is called on the child before it is returned,
* but the child is not probed.
*
* @devp: On entry, points to the previous child; on exit returns the child that
list_for_each_entry(pos, &parent->child_head, sibling_node)
/**
- * device_foreach_child_ofdata_to_platdata() - iterate through children
+ * device_foreach_child_of_to_plat() - iterate through children
*
* This stops when it gets an error, with @pos set to the device that failed to
* read ofdata.
* This creates a for() loop which works through the available children of
* a device in order from start to end. Device ofdata is read by calling
- * device_ofdata_to_platdata() on each one. The devices are not probed.
+ * device_of_to_plat() on each one. The devices are not probed.
*
* @pos: struct udevice * for the current device
* @parent: parent device to scan
*/
-#define device_foreach_child_ofdata_to_platdata(pos, parent) \
+#define device_foreach_child_of_to_plat(pos, parent) \
for (int _ret = device_first_child_ofdata_err(parent, &dev); !_ret; \
_ret = device_next_child_ofdata_err(&dev))
* lists_driver_lookup_name() - Return u_boot_driver corresponding to name
*
* This function returns a pointer to a driver given its name. This is used
- * for binding a driver given its name and platdata.
+ * for binding a driver given its name and plat.
*
* @name: Name of driver to look up
* @return pointer to driver, or NULL if not found
return node;
}
+static inline ofnode ofnode_root(void)
+{
+ ofnode node;
+
+ if (of_live_active())
+ node.np = gd_of_root();
+ else
+ node.of_offset = 0;
+
+ return node;
+}
+
/**
* ofnode_read_u32() - Read a 32-bit integer from a property
*
*/
int ofnode_read_u32_array(ofnode node, const char *propname,
u32 *out_values, size_t sz);
+/**
+ * ofnode_is_enabled() - Checks whether a node is enabled.
+ * This looks for a 'status' property. If this exists, then returns true if
+ * the status is 'okay' and false otherwise. If there is no status property,
+ * it returns true on the assumption that anything mentioned should be enabled
+ * by default.
+ *
+ * @node: node to examine
+ * @return false (not enabled) or true (enabled)
+ */
+bool ofnode_is_enabled(ofnode node);
/**
* ofnode_read_bool() - read a boolean value from a property
*
* This returns an int to avoid a dependency on pci.h
*
- * @reg: reg value from dt-platdata.c array (first member). This is not a
+ * @reg: reg value from dt-plat.c array (first member). This is not a
* pointer type, since the caller may use fdt32_t or fdt64_t depending on
* the address sizes.
* @return device/function for that device (pci_dev_t format)
* available). U-Boot's driver model uses device tree for configuration.
*
* @name: Driver name
- * @platdata: Driver-specific platform data
- * @platdata_size: Size of platform data structure
+ * @plat: Driver-specific platform data
+ * @plat_size: Size of platform data structure
* @parent_idx: Index of the parent driver_info structure
*/
struct driver_info {
const char *name;
- const void *platdata;
+ const void *plat;
#if CONFIG_IS_ENABLED(OF_PLATDATA)
- unsigned short platdata_size;
+ unsigned short plat_size;
short parent_idx;
#endif
};
* available). U-Boot's driver model uses device tree for configuration.
*
* When of-platdata is in use, U_BOOT_DEVICE() cannot be used outside of the
- * dt-platdata.c file created by dtoc
+ * dt-plat.c file created by dtoc
*/
#if CONFIG_IS_ENABLED(OF_PLATDATA) && !defined(DT_PLATDATA_C)
#define U_BOOT_DEVICE(__name) _Static_assert(false, \
#ifndef __fsl_espi_h
#define __fsl_espi_h
-struct fsl_espi_platdata {
+struct fsl_espi_plat {
uint flags;
uint speed_hz;
uint num_chipselect;
#define _LPC32XX_HSUART_PLAT_H
/**
- * struct lpc32xx_hsuart_platdata - NXP LPC32xx HSUART platform data
+ * struct lpc32xx_hsuart_plat - NXP LPC32xx HSUART platform data
*
* @base: Base register address
*/
-struct lpc32xx_hsuart_platdata {
+struct lpc32xx_hsuart_plat {
unsigned long base;
};
#include <mmc.h>
/*
- * struct pxa_mmc_platdata - information about a PXA MMC controller
+ * struct pxa_mmc_plat - information about a PXA MMC controller
*
* @base: MMC controller base register address
*/
*
* @base: Register base address
*/
-struct bcm283x_mu_serial_platdata {
+struct bcm283x_mu_serial_plat {
unsigned long base;
unsigned int clock;
bool skip_init;
#define __serial_coldfire_h
/*
- * struct coldfire_serial_platdata - information about a coldfire port
+ * struct coldfire_serial_plat - information about a coldfire port
*
* @base: Uart port base register address
* @port: Uart port index, for cpu with pinmux for uart / gpio
* baudrtatre: Uart port baudrate
*/
-struct coldfire_serial_platdata {
+struct coldfire_serial_plat {
unsigned long base;
int port;
int baudrate;
#define __serial_mxc_h
/* Information about a serial port */
-struct mxc_serial_platdata {
+struct mxc_serial_plat {
struct mxc_uart *reg; /* address of registers in physical memory */
bool use_dte;
};
* @skip_init: Don't attempt to change port configuration (also means @clock
* is ignored)
*/
-struct pl01x_serial_platdata {
+struct pl01x_serial_plat {
unsigned long base;
enum pl01x_type type;
unsigned int clock;
#endif
/*
- * struct pxa_serial_platdata - information about a PXA port
+ * struct pxa_serial_plat - information about a PXA port
*
* @base: Uart port base register address
* @port: Uart port index, for cpu with pinmux for uart / gpio
* baudrtatre: Uart port baudrate
*/
-struct pxa_serial_platdata {
+struct pxa_serial_plat {
struct pxa_uart_regs *base;
int port;
int baudrate;
* @clk_mode: Clock mode, set internal (INT) or external (EXT)
* @type: Type of SCIF
*/
-struct sh_serial_platdata {
+struct sh_serial_plat {
unsigned long base;
unsigned int clk;
enum sh_clk_mode clk_mode;
#define MAX_CTAR_FIELDS 8
/*
- * struct coldfire_spi_platdata - information about a coldfire spi module
+ * struct coldfire_spi_plat - information about a coldfire spi module
*
* @regs_addr: base address for module registers
* @speed_hz: default SCK frequency
* @mode: default SPI mode
* @num_cs: number of DSPI chipselect signals
*/
-struct coldfire_spi_platdata {
+struct coldfire_spi_plat {
fdt_addr_t regs_addr;
uint speed_hz;
uint mode;
#ifndef __spi_davinci_h
#define __spi_davinci_h
-struct davinci_spi_platdata {
+struct davinci_spi_plat {
struct davinci_spi_regs *regs;
u8 num_cs; /* total no. of CS available */
};
*
* Structure for use with U_BOOT_DEVICE for pl022 SPI devices or to use
- * in ofdata_to_platdata.
+ * in of_to_plat.
*/
#ifndef __spi_pl022_h
void dm_fixup_for_gd_move(struct global_data *new_gd);
/**
- * dm_scan_platdata() - Scan all platform data and bind drivers
+ * dm_scan_plat() - Scan all platform data and bind drivers
*
- * This scans all available platdata and creates drivers for each
+ * This scans all available plat and creates drivers for each
*
* @pre_reloc_only: If true, bind only drivers with the DM_FLAG_PRE_RELOC
* flag. If false bind all drivers.
* @return 0 if OK, -ve on error
*/
-int dm_scan_platdata(bool pre_reloc_only);
+int dm_scan_plat(bool pre_reloc_only);
/**
* dm_scan_fdt() - Scan the device tree and bind drivers
* This scans the device tree and creates a driver for each node. Only
* the top-level subnodes are examined.
*
- * @blob: Pointer to device tree blob
* @pre_reloc_only: If true, bind only nodes with special devicetree properties,
* or drivers with the DM_FLAG_PRE_RELOC flag. If false bind all drivers.
* @return 0 if OK, -ve on error
*/
-int dm_scan_fdt(const void *blob, bool pre_reloc_only);
+int dm_scan_fdt(bool pre_reloc_only);
/**
- * dm_extended_scan_fdt() - Scan the device tree and bind drivers
+ * dm_extended_scan() - Scan the device tree and bind drivers
*
* This calls dm_scna_dft() which scans the device tree and creates a driver
* for each node. the top-level subnodes are examined and also all sub-nodes
* of "clocks" node.
*
- * @blob: Pointer to device tree blob
* @pre_reloc_only: If true, bind only nodes with special devicetree properties,
* or drivers with the DM_FLAG_PRE_RELOC flag. If false bind all drivers.
* @return 0 if OK, -ve on error
*/
-int dm_extended_scan_fdt(const void *blob, bool pre_reloc_only);
+int dm_extended_scan(bool pre_reloc_only);
/**
* dm_scan_other() - Scan for other devices
* @child_post_probe: Called after a child in this uclass is probed
* @init: Called to set up the uclass
* @destroy: Called to destroy the uclass
- * @priv_auto_alloc_size: If non-zero this is the size of the private data
+ * @priv_auto: If non-zero this is the size of the private data
* to be allocated in the uclass's ->priv pointer. If zero, then the uclass
* driver is responsible for allocating any data required.
- * @per_device_auto_alloc_size: Each device can hold private data owned
+ * @per_device_auto: Each device can hold private data owned
* by the uclass. If required this will be automatically allocated if this
* value is non-zero.
- * @per_device_platdata_auto_alloc_size: Each device can hold platform data
- * owned by the uclass as 'dev->uclass_platdata'. If the value is non-zero,
+ * @per_device_plat_auto: Each device can hold platform data
+ * owned by the uclass as 'dev->uclass_plat'. If the value is non-zero,
* then this will be automatically allocated.
- * @per_child_auto_alloc_size: Each child device (of a parent in this
+ * @per_child_auto: Each child device (of a parent in this
* uclass) can hold parent data for the device/uclass. This value is only
* used as a fallback if this member is 0 in the driver.
- * @per_child_platdata_auto_alloc_size: A bus likes to store information about
+ * @per_child_plat_auto: A bus likes to store information about
* its children. If non-zero this is the size of this data, to be allocated
- * in the child device's parent_platdata pointer. This value is only used as
+ * in the child device's parent_plat pointer. This value is only used as
* a fallback if this member is 0 in the driver.
* @ops: Uclass operations, providing the consistent interface to devices
* within the uclass.
int (*child_post_probe)(struct udevice *dev);
int (*init)(struct uclass *class);
int (*destroy)(struct uclass *class);
- int priv_auto_alloc_size;
- int per_device_auto_alloc_size;
- int per_device_platdata_auto_alloc_size;
- int per_child_auto_alloc_size;
- int per_child_platdata_auto_alloc_size;
+ int priv_auto;
+ int per_device_auto;
+ int per_device_plat_auto;
+ int per_child_auto;
+ int per_child_plat_auto;
const void *ops;
uint32_t flags;
};
* ...
*
* Inside U_BOOT_DRIVER():
- * .platdata_auto_alloc_size = sizeof(struct rockchip_mmc_plat),
+ * .plat_auto = sizeof(struct rockchip_mmc_plat),
*
* To access platform data:
- * struct rockchip_mmc_plat *plat = dev_get_platdata(dev);
+ * struct rockchip_mmc_plat *plat = dev_get_plat(dev);
*
* See rockchip_dw_mmc.c for an example.
*
* @mtdpart: MTD partition for ubi partition.
* @ubivol: UBI volume-name for ubifsmount.
*/
-struct device_platdata {
+struct device_plat {
struct phandle_part phandlepart;
char *mtdpart;
char *ubivol;
* An I2C chip is a device on the I2C bus. It sits at a particular address
* and normally supports 7-bit or 10-bit addressing.
*
- * To obtain this structure, use dev_get_parent_platdata(dev) where dev is
+ * To obtain this structure, use dev_get_parent_plat(dev) where dev is
* the chip to examine.
*
* @chip_addr: Chip address on bus
struct udevice **devp);
/**
- * i2c_chip_ofdata_to_platdata() - Decode standard I2C platform data
+ * i2c_chip_of_to_plat() - Decode standard I2C platform data
*
* This decodes the chip address from a device tree node and puts it into
* its dm_i2c_chip structure. This should be called in your driver's
- * ofdata_to_platdata() method.
+ * of_to_plat() method.
*
* @blob: Device tree blob
* @node: Node offset to read from
* @spi: Place to put the decoded information
*/
-int i2c_chip_ofdata_to_platdata(struct udevice *dev, struct dm_i2c_chip *chip);
+int i2c_chip_of_to_plat(struct udevice *dev, struct dm_i2c_chip *chip);
/**
* i2c_dump_msgs() - Dump a list of I2C messages
extern struct acpi_ops i2c_acpi_ops;
/**
- * acpi_i2c_ofdata_to_platdata() - Read properties intended for ACPI
+ * acpi_i2c_of_to_plat() - Read properties intended for ACPI
*
* This reads the generic I2C properties from the device tree, so that these
* can be used to create ACPI information for the device.
* @dev: I2C device to process
* @return 0 if OK, -EINVAL if acpi,hid is not present
*/
-int acpi_i2c_ofdata_to_platdata(struct udevice *dev);
+int acpi_i2c_of_to_plat(struct udevice *dev);
#ifndef CONFIG_DM_I2C
unsigned long fixed_rate;
};
-#define to_clk_fixed_rate(dev) ((struct clk_fixed_rate *)dev_get_platdata(dev))
+#define to_clk_fixed_rate(dev) ((struct clk_fixed_rate *)dev_get_plat(dev))
struct clk_composite {
struct clk clk;
* @enetaddr: The Ethernet MAC address that is loaded from EEPROM or env
* @phy_interface: PHY interface to use - see PHY_INTERFACE_MODE_...
* @max_speed: Maximum speed of Ethernet connection supported by MAC
- * @priv_pdata: device specific platdata
+ * @priv_pdata: device specific plat
*/
struct eth_pdata {
phys_addr_t iobase;
};
/**
- * struct ns16550_platdata - information about a NS16550 port
+ * struct ns16550_plat - information about a NS16550 port
*
* @base: Base register address
* @reg_width: IO accesses size of registers (in bytes, 1 or 4)
* @flags: A few flags (enum ns16550_flags)
* @bdf: PCI slot/function (pci_dev_t)
*/
-struct ns16550_platdata {
+struct ns16550_plat {
unsigned long base;
int reg_width;
int reg_shift;
UART_REG(ssr); /* 11*/
#endif
#ifdef CONFIG_DM_SERIAL
- struct ns16550_platdata *plat;
+ struct ns16550_plat *plat;
#endif
};
int ns16550_calc_divisor(NS16550_t port, int clock, int baudrate);
/**
- * ns16550_serial_ofdata_to_platdata() - convert DT to platform data
+ * ns16550_serial_of_to_plat() - convert DT to platform data
*
* Decode a device tree node for an ns16550 device. This includes the
* register base address and register shift properties. The caller must set
* @dev: dev to decode platform data for
* @return: 0 if OK, -EINVAL on error
*/
-int ns16550_serial_ofdata_to_platdata(struct udevice *dev);
+int ns16550_serial_of_to_plat(struct udevice *dev);
/**
* ns16550_serial_probe() - probe a serial port
*/
void os_relaunch(char *argv[]);
+/**
+ * os_setup_signal_handlers() - setup signal handlers
+ *
+ * Install signal handlers for SIGBUS and SIGSEGV.
+ *
+ * Return: 0 for success
+ */
+int os_setup_signal_handlers(void);
+
+/**
+ * os_signal_action() - handle a signal
+ *
+ * @sig: signal
+ * @pc: program counter
+ */
+void os_signal_action(int sig, unsigned long pc);
+
#endif
#define PCH_P2SB_HBDF 0x70
/**
- * struct p2sb_child_platdata - Information about each child of a p2sb device
+ * struct p2sb_child_plat - Information about each child of a p2sb device
*
* @pid: Port ID for this child
*/
-struct p2sb_child_platdata {
+struct p2sb_child_plat {
uint pid;
};
#ifdef CONFIG_DM_PCI
/**
- * struct pci_child_platdata - information stored about each PCI device
+ * struct pci_child_plat - information stored about each PCI device
*
* Every device on a PCI bus has this per-child data.
*
- * It can be accessed using dev_get_parent_platdata(dev) if dev->parent is a
+ * It can be accessed using dev_get_parent_plat(dev) if dev->parent is a
* PCI bus (i.e. UCLASS_PCI)
*
* @devfn: Encoded device and function index - see PCI_DEVFN()
* @pfdev: Handle to Physical Function device
* @virtid: Virtual Function Index
*/
-struct pci_child_platdata {
+struct pci_child_plat {
int devfn;
unsigned short vendor;
unsigned short device;
*/
int pmc_global_reset_set_enable(struct udevice *dev, bool enable);
-int pmc_ofdata_to_uc_platdata(struct udevice *dev);
+int pmc_ofdata_to_uc_plat(struct udevice *dev);
int pmc_disable_tco_base(ulong tco_base);
* 'UCLASS_REGULATOR' and the regulator driver API.
*
* The regulator uclass - is based on uclass platform data which is allocated,
- * automatically for each regulator device on bind and 'dev->uclass_platdata'
- * points to it. The data type is: 'struct dm_regulator_uclass_platdata'.
+ * automatically for each regulator device on bind and 'dev->uclass_plat'
+ * points to it. The data type is: 'struct dm_regulator_uclass_plat'.
* The uclass file: 'drivers/power/regulator/regulator-uclass.c'
*
* The regulator device - is based on driver's model 'struct udevice'.
* The API can use regulator name in two meanings:
* - devname - the regulator device's name: 'dev->name'
- * - platname - the device's platdata's name. So in the code it looks like:
- * 'uc_pdata = dev->uclass_platdata'; 'name = uc_pdata->name'.
+ * - platname - the device's plat's name. So in the code it looks like:
+ * 'uc_pdata = dev->uclass_plat'; 'name = uc_pdata->name'.
*
* The regulator device driver - provide an implementation of uclass operations
* pointed by 'dev->driver->ops' as a struct of type 'struct dm_regulator_ops'.
};
/**
- * struct dm_regulator_uclass_platdata - pointed by dev->uclass_platdata, and
+ * struct dm_regulator_uclass_plat - pointed by dev->uclass_plat, and
* allocated on each regulator bind. This structure holds an information
* about each regulator's constraints and supported operation modes.
* There is no "step" voltage value - so driver should take care of this.
* The constraints: type, mode, mode_count, can be set by device driver, e.g.
* by the driver '.probe' method.
*/
-struct dm_regulator_uclass_platdata {
+struct dm_regulator_uclass_plat {
enum regulator_type type;
struct dm_regulator_mode *mode;
int mode_count;
* regulator_autoset: setup the voltage/current on a regulator
*
* The setup depends on constraints found in device's uclass's platform data
- * (struct dm_regulator_uclass_platdata):
+ * (struct dm_regulator_uclass_plat):
*
* - Enable - will set - if any of: 'always_on' or 'boot_on' is set to true,
* or if both are unset, then the function returns
*
* The function returns on the first-encountered error.
*
- * @platname - expected string for dm_regulator_uclass_platdata .name field
+ * @platname - expected string for dm_regulator_uclass_plat .name field
* @devp - returned pointer to the regulator device - if non-NULL passed
* @return: 0 on success or negative value of errno.
*/
/**
* regulator_autoset_by_name: setup the regulator given by its uclass's
* platform data name field. The setup depends on constraints found in device's
- * uclass's platform data (struct dm_regulator_uclass_platdata):
+ * uclass's platform data (struct dm_regulator_uclass_plat):
* - Enable - will set - if any of: 'always_on' or 'boot_on' is set to true,
* or if both are unset, then the function returns
* - Voltage value - will set - if '.min_uV' and '.max_uV' values are equal
*
* The function returns on first encountered error.
*
- * @platname - expected string for dm_regulator_uclass_platdata .name field
+ * @platname - expected string for dm_regulator_uclass_plat .name field
* @devp - returned pointer to the regulator device - if non-NULL passed
* @return: 0 on success or negative value of errno.
*
* regulator_autoset_by_name() for each name from the list.
*
* @list_platname - an array of expected strings for .name field of each
- * regulator's uclass platdata
+ * regulator's uclass plat
* @list_devp - an array of returned pointers to the successfully setup
* regulator devices if non-NULL passed
* @verbose - (true/false) print each regulator setup info, or be quiet
/**
* regulator_get_by_platname: returns the pointer to the pmic regulator device.
- * Search by name, found in regulator uclass platdata.
+ * Search by name, found in regulator uclass plat.
*
- * @platname - expected string for uc_pdata->name of regulator uclass platdata
+ * @platname - expected string for uc_pdata->name of regulator uclass plat
* @devp - returns pointer to the regulator device or NULL on error
* @return 0 on success or negative value of errno.
*
int regmap_init_mem(ofnode node, struct regmap **mapp);
/**
- * regmap_init_mem_platdata() - Set up a new memory register map for
+ * regmap_init_mem_plat() - Set up a new memory register map for
* of-platdata
*
* @dev: Device that uses this map
* Use regmap_uninit() to free it.
*
*/
-int regmap_init_mem_platdata(struct udevice *dev, fdt_val_t *reg, int count,
- struct regmap **mapp);
+int regmap_init_mem_plat(struct udevice *dev, fdt_val_t *reg, int count,
+ struct regmap **mapp);
int regmap_init_mem_index(ofnode node, struct regmap **mapp, int index);
* @mem_type: one of 'enum rproc_mem_type'
* @driver_plat_data: driver specific platform data that may be needed.
*
- * This can be accessed with dev_get_uclass_platdata() for any UCLASS_REMOTEPROC
+ * This can be accessed with dev_get_uclass_plat() for any UCLASS_REMOTEPROC
* device.
*
*/
#define SCSI_WRITE_SAME 0x41 /* Write Same (O) */
/**
- * struct scsi_platdata - stores information about SCSI controller
+ * struct scsi_plat - stores information about SCSI controller
*
* @base: Controller base address
* @max_lun: Maximum number of logical units
* @max_id: Maximum number of target ids
* @max_bytes_per_req: Maximum number of bytes per read/write request
*/
-struct scsi_platdata {
+struct scsi_plat {
unsigned long base;
unsigned long max_lun;
unsigned long max_id;
* ...
*
* Inside U_BOOT_DRIVER():
- * .platdata_auto_alloc_size = sizeof(struct msm_sdhc_plat),
+ * .plat_auto = sizeof(struct msm_sdhc_plat),
*
* To access platform data:
- * struct msm_sdhc_plat *plat = dev_get_platdata(dev);
+ * struct msm_sdhc_plat *plat = dev_get_plat(dev);
*
* See msm_sdhci.c for an example.
*
};
/**
- * struct dm_spi_platdata - platform data for all SPI slaves
+ * struct dm_spi_plat - platform data for all SPI slaves
*
* This describes a SPI slave, a child device of the SPI bus. To obtain this
- * struct from a spi_slave, use dev_get_parent_platdata(dev) or
- * dev_get_parent_platdata(slave->dev).
+ * struct from a spi_slave, use dev_get_parent_plat(dev) or
+ * dev_get_parent_plat(slave->dev).
*
* This data is immuatable. Each time the device is probed, @max_hz and @mode
* will be copied to struct spi_slave.
* @max_hz: Maximum bus speed that this slave can tolerate
* @mode: SPI mode to use for this device (see SPI mode flags)
*/
-struct dm_spi_slave_platdata {
+struct dm_spi_slave_plat {
unsigned int cs;
uint max_hz;
uint mode;
*
* For driver model this is the per-child data used by the SPI bus. It can
* be accessed using dev_get_parent_priv() on the slave device. The SPI uclass
- * sets uip per_child_auto_alloc_size to sizeof(struct spi_slave), and the
+ * sets up per_child_auto to sizeof(struct spi_slave), and the
* driver should not override it. Two platform data fields (max_hz and mode)
* are copied into this structure to provide an initial value. This allows
* them to be changed, since we should never change platform data in drivers.
* is automatically bound on this chip select with requested speed and mode.
*
* Ths new slave device is probed ready for use with the speed and mode
- * from platdata when available or the requested values.
+ * from plat when available or the requested values.
*
* @busnum: SPI bus number
* @cs: Chip select to look for
- * @speed: SPI speed to use for this slave when not available in platdata
- * @mode: SPI mode to use for this slave when not available in platdata
+ * @speed: SPI speed to use for this slave when not available in plat
+ * @mode: SPI mode to use for this slave when not available in plat
* @drv_name: Name of driver to attach to this chip select
* @dev_name: Name of the new device thus created
* @busp: Returns bus device
int spi_find_chip_select(struct udevice *bus, int cs, struct udevice **devp);
/**
- * spi_slave_ofdata_to_platdata() - decode standard SPI platform data
+ * spi_slave_of_to_plat() - decode standard SPI platform data
*
* This decodes the speed and mode for a slave from a device tree node
*
* @node: Node offset to read from
* @plat: Place to put the decoded information
*/
-int spi_slave_ofdata_to_platdata(struct udevice *dev,
- struct dm_spi_slave_platdata *plat);
+int spi_slave_of_to_plat(struct udevice *dev, struct dm_spi_slave_plat *plat);
/**
* spi_cs_info() - Check information on a chip select
*
* Update: 64-bit is now supported and we have an education crisis.
*/
-struct syscon_base_platdata {
+struct syscon_base_plat {
fdt_val_t reg[2];
};
#endif
#if CONFIG_IS_ENABLED(DM_USB)
/**
- * struct usb_platdata - Platform data about a USB controller
+ * struct usb_plat - Platform data about a USB controller
*
- * Given a USB controller (UCLASS_USB) dev this is dev_get_platdata(dev)
+ * Given a USB controller (UCLASS_USB) dev this is dev_get_plat(dev)
*/
-struct usb_platdata {
+struct usb_plat {
enum usb_init_type init_type;
};
/**
- * struct usb_dev_platdata - Platform data about a USB device
+ * struct usb_dev_plat - Platform data about a USB device
*
- * Given a USB device dev this structure is dev_get_parent_platdata(dev).
+ * Given a USB device dev this structure is dev_get_parent_plat(dev).
* This is used by sandbox to provide emulation data also.
*
* @id: ID used to match this device
* @strings: List of descriptor strings (for sandbox emulation purposes)
* @desc_list: List of descriptors (for sandbox emulation purposes)
*/
-struct usb_dev_platdata {
+struct usb_dev_plat {
struct usb_device_id id;
int devnum;
/*
};
/**
- * struct usb_emul_platdata - platform data about the USB emulator
+ * struct usb_emul_plat - platform data about the USB emulator
*
* Given a USB emulator (UCLASS_USB_EMUL) 'dev', this is
- * dev_get_uclass_platdata(dev).
+ * dev_get_uclass_plat(dev).
*
* @port1: USB emulator device port number on the parent hub
*/
-struct usb_emul_platdata {
+struct usb_emul_plat {
int port1; /* Port number (numbered from 1) */
};
extern struct vbe_mode_info mode_info;
struct video_priv;
-struct video_uc_platdata;
+struct video_uc_plat;
int vbe_setup_video_priv(struct vesa_mode_info *vesa,
struct video_priv *uc_priv,
- struct video_uc_platdata *plat);
+ struct video_uc_plat *plat);
int vbe_setup_video(struct udevice *dev, int (*int15_handler)(void));
#endif
struct udevice;
/**
- * struct video_uc_platdata - uclass platform data for a video device
+ * struct video_uc_plat - uclass platform data for a video device
*
* This holds information that the uclass needs to know about each device. It
- * is accessed using dev_get_uclass_platdata(dev). See 'Theory of operation' at
+ * is accessed using dev_get_uclass_plat(dev). See 'Theory of operation' at
* the top of video-uclass.c for details on how this information is set.
*
* @align: Frame-buffer alignment, indicating the memory boundary the frame
* @copy_base: Base address of a hardware copy of the frame buffer. See
* CONFIG_VIDEO_COPY.
*/
-struct video_uc_platdata {
+struct video_uc_plat {
uint align;
uint size;
ulong base;
* @fb: Frame buffer
* @fb_size: Frame buffer size
* @copy_fb: Copy of the frame buffer to keep up to date; see struct
- * video_uc_platdata
+ * video_uc_plat
* @line_length: Length of each frame buffer line, in bytes. This can be
* set by the driver, but if not, the uclass will set it after
* probing
*
* Note: This function is for internal use.
*
- * This uses the uclass platdata's @size and @align members to figure out
+ * This uses the uclass plat's @size and @align members to figure out
* a size and position for each frame buffer as part of the pre-relocation
* process of determining the post-relocation memory layout.
*
static int acpi_device_set_i2c(const struct udevice *dev, struct acpi_i2c *i2c,
const char *scope)
{
- struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
+ struct dm_i2c_chip *chip = dev_get_parent_plat(dev);
struct udevice *bus = dev_get_parent(dev);
memset(i2c, '\0', sizeof(*i2c));
static int acpi_device_set_spi(const struct udevice *dev, struct acpi_spi *spi,
const char *scope)
{
- struct dm_spi_slave_platdata *plat;
+ struct dm_spi_slave_plat *plat;
struct spi_slave *slave = dev_get_parent_priv(dev);
- plat = dev_get_parent_platdata(slave->dev);
+ plat = dev_get_parent_plat(slave->dev);
memset(spi, '\0', sizeof(*spi));
spi->device_select = plat->cs;
spi->device_select_polarity = SPI_POLARITY_LOW;
* handle handle of the controller on which this driver is installed
* io block io protocol proxied by this driver
*/
-struct efi_blk_platdata {
+struct efi_blk_plat {
efi_handle_t handle;
struct efi_block_io *io;
};
static ulong efi_bl_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
void *buffer)
{
- struct efi_blk_platdata *platdata = dev_get_platdata(dev);
- struct efi_block_io *io = platdata->io;
+ struct efi_blk_plat *plat = dev_get_plat(dev);
+ struct efi_block_io *io = plat->io;
efi_status_t ret;
EFI_PRINT("%s: read '%s', from block " LBAFU ", " LBAFU " blocks\n",
static ulong efi_bl_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
const void *buffer)
{
- struct efi_blk_platdata *platdata = dev_get_platdata(dev);
- struct efi_block_io *io = platdata->io;
+ struct efi_blk_plat *plat = dev_get_plat(dev);
+ struct efi_block_io *io = plat->io;
efi_status_t ret;
EFI_PRINT("%s: write '%s', from block " LBAFU ", " LBAFU " blocks\n",
struct blk_desc *desc;
const char *if_typename;
- desc = dev_get_uclass_platdata(dev);
+ desc = dev_get_uclass_plat(dev);
if_typename = blk_get_if_type_name(desc->if_type);
return efi_disk_create_partitions(handle, desc, if_typename,
struct efi_object *obj = efi_search_obj(handle);
struct efi_block_io *io = interface;
int disks;
- struct efi_blk_platdata *platdata;
+ struct efi_blk_plat *plat;
EFI_PRINT("%s: handle %p, interface %p\n", __func__, handle, io);
/* Set the DM_FLAG_NAME_ALLOCED flag to avoid a memory leak */
device_set_name_alloced(bdev);
- platdata = dev_get_platdata(bdev);
- platdata->handle = handle;
- platdata->io = interface;
+ plat = dev_get_plat(bdev);
+ plat->handle = handle;
+ plat->io = interface;
ret = device_probe(bdev);
if (ret)
.name = "efi_blk",
.id = UCLASS_BLK,
.ops = &efi_blk_ops,
- .platdata_auto_alloc_size = sizeof(struct efi_blk_platdata),
+ .plat_auto = sizeof(struct efi_blk_plat),
};
/* EFI driver operators */
case UCLASS_ETH: {
struct efi_device_path_mac_addr *dp =
dp_fill(buf, dev->parent);
- struct eth_pdata *pdata = dev->platdata;
+ struct eth_pdata *pdata = dev->plat;
dp->dp.type = DEVICE_PATH_TYPE_MESSAGING_DEVICE;
dp->dp.sub_type = DEVICE_PATH_SUB_TYPE_MSG_MAC_ADDR;
case UCLASS_ROOT: {
/* stop traversing parents at this point: */
struct efi_device_path_vendor *dp;
- struct blk_desc *desc = dev_get_uclass_platdata(dev);
+ struct blk_desc *desc = dev_get_uclass_plat(dev);
dp_fill(buf, dev->parent);
dp = buf;
#ifdef CONFIG_VIRTIO_BLK
case UCLASS_VIRTIO: {
struct efi_device_path_vendor *dp;
- struct blk_desc *desc = dev_get_uclass_platdata(dev);
+ struct blk_desc *desc = dev_get_uclass_plat(dev);
dp_fill(buf, dev->parent);
dp = buf;
case UCLASS_IDE: {
struct efi_device_path_atapi *dp =
dp_fill(buf, dev->parent);
- struct blk_desc *desc = dev_get_uclass_platdata(dev);
+ struct blk_desc *desc = dev_get_uclass_plat(dev);
dp->dp.type = DEVICE_PATH_TYPE_MESSAGING_DEVICE;
dp->dp.sub_type = DEVICE_PATH_SUB_TYPE_MSG_ATAPI;
case UCLASS_SCSI: {
struct efi_device_path_scsi *dp =
dp_fill(buf, dev->parent);
- struct blk_desc *desc = dev_get_uclass_platdata(dev);
+ struct blk_desc *desc = dev_get_uclass_plat(dev);
dp->dp.type = DEVICE_PATH_TYPE_MESSAGING_DEVICE;
dp->dp.sub_type = DEVICE_PATH_SUB_TYPE_MSG_SCSI;
case UCLASS_MMC: {
struct efi_device_path_sd_mmc_path *sddp =
dp_fill(buf, dev->parent);
- struct blk_desc *desc = dev_get_uclass_platdata(dev);
+ struct blk_desc *desc = dev_get_uclass_plat(dev);
sddp->dp.type = DEVICE_PATH_TYPE_MESSAGING_DEVICE;
sddp->dp.sub_type = is_sd(desc) ?
case UCLASS_AHCI: {
struct efi_device_path_sata *dp =
dp_fill(buf, dev->parent);
- struct blk_desc *desc = dev_get_uclass_platdata(dev);
+ struct blk_desc *desc = dev_get_uclass_plat(dev);
dp->dp.type = DEVICE_PATH_TYPE_MESSAGING_DEVICE;
dp->dp.sub_type = DEVICE_PATH_SUB_TYPE_MSG_SATA;
for (uclass_first_device_check(UCLASS_BLK, &dev); dev;
uclass_next_device_check(&dev)) {
- struct blk_desc *desc = dev_get_uclass_platdata(dev);
+ struct blk_desc *desc = dev_get_uclass_plat(dev);
const char *if_typename = blk_get_if_type_name(desc->if_type);
/* Add block device for the full device */
asm volatile (".word 0xe7f7defb\n");
#elif defined(CONFIG_RISCV)
asm volatile (".word 0xffffffff\n");
+#elif defined(CONFIG_SANDBOX)
+ asm volatile (".word 0xffffffff\n");
#elif defined(CONFIG_X86)
asm volatile (".word 0xffff\n");
#endif
uclass_find_first_device(UCLASS_CPU, &cpu);
if (cpu) {
- struct cpu_platdata *plat = dev_get_parent_platdata(cpu);
+ struct cpu_plat *plat = dev_get_parent_plat(cpu);
if (plat->family)
processor_family = plat->family;
struct eth_pdata *pdata;
if (eth_get_dev()) {
- pdata = eth_get_dev()->platdata;
+ pdata = eth_get_dev()->plat;
return pdata->enetaddr;
}
/* seq is valid since the device is active */
if (eth_get_ops(dev)->write_hwaddr && !eth_mac_skip(dev->seq)) {
- pdata = dev->platdata;
+ pdata = dev->plat;
if (!is_valid_ethaddr(pdata->enetaddr)) {
printf("\nError: %s address %pM illegal value\n",
dev->name, pdata->enetaddr);
retval = uclass_find_device_by_seq(UCLASS_ETH, index, false, &dev);
if (!retval) {
- struct eth_pdata *pdata = dev->platdata;
+ struct eth_pdata *pdata = dev->plat;
switch (op) {
case env_op_create:
case env_op_overwrite:
static int eth_post_probe(struct udevice *dev)
{
struct eth_device_priv *priv = dev->uclass_priv;
- struct eth_pdata *pdata = dev->platdata;
+ struct eth_pdata *pdata = dev->plat;
unsigned char env_enetaddr[ARP_HLEN];
char *source = "DT";
static int eth_pre_remove(struct udevice *dev)
{
- struct eth_pdata *pdata = dev->platdata;
+ struct eth_pdata *pdata = dev->plat;
eth_get_ops(dev)->stop(dev);
.pre_unbind = eth_pre_unbind,
.post_probe = eth_post_probe,
.pre_remove = eth_pre_remove,
- .priv_auto_alloc_size = sizeof(struct eth_uclass_priv),
- .per_device_auto_alloc_size = sizeof(struct eth_device_priv),
+ .priv_auto = sizeof(struct eth_uclass_priv),
+ .per_device_auto = sizeof(struct eth_device_priv),
.flags = DM_UC_FLAG_SEQ_ALIAS,
};
struct udevice *mux = ch->parent;
struct mdio_mux_perdev_priv *priv = dev_get_uclass_priv(mux);
struct mdio_mux_ops *ops = mdio_mux_get_ops(mux);
- struct mdio_mux_ch_data *ch_data = dev_get_parent_platdata(ch);
+ struct mdio_mux_ch_data *ch_data = dev_get_parent_plat(ch);
int err = 0;
if (sel) {
/* Picks up the mux selection value for each child */
static int dm_mdio_mux_child_post_bind(struct udevice *ch)
{
- struct mdio_mux_ch_data *ch_data = dev_get_parent_platdata(ch);
+ struct mdio_mux_ch_data *ch_data = dev_get_parent_plat(ch);
ch_data->sel = dev_read_u32_default(ch, "reg", MDIO_MUX_SELECT_NONE);
.child_post_bind = dm_mdio_mux_child_post_bind,
.post_bind = dm_mdio_mux_post_bind,
.post_probe = dm_mdio_mux_post_probe,
- .per_device_auto_alloc_size = sizeof(struct mdio_mux_perdev_priv),
- .per_child_platdata_auto_alloc_size = sizeof(struct mdio_mux_ch_data),
+ .per_device_auto = sizeof(struct mdio_mux_perdev_priv),
+ .per_child_plat_auto = sizeof(struct mdio_mux_ch_data),
};
.post_bind = dm_mdio_post_bind,
.post_probe = dm_mdio_post_probe,
.pre_remove = dm_mdio_pre_remove,
- .per_device_auto_alloc_size = sizeof(struct mdio_perdev_priv),
+ .per_device_auto = sizeof(struct mdio_perdev_priv),
};
return $comment;
}
+# Args:
+# line: Patch line to check
+# auto: Auto variable name, e.g. "per_child_auto"
+# suffix: Suffix to expect on member, e.g. "_priv"
+# warning: Warning name, e.g. "PRIV_AUTO"
+sub u_boot_struct_name {
+ my ($line, $auto, $suffix, $warning) = @_;
+
+ # Use _priv as a suffix for the device-private data struct
+ if ($line =~ /^\+\s*\.${auto}\s*=\s*sizeof\(struct\((\w+)\).*/) {
+ my $struct_name = $1;
+ if ($struct_name !~ /^\w+${suffix}/) {
+ WARN($warning, "struct \'$struct_name\' should have a ${suffix} suffix");
+ }
+ }
+}
+
# Checks specific to U-Boot
sub u_boot_line {
my ($realfile, $line, $rawline, $herecurr) = @_;
ERROR("CONFIG_IS_ENABLED_CONFIG",
"CONFIG_IS_ENABLED() takes values without the CONFIG_ prefix\n" . $herecurr);
}
+
+ # Use _priv as a suffix for the device-private data struct
+ if ($line =~ /^\+\s*\.priv_auto\s*=\s*sizeof\(struct\((\w+)\).*/) {
+ my $struct_name = $1;
+ if ($struct_name !~ /^\w+_priv/) {
+ WARN("PRIV_AUTO", "struct \'$struct_name\' should have a _priv suffix");
+ }
+ }
+
+ # Check struct names for the 'auto' members of struct driver
+ u_boot_struct_name($line, "priv_auto", "_priv", "PRIV_AUTO");
+ u_boot_struct_name($line, "plat_auto", "_plat", "PLAT_AUTO");
+ u_boot_struct_name($line, "per_child_auto", "_priv", "CHILD_PRIV_AUTO");
+ u_boot_struct_name($line, "per_child_plat_auto", "_plat",
+ "CHILD_PLAT_AUTO");
+
+ # Now the ones for struct uclass, skipping those in common with above
+ u_boot_struct_name($line, "per_device_auto", "_priv",
+ "DEVICE_PRIV_AUTO");
+ u_boot_struct_name($line, "per_device_plat_auto", "_plat",
+ "DEVICE_PLAT_AUTO");
}
sub process {
#define BUF_SIZE 4096
/**
- * struct testacpi_platdata - Platform data for the test ACPI device
+ * struct testacpi_plat - Platform data for the test ACPI device
*
* @no_name: true to emit an empty ACPI name from testacpi_get_name()
* @return_error: true to return an error instead of a name
*/
-struct testacpi_platdata {
+struct testacpi_plat {
bool return_error;
bool no_name;
};
static int testacpi_get_name(const struct udevice *dev, char *out_name)
{
- struct testacpi_platdata *plat = dev_get_platdata(dev);
+ struct testacpi_plat *plat = dev_get_plat(dev);
if (plat->return_error)
return -EINVAL;
.of_match = testacpi_ids,
.id = UCLASS_TEST_ACPI,
.bind = dm_scan_fdt_dev,
- .platdata_auto_alloc_size = sizeof(struct testacpi_platdata),
+ .plat_auto = sizeof(struct testacpi_plat),
ACPI_OPS_PTR(&testacpi_ops)
};
/* Test acpi_device_path() */
static int dm_test_acpi_device_path(struct unit_test_state *uts)
{
- struct testacpi_platdata *plat;
+ struct testacpi_plat *plat;
char buf[ACPI_PATH_MAX];
struct udevice *dev, *child;
buf);
/* Test handling of a device which doesn't produce a name */
- plat = dev_get_platdata(dev);
+ plat = dev_get_plat(dev);
plat->no_name = true;
ut_assertok(acpi_device_path(child, buf, sizeof(buf)));
ut_asserteq_str("\\_SB." ACPI_TEST_CHILD_NAME, buf);
/* Test handling of a device which returns an error */
- plat = dev_get_platdata(dev);
+ plat = dev_get_plat(dev);
plat->return_error = true;
ut_asserteq(-EINVAL, acpi_device_path(child, buf, sizeof(buf)));
ut_assertok(regulator_set_value(supply, SANDBOX_BUCK2_SET_UV));
ut_asserteq(SANDBOX_BUCK2_SET_UV, regulator_get_value(supply));
- /* Update ADC platdata and get new Vdd value */
+ /* Update ADC plat and get new Vdd value */
ut_assertok(adc_vdd_value(dev, &uV));
ut_asserteq(SANDBOX_BUCK2_SET_UV, uV);
* Check that the block device devnum matches its parent's
* sequence number
*/
- desc = dev_get_uclass_platdata(dev);
+ desc = dev_get_uclass_plat(dev);
ut_asserteq(desc->devnum, i);
}
DECLARE_GLOBAL_DATA_PTR;
-struct dm_test_parent_platdata {
+struct dm_test_parent_plat {
int count;
int bind_flag;
int uclass_bind_flag;
static int testbus_child_post_bind(struct udevice *dev)
{
- struct dm_test_parent_platdata *plat;
+ struct dm_test_parent_plat *plat;
- plat = dev_get_parent_platdata(dev);
+ plat = dev_get_parent_plat(dev);
plat->bind_flag = 1;
plat->uclass_bind_flag = 2;
.id = UCLASS_TEST_BUS,
.probe = testbus_drv_probe,
.child_post_bind = testbus_child_post_bind,
- .priv_auto_alloc_size = sizeof(struct dm_test_priv),
- .platdata_auto_alloc_size = sizeof(struct dm_test_pdata),
- .per_child_auto_alloc_size = sizeof(struct dm_test_parent_data),
- .per_child_platdata_auto_alloc_size =
- sizeof(struct dm_test_parent_platdata),
+ .priv_auto = sizeof(struct dm_test_priv),
+ .plat_auto = sizeof(struct dm_test_pdata),
+ .per_child_auto = sizeof(struct dm_test_parent_data),
+ .per_child_plat_auto = sizeof(struct dm_test_parent_plat),
.child_pre_probe = testbus_child_pre_probe,
.child_post_remove = testbus_child_post_remove,
};
/* Set the driver size to 0 so that the uclass size is used */
ut_assertok(uclass_find_device(UCLASS_TEST_BUS, 0, &bus));
drv = (struct driver *)bus->driver;
- size = drv->per_child_auto_alloc_size;
+ size = drv->per_child_auto;
#ifdef CONFIG_SANDBOX
os_mprotect_allow(bus->uclass->uc_drv, sizeof(*bus->uclass->uc_drv));
os_mprotect_allow(drv, sizeof(*drv));
#endif
- bus->uclass->uc_drv->per_child_auto_alloc_size = size;
- drv->per_child_auto_alloc_size = 0;
+ bus->uclass->uc_drv->per_child_auto = size;
+ drv->per_child_auto = 0;
ret = test_bus_parent_data(uts);
if (ret)
return ret;
- bus->uclass->uc_drv->per_child_auto_alloc_size = 0;
- drv->per_child_auto_alloc_size = size;
+ bus->uclass->uc_drv->per_child_auto = 0;
+ drv->per_child_auto = size;
return 0;
}
}
DM_TEST(dm_test_bus_parent_ops, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
-static int test_bus_parent_platdata(struct unit_test_state *uts)
+static int test_bus_parent_plat(struct unit_test_state *uts)
{
- struct dm_test_parent_platdata *plat;
+ struct dm_test_parent_plat *plat;
struct udevice *bus, *dev;
/* Check that the bus has no children */
dev;
device_find_next_child(&dev)) {
/* Check that platform data is allocated */
- plat = dev_get_parent_platdata(dev);
+ plat = dev_get_parent_plat(dev);
ut_assert(plat != NULL);
/*
device_probe(dev);
device_remove(dev, DM_REMOVE_NORMAL);
- ut_asserteq_ptr(plat, dev_get_parent_platdata(dev));
+ ut_asserteq_ptr(plat, dev_get_parent_plat(dev));
ut_asserteq(1, plat->count);
ut_assertok(device_probe(dev));
}
dev;
device_find_next_child(&dev)) {
/* Check that platform data is allocated */
- plat = dev_get_parent_platdata(dev);
+ plat = dev_get_parent_plat(dev);
ut_assert(plat != NULL);
ut_asserteq(1, plat->count);
}
device_unbind(dev);
} while (dev);
- /* Now the child platdata should be removed and re-added */
+ /* Now the child plat should be removed and re-added */
device_probe(bus);
for (device_find_first_child(bus, &dev);
dev;
device_find_next_child(&dev)) {
/* Check that platform data is allocated */
- plat = dev_get_parent_platdata(dev);
+ plat = dev_get_parent_plat(dev);
ut_assert(plat != NULL);
ut_asserteq(0, plat->count);
}
}
/* Test that the bus can store platform data about each child */
-static int dm_test_bus_parent_platdata(struct unit_test_state *uts)
+static int dm_test_bus_parent_plat(struct unit_test_state *uts)
{
- return test_bus_parent_platdata(uts);
+ return test_bus_parent_plat(uts);
}
-DM_TEST(dm_test_bus_parent_platdata, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_bus_parent_plat, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
/* As above but the size is controlled by the uclass */
-static int dm_test_bus_parent_platdata_uclass(struct unit_test_state *uts)
+static int dm_test_bus_parent_plat_uclass(struct unit_test_state *uts)
{
struct udevice *bus;
struct driver *drv;
/* Set the driver size to 0 so that the uclass size is used */
ut_assertok(uclass_find_device(UCLASS_TEST_BUS, 0, &bus));
drv = (struct driver *)bus->driver;
- size = drv->per_child_platdata_auto_alloc_size;
+ size = drv->per_child_plat_auto;
#ifdef CONFIG_SANDBOX
os_mprotect_allow(bus->uclass->uc_drv, sizeof(*bus->uclass->uc_drv));
os_mprotect_allow(drv, sizeof(*drv));
#endif
- bus->uclass->uc_drv->per_child_platdata_auto_alloc_size = size;
- drv->per_child_platdata_auto_alloc_size = 0;
- ret = test_bus_parent_platdata(uts);
+ bus->uclass->uc_drv->per_child_plat_auto = size;
+ drv->per_child_plat_auto = 0;
+ ret = test_bus_parent_plat(uts);
if (ret)
return ret;
- bus->uclass->uc_drv->per_child_platdata_auto_alloc_size = 0;
- drv->per_child_platdata_auto_alloc_size = size;
+ bus->uclass->uc_drv->per_child_plat_auto = 0;
+ drv->per_child_plat_auto = size;
return 0;
}
-DM_TEST(dm_test_bus_parent_platdata_uclass,
+DM_TEST(dm_test_bus_parent_plat_uclass,
UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
/* Test that the child post_bind method is called */
static int dm_test_bus_child_post_bind(struct unit_test_state *uts)
{
- struct dm_test_parent_platdata *plat;
+ struct dm_test_parent_plat *plat;
struct udevice *bus, *dev;
ut_assertok(uclass_get_device(UCLASS_TEST_BUS, 0, &bus));
dev;
device_find_next_child(&dev)) {
/* Check that platform data is allocated */
- plat = dev_get_parent_platdata(dev);
+ plat = dev_get_parent_plat(dev);
ut_assert(plat != NULL);
ut_asserteq(1, plat->bind_flag);
}
/* Test that the child post_bind method is called */
static int dm_test_bus_child_post_bind_uclass(struct unit_test_state *uts)
{
- struct dm_test_parent_platdata *plat;
+ struct dm_test_parent_plat *plat;
struct udevice *bus, *dev;
ut_assertok(uclass_get_device(UCLASS_TEST_BUS, 0, &bus));
dev;
device_find_next_child(&dev)) {
/* Check that platform data is allocated */
- plat = dev_get_parent_platdata(dev);
+ plat = dev_get_parent_plat(dev);
ut_assert(plat != NULL);
ut_asserteq(2, plat->uclass_bind_flag);
}
U_BOOT_DEVICE(dm_test_info1) = {
.name = "test_drv",
- .platdata = &test_pdata[0],
+ .plat = &test_pdata[0],
};
U_BOOT_DEVICE(dm_test_info2) = {
.name = "test_drv",
- .platdata = &test_pdata[1],
+ .plat = &test_pdata[1],
};
U_BOOT_DEVICE(dm_test_info3) = {
.name = "test_drv",
- .platdata = &test_pdata[2],
+ .plat = &test_pdata[2],
};
static struct driver_info driver_info_manual = {
.name = "test_manual_drv",
- .platdata = &test_pdata_manual,
+ .plat = &test_pdata_manual,
};
static struct driver_info driver_info_pre_reloc = {
.name = "test_pre_reloc_drv",
- .platdata = &test_pdata_pre_reloc,
+ .plat = &test_pdata_pre_reloc,
};
static struct driver_info driver_info_act_dma = {
return 0;
}
-/* Test that binding with platdata occurs correctly */
+/* Test that binding with plat occurs correctly */
static int dm_test_autobind(struct unit_test_state *uts)
{
struct dm_test_state *dms = uts->priv;
ut_asserteq(0, list_count_items(&gd->dm_root->child_head));
ut_asserteq(0, dm_testdrv_op_count[DM_TEST_OP_POST_BIND]);
- ut_assertok(dm_scan_platdata(false));
+ ut_assertok(dm_scan_plat(false));
/* We should have our test class now at least, plus more children */
ut_assert(1 < list_count_items(&gd->uclass_root));
}
DM_TEST(dm_test_autobind, 0);
-/* Test that binding with uclass platdata allocation occurs correctly */
+/* Test that binding with uclass plat allocation occurs correctly */
static int dm_test_autobind_uclass_pdata_alloc(struct unit_test_state *uts)
{
struct dm_test_perdev_uc_pdata *uc_pdata;
/**
* Test if test uclass driver requires allocation for the uclass
- * platform data and then check the dev->uclass_platdata pointer.
+ * platform data and then check the dev->uclass_plat pointer.
*/
- ut_assert(uc->uc_drv->per_device_platdata_auto_alloc_size);
+ ut_assert(uc->uc_drv->per_device_plat_auto);
for (uclass_find_first_device(UCLASS_TEST, &dev);
dev;
uclass_find_next_device(&dev)) {
ut_assertnonnull(dev);
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
ut_assert(uc_pdata);
}
}
DM_TEST(dm_test_autobind_uclass_pdata_alloc, UT_TESTF_SCAN_PDATA);
-/* Test that binding with uclass platdata setting occurs correctly */
+/* Test that binding with uclass plat setting occurs correctly */
static int dm_test_autobind_uclass_pdata_valid(struct unit_test_state *uts)
{
struct dm_test_perdev_uc_pdata *uc_pdata;
uclass_find_next_device(&dev)) {
ut_assertnonnull(dev);
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
ut_assert(uc_pdata);
ut_assert(uc_pdata->intval1 == TEST_UC_PDATA_INTVAL1);
ut_assert(uc_pdata->intval2 == TEST_UC_PDATA_INTVAL2);
ut_assert(priv);
ut_asserteq(expected_base_add, priv->base_add);
- pdata = dev->platdata;
+ pdata = dev->plat;
expected_base_add += pdata->ping_add;
}
}
DM_TEST(dm_test_autoprobe, UT_TESTF_SCAN_PDATA);
-/* Check that we see the correct platdata in each device */
-static int dm_test_platdata(struct unit_test_state *uts)
+/* Check that we see the correct plat in each device */
+static int dm_test_plat(struct unit_test_state *uts)
{
const struct dm_test_pdata *pdata;
struct udevice *dev;
for (i = 0; i < 3; i++) {
ut_assertok(uclass_find_device(UCLASS_TEST, i, &dev));
ut_assert(dev);
- pdata = dev->platdata;
+ pdata = dev->plat;
ut_assert(pdata->ping_add == test_pdata[i].ping_add);
}
return 0;
}
-DM_TEST(dm_test_platdata, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_plat, UT_TESTF_SCAN_PDATA);
/* Test that we can bind, probe, remove, unbind a driver */
static int dm_test_lifecycle(struct unit_test_state *uts)
int expected;
int pingret;
- /* Getting the child device should allocate platdata / priv */
+ /* Getting the child device should allocate plat / priv */
ut_assertok(testfdt_ping(dev, 10, &pingret));
ut_assert(dev->priv);
- ut_assert(dev->platdata);
+ ut_assert(dev->plat);
expected = 10 + base;
ut_asserteq(expected, pingret);
/*
* Get the 'reg' property, which tells us what the ping add
- * should be. We don't use the platdata because we want
+ * should be. We don't use the plat because we want
* to test the code that sets that up (testfdt_drv_probe()).
*/
base = test_pdata[i].ping_add;
dm_leak_check_start(uts);
- ut_assertok(dm_scan_platdata(false));
- ut_assertok(dm_scan_fdt(gd->fdt_blob, false));
+ ut_assertok(dm_scan_plat(false));
+ ut_assertok(dm_scan_fdt(false));
/* Scanning the uclass is enough to probe all the devices */
for (id = UCLASS_ROOT; id < UCLASS_COUNT; id++) {
&driver_info_manual, &dev));
pdata = calloc(1, sizeof(*pdata));
pdata->ping_add = key + i;
- dev->platdata = pdata;
+ dev->plat = pdata;
if (child)
child[i] = dev;
}
*/
ut_asserteq(-ENODEV, device_find_first_inactive_child(parent,
UCLASS_TEST, &dev1));
- ut_assertok(device_bind_ofnode(parent, DM_GET_DRIVER(test_drv),
- "test_child", 0, ofnode_null(), &dev1));
+ ut_assertok(device_bind(parent, DM_GET_DRIVER(test_drv),
+ "test_child", 0, ofnode_null(), &dev1));
ut_assertok(device_find_first_inactive_child(parent, UCLASS_TEST,
&dev2));
ut_asserteq(1, stats.allocs);
ut_asserteq(TEST_DEVRES_SIZE, stats.total_size);
- /* Getting platdata should add one allocation */
- ut_assertok(device_ofdata_to_platdata(dev));
+ /* Getting plat should add one allocation */
+ ut_assertok(device_of_to_plat(dev));
devres_get_stats(dev, &stats);
ut_asserteq(2, stats.allocs);
ut_asserteq(TEST_DEVRES_SIZE + TEST_DEVRES_SIZE3, stats.total_size);
/*
* We expect to get 4 banks. One is anonymous (just numbered) and
- * comes from platdata. The other are named a (20 gpios),
+ * comes from plat. The other are named a (20 gpios),
* b (10 gpios) and c (10 gpios) and come from the device tree. See
* test/dm/test.dts.
*/
.of_match = mux_emul_of_match,
.ops = &mux_emul_ops,
.probe = mux_emul_probe,
- .priv_auto_alloc_size = sizeof(struct mux_emul_priv),
+ .priv_auto = sizeof(struct mux_emul_priv),
};
static int dm_test_mux_emul_default_state(struct unit_test_state *uts)
#include <test/ut.h>
/* Test that we can find a device using of-platdata */
-static int dm_test_of_platdata_base(struct unit_test_state *uts)
+static int dm_test_of_plat_base(struct unit_test_state *uts)
{
struct udevice *dev;
return 0;
}
-DM_TEST(dm_test_of_platdata_base, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_of_plat_base, UT_TESTF_SCAN_PDATA);
/* Test that we can read properties from a device */
-static int dm_test_of_platdata_props(struct unit_test_state *uts)
+static int dm_test_of_plat_props(struct unit_test_state *uts)
{
struct dtd_sandbox_spl_test *plat;
struct udevice *dev;
ut_asserteq_str("sandbox_clk_test", dev->name);
ut_assertok(uclass_next_device_err(&dev));
- plat = dev_get_platdata(dev);
+ plat = dev_get_plat(dev);
ut_assert(plat->boolval);
ut_asserteq(1, plat->intval);
ut_asserteq(4, ARRAY_SIZE(plat->intarray));
ut_asserteq_str("", plat->stringarray[2]);
ut_assertok(uclass_next_device_err(&dev));
- plat = dev_get_platdata(dev);
+ plat = dev_get_plat(dev);
ut_assert(!plat->boolval);
ut_asserteq(3, plat->intval);
ut_asserteq(5, plat->intarray[0]);
ut_asserteq_str("message", plat->stringarray[2]);
ut_assertok(uclass_next_device_err(&dev));
- plat = dev_get_platdata(dev);
+ plat = dev_get_plat(dev);
ut_assert(!plat->boolval);
ut_asserteq_str("one", plat->stringarray[0]);
ut_asserteq_str("", plat->stringarray[1]);
ut_asserteq_str("", plat->stringarray[2]);
ut_assertok(uclass_next_device_err(&dev));
- plat = dev_get_platdata(dev);
+ plat = dev_get_plat(dev);
ut_assert(!plat->boolval);
ut_asserteq_str("spl", plat->stringarray[0]);
return 0;
}
-DM_TEST(dm_test_of_platdata_props, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_of_plat_props, UT_TESTF_SCAN_PDATA);
/*
* find_driver_info - recursively find the driver_info for a device
}
/* Check that every device is recorded in its driver_info struct */
-static int dm_test_of_platdata_dev(struct unit_test_state *uts)
+static int dm_test_of_plat_dev(struct unit_test_state *uts)
{
const struct driver_info *info =
ll_entry_start(struct driver_info, driver_info);
return 0;
}
-DM_TEST(dm_test_of_platdata_dev, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_of_plat_dev, UT_TESTF_SCAN_PDATA);
/* Test handling of phandles that point to other devices */
-static int dm_test_of_platdata_phandle(struct unit_test_state *uts)
+static int dm_test_of_plat_phandle(struct unit_test_state *uts)
{
struct dtd_sandbox_clk_test *plat;
struct udevice *dev, *clk;
ut_assertok(uclass_first_device_err(UCLASS_MISC, &dev));
ut_asserteq_str("sandbox_clk_test", dev->name);
- plat = dev_get_platdata(dev);
+ plat = dev_get_plat(dev);
ut_assertok(device_get_by_driver_info_idx(plat->clocks[0].idx, &clk));
ut_asserteq_str("fixed_clock", clk->name);
return 0;
}
-DM_TEST(dm_test_of_platdata_phandle, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_of_plat_phandle, UT_TESTF_SCAN_PDATA);
#if CONFIG_IS_ENABLED(OF_PLATDATA_PARENT)
/* Test that device parents are correctly set up */
-static int dm_test_of_platdata_parent(struct unit_test_state *uts)
+static int dm_test_of_plat_parent(struct unit_test_state *uts)
{
struct udevice *rtc, *i2c;
return 0;
}
-DM_TEST(dm_test_of_platdata_parent, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_of_plat_parent, UT_TESTF_SCAN_PDATA);
#endif
}
DM_TEST(dm_test_ofnode_get_child_count,
UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+
+static int dm_test_ofnode_is_enabled(struct unit_test_state *uts)
+{
+ ofnode root_node = ofnode_path("/");
+ ofnode node = ofnode_path("/usb@0");
+
+ ut_assert(ofnode_is_enabled(root_node));
+ ut_assert(!ofnode_is_enabled(node));
+
+ return 0;
+}
+DM_TEST(dm_test_ofnode_is_enabled, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
ut_asserteq(4, len);
break;
case 3:
- /* only for platdata */
+ /* only for plat */
ut_asserteq_str("name", propname);
ut_asserteq(6, len);
ut_asserteq_str("flash", value);
.of_match = regmaptest_ids,
.id = UCLASS_NOP,
.probe = remaptest_probe,
- .priv_auto_alloc_size = sizeof(struct regmaptest_priv),
+ .priv_auto = sizeof(struct regmaptest_priv),
};
static int dm_test_devm_regmap(struct unit_test_state *uts)
/* Test regulator get method */
static int dm_test_power_regulator_get(struct unit_test_state *uts)
{
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
struct udevice *dev_by_devname;
struct udevice *dev_by_platname;
const char *devname;
* a device with the name equal to the requested one.
*/
ut_assertok(regulator_get_by_platname(platname, &dev_by_platname));
- uc_pdata = dev_get_uclass_platdata(dev_by_platname);
+ uc_pdata = dev_get_uclass_plat(dev_by_platname);
ut_assert(uc_pdata);
ut_asserteq_str(platname, uc_pdata->name);
/* Test regulator set and get Voltage method */
static int dm_test_power_regulator_set_get_voltage(struct unit_test_state *uts)
{
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
struct udevice *dev;
const char *platname;
int val_set, val_get;
platname = regulator_names[BUCK1][PLATNAME];
ut_assertok(regulator_get_by_platname(platname, &dev));
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
ut_assert(uc_pdata);
val_set = uc_pdata->min_uV;
/* Test regulator set and get Current method */
static int dm_test_power_regulator_set_get_current(struct unit_test_state *uts)
{
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
struct udevice *dev;
const char *platname;
int val_set, val_get;
platname = regulator_names[LDO1][PLATNAME];
ut_assertok(regulator_get_by_platname(platname, &dev));
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
ut_assert(uc_pdata);
val_set = uc_pdata->min_uA;
platname = regulator_names[LDO2][PLATNAME];
ut_assertok(regulator_get_by_platname(platname, &dev));
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
ut_assert(uc_pdata);
ut_asserteq(-ENODATA, uc_pdata->min_uA);
ut_asserteq(-ENODATA, uc_pdata->max_uA);
/* Test regulator set and get suspend Voltage method */
static int dm_test_power_regulator_set_get_suspend_voltage(struct unit_test_state *uts)
{
- struct dm_regulator_uclass_platdata *uc_pdata;
+ struct dm_regulator_uclass_plat *uc_pdata;
const struct dm_regulator_ops *ops;
struct udevice *dev;
const char *platname;
platname = regulator_names[BUCK1][PLATNAME];
ut_assertok(regulator_get_by_platname(platname, &dev));
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
ut_assert(uc_pdata);
ops = dev_get_driver_ops(dev);
static int testdrv_ping(struct udevice *dev, int pingval, int *pingret)
{
- const struct dm_test_pdata *pdata = dev_get_platdata(dev);
+ const struct dm_test_pdata *pdata = dev_get_plat(dev);
struct dm_test_priv *priv = dev_get_priv(dev);
*pingret = pingval + pdata->ping_add;
.probe = test_probe,
.remove = test_remove,
.unbind = test_unbind,
- .priv_auto_alloc_size = sizeof(struct dm_test_priv),
+ .priv_auto = sizeof(struct dm_test_priv),
};
U_BOOT_DRIVER(test2_drv) = {
.probe = test_probe,
.remove = test_remove,
.unbind = test_unbind,
- .priv_auto_alloc_size = sizeof(struct dm_test_priv),
+ .priv_auto = sizeof(struct dm_test_priv),
};
static int test_manual_drv_ping(struct udevice *dev, int pingval, int *pingret)
static int testfdt_drv_ping(struct udevice *dev, int pingval, int *pingret)
{
- const struct dm_test_pdata *pdata = dev->platdata;
+ const struct dm_test_pdata *pdata = dev->plat;
struct dm_test_priv *priv = dev_get_priv(dev);
*pingret = pingval + pdata->ping_add;
.ping = testfdt_drv_ping,
};
-static int testfdt_ofdata_to_platdata(struct udevice *dev)
+static int testfdt_of_to_plat(struct udevice *dev)
{
- struct dm_test_pdata *pdata = dev_get_platdata(dev);
+ struct dm_test_pdata *pdata = dev_get_plat(dev);
pdata->ping_add = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"ping-add", -1);
.name = "testfdt_drv",
.of_match = testfdt_ids,
.id = UCLASS_TEST_FDT,
- .ofdata_to_platdata = testfdt_ofdata_to_platdata,
+ .of_to_plat = testfdt_of_to_plat,
.probe = testfdt_drv_probe,
.ops = &test_ops,
- .priv_auto_alloc_size = sizeof(struct dm_test_priv),
- .platdata_auto_alloc_size = sizeof(struct dm_test_pdata),
+ .priv_auto = sizeof(struct dm_test_priv),
+ .plat_auto = sizeof(struct dm_test_pdata),
};
static const struct udevice_id testfdt1_ids[] = {
.name = "testfdt1_drv",
.of_match = testfdt1_ids,
.id = UCLASS_TEST_FDT,
- .ofdata_to_platdata = testfdt_ofdata_to_platdata,
+ .of_to_plat = testfdt_of_to_plat,
.probe = testfdt_drv_probe,
.ops = &test_ops,
- .priv_auto_alloc_size = sizeof(struct dm_test_priv),
- .platdata_auto_alloc_size = sizeof(struct dm_test_pdata),
+ .priv_auto = sizeof(struct dm_test_priv),
+ .plat_auto = sizeof(struct dm_test_pdata),
.flags = DM_FLAG_PRE_RELOC,
};
static int testprobe_drv_probe(struct udevice *dev)
{
- struct dm_testprobe_pdata *pdata = dev_get_platdata(dev);
+ struct dm_testprobe_pdata *pdata = dev_get_plat(dev);
return pdata->probe_err;
}
.of_match = testprobe_ids,
.id = UCLASS_TEST_PROBE,
.probe = testprobe_drv_probe,
- .platdata_auto_alloc_size = sizeof(struct dm_testprobe_pdata),
+ .plat_auto = sizeof(struct dm_testprobe_pdata),
};
UCLASS_DRIVER(testprobe) = {
static int testdevres_drv_bind(struct udevice *dev)
{
- struct dm_testdevres_pdata *pdata = dev_get_platdata(dev);
+ struct dm_testdevres_pdata *pdata = dev_get_plat(dev);
pdata->ptr = devm_kmalloc(dev, TEST_DEVRES_SIZE, 0);
return 0;
}
-static int testdevres_drv_ofdata_to_platdata(struct udevice *dev)
+static int testdevres_drv_of_to_plat(struct udevice *dev)
{
struct dm_testdevres_priv *priv = dev_get_priv(dev);
.of_match = testdevres_ids,
.id = UCLASS_TEST_DEVRES,
.bind = testdevres_drv_bind,
- .ofdata_to_platdata = testdevres_drv_ofdata_to_platdata,
+ .of_to_plat = testdevres_drv_of_to_plat,
.probe = testdevres_drv_probe,
- .platdata_auto_alloc_size = sizeof(struct dm_testdevres_pdata),
- .priv_auto_alloc_size = sizeof(struct dm_testdevres_priv),
+ .plat_auto = sizeof(struct dm_testdevres_pdata),
+ .priv_auto = sizeof(struct dm_testdevres_priv),
};
UCLASS_DRIVER(testdevres) = {
/*
* Get the 'ping-expect' property, which tells us what the
- * ping add should be. We don't use the platdata because we
+ * ping add should be. We don't use the plat because we
* want to test the code that sets that up
* (testfdt_drv_probe()).
*/
int ret;
int i;
- ret = dm_extended_scan_fdt(gd->fdt_blob, false);
+ ret = dm_extended_scan(false);
ut_assert(!ret);
ret = uclass_get(UCLASS_TEST_FDT, &uc);
ret = uclass_find_device(UCLASS_TEST_FDT, i, &dev);
ut_assert(!ret);
ut_assert(!dev_get_priv(dev));
- ut_assert(dev->platdata);
+ ut_assert(dev->plat);
}
ut_assertok(dm_check_devices(uts, num_devices));
struct uclass *uc;
int ret;
- ret = dm_scan_fdt(gd->fdt_blob, true);
+ ret = dm_scan_fdt(true);
ut_assert(!ret);
ret = uclass_get(UCLASS_TEST_FDT, &uc);
/* Remove them and try again, with an error on the second one */
ut_assertok(uclass_get_device(UCLASS_TEST_PROBE, 1, &dev));
- pdata = dev_get_platdata(dev);
+ pdata = dev_get_plat(dev);
pdata->probe_err = -ENOMEM;
device_remove(parent, DM_REMOVE_NORMAL);
ut_assertok(uclass_first_device(UCLASS_TEST_PROBE, &dev));
/* Now an error on the first one */
ut_assertok(uclass_get_device(UCLASS_TEST_PROBE, 0, &dev));
- pdata = dev_get_platdata(dev);
+ pdata = dev_get_plat(dev);
pdata->probe_err = -ENOENT;
device_remove(parent, DM_REMOVE_NORMAL);
ut_asserteq(-ENOENT, uclass_first_device(UCLASS_TEST_PROBE, &dev));
ut_assertok(check_devices(uts, devlist, 0));
/* Remove them and try again, with an error on the second one */
- pdata = dev_get_platdata(devlist[1]);
+ pdata = dev_get_plat(devlist[1]);
pdata->probe_err = -ENOENT - 1;
device_remove(parent, DM_REMOVE_NORMAL);
ut_assertok(check_devices(uts, devlist, 1 << 1));
/* Now an error on the first one */
- pdata = dev_get_platdata(devlist[0]);
+ pdata = dev_get_plat(devlist[0]);
pdata->probe_err = -ENOENT - 0;
device_remove(parent, DM_REMOVE_NORMAL);
ut_assertok(check_devices(uts, devlist, 3 << 0));
/* Now errors on all */
- pdata = dev_get_platdata(devlist[2]);
+ pdata = dev_get_plat(devlist[2]);
pdata->probe_err = -ENOENT - 2;
- pdata = dev_get_platdata(devlist[3]);
+ pdata = dev_get_plat(devlist[3]);
pdata->probe_err = -ENOENT - 3;
device_remove(parent, DM_REMOVE_NORMAL);
ut_assertok(check_devices(uts, devlist, 0xf << 0));
ut_assertok(uclass_first_device_err(UCLASS_TEST_BUS, &bus));
count = 0;
- device_foreach_child_ofdata_to_platdata(dev, bus) {
+ device_foreach_child_of_to_plat(dev, bus) {
ut_assert(dev->flags & DM_FLAG_PLATDATA_VALID);
ut_assert(!(dev->flags & DM_FLAG_ACTIVATED));
count++;
ut_assert(!(dev->flags & DM_FLAG_PLATDATA_VALID));
/* read the child's ofdata which should cause the parent's to be read */
- ut_assertok(device_ofdata_to_platdata(dev));
+ ut_assertok(device_of_to_plat(dev));
ut_assert(dev->flags & DM_FLAG_PLATDATA_VALID);
ut_assert(bus->flags & DM_FLAG_PLATDATA_VALID);
uts->start = mallinfo();
if (test->flags & UT_TESTF_SCAN_PDATA)
- ut_assertok(dm_scan_platdata(false));
+ ut_assertok(dm_scan_plat(false));
if (test->flags & UT_TESTF_PROBE_TEST)
ut_assertok(do_autoprobe(uts));
if (!CONFIG_IS_ENABLED(OF_PLATDATA) &&
(test->flags & UT_TESTF_SCAN_FDT))
- ut_assertok(dm_extended_scan_fdt(gd->fdt_blob, false));
+ ut_assertok(dm_extended_scan(false));
/*
* Silence the console and rely on console recording to get
gd_set_of_root(uts->of_root);
gd->dm_root = NULL;
ut_assertok(dm_init(CONFIG_IS_ENABLED(OF_LIVE)));
- dm_scan_platdata(false);
+ dm_scan_plat(false);
if (!CONFIG_IS_ENABLED(OF_PLATDATA))
- dm_scan_fdt(gd->fdt_blob, false);
+ dm_scan_fdt(false);
return uts->fail_count ? CMD_RET_FAILURE : 0;
}
dm_testdrv_op_count[DM_TEST_OP_POST_BIND]++;
ut_assert(!device_active(dev));
- uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata = dev_get_uclass_plat(dev);
ut_assert(uc_pdata);
uc_pdata->intval1 = TEST_UC_PDATA_INTVAL1;
if (&prev->uclass_node != &uc->dev_head) {
struct dm_test_uclass_perdev_priv *prev_uc_priv
= dev_get_uclass_priv(prev);
- struct dm_test_pdata *pdata = prev->platdata;
+ struct dm_test_pdata *pdata = prev->plat;
ut_assert(pdata);
ut_assert(prev_uc_priv);
.pre_remove = test_pre_remove,
.init = test_init,
.destroy = test_destroy,
- .priv_auto_alloc_size = sizeof(struct dm_test_uclass_priv),
- .per_device_auto_alloc_size = sizeof(struct dm_test_uclass_perdev_priv),
- .per_device_platdata_auto_alloc_size =
- sizeof(struct dm_test_perdev_uc_pdata),
+ .priv_auto = sizeof(struct dm_test_uclass_priv),
+ .per_device_auto = sizeof(struct dm_test_uclass_perdev_priv),
+ .per_device_plat_auto = sizeof(struct dm_test_perdev_uc_pdata),
};
ut_assertok(uclass_find_device(UCLASS_VIDEO, 0, &dev));
ut_assert(!device_active(dev));
- plat = dev_get_platdata(dev);
+ plat = dev_get_plat(dev);
plat->vidconsole_drv_name = "vidconsole0";
return 0;
ut_assertok(uclass_find_device(UCLASS_VIDEO, 0, &dev));
ut_assert(!device_active(dev));
- plat = dev_get_platdata(dev);
+ plat = dev_get_plat(dev);
plat->rot = rot;
ut_assertok(uclass_get_device(UCLASS_VIDEO, 0, &dev));
ut_assertok(uclass_find_device(UCLASS_VIDEO, 0, &dev));
ut_assert(!device_active(dev));
- plat = dev_get_platdata(dev);
+ plat = dev_get_plat(dev);
plat->font_size = 100;
ut_assertok(uclass_get_device(UCLASS_VIDEO, 0, &dev));
ut_assertok(uclass_find_device(UCLASS_VIDEO, 0, &dev));
ut_assert(!device_active(dev));
- plat = dev_get_platdata(dev);
+ plat = dev_get_plat(dev);
plat->font_size = 100;
ut_assertok(uclass_get_device(UCLASS_VIDEO, 0, &dev));
u_boot_console.kill(signal.SIGINT)
assert(u_boot_console.validate_exited())
+
+def test_exception_reset(u_boot_console):
+ """Test that SIGILL causes a reset."""
+
+ u_boot_console.run_command('exception undefined', wait_for_prompt=False)
+ m = u_boot_console.p.expect(['resetting ...', 'U-Boot'])
+ if m != 0:
+ raise Exception('SIGILL did not lead to reset')
+ m = u_boot_console.p.expect(['U-Boot', '=>'])
+ if m != 0:
+ raise Exception('SIGILL did not lead to reset')
+ u_boot_console.restart_uboot()
+
+def test_exception_exit(u_boot_console):
+ """Test that SIGILL causes a reset."""
+
+ u_boot_console.run_command('exception undefined', wait_for_prompt=False)
+ assert(u_boot_console.validate_exited())
# Spilt the text into two parts so that we can make the entry point two
# bytes after the start of the text section
- text_bytes1 = ['\t.byte\t%#x' % tools.ToByte(byte) for byte in text[:2]]
- text_bytes2 = ['\t.byte\t%#x' % tools.ToByte(byte) for byte in text[2:]]
- data_bytes = ['\t.byte\t%#x' % tools.ToByte(byte) for byte in data]
+ text_bytes1 = ['\t.byte\t%#x' % byte for byte in text[:2]]
+ text_bytes2 = ['\t.byte\t%#x' % byte for byte in text[2:]]
+ data_bytes = ['\t.byte\t%#x' % byte for byte in data]
with open(s_file, 'w') as fd:
print('''/* Auto-generated C program to produce an ELF file for testing */
if pos is not None:
pos -= entry.section.GetRootSkipAtStart()
areas.append(fmap_util.FmapArea(pos or 0, entry.size or 0,
- tools.FromUnicode(entry.name), 0))
+ entry.name, 0))
entries = self.GetImage().GetEntries()
areas = []
self.assertEquals('me.bin', val)
prop = node.props['intval']
- self.assertEquals(fdt.TYPE_INT, prop.type)
+ self.assertEquals(fdt.Type.INT, prop.type)
self.assertEquals(3, fdt_util.GetInt(node, 'intval'))
prop = node.props['intarray']
- self.assertEquals(fdt.TYPE_INT, prop.type)
+ self.assertEquals(fdt.Type.INT, prop.type)
self.assertEquals(list, type(prop.value))
self.assertEquals(2, len(prop.value))
self.assertEquals([5, 6],
[fdt_util.fdt32_to_cpu(val) for val in prop.value])
prop = node.props['byteval']
- self.assertEquals(fdt.TYPE_BYTE, prop.type)
+ self.assertEquals(fdt.Type.BYTE, prop.type)
self.assertEquals(chr(8), prop.value)
prop = node.props['bytearray']
- self.assertEquals(fdt.TYPE_BYTE, prop.type)
+ self.assertEquals(fdt.Type.BYTE, prop.type)
self.assertEquals(list, type(prop.value))
self.assertEquals(str, type(prop.value[0]))
self.assertEquals(3, len(prop.value))
self.assertEquals([chr(1), '#', '4'], prop.value)
prop = node.props['longbytearray']
- self.assertEquals(fdt.TYPE_INT, prop.type)
+ self.assertEquals(fdt.Type.INT, prop.type)
self.assertEquals(0x090a0b0c, fdt_util.GetInt(node, 'longbytearray'))
prop = node.props['stringval']
- self.assertEquals(fdt.TYPE_STRING, prop.type)
+ self.assertEquals(fdt.Type.STRING, prop.type)
self.assertEquals('message2', fdt_util.GetString(node, 'stringval'))
prop = node.props['stringarray']
- self.assertEquals(fdt.TYPE_STRING, prop.type)
+ self.assertEquals(fdt.Type.STRING, prop.type)
self.assertEquals(list, type(prop.value))
self.assertEquals(3, len(prop.value))
self.assertEquals(['another', 'multi-word', 'message'], prop.value)
ConvertName(names, params)
return struct.pack(fmt, *params)
- values = FmapHeader(FMAP_SIGNATURE, 1, 0, 0, image_size,
- tools.FromUnicode(name), len(areas))
+ values = FmapHeader(FMAP_SIGNATURE, 1, 0, 0, image_size, name, len(areas))
blob = _FormatBlob(FMAP_HEADER_FORMAT, FMAP_HEADER_NAMES, values)
for area in areas:
blob += _FormatBlob(FMAP_AREA_FORMAT, FMAP_AREA_NAMES, area)
This supports converting device tree data to C structures definitions and
static data.
+
+See doc/driver-model/of-plat.rst for more informaiton
"""
import collections
from dtoc import fdt
from dtoc import fdt_util
-from patman import tools
-# When we see these properties we ignore them - i.e. do not create a structure member
+# When we see these properties we ignore them - i.e. do not create a structure
+# member
PROP_IGNORE_LIST = [
'#address-cells',
'#gpio-cells',
'u-boot,dm-spl',
]
-# C type declarations for the tyues we support
+# C type declarations for the types we support
TYPE_NAMES = {
- fdt.TYPE_INT: 'fdt32_t',
- fdt.TYPE_BYTE: 'unsigned char',
- fdt.TYPE_STRING: 'const char *',
- fdt.TYPE_BOOL: 'bool',
- fdt.TYPE_INT64: 'fdt64_t',
+ fdt.Type.INT: 'fdt32_t',
+ fdt.Type.BYTE: 'unsigned char',
+ fdt.Type.STRING: 'const char *',
+ fdt.Type.BOOL: 'bool',
+ fdt.Type.INT64: 'fdt64_t',
}
STRUCT_PREFIX = 'dtd_'
(400ms for 1m calls versus 1000ms for the 're' version).
Args:
- name: Name to convert
+ name (str): Name to convert
Return:
- String containing the C version of this name
+ str: String containing the C version of this name
"""
new = name.replace('@', '_at_')
new = new.replace('-', '_')
"""Append tabs to a line of text to reach a tab stop.
Args:
- num_tabs: Tab stop to obtain (0 = column 0, 1 = column 8, etc.)
- line: Line of text to append to
+ num_tabs (int): Tab stop to obtain (0 = column 0, 1 = column 8, etc.)
+ line (str): Line of text to append to
Returns:
- line with the correct number of tabs appeneded. If the line already
+ str: line with the correct number of tabs appeneded. If the line already
extends past that tab stop then a single space is appended.
"""
if len(line) >= num_tabs * 8:
For booleans this return 'true'
Args:
- type: Data type (fdt_util)
- value: Data value, as a string of bytes
+ ftype (fdt.Type): Data type (fdt_util)
+ value (bytes): Data value, as a string of bytes
+
+ Returns:
+ str: String representation of the value
"""
- if ftype == fdt.TYPE_INT:
+ if ftype == fdt.Type.INT:
return '%#x' % fdt_util.fdt32_to_cpu(value)
- elif ftype == fdt.TYPE_BYTE:
- return '%#x' % tools.ToByte(value[0])
- elif ftype == fdt.TYPE_STRING:
+ elif ftype == fdt.Type.BYTE:
+ char = value[0]
+ return '%#x' % (ord(char) if isinstance(char, str) else char)
+ elif ftype == fdt.Type.STRING:
# Handle evil ACPI backslashes by adding another backslash before them.
# So "\\_SB.GPO0" in the device tree effectively stays like that in C
return '"%s"' % value.replace('\\', '\\\\')
- elif ftype == fdt.TYPE_BOOL:
+ elif ftype == fdt.Type.BOOL:
return 'true'
- elif ftype == fdt.TYPE_INT64:
+ else: # ftype == fdt.Type.INT64:
return '%#x' % value
def get_compat_name(node):
"""Get the node's list of compatible string as a C identifiers
Args:
- node: Node object to check
+ node (fdt.Node): Node object to check
Return:
List of C identifiers for all the compatible strings
"""
_drivers_additional: List of additional drivers to use during scanning
"""
def __init__(self, dtb_fname, include_disabled, warning_disabled,
- drivers_additional=[]):
+ drivers_additional=None):
self._fdt = None
self._dtb_fname = dtb_fname
self._valid_nodes = None
self._lines = []
self._drivers = []
self._driver_aliases = {}
- self._drivers_additional = drivers_additional
+ self._drivers_additional = drivers_additional or []
def get_normalized_compat_name(self, node):
"""Get a node's normalized compat name
file.
Args:
- fname: Filename to send output to, or '-' for stdout
+ fname (str): Filename to send output to, or '-' for stdout
"""
if fname == '-':
self._outfile = sys.stdout
"""Output a string to the output file
Args:
- line: String to output
+ line (str): String to output
"""
self._outfile.write(line)
"""Buffer up a string to send later
Args:
- line: String to add to our 'buffer' list
+ line (str): String to add to our 'buffer' list
"""
self._lines.append(line)
"""Get the contents of the output buffer, and clear it
Returns:
- The output buffer, which is then cleared for future use
+ list(str): The output buffer, which is then cleared for future use
"""
lines = self._lines
self._lines = []
or not. As an interim measure, use a list of known property names.
Args:
- prop: Prop object to check
- Return:
- Number of argument cells is this is a phandle, else None
+ prop (fdt.Prop): Prop object to check
+ node_name (str): Node name, only used for raising an error
+ Returns:
+ int or None: Number of argument cells is this is a phandle,
+ else None
+ Raises:
+ ValueError: if the phandle cannot be parsed or the required property
+ is not present
"""
if prop.name in ['clocks', 'cd-gpios']:
if not isinstance(prop.value, list):
break
if not cells:
raise ValueError("Node '%s' has no cells property" %
- (target.name))
+ (target.name))
num_args = fdt_util.fdt32_to_cpu(cells.value)
max_args = max(max_args, num_args)
args.append(num_args)
return PhandleInfo(max_args, args)
return None
- def scan_driver(self, fn):
+ def scan_driver(self, fname):
"""Scan a driver file to build a list of driver names and aliases
This procedure will populate self._drivers and self._driver_aliases
Args
- fn: Driver filename to scan
+ fname: Driver filename to scan
"""
- with open(fn, encoding='utf-8') as fd:
+ with open(fname, encoding='utf-8') as inf:
try:
- buff = fd.read()
+ buff = inf.read()
except UnicodeDecodeError:
# This seems to happen on older Python versions
- print("Skipping file '%s' due to unicode error" % fn)
+ print("Skipping file '%s' due to unicode error" % fname)
return
# The following re will search for driver names declared as
# The following re will search for driver aliases declared as
# U_BOOT_DRIVER_ALIAS(alias, driver_name)
- driver_aliases = re.findall('U_BOOT_DRIVER_ALIAS\(\s*(\w+)\s*,\s*(\w+)\s*\)',
- buff)
+ driver_aliases = re.findall(
+ 'U_BOOT_DRIVER_ALIAS\(\s*(\w+)\s*,\s*(\w+)\s*\)',
+ buff)
for alias in driver_aliases: # pragma: no cover
if len(alias) != 2:
basedir = sys.argv[0].replace('tools/dtoc/dtoc', '')
if basedir == '':
basedir = './'
- for (dirpath, dirnames, filenames) in os.walk(basedir):
- for fn in filenames:
- if not fn.endswith('.c'):
+ for (dirpath, _, filenames) in os.walk(basedir):
+ for fname in filenames:
+ if not fname.endswith('.c'):
continue
- self.scan_driver(dirpath + '/' + fn)
+ self.scan_driver(dirpath + '/' + fname)
- for fn in self._drivers_additional:
- if not isinstance(fn, str) or len(fn) == 0:
+ for fname in self._drivers_additional:
+ if not isinstance(fname, str) or len(fname) == 0:
continue
- if fn[0] == '/':
- self.scan_driver(fn)
+ if fname[0] == '/':
+ self.scan_driver(fname)
else:
- self.scan_driver(basedir + '/' + fn)
+ self.scan_driver(basedir + '/' + fname)
def scan_dtb(self):
"""Scan the device tree to obtain a tree of nodes and properties
"""Get the number of cells in addresses and sizes for this node
Args:
- node: Node to check
+ node (fdt.None): Node to check
Returns:
Tuple:
Number of size cells for this node
"""
parent = node.parent
- na, ns = 2, 2
+ num_addr, num_size = 2, 2
if parent:
- na_prop = parent.props.get('#address-cells')
- ns_prop = parent.props.get('#size-cells')
- if na_prop:
- na = fdt_util.fdt32_to_cpu(na_prop.value)
- if ns_prop:
- ns = fdt_util.fdt32_to_cpu(ns_prop.value)
- return na, ns
+ addr_prop = parent.props.get('#address-cells')
+ size_prop = parent.props.get('#size-cells')
+ if addr_prop:
+ num_addr = fdt_util.fdt32_to_cpu(addr_prop.value)
+ if size_prop:
+ num_size = fdt_util.fdt32_to_cpu(size_prop.value)
+ return num_addr, num_size
def scan_reg_sizes(self):
"""Scan for 64-bit 'reg' properties and update the values
reg = node.props.get('reg')
if not reg:
continue
- na, ns = self.get_num_cells(node)
- total = na + ns
+ num_addr, num_size = self.get_num_cells(node)
+ total = num_addr + num_size
- if reg.type != fdt.TYPE_INT:
+ if reg.type != fdt.Type.INT:
raise ValueError("Node '%s' reg property is not an int" %
node.name)
if len(reg.value) % total:
- raise ValueError("Node '%s' reg property has %d cells "
- 'which is not a multiple of na + ns = %d + %d)' %
- (node.name, len(reg.value), na, ns))
- reg.na = na
- reg.ns = ns
- if na != 1 or ns != 1:
- reg.type = fdt.TYPE_INT64
+ raise ValueError(
+ "Node '%s' reg property has %d cells "
+ 'which is not a multiple of na + ns = %d + %d)' %
+ (node.name, len(reg.value), num_addr, num_size))
+ reg.num_addr = num_addr
+ reg.num_size = num_size
+ if num_addr != 1 or num_size != 1:
+ reg.type = fdt.Type.INT64
i = 0
new_value = []
val = reg.value
if not isinstance(val, list):
val = [val]
while i < len(val):
- addr = fdt_util.fdt_cells_to_cpu(val[i:], reg.na)
- i += na
- size = fdt_util.fdt_cells_to_cpu(val[i:], reg.ns)
- i += ns
+ addr = fdt_util.fdt_cells_to_cpu(val[i:], reg.num_addr)
+ i += num_addr
+ size = fdt_util.fdt_cells_to_cpu(val[i:], reg.num_size)
+ i += num_size
new_value += [addr, size]
reg.value = new_value
else:
structs[node_name] = fields
- upto = 0
for node in self._valid_nodes:
node_name, _ = self.get_normalized_compat_name(node)
struct = structs[node_name]
for name, prop in node.props.items():
if name not in PROP_IGNORE_LIST and name[0] != '#':
prop.Widen(struct[name])
- upto += 1
return structs
"""Output the C code for a node
Args:
- node: node to output
+ node (fdt.Node): node to output
"""
def _output_list(node, prop):
"""Output the C code for a devicetree property that holds a list
if info:
# Process the list as pairs of (phandle, id)
pos = 0
- item = 0
for args in info.args:
phandle_cell = prop.value[pos]
phandle = fdt_util.fdt32_to_cpu(phandle_cell)
target_node = self._fdt.phandle_to_node[phandle]
- name = conv_name_to_c(target_node.name)
arg_values = []
for i in range(args):
arg_values.append(
pos += 1 + args
vals.append('\t{%d, {%s}}' % (target_node.idx,
', '.join(arg_values)))
- item += 1
for val in vals:
self.buf('\n\t\t%s,' % val)
else:
# Add a device declaration
self.buf('U_BOOT_DEVICE(%s) = {\n' % var_name)
self.buf('\t.name\t\t= "%s",\n' % struct_name)
- self.buf('\t.platdata\t= &%s%s,\n' % (VAL_PREFIX, var_name))
- self.buf('\t.platdata_size\t= sizeof(%s%s),\n' % (VAL_PREFIX, var_name))
+ self.buf('\t.plat\t= &%s%s,\n' % (VAL_PREFIX, var_name))
+ self.buf('\t.plat_size\t= sizeof(%s%s),\n' % (VAL_PREFIX, var_name))
idx = -1
if node.parent and node.parent in self._valid_nodes:
idx = node.parent.idx
self.out(''.join(self.get_buf()))
def run_steps(args, dtb_file, include_disabled, output, warning_disabled=False,
- drivers_additional=[]):
+ drivers_additional=None):
"""Run all the steps of the dtoc tool
Args:
- args: List of non-option arguments provided to the problem
- dtb_file: Filename of dtb file to process
- include_disabled: True to include disabled nodes
- output: Name of output file
+ args (list): List of non-option arguments provided to the problem
+ dtb_file (str): Filename of dtb file to process
+ include_disabled (bool): True to include disabled nodes
+ output (str): Name of output file
+ warning_disabled (bool): True to avoid showing warnings about missing
+ drivers
+ _drivers_additional (list): List of additional drivers to use during
+ scanning
+ Raises:
+ ValueError: if args has no command, or an unknown command
"""
if not args:
raise ValueError('Please specify a command: struct, platdata')
- plat = DtbPlatdata(dtb_file, include_disabled, warning_disabled, drivers_additional)
+ plat = DtbPlatdata(dtb_file, include_disabled, warning_disabled,
+ drivers_additional)
plat.scan_drivers()
plat.scan_dtb()
plat.scan_tree()
#
+from enum import IntEnum
import struct
import sys
# so it is fairly efficient.
# A list of types we support
-(TYPE_BYTE, TYPE_INT, TYPE_STRING, TYPE_BOOL, TYPE_INT64) = range(5)
+class Type(IntEnum):
+ (BYTE, INT, STRING, BOOL, INT64) = range(5)
+
+ def is_wider_than(self, other):
+ """Check if another type is 'wider' than this one
+
+ A wider type is one that holds more information than an earlier one,
+ similar to the concept of type-widening in C.
+
+ This uses a simple arithmetic comparison, since type values are in order
+ from narrowest (BYTE) to widest (INT64).
+
+ Args:
+ other: Other type to compare against
+
+ Return:
+ True if the other type is wider
+ """
+ return self.value > other.value
def CheckErr(errnum, msg):
if errnum:
Type of data
Data, either a single element or a list of elements. Each element
is one of:
- TYPE_STRING: str/bytes value from the property
- TYPE_INT: a byte-swapped integer stored as a 4-byte str/bytes
- TYPE_BYTE: a byte stored as a single-byte str/bytes
+ Type.STRING: str/bytes value from the property
+ Type.INT: a byte-swapped integer stored as a 4-byte str/bytes
+ Type.BYTE: a byte stored as a single-byte str/bytes
"""
data = bytes(data)
size = len(data)
is_string = False
if is_string:
if count == 1:
- return TYPE_STRING, strings[0].decode()
+ return Type.STRING, strings[0].decode()
else:
- return TYPE_STRING, [s.decode() for s in strings[:-1]]
+ return Type.STRING, [s.decode() for s in strings[:-1]]
if size % 4:
if size == 1:
- return TYPE_BYTE, tools.ToChar(data[0])
+ return Type.BYTE, chr(data[0])
else:
- return TYPE_BYTE, [tools.ToChar(ch) for ch in list(data)]
+ return Type.BYTE, [chr(ch) for ch in list(data)]
val = []
for i in range(0, size, 4):
val.append(data[i:i + 4])
if size == 4:
- return TYPE_INT, val[0]
+ return Type.INT, val[0]
else:
- return TYPE_INT, val
+ return Type.INT, val
class Prop:
self.bytes = bytes(data)
self.dirty = False
if not data:
- self.type = TYPE_BOOL
+ self.type = Type.BOOL
self.value = True
return
self.type, self.value = BytesToValue(bytes(data))
update the current property to be like the second, since it is less
specific.
"""
- if newprop.type < self.type:
- # Special handling to convert an int into bytes
- if self.type == TYPE_INT and newprop.type == TYPE_BYTE:
+ if self.type.is_wider_than(newprop.type):
+ if self.type == Type.INT and newprop.type == Type.BYTE:
if type(self.value) == list:
new_value = []
for val in self.value:
- new_value += [tools.ToChar(by) for by in val]
+ new_value += [chr(by) for by in val]
else:
- new_value = [tools.ToChar(by) for by in self.value]
+ new_value = [chr(by) for by in self.value]
self.value = new_value
self.type = newprop.type
Returns:
A single value of the given type
"""
- if type == TYPE_BYTE:
+ if type == Type.BYTE:
return chr(0)
- elif type == TYPE_INT:
+ elif type == Type.INT:
return struct.pack('>I', 0);
- elif type == TYPE_STRING:
+ elif type == Type.STRING:
return ''
else:
return True
"""
self.bytes = struct.pack('>I', val);
self.value = self.bytes
- self.type = TYPE_INT
+ self.type = Type.INT
self.dirty = True
def SetData(self, bytes):
def test_get_value(self):
"""Test operation of get_value() function"""
self.assertEqual('0x45',
- get_value(fdt.TYPE_INT, struct.pack('>I', 0x45)))
+ get_value(fdt.Type.INT, struct.pack('>I', 0x45)))
self.assertEqual('0x45',
- get_value(fdt.TYPE_BYTE, struct.pack('<I', 0x45)))
+ get_value(fdt.Type.BYTE, struct.pack('<I', 0x45)))
self.assertEqual('0x0',
- get_value(fdt.TYPE_BYTE, struct.pack('>I', 0x45)))
- self.assertEqual('"test"', get_value(fdt.TYPE_STRING, 'test'))
- self.assertEqual('true', get_value(fdt.TYPE_BOOL, None))
+ get_value(fdt.Type.BYTE, struct.pack('>I', 0x45)))
+ self.assertEqual('"test"', get_value(fdt.Type.STRING, 'test'))
+ self.assertEqual('true', get_value(fdt.Type.BOOL, None))
def test_get_compat_name(self):
"""Test operation of get_compat_name() function"""
};
U_BOOT_DEVICE(i2c_at_0) = {
\t.name\t\t= "sandbox_i2c_test",
-\t.platdata\t= &dtv_i2c_at_0,
-\t.platdata_size\t= sizeof(dtv_i2c_at_0),
+\t.plat\t= &dtv_i2c_at_0,
+\t.plat_size\t= sizeof(dtv_i2c_at_0),
\t.parent_idx\t= -1,
};
};
U_BOOT_DEVICE(pmic_at_9) = {
\t.name\t\t= "sandbox_pmic_test",
-\t.platdata\t= &dtv_pmic_at_9,
-\t.platdata_size\t= sizeof(dtv_pmic_at_9),
+\t.plat\t= &dtv_pmic_at_9,
+\t.plat_size\t= sizeof(dtv_pmic_at_9),
\t.parent_idx\t= 0,
};
};
U_BOOT_DEVICE(spl_test) = {
\t.name\t\t= "sandbox_spl_test",
-\t.platdata\t= &dtv_spl_test,
-\t.platdata_size\t= sizeof(dtv_spl_test),
+\t.plat\t= &dtv_spl_test,
+\t.plat_size\t= sizeof(dtv_spl_test),
\t.parent_idx\t= -1,
};
};
U_BOOT_DEVICE(spl_test2) = {
\t.name\t\t= "sandbox_spl_test",
-\t.platdata\t= &dtv_spl_test2,
-\t.platdata_size\t= sizeof(dtv_spl_test2),
+\t.plat\t= &dtv_spl_test2,
+\t.plat_size\t= sizeof(dtv_spl_test2),
\t.parent_idx\t= -1,
};
};
U_BOOT_DEVICE(spl_test3) = {
\t.name\t\t= "sandbox_spl_test",
-\t.platdata\t= &dtv_spl_test3,
-\t.platdata_size\t= sizeof(dtv_spl_test3),
+\t.plat\t= &dtv_spl_test3,
+\t.plat_size\t= sizeof(dtv_spl_test3),
\t.parent_idx\t= -1,
};
};
U_BOOT_DEVICE(spl_test4) = {
\t.name\t\t= "sandbox_spl_test_2",
-\t.platdata\t= &dtv_spl_test4,
-\t.platdata_size\t= sizeof(dtv_spl_test4),
+\t.plat\t= &dtv_spl_test4,
+\t.plat_size\t= sizeof(dtv_spl_test4),
\t.parent_idx\t= -1,
};
};
U_BOOT_DEVICE(gpios_at_0) = {
\t.name\t\t= "sandbox_gpio",
-\t.platdata\t= &dtv_gpios_at_0,
-\t.platdata_size\t= sizeof(dtv_gpios_at_0),
+\t.plat\t= &dtv_gpios_at_0,
+\t.plat_size\t= sizeof(dtv_gpios_at_0),
\t.parent_idx\t= -1,
};
};
U_BOOT_DEVICE(spl_test) = {
\t.name\t\t= "invalid",
-\t.platdata\t= &dtv_spl_test,
-\t.platdata_size\t= sizeof(dtv_spl_test),
+\t.plat\t= &dtv_spl_test,
+\t.plat_size\t= sizeof(dtv_spl_test),
\t.parent_idx\t= -1,
};
};
U_BOOT_DEVICE(phandle2_target) = {
\t.name\t\t= "target",
-\t.platdata\t= &dtv_phandle2_target,
-\t.platdata_size\t= sizeof(dtv_phandle2_target),
+\t.plat\t= &dtv_phandle2_target,
+\t.plat_size\t= sizeof(dtv_phandle2_target),
\t.parent_idx\t= -1,
};
};
U_BOOT_DEVICE(phandle3_target) = {
\t.name\t\t= "target",
-\t.platdata\t= &dtv_phandle3_target,
-\t.platdata_size\t= sizeof(dtv_phandle3_target),
+\t.plat\t= &dtv_phandle3_target,
+\t.plat_size\t= sizeof(dtv_phandle3_target),
\t.parent_idx\t= -1,
};
};
U_BOOT_DEVICE(phandle_target) = {
\t.name\t\t= "target",
-\t.platdata\t= &dtv_phandle_target,
-\t.platdata_size\t= sizeof(dtv_phandle_target),
+\t.plat\t= &dtv_phandle_target,
+\t.plat_size\t= sizeof(dtv_phandle_target),
\t.parent_idx\t= -1,
};
};
U_BOOT_DEVICE(phandle_source) = {
\t.name\t\t= "source",
-\t.platdata\t= &dtv_phandle_source,
-\t.platdata_size\t= sizeof(dtv_phandle_source),
+\t.plat\t= &dtv_phandle_source,
+\t.plat_size\t= sizeof(dtv_phandle_source),
\t.parent_idx\t= -1,
};
};
U_BOOT_DEVICE(phandle_source2) = {
\t.name\t\t= "source",
-\t.platdata\t= &dtv_phandle_source2,
-\t.platdata_size\t= sizeof(dtv_phandle_source2),
+\t.plat\t= &dtv_phandle_source2,
+\t.plat_size\t= sizeof(dtv_phandle_source2),
\t.parent_idx\t= -1,
};
};
U_BOOT_DEVICE(phandle_target) = {
\t.name\t\t= "target",
-\t.platdata\t= &dtv_phandle_target,
-\t.platdata_size\t= sizeof(dtv_phandle_target),
+\t.plat\t= &dtv_phandle_target,
+\t.plat_size\t= sizeof(dtv_phandle_target),
\t.parent_idx\t= -1,
};
};
U_BOOT_DEVICE(phandle_source2) = {
\t.name\t\t= "source",
-\t.platdata\t= &dtv_phandle_source2,
-\t.platdata_size\t= sizeof(dtv_phandle_source2),
+\t.plat\t= &dtv_phandle_source2,
+\t.plat_size\t= sizeof(dtv_phandle_source2),
\t.parent_idx\t= -1,
};
};
U_BOOT_DEVICE(phandle2_target) = {
\t.name\t\t= "target",
-\t.platdata\t= &dtv_phandle2_target,
-\t.platdata_size\t= sizeof(dtv_phandle2_target),
+\t.plat\t= &dtv_phandle2_target,
+\t.plat_size\t= sizeof(dtv_phandle2_target),
\t.parent_idx\t= -1,
};
};
U_BOOT_DEVICE(phandle3_target) = {
\t.name\t\t= "target",
-\t.platdata\t= &dtv_phandle3_target,
-\t.platdata_size\t= sizeof(dtv_phandle3_target),
+\t.plat\t= &dtv_phandle3_target,
+\t.plat_size\t= sizeof(dtv_phandle3_target),
\t.parent_idx\t= -1,
};
};
U_BOOT_DEVICE(phandle_target) = {
\t.name\t\t= "target",
-\t.platdata\t= &dtv_phandle_target,
-\t.platdata_size\t= sizeof(dtv_phandle_target),
+\t.plat\t= &dtv_phandle_target,
+\t.plat_size\t= sizeof(dtv_phandle_target),
\t.parent_idx\t= -1,
};
};
U_BOOT_DEVICE(phandle_source) = {
\t.name\t\t= "source",
-\t.platdata\t= &dtv_phandle_source,
-\t.platdata_size\t= sizeof(dtv_phandle_source),
+\t.plat\t= &dtv_phandle_source,
+\t.plat_size\t= sizeof(dtv_phandle_source),
\t.parent_idx\t= -1,
};
};
U_BOOT_DEVICE(phandle_source2) = {
\t.name\t\t= "source",
-\t.platdata\t= &dtv_phandle_source2,
-\t.platdata_size\t= sizeof(dtv_phandle_source2),
+\t.plat\t= &dtv_phandle_source2,
+\t.plat_size\t= sizeof(dtv_phandle_source2),
\t.parent_idx\t= -1,
};
};
U_BOOT_DEVICE(test1) = {
\t.name\t\t= "test1",
-\t.platdata\t= &dtv_test1,
-\t.platdata_size\t= sizeof(dtv_test1),
+\t.plat\t= &dtv_test1,
+\t.plat_size\t= sizeof(dtv_test1),
\t.parent_idx\t= -1,
};
};
U_BOOT_DEVICE(test2) = {
\t.name\t\t= "test2",
-\t.platdata\t= &dtv_test2,
-\t.platdata_size\t= sizeof(dtv_test2),
+\t.plat\t= &dtv_test2,
+\t.plat_size\t= sizeof(dtv_test2),
\t.parent_idx\t= -1,
};
};
U_BOOT_DEVICE(test3) = {
\t.name\t\t= "test3",
-\t.platdata\t= &dtv_test3,
-\t.platdata_size\t= sizeof(dtv_test3),
+\t.plat\t= &dtv_test3,
+\t.plat_size\t= sizeof(dtv_test3),
\t.parent_idx\t= -1,
};
};
U_BOOT_DEVICE(test1) = {
\t.name\t\t= "test1",
-\t.platdata\t= &dtv_test1,
-\t.platdata_size\t= sizeof(dtv_test1),
+\t.plat\t= &dtv_test1,
+\t.plat_size\t= sizeof(dtv_test1),
\t.parent_idx\t= -1,
};
};
U_BOOT_DEVICE(test2) = {
\t.name\t\t= "test2",
-\t.platdata\t= &dtv_test2,
-\t.platdata_size\t= sizeof(dtv_test2),
+\t.plat\t= &dtv_test2,
+\t.plat_size\t= sizeof(dtv_test2),
\t.parent_idx\t= -1,
};
};
U_BOOT_DEVICE(test1) = {
\t.name\t\t= "test1",
-\t.platdata\t= &dtv_test1,
-\t.platdata_size\t= sizeof(dtv_test1),
+\t.plat\t= &dtv_test1,
+\t.plat_size\t= sizeof(dtv_test1),
\t.parent_idx\t= -1,
};
};
U_BOOT_DEVICE(test2) = {
\t.name\t\t= "test2",
-\t.platdata\t= &dtv_test2,
-\t.platdata_size\t= sizeof(dtv_test2),
+\t.plat\t= &dtv_test2,
+\t.plat_size\t= sizeof(dtv_test2),
\t.parent_idx\t= -1,
};
};
U_BOOT_DEVICE(test3) = {
\t.name\t\t= "test3",
-\t.platdata\t= &dtv_test3,
-\t.platdata_size\t= sizeof(dtv_test3),
+\t.plat\t= &dtv_test3,
+\t.plat_size\t= sizeof(dtv_test3),
\t.parent_idx\t= -1,
};
};
U_BOOT_DEVICE(test1) = {
\t.name\t\t= "test1",
-\t.platdata\t= &dtv_test1,
-\t.platdata_size\t= sizeof(dtv_test1),
+\t.plat\t= &dtv_test1,
+\t.plat_size\t= sizeof(dtv_test1),
\t.parent_idx\t= -1,
};
};
U_BOOT_DEVICE(test2) = {
\t.name\t\t= "test2",
-\t.platdata\t= &dtv_test2,
-\t.platdata_size\t= sizeof(dtv_test2),
+\t.plat\t= &dtv_test2,
+\t.plat_size\t= sizeof(dtv_test2),
\t.parent_idx\t= -1,
};
};
U_BOOT_DEVICE(test3) = {
\t.name\t\t= "test3",
-\t.platdata\t= &dtv_test3,
-\t.platdata_size\t= sizeof(dtv_test3),
+\t.plat\t= &dtv_test3,
+\t.plat_size\t= sizeof(dtv_test3),
\t.parent_idx\t= -1,
};
};
U_BOOT_DEVICE(spl_test) = {
\t.name\t\t= "sandbox_spl_test",
-\t.platdata\t= &dtv_spl_test,
-\t.platdata_size\t= sizeof(dtv_spl_test),
+\t.plat\t= &dtv_spl_test,
+\t.plat_size\t= sizeof(dtv_spl_test),
\t.parent_idx\t= -1,
};
};
U_BOOT_DEVICE(spl_test2) = {
\t.name\t\t= "sandbox_spl_test",
-\t.platdata\t= &dtv_spl_test2,
-\t.platdata_size\t= sizeof(dtv_spl_test2),
+\t.plat\t= &dtv_spl_test2,
+\t.plat_size\t= sizeof(dtv_spl_test2),
\t.parent_idx\t= -1,
};
from dtoc import fdt
from dtoc import fdt_util
from dtoc.fdt_util import fdt32_to_cpu
-from fdt import TYPE_BYTE, TYPE_INT, TYPE_STRING, TYPE_BOOL, BytesToValue
+from fdt import Type, BytesToValue
import libfdt
from patman import command
from patman import test_util
# Add 12, which is sizeof(struct fdt_property), to get to start of data
offset = prop.GetOffset() + 12
data = dtb.GetContents()[offset:offset + len(prop.value)]
- return prop, [tools.ToChar(x) for x in data]
+ return prop, [chr(x) for x in data]
class TestFdt(unittest.TestCase):
def testBytesToValue(self):
self.assertEqual(BytesToValue(b'this\0is\0'),
- (TYPE_STRING, ['this', 'is']))
+ (Type.STRING, ['this', 'is']))
class TestNode(unittest.TestCase):
"""Test operation of the Node class"""
def testMakeProp(self):
"""Test we can convert all the the types that are supported"""
prop = self._ConvertProp('boolval')
- self.assertEqual(fdt.TYPE_BOOL, prop.type)
+ self.assertEqual(Type.BOOL, prop.type)
self.assertEqual(True, prop.value)
prop = self._ConvertProp('intval')
- self.assertEqual(fdt.TYPE_INT, prop.type)
+ self.assertEqual(Type.INT, prop.type)
self.assertEqual(1, fdt32_to_cpu(prop.value))
prop = self._ConvertProp('intarray')
- self.assertEqual(fdt.TYPE_INT, prop.type)
+ self.assertEqual(Type.INT, prop.type)
val = [fdt32_to_cpu(val) for val in prop.value]
self.assertEqual([2, 3, 4], val)
prop = self._ConvertProp('byteval')
- self.assertEqual(fdt.TYPE_BYTE, prop.type)
+ self.assertEqual(Type.BYTE, prop.type)
self.assertEqual(5, ord(prop.value))
prop = self._ConvertProp('longbytearray')
- self.assertEqual(fdt.TYPE_BYTE, prop.type)
+ self.assertEqual(Type.BYTE, prop.type)
val = [ord(val) for val in prop.value]
self.assertEqual([9, 10, 11, 12, 13, 14, 15, 16, 17], val)
prop = self._ConvertProp('stringval')
- self.assertEqual(fdt.TYPE_STRING, prop.type)
+ self.assertEqual(Type.STRING, prop.type)
self.assertEqual('message', prop.value)
prop = self._ConvertProp('stringarray')
- self.assertEqual(fdt.TYPE_STRING, prop.type)
+ self.assertEqual(Type.STRING, prop.type)
self.assertEqual(['multi-word', 'message'], prop.value)
prop = self._ConvertProp('notstring')
- self.assertEqual(fdt.TYPE_BYTE, prop.type)
+ self.assertEqual(Type.BYTE, prop.type)
val = [ord(val) for val in prop.value]
self.assertEqual([0x20, 0x21, 0x22, 0x10, 0], val)
def testGetEmpty(self):
"""Tests the GetEmpty() function for the various supported types"""
- self.assertEqual(True, fdt.Prop.GetEmpty(fdt.TYPE_BOOL))
- self.assertEqual(chr(0), fdt.Prop.GetEmpty(fdt.TYPE_BYTE))
- self.assertEqual(tools.GetBytes(0, 4), fdt.Prop.GetEmpty(fdt.TYPE_INT))
- self.assertEqual('', fdt.Prop.GetEmpty(fdt.TYPE_STRING))
+ self.assertEqual(True, fdt.Prop.GetEmpty(Type.BOOL))
+ self.assertEqual(chr(0), fdt.Prop.GetEmpty(Type.BYTE))
+ self.assertEqual(tools.GetBytes(0, 4), fdt.Prop.GetEmpty(Type.INT))
+ self.assertEqual('', fdt.Prop.GetEmpty(Type.STRING))
def testGetOffset(self):
"""Test we can get the offset of a property"""
# No action
prop2 = node2.props['intval']
prop.Widen(prop2)
- self.assertEqual(fdt.TYPE_INT, prop.type)
+ self.assertEqual(Type.INT, prop.type)
self.assertEqual(1, fdt32_to_cpu(prop.value))
# Convert singla value to array
prop2 = self.node.props['intarray']
prop.Widen(prop2)
- self.assertEqual(fdt.TYPE_INT, prop.type)
+ self.assertEqual(Type.INT, prop.type)
self.assertTrue(isinstance(prop.value, list))
# A 4-byte array looks like a single integer. When widened by a longer
if 'Cc:' not in prev:
break
- self.assertEqual('Cc: %s' % tools.FromUnicode(stefan), next(lines))
+ self.assertEqual('Cc: %s' % stefan, next(lines))
self.assertEqual('Version: 3', next(lines))
self.assertEqual('Prefix:\t RFC', next(lines))
self.assertEqual('Cover: 4 lines', next(lines))
self.assertEqual(' Cc: %s' % self.fred, next(lines))
- self.assertEqual(' Cc: %s' % tools.FromUnicode(self.leb),
+ self.assertEqual(' Cc: %s' % self.leb,
next(lines))
- self.assertEqual(' Cc: %s' % tools.FromUnicode(mel), next(lines))
+ self.assertEqual(' Cc: %s' % mel, next(lines))
self.assertEqual(' Cc: %s' % rick, next(lines))
expected = ('Git command: git send-email --annotate '
'--cc "%s" --cc-cmd "%s send --cc-cmd %s" %s %s'
% (in_reply_to, stefan, sys.argv[0], cc_file, cover_fname,
' '.join(args)))
- self.assertEqual(expected, tools.ToUnicode(next(lines)))
+ self.assertEqual(expected, next(lines))
- self.assertEqual(('%s %s\0%s' % (args[0], rick, stefan)),
- tools.ToUnicode(cc_lines[0]))
+ self.assertEqual(('%s %s\0%s' % (args[0], rick, stefan)), cc_lines[0])
self.assertEqual(
'%s %s\0%s\0%s\0%s' % (args[1], self.fred, self.leb, rick, stefan),
- tools.ToUnicode(cc_lines[1]))
+ cc_lines[1])
expected = '''
This is a test of how the cover
raw += LookupEmail(item, alias, raise_on_error=raise_on_error)
result = []
for item in raw:
- item = tools.FromUnicode(item)
if not item in result:
result.append(item)
if tag:
if smtp_server:
cmd.append('--smtp-server=%s' % smtp_server)
if in_reply_to:
- cmd.append('--in-reply-to="%s"' % tools.FromUnicode(in_reply_to))
+ cmd.append('--in-reply-to="%s"' % in_reply_to)
if thread:
cmd.append('--thread')
for x in set(cc) & set(settings.bounces):
print(col.Color(col.YELLOW, 'Skipping "%s"' % x))
cc = set(cc) - set(settings.bounces)
- cc = [tools.FromUnicode(m) for m in cc]
if limit is not None:
cc = cc[:limit]
all_ccs += cc
if cover_fname:
cover_cc = gitutil.BuildEmailList(self.get('cover_cc', ''))
- cover_cc = [tools.FromUnicode(m) for m in cover_cc]
cover_cc = list(set(cover_cc + all_ccs))
if limit is not None:
cover_cc = cover_cc[:limit]
- cc_list = '\0'.join([tools.ToUnicode(x) for x in sorted(cover_cc)])
+ cc_list = '\0'.join([x for x in sorted(cover_cc)])
print(cover_fname, cc_list, file=fd)
fd.close()
val = ConfigParser.SafeConfigParser.get(
self, section, option, *args, **kwargs
)
- return tools.ToUnicode(val)
+ return val
def items(self, section, *args, **kwargs):
"""Extend SafeConfigParser to add project_section to section.
item_dict = dict(top_items)
item_dict.update(project_items)
- return {(tools.ToUnicode(item), tools.ToUnicode(val))
- for item, val in item_dict.items()}
+ return {(item, val) for item, val in item_dict.items()}
def ReadGitAliases(fname):
"""Read a git alias file. This is in the form used by git:
pm.add_line('common/main.c', 'if (CONFIG_IS_ENABLED(CONFIG_CLK))')
self.checkSingleMessage(pm, 'CONFIG_IS_ENABLED_CONFIG', 'error')
+ def check_struct(self, auto, suffix, warning):
+ """Check one of the warnings for struct naming
+
+ Args:
+ auto: Auto variable name, e.g. 'per_child_auto'
+ suffix: Suffix to expect on member, e.g. '_priv'
+ warning: Warning name, e.g. 'PRIV_AUTO'
+ """
+ pm = PatchMaker()
+ pm.add_line('common/main.c', '.%s = sizeof(struct(fred)),' % auto)
+ pm.add_line('common/main.c', '.%s = sizeof(struct(mary%s)),' %
+ (auto, suffix))
+ self.checkSingleMessage(
+ pm, warning, "struct 'fred' should have a %s suffix" % suffix)
+
+ def testDmDriverAuto(self):
+ """Check for the correct suffix on 'struct driver' auto members"""
+ self.check_struct('priv_auto', '_priv', 'PRIV_AUTO')
+ self.check_struct('plat_auto', '_plat', 'PLAT_AUTO')
+ self.check_struct('per_child_auto', '_priv', 'CHILD_PRIV_AUTO')
+ self.check_struct('per_child_plat_auto', '_plat', 'CHILD_PLAT_AUTO')
+
+ def testDmUclassAuto(self):
+ """Check for the correct suffix on 'struct uclass' auto members"""
+ # Some of these are omitted since they match those from struct driver
+ self.check_struct('per_device_auto', '_priv', 'DEVICE_PRIV_AUTO')
+ self.check_struct('per_device_plat_auto', '_plat', 'DEVICE_PLAT_AUTO')
+
if __name__ == "__main__":
unittest.main()
def GetBytes(byte, size):
"""Get a string of bytes of a given size
- This handles the unfortunate different between Python 2 and Python 2.
-
Args:
byte: Numeric byte value to use
size: Size of bytes/string to return
Returns:
A bytes type with 'byte' repeated 'size' times
"""
- if sys.version_info[0] >= 3:
- data = bytes([byte]) * size
- else:
- data = chr(byte) * size
- return data
-
-def ToUnicode(val):
- """Make sure a value is a unicode string
-
- This allows some amount of compatibility between Python 2 and Python3. For
- the former, it returns a unicode object.
-
- Args:
- val: string or unicode object
-
- Returns:
- unicode version of val
- """
- if sys.version_info[0] >= 3:
- return val
- return val if isinstance(val, unicode) else val.decode('utf-8')
-
-def FromUnicode(val):
- """Make sure a value is a non-unicode string
-
- This allows some amount of compatibility between Python 2 and Python3. For
- the former, it converts a unicode object to a string.
-
- Args:
- val: string or unicode object
-
- Returns:
- non-unicode version of val
- """
- if sys.version_info[0] >= 3:
- return val
- return val if isinstance(val, str) else val.encode('utf-8')
-
-def ToByte(ch):
- """Convert a character to an ASCII value
-
- This is useful because in Python 2 bytes is an alias for str, but in
- Python 3 they are separate types. This function converts the argument to
- an ASCII value in either case.
-
- Args:
- ch: A string (Python 2) or byte (Python 3) value
-
- Returns:
- integer ASCII value for ch
- """
- return ord(ch) if type(ch) == str else ch
-
-def ToChar(byte):
- """Convert a byte to a character
-
- This is useful because in Python 2 bytes is an alias for str, but in
- Python 3 they are separate types. This function converts an ASCII value to
- a value with the appropriate type in either case.
-
- Args:
- byte: A byte or str value
- """
- return chr(byte) if type(byte) != str else byte
-
-def ToChars(byte_list):
- """Convert a list of bytes to a str/bytes type
-
- Args:
- byte_list: List of ASCII values representing the string
-
- Returns:
- string made by concatenating all the ASCII values
- """
- return ''.join([chr(byte) for byte in byte_list])
+ return bytes([byte]) * size
def ToBytes(string):
"""Convert a str type into a bytes type
string: string to convert
Returns:
- Python 3: A bytes type
- Python 2: A string type
+ A bytes type
"""
- if sys.version_info[0] >= 3:
- return string.encode('utf-8')
- return string
+ return string.encode('utf-8')
def ToString(bval):
"""Convert a bytes type into a str type
projects / u-boot.git / commitdiff