[u-boot.git] / drivers / spi / atmel-quadspi.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Driver for Atmel QSPI Controller
 *
 * Copyright (C) 2015 Atmel Corporation
 * Copyright (C) 2018 Cryptera A/S
 *
 * Author: Cyrille Pitchen <[email protected]>
 * Author: Piotr Bugalski <[email protected]>
 */

#include <malloc.h>
#include <asm/io.h>
#include <clk.h>
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <fdtdec.h>
#include <dm/device_compat.h>
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/ioport.h>
#include <mach/clk.h>
#include <spi.h>
#include <spi-mem.h>

/* QSPI register offsets */
#define QSPI_CR      0x0000  /* Control Register */
#define QSPI_MR      0x0004  /* Mode Register */
#define QSPI_RD      0x0008  /* Receive Data Register */
#define QSPI_TD      0x000c  /* Transmit Data Register */
#define QSPI_SR      0x0010  /* Status Register */
#define QSPI_IER     0x0014  /* Interrupt Enable Register */
#define QSPI_IDR     0x0018  /* Interrupt Disable Register */
#define QSPI_IMR     0x001c  /* Interrupt Mask Register */
#define QSPI_SCR     0x0020  /* Serial Clock Register */

#define QSPI_IAR     0x0030  /* Instruction Address Register */
#define QSPI_ICR     0x0034  /* Instruction Code Register */
#define QSPI_WICR    0x0034  /* Write Instruction Code Register */
#define QSPI_IFR     0x0038  /* Instruction Frame Register */
#define QSPI_RICR    0x003C  /* Read Instruction Code Register */

#define QSPI_SMR     0x0040  /* Scrambling Mode Register */
#define QSPI_SKR     0x0044  /* Scrambling Key Register */

#define QSPI_WPMR    0x00E4  /* Write Protection Mode Register */
#define QSPI_WPSR    0x00E8  /* Write Protection Status Register */

#define QSPI_VERSION 0x00FC  /* Version Register */

/* Bitfields in QSPI_CR (Control Register) */
#define QSPI_CR_QSPIEN                  BIT(0)
#define QSPI_CR_QSPIDIS                 BIT(1)
#define QSPI_CR_SWRST                   BIT(7)
#define QSPI_CR_LASTXFER                BIT(24)

/* Bitfields in QSPI_MR (Mode Register) */
#define QSPI_MR_SMM                     BIT(0)
#define QSPI_MR_LLB                     BIT(1)
#define QSPI_MR_WDRBT                   BIT(2)
#define QSPI_MR_SMRM                    BIT(3)
#define QSPI_MR_CSMODE_MASK             GENMASK(5, 4)
#define QSPI_MR_CSMODE_NOT_RELOADED     (0 << 4)
#define QSPI_MR_CSMODE_LASTXFER         (1 << 4)
#define QSPI_MR_CSMODE_SYSTEMATICALLY   (2 << 4)
#define QSPI_MR_NBBITS_MASK             GENMASK(11, 8)
#define QSPI_MR_NBBITS(n)               ((((n) - 8) << 8) & QSPI_MR_NBBITS_MASK)
#define QSPI_MR_DLYBCT_MASK             GENMASK(23, 16)
#define QSPI_MR_DLYBCT(n)               (((n) << 16) & QSPI_MR_DLYBCT_MASK)
#define QSPI_MR_DLYCS_MASK              GENMASK(31, 24)
#define QSPI_MR_DLYCS(n)                (((n) << 24) & QSPI_MR_DLYCS_MASK)

/* Bitfields in QSPI_SR/QSPI_IER/QSPI_IDR/QSPI_IMR  */
#define QSPI_SR_RDRF                    BIT(0)
#define QSPI_SR_TDRE                    BIT(1)
#define QSPI_SR_TXEMPTY                 BIT(2)
#define QSPI_SR_OVRES                   BIT(3)
#define QSPI_SR_CSR                     BIT(8)
#define QSPI_SR_CSS                     BIT(9)
#define QSPI_SR_INSTRE                  BIT(10)
#define QSPI_SR_QSPIENS                 BIT(24)

#define QSPI_SR_CMD_COMPLETED	(QSPI_SR_INSTRE | QSPI_SR_CSR)

/* Bitfields in QSPI_SCR (Serial Clock Register) */
#define QSPI_SCR_CPOL                   BIT(0)
#define QSPI_SCR_CPHA                   BIT(1)
#define QSPI_SCR_SCBR_MASK              GENMASK(15, 8)
#define QSPI_SCR_SCBR(n)                (((n) << 8) & QSPI_SCR_SCBR_MASK)
#define QSPI_SCR_DLYBS_MASK             GENMASK(23, 16)
#define QSPI_SCR_DLYBS(n)               (((n) << 16) & QSPI_SCR_DLYBS_MASK)

/* Bitfields in QSPI_ICR (Read/Write Instruction Code Register) */
#define QSPI_ICR_INST_MASK              GENMASK(7, 0)
#define QSPI_ICR_INST(inst)             (((inst) << 0) & QSPI_ICR_INST_MASK)
#define QSPI_ICR_OPT_MASK               GENMASK(23, 16)
#define QSPI_ICR_OPT(opt)               (((opt) << 16) & QSPI_ICR_OPT_MASK)

/* Bitfields in QSPI_IFR (Instruction Frame Register) */
#define QSPI_IFR_WIDTH_MASK             GENMASK(2, 0)
#define QSPI_IFR_WIDTH_SINGLE_BIT_SPI   (0 << 0)
#define QSPI_IFR_WIDTH_DUAL_OUTPUT      (1 << 0)
#define QSPI_IFR_WIDTH_QUAD_OUTPUT      (2 << 0)
#define QSPI_IFR_WIDTH_DUAL_IO          (3 << 0)
#define QSPI_IFR_WIDTH_QUAD_IO          (4 << 0)
#define QSPI_IFR_WIDTH_DUAL_CMD         (5 << 0)
#define QSPI_IFR_WIDTH_QUAD_CMD         (6 << 0)
#define QSPI_IFR_INSTEN                 BIT(4)
#define QSPI_IFR_ADDREN                 BIT(5)
#define QSPI_IFR_OPTEN                  BIT(6)
#define QSPI_IFR_DATAEN                 BIT(7)
#define QSPI_IFR_OPTL_MASK              GENMASK(9, 8)
#define QSPI_IFR_OPTL_1BIT              (0 << 8)
#define QSPI_IFR_OPTL_2BIT              (1 << 8)
#define QSPI_IFR_OPTL_4BIT              (2 << 8)
#define QSPI_IFR_OPTL_8BIT              (3 << 8)
#define QSPI_IFR_ADDRL                  BIT(10)
#define QSPI_IFR_TFRTYP_MEM		BIT(12)
#define QSPI_IFR_SAMA5D2_WRITE_TRSFR	BIT(13)
#define QSPI_IFR_CRM                    BIT(14)
#define QSPI_IFR_NBDUM_MASK             GENMASK(20, 16)
#define QSPI_IFR_NBDUM(n)               (((n) << 16) & QSPI_IFR_NBDUM_MASK)
#define QSPI_IFR_APBTFRTYP_READ		BIT(24)	/* Defined in SAM9X60 */

/* Bitfields in QSPI_SMR (Scrambling Mode Register) */
#define QSPI_SMR_SCREN                  BIT(0)
#define QSPI_SMR_RVDIS                  BIT(1)

/* Bitfields in QSPI_WPMR (Write Protection Mode Register) */
#define QSPI_WPMR_WPEN                  BIT(0)
#define QSPI_WPMR_WPKEY_MASK            GENMASK(31, 8)
#define QSPI_WPMR_WPKEY(wpkey)          (((wpkey) << 8) & QSPI_WPMR_WPKEY_MASK)

/* Bitfields in QSPI_WPSR (Write Protection Status Register) */
#define QSPI_WPSR_WPVS                  BIT(0)
#define QSPI_WPSR_WPVSRC_MASK           GENMASK(15, 8)
#define QSPI_WPSR_WPVSRC(src)           (((src) << 8) & QSPI_WPSR_WPVSRC)

struct atmel_qspi_caps {
	bool has_qspick;
	bool has_ricr;
};

struct atmel_qspi {
	void __iomem *regs;
	void __iomem *mem;
	resource_size_t mmap_size;
	const struct atmel_qspi_caps *caps;
	struct udevice *dev;
	ulong bus_clk_rate;
	u32 mr;
};

struct atmel_qspi_mode {
	u8 cmd_buswidth;
	u8 addr_buswidth;
	u8 data_buswidth;
	u32 config;
};

static const struct atmel_qspi_mode atmel_qspi_modes[] = {
	{ 1, 1, 1, QSPI_IFR_WIDTH_SINGLE_BIT_SPI },
	{ 1, 1, 2, QSPI_IFR_WIDTH_DUAL_OUTPUT },
	{ 1, 1, 4, QSPI_IFR_WIDTH_QUAD_OUTPUT },
	{ 1, 2, 2, QSPI_IFR_WIDTH_DUAL_IO },
	{ 1, 4, 4, QSPI_IFR_WIDTH_QUAD_IO },
	{ 2, 2, 2, QSPI_IFR_WIDTH_DUAL_CMD },
	{ 4, 4, 4, QSPI_IFR_WIDTH_QUAD_CMD },
};

#ifdef VERBOSE_DEBUG
static const char *atmel_qspi_reg_name(u32 offset, char *tmp, size_t sz)
{
	switch (offset) {
	case QSPI_CR:
		return "CR";
	case QSPI_MR:
		return "MR";
	case QSPI_RD:
		return "MR";
	case QSPI_TD:
		return "TD";
	case QSPI_SR:
		return "SR";
	case QSPI_IER:
		return "IER";
	case QSPI_IDR:
		return "IDR";
	case QSPI_IMR:
		return "IMR";
	case QSPI_SCR:
		return "SCR";
	case QSPI_IAR:
		return "IAR";
	case QSPI_ICR:
		return "ICR/WICR";
	case QSPI_IFR:
		return "IFR";
	case QSPI_RICR:
		return "RICR";
	case QSPI_SMR:
		return "SMR";
	case QSPI_SKR:
		return "SKR";
	case QSPI_WPMR:
		return "WPMR";
	case QSPI_WPSR:
		return "WPSR";
	case QSPI_VERSION:
		return "VERSION";
	default:
		snprintf(tmp, sz, "0x%02x", offset);
		break;
	}

	return tmp;
}
#endif /* VERBOSE_DEBUG */

static u32 atmel_qspi_read(struct atmel_qspi *aq, u32 offset)
{
	u32 value = readl(aq->regs + offset);

#ifdef VERBOSE_DEBUG
	char tmp[16];

	dev_vdbg(aq->dev, "read 0x%08x from %s\n", value,
		 atmel_qspi_reg_name(offset, tmp, sizeof(tmp)));
#endif /* VERBOSE_DEBUG */

	return value;
}

static void atmel_qspi_write(u32 value, struct atmel_qspi *aq, u32 offset)
{
#ifdef VERBOSE_DEBUG
	char tmp[16];

	dev_vdbg(aq->dev, "write 0x%08x into %s\n", value,
		 atmel_qspi_reg_name(offset, tmp, sizeof(tmp)));
#endif /* VERBOSE_DEBUG */

	writel(value, aq->regs + offset);
}

static inline bool atmel_qspi_is_compatible(const struct spi_mem_op *op,
					    const struct atmel_qspi_mode *mode)
{
	if (op->cmd.buswidth != mode->cmd_buswidth)
		return false;

	if (op->addr.nbytes && op->addr.buswidth != mode->addr_buswidth)
		return false;

	if (op->data.nbytes && op->data.buswidth != mode->data_buswidth)
		return false;

	return true;
}

static int atmel_qspi_find_mode(const struct spi_mem_op *op)
{
	u32 i;

	for (i = 0; i < ARRAY_SIZE(atmel_qspi_modes); i++)
		if (atmel_qspi_is_compatible(op, &atmel_qspi_modes[i]))
			return i;

	return -ENOTSUPP;
}

static bool atmel_qspi_supports_op(struct spi_slave *slave,
				   const struct spi_mem_op *op)
{
	if (atmel_qspi_find_mode(op) < 0)
		return false;

	/* special case not supported by hardware */
	if (op->addr.nbytes == 2 && op->cmd.buswidth != op->addr.buswidth &&
	    op->dummy.nbytes == 0)
		return false;

	return true;
}

static int atmel_qspi_set_cfg(struct atmel_qspi *aq,
			      const struct spi_mem_op *op, u32 *offset)
{
	u32 iar, icr, ifr;
	u32 dummy_cycles = 0;
	int mode;

	iar = 0;
	icr = QSPI_ICR_INST(op->cmd.opcode);
	ifr = QSPI_IFR_INSTEN;

	mode = atmel_qspi_find_mode(op);
	if (mode < 0)
		return mode;
	ifr |= atmel_qspi_modes[mode].config;

	if (op->dummy.buswidth && op->dummy.nbytes)
		dummy_cycles = op->dummy.nbytes * 8 / op->dummy.buswidth;

	/*
	 * The controller allows 24 and 32-bit addressing while NAND-flash
	 * requires 16-bit long. Handling 8-bit long addresses is done using
	 * the option field. For the 16-bit addresses, the workaround depends
	 * of the number of requested dummy bits. If there are 8 or more dummy
	 * cycles, the address is shifted and sent with the first dummy byte.
	 * Otherwise opcode is disabled and the first byte of the address
	 * contains the command opcode (works only if the opcode and address
	 * use the same buswidth). The limitation is when the 16-bit address is
	 * used without enough dummy cycles and the opcode is using a different
	 * buswidth than the address.
	 */
	if (op->addr.buswidth) {
		switch (op->addr.nbytes) {
		case 0:
			break;
		case 1:
			ifr |= QSPI_IFR_OPTEN | QSPI_IFR_OPTL_8BIT;
			icr |= QSPI_ICR_OPT(op->addr.val & 0xff);
			break;
		case 2:
			if (dummy_cycles < 8 / op->addr.buswidth) {
				ifr &= ~QSPI_IFR_INSTEN;
				ifr |= QSPI_IFR_ADDREN;
				iar = (op->cmd.opcode << 16) |
					(op->addr.val & 0xffff);
			} else {
				ifr |= QSPI_IFR_ADDREN;
				iar = (op->addr.val << 8) & 0xffffff;
				dummy_cycles -= 8 / op->addr.buswidth;
			}
			break;
		case 3:
			ifr |= QSPI_IFR_ADDREN;
			iar = op->addr.val & 0xffffff;
			break;
		case 4:
			ifr |= QSPI_IFR_ADDREN | QSPI_IFR_ADDRL;
			iar = op->addr.val & 0x7ffffff;
			break;
		default:
			return -ENOTSUPP;
		}
	}

	/* offset of the data access in the QSPI memory space */
	*offset = iar;

	/* Set number of dummy cycles */
	if (dummy_cycles)
		ifr |= QSPI_IFR_NBDUM(dummy_cycles);

	/* Set data enable */
	if (op->data.nbytes)
		ifr |= QSPI_IFR_DATAEN;

	/*
	 * If the QSPI controller is set in regular SPI mode, set it in
	 * Serial Memory Mode (SMM).
	 */
	if (aq->mr != QSPI_MR_SMM) {
		atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR);
		aq->mr = QSPI_MR_SMM;
	}

	/* Clear pending interrupts */
	(void)atmel_qspi_read(aq, QSPI_SR);

	if (aq->caps->has_ricr) {
		if (!op->addr.nbytes && op->data.dir == SPI_MEM_DATA_IN)
			ifr |= QSPI_IFR_APBTFRTYP_READ;

		/* Set QSPI Instruction Frame registers */
		atmel_qspi_write(iar, aq, QSPI_IAR);
		if (op->data.dir == SPI_MEM_DATA_IN)
			atmel_qspi_write(icr, aq, QSPI_RICR);
		else
			atmel_qspi_write(icr, aq, QSPI_WICR);
		atmel_qspi_write(ifr, aq, QSPI_IFR);
	} else {
		if (op->data.dir == SPI_MEM_DATA_OUT)
			ifr |= QSPI_IFR_SAMA5D2_WRITE_TRSFR;

		/* Set QSPI Instruction Frame registers */
		atmel_qspi_write(iar, aq, QSPI_IAR);
		atmel_qspi_write(icr, aq, QSPI_ICR);
		atmel_qspi_write(ifr, aq, QSPI_IFR);
	}

	return 0;
}

static int atmel_qspi_exec_op(struct spi_slave *slave,
			      const struct spi_mem_op *op)
{
	struct atmel_qspi *aq = dev_get_priv(slave->dev->parent);
	u32 sr, imr, offset;
	int err;

	/*
	 * Check if the address exceeds the MMIO window size. An improvement
	 * would be to add support for regular SPI mode and fall back to it
	 * when the flash memories overrun the controller's memory space.
	 */
	if (op->addr.val + op->data.nbytes > aq->mmap_size)
		return -ENOTSUPP;

	err = atmel_qspi_set_cfg(aq, op, &offset);
	if (err)
		return err;

	/* Skip to the final steps if there is no data */
	if (op->data.nbytes) {
		/* Dummy read of QSPI_IFR to synchronize APB and AHB accesses */
		(void)atmel_qspi_read(aq, QSPI_IFR);

		/* Send/Receive data */
		if (op->data.dir == SPI_MEM_DATA_IN)
			memcpy_fromio(op->data.buf.in, aq->mem + offset,
				      op->data.nbytes);
		else
			memcpy_toio(aq->mem + offset, op->data.buf.out,
				    op->data.nbytes);

		/* Release the chip-select */
		atmel_qspi_write(QSPI_CR_LASTXFER, aq, QSPI_CR);
	}

	/* Poll INSTruction End and Chip Select Rise flags. */
	imr = QSPI_SR_INSTRE | QSPI_SR_CSR;
	return readl_poll_timeout(aq->regs + QSPI_SR, sr, (sr & imr) == imr,
				  1000000);
}

static int atmel_qspi_set_speed(struct udevice *bus, uint hz)
{
	struct atmel_qspi *aq = dev_get_priv(bus);
	u32 scr, scbr, mask, new_value;

	/* Compute the QSPI baudrate */
	scbr = DIV_ROUND_UP(aq->bus_clk_rate, hz);
	if (scbr > 0)
		scbr--;

	new_value = QSPI_SCR_SCBR(scbr);
	mask = QSPI_SCR_SCBR_MASK;

	scr = atmel_qspi_read(aq, QSPI_SCR);
	if ((scr & mask) == new_value)
		return 0;

	scr = (scr & ~mask) | new_value;
	atmel_qspi_write(scr, aq, QSPI_SCR);

	return 0;
}

static int atmel_qspi_set_mode(struct udevice *bus, uint mode)
{
	struct atmel_qspi *aq = dev_get_priv(bus);
	u32 scr, mask, new_value = 0;

	if (mode & SPI_CPOL)
		new_value = QSPI_SCR_CPOL;
	if (mode & SPI_CPHA)
		new_value = QSPI_SCR_CPHA;

	mask = QSPI_SCR_CPOL | QSPI_SCR_CPHA;

	scr = atmel_qspi_read(aq, QSPI_SCR);
	if ((scr & mask) == new_value)
		return 0;

	scr = (scr & ~mask) | new_value;
	atmel_qspi_write(scr, aq, QSPI_SCR);

	return 0;
}

static int atmel_qspi_enable_clk(struct udevice *dev)
{
	struct atmel_qspi *aq = dev_get_priv(dev);
	struct clk pclk, qspick;
	int ret;

	ret = clk_get_by_name(dev, "pclk", &pclk);
	if (ret)
		ret = clk_get_by_index(dev, 0, &pclk);

	if (ret) {
		dev_err(dev, "Missing QSPI peripheral clock\n");
		return ret;
	}

	ret = clk_enable(&pclk);
	if (ret) {
		dev_err(dev, "Failed to enable QSPI peripheral clock\n");
		goto free_pclk;
	}

	if (aq->caps->has_qspick) {
		/* Get the QSPI system clock */
		ret = clk_get_by_name(dev, "qspick", &qspick);
		if (ret) {
			dev_err(dev, "Missing QSPI peripheral clock\n");
			goto free_pclk;
		}

		ret = clk_enable(&qspick);
		if (ret)
			dev_err(dev, "Failed to enable QSPI system clock\n");
		clk_free(&qspick);
	}

	aq->bus_clk_rate = clk_get_rate(&pclk);
	if (!aq->bus_clk_rate)
		ret = -EINVAL;

free_pclk:
	clk_free(&pclk);

	return ret;
}

static void atmel_qspi_init(struct atmel_qspi *aq)
{
	/* Reset the QSPI controller */
	atmel_qspi_write(QSPI_CR_SWRST, aq, QSPI_CR);

	/* Set the QSPI controller by default in Serial Memory Mode */
	atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR);
	aq->mr = QSPI_MR_SMM;

	/* Enable the QSPI controller */
	atmel_qspi_write(QSPI_CR_QSPIEN, aq, QSPI_CR);
}

static int atmel_qspi_probe(struct udevice *dev)
{
	struct atmel_qspi *aq = dev_get_priv(dev);
	struct resource res;
	int ret;

	aq->caps = (struct atmel_qspi_caps *)dev_get_driver_data(dev);
	if (!aq->caps) {
		dev_err(dev, "Could not retrieve QSPI caps\n");
		return -EINVAL;
	};

	/* Map the registers */
	ret = dev_read_resource_byname(dev, "qspi_base", &res);
	if (ret) {
		dev_err(dev, "missing registers\n");
		return ret;
	}

	aq->regs = devm_ioremap(dev, res.start, resource_size(&res));
	if (IS_ERR(aq->regs))
		return PTR_ERR(aq->regs);

	/* Map the AHB memory */
	ret = dev_read_resource_byname(dev, "qspi_mmap", &res);
	if (ret) {
		dev_err(dev, "missing AHB memory\n");
		return ret;
	}

	aq->mem = devm_ioremap(dev, res.start, resource_size(&res));
	if (IS_ERR(aq->mem))
		return PTR_ERR(aq->mem);

	aq->mmap_size = resource_size(&res);

	ret = atmel_qspi_enable_clk(dev);
	if (ret)
		return ret;

	aq->dev = dev;

	atmel_qspi_init(aq);

	return 0;
}

static const struct spi_controller_mem_ops atmel_qspi_mem_ops = {
	.supports_op = atmel_qspi_supports_op,
	.exec_op = atmel_qspi_exec_op,
};

static const struct dm_spi_ops atmel_qspi_ops = {
	.set_speed = atmel_qspi_set_speed,
	.set_mode = atmel_qspi_set_mode,
	.mem_ops = &atmel_qspi_mem_ops,
};

static const struct atmel_qspi_caps atmel_sama5d2_qspi_caps = {};

static const struct atmel_qspi_caps atmel_sam9x60_qspi_caps = {
	.has_qspick = true,
	.has_ricr = true,
};

static const struct udevice_id atmel_qspi_ids[] = {
	{
		.compatible = "atmel,sama5d2-qspi",
		.data = (ulong)&atmel_sama5d2_qspi_caps,
	},
	{
		.compatible = "microchip,sam9x60-qspi",
		.data = (ulong)&atmel_sam9x60_qspi_caps,
	},
	{ /* sentinel */ }
};

U_BOOT_DRIVER(atmel_qspi) = {
	.name           = "atmel_qspi",
	.id             = UCLASS_SPI,
	.of_match       = atmel_qspi_ids,
	.ops            = &atmel_qspi_ops,
	.priv_auto	= sizeof(struct atmel_qspi),
	.probe          = atmel_qspi_probe,
};
Commit	Line	Data
24c8ff46 TA	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Driver for Atmel QSPI Controller
	4	*
	5	* Copyright (C) 2015 Atmel Corporation
	6	* Copyright (C) 2018 Cryptera A/S
	7	*
	8	* Author: Cyrille Pitchen <[email protected]>
	9	* Author: Piotr Bugalski <[email protected]>
	10	*/
	11
336d4615	12	#include <malloc.h>
24c8ff46 TA	13	#include <asm/io.h>
	14	#include <clk.h>
	15	#include <common.h>
	16	#include <dm.h>
	17	#include <errno.h>
	18	#include <fdtdec.h>
336d4615	19	#include <dm/device_compat.h>
cd93d625	20	#include <linux/bitops.h>
61b29b82	21	#include <linux/err.h>
24c8ff46 TA	22	#include <linux/io.h>
	23	#include <linux/iopoll.h>
	24	#include <linux/ioport.h>
	25	#include <mach/clk.h>
	26	#include <spi.h>
	27	#include <spi-mem.h>
	28
	29	/* QSPI register offsets */
	30	#define QSPI_CR 0x0000 /* Control Register */
	31	#define QSPI_MR 0x0004 /* Mode Register */
	32	#define QSPI_RD 0x0008 /* Receive Data Register */
	33	#define QSPI_TD 0x000c /* Transmit Data Register */
	34	#define QSPI_SR 0x0010 /* Status Register */
	35	#define QSPI_IER 0x0014 /* Interrupt Enable Register */
	36	#define QSPI_IDR 0x0018 /* Interrupt Disable Register */
	37	#define QSPI_IMR 0x001c /* Interrupt Mask Register */
	38	#define QSPI_SCR 0x0020 /* Serial Clock Register */
	39
	40	#define QSPI_IAR 0x0030 /* Instruction Address Register */
	41	#define QSPI_ICR 0x0034 /* Instruction Code Register */
	42	#define QSPI_WICR 0x0034 /* Write Instruction Code Register */
	43	#define QSPI_IFR 0x0038 /* Instruction Frame Register */
	44	#define QSPI_RICR 0x003C /* Read Instruction Code Register */
	45
	46	#define QSPI_SMR 0x0040 /* Scrambling Mode Register */
	47	#define QSPI_SKR 0x0044 /* Scrambling Key Register */
	48
	49	#define QSPI_WPMR 0x00E4 /* Write Protection Mode Register */
	50	#define QSPI_WPSR 0x00E8 /* Write Protection Status Register */
	51
	52	#define QSPI_VERSION 0x00FC /* Version Register */
	53
	54	/* Bitfields in QSPI_CR (Control Register) */
	55	#define QSPI_CR_QSPIEN BIT(0)
	56	#define QSPI_CR_QSPIDIS BIT(1)
	57	#define QSPI_CR_SWRST BIT(7)
	58	#define QSPI_CR_LASTXFER BIT(24)
	59
	60	/* Bitfields in QSPI_MR (Mode Register) */
	61	#define QSPI_MR_SMM BIT(0)
	62	#define QSPI_MR_LLB BIT(1)
	63	#define QSPI_MR_WDRBT BIT(2)
	64	#define QSPI_MR_SMRM BIT(3)
	65	#define QSPI_MR_CSMODE_MASK GENMASK(5, 4)
	66	#define QSPI_MR_CSMODE_NOT_RELOADED (0 << 4)
	67	#define QSPI_MR_CSMODE_LASTXFER (1 << 4)
	68	#define QSPI_MR_CSMODE_SYSTEMATICALLY (2 << 4)
	69	#define QSPI_MR_NBBITS_MASK GENMASK(11, 8)
	70	#define QSPI_MR_NBBITS(n) ((((n) - 8) << 8) & QSPI_MR_NBBITS_MASK)
	71	#define QSPI_MR_DLYBCT_MASK GENMASK(23, 16)
	72	#define QSPI_MR_DLYBCT(n) (((n) << 16) & QSPI_MR_DLYBCT_MASK)
	73	#define QSPI_MR_DLYCS_MASK GENMASK(31, 24)
	74	#define QSPI_MR_DLYCS(n) (((n) << 24) & QSPI_MR_DLYCS_MASK)
	75
	76	/* Bitfields in QSPI_SR/QSPI_IER/QSPI_IDR/QSPI_IMR */
	77	#define QSPI_SR_RDRF BIT(0)
	78	#define QSPI_SR_TDRE BIT(1)
	79	#define QSPI_SR_TXEMPTY BIT(2)
	80	#define QSPI_SR_OVRES BIT(3)
	81	#define QSPI_SR_CSR BIT(8)
	82	#define QSPI_SR_CSS BIT(9)
	83	#define QSPI_SR_INSTRE BIT(10)
	84	#define QSPI_SR_QSPIENS BIT(24)
	85
86	#define QSPI_SR_CMD_COMPLETED (QSPI_SR_INSTRE \| QSPI_SR_CSR)
87
88	/* Bitfields in QSPI_SCR (Serial Clock Register) */
89	#define QSPI_SCR_CPOL BIT(0)
90	#define QSPI_SCR_CPHA BIT(1)
91	#define QSPI_SCR_SCBR_MASK GENMASK(15, 8)
92	#define QSPI_SCR_SCBR(n) (((n) << 8) & QSPI_SCR_SCBR_MASK)
93	#define QSPI_SCR_DLYBS_MASK GENMASK(23, 16)
94	#define QSPI_SCR_DLYBS(n) (((n) << 16) & QSPI_SCR_DLYBS_MASK)
95
96	/* Bitfields in QSPI_ICR (Read/Write Instruction Code Register) */
97	#define QSPI_ICR_INST_MASK GENMASK(7, 0)
98	#define QSPI_ICR_INST(inst) (((inst) << 0) & QSPI_ICR_INST_MASK)
99	#define QSPI_ICR_OPT_MASK GENMASK(23, 16)
100	#define QSPI_ICR_OPT(opt) (((opt) << 16) & QSPI_ICR_OPT_MASK)
101
102	/* Bitfields in QSPI_IFR (Instruction Frame Register) */
103	#define QSPI_IFR_WIDTH_MASK GENMASK(2, 0)
104	#define QSPI_IFR_WIDTH_SINGLE_BIT_SPI (0 << 0)
105	#define QSPI_IFR_WIDTH_DUAL_OUTPUT (1 << 0)
106	#define QSPI_IFR_WIDTH_QUAD_OUTPUT (2 << 0)
107	#define QSPI_IFR_WIDTH_DUAL_IO (3 << 0)
108	#define QSPI_IFR_WIDTH_QUAD_IO (4 << 0)
109	#define QSPI_IFR_WIDTH_DUAL_CMD (5 << 0)
110	#define QSPI_IFR_WIDTH_QUAD_CMD (6 << 0)
111	#define QSPI_IFR_INSTEN BIT(4)
112	#define QSPI_IFR_ADDREN BIT(5)
113	#define QSPI_IFR_OPTEN BIT(6)
114	#define QSPI_IFR_DATAEN BIT(7)
115	#define QSPI_IFR_OPTL_MASK GENMASK(9, 8)
116	#define QSPI_IFR_OPTL_1BIT (0 << 8)
117	#define QSPI_IFR_OPTL_2BIT (1 << 8)
118	#define QSPI_IFR_OPTL_4BIT (2 << 8)
119	#define QSPI_IFR_OPTL_8BIT (3 << 8)
120	#define QSPI_IFR_ADDRL BIT(10)
121	#define QSPI_IFR_TFRTYP_MEM BIT(12)
122	#define QSPI_IFR_SAMA5D2_WRITE_TRSFR BIT(13)
123	#define QSPI_IFR_CRM BIT(14)
124	#define QSPI_IFR_NBDUM_MASK GENMASK(20, 16)
125	#define QSPI_IFR_NBDUM(n) (((n) << 16) & QSPI_IFR_NBDUM_MASK)
126	#define QSPI_IFR_APBTFRTYP_READ BIT(24) /* Defined in SAM9X60 */
127
128	/* Bitfields in QSPI_SMR (Scrambling Mode Register) */
129	#define QSPI_SMR_SCREN BIT(0)
130	#define QSPI_SMR_RVDIS BIT(1)
131
132	/* Bitfields in QSPI_WPMR (Write Protection Mode Register) */
133	#define QSPI_WPMR_WPEN BIT(0)
134	#define QSPI_WPMR_WPKEY_MASK GENMASK(31, 8)
135	#define QSPI_WPMR_WPKEY(wpkey) (((wpkey) << 8) & QSPI_WPMR_WPKEY_MASK)
136
137	/* Bitfields in QSPI_WPSR (Write Protection Status Register) */
138	#define QSPI_WPSR_WPVS BIT(0)
139	#define QSPI_WPSR_WPVSRC_MASK GENMASK(15, 8)
140	#define QSPI_WPSR_WPVSRC(src) (((src) << 8) & QSPI_WPSR_WPVSRC)
141
142	struct atmel_qspi_caps {
143	bool has_qspick;
144	bool has_ricr;
145	};
146
147	struct atmel_qspi {
148	void __iomem *regs;
149	void __iomem *mem;
ba03a6c9	150	resource_size_t mmap_size;
24c8ff46	151	const struct atmel_qspi_caps *caps;
52e2565b	152	struct udevice *dev;
24c8ff46 TA	153	ulong bus_clk_rate;
	154	u32 mr;
	155	};
	156
	157	struct atmel_qspi_mode {
	158	u8 cmd_buswidth;
	159	u8 addr_buswidth;
	160	u8 data_buswidth;
	161	u32 config;
	162	};
	163
	164	static const struct atmel_qspi_mode atmel_qspi_modes[] = {
	165	{ 1, 1, 1, QSPI_IFR_WIDTH_SINGLE_BIT_SPI },
	166	{ 1, 1, 2, QSPI_IFR_WIDTH_DUAL_OUTPUT },
	167	{ 1, 1, 4, QSPI_IFR_WIDTH_QUAD_OUTPUT },
	168	{ 1, 2, 2, QSPI_IFR_WIDTH_DUAL_IO },
	169	{ 1, 4, 4, QSPI_IFR_WIDTH_QUAD_IO },
	170	{ 2, 2, 2, QSPI_IFR_WIDTH_DUAL_CMD },
	171	{ 4, 4, 4, QSPI_IFR_WIDTH_QUAD_CMD },
	172	};
	173
52e2565b TA	174	#ifdef VERBOSE_DEBUG
	175	static const char atmel_qspi_reg_name(u32 offset, char tmp, size_t sz)
	176	{
	177	switch (offset) {
	178	case QSPI_CR:
	179	return "CR";
	180	case QSPI_MR:
	181	return "MR";
	182	case QSPI_RD:
	183	return "MR";
	184	case QSPI_TD:
	185	return "TD";
	186	case QSPI_SR:
	187	return "SR";
	188	case QSPI_IER:
	189	return "IER";
	190	case QSPI_IDR:
	191	return "IDR";
	192	case QSPI_IMR:
	193	return "IMR";
	194	case QSPI_SCR:
	195	return "SCR";
	196	case QSPI_IAR:
	197	return "IAR";
	198	case QSPI_ICR:
	199	return "ICR/WICR";
	200	case QSPI_IFR:
	201	return "IFR";
	202	case QSPI_RICR:
	203	return "RICR";
	204	case QSPI_SMR:
	205	return "SMR";
	206	case QSPI_SKR:
	207	return "SKR";
	208	case QSPI_WPMR:
	209	return "WPMR";
	210	case QSPI_WPSR:
	211	return "WPSR";
	212	case QSPI_VERSION:
	213	return "VERSION";
	214	default:
	215	snprintf(tmp, sz, "0x%02x", offset);
	216	break;
	217	}
	218
	219	return tmp;
	220	}
	221	#endif /* VERBOSE_DEBUG */
	222
	223	static u32 atmel_qspi_read(struct atmel_qspi *aq, u32 offset)
	224	{
	225	u32 value = readl(aq->regs + offset);
	226
	227	#ifdef VERBOSE_DEBUG
	228	char tmp[16];
	229
	230	dev_vdbg(aq->dev, "read 0x%08x from %s\n", value,
	231	atmel_qspi_reg_name(offset, tmp, sizeof(tmp)));
	232	#endif /* VERBOSE_DEBUG */
	233
	234	return value;
	235	}
	236
	237	static void atmel_qspi_write(u32 value, struct atmel_qspi *aq, u32 offset)
238	{
239	#ifdef VERBOSE_DEBUG
240	char tmp[16];
241
242	dev_vdbg(aq->dev, "write 0x%08x into %s\n", value,
243	atmel_qspi_reg_name(offset, tmp, sizeof(tmp)));
244	#endif /* VERBOSE_DEBUG */
245
246	writel(value, aq->regs + offset);
247	}
248
24c8ff46 TA	249	static inline bool atmel_qspi_is_compatible(const struct spi_mem_op *op,
	250	const struct atmel_qspi_mode *mode)
	251	{
	252	if (op->cmd.buswidth != mode->cmd_buswidth)
	253	return false;
	254
	255	if (op->addr.nbytes && op->addr.buswidth != mode->addr_buswidth)
	256	return false;
	257
	258	if (op->data.nbytes && op->data.buswidth != mode->data_buswidth)
	259	return false;
	260
	261	return true;
	262	}
	263
	264	static int atmel_qspi_find_mode(const struct spi_mem_op *op)
	265	{
	266	u32 i;
	267
	268	for (i = 0; i < ARRAY_SIZE(atmel_qspi_modes); i++)
	269	if (atmel_qspi_is_compatible(op, &atmel_qspi_modes[i]))
	270	return i;
	271
	272	return -ENOTSUPP;
	273	}
	274
	275	static bool atmel_qspi_supports_op(struct spi_slave *slave,
	276	const struct spi_mem_op *op)
	277	{
	278	if (atmel_qspi_find_mode(op) < 0)
	279	return false;
	280
	281	/* special case not supported by hardware */
	282	if (op->addr.nbytes == 2 && op->cmd.buswidth != op->addr.buswidth &&
	283	op->dummy.nbytes == 0)
	284	return false;
	285
	286	return true;
	287	}
	288
	289	static int atmel_qspi_set_cfg(struct atmel_qspi *aq,
	290	const struct spi_mem_op op, u32 offset)
	291	{
	292	u32 iar, icr, ifr;
	293	u32 dummy_cycles = 0;
	294	int mode;
	295
	296	iar = 0;
	297	icr = QSPI_ICR_INST(op->cmd.opcode);
	298	ifr = QSPI_IFR_INSTEN;
	299
	300	mode = atmel_qspi_find_mode(op);
	301	if (mode < 0)
	302	return mode;
	303	ifr \|= atmel_qspi_modes[mode].config;
	304
	305	if (op->dummy.buswidth && op->dummy.nbytes)
	306	dummy_cycles = op->dummy.nbytes * 8 / op->dummy.buswidth;
	307
	308	/*
	309	* The controller allows 24 and 32-bit addressing while NAND-flash
	310	* requires 16-bit long. Handling 8-bit long addresses is done using
	311	* the option field. For the 16-bit addresses, the workaround depends
	312	* of the number of requested dummy bits. If there are 8 or more dummy
313	* cycles, the address is shifted and sent with the first dummy byte.
314	* Otherwise opcode is disabled and the first byte of the address
315	* contains the command opcode (works only if the opcode and address
316	* use the same buswidth). The limitation is when the 16-bit address is
317	* used without enough dummy cycles and the opcode is using a different
318	* buswidth than the address.
319	*/
320	if (op->addr.buswidth) {
321	switch (op->addr.nbytes) {
322	case 0:
323	break;
324	case 1:
325	ifr \|= QSPI_IFR_OPTEN \| QSPI_IFR_OPTL_8BIT;
326	icr \|= QSPI_ICR_OPT(op->addr.val & 0xff);
327	break;
328	case 2:
329	if (dummy_cycles < 8 / op->addr.buswidth) {
330	ifr &= ~QSPI_IFR_INSTEN;
331	ifr \|= QSPI_IFR_ADDREN;
332	iar = (op->cmd.opcode << 16) \|
333	(op->addr.val & 0xffff);
334	} else {
335	ifr \|= QSPI_IFR_ADDREN;
336	iar = (op->addr.val << 8) & 0xffffff;
337	dummy_cycles -= 8 / op->addr.buswidth;
338	}
339	break;
340	case 3:
341	ifr \|= QSPI_IFR_ADDREN;
342	iar = op->addr.val & 0xffffff;
343	break;
344	case 4:
345	ifr \|= QSPI_IFR_ADDREN \| QSPI_IFR_ADDRL;
346	iar = op->addr.val & 0x7ffffff;
347	break;
348	default:
349	return -ENOTSUPP;
350	}
351	}
352
353	/* offset of the data access in the QSPI memory space */
354	*offset = iar;
355
356	/* Set number of dummy cycles */
357	if (dummy_cycles)
358	ifr \|= QSPI_IFR_NBDUM(dummy_cycles);
359
360	/* Set data enable */
361	if (op->data.nbytes)
362	ifr \|= QSPI_IFR_DATAEN;
363
364	/*
365	* If the QSPI controller is set in regular SPI mode, set it in
366	* Serial Memory Mode (SMM).
367	*/
368	if (aq->mr != QSPI_MR_SMM) {
52e2565b	369	atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR);
24c8ff46 TA	370	aq->mr = QSPI_MR_SMM;
	371	}
	372
	373	/* Clear pending interrupts */
52e2565b	374	(void)atmel_qspi_read(aq, QSPI_SR);
24c8ff46 TA	375
	376	if (aq->caps->has_ricr) {
	377	if (!op->addr.nbytes && op->data.dir == SPI_MEM_DATA_IN)
	378	ifr \|= QSPI_IFR_APBTFRTYP_READ;
	379
	380	/* Set QSPI Instruction Frame registers */
52e2565b	381	atmel_qspi_write(iar, aq, QSPI_IAR);
24c8ff46	382	if (op->data.dir == SPI_MEM_DATA_IN)
52e2565b	383	atmel_qspi_write(icr, aq, QSPI_RICR);
24c8ff46	384	else
52e2565b TA	385	atmel_qspi_write(icr, aq, QSPI_WICR);
52e2565b TA	386	atmel_qspi_write(ifr, aq, QSPI_IFR);
24c8ff46 TA	387	} else {
	388	if (op->data.dir == SPI_MEM_DATA_OUT)
	389	ifr \|= QSPI_IFR_SAMA5D2_WRITE_TRSFR;
	390
	391	/* Set QSPI Instruction Frame registers */
52e2565b TA	392	atmel_qspi_write(iar, aq, QSPI_IAR);
	393	atmel_qspi_write(icr, aq, QSPI_ICR);
	394	atmel_qspi_write(ifr, aq, QSPI_IFR);
24c8ff46 TA	395	}
	396
	397	return 0;
	398	}
	399
	400	static int atmel_qspi_exec_op(struct spi_slave *slave,
	401	const struct spi_mem_op *op)
	402	{
	403	struct atmel_qspi *aq = dev_get_priv(slave->dev->parent);
	404	u32 sr, imr, offset;
	405	int err;
	406
ba03a6c9 TA	407	/*
	408	* Check if the address exceeds the MMIO window size. An improvement
	409	* would be to add support for regular SPI mode and fall back to it
	410	* when the flash memories overrun the controller's memory space.
	411	*/
	412	if (op->addr.val + op->data.nbytes > aq->mmap_size)
	413	return -ENOTSUPP;
	414
24c8ff46 TA	415	err = atmel_qspi_set_cfg(aq, op, &offset);
	416	if (err)
	417	return err;
	418
	419	/* Skip to the final steps if there is no data */
	420	if (op->data.nbytes) {
	421	/* Dummy read of QSPI_IFR to synchronize APB and AHB accesses */
52e2565b	422	(void)atmel_qspi_read(aq, QSPI_IFR);
24c8ff46 TA	423
	424	/* Send/Receive data */
	425	if (op->data.dir == SPI_MEM_DATA_IN)
	426	memcpy_fromio(op->data.buf.in, aq->mem + offset,
	427	op->data.nbytes);
	428	else
	429	memcpy_toio(aq->mem + offset, op->data.buf.out,
	430	op->data.nbytes);
	431
	432	/* Release the chip-select */
52e2565b	433	atmel_qspi_write(QSPI_CR_LASTXFER, aq, QSPI_CR);
24c8ff46 TA	434	}
	435
	436	/* Poll INSTruction End and Chip Select Rise flags. */
	437	imr = QSPI_SR_INSTRE \| QSPI_SR_CSR;
	438	return readl_poll_timeout(aq->regs + QSPI_SR, sr, (sr & imr) == imr,
	439	1000000);
	440	}
	441
	442	static int atmel_qspi_set_speed(struct udevice *bus, uint hz)
	443	{
	444	struct atmel_qspi *aq = dev_get_priv(bus);
	445	u32 scr, scbr, mask, new_value;
	446
	447	/* Compute the QSPI baudrate */
	448	scbr = DIV_ROUND_UP(aq->bus_clk_rate, hz);
	449	if (scbr > 0)
	450	scbr--;
	451
	452	new_value = QSPI_SCR_SCBR(scbr);
	453	mask = QSPI_SCR_SCBR_MASK;
	454
52e2565b	455	scr = atmel_qspi_read(aq, QSPI_SCR);
24c8ff46 TA	456	if ((scr & mask) == new_value)
	457	return 0;
	458
	459	scr = (scr & ~mask) \| new_value;
52e2565b	460	atmel_qspi_write(scr, aq, QSPI_SCR);
24c8ff46 TA	461
	462	return 0;
	463	}
	464
	465	static int atmel_qspi_set_mode(struct udevice *bus, uint mode)
	466	{
	467	struct atmel_qspi *aq = dev_get_priv(bus);
	468	u32 scr, mask, new_value = 0;
	469
	470	if (mode & SPI_CPOL)
	471	new_value = QSPI_SCR_CPOL;
	472	if (mode & SPI_CPHA)
	473	new_value = QSPI_SCR_CPHA;
	474
	475	mask = QSPI_SCR_CPOL \| QSPI_SCR_CPHA;
	476
52e2565b	477	scr = atmel_qspi_read(aq, QSPI_SCR);
24c8ff46 TA	478	if ((scr & mask) == new_value)
	479	return 0;
	480
	481	scr = (scr & ~mask) \| new_value;
52e2565b	482	atmel_qspi_write(scr, aq, QSPI_SCR);
24c8ff46 TA	483
	484	return 0;
	485	}
	486
	487	static int atmel_qspi_enable_clk(struct udevice *dev)
	488	{
	489	struct atmel_qspi *aq = dev_get_priv(dev);
	490	struct clk pclk, qspick;
	491	int ret;
	492
	493	ret = clk_get_by_name(dev, "pclk", &pclk);
	494	if (ret)
	495	ret = clk_get_by_index(dev, 0, &pclk);
	496
	497	if (ret) {
	498	dev_err(dev, "Missing QSPI peripheral clock\n");
	499	return ret;
	500	}
	501
	502	ret = clk_enable(&pclk);
	503	if (ret) {
	504	dev_err(dev, "Failed to enable QSPI peripheral clock\n");
	505	goto free_pclk;
	506	}
	507
	508	if (aq->caps->has_qspick) {
	509	/* Get the QSPI system clock */
	510	ret = clk_get_by_name(dev, "qspick", &qspick);
	511	if (ret) {
	512	dev_err(dev, "Missing QSPI peripheral clock\n");
	513	goto free_pclk;
	514	}
	515
	516	ret = clk_enable(&qspick);
	517	if (ret)
	518	dev_err(dev, "Failed to enable QSPI system clock\n");
	519	clk_free(&qspick);
	520	}
	521
	522	aq->bus_clk_rate = clk_get_rate(&pclk);
	523	if (!aq->bus_clk_rate)
	524	ret = -EINVAL;
	525
	526	free_pclk:
	527	clk_free(&pclk);
	528
	529	return ret;
	530	}
	531
	532	static void atmel_qspi_init(struct atmel_qspi *aq)
	533	{
	534	/* Reset the QSPI controller */
52e2565b	535	atmel_qspi_write(QSPI_CR_SWRST, aq, QSPI_CR);
24c8ff46 TA	536
24c8ff46 TA	537	/* Set the QSPI controller by default in Serial Memory Mode */
52e2565b	538	atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR);
24c8ff46 TA	539	aq->mr = QSPI_MR_SMM;
	540
	541	/* Enable the QSPI controller */
52e2565b	542	atmel_qspi_write(QSPI_CR_QSPIEN, aq, QSPI_CR);
24c8ff46 TA	543	}
	544
	545	static int atmel_qspi_probe(struct udevice *dev)
	546	{
	547	struct atmel_qspi *aq = dev_get_priv(dev);
	548	struct resource res;
	549	int ret;
	550
	551	aq->caps = (struct atmel_qspi_caps *)dev_get_driver_data(dev);
	552	if (!aq->caps) {
	553	dev_err(dev, "Could not retrieve QSPI caps\n");
	554	return -EINVAL;
	555	};
	556
	557	/* Map the registers */
	558	ret = dev_read_resource_byname(dev, "qspi_base", &res);
	559	if (ret) {
	560	dev_err(dev, "missing registers\n");
	561	return ret;
	562	}
	563
	564	aq->regs = devm_ioremap(dev, res.start, resource_size(&res));
	565	if (IS_ERR(aq->regs))
	566	return PTR_ERR(aq->regs);
	567
	568	/* Map the AHB memory */
	569	ret = dev_read_resource_byname(dev, "qspi_mmap", &res);
	570	if (ret) {
	571	dev_err(dev, "missing AHB memory\n");
	572	return ret;
	573	}
	574
	575	aq->mem = devm_ioremap(dev, res.start, resource_size(&res));
	576	if (IS_ERR(aq->mem))
	577	return PTR_ERR(aq->mem);
	578
ba03a6c9 TA	579	aq->mmap_size = resource_size(&res);
ba03a6c9 TA	580
24c8ff46 TA	581	ret = atmel_qspi_enable_clk(dev);
	582	if (ret)
	583	return ret;
	584
52e2565b TA	585	aq->dev = dev;
52e2565b TA	586
24c8ff46 TA	587	atmel_qspi_init(aq);
	588
	589	return 0;
	590	}
	591
	592	static const struct spi_controller_mem_ops atmel_qspi_mem_ops = {
	593	.supports_op = atmel_qspi_supports_op,
	594	.exec_op = atmel_qspi_exec_op,
	595	};
	596
	597	static const struct dm_spi_ops atmel_qspi_ops = {
	598	.set_speed = atmel_qspi_set_speed,
	599	.set_mode = atmel_qspi_set_mode,
	600	.mem_ops = &atmel_qspi_mem_ops,
	601	};
	602
	603	static const struct atmel_qspi_caps atmel_sama5d2_qspi_caps = {};
	604
	605	static const struct atmel_qspi_caps atmel_sam9x60_qspi_caps = {
	606	.has_qspick = true,
	607	.has_ricr = true,
	608	};
	609
	610	static const struct udevice_id atmel_qspi_ids[] = {
	611	{
	612	.compatible = "atmel,sama5d2-qspi",
	613	.data = (ulong)&atmel_sama5d2_qspi_caps,
	614	},
	615	{
	616	.compatible = "microchip,sam9x60-qspi",
	617	.data = (ulong)&atmel_sam9x60_qspi_caps,
	618	},
	619	{ /* sentinel */ }
	620	};
	621
	622	U_BOOT_DRIVER(atmel_qspi) = {
	623	.name = "atmel_qspi",
	624	.id = UCLASS_SPI,
	625	.of_match = atmel_qspi_ids,
	626	.ops = &atmel_qspi_ops,
41575d8e	627	.priv_auto = sizeof(struct atmel_qspi),
24c8ff46 TA	628	.probe = atmel_qspi_probe,
24c8ff46 TA	629	};