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Merge tag 'dm-pull-14dec20' of git://git.denx.de/u-boot-dm into next
[u-boot.git] / drivers / net / e1000.c
CommitLineData
83d290c5 1// SPDX-License-Identifier: GPL-2.0+
682011ff 2/**************************************************************************
ac3315c2 3Intel Pro 1000 for ppcboot/das-u-boot
682011ff
WD		 4Drivers are port from Intel's Linux driver e1000-4.3.15
5and from Etherboot pro 1000 driver by mrakes at vivato dot net
6tested on both gig copper and gig fiber boards
7***************************************************************************/
8/*******************************************************************************
9
8bde7f77 10
682011ff 11 Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
8bde7f77 12
8bde7f77 13
682011ff
WD		 14 Contact Information:
15 Linux NICS <[email protected]>
16 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
17
18*******************************************************************************/
19/*
20 * Copyright (C) Archway Digital Solutions.
21 *
22 * written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org>
23 * 2/9/2002
24 *
25 * Copyright (C) Linux Networx.
26 * Massive upgrade to work with the new intel gigabit NICs.
27 * <ebiederman at lnxi dot com>
2c2668f9
RZ		 28 *
29 * Copyright 2011 Freescale Semiconductor, Inc.
682011ff
WD		 30 */
31
c752cd2a 32#include <common.h>
09140113 33#include <command.h>
1eb69ae4 34#include <cpu_func.h>
c6d80a15 35#include <dm.h>
5c5e707a 36#include <errno.h>
f7ae49fc 37#include <log.h>
336d4615 38#include <malloc.h>
cf92e05c 39#include <memalign.h>
90526e9f 40#include <net.h>
5c5e707a 41#include <pci.h>
c05ed00a 42#include <linux/delay.h>
682011ff 43#include "e1000.h"
90526e9f 44#include <asm/cache.h>
682011ff 45
682011ff
WD		 46#define TOUT_LOOP 100000
47
81dab9af
BM		 48#ifdef CONFIG_DM_ETH
49#define virt_to_bus(devno, v) dm_pci_virt_to_mem(devno, (void *) (v))
50#define bus_to_phys(devno, a) dm_pci_mem_to_phys(devno, a)
51#else
f81ecb5d 52#define virt_to_bus(devno, v) pci_virt_to_mem(devno, (void *) (v))
682011ff 53#define bus_to_phys(devno, a) pci_mem_to_phys(devno, a)
81dab9af 54#endif
682011ff 55
9ea005fb
RZ		 56#define E1000_DEFAULT_PCI_PBA 0x00000030
57#define E1000_DEFAULT_PCIE_PBA 0x000a0026
682011ff
WD		 58
59/* NIC specific static variables go here */
60
873e8e01
MV		 61/* Intel i210 needs the DMA descriptor rings aligned to 128b */
62#define E1000_BUFFER_ALIGN 128
682011ff 63
c6d80a15
SG		 64/*
65 * TODO([email protected]): Even with driver model we share these buffers.
66 * Concurrent receiving on multiple active Ethernet devices will not work.
67 * Normally U-Boot does not support this anyway. To fix it in this driver,
68 * move these buffers and the tx/rx pointers to struct e1000_hw.
69 */
873e8e01
MV		 70DEFINE_ALIGN_BUFFER(struct e1000_tx_desc, tx_base, 16, E1000_BUFFER_ALIGN);
71DEFINE_ALIGN_BUFFER(struct e1000_rx_desc, rx_base, 16, E1000_BUFFER_ALIGN);
72DEFINE_ALIGN_BUFFER(unsigned char, packet, 4096, E1000_BUFFER_ALIGN);
682011ff
WD		 73
74static int tx_tail;
75static int rx_tail, rx_last;
c6d80a15
SG		 76#ifdef CONFIG_DM_ETH
77static int num_cards; /* Number of E1000 devices seen so far */
78#endif
682011ff 79
d60626f8 80static struct pci_device_id e1000_supported[] = {
5c5e707a
SG		 81 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542) },
82 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER) },
83 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER) },
84 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER) },
85 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER) },
86 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER) },
87 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM) },
88 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM) },
89 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER) },
90 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545GM_COPPER) },
91 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER) },
92 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER) },
93 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER) },
94 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_COPPER) },
95 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM) },
96 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER) },
97 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF) },
aa070789 98 /* E1000 PCIe card */
5c5e707a
SG		 99 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_COPPER) },
100 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_FIBER) },
101 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES) },
102 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER) },
103 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571PT_QUAD_COPPER) },
104 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_FIBER) },
105 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER_LOWPROFILE) },
106 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_DUAL) },
107 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_QUAD) },
108 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_COPPER) },
109 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_FIBER) },
110 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_SERDES) },
111 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI) },
112 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E) },
113 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E_IAMT) },
114 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573L) },
115 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82574L) },
116 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3) },
117 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT) },
118 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT) },
119 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT) },
120 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT) },
121 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED) },
122 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED) },
123 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER) },
124 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_COPPER) },
125 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS) },
126 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES) },
127 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS) },
128 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_1000BASEKX) },
95186063 129
1bc43437 130 {}
682011ff
WD		 131};
132
133/* Function forward declarations */
5c5e707a
SG		 134static int e1000_setup_link(struct e1000_hw *hw);
135static int e1000_setup_fiber_link(struct e1000_hw *hw);
136static int e1000_setup_copper_link(struct e1000_hw *hw);
682011ff
WD		 137static int e1000_phy_setup_autoneg(struct e1000_hw *hw);
138static void e1000_config_collision_dist(struct e1000_hw *hw);
139static int e1000_config_mac_to_phy(struct e1000_hw *hw);
140static int e1000_config_fc_after_link_up(struct e1000_hw *hw);
5c5e707a 141static int e1000_check_for_link(struct e1000_hw *hw);
682011ff 142static int e1000_wait_autoneg(struct e1000_hw *hw);
aa070789 143static int e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed,
682011ff
WD		 144 uint16_t * duplex);
145static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
146 uint16_t * phy_data);
147static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
148 uint16_t phy_data);
aa070789 149static int32_t e1000_phy_hw_reset(struct e1000_hw *hw);
682011ff
WD		 150static int e1000_phy_reset(struct e1000_hw *hw);
151static int e1000_detect_gig_phy(struct e1000_hw *hw);
aa070789
RZ		 152static void e1000_set_media_type(struct e1000_hw *hw);
153
154static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
7e2d991d 155static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask);
aa070789 156static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
682011ff 157
8712adfd
RI		 158#ifndef CONFIG_E1000_NO_NVM
159static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
f1bcad22 160static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw);
ecbd2078
RZ		 161static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
162 uint16_t words,
163 uint16_t *data);
682011ff
WD		 164/******************************************************************************
165 * Raises the EEPROM's clock input.
166 *
167 * hw - Struct containing variables accessed by shared code
168 * eecd - EECD's current value
169 *****************************************************************************/
2326a94d 170void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
682011ff
WD		 171{
172 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
173 * wait 50 microseconds.
174 */
175 *eecd = *eecd | E1000_EECD_SK;
176 E1000_WRITE_REG(hw, EECD, *eecd);
177 E1000_WRITE_FLUSH(hw);
178 udelay(50);
179}
180
181/******************************************************************************
182 * Lowers the EEPROM's clock input.
183 *
8bde7f77 184 * hw - Struct containing variables accessed by shared code
682011ff
WD		 185 * eecd - EECD's current value
186 *****************************************************************************/
2326a94d 187void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
682011ff 188{
8bde7f77
WD		 189 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
190 * wait 50 microseconds.
682011ff
WD		 191 */
192 *eecd = *eecd & ~E1000_EECD_SK;
193 E1000_WRITE_REG(hw, EECD, *eecd);
194 E1000_WRITE_FLUSH(hw);
195 udelay(50);
196}
197
198/******************************************************************************
199 * Shift data bits out to the EEPROM.
200 *
201 * hw - Struct containing variables accessed by shared code
202 * data - data to send to the EEPROM
203 * count - number of bits to shift out
204 *****************************************************************************/
205static void
206e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count)
207{
208 uint32_t eecd;
209 uint32_t mask;
210
211 /* We need to shift "count" bits out to the EEPROM. So, value in the
212 * "data" parameter will be shifted out to the EEPROM one bit at a time.
8bde7f77 213 * In order to do this, "data" must be broken down into bits.
682011ff
WD		 214 */
215 mask = 0x01 << (count - 1);
216 eecd = E1000_READ_REG(hw, EECD);
217 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
218 do {
219 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
220 * and then raising and then lowering the clock (the SK bit controls
221 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
222 * by setting "DI" to "0" and then raising and then lowering the clock.
223 */
224 eecd &= ~E1000_EECD_DI;
225
226 if (data & mask)
227 eecd |= E1000_EECD_DI;
228
229 E1000_WRITE_REG(hw, EECD, eecd);
230 E1000_WRITE_FLUSH(hw);
231
232 udelay(50);
233
234 e1000_raise_ee_clk(hw, &eecd);
235 e1000_lower_ee_clk(hw, &eecd);
236
237 mask = mask >> 1;
238
239 } while (mask);
240
241 /* We leave the "DI" bit set to "0" when we leave this routine. */
242 eecd &= ~E1000_EECD_DI;
243 E1000_WRITE_REG(hw, EECD, eecd);
244}
245
246/******************************************************************************
247 * Shift data bits in from the EEPROM
248 *
249 * hw - Struct containing variables accessed by shared code
250 *****************************************************************************/
251static uint16_t
aa070789 252e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count)
682011ff
WD		 253{
254 uint32_t eecd;
255 uint32_t i;
256 uint16_t data;
257
aa070789
RZ		 258 /* In order to read a register from the EEPROM, we need to shift 'count'
259 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
260 * input to the EEPROM (setting the SK bit), and then reading the
261 * value of the "DO" bit. During this "shifting in" process the
262 * "DI" bit should always be clear.
682011ff
WD		 263 */
264
265 eecd = E1000_READ_REG(hw, EECD);
266
267 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
268 data = 0;
269
aa070789 270 for (i = 0; i < count; i++) {
682011ff
WD		 271 data = data << 1;
272 e1000_raise_ee_clk(hw, &eecd);
273
274 eecd = E1000_READ_REG(hw, EECD);
275
276 eecd &= ~(E1000_EECD_DI);
277 if (eecd & E1000_EECD_DO)
278 data |= 1;
279
280 e1000_lower_ee_clk(hw, &eecd);
281 }
282
283 return data;
284}
285
286/******************************************************************************
aa070789 287 * Returns EEPROM to a "standby" state
682011ff
WD		 288 *
289 * hw - Struct containing variables accessed by shared code
682011ff 290 *****************************************************************************/
2326a94d 291void e1000_standby_eeprom(struct e1000_hw *hw)
682011ff 292{
aa070789 293 struct e1000_eeprom_info *eeprom = &hw->eeprom;
682011ff
WD		 294 uint32_t eecd;
295
296 eecd = E1000_READ_REG(hw, EECD);
297
aa070789
RZ		 298 if (eeprom->type == e1000_eeprom_microwire) {
299 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
300 E1000_WRITE_REG(hw, EECD, eecd);
301 E1000_WRITE_FLUSH(hw);
302 udelay(eeprom->delay_usec);
682011ff 303
aa070789
RZ		 304 /* Clock high */
305 eecd |= E1000_EECD_SK;
306 E1000_WRITE_REG(hw, EECD, eecd);
307 E1000_WRITE_FLUSH(hw);
308 udelay(eeprom->delay_usec);
309
310 /* Select EEPROM */
311 eecd |= E1000_EECD_CS;
312 E1000_WRITE_REG(hw, EECD, eecd);
313 E1000_WRITE_FLUSH(hw);
314 udelay(eeprom->delay_usec);
315
316 /* Clock low */
317 eecd &= ~E1000_EECD_SK;
318 E1000_WRITE_REG(hw, EECD, eecd);
319 E1000_WRITE_FLUSH(hw);
320 udelay(eeprom->delay_usec);
321 } else if (eeprom->type == e1000_eeprom_spi) {
322 /* Toggle CS to flush commands */
323 eecd |= E1000_EECD_CS;
324 E1000_WRITE_REG(hw, EECD, eecd);
325 E1000_WRITE_FLUSH(hw);
326 udelay(eeprom->delay_usec);
327 eecd &= ~E1000_EECD_CS;
328 E1000_WRITE_REG(hw, EECD, eecd);
329 E1000_WRITE_FLUSH(hw);
330 udelay(eeprom->delay_usec);
331 }
332}
333
334/***************************************************************************
335* Description: Determines if the onboard NVM is FLASH or EEPROM.
336*
337* hw - Struct containing variables accessed by shared code
338****************************************************************************/
472d5460 339static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
aa070789
RZ		 340{
341 uint32_t eecd = 0;
342
343 DEBUGFUNC();
344
345 if (hw->mac_type == e1000_ich8lan)
472d5460 346 return false;
aa070789 347
2c2668f9 348 if (hw->mac_type == e1000_82573 || hw->mac_type == e1000_82574) {
aa070789
RZ		 349 eecd = E1000_READ_REG(hw, EECD);
350
351 /* Isolate bits 15 & 16 */
352 eecd = ((eecd >> 15) & 0x03);
353
354 /* If both bits are set, device is Flash type */
355 if (eecd == 0x03)
472d5460 356 return false;
aa070789 357 }
472d5460 358 return true;
682011ff
WD		 359}
360
361/******************************************************************************
aa070789 362 * Prepares EEPROM for access
8bde7f77 363 *
682011ff 364 * hw - Struct containing variables accessed by shared code
aa070789
RZ		 365 *
366 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
367 * function should be called before issuing a command to the EEPROM.
682011ff 368 *****************************************************************************/
2326a94d 369int32_t e1000_acquire_eeprom(struct e1000_hw *hw)
682011ff 370{
aa070789
RZ		 371 struct e1000_eeprom_info *eeprom = &hw->eeprom;
372 uint32_t eecd, i = 0;
682011ff 373
f81ecb5d 374 DEBUGFUNC();
aa070789
RZ		 375
376 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
377 return -E1000_ERR_SWFW_SYNC;
682011ff
WD		 378 eecd = E1000_READ_REG(hw, EECD);
379
95186063 380 if (hw->mac_type != e1000_82573 && hw->mac_type != e1000_82574) {
aa070789
RZ		 381 /* Request EEPROM Access */
382 if (hw->mac_type > e1000_82544) {
383 eecd |= E1000_EECD_REQ;
384 E1000_WRITE_REG(hw, EECD, eecd);
385 eecd = E1000_READ_REG(hw, EECD);
386 while ((!(eecd & E1000_EECD_GNT)) &&
387 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
388 i++;
389 udelay(5);
390 eecd = E1000_READ_REG(hw, EECD);
391 }
392 if (!(eecd & E1000_EECD_GNT)) {
393 eecd &= ~E1000_EECD_REQ;
394 E1000_WRITE_REG(hw, EECD, eecd);
395 DEBUGOUT("Could not acquire EEPROM grant\n");
396 return -E1000_ERR_EEPROM;
397 }
398 }
399 }
682011ff 400
aa070789 401 /* Setup EEPROM for Read/Write */
682011ff 402
aa070789
RZ		 403 if (eeprom->type == e1000_eeprom_microwire) {
404 /* Clear SK and DI */
405 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
406 E1000_WRITE_REG(hw, EECD, eecd);
682011ff 407
aa070789
RZ		 408 /* Set CS */
409 eecd |= E1000_EECD_CS;
410 E1000_WRITE_REG(hw, EECD, eecd);
411 } else if (eeprom->type == e1000_eeprom_spi) {
412 /* Clear SK and CS */
413 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
414 E1000_WRITE_REG(hw, EECD, eecd);
415 udelay(1);
416 }
417
418 return E1000_SUCCESS;
682011ff
WD		 419}
420
421/******************************************************************************
aa070789
RZ		 422 * Sets up eeprom variables in the hw struct. Must be called after mac_type
423 * is configured. Additionally, if this is ICH8, the flash controller GbE
424 * registers must be mapped, or this will crash.
682011ff
WD		 425 *
426 * hw - Struct containing variables accessed by shared code
682011ff 427 *****************************************************************************/
aa070789 428static int32_t e1000_init_eeprom_params(struct e1000_hw *hw)
682011ff 429{
aa070789 430 struct e1000_eeprom_info *eeprom = &hw->eeprom;
95186063 431 uint32_t eecd;
aa070789
RZ		 432 int32_t ret_val = E1000_SUCCESS;
433 uint16_t eeprom_size;
682011ff 434
95186063
MV		 435 if (hw->mac_type == e1000_igb)
436 eecd = E1000_READ_REG(hw, I210_EECD);
437 else
438 eecd = E1000_READ_REG(hw, EECD);
439
f81ecb5d 440 DEBUGFUNC();
aa070789
RZ		 441
442 switch (hw->mac_type) {
443 case e1000_82542_rev2_0:
444 case e1000_82542_rev2_1:
445 case e1000_82543:
446 case e1000_82544:
447 eeprom->type = e1000_eeprom_microwire;
448 eeprom->word_size = 64;
449 eeprom->opcode_bits = 3;
450 eeprom->address_bits = 6;
451 eeprom->delay_usec = 50;
472d5460
YS		 452 eeprom->use_eerd = false;
453 eeprom->use_eewr = false;
aa070789
RZ		 454 break;
455 case e1000_82540:
456 case e1000_82545:
457 case e1000_82545_rev_3:
458 case e1000_82546:
459 case e1000_82546_rev_3:
460 eeprom->type = e1000_eeprom_microwire;
461 eeprom->opcode_bits = 3;
462 eeprom->delay_usec = 50;
463 if (eecd & E1000_EECD_SIZE) {
464 eeprom->word_size = 256;
465 eeprom->address_bits = 8;
466 } else {
467 eeprom->word_size = 64;
468 eeprom->address_bits = 6;
469 }
472d5460
YS		 470 eeprom->use_eerd = false;
471 eeprom->use_eewr = false;
aa070789
RZ		 472 break;
473 case e1000_82541:
474 case e1000_82541_rev_2:
475 case e1000_82547:
476 case e1000_82547_rev_2:
477 if (eecd & E1000_EECD_TYPE) {
478 eeprom->type = e1000_eeprom_spi;
479 eeprom->opcode_bits = 8;
480 eeprom->delay_usec = 1;
481 if (eecd & E1000_EECD_ADDR_BITS) {
482 eeprom->page_size = 32;
483 eeprom->address_bits = 16;
484 } else {
485 eeprom->page_size = 8;
486 eeprom->address_bits = 8;
487 }
488 } else {
489 eeprom->type = e1000_eeprom_microwire;
490 eeprom->opcode_bits = 3;
491 eeprom->delay_usec = 50;
492 if (eecd & E1000_EECD_ADDR_BITS) {
493 eeprom->word_size = 256;
494 eeprom->address_bits = 8;
495 } else {
496 eeprom->word_size = 64;
497 eeprom->address_bits = 6;
498 }
499 }
472d5460
YS		 500 eeprom->use_eerd = false;
501 eeprom->use_eewr = false;
aa070789
RZ		 502 break;
503 case e1000_82571:
504 case e1000_82572:
505 eeprom->type = e1000_eeprom_spi;
506 eeprom->opcode_bits = 8;
507 eeprom->delay_usec = 1;
508 if (eecd & E1000_EECD_ADDR_BITS) {
509 eeprom->page_size = 32;
510 eeprom->address_bits = 16;
511 } else {
512 eeprom->page_size = 8;
513 eeprom->address_bits = 8;
514 }
472d5460
YS		 515 eeprom->use_eerd = false;
516 eeprom->use_eewr = false;
aa070789
RZ		 517 break;
518 case e1000_82573:
2c2668f9 519 case e1000_82574:
aa070789
RZ		 520 eeprom->type = e1000_eeprom_spi;
521 eeprom->opcode_bits = 8;
522 eeprom->delay_usec = 1;
523 if (eecd & E1000_EECD_ADDR_BITS) {
524 eeprom->page_size = 32;
525 eeprom->address_bits = 16;
526 } else {
527 eeprom->page_size = 8;
528 eeprom->address_bits = 8;
682011ff 529 }
472d5460 530 if (e1000_is_onboard_nvm_eeprom(hw) == false) {
95186063
MV		 531 eeprom->use_eerd = true;
532 eeprom->use_eewr = true;
533
aa070789
RZ		 534 eeprom->type = e1000_eeprom_flash;
535 eeprom->word_size = 2048;
536
537 /* Ensure that the Autonomous FLASH update bit is cleared due to
538 * Flash update issue on parts which use a FLASH for NVM. */
539 eecd &= ~E1000_EECD_AUPDEN;
682011ff 540 E1000_WRITE_REG(hw, EECD, eecd);
682011ff 541 }
aa070789
RZ		 542 break;
543 case e1000_80003es2lan:
544 eeprom->type = e1000_eeprom_spi;
545 eeprom->opcode_bits = 8;
546 eeprom->delay_usec = 1;
547 if (eecd & E1000_EECD_ADDR_BITS) {
548 eeprom->page_size = 32;
549 eeprom->address_bits = 16;
550 } else {
551 eeprom->page_size = 8;
552 eeprom->address_bits = 8;
553 }
472d5460
YS		 554 eeprom->use_eerd = true;
555 eeprom->use_eewr = false;
aa070789 556 break;
95186063
MV		 557 case e1000_igb:
558 /* i210 has 4k of iNVM mapped as EEPROM */
559 eeprom->type = e1000_eeprom_invm;
560 eeprom->opcode_bits = 8;
561 eeprom->delay_usec = 1;
562 eeprom->page_size = 32;
563 eeprom->address_bits = 16;
564 eeprom->use_eerd = true;
565 eeprom->use_eewr = false;
566 break;
aa070789
RZ		 567 default:
568 break;
682011ff
WD		 569 }
570
95186063
MV		 571 if (eeprom->type == e1000_eeprom_spi ||
572 eeprom->type == e1000_eeprom_invm) {
aa070789
RZ		 573 /* eeprom_size will be an enum [0..8] that maps
574 * to eeprom sizes 128B to
575 * 32KB (incremented by powers of 2).
576 */
577 if (hw->mac_type <= e1000_82547_rev_2) {
578 /* Set to default value for initial eeprom read. */
579 eeprom->word_size = 64;
580 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1,
581 &eeprom_size);
582 if (ret_val)
583 return ret_val;
584 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK)
585 >> EEPROM_SIZE_SHIFT;
586 /* 256B eeprom size was not supported in earlier
587 * hardware, so we bump eeprom_size up one to
588 * ensure that "1" (which maps to 256B) is never
589 * the result used in the shifting logic below. */
590 if (eeprom_size)
591 eeprom_size++;
592 } else {
593 eeprom_size = (uint16_t)((eecd &
594 E1000_EECD_SIZE_EX_MASK) >>
595 E1000_EECD_SIZE_EX_SHIFT);
596 }
597
598 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
599 }
600 return ret_val;
682011ff
WD		 601}
602
aa070789
RZ		 603/******************************************************************************
604 * Polls the status bit (bit 1) of the EERD to determine when the read is done.
605 *
606 * hw - Struct containing variables accessed by shared code
607 *****************************************************************************/
608static int32_t
609e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
682011ff 610{
aa070789
RZ		 611 uint32_t attempts = 100000;
612 uint32_t i, reg = 0;
613 int32_t done = E1000_ERR_EEPROM;
682011ff 614
aa070789 615 for (i = 0; i < attempts; i++) {
95186063
MV		 616 if (eerd == E1000_EEPROM_POLL_READ) {
617 if (hw->mac_type == e1000_igb)
618 reg = E1000_READ_REG(hw, I210_EERD);
619 else
620 reg = E1000_READ_REG(hw, EERD);
621 } else {
622 if (hw->mac_type == e1000_igb)
623 reg = E1000_READ_REG(hw, I210_EEWR);
624 else
625 reg = E1000_READ_REG(hw, EEWR);
626 }
aa070789
RZ		 627
628 if (reg & E1000_EEPROM_RW_REG_DONE) {
629 done = E1000_SUCCESS;
630 break;
631 }
632 udelay(5);
633 }
634
635 return done;
682011ff
WD		 636}
637
aa070789
RZ		 638/******************************************************************************
639 * Reads a 16 bit word from the EEPROM using the EERD register.
640 *
641 * hw - Struct containing variables accessed by shared code
642 * offset - offset of word in the EEPROM to read
643 * data - word read from the EEPROM
644 * words - number of words to read
645 *****************************************************************************/
646static int32_t
647e1000_read_eeprom_eerd(struct e1000_hw *hw,
648 uint16_t offset,
649 uint16_t words,
650 uint16_t *data)
682011ff 651{
aa070789
RZ		 652 uint32_t i, eerd = 0;
653 int32_t error = 0;
654
655 for (i = 0; i < words; i++) {
656 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
657 E1000_EEPROM_RW_REG_START;
658
95186063
MV		 659 if (hw->mac_type == e1000_igb)
660 E1000_WRITE_REG(hw, I210_EERD, eerd);
661 else
662 E1000_WRITE_REG(hw, EERD, eerd);
663
aa070789
RZ		 664 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
665
666 if (error)
667 break;
95186063
MV		 668
669 if (hw->mac_type == e1000_igb) {
670 data[i] = (E1000_READ_REG(hw, I210_EERD) >>
671 E1000_EEPROM_RW_REG_DATA);
672 } else {
673 data[i] = (E1000_READ_REG(hw, EERD) >>
aa070789 674 E1000_EEPROM_RW_REG_DATA);
95186063 675 }
682011ff 676
682011ff 677 }
aa070789
RZ		 678
679 return error;
682011ff
WD		 680}
681
2326a94d 682void e1000_release_eeprom(struct e1000_hw *hw)
682011ff
WD		 683{
684 uint32_t eecd;
682011ff 685
aa070789
RZ		 686 DEBUGFUNC();
687
688 eecd = E1000_READ_REG(hw, EECD);
689
690 if (hw->eeprom.type == e1000_eeprom_spi) {
691 eecd |= E1000_EECD_CS; /* Pull CS high */
692 eecd &= ~E1000_EECD_SK; /* Lower SCK */
693
682011ff 694 E1000_WRITE_REG(hw, EECD, eecd);
aa070789
RZ		 695
696 udelay(hw->eeprom.delay_usec);
697 } else if (hw->eeprom.type == e1000_eeprom_microwire) {
698 /* cleanup eeprom */
699
700 /* CS on Microwire is active-high */
701 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
702
703 E1000_WRITE_REG(hw, EECD, eecd);
704
705 /* Rising edge of clock */
706 eecd |= E1000_EECD_SK;
707 E1000_WRITE_REG(hw, EECD, eecd);
708 E1000_WRITE_FLUSH(hw);
709 udelay(hw->eeprom.delay_usec);
710
711 /* Falling edge of clock */
712 eecd &= ~E1000_EECD_SK;
713 E1000_WRITE_REG(hw, EECD, eecd);
714 E1000_WRITE_FLUSH(hw);
715 udelay(hw->eeprom.delay_usec);
682011ff 716 }
682011ff
WD		 717
718 /* Stop requesting EEPROM access */
719 if (hw->mac_type > e1000_82544) {
682011ff
WD		 720 eecd &= ~E1000_EECD_REQ;
721 E1000_WRITE_REG(hw, EECD, eecd);
722 }
7e2d991d
TH		 723
724 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
682011ff 725}
7e2d991d 726
682011ff 727/******************************************************************************
aa070789 728 * Reads a 16 bit word from the EEPROM.
8bde7f77 729 *
682011ff 730 * hw - Struct containing variables accessed by shared code
682011ff 731 *****************************************************************************/
aa070789
RZ		 732static int32_t
733e1000_spi_eeprom_ready(struct e1000_hw *hw)
682011ff 734{
aa070789
RZ		 735 uint16_t retry_count = 0;
736 uint8_t spi_stat_reg;
682011ff
WD		 737
738 DEBUGFUNC();
739
aa070789
RZ		 740 /* Read "Status Register" repeatedly until the LSB is cleared. The
741 * EEPROM will signal that the command has been completed by clearing
742 * bit 0 of the internal status register. If it's not cleared within
743 * 5 milliseconds, then error out.
744 */
745 retry_count = 0;
746 do {
747 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
748 hw->eeprom.opcode_bits);
749 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
750 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
751 break;
8bde7f77 752
aa070789
RZ		 753 udelay(5);
754 retry_count += 5;
755
756 e1000_standby_eeprom(hw);
757 } while (retry_count < EEPROM_MAX_RETRY_SPI);
758
759 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
760 * only 0-5mSec on 5V devices)
761 */
762 if (retry_count >= EEPROM_MAX_RETRY_SPI) {
763 DEBUGOUT("SPI EEPROM Status error\n");
682011ff
WD		 764 return -E1000_ERR_EEPROM;
765 }
aa070789
RZ		 766
767 return E1000_SUCCESS;
682011ff
WD		 768}
769
770/******************************************************************************
aa070789 771 * Reads a 16 bit word from the EEPROM.
682011ff 772 *
aa070789
RZ		 773 * hw - Struct containing variables accessed by shared code
774 * offset - offset of word in the EEPROM to read
775 * data - word read from the EEPROM
682011ff 776 *****************************************************************************/
aa070789
RZ		 777static int32_t
778e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
779 uint16_t words, uint16_t *data)
682011ff 780{
aa070789
RZ		 781 struct e1000_eeprom_info *eeprom = &hw->eeprom;
782 uint32_t i = 0;
682011ff
WD		 783
784 DEBUGFUNC();
785
aa070789
RZ		 786 /* If eeprom is not yet detected, do so now */
787 if (eeprom->word_size == 0)
788 e1000_init_eeprom_params(hw);
789
790 /* A check for invalid values: offset too large, too many words,
791 * and not enough words.
792 */
793 if ((offset >= eeprom->word_size) ||
794 (words > eeprom->word_size - offset) ||
795 (words == 0)) {
796 DEBUGOUT("\"words\" parameter out of bounds."
797 "Words = %d, size = %d\n", offset, eeprom->word_size);
798 return -E1000_ERR_EEPROM;
799 }
800
801 /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
802 * directly. In this case, we need to acquire the EEPROM so that
803 * FW or other port software does not interrupt.
804 */
472d5460
YS		 805 if (e1000_is_onboard_nvm_eeprom(hw) == true &&
806 hw->eeprom.use_eerd == false) {
aa070789
RZ		 807
808 /* Prepare the EEPROM for bit-bang reading */
809 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
810 return -E1000_ERR_EEPROM;
811 }
812
813 /* Eerd register EEPROM access requires no eeprom aquire/release */
472d5460 814 if (eeprom->use_eerd == true)
aa070789
RZ		 815 return e1000_read_eeprom_eerd(hw, offset, words, data);
816
aa070789
RZ		 817 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have
818 * acquired the EEPROM at this point, so any returns should relase it */
819 if (eeprom->type == e1000_eeprom_spi) {
820 uint16_t word_in;
821 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
822
823 if (e1000_spi_eeprom_ready(hw)) {
824 e1000_release_eeprom(hw);
825 return -E1000_ERR_EEPROM;
826 }
827
828 e1000_standby_eeprom(hw);
829
830 /* Some SPI eeproms use the 8th address bit embedded in
831 * the opcode */
832 if ((eeprom->address_bits == 8) && (offset >= 128))
833 read_opcode |= EEPROM_A8_OPCODE_SPI;
834
835 /* Send the READ command (opcode + addr) */
836 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
837 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2),
838 eeprom->address_bits);
839
840 /* Read the data. The address of the eeprom internally
841 * increments with each byte (spi) being read, saving on the
842 * overhead of eeprom setup and tear-down. The address
843 * counter will roll over if reading beyond the size of
844 * the eeprom, thus allowing the entire memory to be read
845 * starting from any offset. */
846 for (i = 0; i < words; i++) {
847 word_in = e1000_shift_in_ee_bits(hw, 16);
848 data[i] = (word_in >> 8) | (word_in << 8);
849 }
850 } else if (eeprom->type == e1000_eeprom_microwire) {
851 for (i = 0; i < words; i++) {
852 /* Send the READ command (opcode + addr) */
853 e1000_shift_out_ee_bits(hw,
854 EEPROM_READ_OPCODE_MICROWIRE,
855 eeprom->opcode_bits);
856 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
857 eeprom->address_bits);
858
859 /* Read the data. For microwire, each word requires
860 * the overhead of eeprom setup and tear-down. */
861 data[i] = e1000_shift_in_ee_bits(hw, 16);
862 e1000_standby_eeprom(hw);
863 }
864 }
865
866 /* End this read operation */
867 e1000_release_eeprom(hw);
868
869 return E1000_SUCCESS;
870}
871
f1bcad22
HL		 872#ifndef CONFIG_DM_ETH
873/******************************************************************************
874 * e1000_write_eeprom_srwr - Write to Shadow Ram using EEWR
875 * @hw: pointer to the HW structure
876 * @offset: offset within the Shadow Ram to be written to
877 * @words: number of words to write
878 * @data: 16 bit word(s) to be written to the Shadow Ram
879 *
880 * Writes data to Shadow Ram at offset using EEWR register.
881 *
882 * If e1000_update_eeprom_checksum_i210 is not called after this function, the
883 * Shadow Ram will most likely contain an invalid checksum.
884 *****************************************************************************/
885static int32_t e1000_write_eeprom_srwr(struct e1000_hw *hw, uint16_t offset,
886 uint16_t words, uint16_t *data)
887{
888 struct e1000_eeprom_info *eeprom = &hw->eeprom;
889 uint32_t i, k, eewr = 0;
890 uint32_t attempts = 100000;
891 int32_t ret_val = 0;
892
893 /* A check for invalid values: offset too large, too many words,
894 * too many words for the offset, and not enough words.
895 */
896 if ((offset >= eeprom->word_size) ||
897 (words > (eeprom->word_size - offset)) || (words == 0)) {
898 DEBUGOUT("nvm parameter(s) out of bounds\n");
899 ret_val = -E1000_ERR_EEPROM;
900 goto out;
901 }
902
903 for (i = 0; i < words; i++) {
904 eewr = ((offset + i) << E1000_EEPROM_RW_ADDR_SHIFT)
905 | (data[i] << E1000_EEPROM_RW_REG_DATA) |
906 E1000_EEPROM_RW_REG_START;
907
908 E1000_WRITE_REG(hw, I210_EEWR, eewr);
909
910 for (k = 0; k < attempts; k++) {
911 if (E1000_EEPROM_RW_REG_DONE &
912 E1000_READ_REG(hw, I210_EEWR)) {
913 ret_val = 0;
914 break;
915 }
916 udelay(5);
917 }
918
919 if (ret_val) {
920 DEBUGOUT("Shadow RAM write EEWR timed out\n");
921 break;
922 }
923 }
924
925out:
926 return ret_val;
927}
928
929/******************************************************************************
930 * e1000_pool_flash_update_done_i210 - Pool FLUDONE status.
931 * @hw: pointer to the HW structure
932 *
933 *****************************************************************************/
934static int32_t e1000_pool_flash_update_done_i210(struct e1000_hw *hw)
935{
936 int32_t ret_val = -E1000_ERR_EEPROM;
937 uint32_t i, reg;
938
939 for (i = 0; i < E1000_FLUDONE_ATTEMPTS; i++) {
940 reg = E1000_READ_REG(hw, EECD);
941 if (reg & E1000_EECD_FLUDONE_I210) {
942 ret_val = 0;
943 break;
944 }
945 udelay(5);
946 }
947
948 return ret_val;
949}
950
951/******************************************************************************
952 * e1000_update_flash_i210 - Commit EEPROM to the flash
953 * @hw: pointer to the HW structure
954 *
955 *****************************************************************************/
956static int32_t e1000_update_flash_i210(struct e1000_hw *hw)
957{
958 int32_t ret_val = 0;
959 uint32_t flup;
960
961 ret_val = e1000_pool_flash_update_done_i210(hw);
962 if (ret_val == -E1000_ERR_EEPROM) {
963 DEBUGOUT("Flash update time out\n");
964 goto out;
965 }
966
967 flup = E1000_READ_REG(hw, EECD) | E1000_EECD_FLUPD_I210;
968 E1000_WRITE_REG(hw, EECD, flup);
969
970 ret_val = e1000_pool_flash_update_done_i210(hw);
971 if (ret_val)
972 DEBUGOUT("Flash update time out\n");
973 else
974 DEBUGOUT("Flash update complete\n");
975
976out:
977 return ret_val;
978}
979
980/******************************************************************************
981 * e1000_update_eeprom_checksum_i210 - Update EEPROM checksum
982 * @hw: pointer to the HW structure
983 *
984 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
985 * up to the checksum. Then calculates the EEPROM checksum and writes the
986 * value to the EEPROM. Next commit EEPROM data onto the Flash.
987 *****************************************************************************/
988static int32_t e1000_update_eeprom_checksum_i210(struct e1000_hw *hw)
989{
990 int32_t ret_val = 0;
991 uint16_t checksum = 0;
992 uint16_t i, nvm_data;
993
994 /* Read the first word from the EEPROM. If this times out or fails, do
995 * not continue or we could be in for a very long wait while every
996 * EEPROM read fails
997 */
998 ret_val = e1000_read_eeprom_eerd(hw, 0, 1, &nvm_data);
999 if (ret_val) {
1000 DEBUGOUT("EEPROM read failed\n");
1001 goto out;
1002 }
1003
1004 if (!(e1000_get_hw_eeprom_semaphore(hw))) {
1005 /* Do not use hw->nvm.ops.write, hw->nvm.ops.read
1006 * because we do not want to take the synchronization
1007 * semaphores twice here.
1008 */
1009
1010 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
1011 ret_val = e1000_read_eeprom_eerd(hw, i, 1, &nvm_data);
1012 if (ret_val) {
1013 e1000_put_hw_eeprom_semaphore(hw);
1014 DEBUGOUT("EEPROM Read Error while updating checksum.\n");
1015 goto out;
1016 }
1017 checksum += nvm_data;
1018 }
1019 checksum = (uint16_t)EEPROM_SUM - checksum;
1020 ret_val = e1000_write_eeprom_srwr(hw, EEPROM_CHECKSUM_REG, 1,
1021 &checksum);
1022 if (ret_val) {
1023 e1000_put_hw_eeprom_semaphore(hw);
1024 DEBUGOUT("EEPROM Write Error while updating checksum.\n");
1025 goto out;
1026 }
1027
1028 e1000_put_hw_eeprom_semaphore(hw);
1029
1030 ret_val = e1000_update_flash_i210(hw);
1031 } else {
1032 ret_val = -E1000_ERR_SWFW_SYNC;
1033 }
1034
1035out:
1036 return ret_val;
1037}
1038#endif
1039
aa070789
RZ		 1040/******************************************************************************
1041 * Verifies that the EEPROM has a valid checksum
1042 *
1043 * hw - Struct containing variables accessed by shared code
1044 *
1045 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
1046 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
1047 * valid.
1048 *****************************************************************************/
114d7fc0 1049static int e1000_validate_eeprom_checksum(struct e1000_hw *hw)
aa070789 1050{
114d7fc0 1051 uint16_t i, checksum, checksum_reg, *buf;
aa070789
RZ		 1052
1053 DEBUGFUNC();
1054
114d7fc0
KM		 1055 /* Allocate a temporary buffer */
1056 buf = malloc(sizeof(buf[0]) * (EEPROM_CHECKSUM_REG + 1));
1057 if (!buf) {
5c5e707a 1058 E1000_ERR(hw, "Unable to allocate EEPROM buffer!\n");
114d7fc0 1059 return -E1000_ERR_EEPROM;
aa070789
RZ		 1060 }
1061
114d7fc0
KM		 1062 /* Read the EEPROM */
1063 if (e1000_read_eeprom(hw, 0, EEPROM_CHECKSUM_REG + 1, buf) < 0) {
5c5e707a 1064 E1000_ERR(hw, "Unable to read EEPROM!\n");
aa070789
RZ		 1065 return -E1000_ERR_EEPROM;
1066 }
114d7fc0
KM		 1067
1068 /* Compute the checksum */
7a341066 1069 checksum = 0;
114d7fc0
KM		 1070 for (i = 0; i < EEPROM_CHECKSUM_REG; i++)
1071 checksum += buf[i];
1072 checksum = ((uint16_t)EEPROM_SUM) - checksum;
1073 checksum_reg = buf[i];
1074
1075 /* Verify it! */
1076 if (checksum == checksum_reg)
1077 return 0;
1078
1079 /* Hrm, verification failed, print an error */
5c5e707a
SG		 1080 E1000_ERR(hw, "EEPROM checksum is incorrect!\n");
1081 E1000_ERR(hw, " ...register was 0x%04hx, calculated 0x%04hx\n",
1082 checksum_reg, checksum);
114d7fc0
KM		 1083
1084 return -E1000_ERR_EEPROM;
aa070789 1085}
8712adfd 1086#endif /* CONFIG_E1000_NO_NVM */
ecbd2078
RZ		 1087
1088/*****************************************************************************
1089 * Set PHY to class A mode
1090 * Assumes the following operations will follow to enable the new class mode.
1091 * 1. Do a PHY soft reset
1092 * 2. Restart auto-negotiation or force link.
1093 *
1094 * hw - Struct containing variables accessed by shared code
1095 ****************************************************************************/
1096static int32_t
1097e1000_set_phy_mode(struct e1000_hw *hw)
1098{
8712adfd 1099#ifndef CONFIG_E1000_NO_NVM
ecbd2078
RZ		 1100 int32_t ret_val;
1101 uint16_t eeprom_data;
1102
1103 DEBUGFUNC();
1104
1105 if ((hw->mac_type == e1000_82545_rev_3) &&
1106 (hw->media_type == e1000_media_type_copper)) {
1107 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD,
1108 1, &eeprom_data);
1109 if (ret_val)
1110 return ret_val;
1111
1112 if ((eeprom_data != EEPROM_RESERVED_WORD) &&
1113 (eeprom_data & EEPROM_PHY_CLASS_A)) {
1114 ret_val = e1000_write_phy_reg(hw,
1115 M88E1000_PHY_PAGE_SELECT, 0x000B);
1116 if (ret_val)
1117 return ret_val;
1118 ret_val = e1000_write_phy_reg(hw,
1119 M88E1000_PHY_GEN_CONTROL, 0x8104);
1120 if (ret_val)
1121 return ret_val;
1122
472d5460 1123 hw->phy_reset_disable = false;
ecbd2078
RZ		 1124 }
1125 }
8712adfd 1126#endif
ecbd2078
RZ		 1127 return E1000_SUCCESS;
1128}
aa070789 1129
8712adfd 1130#ifndef CONFIG_E1000_NO_NVM
aa070789
RZ		 1131/***************************************************************************
1132 *
1133 * Obtaining software semaphore bit (SMBI) before resetting PHY.
1134 *
1135 * hw: Struct containing variables accessed by shared code
1136 *
1137 * returns: - E1000_ERR_RESET if fail to obtain semaphore.
1138 * E1000_SUCCESS at any other case.
1139 *
1140 ***************************************************************************/
1141static int32_t
1142e1000_get_software_semaphore(struct e1000_hw *hw)
1143{
1144 int32_t timeout = hw->eeprom.word_size + 1;
1145 uint32_t swsm;
1146
1147 DEBUGFUNC();
1148
f1bcad22 1149 if (hw->mac_type != e1000_80003es2lan && hw->mac_type != e1000_igb)
aa070789
RZ		 1150 return E1000_SUCCESS;
1151
1152 while (timeout) {
1153 swsm = E1000_READ_REG(hw, SWSM);
1154 /* If SMBI bit cleared, it is now set and we hold
1155 * the semaphore */
1156 if (!(swsm & E1000_SWSM_SMBI))
1157 break;
1158 mdelay(1);
1159 timeout--;
1160 }
1161
1162 if (!timeout) {
1163 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
1164 return -E1000_ERR_RESET;
1165 }
1166
1167 return E1000_SUCCESS;
1168}
8712adfd 1169#endif
aa070789
RZ		 1170
1171/***************************************************************************
1172 * This function clears HW semaphore bits.
1173 *
1174 * hw: Struct containing variables accessed by shared code
1175 *
1176 * returns: - None.
1177 *
1178 ***************************************************************************/
1179static void
1180e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
1181{
8712adfd 1182#ifndef CONFIG_E1000_NO_NVM
aa070789
RZ		 1183 uint32_t swsm;
1184
1185 DEBUGFUNC();
1186
1187 if (!hw->eeprom_semaphore_present)
1188 return;
1189
1190 swsm = E1000_READ_REG(hw, SWSM);
8f5672ea 1191 if (hw->mac_type == e1000_80003es2lan || hw->mac_type == e1000_igb) {
aa070789
RZ		 1192 /* Release both semaphores. */
1193 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1194 } else
1195 swsm &= ~(E1000_SWSM_SWESMBI);
1196 E1000_WRITE_REG(hw, SWSM, swsm);
8712adfd 1197#endif
aa070789
RZ		 1198}
1199
1200/***************************************************************************
1201 *
1202 * Using the combination of SMBI and SWESMBI semaphore bits when resetting
1203 * adapter or Eeprom access.
1204 *
1205 * hw: Struct containing variables accessed by shared code
1206 *
1207 * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
1208 * E1000_SUCCESS at any other case.
1209 *
1210 ***************************************************************************/
1211static int32_t
1212e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
1213{
8712adfd 1214#ifndef CONFIG_E1000_NO_NVM
aa070789
RZ		 1215 int32_t timeout;
1216 uint32_t swsm;
1217
1218 DEBUGFUNC();
1219
1220 if (!hw->eeprom_semaphore_present)
1221 return E1000_SUCCESS;
1222
f1bcad22 1223 if (hw->mac_type == e1000_80003es2lan || hw->mac_type == e1000_igb) {
aa070789
RZ		 1224 /* Get the SW semaphore. */
1225 if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
1226 return -E1000_ERR_EEPROM;
1227 }
1228
1229 /* Get the FW semaphore. */
1230 timeout = hw->eeprom.word_size + 1;
1231 while (timeout) {
1232 swsm = E1000_READ_REG(hw, SWSM);
1233 swsm |= E1000_SWSM_SWESMBI;
1234 E1000_WRITE_REG(hw, SWSM, swsm);
1235 /* if we managed to set the bit we got the semaphore. */
1236 swsm = E1000_READ_REG(hw, SWSM);
1237 if (swsm & E1000_SWSM_SWESMBI)
1238 break;
1239
1240 udelay(50);
1241 timeout--;
1242 }
1243
1244 if (!timeout) {
1245 /* Release semaphores */
1246 e1000_put_hw_eeprom_semaphore(hw);
1247 DEBUGOUT("Driver can't access the Eeprom - "
1248 "SWESMBI bit is set.\n");
1249 return -E1000_ERR_EEPROM;
1250 }
8712adfd 1251#endif
aa070789
RZ		 1252 return E1000_SUCCESS;
1253}
1254
7e2d991d 1255/* Take ownership of the PHY */
aa070789
RZ		 1256static int32_t
1257e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
1258{
1259 uint32_t swfw_sync = 0;
1260 uint32_t swmask = mask;
1261 uint32_t fwmask = mask << 16;
1262 int32_t timeout = 200;
1263
1264 DEBUGFUNC();
1265 while (timeout) {
1266 if (e1000_get_hw_eeprom_semaphore(hw))
1267 return -E1000_ERR_SWFW_SYNC;
1268
3c63dd53 1269 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
76f8cdb2 1270 if (!(swfw_sync & (fwmask | swmask)))
aa070789
RZ		 1271 break;
1272
1273 /* firmware currently using resource (fwmask) */
1274 /* or other software thread currently using resource (swmask) */
1275 e1000_put_hw_eeprom_semaphore(hw);
1276 mdelay(5);
1277 timeout--;
1278 }
1279
1280 if (!timeout) {
1281 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
1282 return -E1000_ERR_SWFW_SYNC;
1283 }
1284
1285 swfw_sync |= swmask;
1286 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
1287
1288 e1000_put_hw_eeprom_semaphore(hw);
1289 return E1000_SUCCESS;
1290}
1291
7e2d991d
TH		 1292static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask)
1293{
1294 uint32_t swfw_sync = 0;
1295
1296 DEBUGFUNC();
1297 while (e1000_get_hw_eeprom_semaphore(hw))
1298 ; /* Empty */
1299
1300 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
1301 swfw_sync &= ~mask;
1302 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
1303
1304 e1000_put_hw_eeprom_semaphore(hw);
1305}
1306
472d5460 1307static bool e1000_is_second_port(struct e1000_hw *hw)
987b43a1
KM		 1308{
1309 switch (hw->mac_type) {
1310 case e1000_80003es2lan:
1311 case e1000_82546:
1312 case e1000_82571:
1313 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
472d5460 1314 return true;
987b43a1
KM		 1315 /* Fallthrough */
1316 default:
472d5460 1317 return false;
987b43a1
KM		 1318 }
1319}
1320
8712adfd 1321#ifndef CONFIG_E1000_NO_NVM
aa070789 1322/******************************************************************************
e0a75fed 1323 * Reads the adapter's MAC address from the EEPROM
aa070789 1324 *
e0a75fed
HL		 1325 * hw - Struct containing variables accessed by shared code
1326 * enetaddr - buffering where the MAC address will be stored
aa070789 1327 *****************************************************************************/
e0a75fed
HL		 1328static int e1000_read_mac_addr_from_eeprom(struct e1000_hw *hw,
1329 unsigned char enetaddr[6])
aa070789 1330{
aa070789
RZ		 1331 uint16_t offset;
1332 uint16_t eeprom_data;
1333 int i;
1334
aa070789
RZ		 1335 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
1336 offset = i >> 1;
e0a75fed 1337 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
682011ff
WD		 1338 DEBUGOUT("EEPROM Read Error\n");
1339 return -E1000_ERR_EEPROM;
1340 }
5c5e707a
SG		 1341 enetaddr[i] = eeprom_data & 0xff;
1342 enetaddr[i + 1] = (eeprom_data >> 8) & 0xff;
682011ff 1343 }
987b43a1 1344
e0a75fed
HL		 1345 return 0;
1346}
1347
1348/******************************************************************************
1349 * Reads the adapter's MAC address from the RAL/RAH registers
1350 *
1351 * hw - Struct containing variables accessed by shared code
1352 * enetaddr - buffering where the MAC address will be stored
1353 *****************************************************************************/
1354static int e1000_read_mac_addr_from_regs(struct e1000_hw *hw,
1355 unsigned char enetaddr[6])
1356{
1357 uint16_t offset, tmp;
1358 uint32_t reg_data = 0;
1359 int i;
1360
1361 if (hw->mac_type != e1000_igb)
1362 return -E1000_ERR_MAC_TYPE;
1363
1364 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
1365 offset = i >> 1;
1366
1367 if (offset == 0)
1368 reg_data = E1000_READ_REG_ARRAY(hw, RA, 0);
1369 else if (offset == 1)
1370 reg_data >>= 16;
1371 else if (offset == 2)
1372 reg_data = E1000_READ_REG_ARRAY(hw, RA, 1);
1373 tmp = reg_data & 0xffff;
1374
1375 enetaddr[i] = tmp & 0xff;
1376 enetaddr[i + 1] = (tmp >> 8) & 0xff;
1377 }
1378
1379 return 0;
1380}
1381
1382/******************************************************************************
1383 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
1384 * second function of dual function devices
1385 *
1386 * hw - Struct containing variables accessed by shared code
1387 * enetaddr - buffering where the MAC address will be stored
1388 *****************************************************************************/
1389static int e1000_read_mac_addr(struct e1000_hw *hw, unsigned char enetaddr[6])
1390{
1391 int ret_val;
1392
1393 if (hw->mac_type == e1000_igb) {
1394 /* i210 preloads MAC address into RAL/RAH registers */
1395 ret_val = e1000_read_mac_addr_from_regs(hw, enetaddr);
1396 } else {
1397 ret_val = e1000_read_mac_addr_from_eeprom(hw, enetaddr);
1398 }
1399 if (ret_val)
1400 return ret_val;
1401
987b43a1
KM		 1402 /* Invert the last bit if this is the second device */
1403 if (e1000_is_second_port(hw))
5c5e707a 1404 enetaddr[5] ^= 1;
987b43a1 1405
682011ff
WD		 1406 return 0;
1407}
8712adfd 1408#endif
682011ff
WD		 1409
1410/******************************************************************************
1411 * Initializes receive address filters.
1412 *
8bde7f77 1413 * hw - Struct containing variables accessed by shared code
682011ff
WD		 1414 *
1415 * Places the MAC address in receive address register 0 and clears the rest
1416 * of the receive addresss registers. Clears the multicast table. Assumes
1417 * the receiver is in reset when the routine is called.
1418 *****************************************************************************/
1419static void
5c5e707a 1420e1000_init_rx_addrs(struct e1000_hw *hw, unsigned char enetaddr[6])
682011ff 1421{
682011ff
WD		 1422 uint32_t i;
1423 uint32_t addr_low;
1424 uint32_t addr_high;
1425
1426 DEBUGFUNC();
1427
1428 /* Setup the receive address. */
1429 DEBUGOUT("Programming MAC Address into RAR[0]\n");
5c5e707a
SG		 1430 addr_low = (enetaddr[0] |
1431 (enetaddr[1] << 8) |
1432 (enetaddr[2] << 16) | (enetaddr[3] << 24));
682011ff 1433
5c5e707a 1434 addr_high = (enetaddr[4] | (enetaddr[5] << 8) | E1000_RAH_AV);
682011ff
WD		 1435
1436 E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
1437 E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
1438
1439 /* Zero out the other 15 receive addresses. */
1440 DEBUGOUT("Clearing RAR[1-15]\n");
1441 for (i = 1; i < E1000_RAR_ENTRIES; i++) {
1442 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
1443 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
1444 }
1445}
1446
1447/******************************************************************************
1448 * Clears the VLAN filer table
1449 *
1450 * hw - Struct containing variables accessed by shared code
1451 *****************************************************************************/
1452static void
1453e1000_clear_vfta(struct e1000_hw *hw)
1454{
1455 uint32_t offset;
1456
1457 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
1458 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
1459}
1460
1461/******************************************************************************
1462 * Set the mac type member in the hw struct.
8bde7f77 1463 *
682011ff
WD		 1464 * hw - Struct containing variables accessed by shared code
1465 *****************************************************************************/
aa070789 1466int32_t
682011ff
WD		 1467e1000_set_mac_type(struct e1000_hw *hw)
1468{
1469 DEBUGFUNC();
1470
1471 switch (hw->device_id) {
1472 case E1000_DEV_ID_82542:
1473 switch (hw->revision_id) {
1474 case E1000_82542_2_0_REV_ID:
1475 hw->mac_type = e1000_82542_rev2_0;
1476 break;
1477 case E1000_82542_2_1_REV_ID:
1478 hw->mac_type = e1000_82542_rev2_1;
1479 break;
1480 default:
1481 /* Invalid 82542 revision ID */
1482 return -E1000_ERR_MAC_TYPE;
1483 }
1484 break;
1485 case E1000_DEV_ID_82543GC_FIBER:
1486 case E1000_DEV_ID_82543GC_COPPER:
1487 hw->mac_type = e1000_82543;
1488 break;
1489 case E1000_DEV_ID_82544EI_COPPER:
1490 case E1000_DEV_ID_82544EI_FIBER:
1491 case E1000_DEV_ID_82544GC_COPPER:
1492 case E1000_DEV_ID_82544GC_LOM:
1493 hw->mac_type = e1000_82544;
1494 break;
1495 case E1000_DEV_ID_82540EM:
1496 case E1000_DEV_ID_82540EM_LOM:
aa070789
RZ		 1497 case E1000_DEV_ID_82540EP:
1498 case E1000_DEV_ID_82540EP_LOM:
1499 case E1000_DEV_ID_82540EP_LP:
682011ff
WD		 1500 hw->mac_type = e1000_82540;
1501 break;
1502 case E1000_DEV_ID_82545EM_COPPER:
1503 case E1000_DEV_ID_82545EM_FIBER:
1504 hw->mac_type = e1000_82545;
1505 break;
aa070789
RZ		 1506 case E1000_DEV_ID_82545GM_COPPER:
1507 case E1000_DEV_ID_82545GM_FIBER:
1508 case E1000_DEV_ID_82545GM_SERDES:
1509 hw->mac_type = e1000_82545_rev_3;
1510 break;
682011ff
WD		 1511 case E1000_DEV_ID_82546EB_COPPER:
1512 case E1000_DEV_ID_82546EB_FIBER:
aa070789 1513 case E1000_DEV_ID_82546EB_QUAD_COPPER:
682011ff
WD		 1514 hw->mac_type = e1000_82546;
1515 break;
aa070789
RZ		 1516 case E1000_DEV_ID_82546GB_COPPER:
1517 case E1000_DEV_ID_82546GB_FIBER:
1518 case E1000_DEV_ID_82546GB_SERDES:
1519 case E1000_DEV_ID_82546GB_PCIE:
1520 case E1000_DEV_ID_82546GB_QUAD_COPPER:
1521 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
1522 hw->mac_type = e1000_82546_rev_3;
1523 break;
1524 case E1000_DEV_ID_82541EI:
1525 case E1000_DEV_ID_82541EI_MOBILE:
1526 case E1000_DEV_ID_82541ER_LOM:
1527 hw->mac_type = e1000_82541;
1528 break;
ac3315c2 1529 case E1000_DEV_ID_82541ER:
aa070789 1530 case E1000_DEV_ID_82541GI:
aa3b8bf9 1531 case E1000_DEV_ID_82541GI_LF:
aa070789 1532 case E1000_DEV_ID_82541GI_MOBILE:
1aeed8d7
WD		 1533 hw->mac_type = e1000_82541_rev_2;
1534 break;
aa070789
RZ		 1535 case E1000_DEV_ID_82547EI:
1536 case E1000_DEV_ID_82547EI_MOBILE:
1537 hw->mac_type = e1000_82547;
1538 break;
1539 case E1000_DEV_ID_82547GI:
1540 hw->mac_type = e1000_82547_rev_2;
1541 break;
1542 case E1000_DEV_ID_82571EB_COPPER:
1543 case E1000_DEV_ID_82571EB_FIBER:
1544 case E1000_DEV_ID_82571EB_SERDES:
1545 case E1000_DEV_ID_82571EB_SERDES_DUAL:
1546 case E1000_DEV_ID_82571EB_SERDES_QUAD:
1547 case E1000_DEV_ID_82571EB_QUAD_COPPER:
1548 case E1000_DEV_ID_82571PT_QUAD_COPPER:
1549 case E1000_DEV_ID_82571EB_QUAD_FIBER:
1550 case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
1551 hw->mac_type = e1000_82571;
1552 break;
1553 case E1000_DEV_ID_82572EI_COPPER:
1554 case E1000_DEV_ID_82572EI_FIBER:
1555 case E1000_DEV_ID_82572EI_SERDES:
1556 case E1000_DEV_ID_82572EI:
1557 hw->mac_type = e1000_82572;
1558 break;
1559 case E1000_DEV_ID_82573E:
1560 case E1000_DEV_ID_82573E_IAMT:
1561 case E1000_DEV_ID_82573L:
1562 hw->mac_type = e1000_82573;
1563 break;
2c2668f9
RZ		 1564 case E1000_DEV_ID_82574L:
1565 hw->mac_type = e1000_82574;
1566 break;
aa070789
RZ		 1567 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
1568 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
1569 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
1570 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
1571 hw->mac_type = e1000_80003es2lan;
1572 break;
1573 case E1000_DEV_ID_ICH8_IGP_M_AMT:
1574 case E1000_DEV_ID_ICH8_IGP_AMT:
1575 case E1000_DEV_ID_ICH8_IGP_C:
1576 case E1000_DEV_ID_ICH8_IFE:
1577 case E1000_DEV_ID_ICH8_IFE_GT:
1578 case E1000_DEV_ID_ICH8_IFE_G:
1579 case E1000_DEV_ID_ICH8_IGP_M:
1580 hw->mac_type = e1000_ich8lan;
1581 break;
6c499abe
MZ		 1582 case PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED:
1583 case PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED:
95186063 1584 case PCI_DEVICE_ID_INTEL_I210_COPPER:
6c499abe 1585 case PCI_DEVICE_ID_INTEL_I211_COPPER:
95186063
MV		 1586 case PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS:
1587 case PCI_DEVICE_ID_INTEL_I210_SERDES:
1588 case PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS:
1589 case PCI_DEVICE_ID_INTEL_I210_1000BASEKX:
1590 hw->mac_type = e1000_igb;
1591 break;
682011ff
WD		 1592 default:
1593 /* Should never have loaded on this device */
1594 return -E1000_ERR_MAC_TYPE;
1595 }
1596 return E1000_SUCCESS;
1597}
1598
1599/******************************************************************************
1600 * Reset the transmit and receive units; mask and clear all interrupts.
1601 *
1602 * hw - Struct containing variables accessed by shared code
1603 *****************************************************************************/
1604void
1605e1000_reset_hw(struct e1000_hw *hw)
1606{
1607 uint32_t ctrl;
1608 uint32_t ctrl_ext;
682011ff 1609 uint32_t manc;
9ea005fb 1610 uint32_t pba = 0;
95186063 1611 uint32_t reg;
682011ff
WD		 1612
1613 DEBUGFUNC();
1614
9ea005fb
RZ		 1615 /* get the correct pba value for both PCI and PCIe*/
1616 if (hw->mac_type < e1000_82571)
1617 pba = E1000_DEFAULT_PCI_PBA;
1618 else
1619 pba = E1000_DEFAULT_PCIE_PBA;
1620
682011ff
WD		 1621 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
1622 if (hw->mac_type == e1000_82542_rev2_0) {
1623 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
81dab9af
BM		 1624#ifdef CONFIG_DM_ETH
1625 dm_pci_write_config16(hw->pdev, PCI_COMMAND,
1626 hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1627#else
682011ff 1628 pci_write_config_word(hw->pdev, PCI_COMMAND,
aa070789 1629 hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
81dab9af 1630#endif
682011ff
WD		 1631 }
1632
1633 /* Clear interrupt mask to stop board from generating interrupts */
1634 DEBUGOUT("Masking off all interrupts\n");
95186063
MV		 1635 if (hw->mac_type == e1000_igb)
1636 E1000_WRITE_REG(hw, I210_IAM, 0);
682011ff
WD		 1637 E1000_WRITE_REG(hw, IMC, 0xffffffff);
1638
1639 /* Disable the Transmit and Receive units. Then delay to allow
1640 * any pending transactions to complete before we hit the MAC with
1641 * the global reset.
1642 */
1643 E1000_WRITE_REG(hw, RCTL, 0);
1644 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
1645 E1000_WRITE_FLUSH(hw);
1646
c90778ad
CG		 1647 if (hw->mac_type == e1000_igb) {
1648 E1000_WRITE_REG(hw, RXPBS, I210_RXPBSIZE_DEFAULT);
1649 E1000_WRITE_REG(hw, TXPBS, I210_TXPBSIZE_DEFAULT);
1650 }
1651
682011ff 1652 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
472d5460 1653 hw->tbi_compatibility_on = false;
682011ff
WD		 1654
1655 /* Delay to allow any outstanding PCI transactions to complete before
1656 * resetting the device
1657 */
1658 mdelay(10);
1659
1660 /* Issue a global reset to the MAC. This will reset the chip's
1661 * transmit, receive, DMA, and link units. It will not effect
1662 * the current PCI configuration. The global reset bit is self-
1663 * clearing, and should clear within a microsecond.
1664 */
1665 DEBUGOUT("Issuing a global reset to MAC\n");
1666 ctrl = E1000_READ_REG(hw, CTRL);
1667
aa070789 1668 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
682011ff
WD		 1669
1670 /* Force a reload from the EEPROM if necessary */
95186063
MV		 1671 if (hw->mac_type == e1000_igb) {
1672 mdelay(20);
1673 reg = E1000_READ_REG(hw, STATUS);
1674 if (reg & E1000_STATUS_PF_RST_DONE)
1675 DEBUGOUT("PF OK\n");
1676 reg = E1000_READ_REG(hw, I210_EECD);
1677 if (reg & E1000_EECD_AUTO_RD)
1678 DEBUGOUT("EEC OK\n");
1679 } else if (hw->mac_type < e1000_82540) {
682011ff
WD		 1680 /* Wait for reset to complete */
1681 udelay(10);
1682 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1683 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1684 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1685 E1000_WRITE_FLUSH(hw);
1686 /* Wait for EEPROM reload */
1687 mdelay(2);
1688 } else {
1689 /* Wait for EEPROM reload (it happens automatically) */
1690 mdelay(4);
1691 /* Dissable HW ARPs on ASF enabled adapters */
1692 manc = E1000_READ_REG(hw, MANC);
1693 manc &= ~(E1000_MANC_ARP_EN);
1694 E1000_WRITE_REG(hw, MANC, manc);
1695 }
1696
1697 /* Clear interrupt mask to stop board from generating interrupts */
1698 DEBUGOUT("Masking off all interrupts\n");
95186063
MV		 1699 if (hw->mac_type == e1000_igb)
1700 E1000_WRITE_REG(hw, I210_IAM, 0);
682011ff
WD		 1701 E1000_WRITE_REG(hw, IMC, 0xffffffff);
1702
1703 /* Clear any pending interrupt events. */
56b13b1e 1704 E1000_READ_REG(hw, ICR);
682011ff
WD		 1705
1706 /* If MWI was previously enabled, reenable it. */
1707 if (hw->mac_type == e1000_82542_rev2_0) {
81dab9af
BM		 1708#ifdef CONFIG_DM_ETH
1709 dm_pci_write_config16(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1710#else
682011ff 1711 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
81dab9af 1712#endif
682011ff 1713 }
95186063
MV		 1714 if (hw->mac_type != e1000_igb)
1715 E1000_WRITE_REG(hw, PBA, pba);
aa070789
RZ		 1716}
1717
1718/******************************************************************************
1719 *
1720 * Initialize a number of hardware-dependent bits
1721 *
1722 * hw: Struct containing variables accessed by shared code
1723 *
1724 * This function contains hardware limitation workarounds for PCI-E adapters
1725 *
1726 *****************************************************************************/
1727static void
1728e1000_initialize_hardware_bits(struct e1000_hw *hw)
1729{
1730 if ((hw->mac_type >= e1000_82571) &&
1731 (!hw->initialize_hw_bits_disable)) {
1732 /* Settings common to all PCI-express silicon */
1733 uint32_t reg_ctrl, reg_ctrl_ext;
1734 uint32_t reg_tarc0, reg_tarc1;
1735 uint32_t reg_tctl;
1736 uint32_t reg_txdctl, reg_txdctl1;
1737
1738 /* link autonegotiation/sync workarounds */
1739 reg_tarc0 = E1000_READ_REG(hw, TARC0);
1740 reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
1741
1742 /* Enable not-done TX descriptor counting */
1743 reg_txdctl = E1000_READ_REG(hw, TXDCTL);
1744 reg_txdctl |= E1000_TXDCTL_COUNT_DESC;
1745 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
1746
1747 reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1);
1748 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
1749 E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
1750
95186063 1751
aa070789 1752 switch (hw->mac_type) {
063bb708
AP		 1753 case e1000_igb: /* IGB is cool */
1754 return;
aa070789
RZ		 1755 case e1000_82571:
1756 case e1000_82572:
1757 /* Clear PHY TX compatible mode bits */
1758 reg_tarc1 = E1000_READ_REG(hw, TARC1);
1759 reg_tarc1 &= ~((1 << 30)|(1 << 29));
1760
1761 /* link autonegotiation/sync workarounds */
1762 reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23));
1763
1764 /* TX ring control fixes */
1765 reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24));
1766
1767 /* Multiple read bit is reversed polarity */
1768 reg_tctl = E1000_READ_REG(hw, TCTL);
1769 if (reg_tctl & E1000_TCTL_MULR)
1770 reg_tarc1 &= ~(1 << 28);
1771 else
1772 reg_tarc1 |= (1 << 28);
1773
1774 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1775 break;
1776 case e1000_82573:
2c2668f9 1777 case e1000_82574:
aa070789
RZ		 1778 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1779 reg_ctrl_ext &= ~(1 << 23);
1780 reg_ctrl_ext |= (1 << 22);
1781
1782 /* TX byte count fix */
1783 reg_ctrl = E1000_READ_REG(hw, CTRL);
1784 reg_ctrl &= ~(1 << 29);
1785
1786 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
1787 E1000_WRITE_REG(hw, CTRL, reg_ctrl);
1788 break;
1789 case e1000_80003es2lan:
1790 /* improve small packet performace for fiber/serdes */
1791 if ((hw->media_type == e1000_media_type_fiber)
1792 || (hw->media_type ==
1793 e1000_media_type_internal_serdes)) {
1794 reg_tarc0 &= ~(1 << 20);
1795 }
1796
1797 /* Multiple read bit is reversed polarity */
1798 reg_tctl = E1000_READ_REG(hw, TCTL);
1799 reg_tarc1 = E1000_READ_REG(hw, TARC1);
1800 if (reg_tctl & E1000_TCTL_MULR)
1801 reg_tarc1 &= ~(1 << 28);
1802 else
1803 reg_tarc1 |= (1 << 28);
1804
1805 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1806 break;
1807 case e1000_ich8lan:
1808 /* Reduce concurrent DMA requests to 3 from 4 */
1809 if ((hw->revision_id < 3) ||
1810 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
1811 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
1812 reg_tarc0 |= ((1 << 29)|(1 << 28));
1813
1814 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1815 reg_ctrl_ext |= (1 << 22);
1816 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
1817
1818 /* workaround TX hang with TSO=on */
1819 reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23));
1820
1821 /* Multiple read bit is reversed polarity */
1822 reg_tctl = E1000_READ_REG(hw, TCTL);
1823 reg_tarc1 = E1000_READ_REG(hw, TARC1);
1824 if (reg_tctl & E1000_TCTL_MULR)
1825 reg_tarc1 &= ~(1 << 28);
1826 else
1827 reg_tarc1 |= (1 << 28);
1828
1829 /* workaround TX hang with TSO=on */
1830 reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24));
1831
1832 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1833 break;
1834 default:
1835 break;
1836 }
1837
1838 E1000_WRITE_REG(hw, TARC0, reg_tarc0);
1839 }
682011ff
WD		 1840}
1841
1842/******************************************************************************
1843 * Performs basic configuration of the adapter.
1844 *
1845 * hw - Struct containing variables accessed by shared code
8bde7f77
WD		 1846 *
1847 * Assumes that the controller has previously been reset and is in a
682011ff
WD		 1848 * post-reset uninitialized state. Initializes the receive address registers,
1849 * multicast table, and VLAN filter table. Calls routines to setup link
1850 * configuration and flow control settings. Clears all on-chip counters. Leaves
1851 * the transmit and receive units disabled and uninitialized.
1852 *****************************************************************************/
1853static int
5c5e707a 1854e1000_init_hw(struct e1000_hw *hw, unsigned char enetaddr[6])
682011ff 1855{
aa070789 1856 uint32_t ctrl;
682011ff
WD		 1857 uint32_t i;
1858 int32_t ret_val;
1859 uint16_t pcix_cmd_word;
1860 uint16_t pcix_stat_hi_word;
1861 uint16_t cmd_mmrbc;
1862 uint16_t stat_mmrbc;
aa070789
RZ		 1863 uint32_t mta_size;
1864 uint32_t reg_data;
1865 uint32_t ctrl_ext;
682011ff 1866 DEBUGFUNC();
aa070789
RZ		 1867 /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
1868 if ((hw->mac_type == e1000_ich8lan) &&
1869 ((hw->revision_id < 3) ||
1870 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
1871 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
1872 reg_data = E1000_READ_REG(hw, STATUS);
1873 reg_data &= ~0x80000000;
1874 E1000_WRITE_REG(hw, STATUS, reg_data);
682011ff 1875 }
aa070789 1876 /* Do not need initialize Identification LED */
682011ff 1877
aa070789
RZ		 1878 /* Set the media type and TBI compatibility */
1879 e1000_set_media_type(hw);
1880
1881 /* Must be called after e1000_set_media_type
1882 * because media_type is used */
1883 e1000_initialize_hardware_bits(hw);
682011ff
WD		 1884
1885 /* Disabling VLAN filtering. */
1886 DEBUGOUT("Initializing the IEEE VLAN\n");
aa070789
RZ		 1887 /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
1888 if (hw->mac_type != e1000_ich8lan) {
1889 if (hw->mac_type < e1000_82545_rev_3)
1890 E1000_WRITE_REG(hw, VET, 0);
1891 e1000_clear_vfta(hw);
1892 }
682011ff
WD		 1893
1894 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
1895 if (hw->mac_type == e1000_82542_rev2_0) {
1896 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
81dab9af
BM		 1897#ifdef CONFIG_DM_ETH
1898 dm_pci_write_config16(hw->pdev, PCI_COMMAND,
1899 hw->
1900 pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1901#else
682011ff
WD		 1902 pci_write_config_word(hw->pdev, PCI_COMMAND,
1903 hw->
1904 pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
81dab9af 1905#endif
682011ff
WD		 1906 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
1907 E1000_WRITE_FLUSH(hw);
1908 mdelay(5);
1909 }
1910
1911 /* Setup the receive address. This involves initializing all of the Receive
1912 * Address Registers (RARs 0 - 15).
1913 */
5c5e707a 1914 e1000_init_rx_addrs(hw, enetaddr);
682011ff
WD		 1915
1916 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
1917 if (hw->mac_type == e1000_82542_rev2_0) {
1918 E1000_WRITE_REG(hw, RCTL, 0);
1919 E1000_WRITE_FLUSH(hw);
1920 mdelay(1);
81dab9af
BM		 1921#ifdef CONFIG_DM_ETH
1922 dm_pci_write_config16(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1923#else
682011ff 1924 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
81dab9af 1925#endif
682011ff
WD		 1926 }
1927
1928 /* Zero out the Multicast HASH table */
1929 DEBUGOUT("Zeroing the MTA\n");
aa070789
RZ		 1930 mta_size = E1000_MC_TBL_SIZE;
1931 if (hw->mac_type == e1000_ich8lan)
1932 mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
1933 for (i = 0; i < mta_size; i++) {
682011ff 1934 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
aa070789
RZ		 1935 /* use write flush to prevent Memory Write Block (MWB) from
1936 * occuring when accessing our register space */
1937 E1000_WRITE_FLUSH(hw);
1938 }
e97f7fbb 1939
aa070789
RZ		 1940 switch (hw->mac_type) {
1941 case e1000_82545_rev_3:
1942 case e1000_82546_rev_3:
95186063 1943 case e1000_igb:
aa070789
RZ		 1944 break;
1945 default:
682011ff 1946 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
aa070789 1947 if (hw->bus_type == e1000_bus_type_pcix) {
81dab9af
BM		 1948#ifdef CONFIG_DM_ETH
1949 dm_pci_read_config16(hw->pdev, PCIX_COMMAND_REGISTER,
1950 &pcix_cmd_word);
1951 dm_pci_read_config16(hw->pdev, PCIX_STATUS_REGISTER_HI,
1952 &pcix_stat_hi_word);
1953#else
682011ff
WD		 1954 pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
1955 &pcix_cmd_word);
1956 pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI,
1957 &pcix_stat_hi_word);
81dab9af 1958#endif
682011ff
WD		 1959 cmd_mmrbc =
1960 (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
1961 PCIX_COMMAND_MMRBC_SHIFT;
1962 stat_mmrbc =
1963 (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
1964 PCIX_STATUS_HI_MMRBC_SHIFT;
1965 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
1966 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
1967 if (cmd_mmrbc > stat_mmrbc) {
1968 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
1969 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
81dab9af
BM		 1970#ifdef CONFIG_DM_ETH
1971 dm_pci_write_config16(hw->pdev, PCIX_COMMAND_REGISTER,
1972 pcix_cmd_word);
1973#else
682011ff
WD		 1974 pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
1975 pcix_cmd_word);
81dab9af 1976#endif
682011ff
WD		 1977 }
1978 }
aa070789
RZ		 1979 break;
1980 }
1981
1982 /* More time needed for PHY to initialize */
1983 if (hw->mac_type == e1000_ich8lan)
1984 mdelay(15);
95186063
MV		 1985 if (hw->mac_type == e1000_igb)
1986 mdelay(15);
682011ff
WD		 1987
1988 /* Call a subroutine to configure the link and setup flow control. */
5c5e707a 1989 ret_val = e1000_setup_link(hw);
682011ff
WD		 1990
1991 /* Set the transmit descriptor write-back policy */
1992 if (hw->mac_type > e1000_82544) {
1993 ctrl = E1000_READ_REG(hw, TXDCTL);
1994 ctrl =
1995 (ctrl & ~E1000_TXDCTL_WTHRESH) |
1996 E1000_TXDCTL_FULL_TX_DESC_WB;
1997 E1000_WRITE_REG(hw, TXDCTL, ctrl);
1998 }
aa070789 1999
776e66e8 2000 /* Set the receive descriptor write back policy */
776e66e8
RG		 2001 if (hw->mac_type >= e1000_82571) {
2002 ctrl = E1000_READ_REG(hw, RXDCTL);
2003 ctrl =
2004 (ctrl & ~E1000_RXDCTL_WTHRESH) |
2005 E1000_RXDCTL_FULL_RX_DESC_WB;
2006 E1000_WRITE_REG(hw, RXDCTL, ctrl);
2007 }
2008
aa070789
RZ		 2009 switch (hw->mac_type) {
2010 default:
2011 break;
2012 case e1000_80003es2lan:
2013 /* Enable retransmit on late collisions */
2014 reg_data = E1000_READ_REG(hw, TCTL);
2015 reg_data |= E1000_TCTL_RTLC;
2016 E1000_WRITE_REG(hw, TCTL, reg_data);
2017
2018 /* Configure Gigabit Carry Extend Padding */
2019 reg_data = E1000_READ_REG(hw, TCTL_EXT);
2020 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
2021 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
2022 E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
2023
2024 /* Configure Transmit Inter-Packet Gap */
2025 reg_data = E1000_READ_REG(hw, TIPG);
2026 reg_data &= ~E1000_TIPG_IPGT_MASK;
2027 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
2028 E1000_WRITE_REG(hw, TIPG, reg_data);
2029
2030 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
2031 reg_data &= ~0x00100000;
2032 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
2033 /* Fall through */
2034 case e1000_82571:
2035 case e1000_82572:
2036 case e1000_ich8lan:
2037 ctrl = E1000_READ_REG(hw, TXDCTL1);
2038 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH)
2039 | E1000_TXDCTL_FULL_TX_DESC_WB;
2040 E1000_WRITE_REG(hw, TXDCTL1, ctrl);
2041 break;
2c2668f9
RZ		 2042 case e1000_82573:
2043 case e1000_82574:
2044 reg_data = E1000_READ_REG(hw, GCR);
2045 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
2046 E1000_WRITE_REG(hw, GCR, reg_data);
95186063
MV		 2047 case e1000_igb:
2048 break;
aa070789
RZ		 2049 }
2050
aa070789
RZ		 2051 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
2052 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
2053 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
2054 /* Relaxed ordering must be disabled to avoid a parity
2055 * error crash in a PCI slot. */
2056 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
2057 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
2058 }
2059
682011ff
WD		 2060 return ret_val;
2061}
2062
2063/******************************************************************************
2064 * Configures flow control and link settings.
8bde7f77 2065 *
682011ff 2066 * hw - Struct containing variables accessed by shared code
8bde7f77 2067 *
682011ff
WD		 2068 * Determines which flow control settings to use. Calls the apropriate media-
2069 * specific link configuration function. Configures the flow control settings.
2070 * Assuming the adapter has a valid link partner, a valid link should be
8bde7f77 2071 * established. Assumes the hardware has previously been reset and the
682011ff
WD		 2072 * transmitter and receiver are not enabled.
2073 *****************************************************************************/
2074static int
5c5e707a 2075e1000_setup_link(struct e1000_hw *hw)
682011ff 2076{
682011ff 2077 int32_t ret_val;
8712adfd
RI		 2078#ifndef CONFIG_E1000_NO_NVM
2079 uint32_t ctrl_ext;
682011ff 2080 uint16_t eeprom_data;
8712adfd 2081#endif
682011ff
WD		 2082
2083 DEBUGFUNC();
2084
aa070789
RZ		 2085 /* In the case of the phy reset being blocked, we already have a link.
2086 * We do not have to set it up again. */
2087 if (e1000_check_phy_reset_block(hw))
2088 return E1000_SUCCESS;
2089
8712adfd 2090#ifndef CONFIG_E1000_NO_NVM
682011ff
WD		 2091 /* Read and store word 0x0F of the EEPROM. This word contains bits
2092 * that determine the hardware's default PAUSE (flow control) mode,
2093 * a bit that determines whether the HW defaults to enabling or
2094 * disabling auto-negotiation, and the direction of the
2095 * SW defined pins. If there is no SW over-ride of the flow
2096 * control setting, then the variable hw->fc will
2097 * be initialized based on a value in the EEPROM.
2098 */
aa070789
RZ		 2099 if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1,
2100 &eeprom_data) < 0) {
682011ff
WD		 2101 DEBUGOUT("EEPROM Read Error\n");
2102 return -E1000_ERR_EEPROM;
2103 }
8712adfd 2104#endif
682011ff 2105 if (hw->fc == e1000_fc_default) {
aa070789
RZ		 2106 switch (hw->mac_type) {
2107 case e1000_ich8lan:
2108 case e1000_82573:
2c2668f9 2109 case e1000_82574:
95186063 2110 case e1000_igb:
682011ff 2111 hw->fc = e1000_fc_full;
aa070789
RZ		 2112 break;
2113 default:
8712adfd 2114#ifndef CONFIG_E1000_NO_NVM
aa070789
RZ		 2115 ret_val = e1000_read_eeprom(hw,
2116 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
2117 if (ret_val) {
2118 DEBUGOUT("EEPROM Read Error\n");
2119 return -E1000_ERR_EEPROM;
2120 }
aa070789
RZ		 2121 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
2122 hw->fc = e1000_fc_none;
2123 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
2124 EEPROM_WORD0F_ASM_DIR)
2125 hw->fc = e1000_fc_tx_pause;
2126 else
8712adfd 2127#endif
aa070789
RZ		 2128 hw->fc = e1000_fc_full;
2129 break;
2130 }
682011ff
WD		 2131 }
2132
2133 /* We want to save off the original Flow Control configuration just
2134 * in case we get disconnected and then reconnected into a different
2135 * hub or switch with different Flow Control capabilities.
2136 */
2137 if (hw->mac_type == e1000_82542_rev2_0)
2138 hw->fc &= (~e1000_fc_tx_pause);
2139
2140 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
2141 hw->fc &= (~e1000_fc_rx_pause);
2142
2143 hw->original_fc = hw->fc;
2144
2145 DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc);
2146
8712adfd 2147#ifndef CONFIG_E1000_NO_NVM
682011ff
WD		 2148 /* Take the 4 bits from EEPROM word 0x0F that determine the initial
2149 * polarity value for the SW controlled pins, and setup the
2150 * Extended Device Control reg with that info.
2151 * This is needed because one of the SW controlled pins is used for
2152 * signal detection. So this should be done before e1000_setup_pcs_link()
2153 * or e1000_phy_setup() is called.
2154 */
2155 if (hw->mac_type == e1000_82543) {
2156 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
2157 SWDPIO__EXT_SHIFT);
2158 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
2159 }
8712adfd 2160#endif
682011ff
WD		 2161
2162 /* Call the necessary subroutine to configure the link. */
2163 ret_val = (hw->media_type == e1000_media_type_fiber) ?
5c5e707a 2164 e1000_setup_fiber_link(hw) : e1000_setup_copper_link(hw);
682011ff
WD		 2165 if (ret_val < 0) {
2166 return ret_val;
2167 }
2168
2169 /* Initialize the flow control address, type, and PAUSE timer
2170 * registers to their default values. This is done even if flow
2171 * control is disabled, because it does not hurt anything to
2172 * initialize these registers.
2173 */
aa070789
RZ		 2174 DEBUGOUT("Initializing the Flow Control address, type"
2175 "and timer regs\n");
2176
2177 /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
2178 if (hw->mac_type != e1000_ich8lan) {
2179 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
2180 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
2181 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
2182 }
682011ff 2183
682011ff
WD		 2184 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
2185
2186 /* Set the flow control receive threshold registers. Normally,
2187 * these registers will be set to a default threshold that may be
2188 * adjusted later by the driver's runtime code. However, if the
2189 * ability to transmit pause frames in not enabled, then these
8bde7f77 2190 * registers will be set to 0.
682011ff
WD		 2191 */
2192 if (!(hw->fc & e1000_fc_tx_pause)) {
2193 E1000_WRITE_REG(hw, FCRTL, 0);
2194 E1000_WRITE_REG(hw, FCRTH, 0);
2195 } else {
2196 /* We need to set up the Receive Threshold high and low water marks
2197 * as well as (optionally) enabling the transmission of XON frames.
2198 */
2199 if (hw->fc_send_xon) {
2200 E1000_WRITE_REG(hw, FCRTL,
2201 (hw->fc_low_water | E1000_FCRTL_XONE));
2202 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
2203 } else {
2204 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
2205 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
2206 }
2207 }
2208 return ret_val;
2209}
2210
2211/******************************************************************************
2212 * Sets up link for a fiber based adapter
2213 *
2214 * hw - Struct containing variables accessed by shared code
2215 *
2216 * Manipulates Physical Coding Sublayer functions in order to configure
2217 * link. Assumes the hardware has been previously reset and the transmitter
2218 * and receiver are not enabled.
2219 *****************************************************************************/
2220static int
5c5e707a 2221e1000_setup_fiber_link(struct e1000_hw *hw)
682011ff 2222{
682011ff
WD		 2223 uint32_t ctrl;
2224 uint32_t status;
2225 uint32_t txcw = 0;
2226 uint32_t i;
2227 uint32_t signal;
2228 int32_t ret_val;
2229
2230 DEBUGFUNC();
8bde7f77
WD		 2231 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
2232 * set when the optics detect a signal. On older adapters, it will be
682011ff
WD		 2233 * cleared when there is a signal
2234 */
2235 ctrl = E1000_READ_REG(hw, CTRL);
2236 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
2237 signal = E1000_CTRL_SWDPIN1;
2238 else
2239 signal = 0;
2240
5c5e707a 2241 printf("signal for %s is %x (ctrl %08x)!!!!\n", hw->name, signal,
682011ff
WD		 2242 ctrl);
2243 /* Take the link out of reset */
2244 ctrl &= ~(E1000_CTRL_LRST);
2245
2246 e1000_config_collision_dist(hw);
2247
2248 /* Check for a software override of the flow control settings, and setup
2249 * the device accordingly. If auto-negotiation is enabled, then software
2250 * will have to set the "PAUSE" bits to the correct value in the Tranmsit
2251 * Config Word Register (TXCW) and re-start auto-negotiation. However, if
8bde7f77 2252 * auto-negotiation is disabled, then software will have to manually
682011ff
WD		 2253 * configure the two flow control enable bits in the CTRL register.
2254 *
2255 * The possible values of the "fc" parameter are:
1aeed8d7
WD		 2256 * 0: Flow control is completely disabled
2257 * 1: Rx flow control is enabled (we can receive pause frames, but
2258 * not send pause frames).
2259 * 2: Tx flow control is enabled (we can send pause frames but we do
2260 * not support receiving pause frames).
2261 * 3: Both Rx and TX flow control (symmetric) are enabled.
682011ff
WD		 2262 */
2263 switch (hw->fc) {
2264 case e1000_fc_none:
2265 /* Flow control is completely disabled by a software over-ride. */
2266 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
2267 break;
2268 case e1000_fc_rx_pause:
8bde7f77
WD		 2269 /* RX Flow control is enabled and TX Flow control is disabled by a
2270 * software over-ride. Since there really isn't a way to advertise
682011ff
WD		 2271 * that we are capable of RX Pause ONLY, we will advertise that we
2272 * support both symmetric and asymmetric RX PAUSE. Later, we will
2273 * disable the adapter's ability to send PAUSE frames.
2274 */
2275 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
2276 break;
2277 case e1000_fc_tx_pause:
8bde7f77 2278 /* TX Flow control is enabled, and RX Flow control is disabled, by a
682011ff
WD		 2279 * software over-ride.
2280 */
2281 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
2282 break;
2283 case e1000_fc_full:
2284 /* Flow control (both RX and TX) is enabled by a software over-ride. */
2285 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
2286 break;
2287 default:
2288 DEBUGOUT("Flow control param set incorrectly\n");
2289 return -E1000_ERR_CONFIG;
2290 break;
2291 }
2292
2293 /* Since auto-negotiation is enabled, take the link out of reset (the link
2294 * will be in reset, because we previously reset the chip). This will
2295 * restart auto-negotiation. If auto-neogtiation is successful then the
2296 * link-up status bit will be set and the flow control enable bits (RFCE
2297 * and TFCE) will be set according to their negotiated value.
2298 */
2299 DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw);
2300
2301 E1000_WRITE_REG(hw, TXCW, txcw);
2302 E1000_WRITE_REG(hw, CTRL, ctrl);
2303 E1000_WRITE_FLUSH(hw);
2304
2305 hw->txcw = txcw;
2306 mdelay(1);
2307
2308 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
8bde7f77
WD		 2309 * indication in the Device Status Register. Time-out if a link isn't
2310 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
682011ff
WD		 2311 * less than 500 milliseconds even if the other end is doing it in SW).
2312 */
2313 if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
2314 DEBUGOUT("Looking for Link\n");
2315 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
2316 mdelay(10);
2317 status = E1000_READ_REG(hw, STATUS);
2318 if (status & E1000_STATUS_LU)
2319 break;
2320 }
2321 if (i == (LINK_UP_TIMEOUT / 10)) {
8bde7f77 2322 /* AutoNeg failed to achieve a link, so we'll call
682011ff
WD		 2323 * e1000_check_for_link. This routine will force the link up if we
2324 * detect a signal. This will allow us to communicate with
2325 * non-autonegotiating link partners.
2326 */
2327 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
2328 hw->autoneg_failed = 1;
5c5e707a 2329 ret_val = e1000_check_for_link(hw);
682011ff
WD		 2330 if (ret_val < 0) {
2331 DEBUGOUT("Error while checking for link\n");
2332 return ret_val;
2333 }
2334 hw->autoneg_failed = 0;
2335 } else {
2336 hw->autoneg_failed = 0;
2337 DEBUGOUT("Valid Link Found\n");
2338 }
aa070789
RZ		 2339 } else {
2340 DEBUGOUT("No Signal Detected\n");
2341 return -E1000_ERR_NOLINK;
2342 }
2343 return 0;
2344}
2345
aa070789
RZ		 2346/******************************************************************************
2347* Make sure we have a valid PHY and change PHY mode before link setup.
2348*
2349* hw - Struct containing variables accessed by shared code
2350******************************************************************************/
2351static int32_t
2352e1000_copper_link_preconfig(struct e1000_hw *hw)
2353{
2354 uint32_t ctrl;
2355 int32_t ret_val;
2356 uint16_t phy_data;
2357
2358 DEBUGFUNC();
2359
2360 ctrl = E1000_READ_REG(hw, CTRL);
2361 /* With 82543, we need to force speed and duplex on the MAC equal to what
2362 * the PHY speed and duplex configuration is. In addition, we need to
2363 * perform a hardware reset on the PHY to take it out of reset.
2364 */
2365 if (hw->mac_type > e1000_82543) {
2366 ctrl |= E1000_CTRL_SLU;
2367 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2368 E1000_WRITE_REG(hw, CTRL, ctrl);
2369 } else {
2370 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX
2371 | E1000_CTRL_SLU);
2372 E1000_WRITE_REG(hw, CTRL, ctrl);
2373 ret_val = e1000_phy_hw_reset(hw);
2374 if (ret_val)
2375 return ret_val;
2376 }
2377
2378 /* Make sure we have a valid PHY */
2379 ret_val = e1000_detect_gig_phy(hw);
2380 if (ret_val) {
2381 DEBUGOUT("Error, did not detect valid phy.\n");
2382 return ret_val;
2383 }
5abf13e4 2384 DEBUGOUT("Phy ID = %x\n", hw->phy_id);
aa070789 2385
aa070789
RZ		 2386 /* Set PHY to class A mode (if necessary) */
2387 ret_val = e1000_set_phy_mode(hw);
2388 if (ret_val)
2389 return ret_val;
aa070789
RZ		 2390 if ((hw->mac_type == e1000_82545_rev_3) ||
2391 (hw->mac_type == e1000_82546_rev_3)) {
2392 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2393 &phy_data);
2394 phy_data |= 0x00000008;
2395 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2396 phy_data);
2397 }
2398
2399 if (hw->mac_type <= e1000_82543 ||
2400 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
2401 hw->mac_type == e1000_82541_rev_2
2402 || hw->mac_type == e1000_82547_rev_2)
472d5460 2403 hw->phy_reset_disable = false;
aa070789
RZ		 2404
2405 return E1000_SUCCESS;
2406}
2407
2408/*****************************************************************************
2409 *
2410 * This function sets the lplu state according to the active flag. When
2411 * activating lplu this function also disables smart speed and vise versa.
2412 * lplu will not be activated unless the device autonegotiation advertisment
2413 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
2414 * hw: Struct containing variables accessed by shared code
2415 * active - true to enable lplu false to disable lplu.
2416 *
2417 * returns: - E1000_ERR_PHY if fail to read/write the PHY
2418 * E1000_SUCCESS at any other case.
2419 *
2420 ****************************************************************************/
2421
2422static int32_t
472d5460 2423e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
aa070789
RZ		 2424{
2425 uint32_t phy_ctrl = 0;
2426 int32_t ret_val;
2427 uint16_t phy_data;
2428 DEBUGFUNC();
2429
2430 if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
2431 && hw->phy_type != e1000_phy_igp_3)
2432 return E1000_SUCCESS;
2433
2434 /* During driver activity LPLU should not be used or it will attain link
2435 * from the lowest speeds starting from 10Mbps. The capability is used
2436 * for Dx transitions and states */
2437 if (hw->mac_type == e1000_82541_rev_2
2438 || hw->mac_type == e1000_82547_rev_2) {
2439 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
2440 &phy_data);
2441 if (ret_val)
2442 return ret_val;
2443 } else if (hw->mac_type == e1000_ich8lan) {
2444 /* MAC writes into PHY register based on the state transition
2445 * and start auto-negotiation. SW driver can overwrite the
2446 * settings in CSR PHY power control E1000_PHY_CTRL register. */
2447 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
2448 } else {
2449 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2450 &phy_data);
2451 if (ret_val)
2452 return ret_val;
2453 }
2454
2455 if (!active) {
2456 if (hw->mac_type == e1000_82541_rev_2 ||
2457 hw->mac_type == e1000_82547_rev_2) {
2458 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
2459 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
2460 phy_data);
2461 if (ret_val)
2462 return ret_val;
2463 } else {
2464 if (hw->mac_type == e1000_ich8lan) {
2465 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
2466 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2467 } else {
2468 phy_data &= ~IGP02E1000_PM_D3_LPLU;
2469 ret_val = e1000_write_phy_reg(hw,
2470 IGP02E1000_PHY_POWER_MGMT, phy_data);
2471 if (ret_val)
2472 return ret_val;
2473 }
2474 }
2475
2476 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
2477 * Dx states where the power conservation is most important. During
2478 * driver activity we should enable SmartSpeed, so performance is
2479 * maintained. */
2480 if (hw->smart_speed == e1000_smart_speed_on) {
2481 ret_val = e1000_read_phy_reg(hw,
2482 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2483 if (ret_val)
2484 return ret_val;
2485
2486 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
2487 ret_val = e1000_write_phy_reg(hw,
2488 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2489 if (ret_val)
2490 return ret_val;
2491 } else if (hw->smart_speed == e1000_smart_speed_off) {
2492 ret_val = e1000_read_phy_reg(hw,
2493 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2494 if (ret_val)
2495 return ret_val;
2496
2497 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2498 ret_val = e1000_write_phy_reg(hw,
2499 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2500 if (ret_val)
2501 return ret_val;
2502 }
2503
2504 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT)
2505 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) ||
2506 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
2507
2508 if (hw->mac_type == e1000_82541_rev_2 ||
2509 hw->mac_type == e1000_82547_rev_2) {
2510 phy_data |= IGP01E1000_GMII_FLEX_SPD;
2511 ret_val = e1000_write_phy_reg(hw,
2512 IGP01E1000_GMII_FIFO, phy_data);
2513 if (ret_val)
2514 return ret_val;
2515 } else {
2516 if (hw->mac_type == e1000_ich8lan) {
2517 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
2518 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2519 } else {
2520 phy_data |= IGP02E1000_PM_D3_LPLU;
2521 ret_val = e1000_write_phy_reg(hw,
2522 IGP02E1000_PHY_POWER_MGMT, phy_data);
2523 if (ret_val)
2524 return ret_val;
2525 }
2526 }
2527
2528 /* When LPLU is enabled we should disable SmartSpeed */
2529 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2530 &phy_data);
2531 if (ret_val)
2532 return ret_val;
2533
2534 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2535 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2536 phy_data);
2537 if (ret_val)
2538 return ret_val;
2539 }
2540 return E1000_SUCCESS;
2541}
2542
2543/*****************************************************************************
2544 *
2545 * This function sets the lplu d0 state according to the active flag. When
2546 * activating lplu this function also disables smart speed and vise versa.
2547 * lplu will not be activated unless the device autonegotiation advertisment
2548 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
2549 * hw: Struct containing variables accessed by shared code
2550 * active - true to enable lplu false to disable lplu.
2551 *
2552 * returns: - E1000_ERR_PHY if fail to read/write the PHY
2553 * E1000_SUCCESS at any other case.
2554 *
2555 ****************************************************************************/
2556
2557static int32_t
472d5460 2558e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
aa070789
RZ		 2559{
2560 uint32_t phy_ctrl = 0;
2561 int32_t ret_val;
2562 uint16_t phy_data;
2563 DEBUGFUNC();
2564
2565 if (hw->mac_type <= e1000_82547_rev_2)
2566 return E1000_SUCCESS;
2567
2568 if (hw->mac_type == e1000_ich8lan) {
2569 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
95186063
MV		 2570 } else if (hw->mac_type == e1000_igb) {
2571 phy_ctrl = E1000_READ_REG(hw, I210_PHY_CTRL);
aa070789
RZ		 2572 } else {
2573 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2574 &phy_data);
2575 if (ret_val)
2576 return ret_val;
2577 }
2578
2579 if (!active) {
2580 if (hw->mac_type == e1000_ich8lan) {
2581 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2582 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
95186063
MV		 2583 } else if (hw->mac_type == e1000_igb) {
2584 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2585 E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl);
aa070789
RZ		 2586 } else {
2587 phy_data &= ~IGP02E1000_PM_D0_LPLU;
2588 ret_val = e1000_write_phy_reg(hw,
2589 IGP02E1000_PHY_POWER_MGMT, phy_data);
2590 if (ret_val)
2591 return ret_val;
2592 }
2593
95186063
MV		 2594 if (hw->mac_type == e1000_igb)
2595 return E1000_SUCCESS;
2596
aa070789
RZ		 2597 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
2598 * Dx states where the power conservation is most important. During
2599 * driver activity we should enable SmartSpeed, so performance is
2600 * maintained. */
2601 if (hw->smart_speed == e1000_smart_speed_on) {
2602 ret_val = e1000_read_phy_reg(hw,
2603 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2604 if (ret_val)
2605 return ret_val;
2606
2607 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
2608 ret_val = e1000_write_phy_reg(hw,
2609 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2610 if (ret_val)
2611 return ret_val;
2612 } else if (hw->smart_speed == e1000_smart_speed_off) {
2613 ret_val = e1000_read_phy_reg(hw,
2614 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2615 if (ret_val)
2616 return ret_val;
2617
2618 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2619 ret_val = e1000_write_phy_reg(hw,
2620 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2621 if (ret_val)
2622 return ret_val;
2623 }
2624
2625
2626 } else {
2627
2628 if (hw->mac_type == e1000_ich8lan) {
2629 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2630 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
95186063
MV		 2631 } else if (hw->mac_type == e1000_igb) {
2632 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2633 E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl);
aa070789
RZ		 2634 } else {
2635 phy_data |= IGP02E1000_PM_D0_LPLU;
2636 ret_val = e1000_write_phy_reg(hw,
2637 IGP02E1000_PHY_POWER_MGMT, phy_data);
2638 if (ret_val)
2639 return ret_val;
2640 }
2641
95186063
MV		 2642 if (hw->mac_type == e1000_igb)
2643 return E1000_SUCCESS;
2644
aa070789
RZ		 2645 /* When LPLU is enabled we should disable SmartSpeed */
2646 ret_val = e1000_read_phy_reg(hw,
2647 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2648 if (ret_val)
2649 return ret_val;
2650
2651 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2652 ret_val = e1000_write_phy_reg(hw,
2653 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2654 if (ret_val)
2655 return ret_val;
2656
2657 }
2658 return E1000_SUCCESS;
2659}
2660
2661/********************************************************************
2662* Copper link setup for e1000_phy_igp series.
2663*
2664* hw - Struct containing variables accessed by shared code
2665*********************************************************************/
2666static int32_t
2667e1000_copper_link_igp_setup(struct e1000_hw *hw)
2668{
2669 uint32_t led_ctrl;
2670 int32_t ret_val;
2671 uint16_t phy_data;
2672
f81ecb5d 2673 DEBUGFUNC();
aa070789
RZ		 2674
2675 if (hw->phy_reset_disable)
2676 return E1000_SUCCESS;
2677
2678 ret_val = e1000_phy_reset(hw);
2679 if (ret_val) {
2680 DEBUGOUT("Error Resetting the PHY\n");
2681 return ret_val;
2682 }
2683
2684 /* Wait 15ms for MAC to configure PHY from eeprom settings */
2685 mdelay(15);
2686 if (hw->mac_type != e1000_ich8lan) {
2687 /* Configure activity LED after PHY reset */
2688 led_ctrl = E1000_READ_REG(hw, LEDCTL);
2689 led_ctrl &= IGP_ACTIVITY_LED_MASK;
2690 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
2691 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
2692 }
2693
2694 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
2695 if (hw->phy_type == e1000_phy_igp) {
2696 /* disable lplu d3 during driver init */
472d5460 2697 ret_val = e1000_set_d3_lplu_state(hw, false);
aa070789
RZ		 2698 if (ret_val) {
2699 DEBUGOUT("Error Disabling LPLU D3\n");
2700 return ret_val;
2701 }
2702 }
2703
2704 /* disable lplu d0 during driver init */
472d5460 2705 ret_val = e1000_set_d0_lplu_state(hw, false);
aa070789
RZ		 2706 if (ret_val) {
2707 DEBUGOUT("Error Disabling LPLU D0\n");
2708 return ret_val;
2709 }
2710 /* Configure mdi-mdix settings */
2711 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
2712 if (ret_val)
2713 return ret_val;
2714
2715 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
2716 hw->dsp_config_state = e1000_dsp_config_disabled;
2717 /* Force MDI for earlier revs of the IGP PHY */
2718 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX
2719 | IGP01E1000_PSCR_FORCE_MDI_MDIX);
2720 hw->mdix = 1;
2721
2722 } else {
2723 hw->dsp_config_state = e1000_dsp_config_enabled;
2724 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
2725
2726 switch (hw->mdix) {
2727 case 1:
2728 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
2729 break;
2730 case 2:
2731 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
2732 break;
2733 case 0:
2734 default:
2735 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
2736 break;
2737 }
2738 }
2739 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
2740 if (ret_val)
2741 return ret_val;
2742
2743 /* set auto-master slave resolution settings */
2744 if (hw->autoneg) {
2745 e1000_ms_type phy_ms_setting = hw->master_slave;
2746
2747 if (hw->ffe_config_state == e1000_ffe_config_active)
2748 hw->ffe_config_state = e1000_ffe_config_enabled;
2749
2750 if (hw->dsp_config_state == e1000_dsp_config_activated)
2751 hw->dsp_config_state = e1000_dsp_config_enabled;
2752
2753 /* when autonegotiation advertisment is only 1000Mbps then we
2754 * should disable SmartSpeed and enable Auto MasterSlave
2755 * resolution as hardware default. */
2756 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
2757 /* Disable SmartSpeed */
2758 ret_val = e1000_read_phy_reg(hw,
2759 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2760 if (ret_val)
2761 return ret_val;
2762 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2763 ret_val = e1000_write_phy_reg(hw,
2764 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2765 if (ret_val)
2766 return ret_val;
2767 /* Set auto Master/Slave resolution process */
2768 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
2769 &phy_data);
2770 if (ret_val)
2771 return ret_val;
2772 phy_data &= ~CR_1000T_MS_ENABLE;
2773 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
2774 phy_data);
2775 if (ret_val)
2776 return ret_val;
2777 }
2778
2779 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
2780 if (ret_val)
2781 return ret_val;
2782
2783 /* load defaults for future use */
2784 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
2785 ((phy_data & CR_1000T_MS_VALUE) ?
2786 e1000_ms_force_master :
2787 e1000_ms_force_slave) :
2788 e1000_ms_auto;
2789
2790 switch (phy_ms_setting) {
2791 case e1000_ms_force_master:
2792 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
2793 break;
2794 case e1000_ms_force_slave:
2795 phy_data |= CR_1000T_MS_ENABLE;
2796 phy_data &= ~(CR_1000T_MS_VALUE);
2797 break;
2798 case e1000_ms_auto:
2799 phy_data &= ~CR_1000T_MS_ENABLE;
2800 default:
2801 break;
2802 }
2803 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
2804 if (ret_val)
2805 return ret_val;
2806 }
2807
2808 return E1000_SUCCESS;
2809}
2810
2811/*****************************************************************************
2812 * This function checks the mode of the firmware.
2813 *
472d5460 2814 * returns - true when the mode is IAMT or false.
aa070789 2815 ****************************************************************************/
472d5460 2816bool
aa070789
RZ		 2817e1000_check_mng_mode(struct e1000_hw *hw)
2818{
2819 uint32_t fwsm;
2820 DEBUGFUNC();
2821
2822 fwsm = E1000_READ_REG(hw, FWSM);
2823
2824 if (hw->mac_type == e1000_ich8lan) {
2825 if ((fwsm & E1000_FWSM_MODE_MASK) ==
2826 (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
472d5460 2827 return true;
aa070789
RZ		 2828 } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
2829 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
472d5460 2830 return true;
aa070789 2831
472d5460 2832 return false;
aa070789
RZ		 2833}
2834
2835static int32_t
2836e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data)
2837{
987b43a1 2838 uint16_t swfw = E1000_SWFW_PHY0_SM;
aa070789 2839 uint32_t reg_val;
aa070789
RZ		 2840 DEBUGFUNC();
2841
987b43a1 2842 if (e1000_is_second_port(hw))
aa070789 2843 swfw = E1000_SWFW_PHY1_SM;
987b43a1 2844
aa070789
RZ		 2845 if (e1000_swfw_sync_acquire(hw, swfw))
2846 return -E1000_ERR_SWFW_SYNC;
2847
2848 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT)
2849 & E1000_KUMCTRLSTA_OFFSET) | data;
2850 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
2851 udelay(2);
2852
2853 return E1000_SUCCESS;
2854}
2855
2856static int32_t
2857e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data)
2858{
987b43a1 2859 uint16_t swfw = E1000_SWFW_PHY0_SM;
aa070789 2860 uint32_t reg_val;
aa070789
RZ		 2861 DEBUGFUNC();
2862
987b43a1 2863 if (e1000_is_second_port(hw))
aa070789 2864 swfw = E1000_SWFW_PHY1_SM;
987b43a1 2865
95186063
MV		 2866 if (e1000_swfw_sync_acquire(hw, swfw)) {
2867 debug("%s[%i]\n", __func__, __LINE__);
aa070789 2868 return -E1000_ERR_SWFW_SYNC;
95186063 2869 }
aa070789
RZ		 2870
2871 /* Write register address */
2872 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
2873 E1000_KUMCTRLSTA_OFFSET) | E1000_KUMCTRLSTA_REN;
2874 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
2875 udelay(2);
2876
2877 /* Read the data returned */
2878 reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
2879 *data = (uint16_t)reg_val;
2880
2881 return E1000_SUCCESS;
2882}
2883
2884/********************************************************************
2885* Copper link setup for e1000_phy_gg82563 series.
2886*
2887* hw - Struct containing variables accessed by shared code
2888*********************************************************************/
2889static int32_t
2890e1000_copper_link_ggp_setup(struct e1000_hw *hw)
2891{
2892 int32_t ret_val;
2893 uint16_t phy_data;
2894 uint32_t reg_data;
2895
2896 DEBUGFUNC();
2897
2898 if (!hw->phy_reset_disable) {
2899 /* Enable CRS on TX for half-duplex operation. */
2900 ret_val = e1000_read_phy_reg(hw,
2901 GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
2902 if (ret_val)
2903 return ret_val;
2904
2905 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
2906 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
2907 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
2908
2909 ret_val = e1000_write_phy_reg(hw,
2910 GG82563_PHY_MAC_SPEC_CTRL, phy_data);
2911 if (ret_val)
2912 return ret_val;
2913
2914 /* Options:
2915 * MDI/MDI-X = 0 (default)
2916 * 0 - Auto for all speeds
2917 * 1 - MDI mode
2918 * 2 - MDI-X mode
2919 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
2920 */
2921 ret_val = e1000_read_phy_reg(hw,
2922 GG82563_PHY_SPEC_CTRL, &phy_data);
2923 if (ret_val)
2924 return ret_val;
2925
2926 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
2927
2928 switch (hw->mdix) {
2929 case 1:
2930 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
2931 break;
2932 case 2:
2933 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
2934 break;
2935 case 0:
2936 default:
2937 phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
2938 break;
2939 }
2940
2941 /* Options:
2942 * disable_polarity_correction = 0 (default)
2943 * Automatic Correction for Reversed Cable Polarity
2944 * 0 - Disabled
2945 * 1 - Enabled
2946 */
2947 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
2948 ret_val = e1000_write_phy_reg(hw,
2949 GG82563_PHY_SPEC_CTRL, phy_data);
2950
2951 if (ret_val)
2952 return ret_val;
2953
2954 /* SW Reset the PHY so all changes take effect */
2955 ret_val = e1000_phy_reset(hw);
2956 if (ret_val) {
2957 DEBUGOUT("Error Resetting the PHY\n");
2958 return ret_val;
2959 }
2960 } /* phy_reset_disable */
2961
2962 if (hw->mac_type == e1000_80003es2lan) {
2963 /* Bypass RX and TX FIFO's */
2964 ret_val = e1000_write_kmrn_reg(hw,
2965 E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
2966 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS
2967 | E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
2968 if (ret_val)
2969 return ret_val;
2970
2971 ret_val = e1000_read_phy_reg(hw,
2972 GG82563_PHY_SPEC_CTRL_2, &phy_data);
2973 if (ret_val)
2974 return ret_val;
2975
2976 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
2977 ret_val = e1000_write_phy_reg(hw,
2978 GG82563_PHY_SPEC_CTRL_2, phy_data);
2979
2980 if (ret_val)
2981 return ret_val;
2982
2983 reg_data = E1000_READ_REG(hw, CTRL_EXT);
2984 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
2985 E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
2986
2987 ret_val = e1000_read_phy_reg(hw,
2988 GG82563_PHY_PWR_MGMT_CTRL, &phy_data);
2989 if (ret_val)
2990 return ret_val;
2991
2992 /* Do not init these registers when the HW is in IAMT mode, since the
2993 * firmware will have already initialized them. We only initialize
2994 * them if the HW is not in IAMT mode.
2995 */
472d5460 2996 if (e1000_check_mng_mode(hw) == false) {
aa070789
RZ		 2997 /* Enable Electrical Idle on the PHY */
2998 phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
2999 ret_val = e1000_write_phy_reg(hw,
3000 GG82563_PHY_PWR_MGMT_CTRL, phy_data);
3001 if (ret_val)
3002 return ret_val;
3003
3004 ret_val = e1000_read_phy_reg(hw,
3005 GG82563_PHY_KMRN_MODE_CTRL, &phy_data);
3006 if (ret_val)
3007 return ret_val;
3008
3009 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
3010 ret_val = e1000_write_phy_reg(hw,
3011 GG82563_PHY_KMRN_MODE_CTRL, phy_data);
3012
3013 if (ret_val)
3014 return ret_val;
3015 }
3016
3017 /* Workaround: Disable padding in Kumeran interface in the MAC
3018 * and in the PHY to avoid CRC errors.
3019 */
3020 ret_val = e1000_read_phy_reg(hw,
3021 GG82563_PHY_INBAND_CTRL, &phy_data);
3022 if (ret_val)
3023 return ret_val;
3024 phy_data |= GG82563_ICR_DIS_PADDING;
3025 ret_val = e1000_write_phy_reg(hw,
3026 GG82563_PHY_INBAND_CTRL, phy_data);
3027 if (ret_val)
3028 return ret_val;
682011ff 3029 }
aa070789 3030 return E1000_SUCCESS;
682011ff
WD		 3031}
3032
aa070789
RZ		 3033/********************************************************************
3034* Copper link setup for e1000_phy_m88 series.
682011ff
WD		 3035*
3036* hw - Struct containing variables accessed by shared code
aa070789
RZ		 3037*********************************************************************/
3038static int32_t
3039e1000_copper_link_mgp_setup(struct e1000_hw *hw)
682011ff 3040{
682011ff 3041 int32_t ret_val;
682011ff
WD		 3042 uint16_t phy_data;
3043
3044 DEBUGFUNC();
3045
aa070789
RZ		 3046 if (hw->phy_reset_disable)
3047 return E1000_SUCCESS;
682011ff 3048
aa070789
RZ		 3049 /* Enable CRS on TX. This must be set for half-duplex operation. */
3050 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
3051 if (ret_val)
682011ff 3052 return ret_val;
682011ff 3053
682011ff
WD		 3054 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
3055
682011ff
WD		 3056 /* Options:
3057 * MDI/MDI-X = 0 (default)
3058 * 0 - Auto for all speeds
3059 * 1 - MDI mode
3060 * 2 - MDI-X mode
3061 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
3062 */
3063 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
aa070789 3064
682011ff
WD		 3065 switch (hw->mdix) {
3066 case 1:
3067 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
3068 break;
3069 case 2:
3070 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
3071 break;
3072 case 3:
3073 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
3074 break;
3075 case 0:
3076 default:
3077 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
3078 break;
3079 }
682011ff 3080
682011ff
WD		 3081 /* Options:
3082 * disable_polarity_correction = 0 (default)
aa070789 3083 * Automatic Correction for Reversed Cable Polarity
682011ff
WD		 3084 * 0 - Disabled
3085 * 1 - Enabled
3086 */
3087 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
aa070789
RZ		 3088 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
3089 if (ret_val)
3090 return ret_val;
682011ff 3091
aa070789
RZ		 3092 if (hw->phy_revision < M88E1011_I_REV_4) {
3093 /* Force TX_CLK in the Extended PHY Specific Control Register
3094 * to 25MHz clock.
3095 */
3096 ret_val = e1000_read_phy_reg(hw,
3097 M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
3098 if (ret_val)
3099 return ret_val;
3100
3101 phy_data |= M88E1000_EPSCR_TX_CLK_25;
3102
3103 if ((hw->phy_revision == E1000_REVISION_2) &&
3104 (hw->phy_id == M88E1111_I_PHY_ID)) {
3105 /* Vidalia Phy, set the downshift counter to 5x */
3106 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
3107 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
3108 ret_val = e1000_write_phy_reg(hw,
3109 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
3110 if (ret_val)
3111 return ret_val;
3112 } else {
3113 /* Configure Master and Slave downshift values */
3114 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK
3115 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
3116 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X
3117 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
3118 ret_val = e1000_write_phy_reg(hw,
3119 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
3120 if (ret_val)
3121 return ret_val;
3122 }
682011ff
WD		 3123 }
3124
3125 /* SW Reset the PHY so all changes take effect */
3126 ret_val = e1000_phy_reset(hw);
aa070789 3127 if (ret_val) {
682011ff
WD		 3128 DEBUGOUT("Error Resetting the PHY\n");
3129 return ret_val;
3130 }
3131
aa070789
RZ		 3132 return E1000_SUCCESS;
3133}
3134
3135/********************************************************************
3136* Setup auto-negotiation and flow control advertisements,
3137* and then perform auto-negotiation.
3138*
3139* hw - Struct containing variables accessed by shared code
3140*********************************************************************/
3141static int32_t
3142e1000_copper_link_autoneg(struct e1000_hw *hw)
3143{
3144 int32_t ret_val;
3145 uint16_t phy_data;
3146
3147 DEBUGFUNC();
682011ff 3148
682011ff
WD		 3149 /* Perform some bounds checking on the hw->autoneg_advertised
3150 * parameter. If this variable is zero, then set it to the default.
3151 */
3152 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
3153
3154 /* If autoneg_advertised is zero, we assume it was not defaulted
3155 * by the calling code so we set to advertise full capability.
3156 */
3157 if (hw->autoneg_advertised == 0)
3158 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
3159
aa070789
RZ		 3160 /* IFE phy only supports 10/100 */
3161 if (hw->phy_type == e1000_phy_ife)
3162 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
3163
682011ff
WD		 3164 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
3165 ret_val = e1000_phy_setup_autoneg(hw);
aa070789 3166 if (ret_val) {
682011ff
WD		 3167 DEBUGOUT("Error Setting up Auto-Negotiation\n");
3168 return ret_val;
3169 }
3170 DEBUGOUT("Restarting Auto-Neg\n");
3171
3172 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
3173 * the Auto Neg Restart bit in the PHY control register.
3174 */
aa070789
RZ		 3175 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
3176 if (ret_val)
3177 return ret_val;
3178
682011ff 3179 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
aa070789
RZ		 3180 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
3181 if (ret_val)
3182 return ret_val;
3183
682011ff
WD		 3184 /* Does the user want to wait for Auto-Neg to complete here, or
3185 * check at a later time (for example, callback routine).
3186 */
aa070789
RZ		 3187 /* If we do not wait for autonegtation to complete I
3188 * do not see a valid link status.
3189 * wait_autoneg_complete = 1 .
3190 */
682011ff
WD		 3191 if (hw->wait_autoneg_complete) {
3192 ret_val = e1000_wait_autoneg(hw);
aa070789
RZ		 3193 if (ret_val) {
3194 DEBUGOUT("Error while waiting for autoneg"
3195 "to complete\n");
682011ff
WD		 3196 return ret_val;
3197 }
3198 }
aa070789 3199
472d5460 3200 hw->get_link_status = true;
aa070789
RZ		 3201
3202 return E1000_SUCCESS;
3203}
3204
3205/******************************************************************************
3206* Config the MAC and the PHY after link is up.
3207* 1) Set up the MAC to the current PHY speed/duplex
3208* if we are on 82543. If we
3209* are on newer silicon, we only need to configure
3210* collision distance in the Transmit Control Register.
3211* 2) Set up flow control on the MAC to that established with
3212* the link partner.
3213* 3) Config DSP to improve Gigabit link quality for some PHY revisions.
3214*
3215* hw - Struct containing variables accessed by shared code
3216******************************************************************************/
3217static int32_t
3218e1000_copper_link_postconfig(struct e1000_hw *hw)
3219{
3220 int32_t ret_val;
3221 DEBUGFUNC();
3222
3223 if (hw->mac_type >= e1000_82544) {
3224 e1000_config_collision_dist(hw);
3225 } else {
3226 ret_val = e1000_config_mac_to_phy(hw);
3227 if (ret_val) {
3228 DEBUGOUT("Error configuring MAC to PHY settings\n");
3229 return ret_val;
3230 }
3231 }
3232 ret_val = e1000_config_fc_after_link_up(hw);
3233 if (ret_val) {
3234 DEBUGOUT("Error Configuring Flow Control\n");
682011ff
WD		 3235 return ret_val;
3236 }
aa070789
RZ		 3237 return E1000_SUCCESS;
3238}
3239
3240/******************************************************************************
3241* Detects which PHY is present and setup the speed and duplex
3242*
3243* hw - Struct containing variables accessed by shared code
3244******************************************************************************/
3245static int
5c5e707a 3246e1000_setup_copper_link(struct e1000_hw *hw)
aa070789 3247{
aa070789
RZ		 3248 int32_t ret_val;
3249 uint16_t i;
3250 uint16_t phy_data;
3251 uint16_t reg_data;
3252
3253 DEBUGFUNC();
3254
3255 switch (hw->mac_type) {
3256 case e1000_80003es2lan:
3257 case e1000_ich8lan:
3258 /* Set the mac to wait the maximum time between each
3259 * iteration and increase the max iterations when
3260 * polling the phy; this fixes erroneous timeouts at 10Mbps. */
3261 ret_val = e1000_write_kmrn_reg(hw,
3262 GG82563_REG(0x34, 4), 0xFFFF);
3263 if (ret_val)
3264 return ret_val;
3265 ret_val = e1000_read_kmrn_reg(hw,
3266 GG82563_REG(0x34, 9), &reg_data);
3267 if (ret_val)
3268 return ret_val;
3269 reg_data |= 0x3F;
3270 ret_val = e1000_write_kmrn_reg(hw,
3271 GG82563_REG(0x34, 9), reg_data);
3272 if (ret_val)
3273 return ret_val;
3274 default:
3275 break;
3276 }
3277
3278 /* Check if it is a valid PHY and set PHY mode if necessary. */
3279 ret_val = e1000_copper_link_preconfig(hw);
3280 if (ret_val)
3281 return ret_val;
3282 switch (hw->mac_type) {
3283 case e1000_80003es2lan:
3284 /* Kumeran registers are written-only */
3285 reg_data =
3286 E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
3287 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
3288 ret_val = e1000_write_kmrn_reg(hw,
3289 E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data);
3290 if (ret_val)
3291 return ret_val;
3292 break;
3293 default:
3294 break;
3295 }
3296
3297 if (hw->phy_type == e1000_phy_igp ||
3298 hw->phy_type == e1000_phy_igp_3 ||
3299 hw->phy_type == e1000_phy_igp_2) {
3300 ret_val = e1000_copper_link_igp_setup(hw);
3301 if (ret_val)
3302 return ret_val;
95186063
MV		 3303 } else if (hw->phy_type == e1000_phy_m88 ||
3304 hw->phy_type == e1000_phy_igb) {
aa070789
RZ		 3305 ret_val = e1000_copper_link_mgp_setup(hw);
3306 if (ret_val)
3307 return ret_val;
3308 } else if (hw->phy_type == e1000_phy_gg82563) {
3309 ret_val = e1000_copper_link_ggp_setup(hw);
3310 if (ret_val)
3311 return ret_val;
3312 }
3313
3314 /* always auto */
3315 /* Setup autoneg and flow control advertisement
3316 * and perform autonegotiation */
3317 ret_val = e1000_copper_link_autoneg(hw);
3318 if (ret_val)
3319 return ret_val;
682011ff
WD		 3320
3321 /* Check link status. Wait up to 100 microseconds for link to become
3322 * valid.
3323 */
3324 for (i = 0; i < 10; i++) {
aa070789
RZ		 3325 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3326 if (ret_val)
3327 return ret_val;
3328 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3329 if (ret_val)
3330 return ret_val;
3331
682011ff 3332 if (phy_data & MII_SR_LINK_STATUS) {
aa070789
RZ		 3333 /* Config the MAC and PHY after link is up */
3334 ret_val = e1000_copper_link_postconfig(hw);
3335 if (ret_val)
682011ff 3336 return ret_val;
aa070789 3337
682011ff 3338 DEBUGOUT("Valid link established!!!\n");
aa070789 3339 return E1000_SUCCESS;
682011ff
WD		 3340 }
3341 udelay(10);
3342 }
3343
3344 DEBUGOUT("Unable to establish link!!!\n");
aa070789 3345 return E1000_SUCCESS;
682011ff
WD		 3346}
3347
3348/******************************************************************************
3349* Configures PHY autoneg and flow control advertisement settings
3350*
3351* hw - Struct containing variables accessed by shared code
3352******************************************************************************/
aa070789 3353int32_t
682011ff
WD		 3354e1000_phy_setup_autoneg(struct e1000_hw *hw)
3355{
aa070789 3356 int32_t ret_val;
682011ff
WD		 3357 uint16_t mii_autoneg_adv_reg;
3358 uint16_t mii_1000t_ctrl_reg;
3359
3360 DEBUGFUNC();
3361
3362 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
aa070789
RZ		 3363 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
3364 if (ret_val)
3365 return ret_val;
682011ff 3366
aa070789
RZ		 3367 if (hw->phy_type != e1000_phy_ife) {
3368 /* Read the MII 1000Base-T Control Register (Address 9). */
3369 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
3370 &mii_1000t_ctrl_reg);
3371 if (ret_val)
3372 return ret_val;
3373 } else
3374 mii_1000t_ctrl_reg = 0;
682011ff
WD		 3375
3376 /* Need to parse both autoneg_advertised and fc and set up
3377 * the appropriate PHY registers. First we will parse for
3378 * autoneg_advertised software override. Since we can advertise
3379 * a plethora of combinations, we need to check each bit
3380 * individually.
3381 */
3382
3383 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
3384 * Advertisement Register (Address 4) and the 1000 mb speed bits in
aa070789 3385 * the 1000Base-T Control Register (Address 9).
682011ff
WD		 3386 */
3387 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
3388 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
3389
3390 DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised);
3391
3392 /* Do we want to advertise 10 Mb Half Duplex? */
3393 if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
3394 DEBUGOUT("Advertise 10mb Half duplex\n");
3395 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
3396 }
3397
3398 /* Do we want to advertise 10 Mb Full Duplex? */
3399 if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
3400 DEBUGOUT("Advertise 10mb Full duplex\n");
3401 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
3402 }
3403
3404 /* Do we want to advertise 100 Mb Half Duplex? */
3405 if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
3406 DEBUGOUT("Advertise 100mb Half duplex\n");
3407 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
3408 }
3409
3410 /* Do we want to advertise 100 Mb Full Duplex? */
3411 if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
3412 DEBUGOUT("Advertise 100mb Full duplex\n");
3413 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
3414 }
3415
3416 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
3417 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
3418 DEBUGOUT
3419 ("Advertise 1000mb Half duplex requested, request denied!\n");
3420 }
3421
3422 /* Do we want to advertise 1000 Mb Full Duplex? */
3423 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
3424 DEBUGOUT("Advertise 1000mb Full duplex\n");
3425 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
3426 }
3427
3428 /* Check for a software override of the flow control settings, and
3429 * setup the PHY advertisement registers accordingly. If
3430 * auto-negotiation is enabled, then software will have to set the
3431 * "PAUSE" bits to the correct value in the Auto-Negotiation
3432 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
3433 *
3434 * The possible values of the "fc" parameter are:
1aeed8d7
WD		 3435 * 0: Flow control is completely disabled
3436 * 1: Rx flow control is enabled (we can receive pause frames
3437 * but not send pause frames).
3438 * 2: Tx flow control is enabled (we can send pause frames
3439 * but we do not support receiving pause frames).
3440 * 3: Both Rx and TX flow control (symmetric) are enabled.
682011ff 3441 * other: No software override. The flow control configuration
1aeed8d7 3442 * in the EEPROM is used.
682011ff
WD		 3443 */
3444 switch (hw->fc) {
3445 case e1000_fc_none: /* 0 */
3446 /* Flow control (RX & TX) is completely disabled by a
3447 * software over-ride.
3448 */
3449 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3450 break;
3451 case e1000_fc_rx_pause: /* 1 */
3452 /* RX Flow control is enabled, and TX Flow control is
3453 * disabled, by a software over-ride.
3454 */
3455 /* Since there really isn't a way to advertise that we are
3456 * capable of RX Pause ONLY, we will advertise that we
3457 * support both symmetric and asymmetric RX PAUSE. Later
3458 * (in e1000_config_fc_after_link_up) we will disable the
3459 *hw's ability to send PAUSE frames.
3460 */
3461 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3462 break;
3463 case e1000_fc_tx_pause: /* 2 */
3464 /* TX Flow control is enabled, and RX Flow control is
3465 * disabled, by a software over-ride.
3466 */
3467 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
3468 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
3469 break;
3470 case e1000_fc_full: /* 3 */
3471 /* Flow control (both RX and TX) is enabled by a software
3472 * over-ride.
3473 */
3474 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3475 break;
3476 default:
3477 DEBUGOUT("Flow control param set incorrectly\n");
3478 return -E1000_ERR_CONFIG;
3479 }
3480
aa070789
RZ		 3481 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
3482 if (ret_val)
3483 return ret_val;
682011ff
WD		 3484
3485 DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
3486
aa070789
RZ		 3487 if (hw->phy_type != e1000_phy_ife) {
3488 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
3489 mii_1000t_ctrl_reg);
3490 if (ret_val)
3491 return ret_val;
682011ff 3492 }
aa070789
RZ		 3493
3494 return E1000_SUCCESS;
682011ff
WD		 3495}
3496
3497/******************************************************************************
3498* Sets the collision distance in the Transmit Control register
3499*
3500* hw - Struct containing variables accessed by shared code
3501*
3502* Link should have been established previously. Reads the speed and duplex
3503* information from the Device Status register.
3504******************************************************************************/
3505static void
3506e1000_config_collision_dist(struct e1000_hw *hw)
3507{
aa070789
RZ		 3508 uint32_t tctl, coll_dist;
3509
3510 DEBUGFUNC();
3511
3512 if (hw->mac_type < e1000_82543)
3513 coll_dist = E1000_COLLISION_DISTANCE_82542;
3514 else
3515 coll_dist = E1000_COLLISION_DISTANCE;
682011ff
WD		 3516
3517 tctl = E1000_READ_REG(hw, TCTL);
3518
3519 tctl &= ~E1000_TCTL_COLD;
aa070789 3520 tctl |= coll_dist << E1000_COLD_SHIFT;
682011ff
WD		 3521
3522 E1000_WRITE_REG(hw, TCTL, tctl);
3523 E1000_WRITE_FLUSH(hw);
3524}
3525
3526/******************************************************************************
3527* Sets MAC speed and duplex settings to reflect the those in the PHY
3528*
3529* hw - Struct containing variables accessed by shared code
3530* mii_reg - data to write to the MII control register
3531*
3532* The contents of the PHY register containing the needed information need to
3533* be passed in.
3534******************************************************************************/
3535static int
3536e1000_config_mac_to_phy(struct e1000_hw *hw)
3537{
3538 uint32_t ctrl;
3539 uint16_t phy_data;
3540
3541 DEBUGFUNC();
3542
3543 /* Read the Device Control Register and set the bits to Force Speed
3544 * and Duplex.
3545 */
3546 ctrl = E1000_READ_REG(hw, CTRL);
3547 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
95186063
MV		 3548 ctrl &= ~(E1000_CTRL_ILOS);
3549 ctrl |= (E1000_CTRL_SPD_SEL);
682011ff
WD		 3550
3551 /* Set up duplex in the Device Control and Transmit Control
3552 * registers depending on negotiated values.
3553 */
3554 if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) {
3555 DEBUGOUT("PHY Read Error\n");
3556 return -E1000_ERR_PHY;
3557 }
3558 if (phy_data & M88E1000_PSSR_DPLX)
3559 ctrl |= E1000_CTRL_FD;
3560 else
3561 ctrl &= ~E1000_CTRL_FD;
3562
3563 e1000_config_collision_dist(hw);
3564
3565 /* Set up speed in the Device Control register depending on
3566 * negotiated values.
3567 */
3568 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
3569 ctrl |= E1000_CTRL_SPD_1000;
3570 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
3571 ctrl |= E1000_CTRL_SPD_100;
3572 /* Write the configured values back to the Device Control Reg. */
3573 E1000_WRITE_REG(hw, CTRL, ctrl);
3574 return 0;
3575}
3576
3577/******************************************************************************
3578 * Forces the MAC's flow control settings.
8bde7f77 3579 *
682011ff
WD		 3580 * hw - Struct containing variables accessed by shared code
3581 *
3582 * Sets the TFCE and RFCE bits in the device control register to reflect
3583 * the adapter settings. TFCE and RFCE need to be explicitly set by
3584 * software when a Copper PHY is used because autonegotiation is managed
3585 * by the PHY rather than the MAC. Software must also configure these
3586 * bits when link is forced on a fiber connection.
3587 *****************************************************************************/
3588static int
3589e1000_force_mac_fc(struct e1000_hw *hw)
3590{
3591 uint32_t ctrl;
3592
3593 DEBUGFUNC();
3594
3595 /* Get the current configuration of the Device Control Register */
3596 ctrl = E1000_READ_REG(hw, CTRL);
3597
3598 /* Because we didn't get link via the internal auto-negotiation
3599 * mechanism (we either forced link or we got link via PHY
3600 * auto-neg), we have to manually enable/disable transmit an
3601 * receive flow control.
3602 *
3603 * The "Case" statement below enables/disable flow control
3604 * according to the "hw->fc" parameter.
3605 *
3606 * The possible values of the "fc" parameter are:
1aeed8d7
WD		 3607 * 0: Flow control is completely disabled
3608 * 1: Rx flow control is enabled (we can receive pause
3609 * frames but not send pause frames).
3610 * 2: Tx flow control is enabled (we can send pause frames
3611 * frames but we do not receive pause frames).
3612 * 3: Both Rx and TX flow control (symmetric) is enabled.
682011ff
WD		 3613 * other: No other values should be possible at this point.
3614 */
3615
3616 switch (hw->fc) {
3617 case e1000_fc_none:
3618 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
3619 break;
3620 case e1000_fc_rx_pause:
3621 ctrl &= (~E1000_CTRL_TFCE);
3622 ctrl |= E1000_CTRL_RFCE;
3623 break;
3624 case e1000_fc_tx_pause:
3625 ctrl &= (~E1000_CTRL_RFCE);
3626 ctrl |= E1000_CTRL_TFCE;
3627 break;
3628 case e1000_fc_full:
3629 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
3630 break;
3631 default:
3632 DEBUGOUT("Flow control param set incorrectly\n");
3633 return -E1000_ERR_CONFIG;
3634 }
3635
3636 /* Disable TX Flow Control for 82542 (rev 2.0) */
3637 if (hw->mac_type == e1000_82542_rev2_0)
3638 ctrl &= (~E1000_CTRL_TFCE);
3639
3640 E1000_WRITE_REG(hw, CTRL, ctrl);
3641 return 0;
3642}
3643
3644/******************************************************************************
3645 * Configures flow control settings after link is established
8bde7f77 3646 *
682011ff
WD		 3647 * hw - Struct containing variables accessed by shared code
3648 *
3649 * Should be called immediately after a valid link has been established.
3650 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
3651 * and autonegotiation is enabled, the MAC flow control settings will be set
3652 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
3653 * and RFCE bits will be automaticaly set to the negotiated flow control mode.
3654 *****************************************************************************/
aa070789 3655static int32_t
682011ff
WD		 3656e1000_config_fc_after_link_up(struct e1000_hw *hw)
3657{
3658 int32_t ret_val;
3659 uint16_t mii_status_reg;
3660 uint16_t mii_nway_adv_reg;
3661 uint16_t mii_nway_lp_ability_reg;
3662 uint16_t speed;
3663 uint16_t duplex;
3664
3665 DEBUGFUNC();
3666
3667 /* Check for the case where we have fiber media and auto-neg failed
3668 * so we had to force link. In this case, we need to force the
3669 * configuration of the MAC to match the "fc" parameter.
3670 */
aa070789
RZ		 3671 if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed))
3672 || ((hw->media_type == e1000_media_type_internal_serdes)
3673 && (hw->autoneg_failed))
3674 || ((hw->media_type == e1000_media_type_copper)
3675 && (!hw->autoneg))) {
682011ff
WD		 3676 ret_val = e1000_force_mac_fc(hw);
3677 if (ret_val < 0) {
3678 DEBUGOUT("Error forcing flow control settings\n");
3679 return ret_val;
3680 }
3681 }
3682
3683 /* Check for the case where we have copper media and auto-neg is
3684 * enabled. In this case, we need to check and see if Auto-Neg
3685 * has completed, and if so, how the PHY and link partner has
3686 * flow control configured.
3687 */
3688 if (hw->media_type == e1000_media_type_copper) {
3689 /* Read the MII Status Register and check to see if AutoNeg
3690 * has completed. We read this twice because this reg has
3691 * some "sticky" (latched) bits.
3692 */
3693 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
5abf13e4 3694 DEBUGOUT("PHY Read Error\n");
682011ff
WD		 3695 return -E1000_ERR_PHY;
3696 }
3697 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
5abf13e4 3698 DEBUGOUT("PHY Read Error\n");
682011ff
WD		 3699 return -E1000_ERR_PHY;
3700 }
3701
3702 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
3703 /* The AutoNeg process has completed, so we now need to
3704 * read both the Auto Negotiation Advertisement Register
3705 * (Address 4) and the Auto_Negotiation Base Page Ability
3706 * Register (Address 5) to determine how flow control was
3707 * negotiated.
3708 */
3709 if (e1000_read_phy_reg
3710 (hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) {
3711 DEBUGOUT("PHY Read Error\n");
3712 return -E1000_ERR_PHY;
3713 }
3714 if (e1000_read_phy_reg
3715 (hw, PHY_LP_ABILITY,
3716 &mii_nway_lp_ability_reg) < 0) {
3717 DEBUGOUT("PHY Read Error\n");
3718 return -E1000_ERR_PHY;
3719 }
3720
3721 /* Two bits in the Auto Negotiation Advertisement Register
3722 * (Address 4) and two bits in the Auto Negotiation Base
3723 * Page Ability Register (Address 5) determine flow control
3724 * for both the PHY and the link partner. The following
3725 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
3726 * 1999, describes these PAUSE resolution bits and how flow
3727 * control is determined based upon these settings.
3728 * NOTE: DC = Don't Care
3729 *
3730 * LOCAL DEVICE | LINK PARTNER
3731 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
3732 *-------|---------|-------|---------|--------------------
1aeed8d7
WD		 3733 * 0 | 0 | DC | DC | e1000_fc_none
3734 * 0 | 1 | 0 | DC | e1000_fc_none
3735 * 0 | 1 | 1 | 0 | e1000_fc_none
3736 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
3737 * 1 | 0 | 0 | DC | e1000_fc_none
3738 * 1 | DC | 1 | DC | e1000_fc_full
3739 * 1 | 1 | 0 | 0 | e1000_fc_none
3740 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
682011ff
WD		 3741 *
3742 */
3743 /* Are both PAUSE bits set to 1? If so, this implies
3744 * Symmetric Flow Control is enabled at both ends. The
3745 * ASM_DIR bits are irrelevant per the spec.
3746 *
3747 * For Symmetric Flow Control:
3748 *
3749 * LOCAL DEVICE | LINK PARTNER
3750 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3751 *-------|---------|-------|---------|--------------------
1aeed8d7 3752 * 1 | DC | 1 | DC | e1000_fc_full
682011ff
WD		 3753 *
3754 */
3755 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3756 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
3757 /* Now we need to check if the user selected RX ONLY
3758 * of pause frames. In this case, we had to advertise
3759 * FULL flow control because we could not advertise RX
3760 * ONLY. Hence, we must now check to see if we need to
3761 * turn OFF the TRANSMISSION of PAUSE frames.
3762 */
3763 if (hw->original_fc == e1000_fc_full) {
3764 hw->fc = e1000_fc_full;
3765 DEBUGOUT("Flow Control = FULL.\r\n");
3766 } else {
3767 hw->fc = e1000_fc_rx_pause;
3768 DEBUGOUT
3769 ("Flow Control = RX PAUSE frames only.\r\n");
3770 }
3771 }
3772 /* For receiving PAUSE frames ONLY.
3773 *
3774 * LOCAL DEVICE | LINK PARTNER
3775 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3776 *-------|---------|-------|---------|--------------------
1aeed8d7 3777 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
682011ff
WD		 3778 *
3779 */
3780 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3781 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
3782 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
3783 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
3784 {
3785 hw->fc = e1000_fc_tx_pause;
3786 DEBUGOUT
3787 ("Flow Control = TX PAUSE frames only.\r\n");
3788 }
3789 /* For transmitting PAUSE frames ONLY.
3790 *
3791 * LOCAL DEVICE | LINK PARTNER
3792 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3793 *-------|---------|-------|---------|--------------------
1aeed8d7 3794 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
682011ff
WD		 3795 *
3796 */
3797 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3798 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
3799 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
3800 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
3801 {
3802 hw->fc = e1000_fc_rx_pause;
3803 DEBUGOUT
3804 ("Flow Control = RX PAUSE frames only.\r\n");
3805 }
3806 /* Per the IEEE spec, at this point flow control should be
3807 * disabled. However, we want to consider that we could
3808 * be connected to a legacy switch that doesn't advertise
3809 * desired flow control, but can be forced on the link
3810 * partner. So if we advertised no flow control, that is
3811 * what we will resolve to. If we advertised some kind of
3812 * receive capability (Rx Pause Only or Full Flow Control)
3813 * and the link partner advertised none, we will configure
3814 * ourselves to enable Rx Flow Control only. We can do
3815 * this safely for two reasons: If the link partner really
3816 * didn't want flow control enabled, and we enable Rx, no
3817 * harm done since we won't be receiving any PAUSE frames
3818 * anyway. If the intent on the link partner was to have
3819 * flow control enabled, then by us enabling RX only, we
3820 * can at least receive pause frames and process them.
3821 * This is a good idea because in most cases, since we are
3822 * predominantly a server NIC, more times than not we will
3823 * be asked to delay transmission of packets than asking
3824 * our link partner to pause transmission of frames.
3825 */
3826 else if (hw->original_fc == e1000_fc_none ||
3827 hw->original_fc == e1000_fc_tx_pause) {
3828 hw->fc = e1000_fc_none;
3829 DEBUGOUT("Flow Control = NONE.\r\n");
3830 } else {
3831 hw->fc = e1000_fc_rx_pause;
3832 DEBUGOUT
3833 ("Flow Control = RX PAUSE frames only.\r\n");
3834 }
3835
1aeed8d7 3836 /* Now we need to do one last check... If we auto-
682011ff
WD		 3837 * negotiated to HALF DUPLEX, flow control should not be
3838 * enabled per IEEE 802.3 spec.
3839 */
3840 e1000_get_speed_and_duplex(hw, &speed, &duplex);
3841
3842 if (duplex == HALF_DUPLEX)
3843 hw->fc = e1000_fc_none;
3844
3845 /* Now we call a subroutine to actually force the MAC
3846 * controller to use the correct flow control settings.
3847 */
3848 ret_val = e1000_force_mac_fc(hw);
3849 if (ret_val < 0) {
3850 DEBUGOUT
3851 ("Error forcing flow control settings\n");
3852 return ret_val;
3853 }
3854 } else {
3855 DEBUGOUT
3856 ("Copper PHY and Auto Neg has not completed.\r\n");
3857 }
3858 }
aa070789 3859 return E1000_SUCCESS;
682011ff
WD		 3860}
3861
3862/******************************************************************************
3863 * Checks to see if the link status of the hardware has changed.
3864 *
3865 * hw - Struct containing variables accessed by shared code
3866 *
3867 * Called by any function that needs to check the link status of the adapter.
3868 *****************************************************************************/
3869static int
5c5e707a 3870e1000_check_for_link(struct e1000_hw *hw)
682011ff 3871{
682011ff
WD		 3872 uint32_t rxcw;
3873 uint32_t ctrl;
3874 uint32_t status;
3875 uint32_t rctl;
3876 uint32_t signal;
3877 int32_t ret_val;
3878 uint16_t phy_data;
3879 uint16_t lp_capability;
3880
3881 DEBUGFUNC();
3882
8bde7f77
WD		 3883 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
3884 * set when the optics detect a signal. On older adapters, it will be
682011ff
WD		 3885 * cleared when there is a signal
3886 */
3887 ctrl = E1000_READ_REG(hw, CTRL);
3888 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
3889 signal = E1000_CTRL_SWDPIN1;
3890 else
3891 signal = 0;
3892
3893 status = E1000_READ_REG(hw, STATUS);
3894 rxcw = E1000_READ_REG(hw, RXCW);
3895 DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw);
3896
3897 /* If we have a copper PHY then we only want to go out to the PHY
3898 * registers to see if Auto-Neg has completed and/or if our link
1aeed8d7 3899 * status has changed. The get_link_status flag will be set if we
682011ff
WD		 3900 * receive a Link Status Change interrupt or we have Rx Sequence
3901 * Errors.
3902 */
3903 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
3904 /* First we want to see if the MII Status Register reports
3905 * link. If so, then we want to get the current speed/duplex
3906 * of the PHY.
3907 * Read the register twice since the link bit is sticky.
3908 */
3909 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3910 DEBUGOUT("PHY Read Error\n");
3911 return -E1000_ERR_PHY;
3912 }
3913 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3914 DEBUGOUT("PHY Read Error\n");
3915 return -E1000_ERR_PHY;
3916 }
3917
3918 if (phy_data & MII_SR_LINK_STATUS) {
472d5460 3919 hw->get_link_status = false;
682011ff
WD		 3920 } else {
3921 /* No link detected */
3922 return -E1000_ERR_NOLINK;
3923 }
3924
3925 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
3926 * have Si on board that is 82544 or newer, Auto
3927 * Speed Detection takes care of MAC speed/duplex
3928 * configuration. So we only need to configure Collision
3929 * Distance in the MAC. Otherwise, we need to force
3930 * speed/duplex on the MAC to the current PHY speed/duplex
3931 * settings.
3932 */
3933 if (hw->mac_type >= e1000_82544)
3934 e1000_config_collision_dist(hw);
3935 else {
3936 ret_val = e1000_config_mac_to_phy(hw);
3937 if (ret_val < 0) {
3938 DEBUGOUT
3939 ("Error configuring MAC to PHY settings\n");
3940 return ret_val;
3941 }
3942 }
3943
8bde7f77 3944 /* Configure Flow Control now that Auto-Neg has completed. First, we
682011ff
WD		 3945 * need to restore the desired flow control settings because we may
3946 * have had to re-autoneg with a different link partner.
3947 */
3948 ret_val = e1000_config_fc_after_link_up(hw);
3949 if (ret_val < 0) {
3950 DEBUGOUT("Error configuring flow control\n");
3951 return ret_val;
3952 }
3953
3954 /* At this point we know that we are on copper and we have
3955 * auto-negotiated link. These are conditions for checking the link
1aeed8d7 3956 * parter capability register. We use the link partner capability to
682011ff
WD		 3957 * determine if TBI Compatibility needs to be turned on or off. If
3958 * the link partner advertises any speed in addition to Gigabit, then
3959 * we assume that they are GMII-based, and TBI compatibility is not
3960 * needed. If no other speeds are advertised, we assume the link
3961 * partner is TBI-based, and we turn on TBI Compatibility.
3962 */
3963 if (hw->tbi_compatibility_en) {
3964 if (e1000_read_phy_reg
3965 (hw, PHY_LP_ABILITY, &lp_capability) < 0) {
3966 DEBUGOUT("PHY Read Error\n");
3967 return -E1000_ERR_PHY;
3968 }
3969 if (lp_capability & (NWAY_LPAR_10T_HD_CAPS |
3970 NWAY_LPAR_10T_FD_CAPS |
3971 NWAY_LPAR_100TX_HD_CAPS |
3972 NWAY_LPAR_100TX_FD_CAPS |
3973 NWAY_LPAR_100T4_CAPS)) {
8bde7f77 3974 /* If our link partner advertises anything in addition to
682011ff
WD		 3975 * gigabit, we do not need to enable TBI compatibility.
3976 */
3977 if (hw->tbi_compatibility_on) {
3978 /* If we previously were in the mode, turn it off. */
3979 rctl = E1000_READ_REG(hw, RCTL);
3980 rctl &= ~E1000_RCTL_SBP;
3981 E1000_WRITE_REG(hw, RCTL, rctl);
472d5460 3982 hw->tbi_compatibility_on = false;
682011ff
WD		 3983 }
3984 } else {
3985 /* If TBI compatibility is was previously off, turn it on. For
3986 * compatibility with a TBI link partner, we will store bad
3987 * packets. Some frames have an additional byte on the end and
3988 * will look like CRC errors to to the hardware.
3989 */
3990 if (!hw->tbi_compatibility_on) {
472d5460 3991 hw->tbi_compatibility_on = true;
682011ff
WD		 3992 rctl = E1000_READ_REG(hw, RCTL);
3993 rctl |= E1000_RCTL_SBP;
3994 E1000_WRITE_REG(hw, RCTL, rctl);
3995 }
3996 }
3997 }
3998 }
3999 /* If we don't have link (auto-negotiation failed or link partner cannot
4000 * auto-negotiate), the cable is plugged in (we have signal), and our
4001 * link partner is not trying to auto-negotiate with us (we are receiving
4002 * idles or data), we need to force link up. We also need to give
4003 * auto-negotiation time to complete, in case the cable was just plugged
4004 * in. The autoneg_failed flag does this.
4005 */
4006 else if ((hw->media_type == e1000_media_type_fiber) &&
4007 (!(status & E1000_STATUS_LU)) &&
4008 ((ctrl & E1000_CTRL_SWDPIN1) == signal) &&
4009 (!(rxcw & E1000_RXCW_C))) {
4010 if (hw->autoneg_failed == 0) {
4011 hw->autoneg_failed = 1;
4012 return 0;
4013 }
4014 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
4015
4016 /* Disable auto-negotiation in the TXCW register */
4017 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
4018
4019 /* Force link-up and also force full-duplex. */
4020 ctrl = E1000_READ_REG(hw, CTRL);
4021 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
4022 E1000_WRITE_REG(hw, CTRL, ctrl);
4023
4024 /* Configure Flow Control after forcing link up. */
4025 ret_val = e1000_config_fc_after_link_up(hw);
4026 if (ret_val < 0) {
4027 DEBUGOUT("Error configuring flow control\n");
4028 return ret_val;
4029 }
4030 }
4031 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
4032 * auto-negotiation in the TXCW register and disable forced link in the
4033 * Device Control register in an attempt to auto-negotiate with our link
4034 * partner.
4035 */
4036 else if ((hw->media_type == e1000_media_type_fiber) &&
4037 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
4038 DEBUGOUT
4039 ("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
4040 E1000_WRITE_REG(hw, TXCW, hw->txcw);
4041 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
4042 }
4043 return 0;
4044}
4045
aa070789
RZ		 4046/******************************************************************************
4047* Configure the MAC-to-PHY interface for 10/100Mbps
4048*
4049* hw - Struct containing variables accessed by shared code
4050******************************************************************************/
4051static int32_t
4052e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
4053{
4054 int32_t ret_val = E1000_SUCCESS;
4055 uint32_t tipg;
4056 uint16_t reg_data;
4057
4058 DEBUGFUNC();
4059
4060 reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
4061 ret_val = e1000_write_kmrn_reg(hw,
4062 E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
4063 if (ret_val)
4064 return ret_val;
4065
4066 /* Configure Transmit Inter-Packet Gap */
4067 tipg = E1000_READ_REG(hw, TIPG);
4068 tipg &= ~E1000_TIPG_IPGT_MASK;
4069 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
4070 E1000_WRITE_REG(hw, TIPG, tipg);
4071
4072 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
4073
4074 if (ret_val)
4075 return ret_val;
4076
4077 if (duplex == HALF_DUPLEX)
4078 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
4079 else
4080 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
4081
4082 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
4083
4084 return ret_val;
4085}
4086
4087static int32_t
4088e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
4089{
4090 int32_t ret_val = E1000_SUCCESS;
4091 uint16_t reg_data;
4092 uint32_t tipg;
4093
4094 DEBUGFUNC();
4095
4096 reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
4097 ret_val = e1000_write_kmrn_reg(hw,
4098 E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
4099 if (ret_val)
4100 return ret_val;
4101
4102 /* Configure Transmit Inter-Packet Gap */
4103 tipg = E1000_READ_REG(hw, TIPG);
4104 tipg &= ~E1000_TIPG_IPGT_MASK;
4105 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
4106 E1000_WRITE_REG(hw, TIPG, tipg);
4107
4108 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
4109
4110 if (ret_val)
4111 return ret_val;
4112
4113 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
4114 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
4115
4116 return ret_val;
4117}
4118
682011ff
WD		 4119/******************************************************************************
4120 * Detects the current speed and duplex settings of the hardware.
4121 *
4122 * hw - Struct containing variables accessed by shared code
4123 * speed - Speed of the connection
4124 * duplex - Duplex setting of the connection
4125 *****************************************************************************/
aa070789
RZ		 4126static int
4127e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed,
4128 uint16_t *duplex)
682011ff
WD		 4129{
4130 uint32_t status;
aa070789
RZ		 4131 int32_t ret_val;
4132 uint16_t phy_data;
682011ff
WD		 4133
4134 DEBUGFUNC();
4135
4136 if (hw->mac_type >= e1000_82543) {
4137 status = E1000_READ_REG(hw, STATUS);
4138 if (status & E1000_STATUS_SPEED_1000) {
4139 *speed = SPEED_1000;
4140 DEBUGOUT("1000 Mbs, ");
4141 } else if (status & E1000_STATUS_SPEED_100) {
4142 *speed = SPEED_100;
4143 DEBUGOUT("100 Mbs, ");
4144 } else {
4145 *speed = SPEED_10;
4146 DEBUGOUT("10 Mbs, ");
4147 }
4148
4149 if (status & E1000_STATUS_FD) {
4150 *duplex = FULL_DUPLEX;
4151 DEBUGOUT("Full Duplex\r\n");
4152 } else {
4153 *duplex = HALF_DUPLEX;
4154 DEBUGOUT(" Half Duplex\r\n");
4155 }
4156 } else {
4157 DEBUGOUT("1000 Mbs, Full Duplex\r\n");
4158 *speed = SPEED_1000;
4159 *duplex = FULL_DUPLEX;
4160 }
aa070789
RZ		 4161
4162 /* IGP01 PHY may advertise full duplex operation after speed downgrade
4163 * even if it is operating at half duplex. Here we set the duplex
4164 * settings to match the duplex in the link partner's capabilities.
4165 */
4166 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
4167 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
4168 if (ret_val)
4169 return ret_val;
4170
4171 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
4172 *duplex = HALF_DUPLEX;
4173 else {
4174 ret_val = e1000_read_phy_reg(hw,
4175 PHY_LP_ABILITY, &phy_data);
4176 if (ret_val)
4177 return ret_val;
4178 if ((*speed == SPEED_100 &&
4179 !(phy_data & NWAY_LPAR_100TX_FD_CAPS))
4180 || (*speed == SPEED_10
4181 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
4182 *duplex = HALF_DUPLEX;
4183 }
4184 }
4185
4186 if ((hw->mac_type == e1000_80003es2lan) &&
4187 (hw->media_type == e1000_media_type_copper)) {
4188 if (*speed == SPEED_1000)
4189 ret_val = e1000_configure_kmrn_for_1000(hw);
4190 else
4191 ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
4192 if (ret_val)
4193 return ret_val;
4194 }
4195 return E1000_SUCCESS;
682011ff
WD		 4196}
4197
4198/******************************************************************************
4199* Blocks until autoneg completes or times out (~4.5 seconds)
4200*
4201* hw - Struct containing variables accessed by shared code
4202******************************************************************************/
4203static int
4204e1000_wait_autoneg(struct e1000_hw *hw)
4205{
4206 uint16_t i;
4207 uint16_t phy_data;
4208
4209 DEBUGFUNC();
4210 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
4211
faa765d4 4212 /* We will wait for autoneg to complete or timeout to expire. */
682011ff
WD		 4213 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
4214 /* Read the MII Status Register and wait for Auto-Neg
4215 * Complete bit to be set.
4216 */
4217 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
4218 DEBUGOUT("PHY Read Error\n");
4219 return -E1000_ERR_PHY;
4220 }
4221 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
4222 DEBUGOUT("PHY Read Error\n");
4223 return -E1000_ERR_PHY;
4224 }
4225 if (phy_data & MII_SR_AUTONEG_COMPLETE) {
4226 DEBUGOUT("Auto-Neg complete.\n");
4227 return 0;
4228 }
4229 mdelay(100);
4230 }
4231 DEBUGOUT("Auto-Neg timedout.\n");
4232 return -E1000_ERR_TIMEOUT;
4233}
4234
4235/******************************************************************************
4236* Raises the Management Data Clock
4237*
4238* hw - Struct containing variables accessed by shared code
4239* ctrl - Device control register's current value
4240******************************************************************************/
4241static void
4242e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
4243{
4244 /* Raise the clock input to the Management Data Clock (by setting the MDC
4245 * bit), and then delay 2 microseconds.
4246 */
4247 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
4248 E1000_WRITE_FLUSH(hw);
4249 udelay(2);
4250}
4251
4252/******************************************************************************
4253* Lowers the Management Data Clock
4254*
4255* hw - Struct containing variables accessed by shared code
4256* ctrl - Device control register's current value
4257******************************************************************************/
4258static void
4259e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
4260{
4261 /* Lower the clock input to the Management Data Clock (by clearing the MDC
4262 * bit), and then delay 2 microseconds.
4263 */
4264 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
4265 E1000_WRITE_FLUSH(hw);
4266 udelay(2);
4267}
4268
4269/******************************************************************************
4270* Shifts data bits out to the PHY
4271*
4272* hw - Struct containing variables accessed by shared code
4273* data - Data to send out to the PHY
4274* count - Number of bits to shift out
4275*
4276* Bits are shifted out in MSB to LSB order.
4277******************************************************************************/
4278static void
4279e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count)
4280{
4281 uint32_t ctrl;
4282 uint32_t mask;
4283
4284 /* We need to shift "count" number of bits out to the PHY. So, the value
8bde7f77 4285 * in the "data" parameter will be shifted out to the PHY one bit at a
682011ff
WD		 4286 * time. In order to do this, "data" must be broken down into bits.
4287 */
4288 mask = 0x01;
4289 mask <<= (count - 1);
4290
4291 ctrl = E1000_READ_REG(hw, CTRL);
4292
4293 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
4294 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
4295
4296 while (mask) {
4297 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
4298 * then raising and lowering the Management Data Clock. A "0" is
4299 * shifted out to the PHY by setting the MDIO bit to "0" and then
4300 * raising and lowering the clock.
4301 */
4302 if (data & mask)
4303 ctrl |= E1000_CTRL_MDIO;
4304 else
4305 ctrl &= ~E1000_CTRL_MDIO;
4306
4307 E1000_WRITE_REG(hw, CTRL, ctrl);
4308 E1000_WRITE_FLUSH(hw);
4309
4310 udelay(2);
4311
4312 e1000_raise_mdi_clk(hw, &ctrl);
4313 e1000_lower_mdi_clk(hw, &ctrl);
4314
4315 mask = mask >> 1;
4316 }
4317}
4318
4319/******************************************************************************
4320* Shifts data bits in from the PHY
4321*
4322* hw - Struct containing variables accessed by shared code
4323*
8bde7f77 4324* Bits are shifted in in MSB to LSB order.
682011ff
WD		 4325******************************************************************************/
4326static uint16_t
4327e1000_shift_in_mdi_bits(struct e1000_hw *hw)
4328{
4329 uint32_t ctrl;
4330 uint16_t data = 0;
4331 uint8_t i;
4332
4333 /* In order to read a register from the PHY, we need to shift in a total
4334 * of 18 bits from the PHY. The first two bit (turnaround) times are used
4335 * to avoid contention on the MDIO pin when a read operation is performed.
4336 * These two bits are ignored by us and thrown away. Bits are "shifted in"
4337 * by raising the input to the Management Data Clock (setting the MDC bit),
4338 * and then reading the value of the MDIO bit.
4339 */
4340 ctrl = E1000_READ_REG(hw, CTRL);
4341
4342 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
4343 ctrl &= ~E1000_CTRL_MDIO_DIR;
4344 ctrl &= ~E1000_CTRL_MDIO;
4345
4346 E1000_WRITE_REG(hw, CTRL, ctrl);
4347 E1000_WRITE_FLUSH(hw);
4348
4349 /* Raise and Lower the clock before reading in the data. This accounts for
4350 * the turnaround bits. The first clock occurred when we clocked out the
4351 * last bit of the Register Address.
4352 */
4353 e1000_raise_mdi_clk(hw, &ctrl);
4354 e1000_lower_mdi_clk(hw, &ctrl);
4355
4356 for (data = 0, i = 0; i < 16; i++) {
4357 data = data << 1;
4358 e1000_raise_mdi_clk(hw, &ctrl);
4359 ctrl = E1000_READ_REG(hw, CTRL);
4360 /* Check to see if we shifted in a "1". */
4361 if (ctrl & E1000_CTRL_MDIO)
4362 data |= 1;
4363 e1000_lower_mdi_clk(hw, &ctrl);
4364 }
4365
4366 e1000_raise_mdi_clk(hw, &ctrl);
4367 e1000_lower_mdi_clk(hw, &ctrl);
4368
4369 return data;
4370}
4371
4372/*****************************************************************************
4373* Reads the value from a PHY register
4374*
4375* hw - Struct containing variables accessed by shared code
4376* reg_addr - address of the PHY register to read
4377******************************************************************************/
4378static int
4379e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data)
4380{
4381 uint32_t i;
4382 uint32_t mdic = 0;
4383 const uint32_t phy_addr = 1;
4384
4385 if (reg_addr > MAX_PHY_REG_ADDRESS) {
4386 DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
4387 return -E1000_ERR_PARAM;
4388 }
4389
4390 if (hw->mac_type > e1000_82543) {
4391 /* Set up Op-code, Phy Address, and register address in the MDI
4392 * Control register. The MAC will take care of interfacing with the
4393 * PHY to retrieve the desired data.
4394 */
4395 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
4396 (phy_addr << E1000_MDIC_PHY_SHIFT) |
4397 (E1000_MDIC_OP_READ));
4398
4399 E1000_WRITE_REG(hw, MDIC, mdic);
4400
4401 /* Poll the ready bit to see if the MDI read completed */
4402 for (i = 0; i < 64; i++) {
4403 udelay(10);
4404 mdic = E1000_READ_REG(hw, MDIC);
4405 if (mdic & E1000_MDIC_READY)
4406 break;
4407 }
4408 if (!(mdic & E1000_MDIC_READY)) {
4409 DEBUGOUT("MDI Read did not complete\n");
4410 return -E1000_ERR_PHY;
4411 }
4412 if (mdic & E1000_MDIC_ERROR) {
4413 DEBUGOUT("MDI Error\n");
4414 return -E1000_ERR_PHY;
4415 }
4416 *phy_data = (uint16_t) mdic;
4417 } else {
4418 /* We must first send a preamble through the MDIO pin to signal the
4419 * beginning of an MII instruction. This is done by sending 32
4420 * consecutive "1" bits.
4421 */
4422 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
4423
4424 /* Now combine the next few fields that are required for a read
4425 * operation. We use this method instead of calling the
4426 * e1000_shift_out_mdi_bits routine five different times. The format of
4427 * a MII read instruction consists of a shift out of 14 bits and is
4428 * defined as follows:
4429 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
4430 * followed by a shift in of 18 bits. This first two bits shifted in
4431 * are TurnAround bits used to avoid contention on the MDIO pin when a
4432 * READ operation is performed. These two bits are thrown away
4433 * followed by a shift in of 16 bits which contains the desired data.
4434 */
4435 mdic = ((reg_addr) | (phy_addr << 5) |
4436 (PHY_OP_READ << 10) | (PHY_SOF << 12));
4437
4438 e1000_shift_out_mdi_bits(hw, mdic, 14);
4439
4440 /* Now that we've shifted out the read command to the MII, we need to
4441 * "shift in" the 16-bit value (18 total bits) of the requested PHY
4442 * register address.
4443 */
4444 *phy_data = e1000_shift_in_mdi_bits(hw);
4445 }
4446 return 0;
4447}
4448
4449/******************************************************************************
4450* Writes a value to a PHY register
4451*
4452* hw - Struct containing variables accessed by shared code
4453* reg_addr - address of the PHY register to write
4454* data - data to write to the PHY
4455******************************************************************************/
4456static int
4457e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data)
4458{
4459 uint32_t i;
4460 uint32_t mdic = 0;
4461 const uint32_t phy_addr = 1;
4462
4463 if (reg_addr > MAX_PHY_REG_ADDRESS) {
4464 DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
4465 return -E1000_ERR_PARAM;
4466 }
4467
4468 if (hw->mac_type > e1000_82543) {
4469 /* Set up Op-code, Phy Address, register address, and data intended
4470 * for the PHY register in the MDI Control register. The MAC will take
4471 * care of interfacing with the PHY to send the desired data.
4472 */
4473 mdic = (((uint32_t) phy_data) |
4474 (reg_addr << E1000_MDIC_REG_SHIFT) |
4475 (phy_addr << E1000_MDIC_PHY_SHIFT) |
4476 (E1000_MDIC_OP_WRITE));
4477
4478 E1000_WRITE_REG(hw, MDIC, mdic);
4479
4480 /* Poll the ready bit to see if the MDI read completed */
4481 for (i = 0; i < 64; i++) {
4482 udelay(10);
4483 mdic = E1000_READ_REG(hw, MDIC);
4484 if (mdic & E1000_MDIC_READY)
4485 break;
4486 }
4487 if (!(mdic & E1000_MDIC_READY)) {
4488 DEBUGOUT("MDI Write did not complete\n");
4489 return -E1000_ERR_PHY;
4490 }
4491 } else {
4492 /* We'll need to use the SW defined pins to shift the write command
4493 * out to the PHY. We first send a preamble to the PHY to signal the
8bde7f77 4494 * beginning of the MII instruction. This is done by sending 32
682011ff
WD		 4495 * consecutive "1" bits.
4496 */
4497 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
4498
8bde7f77 4499 /* Now combine the remaining required fields that will indicate a
682011ff
WD		 4500 * write operation. We use this method instead of calling the
4501 * e1000_shift_out_mdi_bits routine for each field in the command. The
4502 * format of a MII write instruction is as follows:
4503 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
4504 */
4505 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
4506 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
4507 mdic <<= 16;
4508 mdic |= (uint32_t) phy_data;
4509
4510 e1000_shift_out_mdi_bits(hw, mdic, 32);
4511 }
4512 return 0;
4513}
4514
aa070789
RZ		 4515/******************************************************************************
4516 * Checks if PHY reset is blocked due to SOL/IDER session, for example.
4517 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to
4518 * the caller to figure out how to deal with it.
4519 *
4520 * hw - Struct containing variables accessed by shared code
4521 *
4522 * returns: - E1000_BLK_PHY_RESET
4523 * E1000_SUCCESS
4524 *
4525 *****************************************************************************/
4526int32_t
4527e1000_check_phy_reset_block(struct e1000_hw *hw)
4528{
4529 uint32_t manc = 0;
4530 uint32_t fwsm = 0;
4531
4532 if (hw->mac_type == e1000_ich8lan) {
4533 fwsm = E1000_READ_REG(hw, FWSM);
4534 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
4535 : E1000_BLK_PHY_RESET;
4536 }
4537
4538 if (hw->mac_type > e1000_82547_rev_2)
4539 manc = E1000_READ_REG(hw, MANC);
4540 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
4541 E1000_BLK_PHY_RESET : E1000_SUCCESS;
4542}
4543
4544/***************************************************************************
4545 * Checks if the PHY configuration is done
4546 *
4547 * hw: Struct containing variables accessed by shared code
4548 *
4549 * returns: - E1000_ERR_RESET if fail to reset MAC
4550 * E1000_SUCCESS at any other case.
4551 *
4552 ***************************************************************************/
4553static int32_t
4554e1000_get_phy_cfg_done(struct e1000_hw *hw)
4555{
4556 int32_t timeout = PHY_CFG_TIMEOUT;
4557 uint32_t cfg_mask = E1000_EEPROM_CFG_DONE;
4558
4559 DEBUGFUNC();
4560
4561 switch (hw->mac_type) {
4562 default:
4563 mdelay(10);
4564 break;
987b43a1 4565
aa070789
RZ		 4566 case e1000_80003es2lan:
4567 /* Separate *_CFG_DONE_* bit for each port */
987b43a1 4568 if (e1000_is_second_port(hw))
aa070789 4569 cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
987b43a1
KM		 4570 /* Fall Through */
4571
aa070789
RZ		 4572 case e1000_82571:
4573 case e1000_82572:
95186063 4574 case e1000_igb:
aa070789 4575 while (timeout) {
95186063
MV		 4576 if (hw->mac_type == e1000_igb) {
4577 if (E1000_READ_REG(hw, I210_EEMNGCTL) & cfg_mask)
4578 break;
4579 } else {
4580 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
4581 break;
4582 }
4583 mdelay(1);
aa070789
RZ		 4584 timeout--;
4585 }
4586 if (!timeout) {
4587 DEBUGOUT("MNG configuration cycle has not "
4588 "completed.\n");
4589 return -E1000_ERR_RESET;
4590 }
4591 break;
4592 }
4593
4594 return E1000_SUCCESS;
4595}
4596
682011ff
WD		 4597/******************************************************************************
4598* Returns the PHY to the power-on reset state
4599*
4600* hw - Struct containing variables accessed by shared code
4601******************************************************************************/
aa070789 4602int32_t
682011ff
WD		 4603e1000_phy_hw_reset(struct e1000_hw *hw)
4604{
987b43a1 4605 uint16_t swfw = E1000_SWFW_PHY0_SM;
aa070789
RZ		 4606 uint32_t ctrl, ctrl_ext;
4607 uint32_t led_ctrl;
4608 int32_t ret_val;
682011ff
WD		 4609
4610 DEBUGFUNC();
4611
aa070789
RZ		 4612 /* In the case of the phy reset being blocked, it's not an error, we
4613 * simply return success without performing the reset. */
4614 ret_val = e1000_check_phy_reset_block(hw);
4615 if (ret_val)
4616 return E1000_SUCCESS;
4617
682011ff
WD		 4618 DEBUGOUT("Resetting Phy...\n");
4619
4620 if (hw->mac_type > e1000_82543) {
987b43a1 4621 if (e1000_is_second_port(hw))
aa070789 4622 swfw = E1000_SWFW_PHY1_SM;
987b43a1 4623
aa070789
RZ		 4624 if (e1000_swfw_sync_acquire(hw, swfw)) {
4625 DEBUGOUT("Unable to acquire swfw sync\n");
4626 return -E1000_ERR_SWFW_SYNC;
4627 }
987b43a1 4628
682011ff
WD		 4629 /* Read the device control register and assert the E1000_CTRL_PHY_RST
4630 * bit. Then, take it out of reset.
4631 */
4632 ctrl = E1000_READ_REG(hw, CTRL);
4633 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
4634 E1000_WRITE_FLUSH(hw);
aa070789
RZ		 4635
4636 if (hw->mac_type < e1000_82571)
4637 udelay(10);
4638 else
4639 udelay(100);
4640
682011ff
WD		 4641 E1000_WRITE_REG(hw, CTRL, ctrl);
4642 E1000_WRITE_FLUSH(hw);
aa070789
RZ		 4643
4644 if (hw->mac_type >= e1000_82571)
4645 mdelay(10);
3c63dd53 4646
682011ff
WD		 4647 } else {
4648 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
4649 * bit to put the PHY into reset. Then, take it out of reset.
4650 */
4651 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
4652 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
4653 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
4654 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4655 E1000_WRITE_FLUSH(hw);
4656 mdelay(10);
4657 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
4658 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4659 E1000_WRITE_FLUSH(hw);
4660 }
4661 udelay(150);
aa070789
RZ		 4662
4663 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
4664 /* Configure activity LED after PHY reset */
4665 led_ctrl = E1000_READ_REG(hw, LEDCTL);
4666 led_ctrl &= IGP_ACTIVITY_LED_MASK;
4667 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
4668 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
4669 }
4670
7e2d991d
TH		 4671 e1000_swfw_sync_release(hw, swfw);
4672
aa070789
RZ		 4673 /* Wait for FW to finish PHY configuration. */
4674 ret_val = e1000_get_phy_cfg_done(hw);
4675 if (ret_val != E1000_SUCCESS)
4676 return ret_val;
4677
4678 return ret_val;
4679}
4680
4681/******************************************************************************
4682 * IGP phy init script - initializes the GbE PHY
4683 *
4684 * hw - Struct containing variables accessed by shared code
4685 *****************************************************************************/
4686static void
4687e1000_phy_init_script(struct e1000_hw *hw)
4688{
4689 uint32_t ret_val;
4690 uint16_t phy_saved_data;
4691 DEBUGFUNC();
4692
4693 if (hw->phy_init_script) {
4694 mdelay(20);
4695
4696 /* Save off the current value of register 0x2F5B to be
4697 * restored at the end of this routine. */
4698 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
4699
4700 /* Disabled the PHY transmitter */
4701 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
4702
4703 mdelay(20);
4704
4705 e1000_write_phy_reg(hw, 0x0000, 0x0140);
4706
4707 mdelay(5);
4708
4709 switch (hw->mac_type) {
4710 case e1000_82541:
4711 case e1000_82547:
4712 e1000_write_phy_reg(hw, 0x1F95, 0x0001);
4713
4714 e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
4715
4716 e1000_write_phy_reg(hw, 0x1F79, 0x0018);
4717
4718 e1000_write_phy_reg(hw, 0x1F30, 0x1600);
4719
4720 e1000_write_phy_reg(hw, 0x1F31, 0x0014);
4721
4722 e1000_write_phy_reg(hw, 0x1F32, 0x161C);
4723
4724 e1000_write_phy_reg(hw, 0x1F94, 0x0003);
4725
4726 e1000_write_phy_reg(hw, 0x1F96, 0x003F);
4727
4728 e1000_write_phy_reg(hw, 0x2010, 0x0008);
4729 break;
4730
4731 case e1000_82541_rev_2:
4732 case e1000_82547_rev_2:
4733 e1000_write_phy_reg(hw, 0x1F73, 0x0099);
4734 break;
4735 default:
4736 break;
4737 }
4738
4739 e1000_write_phy_reg(hw, 0x0000, 0x3300);
4740
4741 mdelay(20);
4742
4743 /* Now enable the transmitter */
56b13b1e
ZRR		 4744 if (!ret_val)
4745 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
aa070789
RZ		 4746
4747 if (hw->mac_type == e1000_82547) {
4748 uint16_t fused, fine, coarse;
4749
4750 /* Move to analog registers page */
4751 e1000_read_phy_reg(hw,
4752 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
4753
4754 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
4755 e1000_read_phy_reg(hw,
4756 IGP01E1000_ANALOG_FUSE_STATUS, &fused);
4757
4758 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
4759 coarse = fused
4760 & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
4761
4762 if (coarse >
4763 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
4764 coarse -=
4765 IGP01E1000_ANALOG_FUSE_COARSE_10;
4766 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
4767 } else if (coarse
4768 == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
4769 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
4770
4771 fused = (fused
4772 & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
4773 (fine
4774 & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
4775 (coarse
4776 & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
4777
4778 e1000_write_phy_reg(hw,
4779 IGP01E1000_ANALOG_FUSE_CONTROL, fused);
4780 e1000_write_phy_reg(hw,
4781 IGP01E1000_ANALOG_FUSE_BYPASS,
4782 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
4783 }
4784 }
4785 }
682011ff
WD		 4786}
4787
4788/******************************************************************************
4789* Resets the PHY
4790*
4791* hw - Struct containing variables accessed by shared code
4792*
aa070789 4793* Sets bit 15 of the MII Control register
682011ff 4794******************************************************************************/
aa070789 4795int32_t
682011ff
WD		 4796e1000_phy_reset(struct e1000_hw *hw)
4797{
aa070789 4798 int32_t ret_val;
682011ff
WD		 4799 uint16_t phy_data;
4800
4801 DEBUGFUNC();
4802
aa070789
RZ		 4803 /* In the case of the phy reset being blocked, it's not an error, we
4804 * simply return success without performing the reset. */
4805 ret_val = e1000_check_phy_reset_block(hw);
4806 if (ret_val)
4807 return E1000_SUCCESS;
4808
4809 switch (hw->phy_type) {
4810 case e1000_phy_igp:
4811 case e1000_phy_igp_2:
4812 case e1000_phy_igp_3:
4813 case e1000_phy_ife:
95186063 4814 case e1000_phy_igb:
aa070789
RZ		 4815 ret_val = e1000_phy_hw_reset(hw);
4816 if (ret_val)
4817 return ret_val;
4818 break;
4819 default:
4820 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
4821 if (ret_val)
4822 return ret_val;
4823
4824 phy_data |= MII_CR_RESET;
4825 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
4826 if (ret_val)
4827 return ret_val;
4828
4829 udelay(1);
4830 break;
682011ff 4831 }
aa070789
RZ		 4832
4833 if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
4834 e1000_phy_init_script(hw);
4835
4836 return E1000_SUCCESS;
682011ff
WD		 4837}
4838
1aeed8d7 4839static int e1000_set_phy_type (struct e1000_hw *hw)
ac3315c2 4840{
1aeed8d7
WD		 4841 DEBUGFUNC ();
4842
4843 if (hw->mac_type == e1000_undefined)
4844 return -E1000_ERR_PHY_TYPE;
4845
4846 switch (hw->phy_id) {
4847 case M88E1000_E_PHY_ID:
4848 case M88E1000_I_PHY_ID:
4849 case M88E1011_I_PHY_ID:
aa070789 4850 case M88E1111_I_PHY_ID:
1aeed8d7
WD		 4851 hw->phy_type = e1000_phy_m88;
4852 break;
4853 case IGP01E1000_I_PHY_ID:
4854 if (hw->mac_type == e1000_82541 ||
aa070789
RZ		 4855 hw->mac_type == e1000_82541_rev_2 ||
4856 hw->mac_type == e1000_82547 ||
4857 hw->mac_type == e1000_82547_rev_2) {
1aeed8d7 4858 hw->phy_type = e1000_phy_igp;
aa070789
RZ		 4859 break;
4860 }
4861 case IGP03E1000_E_PHY_ID:
4862 hw->phy_type = e1000_phy_igp_3;
4863 break;
4864 case IFE_E_PHY_ID:
4865 case IFE_PLUS_E_PHY_ID:
4866 case IFE_C_E_PHY_ID:
4867 hw->phy_type = e1000_phy_ife;
4868 break;
4869 case GG82563_E_PHY_ID:
4870 if (hw->mac_type == e1000_80003es2lan) {
4871 hw->phy_type = e1000_phy_gg82563;
1aeed8d7
WD		 4872 break;
4873 }
2c2668f9
RZ		 4874 case BME1000_E_PHY_ID:
4875 hw->phy_type = e1000_phy_bm;
4876 break;
95186063
MV		 4877 case I210_I_PHY_ID:
4878 hw->phy_type = e1000_phy_igb;
4879 break;
1aeed8d7
WD		 4880 /* Fall Through */
4881 default:
4882 /* Should never have loaded on this device */
4883 hw->phy_type = e1000_phy_undefined;
4884 return -E1000_ERR_PHY_TYPE;
4885 }
4886
4887 return E1000_SUCCESS;
ac3315c2
AS		 4888}
4889
682011ff
WD		 4890/******************************************************************************
4891* Probes the expected PHY address for known PHY IDs
4892*
4893* hw - Struct containing variables accessed by shared code
4894******************************************************************************/
aa070789 4895static int32_t
682011ff
WD		 4896e1000_detect_gig_phy(struct e1000_hw *hw)
4897{
aa070789 4898 int32_t phy_init_status, ret_val;
682011ff 4899 uint16_t phy_id_high, phy_id_low;
472d5460 4900 bool match = false;
682011ff
WD		 4901
4902 DEBUGFUNC();
4903
aa070789
RZ		 4904 /* The 82571 firmware may still be configuring the PHY. In this
4905 * case, we cannot access the PHY until the configuration is done. So
4906 * we explicitly set the PHY values. */
4907 if (hw->mac_type == e1000_82571 ||
4908 hw->mac_type == e1000_82572) {
4909 hw->phy_id = IGP01E1000_I_PHY_ID;
4910 hw->phy_type = e1000_phy_igp_2;
4911 return E1000_SUCCESS;
682011ff 4912 }
aa070789
RZ		 4913
4914 /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a
4915 * work- around that forces PHY page 0 to be set or the reads fail.
4916 * The rest of the code in this routine uses e1000_read_phy_reg to
4917 * read the PHY ID. So for ESB-2 we need to have this set so our
4918 * reads won't fail. If the attached PHY is not a e1000_phy_gg82563,
4919 * the routines below will figure this out as well. */
4920 if (hw->mac_type == e1000_80003es2lan)
4921 hw->phy_type = e1000_phy_gg82563;
4922
4923 /* Read the PHY ID Registers to identify which PHY is onboard. */
4924 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
4925 if (ret_val)
4926 return ret_val;
4927
682011ff 4928 hw->phy_id = (uint32_t) (phy_id_high << 16);
aa070789
RZ		 4929 udelay(20);
4930 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
4931 if (ret_val)
4932 return ret_val;
4933
682011ff 4934 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
aa070789 4935 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
682011ff
WD		 4936
4937 switch (hw->mac_type) {
4938 case e1000_82543:
4939 if (hw->phy_id == M88E1000_E_PHY_ID)
472d5460 4940 match = true;
682011ff
WD		 4941 break;
4942 case e1000_82544:
4943 if (hw->phy_id == M88E1000_I_PHY_ID)
472d5460 4944 match = true;
682011ff
WD		 4945 break;
4946 case e1000_82540:
4947 case e1000_82545:
aa070789 4948 case e1000_82545_rev_3:
682011ff 4949 case e1000_82546:
aa070789 4950 case e1000_82546_rev_3:
682011ff 4951 if (hw->phy_id == M88E1011_I_PHY_ID)
472d5460 4952 match = true;
682011ff 4953 break;
aa070789 4954 case e1000_82541:
ac3315c2 4955 case e1000_82541_rev_2:
aa070789
RZ		 4956 case e1000_82547:
4957 case e1000_82547_rev_2:
ac3315c2 4958 if(hw->phy_id == IGP01E1000_I_PHY_ID)
472d5460 4959 match = true;
ac3315c2
AS		 4960
4961 break;
aa070789
RZ		 4962 case e1000_82573:
4963 if (hw->phy_id == M88E1111_I_PHY_ID)
472d5460 4964 match = true;
aa070789 4965 break;
2c2668f9
RZ		 4966 case e1000_82574:
4967 if (hw->phy_id == BME1000_E_PHY_ID)
472d5460 4968 match = true;
2c2668f9 4969 break;
aa070789
RZ		 4970 case e1000_80003es2lan:
4971 if (hw->phy_id == GG82563_E_PHY_ID)
472d5460 4972 match = true;
aa070789
RZ		 4973 break;
4974 case e1000_ich8lan:
4975 if (hw->phy_id == IGP03E1000_E_PHY_ID)
472d5460 4976 match = true;
aa070789 4977 if (hw->phy_id == IFE_E_PHY_ID)
472d5460 4978 match = true;
aa070789 4979 if (hw->phy_id == IFE_PLUS_E_PHY_ID)
472d5460 4980 match = true;
aa070789 4981 if (hw->phy_id == IFE_C_E_PHY_ID)
472d5460 4982 match = true;
aa070789 4983 break;
95186063
MV		 4984 case e1000_igb:
4985 if (hw->phy_id == I210_I_PHY_ID)
4986 match = true;
4987 break;
682011ff
WD		 4988 default:
4989 DEBUGOUT("Invalid MAC type %d\n", hw->mac_type);
4990 return -E1000_ERR_CONFIG;
4991 }
ac3315c2
AS		 4992
4993 phy_init_status = e1000_set_phy_type(hw);
4994
4995 if ((match) && (phy_init_status == E1000_SUCCESS)) {
682011ff
WD		 4996 DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id);
4997 return 0;
4998 }
4999 DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id);
5000 return -E1000_ERR_PHY;
5001}
5002
aa070789
RZ		 5003/*****************************************************************************
5004 * Set media type and TBI compatibility.
5005 *
5006 * hw - Struct containing variables accessed by shared code
5007 * **************************************************************************/
5008void
5009e1000_set_media_type(struct e1000_hw *hw)
5010{
5011 uint32_t status;
5012
5013 DEBUGFUNC();
5014
5015 if (hw->mac_type != e1000_82543) {
5016 /* tbi_compatibility is only valid on 82543 */
472d5460 5017 hw->tbi_compatibility_en = false;
aa070789
RZ		 5018 }
5019
5020 switch (hw->device_id) {
5021 case E1000_DEV_ID_82545GM_SERDES:
5022 case E1000_DEV_ID_82546GB_SERDES:
5023 case E1000_DEV_ID_82571EB_SERDES:
5024 case E1000_DEV_ID_82571EB_SERDES_DUAL:
5025 case E1000_DEV_ID_82571EB_SERDES_QUAD:
5026 case E1000_DEV_ID_82572EI_SERDES:
5027 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
5028 hw->media_type = e1000_media_type_internal_serdes;
5029 break;
5030 default:
5031 switch (hw->mac_type) {
5032 case e1000_82542_rev2_0:
5033 case e1000_82542_rev2_1:
5034 hw->media_type = e1000_media_type_fiber;
5035 break;
5036 case e1000_ich8lan:
5037 case e1000_82573:
2c2668f9 5038 case e1000_82574:
95186063 5039 case e1000_igb:
aa070789
RZ		 5040 /* The STATUS_TBIMODE bit is reserved or reused
5041 * for the this device.
5042 */
5043 hw->media_type = e1000_media_type_copper;
5044 break;
5045 default:
5046 status = E1000_READ_REG(hw, STATUS);
5047 if (status & E1000_STATUS_TBIMODE) {
5048 hw->media_type = e1000_media_type_fiber;
5049 /* tbi_compatibility not valid on fiber */
472d5460 5050 hw->tbi_compatibility_en = false;
aa070789
RZ		 5051 } else {
5052 hw->media_type = e1000_media_type_copper;
5053 }
5054 break;
5055 }
5056 }
5057}
5058
682011ff
WD		 5059/**
5060 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
5061 *
5062 * e1000_sw_init initializes the Adapter private data structure.
5063 * Fields are initialized based on PCI device information and
5064 * OS network device settings (MTU size).
5065 **/
5066
5067static int
5c5e707a 5068e1000_sw_init(struct e1000_hw *hw)
682011ff 5069{
682011ff
WD		 5070 int result;
5071
5072 /* PCI config space info */
81dab9af
BM		 5073#ifdef CONFIG_DM_ETH
5074 dm_pci_read_config16(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id);
5075 dm_pci_read_config16(hw->pdev, PCI_DEVICE_ID, &hw->device_id);
5076 dm_pci_read_config16(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID,
5077 &hw->subsystem_vendor_id);
5078 dm_pci_read_config16(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
5079
5080 dm_pci_read_config8(hw->pdev, PCI_REVISION_ID, &hw->revision_id);
5081 dm_pci_read_config16(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word);
5082#else
682011ff
WD		 5083 pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id);
5084 pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id);
5085 pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID,
5086 &hw->subsystem_vendor_id);
5087 pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
5088
5089 pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id);
5090 pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word);
81dab9af 5091#endif
682011ff
WD		 5092
5093 /* identify the MAC */
5094 result = e1000_set_mac_type(hw);
5095 if (result) {
5c5e707a 5096 E1000_ERR(hw, "Unknown MAC Type\n");
682011ff
WD		 5097 return result;
5098 }
5099
aa070789
RZ		 5100 switch (hw->mac_type) {
5101 default:
5102 break;
5103 case e1000_82541:
5104 case e1000_82547:
5105 case e1000_82541_rev_2:
5106 case e1000_82547_rev_2:
5107 hw->phy_init_script = 1;
5108 break;
5109 }
5110
682011ff
WD		 5111 /* flow control settings */
5112 hw->fc_high_water = E1000_FC_HIGH_THRESH;
5113 hw->fc_low_water = E1000_FC_LOW_THRESH;
5114 hw->fc_pause_time = E1000_FC_PAUSE_TIME;
5115 hw->fc_send_xon = 1;
5116
5117 /* Media type - copper or fiber */
95186063 5118 hw->tbi_compatibility_en = true;
aa070789 5119 e1000_set_media_type(hw);
682011ff
WD		 5120
5121 if (hw->mac_type >= e1000_82543) {
5122 uint32_t status = E1000_READ_REG(hw, STATUS);
5123
5124 if (status & E1000_STATUS_TBIMODE) {
5125 DEBUGOUT("fiber interface\n");
5126 hw->media_type = e1000_media_type_fiber;
5127 } else {
5128 DEBUGOUT("copper interface\n");
5129 hw->media_type = e1000_media_type_copper;
5130 }
5131 } else {
5132 hw->media_type = e1000_media_type_fiber;
5133 }
5134
472d5460 5135 hw->wait_autoneg_complete = true;
682011ff
WD		 5136 if (hw->mac_type < e1000_82543)
5137 hw->report_tx_early = 0;
5138 else
5139 hw->report_tx_early = 1;
5140
682011ff
WD		 5141 return E1000_SUCCESS;
5142}
5143
5144void
5145fill_rx(struct e1000_hw *hw)
5146{
5147 struct e1000_rx_desc *rd;
06e07f65 5148 unsigned long flush_start, flush_end;
682011ff
WD		 5149
5150 rx_last = rx_tail;
5151 rd = rx_base + rx_tail;
5152 rx_tail = (rx_tail + 1) % 8;
5153 memset(rd, 0, 16);
06e07f65 5154 rd->buffer_addr = cpu_to_le64((unsigned long)packet);
873e8e01
MV		 5155
5156 /*
5157 * Make sure there are no stale data in WB over this area, which
5158 * might get written into the memory while the e1000 also writes
5159 * into the same memory area.
5160 */
06e07f65
ML		 5161 invalidate_dcache_range((unsigned long)packet,
5162 (unsigned long)packet + 4096);
873e8e01 5163 /* Dump the DMA descriptor into RAM. */
06e07f65 5164 flush_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1);
873e8e01
MV		 5165 flush_end = flush_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN);
5166 flush_dcache_range(flush_start, flush_end);
5167
682011ff
WD		 5168 E1000_WRITE_REG(hw, RDT, rx_tail);
5169}
5170
5171/**
5172 * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
5173 * @adapter: board private structure
5174 *
5175 * Configure the Tx unit of the MAC after a reset.
5176 **/
5177
5178static void
5179e1000_configure_tx(struct e1000_hw *hw)
5180{
682011ff 5181 unsigned long tctl;
aa070789
RZ		 5182 unsigned long tipg, tarc;
5183 uint32_t ipgr1, ipgr2;
682011ff 5184
1d8a078b
BM		 5185 E1000_WRITE_REG(hw, TDBAL, lower_32_bits((unsigned long)tx_base));
5186 E1000_WRITE_REG(hw, TDBAH, upper_32_bits((unsigned long)tx_base));
682011ff
WD		 5187
5188 E1000_WRITE_REG(hw, TDLEN, 128);
5189
5190 /* Setup the HW Tx Head and Tail descriptor pointers */
5191 E1000_WRITE_REG(hw, TDH, 0);
5192 E1000_WRITE_REG(hw, TDT, 0);
5193 tx_tail = 0;
5194
aa070789
RZ		 5195 /* Set the default values for the Tx Inter Packet Gap timer */
5196 if (hw->mac_type <= e1000_82547_rev_2 &&
5197 (hw->media_type == e1000_media_type_fiber ||
5198 hw->media_type == e1000_media_type_internal_serdes))
5199 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
5200 else
5201 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
5202
682011ff
WD		 5203 /* Set the default values for the Tx Inter Packet Gap timer */
5204 switch (hw->mac_type) {
5205 case e1000_82542_rev2_0:
5206 case e1000_82542_rev2_1:
5207 tipg = DEFAULT_82542_TIPG_IPGT;
aa070789
RZ		 5208 ipgr1 = DEFAULT_82542_TIPG_IPGR1;
5209 ipgr2 = DEFAULT_82542_TIPG_IPGR2;
5210 break;
5211 case e1000_80003es2lan:
5212 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
5213 ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2;
682011ff
WD		 5214 break;
5215 default:
aa070789
RZ		 5216 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
5217 ipgr2 = DEFAULT_82543_TIPG_IPGR2;
5218 break;
682011ff 5219 }
aa070789
RZ		 5220 tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
5221 tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
682011ff 5222 E1000_WRITE_REG(hw, TIPG, tipg);
682011ff
WD		 5223 /* Program the Transmit Control Register */
5224 tctl = E1000_READ_REG(hw, TCTL);
5225 tctl &= ~E1000_TCTL_CT;
5226 tctl |= E1000_TCTL_EN | E1000_TCTL_PSP |
5227 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
aa070789
RZ		 5228
5229 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
5230 tarc = E1000_READ_REG(hw, TARC0);
5231 /* set the speed mode bit, we'll clear it if we're not at
5232 * gigabit link later */
5233 /* git bit can be set to 1*/
5234 } else if (hw->mac_type == e1000_80003es2lan) {
5235 tarc = E1000_READ_REG(hw, TARC0);
5236 tarc |= 1;
5237 E1000_WRITE_REG(hw, TARC0, tarc);
5238 tarc = E1000_READ_REG(hw, TARC1);
5239 tarc |= 1;
5240 E1000_WRITE_REG(hw, TARC1, tarc);
5241 }
5242
682011ff
WD		 5243
5244 e1000_config_collision_dist(hw);
aa070789
RZ		 5245 /* Setup Transmit Descriptor Settings for eop descriptor */
5246 hw->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
682011ff 5247
aa070789
RZ		 5248 /* Need to set up RS bit */
5249 if (hw->mac_type < e1000_82543)
5250 hw->txd_cmd |= E1000_TXD_CMD_RPS;
682011ff 5251 else
aa070789 5252 hw->txd_cmd |= E1000_TXD_CMD_RS;
95186063
MV		 5253
5254
5255 if (hw->mac_type == e1000_igb) {
5256 E1000_WRITE_REG(hw, TCTL_EXT, 0x42 << 10);
5257
5258 uint32_t reg_txdctl = E1000_READ_REG(hw, TXDCTL);
5259 reg_txdctl |= 1 << 25;
5260 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
5261 mdelay(20);
5262 }
5263
5264
5265
aa070789 5266 E1000_WRITE_REG(hw, TCTL, tctl);
95186063
MV		 5267
5268
682011ff
WD		 5269}
5270
5271/**
5272 * e1000_setup_rctl - configure the receive control register
5273 * @adapter: Board private structure
5274 **/
5275static void
5276e1000_setup_rctl(struct e1000_hw *hw)
5277{
5278 uint32_t rctl;
5279
5280 rctl = E1000_READ_REG(hw, RCTL);
5281
5282 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
5283
aa070789
RZ		 5284 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO
5285 | E1000_RCTL_RDMTS_HALF; /* |
5286 (hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */
682011ff
WD		 5287
5288 if (hw->tbi_compatibility_on == 1)
5289 rctl |= E1000_RCTL_SBP;
5290 else
5291 rctl &= ~E1000_RCTL_SBP;
5292
5293 rctl &= ~(E1000_RCTL_SZ_4096);
682011ff
WD		 5294 rctl |= E1000_RCTL_SZ_2048;
5295 rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE);
682011ff
WD		 5296 E1000_WRITE_REG(hw, RCTL, rctl);
5297}
5298
5299/**
5300 * e1000_configure_rx - Configure 8254x Receive Unit after Reset
5301 * @adapter: board private structure
5302 *
5303 * Configure the Rx unit of the MAC after a reset.
5304 **/
5305static void
5306e1000_configure_rx(struct e1000_hw *hw)
5307{
aa070789 5308 unsigned long rctl, ctrl_ext;
682011ff 5309 rx_tail = 0;
1d8a078b 5310
682011ff
WD		 5311 /* make sure receives are disabled while setting up the descriptors */
5312 rctl = E1000_READ_REG(hw, RCTL);
5313 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
682011ff 5314 if (hw->mac_type >= e1000_82540) {
682011ff
WD		 5315 /* Set the interrupt throttling rate. Value is calculated
5316 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */
1aeed8d7
WD		 5317#define MAX_INTS_PER_SEC 8000
5318#define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256)
682011ff
WD		 5319 E1000_WRITE_REG(hw, ITR, DEFAULT_ITR);
5320 }
5321
aa070789
RZ		 5322 if (hw->mac_type >= e1000_82571) {
5323 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
5324 /* Reset delay timers after every interrupt */
5325 ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR;
5326 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
5327 E1000_WRITE_FLUSH(hw);
5328 }
682011ff 5329 /* Setup the Base and Length of the Rx Descriptor Ring */
1d8a078b
BM		 5330 E1000_WRITE_REG(hw, RDBAL, lower_32_bits((unsigned long)rx_base));
5331 E1000_WRITE_REG(hw, RDBAH, upper_32_bits((unsigned long)rx_base));
682011ff
WD		 5332
5333 E1000_WRITE_REG(hw, RDLEN, 128);
5334
5335 /* Setup the HW Rx Head and Tail Descriptor Pointers */
5336 E1000_WRITE_REG(hw, RDH, 0);
5337 E1000_WRITE_REG(hw, RDT, 0);
682011ff
WD		 5338 /* Enable Receives */
5339
95186063
MV		 5340 if (hw->mac_type == e1000_igb) {
5341
5342 uint32_t reg_rxdctl = E1000_READ_REG(hw, RXDCTL);
5343 reg_rxdctl |= 1 << 25;
5344 E1000_WRITE_REG(hw, RXDCTL, reg_rxdctl);
5345 mdelay(20);
5346 }
5347
682011ff 5348 E1000_WRITE_REG(hw, RCTL, rctl);
95186063 5349
682011ff
WD		 5350 fill_rx(hw);
5351}
5352
5353/**************************************************************************
5354POLL - Wait for a frame
5355***************************************************************************/
5356static int
5c5e707a 5357_e1000_poll(struct e1000_hw *hw)
682011ff 5358{
682011ff 5359 struct e1000_rx_desc *rd;
06e07f65 5360 unsigned long inval_start, inval_end;
873e8e01
MV		 5361 uint32_t len;
5362
682011ff
WD		 5363 /* return true if there's an ethernet packet ready to read */
5364 rd = rx_base + rx_last;
873e8e01
MV		 5365
5366 /* Re-load the descriptor from RAM. */
06e07f65 5367 inval_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1);
873e8e01
MV		 5368 inval_end = inval_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN);
5369 invalidate_dcache_range(inval_start, inval_end);
5370
a40b2dff 5371 if (!(rd->status & E1000_RXD_STAT_DD))
682011ff 5372 return 0;
5abf13e4 5373 /* DEBUGOUT("recv: packet len=%d\n", rd->length); */
873e8e01 5374 /* Packet received, make sure the data are re-loaded from RAM. */
a40b2dff 5375 len = le16_to_cpu(rd->length);
06e07f65
ML		 5376 invalidate_dcache_range((unsigned long)packet,
5377 (unsigned long)packet +
5378 roundup(len, ARCH_DMA_MINALIGN));
5c5e707a 5379 return len;
682011ff
WD		 5380}
5381
5c5e707a 5382static int _e1000_transmit(struct e1000_hw *hw, void *txpacket, int length)
682011ff 5383{
873e8e01 5384 void *nv_packet = (void *)txpacket;
682011ff
WD		 5385 struct e1000_tx_desc *txp;
5386 int i = 0;
06e07f65 5387 unsigned long flush_start, flush_end;
682011ff
WD		 5388
5389 txp = tx_base + tx_tail;
5390 tx_tail = (tx_tail + 1) % 8;
5391
8aa858cb 5392 txp->buffer_addr = cpu_to_le64(virt_to_bus(hw->pdev, nv_packet));
aa070789 5393 txp->lower.data = cpu_to_le32(hw->txd_cmd | length);
682011ff 5394 txp->upper.data = 0;
873e8e01
MV		 5395
5396 /* Dump the packet into RAM so e1000 can pick them. */
06e07f65
ML		 5397 flush_dcache_range((unsigned long)nv_packet,
5398 (unsigned long)nv_packet +
5399 roundup(length, ARCH_DMA_MINALIGN));
873e8e01 5400 /* Dump the descriptor into RAM as well. */
06e07f65 5401 flush_start = ((unsigned long)txp) & ~(ARCH_DMA_MINALIGN - 1);
873e8e01
MV		 5402 flush_end = flush_start + roundup(sizeof(*txp), ARCH_DMA_MINALIGN);
5403 flush_dcache_range(flush_start, flush_end);
5404
682011ff
WD		 5405 E1000_WRITE_REG(hw, TDT, tx_tail);
5406
aa070789 5407 E1000_WRITE_FLUSH(hw);
873e8e01
MV		 5408 while (1) {
5409 invalidate_dcache_range(flush_start, flush_end);
5410 if (le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD)
5411 break;
682011ff
WD		 5412 if (i++ > TOUT_LOOP) {
5413 DEBUGOUT("e1000: tx timeout\n");
5414 return 0;
5415 }
5416 udelay(10); /* give the nic a chance to write to the register */
5417 }
5418 return 1;
5419}
5420
682011ff 5421static void
5c5e707a 5422_e1000_disable(struct e1000_hw *hw)
682011ff 5423{
682011ff
WD		 5424 /* Turn off the ethernet interface */
5425 E1000_WRITE_REG(hw, RCTL, 0);
5426 E1000_WRITE_REG(hw, TCTL, 0);
5427
5428 /* Clear the transmit ring */
5429 E1000_WRITE_REG(hw, TDH, 0);
5430 E1000_WRITE_REG(hw, TDT, 0);
5431
5432 /* Clear the receive ring */
5433 E1000_WRITE_REG(hw, RDH, 0);
5434 E1000_WRITE_REG(hw, RDT, 0);
5435
682011ff 5436 mdelay(10);
5c5e707a 5437}
682011ff 5438
5c5e707a
SG		 5439/*reset function*/
5440static inline int
5441e1000_reset(struct e1000_hw *hw, unsigned char enetaddr[6])
5442{
5443 e1000_reset_hw(hw);
5444 if (hw->mac_type >= e1000_82544)
5445 E1000_WRITE_REG(hw, WUC, 0);
5446
5447 return e1000_init_hw(hw, enetaddr);
682011ff
WD		 5448}
5449
682011ff 5450static int
5c5e707a 5451_e1000_init(struct e1000_hw *hw, unsigned char enetaddr[6])
682011ff 5452{
682011ff
WD		 5453 int ret_val = 0;
5454
5c5e707a 5455 ret_val = e1000_reset(hw, enetaddr);
682011ff
WD		 5456 if (ret_val < 0) {
5457 if ((ret_val == -E1000_ERR_NOLINK) ||
5458 (ret_val == -E1000_ERR_TIMEOUT)) {
5c5e707a 5459 E1000_ERR(hw, "Valid Link not detected: %d\n", ret_val);
682011ff 5460 } else {
5c5e707a 5461 E1000_ERR(hw, "Hardware Initialization Failed\n");
682011ff 5462 }
5c5e707a 5463 return ret_val;
682011ff
WD		 5464 }
5465 e1000_configure_tx(hw);
5466 e1000_setup_rctl(hw);
5467 e1000_configure_rx(hw);
5c5e707a 5468 return 0;
682011ff
WD		 5469}
5470
aa070789
RZ		 5471/******************************************************************************
5472 * Gets the current PCI bus type of hardware
5473 *
5474 * hw - Struct containing variables accessed by shared code
5475 *****************************************************************************/
5476void e1000_get_bus_type(struct e1000_hw *hw)
5477{
5478 uint32_t status;
5479
5480 switch (hw->mac_type) {
5481 case e1000_82542_rev2_0:
5482 case e1000_82542_rev2_1:
5483 hw->bus_type = e1000_bus_type_pci;
5484 break;
5485 case e1000_82571:
5486 case e1000_82572:
5487 case e1000_82573:
2c2668f9 5488 case e1000_82574:
aa070789 5489 case e1000_80003es2lan:
aa070789 5490 case e1000_ich8lan:
95186063 5491 case e1000_igb:
aa070789
RZ		 5492 hw->bus_type = e1000_bus_type_pci_express;
5493 break;
5494 default:
5495 status = E1000_READ_REG(hw, STATUS);
5496 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
5497 e1000_bus_type_pcix : e1000_bus_type_pci;
5498 break;
5499 }
5500}
5501
c6d80a15 5502#ifndef CONFIG_DM_ETH
ce5207e1
KM		 5503/* A list of all registered e1000 devices */
5504static LIST_HEAD(e1000_hw_list);
c6d80a15 5505#endif
ce5207e1 5506
81dab9af
BM		 5507#ifdef CONFIG_DM_ETH
5508static int e1000_init_one(struct e1000_hw *hw, int cardnum,
5509 struct udevice *devno, unsigned char enetaddr[6])
5510#else
5c5e707a
SG		 5511static int e1000_init_one(struct e1000_hw *hw, int cardnum, pci_dev_t devno,
5512 unsigned char enetaddr[6])
81dab9af 5513#endif
5c5e707a
SG		 5514{
5515 u32 val;
5516
5517 /* Assign the passed-in values */
81dab9af 5518#ifdef CONFIG_DM_ETH
5c5e707a 5519 hw->pdev = devno;
81dab9af
BM		 5520#else
5521 hw->pdev = devno;
5522#endif
5c5e707a
SG		 5523 hw->cardnum = cardnum;
5524
5525 /* Print a debug message with the IO base address */
81dab9af
BM		 5526#ifdef CONFIG_DM_ETH
5527 dm_pci_read_config32(devno, PCI_BASE_ADDRESS_0, &val);
5528#else
5c5e707a 5529 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &val);
81dab9af 5530#endif
5c5e707a
SG		 5531 E1000_DBG(hw, "iobase 0x%08x\n", val & 0xfffffff0);
5532
5533 /* Try to enable I/O accesses and bus-mastering */
5534 val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
81dab9af
BM		 5535#ifdef CONFIG_DM_ETH
5536 dm_pci_write_config32(devno, PCI_COMMAND, val);
5537#else
5c5e707a 5538 pci_write_config_dword(devno, PCI_COMMAND, val);
81dab9af 5539#endif
5c5e707a
SG		 5540
5541 /* Make sure it worked */
81dab9af
BM		 5542#ifdef CONFIG_DM_ETH
5543 dm_pci_read_config32(devno, PCI_COMMAND, &val);
5544#else
5c5e707a 5545 pci_read_config_dword(devno, PCI_COMMAND, &val);
81dab9af 5546#endif
5c5e707a
SG		 5547 if (!(val & PCI_COMMAND_MEMORY)) {
5548 E1000_ERR(hw, "Can't enable I/O memory\n");
5549 return -ENOSPC;
5550 }
5551 if (!(val & PCI_COMMAND_MASTER)) {
5552 E1000_ERR(hw, "Can't enable bus-mastering\n");
5553 return -EPERM;
5554 }
5555
5556 /* Are these variables needed? */
5557 hw->fc = e1000_fc_default;
5558 hw->original_fc = e1000_fc_default;
5559 hw->autoneg_failed = 0;
5560 hw->autoneg = 1;
5561 hw->get_link_status = true;
5562#ifndef CONFIG_E1000_NO_NVM
5563 hw->eeprom_semaphore_present = true;
5564#endif
81dab9af
BM		 5565#ifdef CONFIG_DM_ETH
5566 hw->hw_addr = dm_pci_map_bar(devno, PCI_BASE_ADDRESS_0,
5567 PCI_REGION_MEM);
5568#else
5c5e707a
SG		 5569 hw->hw_addr = pci_map_bar(devno, PCI_BASE_ADDRESS_0,
5570 PCI_REGION_MEM);
81dab9af 5571#endif
5c5e707a
SG		 5572 hw->mac_type = e1000_undefined;
5573
5574 /* MAC and Phy settings */
5575 if (e1000_sw_init(hw) < 0) {
5576 E1000_ERR(hw, "Software init failed\n");
5577 return -EIO;
5578 }
5579 if (e1000_check_phy_reset_block(hw))
5580 E1000_ERR(hw, "PHY Reset is blocked!\n");
5581
5582 /* Basic init was OK, reset the hardware and allow SPI access */
5583 e1000_reset_hw(hw);
5584
5585#ifndef CONFIG_E1000_NO_NVM
5586 /* Validate the EEPROM and get chipset information */
5c5e707a
SG		 5587 if (e1000_init_eeprom_params(hw)) {
5588 E1000_ERR(hw, "EEPROM is invalid!\n");
5589 return -EINVAL;
5590 }
5591 if ((E1000_READ_REG(hw, I210_EECD) & E1000_EECD_FLUPD) &&
5592 e1000_validate_eeprom_checksum(hw))
5593 return -ENXIO;
5c5e707a
SG		 5594 e1000_read_mac_addr(hw, enetaddr);
5595#endif
5596 e1000_get_bus_type(hw);
5597
5598#ifndef CONFIG_E1000_NO_NVM
5599 printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n ",
5600 enetaddr[0], enetaddr[1], enetaddr[2],
5601 enetaddr[3], enetaddr[4], enetaddr[5]);
5602#else
5603 memset(enetaddr, 0, 6);
5604 printf("e1000: no NVM\n");
5605#endif
5606
5607 return 0;
5608}
5609
5610/* Put the name of a device in a string */
5611static void e1000_name(char *str, int cardnum)
5612{
5613 sprintf(str, "e1000#%u", cardnum);
5614}
5615
c6d80a15 5616#ifndef CONFIG_DM_ETH
5c5e707a
SG		 5617/**************************************************************************
5618TRANSMIT - Transmit a frame
5619***************************************************************************/
5620static int e1000_transmit(struct eth_device *nic, void *txpacket, int length)
5621{
5622 struct e1000_hw *hw = nic->priv;
5623
5624 return _e1000_transmit(hw, txpacket, length);
5625}
5626
5627/**************************************************************************
5628DISABLE - Turn off ethernet interface
5629***************************************************************************/
5630static void
5631e1000_disable(struct eth_device *nic)
5632{
5633 struct e1000_hw *hw = nic->priv;
5634
5635 _e1000_disable(hw);
5636}
5637
5638/**************************************************************************
5639INIT - set up ethernet interface(s)
5640***************************************************************************/
5641static int
b75d8dc5 5642e1000_init(struct eth_device *nic, struct bd_info *bis)
5c5e707a
SG		 5643{
5644 struct e1000_hw *hw = nic->priv;
5645
5646 return _e1000_init(hw, nic->enetaddr);
5647}
5648
5649static int
5650e1000_poll(struct eth_device *nic)
5651{
5652 struct e1000_hw *hw = nic->priv;
5653 int len;
5654
5655 len = _e1000_poll(hw);
5656 if (len) {
5657 net_process_received_packet((uchar *)packet, len);
5658 fill_rx(hw);
5659 }
5660
5661 return len ? 1 : 0;
5662}
5663
8d9bde0d
HL		 5664static int e1000_write_hwaddr(struct eth_device *dev)
5665{
5666#ifndef CONFIG_E1000_NO_NVM
5667 unsigned char *mac = dev->enetaddr;
5668 unsigned char current_mac[6];
5669 struct e1000_hw *hw = dev->priv;
5670 uint16_t data[3];
5671 int ret_val, i;
5672
5673 DEBUGOUT("%s: mac=%pM\n", __func__, mac);
5674
5675 memset(current_mac, 0, 6);
5676
5677 /* Read from EEPROM, not from registers, to make sure
5678 * the address is persistently configured
5679 */
5680 ret_val = e1000_read_mac_addr_from_eeprom(hw, current_mac);
5681 DEBUGOUT("%s: current mac=%pM\n", __func__, current_mac);
5682
5683 /* Only write to EEPROM if the given address is different or
5684 * reading the current address failed
5685 */
5686 if (!ret_val && memcmp(current_mac, mac, 6) == 0)
5687 return 0;
5688
5689 for (i = 0; i < 3; ++i)
5690 data[i] = mac[i * 2 + 1] << 8 | mac[i * 2];
5691
5692 ret_val = e1000_write_eeprom_srwr(hw, 0x0, 3, data);
5693
5694 if (!ret_val)
5695 ret_val = e1000_update_eeprom_checksum_i210(hw);
5696
5697 return ret_val;
5698#else
5699 return 0;
5700#endif
5701}
5702
682011ff
WD		 5703/**************************************************************************
5704PROBE - Look for an adapter, this routine's visible to the outside
5705You should omit the last argument struct pci_device * for a non-PCI NIC
5706***************************************************************************/
5707int
b75d8dc5 5708e1000_initialize(struct bd_info * bis)
682011ff 5709{
d60626f8 5710 unsigned int i;
682011ff 5711 pci_dev_t devno;
5c5e707a 5712 int ret;
682011ff 5713
f81ecb5d
TT		 5714 DEBUGFUNC();
5715
d60626f8
KM		 5716 /* Find and probe all the matching PCI devices */
5717 for (i = 0; (devno = pci_find_devices(e1000_supported, i)) >= 0; i++) {
d60626f8
KM		 5718 /*
5719 * These will never get freed due to errors, this allows us to
a187559e 5720 * perform SPI EEPROM programming from U-Boot, for example.
d60626f8
KM		 5721 */
5722 struct eth_device *nic = malloc(sizeof(*nic));
5723 struct e1000_hw *hw = malloc(sizeof(*hw));
5724 if (!nic || !hw) {
5725 printf("e1000#%u: Out of Memory!\n", i);
4b29bdb0 5726 free(nic);
d60626f8
KM		 5727 free(hw);
5728 continue;
4b29bdb0
KG		 5729 }
5730
d60626f8 5731 /* Make sure all of the fields are initially zeroed */
f7ac99fd 5732 memset(nic, 0, sizeof(*nic));
4b29bdb0 5733 memset(hw, 0, sizeof(*hw));
682011ff 5734 nic->priv = hw;
682011ff 5735
d60626f8 5736 /* Generate a card name */
5c5e707a
SG		 5737 e1000_name(nic->name, i);
5738 hw->name = nic->name;
682011ff 5739
5c5e707a
SG		 5740 ret = e1000_init_one(hw, i, devno, nic->enetaddr);
5741 if (ret)
d60626f8 5742 continue;
ce5207e1 5743 list_add_tail(&hw->list_node, &e1000_hw_list);
d60626f8 5744
5c5e707a 5745 hw->nic = nic;
682011ff 5746
d60626f8 5747 /* Set up the function pointers and register the device */
682011ff
WD		 5748 nic->init = e1000_init;
5749 nic->recv = e1000_poll;
5750 nic->send = e1000_transmit;
5751 nic->halt = e1000_disable;
8d9bde0d 5752 nic->write_hwaddr = e1000_write_hwaddr;
682011ff 5753 eth_register(nic);
682011ff 5754 }
d60626f8
KM		 5755
5756 return i;
682011ff 5757}
ce5207e1
KM		 5758
5759struct e1000_hw *e1000_find_card(unsigned int cardnum)
5760{
5761 struct e1000_hw *hw;
5762
5763 list_for_each_entry(hw, &e1000_hw_list, list_node)
5764 if (hw->cardnum == cardnum)
5765 return hw;
5766
5767 return NULL;
5768}
c6d80a15 5769#endif /* !CONFIG_DM_ETH */
ce5207e1
KM		 5770
5771#ifdef CONFIG_CMD_E1000
09140113
SG		 5772static int do_e1000(struct cmd_tbl *cmdtp, int flag, int argc,
5773 char *const argv[])
ce5207e1 5774{
5c5e707a 5775 unsigned char *mac = NULL;
c6d80a15
SG		 5776#ifdef CONFIG_DM_ETH
5777 struct eth_pdata *plat;
5778 struct udevice *dev;
5779 char name[30];
5780 int ret;
eb4e8ceb
AB		 5781#endif
5782#if !defined(CONFIG_DM_ETH) || defined(CONFIG_E1000_SPI)
ce5207e1 5783 struct e1000_hw *hw;
c6d80a15
SG		 5784#endif
5785 int cardnum;
ce5207e1
KM		 5786
5787 if (argc < 3) {
5788 cmd_usage(cmdtp);
5789 return 1;
5790 }
5791
5792 /* Make sure we can find the requested e1000 card */
5c5e707a 5793 cardnum = simple_strtoul(argv[1], NULL, 10);
c6d80a15
SG		 5794#ifdef CONFIG_DM_ETH
5795 e1000_name(name, cardnum);
5796 ret = uclass_get_device_by_name(UCLASS_ETH, name, &dev);
5797 if (!ret) {
c69cda25 5798 plat = dev_get_plat(dev);
c6d80a15
SG		 5799 mac = plat->enetaddr;
5800 }
5801#else
5c5e707a
SG		 5802 hw = e1000_find_card(cardnum);
5803 if (hw)
5804 mac = hw->nic->enetaddr;
c6d80a15 5805#endif
5c5e707a 5806 if (!mac) {
ce5207e1
KM		 5807 printf("e1000: ERROR: No such device: e1000#%s\n", argv[1]);
5808 return 1;
5809 }
5810
5811 if (!strcmp(argv[2], "print-mac-address")) {
ce5207e1
KM		 5812 printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
5813 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
5814 return 0;
5815 }
5816
5817#ifdef CONFIG_E1000_SPI
eb4e8ceb
AB		 5818#ifdef CONFIG_DM_ETH
5819 hw = dev_get_priv(dev);
5820#endif
ce5207e1
KM		 5821 /* Handle the "SPI" subcommand */
5822 if (!strcmp(argv[2], "spi"))
5823 return do_e1000_spi(cmdtp, hw, argc - 3, argv + 3);
5824#endif
5825
5826 cmd_usage(cmdtp);
5827 return 1;
5828}
5829
5830U_BOOT_CMD(
5831 e1000, 7, 0, do_e1000,
5832 "Intel e1000 controller management",
5833 /* */"<card#> print-mac-address\n"
5834#ifdef CONFIG_E1000_SPI
5835 "e1000 <card#> spi show [<offset> [<length>]]\n"
5836 "e1000 <card#> spi dump <addr> <offset> <length>\n"
5837 "e1000 <card#> spi program <addr> <offset> <length>\n"
5838 "e1000 <card#> spi checksum [update]\n"
5839#endif
5840 " - Manage the Intel E1000 PCI device"
5841);
5842#endif /* not CONFIG_CMD_E1000 */
c6d80a15
SG		 5843
5844#ifdef CONFIG_DM_ETH
5845static int e1000_eth_start(struct udevice *dev)
5846{
c69cda25 5847 struct eth_pdata *plat = dev_get_plat(dev);
c6d80a15
SG		 5848 struct e1000_hw *hw = dev_get_priv(dev);
5849
5850 return _e1000_init(hw, plat->enetaddr);
5851}
5852
5853static void e1000_eth_stop(struct udevice *dev)
5854{
5855 struct e1000_hw *hw = dev_get_priv(dev);
5856
5857 _e1000_disable(hw);
5858}
5859
5860static int e1000_eth_send(struct udevice *dev, void *packet, int length)
5861{
5862 struct e1000_hw *hw = dev_get_priv(dev);
5863 int ret;
5864
5865 ret = _e1000_transmit(hw, packet, length);
5866
5867 return ret ? 0 : -ETIMEDOUT;
5868}
5869
5870static int e1000_eth_recv(struct udevice *dev, int flags, uchar **packetp)
5871{
5872 struct e1000_hw *hw = dev_get_priv(dev);
5873 int len;
5874
5875 len = _e1000_poll(hw);
5876 if (len)
5877 *packetp = packet;
5878
5879 return len ? len : -EAGAIN;
5880}
5881
5882static int e1000_free_pkt(struct udevice *dev, uchar *packet, int length)
5883{
5884 struct e1000_hw *hw = dev_get_priv(dev);
5885
5886 fill_rx(hw);
5887
5888 return 0;
5889}
5890
5891static int e1000_eth_probe(struct udevice *dev)
5892{
c69cda25 5893 struct eth_pdata *plat = dev_get_plat(dev);
c6d80a15
SG		 5894 struct e1000_hw *hw = dev_get_priv(dev);
5895 int ret;
5896
5897 hw->name = dev->name;
21ccce1b 5898 ret = e1000_init_one(hw, trailing_strtol(dev->name),
81dab9af 5899 dev, plat->enetaddr);
c6d80a15
SG		 5900 if (ret < 0) {
5901 printf(pr_fmt("failed to initialize card: %d\n"), ret);
5902 return ret;
5903 }
5904
5905 return 0;
5906}
5907
5908static int e1000_eth_bind(struct udevice *dev)
5909{
5910 char name[20];
5911
5912 /*
5913 * A simple way to number the devices. When device tree is used this
5914 * is unnecessary, but when the device is just discovered on the PCI
5915 * bus we need a name. We could instead have the uclass figure out
5916 * which devices are different and number them.
5917 */
5918 e1000_name(name, num_cards++);
5919
5920 return device_set_name(dev, name);
5921}
5922
5923static const struct eth_ops e1000_eth_ops = {
5924 .start = e1000_eth_start,
5925 .send = e1000_eth_send,
5926 .recv = e1000_eth_recv,
5927 .stop = e1000_eth_stop,
5928 .free_pkt = e1000_free_pkt,
5929};
5930
5931static const struct udevice_id e1000_eth_ids[] = {
5932 { .compatible = "intel,e1000" },
5933 { }
5934};
5935
5936U_BOOT_DRIVER(eth_e1000) = {
5937 .name = "eth_e1000",
5938 .id = UCLASS_ETH,
5939 .of_match = e1000_eth_ids,
5940 .bind = e1000_eth_bind,
5941 .probe = e1000_eth_probe,
5942 .ops = &e1000_eth_ops,
41575d8e 5943 .priv_auto = sizeof(struct e1000_hw),
caa4daa2 5944 .plat_auto = sizeof(struct eth_pdata),
c6d80a15
SG		 5945};
5946
5947U_BOOT_PCI_DEVICE(eth_e1000, e1000_supported);
5948#endif
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