[u-boot.git] / drivers / video / imx / mxc_ipuv3_fb.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Porting to u-boot:
 *
 * (C) Copyright 2010
 * Stefano Babic, DENX Software Engineering, [email protected]
 *
 * MX51 Linux framebuffer:
 *
 * (C) Copyright 2004-2010 Freescale Semiconductor, Inc.
 */

#include <common.h>
#include <log.h>
#include <part.h>
#include <asm/cache.h>
#include <linux/errno.h>
#include <asm/global_data.h>
#include <linux/string.h>
#include <linux/list.h>
#include <linux/fb.h>
#include <asm/io.h>
#include <asm/mach-imx/video.h>
#include <malloc.h>
#include <video_fb.h>
#include "../videomodes.h"
#include "ipu.h"
#include "mxcfb.h"
#include "ipu_regs.h"
#include "display.h"
#include <panel.h>

#include <dm.h>
#include <video.h>

DECLARE_GLOBAL_DATA_PTR;

static int mxcfb_map_video_memory(struct fb_info *fbi);
static int mxcfb_unmap_video_memory(struct fb_info *fbi);

static struct fb_videomode const *gmode;
static uint8_t gdisp;
static uint32_t gpixfmt;

static void fb_videomode_to_var(struct fb_var_screeninfo *var,
			 const struct fb_videomode *mode)
{
	var->xres = mode->xres;
	var->yres = mode->yres;
	var->xres_virtual = mode->xres;
	var->yres_virtual = mode->yres;
	var->xoffset = 0;
	var->yoffset = 0;
	var->pixclock = mode->pixclock;
	var->left_margin = mode->left_margin;
	var->right_margin = mode->right_margin;
	var->upper_margin = mode->upper_margin;
	var->lower_margin = mode->lower_margin;
	var->hsync_len = mode->hsync_len;
	var->vsync_len = mode->vsync_len;
	var->sync = mode->sync;
	var->vmode = mode->vmode & FB_VMODE_MASK;
}

/*
 * Structure containing the MXC specific framebuffer information.
 */
struct mxcfb_info {
	struct udevice *udev;
	int blank;
	ipu_channel_t ipu_ch;
	int ipu_di;
	u32 ipu_di_pix_fmt;
	unsigned char overlay;
	unsigned char alpha_chan_en;
	dma_addr_t alpha_phy_addr0;
	dma_addr_t alpha_phy_addr1;
	void *alpha_virt_addr0;
	void *alpha_virt_addr1;
	uint32_t alpha_mem_len;
	uint32_t cur_ipu_buf;
	uint32_t cur_ipu_alpha_buf;

	u32 pseudo_palette[16];
};

enum {
	BOTH_ON,
	SRC_ON,
	TGT_ON,
	BOTH_OFF
};

static unsigned long default_bpp = 16;
static unsigned char g_dp_in_use;
static struct fb_info *mxcfb_info[3];
static int ext_clk_used;

static uint32_t bpp_to_pixfmt(struct fb_info *fbi)
{
	uint32_t pixfmt = 0;

	debug("bpp_to_pixfmt: %d\n", fbi->var.bits_per_pixel);

	if (fbi->var.nonstd)
		return fbi->var.nonstd;

	switch (fbi->var.bits_per_pixel) {
	case 24:
		pixfmt = IPU_PIX_FMT_BGR24;
		break;
	case 32:
		pixfmt = IPU_PIX_FMT_BGR32;
		break;
	case 16:
		pixfmt = IPU_PIX_FMT_RGB565;
		break;
	}
	return pixfmt;
}

static int setup_disp_channel1(struct fb_info *fbi)
{
	ipu_channel_params_t params;
	struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par;

	memset(&params, 0, sizeof(params));
	params.mem_dp_bg_sync.di = mxc_fbi->ipu_di;

	debug("%s called\n", __func__);
	/*
	 * Assuming interlaced means yuv output, below setting also
	 * valid for mem_dc_sync. FG should have the same vmode as BG.
	 */
	if (fbi->var.vmode & FB_VMODE_INTERLACED) {
		params.mem_dp_bg_sync.interlaced = 1;
		params.mem_dp_bg_sync.out_pixel_fmt =
			IPU_PIX_FMT_YUV444;
	} else {
		if (mxc_fbi->ipu_di_pix_fmt) {
			params.mem_dp_bg_sync.out_pixel_fmt =
				mxc_fbi->ipu_di_pix_fmt;
		} else {
			params.mem_dp_bg_sync.out_pixel_fmt =
				IPU_PIX_FMT_RGB666;
		}
	}
	params.mem_dp_bg_sync.in_pixel_fmt = bpp_to_pixfmt(fbi);
	if (mxc_fbi->alpha_chan_en)
		params.mem_dp_bg_sync.alpha_chan_en = 1;

	ipu_init_channel(mxc_fbi->ipu_ch, &params);

	return 0;
}

static int setup_disp_channel2(struct fb_info *fbi)
{
	int retval = 0;
	struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par;

	mxc_fbi->cur_ipu_buf = 1;
	if (mxc_fbi->alpha_chan_en)
		mxc_fbi->cur_ipu_alpha_buf = 1;

	fbi->var.xoffset = fbi->var.yoffset = 0;

	debug("%s: %x %d %d %d %lx %lx\n",
		__func__,
		mxc_fbi->ipu_ch,
		fbi->var.xres,
		fbi->var.yres,
		fbi->fix.line_length,
		fbi->fix.smem_start,
		fbi->fix.smem_start +
		(fbi->fix.line_length * fbi->var.yres));

	retval = ipu_init_channel_buffer(mxc_fbi->ipu_ch, IPU_INPUT_BUFFER,
					 bpp_to_pixfmt(fbi),
					 fbi->var.xres, fbi->var.yres,
					 fbi->fix.line_length,
					 fbi->fix.smem_start +
					 (fbi->fix.line_length * fbi->var.yres),
					 fbi->fix.smem_start,
					 0, 0);
	if (retval)
		printf("ipu_init_channel_buffer error %d\n", retval);

	return retval;
}

/*
 * Set framebuffer parameters and change the operating mode.
 *
 * @param       info     framebuffer information pointer
 */
static int mxcfb_set_par(struct fb_info *fbi)
{
	int retval = 0;
	u32 mem_len;
	ipu_di_signal_cfg_t sig_cfg;
	struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par;
	uint32_t out_pixel_fmt;

	ipu_disable_channel(mxc_fbi->ipu_ch);
	ipu_uninit_channel(mxc_fbi->ipu_ch);

	mem_len = fbi->var.yres_virtual * fbi->fix.line_length;
	if (!fbi->fix.smem_start || (mem_len > fbi->fix.smem_len)) {
		if (fbi->fix.smem_start)
			mxcfb_unmap_video_memory(fbi);

		if (mxcfb_map_video_memory(fbi) < 0)
			return -ENOMEM;
	}

	setup_disp_channel1(fbi);

	memset(&sig_cfg, 0, sizeof(sig_cfg));
	if (fbi->var.vmode & FB_VMODE_INTERLACED) {
		sig_cfg.interlaced = 1;
		out_pixel_fmt = IPU_PIX_FMT_YUV444;
	} else {
		if (mxc_fbi->ipu_di_pix_fmt)
			out_pixel_fmt = mxc_fbi->ipu_di_pix_fmt;
		else
			out_pixel_fmt = IPU_PIX_FMT_RGB666;
	}
	if (fbi->var.vmode & FB_VMODE_ODD_FLD_FIRST) /* PAL */
		sig_cfg.odd_field_first = 1;
	if ((fbi->var.sync & FB_SYNC_EXT) || ext_clk_used)
		sig_cfg.ext_clk = 1;
	if (fbi->var.sync & FB_SYNC_HOR_HIGH_ACT)
		sig_cfg.Hsync_pol = 1;
	if (fbi->var.sync & FB_SYNC_VERT_HIGH_ACT)
		sig_cfg.Vsync_pol = 1;
	if (!(fbi->var.sync & FB_SYNC_CLK_LAT_FALL))
		sig_cfg.clk_pol = 1;
	if (fbi->var.sync & FB_SYNC_DATA_INVERT)
		sig_cfg.data_pol = 1;
	if (!(fbi->var.sync & FB_SYNC_OE_LOW_ACT))
		sig_cfg.enable_pol = 1;
	if (fbi->var.sync & FB_SYNC_CLK_IDLE_EN)
		sig_cfg.clkidle_en = 1;

	debug("pixclock = %lu Hz\n", PICOS2KHZ(fbi->var.pixclock) * 1000UL);

	if (ipu_init_sync_panel(mxc_fbi->ipu_di,
				(PICOS2KHZ(fbi->var.pixclock)) * 1000UL,
				fbi->var.xres, fbi->var.yres,
				out_pixel_fmt,
				fbi->var.left_margin,
				fbi->var.hsync_len,
				fbi->var.right_margin,
				fbi->var.upper_margin,
				fbi->var.vsync_len,
				fbi->var.lower_margin,
				0, sig_cfg) != 0) {
		puts("mxcfb: Error initializing panel.\n");
		return -EINVAL;
	}

	retval = setup_disp_channel2(fbi);
	if (retval)
		return retval;

	if (mxc_fbi->blank == FB_BLANK_UNBLANK)
		ipu_enable_channel(mxc_fbi->ipu_ch);

	return retval;
}

/*
 * Check framebuffer variable parameters and adjust to valid values.
 *
 * @param       var      framebuffer variable parameters
 *
 * @param       info     framebuffer information pointer
 */
static int mxcfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
{
	u32 vtotal;
	u32 htotal;

	if (var->xres_virtual < var->xres)
		var->xres_virtual = var->xres;
	if (var->yres_virtual < var->yres)
		var->yres_virtual = var->yres;

	if ((var->bits_per_pixel != 32) && (var->bits_per_pixel != 24) &&
	    (var->bits_per_pixel != 16) && (var->bits_per_pixel != 8))
		var->bits_per_pixel = default_bpp;

	switch (var->bits_per_pixel) {
	case 8:
		var->red.length = 3;
		var->red.offset = 5;
		var->red.msb_right = 0;

		var->green.length = 3;
		var->green.offset = 2;
		var->green.msb_right = 0;

		var->blue.length = 2;
		var->blue.offset = 0;
		var->blue.msb_right = 0;

		var->transp.length = 0;
		var->transp.offset = 0;
		var->transp.msb_right = 0;
		break;
	case 16:
		var->red.length = 5;
		var->red.offset = 11;
		var->red.msb_right = 0;

		var->green.length = 6;
		var->green.offset = 5;
		var->green.msb_right = 0;

		var->blue.length = 5;
		var->blue.offset = 0;
		var->blue.msb_right = 0;

		var->transp.length = 0;
		var->transp.offset = 0;
		var->transp.msb_right = 0;
		break;
	case 24:
		var->red.length = 8;
		var->red.offset = 16;
		var->red.msb_right = 0;

		var->green.length = 8;
		var->green.offset = 8;
		var->green.msb_right = 0;

		var->blue.length = 8;
		var->blue.offset = 0;
		var->blue.msb_right = 0;

		var->transp.length = 0;
		var->transp.offset = 0;
		var->transp.msb_right = 0;
		break;
	case 32:
		var->red.length = 8;
		var->red.offset = 16;
		var->red.msb_right = 0;

		var->green.length = 8;
		var->green.offset = 8;
		var->green.msb_right = 0;

		var->blue.length = 8;
		var->blue.offset = 0;
		var->blue.msb_right = 0;

		var->transp.length = 8;
		var->transp.offset = 24;
		var->transp.msb_right = 0;
		break;
	}

	if (var->pixclock < 1000) {
		htotal = var->xres + var->right_margin + var->hsync_len +
		    var->left_margin;
		vtotal = var->yres + var->lower_margin + var->vsync_len +
		    var->upper_margin;
		var->pixclock = (vtotal * htotal * 6UL) / 100UL;
		var->pixclock = KHZ2PICOS(var->pixclock);
		printf("pixclock set for 60Hz refresh = %u ps\n",
			var->pixclock);
	}

	var->height = -1;
	var->width = -1;
	var->grayscale = 0;

	return 0;
}

static int mxcfb_map_video_memory(struct fb_info *fbi)
{
	struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par;
	struct video_uc_plat *plat = dev_get_uclass_plat(mxc_fbi->udev);

	if (fbi->fix.smem_len < fbi->var.yres_virtual * fbi->fix.line_length) {
		fbi->fix.smem_len = fbi->var.yres_virtual *
				    fbi->fix.line_length;
	}
	fbi->fix.smem_len = roundup(fbi->fix.smem_len, ARCH_DMA_MINALIGN);

	fbi->screen_base = (char *)plat->base;

	fbi->fix.smem_start = (unsigned long)fbi->screen_base;
	if (fbi->screen_base == 0) {
		puts("Unable to allocate framebuffer memory\n");
		fbi->fix.smem_len = 0;
		fbi->fix.smem_start = 0;
		return -EBUSY;
	}

	debug("allocated fb @ paddr=0x%08X, size=%d.\n",
		(uint32_t) fbi->fix.smem_start, fbi->fix.smem_len);

	fbi->screen_size = fbi->fix.smem_len;
	gd->fb_base = fbi->fix.smem_start;

	/* Clear the screen */
	memset((char *)fbi->screen_base, 0, fbi->fix.smem_len);

	return 0;
}

static int mxcfb_unmap_video_memory(struct fb_info *fbi)
{
	fbi->screen_base = 0;
	fbi->fix.smem_start = 0;
	fbi->fix.smem_len = 0;
	return 0;
}

/*
 * Initializes the framebuffer information pointer. After allocating
 * sufficient memory for the framebuffer structure, the fields are
 * filled with custom information passed in from the configurable
 * structures.  This includes information such as bits per pixel,
 * color maps, screen width/height and RGBA offsets.
 *
 * @return      Framebuffer structure initialized with our information
 */
static struct fb_info *mxcfb_init_fbinfo(void)
{
#define BYTES_PER_LONG 4
#define PADDING (BYTES_PER_LONG - (sizeof(struct fb_info) % BYTES_PER_LONG))
	struct fb_info *fbi;
	struct mxcfb_info *mxcfbi;
	char *p;
	int size = sizeof(struct mxcfb_info) + PADDING +
		sizeof(struct fb_info);

	debug("%s: %d %d %d %d\n",
		__func__,
		PADDING,
		size,
		sizeof(struct mxcfb_info),
		sizeof(struct fb_info));
	/*
	 * Allocate sufficient memory for the fb structure
	 */

	p = malloc(size);
	if (!p)
		return NULL;

	memset(p, 0, size);

	fbi = (struct fb_info *)p;
	fbi->par = p + sizeof(struct fb_info) + PADDING;

	mxcfbi = (struct mxcfb_info *)fbi->par;
	debug("Framebuffer structures at: fbi=0x%x mxcfbi=0x%x\n",
		(unsigned int)fbi, (unsigned int)mxcfbi);

	fbi->var.activate = FB_ACTIVATE_NOW;

	fbi->flags = FBINFO_FLAG_DEFAULT;
	fbi->pseudo_palette = mxcfbi->pseudo_palette;

	return fbi;
}

extern struct clk *g_ipu_clk;

/*
 * Probe routine for the framebuffer driver. It is called during the
 * driver binding process. The following functions are performed in
 * this routine: Framebuffer initialization, Memory allocation and
 * mapping, Framebuffer registration, IPU initialization.
 *
 * @return      Appropriate error code to the kernel common code
 */
static int mxcfb_probe(struct udevice *dev, u32 interface_pix_fmt,
		       uint8_t disp, struct fb_videomode const *mode)
{
	struct fb_info *fbi;
	struct mxcfb_info *mxcfbi;

	/*
	 * Initialize FB structures
	 */
	fbi = mxcfb_init_fbinfo();
	if (!fbi)
		return -ENOMEM;

	mxcfbi = (struct mxcfb_info *)fbi->par;

	if (!g_dp_in_use) {
		mxcfbi->ipu_ch = MEM_BG_SYNC;
		mxcfbi->blank = FB_BLANK_UNBLANK;
	} else {
		mxcfbi->ipu_ch = MEM_DC_SYNC;
		mxcfbi->blank = FB_BLANK_POWERDOWN;
	}

	mxcfbi->ipu_di = disp;
	mxcfbi->udev = dev;

	if (!ipu_clk_enabled())
		clk_enable(g_ipu_clk);

	ipu_disp_set_global_alpha(mxcfbi->ipu_ch, 1, 0x80);
	ipu_disp_set_color_key(mxcfbi->ipu_ch, 0, 0);

	g_dp_in_use = 1;

	mxcfb_info[mxcfbi->ipu_di] = fbi;

	/* Need dummy values until real panel is configured */

	mxcfbi->ipu_di_pix_fmt = interface_pix_fmt;
	fb_videomode_to_var(&fbi->var, mode);
	fbi->var.bits_per_pixel = 16;
	fbi->fix.line_length = fbi->var.xres_virtual *
			       (fbi->var.bits_per_pixel / 8);
	fbi->fix.smem_len = fbi->var.yres_virtual * fbi->fix.line_length;

	mxcfb_check_var(&fbi->var, fbi);

	/* Default Y virtual size is 2x panel size */
	fbi->var.yres_virtual = fbi->var.yres * 2;

	/* allocate fb first */
	if (mxcfb_map_video_memory(fbi) < 0)
		return -ENOMEM;

	mxcfb_set_par(fbi);

#ifdef DEBUG
	ipu_dump_registers();
#endif

	return 0;
}

void ipuv3_fb_shutdown(void)
{
	int i;
	struct ipu_stat *stat = (struct ipu_stat *)IPU_STAT;

	if (!ipu_clk_enabled())
		return;

	for (i = 0; i < ARRAY_SIZE(mxcfb_info); i++) {
		struct fb_info *fbi = mxcfb_info[i];
		if (fbi) {
			struct mxcfb_info *mxc_fbi = fbi->par;
			ipu_disable_channel(mxc_fbi->ipu_ch);
			ipu_uninit_channel(mxc_fbi->ipu_ch);
		}
	}
	for (i = 0; i < ARRAY_SIZE(stat->int_stat); i++) {
		__raw_writel(__raw_readl(&stat->int_stat[i]),
			     &stat->int_stat[i]);
	}
}

int ipuv3_fb_init(struct fb_videomode const *mode,
		  uint8_t disp,
		  uint32_t pixfmt)
{
	gmode = mode;
	gdisp = disp;
	gpixfmt = pixfmt;

	return 0;
}

enum {
	/* Maximum display size we support */
	LCD_MAX_WIDTH		= 1920,
	LCD_MAX_HEIGHT		= 1080,
	LCD_MAX_LOG2_BPP	= VIDEO_BPP16,
};

static int ipuv3_video_probe(struct udevice *dev)
{
	struct video_uc_plat *plat = dev_get_uclass_plat(dev);
	struct video_priv *uc_priv = dev_get_uclass_priv(dev);
#if defined(CONFIG_DISPLAY)
	struct udevice *disp_dev;
#endif
	u32 fb_start, fb_end;
	int ret;

	debug("%s() plat: base 0x%lx, size 0x%x\n",
	      __func__, plat->base, plat->size);

	ret = ipu_probe();
	if (ret)
		return ret;

	ret = ipu_displays_init();
	if (ret < 0)
		return ret;

	ret = mxcfb_probe(dev, gpixfmt, gdisp, gmode);
	if (ret < 0)
		return ret;

#if defined(CONFIG_DISPLAY)
	ret = uclass_first_device(UCLASS_DISPLAY, &disp_dev);
	if (disp_dev) {
		ret = display_enable(disp_dev, 16, NULL);
		if (ret < 0)
			return ret;
	}
#endif
	if (CONFIG_IS_ENABLED(PANEL)) {
		struct udevice *panel_dev;

		ret = uclass_get_device(UCLASS_PANEL, 0, &panel_dev);
		if (panel_dev)
			panel_enable_backlight(panel_dev);
	}

	uc_priv->xsize = gmode->xres;
	uc_priv->ysize = gmode->yres;
	uc_priv->bpix = LCD_MAX_LOG2_BPP;

	/* Enable dcache for the frame buffer */
	fb_start = plat->base & ~(MMU_SECTION_SIZE - 1);
	fb_end = plat->base + plat->size;
	fb_end = ALIGN(fb_end, 1 << MMU_SECTION_SHIFT);
	mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start,
					DCACHE_WRITEBACK);
	video_set_flush_dcache(dev, true);
	gd->fb_base = fb_start;

	return 0;
}

struct ipuv3_video_priv {
	ulong regs;
};

static int ipuv3_video_bind(struct udevice *dev)
{
	struct video_uc_plat *plat = dev_get_uclass_plat(dev);

	plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
		     (1 << VIDEO_BPP32) / 8;

	return 0;
}

static const struct udevice_id ipuv3_video_ids[] = {
#ifdef CONFIG_ARCH_MX6
	{ .compatible = "fsl,imx6q-ipu" },
#endif
#ifdef CONFIG_ARCH_MX5
	{ .compatible = "fsl,imx53-ipu" },
#endif
	{ }
};

U_BOOT_DRIVER(fsl_imx6q_ipu) = {
	.name	= "fsl_imx6q_ipu",
	.id	= UCLASS_VIDEO,
	.of_match = ipuv3_video_ids,
	.bind	= ipuv3_video_bind,
	.probe	= ipuv3_video_probe,
	.priv_auto	= sizeof(struct ipuv3_video_priv),
	.flags	= DM_FLAG_PRE_RELOC,
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
5dda7945 SB	2	/*
	3	* Porting to u-boot:
	4	*
	5	* (C) Copyright 2010
	6	* Stefano Babic, DENX Software Engineering, [email protected]
	7	*
	8	* MX51 Linux framebuffer:
	9	*
	10	* (C) Copyright 2004-2010 Freescale Semiconductor, Inc.
5dda7945 SB	11	*/
5dda7945 SB	12
5dda7945	13	#include <common.h>
f7ae49fc	14	#include <log.h>
e6f6f9e6	15	#include <part.h>
90526e9f	16	#include <asm/cache.h>
1221ce45	17	#include <linux/errno.h>
a69214dc	18	#include <asm/global_data.h>
5dda7945 SB	19	#include <linux/string.h>
	20	#include <linux/list.h>
	21	#include <linux/fb.h>
	22	#include <asm/io.h>
57f065fe	23	#include <asm/mach-imx/video.h>
5dda7945	24	#include <malloc.h>
e9934f0b	25	#include <video_fb.h>
bffd1314	26	#include "../videomodes.h"
5dda7945 SB	27	#include "ipu.h"
5dda7945 SB	28	#include "mxcfb.h"
5f8e17ce	29	#include "ipu_regs.h"
f4ec1ae0	30	#include "display.h"
42a7ce27	31	#include <panel.h>
5dda7945	32
57f065fe AG	33	#include <dm.h>
	34	#include <video.h>
	35
a69214dc EN	36	DECLARE_GLOBAL_DATA_PTR;
a69214dc EN	37
5dda7945 SB	38	static int mxcfb_map_video_memory(struct fb_info *fbi);
	39	static int mxcfb_unmap_video_memory(struct fb_info *fbi);
	40
09c8bb26	41	static struct fb_videomode const *gmode;
02ae1a18 MV	42	static uint8_t gdisp;
02ae1a18 MV	43	static uint32_t gpixfmt;
5dda7945	44
c5fe2532	45	static void fb_videomode_to_var(struct fb_var_screeninfo *var,
5dda7945 SB	46	const struct fb_videomode *mode)
	47	{
	48	var->xres = mode->xres;
	49	var->yres = mode->yres;
	50	var->xres_virtual = mode->xres;
	51	var->yres_virtual = mode->yres;
	52	var->xoffset = 0;
	53	var->yoffset = 0;
	54	var->pixclock = mode->pixclock;
	55	var->left_margin = mode->left_margin;
	56	var->right_margin = mode->right_margin;
	57	var->upper_margin = mode->upper_margin;
	58	var->lower_margin = mode->lower_margin;
	59	var->hsync_len = mode->hsync_len;
	60	var->vsync_len = mode->vsync_len;
	61	var->sync = mode->sync;
	62	var->vmode = mode->vmode & FB_VMODE_MASK;
	63	}
	64
	65	/*
	66	* Structure containing the MXC specific framebuffer information.
	67	*/
	68	struct mxcfb_info {
3ce83ee0	69	struct udevice *udev;
5dda7945 SB	70	int blank;
	71	ipu_channel_t ipu_ch;
	72	int ipu_di;
	73	u32 ipu_di_pix_fmt;
	74	unsigned char overlay;
	75	unsigned char alpha_chan_en;
	76	dma_addr_t alpha_phy_addr0;
	77	dma_addr_t alpha_phy_addr1;
	78	void *alpha_virt_addr0;
	79	void *alpha_virt_addr1;
	80	uint32_t alpha_mem_len;
	81	uint32_t cur_ipu_buf;
	82	uint32_t cur_ipu_alpha_buf;
	83
	84	u32 pseudo_palette[16];
	85	};
	86
	87	enum {
	88	BOTH_ON,
	89	SRC_ON,
	90	TGT_ON,
	91	BOTH_OFF
	92	};
	93
	94	static unsigned long default_bpp = 16;
	95	static unsigned char g_dp_in_use;
	96	static struct fb_info *mxcfb_info[3];
	97	static int ext_clk_used;
	98
	99	static uint32_t bpp_to_pixfmt(struct fb_info *fbi)
	100	{
	101	uint32_t pixfmt = 0;
	102
	103	debug("bpp_to_pixfmt: %d\n", fbi->var.bits_per_pixel);
	104
	105	if (fbi->var.nonstd)
	106	return fbi->var.nonstd;
	107
	108	switch (fbi->var.bits_per_pixel) {
	109	case 24:
	110	pixfmt = IPU_PIX_FMT_BGR24;
	111	break;
	112	case 32:
	113	pixfmt = IPU_PIX_FMT_BGR32;
	114	break;
	115	case 16:
	116	pixfmt = IPU_PIX_FMT_RGB565;
	117	break;
	118	}
	119	return pixfmt;
	120	}
	121
5dda7945 SB	122	static int setup_disp_channel1(struct fb_info *fbi)
	123	{
	124	ipu_channel_params_t params;
	125	struct mxcfb_info mxc_fbi = (struct mxcfb_info )fbi->par;
	126
	127	memset(&params, 0, sizeof(params));
	128	params.mem_dp_bg_sync.di = mxc_fbi->ipu_di;
	129
	130	debug("%s called\n", __func__);
	131	/*
	132	* Assuming interlaced means yuv output, below setting also
	133	* valid for mem_dc_sync. FG should have the same vmode as BG.
	134	*/
	135	if (fbi->var.vmode & FB_VMODE_INTERLACED) {
	136	params.mem_dp_bg_sync.interlaced = 1;
	137	params.mem_dp_bg_sync.out_pixel_fmt =
	138	IPU_PIX_FMT_YUV444;
	139	} else {
	140	if (mxc_fbi->ipu_di_pix_fmt) {
	141	params.mem_dp_bg_sync.out_pixel_fmt =
	142	mxc_fbi->ipu_di_pix_fmt;
	143	} else {
	144	params.mem_dp_bg_sync.out_pixel_fmt =
	145	IPU_PIX_FMT_RGB666;
	146	}
	147	}
	148	params.mem_dp_bg_sync.in_pixel_fmt = bpp_to_pixfmt(fbi);
	149	if (mxc_fbi->alpha_chan_en)
	150	params.mem_dp_bg_sync.alpha_chan_en = 1;
	151
	152	ipu_init_channel(mxc_fbi->ipu_ch, &params);
	153
	154	return 0;
	155	}
	156
	157	static int setup_disp_channel2(struct fb_info *fbi)
	158	{
	159	int retval = 0;
	160	struct mxcfb_info mxc_fbi = (struct mxcfb_info )fbi->par;
	161
	162	mxc_fbi->cur_ipu_buf = 1;
	163	if (mxc_fbi->alpha_chan_en)
	164	mxc_fbi->cur_ipu_alpha_buf = 1;
	165
	166	fbi->var.xoffset = fbi->var.yoffset = 0;
	167
	168	debug("%s: %x %d %d %d %lx %lx\n",
	169	__func__,
	170	mxc_fbi->ipu_ch,
	171	fbi->var.xres,
	172	fbi->var.yres,
	173	fbi->fix.line_length,
	174	fbi->fix.smem_start,
	175	fbi->fix.smem_start +
	176	(fbi->fix.line_length * fbi->var.yres));
	177
	178	retval = ipu_init_channel_buffer(mxc_fbi->ipu_ch, IPU_INPUT_BUFFER,
	179	bpp_to_pixfmt(fbi),
	180	fbi->var.xres, fbi->var.yres,
	181	fbi->fix.line_length,
	182	fbi->fix.smem_start +
	183	(fbi->fix.line_length * fbi->var.yres),
	184	fbi->fix.smem_start,
	185	0, 0);
186	if (retval)
187	printf("ipu_init_channel_buffer error %d\n", retval);
188
189	return retval;
190	}
191
192	/*
193	* Set framebuffer parameters and change the operating mode.
194	*
195	* @param info framebuffer information pointer
196	*/
197	static int mxcfb_set_par(struct fb_info *fbi)
198	{
199	int retval = 0;
200	u32 mem_len;
201	ipu_di_signal_cfg_t sig_cfg;
202	struct mxcfb_info mxc_fbi = (struct mxcfb_info )fbi->par;
203	uint32_t out_pixel_fmt;
204
205	ipu_disable_channel(mxc_fbi->ipu_ch);
206	ipu_uninit_channel(mxc_fbi->ipu_ch);
5dda7945 SB	207
	208	mem_len = fbi->var.yres_virtual * fbi->fix.line_length;
	209	if (!fbi->fix.smem_start \|\| (mem_len > fbi->fix.smem_len)) {
	210	if (fbi->fix.smem_start)
	211	mxcfb_unmap_video_memory(fbi);
	212
	213	if (mxcfb_map_video_memory(fbi) < 0)
	214	return -ENOMEM;
	215	}
	216
	217	setup_disp_channel1(fbi);
	218
	219	memset(&sig_cfg, 0, sizeof(sig_cfg));
	220	if (fbi->var.vmode & FB_VMODE_INTERLACED) {
	221	sig_cfg.interlaced = 1;
	222	out_pixel_fmt = IPU_PIX_FMT_YUV444;
	223	} else {
	224	if (mxc_fbi->ipu_di_pix_fmt)
	225	out_pixel_fmt = mxc_fbi->ipu_di_pix_fmt;
	226	else
	227	out_pixel_fmt = IPU_PIX_FMT_RGB666;
	228	}
	229	if (fbi->var.vmode & FB_VMODE_ODD_FLD_FIRST) /* PAL */
	230	sig_cfg.odd_field_first = 1;
	231	if ((fbi->var.sync & FB_SYNC_EXT) \|\| ext_clk_used)
	232	sig_cfg.ext_clk = 1;
	233	if (fbi->var.sync & FB_SYNC_HOR_HIGH_ACT)
	234	sig_cfg.Hsync_pol = 1;
	235	if (fbi->var.sync & FB_SYNC_VERT_HIGH_ACT)
	236	sig_cfg.Vsync_pol = 1;
	237	if (!(fbi->var.sync & FB_SYNC_CLK_LAT_FALL))
	238	sig_cfg.clk_pol = 1;
	239	if (fbi->var.sync & FB_SYNC_DATA_INVERT)
	240	sig_cfg.data_pol = 1;
	241	if (!(fbi->var.sync & FB_SYNC_OE_LOW_ACT))
	242	sig_cfg.enable_pol = 1;
	243	if (fbi->var.sync & FB_SYNC_CLK_IDLE_EN)
	244	sig_cfg.clkidle_en = 1;
	245
c1420328	246	debug("pixclock = %lu Hz\n", PICOS2KHZ(fbi->var.pixclock) * 1000UL);
5dda7945 SB	247
	248	if (ipu_init_sync_panel(mxc_fbi->ipu_di,
	249	(PICOS2KHZ(fbi->var.pixclock)) * 1000UL,
	250	fbi->var.xres, fbi->var.yres,
	251	out_pixel_fmt,
	252	fbi->var.left_margin,
	253	fbi->var.hsync_len,
	254	fbi->var.right_margin,
	255	fbi->var.upper_margin,
	256	fbi->var.vsync_len,
	257	fbi->var.lower_margin,
	258	0, sig_cfg) != 0) {
	259	puts("mxcfb: Error initializing panel.\n");
	260	return -EINVAL;
	261	}
	262
	263	retval = setup_disp_channel2(fbi);
	264	if (retval)
	265	return retval;
	266
	267	if (mxc_fbi->blank == FB_BLANK_UNBLANK)
	268	ipu_enable_channel(mxc_fbi->ipu_ch);
	269
	270	return retval;
	271	}
	272
	273	/*
	274	* Check framebuffer variable parameters and adjust to valid values.
	275	*
	276	* @param var framebuffer variable parameters
	277	*
	278	* @param info framebuffer information pointer
	279	*/
	280	static int mxcfb_check_var(struct fb_var_screeninfo var, struct fb_info info)
	281	{
	282	u32 vtotal;
	283	u32 htotal;
	284
	285	if (var->xres_virtual < var->xres)
	286	var->xres_virtual = var->xres;
	287	if (var->yres_virtual < var->yres)
	288	var->yres_virtual = var->yres;
	289
	290	if ((var->bits_per_pixel != 32) && (var->bits_per_pixel != 24) &&
	291	(var->bits_per_pixel != 16) && (var->bits_per_pixel != 8))
	292	var->bits_per_pixel = default_bpp;
	293
	294	switch (var->bits_per_pixel) {
	295	case 8:
	296	var->red.length = 3;
	297	var->red.offset = 5;
	298	var->red.msb_right = 0;
	299
	300	var->green.length = 3;
	301	var->green.offset = 2;
	302	var->green.msb_right = 0;
	303
	304	var->blue.length = 2;
	305	var->blue.offset = 0;
	306	var->blue.msb_right = 0;
	307
	308	var->transp.length = 0;
	309	var->transp.offset = 0;
	310	var->transp.msb_right = 0;
311	break;
312	case 16:
313	var->red.length = 5;
314	var->red.offset = 11;
315	var->red.msb_right = 0;
316
317	var->green.length = 6;
318	var->green.offset = 5;
319	var->green.msb_right = 0;
320
321	var->blue.length = 5;
322	var->blue.offset = 0;
323	var->blue.msb_right = 0;
324
325	var->transp.length = 0;
326	var->transp.offset = 0;
327	var->transp.msb_right = 0;
328	break;
329	case 24:
330	var->red.length = 8;
331	var->red.offset = 16;
332	var->red.msb_right = 0;
333
334	var->green.length = 8;
335	var->green.offset = 8;
336	var->green.msb_right = 0;
337
338	var->blue.length = 8;
339	var->blue.offset = 0;
340	var->blue.msb_right = 0;
341
342	var->transp.length = 0;
343	var->transp.offset = 0;
344	var->transp.msb_right = 0;
345	break;
346	case 32:
347	var->red.length = 8;
348	var->red.offset = 16;
349	var->red.msb_right = 0;
350
351	var->green.length = 8;
352	var->green.offset = 8;
353	var->green.msb_right = 0;
354
355	var->blue.length = 8;
356	var->blue.offset = 0;
357	var->blue.msb_right = 0;
358
359	var->transp.length = 8;
360	var->transp.offset = 24;
361	var->transp.msb_right = 0;
362	break;
363	}
364
365	if (var->pixclock < 1000) {
366	htotal = var->xres + var->right_margin + var->hsync_len +
367	var->left_margin;
368	vtotal = var->yres + var->lower_margin + var->vsync_len +
369	var->upper_margin;
370	var->pixclock = (vtotal * htotal * 6UL) / 100UL;
371	var->pixclock = KHZ2PICOS(var->pixclock);
372	printf("pixclock set for 60Hz refresh = %u ps\n",
373	var->pixclock);
374	}
375
376	var->height = -1;
377	var->width = -1;
378	var->grayscale = 0;
379
380	return 0;
381	}
382
383	static int mxcfb_map_video_memory(struct fb_info *fbi)
384	{
3ce83ee0	385	struct mxcfb_info mxc_fbi = (struct mxcfb_info )fbi->par;
8a8d24bd	386	struct video_uc_plat *plat = dev_get_uclass_plat(mxc_fbi->udev);
3ce83ee0	387
5dda7945 SB	388	if (fbi->fix.smem_len < fbi->var.yres_virtual * fbi->fix.line_length) {
	389	fbi->fix.smem_len = fbi->var.yres_virtual *
	390	fbi->fix.line_length;
	391	}
4acb4d39	392	fbi->fix.smem_len = roundup(fbi->fix.smem_len, ARCH_DMA_MINALIGN);
57f065fe	393
3ce83ee0	394	fbi->screen_base = (char *)plat->base;
57f065fe	395
e9934f0b	396	fbi->fix.smem_start = (unsigned long)fbi->screen_base;
5dda7945 SB	397	if (fbi->screen_base == 0) {
	398	puts("Unable to allocate framebuffer memory\n");
	399	fbi->fix.smem_len = 0;
	400	fbi->fix.smem_start = 0;
	401	return -EBUSY;
	402	}
	403
	404	debug("allocated fb @ paddr=0x%08X, size=%d.\n",
	405	(uint32_t) fbi->fix.smem_start, fbi->fix.smem_len);
	406
	407	fbi->screen_size = fbi->fix.smem_len;
a69214dc EN	408	gd->fb_base = fbi->fix.smem_start;
a69214dc EN	409
5dda7945 SB	410	/* Clear the screen */
	411	memset((char *)fbi->screen_base, 0, fbi->fix.smem_len);
	412
	413	return 0;
	414	}
	415
	416	static int mxcfb_unmap_video_memory(struct fb_info *fbi)
	417	{
	418	fbi->screen_base = 0;
	419	fbi->fix.smem_start = 0;
	420	fbi->fix.smem_len = 0;
	421	return 0;
	422	}
	423
	424	/*
	425	* Initializes the framebuffer information pointer. After allocating
	426	* sufficient memory for the framebuffer structure, the fields are
	427	* filled with custom information passed in from the configurable
	428	* structures. This includes information such as bits per pixel,
	429	* color maps, screen width/height and RGBA offsets.
	430	*
	431	* @return Framebuffer structure initialized with our information
	432	*/
	433	static struct fb_info *mxcfb_init_fbinfo(void)
	434	{
	435	#define BYTES_PER_LONG 4
	436	#define PADDING (BYTES_PER_LONG - (sizeof(struct fb_info) % BYTES_PER_LONG))
	437	struct fb_info *fbi;
	438	struct mxcfb_info *mxcfbi;
	439	char *p;
	440	int size = sizeof(struct mxcfb_info) + PADDING +
	441	sizeof(struct fb_info);
	442
	443	debug("%s: %d %d %d %d\n",
	444	__func__,
	445	PADDING,
	446	size,
	447	sizeof(struct mxcfb_info),
	448	sizeof(struct fb_info));
	449	/*
	450	* Allocate sufficient memory for the fb structure
	451	*/
	452
	453	p = malloc(size);
	454	if (!p)
	455	return NULL;
	456
	457	memset(p, 0, size);
	458
	459	fbi = (struct fb_info *)p;
	460	fbi->par = p + sizeof(struct fb_info) + PADDING;
	461
	462	mxcfbi = (struct mxcfb_info *)fbi->par;
	463	debug("Framebuffer structures at: fbi=0x%x mxcfbi=0x%x\n",
	464	(unsigned int)fbi, (unsigned int)mxcfbi);
	465
	466	fbi->var.activate = FB_ACTIVATE_NOW;
	467
	468	fbi->flags = FBINFO_FLAG_DEFAULT;
	469	fbi->pseudo_palette = mxcfbi->pseudo_palette;
	470
	471	return fbi;
	472	}
	473
db755b36 AG	474	extern struct clk *g_ipu_clk;
db755b36 AG	475
5dda7945 SB	476	/*
5dda7945 SB	477	* Probe routine for the framebuffer driver. It is called during the
c1420328	478	* driver binding process. The following functions are performed in
5dda7945 SB	479	* this routine: Framebuffer initialization, Memory allocation and
	480	* mapping, Framebuffer registration, IPU initialization.
	481	*
	482	* @return Appropriate error code to the kernel common code
	483	*/
3ce83ee0 AG	484	static int mxcfb_probe(struct udevice *dev, u32 interface_pix_fmt,
3ce83ee0 AG	485	uint8_t disp, struct fb_videomode const *mode)
5dda7945 SB	486	{
	487	struct fb_info *fbi;
	488	struct mxcfb_info *mxcfbi;
5dda7945 SB	489
	490	/*
	491	* Initialize FB structures
	492	*/
	493	fbi = mxcfb_init_fbinfo();
db755b36 AG	494	if (!fbi)
	495	return -ENOMEM;
	496
5dda7945 SB	497	mxcfbi = (struct mxcfb_info *)fbi->par;
	498
	499	if (!g_dp_in_use) {
	500	mxcfbi->ipu_ch = MEM_BG_SYNC;
	501	mxcfbi->blank = FB_BLANK_UNBLANK;
	502	} else {
	503	mxcfbi->ipu_ch = MEM_DC_SYNC;
	504	mxcfbi->blank = FB_BLANK_POWERDOWN;
	505	}
	506
02ae1a18	507	mxcfbi->ipu_di = disp;
3ce83ee0	508	mxcfbi->udev = dev;
5dda7945	509
db755b36 AG	510	if (!ipu_clk_enabled())
	511	clk_enable(g_ipu_clk);
	512
5dda7945 SB	513	ipu_disp_set_global_alpha(mxcfbi->ipu_ch, 1, 0x80);
5dda7945 SB	514	ipu_disp_set_color_key(mxcfbi->ipu_ch, 0, 0);
5dda7945 SB	515
	516	g_dp_in_use = 1;
	517
	518	mxcfb_info[mxcfbi->ipu_di] = fbi;
	519
	520	/* Need dummy values until real panel is configured */
5dda7945 SB	521
	522	mxcfbi->ipu_di_pix_fmt = interface_pix_fmt;
	523	fb_videomode_to_var(&fbi->var, mode);
e9934f0b	524	fbi->var.bits_per_pixel = 16;
db755b36 AG	525	fbi->fix.line_length = fbi->var.xres_virtual *
db755b36 AG	526	(fbi->var.bits_per_pixel / 8);
e9934f0b	527	fbi->fix.smem_len = fbi->var.yres_virtual * fbi->fix.line_length;
5dda7945 SB	528
	529	mxcfb_check_var(&fbi->var, fbi);
	530
	531	/* Default Y virtual size is 2x panel size */
	532	fbi->var.yres_virtual = fbi->var.yres * 2;
	533
c1420328	534	/* allocate fb first */
5dda7945 SB	535	if (mxcfb_map_video_memory(fbi) < 0)
	536	return -ENOMEM;
	537
	538	mxcfb_set_par(fbi);
	539
db755b36	540	#ifdef DEBUG
5dda7945	541	ipu_dump_registers();
db755b36	542	#endif
5dda7945 SB	543
5dda7945 SB	544	return 0;
5dda7945 SB	545	}
5dda7945 SB	546
5f8e17ce EN	547	void ipuv3_fb_shutdown(void)
5f8e17ce EN	548	{
0d1ae97c	549	int i;
9493d05a	550	struct ipu_stat stat = (struct ipu_stat )IPU_STAT;
5f8e17ce	551
f8ba7f27 AG	552	if (!ipu_clk_enabled())
	553	return;
	554
5f8e17ce EN	555	for (i = 0; i < ARRAY_SIZE(mxcfb_info); i++) {
	556	struct fb_info *fbi = mxcfb_info[i];
	557	if (fbi) {
	558	struct mxcfb_info *mxc_fbi = fbi->par;
	559	ipu_disable_channel(mxc_fbi->ipu_ch);
	560	ipu_uninit_channel(mxc_fbi->ipu_ch);
	561	}
	562	}
	563	for (i = 0; i < ARRAY_SIZE(stat->int_stat); i++) {
	564	__raw_writel(__raw_readl(&stat->int_stat[i]),
	565	&stat->int_stat[i]);
	566	}
	567	}
	568
09c8bb26 EN	569	int ipuv3_fb_init(struct fb_videomode const *mode,
	570	uint8_t disp,
	571	uint32_t pixfmt)
e9934f0b SB	572	{
e9934f0b SB	573	gmode = mode;
02ae1a18 MV	574	gdisp = disp;
02ae1a18 MV	575	gpixfmt = pixfmt;
e9934f0b SB	576
e9934f0b SB	577	return 0;
5dda7945	578	}
57f065fe	579
57f065fe AG	580	enum {
	581	/* Maximum display size we support */
	582	LCD_MAX_WIDTH = 1920,
	583	LCD_MAX_HEIGHT = 1080,
	584	LCD_MAX_LOG2_BPP = VIDEO_BPP16,
	585	};
	586
	587	static int ipuv3_video_probe(struct udevice *dev)
	588	{
8a8d24bd	589	struct video_uc_plat *plat = dev_get_uclass_plat(dev);
57f065fe	590	struct video_priv *uc_priv = dev_get_uclass_priv(dev);
f4ec1ae0 HS	591	#if defined(CONFIG_DISPLAY)
	592	struct udevice *disp_dev;
	593	#endif
57f065fe AG	594	u32 fb_start, fb_end;
	595	int ret;
	596
	597	debug("%s() plat: base 0x%lx, size 0x%x\n",
	598	__func__, plat->base, plat->size);
	599
	600	ret = ipu_probe();
	601	if (ret)
	602	return ret;
	603
	604	ret = ipu_displays_init();
	605	if (ret < 0)
	606	return ret;
	607
3ce83ee0	608	ret = mxcfb_probe(dev, gpixfmt, gdisp, gmode);
57f065fe AG	609	if (ret < 0)
	610	return ret;
	611
f4ec1ae0 HS	612	#if defined(CONFIG_DISPLAY)
	613	ret = uclass_first_device(UCLASS_DISPLAY, &disp_dev);
	614	if (disp_dev) {
	615	ret = display_enable(disp_dev, 16, NULL);
	616	if (ret < 0)
	617	return ret;
	618	}
	619	#endif
0b12f76f AG	620	if (CONFIG_IS_ENABLED(PANEL)) {
	621	struct udevice *panel_dev;
	622
	623	ret = uclass_get_device(UCLASS_PANEL, 0, &panel_dev);
	624	if (panel_dev)
	625	panel_enable_backlight(panel_dev);
	626	}
f4ec1ae0	627
57f065fe AG	628	uc_priv->xsize = gmode->xres;
	629	uc_priv->ysize = gmode->yres;
	630	uc_priv->bpix = LCD_MAX_LOG2_BPP;
	631
	632	/* Enable dcache for the frame buffer */
	633	fb_start = plat->base & ~(MMU_SECTION_SIZE - 1);
	634	fb_end = plat->base + plat->size;
	635	fb_end = ALIGN(fb_end, 1 << MMU_SECTION_SHIFT);
	636	mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start,
	637	DCACHE_WRITEBACK);
	638	video_set_flush_dcache(dev, true);
f03e56ad	639	gd->fb_base = fb_start;
57f065fe AG	640
	641	return 0;
	642	}
	643
	644	struct ipuv3_video_priv {
	645	ulong regs;
	646	};
	647
	648	static int ipuv3_video_bind(struct udevice *dev)
	649	{
8a8d24bd	650	struct video_uc_plat *plat = dev_get_uclass_plat(dev);
57f065fe AG	651
57f065fe AG	652	plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
b5e1a82e	653	(1 << VIDEO_BPP32) / 8;
57f065fe AG	654
	655	return 0;
	656	}
	657
	658	static const struct udevice_id ipuv3_video_ids[] = {
db755b36	659	#ifdef CONFIG_ARCH_MX6
57f065fe	660	{ .compatible = "fsl,imx6q-ipu" },
db755b36 AG	661	#endif
db755b36 AG	662	#ifdef CONFIG_ARCH_MX5
01c9dd21	663	{ .compatible = "fsl,imx53-ipu" },
db755b36	664	#endif
57f065fe AG	665	{ }
	666	};
	667
24968d9e WL	668	U_BOOT_DRIVER(fsl_imx6q_ipu) = {
24968d9e WL	669	.name = "fsl_imx6q_ipu",
57f065fe AG	670	.id = UCLASS_VIDEO,
	671	.of_match = ipuv3_video_ids,
	672	.bind = ipuv3_video_bind,
	673	.probe = ipuv3_video_probe,
41575d8e	674	.priv_auto = sizeof(struct ipuv3_video_priv),
57f065fe AG	675	.flags = DM_FLAG_PRE_RELOC,
57f065fe AG	676	};