[u-boot.git] / drivers / pinctrl / mtmips / pinctrl-mt7628.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2019 MediaTek Inc. All Rights Reserved.
 *
 * Author: Weijie Gao <[email protected]>
 */

#include <common.h>
#include <dm.h>
#include <dm/pinctrl.h>
#include <linux/bitops.h>
#include <linux/io.h>

#include "pinctrl-mtmips-common.h"

DECLARE_GLOBAL_DATA_PTR;

#define AGPIO_OFS			0
#define GPIOMODE1_OFS			0x24
#define GPIOMODE2_OFS			0x28

#define EPHY4_1_PAD_SHIFT		17
#define EPHY4_1_PAD_MASK		0x0f
#define EPHY0_SHIFT			16
#define RF_OLT_MODE_SHIFT		12
#define N9_EINT_SRC_SHIFT		9
#define WLED_OD_SHIFT			8
#define REF_CLKO_PAD_SHIFT		4
#define I2S_CLK_PAD_SHIFT		3
#define I2S_WS_PAD_SHIFT		2
#define I2S_SDO_PAD_SHIFT		1
#define I2S_SDI_PAD_SHIFT		0

#define GM4_MASK			3

#define P4LED_K_SHIFT			26
#define P3LED_K_SHIFT			24
#define P2LED_K_SHIFT			22
#define P1LED_K_SHIFT			20
#define P0LED_K_SHIFT			18
#define WLED_K_SHIFT			16
#define P4LED_A_SHIFT			10
#define P3LED_A_SHIFT			8
#define P2LED_A_SHIFT			6
#define P1LED_A_SHIFT			4
#define P0LED_A_SHIFT			2
#define WLED_A_SHIFT			0

#define PWM1_SHIFT			30
#define PWM0_SHIFT			28
#define UART2_SHIFT			26
#define UART1_SHIFT			24
#define I2C_SHIFT			20
#define REFCLK_SHIFT			18
#define PERST_SHIFT			16
#define ESD_SHIFT			15
#define WDT_SHIFT			14
#define SPI_SHIFT			12
#define SDMODE_SHIFT			10
#define UART0_SHIFT			8
#define I2S_SHIFT			6
#define SPI_CS1_SHIFT			4
#define SPIS_SHIFT			2
#define GPIO0_SHIFT			0

#define PAD_PU_G0_REG			0x00
#define PAD_PU_G1_REG			0x04
#define PAD_PD_G0_REG			0x10
#define PAD_PD_G1_REG			0x14
#define PAD_SR_G0_REG			0x20
#define PAD_SR_G1_REG			0x24
#define PAD_SMT_G0_REG			0x30
#define PAD_SMT_G1_REG			0x34
#define PAD_E2_G0_REG			0x40
#define PAD_E2_G1_REG			0x44
#define PAD_E4_G0_REG			0x50
#define PAD_E4_G1_REG			0x54
#define PAD_E8_G0_REG			0x60
#define PAD_E8_G1_REG			0x64

#define PIN_CONFIG_DRIVE_STRENGTH_28	(PIN_CONFIG_END + 1)
#define PIN_CONFIG_DRIVE_STRENGTH_4G	(PIN_CONFIG_END + 2)

struct mt7628_pinctrl_priv {
	struct mtmips_pinctrl_priv mp;

	void __iomem *pcbase;
};

#if CONFIG_IS_ENABLED(PINMUX)
static const struct mtmips_pmx_func ephy4_1_pad_grp[] = {
	FUNC("digital", 0xf),
	FUNC("analog", 0),
};

static const struct mtmips_pmx_func ephy0_grp[] = {
	FUNC("disable", 1),
	FUNC("enable", 0),
};

static const struct mtmips_pmx_func rf_olt_grp[] = {
	FUNC("enable", 1),
	FUNC("disable", 0),
};

static const struct mtmips_pmx_func n9_eint_src_grp[] = {
	FUNC("gpio", 1),
	FUNC("utif", 0),
};

static const struct mtmips_pmx_func wlen_od_grp[] = {
	FUNC("enable", 1),
	FUNC("disable", 0),
};

static const struct mtmips_pmx_func ref_clko_grp[] = {
	FUNC("digital", 1),
	FUNC("analog", 0),
};

static const struct mtmips_pmx_func i2s_clk_grp[] = {
	FUNC("digital", 1),
	FUNC("analog", 0),
};

static const struct mtmips_pmx_func i2s_ws_grp[] = {
	FUNC("digital", 1),
	FUNC("analog", 0),
};

static const struct mtmips_pmx_func i2s_sdo_grp[] = {
	FUNC("digital", 1),
	FUNC("analog", 0),
};

static const struct mtmips_pmx_func i2s_sdi_grp[] = {
	FUNC("digital", 1),
	FUNC("analog", 0),
};

static const struct mtmips_pmx_func pwm1_grp[] = {
	FUNC("sdxc d6", 3),
	FUNC("utif", 2),
	FUNC("gpio", 1),
	FUNC("pwm1", 0),
};

static const struct mtmips_pmx_func pwm0_grp[] = {
	FUNC("sdxc d7", 3),
	FUNC("utif", 2),
	FUNC("gpio", 1),
	FUNC("pwm0", 0),
};

static const struct mtmips_pmx_func uart2_grp[] = {
	FUNC("sdxc d5 d4", 3),
	FUNC("pwm", 2),
	FUNC("gpio", 1),
	FUNC("uart2", 0),
};

static const struct mtmips_pmx_func uart1_grp[] = {
	FUNC("sw_r", 3),
	FUNC("pwm", 2),
	FUNC("gpio", 1),
	FUNC("uart1", 0),
};

static const struct mtmips_pmx_func i2c_grp[] = {
	FUNC("-", 3),
	FUNC("debug", 2),
	FUNC("gpio", 1),
	FUNC("i2c", 0),
};

static const struct mtmips_pmx_func refclk_grp[] = {
	FUNC("gpio", 1),
	FUNC("refclk", 0),
};

static const struct mtmips_pmx_func perst_grp[] = {
	FUNC("gpio", 1),
	FUNC("perst", 0),
};

static const struct mtmips_pmx_func esd_grp[] = {
	FUNC("router", 1),
	FUNC("iot", 0),
};

static const struct mtmips_pmx_func wdt_grp[] = {
	FUNC("gpio", 1),
	FUNC("wdt", 0),
};

static const struct mtmips_pmx_func spi_grp[] = {
	FUNC("gpio", 1),
	FUNC("spi", 0),
};

static const struct mtmips_pmx_func sd_mode_grp[] = {
	FUNC("n9 jtag", 3),
	FUNC("utif1", 2),
	FUNC("gpio", 1),
	FUNC("sdxc", 0),
};

static const struct mtmips_pmx_func uart0_grp[] = {
	FUNC("-", 3),
	FUNC("-", 2),
	FUNC("gpio", 1),
	FUNC("uart0", 0),
};

static const struct mtmips_pmx_func i2s_grp[] = {
	FUNC("antenna", 3),
	FUNC("pcm", 2),
	FUNC("gpio", 1),
	FUNC("i2s", 0),
};

static const struct mtmips_pmx_func spi_cs1_grp[] = {
	FUNC("-", 3),
	FUNC("refclk", 2),
	FUNC("gpio", 1),
	FUNC("spi cs1", 0),
};

static const struct mtmips_pmx_func spis_grp[] = {
	FUNC("pwm_uart2", 3),
	FUNC("utif", 2),
	FUNC("gpio", 1),
	FUNC("spis", 0),
};

static const struct mtmips_pmx_func gpio0_grp[] = {
	FUNC("perst", 3),
	FUNC("refclk", 2),
	FUNC("gpio", 1),
	FUNC("gpio0", 0),
};

static const struct mtmips_pmx_func wled_a_grp[] = {
	FUNC("-", 3),
	FUNC("-", 2),
	FUNC("gpio", 1),
	FUNC("led", 0),
};

static const struct mtmips_pmx_func p0led_a_grp[] = {
	FUNC("jtag", 3),
	FUNC("rsvd", 2),
	FUNC("gpio", 1),
	FUNC("led", 0),
};

static const struct mtmips_pmx_func p1led_a_grp[] = {
	FUNC("jtag", 3),
	FUNC("utif", 2),
	FUNC("gpio", 1),
	FUNC("led", 0),
};

static const struct mtmips_pmx_func p2led_a_grp[] = {
	FUNC("jtag", 3),
	FUNC("utif", 2),
	FUNC("gpio", 1),
	FUNC("led", 0),
};

static const struct mtmips_pmx_func p3led_a_grp[] = {
	FUNC("jtag", 3),
	FUNC("utif", 2),
	FUNC("gpio", 1),
	FUNC("led", 0),
};

static const struct mtmips_pmx_func p4led_a_grp[] = {
	FUNC("jtag", 3),
	FUNC("utif", 2),
	FUNC("gpio", 1),
	FUNC("led", 0),
};

static const struct mtmips_pmx_func wled_k_grp[] = {
	FUNC("-", 3),
	FUNC("-", 2),
	FUNC("gpio", 1),
	FUNC("led", 0),
};

static const struct mtmips_pmx_func p0led_k_grp[] = {
	FUNC("jtag", 3),
	FUNC("rsvd", 2),
	FUNC("gpio", 1),
	FUNC("led", 0),
};

static const struct mtmips_pmx_func p1led_k_grp[] = {
	FUNC("jtag", 3),
	FUNC("utif", 2),
	FUNC("gpio", 1),
	FUNC("led", 0),
};

static const struct mtmips_pmx_func p2led_k_grp[] = {
	FUNC("jtag", 3),
	FUNC("utif", 2),
	FUNC("gpio", 1),
	FUNC("led", 0),
};

static const struct mtmips_pmx_func p3led_k_grp[] = {
	FUNC("jtag", 3),
	FUNC("utif", 2),
	FUNC("gpio", 1),
	FUNC("led", 0),
};

static const struct mtmips_pmx_func p4led_k_grp[] = {
	FUNC("jtag", 3),
	FUNC("utif", 2),
	FUNC("gpio", 1),
	FUNC("led", 0),
};

static const struct mtmips_pmx_group mt7628_pinmux_data[] = {
	GRP("ephy4_1_pad", ephy4_1_pad_grp, AGPIO_OFS, EPHY4_1_PAD_SHIFT,
	    EPHY4_1_PAD_MASK),
	GRP("ephy0", ephy0_grp, AGPIO_OFS, EPHY0_SHIFT, 1),
	GRP("rf_olt", rf_olt_grp, AGPIO_OFS, RF_OLT_MODE_SHIFT, 1),
	GRP("n9_eint_src", n9_eint_src_grp, AGPIO_OFS, N9_EINT_SRC_SHIFT, 1),
	GRP("wlen_od", wlen_od_grp, AGPIO_OFS, WLED_OD_SHIFT, 1),
	GRP("ref_clko_pad", ref_clko_grp, AGPIO_OFS, REF_CLKO_PAD_SHIFT, 1),
	GRP("i2s_clk_pad", i2s_clk_grp, AGPIO_OFS, I2S_CLK_PAD_SHIFT, 1),
	GRP("i2s_ws_pad", i2s_ws_grp, AGPIO_OFS, I2S_WS_PAD_SHIFT, 1),
	GRP("i2s_sdo_pad", i2s_sdo_grp, AGPIO_OFS, I2S_SDO_PAD_SHIFT, 1),
	GRP("i2s_sdi_pad", i2s_sdi_grp, AGPIO_OFS, I2S_SDI_PAD_SHIFT, 1),
	GRP("pwm1", pwm1_grp, GPIOMODE1_OFS, PWM1_SHIFT, GM4_MASK),
	GRP("pwm0", pwm0_grp, GPIOMODE1_OFS, PWM0_SHIFT, GM4_MASK),
	GRP("uart2", uart2_grp, GPIOMODE1_OFS, UART2_SHIFT, GM4_MASK),
	GRP("uart1", uart1_grp, GPIOMODE1_OFS, UART1_SHIFT, GM4_MASK),
	GRP("i2c", i2c_grp, GPIOMODE1_OFS, I2C_SHIFT, GM4_MASK),
	GRP("refclk", refclk_grp, GPIOMODE1_OFS, REFCLK_SHIFT, 1),
	GRP("perst", perst_grp, GPIOMODE1_OFS, PERST_SHIFT, 1),
	GRP("sd router", esd_grp, GPIOMODE1_OFS, ESD_SHIFT, 1),
	GRP("wdt", wdt_grp, GPIOMODE1_OFS, WDT_SHIFT, 1),
	GRP("spi", spi_grp, GPIOMODE1_OFS, SPI_SHIFT, 1),
	GRP("sdmode", sd_mode_grp, GPIOMODE1_OFS, SDMODE_SHIFT, GM4_MASK),
	GRP("uart0", uart0_grp, GPIOMODE1_OFS, UART0_SHIFT, GM4_MASK),
	GRP("i2s", i2s_grp, GPIOMODE1_OFS, I2S_SHIFT, GM4_MASK),
	GRP("spi cs1", spi_cs1_grp, GPIOMODE1_OFS, SPI_CS1_SHIFT, GM4_MASK),
	GRP("spis", spis_grp, GPIOMODE1_OFS, SPIS_SHIFT, GM4_MASK),
	GRP("gpio0", gpio0_grp, GPIOMODE1_OFS, GPIO0_SHIFT, GM4_MASK),
	GRP("wled_a", wled_a_grp, GPIOMODE2_OFS, WLED_A_SHIFT, GM4_MASK),
	GRP("p0led_a", p0led_a_grp, GPIOMODE2_OFS, P0LED_A_SHIFT, GM4_MASK),
	GRP("p1led_a", p1led_a_grp, GPIOMODE2_OFS, P1LED_A_SHIFT, GM4_MASK),
	GRP("p2led_a", p2led_a_grp, GPIOMODE2_OFS, P2LED_A_SHIFT, GM4_MASK),
	GRP("p3led_a", p3led_a_grp, GPIOMODE2_OFS, P3LED_A_SHIFT, GM4_MASK),
	GRP("p4led_a", p4led_a_grp, GPIOMODE2_OFS, P4LED_A_SHIFT, GM4_MASK),
	GRP("wled_k", wled_k_grp, GPIOMODE2_OFS, WLED_K_SHIFT, GM4_MASK),
	GRP("p0led_k", p0led_k_grp, GPIOMODE2_OFS, P0LED_K_SHIFT, GM4_MASK),
	GRP("p1led_k", p1led_k_grp, GPIOMODE2_OFS, P1LED_K_SHIFT, GM4_MASK),
	GRP("p2led_k", p2led_k_grp, GPIOMODE2_OFS, P2LED_K_SHIFT, GM4_MASK),
	GRP("p3led_k", p3led_k_grp, GPIOMODE2_OFS, P3LED_K_SHIFT, GM4_MASK),
	GRP("p4led_k", p4led_k_grp, GPIOMODE2_OFS, P4LED_K_SHIFT, GM4_MASK),
};

static int mt7628_get_groups_count(struct udevice *dev)
{
	return ARRAY_SIZE(mt7628_pinmux_data);
}

static const char *mt7628_get_group_name(struct udevice *dev,
					 unsigned int selector)
{
	return mt7628_pinmux_data[selector].name;
}
#endif /* CONFIG_IS_ENABLED(PINMUX) */

#if CONFIG_IS_ENABLED(PINCONF)
static const struct pinconf_param mt7628_conf_params[] = {
	{ "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
	{ "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
	{ "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
	{ "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 },
	{ "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 },
	{ "drive-strength-28", PIN_CONFIG_DRIVE_STRENGTH_28, 0 },
	{ "drive-strength-4g", PIN_CONFIG_DRIVE_STRENGTH_4G, 0 },
	{ "slew-rate", PIN_CONFIG_SLEW_RATE, 0 },
};

static const char *const mt7628_pins[] = {
	"i2s_sdi",
	"i2s_sdo",
	"i2s_ws",
	"i2s_clk",
	"i2s_sclk",
	"i2c_sd",
	"spi_cs1",
	"spi_clk",
	"spi_mosi",
	"spi_miso",
	"spi_cs0",
	"gpio0",
	"uart0_txd",
	"uart0_rxd",
	"spis_cs",
	"spis_clk",
	"spis_miso",
	"spis_mosi",
	"pwm_ch0",
	"pwm_ch1",
	"uart2_txd",
	"uart2_rxd",
	"sd_wp",
	"sd_cd",
	"sd_d1",
	"sd_d0",
	"sd_clk",
	"sd_cmd",
	"sd_d3",
	"sd_d2",
	"ephy_led4_k",
	"ephy_led3_k",
	"ephy_led2_k",
	"ephy_led1_k",
	"ephy_led0_k",
	"wled_k",
	"perst_n",
	"co_clko",
	"wdt",
	"ephy_led4_a",
	"ephy_led3_a",
	"ephy_led2_a",
	"ephy_led1_a",
	"ephy_led0_a",
	"wled_a",
	"uart1_txd",
	"uart1_rxd",
};

static const u32 mt7628_drv_strength_28_tbl[] = {2, 4, 6, 8};
static const u32 mt7628_drv_strength_4g_tbl[] = {4, 8, 12, 16};

static int mt7628_set_drv_strength(void __iomem *base, u32 val, u32 bit,
				   const u32 tbl[], u32 reg_lo, u32 reg_hi)
{
	int i;

	for (i = 0; i < 4; i++)
		if (tbl[i] == val)
			break;

	if (i >= 4)
		return -EINVAL;

	clrsetbits_32(base + reg_lo, BIT(bit), (i & 1) << bit);
	clrsetbits_32(base + reg_hi, BIT(bit), ((i >> 1) & 1) << bit);

	return 0;
}

static int mt7628_get_pins_count(struct udevice *dev)
{
	return ARRAY_SIZE(mt7628_pins);
}

static const char *mt7628_get_pin_name(struct udevice *dev,
				       unsigned int selector)
{
	return mt7628_pins[selector];
}

static int mt7628_pinconf_set(struct udevice *dev, unsigned int pin_selector,
			      unsigned int param, unsigned int argument)
{
	struct mt7628_pinctrl_priv *priv = dev_get_priv(dev);
	u32 offs, bit;
	int ret = 0;

	offs = (pin_selector / 32) * 4;
	bit = pin_selector % 32;

	switch (param) {
	case PIN_CONFIG_BIAS_DISABLE:
		clrbits_32(priv->pcbase + offs + PAD_PU_G0_REG, BIT(bit));
		clrbits_32(priv->pcbase + offs + PAD_PD_G0_REG, BIT(bit));
		break;
	case PIN_CONFIG_BIAS_PULL_UP:
		setbits_32(priv->pcbase + offs + PAD_PU_G0_REG, BIT(bit));
		clrbits_32(priv->pcbase + offs + PAD_PD_G0_REG, BIT(bit));
		break;
	case PIN_CONFIG_BIAS_PULL_DOWN:
		clrbits_32(priv->pcbase + offs + PAD_PU_G0_REG, BIT(bit));
		setbits_32(priv->pcbase + offs + PAD_PD_G0_REG, BIT(bit));
		break;
	case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
		clrsetbits_32(priv->pcbase + offs + PAD_SMT_G0_REG,
			      BIT(bit), (!!argument) << bit);
		break;
	case PIN_CONFIG_DRIVE_STRENGTH_28:
		ret = mt7628_set_drv_strength(priv->pcbase + offs, argument,
					      bit, mt7628_drv_strength_28_tbl,
					      PAD_E2_G0_REG, PAD_E4_G0_REG);
		break;
	case PIN_CONFIG_DRIVE_STRENGTH_4G:
		ret = mt7628_set_drv_strength(priv->pcbase + offs, argument,
					      bit, mt7628_drv_strength_4g_tbl,
					      PAD_E4_G0_REG, PAD_E8_G0_REG);
		break;
	case PIN_CONFIG_SLEW_RATE:
		clrsetbits_32(priv->pcbase + offs + PAD_SR_G0_REG,
			      BIT(bit), (!!argument) << bit);
		break;
	default:
		ret = -EINVAL;
	}

	return ret;
}
#endif

static int mt7628_pinctrl_probe(struct udevice *dev)
{
	struct mt7628_pinctrl_priv *priv = dev_get_priv(dev);
	int ret = 0;

#if CONFIG_IS_ENABLED(PINMUX)
	ret = mtmips_pinctrl_probe(&priv->mp, ARRAY_SIZE(mt7628_pinmux_data),
				   mt7628_pinmux_data);
#endif /* CONFIG_IS_ENABLED(PINMUX) */

	return ret;
}

static int mt7628_pinctrl_of_to_plat(struct udevice *dev)
{
	struct mt7628_pinctrl_priv *priv = dev_get_priv(dev);

	priv->mp.base = (void __iomem *)dev_remap_addr_index(dev, 0);

	if (!priv->mp.base)
		return -EINVAL;

	priv->pcbase = (void __iomem *)dev_remap_addr_index(dev, 1);

	if (!priv->pcbase)
		return -EINVAL;

	return 0;
}

static const struct pinctrl_ops mt7628_pinctrl_ops = {
#if CONFIG_IS_ENABLED(PINMUX)
	.get_groups_count = mt7628_get_groups_count,
	.get_group_name = mt7628_get_group_name,
	.get_functions_count = mtmips_get_functions_count,
	.get_function_name = mtmips_get_function_name,
	.pinmux_group_set = mtmips_pinmux_group_set,
#endif /* CONFIG_IS_ENABLED(PINMUX) */
#if CONFIG_IS_ENABLED(PINCONF)
	.pinconf_num_params = ARRAY_SIZE(mt7628_conf_params),
	.pinconf_params = mt7628_conf_params,
	.get_pins_count = mt7628_get_pins_count,
	.get_pin_name = mt7628_get_pin_name,
	.pinconf_set = mt7628_pinconf_set,
#endif /* CONFIG_IS_ENABLED(PINCONF) */
	.set_state = pinctrl_generic_set_state,
};

static const struct udevice_id mt7628_pinctrl_ids[] = {
	{ .compatible = "mediatek,mt7628-pinctrl" },
	{ }
};

U_BOOT_DRIVER(mt7628_pinctrl) = {
	.name = "mt7628-pinctrl",
	.id = UCLASS_PINCTRL,
	.of_match = mt7628_pinctrl_ids,
	.of_to_plat = mt7628_pinctrl_of_to_plat,
	.ops = &mt7628_pinctrl_ops,
	.probe = mt7628_pinctrl_probe,
	.priv_auto	= sizeof(struct mt7628_pinctrl_priv),
};
Commit	Line	Data
3fad441c WG	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Copyright (C) 2019 MediaTek Inc. All Rights Reserved.
	4	*
	5	* Author: Weijie Gao <[email protected]>
	6	*/
	7
	8	#include <common.h>
	9	#include <dm.h>
	10	#include <dm/pinctrl.h>
	11	#include <linux/bitops.h>
	12	#include <linux/io.h>
	13
	14	#include "pinctrl-mtmips-common.h"
	15
	16	DECLARE_GLOBAL_DATA_PTR;
	17
	18	#define AGPIO_OFS 0
	19	#define GPIOMODE1_OFS 0x24
	20	#define GPIOMODE2_OFS 0x28
	21
	22	#define EPHY4_1_PAD_SHIFT 17
	23	#define EPHY4_1_PAD_MASK 0x0f
	24	#define EPHY0_SHIFT 16
	25	#define RF_OLT_MODE_SHIFT 12
	26	#define N9_EINT_SRC_SHIFT 9
	27	#define WLED_OD_SHIFT 8
	28	#define REF_CLKO_PAD_SHIFT 4
	29	#define I2S_CLK_PAD_SHIFT 3
	30	#define I2S_WS_PAD_SHIFT 2
	31	#define I2S_SDO_PAD_SHIFT 1
	32	#define I2S_SDI_PAD_SHIFT 0
	33
	34	#define GM4_MASK 3
	35
	36	#define P4LED_K_SHIFT 26
	37	#define P3LED_K_SHIFT 24
	38	#define P2LED_K_SHIFT 22
	39	#define P1LED_K_SHIFT 20
	40	#define P0LED_K_SHIFT 18
	41	#define WLED_K_SHIFT 16
	42	#define P4LED_A_SHIFT 10
	43	#define P3LED_A_SHIFT 8
	44	#define P2LED_A_SHIFT 6
	45	#define P1LED_A_SHIFT 4
	46	#define P0LED_A_SHIFT 2
	47	#define WLED_A_SHIFT 0
	48
	49	#define PWM1_SHIFT 30
	50	#define PWM0_SHIFT 28
	51	#define UART2_SHIFT 26
	52	#define UART1_SHIFT 24
	53	#define I2C_SHIFT 20
	54	#define REFCLK_SHIFT 18
	55	#define PERST_SHIFT 16
	56	#define ESD_SHIFT 15
	57	#define WDT_SHIFT 14
	58	#define SPI_SHIFT 12
	59	#define SDMODE_SHIFT 10
	60	#define UART0_SHIFT 8
	61	#define I2S_SHIFT 6
	62	#define SPI_CS1_SHIFT 4
	63	#define SPIS_SHIFT 2
	64	#define GPIO0_SHIFT 0
65
66	#define PAD_PU_G0_REG 0x00
67	#define PAD_PU_G1_REG 0x04
68	#define PAD_PD_G0_REG 0x10
69	#define PAD_PD_G1_REG 0x14
70	#define PAD_SR_G0_REG 0x20
71	#define PAD_SR_G1_REG 0x24
72	#define PAD_SMT_G0_REG 0x30
73	#define PAD_SMT_G1_REG 0x34
74	#define PAD_E2_G0_REG 0x40
75	#define PAD_E2_G1_REG 0x44
76	#define PAD_E4_G0_REG 0x50
77	#define PAD_E4_G1_REG 0x54
78	#define PAD_E8_G0_REG 0x60
79	#define PAD_E8_G1_REG 0x64
80
81	#define PIN_CONFIG_DRIVE_STRENGTH_28 (PIN_CONFIG_END + 1)
82	#define PIN_CONFIG_DRIVE_STRENGTH_4G (PIN_CONFIG_END + 2)
83
84	struct mt7628_pinctrl_priv {
85	struct mtmips_pinctrl_priv mp;
86
87	void __iomem *pcbase;
88	};
89
90	#if CONFIG_IS_ENABLED(PINMUX)
91	static const struct mtmips_pmx_func ephy4_1_pad_grp[] = {
92	FUNC("digital", 0xf),
93	FUNC("analog", 0),
94	};
95
96	static const struct mtmips_pmx_func ephy0_grp[] = {
97	FUNC("disable", 1),
98	FUNC("enable", 0),
99	};
100
101	static const struct mtmips_pmx_func rf_olt_grp[] = {
102	FUNC("enable", 1),
103	FUNC("disable", 0),
104	};
105
106	static const struct mtmips_pmx_func n9_eint_src_grp[] = {
107	FUNC("gpio", 1),
108	FUNC("utif", 0),
109	};
110
111	static const struct mtmips_pmx_func wlen_od_grp[] = {
112	FUNC("enable", 1),
113	FUNC("disable", 0),
114	};
115
116	static const struct mtmips_pmx_func ref_clko_grp[] = {
117	FUNC("digital", 1),
118	FUNC("analog", 0),
119	};
120
121	static const struct mtmips_pmx_func i2s_clk_grp[] = {
122	FUNC("digital", 1),
123	FUNC("analog", 0),
124	};
125
126	static const struct mtmips_pmx_func i2s_ws_grp[] = {
127	FUNC("digital", 1),
128	FUNC("analog", 0),
129	};
130
131	static const struct mtmips_pmx_func i2s_sdo_grp[] = {
132	FUNC("digital", 1),
133	FUNC("analog", 0),
134	};
135
136	static const struct mtmips_pmx_func i2s_sdi_grp[] = {
137	FUNC("digital", 1),
138	FUNC("analog", 0),
139	};
140
141	static const struct mtmips_pmx_func pwm1_grp[] = {
142	FUNC("sdxc d6", 3),
143	FUNC("utif", 2),
144	FUNC("gpio", 1),
145	FUNC("pwm1", 0),
146	};
147
148	static const struct mtmips_pmx_func pwm0_grp[] = {
149	FUNC("sdxc d7", 3),
150	FUNC("utif", 2),
151	FUNC("gpio", 1),
152	FUNC("pwm0", 0),
153	};
154
155	static const struct mtmips_pmx_func uart2_grp[] = {
156	FUNC("sdxc d5 d4", 3),
157	FUNC("pwm", 2),
158	FUNC("gpio", 1),
159	FUNC("uart2", 0),
160	};
161
162	static const struct mtmips_pmx_func uart1_grp[] = {
163	FUNC("sw_r", 3),
164	FUNC("pwm", 2),
165	FUNC("gpio", 1),
166	FUNC("uart1", 0),
167	};
168
169	static const struct mtmips_pmx_func i2c_grp[] = {
170	FUNC("-", 3),
171	FUNC("debug", 2),
172	FUNC("gpio", 1),
173	FUNC("i2c", 0),
174	};
175
176	static const struct mtmips_pmx_func refclk_grp[] = {
177	FUNC("gpio", 1),
178	FUNC("refclk", 0),
179	};
180
181	static const struct mtmips_pmx_func perst_grp[] = {
182	FUNC("gpio", 1),
183	FUNC("perst", 0),
184	};
185
186	static const struct mtmips_pmx_func esd_grp[] = {
187	FUNC("router", 1),
188	FUNC("iot", 0),
189	};
190
191	static const struct mtmips_pmx_func wdt_grp[] = {
192	FUNC("gpio", 1),
193	FUNC("wdt", 0),
194	};
195
196	static const struct mtmips_pmx_func spi_grp[] = {
197	FUNC("gpio", 1),
198	FUNC("spi", 0),
199	};
200
201	static const struct mtmips_pmx_func sd_mode_grp[] = {
202	FUNC("n9 jtag", 3),
203	FUNC("utif1", 2),
204	FUNC("gpio", 1),
205	FUNC("sdxc", 0),
206	};
207
208	static const struct mtmips_pmx_func uart0_grp[] = {
209	FUNC("-", 3),
210	FUNC("-", 2),
211	FUNC("gpio", 1),
212	FUNC("uart0", 0),
213	};
214
215	static const struct mtmips_pmx_func i2s_grp[] = {
216	FUNC("antenna", 3),
217	FUNC("pcm", 2),
218	FUNC("gpio", 1),
219	FUNC("i2s", 0),
220	};
221
222	static const struct mtmips_pmx_func spi_cs1_grp[] = {
223	FUNC("-", 3),
224	FUNC("refclk", 2),
225	FUNC("gpio", 1),
226	FUNC("spi cs1", 0),
227	};
228
229	static const struct mtmips_pmx_func spis_grp[] = {
230	FUNC("pwm_uart2", 3),
231	FUNC("utif", 2),
232	FUNC("gpio", 1),
233	FUNC("spis", 0),
234	};
235
236	static const struct mtmips_pmx_func gpio0_grp[] = {
237	FUNC("perst", 3),
238	FUNC("refclk", 2),
239	FUNC("gpio", 1),
240	FUNC("gpio0", 0),
241	};
242
243	static const struct mtmips_pmx_func wled_a_grp[] = {
244	FUNC("-", 3),
245	FUNC("-", 2),
246	FUNC("gpio", 1),
247	FUNC("led", 0),
248	};
249
250	static const struct mtmips_pmx_func p0led_a_grp[] = {
251	FUNC("jtag", 3),
252	FUNC("rsvd", 2),
253	FUNC("gpio", 1),
254	FUNC("led", 0),
255	};
256
257	static const struct mtmips_pmx_func p1led_a_grp[] = {
258	FUNC("jtag", 3),
259	FUNC("utif", 2),
260	FUNC("gpio", 1),
261	FUNC("led", 0),
262	};
263
264	static const struct mtmips_pmx_func p2led_a_grp[] = {
265	FUNC("jtag", 3),
266	FUNC("utif", 2),
267	FUNC("gpio", 1),
268	FUNC("led", 0),
269	};
270
271	static const struct mtmips_pmx_func p3led_a_grp[] = {
272	FUNC("jtag", 3),
273	FUNC("utif", 2),
274	FUNC("gpio", 1),
275	FUNC("led", 0),
276	};
277
278	static const struct mtmips_pmx_func p4led_a_grp[] = {
279	FUNC("jtag", 3),
280	FUNC("utif", 2),
281	FUNC("gpio", 1),
282	FUNC("led", 0),
283	};
284
285	static const struct mtmips_pmx_func wled_k_grp[] = {
286	FUNC("-", 3),
287	FUNC("-", 2),
288	FUNC("gpio", 1),
289	FUNC("led", 0),
290	};
291
292	static const struct mtmips_pmx_func p0led_k_grp[] = {
293	FUNC("jtag", 3),
294	FUNC("rsvd", 2),
295	FUNC("gpio", 1),
296	FUNC("led", 0),
297	};
298
299	static const struct mtmips_pmx_func p1led_k_grp[] = {
300	FUNC("jtag", 3),
301	FUNC("utif", 2),
302	FUNC("gpio", 1),
303	FUNC("led", 0),
304	};
305
306	static const struct mtmips_pmx_func p2led_k_grp[] = {
307	FUNC("jtag", 3),
308	FUNC("utif", 2),
309	FUNC("gpio", 1),
310	FUNC("led", 0),
311	};
312
313	static const struct mtmips_pmx_func p3led_k_grp[] = {
314	FUNC("jtag", 3),
315	FUNC("utif", 2),
316	FUNC("gpio", 1),
317	FUNC("led", 0),
318	};
319
320	static const struct mtmips_pmx_func p4led_k_grp[] = {
321	FUNC("jtag", 3),
322	FUNC("utif", 2),
323	FUNC("gpio", 1),
324	FUNC("led", 0),
325	};
326
327	static const struct mtmips_pmx_group mt7628_pinmux_data[] = {
328	GRP("ephy4_1_pad", ephy4_1_pad_grp, AGPIO_OFS, EPHY4_1_PAD_SHIFT,
329	EPHY4_1_PAD_MASK),
330	GRP("ephy0", ephy0_grp, AGPIO_OFS, EPHY0_SHIFT, 1),
331	GRP("rf_olt", rf_olt_grp, AGPIO_OFS, RF_OLT_MODE_SHIFT, 1),
332	GRP("n9_eint_src", n9_eint_src_grp, AGPIO_OFS, N9_EINT_SRC_SHIFT, 1),
333	GRP("wlen_od", wlen_od_grp, AGPIO_OFS, WLED_OD_SHIFT, 1),
334	GRP("ref_clko_pad", ref_clko_grp, AGPIO_OFS, REF_CLKO_PAD_SHIFT, 1),
335	GRP("i2s_clk_pad", i2s_clk_grp, AGPIO_OFS, I2S_CLK_PAD_SHIFT, 1),
336	GRP("i2s_ws_pad", i2s_ws_grp, AGPIO_OFS, I2S_WS_PAD_SHIFT, 1),
337	GRP("i2s_sdo_pad", i2s_sdo_grp, AGPIO_OFS, I2S_SDO_PAD_SHIFT, 1),
338	GRP("i2s_sdi_pad", i2s_sdi_grp, AGPIO_OFS, I2S_SDI_PAD_SHIFT, 1),
339	GRP("pwm1", pwm1_grp, GPIOMODE1_OFS, PWM1_SHIFT, GM4_MASK),
340	GRP("pwm0", pwm0_grp, GPIOMODE1_OFS, PWM0_SHIFT, GM4_MASK),
341	GRP("uart2", uart2_grp, GPIOMODE1_OFS, UART2_SHIFT, GM4_MASK),
342	GRP("uart1", uart1_grp, GPIOMODE1_OFS, UART1_SHIFT, GM4_MASK),
343	GRP("i2c", i2c_grp, GPIOMODE1_OFS, I2C_SHIFT, GM4_MASK),
344	GRP("refclk", refclk_grp, GPIOMODE1_OFS, REFCLK_SHIFT, 1),
345	GRP("perst", perst_grp, GPIOMODE1_OFS, PERST_SHIFT, 1),
346	GRP("sd router", esd_grp, GPIOMODE1_OFS, ESD_SHIFT, 1),
347	GRP("wdt", wdt_grp, GPIOMODE1_OFS, WDT_SHIFT, 1),
348	GRP("spi", spi_grp, GPIOMODE1_OFS, SPI_SHIFT, 1),
349	GRP("sdmode", sd_mode_grp, GPIOMODE1_OFS, SDMODE_SHIFT, GM4_MASK),
350	GRP("uart0", uart0_grp, GPIOMODE1_OFS, UART0_SHIFT, GM4_MASK),
351	GRP("i2s", i2s_grp, GPIOMODE1_OFS, I2S_SHIFT, GM4_MASK),
352	GRP("spi cs1", spi_cs1_grp, GPIOMODE1_OFS, SPI_CS1_SHIFT, GM4_MASK),
353	GRP("spis", spis_grp, GPIOMODE1_OFS, SPIS_SHIFT, GM4_MASK),
354	GRP("gpio0", gpio0_grp, GPIOMODE1_OFS, GPIO0_SHIFT, GM4_MASK),
355	GRP("wled_a", wled_a_grp, GPIOMODE2_OFS, WLED_A_SHIFT, GM4_MASK),
356	GRP("p0led_a", p0led_a_grp, GPIOMODE2_OFS, P0LED_A_SHIFT, GM4_MASK),
357	GRP("p1led_a", p1led_a_grp, GPIOMODE2_OFS, P1LED_A_SHIFT, GM4_MASK),
358	GRP("p2led_a", p2led_a_grp, GPIOMODE2_OFS, P2LED_A_SHIFT, GM4_MASK),
359	GRP("p3led_a", p3led_a_grp, GPIOMODE2_OFS, P3LED_A_SHIFT, GM4_MASK),
360	GRP("p4led_a", p4led_a_grp, GPIOMODE2_OFS, P4LED_A_SHIFT, GM4_MASK),
361	GRP("wled_k", wled_k_grp, GPIOMODE2_OFS, WLED_K_SHIFT, GM4_MASK),
362	GRP("p0led_k", p0led_k_grp, GPIOMODE2_OFS, P0LED_K_SHIFT, GM4_MASK),
363	GRP("p1led_k", p1led_k_grp, GPIOMODE2_OFS, P1LED_K_SHIFT, GM4_MASK),
364	GRP("p2led_k", p2led_k_grp, GPIOMODE2_OFS, P2LED_K_SHIFT, GM4_MASK),
365	GRP("p3led_k", p3led_k_grp, GPIOMODE2_OFS, P3LED_K_SHIFT, GM4_MASK),
366	GRP("p4led_k", p4led_k_grp, GPIOMODE2_OFS, P4LED_K_SHIFT, GM4_MASK),
367	};
368
369	static int mt7628_get_groups_count(struct udevice *dev)
370	{
371	return ARRAY_SIZE(mt7628_pinmux_data);
372	}
373
374	static const char mt7628_get_group_name(struct udevice dev,
375	unsigned int selector)
376	{
377	return mt7628_pinmux_data[selector].name;
378	}
379	#endif /* CONFIG_IS_ENABLED(PINMUX) */
380
381	#if CONFIG_IS_ENABLED(PINCONF)
382	static const struct pinconf_param mt7628_conf_params[] = {
383	{ "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
384	{ "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
385	{ "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
386	{ "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 },
387	{ "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 },
388	{ "drive-strength-28", PIN_CONFIG_DRIVE_STRENGTH_28, 0 },
389	{ "drive-strength-4g", PIN_CONFIG_DRIVE_STRENGTH_4G, 0 },
390	{ "slew-rate", PIN_CONFIG_SLEW_RATE, 0 },
391	};
392
393	static const char *const mt7628_pins[] = {
394	"i2s_sdi",
395	"i2s_sdo",
396	"i2s_ws",
397	"i2s_clk",
398	"i2s_sclk",
399	"i2c_sd",
400	"spi_cs1",
401	"spi_clk",
402	"spi_mosi",
403	"spi_miso",
404	"spi_cs0",
405	"gpio0",
406	"uart0_txd",
407	"uart0_rxd",
408	"spis_cs",
409	"spis_clk",
410	"spis_miso",
411	"spis_mosi",
412	"pwm_ch0",
413	"pwm_ch1",
414	"uart2_txd",
415	"uart2_rxd",
416	"sd_wp",
417	"sd_cd",
418	"sd_d1",
419	"sd_d0",
420	"sd_clk",
421	"sd_cmd",
422	"sd_d3",
423	"sd_d2",
424	"ephy_led4_k",
425	"ephy_led3_k",
426	"ephy_led2_k",
427	"ephy_led1_k",
428	"ephy_led0_k",
429	"wled_k",
430	"perst_n",
431	"co_clko",
432	"wdt",
433	"ephy_led4_a",
434	"ephy_led3_a",
435	"ephy_led2_a",
436	"ephy_led1_a",
437	"ephy_led0_a",
438	"wled_a",
439	"uart1_txd",
440	"uart1_rxd",
441	};
442
443	static const u32 mt7628_drv_strength_28_tbl[] = {2, 4, 6, 8};
444	static const u32 mt7628_drv_strength_4g_tbl[] = {4, 8, 12, 16};
445
446	static int mt7628_set_drv_strength(void __iomem *base, u32 val, u32 bit,
447	const u32 tbl[], u32 reg_lo, u32 reg_hi)
448	{
449	int i;
450
451	for (i = 0; i < 4; i++)
452	if (tbl[i] == val)
453	break;
454
455	if (i >= 4)
456	return -EINVAL;
457
458	clrsetbits_32(base + reg_lo, BIT(bit), (i & 1) << bit);
459	clrsetbits_32(base + reg_hi, BIT(bit), ((i >> 1) & 1) << bit);
460
461	return 0;
462	}
463
464	static int mt7628_get_pins_count(struct udevice *dev)
465	{
466	return ARRAY_SIZE(mt7628_pins);
467	}
468
469	static const char mt7628_get_pin_name(struct udevice dev,
470	unsigned int selector)
471	{
472	return mt7628_pins[selector];
473	}
474
475	static int mt7628_pinconf_set(struct udevice *dev, unsigned int pin_selector,
476	unsigned int param, unsigned int argument)
477	{
478	struct mt7628_pinctrl_priv *priv = dev_get_priv(dev);
479	u32 offs, bit;
480	int ret = 0;
481
482	offs = (pin_selector / 32) * 4;
483	bit = pin_selector % 32;
484
485	switch (param) {
486	case PIN_CONFIG_BIAS_DISABLE:
487	clrbits_32(priv->pcbase + offs + PAD_PU_G0_REG, BIT(bit));
488	clrbits_32(priv->pcbase + offs + PAD_PD_G0_REG, BIT(bit));
489	break;
490	case PIN_CONFIG_BIAS_PULL_UP:
491	setbits_32(priv->pcbase + offs + PAD_PU_G0_REG, BIT(bit));
492	clrbits_32(priv->pcbase + offs + PAD_PD_G0_REG, BIT(bit));
493	break;
494	case PIN_CONFIG_BIAS_PULL_DOWN:
495	clrbits_32(priv->pcbase + offs + PAD_PU_G0_REG, BIT(bit));
496	setbits_32(priv->pcbase + offs + PAD_PD_G0_REG, BIT(bit));
497	break;
498	case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
499	clrsetbits_32(priv->pcbase + offs + PAD_SMT_G0_REG,
500	BIT(bit), (!!argument) << bit);
501	break;
502	case PIN_CONFIG_DRIVE_STRENGTH_28:
503	ret = mt7628_set_drv_strength(priv->pcbase + offs, argument,
504	bit, mt7628_drv_strength_28_tbl,
505	PAD_E2_G0_REG, PAD_E4_G0_REG);
506	break;
507	case PIN_CONFIG_DRIVE_STRENGTH_4G:
508	ret = mt7628_set_drv_strength(priv->pcbase + offs, argument,
509	bit, mt7628_drv_strength_4g_tbl,
510	PAD_E4_G0_REG, PAD_E8_G0_REG);
511	break;
512	case PIN_CONFIG_SLEW_RATE:
513	clrsetbits_32(priv->pcbase + offs + PAD_SR_G0_REG,
514	BIT(bit), (!!argument) << bit);
515	break;
516	default:
517	ret = -EINVAL;
518	}
519
520	return ret;
521	}
522	#endif
523
524	static int mt7628_pinctrl_probe(struct udevice *dev)
525	{
526	struct mt7628_pinctrl_priv *priv = dev_get_priv(dev);
527	int ret = 0;
528
529	#if CONFIG_IS_ENABLED(PINMUX)
530	ret = mtmips_pinctrl_probe(&priv->mp, ARRAY_SIZE(mt7628_pinmux_data),
531	mt7628_pinmux_data);
532	#endif /* CONFIG_IS_ENABLED(PINMUX) */
533
534	return ret;
535	}
536
d1998a9f	537	static int mt7628_pinctrl_of_to_plat(struct udevice *dev)
3fad441c WG	538	{
	539	struct mt7628_pinctrl_priv *priv = dev_get_priv(dev);
	540
	541	priv->mp.base = (void __iomem *)dev_remap_addr_index(dev, 0);
	542
	543	if (!priv->mp.base)
	544	return -EINVAL;
	545
	546	priv->pcbase = (void __iomem *)dev_remap_addr_index(dev, 1);
	547
	548	if (!priv->pcbase)
	549	return -EINVAL;
	550
	551	return 0;
	552	}
	553
	554	static const struct pinctrl_ops mt7628_pinctrl_ops = {
	555	#if CONFIG_IS_ENABLED(PINMUX)
	556	.get_groups_count = mt7628_get_groups_count,
	557	.get_group_name = mt7628_get_group_name,
	558	.get_functions_count = mtmips_get_functions_count,
	559	.get_function_name = mtmips_get_function_name,
	560	.pinmux_group_set = mtmips_pinmux_group_set,
	561	#endif /* CONFIG_IS_ENABLED(PINMUX) */
	562	#if CONFIG_IS_ENABLED(PINCONF)
	563	.pinconf_num_params = ARRAY_SIZE(mt7628_conf_params),
	564	.pinconf_params = mt7628_conf_params,
	565	.get_pins_count = mt7628_get_pins_count,
	566	.get_pin_name = mt7628_get_pin_name,
	567	.pinconf_set = mt7628_pinconf_set,
	568	#endif /* CONFIG_IS_ENABLED(PINCONF) */
	569	.set_state = pinctrl_generic_set_state,
	570	};
	571
	572	static const struct udevice_id mt7628_pinctrl_ids[] = {
	573	{ .compatible = "mediatek,mt7628-pinctrl" },
	574	{ }
	575	};
	576
	577	U_BOOT_DRIVER(mt7628_pinctrl) = {
	578	.name = "mt7628-pinctrl",
	579	.id = UCLASS_PINCTRL,
	580	.of_match = mt7628_pinctrl_ids,
d1998a9f	581	.of_to_plat = mt7628_pinctrl_of_to_plat,
3fad441c WG	582	.ops = &mt7628_pinctrl_ops,
3fad441c WG	583	.probe = mt7628_pinctrl_probe,
41575d8e	584	.priv_auto = sizeof(struct mt7628_pinctrl_priv),
3fad441c	585	};