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[qemu.git] / target / i386 / kvm.c
CommitLineData
05330448
AL		 1/*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <[email protected]>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
b6a0aa05 15#include "qemu/osdep.h"
da34e65c 16#include "qapi/error.h"
05330448 17#include <sys/ioctl.h>
25d2e361 18#include <sys/utsname.h>
05330448
AL		 19
20#include <linux/kvm.h>
1814eab6 21#include "standard-headers/asm-x86/kvm_para.h"
05330448 22
33c11879 23#include "cpu.h"
9c17d615 24#include "sysemu/sysemu.h"
b3946626 25#include "sysemu/hw_accel.h"
6410848b 26#include "sysemu/kvm_int.h"
71e8a915 27#include "sysemu/reset.h"
1d31f66b 28#include "kvm_i386.h"
50efe82c 29#include "hyperv.h"
5e953812 30#include "hyperv-proto.h"
50efe82c 31
022c62cb 32#include "exec/gdbstub.h"
1de7afc9 33#include "qemu/host-utils.h"
db725815 34#include "qemu/main-loop.h"
1de7afc9 35#include "qemu/config-file.h"
1c4a55db 36#include "qemu/error-report.h"
0d09e41a
PB		 37#include "hw/i386/pc.h"
38#include "hw/i386/apic.h"
e0723c45
PB		 39#include "hw/i386/apic_internal.h"
40#include "hw/i386/apic-msidef.h"
8b5ed7df 41#include "hw/i386/intel_iommu.h"
e1d4fb2d 42#include "hw/i386/x86-iommu.h"
50efe82c 43
a2cb15b0 44#include "hw/pci/pci.h"
15eafc2e 45#include "hw/pci/msi.h"
fd563564 46#include "hw/pci/msix.h"
795c40b8 47#include "migration/blocker.h"
4c663752 48#include "exec/memattrs.h"
8b5ed7df 49#include "trace.h"
05330448
AL		 50
51//#define DEBUG_KVM
52
53#ifdef DEBUG_KVM
8c0d577e 54#define DPRINTF(fmt, ...) \
05330448
AL		 55 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
56#else
8c0d577e 57#define DPRINTF(fmt, ...) \
05330448
AL		 58 do { } while (0)
59#endif
60
1a03675d
GC		 61#define MSR_KVM_WALL_CLOCK 0x11
62#define MSR_KVM_SYSTEM_TIME 0x12
63
d1138251
EH		 64/* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
65 * 255 kvm_msr_entry structs */
66#define MSR_BUF_SIZE 4096
d71b62a1 67
94a8d39a
JK		 68const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
69 KVM_CAP_INFO(SET_TSS_ADDR),
70 KVM_CAP_INFO(EXT_CPUID),
71 KVM_CAP_INFO(MP_STATE),
72 KVM_CAP_LAST_INFO
73};
25d2e361 74
c3a3a7d3
JK		 75static bool has_msr_star;
76static bool has_msr_hsave_pa;
c9b8f6b6 77static bool has_msr_tsc_aux;
f28558d3 78static bool has_msr_tsc_adjust;
aa82ba54 79static bool has_msr_tsc_deadline;
df67696e 80static bool has_msr_feature_control;
21e87c46 81static bool has_msr_misc_enable;
fc12d72e 82static bool has_msr_smbase;
79e9ebeb 83static bool has_msr_bndcfgs;
25d2e361 84static int lm_capable_kernel;
7bc3d711 85static bool has_msr_hv_hypercall;
f2a53c9e 86static bool has_msr_hv_crash;
744b8a94 87static bool has_msr_hv_reset;
8c145d7c 88static bool has_msr_hv_vpindex;
e9688fab 89static bool hv_vpindex_settable;
46eb8f98 90static bool has_msr_hv_runtime;
866eea9a 91static bool has_msr_hv_synic;
ff99aa64 92static bool has_msr_hv_stimer;
d72bc7f6 93static bool has_msr_hv_frequencies;
ba6a4fd9 94static bool has_msr_hv_reenlightenment;
18cd2c17 95static bool has_msr_xss;
a33a2cfe 96static bool has_msr_spec_ctrl;
cfeea0c0 97static bool has_msr_virt_ssbd;
e13713db 98static bool has_msr_smi_count;
aec5e9c3 99static bool has_msr_arch_capabs;
597360c0 100static bool has_msr_core_capabs;
b827df58 101
0b368a10
JD		 102static uint32_t has_architectural_pmu_version;
103static uint32_t num_architectural_pmu_gp_counters;
104static uint32_t num_architectural_pmu_fixed_counters;
0d894367 105
28143b40
TH		 106static int has_xsave;
107static int has_xcrs;
108static int has_pit_state2;
fd13f23b 109static int has_exception_payload;
28143b40 110
87f8b626
AR		 111static bool has_msr_mcg_ext_ctl;
112
494e95e9 113static struct kvm_cpuid2 *cpuid_cache;
f57bceb6 114static struct kvm_msr_list *kvm_feature_msrs;
494e95e9 115
28143b40
TH		 116int kvm_has_pit_state2(void)
117{
118 return has_pit_state2;
119}
120
355023f2
PB		 121bool kvm_has_smm(void)
122{
123 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
124}
125
6053a86f
MT		 126bool kvm_has_adjust_clock_stable(void)
127{
128 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
129
130 return (ret == KVM_CLOCK_TSC_STABLE);
131}
132
79a197ab
LA		 133bool kvm_has_exception_payload(void)
134{
135 return has_exception_payload;
136}
137
1d31f66b
PM		 138bool kvm_allows_irq0_override(void)
139{
140 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
141}
142
fb506e70
RK		 143static bool kvm_x2apic_api_set_flags(uint64_t flags)
144{
145 KVMState *s = KVM_STATE(current_machine->accelerator);
146
147 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
148}
149
e391c009 150#define MEMORIZE(fn, _result) \
2a138ec3 151 ({ \
2a138ec3
RK		 152 static bool _memorized; \
153 \
154 if (_memorized) { \
155 return _result; \
156 } \
157 _memorized = true; \
158 _result = fn; \
159 })
160
e391c009
IM		 161static bool has_x2apic_api;
162
163bool kvm_has_x2apic_api(void)
164{
165 return has_x2apic_api;
166}
167
fb506e70
RK		 168bool kvm_enable_x2apic(void)
169{
2a138ec3
RK		 170 return MEMORIZE(
171 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
e391c009
IM		 172 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
173 has_x2apic_api);
fb506e70
RK		 174}
175
e9688fab
RK		 176bool kvm_hv_vpindex_settable(void)
177{
178 return hv_vpindex_settable;
179}
180
0fd7e098
LL		 181static int kvm_get_tsc(CPUState *cs)
182{
183 X86CPU *cpu = X86_CPU(cs);
184 CPUX86State *env = &cpu->env;
185 struct {
186 struct kvm_msrs info;
187 struct kvm_msr_entry entries[1];
188 } msr_data;
189 int ret;
190
191 if (env->tsc_valid) {
192 return 0;
193 }
194
195 msr_data.info.nmsrs = 1;
196 msr_data.entries[0].index = MSR_IA32_TSC;
197 env->tsc_valid = !runstate_is_running();
198
199 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
200 if (ret < 0) {
201 return ret;
202 }
203
48e1a45c 204 assert(ret == 1);
0fd7e098
LL		 205 env->tsc = msr_data.entries[0].data;
206 return 0;
207}
208
14e6fe12 209static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
0fd7e098 210{
0fd7e098
LL		 211 kvm_get_tsc(cpu);
212}
213
214void kvm_synchronize_all_tsc(void)
215{
216 CPUState *cpu;
217
218 if (kvm_enabled()) {
219 CPU_FOREACH(cpu) {
14e6fe12 220 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
0fd7e098
LL		 221 }
222 }
223}
224
b827df58
AK		 225static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
226{
227 struct kvm_cpuid2 *cpuid;
228 int r, size;
229
230 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
e42a92ae 231 cpuid = g_malloc0(size);
b827df58
AK		 232 cpuid->nent = max;
233 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
76ae317f
MM		 234 if (r == 0 && cpuid->nent >= max) {
235 r = -E2BIG;
236 }
b827df58
AK		 237 if (r < 0) {
238 if (r == -E2BIG) {
7267c094 239 g_free(cpuid);
b827df58
AK		 240 return NULL;
241 } else {
242 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
243 strerror(-r));
244 exit(1);
245 }
246 }
247 return cpuid;
248}
249
dd87f8a6
EH		 250/* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
251 * for all entries.
252 */
253static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
254{
255 struct kvm_cpuid2 *cpuid;
256 int max = 1;
494e95e9
CP		 257
258 if (cpuid_cache != NULL) {
259 return cpuid_cache;
260 }
dd87f8a6
EH		 261 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
262 max *= 2;
263 }
494e95e9 264 cpuid_cache = cpuid;
dd87f8a6
EH		 265 return cpuid;
266}
267
a443bc34 268static const struct kvm_para_features {
0c31b744
GC		 269 int cap;
270 int feature;
271} para_features[] = {
272 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
273 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
274 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
0c31b744 275 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
0c31b744
GC		 276};
277
ba9bc59e 278static int get_para_features(KVMState *s)
0c31b744
GC		 279{
280 int i, features = 0;
281
8e03c100 282 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
ba9bc59e 283 if (kvm_check_extension(s, para_features[i].cap)) {
0c31b744
GC		 284 features |= (1 << para_features[i].feature);
285 }
286 }
287
288 return features;
289}
0c31b744 290
40e80ee4
EH		 291static bool host_tsx_blacklisted(void)
292{
293 int family, model, stepping;\
294 char vendor[CPUID_VENDOR_SZ + 1];
295
296 host_vendor_fms(vendor, &family, &model, &stepping);
297
298 /* Check if we are running on a Haswell host known to have broken TSX */
299 return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
300 (family == 6) &&
301 ((model == 63 && stepping < 4) ||
302 model == 60 || model == 69 || model == 70);
303}
0c31b744 304
829ae2f9
EH		 305/* Returns the value for a specific register on the cpuid entry
306 */
307static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
308{
309 uint32_t ret = 0;
310 switch (reg) {
311 case R_EAX:
312 ret = entry->eax;
313 break;
314 case R_EBX:
315 ret = entry->ebx;
316 break;
317 case R_ECX:
318 ret = entry->ecx;
319 break;
320 case R_EDX:
321 ret = entry->edx;
322 break;
323 }
324 return ret;
325}
326
4fb73f1d
EH		 327/* Find matching entry for function/index on kvm_cpuid2 struct
328 */
329static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
330 uint32_t function,
331 uint32_t index)
332{
333 int i;
334 for (i = 0; i < cpuid->nent; ++i) {
335 if (cpuid->entries[i].function == function &&
336 cpuid->entries[i].index == index) {
337 return &cpuid->entries[i];
338 }
339 }
340 /* not found: */
341 return NULL;
342}
343
ba9bc59e 344uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
c958a8bd 345 uint32_t index, int reg)
b827df58
AK		 346{
347 struct kvm_cpuid2 *cpuid;
b827df58
AK		 348 uint32_t ret = 0;
349 uint32_t cpuid_1_edx;
8c723b79 350 bool found = false;
b827df58 351
dd87f8a6 352 cpuid = get_supported_cpuid(s);
b827df58 353
4fb73f1d
EH		 354 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
355 if (entry) {
356 found = true;
357 ret = cpuid_entry_get_reg(entry, reg);
b827df58
AK		 358 }
359
7b46e5ce
EH		 360 /* Fixups for the data returned by KVM, below */
361
c2acb022
EH		 362 if (function == 1 && reg == R_EDX) {
363 /* KVM before 2.6.30 misreports the following features */
364 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
84bd945c
EH		 365 } else if (function == 1 && reg == R_ECX) {
366 /* We can set the hypervisor flag, even if KVM does not return it on
367 * GET_SUPPORTED_CPUID
368 */
369 ret |= CPUID_EXT_HYPERVISOR;
ac67ee26
EH		 370 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
371 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
372 * and the irqchip is in the kernel.
373 */
374 if (kvm_irqchip_in_kernel() &&
375 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
376 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
377 }
41e5e76d
EH		 378
379 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
380 * without the in-kernel irqchip
381 */
382 if (!kvm_irqchip_in_kernel()) {
383 ret &= ~CPUID_EXT_X2APIC;
b827df58 384 }
2266d443
MT		 385
386 if (enable_cpu_pm) {
387 int disable_exits = kvm_check_extension(s,
388 KVM_CAP_X86_DISABLE_EXITS);
389
390 if (disable_exits & KVM_X86_DISABLE_EXITS_MWAIT) {
391 ret |= CPUID_EXT_MONITOR;
392 }
393 }
28b8e4d0
JK		 394 } else if (function == 6 && reg == R_EAX) {
395 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
40e80ee4
EH		 396 } else if (function == 7 && index == 0 && reg == R_EBX) {
397 if (host_tsx_blacklisted()) {
398 ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
399 }
485b1d25
EH		 400 } else if (function == 7 && index == 0 && reg == R_EDX) {
401 /*
402 * Linux v4.17-v4.20 incorrectly return ARCH_CAPABILITIES on SVM hosts.
403 * We can detect the bug by checking if MSR_IA32_ARCH_CAPABILITIES is
404 * returned by KVM_GET_MSR_INDEX_LIST.
405 */
406 if (!has_msr_arch_capabs) {
407 ret &= ~CPUID_7_0_EDX_ARCH_CAPABILITIES;
408 }
f98bbd83
BM		 409 } else if (function == 0x80000001 && reg == R_ECX) {
410 /*
411 * It's safe to enable TOPOEXT even if it's not returned by
412 * GET_SUPPORTED_CPUID. Unconditionally enabling TOPOEXT here allows
413 * us to keep CPU models including TOPOEXT runnable on older kernels.
414 */
415 ret |= CPUID_EXT3_TOPOEXT;
c2acb022
EH		 416 } else if (function == 0x80000001 && reg == R_EDX) {
417 /* On Intel, kvm returns cpuid according to the Intel spec,
418 * so add missing bits according to the AMD spec:
419 */
420 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
421 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
64877477
EH		 422 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
423 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
424 * be enabled without the in-kernel irqchip
425 */
426 if (!kvm_irqchip_in_kernel()) {
427 ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
428 }
be777326 429 } else if (function == KVM_CPUID_FEATURES && reg == R_EDX) {
2af1acad 430 ret |= 1U << KVM_HINTS_REALTIME;
be777326 431 found = 1;
b827df58
AK		 432 }
433
0c31b744 434 /* fallback for older kernels */
8c723b79 435 if ((function == KVM_CPUID_FEATURES) && !found) {
ba9bc59e 436 ret = get_para_features(s);
b9bec74b 437 }
0c31b744
GC		 438
439 return ret;
bb0300dc 440}
bb0300dc 441
f57bceb6
RH		 442uint32_t kvm_arch_get_supported_msr_feature(KVMState *s, uint32_t index)
443{
444 struct {
445 struct kvm_msrs info;
446 struct kvm_msr_entry entries[1];
447 } msr_data;
448 uint32_t ret;
449
450 if (kvm_feature_msrs == NULL) { /* Host doesn't support feature MSRs */
451 return 0;
452 }
453
454 /* Check if requested MSR is supported feature MSR */
455 int i;
456 for (i = 0; i < kvm_feature_msrs->nmsrs; i++)
457 if (kvm_feature_msrs->indices[i] == index) {
458 break;
459 }
460 if (i == kvm_feature_msrs->nmsrs) {
461 return 0; /* if the feature MSR is not supported, simply return 0 */
462 }
463
464 msr_data.info.nmsrs = 1;
465 msr_data.entries[0].index = index;
466
467 ret = kvm_ioctl(s, KVM_GET_MSRS, &msr_data);
468 if (ret != 1) {
469 error_report("KVM get MSR (index=0x%x) feature failed, %s",
470 index, strerror(-ret));
471 exit(1);
472 }
473
474 return msr_data.entries[0].data;
475}
476
477
3c85e74f
HY		 478typedef struct HWPoisonPage {
479 ram_addr_t ram_addr;
480 QLIST_ENTRY(HWPoisonPage) list;
481} HWPoisonPage;
482
483static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
484 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
485
486static void kvm_unpoison_all(void *param)
487{
488 HWPoisonPage *page, *next_page;
489
490 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
491 QLIST_REMOVE(page, list);
492 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
7267c094 493 g_free(page);
3c85e74f
HY		 494 }
495}
496
3c85e74f
HY		 497static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
498{
499 HWPoisonPage *page;
500
501 QLIST_FOREACH(page, &hwpoison_page_list, list) {
502 if (page->ram_addr == ram_addr) {
503 return;
504 }
505 }
ab3ad07f 506 page = g_new(HWPoisonPage, 1);
3c85e74f
HY		 507 page->ram_addr = ram_addr;
508 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
509}
510
e7701825
MT		 511static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
512 int *max_banks)
513{
514 int r;
515
14a09518 516 r = kvm_check_extension(s, KVM_CAP_MCE);
e7701825
MT		 517 if (r > 0) {
518 *max_banks = r;
519 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
520 }
521 return -ENOSYS;
522}
523
bee615d4 524static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
e7701825 525{
87f8b626 526 CPUState *cs = CPU(cpu);
bee615d4 527 CPUX86State *env = &cpu->env;
c34d440a
JK		 528 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
529 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
530 uint64_t mcg_status = MCG_STATUS_MCIP;
87f8b626 531 int flags = 0;
e7701825 532
c34d440a
JK		 533 if (code == BUS_MCEERR_AR) {
534 status |= MCI_STATUS_AR | 0x134;
535 mcg_status |= MCG_STATUS_EIPV;
536 } else {
537 status |= 0xc0;
538 mcg_status |= MCG_STATUS_RIPV;
419fb20a 539 }
87f8b626
AR		 540
541 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
542 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
543 * guest kernel back into env->mcg_ext_ctl.
544 */
545 cpu_synchronize_state(cs);
546 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
547 mcg_status |= MCG_STATUS_LMCE;
548 flags = 0;
549 }
550
8c5cf3b6 551 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
87f8b626 552 (MCM_ADDR_PHYS << 6) | 0xc, flags);
419fb20a 553}
419fb20a
JK		 554
555static void hardware_memory_error(void)
556{
557 fprintf(stderr, "Hardware memory error!\n");
558 exit(1);
559}
560
2ae41db2 561void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
419fb20a 562{
20d695a9
AF		 563 X86CPU *cpu = X86_CPU(c);
564 CPUX86State *env = &cpu->env;
419fb20a 565 ram_addr_t ram_addr;
a8170e5e 566 hwaddr paddr;
419fb20a 567
4d39892c
PB		 568 /* If we get an action required MCE, it has been injected by KVM
569 * while the VM was running. An action optional MCE instead should
570 * be coming from the main thread, which qemu_init_sigbus identifies
571 * as the "early kill" thread.
572 */
a16fc07e 573 assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
20e0ff59 574
20e0ff59 575 if ((env->mcg_cap & MCG_SER_P) && addr) {
07bdaa41 576 ram_addr = qemu_ram_addr_from_host(addr);
20e0ff59
PB		 577 if (ram_addr != RAM_ADDR_INVALID &&
578 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
579 kvm_hwpoison_page_add(ram_addr);
580 kvm_mce_inject(cpu, paddr, code);
2ae41db2 581 return;
419fb20a 582 }
20e0ff59
PB		 583
584 fprintf(stderr, "Hardware memory error for memory used by "
585 "QEMU itself instead of guest system!\n");
419fb20a 586 }
20e0ff59
PB		 587
588 if (code == BUS_MCEERR_AR) {
589 hardware_memory_error();
590 }
591
592 /* Hope we are lucky for AO MCE */
419fb20a
JK		 593}
594
fd13f23b
LA		 595static void kvm_reset_exception(CPUX86State *env)
596{
597 env->exception_nr = -1;
598 env->exception_pending = 0;
599 env->exception_injected = 0;
600 env->exception_has_payload = false;
601 env->exception_payload = 0;
602}
603
604static void kvm_queue_exception(CPUX86State *env,
605 int32_t exception_nr,
606 uint8_t exception_has_payload,
607 uint64_t exception_payload)
608{
609 assert(env->exception_nr == -1);
610 assert(!env->exception_pending);
611 assert(!env->exception_injected);
612 assert(!env->exception_has_payload);
613
614 env->exception_nr = exception_nr;
615
616 if (has_exception_payload) {
617 env->exception_pending = 1;
618
619 env->exception_has_payload = exception_has_payload;
620 env->exception_payload = exception_payload;
621 } else {
622 env->exception_injected = 1;
623
624 if (exception_nr == EXCP01_DB) {
625 assert(exception_has_payload);
626 env->dr[6] = exception_payload;
627 } else if (exception_nr == EXCP0E_PAGE) {
628 assert(exception_has_payload);
629 env->cr[2] = exception_payload;
630 } else {
631 assert(!exception_has_payload);
632 }
633 }
634}
635
1bc22652 636static int kvm_inject_mce_oldstyle(X86CPU *cpu)
ab443475 637{
1bc22652
AF		 638 CPUX86State *env = &cpu->env;
639
fd13f23b 640 if (!kvm_has_vcpu_events() && env->exception_nr == EXCP12_MCHK) {
ab443475
JK		 641 unsigned int bank, bank_num = env->mcg_cap & 0xff;
642 struct kvm_x86_mce mce;
643
fd13f23b 644 kvm_reset_exception(env);
ab443475
JK		 645
646 /*
647 * There must be at least one bank in use if an MCE is pending.
648 * Find it and use its values for the event injection.
649 */
650 for (bank = 0; bank < bank_num; bank++) {
651 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
652 break;
653 }
654 }
655 assert(bank < bank_num);
656
657 mce.bank = bank;
658 mce.status = env->mce_banks[bank * 4 + 1];
659 mce.mcg_status = env->mcg_status;
660 mce.addr = env->mce_banks[bank * 4 + 2];
661 mce.misc = env->mce_banks[bank * 4 + 3];
662
1bc22652 663 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
ab443475 664 }
ab443475
JK		 665 return 0;
666}
667
1dfb4dd9 668static void cpu_update_state(void *opaque, int running, RunState state)
b8cc45d6 669{
317ac620 670 CPUX86State *env = opaque;
b8cc45d6
GC		 671
672 if (running) {
673 env->tsc_valid = false;
674 }
675}
676
83b17af5 677unsigned long kvm_arch_vcpu_id(CPUState *cs)
b164e48e 678{
83b17af5 679 X86CPU *cpu = X86_CPU(cs);
7e72a45c 680 return cpu->apic_id;
b164e48e
EH		 681}
682
92067bf4
IM		 683#ifndef KVM_CPUID_SIGNATURE_NEXT
684#define KVM_CPUID_SIGNATURE_NEXT 0x40000100
685#endif
686
92067bf4
IM		 687static bool hyperv_enabled(X86CPU *cpu)
688{
7bc3d711
PB		 689 CPUState *cs = CPU(cpu);
690 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
2d384d7c 691 ((cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY) ||
e48ddcc6 692 cpu->hyperv_features || cpu->hyperv_passthrough);
92067bf4
IM		 693}
694
5031283d
HZ		 695static int kvm_arch_set_tsc_khz(CPUState *cs)
696{
697 X86CPU *cpu = X86_CPU(cs);
698 CPUX86State *env = &cpu->env;
699 int r;
700
701 if (!env->tsc_khz) {
702 return 0;
703 }
704
705 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
706 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
707 -ENOTSUP;
708 if (r < 0) {
709 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
710 * TSC frequency doesn't match the one we want.
711 */
712 int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
713 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
714 -ENOTSUP;
715 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
3dc6f869
AF		 716 warn_report("TSC frequency mismatch between "
717 "VM (%" PRId64 " kHz) and host (%d kHz), "
718 "and TSC scaling unavailable",
719 env->tsc_khz, cur_freq);
5031283d
HZ		 720 return r;
721 }
722 }
723
724 return 0;
725}
726
4bb95b82
LP		 727static bool tsc_is_stable_and_known(CPUX86State *env)
728{
729 if (!env->tsc_khz) {
730 return false;
731 }
732 return (env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
733 || env->user_tsc_khz;
734}
735
6760bd20
VK		 736static struct {
737 const char *desc;
738 struct {
739 uint32_t fw;
740 uint32_t bits;
741 } flags[2];
c6861930 742 uint64_t dependencies;
6760bd20
VK		 743} kvm_hyperv_properties[] = {
744 [HYPERV_FEAT_RELAXED] = {
745 .desc = "relaxed timing (hv-relaxed)",
746 .flags = {
747 {.fw = FEAT_HYPERV_EAX,
748 .bits = HV_HYPERCALL_AVAILABLE},
749 {.fw = FEAT_HV_RECOMM_EAX,
750 .bits = HV_RELAXED_TIMING_RECOMMENDED}
751 }
752 },
753 [HYPERV_FEAT_VAPIC] = {
754 .desc = "virtual APIC (hv-vapic)",
755 .flags = {
756 {.fw = FEAT_HYPERV_EAX,
757 .bits = HV_HYPERCALL_AVAILABLE | HV_APIC_ACCESS_AVAILABLE},
758 {.fw = FEAT_HV_RECOMM_EAX,
759 .bits = HV_APIC_ACCESS_RECOMMENDED}
760 }
761 },
762 [HYPERV_FEAT_TIME] = {
763 .desc = "clocksources (hv-time)",
764 .flags = {
765 {.fw = FEAT_HYPERV_EAX,
766 .bits = HV_HYPERCALL_AVAILABLE | HV_TIME_REF_COUNT_AVAILABLE |
767 HV_REFERENCE_TSC_AVAILABLE}
768 }
769 },
770 [HYPERV_FEAT_CRASH] = {
771 .desc = "crash MSRs (hv-crash)",
772 .flags = {
773 {.fw = FEAT_HYPERV_EDX,
774 .bits = HV_GUEST_CRASH_MSR_AVAILABLE}
775 }
776 },
777 [HYPERV_FEAT_RESET] = {
778 .desc = "reset MSR (hv-reset)",
779 .flags = {
780 {.fw = FEAT_HYPERV_EAX,
781 .bits = HV_RESET_AVAILABLE}
782 }
783 },
784 [HYPERV_FEAT_VPINDEX] = {
785 .desc = "VP_INDEX MSR (hv-vpindex)",
786 .flags = {
787 {.fw = FEAT_HYPERV_EAX,
788 .bits = HV_VP_INDEX_AVAILABLE}
789 }
790 },
791 [HYPERV_FEAT_RUNTIME] = {
792 .desc = "VP_RUNTIME MSR (hv-runtime)",
793 .flags = {
794 {.fw = FEAT_HYPERV_EAX,
795 .bits = HV_VP_RUNTIME_AVAILABLE}
796 }
797 },
798 [HYPERV_FEAT_SYNIC] = {
799 .desc = "synthetic interrupt controller (hv-synic)",
800 .flags = {
801 {.fw = FEAT_HYPERV_EAX,
802 .bits = HV_SYNIC_AVAILABLE}
803 }
804 },
805 [HYPERV_FEAT_STIMER] = {
806 .desc = "synthetic timers (hv-stimer)",
807 .flags = {
808 {.fw = FEAT_HYPERV_EAX,
809 .bits = HV_SYNTIMERS_AVAILABLE}
c6861930
VK		 810 },
811 .dependencies = BIT(HYPERV_FEAT_SYNIC) | BIT(HYPERV_FEAT_TIME)
6760bd20
VK		 812 },
813 [HYPERV_FEAT_FREQUENCIES] = {
814 .desc = "frequency MSRs (hv-frequencies)",
815 .flags = {
816 {.fw = FEAT_HYPERV_EAX,
817 .bits = HV_ACCESS_FREQUENCY_MSRS},
818 {.fw = FEAT_HYPERV_EDX,
819 .bits = HV_FREQUENCY_MSRS_AVAILABLE}
820 }
821 },
822 [HYPERV_FEAT_REENLIGHTENMENT] = {
823 .desc = "reenlightenment MSRs (hv-reenlightenment)",
824 .flags = {
825 {.fw = FEAT_HYPERV_EAX,
826 .bits = HV_ACCESS_REENLIGHTENMENTS_CONTROL}
827 }
828 },
829 [HYPERV_FEAT_TLBFLUSH] = {
830 .desc = "paravirtualized TLB flush (hv-tlbflush)",
831 .flags = {
832 {.fw = FEAT_HV_RECOMM_EAX,
833 .bits = HV_REMOTE_TLB_FLUSH_RECOMMENDED |
834 HV_EX_PROCESSOR_MASKS_RECOMMENDED}
bd59fbdf
VK		 835 },
836 .dependencies = BIT(HYPERV_FEAT_VPINDEX)
6760bd20
VK		 837 },
838 [HYPERV_FEAT_EVMCS] = {
839 .desc = "enlightened VMCS (hv-evmcs)",
840 .flags = {
841 {.fw = FEAT_HV_RECOMM_EAX,
842 .bits = HV_ENLIGHTENED_VMCS_RECOMMENDED}
8caba36d
VK		 843 },
844 .dependencies = BIT(HYPERV_FEAT_VAPIC)
6760bd20
VK		 845 },
846 [HYPERV_FEAT_IPI] = {
847 .desc = "paravirtualized IPI (hv-ipi)",
848 .flags = {
849 {.fw = FEAT_HV_RECOMM_EAX,
850 .bits = HV_CLUSTER_IPI_RECOMMENDED |
851 HV_EX_PROCESSOR_MASKS_RECOMMENDED}
bd59fbdf
VK		 852 },
853 .dependencies = BIT(HYPERV_FEAT_VPINDEX)
6760bd20 854 },
128531d9
VK		 855 [HYPERV_FEAT_STIMER_DIRECT] = {
856 .desc = "direct mode synthetic timers (hv-stimer-direct)",
857 .flags = {
858 {.fw = FEAT_HYPERV_EDX,
859 .bits = HV_STIMER_DIRECT_MODE_AVAILABLE}
860 },
861 .dependencies = BIT(HYPERV_FEAT_STIMER)
862 },
6760bd20
VK		 863};
864
865static struct kvm_cpuid2 *try_get_hv_cpuid(CPUState *cs, int max)
866{
867 struct kvm_cpuid2 *cpuid;
868 int r, size;
869
870 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
871 cpuid = g_malloc0(size);
872 cpuid->nent = max;
873
874 r = kvm_vcpu_ioctl(cs, KVM_GET_SUPPORTED_HV_CPUID, cpuid);
875 if (r == 0 && cpuid->nent >= max) {
876 r = -E2BIG;
877 }
878 if (r < 0) {
879 if (r == -E2BIG) {
880 g_free(cpuid);
881 return NULL;
882 } else {
883 fprintf(stderr, "KVM_GET_SUPPORTED_HV_CPUID failed: %s\n",
884 strerror(-r));
885 exit(1);
886 }
887 }
888 return cpuid;
889}
890
891/*
892 * Run KVM_GET_SUPPORTED_HV_CPUID ioctl(), allocating a buffer large enough
893 * for all entries.
894 */
895static struct kvm_cpuid2 *get_supported_hv_cpuid(CPUState *cs)
896{
897 struct kvm_cpuid2 *cpuid;
898 int max = 7; /* 0x40000000..0x40000005, 0x4000000A */
899
900 /*
901 * When the buffer is too small, KVM_GET_SUPPORTED_HV_CPUID fails with
902 * -E2BIG, however, it doesn't report back the right size. Keep increasing
903 * it and re-trying until we succeed.
904 */
905 while ((cpuid = try_get_hv_cpuid(cs, max)) == NULL) {
906 max++;
907 }
908 return cpuid;
909}
910
911/*
912 * When KVM_GET_SUPPORTED_HV_CPUID is not supported we fill CPUID feature
913 * leaves from KVM_CAP_HYPERV* and present MSRs data.
914 */
915static struct kvm_cpuid2 *get_supported_hv_cpuid_legacy(CPUState *cs)
c35bd19a
EY		 916{
917 X86CPU *cpu = X86_CPU(cs);
6760bd20
VK		 918 struct kvm_cpuid2 *cpuid;
919 struct kvm_cpuid_entry2 *entry_feat, *entry_recomm;
920
921 /* HV_CPUID_FEATURES, HV_CPUID_ENLIGHTMENT_INFO */
922 cpuid = g_malloc0(sizeof(*cpuid) + 2 * sizeof(*cpuid->entries));
923 cpuid->nent = 2;
924
925 /* HV_CPUID_VENDOR_AND_MAX_FUNCTIONS */
926 entry_feat = &cpuid->entries[0];
927 entry_feat->function = HV_CPUID_FEATURES;
928
929 entry_recomm = &cpuid->entries[1];
930 entry_recomm->function = HV_CPUID_ENLIGHTMENT_INFO;
931 entry_recomm->ebx = cpu->hyperv_spinlock_attempts;
932
933 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0) {
934 entry_feat->eax |= HV_HYPERCALL_AVAILABLE;
935 entry_feat->eax |= HV_APIC_ACCESS_AVAILABLE;
936 entry_feat->edx |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
937 entry_recomm->eax |= HV_RELAXED_TIMING_RECOMMENDED;
938 entry_recomm->eax |= HV_APIC_ACCESS_RECOMMENDED;
939 }
c35bd19a 940
6760bd20
VK		 941 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) {
942 entry_feat->eax |= HV_TIME_REF_COUNT_AVAILABLE;
943 entry_feat->eax |= HV_REFERENCE_TSC_AVAILABLE;
c35bd19a 944 }
6760bd20
VK		 945
946 if (has_msr_hv_frequencies) {
947 entry_feat->eax |= HV_ACCESS_FREQUENCY_MSRS;
948 entry_feat->edx |= HV_FREQUENCY_MSRS_AVAILABLE;
c35bd19a 949 }
6760bd20
VK		 950
951 if (has_msr_hv_crash) {
952 entry_feat->edx |= HV_GUEST_CRASH_MSR_AVAILABLE;
9445597b 953 }
6760bd20
VK		 954
955 if (has_msr_hv_reenlightenment) {
956 entry_feat->eax |= HV_ACCESS_REENLIGHTENMENTS_CONTROL;
c35bd19a 957 }
6760bd20
VK		 958
959 if (has_msr_hv_reset) {
960 entry_feat->eax |= HV_RESET_AVAILABLE;
c35bd19a 961 }
6760bd20
VK		 962
963 if (has_msr_hv_vpindex) {
964 entry_feat->eax |= HV_VP_INDEX_AVAILABLE;
ba6a4fd9 965 }
6760bd20
VK		 966
967 if (has_msr_hv_runtime) {
968 entry_feat->eax |= HV_VP_RUNTIME_AVAILABLE;
c35bd19a 969 }
6760bd20
VK		 970
971 if (has_msr_hv_synic) {
972 unsigned int cap = cpu->hyperv_synic_kvm_only ?
973 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
974
975 if (kvm_check_extension(cs->kvm_state, cap) > 0) {
976 entry_feat->eax |= HV_SYNIC_AVAILABLE;
1221f150 977 }
c35bd19a 978 }
6760bd20
VK		 979
980 if (has_msr_hv_stimer) {
981 entry_feat->eax |= HV_SYNTIMERS_AVAILABLE;
c35bd19a 982 }
9b4cf107 983
6760bd20
VK		 984 if (kvm_check_extension(cs->kvm_state,
985 KVM_CAP_HYPERV_TLBFLUSH) > 0) {
986 entry_recomm->eax |= HV_REMOTE_TLB_FLUSH_RECOMMENDED;
987 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
988 }
c35bd19a 989
6760bd20
VK		 990 if (kvm_check_extension(cs->kvm_state,
991 KVM_CAP_HYPERV_ENLIGHTENED_VMCS) > 0) {
992 entry_recomm->eax |= HV_ENLIGHTENED_VMCS_RECOMMENDED;
c35bd19a 993 }
6760bd20
VK		 994
995 if (kvm_check_extension(cs->kvm_state,
996 KVM_CAP_HYPERV_SEND_IPI) > 0) {
997 entry_recomm->eax |= HV_CLUSTER_IPI_RECOMMENDED;
998 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
c35bd19a 999 }
6760bd20
VK		 1000
1001 return cpuid;
1002}
1003
1004static int hv_cpuid_get_fw(struct kvm_cpuid2 *cpuid, int fw, uint32_t *r)
1005{
1006 struct kvm_cpuid_entry2 *entry;
1007 uint32_t func;
1008 int reg;
1009
1010 switch (fw) {
1011 case FEAT_HYPERV_EAX:
1012 reg = R_EAX;
1013 func = HV_CPUID_FEATURES;
1014 break;
1015 case FEAT_HYPERV_EDX:
1016 reg = R_EDX;
1017 func = HV_CPUID_FEATURES;
1018 break;
1019 case FEAT_HV_RECOMM_EAX:
1020 reg = R_EAX;
1021 func = HV_CPUID_ENLIGHTMENT_INFO;
1022 break;
1023 default:
1024 return -EINVAL;
a2b107db 1025 }
6760bd20
VK		 1026
1027 entry = cpuid_find_entry(cpuid, func, 0);
1028 if (!entry) {
1029 return -ENOENT;
a2b107db 1030 }
6760bd20
VK		 1031
1032 switch (reg) {
1033 case R_EAX:
1034 *r = entry->eax;
1035 break;
1036 case R_EDX:
1037 *r = entry->edx;
1038 break;
1039 default:
1040 return -EINVAL;
a2b107db 1041 }
6760bd20
VK		 1042
1043 return 0;
1044}
1045
1046static int hv_cpuid_check_and_set(CPUState *cs, struct kvm_cpuid2 *cpuid,
1047 int feature)
1048{
1049 X86CPU *cpu = X86_CPU(cs);
1050 CPUX86State *env = &cpu->env;
e48ddcc6 1051 uint32_t r, fw, bits;
c6861930 1052 uint64_t deps;
9dc83cd9 1053 int i, dep_feat;
6760bd20 1054
e48ddcc6 1055 if (!hyperv_feat_enabled(cpu, feature) && !cpu->hyperv_passthrough) {
6760bd20
VK		 1056 return 0;
1057 }
1058
c6861930 1059 deps = kvm_hyperv_properties[feature].dependencies;
9dc83cd9
HR		 1060 while (deps) {
1061 dep_feat = ctz64(deps);
c6861930
VK		 1062 if (!(hyperv_feat_enabled(cpu, dep_feat))) {
1063 fprintf(stderr,
1064 "Hyper-V %s requires Hyper-V %s\n",
1065 kvm_hyperv_properties[feature].desc,
1066 kvm_hyperv_properties[dep_feat].desc);
1067 return 1;
1068 }
9dc83cd9 1069 deps &= ~(1ull << dep_feat);
c6861930
VK		 1070 }
1071
6760bd20
VK		 1072 for (i = 0; i < ARRAY_SIZE(kvm_hyperv_properties[feature].flags); i++) {
1073 fw = kvm_hyperv_properties[feature].flags[i].fw;
1074 bits = kvm_hyperv_properties[feature].flags[i].bits;
1075
1076 if (!fw) {
1077 continue;
a2b107db 1078 }
6760bd20
VK		 1079
1080 if (hv_cpuid_get_fw(cpuid, fw, &r) || (r & bits) != bits) {
e48ddcc6
VK		 1081 if (hyperv_feat_enabled(cpu, feature)) {
1082 fprintf(stderr,
1083 "Hyper-V %s is not supported by kernel\n",
1084 kvm_hyperv_properties[feature].desc);
1085 return 1;
1086 } else {
1087 return 0;
1088 }
6760bd20
VK		 1089 }
1090
1091 env->features[fw] |= bits;
a2b107db 1092 }
6760bd20 1093
e48ddcc6
VK		 1094 if (cpu->hyperv_passthrough) {
1095 cpu->hyperv_features |= BIT(feature);
1096 }
1097
6760bd20
VK		 1098 return 0;
1099}
1100
2344d22e
VK		 1101/*
1102 * Fill in Hyper-V CPUIDs. Returns the number of entries filled in cpuid_ent in
1103 * case of success, errno < 0 in case of failure and 0 when no Hyper-V
1104 * extentions are enabled.
1105 */
1106static int hyperv_handle_properties(CPUState *cs,
1107 struct kvm_cpuid_entry2 *cpuid_ent)
6760bd20
VK		 1108{
1109 X86CPU *cpu = X86_CPU(cs);
1110 CPUX86State *env = &cpu->env;
1111 struct kvm_cpuid2 *cpuid;
2344d22e
VK		 1112 struct kvm_cpuid_entry2 *c;
1113 uint32_t signature[3];
1114 uint32_t cpuid_i = 0;
e48ddcc6 1115 int r;
6760bd20 1116
2344d22e
VK		 1117 if (!hyperv_enabled(cpu))
1118 return 0;
1119
e48ddcc6
VK		 1120 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) ||
1121 cpu->hyperv_passthrough) {
a2b107db
VK		 1122 uint16_t evmcs_version;
1123
e48ddcc6
VK		 1124 r = kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_ENLIGHTENED_VMCS, 0,
1125 (uintptr_t)&evmcs_version);
1126
1127 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) && r) {
6760bd20
VK		 1128 fprintf(stderr, "Hyper-V %s is not supported by kernel\n",
1129 kvm_hyperv_properties[HYPERV_FEAT_EVMCS].desc);
a2b107db
VK		 1130 return -ENOSYS;
1131 }
e48ddcc6
VK		 1132
1133 if (!r) {
1134 env->features[FEAT_HV_RECOMM_EAX] |=
1135 HV_ENLIGHTENED_VMCS_RECOMMENDED;
1136 env->features[FEAT_HV_NESTED_EAX] = evmcs_version;
1137 }
a2b107db
VK		 1138 }
1139
6760bd20
VK		 1140 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_CPUID) > 0) {
1141 cpuid = get_supported_hv_cpuid(cs);
1142 } else {
1143 cpuid = get_supported_hv_cpuid_legacy(cs);
1144 }
1145
e48ddcc6
VK		 1146 if (cpu->hyperv_passthrough) {
1147 memcpy(cpuid_ent, &cpuid->entries[0],
1148 cpuid->nent * sizeof(cpuid->entries[0]));
1149
1150 c = cpuid_find_entry(cpuid, HV_CPUID_FEATURES, 0);
1151 if (c) {
1152 env->features[FEAT_HYPERV_EAX] = c->eax;
1153 env->features[FEAT_HYPERV_EBX] = c->ebx;
1154 env->features[FEAT_HYPERV_EDX] = c->eax;
1155 }
1156 c = cpuid_find_entry(cpuid, HV_CPUID_ENLIGHTMENT_INFO, 0);
1157 if (c) {
1158 env->features[FEAT_HV_RECOMM_EAX] = c->eax;
1159
1160 /* hv-spinlocks may have been overriden */
1161 if (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY) {
1162 c->ebx = cpu->hyperv_spinlock_attempts;
1163 }
1164 }
1165 c = cpuid_find_entry(cpuid, HV_CPUID_NESTED_FEATURES, 0);
1166 if (c) {
1167 env->features[FEAT_HV_NESTED_EAX] = c->eax;
1168 }
1169 }
1170
6760bd20 1171 /* Features */
e48ddcc6 1172 r = hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_RELAXED);
6760bd20
VK		 1173 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_VAPIC);
1174 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_TIME);
1175 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_CRASH);
1176 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_RESET);
1177 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_VPINDEX);
1178 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_RUNTIME);
1179 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_SYNIC);
1180 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_STIMER);
1181 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_FREQUENCIES);
1182 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_REENLIGHTENMENT);
1183 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_TLBFLUSH);
1184 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_EVMCS);
1185 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_IPI);
128531d9 1186 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_STIMER_DIRECT);
6760bd20 1187
c6861930 1188 /* Additional dependencies not covered by kvm_hyperv_properties[] */
6760bd20
VK		 1189 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC) &&
1190 !cpu->hyperv_synic_kvm_only &&
1191 !hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)) {
c6861930 1192 fprintf(stderr, "Hyper-V %s requires Hyper-V %s\n",
6760bd20
VK		 1193 kvm_hyperv_properties[HYPERV_FEAT_SYNIC].desc,
1194 kvm_hyperv_properties[HYPERV_FEAT_VPINDEX].desc);
1195 r |= 1;
1196 }
1197
1198 /* Not exposed by KVM but needed to make CPU hotplug in Windows work */
1199 env->features[FEAT_HYPERV_EDX] |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
1200
2344d22e
VK		 1201 if (r) {
1202 r = -ENOSYS;
1203 goto free;
1204 }
1205
e48ddcc6
VK		 1206 if (cpu->hyperv_passthrough) {
1207 /* We already copied all feature words from KVM as is */
1208 r = cpuid->nent;
1209 goto free;
1210 }
1211
2344d22e
VK		 1212 c = &cpuid_ent[cpuid_i++];
1213 c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
1214 if (!cpu->hyperv_vendor_id) {
1215 memcpy(signature, "Microsoft Hv", 12);
1216 } else {
1217 size_t len = strlen(cpu->hyperv_vendor_id);
1218
1219 if (len > 12) {
1220 error_report("hv-vendor-id truncated to 12 characters");
1221 len = 12;
1222 }
1223 memset(signature, 0, 12);
1224 memcpy(signature, cpu->hyperv_vendor_id, len);
1225 }
1226 c->eax = hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) ?
1227 HV_CPUID_NESTED_FEATURES : HV_CPUID_IMPLEMENT_LIMITS;
1228 c->ebx = signature[0];
1229 c->ecx = signature[1];
1230 c->edx = signature[2];
1231
1232 c = &cpuid_ent[cpuid_i++];
1233 c->function = HV_CPUID_INTERFACE;
1234 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
1235 c->eax = signature[0];
1236 c->ebx = 0;
1237 c->ecx = 0;
1238 c->edx = 0;
1239
1240 c = &cpuid_ent[cpuid_i++];
1241 c->function = HV_CPUID_VERSION;
1242 c->eax = 0x00001bbc;
1243 c->ebx = 0x00060001;
1244
1245 c = &cpuid_ent[cpuid_i++];
1246 c->function = HV_CPUID_FEATURES;
1247 c->eax = env->features[FEAT_HYPERV_EAX];
1248 c->ebx = env->features[FEAT_HYPERV_EBX];
1249 c->edx = env->features[FEAT_HYPERV_EDX];
1250
1251 c = &cpuid_ent[cpuid_i++];
1252 c->function = HV_CPUID_ENLIGHTMENT_INFO;
1253 c->eax = env->features[FEAT_HV_RECOMM_EAX];
1254 c->ebx = cpu->hyperv_spinlock_attempts;
1255
1256 c = &cpuid_ent[cpuid_i++];
1257 c->function = HV_CPUID_IMPLEMENT_LIMITS;
1258 c->eax = cpu->hv_max_vps;
1259 c->ebx = 0x40;
1260
1261 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) {
1262 __u32 function;
1263
1264 /* Create zeroed 0x40000006..0x40000009 leaves */
1265 for (function = HV_CPUID_IMPLEMENT_LIMITS + 1;
1266 function < HV_CPUID_NESTED_FEATURES; function++) {
1267 c = &cpuid_ent[cpuid_i++];
1268 c->function = function;
1269 }
1270
1271 c = &cpuid_ent[cpuid_i++];
1272 c->function = HV_CPUID_NESTED_FEATURES;
1273 c->eax = env->features[FEAT_HV_NESTED_EAX];
1274 }
1275 r = cpuid_i;
1276
1277free:
6760bd20
VK		 1278 g_free(cpuid);
1279
2344d22e 1280 return r;
c35bd19a
EY		 1281}
1282
e48ddcc6
VK		 1283static Error *hv_passthrough_mig_blocker;
1284
e9688fab
RK		 1285static int hyperv_init_vcpu(X86CPU *cpu)
1286{
729ce7e1 1287 CPUState *cs = CPU(cpu);
e48ddcc6 1288 Error *local_err = NULL;
729ce7e1
RK		 1289 int ret;
1290
e48ddcc6
VK		 1291 if (cpu->hyperv_passthrough && hv_passthrough_mig_blocker == NULL) {
1292 error_setg(&hv_passthrough_mig_blocker,
1293 "'hv-passthrough' CPU flag prevents migration, use explicit"
1294 " set of hv-* flags instead");
1295 ret = migrate_add_blocker(hv_passthrough_mig_blocker, &local_err);
1296 if (local_err) {
1297 error_report_err(local_err);
1298 error_free(hv_passthrough_mig_blocker);
1299 return ret;
1300 }
1301 }
1302
2d384d7c 1303 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && !hv_vpindex_settable) {
e9688fab
RK		 1304 /*
1305 * the kernel doesn't support setting vp_index; assert that its value
1306 * is in sync
1307 */
e9688fab
RK		 1308 struct {
1309 struct kvm_msrs info;
1310 struct kvm_msr_entry entries[1];
1311 } msr_data = {
1312 .info.nmsrs = 1,
1313 .entries[0].index = HV_X64_MSR_VP_INDEX,
1314 };
1315
729ce7e1 1316 ret = kvm_vcpu_ioctl(cs, KVM_GET_MSRS, &msr_data);
e9688fab
RK		 1317 if (ret < 0) {
1318 return ret;
1319 }
1320 assert(ret == 1);
1321
701189e3 1322 if (msr_data.entries[0].data != hyperv_vp_index(CPU(cpu))) {
e9688fab
RK		 1323 error_report("kernel's vp_index != QEMU's vp_index");
1324 return -ENXIO;
1325 }
1326 }
1327
2d384d7c 1328 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
9b4cf107
RK		 1329 uint32_t synic_cap = cpu->hyperv_synic_kvm_only ?
1330 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
1331 ret = kvm_vcpu_enable_cap(cs, synic_cap, 0);
729ce7e1
RK		 1332 if (ret < 0) {
1333 error_report("failed to turn on HyperV SynIC in KVM: %s",
1334 strerror(-ret));
1335 return ret;
1336 }
606c34bf 1337
9b4cf107
RK		 1338 if (!cpu->hyperv_synic_kvm_only) {
1339 ret = hyperv_x86_synic_add(cpu);
1340 if (ret < 0) {
1341 error_report("failed to create HyperV SynIC: %s",
1342 strerror(-ret));
1343 return ret;
1344 }
606c34bf 1345 }
729ce7e1
RK		 1346 }
1347
e9688fab
RK		 1348 return 0;
1349}
1350
68bfd0ad
MT		 1351static Error *invtsc_mig_blocker;
1352
f8bb0565 1353#define KVM_MAX_CPUID_ENTRIES 100
0893d460 1354
20d695a9 1355int kvm_arch_init_vcpu(CPUState *cs)
05330448
AL		 1356{
1357 struct {
486bd5a2 1358 struct kvm_cpuid2 cpuid;
f8bb0565 1359 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
9115bb12
PM		 1360 } cpuid_data;
1361 /*
1362 * The kernel defines these structs with padding fields so there
1363 * should be no extra padding in our cpuid_data struct.
1364 */
1365 QEMU_BUILD_BUG_ON(sizeof(cpuid_data) !=
1366 sizeof(struct kvm_cpuid2) +
1367 sizeof(struct kvm_cpuid_entry2) * KVM_MAX_CPUID_ENTRIES);
1368
20d695a9
AF		 1369 X86CPU *cpu = X86_CPU(cs);
1370 CPUX86State *env = &cpu->env;
486bd5a2 1371 uint32_t limit, i, j, cpuid_i;
a33609ca 1372 uint32_t unused;
bb0300dc 1373 struct kvm_cpuid_entry2 *c;
bb0300dc 1374 uint32_t signature[3];
234cc647 1375 int kvm_base = KVM_CPUID_SIGNATURE;
ebbfef2f 1376 int max_nested_state_len;
e7429073 1377 int r;
fe44dc91 1378 Error *local_err = NULL;
05330448 1379
ef4cbe14
SW		 1380 memset(&cpuid_data, 0, sizeof(cpuid_data));
1381
05330448
AL		 1382 cpuid_i = 0;
1383
ddb98b5a
LP		 1384 r = kvm_arch_set_tsc_khz(cs);
1385 if (r < 0) {
6b2341ee 1386 return r;
ddb98b5a
LP		 1387 }
1388
1389 /* vcpu's TSC frequency is either specified by user, or following
1390 * the value used by KVM if the former is not present. In the
1391 * latter case, we query it from KVM and record in env->tsc_khz,
1392 * so that vcpu's TSC frequency can be migrated later via this field.
1393 */
1394 if (!env->tsc_khz) {
1395 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
1396 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
1397 -ENOTSUP;
1398 if (r > 0) {
1399 env->tsc_khz = r;
1400 }
1401 }
1402
bb0300dc 1403 /* Paravirtualization CPUIDs */
2344d22e
VK		 1404 r = hyperv_handle_properties(cs, cpuid_data.entries);
1405 if (r < 0) {
1406 return r;
1407 } else if (r > 0) {
1408 cpuid_i = r;
234cc647 1409 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
7bc3d711 1410 has_msr_hv_hypercall = true;
eab70139
VR		 1411 }
1412
f522d2ac
AW		 1413 if (cpu->expose_kvm) {
1414 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
1415 c = &cpuid_data.entries[cpuid_i++];
1416 c->function = KVM_CPUID_SIGNATURE | kvm_base;
79b6f2f6 1417 c->eax = KVM_CPUID_FEATURES | kvm_base;
f522d2ac
AW		 1418 c->ebx = signature[0];
1419 c->ecx = signature[1];
1420 c->edx = signature[2];
234cc647 1421
f522d2ac
AW		 1422 c = &cpuid_data.entries[cpuid_i++];
1423 c->function = KVM_CPUID_FEATURES | kvm_base;
1424 c->eax = env->features[FEAT_KVM];
be777326 1425 c->edx = env->features[FEAT_KVM_HINTS];
f522d2ac 1426 }
917367aa 1427
a33609ca 1428 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
05330448
AL		 1429
1430 for (i = 0; i <= limit; i++) {
f8bb0565
IM		 1431 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1432 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
1433 abort();
1434 }
bb0300dc 1435 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 1436
1437 switch (i) {
a36b1029
AL		 1438 case 2: {
1439 /* Keep reading function 2 till all the input is received */
1440 int times;
1441
a36b1029 1442 c->function = i;
a33609ca
AL		 1443 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
1444 KVM_CPUID_FLAG_STATE_READ_NEXT;
1445 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1446 times = c->eax & 0xff;
a36b1029
AL		 1447
1448 for (j = 1; j < times; ++j) {
f8bb0565
IM		 1449 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1450 fprintf(stderr, "cpuid_data is full, no space for "
1451 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
1452 abort();
1453 }
a33609ca 1454 c = &cpuid_data.entries[cpuid_i++];
a36b1029 1455 c->function = i;
a33609ca
AL		 1456 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
1457 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
a36b1029
AL		 1458 }
1459 break;
1460 }
a94e1428
LX		 1461 case 0x1f:
1462 if (env->nr_dies < 2) {
1463 break;
1464 }
486bd5a2
AL		 1465 case 4:
1466 case 0xb:
1467 case 0xd:
1468 for (j = 0; ; j++) {
31e8c696
AP		 1469 if (i == 0xd && j == 64) {
1470 break;
1471 }
a94e1428
LX		 1472
1473 if (i == 0x1f && j == 64) {
1474 break;
1475 }
1476
486bd5a2
AL		 1477 c->function = i;
1478 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1479 c->index = j;
a33609ca 1480 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2 1481
b9bec74b 1482 if (i == 4 && c->eax == 0) {
486bd5a2 1483 break;
b9bec74b
JK		 1484 }
1485 if (i == 0xb && !(c->ecx & 0xff00)) {
486bd5a2 1486 break;
b9bec74b 1487 }
a94e1428
LX		 1488 if (i == 0x1f && !(c->ecx & 0xff00)) {
1489 break;
1490 }
b9bec74b 1491 if (i == 0xd && c->eax == 0) {
31e8c696 1492 continue;
b9bec74b 1493 }
f8bb0565
IM		 1494 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1495 fprintf(stderr, "cpuid_data is full, no space for "
1496 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1497 abort();
1498 }
a33609ca 1499 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 1500 }
1501 break;
e37a5c7f
CP		 1502 case 0x14: {
1503 uint32_t times;
1504
1505 c->function = i;
1506 c->index = 0;
1507 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1508 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1509 times = c->eax;
1510
1511 for (j = 1; j <= times; ++j) {
1512 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1513 fprintf(stderr, "cpuid_data is full, no space for "
1514 "cpuid(eax:0x14,ecx:0x%x)\n", j);
1515 abort();
1516 }
1517 c = &cpuid_data.entries[cpuid_i++];
1518 c->function = i;
1519 c->index = j;
1520 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1521 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1522 }
1523 break;
1524 }
486bd5a2 1525 default:
486bd5a2 1526 c->function = i;
a33609ca
AL		 1527 c->flags = 0;
1528 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2
AL		 1529 break;
1530 }
05330448 1531 }
0d894367
PB		 1532
1533 if (limit >= 0x0a) {
0b368a10 1534 uint32_t eax, edx;
0d894367 1535
0b368a10
JD		 1536 cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx);
1537
1538 has_architectural_pmu_version = eax & 0xff;
1539 if (has_architectural_pmu_version > 0) {
1540 num_architectural_pmu_gp_counters = (eax & 0xff00) >> 8;
0d894367
PB		 1541
1542 /* Shouldn't be more than 32, since that's the number of bits
1543 * available in EBX to tell us _which_ counters are available.
1544 * Play it safe.
1545 */
0b368a10
JD		 1546 if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) {
1547 num_architectural_pmu_gp_counters = MAX_GP_COUNTERS;
1548 }
1549
1550 if (has_architectural_pmu_version > 1) {
1551 num_architectural_pmu_fixed_counters = edx & 0x1f;
1552
1553 if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNTERS) {
1554 num_architectural_pmu_fixed_counters = MAX_FIXED_COUNTERS;
1555 }
0d894367
PB		 1556 }
1557 }
1558 }
1559
a33609ca 1560 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
05330448
AL		 1561
1562 for (i = 0x80000000; i <= limit; i++) {
f8bb0565
IM		 1563 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1564 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
1565 abort();
1566 }
bb0300dc 1567 c = &cpuid_data.entries[cpuid_i++];
05330448 1568
8f4202fb
BM		 1569 switch (i) {
1570 case 0x8000001d:
1571 /* Query for all AMD cache information leaves */
1572 for (j = 0; ; j++) {
1573 c->function = i;
1574 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1575 c->index = j;
1576 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1577
1578 if (c->eax == 0) {
1579 break;
1580 }
1581 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1582 fprintf(stderr, "cpuid_data is full, no space for "
1583 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1584 abort();
1585 }
1586 c = &cpuid_data.entries[cpuid_i++];
1587 }
1588 break;
1589 default:
1590 c->function = i;
1591 c->flags = 0;
1592 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1593 break;
1594 }
05330448
AL		 1595 }
1596
b3baa152
BW		 1597 /* Call Centaur's CPUID instructions they are supported. */
1598 if (env->cpuid_xlevel2 > 0) {
b3baa152
BW		 1599 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
1600
1601 for (i = 0xC0000000; i <= limit; i++) {
f8bb0565
IM		 1602 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1603 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
1604 abort();
1605 }
b3baa152
BW		 1606 c = &cpuid_data.entries[cpuid_i++];
1607
1608 c->function = i;
1609 c->flags = 0;
1610 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1611 }
1612 }
1613
05330448
AL		 1614 cpuid_data.cpuid.nent = cpuid_i;
1615
e7701825 1616 if (((env->cpuid_version >> 8)&0xF) >= 6
0514ef2f 1617 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
fc7a504c 1618 (CPUID_MCE | CPUID_MCA)
a60f24b5 1619 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
5120901a 1620 uint64_t mcg_cap, unsupported_caps;
e7701825 1621 int banks;
32a42024 1622 int ret;
e7701825 1623
a60f24b5 1624 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
75d49497
JK		 1625 if (ret < 0) {
1626 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
1627 return ret;
e7701825 1628 }
75d49497 1629
2590f15b 1630 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
49b69cbf 1631 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
2590f15b 1632 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
49b69cbf 1633 return -ENOTSUP;
75d49497 1634 }
49b69cbf 1635
5120901a
EH		 1636 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
1637 if (unsupported_caps) {
87f8b626
AR		 1638 if (unsupported_caps & MCG_LMCE_P) {
1639 error_report("kvm: LMCE not supported");
1640 return -ENOTSUP;
1641 }
3dc6f869
AF		 1642 warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64,
1643 unsupported_caps);
5120901a
EH		 1644 }
1645
2590f15b
EH		 1646 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
1647 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
75d49497
JK		 1648 if (ret < 0) {
1649 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
1650 return ret;
1651 }
e7701825 1652 }
e7701825 1653
b8cc45d6
GC		 1654 qemu_add_vm_change_state_handler(cpu_update_state, env);
1655
df67696e
LJ		 1656 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
1657 if (c) {
1658 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
1659 !!(c->ecx & CPUID_EXT_SMX);
1660 }
1661
87f8b626
AR		 1662 if (env->mcg_cap & MCG_LMCE_P) {
1663 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
1664 }
1665
d99569d9
EH		 1666 if (!env->user_tsc_khz) {
1667 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
1668 invtsc_mig_blocker == NULL) {
d99569d9
EH		 1669 error_setg(&invtsc_mig_blocker,
1670 "State blocked by non-migratable CPU device"
1671 " (invtsc flag)");
fe44dc91
AA		 1672 r = migrate_add_blocker(invtsc_mig_blocker, &local_err);
1673 if (local_err) {
1674 error_report_err(local_err);
1675 error_free(invtsc_mig_blocker);
79a197ab 1676 return r;
fe44dc91 1677 }
d99569d9 1678 }
68bfd0ad
MT		 1679 }
1680
9954a158
PDJ		 1681 if (cpu->vmware_cpuid_freq
1682 /* Guests depend on 0x40000000 to detect this feature, so only expose
1683 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
1684 && cpu->expose_kvm
1685 && kvm_base == KVM_CPUID_SIGNATURE
1686 /* TSC clock must be stable and known for this feature. */
4bb95b82 1687 && tsc_is_stable_and_known(env)) {
9954a158
PDJ		 1688
1689 c = &cpuid_data.entries[cpuid_i++];
1690 c->function = KVM_CPUID_SIGNATURE | 0x10;
1691 c->eax = env->tsc_khz;
1692 /* LAPIC resolution of 1ns (freq: 1GHz) is hardcoded in KVM's
1693 * APIC_BUS_CYCLE_NS */
1694 c->ebx = 1000000;
1695 c->ecx = c->edx = 0;
1696
1697 c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
1698 c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
1699 }
1700
1701 cpuid_data.cpuid.nent = cpuid_i;
1702
1703 cpuid_data.cpuid.padding = 0;
1704 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
1705 if (r) {
1706 goto fail;
1707 }
1708
28143b40 1709 if (has_xsave) {
5b8063c4 1710 env->xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
fabacc0f 1711 }
ebbfef2f
LA		 1712
1713 max_nested_state_len = kvm_max_nested_state_length();
1714 if (max_nested_state_len > 0) {
1715 assert(max_nested_state_len >= offsetof(struct kvm_nested_state, data));
ebbfef2f 1716
1e44f3ab
PB		 1717 if (cpu_has_vmx(env)) {
1718 struct kvm_vmx_nested_state_hdr *vmx_hdr;
ebbfef2f 1719
1e44f3ab
PB		 1720 env->nested_state = g_malloc0(max_nested_state_len);
1721 env->nested_state->size = max_nested_state_len;
ebbfef2f 1722 env->nested_state->format = KVM_STATE_NESTED_FORMAT_VMX;
1e44f3ab
PB		 1723
1724 vmx_hdr = &env->nested_state->hdr.vmx;
ebbfef2f
LA		 1725 vmx_hdr->vmxon_pa = -1ull;
1726 vmx_hdr->vmcs12_pa = -1ull;
1727 }
1728 }
1729
d71b62a1 1730 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
fabacc0f 1731
273c515c
PB		 1732 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
1733 has_msr_tsc_aux = false;
1734 }
d1ae67f6 1735
e9688fab
RK		 1736 r = hyperv_init_vcpu(cpu);
1737 if (r) {
1738 goto fail;
1739 }
1740
e7429073 1741 return 0;
fe44dc91
AA		 1742
1743 fail:
1744 migrate_del_blocker(invtsc_mig_blocker);
6b2341ee 1745
fe44dc91 1746 return r;
05330448
AL		 1747}
1748
b1115c99
LA		 1749int kvm_arch_destroy_vcpu(CPUState *cs)
1750{
1751 X86CPU *cpu = X86_CPU(cs);
ebbfef2f 1752 CPUX86State *env = &cpu->env;
b1115c99
LA		 1753
1754 if (cpu->kvm_msr_buf) {
1755 g_free(cpu->kvm_msr_buf);
1756 cpu->kvm_msr_buf = NULL;
1757 }
1758
ebbfef2f
LA		 1759 if (env->nested_state) {
1760 g_free(env->nested_state);
1761 env->nested_state = NULL;
1762 }
1763
b1115c99
LA		 1764 return 0;
1765}
1766
50a2c6e5 1767void kvm_arch_reset_vcpu(X86CPU *cpu)
caa5af0f 1768{
20d695a9 1769 CPUX86State *env = &cpu->env;
dd673288 1770
1a5e9d2f 1771 env->xcr0 = 1;
ddced198 1772 if (kvm_irqchip_in_kernel()) {
dd673288 1773 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
ddced198
MT		 1774 KVM_MP_STATE_UNINITIALIZED;
1775 } else {
1776 env->mp_state = KVM_MP_STATE_RUNNABLE;
1777 }
689141dd 1778
2d384d7c 1779 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
689141dd
RK		 1780 int i;
1781 for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) {
1782 env->msr_hv_synic_sint[i] = HV_SINT_MASKED;
1783 }
606c34bf
RK		 1784
1785 hyperv_x86_synic_reset(cpu);
689141dd 1786 }
caa5af0f
JK		 1787}
1788
e0723c45
PB		 1789void kvm_arch_do_init_vcpu(X86CPU *cpu)
1790{
1791 CPUX86State *env = &cpu->env;
1792
1793 /* APs get directly into wait-for-SIPI state. */
1794 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
1795 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
1796 }
1797}
1798
f57bceb6
RH		 1799static int kvm_get_supported_feature_msrs(KVMState *s)
1800{
1801 int ret = 0;
1802
1803 if (kvm_feature_msrs != NULL) {
1804 return 0;
1805 }
1806
1807 if (!kvm_check_extension(s, KVM_CAP_GET_MSR_FEATURES)) {
1808 return 0;
1809 }
1810
1811 struct kvm_msr_list msr_list;
1812
1813 msr_list.nmsrs = 0;
1814 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, &msr_list);
1815 if (ret < 0 && ret != -E2BIG) {
1816 error_report("Fetch KVM feature MSR list failed: %s",
1817 strerror(-ret));
1818 return ret;
1819 }
1820
1821 assert(msr_list.nmsrs > 0);
1822 kvm_feature_msrs = (struct kvm_msr_list *) \
1823 g_malloc0(sizeof(msr_list) +
1824 msr_list.nmsrs * sizeof(msr_list.indices[0]));
1825
1826 kvm_feature_msrs->nmsrs = msr_list.nmsrs;
1827 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, kvm_feature_msrs);
1828
1829 if (ret < 0) {
1830 error_report("Fetch KVM feature MSR list failed: %s",
1831 strerror(-ret));
1832 g_free(kvm_feature_msrs);
1833 kvm_feature_msrs = NULL;
1834 return ret;
1835 }
1836
1837 return 0;
1838}
1839
c3a3a7d3 1840static int kvm_get_supported_msrs(KVMState *s)
05330448 1841{
75b10c43 1842 static int kvm_supported_msrs;
c3a3a7d3 1843 int ret = 0;
05330448
AL		 1844
1845 /* first time */
75b10c43 1846 if (kvm_supported_msrs == 0) {
05330448
AL		 1847 struct kvm_msr_list msr_list, *kvm_msr_list;
1848
75b10c43 1849 kvm_supported_msrs = -1;
05330448
AL		 1850
1851 /* Obtain MSR list from KVM. These are the MSRs that we must
1852 * save/restore */
4c9f7372 1853 msr_list.nmsrs = 0;
c3a3a7d3 1854 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
6fb6d245 1855 if (ret < 0 && ret != -E2BIG) {
c3a3a7d3 1856 return ret;
6fb6d245 1857 }
d9db889f
JK		 1858 /* Old kernel modules had a bug and could write beyond the provided
1859 memory. Allocate at least a safe amount of 1K. */
7267c094 1860 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
d9db889f
JK		 1861 msr_list.nmsrs *
1862 sizeof(msr_list.indices[0])));
05330448 1863
55308450 1864 kvm_msr_list->nmsrs = msr_list.nmsrs;
c3a3a7d3 1865 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
05330448
AL		 1866 if (ret >= 0) {
1867 int i;
1868
1869 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
1d268dec
LP		 1870 switch (kvm_msr_list->indices[i]) {
1871 case MSR_STAR:
c3a3a7d3 1872 has_msr_star = true;
1d268dec
LP		 1873 break;
1874 case MSR_VM_HSAVE_PA:
c3a3a7d3 1875 has_msr_hsave_pa = true;
1d268dec
LP		 1876 break;
1877 case MSR_TSC_AUX:
c9b8f6b6 1878 has_msr_tsc_aux = true;
1d268dec
LP		 1879 break;
1880 case MSR_TSC_ADJUST:
f28558d3 1881 has_msr_tsc_adjust = true;
1d268dec
LP		 1882 break;
1883 case MSR_IA32_TSCDEADLINE:
aa82ba54 1884 has_msr_tsc_deadline = true;
1d268dec
LP		 1885 break;
1886 case MSR_IA32_SMBASE:
fc12d72e 1887 has_msr_smbase = true;
1d268dec 1888 break;
e13713db
LA		 1889 case MSR_SMI_COUNT:
1890 has_msr_smi_count = true;
1891 break;
1d268dec 1892 case MSR_IA32_MISC_ENABLE:
21e87c46 1893 has_msr_misc_enable = true;
1d268dec
LP		 1894 break;
1895 case MSR_IA32_BNDCFGS:
79e9ebeb 1896 has_msr_bndcfgs = true;
1d268dec
LP		 1897 break;
1898 case MSR_IA32_XSS:
18cd2c17 1899 has_msr_xss = true;
3c254ab8 1900 break;
1d268dec 1901 case HV_X64_MSR_CRASH_CTL:
f2a53c9e 1902 has_msr_hv_crash = true;
1d268dec
LP		 1903 break;
1904 case HV_X64_MSR_RESET:
744b8a94 1905 has_msr_hv_reset = true;
1d268dec
LP		 1906 break;
1907 case HV_X64_MSR_VP_INDEX:
8c145d7c 1908 has_msr_hv_vpindex = true;
1d268dec
LP		 1909 break;
1910 case HV_X64_MSR_VP_RUNTIME:
46eb8f98 1911 has_msr_hv_runtime = true;
1d268dec
LP		 1912 break;
1913 case HV_X64_MSR_SCONTROL:
866eea9a 1914 has_msr_hv_synic = true;
1d268dec
LP		 1915 break;
1916 case HV_X64_MSR_STIMER0_CONFIG:
ff99aa64 1917 has_msr_hv_stimer = true;
1d268dec 1918 break;
d72bc7f6
LP		 1919 case HV_X64_MSR_TSC_FREQUENCY:
1920 has_msr_hv_frequencies = true;
1921 break;
ba6a4fd9
VK		 1922 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
1923 has_msr_hv_reenlightenment = true;
1924 break;
a33a2cfe
PB		 1925 case MSR_IA32_SPEC_CTRL:
1926 has_msr_spec_ctrl = true;
1927 break;
cfeea0c0
KRW		 1928 case MSR_VIRT_SSBD:
1929 has_msr_virt_ssbd = true;
1930 break;
aec5e9c3
BD		 1931 case MSR_IA32_ARCH_CAPABILITIES:
1932 has_msr_arch_capabs = true;
1933 break;
597360c0
XL		 1934 case MSR_IA32_CORE_CAPABILITY:
1935 has_msr_core_capabs = true;
1936 break;
ff99aa64 1937 }
05330448
AL		 1938 }
1939 }
1940
7267c094 1941 g_free(kvm_msr_list);
05330448
AL		 1942 }
1943
c3a3a7d3 1944 return ret;
05330448
AL		 1945}
1946
6410848b
PB		 1947static Notifier smram_machine_done;
1948static KVMMemoryListener smram_listener;
1949static AddressSpace smram_address_space;
1950static MemoryRegion smram_as_root;
1951static MemoryRegion smram_as_mem;
1952
1953static void register_smram_listener(Notifier *n, void *unused)
1954{
1955 MemoryRegion *smram =
1956 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1957
1958 /* Outer container... */
1959 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1960 memory_region_set_enabled(&smram_as_root, true);
1961
1962 /* ... with two regions inside: normal system memory with low
1963 * priority, and...
1964 */
1965 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1966 get_system_memory(), 0, ~0ull);
1967 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1968 memory_region_set_enabled(&smram_as_mem, true);
1969
1970 if (smram) {
1971 /* ... SMRAM with higher priority */
1972 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1973 memory_region_set_enabled(smram, true);
1974 }
1975
1976 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1977 kvm_memory_listener_register(kvm_state, &smram_listener,
1978 &smram_address_space, 1);
1979}
1980
b16565b3 1981int kvm_arch_init(MachineState *ms, KVMState *s)
20420430 1982{
11076198 1983 uint64_t identity_base = 0xfffbc000;
39d6960a 1984 uint64_t shadow_mem;
20420430 1985 int ret;
25d2e361 1986 struct utsname utsname;
20420430 1987
28143b40 1988 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
28143b40 1989 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
28143b40 1990 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
28143b40 1991
e9688fab
RK		 1992 hv_vpindex_settable = kvm_check_extension(s, KVM_CAP_HYPERV_VP_INDEX);
1993
fd13f23b
LA		 1994 has_exception_payload = kvm_check_extension(s, KVM_CAP_EXCEPTION_PAYLOAD);
1995 if (has_exception_payload) {
1996 ret = kvm_vm_enable_cap(s, KVM_CAP_EXCEPTION_PAYLOAD, 0, true);
1997 if (ret < 0) {
1998 error_report("kvm: Failed to enable exception payload cap: %s",
1999 strerror(-ret));
2000 return ret;
2001 }
2002 }
2003
c3a3a7d3 2004 ret = kvm_get_supported_msrs(s);
20420430 2005 if (ret < 0) {
20420430
SY		 2006 return ret;
2007 }
25d2e361 2008
f57bceb6
RH		 2009 kvm_get_supported_feature_msrs(s);
2010
25d2e361
MT		 2011 uname(&utsname);
2012 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
2013
4c5b10b7 2014 /*
11076198
JK		 2015 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
2016 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
2017 * Since these must be part of guest physical memory, we need to allocate
2018 * them, both by setting their start addresses in the kernel and by
2019 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
2020 *
2021 * Older KVM versions may not support setting the identity map base. In
2022 * that case we need to stick with the default, i.e. a 256K maximum BIOS
2023 * size.
4c5b10b7 2024 */
11076198
JK		 2025 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
2026 /* Allows up to 16M BIOSes. */
2027 identity_base = 0xfeffc000;
2028
2029 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
2030 if (ret < 0) {
2031 return ret;
2032 }
4c5b10b7 2033 }
e56ff191 2034
11076198
JK		 2035 /* Set TSS base one page after EPT identity map. */
2036 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
20420430
SY		 2037 if (ret < 0) {
2038 return ret;
2039 }
2040
11076198
JK		 2041 /* Tell fw_cfg to notify the BIOS to reserve the range. */
2042 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
20420430 2043 if (ret < 0) {
11076198 2044 fprintf(stderr, "e820_add_entry() table is full\n");
20420430
SY		 2045 return ret;
2046 }
3c85e74f 2047 qemu_register_reset(kvm_unpoison_all, NULL);
20420430 2048
4689b77b 2049 shadow_mem = machine_kvm_shadow_mem(ms);
36ad0e94
MA		 2050 if (shadow_mem != -1) {
2051 shadow_mem /= 4096;
2052 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
2053 if (ret < 0) {
2054 return ret;
39d6960a
JK		 2055 }
2056 }
6410848b 2057
d870cfde
GA		 2058 if (kvm_check_extension(s, KVM_CAP_X86_SMM) &&
2059 object_dynamic_cast(OBJECT(ms), TYPE_PC_MACHINE) &&
2060 pc_machine_is_smm_enabled(PC_MACHINE(ms))) {
6410848b
PB		 2061 smram_machine_done.notify = register_smram_listener;
2062 qemu_add_machine_init_done_notifier(&smram_machine_done);
2063 }
6f131f13
MT		 2064
2065 if (enable_cpu_pm) {
2066 int disable_exits = kvm_check_extension(s, KVM_CAP_X86_DISABLE_EXITS);
2067 int ret;
2068
2069/* Work around for kernel header with a typo. TODO: fix header and drop. */
2070#if defined(KVM_X86_DISABLE_EXITS_HTL) && !defined(KVM_X86_DISABLE_EXITS_HLT)
2071#define KVM_X86_DISABLE_EXITS_HLT KVM_X86_DISABLE_EXITS_HTL
2072#endif
2073 if (disable_exits) {
2074 disable_exits &= (KVM_X86_DISABLE_EXITS_MWAIT |
2075 KVM_X86_DISABLE_EXITS_HLT |
2076 KVM_X86_DISABLE_EXITS_PAUSE);
2077 }
2078
2079 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_DISABLE_EXITS, 0,
2080 disable_exits);
2081 if (ret < 0) {
2082 error_report("kvm: guest stopping CPU not supported: %s",
2083 strerror(-ret));
2084 }
2085 }
2086
11076198 2087 return 0;
05330448 2088}
b9bec74b 2089
05330448
AL		 2090static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
2091{
2092 lhs->selector = rhs->selector;
2093 lhs->base = rhs->base;
2094 lhs->limit = rhs->limit;
2095 lhs->type = 3;
2096 lhs->present = 1;
2097 lhs->dpl = 3;
2098 lhs->db = 0;
2099 lhs->s = 1;
2100 lhs->l = 0;
2101 lhs->g = 0;
2102 lhs->avl = 0;
2103 lhs->unusable = 0;
2104}
2105
2106static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
2107{
2108 unsigned flags = rhs->flags;
2109 lhs->selector = rhs->selector;
2110 lhs->base = rhs->base;
2111 lhs->limit = rhs->limit;
2112 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
2113 lhs->present = (flags & DESC_P_MASK) != 0;
acaa7550 2114 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
05330448
AL		 2115 lhs->db = (flags >> DESC_B_SHIFT) & 1;
2116 lhs->s = (flags & DESC_S_MASK) != 0;
2117 lhs->l = (flags >> DESC_L_SHIFT) & 1;
2118 lhs->g = (flags & DESC_G_MASK) != 0;
2119 lhs->avl = (flags & DESC_AVL_MASK) != 0;
4cae9c97 2120 lhs->unusable = !lhs->present;
7e680753 2121 lhs->padding = 0;
05330448
AL		 2122}
2123
2124static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
2125{
2126 lhs->selector = rhs->selector;
2127 lhs->base = rhs->base;
2128 lhs->limit = rhs->limit;
d45fc087
RP		 2129 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
2130 ((rhs->present && !rhs->unusable) * DESC_P_MASK) |
2131 (rhs->dpl << DESC_DPL_SHIFT) |
2132 (rhs->db << DESC_B_SHIFT) |
2133 (rhs->s * DESC_S_MASK) |
2134 (rhs->l << DESC_L_SHIFT) |
2135 (rhs->g * DESC_G_MASK) |
2136 (rhs->avl * DESC_AVL_MASK);
05330448
AL		 2137}
2138
2139static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
2140{
b9bec74b 2141 if (set) {
05330448 2142 *kvm_reg = *qemu_reg;
b9bec74b 2143 } else {
05330448 2144 *qemu_reg = *kvm_reg;
b9bec74b 2145 }
05330448
AL		 2146}
2147
1bc22652 2148static int kvm_getput_regs(X86CPU *cpu, int set)
05330448 2149{
1bc22652 2150 CPUX86State *env = &cpu->env;
05330448
AL		 2151 struct kvm_regs regs;
2152 int ret = 0;
2153
2154 if (!set) {
1bc22652 2155 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
b9bec74b 2156 if (ret < 0) {
05330448 2157 return ret;
b9bec74b 2158 }
05330448
AL		 2159 }
2160
2161 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
2162 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
2163 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
2164 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
2165 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
2166 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
2167 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
2168 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
2169#ifdef TARGET_X86_64
2170 kvm_getput_reg(&regs.r8, &env->regs[8], set);
2171 kvm_getput_reg(&regs.r9, &env->regs[9], set);
2172 kvm_getput_reg(&regs.r10, &env->regs[10], set);
2173 kvm_getput_reg(&regs.r11, &env->regs[11], set);
2174 kvm_getput_reg(&regs.r12, &env->regs[12], set);
2175 kvm_getput_reg(&regs.r13, &env->regs[13], set);
2176 kvm_getput_reg(&regs.r14, &env->regs[14], set);
2177 kvm_getput_reg(&regs.r15, &env->regs[15], set);
2178#endif
2179
2180 kvm_getput_reg(&regs.rflags, &env->eflags, set);
2181 kvm_getput_reg(&regs.rip, &env->eip, set);
2182
b9bec74b 2183 if (set) {
1bc22652 2184 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
b9bec74b 2185 }
05330448
AL		 2186
2187 return ret;
2188}
2189
1bc22652 2190static int kvm_put_fpu(X86CPU *cpu)
05330448 2191{
1bc22652 2192 CPUX86State *env = &cpu->env;
05330448
AL		 2193 struct kvm_fpu fpu;
2194 int i;
2195
2196 memset(&fpu, 0, sizeof fpu);
2197 fpu.fsw = env->fpus & ~(7 << 11);
2198 fpu.fsw |= (env->fpstt & 7) << 11;
2199 fpu.fcw = env->fpuc;
42cc8fa6
JK		 2200 fpu.last_opcode = env->fpop;
2201 fpu.last_ip = env->fpip;
2202 fpu.last_dp = env->fpdp;
b9bec74b
JK		 2203 for (i = 0; i < 8; ++i) {
2204 fpu.ftwx |= (!env->fptags[i]) << i;
2205 }
05330448 2206 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
bee81887 2207 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 2208 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
2209 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
bee81887 2210 }
05330448
AL		 2211 fpu.mxcsr = env->mxcsr;
2212
1bc22652 2213 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
05330448
AL		 2214}
2215
6b42494b
JK		 2216#define XSAVE_FCW_FSW 0
2217#define XSAVE_FTW_FOP 1
f1665b21
SY		 2218#define XSAVE_CWD_RIP 2
2219#define XSAVE_CWD_RDP 4
2220#define XSAVE_MXCSR 6
2221#define XSAVE_ST_SPACE 8
2222#define XSAVE_XMM_SPACE 40
2223#define XSAVE_XSTATE_BV 128
2224#define XSAVE_YMMH_SPACE 144
79e9ebeb
LJ		 2225#define XSAVE_BNDREGS 240
2226#define XSAVE_BNDCSR 256
9aecd6f8
CP		 2227#define XSAVE_OPMASK 272
2228#define XSAVE_ZMM_Hi256 288
2229#define XSAVE_Hi16_ZMM 416
f74eefe0 2230#define XSAVE_PKRU 672
f1665b21 2231
b503717d 2232#define XSAVE_BYTE_OFFSET(word_offset) \
f18793b0 2233 ((word_offset) * sizeof_field(struct kvm_xsave, region[0]))
b503717d
EH		 2234
2235#define ASSERT_OFFSET(word_offset, field) \
2236 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
2237 offsetof(X86XSaveArea, field))
2238
2239ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
2240ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
2241ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
2242ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
2243ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
2244ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
2245ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
2246ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
2247ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
2248ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
2249ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
2250ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
2251ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
2252ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
2253ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
2254
1bc22652 2255static int kvm_put_xsave(X86CPU *cpu)
f1665b21 2256{
1bc22652 2257 CPUX86State *env = &cpu->env;
5b8063c4 2258 X86XSaveArea *xsave = env->xsave_buf;
f1665b21 2259
28143b40 2260 if (!has_xsave) {
1bc22652 2261 return kvm_put_fpu(cpu);
b9bec74b 2262 }
86a57621 2263 x86_cpu_xsave_all_areas(cpu, xsave);
f1665b21 2264
9be38598 2265 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
f1665b21
SY		 2266}
2267
1bc22652 2268static int kvm_put_xcrs(X86CPU *cpu)
f1665b21 2269{
1bc22652 2270 CPUX86State *env = &cpu->env;
bdfc8480 2271 struct kvm_xcrs xcrs = {};
f1665b21 2272
28143b40 2273 if (!has_xcrs) {
f1665b21 2274 return 0;
b9bec74b 2275 }
f1665b21
SY		 2276
2277 xcrs.nr_xcrs = 1;
2278 xcrs.flags = 0;
2279 xcrs.xcrs[0].xcr = 0;
2280 xcrs.xcrs[0].value = env->xcr0;
1bc22652 2281 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
f1665b21
SY		 2282}
2283
1bc22652 2284static int kvm_put_sregs(X86CPU *cpu)
05330448 2285{
1bc22652 2286 CPUX86State *env = &cpu->env;
05330448
AL		 2287 struct kvm_sregs sregs;
2288
0e607a80
JK		 2289 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
2290 if (env->interrupt_injected >= 0) {
2291 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
2292 (uint64_t)1 << (env->interrupt_injected % 64);
2293 }
05330448
AL		 2294
2295 if ((env->eflags & VM_MASK)) {
b9bec74b
JK		 2296 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
2297 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
2298 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
2299 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
2300 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
2301 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
05330448 2302 } else {
b9bec74b
JK		 2303 set_seg(&sregs.cs, &env->segs[R_CS]);
2304 set_seg(&sregs.ds, &env->segs[R_DS]);
2305 set_seg(&sregs.es, &env->segs[R_ES]);
2306 set_seg(&sregs.fs, &env->segs[R_FS]);
2307 set_seg(&sregs.gs, &env->segs[R_GS]);
2308 set_seg(&sregs.ss, &env->segs[R_SS]);
05330448
AL		 2309 }
2310
2311 set_seg(&sregs.tr, &env->tr);
2312 set_seg(&sregs.ldt, &env->ldt);
2313
2314 sregs.idt.limit = env->idt.limit;
2315 sregs.idt.base = env->idt.base;
7e680753 2316 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
05330448
AL		 2317 sregs.gdt.limit = env->gdt.limit;
2318 sregs.gdt.base = env->gdt.base;
7e680753 2319 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
05330448
AL		 2320
2321 sregs.cr0 = env->cr[0];
2322 sregs.cr2 = env->cr[2];
2323 sregs.cr3 = env->cr[3];
2324 sregs.cr4 = env->cr[4];
2325
02e51483
CF		 2326 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
2327 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
05330448
AL		 2328
2329 sregs.efer = env->efer;
2330
1bc22652 2331 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
05330448
AL		 2332}
2333
d71b62a1
EH		 2334static void kvm_msr_buf_reset(X86CPU *cpu)
2335{
2336 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
2337}
2338
9c600a84
EH		 2339static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
2340{
2341 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
2342 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
2343 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
2344
2345 assert((void *)(entry + 1) <= limit);
2346
1abc2cae
EH		 2347 entry->index = index;
2348 entry->reserved = 0;
2349 entry->data = value;
9c600a84
EH		 2350 msrs->nmsrs++;
2351}
2352
73e1b8f2
PB		 2353static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
2354{
2355 kvm_msr_buf_reset(cpu);
2356 kvm_msr_entry_add(cpu, index, value);
2357
2358 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
2359}
2360
f8d9ccf8
DDAG		 2361void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
2362{
2363 int ret;
2364
2365 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
2366 assert(ret == 1);
2367}
2368
7477cd38
MT		 2369static int kvm_put_tscdeadline_msr(X86CPU *cpu)
2370{
2371 CPUX86State *env = &cpu->env;
48e1a45c 2372 int ret;
7477cd38
MT		 2373
2374 if (!has_msr_tsc_deadline) {
2375 return 0;
2376 }
2377
73e1b8f2 2378 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
48e1a45c
PB		 2379 if (ret < 0) {
2380 return ret;
2381 }
2382
2383 assert(ret == 1);
2384 return 0;
7477cd38
MT		 2385}
2386
6bdf863d
JK		 2387/*
2388 * Provide a separate write service for the feature control MSR in order to
2389 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
2390 * before writing any other state because forcibly leaving nested mode
2391 * invalidates the VCPU state.
2392 */
2393static int kvm_put_msr_feature_control(X86CPU *cpu)
2394{
48e1a45c
PB		 2395 int ret;
2396
2397 if (!has_msr_feature_control) {
2398 return 0;
2399 }
6bdf863d 2400
73e1b8f2
PB		 2401 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
2402 cpu->env.msr_ia32_feature_control);
48e1a45c
PB		 2403 if (ret < 0) {
2404 return ret;
2405 }
2406
2407 assert(ret == 1);
2408 return 0;
6bdf863d
JK		 2409}
2410
1bc22652 2411static int kvm_put_msrs(X86CPU *cpu, int level)
05330448 2412{
1bc22652 2413 CPUX86State *env = &cpu->env;
9c600a84 2414 int i;
48e1a45c 2415 int ret;
05330448 2416
d71b62a1
EH		 2417 kvm_msr_buf_reset(cpu);
2418
9c600a84
EH		 2419 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
2420 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
2421 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
2422 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
c3a3a7d3 2423 if (has_msr_star) {
9c600a84 2424 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
b9bec74b 2425 }
c3a3a7d3 2426 if (has_msr_hsave_pa) {
9c600a84 2427 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
b9bec74b 2428 }
c9b8f6b6 2429 if (has_msr_tsc_aux) {
9c600a84 2430 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
c9b8f6b6 2431 }
f28558d3 2432 if (has_msr_tsc_adjust) {
9c600a84 2433 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
f28558d3 2434 }
21e87c46 2435 if (has_msr_misc_enable) {
9c600a84 2436 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
21e87c46
AK		 2437 env->msr_ia32_misc_enable);
2438 }
fc12d72e 2439 if (has_msr_smbase) {
9c600a84 2440 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
fc12d72e 2441 }
e13713db
LA		 2442 if (has_msr_smi_count) {
2443 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, env->msr_smi_count);
2444 }
439d19f2 2445 if (has_msr_bndcfgs) {
9c600a84 2446 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
439d19f2 2447 }
18cd2c17 2448 if (has_msr_xss) {
9c600a84 2449 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
18cd2c17 2450 }
a33a2cfe
PB		 2451 if (has_msr_spec_ctrl) {
2452 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
2453 }
cfeea0c0
KRW		 2454 if (has_msr_virt_ssbd) {
2455 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd);
2456 }
2457
05330448 2458#ifdef TARGET_X86_64
25d2e361 2459 if (lm_capable_kernel) {
9c600a84
EH		 2460 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
2461 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
2462 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
2463 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
25d2e361 2464 }
05330448 2465#endif
a33a2cfe 2466
d86f9636 2467 /* If host supports feature MSR, write down. */
aec5e9c3
BD		 2468 if (has_msr_arch_capabs) {
2469 kvm_msr_entry_add(cpu, MSR_IA32_ARCH_CAPABILITIES,
2470 env->features[FEAT_ARCH_CAPABILITIES]);
d86f9636
RH		 2471 }
2472
597360c0
XL		 2473 if (has_msr_core_capabs) {
2474 kvm_msr_entry_add(cpu, MSR_IA32_CORE_CAPABILITY,
2475 env->features[FEAT_CORE_CAPABILITY]);
2476 }
2477
ff5c186b 2478 /*
0d894367
PB		 2479 * The following MSRs have side effects on the guest or are too heavy
2480 * for normal writeback. Limit them to reset or full state updates.
ff5c186b
JK		 2481 */
2482 if (level >= KVM_PUT_RESET_STATE) {
9c600a84
EH		 2483 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
2484 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
2485 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
55c911a5 2486 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
9c600a84 2487 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
c5999bfc 2488 }
55c911a5 2489 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 2490 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
bc9a839d 2491 }
55c911a5 2492 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 2493 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
917367aa 2494 }
0b368a10
JD		 2495 if (has_architectural_pmu_version > 0) {
2496 if (has_architectural_pmu_version > 1) {
2497 /* Stop the counter. */
2498 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2499 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2500 }
0d894367
PB		 2501
2502 /* Set the counter values. */
0b368a10 2503 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
9c600a84 2504 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
0d894367
PB		 2505 env->msr_fixed_counters[i]);
2506 }
0b368a10 2507 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
9c600a84 2508 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
0d894367 2509 env->msr_gp_counters[i]);
9c600a84 2510 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
0d894367
PB		 2511 env->msr_gp_evtsel[i]);
2512 }
0b368a10
JD		 2513 if (has_architectural_pmu_version > 1) {
2514 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
2515 env->msr_global_status);
2516 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
2517 env->msr_global_ovf_ctrl);
2518
2519 /* Now start the PMU. */
2520 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
2521 env->msr_fixed_ctr_ctrl);
2522 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
2523 env->msr_global_ctrl);
2524 }
0d894367 2525 }
da1cc323
EY		 2526 /*
2527 * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add,
2528 * only sync them to KVM on the first cpu
2529 */
2530 if (current_cpu == first_cpu) {
2531 if (has_msr_hv_hypercall) {
2532 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
2533 env->msr_hv_guest_os_id);
2534 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
2535 env->msr_hv_hypercall);
2536 }
2d384d7c 2537 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) {
da1cc323
EY		 2538 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC,
2539 env->msr_hv_tsc);
2540 }
2d384d7c 2541 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) {
ba6a4fd9
VK		 2542 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL,
2543 env->msr_hv_reenlightenment_control);
2544 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL,
2545 env->msr_hv_tsc_emulation_control);
2546 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS,
2547 env->msr_hv_tsc_emulation_status);
2548 }
eab70139 2549 }
2d384d7c 2550 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
9c600a84 2551 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
5ef68987 2552 env->msr_hv_vapic);
eab70139 2553 }
f2a53c9e
AS		 2554 if (has_msr_hv_crash) {
2555 int j;
2556
5e953812 2557 for (j = 0; j < HV_CRASH_PARAMS; j++)
9c600a84 2558 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
f2a53c9e
AS		 2559 env->msr_hv_crash_params[j]);
2560
5e953812 2561 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_NOTIFY);
f2a53c9e 2562 }
46eb8f98 2563 if (has_msr_hv_runtime) {
9c600a84 2564 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
46eb8f98 2565 }
2d384d7c
VK		 2566 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)
2567 && hv_vpindex_settable) {
701189e3
RK		 2568 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_INDEX,
2569 hyperv_vp_index(CPU(cpu)));
e9688fab 2570 }
2d384d7c 2571 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
866eea9a
AS		 2572 int j;
2573
09df29b6
RK		 2574 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, HV_SYNIC_VERSION);
2575
9c600a84 2576 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
866eea9a 2577 env->msr_hv_synic_control);
9c600a84 2578 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
866eea9a 2579 env->msr_hv_synic_evt_page);
9c600a84 2580 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
866eea9a
AS		 2581 env->msr_hv_synic_msg_page);
2582
2583 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
9c600a84 2584 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
866eea9a
AS		 2585 env->msr_hv_synic_sint[j]);
2586 }
2587 }
ff99aa64
AS		 2588 if (has_msr_hv_stimer) {
2589 int j;
2590
2591 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
9c600a84 2592 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
ff99aa64
AS		 2593 env->msr_hv_stimer_config[j]);
2594 }
2595
2596 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
9c600a84 2597 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
ff99aa64
AS		 2598 env->msr_hv_stimer_count[j]);
2599 }
2600 }
1eabfce6 2601 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
112dad69
DDAG		 2602 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
2603
9c600a84
EH		 2604 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
2605 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
2606 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
2607 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
2608 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
2609 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
2610 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
2611 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
2612 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
2613 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
2614 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
2615 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
d1ae67f6 2616 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
112dad69
DDAG		 2617 /* The CPU GPs if we write to a bit above the physical limit of
2618 * the host CPU (and KVM emulates that)
2619 */
2620 uint64_t mask = env->mtrr_var[i].mask;
2621 mask &= phys_mask;
2622
9c600a84
EH		 2623 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
2624 env->mtrr_var[i].base);
112dad69 2625 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
d1ae67f6
AW		 2626 }
2627 }
b77146e9
CP		 2628 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
2629 int addr_num = kvm_arch_get_supported_cpuid(kvm_state,
2630 0x14, 1, R_EAX) & 0x7;
2631
2632 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL,
2633 env->msr_rtit_ctrl);
2634 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS,
2635 env->msr_rtit_status);
2636 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE,
2637 env->msr_rtit_output_base);
2638 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK,
2639 env->msr_rtit_output_mask);
2640 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH,
2641 env->msr_rtit_cr3_match);
2642 for (i = 0; i < addr_num; i++) {
2643 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i,
2644 env->msr_rtit_addrs[i]);
2645 }
2646 }
6bdf863d
JK		 2647
2648 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
2649 * kvm_put_msr_feature_control. */
ea643051 2650 }
57780495 2651 if (env->mcg_cap) {
d8da8574 2652 int i;
b9bec74b 2653
9c600a84
EH		 2654 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
2655 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
87f8b626
AR		 2656 if (has_msr_mcg_ext_ctl) {
2657 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
2658 }
c34d440a 2659 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 2660 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
57780495
MT		 2661 }
2662 }
1a03675d 2663
d71b62a1 2664 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
48e1a45c
PB		 2665 if (ret < 0) {
2666 return ret;
2667 }
05330448 2668
c70b11d1
EH		 2669 if (ret < cpu->kvm_msr_buf->nmsrs) {
2670 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2671 error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
2672 (uint32_t)e->index, (uint64_t)e->data);
2673 }
2674
9c600a84 2675 assert(ret == cpu->kvm_msr_buf->nmsrs);
48e1a45c 2676 return 0;
05330448
AL		 2677}
2678
2679
1bc22652 2680static int kvm_get_fpu(X86CPU *cpu)
05330448 2681{
1bc22652 2682 CPUX86State *env = &cpu->env;
05330448
AL		 2683 struct kvm_fpu fpu;
2684 int i, ret;
2685
1bc22652 2686 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
b9bec74b 2687 if (ret < 0) {
05330448 2688 return ret;
b9bec74b 2689 }
05330448
AL		 2690
2691 env->fpstt = (fpu.fsw >> 11) & 7;
2692 env->fpus = fpu.fsw;
2693 env->fpuc = fpu.fcw;
42cc8fa6
JK		 2694 env->fpop = fpu.last_opcode;
2695 env->fpip = fpu.last_ip;
2696 env->fpdp = fpu.last_dp;
b9bec74b
JK		 2697 for (i = 0; i < 8; ++i) {
2698 env->fptags[i] = !((fpu.ftwx >> i) & 1);
2699 }
05330448 2700 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
bee81887 2701 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 2702 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
2703 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
bee81887 2704 }
05330448
AL		 2705 env->mxcsr = fpu.mxcsr;
2706
2707 return 0;
2708}
2709
1bc22652 2710static int kvm_get_xsave(X86CPU *cpu)
f1665b21 2711{
1bc22652 2712 CPUX86State *env = &cpu->env;
5b8063c4 2713 X86XSaveArea *xsave = env->xsave_buf;
86a57621 2714 int ret;
f1665b21 2715
28143b40 2716 if (!has_xsave) {
1bc22652 2717 return kvm_get_fpu(cpu);
b9bec74b 2718 }
f1665b21 2719
1bc22652 2720 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
0f53994f 2721 if (ret < 0) {
f1665b21 2722 return ret;
0f53994f 2723 }
86a57621 2724 x86_cpu_xrstor_all_areas(cpu, xsave);
f1665b21 2725
f1665b21 2726 return 0;
f1665b21
SY		 2727}
2728
1bc22652 2729static int kvm_get_xcrs(X86CPU *cpu)
f1665b21 2730{
1bc22652 2731 CPUX86State *env = &cpu->env;
f1665b21
SY		 2732 int i, ret;
2733 struct kvm_xcrs xcrs;
2734
28143b40 2735 if (!has_xcrs) {
f1665b21 2736 return 0;
b9bec74b 2737 }
f1665b21 2738
1bc22652 2739 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
b9bec74b 2740 if (ret < 0) {
f1665b21 2741 return ret;
b9bec74b 2742 }
f1665b21 2743
b9bec74b 2744 for (i = 0; i < xcrs.nr_xcrs; i++) {
f1665b21 2745 /* Only support xcr0 now */
0fd53fec
PB		 2746 if (xcrs.xcrs[i].xcr == 0) {
2747 env->xcr0 = xcrs.xcrs[i].value;
f1665b21
SY		 2748 break;
2749 }
b9bec74b 2750 }
f1665b21 2751 return 0;
f1665b21
SY		 2752}
2753
1bc22652 2754static int kvm_get_sregs(X86CPU *cpu)
05330448 2755{
1bc22652 2756 CPUX86State *env = &cpu->env;
05330448 2757 struct kvm_sregs sregs;
0e607a80 2758 int bit, i, ret;
05330448 2759
1bc22652 2760 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
b9bec74b 2761 if (ret < 0) {
05330448 2762 return ret;
b9bec74b 2763 }
05330448 2764
0e607a80
JK		 2765 /* There can only be one pending IRQ set in the bitmap at a time, so try
2766 to find it and save its number instead (-1 for none). */
2767 env->interrupt_injected = -1;
2768 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
2769 if (sregs.interrupt_bitmap[i]) {
2770 bit = ctz64(sregs.interrupt_bitmap[i]);
2771 env->interrupt_injected = i * 64 + bit;
2772 break;
2773 }
2774 }
05330448
AL		 2775
2776 get_seg(&env->segs[R_CS], &sregs.cs);
2777 get_seg(&env->segs[R_DS], &sregs.ds);
2778 get_seg(&env->segs[R_ES], &sregs.es);
2779 get_seg(&env->segs[R_FS], &sregs.fs);
2780 get_seg(&env->segs[R_GS], &sregs.gs);
2781 get_seg(&env->segs[R_SS], &sregs.ss);
2782
2783 get_seg(&env->tr, &sregs.tr);
2784 get_seg(&env->ldt, &sregs.ldt);
2785
2786 env->idt.limit = sregs.idt.limit;
2787 env->idt.base = sregs.idt.base;
2788 env->gdt.limit = sregs.gdt.limit;
2789 env->gdt.base = sregs.gdt.base;
2790
2791 env->cr[0] = sregs.cr0;
2792 env->cr[2] = sregs.cr2;
2793 env->cr[3] = sregs.cr3;
2794 env->cr[4] = sregs.cr4;
2795
05330448 2796 env->efer = sregs.efer;
cce47516
JK		 2797
2798 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
35b1b927 2799 x86_update_hflags(env);
05330448
AL		 2800
2801 return 0;
2802}
2803
1bc22652 2804static int kvm_get_msrs(X86CPU *cpu)
05330448 2805{
1bc22652 2806 CPUX86State *env = &cpu->env;
d71b62a1 2807 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
9c600a84 2808 int ret, i;
fcc35e7c 2809 uint64_t mtrr_top_bits;
05330448 2810
d71b62a1
EH		 2811 kvm_msr_buf_reset(cpu);
2812
9c600a84
EH		 2813 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
2814 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
2815 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
2816 kvm_msr_entry_add(cpu, MSR_PAT, 0);
c3a3a7d3 2817 if (has_msr_star) {
9c600a84 2818 kvm_msr_entry_add(cpu, MSR_STAR, 0);
b9bec74b 2819 }
c3a3a7d3 2820 if (has_msr_hsave_pa) {
9c600a84 2821 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
b9bec74b 2822 }
c9b8f6b6 2823 if (has_msr_tsc_aux) {
9c600a84 2824 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
c9b8f6b6 2825 }
f28558d3 2826 if (has_msr_tsc_adjust) {
9c600a84 2827 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
f28558d3 2828 }
aa82ba54 2829 if (has_msr_tsc_deadline) {
9c600a84 2830 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
aa82ba54 2831 }
21e87c46 2832 if (has_msr_misc_enable) {
9c600a84 2833 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
21e87c46 2834 }
fc12d72e 2835 if (has_msr_smbase) {
9c600a84 2836 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
fc12d72e 2837 }
e13713db
LA		 2838 if (has_msr_smi_count) {
2839 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, 0);
2840 }
df67696e 2841 if (has_msr_feature_control) {
9c600a84 2842 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
df67696e 2843 }
79e9ebeb 2844 if (has_msr_bndcfgs) {
9c600a84 2845 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
79e9ebeb 2846 }
18cd2c17 2847 if (has_msr_xss) {
9c600a84 2848 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
18cd2c17 2849 }
a33a2cfe
PB		 2850 if (has_msr_spec_ctrl) {
2851 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
2852 }
cfeea0c0
KRW		 2853 if (has_msr_virt_ssbd) {
2854 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0);
2855 }
b8cc45d6 2856 if (!env->tsc_valid) {
9c600a84 2857 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
1354869c 2858 env->tsc_valid = !runstate_is_running();
b8cc45d6
GC		 2859 }
2860
05330448 2861#ifdef TARGET_X86_64
25d2e361 2862 if (lm_capable_kernel) {
9c600a84
EH		 2863 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
2864 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
2865 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
2866 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
25d2e361 2867 }
05330448 2868#endif
9c600a84
EH		 2869 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
2870 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
55c911a5 2871 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
9c600a84 2872 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
c5999bfc 2873 }
55c911a5 2874 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 2875 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
bc9a839d 2876 }
55c911a5 2877 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 2878 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
917367aa 2879 }
0b368a10
JD		 2880 if (has_architectural_pmu_version > 0) {
2881 if (has_architectural_pmu_version > 1) {
2882 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2883 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2884 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
2885 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
2886 }
2887 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
9c600a84 2888 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
0d894367 2889 }
0b368a10 2890 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
9c600a84
EH		 2891 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
2892 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
0d894367
PB		 2893 }
2894 }
1a03675d 2895
57780495 2896 if (env->mcg_cap) {
9c600a84
EH		 2897 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
2898 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
87f8b626
AR		 2899 if (has_msr_mcg_ext_ctl) {
2900 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
2901 }
b9bec74b 2902 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 2903 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
b9bec74b 2904 }
57780495 2905 }
57780495 2906
1c90ef26 2907 if (has_msr_hv_hypercall) {
9c600a84
EH		 2908 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
2909 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
1c90ef26 2910 }
2d384d7c 2911 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
9c600a84 2912 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
5ef68987 2913 }
2d384d7c 2914 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) {
9c600a84 2915 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
48a5f3bc 2916 }
2d384d7c 2917 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) {
ba6a4fd9
VK		 2918 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL, 0);
2919 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL, 0);
2920 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS, 0);
2921 }
f2a53c9e
AS		 2922 if (has_msr_hv_crash) {
2923 int j;
2924
5e953812 2925 for (j = 0; j < HV_CRASH_PARAMS; j++) {
9c600a84 2926 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
f2a53c9e
AS		 2927 }
2928 }
46eb8f98 2929 if (has_msr_hv_runtime) {
9c600a84 2930 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
46eb8f98 2931 }
2d384d7c 2932 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
866eea9a
AS		 2933 uint32_t msr;
2934
9c600a84 2935 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
9c600a84
EH		 2936 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
2937 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
866eea9a 2938 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
9c600a84 2939 kvm_msr_entry_add(cpu, msr, 0);
866eea9a
AS		 2940 }
2941 }
ff99aa64
AS		 2942 if (has_msr_hv_stimer) {
2943 uint32_t msr;
2944
2945 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2946 msr++) {
9c600a84 2947 kvm_msr_entry_add(cpu, msr, 0);
ff99aa64
AS		 2948 }
2949 }
1eabfce6 2950 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
9c600a84
EH		 2951 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
2952 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
2953 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
2954 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
2955 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
2956 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
2957 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
2958 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
2959 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
2960 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
2961 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
2962 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
d1ae67f6 2963 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
9c600a84
EH		 2964 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
2965 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
d1ae67f6
AW		 2966 }
2967 }
5ef68987 2968
b77146e9
CP		 2969 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
2970 int addr_num =
2971 kvm_arch_get_supported_cpuid(kvm_state, 0x14, 1, R_EAX) & 0x7;
2972
2973 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 0);
2974 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 0);
2975 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, 0);
2976 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, 0);
2977 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, 0);
2978 for (i = 0; i < addr_num; i++) {
2979 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 0);
2980 }
2981 }
2982
d71b62a1 2983 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
b9bec74b 2984 if (ret < 0) {
05330448 2985 return ret;
b9bec74b 2986 }
05330448 2987
c70b11d1
EH		 2988 if (ret < cpu->kvm_msr_buf->nmsrs) {
2989 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2990 error_report("error: failed to get MSR 0x%" PRIx32,
2991 (uint32_t)e->index);
2992 }
2993
9c600a84 2994 assert(ret == cpu->kvm_msr_buf->nmsrs);
fcc35e7c
DDAG		 2995 /*
2996 * MTRR masks: Each mask consists of 5 parts
2997 * a 10..0: must be zero
2998 * b 11 : valid bit
2999 * c n-1.12: actual mask bits
3000 * d 51..n: reserved must be zero
3001 * e 63.52: reserved must be zero
3002 *
3003 * 'n' is the number of physical bits supported by the CPU and is
3004 * apparently always <= 52. We know our 'n' but don't know what
3005 * the destinations 'n' is; it might be smaller, in which case
3006 * it masks (c) on loading. It might be larger, in which case
3007 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
3008 * we're migrating to.
3009 */
3010
3011 if (cpu->fill_mtrr_mask) {
3012 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
3013 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
3014 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
3015 } else {
3016 mtrr_top_bits = 0;
3017 }
3018
05330448 3019 for (i = 0; i < ret; i++) {
0d894367
PB		 3020 uint32_t index = msrs[i].index;
3021 switch (index) {
05330448
AL		 3022 case MSR_IA32_SYSENTER_CS:
3023 env->sysenter_cs = msrs[i].data;
3024 break;
3025 case MSR_IA32_SYSENTER_ESP:
3026 env->sysenter_esp = msrs[i].data;
3027 break;
3028 case MSR_IA32_SYSENTER_EIP:
3029 env->sysenter_eip = msrs[i].data;
3030 break;
0c03266a
JK		 3031 case MSR_PAT:
3032 env->pat = msrs[i].data;
3033 break;
05330448
AL		 3034 case MSR_STAR:
3035 env->star = msrs[i].data;
3036 break;
3037#ifdef TARGET_X86_64
3038 case MSR_CSTAR:
3039 env->cstar = msrs[i].data;
3040 break;
3041 case MSR_KERNELGSBASE:
3042 env->kernelgsbase = msrs[i].data;
3043 break;
3044 case MSR_FMASK:
3045 env->fmask = msrs[i].data;
3046 break;
3047 case MSR_LSTAR:
3048 env->lstar = msrs[i].data;
3049 break;
3050#endif
3051 case MSR_IA32_TSC:
3052 env->tsc = msrs[i].data;
3053 break;
c9b8f6b6
AS		 3054 case MSR_TSC_AUX:
3055 env->tsc_aux = msrs[i].data;
3056 break;
f28558d3
WA		 3057 case MSR_TSC_ADJUST:
3058 env->tsc_adjust = msrs[i].data;
3059 break;
aa82ba54
LJ		 3060 case MSR_IA32_TSCDEADLINE:
3061 env->tsc_deadline = msrs[i].data;
3062 break;
aa851e36
MT		 3063 case MSR_VM_HSAVE_PA:
3064 env->vm_hsave = msrs[i].data;
3065 break;
1a03675d
GC		 3066 case MSR_KVM_SYSTEM_TIME:
3067 env->system_time_msr = msrs[i].data;
3068 break;
3069 case MSR_KVM_WALL_CLOCK:
3070 env->wall_clock_msr = msrs[i].data;
3071 break;
57780495
MT		 3072 case MSR_MCG_STATUS:
3073 env->mcg_status = msrs[i].data;
3074 break;
3075 case MSR_MCG_CTL:
3076 env->mcg_ctl = msrs[i].data;
3077 break;
87f8b626
AR		 3078 case MSR_MCG_EXT_CTL:
3079 env->mcg_ext_ctl = msrs[i].data;
3080 break;
21e87c46
AK		 3081 case MSR_IA32_MISC_ENABLE:
3082 env->msr_ia32_misc_enable = msrs[i].data;
3083 break;
fc12d72e
PB		 3084 case MSR_IA32_SMBASE:
3085 env->smbase = msrs[i].data;
3086 break;
e13713db
LA		 3087 case MSR_SMI_COUNT:
3088 env->msr_smi_count = msrs[i].data;
3089 break;
0779caeb
ACL		 3090 case MSR_IA32_FEATURE_CONTROL:
3091 env->msr_ia32_feature_control = msrs[i].data;
df67696e 3092 break;
79e9ebeb
LJ		 3093 case MSR_IA32_BNDCFGS:
3094 env->msr_bndcfgs = msrs[i].data;
3095 break;
18cd2c17
WL		 3096 case MSR_IA32_XSS:
3097 env->xss = msrs[i].data;
3098 break;
57780495 3099 default:
57780495
MT		 3100 if (msrs[i].index >= MSR_MC0_CTL &&
3101 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
3102 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
57780495 3103 }
d8da8574 3104 break;
f6584ee2
GN		 3105 case MSR_KVM_ASYNC_PF_EN:
3106 env->async_pf_en_msr = msrs[i].data;
3107 break;
bc9a839d
MT		 3108 case MSR_KVM_PV_EOI_EN:
3109 env->pv_eoi_en_msr = msrs[i].data;
3110 break;
917367aa
MT		 3111 case MSR_KVM_STEAL_TIME:
3112 env->steal_time_msr = msrs[i].data;
3113 break;
0d894367
PB		 3114 case MSR_CORE_PERF_FIXED_CTR_CTRL:
3115 env->msr_fixed_ctr_ctrl = msrs[i].data;
3116 break;
3117 case MSR_CORE_PERF_GLOBAL_CTRL:
3118 env->msr_global_ctrl = msrs[i].data;
3119 break;
3120 case MSR_CORE_PERF_GLOBAL_STATUS:
3121 env->msr_global_status = msrs[i].data;
3122 break;
3123 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
3124 env->msr_global_ovf_ctrl = msrs[i].data;
3125 break;
3126 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
3127 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
3128 break;
3129 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
3130 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
3131 break;
3132 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
3133 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
3134 break;
1c90ef26
VR		 3135 case HV_X64_MSR_HYPERCALL:
3136 env->msr_hv_hypercall = msrs[i].data;
3137 break;
3138 case HV_X64_MSR_GUEST_OS_ID:
3139 env->msr_hv_guest_os_id = msrs[i].data;
3140 break;
5ef68987
VR		 3141 case HV_X64_MSR_APIC_ASSIST_PAGE:
3142 env->msr_hv_vapic = msrs[i].data;
3143 break;
48a5f3bc
VR		 3144 case HV_X64_MSR_REFERENCE_TSC:
3145 env->msr_hv_tsc = msrs[i].data;
3146 break;
f2a53c9e
AS		 3147 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3148 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
3149 break;
46eb8f98
AS		 3150 case HV_X64_MSR_VP_RUNTIME:
3151 env->msr_hv_runtime = msrs[i].data;
3152 break;
866eea9a
AS		 3153 case HV_X64_MSR_SCONTROL:
3154 env->msr_hv_synic_control = msrs[i].data;
3155 break;
866eea9a
AS		 3156 case HV_X64_MSR_SIEFP:
3157 env->msr_hv_synic_evt_page = msrs[i].data;
3158 break;
3159 case HV_X64_MSR_SIMP:
3160 env->msr_hv_synic_msg_page = msrs[i].data;
3161 break;
3162 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
3163 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
ff99aa64
AS		 3164 break;
3165 case HV_X64_MSR_STIMER0_CONFIG:
3166 case HV_X64_MSR_STIMER1_CONFIG:
3167 case HV_X64_MSR_STIMER2_CONFIG:
3168 case HV_X64_MSR_STIMER3_CONFIG:
3169 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
3170 msrs[i].data;
3171 break;
3172 case HV_X64_MSR_STIMER0_COUNT:
3173 case HV_X64_MSR_STIMER1_COUNT:
3174 case HV_X64_MSR_STIMER2_COUNT:
3175 case HV_X64_MSR_STIMER3_COUNT:
3176 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
3177 msrs[i].data;
866eea9a 3178 break;
ba6a4fd9
VK		 3179 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3180 env->msr_hv_reenlightenment_control = msrs[i].data;
3181 break;
3182 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3183 env->msr_hv_tsc_emulation_control = msrs[i].data;
3184 break;
3185 case HV_X64_MSR_TSC_EMULATION_STATUS:
3186 env->msr_hv_tsc_emulation_status = msrs[i].data;
3187 break;
d1ae67f6
AW		 3188 case MSR_MTRRdefType:
3189 env->mtrr_deftype = msrs[i].data;
3190 break;
3191 case MSR_MTRRfix64K_00000:
3192 env->mtrr_fixed[0] = msrs[i].data;
3193 break;
3194 case MSR_MTRRfix16K_80000:
3195 env->mtrr_fixed[1] = msrs[i].data;
3196 break;
3197 case MSR_MTRRfix16K_A0000:
3198 env->mtrr_fixed[2] = msrs[i].data;
3199 break;
3200 case MSR_MTRRfix4K_C0000:
3201 env->mtrr_fixed[3] = msrs[i].data;
3202 break;
3203 case MSR_MTRRfix4K_C8000:
3204 env->mtrr_fixed[4] = msrs[i].data;
3205 break;
3206 case MSR_MTRRfix4K_D0000:
3207 env->mtrr_fixed[5] = msrs[i].data;
3208 break;
3209 case MSR_MTRRfix4K_D8000:
3210 env->mtrr_fixed[6] = msrs[i].data;
3211 break;
3212 case MSR_MTRRfix4K_E0000:
3213 env->mtrr_fixed[7] = msrs[i].data;
3214 break;
3215 case MSR_MTRRfix4K_E8000:
3216 env->mtrr_fixed[8] = msrs[i].data;
3217 break;
3218 case MSR_MTRRfix4K_F0000:
3219 env->mtrr_fixed[9] = msrs[i].data;
3220 break;
3221 case MSR_MTRRfix4K_F8000:
3222 env->mtrr_fixed[10] = msrs[i].data;
3223 break;
3224 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
3225 if (index & 1) {
fcc35e7c
DDAG		 3226 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
3227 mtrr_top_bits;
d1ae67f6
AW		 3228 } else {
3229 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
3230 }
3231 break;
a33a2cfe
PB		 3232 case MSR_IA32_SPEC_CTRL:
3233 env->spec_ctrl = msrs[i].data;
3234 break;
cfeea0c0
KRW		 3235 case MSR_VIRT_SSBD:
3236 env->virt_ssbd = msrs[i].data;
3237 break;
b77146e9
CP		 3238 case MSR_IA32_RTIT_CTL:
3239 env->msr_rtit_ctrl = msrs[i].data;
3240 break;
3241 case MSR_IA32_RTIT_STATUS:
3242 env->msr_rtit_status = msrs[i].data;
3243 break;
3244 case MSR_IA32_RTIT_OUTPUT_BASE:
3245 env->msr_rtit_output_base = msrs[i].data;
3246 break;
3247 case MSR_IA32_RTIT_OUTPUT_MASK:
3248 env->msr_rtit_output_mask = msrs[i].data;
3249 break;
3250 case MSR_IA32_RTIT_CR3_MATCH:
3251 env->msr_rtit_cr3_match = msrs[i].data;
3252 break;
3253 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
3254 env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] = msrs[i].data;
3255 break;
05330448
AL		 3256 }
3257 }
3258
3259 return 0;
3260}
3261
1bc22652 3262static int kvm_put_mp_state(X86CPU *cpu)
9bdbe550 3263{
1bc22652 3264 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
9bdbe550 3265
1bc22652 3266 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
9bdbe550
HB		 3267}
3268
23d02d9b 3269static int kvm_get_mp_state(X86CPU *cpu)
9bdbe550 3270{
259186a7 3271 CPUState *cs = CPU(cpu);
23d02d9b 3272 CPUX86State *env = &cpu->env;
9bdbe550
HB		 3273 struct kvm_mp_state mp_state;
3274 int ret;
3275
259186a7 3276 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
9bdbe550
HB		 3277 if (ret < 0) {
3278 return ret;
3279 }
3280 env->mp_state = mp_state.mp_state;
c14750e8 3281 if (kvm_irqchip_in_kernel()) {
259186a7 3282 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
c14750e8 3283 }
9bdbe550
HB		 3284 return 0;
3285}
3286
1bc22652 3287static int kvm_get_apic(X86CPU *cpu)
680c1c6f 3288{
02e51483 3289 DeviceState *apic = cpu->apic_state;
680c1c6f
JK		 3290 struct kvm_lapic_state kapic;
3291 int ret;
3292
3d4b2649 3293 if (apic && kvm_irqchip_in_kernel()) {
1bc22652 3294 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
680c1c6f
JK		 3295 if (ret < 0) {
3296 return ret;
3297 }
3298
3299 kvm_get_apic_state(apic, &kapic);
3300 }
3301 return 0;
3302}
3303
1bc22652 3304static int kvm_put_vcpu_events(X86CPU *cpu, int level)
a0fb002c 3305{
fc12d72e 3306 CPUState *cs = CPU(cpu);
1bc22652 3307 CPUX86State *env = &cpu->env;
076796f8 3308 struct kvm_vcpu_events events = {};
a0fb002c
JK		 3309
3310 if (!kvm_has_vcpu_events()) {
3311 return 0;
3312 }
3313
fd13f23b
LA		 3314 events.flags = 0;
3315
3316 if (has_exception_payload) {
3317 events.flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
3318 events.exception.pending = env->exception_pending;
3319 events.exception_has_payload = env->exception_has_payload;
3320 events.exception_payload = env->exception_payload;
3321 }
3322 events.exception.nr = env->exception_nr;
3323 events.exception.injected = env->exception_injected;
a0fb002c
JK		 3324 events.exception.has_error_code = env->has_error_code;
3325 events.exception.error_code = env->error_code;
3326
3327 events.interrupt.injected = (env->interrupt_injected >= 0);
3328 events.interrupt.nr = env->interrupt_injected;
3329 events.interrupt.soft = env->soft_interrupt;
3330
3331 events.nmi.injected = env->nmi_injected;
3332 events.nmi.pending = env->nmi_pending;
3333 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
3334
3335 events.sipi_vector = env->sipi_vector;
3336
fc12d72e
PB		 3337 if (has_msr_smbase) {
3338 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
3339 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
3340 if (kvm_irqchip_in_kernel()) {
3341 /* As soon as these are moved to the kernel, remove them
3342 * from cs->interrupt_request.
3343 */
3344 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
3345 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
3346 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
3347 } else {
3348 /* Keep these in cs->interrupt_request. */
3349 events.smi.pending = 0;
3350 events.smi.latched_init = 0;
3351 }
fc3a1fd7
DDAG		 3352 /* Stop SMI delivery on old machine types to avoid a reboot
3353 * on an inward migration of an old VM.
3354 */
3355 if (!cpu->kvm_no_smi_migration) {
3356 events.flags |= KVM_VCPUEVENT_VALID_SMM;
3357 }
fc12d72e
PB		 3358 }
3359
ea643051 3360 if (level >= KVM_PUT_RESET_STATE) {
4fadfa00
PH		 3361 events.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING;
3362 if (env->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
3363 events.flags |= KVM_VCPUEVENT_VALID_SIPI_VECTOR;
3364 }
ea643051 3365 }
aee028b9 3366
1bc22652 3367 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
a0fb002c
JK		 3368}
3369
1bc22652 3370static int kvm_get_vcpu_events(X86CPU *cpu)
a0fb002c 3371{
1bc22652 3372 CPUX86State *env = &cpu->env;
a0fb002c
JK		 3373 struct kvm_vcpu_events events;
3374 int ret;
3375
3376 if (!kvm_has_vcpu_events()) {
3377 return 0;
3378 }
3379
fc12d72e 3380 memset(&events, 0, sizeof(events));
1bc22652 3381 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
a0fb002c
JK		 3382 if (ret < 0) {
3383 return ret;
3384 }
fd13f23b
LA		 3385
3386 if (events.flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
3387 env->exception_pending = events.exception.pending;
3388 env->exception_has_payload = events.exception_has_payload;
3389 env->exception_payload = events.exception_payload;
3390 } else {
3391 env->exception_pending = 0;
3392 env->exception_has_payload = false;
3393 }
3394 env->exception_injected = events.exception.injected;
3395 env->exception_nr =
3396 (env->exception_pending || env->exception_injected) ?
3397 events.exception.nr : -1;
a0fb002c
JK		 3398 env->has_error_code = events.exception.has_error_code;
3399 env->error_code = events.exception.error_code;
3400
3401 env->interrupt_injected =
3402 events.interrupt.injected ? events.interrupt.nr : -1;
3403 env->soft_interrupt = events.interrupt.soft;
3404
3405 env->nmi_injected = events.nmi.injected;
3406 env->nmi_pending = events.nmi.pending;
3407 if (events.nmi.masked) {
3408 env->hflags2 |= HF2_NMI_MASK;
3409 } else {
3410 env->hflags2 &= ~HF2_NMI_MASK;
3411 }
3412
fc12d72e
PB		 3413 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
3414 if (events.smi.smm) {
3415 env->hflags |= HF_SMM_MASK;
3416 } else {
3417 env->hflags &= ~HF_SMM_MASK;
3418 }
3419 if (events.smi.pending) {
3420 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
3421 } else {
3422 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
3423 }
3424 if (events.smi.smm_inside_nmi) {
3425 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
3426 } else {
3427 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
3428 }
3429 if (events.smi.latched_init) {
3430 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
3431 } else {
3432 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
3433 }
3434 }
3435
a0fb002c 3436 env->sipi_vector = events.sipi_vector;
a0fb002c
JK		 3437
3438 return 0;
3439}
3440
1bc22652 3441static int kvm_guest_debug_workarounds(X86CPU *cpu)
b0b1d690 3442{
ed2803da 3443 CPUState *cs = CPU(cpu);
1bc22652 3444 CPUX86State *env = &cpu->env;
b0b1d690 3445 int ret = 0;
b0b1d690
JK		 3446 unsigned long reinject_trap = 0;
3447
3448 if (!kvm_has_vcpu_events()) {
fd13f23b 3449 if (env->exception_nr == EXCP01_DB) {
b0b1d690 3450 reinject_trap = KVM_GUESTDBG_INJECT_DB;
37936ac7 3451 } else if (env->exception_injected == EXCP03_INT3) {
b0b1d690
JK		 3452 reinject_trap = KVM_GUESTDBG_INJECT_BP;
3453 }
fd13f23b 3454 kvm_reset_exception(env);
b0b1d690
JK		 3455 }
3456
3457 /*
3458 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
3459 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
3460 * by updating the debug state once again if single-stepping is on.
3461 * Another reason to call kvm_update_guest_debug here is a pending debug
3462 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
3463 * reinject them via SET_GUEST_DEBUG.
3464 */
3465 if (reinject_trap ||
ed2803da 3466 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
38e478ec 3467 ret = kvm_update_guest_debug(cs, reinject_trap);
b0b1d690 3468 }
b0b1d690
JK		 3469 return ret;
3470}
3471
1bc22652 3472static int kvm_put_debugregs(X86CPU *cpu)
ff44f1a3 3473{
1bc22652 3474 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 3475 struct kvm_debugregs dbgregs;
3476 int i;
3477
3478 if (!kvm_has_debugregs()) {
3479 return 0;
3480 }
3481
3482 for (i = 0; i < 4; i++) {
3483 dbgregs.db[i] = env->dr[i];
3484 }
3485 dbgregs.dr6 = env->dr[6];
3486 dbgregs.dr7 = env->dr[7];
3487 dbgregs.flags = 0;
3488
1bc22652 3489 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
ff44f1a3
JK		 3490}
3491
1bc22652 3492static int kvm_get_debugregs(X86CPU *cpu)
ff44f1a3 3493{
1bc22652 3494 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 3495 struct kvm_debugregs dbgregs;
3496 int i, ret;
3497
3498 if (!kvm_has_debugregs()) {
3499 return 0;
3500 }
3501
1bc22652 3502 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
ff44f1a3 3503 if (ret < 0) {
b9bec74b 3504 return ret;
ff44f1a3
JK		 3505 }
3506 for (i = 0; i < 4; i++) {
3507 env->dr[i] = dbgregs.db[i];
3508 }
3509 env->dr[4] = env->dr[6] = dbgregs.dr6;
3510 env->dr[5] = env->dr[7] = dbgregs.dr7;
ff44f1a3
JK		 3511
3512 return 0;
3513}
3514
ebbfef2f
LA		 3515static int kvm_put_nested_state(X86CPU *cpu)
3516{
3517 CPUX86State *env = &cpu->env;
3518 int max_nested_state_len = kvm_max_nested_state_length();
3519
1e44f3ab 3520 if (!env->nested_state) {
ebbfef2f
LA		 3521 return 0;
3522 }
3523
3524 assert(env->nested_state->size <= max_nested_state_len);
3525 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_NESTED_STATE, env->nested_state);
3526}
3527
3528static int kvm_get_nested_state(X86CPU *cpu)
3529{
3530 CPUX86State *env = &cpu->env;
3531 int max_nested_state_len = kvm_max_nested_state_length();
3532 int ret;
3533
1e44f3ab 3534 if (!env->nested_state) {
ebbfef2f
LA		 3535 return 0;
3536 }
3537
3538 /*
3539 * It is possible that migration restored a smaller size into
3540 * nested_state->hdr.size than what our kernel support.
3541 * We preserve migration origin nested_state->hdr.size for
3542 * call to KVM_SET_NESTED_STATE but wish that our next call
3543 * to KVM_GET_NESTED_STATE will use max size our kernel support.
3544 */
3545 env->nested_state->size = max_nested_state_len;
3546
3547 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_NESTED_STATE, env->nested_state);
3548 if (ret < 0) {
3549 return ret;
3550 }
3551
3552 if (env->nested_state->flags & KVM_STATE_NESTED_GUEST_MODE) {
3553 env->hflags |= HF_GUEST_MASK;
3554 } else {
3555 env->hflags &= ~HF_GUEST_MASK;
3556 }
3557
3558 return ret;
3559}
3560
20d695a9 3561int kvm_arch_put_registers(CPUState *cpu, int level)
05330448 3562{
20d695a9 3563 X86CPU *x86_cpu = X86_CPU(cpu);
05330448
AL		 3564 int ret;
3565
2fa45344 3566 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
dbaa07c4 3567
48e1a45c 3568 if (level >= KVM_PUT_RESET_STATE) {
bec7156a
JK		 3569 ret = kvm_put_nested_state(x86_cpu);
3570 if (ret < 0) {
3571 return ret;
3572 }
3573
6bdf863d
JK		 3574 ret = kvm_put_msr_feature_control(x86_cpu);
3575 if (ret < 0) {
3576 return ret;
3577 }
3578 }
3579
36f96c4b
HZ		 3580 if (level == KVM_PUT_FULL_STATE) {
3581 /* We don't check for kvm_arch_set_tsc_khz() errors here,
3582 * because TSC frequency mismatch shouldn't abort migration,
3583 * unless the user explicitly asked for a more strict TSC
3584 * setting (e.g. using an explicit "tsc-freq" option).
3585 */
3586 kvm_arch_set_tsc_khz(cpu);
3587 }
3588
1bc22652 3589 ret = kvm_getput_regs(x86_cpu, 1);
b9bec74b 3590 if (ret < 0) {
05330448 3591 return ret;
b9bec74b 3592 }
1bc22652 3593 ret = kvm_put_xsave(x86_cpu);
b9bec74b 3594 if (ret < 0) {
f1665b21 3595 return ret;
b9bec74b 3596 }
1bc22652 3597 ret = kvm_put_xcrs(x86_cpu);
b9bec74b 3598 if (ret < 0) {
05330448 3599 return ret;
b9bec74b 3600 }
1bc22652 3601 ret = kvm_put_sregs(x86_cpu);
b9bec74b 3602 if (ret < 0) {
05330448 3603 return ret;
b9bec74b 3604 }
ab443475 3605 /* must be before kvm_put_msrs */
1bc22652 3606 ret = kvm_inject_mce_oldstyle(x86_cpu);
ab443475
JK		 3607 if (ret < 0) {
3608 return ret;
3609 }
1bc22652 3610 ret = kvm_put_msrs(x86_cpu, level);
b9bec74b 3611 if (ret < 0) {
05330448 3612 return ret;
b9bec74b 3613 }
4fadfa00
PH		 3614 ret = kvm_put_vcpu_events(x86_cpu, level);
3615 if (ret < 0) {
3616 return ret;
3617 }
ea643051 3618 if (level >= KVM_PUT_RESET_STATE) {
1bc22652 3619 ret = kvm_put_mp_state(x86_cpu);
b9bec74b 3620 if (ret < 0) {
680c1c6f
JK		 3621 return ret;
3622 }
ea643051 3623 }
7477cd38
MT		 3624
3625 ret = kvm_put_tscdeadline_msr(x86_cpu);
3626 if (ret < 0) {
3627 return ret;
3628 }
1bc22652 3629 ret = kvm_put_debugregs(x86_cpu);
b9bec74b 3630 if (ret < 0) {
b0b1d690 3631 return ret;
b9bec74b 3632 }
b0b1d690 3633 /* must be last */
1bc22652 3634 ret = kvm_guest_debug_workarounds(x86_cpu);
b9bec74b 3635 if (ret < 0) {
ff44f1a3 3636 return ret;
b9bec74b 3637 }
05330448
AL		 3638 return 0;
3639}
3640
20d695a9 3641int kvm_arch_get_registers(CPUState *cs)
05330448 3642{
20d695a9 3643 X86CPU *cpu = X86_CPU(cs);
05330448
AL		 3644 int ret;
3645
20d695a9 3646 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
dbaa07c4 3647
4fadfa00 3648 ret = kvm_get_vcpu_events(cpu);
b9bec74b 3649 if (ret < 0) {
f4f1110e 3650 goto out;
b9bec74b 3651 }
4fadfa00
PH		 3652 /*
3653 * KVM_GET_MPSTATE can modify CS and RIP, call it before
3654 * KVM_GET_REGS and KVM_GET_SREGS.
3655 */
3656 ret = kvm_get_mp_state(cpu);
b9bec74b 3657 if (ret < 0) {
f4f1110e 3658 goto out;
b9bec74b 3659 }
4fadfa00 3660 ret = kvm_getput_regs(cpu, 0);
b9bec74b 3661 if (ret < 0) {
f4f1110e 3662 goto out;
b9bec74b 3663 }
4fadfa00 3664 ret = kvm_get_xsave(cpu);
b9bec74b 3665 if (ret < 0) {
f4f1110e 3666 goto out;
b9bec74b 3667 }
4fadfa00 3668 ret = kvm_get_xcrs(cpu);
b9bec74b 3669 if (ret < 0) {
f4f1110e 3670 goto out;
b9bec74b 3671 }
4fadfa00 3672 ret = kvm_get_sregs(cpu);
b9bec74b 3673 if (ret < 0) {
f4f1110e 3674 goto out;
b9bec74b 3675 }
4fadfa00 3676 ret = kvm_get_msrs(cpu);
680c1c6f 3677 if (ret < 0) {
f4f1110e 3678 goto out;
680c1c6f 3679 }
4fadfa00 3680 ret = kvm_get_apic(cpu);
b9bec74b 3681 if (ret < 0) {
f4f1110e 3682 goto out;
b9bec74b 3683 }
1bc22652 3684 ret = kvm_get_debugregs(cpu);
b9bec74b 3685 if (ret < 0) {
f4f1110e 3686 goto out;
b9bec74b 3687 }
ebbfef2f
LA		 3688 ret = kvm_get_nested_state(cpu);
3689 if (ret < 0) {
3690 goto out;
3691 }
f4f1110e
RH		 3692 ret = 0;
3693 out:
3694 cpu_sync_bndcs_hflags(&cpu->env);
3695 return ret;
05330448
AL		 3696}
3697
20d695a9 3698void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
05330448 3699{
20d695a9
AF		 3700 X86CPU *x86_cpu = X86_CPU(cpu);
3701 CPUX86State *env = &x86_cpu->env;
ce377af3
JK		 3702 int ret;
3703
276ce815 3704 /* Inject NMI */
fc12d72e
PB		 3705 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
3706 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
3707 qemu_mutex_lock_iothread();
3708 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
3709 qemu_mutex_unlock_iothread();
3710 DPRINTF("injected NMI\n");
3711 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
3712 if (ret < 0) {
3713 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
3714 strerror(-ret));
3715 }
3716 }
3717 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
3718 qemu_mutex_lock_iothread();
3719 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
3720 qemu_mutex_unlock_iothread();
3721 DPRINTF("injected SMI\n");
3722 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
3723 if (ret < 0) {
3724 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
3725 strerror(-ret));
3726 }
ce377af3 3727 }
276ce815
LJ		 3728 }
3729
15eafc2e 3730 if (!kvm_pic_in_kernel()) {
4b8523ee
JK		 3731 qemu_mutex_lock_iothread();
3732 }
3733
e0723c45
PB		 3734 /* Force the VCPU out of its inner loop to process any INIT requests
3735 * or (for userspace APIC, but it is cheap to combine the checks here)
3736 * pending TPR access reports.
3737 */
3738 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
fc12d72e
PB		 3739 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
3740 !(env->hflags & HF_SMM_MASK)) {
3741 cpu->exit_request = 1;
3742 }
3743 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
3744 cpu->exit_request = 1;
3745 }
e0723c45 3746 }
05330448 3747
15eafc2e 3748 if (!kvm_pic_in_kernel()) {
db1669bc
JK		 3749 /* Try to inject an interrupt if the guest can accept it */
3750 if (run->ready_for_interrupt_injection &&
259186a7 3751 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
db1669bc
JK		 3752 (env->eflags & IF_MASK)) {
3753 int irq;
3754
259186a7 3755 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
db1669bc
JK		 3756 irq = cpu_get_pic_interrupt(env);
3757 if (irq >= 0) {
3758 struct kvm_interrupt intr;
3759
3760 intr.irq = irq;
db1669bc 3761 DPRINTF("injected interrupt %d\n", irq);
1bc22652 3762 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
ce377af3
JK		 3763 if (ret < 0) {
3764 fprintf(stderr,
3765 "KVM: injection failed, interrupt lost (%s)\n",
3766 strerror(-ret));
3767 }
db1669bc
JK		 3768 }
3769 }
05330448 3770
db1669bc
JK		 3771 /* If we have an interrupt but the guest is not ready to receive an
3772 * interrupt, request an interrupt window exit. This will
3773 * cause a return to userspace as soon as the guest is ready to
3774 * receive interrupts. */
259186a7 3775 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
db1669bc
JK		 3776 run->request_interrupt_window = 1;
3777 } else {
3778 run->request_interrupt_window = 0;
3779 }
3780
3781 DPRINTF("setting tpr\n");
02e51483 3782 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
4b8523ee
JK		 3783
3784 qemu_mutex_unlock_iothread();
db1669bc 3785 }
05330448
AL		 3786}
3787
4c663752 3788MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
05330448 3789{
20d695a9
AF		 3790 X86CPU *x86_cpu = X86_CPU(cpu);
3791 CPUX86State *env = &x86_cpu->env;
3792
fc12d72e
PB		 3793 if (run->flags & KVM_RUN_X86_SMM) {
3794 env->hflags |= HF_SMM_MASK;
3795 } else {
f5c052b9 3796 env->hflags &= ~HF_SMM_MASK;
fc12d72e 3797 }
b9bec74b 3798 if (run->if_flag) {
05330448 3799 env->eflags |= IF_MASK;
b9bec74b 3800 } else {
05330448 3801 env->eflags &= ~IF_MASK;
b9bec74b 3802 }
4b8523ee
JK		 3803
3804 /* We need to protect the apic state against concurrent accesses from
3805 * different threads in case the userspace irqchip is used. */
3806 if (!kvm_irqchip_in_kernel()) {
3807 qemu_mutex_lock_iothread();
3808 }
02e51483
CF		 3809 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
3810 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
4b8523ee
JK		 3811 if (!kvm_irqchip_in_kernel()) {
3812 qemu_mutex_unlock_iothread();
3813 }
f794aa4a 3814 return cpu_get_mem_attrs(env);
05330448
AL		 3815}
3816
20d695a9 3817int kvm_arch_process_async_events(CPUState *cs)
0af691d7 3818{
20d695a9
AF		 3819 X86CPU *cpu = X86_CPU(cs);
3820 CPUX86State *env = &cpu->env;
232fc23b 3821
259186a7 3822 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
ab443475
JK		 3823 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
3824 assert(env->mcg_cap);
3825
259186a7 3826 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
ab443475 3827
dd1750d7 3828 kvm_cpu_synchronize_state(cs);
ab443475 3829
fd13f23b 3830 if (env->exception_nr == EXCP08_DBLE) {
ab443475 3831 /* this means triple fault */
cf83f140 3832 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
fcd7d003 3833 cs->exit_request = 1;
ab443475
JK		 3834 return 0;
3835 }
fd13f23b 3836 kvm_queue_exception(env, EXCP12_MCHK, 0, 0);
ab443475
JK		 3837 env->has_error_code = 0;
3838
259186a7 3839 cs->halted = 0;
ab443475
JK		 3840 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
3841 env->mp_state = KVM_MP_STATE_RUNNABLE;
3842 }
3843 }
3844
fc12d72e
PB		 3845 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
3846 !(env->hflags & HF_SMM_MASK)) {
e0723c45
PB		 3847 kvm_cpu_synchronize_state(cs);
3848 do_cpu_init(cpu);
3849 }
3850
db1669bc
JK		 3851 if (kvm_irqchip_in_kernel()) {
3852 return 0;
3853 }
3854
259186a7
AF		 3855 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
3856 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
02e51483 3857 apic_poll_irq(cpu->apic_state);
5d62c43a 3858 }
259186a7 3859 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
4601f7b0 3860 (env->eflags & IF_MASK)) ||
259186a7
AF		 3861 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
3862 cs->halted = 0;
6792a57b 3863 }
259186a7 3864 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
dd1750d7 3865 kvm_cpu_synchronize_state(cs);
232fc23b 3866 do_cpu_sipi(cpu);
0af691d7 3867 }
259186a7
AF		 3868 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
3869 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
dd1750d7 3870 kvm_cpu_synchronize_state(cs);
02e51483 3871 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
d362e757
JK		 3872 env->tpr_access_type);
3873 }
0af691d7 3874
259186a7 3875 return cs->halted;
0af691d7
MT		 3876}
3877
839b5630 3878static int kvm_handle_halt(X86CPU *cpu)
05330448 3879{
259186a7 3880 CPUState *cs = CPU(cpu);
839b5630
AF		 3881 CPUX86State *env = &cpu->env;
3882
259186a7 3883 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
05330448 3884 (env->eflags & IF_MASK)) &&
259186a7
AF		 3885 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
3886 cs->halted = 1;
bb4ea393 3887 return EXCP_HLT;
05330448
AL		 3888 }
3889
bb4ea393 3890 return 0;
05330448
AL		 3891}
3892
f7575c96 3893static int kvm_handle_tpr_access(X86CPU *cpu)
d362e757 3894{
f7575c96
AF		 3895 CPUState *cs = CPU(cpu);
3896 struct kvm_run *run = cs->kvm_run;
d362e757 3897
02e51483 3898 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
d362e757
JK		 3899 run->tpr_access.is_write ? TPR_ACCESS_WRITE
3900 : TPR_ACCESS_READ);
3901 return 1;
3902}
3903
f17ec444 3904int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9 3905{
38972938 3906 static const uint8_t int3 = 0xcc;
64bf3f4e 3907
f17ec444
AF		 3908 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
3909 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
e22a25c9 3910 return -EINVAL;
b9bec74b 3911 }
e22a25c9
AL		 3912 return 0;
3913}
3914
f17ec444 3915int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9
AL		 3916{
3917 uint8_t int3;
3918
f17ec444
AF		 3919 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
3920 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
e22a25c9 3921 return -EINVAL;
b9bec74b 3922 }
e22a25c9
AL		 3923 return 0;
3924}
3925
3926static struct {
3927 target_ulong addr;
3928 int len;
3929 int type;
3930} hw_breakpoint[4];
3931
3932static int nb_hw_breakpoint;
3933
3934static int find_hw_breakpoint(target_ulong addr, int len, int type)
3935{
3936 int n;
3937
b9bec74b 3938 for (n = 0; n < nb_hw_breakpoint; n++) {
e22a25c9 3939 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
b9bec74b 3940 (hw_breakpoint[n].len == len || len == -1)) {
e22a25c9 3941 return n;
b9bec74b
JK		 3942 }
3943 }
e22a25c9
AL		 3944 return -1;
3945}
3946
3947int kvm_arch_insert_hw_breakpoint(target_ulong addr,
3948 target_ulong len, int type)
3949{
3950 switch (type) {
3951 case GDB_BREAKPOINT_HW:
3952 len = 1;
3953 break;
3954 case GDB_WATCHPOINT_WRITE:
3955 case GDB_WATCHPOINT_ACCESS:
3956 switch (len) {
3957 case 1:
3958 break;
3959 case 2:
3960 case 4:
3961 case 8:
b9bec74b 3962 if (addr & (len - 1)) {
e22a25c9 3963 return -EINVAL;
b9bec74b 3964 }
e22a25c9
AL		 3965 break;
3966 default:
3967 return -EINVAL;
3968 }
3969 break;
3970 default:
3971 return -ENOSYS;
3972 }
3973
b9bec74b 3974 if (nb_hw_breakpoint == 4) {
e22a25c9 3975 return -ENOBUFS;
b9bec74b
JK		 3976 }
3977 if (find_hw_breakpoint(addr, len, type) >= 0) {
e22a25c9 3978 return -EEXIST;
b9bec74b 3979 }
e22a25c9
AL		 3980 hw_breakpoint[nb_hw_breakpoint].addr = addr;
3981 hw_breakpoint[nb_hw_breakpoint].len = len;
3982 hw_breakpoint[nb_hw_breakpoint].type = type;
3983 nb_hw_breakpoint++;
3984
3985 return 0;
3986}
3987
3988int kvm_arch_remove_hw_breakpoint(target_ulong addr,
3989 target_ulong len, int type)
3990{
3991 int n;
3992
3993 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
b9bec74b 3994 if (n < 0) {
e22a25c9 3995 return -ENOENT;
b9bec74b 3996 }
e22a25c9
AL		 3997 nb_hw_breakpoint--;
3998 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
3999
4000 return 0;
4001}
4002
4003void kvm_arch_remove_all_hw_breakpoints(void)
4004{
4005 nb_hw_breakpoint = 0;
4006}
4007
4008static CPUWatchpoint hw_watchpoint;
4009
a60f24b5 4010static int kvm_handle_debug(X86CPU *cpu,
48405526 4011 struct kvm_debug_exit_arch *arch_info)
e22a25c9 4012{
ed2803da 4013 CPUState *cs = CPU(cpu);
a60f24b5 4014 CPUX86State *env = &cpu->env;
f2574737 4015 int ret = 0;
e22a25c9
AL		 4016 int n;
4017
37936ac7
LA		 4018 if (arch_info->exception == EXCP01_DB) {
4019 if (arch_info->dr6 & DR6_BS) {
ed2803da 4020 if (cs->singlestep_enabled) {
f2574737 4021 ret = EXCP_DEBUG;
b9bec74b 4022 }
e22a25c9 4023 } else {
b9bec74b
JK		 4024 for (n = 0; n < 4; n++) {
4025 if (arch_info->dr6 & (1 << n)) {
e22a25c9
AL		 4026 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
4027 case 0x0:
f2574737 4028 ret = EXCP_DEBUG;
e22a25c9
AL		 4029 break;
4030 case 0x1:
f2574737 4031 ret = EXCP_DEBUG;
ff4700b0 4032 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 4033 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
4034 hw_watchpoint.flags = BP_MEM_WRITE;
4035 break;
4036 case 0x3:
f2574737 4037 ret = EXCP_DEBUG;
ff4700b0 4038 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 4039 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
4040 hw_watchpoint.flags = BP_MEM_ACCESS;
4041 break;
4042 }
b9bec74b
JK		 4043 }
4044 }
e22a25c9 4045 }
ff4700b0 4046 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
f2574737 4047 ret = EXCP_DEBUG;
b9bec74b 4048 }
f2574737 4049 if (ret == 0) {
ff4700b0 4050 cpu_synchronize_state(cs);
fd13f23b 4051 assert(env->exception_nr == -1);
b0b1d690 4052
f2574737 4053 /* pass to guest */
fd13f23b
LA		 4054 kvm_queue_exception(env, arch_info->exception,
4055 arch_info->exception == EXCP01_DB,
4056 arch_info->dr6);
48405526 4057 env->has_error_code = 0;
b0b1d690 4058 }
e22a25c9 4059
f2574737 4060 return ret;
e22a25c9
AL		 4061}
4062
20d695a9 4063void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
e22a25c9
AL		 4064{
4065 const uint8_t type_code[] = {
4066 [GDB_BREAKPOINT_HW] = 0x0,
4067 [GDB_WATCHPOINT_WRITE] = 0x1,
4068 [GDB_WATCHPOINT_ACCESS] = 0x3
4069 };
4070 const uint8_t len_code[] = {
4071 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
4072 };
4073 int n;
4074
a60f24b5 4075 if (kvm_sw_breakpoints_active(cpu)) {
e22a25c9 4076 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
b9bec74b 4077 }
e22a25c9
AL		 4078 if (nb_hw_breakpoint > 0) {
4079 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
4080 dbg->arch.debugreg[7] = 0x0600;
4081 for (n = 0; n < nb_hw_breakpoint; n++) {
4082 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
4083 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
4084 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
95c077c9 4085 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
e22a25c9
AL		 4086 }
4087 }
4088}
4513d923 4089
2a4dac83
JK		 4090static bool host_supports_vmx(void)
4091{
4092 uint32_t ecx, unused;
4093
4094 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
4095 return ecx & CPUID_EXT_VMX;
4096}
4097
4098#define VMX_INVALID_GUEST_STATE 0x80000021
4099
20d695a9 4100int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2a4dac83 4101{
20d695a9 4102 X86CPU *cpu = X86_CPU(cs);
2a4dac83
JK		 4103 uint64_t code;
4104 int ret;
4105
4106 switch (run->exit_reason) {
4107 case KVM_EXIT_HLT:
4108 DPRINTF("handle_hlt\n");
4b8523ee 4109 qemu_mutex_lock_iothread();
839b5630 4110 ret = kvm_handle_halt(cpu);
4b8523ee 4111 qemu_mutex_unlock_iothread();
2a4dac83
JK		 4112 break;
4113 case KVM_EXIT_SET_TPR:
4114 ret = 0;
4115 break;
d362e757 4116 case KVM_EXIT_TPR_ACCESS:
4b8523ee 4117 qemu_mutex_lock_iothread();
f7575c96 4118 ret = kvm_handle_tpr_access(cpu);
4b8523ee 4119 qemu_mutex_unlock_iothread();
d362e757 4120 break;
2a4dac83
JK		 4121 case KVM_EXIT_FAIL_ENTRY:
4122 code = run->fail_entry.hardware_entry_failure_reason;
4123 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
4124 code);
4125 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
4126 fprintf(stderr,
12619721 4127 "\nIf you're running a guest on an Intel machine without "
2a4dac83
JK		 4128 "unrestricted mode\n"
4129 "support, the failure can be most likely due to the guest "
4130 "entering an invalid\n"
4131 "state for Intel VT. For example, the guest maybe running "
4132 "in big real mode\n"
4133 "which is not supported on less recent Intel processors."
4134 "\n\n");
4135 }
4136 ret = -1;
4137 break;
4138 case KVM_EXIT_EXCEPTION:
4139 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
4140 run->ex.exception, run->ex.error_code);
4141 ret = -1;
4142 break;
f2574737
JK		 4143 case KVM_EXIT_DEBUG:
4144 DPRINTF("kvm_exit_debug\n");
4b8523ee 4145 qemu_mutex_lock_iothread();
a60f24b5 4146 ret = kvm_handle_debug(cpu, &run->debug.arch);
4b8523ee 4147 qemu_mutex_unlock_iothread();
f2574737 4148 break;
50efe82c
AS		 4149 case KVM_EXIT_HYPERV:
4150 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
4151 break;
15eafc2e
PB		 4152 case KVM_EXIT_IOAPIC_EOI:
4153 ioapic_eoi_broadcast(run->eoi.vector);
4154 ret = 0;
4155 break;
2a4dac83
JK		 4156 default:
4157 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
4158 ret = -1;
4159 break;
4160 }
4161
4162 return ret;
4163}
4164
20d695a9 4165bool kvm_arch_stop_on_emulation_error(CPUState *cs)
4513d923 4166{
20d695a9
AF		 4167 X86CPU *cpu = X86_CPU(cs);
4168 CPUX86State *env = &cpu->env;
4169
dd1750d7 4170 kvm_cpu_synchronize_state(cs);
b9bec74b
JK		 4171 return !(env->cr[0] & CR0_PE_MASK) ||
4172 ((env->segs[R_CS].selector & 3) != 3);
4513d923 4173}
84b058d7
JK		 4174
4175void kvm_arch_init_irq_routing(KVMState *s)
4176{
4177 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
4178 /* If kernel can't do irq routing, interrupt source
4179 * override 0->2 cannot be set up as required by HPET.
4180 * So we have to disable it.
4181 */
4182 no_hpet = 1;
4183 }
cc7e0ddf 4184 /* We know at this point that we're using the in-kernel
614e41bc 4185 * irqchip, so we can use irqfds, and on x86 we know
f3e1bed8 4186 * we can use msi via irqfd and GSI routing.
cc7e0ddf 4187 */
614e41bc 4188 kvm_msi_via_irqfd_allowed = true;
f3e1bed8 4189 kvm_gsi_routing_allowed = true;
15eafc2e
PB		 4190
4191 if (kvm_irqchip_is_split()) {
4192 int i;
4193
4194 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
4195 MSI routes for signaling interrupts to the local apics. */
4196 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
d1f6af6a 4197 if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
15eafc2e
PB		 4198 error_report("Could not enable split IRQ mode.");
4199 exit(1);
4200 }
4201 }
4202 }
4203}
4204
4205int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
4206{
4207 int ret;
4208 if (machine_kernel_irqchip_split(ms)) {
4209 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
4210 if (ret) {
df3c286c 4211 error_report("Could not enable split irqchip mode: %s",
15eafc2e
PB		 4212 strerror(-ret));
4213 exit(1);
4214 } else {
4215 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
4216 kvm_split_irqchip = true;
4217 return 1;
4218 }
4219 } else {
4220 return 0;
4221 }
84b058d7 4222}
b139bd30
JK		 4223
4224/* Classic KVM device assignment interface. Will remain x86 only. */
4225int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
4226 uint32_t flags, uint32_t *dev_id)
4227{
4228 struct kvm_assigned_pci_dev dev_data = {
4229 .segnr = dev_addr->domain,
4230 .busnr = dev_addr->bus,
4231 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
4232 .flags = flags,
4233 };
4234 int ret;
4235
4236 dev_data.assigned_dev_id =
4237 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
4238
4239 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
4240 if (ret < 0) {
4241 return ret;
4242 }
4243
4244 *dev_id = dev_data.assigned_dev_id;
4245
4246 return 0;
4247}
4248
4249int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
4250{
4251 struct kvm_assigned_pci_dev dev_data = {
4252 .assigned_dev_id = dev_id,
4253 };
4254
4255 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
4256}
4257
4258static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
4259 uint32_t irq_type, uint32_t guest_irq)
4260{
4261 struct kvm_assigned_irq assigned_irq = {
4262 .assigned_dev_id = dev_id,
4263 .guest_irq = guest_irq,
4264 .flags = irq_type,
4265 };
4266
4267 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
4268 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
4269 } else {
4270 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
4271 }
4272}
4273
4274int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
4275 uint32_t guest_irq)
4276{
4277 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
4278 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
4279
4280 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
4281}
4282
4283int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
4284{
4285 struct kvm_assigned_pci_dev dev_data = {
4286 .assigned_dev_id = dev_id,
4287 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
4288 };
4289
4290 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
4291}
4292
4293static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
4294 uint32_t type)
4295{
4296 struct kvm_assigned_irq assigned_irq = {
4297 .assigned_dev_id = dev_id,
4298 .flags = type,
4299 };
4300
4301 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
4302}
4303
4304int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
4305{
4306 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
4307 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
4308}
4309
4310int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
4311{
4312 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
4313 KVM_DEV_IRQ_GUEST_MSI, virq);
4314}
4315
4316int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
4317{
4318 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
4319 KVM_DEV_IRQ_HOST_MSI);
4320}
4321
4322bool kvm_device_msix_supported(KVMState *s)
4323{
4324 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
4325 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
4326 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
4327}
4328
4329int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
4330 uint32_t nr_vectors)
4331{
4332 struct kvm_assigned_msix_nr msix_nr = {
4333 .assigned_dev_id = dev_id,
4334 .entry_nr = nr_vectors,
4335 };
4336
4337 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
4338}
4339
4340int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
4341 int virq)
4342{
4343 struct kvm_assigned_msix_entry msix_entry = {
4344 .assigned_dev_id = dev_id,
4345 .gsi = virq,
4346 .entry = vector,
4347 };
4348
4349 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
4350}
4351
4352int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
4353{
4354 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
4355 KVM_DEV_IRQ_GUEST_MSIX, 0);
4356}
4357
4358int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
4359{
4360 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
4361 KVM_DEV_IRQ_HOST_MSIX);
4362}
9e03a040
FB		 4363
4364int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
dc9f06ca 4365 uint64_t address, uint32_t data, PCIDevice *dev)
9e03a040 4366{
8b5ed7df
PX		 4367 X86IOMMUState *iommu = x86_iommu_get_default();
4368
4369 if (iommu) {
4370 int ret;
4371 MSIMessage src, dst;
4372 X86IOMMUClass *class = X86_IOMMU_GET_CLASS(iommu);
4373
0ea1472d
JK		 4374 if (!class->int_remap) {
4375 return 0;
4376 }
4377
8b5ed7df
PX		 4378 src.address = route->u.msi.address_hi;
4379 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
4380 src.address |= route->u.msi.address_lo;
4381 src.data = route->u.msi.data;
4382
4383 ret = class->int_remap(iommu, &src, &dst, dev ? \
4384 pci_requester_id(dev) : \
4385 X86_IOMMU_SID_INVALID);
4386 if (ret) {
4387 trace_kvm_x86_fixup_msi_error(route->gsi);
4388 return 1;
4389 }
4390
4391 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
4392 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
4393 route->u.msi.data = dst.data;
4394 }
4395
9e03a040
FB		 4396 return 0;
4397}
1850b6b7 4398
38d87493
PX		 4399typedef struct MSIRouteEntry MSIRouteEntry;
4400
4401struct MSIRouteEntry {
4402 PCIDevice *dev; /* Device pointer */
4403 int vector; /* MSI/MSIX vector index */
4404 int virq; /* Virtual IRQ index */
4405 QLIST_ENTRY(MSIRouteEntry) list;
4406};
4407
4408/* List of used GSI routes */
4409static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
4410 QLIST_HEAD_INITIALIZER(msi_route_list);
4411
e1d4fb2d
PX		 4412static void kvm_update_msi_routes_all(void *private, bool global,
4413 uint32_t index, uint32_t mask)
4414{
a56de056 4415 int cnt = 0, vector;
e1d4fb2d
PX		 4416 MSIRouteEntry *entry;
4417 MSIMessage msg;
fd563564
PX		 4418 PCIDevice *dev;
4419
e1d4fb2d
PX		 4420 /* TODO: explicit route update */
4421 QLIST_FOREACH(entry, &msi_route_list, list) {
4422 cnt++;
a56de056 4423 vector = entry->vector;
fd563564 4424 dev = entry->dev;
a56de056
PX		 4425 if (msix_enabled(dev) && !msix_is_masked(dev, vector)) {
4426 msg = msix_get_message(dev, vector);
4427 } else if (msi_enabled(dev) && !msi_is_masked(dev, vector)) {
4428 msg = msi_get_message(dev, vector);
4429 } else {
4430 /*
4431 * Either MSI/MSIX is disabled for the device, or the
4432 * specific message was masked out. Skip this one.
4433 */
fd563564
PX		 4434 continue;
4435 }
fd563564 4436 kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev);
e1d4fb2d 4437 }
3f1fea0f 4438 kvm_irqchip_commit_routes(kvm_state);
e1d4fb2d
PX		 4439 trace_kvm_x86_update_msi_routes(cnt);
4440}
4441
38d87493
PX		 4442int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
4443 int vector, PCIDevice *dev)
4444{
e1d4fb2d 4445 static bool notify_list_inited = false;
38d87493
PX		 4446 MSIRouteEntry *entry;
4447
4448 if (!dev) {
4449 /* These are (possibly) IOAPIC routes only used for split
4450 * kernel irqchip mode, while what we are housekeeping are
4451 * PCI devices only. */
4452 return 0;
4453 }
4454
4455 entry = g_new0(MSIRouteEntry, 1);
4456 entry->dev = dev;
4457 entry->vector = vector;
4458 entry->virq = route->gsi;
4459 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
4460
4461 trace_kvm_x86_add_msi_route(route->gsi);
e1d4fb2d
PX		 4462
4463 if (!notify_list_inited) {
4464 /* For the first time we do add route, add ourselves into
4465 * IOMMU's IEC notify list if needed. */
4466 X86IOMMUState *iommu = x86_iommu_get_default();
4467 if (iommu) {
4468 x86_iommu_iec_register_notifier(iommu,
4469 kvm_update_msi_routes_all,
4470 NULL);
4471 }
4472 notify_list_inited = true;
4473 }
38d87493
PX		 4474 return 0;
4475}
4476
4477int kvm_arch_release_virq_post(int virq)
4478{
4479 MSIRouteEntry *entry, *next;
4480 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
4481 if (entry->virq == virq) {
4482 trace_kvm_x86_remove_msi_route(virq);
4483 QLIST_REMOVE(entry, list);
01960e6d 4484 g_free(entry);
38d87493
PX		 4485 break;
4486 }
4487 }
9e03a040
FB		 4488 return 0;
4489}
1850b6b7
EA		 4490
4491int kvm_arch_msi_data_to_gsi(uint32_t data)
4492{
4493 abort();
4494}
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