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target-i386: kvm: Abort if MCE bank count is not supported by host
[qemu.git] / target-i386 / kvm.c
CommitLineData
05330448
AL		 1/*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <[email protected]>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15#include <sys/types.h>
16#include <sys/ioctl.h>
17#include <sys/mman.h>
25d2e361 18#include <sys/utsname.h>
05330448
AL		 19
20#include <linux/kvm.h>
5802e066 21#include <linux/kvm_para.h>
05330448
AL		 22
23#include "qemu-common.h"
9c17d615 24#include "sysemu/sysemu.h"
6410848b 25#include "sysemu/kvm_int.h"
1d31f66b 26#include "kvm_i386.h"
05330448 27#include "cpu.h"
022c62cb 28#include "exec/gdbstub.h"
1de7afc9
PB		 29#include "qemu/host-utils.h"
30#include "qemu/config-file.h"
1c4a55db 31#include "qemu/error-report.h"
0d09e41a
PB		 32#include "hw/i386/pc.h"
33#include "hw/i386/apic.h"
e0723c45
PB		 34#include "hw/i386/apic_internal.h"
35#include "hw/i386/apic-msidef.h"
022c62cb 36#include "exec/ioport.h"
73aa529a 37#include "standard-headers/asm-x86/hyperv.h"
a2cb15b0 38#include "hw/pci/pci.h"
68bfd0ad 39#include "migration/migration.h"
4c663752 40#include "exec/memattrs.h"
05330448
AL		 41
42//#define DEBUG_KVM
43
44#ifdef DEBUG_KVM
8c0d577e 45#define DPRINTF(fmt, ...) \
05330448
AL		 46 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
47#else
8c0d577e 48#define DPRINTF(fmt, ...) \
05330448
AL		 49 do { } while (0)
50#endif
51
1a03675d
GC		 52#define MSR_KVM_WALL_CLOCK 0x11
53#define MSR_KVM_SYSTEM_TIME 0x12
54
c0532a76
MT		 55#ifndef BUS_MCEERR_AR
56#define BUS_MCEERR_AR 4
57#endif
58#ifndef BUS_MCEERR_AO
59#define BUS_MCEERR_AO 5
60#endif
61
94a8d39a
JK		 62const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
63 KVM_CAP_INFO(SET_TSS_ADDR),
64 KVM_CAP_INFO(EXT_CPUID),
65 KVM_CAP_INFO(MP_STATE),
66 KVM_CAP_LAST_INFO
67};
25d2e361 68
c3a3a7d3
JK		 69static bool has_msr_star;
70static bool has_msr_hsave_pa;
c9b8f6b6 71static bool has_msr_tsc_aux;
f28558d3 72static bool has_msr_tsc_adjust;
aa82ba54 73static bool has_msr_tsc_deadline;
df67696e 74static bool has_msr_feature_control;
c5999bfc 75static bool has_msr_async_pf_en;
bc9a839d 76static bool has_msr_pv_eoi_en;
21e87c46 77static bool has_msr_misc_enable;
fc12d72e 78static bool has_msr_smbase;
79e9ebeb 79static bool has_msr_bndcfgs;
917367aa 80static bool has_msr_kvm_steal_time;
25d2e361 81static int lm_capable_kernel;
7bc3d711
PB		 82static bool has_msr_hv_hypercall;
83static bool has_msr_hv_vapic;
48a5f3bc 84static bool has_msr_hv_tsc;
f2a53c9e 85static bool has_msr_hv_crash;
744b8a94 86static bool has_msr_hv_reset;
8c145d7c 87static bool has_msr_hv_vpindex;
46eb8f98 88static bool has_msr_hv_runtime;
d1ae67f6 89static bool has_msr_mtrr;
18cd2c17 90static bool has_msr_xss;
b827df58 91
0d894367
PB		 92static bool has_msr_architectural_pmu;
93static uint32_t num_architectural_pmu_counters;
94
28143b40
TH		 95static int has_xsave;
96static int has_xcrs;
97static int has_pit_state2;
98
99int kvm_has_pit_state2(void)
100{
101 return has_pit_state2;
102}
103
355023f2
PB		 104bool kvm_has_smm(void)
105{
106 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
107}
108
1d31f66b
PM		 109bool kvm_allows_irq0_override(void)
110{
111 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
112}
113
0fd7e098
LL		 114static int kvm_get_tsc(CPUState *cs)
115{
116 X86CPU *cpu = X86_CPU(cs);
117 CPUX86State *env = &cpu->env;
118 struct {
119 struct kvm_msrs info;
120 struct kvm_msr_entry entries[1];
121 } msr_data;
122 int ret;
123
124 if (env->tsc_valid) {
125 return 0;
126 }
127
128 msr_data.info.nmsrs = 1;
129 msr_data.entries[0].index = MSR_IA32_TSC;
130 env->tsc_valid = !runstate_is_running();
131
132 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
133 if (ret < 0) {
134 return ret;
135 }
136
137 env->tsc = msr_data.entries[0].data;
138 return 0;
139}
140
141static inline void do_kvm_synchronize_tsc(void *arg)
142{
143 CPUState *cpu = arg;
144
145 kvm_get_tsc(cpu);
146}
147
148void kvm_synchronize_all_tsc(void)
149{
150 CPUState *cpu;
151
152 if (kvm_enabled()) {
153 CPU_FOREACH(cpu) {
154 run_on_cpu(cpu, do_kvm_synchronize_tsc, cpu);
155 }
156 }
157}
158
b827df58
AK		 159static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
160{
161 struct kvm_cpuid2 *cpuid;
162 int r, size;
163
164 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
e42a92ae 165 cpuid = g_malloc0(size);
b827df58
AK		 166 cpuid->nent = max;
167 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
76ae317f
MM		 168 if (r == 0 && cpuid->nent >= max) {
169 r = -E2BIG;
170 }
b827df58
AK		 171 if (r < 0) {
172 if (r == -E2BIG) {
7267c094 173 g_free(cpuid);
b827df58
AK		 174 return NULL;
175 } else {
176 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
177 strerror(-r));
178 exit(1);
179 }
180 }
181 return cpuid;
182}
183
dd87f8a6
EH		 184/* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
185 * for all entries.
186 */
187static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
188{
189 struct kvm_cpuid2 *cpuid;
190 int max = 1;
191 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
192 max *= 2;
193 }
194 return cpuid;
195}
196
a443bc34 197static const struct kvm_para_features {
0c31b744
GC		 198 int cap;
199 int feature;
200} para_features[] = {
201 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
202 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
203 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
0c31b744 204 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
0c31b744
GC		 205};
206
ba9bc59e 207static int get_para_features(KVMState *s)
0c31b744
GC		 208{
209 int i, features = 0;
210
8e03c100 211 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
ba9bc59e 212 if (kvm_check_extension(s, para_features[i].cap)) {
0c31b744
GC		 213 features |= (1 << para_features[i].feature);
214 }
215 }
216
217 return features;
218}
0c31b744
GC		 219
220
829ae2f9
EH		 221/* Returns the value for a specific register on the cpuid entry
222 */
223static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
224{
225 uint32_t ret = 0;
226 switch (reg) {
227 case R_EAX:
228 ret = entry->eax;
229 break;
230 case R_EBX:
231 ret = entry->ebx;
232 break;
233 case R_ECX:
234 ret = entry->ecx;
235 break;
236 case R_EDX:
237 ret = entry->edx;
238 break;
239 }
240 return ret;
241}
242
4fb73f1d
EH		 243/* Find matching entry for function/index on kvm_cpuid2 struct
244 */
245static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
246 uint32_t function,
247 uint32_t index)
248{
249 int i;
250 for (i = 0; i < cpuid->nent; ++i) {
251 if (cpuid->entries[i].function == function &&
252 cpuid->entries[i].index == index) {
253 return &cpuid->entries[i];
254 }
255 }
256 /* not found: */
257 return NULL;
258}
259
ba9bc59e 260uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
c958a8bd 261 uint32_t index, int reg)
b827df58
AK		 262{
263 struct kvm_cpuid2 *cpuid;
b827df58
AK		 264 uint32_t ret = 0;
265 uint32_t cpuid_1_edx;
8c723b79 266 bool found = false;
b827df58 267
dd87f8a6 268 cpuid = get_supported_cpuid(s);
b827df58 269
4fb73f1d
EH		 270 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
271 if (entry) {
272 found = true;
273 ret = cpuid_entry_get_reg(entry, reg);
b827df58
AK		 274 }
275
7b46e5ce
EH		 276 /* Fixups for the data returned by KVM, below */
277
c2acb022
EH		 278 if (function == 1 && reg == R_EDX) {
279 /* KVM before 2.6.30 misreports the following features */
280 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
84bd945c
EH		 281 } else if (function == 1 && reg == R_ECX) {
282 /* We can set the hypervisor flag, even if KVM does not return it on
283 * GET_SUPPORTED_CPUID
284 */
285 ret |= CPUID_EXT_HYPERVISOR;
ac67ee26
EH		 286 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
287 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
288 * and the irqchip is in the kernel.
289 */
290 if (kvm_irqchip_in_kernel() &&
291 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
292 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
293 }
41e5e76d
EH		 294
295 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
296 * without the in-kernel irqchip
297 */
298 if (!kvm_irqchip_in_kernel()) {
299 ret &= ~CPUID_EXT_X2APIC;
b827df58 300 }
28b8e4d0
JK		 301 } else if (function == 6 && reg == R_EAX) {
302 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
c2acb022
EH		 303 } else if (function == 0x80000001 && reg == R_EDX) {
304 /* On Intel, kvm returns cpuid according to the Intel spec,
305 * so add missing bits according to the AMD spec:
306 */
307 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
308 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
b827df58
AK		 309 }
310
7267c094 311 g_free(cpuid);
b827df58 312
0c31b744 313 /* fallback for older kernels */
8c723b79 314 if ((function == KVM_CPUID_FEATURES) && !found) {
ba9bc59e 315 ret = get_para_features(s);
b9bec74b 316 }
0c31b744
GC		 317
318 return ret;
bb0300dc 319}
bb0300dc 320
3c85e74f
HY		 321typedef struct HWPoisonPage {
322 ram_addr_t ram_addr;
323 QLIST_ENTRY(HWPoisonPage) list;
324} HWPoisonPage;
325
326static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
327 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
328
329static void kvm_unpoison_all(void *param)
330{
331 HWPoisonPage *page, *next_page;
332
333 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
334 QLIST_REMOVE(page, list);
335 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
7267c094 336 g_free(page);
3c85e74f
HY		 337 }
338}
339
3c85e74f
HY		 340static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
341{
342 HWPoisonPage *page;
343
344 QLIST_FOREACH(page, &hwpoison_page_list, list) {
345 if (page->ram_addr == ram_addr) {
346 return;
347 }
348 }
ab3ad07f 349 page = g_new(HWPoisonPage, 1);
3c85e74f
HY		 350 page->ram_addr = ram_addr;
351 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
352}
353
e7701825
MT		 354static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
355 int *max_banks)
356{
357 int r;
358
14a09518 359 r = kvm_check_extension(s, KVM_CAP_MCE);
e7701825
MT		 360 if (r > 0) {
361 *max_banks = r;
362 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
363 }
364 return -ENOSYS;
365}
366
bee615d4 367static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
e7701825 368{
bee615d4 369 CPUX86State *env = &cpu->env;
c34d440a
JK		 370 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
371 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
372 uint64_t mcg_status = MCG_STATUS_MCIP;
e7701825 373
c34d440a
JK		 374 if (code == BUS_MCEERR_AR) {
375 status |= MCI_STATUS_AR | 0x134;
376 mcg_status |= MCG_STATUS_EIPV;
377 } else {
378 status |= 0xc0;
379 mcg_status |= MCG_STATUS_RIPV;
419fb20a 380 }
8c5cf3b6 381 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
c34d440a
JK		 382 (MCM_ADDR_PHYS << 6) | 0xc,
383 cpu_x86_support_mca_broadcast(env) ?
384 MCE_INJECT_BROADCAST : 0);
419fb20a 385}
419fb20a
JK		 386
387static void hardware_memory_error(void)
388{
389 fprintf(stderr, "Hardware memory error!\n");
390 exit(1);
391}
392
20d695a9 393int kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
419fb20a 394{
20d695a9
AF		 395 X86CPU *cpu = X86_CPU(c);
396 CPUX86State *env = &cpu->env;
419fb20a 397 ram_addr_t ram_addr;
a8170e5e 398 hwaddr paddr;
419fb20a
JK		 399
400 if ((env->mcg_cap & MCG_SER_P) && addr
c34d440a 401 && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
1b5ec234 402 if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL ||
a60f24b5 403 !kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
419fb20a
JK		 404 fprintf(stderr, "Hardware memory error for memory used by "
405 "QEMU itself instead of guest system!\n");
406 /* Hope we are lucky for AO MCE */
407 if (code == BUS_MCEERR_AO) {
408 return 0;
409 } else {
410 hardware_memory_error();
411 }
412 }
3c85e74f 413 kvm_hwpoison_page_add(ram_addr);
bee615d4 414 kvm_mce_inject(cpu, paddr, code);
e56ff191 415 } else {
419fb20a
JK		 416 if (code == BUS_MCEERR_AO) {
417 return 0;
418 } else if (code == BUS_MCEERR_AR) {
419 hardware_memory_error();
420 } else {
421 return 1;
422 }
423 }
424 return 0;
425}
426
427int kvm_arch_on_sigbus(int code, void *addr)
428{
182735ef
AF		 429 X86CPU *cpu = X86_CPU(first_cpu);
430
431 if ((cpu->env.mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
419fb20a 432 ram_addr_t ram_addr;
a8170e5e 433 hwaddr paddr;
419fb20a
JK		 434
435 /* Hope we are lucky for AO MCE */
1b5ec234 436 if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL ||
182735ef 437 !kvm_physical_memory_addr_from_host(first_cpu->kvm_state,
a60f24b5 438 addr, &paddr)) {
419fb20a
JK		 439 fprintf(stderr, "Hardware memory error for memory used by "
440 "QEMU itself instead of guest system!: %p\n", addr);
441 return 0;
442 }
3c85e74f 443 kvm_hwpoison_page_add(ram_addr);
182735ef 444 kvm_mce_inject(X86_CPU(first_cpu), paddr, code);
e56ff191 445 } else {
419fb20a
JK		 446 if (code == BUS_MCEERR_AO) {
447 return 0;
448 } else if (code == BUS_MCEERR_AR) {
449 hardware_memory_error();
450 } else {
451 return 1;
452 }
453 }
454 return 0;
455}
e7701825 456
1bc22652 457static int kvm_inject_mce_oldstyle(X86CPU *cpu)
ab443475 458{
1bc22652
AF		 459 CPUX86State *env = &cpu->env;
460
ab443475
JK		 461 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
462 unsigned int bank, bank_num = env->mcg_cap & 0xff;
463 struct kvm_x86_mce mce;
464
465 env->exception_injected = -1;
466
467 /*
468 * There must be at least one bank in use if an MCE is pending.
469 * Find it and use its values for the event injection.
470 */
471 for (bank = 0; bank < bank_num; bank++) {
472 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
473 break;
474 }
475 }
476 assert(bank < bank_num);
477
478 mce.bank = bank;
479 mce.status = env->mce_banks[bank * 4 + 1];
480 mce.mcg_status = env->mcg_status;
481 mce.addr = env->mce_banks[bank * 4 + 2];
482 mce.misc = env->mce_banks[bank * 4 + 3];
483
1bc22652 484 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
ab443475 485 }
ab443475
JK		 486 return 0;
487}
488
1dfb4dd9 489static void cpu_update_state(void *opaque, int running, RunState state)
b8cc45d6 490{
317ac620 491 CPUX86State *env = opaque;
b8cc45d6
GC		 492
493 if (running) {
494 env->tsc_valid = false;
495 }
496}
497
83b17af5 498unsigned long kvm_arch_vcpu_id(CPUState *cs)
b164e48e 499{
83b17af5 500 X86CPU *cpu = X86_CPU(cs);
7e72a45c 501 return cpu->apic_id;
b164e48e
EH		 502}
503
92067bf4
IM		 504#ifndef KVM_CPUID_SIGNATURE_NEXT
505#define KVM_CPUID_SIGNATURE_NEXT 0x40000100
506#endif
507
508static bool hyperv_hypercall_available(X86CPU *cpu)
509{
510 return cpu->hyperv_vapic ||
511 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
512}
513
514static bool hyperv_enabled(X86CPU *cpu)
515{
7bc3d711
PB		 516 CPUState *cs = CPU(cpu);
517 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
518 (hyperv_hypercall_available(cpu) ||
48a5f3bc 519 cpu->hyperv_time ||
f2a53c9e 520 cpu->hyperv_relaxed_timing ||
744b8a94 521 cpu->hyperv_crash ||
8c145d7c 522 cpu->hyperv_reset ||
46eb8f98
AS		 523 cpu->hyperv_vpindex ||
524 cpu->hyperv_runtime);
92067bf4
IM		 525}
526
68bfd0ad
MT		 527static Error *invtsc_mig_blocker;
528
f8bb0565 529#define KVM_MAX_CPUID_ENTRIES 100
0893d460 530
20d695a9 531int kvm_arch_init_vcpu(CPUState *cs)
05330448
AL		 532{
533 struct {
486bd5a2 534 struct kvm_cpuid2 cpuid;
f8bb0565 535 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
541dc0d4 536 } QEMU_PACKED cpuid_data;
20d695a9
AF		 537 X86CPU *cpu = X86_CPU(cs);
538 CPUX86State *env = &cpu->env;
486bd5a2 539 uint32_t limit, i, j, cpuid_i;
a33609ca 540 uint32_t unused;
bb0300dc 541 struct kvm_cpuid_entry2 *c;
bb0300dc 542 uint32_t signature[3];
234cc647 543 int kvm_base = KVM_CPUID_SIGNATURE;
e7429073 544 int r;
05330448 545
ef4cbe14
SW		 546 memset(&cpuid_data, 0, sizeof(cpuid_data));
547
05330448
AL		 548 cpuid_i = 0;
549
bb0300dc 550 /* Paravirtualization CPUIDs */
234cc647
PB		 551 if (hyperv_enabled(cpu)) {
552 c = &cpuid_data.entries[cpuid_i++];
553 c->function = HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
1c4a55db
AW		 554 if (!cpu->hyperv_vendor_id) {
555 memcpy(signature, "Microsoft Hv", 12);
556 } else {
557 size_t len = strlen(cpu->hyperv_vendor_id);
558
559 if (len > 12) {
560 error_report("hv-vendor-id truncated to 12 characters");
561 len = 12;
562 }
563 memset(signature, 0, 12);
564 memcpy(signature, cpu->hyperv_vendor_id, len);
565 }
eab70139 566 c->eax = HYPERV_CPUID_MIN;
234cc647
PB		 567 c->ebx = signature[0];
568 c->ecx = signature[1];
569 c->edx = signature[2];
0c31b744 570
234cc647
PB		 571 c = &cpuid_data.entries[cpuid_i++];
572 c->function = HYPERV_CPUID_INTERFACE;
eab70139
VR		 573 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
574 c->eax = signature[0];
234cc647
PB		 575 c->ebx = 0;
576 c->ecx = 0;
577 c->edx = 0;
eab70139
VR		 578
579 c = &cpuid_data.entries[cpuid_i++];
eab70139
VR		 580 c->function = HYPERV_CPUID_VERSION;
581 c->eax = 0x00001bbc;
582 c->ebx = 0x00060001;
583
584 c = &cpuid_data.entries[cpuid_i++];
eab70139 585 c->function = HYPERV_CPUID_FEATURES;
92067bf4 586 if (cpu->hyperv_relaxed_timing) {
eab70139
VR		 587 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
588 }
92067bf4 589 if (cpu->hyperv_vapic) {
eab70139
VR		 590 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
591 c->eax |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
7bc3d711 592 has_msr_hv_vapic = true;
eab70139 593 }
48a5f3bc
VR		 594 if (cpu->hyperv_time &&
595 kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) {
596 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
597 c->eax |= HV_X64_MSR_TIME_REF_COUNT_AVAILABLE;
598 c->eax |= 0x200;
599 has_msr_hv_tsc = true;
600 }
f2a53c9e
AS		 601 if (cpu->hyperv_crash && has_msr_hv_crash) {
602 c->edx |= HV_X64_GUEST_CRASH_MSR_AVAILABLE;
603 }
744b8a94
AS		 604 if (cpu->hyperv_reset && has_msr_hv_reset) {
605 c->eax |= HV_X64_MSR_RESET_AVAILABLE;
606 }
8c145d7c
AS		 607 if (cpu->hyperv_vpindex && has_msr_hv_vpindex) {
608 c->eax |= HV_X64_MSR_VP_INDEX_AVAILABLE;
609 }
46eb8f98
AS		 610 if (cpu->hyperv_runtime && has_msr_hv_runtime) {
611 c->eax |= HV_X64_MSR_VP_RUNTIME_AVAILABLE;
612 }
eab70139 613 c = &cpuid_data.entries[cpuid_i++];
eab70139 614 c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
92067bf4 615 if (cpu->hyperv_relaxed_timing) {
eab70139
VR		 616 c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
617 }
7bc3d711 618 if (has_msr_hv_vapic) {
eab70139
VR		 619 c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
620 }
92067bf4 621 c->ebx = cpu->hyperv_spinlock_attempts;
eab70139
VR		 622
623 c = &cpuid_data.entries[cpuid_i++];
eab70139
VR		 624 c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
625 c->eax = 0x40;
626 c->ebx = 0x40;
627
234cc647 628 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
7bc3d711 629 has_msr_hv_hypercall = true;
eab70139
VR		 630 }
631
f522d2ac
AW		 632 if (cpu->expose_kvm) {
633 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
634 c = &cpuid_data.entries[cpuid_i++];
635 c->function = KVM_CPUID_SIGNATURE | kvm_base;
79b6f2f6 636 c->eax = KVM_CPUID_FEATURES | kvm_base;
f522d2ac
AW		 637 c->ebx = signature[0];
638 c->ecx = signature[1];
639 c->edx = signature[2];
234cc647 640
f522d2ac
AW		 641 c = &cpuid_data.entries[cpuid_i++];
642 c->function = KVM_CPUID_FEATURES | kvm_base;
643 c->eax = env->features[FEAT_KVM];
234cc647 644
f522d2ac 645 has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF);
bb0300dc 646
f522d2ac 647 has_msr_pv_eoi_en = c->eax & (1 << KVM_FEATURE_PV_EOI);
bc9a839d 648
f522d2ac
AW		 649 has_msr_kvm_steal_time = c->eax & (1 << KVM_FEATURE_STEAL_TIME);
650 }
917367aa 651
a33609ca 652 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
05330448
AL		 653
654 for (i = 0; i <= limit; i++) {
f8bb0565
IM		 655 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
656 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
657 abort();
658 }
bb0300dc 659 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 660
661 switch (i) {
a36b1029
AL		 662 case 2: {
663 /* Keep reading function 2 till all the input is received */
664 int times;
665
a36b1029 666 c->function = i;
a33609ca
AL		 667 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
668 KVM_CPUID_FLAG_STATE_READ_NEXT;
669 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
670 times = c->eax & 0xff;
a36b1029
AL		 671
672 for (j = 1; j < times; ++j) {
f8bb0565
IM		 673 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
674 fprintf(stderr, "cpuid_data is full, no space for "
675 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
676 abort();
677 }
a33609ca 678 c = &cpuid_data.entries[cpuid_i++];
a36b1029 679 c->function = i;
a33609ca
AL		 680 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
681 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
a36b1029
AL		 682 }
683 break;
684 }
486bd5a2
AL		 685 case 4:
686 case 0xb:
687 case 0xd:
688 for (j = 0; ; j++) {
31e8c696
AP		 689 if (i == 0xd && j == 64) {
690 break;
691 }
486bd5a2
AL		 692 c->function = i;
693 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
694 c->index = j;
a33609ca 695 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2 696
b9bec74b 697 if (i == 4 && c->eax == 0) {
486bd5a2 698 break;
b9bec74b
JK		 699 }
700 if (i == 0xb && !(c->ecx & 0xff00)) {
486bd5a2 701 break;
b9bec74b
JK		 702 }
703 if (i == 0xd && c->eax == 0) {
31e8c696 704 continue;
b9bec74b 705 }
f8bb0565
IM		 706 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
707 fprintf(stderr, "cpuid_data is full, no space for "
708 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
709 abort();
710 }
a33609ca 711 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 712 }
713 break;
714 default:
486bd5a2 715 c->function = i;
a33609ca
AL		 716 c->flags = 0;
717 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2
AL		 718 break;
719 }
05330448 720 }
0d894367
PB		 721
722 if (limit >= 0x0a) {
723 uint32_t ver;
724
725 cpu_x86_cpuid(env, 0x0a, 0, &ver, &unused, &unused, &unused);
726 if ((ver & 0xff) > 0) {
727 has_msr_architectural_pmu = true;
728 num_architectural_pmu_counters = (ver & 0xff00) >> 8;
729
730 /* Shouldn't be more than 32, since that's the number of bits
731 * available in EBX to tell us _which_ counters are available.
732 * Play it safe.
733 */
734 if (num_architectural_pmu_counters > MAX_GP_COUNTERS) {
735 num_architectural_pmu_counters = MAX_GP_COUNTERS;
736 }
737 }
738 }
739
a33609ca 740 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
05330448
AL		 741
742 for (i = 0x80000000; i <= limit; i++) {
f8bb0565
IM		 743 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
744 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
745 abort();
746 }
bb0300dc 747 c = &cpuid_data.entries[cpuid_i++];
05330448 748
05330448 749 c->function = i;
a33609ca
AL		 750 c->flags = 0;
751 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
05330448
AL		 752 }
753
b3baa152
BW		 754 /* Call Centaur's CPUID instructions they are supported. */
755 if (env->cpuid_xlevel2 > 0) {
b3baa152
BW		 756 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
757
758 for (i = 0xC0000000; i <= limit; i++) {
f8bb0565
IM		 759 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
760 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
761 abort();
762 }
b3baa152
BW		 763 c = &cpuid_data.entries[cpuid_i++];
764
765 c->function = i;
766 c->flags = 0;
767 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
768 }
769 }
770
05330448
AL		 771 cpuid_data.cpuid.nent = cpuid_i;
772
e7701825 773 if (((env->cpuid_version >> 8)&0xF) >= 6
0514ef2f 774 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
fc7a504c 775 (CPUID_MCE | CPUID_MCA)
a60f24b5 776 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
e7701825
MT		 777 uint64_t mcg_cap;
778 int banks;
32a42024 779 int ret;
e7701825 780
a60f24b5 781 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
75d49497
JK		 782 if (ret < 0) {
783 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
784 return ret;
e7701825 785 }
75d49497 786
49b69cbf
EH		 787 if (banks < MCE_BANKS_DEF) {
788 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
789 MCE_BANKS_DEF, banks);
790 return -ENOTSUP;
75d49497 791 }
49b69cbf 792
75d49497 793 mcg_cap &= MCE_CAP_DEF;
49b69cbf 794 mcg_cap |= MCE_BANKS_DEF;
1bc22652 795 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &mcg_cap);
75d49497
JK		 796 if (ret < 0) {
797 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
798 return ret;
799 }
800
801 env->mcg_cap = mcg_cap;
e7701825 802 }
e7701825 803
b8cc45d6
GC		 804 qemu_add_vm_change_state_handler(cpu_update_state, env);
805
df67696e
LJ		 806 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
807 if (c) {
808 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
809 !!(c->ecx & CPUID_EXT_SMX);
810 }
811
68bfd0ad
MT		 812 c = cpuid_find_entry(&cpuid_data.cpuid, 0x80000007, 0);
813 if (c && (c->edx & 1<<8) && invtsc_mig_blocker == NULL) {
814 /* for migration */
815 error_setg(&invtsc_mig_blocker,
816 "State blocked by non-migratable CPU device"
817 " (invtsc flag)");
818 migrate_add_blocker(invtsc_mig_blocker);
819 /* for savevm */
820 vmstate_x86_cpu.unmigratable = 1;
821 }
822
7e680753 823 cpuid_data.cpuid.padding = 0;
1bc22652 824 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
fdc9c41a
JK		 825 if (r) {
826 return r;
827 }
e7429073 828
a60f24b5 829 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL);
e7429073 830 if (r && env->tsc_khz) {
1bc22652 831 r = kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz);
e7429073
JR		 832 if (r < 0) {
833 fprintf(stderr, "KVM_SET_TSC_KHZ failed\n");
834 return r;
835 }
836 }
e7429073 837
28143b40 838 if (has_xsave) {
fabacc0f
JK		 839 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
840 }
841
d1ae67f6
AW		 842 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
843 has_msr_mtrr = true;
844 }
845
e7429073 846 return 0;
05330448
AL		 847}
848
50a2c6e5 849void kvm_arch_reset_vcpu(X86CPU *cpu)
caa5af0f 850{
20d695a9 851 CPUX86State *env = &cpu->env;
dd673288 852
e73223a5 853 env->exception_injected = -1;
0e607a80 854 env->interrupt_injected = -1;
1a5e9d2f 855 env->xcr0 = 1;
ddced198 856 if (kvm_irqchip_in_kernel()) {
dd673288 857 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
ddced198
MT		 858 KVM_MP_STATE_UNINITIALIZED;
859 } else {
860 env->mp_state = KVM_MP_STATE_RUNNABLE;
861 }
caa5af0f
JK		 862}
863
e0723c45
PB		 864void kvm_arch_do_init_vcpu(X86CPU *cpu)
865{
866 CPUX86State *env = &cpu->env;
867
868 /* APs get directly into wait-for-SIPI state. */
869 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
870 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
871 }
872}
873
c3a3a7d3 874static int kvm_get_supported_msrs(KVMState *s)
05330448 875{
75b10c43 876 static int kvm_supported_msrs;
c3a3a7d3 877 int ret = 0;
05330448
AL		 878
879 /* first time */
75b10c43 880 if (kvm_supported_msrs == 0) {
05330448
AL		 881 struct kvm_msr_list msr_list, *kvm_msr_list;
882
75b10c43 883 kvm_supported_msrs = -1;
05330448
AL		 884
885 /* Obtain MSR list from KVM. These are the MSRs that we must
886 * save/restore */
4c9f7372 887 msr_list.nmsrs = 0;
c3a3a7d3 888 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
6fb6d245 889 if (ret < 0 && ret != -E2BIG) {
c3a3a7d3 890 return ret;
6fb6d245 891 }
d9db889f
JK		 892 /* Old kernel modules had a bug and could write beyond the provided
893 memory. Allocate at least a safe amount of 1K. */
7267c094 894 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
d9db889f
JK		 895 msr_list.nmsrs *
896 sizeof(msr_list.indices[0])));
05330448 897
55308450 898 kvm_msr_list->nmsrs = msr_list.nmsrs;
c3a3a7d3 899 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
05330448
AL		 900 if (ret >= 0) {
901 int i;
902
903 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
904 if (kvm_msr_list->indices[i] == MSR_STAR) {
c3a3a7d3 905 has_msr_star = true;
75b10c43
MT		 906 continue;
907 }
908 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
c3a3a7d3 909 has_msr_hsave_pa = true;
75b10c43 910 continue;
05330448 911 }
c9b8f6b6
AS		 912 if (kvm_msr_list->indices[i] == MSR_TSC_AUX) {
913 has_msr_tsc_aux = true;
914 continue;
915 }
f28558d3
WA		 916 if (kvm_msr_list->indices[i] == MSR_TSC_ADJUST) {
917 has_msr_tsc_adjust = true;
918 continue;
919 }
aa82ba54
LJ		 920 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
921 has_msr_tsc_deadline = true;
922 continue;
923 }
fc12d72e
PB		 924 if (kvm_msr_list->indices[i] == MSR_IA32_SMBASE) {
925 has_msr_smbase = true;
926 continue;
927 }
21e87c46
AK		 928 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
929 has_msr_misc_enable = true;
930 continue;
931 }
79e9ebeb
LJ		 932 if (kvm_msr_list->indices[i] == MSR_IA32_BNDCFGS) {
933 has_msr_bndcfgs = true;
934 continue;
935 }
18cd2c17
WL		 936 if (kvm_msr_list->indices[i] == MSR_IA32_XSS) {
937 has_msr_xss = true;
938 continue;
939 }
f2a53c9e
AS		 940 if (kvm_msr_list->indices[i] == HV_X64_MSR_CRASH_CTL) {
941 has_msr_hv_crash = true;
942 continue;
943 }
744b8a94
AS		 944 if (kvm_msr_list->indices[i] == HV_X64_MSR_RESET) {
945 has_msr_hv_reset = true;
946 continue;
947 }
8c145d7c
AS		 948 if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_INDEX) {
949 has_msr_hv_vpindex = true;
950 continue;
951 }
46eb8f98
AS		 952 if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_RUNTIME) {
953 has_msr_hv_runtime = true;
954 continue;
955 }
05330448
AL		 956 }
957 }
958
7267c094 959 g_free(kvm_msr_list);
05330448
AL		 960 }
961
c3a3a7d3 962 return ret;
05330448
AL		 963}
964
6410848b
PB		 965static Notifier smram_machine_done;
966static KVMMemoryListener smram_listener;
967static AddressSpace smram_address_space;
968static MemoryRegion smram_as_root;
969static MemoryRegion smram_as_mem;
970
971static void register_smram_listener(Notifier *n, void *unused)
972{
973 MemoryRegion *smram =
974 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
975
976 /* Outer container... */
977 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
978 memory_region_set_enabled(&smram_as_root, true);
979
980 /* ... with two regions inside: normal system memory with low
981 * priority, and...
982 */
983 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
984 get_system_memory(), 0, ~0ull);
985 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
986 memory_region_set_enabled(&smram_as_mem, true);
987
988 if (smram) {
989 /* ... SMRAM with higher priority */
990 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
991 memory_region_set_enabled(smram, true);
992 }
993
994 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
995 kvm_memory_listener_register(kvm_state, &smram_listener,
996 &smram_address_space, 1);
997}
998
b16565b3 999int kvm_arch_init(MachineState *ms, KVMState *s)
20420430 1000{
11076198 1001 uint64_t identity_base = 0xfffbc000;
39d6960a 1002 uint64_t shadow_mem;
20420430 1003 int ret;
25d2e361 1004 struct utsname utsname;
20420430 1005
28143b40
TH		 1006#ifdef KVM_CAP_XSAVE
1007 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
1008#endif
1009
1010#ifdef KVM_CAP_XCRS
1011 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
1012#endif
1013
1014#ifdef KVM_CAP_PIT_STATE2
1015 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
1016#endif
1017
c3a3a7d3 1018 ret = kvm_get_supported_msrs(s);
20420430 1019 if (ret < 0) {
20420430
SY		 1020 return ret;
1021 }
25d2e361
MT		 1022
1023 uname(&utsname);
1024 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1025
4c5b10b7 1026 /*
11076198
JK		 1027 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1028 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
1029 * Since these must be part of guest physical memory, we need to allocate
1030 * them, both by setting their start addresses in the kernel and by
1031 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1032 *
1033 * Older KVM versions may not support setting the identity map base. In
1034 * that case we need to stick with the default, i.e. a 256K maximum BIOS
1035 * size.
4c5b10b7 1036 */
11076198
JK		 1037 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1038 /* Allows up to 16M BIOSes. */
1039 identity_base = 0xfeffc000;
1040
1041 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1042 if (ret < 0) {
1043 return ret;
1044 }
4c5b10b7 1045 }
e56ff191 1046
11076198
JK		 1047 /* Set TSS base one page after EPT identity map. */
1048 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
20420430
SY		 1049 if (ret < 0) {
1050 return ret;
1051 }
1052
11076198
JK		 1053 /* Tell fw_cfg to notify the BIOS to reserve the range. */
1054 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
20420430 1055 if (ret < 0) {
11076198 1056 fprintf(stderr, "e820_add_entry() table is full\n");
20420430
SY		 1057 return ret;
1058 }
3c85e74f 1059 qemu_register_reset(kvm_unpoison_all, NULL);
20420430 1060
4689b77b 1061 shadow_mem = machine_kvm_shadow_mem(ms);
36ad0e94
MA		 1062 if (shadow_mem != -1) {
1063 shadow_mem /= 4096;
1064 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1065 if (ret < 0) {
1066 return ret;
39d6960a
JK		 1067 }
1068 }
6410848b
PB		 1069
1070 if (kvm_check_extension(s, KVM_CAP_X86_SMM)) {
1071 smram_machine_done.notify = register_smram_listener;
1072 qemu_add_machine_init_done_notifier(&smram_machine_done);
1073 }
11076198 1074 return 0;
05330448 1075}
b9bec74b 1076
05330448
AL		 1077static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1078{
1079 lhs->selector = rhs->selector;
1080 lhs->base = rhs->base;
1081 lhs->limit = rhs->limit;
1082 lhs->type = 3;
1083 lhs->present = 1;
1084 lhs->dpl = 3;
1085 lhs->db = 0;
1086 lhs->s = 1;
1087 lhs->l = 0;
1088 lhs->g = 0;
1089 lhs->avl = 0;
1090 lhs->unusable = 0;
1091}
1092
1093static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1094{
1095 unsigned flags = rhs->flags;
1096 lhs->selector = rhs->selector;
1097 lhs->base = rhs->base;
1098 lhs->limit = rhs->limit;
1099 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
1100 lhs->present = (flags & DESC_P_MASK) != 0;
acaa7550 1101 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
05330448
AL		 1102 lhs->db = (flags >> DESC_B_SHIFT) & 1;
1103 lhs->s = (flags & DESC_S_MASK) != 0;
1104 lhs->l = (flags >> DESC_L_SHIFT) & 1;
1105 lhs->g = (flags & DESC_G_MASK) != 0;
1106 lhs->avl = (flags & DESC_AVL_MASK) != 0;
1107 lhs->unusable = 0;
7e680753 1108 lhs->padding = 0;
05330448
AL		 1109}
1110
1111static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
1112{
1113 lhs->selector = rhs->selector;
1114 lhs->base = rhs->base;
1115 lhs->limit = rhs->limit;
b9bec74b
JK		 1116 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
1117 (rhs->present * DESC_P_MASK) |
1118 (rhs->dpl << DESC_DPL_SHIFT) |
1119 (rhs->db << DESC_B_SHIFT) |
1120 (rhs->s * DESC_S_MASK) |
1121 (rhs->l << DESC_L_SHIFT) |
1122 (rhs->g * DESC_G_MASK) |
1123 (rhs->avl * DESC_AVL_MASK);
05330448
AL		 1124}
1125
1126static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
1127{
b9bec74b 1128 if (set) {
05330448 1129 *kvm_reg = *qemu_reg;
b9bec74b 1130 } else {
05330448 1131 *qemu_reg = *kvm_reg;
b9bec74b 1132 }
05330448
AL		 1133}
1134
1bc22652 1135static int kvm_getput_regs(X86CPU *cpu, int set)
05330448 1136{
1bc22652 1137 CPUX86State *env = &cpu->env;
05330448
AL		 1138 struct kvm_regs regs;
1139 int ret = 0;
1140
1141 if (!set) {
1bc22652 1142 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
b9bec74b 1143 if (ret < 0) {
05330448 1144 return ret;
b9bec74b 1145 }
05330448
AL		 1146 }
1147
1148 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
1149 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
1150 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
1151 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
1152 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
1153 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
1154 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
1155 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
1156#ifdef TARGET_X86_64
1157 kvm_getput_reg(&regs.r8, &env->regs[8], set);
1158 kvm_getput_reg(&regs.r9, &env->regs[9], set);
1159 kvm_getput_reg(&regs.r10, &env->regs[10], set);
1160 kvm_getput_reg(&regs.r11, &env->regs[11], set);
1161 kvm_getput_reg(&regs.r12, &env->regs[12], set);
1162 kvm_getput_reg(&regs.r13, &env->regs[13], set);
1163 kvm_getput_reg(&regs.r14, &env->regs[14], set);
1164 kvm_getput_reg(&regs.r15, &env->regs[15], set);
1165#endif
1166
1167 kvm_getput_reg(&regs.rflags, &env->eflags, set);
1168 kvm_getput_reg(&regs.rip, &env->eip, set);
1169
b9bec74b 1170 if (set) {
1bc22652 1171 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
b9bec74b 1172 }
05330448
AL		 1173
1174 return ret;
1175}
1176
1bc22652 1177static int kvm_put_fpu(X86CPU *cpu)
05330448 1178{
1bc22652 1179 CPUX86State *env = &cpu->env;
05330448
AL		 1180 struct kvm_fpu fpu;
1181 int i;
1182
1183 memset(&fpu, 0, sizeof fpu);
1184 fpu.fsw = env->fpus & ~(7 << 11);
1185 fpu.fsw |= (env->fpstt & 7) << 11;
1186 fpu.fcw = env->fpuc;
42cc8fa6
JK		 1187 fpu.last_opcode = env->fpop;
1188 fpu.last_ip = env->fpip;
1189 fpu.last_dp = env->fpdp;
b9bec74b
JK		 1190 for (i = 0; i < 8; ++i) {
1191 fpu.ftwx |= (!env->fptags[i]) << i;
1192 }
05330448 1193 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
bee81887
PB		 1194 for (i = 0; i < CPU_NB_REGS; i++) {
1195 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].XMM_Q(0));
1196 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].XMM_Q(1));
1197 }
05330448
AL		 1198 fpu.mxcsr = env->mxcsr;
1199
1bc22652 1200 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
05330448
AL		 1201}
1202
6b42494b
JK		 1203#define XSAVE_FCW_FSW 0
1204#define XSAVE_FTW_FOP 1
f1665b21
SY		 1205#define XSAVE_CWD_RIP 2
1206#define XSAVE_CWD_RDP 4
1207#define XSAVE_MXCSR 6
1208#define XSAVE_ST_SPACE 8
1209#define XSAVE_XMM_SPACE 40
1210#define XSAVE_XSTATE_BV 128
1211#define XSAVE_YMMH_SPACE 144
79e9ebeb
LJ		 1212#define XSAVE_BNDREGS 240
1213#define XSAVE_BNDCSR 256
9aecd6f8
CP		 1214#define XSAVE_OPMASK 272
1215#define XSAVE_ZMM_Hi256 288
1216#define XSAVE_Hi16_ZMM 416
f1665b21 1217
1bc22652 1218static int kvm_put_xsave(X86CPU *cpu)
f1665b21 1219{
1bc22652 1220 CPUX86State *env = &cpu->env;
fabacc0f 1221 struct kvm_xsave* xsave = env->kvm_xsave_buf;
42cc8fa6 1222 uint16_t cwd, swd, twd;
b7711471 1223 uint8_t *xmm, *ymmh, *zmmh;
fabacc0f 1224 int i, r;
f1665b21 1225
28143b40 1226 if (!has_xsave) {
1bc22652 1227 return kvm_put_fpu(cpu);
b9bec74b 1228 }
f1665b21 1229
f1665b21 1230 memset(xsave, 0, sizeof(struct kvm_xsave));
6115c0a8 1231 twd = 0;
f1665b21
SY		 1232 swd = env->fpus & ~(7 << 11);
1233 swd |= (env->fpstt & 7) << 11;
1234 cwd = env->fpuc;
b9bec74b 1235 for (i = 0; i < 8; ++i) {
f1665b21 1236 twd |= (!env->fptags[i]) << i;
b9bec74b 1237 }
6b42494b
JK		 1238 xsave->region[XSAVE_FCW_FSW] = (uint32_t)(swd << 16) + cwd;
1239 xsave->region[XSAVE_FTW_FOP] = (uint32_t)(env->fpop << 16) + twd;
42cc8fa6
JK		 1240 memcpy(&xsave->region[XSAVE_CWD_RIP], &env->fpip, sizeof(env->fpip));
1241 memcpy(&xsave->region[XSAVE_CWD_RDP], &env->fpdp, sizeof(env->fpdp));
f1665b21
SY		 1242 memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
1243 sizeof env->fpregs);
f1665b21
SY		 1244 xsave->region[XSAVE_MXCSR] = env->mxcsr;
1245 *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
79e9ebeb
LJ		 1246 memcpy(&xsave->region[XSAVE_BNDREGS], env->bnd_regs,
1247 sizeof env->bnd_regs);
1248 memcpy(&xsave->region[XSAVE_BNDCSR], &env->bndcs_regs,
1249 sizeof(env->bndcs_regs));
9aecd6f8
CP		 1250 memcpy(&xsave->region[XSAVE_OPMASK], env->opmask_regs,
1251 sizeof env->opmask_regs);
bee81887
PB		 1252
1253 xmm = (uint8_t *)&xsave->region[XSAVE_XMM_SPACE];
b7711471
PB		 1254 ymmh = (uint8_t *)&xsave->region[XSAVE_YMMH_SPACE];
1255 zmmh = (uint8_t *)&xsave->region[XSAVE_ZMM_Hi256];
1256 for (i = 0; i < CPU_NB_REGS; i++, xmm += 16, ymmh += 16, zmmh += 32) {
bee81887
PB		 1257 stq_p(xmm, env->xmm_regs[i].XMM_Q(0));
1258 stq_p(xmm+8, env->xmm_regs[i].XMM_Q(1));
b7711471
PB		 1259 stq_p(ymmh, env->xmm_regs[i].XMM_Q(2));
1260 stq_p(ymmh+8, env->xmm_regs[i].XMM_Q(3));
1261 stq_p(zmmh, env->xmm_regs[i].XMM_Q(4));
1262 stq_p(zmmh+8, env->xmm_regs[i].XMM_Q(5));
1263 stq_p(zmmh+16, env->xmm_regs[i].XMM_Q(6));
1264 stq_p(zmmh+24, env->xmm_regs[i].XMM_Q(7));
bee81887
PB		 1265 }
1266
9aecd6f8 1267#ifdef TARGET_X86_64
b7711471
PB		 1268 memcpy(&xsave->region[XSAVE_Hi16_ZMM], &env->xmm_regs[16],
1269 16 * sizeof env->xmm_regs[16]);
9aecd6f8 1270#endif
1bc22652 1271 r = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
0f53994f 1272 return r;
f1665b21
SY		 1273}
1274
1bc22652 1275static int kvm_put_xcrs(X86CPU *cpu)
f1665b21 1276{
1bc22652 1277 CPUX86State *env = &cpu->env;
bdfc8480 1278 struct kvm_xcrs xcrs = {};
f1665b21 1279
28143b40 1280 if (!has_xcrs) {
f1665b21 1281 return 0;
b9bec74b 1282 }
f1665b21
SY		 1283
1284 xcrs.nr_xcrs = 1;
1285 xcrs.flags = 0;
1286 xcrs.xcrs[0].xcr = 0;
1287 xcrs.xcrs[0].value = env->xcr0;
1bc22652 1288 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
f1665b21
SY		 1289}
1290
1bc22652 1291static int kvm_put_sregs(X86CPU *cpu)
05330448 1292{
1bc22652 1293 CPUX86State *env = &cpu->env;
05330448
AL		 1294 struct kvm_sregs sregs;
1295
0e607a80
JK		 1296 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1297 if (env->interrupt_injected >= 0) {
1298 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1299 (uint64_t)1 << (env->interrupt_injected % 64);
1300 }
05330448
AL		 1301
1302 if ((env->eflags & VM_MASK)) {
b9bec74b
JK		 1303 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1304 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1305 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1306 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1307 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1308 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
05330448 1309 } else {
b9bec74b
JK		 1310 set_seg(&sregs.cs, &env->segs[R_CS]);
1311 set_seg(&sregs.ds, &env->segs[R_DS]);
1312 set_seg(&sregs.es, &env->segs[R_ES]);
1313 set_seg(&sregs.fs, &env->segs[R_FS]);
1314 set_seg(&sregs.gs, &env->segs[R_GS]);
1315 set_seg(&sregs.ss, &env->segs[R_SS]);
05330448
AL		 1316 }
1317
1318 set_seg(&sregs.tr, &env->tr);
1319 set_seg(&sregs.ldt, &env->ldt);
1320
1321 sregs.idt.limit = env->idt.limit;
1322 sregs.idt.base = env->idt.base;
7e680753 1323 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
05330448
AL		 1324 sregs.gdt.limit = env->gdt.limit;
1325 sregs.gdt.base = env->gdt.base;
7e680753 1326 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
05330448
AL		 1327
1328 sregs.cr0 = env->cr[0];
1329 sregs.cr2 = env->cr[2];
1330 sregs.cr3 = env->cr[3];
1331 sregs.cr4 = env->cr[4];
1332
02e51483
CF		 1333 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1334 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
05330448
AL		 1335
1336 sregs.efer = env->efer;
1337
1bc22652 1338 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
05330448
AL		 1339}
1340
1341static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
1342 uint32_t index, uint64_t value)
1343{
1344 entry->index = index;
c7fe4b12 1345 entry->reserved = 0;
05330448
AL		 1346 entry->data = value;
1347}
1348
7477cd38
MT		 1349static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1350{
1351 CPUX86State *env = &cpu->env;
1352 struct {
1353 struct kvm_msrs info;
1354 struct kvm_msr_entry entries[1];
1355 } msr_data;
1356 struct kvm_msr_entry *msrs = msr_data.entries;
1357
1358 if (!has_msr_tsc_deadline) {
1359 return 0;
1360 }
1361
1362 kvm_msr_entry_set(&msrs[0], MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1363
c7fe4b12
CB		 1364 msr_data.info = (struct kvm_msrs) {
1365 .nmsrs = 1,
1366 };
7477cd38
MT		 1367
1368 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1369}
1370
6bdf863d
JK		 1371/*
1372 * Provide a separate write service for the feature control MSR in order to
1373 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1374 * before writing any other state because forcibly leaving nested mode
1375 * invalidates the VCPU state.
1376 */
1377static int kvm_put_msr_feature_control(X86CPU *cpu)
1378{
1379 struct {
1380 struct kvm_msrs info;
1381 struct kvm_msr_entry entry;
1382 } msr_data;
1383
1384 kvm_msr_entry_set(&msr_data.entry, MSR_IA32_FEATURE_CONTROL,
1385 cpu->env.msr_ia32_feature_control);
c7fe4b12
CB		 1386
1387 msr_data.info = (struct kvm_msrs) {
1388 .nmsrs = 1,
1389 };
1390
6bdf863d
JK		 1391 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1392}
1393
1bc22652 1394static int kvm_put_msrs(X86CPU *cpu, int level)
05330448 1395{
1bc22652 1396 CPUX86State *env = &cpu->env;
05330448
AL		 1397 struct {
1398 struct kvm_msrs info;
d1ae67f6 1399 struct kvm_msr_entry entries[150];
05330448
AL		 1400 } msr_data;
1401 struct kvm_msr_entry *msrs = msr_data.entries;
0d894367 1402 int n = 0, i;
05330448
AL		 1403
1404 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1405 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1406 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
0c03266a 1407 kvm_msr_entry_set(&msrs[n++], MSR_PAT, env->pat);
c3a3a7d3 1408 if (has_msr_star) {
b9bec74b
JK		 1409 kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
1410 }
c3a3a7d3 1411 if (has_msr_hsave_pa) {
75b10c43 1412 kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
b9bec74b 1413 }
c9b8f6b6
AS		 1414 if (has_msr_tsc_aux) {
1415 kvm_msr_entry_set(&msrs[n++], MSR_TSC_AUX, env->tsc_aux);
1416 }
f28558d3
WA		 1417 if (has_msr_tsc_adjust) {
1418 kvm_msr_entry_set(&msrs[n++], MSR_TSC_ADJUST, env->tsc_adjust);
1419 }
21e87c46
AK		 1420 if (has_msr_misc_enable) {
1421 kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE,
1422 env->msr_ia32_misc_enable);
1423 }
fc12d72e
PB		 1424 if (has_msr_smbase) {
1425 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SMBASE, env->smbase);
1426 }
439d19f2
PB		 1427 if (has_msr_bndcfgs) {
1428 kvm_msr_entry_set(&msrs[n++], MSR_IA32_BNDCFGS, env->msr_bndcfgs);
1429 }
18cd2c17
WL		 1430 if (has_msr_xss) {
1431 kvm_msr_entry_set(&msrs[n++], MSR_IA32_XSS, env->xss);
1432 }
05330448 1433#ifdef TARGET_X86_64
25d2e361
MT		 1434 if (lm_capable_kernel) {
1435 kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
1436 kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
1437 kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
1438 kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
1439 }
05330448 1440#endif
ff5c186b 1441 /*
0d894367
PB		 1442 * The following MSRs have side effects on the guest or are too heavy
1443 * for normal writeback. Limit them to reset or full state updates.
ff5c186b
JK		 1444 */
1445 if (level >= KVM_PUT_RESET_STATE) {
0522604b 1446 kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
ea643051
JK		 1447 kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
1448 env->system_time_msr);
1449 kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
c5999bfc
JK		 1450 if (has_msr_async_pf_en) {
1451 kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN,
1452 env->async_pf_en_msr);
1453 }
bc9a839d
MT		 1454 if (has_msr_pv_eoi_en) {
1455 kvm_msr_entry_set(&msrs[n++], MSR_KVM_PV_EOI_EN,
1456 env->pv_eoi_en_msr);
1457 }
917367aa
MT		 1458 if (has_msr_kvm_steal_time) {
1459 kvm_msr_entry_set(&msrs[n++], MSR_KVM_STEAL_TIME,
1460 env->steal_time_msr);
1461 }
0d894367
PB		 1462 if (has_msr_architectural_pmu) {
1463 /* Stop the counter. */
1464 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1465 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL, 0);
1466
1467 /* Set the counter values. */
1468 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1469 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR0 + i,
1470 env->msr_fixed_counters[i]);
1471 }
1472 for (i = 0; i < num_architectural_pmu_counters; i++) {
1473 kvm_msr_entry_set(&msrs[n++], MSR_P6_PERFCTR0 + i,
1474 env->msr_gp_counters[i]);
1475 kvm_msr_entry_set(&msrs[n++], MSR_P6_EVNTSEL0 + i,
1476 env->msr_gp_evtsel[i]);
1477 }
1478 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_STATUS,
1479 env->msr_global_status);
1480 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1481 env->msr_global_ovf_ctrl);
1482
1483 /* Now start the PMU. */
1484 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL,
1485 env->msr_fixed_ctr_ctrl);
1486 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL,
1487 env->msr_global_ctrl);
1488 }
7bc3d711 1489 if (has_msr_hv_hypercall) {
1c90ef26
VR		 1490 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_GUEST_OS_ID,
1491 env->msr_hv_guest_os_id);
1492 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_HYPERCALL,
1493 env->msr_hv_hypercall);
eab70139 1494 }
7bc3d711 1495 if (has_msr_hv_vapic) {
5ef68987
VR		 1496 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_APIC_ASSIST_PAGE,
1497 env->msr_hv_vapic);
eab70139 1498 }
48a5f3bc
VR		 1499 if (has_msr_hv_tsc) {
1500 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_REFERENCE_TSC,
1501 env->msr_hv_tsc);
1502 }
f2a53c9e
AS		 1503 if (has_msr_hv_crash) {
1504 int j;
1505
1506 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++)
1507 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_CRASH_P0 + j,
1508 env->msr_hv_crash_params[j]);
1509
1510 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_CRASH_CTL,
1511 HV_X64_MSR_CRASH_CTL_NOTIFY);
1512 }
46eb8f98
AS		 1513 if (has_msr_hv_runtime) {
1514 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_VP_RUNTIME,
1515 env->msr_hv_runtime);
1516 }
d1ae67f6
AW		 1517 if (has_msr_mtrr) {
1518 kvm_msr_entry_set(&msrs[n++], MSR_MTRRdefType, env->mtrr_deftype);
1519 kvm_msr_entry_set(&msrs[n++],
1520 MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
1521 kvm_msr_entry_set(&msrs[n++],
1522 MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
1523 kvm_msr_entry_set(&msrs[n++],
1524 MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
1525 kvm_msr_entry_set(&msrs[n++],
1526 MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
1527 kvm_msr_entry_set(&msrs[n++],
1528 MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
1529 kvm_msr_entry_set(&msrs[n++],
1530 MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
1531 kvm_msr_entry_set(&msrs[n++],
1532 MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
1533 kvm_msr_entry_set(&msrs[n++],
1534 MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
1535 kvm_msr_entry_set(&msrs[n++],
1536 MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
1537 kvm_msr_entry_set(&msrs[n++],
1538 MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
1539 kvm_msr_entry_set(&msrs[n++],
1540 MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
1541 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
1542 kvm_msr_entry_set(&msrs[n++],
1543 MSR_MTRRphysBase(i), env->mtrr_var[i].base);
1544 kvm_msr_entry_set(&msrs[n++],
1545 MSR_MTRRphysMask(i), env->mtrr_var[i].mask);
1546 }
1547 }
6bdf863d
JK		 1548
1549 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1550 * kvm_put_msr_feature_control. */
ea643051 1551 }
57780495 1552 if (env->mcg_cap) {
d8da8574 1553 int i;
b9bec74b 1554
c34d440a
JK		 1555 kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
1556 kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl);
1557 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1558 kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]);
57780495
MT		 1559 }
1560 }
1a03675d 1561
c7fe4b12
CB		 1562 msr_data.info = (struct kvm_msrs) {
1563 .nmsrs = n,
1564 };
05330448 1565
1bc22652 1566 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
05330448
AL		 1567
1568}
1569
1570
1bc22652 1571static int kvm_get_fpu(X86CPU *cpu)
05330448 1572{
1bc22652 1573 CPUX86State *env = &cpu->env;
05330448
AL		 1574 struct kvm_fpu fpu;
1575 int i, ret;
1576
1bc22652 1577 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
b9bec74b 1578 if (ret < 0) {
05330448 1579 return ret;
b9bec74b 1580 }
05330448
AL		 1581
1582 env->fpstt = (fpu.fsw >> 11) & 7;
1583 env->fpus = fpu.fsw;
1584 env->fpuc = fpu.fcw;
42cc8fa6
JK		 1585 env->fpop = fpu.last_opcode;
1586 env->fpip = fpu.last_ip;
1587 env->fpdp = fpu.last_dp;
b9bec74b
JK		 1588 for (i = 0; i < 8; ++i) {
1589 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1590 }
05330448 1591 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
bee81887
PB		 1592 for (i = 0; i < CPU_NB_REGS; i++) {
1593 env->xmm_regs[i].XMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
1594 env->xmm_regs[i].XMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
1595 }
05330448
AL		 1596 env->mxcsr = fpu.mxcsr;
1597
1598 return 0;
1599}
1600
1bc22652 1601static int kvm_get_xsave(X86CPU *cpu)
f1665b21 1602{
1bc22652 1603 CPUX86State *env = &cpu->env;
fabacc0f 1604 struct kvm_xsave* xsave = env->kvm_xsave_buf;
f1665b21 1605 int ret, i;
b7711471 1606 const uint8_t *xmm, *ymmh, *zmmh;
42cc8fa6 1607 uint16_t cwd, swd, twd;
f1665b21 1608
28143b40 1609 if (!has_xsave) {
1bc22652 1610 return kvm_get_fpu(cpu);
b9bec74b 1611 }
f1665b21 1612
1bc22652 1613 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
0f53994f 1614 if (ret < 0) {
f1665b21 1615 return ret;
0f53994f 1616 }
f1665b21 1617
6b42494b
JK		 1618 cwd = (uint16_t)xsave->region[XSAVE_FCW_FSW];
1619 swd = (uint16_t)(xsave->region[XSAVE_FCW_FSW] >> 16);
1620 twd = (uint16_t)xsave->region[XSAVE_FTW_FOP];
1621 env->fpop = (uint16_t)(xsave->region[XSAVE_FTW_FOP] >> 16);
f1665b21
SY		 1622 env->fpstt = (swd >> 11) & 7;
1623 env->fpus = swd;
1624 env->fpuc = cwd;
b9bec74b 1625 for (i = 0; i < 8; ++i) {
f1665b21 1626 env->fptags[i] = !((twd >> i) & 1);
b9bec74b 1627 }
42cc8fa6
JK		 1628 memcpy(&env->fpip, &xsave->region[XSAVE_CWD_RIP], sizeof(env->fpip));
1629 memcpy(&env->fpdp, &xsave->region[XSAVE_CWD_RDP], sizeof(env->fpdp));
f1665b21
SY		 1630 env->mxcsr = xsave->region[XSAVE_MXCSR];
1631 memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
1632 sizeof env->fpregs);
f1665b21 1633 env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
79e9ebeb
LJ		 1634 memcpy(env->bnd_regs, &xsave->region[XSAVE_BNDREGS],
1635 sizeof env->bnd_regs);
1636 memcpy(&env->bndcs_regs, &xsave->region[XSAVE_BNDCSR],
1637 sizeof(env->bndcs_regs));
9aecd6f8
CP		 1638 memcpy(env->opmask_regs, &xsave->region[XSAVE_OPMASK],
1639 sizeof env->opmask_regs);
bee81887
PB		 1640
1641 xmm = (const uint8_t *)&xsave->region[XSAVE_XMM_SPACE];
b7711471
PB		 1642 ymmh = (const uint8_t *)&xsave->region[XSAVE_YMMH_SPACE];
1643 zmmh = (const uint8_t *)&xsave->region[XSAVE_ZMM_Hi256];
1644 for (i = 0; i < CPU_NB_REGS; i++, xmm += 16, ymmh += 16, zmmh += 32) {
bee81887
PB		 1645 env->xmm_regs[i].XMM_Q(0) = ldq_p(xmm);
1646 env->xmm_regs[i].XMM_Q(1) = ldq_p(xmm+8);
b7711471
PB		 1647 env->xmm_regs[i].XMM_Q(2) = ldq_p(ymmh);
1648 env->xmm_regs[i].XMM_Q(3) = ldq_p(ymmh+8);
1649 env->xmm_regs[i].XMM_Q(4) = ldq_p(zmmh);
1650 env->xmm_regs[i].XMM_Q(5) = ldq_p(zmmh+8);
1651 env->xmm_regs[i].XMM_Q(6) = ldq_p(zmmh+16);
1652 env->xmm_regs[i].XMM_Q(7) = ldq_p(zmmh+24);
bee81887
PB		 1653 }
1654
9aecd6f8 1655#ifdef TARGET_X86_64
b7711471
PB		 1656 memcpy(&env->xmm_regs[16], &xsave->region[XSAVE_Hi16_ZMM],
1657 16 * sizeof env->xmm_regs[16]);
9aecd6f8 1658#endif
f1665b21 1659 return 0;
f1665b21
SY		 1660}
1661
1bc22652 1662static int kvm_get_xcrs(X86CPU *cpu)
f1665b21 1663{
1bc22652 1664 CPUX86State *env = &cpu->env;
f1665b21
SY		 1665 int i, ret;
1666 struct kvm_xcrs xcrs;
1667
28143b40 1668 if (!has_xcrs) {
f1665b21 1669 return 0;
b9bec74b 1670 }
f1665b21 1671
1bc22652 1672 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
b9bec74b 1673 if (ret < 0) {
f1665b21 1674 return ret;
b9bec74b 1675 }
f1665b21 1676
b9bec74b 1677 for (i = 0; i < xcrs.nr_xcrs; i++) {
f1665b21 1678 /* Only support xcr0 now */
0fd53fec
PB		 1679 if (xcrs.xcrs[i].xcr == 0) {
1680 env->xcr0 = xcrs.xcrs[i].value;
f1665b21
SY		 1681 break;
1682 }
b9bec74b 1683 }
f1665b21 1684 return 0;
f1665b21
SY		 1685}
1686
1bc22652 1687static int kvm_get_sregs(X86CPU *cpu)
05330448 1688{
1bc22652 1689 CPUX86State *env = &cpu->env;
05330448
AL		 1690 struct kvm_sregs sregs;
1691 uint32_t hflags;
0e607a80 1692 int bit, i, ret;
05330448 1693
1bc22652 1694 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
b9bec74b 1695 if (ret < 0) {
05330448 1696 return ret;
b9bec74b 1697 }
05330448 1698
0e607a80
JK		 1699 /* There can only be one pending IRQ set in the bitmap at a time, so try
1700 to find it and save its number instead (-1 for none). */
1701 env->interrupt_injected = -1;
1702 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1703 if (sregs.interrupt_bitmap[i]) {
1704 bit = ctz64(sregs.interrupt_bitmap[i]);
1705 env->interrupt_injected = i * 64 + bit;
1706 break;
1707 }
1708 }
05330448
AL		 1709
1710 get_seg(&env->segs[R_CS], &sregs.cs);
1711 get_seg(&env->segs[R_DS], &sregs.ds);
1712 get_seg(&env->segs[R_ES], &sregs.es);
1713 get_seg(&env->segs[R_FS], &sregs.fs);
1714 get_seg(&env->segs[R_GS], &sregs.gs);
1715 get_seg(&env->segs[R_SS], &sregs.ss);
1716
1717 get_seg(&env->tr, &sregs.tr);
1718 get_seg(&env->ldt, &sregs.ldt);
1719
1720 env->idt.limit = sregs.idt.limit;
1721 env->idt.base = sregs.idt.base;
1722 env->gdt.limit = sregs.gdt.limit;
1723 env->gdt.base = sregs.gdt.base;
1724
1725 env->cr[0] = sregs.cr0;
1726 env->cr[2] = sregs.cr2;
1727 env->cr[3] = sregs.cr3;
1728 env->cr[4] = sregs.cr4;
1729
05330448 1730 env->efer = sregs.efer;
cce47516
JK		 1731
1732 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
05330448 1733
b9bec74b
JK		 1734#define HFLAG_COPY_MASK \
1735 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1736 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1737 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1738 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
05330448 1739
7125c937 1740 hflags = (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
05330448
AL		 1741 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1742 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
b9bec74b 1743 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
05330448
AL		 1744 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1745 hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
b9bec74b 1746 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
05330448
AL		 1747
1748 if (env->efer & MSR_EFER_LMA) {
1749 hflags |= HF_LMA_MASK;
1750 }
1751
1752 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1753 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1754 } else {
1755 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
b9bec74b 1756 (DESC_B_SHIFT - HF_CS32_SHIFT);
05330448 1757 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
b9bec74b
JK		 1758 (DESC_B_SHIFT - HF_SS32_SHIFT);
1759 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1760 !(hflags & HF_CS32_MASK)) {
1761 hflags |= HF_ADDSEG_MASK;
1762 } else {
1763 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1764 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1765 }
05330448
AL		 1766 }
1767 env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
05330448
AL		 1768
1769 return 0;
1770}
1771
1bc22652 1772static int kvm_get_msrs(X86CPU *cpu)
05330448 1773{
1bc22652 1774 CPUX86State *env = &cpu->env;
05330448
AL		 1775 struct {
1776 struct kvm_msrs info;
d1ae67f6 1777 struct kvm_msr_entry entries[150];
05330448
AL		 1778 } msr_data;
1779 struct kvm_msr_entry *msrs = msr_data.entries;
1780 int ret, i, n;
1781
1782 n = 0;
1783 msrs[n++].index = MSR_IA32_SYSENTER_CS;
1784 msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1785 msrs[n++].index = MSR_IA32_SYSENTER_EIP;
0c03266a 1786 msrs[n++].index = MSR_PAT;
c3a3a7d3 1787 if (has_msr_star) {
b9bec74b
JK		 1788 msrs[n++].index = MSR_STAR;
1789 }
c3a3a7d3 1790 if (has_msr_hsave_pa) {
75b10c43 1791 msrs[n++].index = MSR_VM_HSAVE_PA;
b9bec74b 1792 }
c9b8f6b6
AS		 1793 if (has_msr_tsc_aux) {
1794 msrs[n++].index = MSR_TSC_AUX;
1795 }
f28558d3
WA		 1796 if (has_msr_tsc_adjust) {
1797 msrs[n++].index = MSR_TSC_ADJUST;
1798 }
aa82ba54
LJ		 1799 if (has_msr_tsc_deadline) {
1800 msrs[n++].index = MSR_IA32_TSCDEADLINE;
1801 }
21e87c46
AK		 1802 if (has_msr_misc_enable) {
1803 msrs[n++].index = MSR_IA32_MISC_ENABLE;
1804 }
fc12d72e
PB		 1805 if (has_msr_smbase) {
1806 msrs[n++].index = MSR_IA32_SMBASE;
1807 }
df67696e
LJ		 1808 if (has_msr_feature_control) {
1809 msrs[n++].index = MSR_IA32_FEATURE_CONTROL;
1810 }
79e9ebeb
LJ		 1811 if (has_msr_bndcfgs) {
1812 msrs[n++].index = MSR_IA32_BNDCFGS;
1813 }
18cd2c17
WL		 1814 if (has_msr_xss) {
1815 msrs[n++].index = MSR_IA32_XSS;
1816 }
1817
b8cc45d6
GC		 1818
1819 if (!env->tsc_valid) {
1820 msrs[n++].index = MSR_IA32_TSC;
1354869c 1821 env->tsc_valid = !runstate_is_running();
b8cc45d6
GC		 1822 }
1823
05330448 1824#ifdef TARGET_X86_64
25d2e361
MT		 1825 if (lm_capable_kernel) {
1826 msrs[n++].index = MSR_CSTAR;
1827 msrs[n++].index = MSR_KERNELGSBASE;
1828 msrs[n++].index = MSR_FMASK;
1829 msrs[n++].index = MSR_LSTAR;
1830 }
05330448 1831#endif
1a03675d
GC		 1832 msrs[n++].index = MSR_KVM_SYSTEM_TIME;
1833 msrs[n++].index = MSR_KVM_WALL_CLOCK;
c5999bfc
JK		 1834 if (has_msr_async_pf_en) {
1835 msrs[n++].index = MSR_KVM_ASYNC_PF_EN;
1836 }
bc9a839d
MT		 1837 if (has_msr_pv_eoi_en) {
1838 msrs[n++].index = MSR_KVM_PV_EOI_EN;
1839 }
917367aa
MT		 1840 if (has_msr_kvm_steal_time) {
1841 msrs[n++].index = MSR_KVM_STEAL_TIME;
1842 }
0d894367
PB		 1843 if (has_msr_architectural_pmu) {
1844 msrs[n++].index = MSR_CORE_PERF_FIXED_CTR_CTRL;
1845 msrs[n++].index = MSR_CORE_PERF_GLOBAL_CTRL;
1846 msrs[n++].index = MSR_CORE_PERF_GLOBAL_STATUS;
1847 msrs[n++].index = MSR_CORE_PERF_GLOBAL_OVF_CTRL;
1848 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1849 msrs[n++].index = MSR_CORE_PERF_FIXED_CTR0 + i;
1850 }
1851 for (i = 0; i < num_architectural_pmu_counters; i++) {
1852 msrs[n++].index = MSR_P6_PERFCTR0 + i;
1853 msrs[n++].index = MSR_P6_EVNTSEL0 + i;
1854 }
1855 }
1a03675d 1856
57780495
MT		 1857 if (env->mcg_cap) {
1858 msrs[n++].index = MSR_MCG_STATUS;
1859 msrs[n++].index = MSR_MCG_CTL;
b9bec74b 1860 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
57780495 1861 msrs[n++].index = MSR_MC0_CTL + i;
b9bec74b 1862 }
57780495 1863 }
57780495 1864
1c90ef26
VR		 1865 if (has_msr_hv_hypercall) {
1866 msrs[n++].index = HV_X64_MSR_HYPERCALL;
1867 msrs[n++].index = HV_X64_MSR_GUEST_OS_ID;
1868 }
5ef68987
VR		 1869 if (has_msr_hv_vapic) {
1870 msrs[n++].index = HV_X64_MSR_APIC_ASSIST_PAGE;
1871 }
48a5f3bc
VR		 1872 if (has_msr_hv_tsc) {
1873 msrs[n++].index = HV_X64_MSR_REFERENCE_TSC;
1874 }
f2a53c9e
AS		 1875 if (has_msr_hv_crash) {
1876 int j;
1877
1878 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++) {
1879 msrs[n++].index = HV_X64_MSR_CRASH_P0 + j;
1880 }
1881 }
46eb8f98
AS		 1882 if (has_msr_hv_runtime) {
1883 msrs[n++].index = HV_X64_MSR_VP_RUNTIME;
1884 }
d1ae67f6
AW		 1885 if (has_msr_mtrr) {
1886 msrs[n++].index = MSR_MTRRdefType;
1887 msrs[n++].index = MSR_MTRRfix64K_00000;
1888 msrs[n++].index = MSR_MTRRfix16K_80000;
1889 msrs[n++].index = MSR_MTRRfix16K_A0000;
1890 msrs[n++].index = MSR_MTRRfix4K_C0000;
1891 msrs[n++].index = MSR_MTRRfix4K_C8000;
1892 msrs[n++].index = MSR_MTRRfix4K_D0000;
1893 msrs[n++].index = MSR_MTRRfix4K_D8000;
1894 msrs[n++].index = MSR_MTRRfix4K_E0000;
1895 msrs[n++].index = MSR_MTRRfix4K_E8000;
1896 msrs[n++].index = MSR_MTRRfix4K_F0000;
1897 msrs[n++].index = MSR_MTRRfix4K_F8000;
1898 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
1899 msrs[n++].index = MSR_MTRRphysBase(i);
1900 msrs[n++].index = MSR_MTRRphysMask(i);
1901 }
1902 }
5ef68987 1903
d19ae73e
CB		 1904 msr_data.info = (struct kvm_msrs) {
1905 .nmsrs = n,
1906 };
1907
1bc22652 1908 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
b9bec74b 1909 if (ret < 0) {
05330448 1910 return ret;
b9bec74b 1911 }
05330448
AL		 1912
1913 for (i = 0; i < ret; i++) {
0d894367
PB		 1914 uint32_t index = msrs[i].index;
1915 switch (index) {
05330448
AL		 1916 case MSR_IA32_SYSENTER_CS:
1917 env->sysenter_cs = msrs[i].data;
1918 break;
1919 case MSR_IA32_SYSENTER_ESP:
1920 env->sysenter_esp = msrs[i].data;
1921 break;
1922 case MSR_IA32_SYSENTER_EIP:
1923 env->sysenter_eip = msrs[i].data;
1924 break;
0c03266a
JK		 1925 case MSR_PAT:
1926 env->pat = msrs[i].data;
1927 break;
05330448
AL		 1928 case MSR_STAR:
1929 env->star = msrs[i].data;
1930 break;
1931#ifdef TARGET_X86_64
1932 case MSR_CSTAR:
1933 env->cstar = msrs[i].data;
1934 break;
1935 case MSR_KERNELGSBASE:
1936 env->kernelgsbase = msrs[i].data;
1937 break;
1938 case MSR_FMASK:
1939 env->fmask = msrs[i].data;
1940 break;
1941 case MSR_LSTAR:
1942 env->lstar = msrs[i].data;
1943 break;
1944#endif
1945 case MSR_IA32_TSC:
1946 env->tsc = msrs[i].data;
1947 break;
c9b8f6b6
AS		 1948 case MSR_TSC_AUX:
1949 env->tsc_aux = msrs[i].data;
1950 break;
f28558d3
WA		 1951 case MSR_TSC_ADJUST:
1952 env->tsc_adjust = msrs[i].data;
1953 break;
aa82ba54
LJ		 1954 case MSR_IA32_TSCDEADLINE:
1955 env->tsc_deadline = msrs[i].data;
1956 break;
aa851e36
MT		 1957 case MSR_VM_HSAVE_PA:
1958 env->vm_hsave = msrs[i].data;
1959 break;
1a03675d
GC		 1960 case MSR_KVM_SYSTEM_TIME:
1961 env->system_time_msr = msrs[i].data;
1962 break;
1963 case MSR_KVM_WALL_CLOCK:
1964 env->wall_clock_msr = msrs[i].data;
1965 break;
57780495
MT		 1966 case MSR_MCG_STATUS:
1967 env->mcg_status = msrs[i].data;
1968 break;
1969 case MSR_MCG_CTL:
1970 env->mcg_ctl = msrs[i].data;
1971 break;
21e87c46
AK		 1972 case MSR_IA32_MISC_ENABLE:
1973 env->msr_ia32_misc_enable = msrs[i].data;
1974 break;
fc12d72e
PB		 1975 case MSR_IA32_SMBASE:
1976 env->smbase = msrs[i].data;
1977 break;
0779caeb
ACL		 1978 case MSR_IA32_FEATURE_CONTROL:
1979 env->msr_ia32_feature_control = msrs[i].data;
df67696e 1980 break;
79e9ebeb
LJ		 1981 case MSR_IA32_BNDCFGS:
1982 env->msr_bndcfgs = msrs[i].data;
1983 break;
18cd2c17
WL		 1984 case MSR_IA32_XSS:
1985 env->xss = msrs[i].data;
1986 break;
57780495 1987 default:
57780495
MT		 1988 if (msrs[i].index >= MSR_MC0_CTL &&
1989 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
1990 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
57780495 1991 }
d8da8574 1992 break;
f6584ee2
GN		 1993 case MSR_KVM_ASYNC_PF_EN:
1994 env->async_pf_en_msr = msrs[i].data;
1995 break;
bc9a839d
MT		 1996 case MSR_KVM_PV_EOI_EN:
1997 env->pv_eoi_en_msr = msrs[i].data;
1998 break;
917367aa
MT		 1999 case MSR_KVM_STEAL_TIME:
2000 env->steal_time_msr = msrs[i].data;
2001 break;
0d894367
PB		 2002 case MSR_CORE_PERF_FIXED_CTR_CTRL:
2003 env->msr_fixed_ctr_ctrl = msrs[i].data;
2004 break;
2005 case MSR_CORE_PERF_GLOBAL_CTRL:
2006 env->msr_global_ctrl = msrs[i].data;
2007 break;
2008 case MSR_CORE_PERF_GLOBAL_STATUS:
2009 env->msr_global_status = msrs[i].data;
2010 break;
2011 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
2012 env->msr_global_ovf_ctrl = msrs[i].data;
2013 break;
2014 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
2015 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
2016 break;
2017 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
2018 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
2019 break;
2020 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
2021 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
2022 break;
1c90ef26
VR		 2023 case HV_X64_MSR_HYPERCALL:
2024 env->msr_hv_hypercall = msrs[i].data;
2025 break;
2026 case HV_X64_MSR_GUEST_OS_ID:
2027 env->msr_hv_guest_os_id = msrs[i].data;
2028 break;
5ef68987
VR		 2029 case HV_X64_MSR_APIC_ASSIST_PAGE:
2030 env->msr_hv_vapic = msrs[i].data;
2031 break;
48a5f3bc
VR		 2032 case HV_X64_MSR_REFERENCE_TSC:
2033 env->msr_hv_tsc = msrs[i].data;
2034 break;
f2a53c9e
AS		 2035 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2036 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
2037 break;
46eb8f98
AS		 2038 case HV_X64_MSR_VP_RUNTIME:
2039 env->msr_hv_runtime = msrs[i].data;
2040 break;
d1ae67f6
AW		 2041 case MSR_MTRRdefType:
2042 env->mtrr_deftype = msrs[i].data;
2043 break;
2044 case MSR_MTRRfix64K_00000:
2045 env->mtrr_fixed[0] = msrs[i].data;
2046 break;
2047 case MSR_MTRRfix16K_80000:
2048 env->mtrr_fixed[1] = msrs[i].data;
2049 break;
2050 case MSR_MTRRfix16K_A0000:
2051 env->mtrr_fixed[2] = msrs[i].data;
2052 break;
2053 case MSR_MTRRfix4K_C0000:
2054 env->mtrr_fixed[3] = msrs[i].data;
2055 break;
2056 case MSR_MTRRfix4K_C8000:
2057 env->mtrr_fixed[4] = msrs[i].data;
2058 break;
2059 case MSR_MTRRfix4K_D0000:
2060 env->mtrr_fixed[5] = msrs[i].data;
2061 break;
2062 case MSR_MTRRfix4K_D8000:
2063 env->mtrr_fixed[6] = msrs[i].data;
2064 break;
2065 case MSR_MTRRfix4K_E0000:
2066 env->mtrr_fixed[7] = msrs[i].data;
2067 break;
2068 case MSR_MTRRfix4K_E8000:
2069 env->mtrr_fixed[8] = msrs[i].data;
2070 break;
2071 case MSR_MTRRfix4K_F0000:
2072 env->mtrr_fixed[9] = msrs[i].data;
2073 break;
2074 case MSR_MTRRfix4K_F8000:
2075 env->mtrr_fixed[10] = msrs[i].data;
2076 break;
2077 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
2078 if (index & 1) {
2079 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data;
2080 } else {
2081 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
2082 }
2083 break;
05330448
AL		 2084 }
2085 }
2086
2087 return 0;
2088}
2089
1bc22652 2090static int kvm_put_mp_state(X86CPU *cpu)
9bdbe550 2091{
1bc22652 2092 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
9bdbe550 2093
1bc22652 2094 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
9bdbe550
HB		 2095}
2096
23d02d9b 2097static int kvm_get_mp_state(X86CPU *cpu)
9bdbe550 2098{
259186a7 2099 CPUState *cs = CPU(cpu);
23d02d9b 2100 CPUX86State *env = &cpu->env;
9bdbe550
HB		 2101 struct kvm_mp_state mp_state;
2102 int ret;
2103
259186a7 2104 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
9bdbe550
HB		 2105 if (ret < 0) {
2106 return ret;
2107 }
2108 env->mp_state = mp_state.mp_state;
c14750e8 2109 if (kvm_irqchip_in_kernel()) {
259186a7 2110 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
c14750e8 2111 }
9bdbe550
HB		 2112 return 0;
2113}
2114
1bc22652 2115static int kvm_get_apic(X86CPU *cpu)
680c1c6f 2116{
02e51483 2117 DeviceState *apic = cpu->apic_state;
680c1c6f
JK		 2118 struct kvm_lapic_state kapic;
2119 int ret;
2120
3d4b2649 2121 if (apic && kvm_irqchip_in_kernel()) {
1bc22652 2122 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
680c1c6f
JK		 2123 if (ret < 0) {
2124 return ret;
2125 }
2126
2127 kvm_get_apic_state(apic, &kapic);
2128 }
2129 return 0;
2130}
2131
1bc22652 2132static int kvm_put_apic(X86CPU *cpu)
680c1c6f 2133{
02e51483 2134 DeviceState *apic = cpu->apic_state;
680c1c6f
JK		 2135 struct kvm_lapic_state kapic;
2136
3d4b2649 2137 if (apic && kvm_irqchip_in_kernel()) {
680c1c6f
JK		 2138 kvm_put_apic_state(apic, &kapic);
2139
1bc22652 2140 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_LAPIC, &kapic);
680c1c6f
JK		 2141 }
2142 return 0;
2143}
2144
1bc22652 2145static int kvm_put_vcpu_events(X86CPU *cpu, int level)
a0fb002c 2146{
fc12d72e 2147 CPUState *cs = CPU(cpu);
1bc22652 2148 CPUX86State *env = &cpu->env;
076796f8 2149 struct kvm_vcpu_events events = {};
a0fb002c
JK		 2150
2151 if (!kvm_has_vcpu_events()) {
2152 return 0;
2153 }
2154
31827373
JK		 2155 events.exception.injected = (env->exception_injected >= 0);
2156 events.exception.nr = env->exception_injected;
a0fb002c
JK		 2157 events.exception.has_error_code = env->has_error_code;
2158 events.exception.error_code = env->error_code;
7e680753 2159 events.exception.pad = 0;
a0fb002c
JK		 2160
2161 events.interrupt.injected = (env->interrupt_injected >= 0);
2162 events.interrupt.nr = env->interrupt_injected;
2163 events.interrupt.soft = env->soft_interrupt;
2164
2165 events.nmi.injected = env->nmi_injected;
2166 events.nmi.pending = env->nmi_pending;
2167 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
7e680753 2168 events.nmi.pad = 0;
a0fb002c
JK		 2169
2170 events.sipi_vector = env->sipi_vector;
2171
fc12d72e
PB		 2172 if (has_msr_smbase) {
2173 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
2174 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
2175 if (kvm_irqchip_in_kernel()) {
2176 /* As soon as these are moved to the kernel, remove them
2177 * from cs->interrupt_request.
2178 */
2179 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
2180 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
2181 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
2182 } else {
2183 /* Keep these in cs->interrupt_request. */
2184 events.smi.pending = 0;
2185 events.smi.latched_init = 0;
2186 }
2187 events.flags |= KVM_VCPUEVENT_VALID_SMM;
2188 }
2189
ea643051
JK		 2190 events.flags = 0;
2191 if (level >= KVM_PUT_RESET_STATE) {
2192 events.flags |=
2193 KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
2194 }
aee028b9 2195
1bc22652 2196 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
a0fb002c
JK		 2197}
2198
1bc22652 2199static int kvm_get_vcpu_events(X86CPU *cpu)
a0fb002c 2200{
1bc22652 2201 CPUX86State *env = &cpu->env;
a0fb002c
JK		 2202 struct kvm_vcpu_events events;
2203 int ret;
2204
2205 if (!kvm_has_vcpu_events()) {
2206 return 0;
2207 }
2208
fc12d72e 2209 memset(&events, 0, sizeof(events));
1bc22652 2210 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
a0fb002c
JK		 2211 if (ret < 0) {
2212 return ret;
2213 }
31827373 2214 env->exception_injected =
a0fb002c
JK		 2215 events.exception.injected ? events.exception.nr : -1;
2216 env->has_error_code = events.exception.has_error_code;
2217 env->error_code = events.exception.error_code;
2218
2219 env->interrupt_injected =
2220 events.interrupt.injected ? events.interrupt.nr : -1;
2221 env->soft_interrupt = events.interrupt.soft;
2222
2223 env->nmi_injected = events.nmi.injected;
2224 env->nmi_pending = events.nmi.pending;
2225 if (events.nmi.masked) {
2226 env->hflags2 |= HF2_NMI_MASK;
2227 } else {
2228 env->hflags2 &= ~HF2_NMI_MASK;
2229 }
2230
fc12d72e
PB		 2231 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2232 if (events.smi.smm) {
2233 env->hflags |= HF_SMM_MASK;
2234 } else {
2235 env->hflags &= ~HF_SMM_MASK;
2236 }
2237 if (events.smi.pending) {
2238 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2239 } else {
2240 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2241 }
2242 if (events.smi.smm_inside_nmi) {
2243 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2244 } else {
2245 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2246 }
2247 if (events.smi.latched_init) {
2248 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2249 } else {
2250 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2251 }
2252 }
2253
a0fb002c 2254 env->sipi_vector = events.sipi_vector;
a0fb002c
JK		 2255
2256 return 0;
2257}
2258
1bc22652 2259static int kvm_guest_debug_workarounds(X86CPU *cpu)
b0b1d690 2260{
ed2803da 2261 CPUState *cs = CPU(cpu);
1bc22652 2262 CPUX86State *env = &cpu->env;
b0b1d690 2263 int ret = 0;
b0b1d690
JK		 2264 unsigned long reinject_trap = 0;
2265
2266 if (!kvm_has_vcpu_events()) {
2267 if (env->exception_injected == 1) {
2268 reinject_trap = KVM_GUESTDBG_INJECT_DB;
2269 } else if (env->exception_injected == 3) {
2270 reinject_trap = KVM_GUESTDBG_INJECT_BP;
2271 }
2272 env->exception_injected = -1;
2273 }
2274
2275 /*
2276 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2277 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2278 * by updating the debug state once again if single-stepping is on.
2279 * Another reason to call kvm_update_guest_debug here is a pending debug
2280 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2281 * reinject them via SET_GUEST_DEBUG.
2282 */
2283 if (reinject_trap ||
ed2803da 2284 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
38e478ec 2285 ret = kvm_update_guest_debug(cs, reinject_trap);
b0b1d690 2286 }
b0b1d690
JK		 2287 return ret;
2288}
2289
1bc22652 2290static int kvm_put_debugregs(X86CPU *cpu)
ff44f1a3 2291{
1bc22652 2292 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 2293 struct kvm_debugregs dbgregs;
2294 int i;
2295
2296 if (!kvm_has_debugregs()) {
2297 return 0;
2298 }
2299
2300 for (i = 0; i < 4; i++) {
2301 dbgregs.db[i] = env->dr[i];
2302 }
2303 dbgregs.dr6 = env->dr[6];
2304 dbgregs.dr7 = env->dr[7];
2305 dbgregs.flags = 0;
2306
1bc22652 2307 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
ff44f1a3
JK		 2308}
2309
1bc22652 2310static int kvm_get_debugregs(X86CPU *cpu)
ff44f1a3 2311{
1bc22652 2312 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 2313 struct kvm_debugregs dbgregs;
2314 int i, ret;
2315
2316 if (!kvm_has_debugregs()) {
2317 return 0;
2318 }
2319
1bc22652 2320 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
ff44f1a3 2321 if (ret < 0) {
b9bec74b 2322 return ret;
ff44f1a3
JK		 2323 }
2324 for (i = 0; i < 4; i++) {
2325 env->dr[i] = dbgregs.db[i];
2326 }
2327 env->dr[4] = env->dr[6] = dbgregs.dr6;
2328 env->dr[5] = env->dr[7] = dbgregs.dr7;
ff44f1a3
JK		 2329
2330 return 0;
2331}
2332
20d695a9 2333int kvm_arch_put_registers(CPUState *cpu, int level)
05330448 2334{
20d695a9 2335 X86CPU *x86_cpu = X86_CPU(cpu);
05330448
AL		 2336 int ret;
2337
2fa45344 2338 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
dbaa07c4 2339
6bdf863d
JK		 2340 if (level >= KVM_PUT_RESET_STATE && has_msr_feature_control) {
2341 ret = kvm_put_msr_feature_control(x86_cpu);
2342 if (ret < 0) {
2343 return ret;
2344 }
2345 }
2346
1bc22652 2347 ret = kvm_getput_regs(x86_cpu, 1);
b9bec74b 2348 if (ret < 0) {
05330448 2349 return ret;
b9bec74b 2350 }
1bc22652 2351 ret = kvm_put_xsave(x86_cpu);
b9bec74b 2352 if (ret < 0) {
f1665b21 2353 return ret;
b9bec74b 2354 }
1bc22652 2355 ret = kvm_put_xcrs(x86_cpu);
b9bec74b 2356 if (ret < 0) {
05330448 2357 return ret;
b9bec74b 2358 }
1bc22652 2359 ret = kvm_put_sregs(x86_cpu);
b9bec74b 2360 if (ret < 0) {
05330448 2361 return ret;
b9bec74b 2362 }
ab443475 2363 /* must be before kvm_put_msrs */
1bc22652 2364 ret = kvm_inject_mce_oldstyle(x86_cpu);
ab443475
JK		 2365 if (ret < 0) {
2366 return ret;
2367 }
1bc22652 2368 ret = kvm_put_msrs(x86_cpu, level);
b9bec74b 2369 if (ret < 0) {
05330448 2370 return ret;
b9bec74b 2371 }
ea643051 2372 if (level >= KVM_PUT_RESET_STATE) {
1bc22652 2373 ret = kvm_put_mp_state(x86_cpu);
b9bec74b 2374 if (ret < 0) {
ea643051 2375 return ret;
b9bec74b 2376 }
1bc22652 2377 ret = kvm_put_apic(x86_cpu);
680c1c6f
JK		 2378 if (ret < 0) {
2379 return ret;
2380 }
ea643051 2381 }
7477cd38
MT		 2382
2383 ret = kvm_put_tscdeadline_msr(x86_cpu);
2384 if (ret < 0) {
2385 return ret;
2386 }
2387
1bc22652 2388 ret = kvm_put_vcpu_events(x86_cpu, level);
b9bec74b 2389 if (ret < 0) {
a0fb002c 2390 return ret;
b9bec74b 2391 }
1bc22652 2392 ret = kvm_put_debugregs(x86_cpu);
b9bec74b 2393 if (ret < 0) {
b0b1d690 2394 return ret;
b9bec74b 2395 }
b0b1d690 2396 /* must be last */
1bc22652 2397 ret = kvm_guest_debug_workarounds(x86_cpu);
b9bec74b 2398 if (ret < 0) {
ff44f1a3 2399 return ret;
b9bec74b 2400 }
05330448
AL		 2401 return 0;
2402}
2403
20d695a9 2404int kvm_arch_get_registers(CPUState *cs)
05330448 2405{
20d695a9 2406 X86CPU *cpu = X86_CPU(cs);
05330448
AL		 2407 int ret;
2408
20d695a9 2409 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
dbaa07c4 2410
1bc22652 2411 ret = kvm_getput_regs(cpu, 0);
b9bec74b 2412 if (ret < 0) {
05330448 2413 return ret;
b9bec74b 2414 }
1bc22652 2415 ret = kvm_get_xsave(cpu);
b9bec74b 2416 if (ret < 0) {
f1665b21 2417 return ret;
b9bec74b 2418 }
1bc22652 2419 ret = kvm_get_xcrs(cpu);
b9bec74b 2420 if (ret < 0) {
05330448 2421 return ret;
b9bec74b 2422 }
1bc22652 2423 ret = kvm_get_sregs(cpu);
b9bec74b 2424 if (ret < 0) {
05330448 2425 return ret;
b9bec74b 2426 }
1bc22652 2427 ret = kvm_get_msrs(cpu);
b9bec74b 2428 if (ret < 0) {
05330448 2429 return ret;
b9bec74b 2430 }
23d02d9b 2431 ret = kvm_get_mp_state(cpu);
b9bec74b 2432 if (ret < 0) {
5a2e3c2e 2433 return ret;
b9bec74b 2434 }
1bc22652 2435 ret = kvm_get_apic(cpu);
680c1c6f
JK		 2436 if (ret < 0) {
2437 return ret;
2438 }
1bc22652 2439 ret = kvm_get_vcpu_events(cpu);
b9bec74b 2440 if (ret < 0) {
a0fb002c 2441 return ret;
b9bec74b 2442 }
1bc22652 2443 ret = kvm_get_debugregs(cpu);
b9bec74b 2444 if (ret < 0) {
ff44f1a3 2445 return ret;
b9bec74b 2446 }
05330448
AL		 2447 return 0;
2448}
2449
20d695a9 2450void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
05330448 2451{
20d695a9
AF		 2452 X86CPU *x86_cpu = X86_CPU(cpu);
2453 CPUX86State *env = &x86_cpu->env;
ce377af3
JK		 2454 int ret;
2455
276ce815 2456 /* Inject NMI */
fc12d72e
PB		 2457 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
2458 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
2459 qemu_mutex_lock_iothread();
2460 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
2461 qemu_mutex_unlock_iothread();
2462 DPRINTF("injected NMI\n");
2463 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
2464 if (ret < 0) {
2465 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
2466 strerror(-ret));
2467 }
2468 }
2469 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
2470 qemu_mutex_lock_iothread();
2471 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
2472 qemu_mutex_unlock_iothread();
2473 DPRINTF("injected SMI\n");
2474 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
2475 if (ret < 0) {
2476 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
2477 strerror(-ret));
2478 }
ce377af3 2479 }
276ce815
LJ		 2480 }
2481
4b8523ee
JK		 2482 if (!kvm_irqchip_in_kernel()) {
2483 qemu_mutex_lock_iothread();
2484 }
2485
e0723c45
PB		 2486 /* Force the VCPU out of its inner loop to process any INIT requests
2487 * or (for userspace APIC, but it is cheap to combine the checks here)
2488 * pending TPR access reports.
2489 */
2490 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
fc12d72e
PB		 2491 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
2492 !(env->hflags & HF_SMM_MASK)) {
2493 cpu->exit_request = 1;
2494 }
2495 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
2496 cpu->exit_request = 1;
2497 }
e0723c45 2498 }
05330448 2499
e0723c45 2500 if (!kvm_irqchip_in_kernel()) {
db1669bc
JK		 2501 /* Try to inject an interrupt if the guest can accept it */
2502 if (run->ready_for_interrupt_injection &&
259186a7 2503 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
db1669bc
JK		 2504 (env->eflags & IF_MASK)) {
2505 int irq;
2506
259186a7 2507 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
db1669bc
JK		 2508 irq = cpu_get_pic_interrupt(env);
2509 if (irq >= 0) {
2510 struct kvm_interrupt intr;
2511
2512 intr.irq = irq;
db1669bc 2513 DPRINTF("injected interrupt %d\n", irq);
1bc22652 2514 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
ce377af3
JK		 2515 if (ret < 0) {
2516 fprintf(stderr,
2517 "KVM: injection failed, interrupt lost (%s)\n",
2518 strerror(-ret));
2519 }
db1669bc
JK		 2520 }
2521 }
05330448 2522
db1669bc
JK		 2523 /* If we have an interrupt but the guest is not ready to receive an
2524 * interrupt, request an interrupt window exit. This will
2525 * cause a return to userspace as soon as the guest is ready to
2526 * receive interrupts. */
259186a7 2527 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
db1669bc
JK		 2528 run->request_interrupt_window = 1;
2529 } else {
2530 run->request_interrupt_window = 0;
2531 }
2532
2533 DPRINTF("setting tpr\n");
02e51483 2534 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
4b8523ee
JK		 2535
2536 qemu_mutex_unlock_iothread();
db1669bc 2537 }
05330448
AL		 2538}
2539
4c663752 2540MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
05330448 2541{
20d695a9
AF		 2542 X86CPU *x86_cpu = X86_CPU(cpu);
2543 CPUX86State *env = &x86_cpu->env;
2544
fc12d72e
PB		 2545 if (run->flags & KVM_RUN_X86_SMM) {
2546 env->hflags |= HF_SMM_MASK;
2547 } else {
2548 env->hflags &= HF_SMM_MASK;
2549 }
b9bec74b 2550 if (run->if_flag) {
05330448 2551 env->eflags |= IF_MASK;
b9bec74b 2552 } else {
05330448 2553 env->eflags &= ~IF_MASK;
b9bec74b 2554 }
4b8523ee
JK		 2555
2556 /* We need to protect the apic state against concurrent accesses from
2557 * different threads in case the userspace irqchip is used. */
2558 if (!kvm_irqchip_in_kernel()) {
2559 qemu_mutex_lock_iothread();
2560 }
02e51483
CF		 2561 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
2562 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
4b8523ee
JK		 2563 if (!kvm_irqchip_in_kernel()) {
2564 qemu_mutex_unlock_iothread();
2565 }
f794aa4a 2566 return cpu_get_mem_attrs(env);
05330448
AL		 2567}
2568
20d695a9 2569int kvm_arch_process_async_events(CPUState *cs)
0af691d7 2570{
20d695a9
AF		 2571 X86CPU *cpu = X86_CPU(cs);
2572 CPUX86State *env = &cpu->env;
232fc23b 2573
259186a7 2574 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
ab443475
JK		 2575 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
2576 assert(env->mcg_cap);
2577
259186a7 2578 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
ab443475 2579
dd1750d7 2580 kvm_cpu_synchronize_state(cs);
ab443475
JK		 2581
2582 if (env->exception_injected == EXCP08_DBLE) {
2583 /* this means triple fault */
2584 qemu_system_reset_request();
fcd7d003 2585 cs->exit_request = 1;
ab443475
JK		 2586 return 0;
2587 }
2588 env->exception_injected = EXCP12_MCHK;
2589 env->has_error_code = 0;
2590
259186a7 2591 cs->halted = 0;
ab443475
JK		 2592 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
2593 env->mp_state = KVM_MP_STATE_RUNNABLE;
2594 }
2595 }
2596
fc12d72e
PB		 2597 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
2598 !(env->hflags & HF_SMM_MASK)) {
e0723c45
PB		 2599 kvm_cpu_synchronize_state(cs);
2600 do_cpu_init(cpu);
2601 }
2602
db1669bc
JK		 2603 if (kvm_irqchip_in_kernel()) {
2604 return 0;
2605 }
2606
259186a7
AF		 2607 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2608 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
02e51483 2609 apic_poll_irq(cpu->apic_state);
5d62c43a 2610 }
259186a7 2611 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
4601f7b0 2612 (env->eflags & IF_MASK)) ||
259186a7
AF		 2613 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2614 cs->halted = 0;
6792a57b 2615 }
259186a7 2616 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
dd1750d7 2617 kvm_cpu_synchronize_state(cs);
232fc23b 2618 do_cpu_sipi(cpu);
0af691d7 2619 }
259186a7
AF		 2620 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
2621 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
dd1750d7 2622 kvm_cpu_synchronize_state(cs);
02e51483 2623 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
d362e757
JK		 2624 env->tpr_access_type);
2625 }
0af691d7 2626
259186a7 2627 return cs->halted;
0af691d7
MT		 2628}
2629
839b5630 2630static int kvm_handle_halt(X86CPU *cpu)
05330448 2631{
259186a7 2632 CPUState *cs = CPU(cpu);
839b5630
AF		 2633 CPUX86State *env = &cpu->env;
2634
259186a7 2635 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
05330448 2636 (env->eflags & IF_MASK)) &&
259186a7
AF		 2637 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2638 cs->halted = 1;
bb4ea393 2639 return EXCP_HLT;
05330448
AL		 2640 }
2641
bb4ea393 2642 return 0;
05330448
AL		 2643}
2644
f7575c96 2645static int kvm_handle_tpr_access(X86CPU *cpu)
d362e757 2646{
f7575c96
AF		 2647 CPUState *cs = CPU(cpu);
2648 struct kvm_run *run = cs->kvm_run;
d362e757 2649
02e51483 2650 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
d362e757
JK		 2651 run->tpr_access.is_write ? TPR_ACCESS_WRITE
2652 : TPR_ACCESS_READ);
2653 return 1;
2654}
2655
f17ec444 2656int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9 2657{
38972938 2658 static const uint8_t int3 = 0xcc;
64bf3f4e 2659
f17ec444
AF		 2660 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
2661 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
e22a25c9 2662 return -EINVAL;
b9bec74b 2663 }
e22a25c9
AL		 2664 return 0;
2665}
2666
f17ec444 2667int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9
AL		 2668{
2669 uint8_t int3;
2670
f17ec444
AF		 2671 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
2672 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
e22a25c9 2673 return -EINVAL;
b9bec74b 2674 }
e22a25c9
AL		 2675 return 0;
2676}
2677
2678static struct {
2679 target_ulong addr;
2680 int len;
2681 int type;
2682} hw_breakpoint[4];
2683
2684static int nb_hw_breakpoint;
2685
2686static int find_hw_breakpoint(target_ulong addr, int len, int type)
2687{
2688 int n;
2689
b9bec74b 2690 for (n = 0; n < nb_hw_breakpoint; n++) {
e22a25c9 2691 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
b9bec74b 2692 (hw_breakpoint[n].len == len || len == -1)) {
e22a25c9 2693 return n;
b9bec74b
JK		 2694 }
2695 }
e22a25c9
AL		 2696 return -1;
2697}
2698
2699int kvm_arch_insert_hw_breakpoint(target_ulong addr,
2700 target_ulong len, int type)
2701{
2702 switch (type) {
2703 case GDB_BREAKPOINT_HW:
2704 len = 1;
2705 break;
2706 case GDB_WATCHPOINT_WRITE:
2707 case GDB_WATCHPOINT_ACCESS:
2708 switch (len) {
2709 case 1:
2710 break;
2711 case 2:
2712 case 4:
2713 case 8:
b9bec74b 2714 if (addr & (len - 1)) {
e22a25c9 2715 return -EINVAL;
b9bec74b 2716 }
e22a25c9
AL		 2717 break;
2718 default:
2719 return -EINVAL;
2720 }
2721 break;
2722 default:
2723 return -ENOSYS;
2724 }
2725
b9bec74b 2726 if (nb_hw_breakpoint == 4) {
e22a25c9 2727 return -ENOBUFS;
b9bec74b
JK		 2728 }
2729 if (find_hw_breakpoint(addr, len, type) >= 0) {
e22a25c9 2730 return -EEXIST;
b9bec74b 2731 }
e22a25c9
AL		 2732 hw_breakpoint[nb_hw_breakpoint].addr = addr;
2733 hw_breakpoint[nb_hw_breakpoint].len = len;
2734 hw_breakpoint[nb_hw_breakpoint].type = type;
2735 nb_hw_breakpoint++;
2736
2737 return 0;
2738}
2739
2740int kvm_arch_remove_hw_breakpoint(target_ulong addr,
2741 target_ulong len, int type)
2742{
2743 int n;
2744
2745 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
b9bec74b 2746 if (n < 0) {
e22a25c9 2747 return -ENOENT;
b9bec74b 2748 }
e22a25c9
AL		 2749 nb_hw_breakpoint--;
2750 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
2751
2752 return 0;
2753}
2754
2755void kvm_arch_remove_all_hw_breakpoints(void)
2756{
2757 nb_hw_breakpoint = 0;
2758}
2759
2760static CPUWatchpoint hw_watchpoint;
2761
a60f24b5 2762static int kvm_handle_debug(X86CPU *cpu,
48405526 2763 struct kvm_debug_exit_arch *arch_info)
e22a25c9 2764{
ed2803da 2765 CPUState *cs = CPU(cpu);
a60f24b5 2766 CPUX86State *env = &cpu->env;
f2574737 2767 int ret = 0;
e22a25c9
AL		 2768 int n;
2769
2770 if (arch_info->exception == 1) {
2771 if (arch_info->dr6 & (1 << 14)) {
ed2803da 2772 if (cs->singlestep_enabled) {
f2574737 2773 ret = EXCP_DEBUG;
b9bec74b 2774 }
e22a25c9 2775 } else {
b9bec74b
JK		 2776 for (n = 0; n < 4; n++) {
2777 if (arch_info->dr6 & (1 << n)) {
e22a25c9
AL		 2778 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
2779 case 0x0:
f2574737 2780 ret = EXCP_DEBUG;
e22a25c9
AL		 2781 break;
2782 case 0x1:
f2574737 2783 ret = EXCP_DEBUG;
ff4700b0 2784 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 2785 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
2786 hw_watchpoint.flags = BP_MEM_WRITE;
2787 break;
2788 case 0x3:
f2574737 2789 ret = EXCP_DEBUG;
ff4700b0 2790 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 2791 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
2792 hw_watchpoint.flags = BP_MEM_ACCESS;
2793 break;
2794 }
b9bec74b
JK		 2795 }
2796 }
e22a25c9 2797 }
ff4700b0 2798 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
f2574737 2799 ret = EXCP_DEBUG;
b9bec74b 2800 }
f2574737 2801 if (ret == 0) {
ff4700b0 2802 cpu_synchronize_state(cs);
48405526 2803 assert(env->exception_injected == -1);
b0b1d690 2804
f2574737 2805 /* pass to guest */
48405526
BS		 2806 env->exception_injected = arch_info->exception;
2807 env->has_error_code = 0;
b0b1d690 2808 }
e22a25c9 2809
f2574737 2810 return ret;
e22a25c9
AL		 2811}
2812
20d695a9 2813void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
e22a25c9
AL		 2814{
2815 const uint8_t type_code[] = {
2816 [GDB_BREAKPOINT_HW] = 0x0,
2817 [GDB_WATCHPOINT_WRITE] = 0x1,
2818 [GDB_WATCHPOINT_ACCESS] = 0x3
2819 };
2820 const uint8_t len_code[] = {
2821 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
2822 };
2823 int n;
2824
a60f24b5 2825 if (kvm_sw_breakpoints_active(cpu)) {
e22a25c9 2826 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
b9bec74b 2827 }
e22a25c9
AL		 2828 if (nb_hw_breakpoint > 0) {
2829 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
2830 dbg->arch.debugreg[7] = 0x0600;
2831 for (n = 0; n < nb_hw_breakpoint; n++) {
2832 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
2833 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
2834 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
95c077c9 2835 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
e22a25c9
AL		 2836 }
2837 }
2838}
4513d923 2839
2a4dac83
JK		 2840static bool host_supports_vmx(void)
2841{
2842 uint32_t ecx, unused;
2843
2844 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
2845 return ecx & CPUID_EXT_VMX;
2846}
2847
2848#define VMX_INVALID_GUEST_STATE 0x80000021
2849
20d695a9 2850int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2a4dac83 2851{
20d695a9 2852 X86CPU *cpu = X86_CPU(cs);
2a4dac83
JK		 2853 uint64_t code;
2854 int ret;
2855
2856 switch (run->exit_reason) {
2857 case KVM_EXIT_HLT:
2858 DPRINTF("handle_hlt\n");
4b8523ee 2859 qemu_mutex_lock_iothread();
839b5630 2860 ret = kvm_handle_halt(cpu);
4b8523ee 2861 qemu_mutex_unlock_iothread();
2a4dac83
JK		 2862 break;
2863 case KVM_EXIT_SET_TPR:
2864 ret = 0;
2865 break;
d362e757 2866 case KVM_EXIT_TPR_ACCESS:
4b8523ee 2867 qemu_mutex_lock_iothread();
f7575c96 2868 ret = kvm_handle_tpr_access(cpu);
4b8523ee 2869 qemu_mutex_unlock_iothread();
d362e757 2870 break;
2a4dac83
JK		 2871 case KVM_EXIT_FAIL_ENTRY:
2872 code = run->fail_entry.hardware_entry_failure_reason;
2873 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
2874 code);
2875 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
2876 fprintf(stderr,
12619721 2877 "\nIf you're running a guest on an Intel machine without "
2a4dac83
JK		 2878 "unrestricted mode\n"
2879 "support, the failure can be most likely due to the guest "
2880 "entering an invalid\n"
2881 "state for Intel VT. For example, the guest maybe running "
2882 "in big real mode\n"
2883 "which is not supported on less recent Intel processors."
2884 "\n\n");
2885 }
2886 ret = -1;
2887 break;
2888 case KVM_EXIT_EXCEPTION:
2889 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
2890 run->ex.exception, run->ex.error_code);
2891 ret = -1;
2892 break;
f2574737
JK		 2893 case KVM_EXIT_DEBUG:
2894 DPRINTF("kvm_exit_debug\n");
4b8523ee 2895 qemu_mutex_lock_iothread();
a60f24b5 2896 ret = kvm_handle_debug(cpu, &run->debug.arch);
4b8523ee 2897 qemu_mutex_unlock_iothread();
f2574737 2898 break;
2a4dac83
JK		 2899 default:
2900 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
2901 ret = -1;
2902 break;
2903 }
2904
2905 return ret;
2906}
2907
20d695a9 2908bool kvm_arch_stop_on_emulation_error(CPUState *cs)
4513d923 2909{
20d695a9
AF		 2910 X86CPU *cpu = X86_CPU(cs);
2911 CPUX86State *env = &cpu->env;
2912
dd1750d7 2913 kvm_cpu_synchronize_state(cs);
b9bec74b
JK		 2914 return !(env->cr[0] & CR0_PE_MASK) ||
2915 ((env->segs[R_CS].selector & 3) != 3);
4513d923 2916}
84b058d7
JK		 2917
2918void kvm_arch_init_irq_routing(KVMState *s)
2919{
2920 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
2921 /* If kernel can't do irq routing, interrupt source
2922 * override 0->2 cannot be set up as required by HPET.
2923 * So we have to disable it.
2924 */
2925 no_hpet = 1;
2926 }
cc7e0ddf 2927 /* We know at this point that we're using the in-kernel
614e41bc 2928 * irqchip, so we can use irqfds, and on x86 we know
f3e1bed8 2929 * we can use msi via irqfd and GSI routing.
cc7e0ddf 2930 */
614e41bc 2931 kvm_msi_via_irqfd_allowed = true;
f3e1bed8 2932 kvm_gsi_routing_allowed = true;
84b058d7 2933}
b139bd30
JK		 2934
2935/* Classic KVM device assignment interface. Will remain x86 only. */
2936int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
2937 uint32_t flags, uint32_t *dev_id)
2938{
2939 struct kvm_assigned_pci_dev dev_data = {
2940 .segnr = dev_addr->domain,
2941 .busnr = dev_addr->bus,
2942 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
2943 .flags = flags,
2944 };
2945 int ret;
2946
2947 dev_data.assigned_dev_id =
2948 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
2949
2950 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
2951 if (ret < 0) {
2952 return ret;
2953 }
2954
2955 *dev_id = dev_data.assigned_dev_id;
2956
2957 return 0;
2958}
2959
2960int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
2961{
2962 struct kvm_assigned_pci_dev dev_data = {
2963 .assigned_dev_id = dev_id,
2964 };
2965
2966 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
2967}
2968
2969static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
2970 uint32_t irq_type, uint32_t guest_irq)
2971{
2972 struct kvm_assigned_irq assigned_irq = {
2973 .assigned_dev_id = dev_id,
2974 .guest_irq = guest_irq,
2975 .flags = irq_type,
2976 };
2977
2978 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
2979 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
2980 } else {
2981 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
2982 }
2983}
2984
2985int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
2986 uint32_t guest_irq)
2987{
2988 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
2989 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
2990
2991 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
2992}
2993
2994int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
2995{
2996 struct kvm_assigned_pci_dev dev_data = {
2997 .assigned_dev_id = dev_id,
2998 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
2999 };
3000
3001 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
3002}
3003
3004static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
3005 uint32_t type)
3006{
3007 struct kvm_assigned_irq assigned_irq = {
3008 .assigned_dev_id = dev_id,
3009 .flags = type,
3010 };
3011
3012 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
3013}
3014
3015int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
3016{
3017 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
3018 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
3019}
3020
3021int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
3022{
3023 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
3024 KVM_DEV_IRQ_GUEST_MSI, virq);
3025}
3026
3027int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
3028{
3029 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
3030 KVM_DEV_IRQ_HOST_MSI);
3031}
3032
3033bool kvm_device_msix_supported(KVMState *s)
3034{
3035 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
3036 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
3037 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
3038}
3039
3040int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
3041 uint32_t nr_vectors)
3042{
3043 struct kvm_assigned_msix_nr msix_nr = {
3044 .assigned_dev_id = dev_id,
3045 .entry_nr = nr_vectors,
3046 };
3047
3048 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
3049}
3050
3051int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
3052 int virq)
3053{
3054 struct kvm_assigned_msix_entry msix_entry = {
3055 .assigned_dev_id = dev_id,
3056 .gsi = virq,
3057 .entry = vector,
3058 };
3059
3060 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
3061}
3062
3063int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
3064{
3065 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
3066 KVM_DEV_IRQ_GUEST_MSIX, 0);
3067}
3068
3069int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
3070{
3071 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
3072 KVM_DEV_IRQ_HOST_MSIX);
3073}
9e03a040
FB		 3074
3075int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
dc9f06ca 3076 uint64_t address, uint32_t data, PCIDevice *dev)
9e03a040
FB		 3077{
3078 return 0;
3079}
1850b6b7
EA		 3080
3081int kvm_arch_msi_data_to_gsi(uint32_t data)
3082{
3083 abort();
3084}
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