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i386/kvm: add support for Direct Mode for Hyper-V synthetic timers
[qemu.git] / target / i386 / kvm.c
CommitLineData
05330448
AL		 1/*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <[email protected]>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
b6a0aa05 15#include "qemu/osdep.h"
da34e65c 16#include "qapi/error.h"
05330448 17#include <sys/ioctl.h>
25d2e361 18#include <sys/utsname.h>
05330448
AL		 19
20#include <linux/kvm.h>
1814eab6 21#include "standard-headers/asm-x86/kvm_para.h"
05330448 22
33c11879 23#include "cpu.h"
9c17d615 24#include "sysemu/sysemu.h"
b3946626 25#include "sysemu/hw_accel.h"
6410848b 26#include "sysemu/kvm_int.h"
1d31f66b 27#include "kvm_i386.h"
50efe82c 28#include "hyperv.h"
5e953812 29#include "hyperv-proto.h"
50efe82c 30
022c62cb 31#include "exec/gdbstub.h"
1de7afc9
PB		 32#include "qemu/host-utils.h"
33#include "qemu/config-file.h"
1c4a55db 34#include "qemu/error-report.h"
0d09e41a
PB		 35#include "hw/i386/pc.h"
36#include "hw/i386/apic.h"
e0723c45
PB		 37#include "hw/i386/apic_internal.h"
38#include "hw/i386/apic-msidef.h"
8b5ed7df 39#include "hw/i386/intel_iommu.h"
e1d4fb2d 40#include "hw/i386/x86-iommu.h"
50efe82c 41
a2cb15b0 42#include "hw/pci/pci.h"
15eafc2e 43#include "hw/pci/msi.h"
fd563564 44#include "hw/pci/msix.h"
795c40b8 45#include "migration/blocker.h"
4c663752 46#include "exec/memattrs.h"
8b5ed7df 47#include "trace.h"
05330448
AL		 48
49//#define DEBUG_KVM
50
51#ifdef DEBUG_KVM
8c0d577e 52#define DPRINTF(fmt, ...) \
05330448
AL		 53 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
54#else
8c0d577e 55#define DPRINTF(fmt, ...) \
05330448
AL		 56 do { } while (0)
57#endif
58
1a03675d
GC		 59#define MSR_KVM_WALL_CLOCK 0x11
60#define MSR_KVM_SYSTEM_TIME 0x12
61
d1138251
EH		 62/* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
63 * 255 kvm_msr_entry structs */
64#define MSR_BUF_SIZE 4096
d71b62a1 65
94a8d39a
JK		 66const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
67 KVM_CAP_INFO(SET_TSS_ADDR),
68 KVM_CAP_INFO(EXT_CPUID),
69 KVM_CAP_INFO(MP_STATE),
70 KVM_CAP_LAST_INFO
71};
25d2e361 72
c3a3a7d3
JK		 73static bool has_msr_star;
74static bool has_msr_hsave_pa;
c9b8f6b6 75static bool has_msr_tsc_aux;
f28558d3 76static bool has_msr_tsc_adjust;
aa82ba54 77static bool has_msr_tsc_deadline;
df67696e 78static bool has_msr_feature_control;
21e87c46 79static bool has_msr_misc_enable;
fc12d72e 80static bool has_msr_smbase;
79e9ebeb 81static bool has_msr_bndcfgs;
25d2e361 82static int lm_capable_kernel;
7bc3d711 83static bool has_msr_hv_hypercall;
f2a53c9e 84static bool has_msr_hv_crash;
744b8a94 85static bool has_msr_hv_reset;
8c145d7c 86static bool has_msr_hv_vpindex;
e9688fab 87static bool hv_vpindex_settable;
46eb8f98 88static bool has_msr_hv_runtime;
866eea9a 89static bool has_msr_hv_synic;
ff99aa64 90static bool has_msr_hv_stimer;
d72bc7f6 91static bool has_msr_hv_frequencies;
ba6a4fd9 92static bool has_msr_hv_reenlightenment;
18cd2c17 93static bool has_msr_xss;
a33a2cfe 94static bool has_msr_spec_ctrl;
cfeea0c0 95static bool has_msr_virt_ssbd;
e13713db 96static bool has_msr_smi_count;
aec5e9c3 97static bool has_msr_arch_capabs;
b827df58 98
0b368a10
JD		 99static uint32_t has_architectural_pmu_version;
100static uint32_t num_architectural_pmu_gp_counters;
101static uint32_t num_architectural_pmu_fixed_counters;
0d894367 102
28143b40
TH		 103static int has_xsave;
104static int has_xcrs;
105static int has_pit_state2;
106
87f8b626
AR		 107static bool has_msr_mcg_ext_ctl;
108
494e95e9 109static struct kvm_cpuid2 *cpuid_cache;
f57bceb6 110static struct kvm_msr_list *kvm_feature_msrs;
494e95e9 111
28143b40
TH		 112int kvm_has_pit_state2(void)
113{
114 return has_pit_state2;
115}
116
355023f2
PB		 117bool kvm_has_smm(void)
118{
119 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
120}
121
6053a86f
MT		 122bool kvm_has_adjust_clock_stable(void)
123{
124 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
125
126 return (ret == KVM_CLOCK_TSC_STABLE);
127}
128
1d31f66b
PM		 129bool kvm_allows_irq0_override(void)
130{
131 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
132}
133
fb506e70
RK		 134static bool kvm_x2apic_api_set_flags(uint64_t flags)
135{
136 KVMState *s = KVM_STATE(current_machine->accelerator);
137
138 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
139}
140
e391c009 141#define MEMORIZE(fn, _result) \
2a138ec3 142 ({ \
2a138ec3
RK		 143 static bool _memorized; \
144 \
145 if (_memorized) { \
146 return _result; \
147 } \
148 _memorized = true; \
149 _result = fn; \
150 })
151
e391c009
IM		 152static bool has_x2apic_api;
153
154bool kvm_has_x2apic_api(void)
155{
156 return has_x2apic_api;
157}
158
fb506e70
RK		 159bool kvm_enable_x2apic(void)
160{
2a138ec3
RK		 161 return MEMORIZE(
162 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
e391c009
IM		 163 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
164 has_x2apic_api);
fb506e70
RK		 165}
166
e9688fab
RK		 167bool kvm_hv_vpindex_settable(void)
168{
169 return hv_vpindex_settable;
170}
171
0fd7e098
LL		 172static int kvm_get_tsc(CPUState *cs)
173{
174 X86CPU *cpu = X86_CPU(cs);
175 CPUX86State *env = &cpu->env;
176 struct {
177 struct kvm_msrs info;
178 struct kvm_msr_entry entries[1];
179 } msr_data;
180 int ret;
181
182 if (env->tsc_valid) {
183 return 0;
184 }
185
186 msr_data.info.nmsrs = 1;
187 msr_data.entries[0].index = MSR_IA32_TSC;
188 env->tsc_valid = !runstate_is_running();
189
190 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
191 if (ret < 0) {
192 return ret;
193 }
194
48e1a45c 195 assert(ret == 1);
0fd7e098
LL		 196 env->tsc = msr_data.entries[0].data;
197 return 0;
198}
199
14e6fe12 200static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
0fd7e098 201{
0fd7e098
LL		 202 kvm_get_tsc(cpu);
203}
204
205void kvm_synchronize_all_tsc(void)
206{
207 CPUState *cpu;
208
209 if (kvm_enabled()) {
210 CPU_FOREACH(cpu) {
14e6fe12 211 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
0fd7e098
LL		 212 }
213 }
214}
215
b827df58
AK		 216static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
217{
218 struct kvm_cpuid2 *cpuid;
219 int r, size;
220
221 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
e42a92ae 222 cpuid = g_malloc0(size);
b827df58
AK		 223 cpuid->nent = max;
224 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
76ae317f
MM		 225 if (r == 0 && cpuid->nent >= max) {
226 r = -E2BIG;
227 }
b827df58
AK		 228 if (r < 0) {
229 if (r == -E2BIG) {
7267c094 230 g_free(cpuid);
b827df58
AK		 231 return NULL;
232 } else {
233 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
234 strerror(-r));
235 exit(1);
236 }
237 }
238 return cpuid;
239}
240
dd87f8a6
EH		 241/* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
242 * for all entries.
243 */
244static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
245{
246 struct kvm_cpuid2 *cpuid;
247 int max = 1;
494e95e9
CP		 248
249 if (cpuid_cache != NULL) {
250 return cpuid_cache;
251 }
dd87f8a6
EH		 252 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
253 max *= 2;
254 }
494e95e9 255 cpuid_cache = cpuid;
dd87f8a6
EH		 256 return cpuid;
257}
258
a443bc34 259static const struct kvm_para_features {
0c31b744
GC		 260 int cap;
261 int feature;
262} para_features[] = {
263 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
264 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
265 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
0c31b744 266 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
0c31b744
GC		 267};
268
ba9bc59e 269static int get_para_features(KVMState *s)
0c31b744
GC		 270{
271 int i, features = 0;
272
8e03c100 273 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
ba9bc59e 274 if (kvm_check_extension(s, para_features[i].cap)) {
0c31b744
GC		 275 features |= (1 << para_features[i].feature);
276 }
277 }
278
279 return features;
280}
0c31b744 281
40e80ee4
EH		 282static bool host_tsx_blacklisted(void)
283{
284 int family, model, stepping;\
285 char vendor[CPUID_VENDOR_SZ + 1];
286
287 host_vendor_fms(vendor, &family, &model, &stepping);
288
289 /* Check if we are running on a Haswell host known to have broken TSX */
290 return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
291 (family == 6) &&
292 ((model == 63 && stepping < 4) ||
293 model == 60 || model == 69 || model == 70);
294}
0c31b744 295
829ae2f9
EH		 296/* Returns the value for a specific register on the cpuid entry
297 */
298static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
299{
300 uint32_t ret = 0;
301 switch (reg) {
302 case R_EAX:
303 ret = entry->eax;
304 break;
305 case R_EBX:
306 ret = entry->ebx;
307 break;
308 case R_ECX:
309 ret = entry->ecx;
310 break;
311 case R_EDX:
312 ret = entry->edx;
313 break;
314 }
315 return ret;
316}
317
4fb73f1d
EH		 318/* Find matching entry for function/index on kvm_cpuid2 struct
319 */
320static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
321 uint32_t function,
322 uint32_t index)
323{
324 int i;
325 for (i = 0; i < cpuid->nent; ++i) {
326 if (cpuid->entries[i].function == function &&
327 cpuid->entries[i].index == index) {
328 return &cpuid->entries[i];
329 }
330 }
331 /* not found: */
332 return NULL;
333}
334
ba9bc59e 335uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
c958a8bd 336 uint32_t index, int reg)
b827df58
AK		 337{
338 struct kvm_cpuid2 *cpuid;
b827df58
AK		 339 uint32_t ret = 0;
340 uint32_t cpuid_1_edx;
8c723b79 341 bool found = false;
b827df58 342
dd87f8a6 343 cpuid = get_supported_cpuid(s);
b827df58 344
4fb73f1d
EH		 345 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
346 if (entry) {
347 found = true;
348 ret = cpuid_entry_get_reg(entry, reg);
b827df58
AK		 349 }
350
7b46e5ce
EH		 351 /* Fixups for the data returned by KVM, below */
352
c2acb022
EH		 353 if (function == 1 && reg == R_EDX) {
354 /* KVM before 2.6.30 misreports the following features */
355 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
84bd945c
EH		 356 } else if (function == 1 && reg == R_ECX) {
357 /* We can set the hypervisor flag, even if KVM does not return it on
358 * GET_SUPPORTED_CPUID
359 */
360 ret |= CPUID_EXT_HYPERVISOR;
ac67ee26
EH		 361 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
362 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
363 * and the irqchip is in the kernel.
364 */
365 if (kvm_irqchip_in_kernel() &&
366 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
367 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
368 }
41e5e76d
EH		 369
370 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
371 * without the in-kernel irqchip
372 */
373 if (!kvm_irqchip_in_kernel()) {
374 ret &= ~CPUID_EXT_X2APIC;
b827df58 375 }
2266d443
MT		 376
377 if (enable_cpu_pm) {
378 int disable_exits = kvm_check_extension(s,
379 KVM_CAP_X86_DISABLE_EXITS);
380
381 if (disable_exits & KVM_X86_DISABLE_EXITS_MWAIT) {
382 ret |= CPUID_EXT_MONITOR;
383 }
384 }
28b8e4d0
JK		 385 } else if (function == 6 && reg == R_EAX) {
386 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
40e80ee4
EH		 387 } else if (function == 7 && index == 0 && reg == R_EBX) {
388 if (host_tsx_blacklisted()) {
389 ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
390 }
485b1d25
EH		 391 } else if (function == 7 && index == 0 && reg == R_EDX) {
392 /*
393 * Linux v4.17-v4.20 incorrectly return ARCH_CAPABILITIES on SVM hosts.
394 * We can detect the bug by checking if MSR_IA32_ARCH_CAPABILITIES is
395 * returned by KVM_GET_MSR_INDEX_LIST.
396 */
397 if (!has_msr_arch_capabs) {
398 ret &= ~CPUID_7_0_EDX_ARCH_CAPABILITIES;
399 }
f98bbd83
BM		 400 } else if (function == 0x80000001 && reg == R_ECX) {
401 /*
402 * It's safe to enable TOPOEXT even if it's not returned by
403 * GET_SUPPORTED_CPUID. Unconditionally enabling TOPOEXT here allows
404 * us to keep CPU models including TOPOEXT runnable on older kernels.
405 */
406 ret |= CPUID_EXT3_TOPOEXT;
c2acb022
EH		 407 } else if (function == 0x80000001 && reg == R_EDX) {
408 /* On Intel, kvm returns cpuid according to the Intel spec,
409 * so add missing bits according to the AMD spec:
410 */
411 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
412 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
64877477
EH		 413 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
414 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
415 * be enabled without the in-kernel irqchip
416 */
417 if (!kvm_irqchip_in_kernel()) {
418 ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
419 }
be777326 420 } else if (function == KVM_CPUID_FEATURES && reg == R_EDX) {
2af1acad 421 ret |= 1U << KVM_HINTS_REALTIME;
be777326 422 found = 1;
b827df58
AK		 423 }
424
0c31b744 425 /* fallback for older kernels */
8c723b79 426 if ((function == KVM_CPUID_FEATURES) && !found) {
ba9bc59e 427 ret = get_para_features(s);
b9bec74b 428 }
0c31b744
GC		 429
430 return ret;
bb0300dc 431}
bb0300dc 432
f57bceb6
RH		 433uint32_t kvm_arch_get_supported_msr_feature(KVMState *s, uint32_t index)
434{
435 struct {
436 struct kvm_msrs info;
437 struct kvm_msr_entry entries[1];
438 } msr_data;
439 uint32_t ret;
440
441 if (kvm_feature_msrs == NULL) { /* Host doesn't support feature MSRs */
442 return 0;
443 }
444
445 /* Check if requested MSR is supported feature MSR */
446 int i;
447 for (i = 0; i < kvm_feature_msrs->nmsrs; i++)
448 if (kvm_feature_msrs->indices[i] == index) {
449 break;
450 }
451 if (i == kvm_feature_msrs->nmsrs) {
452 return 0; /* if the feature MSR is not supported, simply return 0 */
453 }
454
455 msr_data.info.nmsrs = 1;
456 msr_data.entries[0].index = index;
457
458 ret = kvm_ioctl(s, KVM_GET_MSRS, &msr_data);
459 if (ret != 1) {
460 error_report("KVM get MSR (index=0x%x) feature failed, %s",
461 index, strerror(-ret));
462 exit(1);
463 }
464
465 return msr_data.entries[0].data;
466}
467
468
3c85e74f
HY		 469typedef struct HWPoisonPage {
470 ram_addr_t ram_addr;
471 QLIST_ENTRY(HWPoisonPage) list;
472} HWPoisonPage;
473
474static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
475 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
476
477static void kvm_unpoison_all(void *param)
478{
479 HWPoisonPage *page, *next_page;
480
481 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
482 QLIST_REMOVE(page, list);
483 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
7267c094 484 g_free(page);
3c85e74f
HY		 485 }
486}
487
3c85e74f
HY		 488static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
489{
490 HWPoisonPage *page;
491
492 QLIST_FOREACH(page, &hwpoison_page_list, list) {
493 if (page->ram_addr == ram_addr) {
494 return;
495 }
496 }
ab3ad07f 497 page = g_new(HWPoisonPage, 1);
3c85e74f
HY		 498 page->ram_addr = ram_addr;
499 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
500}
501
e7701825
MT		 502static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
503 int *max_banks)
504{
505 int r;
506
14a09518 507 r = kvm_check_extension(s, KVM_CAP_MCE);
e7701825
MT		 508 if (r > 0) {
509 *max_banks = r;
510 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
511 }
512 return -ENOSYS;
513}
514
bee615d4 515static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
e7701825 516{
87f8b626 517 CPUState *cs = CPU(cpu);
bee615d4 518 CPUX86State *env = &cpu->env;
c34d440a
JK		 519 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
520 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
521 uint64_t mcg_status = MCG_STATUS_MCIP;
87f8b626 522 int flags = 0;
e7701825 523
c34d440a
JK		 524 if (code == BUS_MCEERR_AR) {
525 status |= MCI_STATUS_AR | 0x134;
526 mcg_status |= MCG_STATUS_EIPV;
527 } else {
528 status |= 0xc0;
529 mcg_status |= MCG_STATUS_RIPV;
419fb20a 530 }
87f8b626
AR		 531
532 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
533 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
534 * guest kernel back into env->mcg_ext_ctl.
535 */
536 cpu_synchronize_state(cs);
537 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
538 mcg_status |= MCG_STATUS_LMCE;
539 flags = 0;
540 }
541
8c5cf3b6 542 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
87f8b626 543 (MCM_ADDR_PHYS << 6) | 0xc, flags);
419fb20a 544}
419fb20a
JK		 545
546static void hardware_memory_error(void)
547{
548 fprintf(stderr, "Hardware memory error!\n");
549 exit(1);
550}
551
2ae41db2 552void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
419fb20a 553{
20d695a9
AF		 554 X86CPU *cpu = X86_CPU(c);
555 CPUX86State *env = &cpu->env;
419fb20a 556 ram_addr_t ram_addr;
a8170e5e 557 hwaddr paddr;
419fb20a 558
4d39892c
PB		 559 /* If we get an action required MCE, it has been injected by KVM
560 * while the VM was running. An action optional MCE instead should
561 * be coming from the main thread, which qemu_init_sigbus identifies
562 * as the "early kill" thread.
563 */
a16fc07e 564 assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
20e0ff59 565
20e0ff59 566 if ((env->mcg_cap & MCG_SER_P) && addr) {
07bdaa41 567 ram_addr = qemu_ram_addr_from_host(addr);
20e0ff59
PB		 568 if (ram_addr != RAM_ADDR_INVALID &&
569 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
570 kvm_hwpoison_page_add(ram_addr);
571 kvm_mce_inject(cpu, paddr, code);
2ae41db2 572 return;
419fb20a 573 }
20e0ff59
PB		 574
575 fprintf(stderr, "Hardware memory error for memory used by "
576 "QEMU itself instead of guest system!\n");
419fb20a 577 }
20e0ff59
PB		 578
579 if (code == BUS_MCEERR_AR) {
580 hardware_memory_error();
581 }
582
583 /* Hope we are lucky for AO MCE */
419fb20a
JK		 584}
585
1bc22652 586static int kvm_inject_mce_oldstyle(X86CPU *cpu)
ab443475 587{
1bc22652
AF		 588 CPUX86State *env = &cpu->env;
589
ab443475
JK		 590 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
591 unsigned int bank, bank_num = env->mcg_cap & 0xff;
592 struct kvm_x86_mce mce;
593
594 env->exception_injected = -1;
595
596 /*
597 * There must be at least one bank in use if an MCE is pending.
598 * Find it and use its values for the event injection.
599 */
600 for (bank = 0; bank < bank_num; bank++) {
601 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
602 break;
603 }
604 }
605 assert(bank < bank_num);
606
607 mce.bank = bank;
608 mce.status = env->mce_banks[bank * 4 + 1];
609 mce.mcg_status = env->mcg_status;
610 mce.addr = env->mce_banks[bank * 4 + 2];
611 mce.misc = env->mce_banks[bank * 4 + 3];
612
1bc22652 613 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
ab443475 614 }
ab443475
JK		 615 return 0;
616}
617
1dfb4dd9 618static void cpu_update_state(void *opaque, int running, RunState state)
b8cc45d6 619{
317ac620 620 CPUX86State *env = opaque;
b8cc45d6
GC		 621
622 if (running) {
623 env->tsc_valid = false;
624 }
625}
626
83b17af5 627unsigned long kvm_arch_vcpu_id(CPUState *cs)
b164e48e 628{
83b17af5 629 X86CPU *cpu = X86_CPU(cs);
7e72a45c 630 return cpu->apic_id;
b164e48e
EH		 631}
632
92067bf4
IM		 633#ifndef KVM_CPUID_SIGNATURE_NEXT
634#define KVM_CPUID_SIGNATURE_NEXT 0x40000100
635#endif
636
92067bf4
IM		 637static bool hyperv_enabled(X86CPU *cpu)
638{
7bc3d711
PB		 639 CPUState *cs = CPU(cpu);
640 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
2d384d7c 641 ((cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY) ||
e48ddcc6 642 cpu->hyperv_features || cpu->hyperv_passthrough);
92067bf4
IM		 643}
644
5031283d
HZ		 645static int kvm_arch_set_tsc_khz(CPUState *cs)
646{
647 X86CPU *cpu = X86_CPU(cs);
648 CPUX86State *env = &cpu->env;
649 int r;
650
651 if (!env->tsc_khz) {
652 return 0;
653 }
654
655 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
656 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
657 -ENOTSUP;
658 if (r < 0) {
659 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
660 * TSC frequency doesn't match the one we want.
661 */
662 int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
663 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
664 -ENOTSUP;
665 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
3dc6f869
AF		 666 warn_report("TSC frequency mismatch between "
667 "VM (%" PRId64 " kHz) and host (%d kHz), "
668 "and TSC scaling unavailable",
669 env->tsc_khz, cur_freq);
5031283d
HZ		 670 return r;
671 }
672 }
673
674 return 0;
675}
676
4bb95b82
LP		 677static bool tsc_is_stable_and_known(CPUX86State *env)
678{
679 if (!env->tsc_khz) {
680 return false;
681 }
682 return (env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
683 || env->user_tsc_khz;
684}
685
6760bd20
VK		 686static struct {
687 const char *desc;
688 struct {
689 uint32_t fw;
690 uint32_t bits;
691 } flags[2];
c6861930 692 uint64_t dependencies;
6760bd20
VK		 693} kvm_hyperv_properties[] = {
694 [HYPERV_FEAT_RELAXED] = {
695 .desc = "relaxed timing (hv-relaxed)",
696 .flags = {
697 {.fw = FEAT_HYPERV_EAX,
698 .bits = HV_HYPERCALL_AVAILABLE},
699 {.fw = FEAT_HV_RECOMM_EAX,
700 .bits = HV_RELAXED_TIMING_RECOMMENDED}
701 }
702 },
703 [HYPERV_FEAT_VAPIC] = {
704 .desc = "virtual APIC (hv-vapic)",
705 .flags = {
706 {.fw = FEAT_HYPERV_EAX,
707 .bits = HV_HYPERCALL_AVAILABLE | HV_APIC_ACCESS_AVAILABLE},
708 {.fw = FEAT_HV_RECOMM_EAX,
709 .bits = HV_APIC_ACCESS_RECOMMENDED}
710 }
711 },
712 [HYPERV_FEAT_TIME] = {
713 .desc = "clocksources (hv-time)",
714 .flags = {
715 {.fw = FEAT_HYPERV_EAX,
716 .bits = HV_HYPERCALL_AVAILABLE | HV_TIME_REF_COUNT_AVAILABLE |
717 HV_REFERENCE_TSC_AVAILABLE}
718 }
719 },
720 [HYPERV_FEAT_CRASH] = {
721 .desc = "crash MSRs (hv-crash)",
722 .flags = {
723 {.fw = FEAT_HYPERV_EDX,
724 .bits = HV_GUEST_CRASH_MSR_AVAILABLE}
725 }
726 },
727 [HYPERV_FEAT_RESET] = {
728 .desc = "reset MSR (hv-reset)",
729 .flags = {
730 {.fw = FEAT_HYPERV_EAX,
731 .bits = HV_RESET_AVAILABLE}
732 }
733 },
734 [HYPERV_FEAT_VPINDEX] = {
735 .desc = "VP_INDEX MSR (hv-vpindex)",
736 .flags = {
737 {.fw = FEAT_HYPERV_EAX,
738 .bits = HV_VP_INDEX_AVAILABLE}
739 }
740 },
741 [HYPERV_FEAT_RUNTIME] = {
742 .desc = "VP_RUNTIME MSR (hv-runtime)",
743 .flags = {
744 {.fw = FEAT_HYPERV_EAX,
745 .bits = HV_VP_RUNTIME_AVAILABLE}
746 }
747 },
748 [HYPERV_FEAT_SYNIC] = {
749 .desc = "synthetic interrupt controller (hv-synic)",
750 .flags = {
751 {.fw = FEAT_HYPERV_EAX,
752 .bits = HV_SYNIC_AVAILABLE}
753 }
754 },
755 [HYPERV_FEAT_STIMER] = {
756 .desc = "synthetic timers (hv-stimer)",
757 .flags = {
758 {.fw = FEAT_HYPERV_EAX,
759 .bits = HV_SYNTIMERS_AVAILABLE}
c6861930
VK		 760 },
761 .dependencies = BIT(HYPERV_FEAT_SYNIC) | BIT(HYPERV_FEAT_TIME)
6760bd20
VK		 762 },
763 [HYPERV_FEAT_FREQUENCIES] = {
764 .desc = "frequency MSRs (hv-frequencies)",
765 .flags = {
766 {.fw = FEAT_HYPERV_EAX,
767 .bits = HV_ACCESS_FREQUENCY_MSRS},
768 {.fw = FEAT_HYPERV_EDX,
769 .bits = HV_FREQUENCY_MSRS_AVAILABLE}
770 }
771 },
772 [HYPERV_FEAT_REENLIGHTENMENT] = {
773 .desc = "reenlightenment MSRs (hv-reenlightenment)",
774 .flags = {
775 {.fw = FEAT_HYPERV_EAX,
776 .bits = HV_ACCESS_REENLIGHTENMENTS_CONTROL}
777 }
778 },
779 [HYPERV_FEAT_TLBFLUSH] = {
780 .desc = "paravirtualized TLB flush (hv-tlbflush)",
781 .flags = {
782 {.fw = FEAT_HV_RECOMM_EAX,
783 .bits = HV_REMOTE_TLB_FLUSH_RECOMMENDED |
784 HV_EX_PROCESSOR_MASKS_RECOMMENDED}
bd59fbdf
VK		 785 },
786 .dependencies = BIT(HYPERV_FEAT_VPINDEX)
6760bd20
VK		 787 },
788 [HYPERV_FEAT_EVMCS] = {
789 .desc = "enlightened VMCS (hv-evmcs)",
790 .flags = {
791 {.fw = FEAT_HV_RECOMM_EAX,
792 .bits = HV_ENLIGHTENED_VMCS_RECOMMENDED}
8caba36d
VK		 793 },
794 .dependencies = BIT(HYPERV_FEAT_VAPIC)
6760bd20
VK		 795 },
796 [HYPERV_FEAT_IPI] = {
797 .desc = "paravirtualized IPI (hv-ipi)",
798 .flags = {
799 {.fw = FEAT_HV_RECOMM_EAX,
800 .bits = HV_CLUSTER_IPI_RECOMMENDED |
801 HV_EX_PROCESSOR_MASKS_RECOMMENDED}
bd59fbdf
VK		 802 },
803 .dependencies = BIT(HYPERV_FEAT_VPINDEX)
6760bd20 804 },
128531d9
VK		 805 [HYPERV_FEAT_STIMER_DIRECT] = {
806 .desc = "direct mode synthetic timers (hv-stimer-direct)",
807 .flags = {
808 {.fw = FEAT_HYPERV_EDX,
809 .bits = HV_STIMER_DIRECT_MODE_AVAILABLE}
810 },
811 .dependencies = BIT(HYPERV_FEAT_STIMER)
812 },
6760bd20
VK		 813};
814
815static struct kvm_cpuid2 *try_get_hv_cpuid(CPUState *cs, int max)
816{
817 struct kvm_cpuid2 *cpuid;
818 int r, size;
819
820 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
821 cpuid = g_malloc0(size);
822 cpuid->nent = max;
823
824 r = kvm_vcpu_ioctl(cs, KVM_GET_SUPPORTED_HV_CPUID, cpuid);
825 if (r == 0 && cpuid->nent >= max) {
826 r = -E2BIG;
827 }
828 if (r < 0) {
829 if (r == -E2BIG) {
830 g_free(cpuid);
831 return NULL;
832 } else {
833 fprintf(stderr, "KVM_GET_SUPPORTED_HV_CPUID failed: %s\n",
834 strerror(-r));
835 exit(1);
836 }
837 }
838 return cpuid;
839}
840
841/*
842 * Run KVM_GET_SUPPORTED_HV_CPUID ioctl(), allocating a buffer large enough
843 * for all entries.
844 */
845static struct kvm_cpuid2 *get_supported_hv_cpuid(CPUState *cs)
846{
847 struct kvm_cpuid2 *cpuid;
848 int max = 7; /* 0x40000000..0x40000005, 0x4000000A */
849
850 /*
851 * When the buffer is too small, KVM_GET_SUPPORTED_HV_CPUID fails with
852 * -E2BIG, however, it doesn't report back the right size. Keep increasing
853 * it and re-trying until we succeed.
854 */
855 while ((cpuid = try_get_hv_cpuid(cs, max)) == NULL) {
856 max++;
857 }
858 return cpuid;
859}
860
861/*
862 * When KVM_GET_SUPPORTED_HV_CPUID is not supported we fill CPUID feature
863 * leaves from KVM_CAP_HYPERV* and present MSRs data.
864 */
865static struct kvm_cpuid2 *get_supported_hv_cpuid_legacy(CPUState *cs)
c35bd19a
EY		 866{
867 X86CPU *cpu = X86_CPU(cs);
6760bd20
VK		 868 struct kvm_cpuid2 *cpuid;
869 struct kvm_cpuid_entry2 *entry_feat, *entry_recomm;
870
871 /* HV_CPUID_FEATURES, HV_CPUID_ENLIGHTMENT_INFO */
872 cpuid = g_malloc0(sizeof(*cpuid) + 2 * sizeof(*cpuid->entries));
873 cpuid->nent = 2;
874
875 /* HV_CPUID_VENDOR_AND_MAX_FUNCTIONS */
876 entry_feat = &cpuid->entries[0];
877 entry_feat->function = HV_CPUID_FEATURES;
878
879 entry_recomm = &cpuid->entries[1];
880 entry_recomm->function = HV_CPUID_ENLIGHTMENT_INFO;
881 entry_recomm->ebx = cpu->hyperv_spinlock_attempts;
882
883 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0) {
884 entry_feat->eax |= HV_HYPERCALL_AVAILABLE;
885 entry_feat->eax |= HV_APIC_ACCESS_AVAILABLE;
886 entry_feat->edx |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
887 entry_recomm->eax |= HV_RELAXED_TIMING_RECOMMENDED;
888 entry_recomm->eax |= HV_APIC_ACCESS_RECOMMENDED;
889 }
c35bd19a 890
6760bd20
VK		 891 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) {
892 entry_feat->eax |= HV_TIME_REF_COUNT_AVAILABLE;
893 entry_feat->eax |= HV_REFERENCE_TSC_AVAILABLE;
c35bd19a 894 }
6760bd20
VK		 895
896 if (has_msr_hv_frequencies) {
897 entry_feat->eax |= HV_ACCESS_FREQUENCY_MSRS;
898 entry_feat->edx |= HV_FREQUENCY_MSRS_AVAILABLE;
c35bd19a 899 }
6760bd20
VK		 900
901 if (has_msr_hv_crash) {
902 entry_feat->edx |= HV_GUEST_CRASH_MSR_AVAILABLE;
9445597b 903 }
6760bd20
VK		 904
905 if (has_msr_hv_reenlightenment) {
906 entry_feat->eax |= HV_ACCESS_REENLIGHTENMENTS_CONTROL;
c35bd19a 907 }
6760bd20
VK		 908
909 if (has_msr_hv_reset) {
910 entry_feat->eax |= HV_RESET_AVAILABLE;
c35bd19a 911 }
6760bd20
VK		 912
913 if (has_msr_hv_vpindex) {
914 entry_feat->eax |= HV_VP_INDEX_AVAILABLE;
ba6a4fd9 915 }
6760bd20
VK		 916
917 if (has_msr_hv_runtime) {
918 entry_feat->eax |= HV_VP_RUNTIME_AVAILABLE;
c35bd19a 919 }
6760bd20
VK		 920
921 if (has_msr_hv_synic) {
922 unsigned int cap = cpu->hyperv_synic_kvm_only ?
923 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
924
925 if (kvm_check_extension(cs->kvm_state, cap) > 0) {
926 entry_feat->eax |= HV_SYNIC_AVAILABLE;
1221f150 927 }
c35bd19a 928 }
6760bd20
VK		 929
930 if (has_msr_hv_stimer) {
931 entry_feat->eax |= HV_SYNTIMERS_AVAILABLE;
c35bd19a 932 }
9b4cf107 933
6760bd20
VK		 934 if (kvm_check_extension(cs->kvm_state,
935 KVM_CAP_HYPERV_TLBFLUSH) > 0) {
936 entry_recomm->eax |= HV_REMOTE_TLB_FLUSH_RECOMMENDED;
937 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
938 }
c35bd19a 939
6760bd20
VK		 940 if (kvm_check_extension(cs->kvm_state,
941 KVM_CAP_HYPERV_ENLIGHTENED_VMCS) > 0) {
942 entry_recomm->eax |= HV_ENLIGHTENED_VMCS_RECOMMENDED;
c35bd19a 943 }
6760bd20
VK		 944
945 if (kvm_check_extension(cs->kvm_state,
946 KVM_CAP_HYPERV_SEND_IPI) > 0) {
947 entry_recomm->eax |= HV_CLUSTER_IPI_RECOMMENDED;
948 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
c35bd19a 949 }
6760bd20
VK		 950
951 return cpuid;
952}
953
954static int hv_cpuid_get_fw(struct kvm_cpuid2 *cpuid, int fw, uint32_t *r)
955{
956 struct kvm_cpuid_entry2 *entry;
957 uint32_t func;
958 int reg;
959
960 switch (fw) {
961 case FEAT_HYPERV_EAX:
962 reg = R_EAX;
963 func = HV_CPUID_FEATURES;
964 break;
965 case FEAT_HYPERV_EDX:
966 reg = R_EDX;
967 func = HV_CPUID_FEATURES;
968 break;
969 case FEAT_HV_RECOMM_EAX:
970 reg = R_EAX;
971 func = HV_CPUID_ENLIGHTMENT_INFO;
972 break;
973 default:
974 return -EINVAL;
a2b107db 975 }
6760bd20
VK		 976
977 entry = cpuid_find_entry(cpuid, func, 0);
978 if (!entry) {
979 return -ENOENT;
a2b107db 980 }
6760bd20
VK		 981
982 switch (reg) {
983 case R_EAX:
984 *r = entry->eax;
985 break;
986 case R_EDX:
987 *r = entry->edx;
988 break;
989 default:
990 return -EINVAL;
a2b107db 991 }
6760bd20
VK		 992
993 return 0;
994}
995
996static int hv_cpuid_check_and_set(CPUState *cs, struct kvm_cpuid2 *cpuid,
997 int feature)
998{
999 X86CPU *cpu = X86_CPU(cs);
1000 CPUX86State *env = &cpu->env;
e48ddcc6 1001 uint32_t r, fw, bits;
c6861930
VK		 1002 uint64_t deps;
1003 int i, dep_feat = 0;
6760bd20 1004
e48ddcc6 1005 if (!hyperv_feat_enabled(cpu, feature) && !cpu->hyperv_passthrough) {
6760bd20
VK		 1006 return 0;
1007 }
1008
c6861930
VK		 1009 deps = kvm_hyperv_properties[feature].dependencies;
1010 while ((dep_feat = find_next_bit(&deps, 64, dep_feat)) < 64) {
1011 if (!(hyperv_feat_enabled(cpu, dep_feat))) {
1012 fprintf(stderr,
1013 "Hyper-V %s requires Hyper-V %s\n",
1014 kvm_hyperv_properties[feature].desc,
1015 kvm_hyperv_properties[dep_feat].desc);
1016 return 1;
1017 }
1018 dep_feat++;
1019 }
1020
6760bd20
VK		 1021 for (i = 0; i < ARRAY_SIZE(kvm_hyperv_properties[feature].flags); i++) {
1022 fw = kvm_hyperv_properties[feature].flags[i].fw;
1023 bits = kvm_hyperv_properties[feature].flags[i].bits;
1024
1025 if (!fw) {
1026 continue;
a2b107db 1027 }
6760bd20
VK		 1028
1029 if (hv_cpuid_get_fw(cpuid, fw, &r) || (r & bits) != bits) {
e48ddcc6
VK		 1030 if (hyperv_feat_enabled(cpu, feature)) {
1031 fprintf(stderr,
1032 "Hyper-V %s is not supported by kernel\n",
1033 kvm_hyperv_properties[feature].desc);
1034 return 1;
1035 } else {
1036 return 0;
1037 }
6760bd20
VK		 1038 }
1039
1040 env->features[fw] |= bits;
a2b107db 1041 }
6760bd20 1042
e48ddcc6
VK		 1043 if (cpu->hyperv_passthrough) {
1044 cpu->hyperv_features |= BIT(feature);
1045 }
1046
6760bd20
VK		 1047 return 0;
1048}
1049
2344d22e
VK		 1050/*
1051 * Fill in Hyper-V CPUIDs. Returns the number of entries filled in cpuid_ent in
1052 * case of success, errno < 0 in case of failure and 0 when no Hyper-V
1053 * extentions are enabled.
1054 */
1055static int hyperv_handle_properties(CPUState *cs,
1056 struct kvm_cpuid_entry2 *cpuid_ent)
6760bd20
VK		 1057{
1058 X86CPU *cpu = X86_CPU(cs);
1059 CPUX86State *env = &cpu->env;
1060 struct kvm_cpuid2 *cpuid;
2344d22e
VK		 1061 struct kvm_cpuid_entry2 *c;
1062 uint32_t signature[3];
1063 uint32_t cpuid_i = 0;
e48ddcc6 1064 int r;
6760bd20 1065
2344d22e
VK		 1066 if (!hyperv_enabled(cpu))
1067 return 0;
1068
e48ddcc6
VK		 1069 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) ||
1070 cpu->hyperv_passthrough) {
a2b107db
VK		 1071 uint16_t evmcs_version;
1072
e48ddcc6
VK		 1073 r = kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_ENLIGHTENED_VMCS, 0,
1074 (uintptr_t)&evmcs_version);
1075
1076 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) && r) {
6760bd20
VK		 1077 fprintf(stderr, "Hyper-V %s is not supported by kernel\n",
1078 kvm_hyperv_properties[HYPERV_FEAT_EVMCS].desc);
a2b107db
VK		 1079 return -ENOSYS;
1080 }
e48ddcc6
VK		 1081
1082 if (!r) {
1083 env->features[FEAT_HV_RECOMM_EAX] |=
1084 HV_ENLIGHTENED_VMCS_RECOMMENDED;
1085 env->features[FEAT_HV_NESTED_EAX] = evmcs_version;
1086 }
a2b107db
VK		 1087 }
1088
6760bd20
VK		 1089 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_CPUID) > 0) {
1090 cpuid = get_supported_hv_cpuid(cs);
1091 } else {
1092 cpuid = get_supported_hv_cpuid_legacy(cs);
1093 }
1094
e48ddcc6
VK		 1095 if (cpu->hyperv_passthrough) {
1096 memcpy(cpuid_ent, &cpuid->entries[0],
1097 cpuid->nent * sizeof(cpuid->entries[0]));
1098
1099 c = cpuid_find_entry(cpuid, HV_CPUID_FEATURES, 0);
1100 if (c) {
1101 env->features[FEAT_HYPERV_EAX] = c->eax;
1102 env->features[FEAT_HYPERV_EBX] = c->ebx;
1103 env->features[FEAT_HYPERV_EDX] = c->eax;
1104 }
1105 c = cpuid_find_entry(cpuid, HV_CPUID_ENLIGHTMENT_INFO, 0);
1106 if (c) {
1107 env->features[FEAT_HV_RECOMM_EAX] = c->eax;
1108
1109 /* hv-spinlocks may have been overriden */
1110 if (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY) {
1111 c->ebx = cpu->hyperv_spinlock_attempts;
1112 }
1113 }
1114 c = cpuid_find_entry(cpuid, HV_CPUID_NESTED_FEATURES, 0);
1115 if (c) {
1116 env->features[FEAT_HV_NESTED_EAX] = c->eax;
1117 }
1118 }
1119
6760bd20 1120 /* Features */
e48ddcc6 1121 r = hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_RELAXED);
6760bd20
VK		 1122 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_VAPIC);
1123 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_TIME);
1124 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_CRASH);
1125 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_RESET);
1126 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_VPINDEX);
1127 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_RUNTIME);
1128 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_SYNIC);
1129 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_STIMER);
1130 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_FREQUENCIES);
1131 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_REENLIGHTENMENT);
1132 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_TLBFLUSH);
1133 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_EVMCS);
1134 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_IPI);
128531d9 1135 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_STIMER_DIRECT);
6760bd20 1136
c6861930 1137 /* Additional dependencies not covered by kvm_hyperv_properties[] */
6760bd20
VK		 1138 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC) &&
1139 !cpu->hyperv_synic_kvm_only &&
1140 !hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)) {
c6861930 1141 fprintf(stderr, "Hyper-V %s requires Hyper-V %s\n",
6760bd20
VK		 1142 kvm_hyperv_properties[HYPERV_FEAT_SYNIC].desc,
1143 kvm_hyperv_properties[HYPERV_FEAT_VPINDEX].desc);
1144 r |= 1;
1145 }
1146
1147 /* Not exposed by KVM but needed to make CPU hotplug in Windows work */
1148 env->features[FEAT_HYPERV_EDX] |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
1149
2344d22e
VK		 1150 if (r) {
1151 r = -ENOSYS;
1152 goto free;
1153 }
1154
e48ddcc6
VK		 1155 if (cpu->hyperv_passthrough) {
1156 /* We already copied all feature words from KVM as is */
1157 r = cpuid->nent;
1158 goto free;
1159 }
1160
2344d22e
VK		 1161 c = &cpuid_ent[cpuid_i++];
1162 c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
1163 if (!cpu->hyperv_vendor_id) {
1164 memcpy(signature, "Microsoft Hv", 12);
1165 } else {
1166 size_t len = strlen(cpu->hyperv_vendor_id);
1167
1168 if (len > 12) {
1169 error_report("hv-vendor-id truncated to 12 characters");
1170 len = 12;
1171 }
1172 memset(signature, 0, 12);
1173 memcpy(signature, cpu->hyperv_vendor_id, len);
1174 }
1175 c->eax = hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) ?
1176 HV_CPUID_NESTED_FEATURES : HV_CPUID_IMPLEMENT_LIMITS;
1177 c->ebx = signature[0];
1178 c->ecx = signature[1];
1179 c->edx = signature[2];
1180
1181 c = &cpuid_ent[cpuid_i++];
1182 c->function = HV_CPUID_INTERFACE;
1183 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
1184 c->eax = signature[0];
1185 c->ebx = 0;
1186 c->ecx = 0;
1187 c->edx = 0;
1188
1189 c = &cpuid_ent[cpuid_i++];
1190 c->function = HV_CPUID_VERSION;
1191 c->eax = 0x00001bbc;
1192 c->ebx = 0x00060001;
1193
1194 c = &cpuid_ent[cpuid_i++];
1195 c->function = HV_CPUID_FEATURES;
1196 c->eax = env->features[FEAT_HYPERV_EAX];
1197 c->ebx = env->features[FEAT_HYPERV_EBX];
1198 c->edx = env->features[FEAT_HYPERV_EDX];
1199
1200 c = &cpuid_ent[cpuid_i++];
1201 c->function = HV_CPUID_ENLIGHTMENT_INFO;
1202 c->eax = env->features[FEAT_HV_RECOMM_EAX];
1203 c->ebx = cpu->hyperv_spinlock_attempts;
1204
1205 c = &cpuid_ent[cpuid_i++];
1206 c->function = HV_CPUID_IMPLEMENT_LIMITS;
1207 c->eax = cpu->hv_max_vps;
1208 c->ebx = 0x40;
1209
1210 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) {
1211 __u32 function;
1212
1213 /* Create zeroed 0x40000006..0x40000009 leaves */
1214 for (function = HV_CPUID_IMPLEMENT_LIMITS + 1;
1215 function < HV_CPUID_NESTED_FEATURES; function++) {
1216 c = &cpuid_ent[cpuid_i++];
1217 c->function = function;
1218 }
1219
1220 c = &cpuid_ent[cpuid_i++];
1221 c->function = HV_CPUID_NESTED_FEATURES;
1222 c->eax = env->features[FEAT_HV_NESTED_EAX];
1223 }
1224 r = cpuid_i;
1225
1226free:
6760bd20
VK		 1227 g_free(cpuid);
1228
2344d22e 1229 return r;
c35bd19a
EY		 1230}
1231
e48ddcc6
VK		 1232static Error *hv_passthrough_mig_blocker;
1233
e9688fab
RK		 1234static int hyperv_init_vcpu(X86CPU *cpu)
1235{
729ce7e1 1236 CPUState *cs = CPU(cpu);
e48ddcc6 1237 Error *local_err = NULL;
729ce7e1
RK		 1238 int ret;
1239
e48ddcc6
VK		 1240 if (cpu->hyperv_passthrough && hv_passthrough_mig_blocker == NULL) {
1241 error_setg(&hv_passthrough_mig_blocker,
1242 "'hv-passthrough' CPU flag prevents migration, use explicit"
1243 " set of hv-* flags instead");
1244 ret = migrate_add_blocker(hv_passthrough_mig_blocker, &local_err);
1245 if (local_err) {
1246 error_report_err(local_err);
1247 error_free(hv_passthrough_mig_blocker);
1248 return ret;
1249 }
1250 }
1251
2d384d7c 1252 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && !hv_vpindex_settable) {
e9688fab
RK		 1253 /*
1254 * the kernel doesn't support setting vp_index; assert that its value
1255 * is in sync
1256 */
e9688fab
RK		 1257 struct {
1258 struct kvm_msrs info;
1259 struct kvm_msr_entry entries[1];
1260 } msr_data = {
1261 .info.nmsrs = 1,
1262 .entries[0].index = HV_X64_MSR_VP_INDEX,
1263 };
1264
729ce7e1 1265 ret = kvm_vcpu_ioctl(cs, KVM_GET_MSRS, &msr_data);
e9688fab
RK		 1266 if (ret < 0) {
1267 return ret;
1268 }
1269 assert(ret == 1);
1270
701189e3 1271 if (msr_data.entries[0].data != hyperv_vp_index(CPU(cpu))) {
e9688fab
RK		 1272 error_report("kernel's vp_index != QEMU's vp_index");
1273 return -ENXIO;
1274 }
1275 }
1276
2d384d7c 1277 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
9b4cf107
RK		 1278 uint32_t synic_cap = cpu->hyperv_synic_kvm_only ?
1279 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
1280 ret = kvm_vcpu_enable_cap(cs, synic_cap, 0);
729ce7e1
RK		 1281 if (ret < 0) {
1282 error_report("failed to turn on HyperV SynIC in KVM: %s",
1283 strerror(-ret));
1284 return ret;
1285 }
606c34bf 1286
9b4cf107
RK		 1287 if (!cpu->hyperv_synic_kvm_only) {
1288 ret = hyperv_x86_synic_add(cpu);
1289 if (ret < 0) {
1290 error_report("failed to create HyperV SynIC: %s",
1291 strerror(-ret));
1292 return ret;
1293 }
606c34bf 1294 }
729ce7e1
RK		 1295 }
1296
e9688fab
RK		 1297 return 0;
1298}
1299
68bfd0ad 1300static Error *invtsc_mig_blocker;
d98f2607 1301static Error *vmx_mig_blocker;
68bfd0ad 1302
f8bb0565 1303#define KVM_MAX_CPUID_ENTRIES 100
0893d460 1304
20d695a9 1305int kvm_arch_init_vcpu(CPUState *cs)
05330448
AL		 1306{
1307 struct {
486bd5a2 1308 struct kvm_cpuid2 cpuid;
f8bb0565 1309 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
9115bb12
PM		 1310 } cpuid_data;
1311 /*
1312 * The kernel defines these structs with padding fields so there
1313 * should be no extra padding in our cpuid_data struct.
1314 */
1315 QEMU_BUILD_BUG_ON(sizeof(cpuid_data) !=
1316 sizeof(struct kvm_cpuid2) +
1317 sizeof(struct kvm_cpuid_entry2) * KVM_MAX_CPUID_ENTRIES);
1318
20d695a9
AF		 1319 X86CPU *cpu = X86_CPU(cs);
1320 CPUX86State *env = &cpu->env;
486bd5a2 1321 uint32_t limit, i, j, cpuid_i;
a33609ca 1322 uint32_t unused;
bb0300dc 1323 struct kvm_cpuid_entry2 *c;
bb0300dc 1324 uint32_t signature[3];
234cc647 1325 int kvm_base = KVM_CPUID_SIGNATURE;
e7429073 1326 int r;
fe44dc91 1327 Error *local_err = NULL;
05330448 1328
ef4cbe14
SW		 1329 memset(&cpuid_data, 0, sizeof(cpuid_data));
1330
05330448
AL		 1331 cpuid_i = 0;
1332
ddb98b5a
LP		 1333 r = kvm_arch_set_tsc_khz(cs);
1334 if (r < 0) {
1335 goto fail;
1336 }
1337
1338 /* vcpu's TSC frequency is either specified by user, or following
1339 * the value used by KVM if the former is not present. In the
1340 * latter case, we query it from KVM and record in env->tsc_khz,
1341 * so that vcpu's TSC frequency can be migrated later via this field.
1342 */
1343 if (!env->tsc_khz) {
1344 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
1345 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
1346 -ENOTSUP;
1347 if (r > 0) {
1348 env->tsc_khz = r;
1349 }
1350 }
1351
bb0300dc 1352 /* Paravirtualization CPUIDs */
2344d22e
VK		 1353 r = hyperv_handle_properties(cs, cpuid_data.entries);
1354 if (r < 0) {
1355 return r;
1356 } else if (r > 0) {
1357 cpuid_i = r;
234cc647 1358 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
7bc3d711 1359 has_msr_hv_hypercall = true;
eab70139
VR		 1360 }
1361
f522d2ac
AW		 1362 if (cpu->expose_kvm) {
1363 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
1364 c = &cpuid_data.entries[cpuid_i++];
1365 c->function = KVM_CPUID_SIGNATURE | kvm_base;
79b6f2f6 1366 c->eax = KVM_CPUID_FEATURES | kvm_base;
f522d2ac
AW		 1367 c->ebx = signature[0];
1368 c->ecx = signature[1];
1369 c->edx = signature[2];
234cc647 1370
f522d2ac
AW		 1371 c = &cpuid_data.entries[cpuid_i++];
1372 c->function = KVM_CPUID_FEATURES | kvm_base;
1373 c->eax = env->features[FEAT_KVM];
be777326 1374 c->edx = env->features[FEAT_KVM_HINTS];
f522d2ac 1375 }
917367aa 1376
a33609ca 1377 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
05330448
AL		 1378
1379 for (i = 0; i <= limit; i++) {
f8bb0565
IM		 1380 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1381 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
1382 abort();
1383 }
bb0300dc 1384 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 1385
1386 switch (i) {
a36b1029
AL		 1387 case 2: {
1388 /* Keep reading function 2 till all the input is received */
1389 int times;
1390
a36b1029 1391 c->function = i;
a33609ca
AL		 1392 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
1393 KVM_CPUID_FLAG_STATE_READ_NEXT;
1394 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1395 times = c->eax & 0xff;
a36b1029
AL		 1396
1397 for (j = 1; j < times; ++j) {
f8bb0565
IM		 1398 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1399 fprintf(stderr, "cpuid_data is full, no space for "
1400 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
1401 abort();
1402 }
a33609ca 1403 c = &cpuid_data.entries[cpuid_i++];
a36b1029 1404 c->function = i;
a33609ca
AL		 1405 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
1406 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
a36b1029
AL		 1407 }
1408 break;
1409 }
486bd5a2
AL		 1410 case 4:
1411 case 0xb:
1412 case 0xd:
1413 for (j = 0; ; j++) {
31e8c696
AP		 1414 if (i == 0xd && j == 64) {
1415 break;
1416 }
486bd5a2
AL		 1417 c->function = i;
1418 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1419 c->index = j;
a33609ca 1420 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2 1421
b9bec74b 1422 if (i == 4 && c->eax == 0) {
486bd5a2 1423 break;
b9bec74b
JK		 1424 }
1425 if (i == 0xb && !(c->ecx & 0xff00)) {
486bd5a2 1426 break;
b9bec74b
JK		 1427 }
1428 if (i == 0xd && c->eax == 0) {
31e8c696 1429 continue;
b9bec74b 1430 }
f8bb0565
IM		 1431 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1432 fprintf(stderr, "cpuid_data is full, no space for "
1433 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1434 abort();
1435 }
a33609ca 1436 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 1437 }
1438 break;
e37a5c7f
CP		 1439 case 0x14: {
1440 uint32_t times;
1441
1442 c->function = i;
1443 c->index = 0;
1444 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1445 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1446 times = c->eax;
1447
1448 for (j = 1; j <= times; ++j) {
1449 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1450 fprintf(stderr, "cpuid_data is full, no space for "
1451 "cpuid(eax:0x14,ecx:0x%x)\n", j);
1452 abort();
1453 }
1454 c = &cpuid_data.entries[cpuid_i++];
1455 c->function = i;
1456 c->index = j;
1457 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1458 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1459 }
1460 break;
1461 }
486bd5a2 1462 default:
486bd5a2 1463 c->function = i;
a33609ca
AL		 1464 c->flags = 0;
1465 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2
AL		 1466 break;
1467 }
05330448 1468 }
0d894367
PB		 1469
1470 if (limit >= 0x0a) {
0b368a10 1471 uint32_t eax, edx;
0d894367 1472
0b368a10
JD		 1473 cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx);
1474
1475 has_architectural_pmu_version = eax & 0xff;
1476 if (has_architectural_pmu_version > 0) {
1477 num_architectural_pmu_gp_counters = (eax & 0xff00) >> 8;
0d894367
PB		 1478
1479 /* Shouldn't be more than 32, since that's the number of bits
1480 * available in EBX to tell us _which_ counters are available.
1481 * Play it safe.
1482 */
0b368a10
JD		 1483 if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) {
1484 num_architectural_pmu_gp_counters = MAX_GP_COUNTERS;
1485 }
1486
1487 if (has_architectural_pmu_version > 1) {
1488 num_architectural_pmu_fixed_counters = edx & 0x1f;
1489
1490 if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNTERS) {
1491 num_architectural_pmu_fixed_counters = MAX_FIXED_COUNTERS;
1492 }
0d894367
PB		 1493 }
1494 }
1495 }
1496
a33609ca 1497 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
05330448
AL		 1498
1499 for (i = 0x80000000; i <= limit; i++) {
f8bb0565
IM		 1500 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1501 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
1502 abort();
1503 }
bb0300dc 1504 c = &cpuid_data.entries[cpuid_i++];
05330448 1505
8f4202fb
BM		 1506 switch (i) {
1507 case 0x8000001d:
1508 /* Query for all AMD cache information leaves */
1509 for (j = 0; ; j++) {
1510 c->function = i;
1511 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1512 c->index = j;
1513 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1514
1515 if (c->eax == 0) {
1516 break;
1517 }
1518 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1519 fprintf(stderr, "cpuid_data is full, no space for "
1520 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1521 abort();
1522 }
1523 c = &cpuid_data.entries[cpuid_i++];
1524 }
1525 break;
1526 default:
1527 c->function = i;
1528 c->flags = 0;
1529 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1530 break;
1531 }
05330448
AL		 1532 }
1533
b3baa152
BW		 1534 /* Call Centaur's CPUID instructions they are supported. */
1535 if (env->cpuid_xlevel2 > 0) {
b3baa152
BW		 1536 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
1537
1538 for (i = 0xC0000000; i <= limit; i++) {
f8bb0565
IM		 1539 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1540 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
1541 abort();
1542 }
b3baa152
BW		 1543 c = &cpuid_data.entries[cpuid_i++];
1544
1545 c->function = i;
1546 c->flags = 0;
1547 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1548 }
1549 }
1550
05330448
AL		 1551 cpuid_data.cpuid.nent = cpuid_i;
1552
e7701825 1553 if (((env->cpuid_version >> 8)&0xF) >= 6
0514ef2f 1554 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
fc7a504c 1555 (CPUID_MCE | CPUID_MCA)
a60f24b5 1556 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
5120901a 1557 uint64_t mcg_cap, unsupported_caps;
e7701825 1558 int banks;
32a42024 1559 int ret;
e7701825 1560
a60f24b5 1561 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
75d49497
JK		 1562 if (ret < 0) {
1563 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
1564 return ret;
e7701825 1565 }
75d49497 1566
2590f15b 1567 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
49b69cbf 1568 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
2590f15b 1569 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
49b69cbf 1570 return -ENOTSUP;
75d49497 1571 }
49b69cbf 1572
5120901a
EH		 1573 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
1574 if (unsupported_caps) {
87f8b626
AR		 1575 if (unsupported_caps & MCG_LMCE_P) {
1576 error_report("kvm: LMCE not supported");
1577 return -ENOTSUP;
1578 }
3dc6f869
AF		 1579 warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64,
1580 unsupported_caps);
5120901a
EH		 1581 }
1582
2590f15b
EH		 1583 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
1584 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
75d49497
JK		 1585 if (ret < 0) {
1586 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
1587 return ret;
1588 }
e7701825 1589 }
e7701825 1590
b8cc45d6
GC		 1591 qemu_add_vm_change_state_handler(cpu_update_state, env);
1592
df67696e
LJ		 1593 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
1594 if (c) {
1595 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
1596 !!(c->ecx & CPUID_EXT_SMX);
1597 }
1598
d98f2607
PB		 1599 if ((env->features[FEAT_1_ECX] & CPUID_EXT_VMX) && !vmx_mig_blocker) {
1600 error_setg(&vmx_mig_blocker,
1601 "Nested VMX virtualization does not support live migration yet");
1602 r = migrate_add_blocker(vmx_mig_blocker, &local_err);
1603 if (local_err) {
1604 error_report_err(local_err);
1605 error_free(vmx_mig_blocker);
1606 return r;
1607 }
1608 }
1609
87f8b626
AR		 1610 if (env->mcg_cap & MCG_LMCE_P) {
1611 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
1612 }
1613
d99569d9
EH		 1614 if (!env->user_tsc_khz) {
1615 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
1616 invtsc_mig_blocker == NULL) {
d99569d9
EH		 1617 error_setg(&invtsc_mig_blocker,
1618 "State blocked by non-migratable CPU device"
1619 " (invtsc flag)");
fe44dc91
AA		 1620 r = migrate_add_blocker(invtsc_mig_blocker, &local_err);
1621 if (local_err) {
1622 error_report_err(local_err);
1623 error_free(invtsc_mig_blocker);
0c2ed83f 1624 return r;
fe44dc91 1625 }
d99569d9 1626 }
68bfd0ad
MT		 1627 }
1628
9954a158
PDJ		 1629 if (cpu->vmware_cpuid_freq
1630 /* Guests depend on 0x40000000 to detect this feature, so only expose
1631 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
1632 && cpu->expose_kvm
1633 && kvm_base == KVM_CPUID_SIGNATURE
1634 /* TSC clock must be stable and known for this feature. */
4bb95b82 1635 && tsc_is_stable_and_known(env)) {
9954a158
PDJ		 1636
1637 c = &cpuid_data.entries[cpuid_i++];
1638 c->function = KVM_CPUID_SIGNATURE | 0x10;
1639 c->eax = env->tsc_khz;
1640 /* LAPIC resolution of 1ns (freq: 1GHz) is hardcoded in KVM's
1641 * APIC_BUS_CYCLE_NS */
1642 c->ebx = 1000000;
1643 c->ecx = c->edx = 0;
1644
1645 c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
1646 c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
1647 }
1648
1649 cpuid_data.cpuid.nent = cpuid_i;
1650
1651 cpuid_data.cpuid.padding = 0;
1652 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
1653 if (r) {
1654 goto fail;
1655 }
1656
28143b40 1657 if (has_xsave) {
5b8063c4 1658 env->xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
fabacc0f 1659 }
d71b62a1 1660 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
fabacc0f 1661
273c515c
PB		 1662 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
1663 has_msr_tsc_aux = false;
1664 }
d1ae67f6 1665
e9688fab
RK		 1666 r = hyperv_init_vcpu(cpu);
1667 if (r) {
1668 goto fail;
1669 }
1670
e7429073 1671 return 0;
fe44dc91
AA		 1672
1673 fail:
1674 migrate_del_blocker(invtsc_mig_blocker);
1675 return r;
05330448
AL		 1676}
1677
50a2c6e5 1678void kvm_arch_reset_vcpu(X86CPU *cpu)
caa5af0f 1679{
20d695a9 1680 CPUX86State *env = &cpu->env;
dd673288 1681
1a5e9d2f 1682 env->xcr0 = 1;
ddced198 1683 if (kvm_irqchip_in_kernel()) {
dd673288 1684 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
ddced198
MT		 1685 KVM_MP_STATE_UNINITIALIZED;
1686 } else {
1687 env->mp_state = KVM_MP_STATE_RUNNABLE;
1688 }
689141dd 1689
2d384d7c 1690 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
689141dd
RK		 1691 int i;
1692 for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) {
1693 env->msr_hv_synic_sint[i] = HV_SINT_MASKED;
1694 }
606c34bf
RK		 1695
1696 hyperv_x86_synic_reset(cpu);
689141dd 1697 }
caa5af0f
JK		 1698}
1699
e0723c45
PB		 1700void kvm_arch_do_init_vcpu(X86CPU *cpu)
1701{
1702 CPUX86State *env = &cpu->env;
1703
1704 /* APs get directly into wait-for-SIPI state. */
1705 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
1706 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
1707 }
1708}
1709
f57bceb6
RH		 1710static int kvm_get_supported_feature_msrs(KVMState *s)
1711{
1712 int ret = 0;
1713
1714 if (kvm_feature_msrs != NULL) {
1715 return 0;
1716 }
1717
1718 if (!kvm_check_extension(s, KVM_CAP_GET_MSR_FEATURES)) {
1719 return 0;
1720 }
1721
1722 struct kvm_msr_list msr_list;
1723
1724 msr_list.nmsrs = 0;
1725 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, &msr_list);
1726 if (ret < 0 && ret != -E2BIG) {
1727 error_report("Fetch KVM feature MSR list failed: %s",
1728 strerror(-ret));
1729 return ret;
1730 }
1731
1732 assert(msr_list.nmsrs > 0);
1733 kvm_feature_msrs = (struct kvm_msr_list *) \
1734 g_malloc0(sizeof(msr_list) +
1735 msr_list.nmsrs * sizeof(msr_list.indices[0]));
1736
1737 kvm_feature_msrs->nmsrs = msr_list.nmsrs;
1738 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, kvm_feature_msrs);
1739
1740 if (ret < 0) {
1741 error_report("Fetch KVM feature MSR list failed: %s",
1742 strerror(-ret));
1743 g_free(kvm_feature_msrs);
1744 kvm_feature_msrs = NULL;
1745 return ret;
1746 }
1747
1748 return 0;
1749}
1750
c3a3a7d3 1751static int kvm_get_supported_msrs(KVMState *s)
05330448 1752{
75b10c43 1753 static int kvm_supported_msrs;
c3a3a7d3 1754 int ret = 0;
05330448
AL		 1755
1756 /* first time */
75b10c43 1757 if (kvm_supported_msrs == 0) {
05330448
AL		 1758 struct kvm_msr_list msr_list, *kvm_msr_list;
1759
75b10c43 1760 kvm_supported_msrs = -1;
05330448
AL		 1761
1762 /* Obtain MSR list from KVM. These are the MSRs that we must
1763 * save/restore */
4c9f7372 1764 msr_list.nmsrs = 0;
c3a3a7d3 1765 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
6fb6d245 1766 if (ret < 0 && ret != -E2BIG) {
c3a3a7d3 1767 return ret;
6fb6d245 1768 }
d9db889f
JK		 1769 /* Old kernel modules had a bug and could write beyond the provided
1770 memory. Allocate at least a safe amount of 1K. */
7267c094 1771 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
d9db889f
JK		 1772 msr_list.nmsrs *
1773 sizeof(msr_list.indices[0])));
05330448 1774
55308450 1775 kvm_msr_list->nmsrs = msr_list.nmsrs;
c3a3a7d3 1776 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
05330448
AL		 1777 if (ret >= 0) {
1778 int i;
1779
1780 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
1d268dec
LP		 1781 switch (kvm_msr_list->indices[i]) {
1782 case MSR_STAR:
c3a3a7d3 1783 has_msr_star = true;
1d268dec
LP		 1784 break;
1785 case MSR_VM_HSAVE_PA:
c3a3a7d3 1786 has_msr_hsave_pa = true;
1d268dec
LP		 1787 break;
1788 case MSR_TSC_AUX:
c9b8f6b6 1789 has_msr_tsc_aux = true;
1d268dec
LP		 1790 break;
1791 case MSR_TSC_ADJUST:
f28558d3 1792 has_msr_tsc_adjust = true;
1d268dec
LP		 1793 break;
1794 case MSR_IA32_TSCDEADLINE:
aa82ba54 1795 has_msr_tsc_deadline = true;
1d268dec
LP		 1796 break;
1797 case MSR_IA32_SMBASE:
fc12d72e 1798 has_msr_smbase = true;
1d268dec 1799 break;
e13713db
LA		 1800 case MSR_SMI_COUNT:
1801 has_msr_smi_count = true;
1802 break;
1d268dec 1803 case MSR_IA32_MISC_ENABLE:
21e87c46 1804 has_msr_misc_enable = true;
1d268dec
LP		 1805 break;
1806 case MSR_IA32_BNDCFGS:
79e9ebeb 1807 has_msr_bndcfgs = true;
1d268dec
LP		 1808 break;
1809 case MSR_IA32_XSS:
18cd2c17 1810 has_msr_xss = true;
3c254ab8 1811 break;
1d268dec 1812 case HV_X64_MSR_CRASH_CTL:
f2a53c9e 1813 has_msr_hv_crash = true;
1d268dec
LP		 1814 break;
1815 case HV_X64_MSR_RESET:
744b8a94 1816 has_msr_hv_reset = true;
1d268dec
LP		 1817 break;
1818 case HV_X64_MSR_VP_INDEX:
8c145d7c 1819 has_msr_hv_vpindex = true;
1d268dec
LP		 1820 break;
1821 case HV_X64_MSR_VP_RUNTIME:
46eb8f98 1822 has_msr_hv_runtime = true;
1d268dec
LP		 1823 break;
1824 case HV_X64_MSR_SCONTROL:
866eea9a 1825 has_msr_hv_synic = true;
1d268dec
LP		 1826 break;
1827 case HV_X64_MSR_STIMER0_CONFIG:
ff99aa64 1828 has_msr_hv_stimer = true;
1d268dec 1829 break;
d72bc7f6
LP		 1830 case HV_X64_MSR_TSC_FREQUENCY:
1831 has_msr_hv_frequencies = true;
1832 break;
ba6a4fd9
VK		 1833 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
1834 has_msr_hv_reenlightenment = true;
1835 break;
a33a2cfe
PB		 1836 case MSR_IA32_SPEC_CTRL:
1837 has_msr_spec_ctrl = true;
1838 break;
cfeea0c0
KRW		 1839 case MSR_VIRT_SSBD:
1840 has_msr_virt_ssbd = true;
1841 break;
aec5e9c3
BD		 1842 case MSR_IA32_ARCH_CAPABILITIES:
1843 has_msr_arch_capabs = true;
1844 break;
ff99aa64 1845 }
05330448
AL		 1846 }
1847 }
1848
7267c094 1849 g_free(kvm_msr_list);
05330448
AL		 1850 }
1851
c3a3a7d3 1852 return ret;
05330448
AL		 1853}
1854
6410848b
PB		 1855static Notifier smram_machine_done;
1856static KVMMemoryListener smram_listener;
1857static AddressSpace smram_address_space;
1858static MemoryRegion smram_as_root;
1859static MemoryRegion smram_as_mem;
1860
1861static void register_smram_listener(Notifier *n, void *unused)
1862{
1863 MemoryRegion *smram =
1864 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1865
1866 /* Outer container... */
1867 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1868 memory_region_set_enabled(&smram_as_root, true);
1869
1870 /* ... with two regions inside: normal system memory with low
1871 * priority, and...
1872 */
1873 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1874 get_system_memory(), 0, ~0ull);
1875 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1876 memory_region_set_enabled(&smram_as_mem, true);
1877
1878 if (smram) {
1879 /* ... SMRAM with higher priority */
1880 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1881 memory_region_set_enabled(smram, true);
1882 }
1883
1884 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1885 kvm_memory_listener_register(kvm_state, &smram_listener,
1886 &smram_address_space, 1);
1887}
1888
b16565b3 1889int kvm_arch_init(MachineState *ms, KVMState *s)
20420430 1890{
11076198 1891 uint64_t identity_base = 0xfffbc000;
39d6960a 1892 uint64_t shadow_mem;
20420430 1893 int ret;
25d2e361 1894 struct utsname utsname;
20420430 1895
28143b40 1896 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
28143b40 1897 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
28143b40 1898 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
28143b40 1899
e9688fab
RK		 1900 hv_vpindex_settable = kvm_check_extension(s, KVM_CAP_HYPERV_VP_INDEX);
1901
c3a3a7d3 1902 ret = kvm_get_supported_msrs(s);
20420430 1903 if (ret < 0) {
20420430
SY		 1904 return ret;
1905 }
25d2e361 1906
f57bceb6
RH		 1907 kvm_get_supported_feature_msrs(s);
1908
25d2e361
MT		 1909 uname(&utsname);
1910 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1911
4c5b10b7 1912 /*
11076198
JK		 1913 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1914 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
1915 * Since these must be part of guest physical memory, we need to allocate
1916 * them, both by setting their start addresses in the kernel and by
1917 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1918 *
1919 * Older KVM versions may not support setting the identity map base. In
1920 * that case we need to stick with the default, i.e. a 256K maximum BIOS
1921 * size.
4c5b10b7 1922 */
11076198
JK		 1923 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1924 /* Allows up to 16M BIOSes. */
1925 identity_base = 0xfeffc000;
1926
1927 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1928 if (ret < 0) {
1929 return ret;
1930 }
4c5b10b7 1931 }
e56ff191 1932
11076198
JK		 1933 /* Set TSS base one page after EPT identity map. */
1934 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
20420430
SY		 1935 if (ret < 0) {
1936 return ret;
1937 }
1938
11076198
JK		 1939 /* Tell fw_cfg to notify the BIOS to reserve the range. */
1940 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
20420430 1941 if (ret < 0) {
11076198 1942 fprintf(stderr, "e820_add_entry() table is full\n");
20420430
SY		 1943 return ret;
1944 }
3c85e74f 1945 qemu_register_reset(kvm_unpoison_all, NULL);
20420430 1946
4689b77b 1947 shadow_mem = machine_kvm_shadow_mem(ms);
36ad0e94
MA		 1948 if (shadow_mem != -1) {
1949 shadow_mem /= 4096;
1950 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1951 if (ret < 0) {
1952 return ret;
39d6960a
JK		 1953 }
1954 }
6410848b 1955
d870cfde
GA		 1956 if (kvm_check_extension(s, KVM_CAP_X86_SMM) &&
1957 object_dynamic_cast(OBJECT(ms), TYPE_PC_MACHINE) &&
1958 pc_machine_is_smm_enabled(PC_MACHINE(ms))) {
6410848b
PB		 1959 smram_machine_done.notify = register_smram_listener;
1960 qemu_add_machine_init_done_notifier(&smram_machine_done);
1961 }
6f131f13
MT		 1962
1963 if (enable_cpu_pm) {
1964 int disable_exits = kvm_check_extension(s, KVM_CAP_X86_DISABLE_EXITS);
1965 int ret;
1966
1967/* Work around for kernel header with a typo. TODO: fix header and drop. */
1968#if defined(KVM_X86_DISABLE_EXITS_HTL) && !defined(KVM_X86_DISABLE_EXITS_HLT)
1969#define KVM_X86_DISABLE_EXITS_HLT KVM_X86_DISABLE_EXITS_HTL
1970#endif
1971 if (disable_exits) {
1972 disable_exits &= (KVM_X86_DISABLE_EXITS_MWAIT |
1973 KVM_X86_DISABLE_EXITS_HLT |
1974 KVM_X86_DISABLE_EXITS_PAUSE);
1975 }
1976
1977 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_DISABLE_EXITS, 0,
1978 disable_exits);
1979 if (ret < 0) {
1980 error_report("kvm: guest stopping CPU not supported: %s",
1981 strerror(-ret));
1982 }
1983 }
1984
11076198 1985 return 0;
05330448 1986}
b9bec74b 1987
05330448
AL		 1988static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1989{
1990 lhs->selector = rhs->selector;
1991 lhs->base = rhs->base;
1992 lhs->limit = rhs->limit;
1993 lhs->type = 3;
1994 lhs->present = 1;
1995 lhs->dpl = 3;
1996 lhs->db = 0;
1997 lhs->s = 1;
1998 lhs->l = 0;
1999 lhs->g = 0;
2000 lhs->avl = 0;
2001 lhs->unusable = 0;
2002}
2003
2004static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
2005{
2006 unsigned flags = rhs->flags;
2007 lhs->selector = rhs->selector;
2008 lhs->base = rhs->base;
2009 lhs->limit = rhs->limit;
2010 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
2011 lhs->present = (flags & DESC_P_MASK) != 0;
acaa7550 2012 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
05330448
AL		 2013 lhs->db = (flags >> DESC_B_SHIFT) & 1;
2014 lhs->s = (flags & DESC_S_MASK) != 0;
2015 lhs->l = (flags >> DESC_L_SHIFT) & 1;
2016 lhs->g = (flags & DESC_G_MASK) != 0;
2017 lhs->avl = (flags & DESC_AVL_MASK) != 0;
4cae9c97 2018 lhs->unusable = !lhs->present;
7e680753 2019 lhs->padding = 0;
05330448
AL		 2020}
2021
2022static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
2023{
2024 lhs->selector = rhs->selector;
2025 lhs->base = rhs->base;
2026 lhs->limit = rhs->limit;
d45fc087
RP		 2027 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
2028 ((rhs->present && !rhs->unusable) * DESC_P_MASK) |
2029 (rhs->dpl << DESC_DPL_SHIFT) |
2030 (rhs->db << DESC_B_SHIFT) |
2031 (rhs->s * DESC_S_MASK) |
2032 (rhs->l << DESC_L_SHIFT) |
2033 (rhs->g * DESC_G_MASK) |
2034 (rhs->avl * DESC_AVL_MASK);
05330448
AL		 2035}
2036
2037static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
2038{
b9bec74b 2039 if (set) {
05330448 2040 *kvm_reg = *qemu_reg;
b9bec74b 2041 } else {
05330448 2042 *qemu_reg = *kvm_reg;
b9bec74b 2043 }
05330448
AL		 2044}
2045
1bc22652 2046static int kvm_getput_regs(X86CPU *cpu, int set)
05330448 2047{
1bc22652 2048 CPUX86State *env = &cpu->env;
05330448
AL		 2049 struct kvm_regs regs;
2050 int ret = 0;
2051
2052 if (!set) {
1bc22652 2053 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
b9bec74b 2054 if (ret < 0) {
05330448 2055 return ret;
b9bec74b 2056 }
05330448
AL		 2057 }
2058
2059 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
2060 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
2061 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
2062 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
2063 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
2064 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
2065 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
2066 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
2067#ifdef TARGET_X86_64
2068 kvm_getput_reg(&regs.r8, &env->regs[8], set);
2069 kvm_getput_reg(&regs.r9, &env->regs[9], set);
2070 kvm_getput_reg(&regs.r10, &env->regs[10], set);
2071 kvm_getput_reg(&regs.r11, &env->regs[11], set);
2072 kvm_getput_reg(&regs.r12, &env->regs[12], set);
2073 kvm_getput_reg(&regs.r13, &env->regs[13], set);
2074 kvm_getput_reg(&regs.r14, &env->regs[14], set);
2075 kvm_getput_reg(&regs.r15, &env->regs[15], set);
2076#endif
2077
2078 kvm_getput_reg(&regs.rflags, &env->eflags, set);
2079 kvm_getput_reg(&regs.rip, &env->eip, set);
2080
b9bec74b 2081 if (set) {
1bc22652 2082 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
b9bec74b 2083 }
05330448
AL		 2084
2085 return ret;
2086}
2087
1bc22652 2088static int kvm_put_fpu(X86CPU *cpu)
05330448 2089{
1bc22652 2090 CPUX86State *env = &cpu->env;
05330448
AL		 2091 struct kvm_fpu fpu;
2092 int i;
2093
2094 memset(&fpu, 0, sizeof fpu);
2095 fpu.fsw = env->fpus & ~(7 << 11);
2096 fpu.fsw |= (env->fpstt & 7) << 11;
2097 fpu.fcw = env->fpuc;
42cc8fa6
JK		 2098 fpu.last_opcode = env->fpop;
2099 fpu.last_ip = env->fpip;
2100 fpu.last_dp = env->fpdp;
b9bec74b
JK		 2101 for (i = 0; i < 8; ++i) {
2102 fpu.ftwx |= (!env->fptags[i]) << i;
2103 }
05330448 2104 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
bee81887 2105 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 2106 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
2107 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
bee81887 2108 }
05330448
AL		 2109 fpu.mxcsr = env->mxcsr;
2110
1bc22652 2111 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
05330448
AL		 2112}
2113
6b42494b
JK		 2114#define XSAVE_FCW_FSW 0
2115#define XSAVE_FTW_FOP 1
f1665b21
SY		 2116#define XSAVE_CWD_RIP 2
2117#define XSAVE_CWD_RDP 4
2118#define XSAVE_MXCSR 6
2119#define XSAVE_ST_SPACE 8
2120#define XSAVE_XMM_SPACE 40
2121#define XSAVE_XSTATE_BV 128
2122#define XSAVE_YMMH_SPACE 144
79e9ebeb
LJ		 2123#define XSAVE_BNDREGS 240
2124#define XSAVE_BNDCSR 256
9aecd6f8
CP		 2125#define XSAVE_OPMASK 272
2126#define XSAVE_ZMM_Hi256 288
2127#define XSAVE_Hi16_ZMM 416
f74eefe0 2128#define XSAVE_PKRU 672
f1665b21 2129
b503717d 2130#define XSAVE_BYTE_OFFSET(word_offset) \
f18793b0 2131 ((word_offset) * sizeof_field(struct kvm_xsave, region[0]))
b503717d
EH		 2132
2133#define ASSERT_OFFSET(word_offset, field) \
2134 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
2135 offsetof(X86XSaveArea, field))
2136
2137ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
2138ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
2139ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
2140ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
2141ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
2142ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
2143ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
2144ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
2145ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
2146ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
2147ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
2148ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
2149ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
2150ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
2151ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
2152
1bc22652 2153static int kvm_put_xsave(X86CPU *cpu)
f1665b21 2154{
1bc22652 2155 CPUX86State *env = &cpu->env;
5b8063c4 2156 X86XSaveArea *xsave = env->xsave_buf;
f1665b21 2157
28143b40 2158 if (!has_xsave) {
1bc22652 2159 return kvm_put_fpu(cpu);
b9bec74b 2160 }
86a57621 2161 x86_cpu_xsave_all_areas(cpu, xsave);
f1665b21 2162
9be38598 2163 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
f1665b21
SY		 2164}
2165
1bc22652 2166static int kvm_put_xcrs(X86CPU *cpu)
f1665b21 2167{
1bc22652 2168 CPUX86State *env = &cpu->env;
bdfc8480 2169 struct kvm_xcrs xcrs = {};
f1665b21 2170
28143b40 2171 if (!has_xcrs) {
f1665b21 2172 return 0;
b9bec74b 2173 }
f1665b21
SY		 2174
2175 xcrs.nr_xcrs = 1;
2176 xcrs.flags = 0;
2177 xcrs.xcrs[0].xcr = 0;
2178 xcrs.xcrs[0].value = env->xcr0;
1bc22652 2179 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
f1665b21
SY		 2180}
2181
1bc22652 2182static int kvm_put_sregs(X86CPU *cpu)
05330448 2183{
1bc22652 2184 CPUX86State *env = &cpu->env;
05330448
AL		 2185 struct kvm_sregs sregs;
2186
0e607a80
JK		 2187 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
2188 if (env->interrupt_injected >= 0) {
2189 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
2190 (uint64_t)1 << (env->interrupt_injected % 64);
2191 }
05330448
AL		 2192
2193 if ((env->eflags & VM_MASK)) {
b9bec74b
JK		 2194 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
2195 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
2196 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
2197 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
2198 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
2199 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
05330448 2200 } else {
b9bec74b
JK		 2201 set_seg(&sregs.cs, &env->segs[R_CS]);
2202 set_seg(&sregs.ds, &env->segs[R_DS]);
2203 set_seg(&sregs.es, &env->segs[R_ES]);
2204 set_seg(&sregs.fs, &env->segs[R_FS]);
2205 set_seg(&sregs.gs, &env->segs[R_GS]);
2206 set_seg(&sregs.ss, &env->segs[R_SS]);
05330448
AL		 2207 }
2208
2209 set_seg(&sregs.tr, &env->tr);
2210 set_seg(&sregs.ldt, &env->ldt);
2211
2212 sregs.idt.limit = env->idt.limit;
2213 sregs.idt.base = env->idt.base;
7e680753 2214 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
05330448
AL		 2215 sregs.gdt.limit = env->gdt.limit;
2216 sregs.gdt.base = env->gdt.base;
7e680753 2217 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
05330448
AL		 2218
2219 sregs.cr0 = env->cr[0];
2220 sregs.cr2 = env->cr[2];
2221 sregs.cr3 = env->cr[3];
2222 sregs.cr4 = env->cr[4];
2223
02e51483
CF		 2224 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
2225 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
05330448
AL		 2226
2227 sregs.efer = env->efer;
2228
1bc22652 2229 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
05330448
AL		 2230}
2231
d71b62a1
EH		 2232static void kvm_msr_buf_reset(X86CPU *cpu)
2233{
2234 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
2235}
2236
9c600a84
EH		 2237static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
2238{
2239 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
2240 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
2241 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
2242
2243 assert((void *)(entry + 1) <= limit);
2244
1abc2cae
EH		 2245 entry->index = index;
2246 entry->reserved = 0;
2247 entry->data = value;
9c600a84
EH		 2248 msrs->nmsrs++;
2249}
2250
73e1b8f2
PB		 2251static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
2252{
2253 kvm_msr_buf_reset(cpu);
2254 kvm_msr_entry_add(cpu, index, value);
2255
2256 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
2257}
2258
f8d9ccf8
DDAG		 2259void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
2260{
2261 int ret;
2262
2263 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
2264 assert(ret == 1);
2265}
2266
7477cd38
MT		 2267static int kvm_put_tscdeadline_msr(X86CPU *cpu)
2268{
2269 CPUX86State *env = &cpu->env;
48e1a45c 2270 int ret;
7477cd38
MT		 2271
2272 if (!has_msr_tsc_deadline) {
2273 return 0;
2274 }
2275
73e1b8f2 2276 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
48e1a45c
PB		 2277 if (ret < 0) {
2278 return ret;
2279 }
2280
2281 assert(ret == 1);
2282 return 0;
7477cd38
MT		 2283}
2284
6bdf863d
JK		 2285/*
2286 * Provide a separate write service for the feature control MSR in order to
2287 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
2288 * before writing any other state because forcibly leaving nested mode
2289 * invalidates the VCPU state.
2290 */
2291static int kvm_put_msr_feature_control(X86CPU *cpu)
2292{
48e1a45c
PB		 2293 int ret;
2294
2295 if (!has_msr_feature_control) {
2296 return 0;
2297 }
6bdf863d 2298
73e1b8f2
PB		 2299 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
2300 cpu->env.msr_ia32_feature_control);
48e1a45c
PB		 2301 if (ret < 0) {
2302 return ret;
2303 }
2304
2305 assert(ret == 1);
2306 return 0;
6bdf863d
JK		 2307}
2308
1bc22652 2309static int kvm_put_msrs(X86CPU *cpu, int level)
05330448 2310{
1bc22652 2311 CPUX86State *env = &cpu->env;
9c600a84 2312 int i;
48e1a45c 2313 int ret;
05330448 2314
d71b62a1
EH		 2315 kvm_msr_buf_reset(cpu);
2316
9c600a84
EH		 2317 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
2318 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
2319 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
2320 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
c3a3a7d3 2321 if (has_msr_star) {
9c600a84 2322 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
b9bec74b 2323 }
c3a3a7d3 2324 if (has_msr_hsave_pa) {
9c600a84 2325 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
b9bec74b 2326 }
c9b8f6b6 2327 if (has_msr_tsc_aux) {
9c600a84 2328 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
c9b8f6b6 2329 }
f28558d3 2330 if (has_msr_tsc_adjust) {
9c600a84 2331 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
f28558d3 2332 }
21e87c46 2333 if (has_msr_misc_enable) {
9c600a84 2334 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
21e87c46
AK		 2335 env->msr_ia32_misc_enable);
2336 }
fc12d72e 2337 if (has_msr_smbase) {
9c600a84 2338 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
fc12d72e 2339 }
e13713db
LA		 2340 if (has_msr_smi_count) {
2341 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, env->msr_smi_count);
2342 }
439d19f2 2343 if (has_msr_bndcfgs) {
9c600a84 2344 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
439d19f2 2345 }
18cd2c17 2346 if (has_msr_xss) {
9c600a84 2347 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
18cd2c17 2348 }
a33a2cfe
PB		 2349 if (has_msr_spec_ctrl) {
2350 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
2351 }
cfeea0c0
KRW		 2352 if (has_msr_virt_ssbd) {
2353 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd);
2354 }
2355
05330448 2356#ifdef TARGET_X86_64
25d2e361 2357 if (lm_capable_kernel) {
9c600a84
EH		 2358 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
2359 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
2360 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
2361 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
25d2e361 2362 }
05330448 2363#endif
a33a2cfe 2364
d86f9636 2365 /* If host supports feature MSR, write down. */
aec5e9c3
BD		 2366 if (has_msr_arch_capabs) {
2367 kvm_msr_entry_add(cpu, MSR_IA32_ARCH_CAPABILITIES,
2368 env->features[FEAT_ARCH_CAPABILITIES]);
d86f9636
RH		 2369 }
2370
ff5c186b 2371 /*
0d894367
PB		 2372 * The following MSRs have side effects on the guest or are too heavy
2373 * for normal writeback. Limit them to reset or full state updates.
ff5c186b
JK		 2374 */
2375 if (level >= KVM_PUT_RESET_STATE) {
9c600a84
EH		 2376 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
2377 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
2378 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
55c911a5 2379 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
9c600a84 2380 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
c5999bfc 2381 }
55c911a5 2382 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 2383 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
bc9a839d 2384 }
55c911a5 2385 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 2386 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
917367aa 2387 }
0b368a10
JD		 2388 if (has_architectural_pmu_version > 0) {
2389 if (has_architectural_pmu_version > 1) {
2390 /* Stop the counter. */
2391 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2392 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2393 }
0d894367
PB		 2394
2395 /* Set the counter values. */
0b368a10 2396 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
9c600a84 2397 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
0d894367
PB		 2398 env->msr_fixed_counters[i]);
2399 }
0b368a10 2400 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
9c600a84 2401 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
0d894367 2402 env->msr_gp_counters[i]);
9c600a84 2403 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
0d894367
PB		 2404 env->msr_gp_evtsel[i]);
2405 }
0b368a10
JD		 2406 if (has_architectural_pmu_version > 1) {
2407 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
2408 env->msr_global_status);
2409 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
2410 env->msr_global_ovf_ctrl);
2411
2412 /* Now start the PMU. */
2413 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
2414 env->msr_fixed_ctr_ctrl);
2415 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
2416 env->msr_global_ctrl);
2417 }
0d894367 2418 }
da1cc323
EY		 2419 /*
2420 * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add,
2421 * only sync them to KVM on the first cpu
2422 */
2423 if (current_cpu == first_cpu) {
2424 if (has_msr_hv_hypercall) {
2425 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
2426 env->msr_hv_guest_os_id);
2427 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
2428 env->msr_hv_hypercall);
2429 }
2d384d7c 2430 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) {
da1cc323
EY		 2431 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC,
2432 env->msr_hv_tsc);
2433 }
2d384d7c 2434 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) {
ba6a4fd9
VK		 2435 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL,
2436 env->msr_hv_reenlightenment_control);
2437 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL,
2438 env->msr_hv_tsc_emulation_control);
2439 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS,
2440 env->msr_hv_tsc_emulation_status);
2441 }
eab70139 2442 }
2d384d7c 2443 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
9c600a84 2444 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
5ef68987 2445 env->msr_hv_vapic);
eab70139 2446 }
f2a53c9e
AS		 2447 if (has_msr_hv_crash) {
2448 int j;
2449
5e953812 2450 for (j = 0; j < HV_CRASH_PARAMS; j++)
9c600a84 2451 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
f2a53c9e
AS		 2452 env->msr_hv_crash_params[j]);
2453
5e953812 2454 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_NOTIFY);
f2a53c9e 2455 }
46eb8f98 2456 if (has_msr_hv_runtime) {
9c600a84 2457 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
46eb8f98 2458 }
2d384d7c
VK		 2459 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)
2460 && hv_vpindex_settable) {
701189e3
RK		 2461 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_INDEX,
2462 hyperv_vp_index(CPU(cpu)));
e9688fab 2463 }
2d384d7c 2464 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
866eea9a
AS		 2465 int j;
2466
09df29b6
RK		 2467 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, HV_SYNIC_VERSION);
2468
9c600a84 2469 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
866eea9a 2470 env->msr_hv_synic_control);
9c600a84 2471 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
866eea9a 2472 env->msr_hv_synic_evt_page);
9c600a84 2473 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
866eea9a
AS		 2474 env->msr_hv_synic_msg_page);
2475
2476 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
9c600a84 2477 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
866eea9a
AS		 2478 env->msr_hv_synic_sint[j]);
2479 }
2480 }
ff99aa64
AS		 2481 if (has_msr_hv_stimer) {
2482 int j;
2483
2484 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
9c600a84 2485 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
ff99aa64
AS		 2486 env->msr_hv_stimer_config[j]);
2487 }
2488
2489 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
9c600a84 2490 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
ff99aa64
AS		 2491 env->msr_hv_stimer_count[j]);
2492 }
2493 }
1eabfce6 2494 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
112dad69
DDAG		 2495 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
2496
9c600a84
EH		 2497 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
2498 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
2499 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
2500 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
2501 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
2502 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
2503 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
2504 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
2505 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
2506 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
2507 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
2508 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
d1ae67f6 2509 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
112dad69
DDAG		 2510 /* The CPU GPs if we write to a bit above the physical limit of
2511 * the host CPU (and KVM emulates that)
2512 */
2513 uint64_t mask = env->mtrr_var[i].mask;
2514 mask &= phys_mask;
2515
9c600a84
EH		 2516 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
2517 env->mtrr_var[i].base);
112dad69 2518 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
d1ae67f6
AW		 2519 }
2520 }
b77146e9
CP		 2521 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
2522 int addr_num = kvm_arch_get_supported_cpuid(kvm_state,
2523 0x14, 1, R_EAX) & 0x7;
2524
2525 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL,
2526 env->msr_rtit_ctrl);
2527 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS,
2528 env->msr_rtit_status);
2529 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE,
2530 env->msr_rtit_output_base);
2531 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK,
2532 env->msr_rtit_output_mask);
2533 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH,
2534 env->msr_rtit_cr3_match);
2535 for (i = 0; i < addr_num; i++) {
2536 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i,
2537 env->msr_rtit_addrs[i]);
2538 }
2539 }
6bdf863d
JK		 2540
2541 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
2542 * kvm_put_msr_feature_control. */
ea643051 2543 }
57780495 2544 if (env->mcg_cap) {
d8da8574 2545 int i;
b9bec74b 2546
9c600a84
EH		 2547 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
2548 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
87f8b626
AR		 2549 if (has_msr_mcg_ext_ctl) {
2550 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
2551 }
c34d440a 2552 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 2553 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
57780495
MT		 2554 }
2555 }
1a03675d 2556
d71b62a1 2557 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
48e1a45c
PB		 2558 if (ret < 0) {
2559 return ret;
2560 }
05330448 2561
c70b11d1
EH		 2562 if (ret < cpu->kvm_msr_buf->nmsrs) {
2563 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2564 error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
2565 (uint32_t)e->index, (uint64_t)e->data);
2566 }
2567
9c600a84 2568 assert(ret == cpu->kvm_msr_buf->nmsrs);
48e1a45c 2569 return 0;
05330448
AL		 2570}
2571
2572
1bc22652 2573static int kvm_get_fpu(X86CPU *cpu)
05330448 2574{
1bc22652 2575 CPUX86State *env = &cpu->env;
05330448
AL		 2576 struct kvm_fpu fpu;
2577 int i, ret;
2578
1bc22652 2579 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
b9bec74b 2580 if (ret < 0) {
05330448 2581 return ret;
b9bec74b 2582 }
05330448
AL		 2583
2584 env->fpstt = (fpu.fsw >> 11) & 7;
2585 env->fpus = fpu.fsw;
2586 env->fpuc = fpu.fcw;
42cc8fa6
JK		 2587 env->fpop = fpu.last_opcode;
2588 env->fpip = fpu.last_ip;
2589 env->fpdp = fpu.last_dp;
b9bec74b
JK		 2590 for (i = 0; i < 8; ++i) {
2591 env->fptags[i] = !((fpu.ftwx >> i) & 1);
2592 }
05330448 2593 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
bee81887 2594 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 2595 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
2596 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
bee81887 2597 }
05330448
AL		 2598 env->mxcsr = fpu.mxcsr;
2599
2600 return 0;
2601}
2602
1bc22652 2603static int kvm_get_xsave(X86CPU *cpu)
f1665b21 2604{
1bc22652 2605 CPUX86State *env = &cpu->env;
5b8063c4 2606 X86XSaveArea *xsave = env->xsave_buf;
86a57621 2607 int ret;
f1665b21 2608
28143b40 2609 if (!has_xsave) {
1bc22652 2610 return kvm_get_fpu(cpu);
b9bec74b 2611 }
f1665b21 2612
1bc22652 2613 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
0f53994f 2614 if (ret < 0) {
f1665b21 2615 return ret;
0f53994f 2616 }
86a57621 2617 x86_cpu_xrstor_all_areas(cpu, xsave);
f1665b21 2618
f1665b21 2619 return 0;
f1665b21
SY		 2620}
2621
1bc22652 2622static int kvm_get_xcrs(X86CPU *cpu)
f1665b21 2623{
1bc22652 2624 CPUX86State *env = &cpu->env;
f1665b21
SY		 2625 int i, ret;
2626 struct kvm_xcrs xcrs;
2627
28143b40 2628 if (!has_xcrs) {
f1665b21 2629 return 0;
b9bec74b 2630 }
f1665b21 2631
1bc22652 2632 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
b9bec74b 2633 if (ret < 0) {
f1665b21 2634 return ret;
b9bec74b 2635 }
f1665b21 2636
b9bec74b 2637 for (i = 0; i < xcrs.nr_xcrs; i++) {
f1665b21 2638 /* Only support xcr0 now */
0fd53fec
PB		 2639 if (xcrs.xcrs[i].xcr == 0) {
2640 env->xcr0 = xcrs.xcrs[i].value;
f1665b21
SY		 2641 break;
2642 }
b9bec74b 2643 }
f1665b21 2644 return 0;
f1665b21
SY		 2645}
2646
1bc22652 2647static int kvm_get_sregs(X86CPU *cpu)
05330448 2648{
1bc22652 2649 CPUX86State *env = &cpu->env;
05330448 2650 struct kvm_sregs sregs;
0e607a80 2651 int bit, i, ret;
05330448 2652
1bc22652 2653 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
b9bec74b 2654 if (ret < 0) {
05330448 2655 return ret;
b9bec74b 2656 }
05330448 2657
0e607a80
JK		 2658 /* There can only be one pending IRQ set in the bitmap at a time, so try
2659 to find it and save its number instead (-1 for none). */
2660 env->interrupt_injected = -1;
2661 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
2662 if (sregs.interrupt_bitmap[i]) {
2663 bit = ctz64(sregs.interrupt_bitmap[i]);
2664 env->interrupt_injected = i * 64 + bit;
2665 break;
2666 }
2667 }
05330448
AL		 2668
2669 get_seg(&env->segs[R_CS], &sregs.cs);
2670 get_seg(&env->segs[R_DS], &sregs.ds);
2671 get_seg(&env->segs[R_ES], &sregs.es);
2672 get_seg(&env->segs[R_FS], &sregs.fs);
2673 get_seg(&env->segs[R_GS], &sregs.gs);
2674 get_seg(&env->segs[R_SS], &sregs.ss);
2675
2676 get_seg(&env->tr, &sregs.tr);
2677 get_seg(&env->ldt, &sregs.ldt);
2678
2679 env->idt.limit = sregs.idt.limit;
2680 env->idt.base = sregs.idt.base;
2681 env->gdt.limit = sregs.gdt.limit;
2682 env->gdt.base = sregs.gdt.base;
2683
2684 env->cr[0] = sregs.cr0;
2685 env->cr[2] = sregs.cr2;
2686 env->cr[3] = sregs.cr3;
2687 env->cr[4] = sregs.cr4;
2688
05330448 2689 env->efer = sregs.efer;
cce47516
JK		 2690
2691 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
35b1b927 2692 x86_update_hflags(env);
05330448
AL		 2693
2694 return 0;
2695}
2696
1bc22652 2697static int kvm_get_msrs(X86CPU *cpu)
05330448 2698{
1bc22652 2699 CPUX86State *env = &cpu->env;
d71b62a1 2700 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
9c600a84 2701 int ret, i;
fcc35e7c 2702 uint64_t mtrr_top_bits;
05330448 2703
d71b62a1
EH		 2704 kvm_msr_buf_reset(cpu);
2705
9c600a84
EH		 2706 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
2707 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
2708 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
2709 kvm_msr_entry_add(cpu, MSR_PAT, 0);
c3a3a7d3 2710 if (has_msr_star) {
9c600a84 2711 kvm_msr_entry_add(cpu, MSR_STAR, 0);
b9bec74b 2712 }
c3a3a7d3 2713 if (has_msr_hsave_pa) {
9c600a84 2714 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
b9bec74b 2715 }
c9b8f6b6 2716 if (has_msr_tsc_aux) {
9c600a84 2717 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
c9b8f6b6 2718 }
f28558d3 2719 if (has_msr_tsc_adjust) {
9c600a84 2720 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
f28558d3 2721 }
aa82ba54 2722 if (has_msr_tsc_deadline) {
9c600a84 2723 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
aa82ba54 2724 }
21e87c46 2725 if (has_msr_misc_enable) {
9c600a84 2726 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
21e87c46 2727 }
fc12d72e 2728 if (has_msr_smbase) {
9c600a84 2729 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
fc12d72e 2730 }
e13713db
LA		 2731 if (has_msr_smi_count) {
2732 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, 0);
2733 }
df67696e 2734 if (has_msr_feature_control) {
9c600a84 2735 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
df67696e 2736 }
79e9ebeb 2737 if (has_msr_bndcfgs) {
9c600a84 2738 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
79e9ebeb 2739 }
18cd2c17 2740 if (has_msr_xss) {
9c600a84 2741 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
18cd2c17 2742 }
a33a2cfe
PB		 2743 if (has_msr_spec_ctrl) {
2744 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
2745 }
cfeea0c0
KRW		 2746 if (has_msr_virt_ssbd) {
2747 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0);
2748 }
b8cc45d6 2749 if (!env->tsc_valid) {
9c600a84 2750 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
1354869c 2751 env->tsc_valid = !runstate_is_running();
b8cc45d6
GC		 2752 }
2753
05330448 2754#ifdef TARGET_X86_64
25d2e361 2755 if (lm_capable_kernel) {
9c600a84
EH		 2756 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
2757 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
2758 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
2759 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
25d2e361 2760 }
05330448 2761#endif
9c600a84
EH		 2762 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
2763 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
55c911a5 2764 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
9c600a84 2765 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
c5999bfc 2766 }
55c911a5 2767 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 2768 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
bc9a839d 2769 }
55c911a5 2770 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 2771 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
917367aa 2772 }
0b368a10
JD		 2773 if (has_architectural_pmu_version > 0) {
2774 if (has_architectural_pmu_version > 1) {
2775 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2776 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2777 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
2778 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
2779 }
2780 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
9c600a84 2781 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
0d894367 2782 }
0b368a10 2783 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
9c600a84
EH		 2784 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
2785 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
0d894367
PB		 2786 }
2787 }
1a03675d 2788
57780495 2789 if (env->mcg_cap) {
9c600a84
EH		 2790 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
2791 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
87f8b626
AR		 2792 if (has_msr_mcg_ext_ctl) {
2793 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
2794 }
b9bec74b 2795 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 2796 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
b9bec74b 2797 }
57780495 2798 }
57780495 2799
1c90ef26 2800 if (has_msr_hv_hypercall) {
9c600a84
EH		 2801 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
2802 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
1c90ef26 2803 }
2d384d7c 2804 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
9c600a84 2805 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
5ef68987 2806 }
2d384d7c 2807 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) {
9c600a84 2808 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
48a5f3bc 2809 }
2d384d7c 2810 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) {
ba6a4fd9
VK		 2811 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL, 0);
2812 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL, 0);
2813 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS, 0);
2814 }
f2a53c9e
AS		 2815 if (has_msr_hv_crash) {
2816 int j;
2817
5e953812 2818 for (j = 0; j < HV_CRASH_PARAMS; j++) {
9c600a84 2819 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
f2a53c9e
AS		 2820 }
2821 }
46eb8f98 2822 if (has_msr_hv_runtime) {
9c600a84 2823 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
46eb8f98 2824 }
2d384d7c 2825 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
866eea9a
AS		 2826 uint32_t msr;
2827
9c600a84 2828 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
9c600a84
EH		 2829 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
2830 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
866eea9a 2831 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
9c600a84 2832 kvm_msr_entry_add(cpu, msr, 0);
866eea9a
AS		 2833 }
2834 }
ff99aa64
AS		 2835 if (has_msr_hv_stimer) {
2836 uint32_t msr;
2837
2838 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2839 msr++) {
9c600a84 2840 kvm_msr_entry_add(cpu, msr, 0);
ff99aa64
AS		 2841 }
2842 }
1eabfce6 2843 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
9c600a84
EH		 2844 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
2845 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
2846 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
2847 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
2848 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
2849 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
2850 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
2851 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
2852 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
2853 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
2854 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
2855 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
d1ae67f6 2856 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
9c600a84
EH		 2857 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
2858 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
d1ae67f6
AW		 2859 }
2860 }
5ef68987 2861
b77146e9
CP		 2862 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
2863 int addr_num =
2864 kvm_arch_get_supported_cpuid(kvm_state, 0x14, 1, R_EAX) & 0x7;
2865
2866 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 0);
2867 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 0);
2868 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, 0);
2869 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, 0);
2870 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, 0);
2871 for (i = 0; i < addr_num; i++) {
2872 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 0);
2873 }
2874 }
2875
d71b62a1 2876 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
b9bec74b 2877 if (ret < 0) {
05330448 2878 return ret;
b9bec74b 2879 }
05330448 2880
c70b11d1
EH		 2881 if (ret < cpu->kvm_msr_buf->nmsrs) {
2882 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2883 error_report("error: failed to get MSR 0x%" PRIx32,
2884 (uint32_t)e->index);
2885 }
2886
9c600a84 2887 assert(ret == cpu->kvm_msr_buf->nmsrs);
fcc35e7c
DDAG		 2888 /*
2889 * MTRR masks: Each mask consists of 5 parts
2890 * a 10..0: must be zero
2891 * b 11 : valid bit
2892 * c n-1.12: actual mask bits
2893 * d 51..n: reserved must be zero
2894 * e 63.52: reserved must be zero
2895 *
2896 * 'n' is the number of physical bits supported by the CPU and is
2897 * apparently always <= 52. We know our 'n' but don't know what
2898 * the destinations 'n' is; it might be smaller, in which case
2899 * it masks (c) on loading. It might be larger, in which case
2900 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
2901 * we're migrating to.
2902 */
2903
2904 if (cpu->fill_mtrr_mask) {
2905 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
2906 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
2907 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
2908 } else {
2909 mtrr_top_bits = 0;
2910 }
2911
05330448 2912 for (i = 0; i < ret; i++) {
0d894367
PB		 2913 uint32_t index = msrs[i].index;
2914 switch (index) {
05330448
AL		 2915 case MSR_IA32_SYSENTER_CS:
2916 env->sysenter_cs = msrs[i].data;
2917 break;
2918 case MSR_IA32_SYSENTER_ESP:
2919 env->sysenter_esp = msrs[i].data;
2920 break;
2921 case MSR_IA32_SYSENTER_EIP:
2922 env->sysenter_eip = msrs[i].data;
2923 break;
0c03266a
JK		 2924 case MSR_PAT:
2925 env->pat = msrs[i].data;
2926 break;
05330448
AL		 2927 case MSR_STAR:
2928 env->star = msrs[i].data;
2929 break;
2930#ifdef TARGET_X86_64
2931 case MSR_CSTAR:
2932 env->cstar = msrs[i].data;
2933 break;
2934 case MSR_KERNELGSBASE:
2935 env->kernelgsbase = msrs[i].data;
2936 break;
2937 case MSR_FMASK:
2938 env->fmask = msrs[i].data;
2939 break;
2940 case MSR_LSTAR:
2941 env->lstar = msrs[i].data;
2942 break;
2943#endif
2944 case MSR_IA32_TSC:
2945 env->tsc = msrs[i].data;
2946 break;
c9b8f6b6
AS		 2947 case MSR_TSC_AUX:
2948 env->tsc_aux = msrs[i].data;
2949 break;
f28558d3
WA		 2950 case MSR_TSC_ADJUST:
2951 env->tsc_adjust = msrs[i].data;
2952 break;
aa82ba54
LJ		 2953 case MSR_IA32_TSCDEADLINE:
2954 env->tsc_deadline = msrs[i].data;
2955 break;
aa851e36
MT		 2956 case MSR_VM_HSAVE_PA:
2957 env->vm_hsave = msrs[i].data;
2958 break;
1a03675d
GC		 2959 case MSR_KVM_SYSTEM_TIME:
2960 env->system_time_msr = msrs[i].data;
2961 break;
2962 case MSR_KVM_WALL_CLOCK:
2963 env->wall_clock_msr = msrs[i].data;
2964 break;
57780495
MT		 2965 case MSR_MCG_STATUS:
2966 env->mcg_status = msrs[i].data;
2967 break;
2968 case MSR_MCG_CTL:
2969 env->mcg_ctl = msrs[i].data;
2970 break;
87f8b626
AR		 2971 case MSR_MCG_EXT_CTL:
2972 env->mcg_ext_ctl = msrs[i].data;
2973 break;
21e87c46
AK		 2974 case MSR_IA32_MISC_ENABLE:
2975 env->msr_ia32_misc_enable = msrs[i].data;
2976 break;
fc12d72e
PB		 2977 case MSR_IA32_SMBASE:
2978 env->smbase = msrs[i].data;
2979 break;
e13713db
LA		 2980 case MSR_SMI_COUNT:
2981 env->msr_smi_count = msrs[i].data;
2982 break;
0779caeb
ACL		 2983 case MSR_IA32_FEATURE_CONTROL:
2984 env->msr_ia32_feature_control = msrs[i].data;
df67696e 2985 break;
79e9ebeb
LJ		 2986 case MSR_IA32_BNDCFGS:
2987 env->msr_bndcfgs = msrs[i].data;
2988 break;
18cd2c17
WL		 2989 case MSR_IA32_XSS:
2990 env->xss = msrs[i].data;
2991 break;
57780495 2992 default:
57780495
MT		 2993 if (msrs[i].index >= MSR_MC0_CTL &&
2994 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
2995 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
57780495 2996 }
d8da8574 2997 break;
f6584ee2
GN		 2998 case MSR_KVM_ASYNC_PF_EN:
2999 env->async_pf_en_msr = msrs[i].data;
3000 break;
bc9a839d
MT		 3001 case MSR_KVM_PV_EOI_EN:
3002 env->pv_eoi_en_msr = msrs[i].data;
3003 break;
917367aa
MT		 3004 case MSR_KVM_STEAL_TIME:
3005 env->steal_time_msr = msrs[i].data;
3006 break;
0d894367
PB		 3007 case MSR_CORE_PERF_FIXED_CTR_CTRL:
3008 env->msr_fixed_ctr_ctrl = msrs[i].data;
3009 break;
3010 case MSR_CORE_PERF_GLOBAL_CTRL:
3011 env->msr_global_ctrl = msrs[i].data;
3012 break;
3013 case MSR_CORE_PERF_GLOBAL_STATUS:
3014 env->msr_global_status = msrs[i].data;
3015 break;
3016 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
3017 env->msr_global_ovf_ctrl = msrs[i].data;
3018 break;
3019 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
3020 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
3021 break;
3022 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
3023 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
3024 break;
3025 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
3026 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
3027 break;
1c90ef26
VR		 3028 case HV_X64_MSR_HYPERCALL:
3029 env->msr_hv_hypercall = msrs[i].data;
3030 break;
3031 case HV_X64_MSR_GUEST_OS_ID:
3032 env->msr_hv_guest_os_id = msrs[i].data;
3033 break;
5ef68987
VR		 3034 case HV_X64_MSR_APIC_ASSIST_PAGE:
3035 env->msr_hv_vapic = msrs[i].data;
3036 break;
48a5f3bc
VR		 3037 case HV_X64_MSR_REFERENCE_TSC:
3038 env->msr_hv_tsc = msrs[i].data;
3039 break;
f2a53c9e
AS		 3040 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3041 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
3042 break;
46eb8f98
AS		 3043 case HV_X64_MSR_VP_RUNTIME:
3044 env->msr_hv_runtime = msrs[i].data;
3045 break;
866eea9a
AS		 3046 case HV_X64_MSR_SCONTROL:
3047 env->msr_hv_synic_control = msrs[i].data;
3048 break;
866eea9a
AS		 3049 case HV_X64_MSR_SIEFP:
3050 env->msr_hv_synic_evt_page = msrs[i].data;
3051 break;
3052 case HV_X64_MSR_SIMP:
3053 env->msr_hv_synic_msg_page = msrs[i].data;
3054 break;
3055 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
3056 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
ff99aa64
AS		 3057 break;
3058 case HV_X64_MSR_STIMER0_CONFIG:
3059 case HV_X64_MSR_STIMER1_CONFIG:
3060 case HV_X64_MSR_STIMER2_CONFIG:
3061 case HV_X64_MSR_STIMER3_CONFIG:
3062 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
3063 msrs[i].data;
3064 break;
3065 case HV_X64_MSR_STIMER0_COUNT:
3066 case HV_X64_MSR_STIMER1_COUNT:
3067 case HV_X64_MSR_STIMER2_COUNT:
3068 case HV_X64_MSR_STIMER3_COUNT:
3069 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
3070 msrs[i].data;
866eea9a 3071 break;
ba6a4fd9
VK		 3072 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3073 env->msr_hv_reenlightenment_control = msrs[i].data;
3074 break;
3075 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3076 env->msr_hv_tsc_emulation_control = msrs[i].data;
3077 break;
3078 case HV_X64_MSR_TSC_EMULATION_STATUS:
3079 env->msr_hv_tsc_emulation_status = msrs[i].data;
3080 break;
d1ae67f6
AW		 3081 case MSR_MTRRdefType:
3082 env->mtrr_deftype = msrs[i].data;
3083 break;
3084 case MSR_MTRRfix64K_00000:
3085 env->mtrr_fixed[0] = msrs[i].data;
3086 break;
3087 case MSR_MTRRfix16K_80000:
3088 env->mtrr_fixed[1] = msrs[i].data;
3089 break;
3090 case MSR_MTRRfix16K_A0000:
3091 env->mtrr_fixed[2] = msrs[i].data;
3092 break;
3093 case MSR_MTRRfix4K_C0000:
3094 env->mtrr_fixed[3] = msrs[i].data;
3095 break;
3096 case MSR_MTRRfix4K_C8000:
3097 env->mtrr_fixed[4] = msrs[i].data;
3098 break;
3099 case MSR_MTRRfix4K_D0000:
3100 env->mtrr_fixed[5] = msrs[i].data;
3101 break;
3102 case MSR_MTRRfix4K_D8000:
3103 env->mtrr_fixed[6] = msrs[i].data;
3104 break;
3105 case MSR_MTRRfix4K_E0000:
3106 env->mtrr_fixed[7] = msrs[i].data;
3107 break;
3108 case MSR_MTRRfix4K_E8000:
3109 env->mtrr_fixed[8] = msrs[i].data;
3110 break;
3111 case MSR_MTRRfix4K_F0000:
3112 env->mtrr_fixed[9] = msrs[i].data;
3113 break;
3114 case MSR_MTRRfix4K_F8000:
3115 env->mtrr_fixed[10] = msrs[i].data;
3116 break;
3117 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
3118 if (index & 1) {
fcc35e7c
DDAG		 3119 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
3120 mtrr_top_bits;
d1ae67f6
AW		 3121 } else {
3122 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
3123 }
3124 break;
a33a2cfe
PB		 3125 case MSR_IA32_SPEC_CTRL:
3126 env->spec_ctrl = msrs[i].data;
3127 break;
cfeea0c0
KRW		 3128 case MSR_VIRT_SSBD:
3129 env->virt_ssbd = msrs[i].data;
3130 break;
b77146e9
CP		 3131 case MSR_IA32_RTIT_CTL:
3132 env->msr_rtit_ctrl = msrs[i].data;
3133 break;
3134 case MSR_IA32_RTIT_STATUS:
3135 env->msr_rtit_status = msrs[i].data;
3136 break;
3137 case MSR_IA32_RTIT_OUTPUT_BASE:
3138 env->msr_rtit_output_base = msrs[i].data;
3139 break;
3140 case MSR_IA32_RTIT_OUTPUT_MASK:
3141 env->msr_rtit_output_mask = msrs[i].data;
3142 break;
3143 case MSR_IA32_RTIT_CR3_MATCH:
3144 env->msr_rtit_cr3_match = msrs[i].data;
3145 break;
3146 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
3147 env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] = msrs[i].data;
3148 break;
05330448
AL		 3149 }
3150 }
3151
3152 return 0;
3153}
3154
1bc22652 3155static int kvm_put_mp_state(X86CPU *cpu)
9bdbe550 3156{
1bc22652 3157 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
9bdbe550 3158
1bc22652 3159 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
9bdbe550
HB		 3160}
3161
23d02d9b 3162static int kvm_get_mp_state(X86CPU *cpu)
9bdbe550 3163{
259186a7 3164 CPUState *cs = CPU(cpu);
23d02d9b 3165 CPUX86State *env = &cpu->env;
9bdbe550
HB		 3166 struct kvm_mp_state mp_state;
3167 int ret;
3168
259186a7 3169 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
9bdbe550
HB		 3170 if (ret < 0) {
3171 return ret;
3172 }
3173 env->mp_state = mp_state.mp_state;
c14750e8 3174 if (kvm_irqchip_in_kernel()) {
259186a7 3175 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
c14750e8 3176 }
9bdbe550
HB		 3177 return 0;
3178}
3179
1bc22652 3180static int kvm_get_apic(X86CPU *cpu)
680c1c6f 3181{
02e51483 3182 DeviceState *apic = cpu->apic_state;
680c1c6f
JK		 3183 struct kvm_lapic_state kapic;
3184 int ret;
3185
3d4b2649 3186 if (apic && kvm_irqchip_in_kernel()) {
1bc22652 3187 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
680c1c6f
JK		 3188 if (ret < 0) {
3189 return ret;
3190 }
3191
3192 kvm_get_apic_state(apic, &kapic);
3193 }
3194 return 0;
3195}
3196
1bc22652 3197static int kvm_put_vcpu_events(X86CPU *cpu, int level)
a0fb002c 3198{
fc12d72e 3199 CPUState *cs = CPU(cpu);
1bc22652 3200 CPUX86State *env = &cpu->env;
076796f8 3201 struct kvm_vcpu_events events = {};
a0fb002c
JK		 3202
3203 if (!kvm_has_vcpu_events()) {
3204 return 0;
3205 }
3206
31827373
JK		 3207 events.exception.injected = (env->exception_injected >= 0);
3208 events.exception.nr = env->exception_injected;
a0fb002c
JK		 3209 events.exception.has_error_code = env->has_error_code;
3210 events.exception.error_code = env->error_code;
3211
3212 events.interrupt.injected = (env->interrupt_injected >= 0);
3213 events.interrupt.nr = env->interrupt_injected;
3214 events.interrupt.soft = env->soft_interrupt;
3215
3216 events.nmi.injected = env->nmi_injected;
3217 events.nmi.pending = env->nmi_pending;
3218 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
3219
3220 events.sipi_vector = env->sipi_vector;
68c6efe0 3221 events.flags = 0;
a0fb002c 3222
fc12d72e
PB		 3223 if (has_msr_smbase) {
3224 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
3225 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
3226 if (kvm_irqchip_in_kernel()) {
3227 /* As soon as these are moved to the kernel, remove them
3228 * from cs->interrupt_request.
3229 */
3230 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
3231 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
3232 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
3233 } else {
3234 /* Keep these in cs->interrupt_request. */
3235 events.smi.pending = 0;
3236 events.smi.latched_init = 0;
3237 }
fc3a1fd7
DDAG		 3238 /* Stop SMI delivery on old machine types to avoid a reboot
3239 * on an inward migration of an old VM.
3240 */
3241 if (!cpu->kvm_no_smi_migration) {
3242 events.flags |= KVM_VCPUEVENT_VALID_SMM;
3243 }
fc12d72e
PB		 3244 }
3245
ea643051 3246 if (level >= KVM_PUT_RESET_STATE) {
4fadfa00
PH		 3247 events.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING;
3248 if (env->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
3249 events.flags |= KVM_VCPUEVENT_VALID_SIPI_VECTOR;
3250 }
ea643051 3251 }
aee028b9 3252
1bc22652 3253 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
a0fb002c
JK		 3254}
3255
1bc22652 3256static int kvm_get_vcpu_events(X86CPU *cpu)
a0fb002c 3257{
1bc22652 3258 CPUX86State *env = &cpu->env;
a0fb002c
JK		 3259 struct kvm_vcpu_events events;
3260 int ret;
3261
3262 if (!kvm_has_vcpu_events()) {
3263 return 0;
3264 }
3265
fc12d72e 3266 memset(&events, 0, sizeof(events));
1bc22652 3267 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
a0fb002c
JK		 3268 if (ret < 0) {
3269 return ret;
3270 }
31827373 3271 env->exception_injected =
a0fb002c
JK		 3272 events.exception.injected ? events.exception.nr : -1;
3273 env->has_error_code = events.exception.has_error_code;
3274 env->error_code = events.exception.error_code;
3275
3276 env->interrupt_injected =
3277 events.interrupt.injected ? events.interrupt.nr : -1;
3278 env->soft_interrupt = events.interrupt.soft;
3279
3280 env->nmi_injected = events.nmi.injected;
3281 env->nmi_pending = events.nmi.pending;
3282 if (events.nmi.masked) {
3283 env->hflags2 |= HF2_NMI_MASK;
3284 } else {
3285 env->hflags2 &= ~HF2_NMI_MASK;
3286 }
3287
fc12d72e
PB		 3288 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
3289 if (events.smi.smm) {
3290 env->hflags |= HF_SMM_MASK;
3291 } else {
3292 env->hflags &= ~HF_SMM_MASK;
3293 }
3294 if (events.smi.pending) {
3295 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
3296 } else {
3297 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
3298 }
3299 if (events.smi.smm_inside_nmi) {
3300 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
3301 } else {
3302 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
3303 }
3304 if (events.smi.latched_init) {
3305 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
3306 } else {
3307 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
3308 }
3309 }
3310
a0fb002c 3311 env->sipi_vector = events.sipi_vector;
a0fb002c
JK		 3312
3313 return 0;
3314}
3315
1bc22652 3316static int kvm_guest_debug_workarounds(X86CPU *cpu)
b0b1d690 3317{
ed2803da 3318 CPUState *cs = CPU(cpu);
1bc22652 3319 CPUX86State *env = &cpu->env;
b0b1d690 3320 int ret = 0;
b0b1d690
JK		 3321 unsigned long reinject_trap = 0;
3322
3323 if (!kvm_has_vcpu_events()) {
3324 if (env->exception_injected == 1) {
3325 reinject_trap = KVM_GUESTDBG_INJECT_DB;
3326 } else if (env->exception_injected == 3) {
3327 reinject_trap = KVM_GUESTDBG_INJECT_BP;
3328 }
3329 env->exception_injected = -1;
3330 }
3331
3332 /*
3333 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
3334 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
3335 * by updating the debug state once again if single-stepping is on.
3336 * Another reason to call kvm_update_guest_debug here is a pending debug
3337 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
3338 * reinject them via SET_GUEST_DEBUG.
3339 */
3340 if (reinject_trap ||
ed2803da 3341 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
38e478ec 3342 ret = kvm_update_guest_debug(cs, reinject_trap);
b0b1d690 3343 }
b0b1d690
JK		 3344 return ret;
3345}
3346
1bc22652 3347static int kvm_put_debugregs(X86CPU *cpu)
ff44f1a3 3348{
1bc22652 3349 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 3350 struct kvm_debugregs dbgregs;
3351 int i;
3352
3353 if (!kvm_has_debugregs()) {
3354 return 0;
3355 }
3356
3357 for (i = 0; i < 4; i++) {
3358 dbgregs.db[i] = env->dr[i];
3359 }
3360 dbgregs.dr6 = env->dr[6];
3361 dbgregs.dr7 = env->dr[7];
3362 dbgregs.flags = 0;
3363
1bc22652 3364 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
ff44f1a3
JK		 3365}
3366
1bc22652 3367static int kvm_get_debugregs(X86CPU *cpu)
ff44f1a3 3368{
1bc22652 3369 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 3370 struct kvm_debugregs dbgregs;
3371 int i, ret;
3372
3373 if (!kvm_has_debugregs()) {
3374 return 0;
3375 }
3376
1bc22652 3377 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
ff44f1a3 3378 if (ret < 0) {
b9bec74b 3379 return ret;
ff44f1a3
JK		 3380 }
3381 for (i = 0; i < 4; i++) {
3382 env->dr[i] = dbgregs.db[i];
3383 }
3384 env->dr[4] = env->dr[6] = dbgregs.dr6;
3385 env->dr[5] = env->dr[7] = dbgregs.dr7;
ff44f1a3
JK		 3386
3387 return 0;
3388}
3389
20d695a9 3390int kvm_arch_put_registers(CPUState *cpu, int level)
05330448 3391{
20d695a9 3392 X86CPU *x86_cpu = X86_CPU(cpu);
05330448
AL		 3393 int ret;
3394
2fa45344 3395 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
dbaa07c4 3396
48e1a45c 3397 if (level >= KVM_PUT_RESET_STATE) {
6bdf863d
JK		 3398 ret = kvm_put_msr_feature_control(x86_cpu);
3399 if (ret < 0) {
3400 return ret;
3401 }
3402 }
3403
36f96c4b
HZ		 3404 if (level == KVM_PUT_FULL_STATE) {
3405 /* We don't check for kvm_arch_set_tsc_khz() errors here,
3406 * because TSC frequency mismatch shouldn't abort migration,
3407 * unless the user explicitly asked for a more strict TSC
3408 * setting (e.g. using an explicit "tsc-freq" option).
3409 */
3410 kvm_arch_set_tsc_khz(cpu);
3411 }
3412
1bc22652 3413 ret = kvm_getput_regs(x86_cpu, 1);
b9bec74b 3414 if (ret < 0) {
05330448 3415 return ret;
b9bec74b 3416 }
1bc22652 3417 ret = kvm_put_xsave(x86_cpu);
b9bec74b 3418 if (ret < 0) {
f1665b21 3419 return ret;
b9bec74b 3420 }
1bc22652 3421 ret = kvm_put_xcrs(x86_cpu);
b9bec74b 3422 if (ret < 0) {
05330448 3423 return ret;
b9bec74b 3424 }
1bc22652 3425 ret = kvm_put_sregs(x86_cpu);
b9bec74b 3426 if (ret < 0) {
05330448 3427 return ret;
b9bec74b 3428 }
ab443475 3429 /* must be before kvm_put_msrs */
1bc22652 3430 ret = kvm_inject_mce_oldstyle(x86_cpu);
ab443475
JK		 3431 if (ret < 0) {
3432 return ret;
3433 }
1bc22652 3434 ret = kvm_put_msrs(x86_cpu, level);
b9bec74b 3435 if (ret < 0) {
05330448 3436 return ret;
b9bec74b 3437 }
4fadfa00
PH		 3438 ret = kvm_put_vcpu_events(x86_cpu, level);
3439 if (ret < 0) {
3440 return ret;
3441 }
ea643051 3442 if (level >= KVM_PUT_RESET_STATE) {
1bc22652 3443 ret = kvm_put_mp_state(x86_cpu);
b9bec74b 3444 if (ret < 0) {
680c1c6f
JK		 3445 return ret;
3446 }
ea643051 3447 }
7477cd38
MT		 3448
3449 ret = kvm_put_tscdeadline_msr(x86_cpu);
3450 if (ret < 0) {
3451 return ret;
3452 }
1bc22652 3453 ret = kvm_put_debugregs(x86_cpu);
b9bec74b 3454 if (ret < 0) {
b0b1d690 3455 return ret;
b9bec74b 3456 }
b0b1d690 3457 /* must be last */
1bc22652 3458 ret = kvm_guest_debug_workarounds(x86_cpu);
b9bec74b 3459 if (ret < 0) {
ff44f1a3 3460 return ret;
b9bec74b 3461 }
05330448
AL		 3462 return 0;
3463}
3464
20d695a9 3465int kvm_arch_get_registers(CPUState *cs)
05330448 3466{
20d695a9 3467 X86CPU *cpu = X86_CPU(cs);
05330448
AL		 3468 int ret;
3469
20d695a9 3470 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
dbaa07c4 3471
4fadfa00 3472 ret = kvm_get_vcpu_events(cpu);
b9bec74b 3473 if (ret < 0) {
f4f1110e 3474 goto out;
b9bec74b 3475 }
4fadfa00
PH		 3476 /*
3477 * KVM_GET_MPSTATE can modify CS and RIP, call it before
3478 * KVM_GET_REGS and KVM_GET_SREGS.
3479 */
3480 ret = kvm_get_mp_state(cpu);
b9bec74b 3481 if (ret < 0) {
f4f1110e 3482 goto out;
b9bec74b 3483 }
4fadfa00 3484 ret = kvm_getput_regs(cpu, 0);
b9bec74b 3485 if (ret < 0) {
f4f1110e 3486 goto out;
b9bec74b 3487 }
4fadfa00 3488 ret = kvm_get_xsave(cpu);
b9bec74b 3489 if (ret < 0) {
f4f1110e 3490 goto out;
b9bec74b 3491 }
4fadfa00 3492 ret = kvm_get_xcrs(cpu);
b9bec74b 3493 if (ret < 0) {
f4f1110e 3494 goto out;
b9bec74b 3495 }
4fadfa00 3496 ret = kvm_get_sregs(cpu);
b9bec74b 3497 if (ret < 0) {
f4f1110e 3498 goto out;
b9bec74b 3499 }
4fadfa00 3500 ret = kvm_get_msrs(cpu);
680c1c6f 3501 if (ret < 0) {
f4f1110e 3502 goto out;
680c1c6f 3503 }
4fadfa00 3504 ret = kvm_get_apic(cpu);
b9bec74b 3505 if (ret < 0) {
f4f1110e 3506 goto out;
b9bec74b 3507 }
1bc22652 3508 ret = kvm_get_debugregs(cpu);
b9bec74b 3509 if (ret < 0) {
f4f1110e 3510 goto out;
b9bec74b 3511 }
f4f1110e
RH		 3512 ret = 0;
3513 out:
3514 cpu_sync_bndcs_hflags(&cpu->env);
3515 return ret;
05330448
AL		 3516}
3517
20d695a9 3518void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
05330448 3519{
20d695a9
AF		 3520 X86CPU *x86_cpu = X86_CPU(cpu);
3521 CPUX86State *env = &x86_cpu->env;
ce377af3
JK		 3522 int ret;
3523
276ce815 3524 /* Inject NMI */
fc12d72e
PB		 3525 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
3526 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
3527 qemu_mutex_lock_iothread();
3528 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
3529 qemu_mutex_unlock_iothread();
3530 DPRINTF("injected NMI\n");
3531 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
3532 if (ret < 0) {
3533 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
3534 strerror(-ret));
3535 }
3536 }
3537 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
3538 qemu_mutex_lock_iothread();
3539 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
3540 qemu_mutex_unlock_iothread();
3541 DPRINTF("injected SMI\n");
3542 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
3543 if (ret < 0) {
3544 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
3545 strerror(-ret));
3546 }
ce377af3 3547 }
276ce815
LJ		 3548 }
3549
15eafc2e 3550 if (!kvm_pic_in_kernel()) {
4b8523ee
JK		 3551 qemu_mutex_lock_iothread();
3552 }
3553
e0723c45
PB		 3554 /* Force the VCPU out of its inner loop to process any INIT requests
3555 * or (for userspace APIC, but it is cheap to combine the checks here)
3556 * pending TPR access reports.
3557 */
3558 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
fc12d72e
PB		 3559 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
3560 !(env->hflags & HF_SMM_MASK)) {
3561 cpu->exit_request = 1;
3562 }
3563 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
3564 cpu->exit_request = 1;
3565 }
e0723c45 3566 }
05330448 3567
15eafc2e 3568 if (!kvm_pic_in_kernel()) {
db1669bc
JK		 3569 /* Try to inject an interrupt if the guest can accept it */
3570 if (run->ready_for_interrupt_injection &&
259186a7 3571 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
db1669bc
JK		 3572 (env->eflags & IF_MASK)) {
3573 int irq;
3574
259186a7 3575 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
db1669bc
JK		 3576 irq = cpu_get_pic_interrupt(env);
3577 if (irq >= 0) {
3578 struct kvm_interrupt intr;
3579
3580 intr.irq = irq;
db1669bc 3581 DPRINTF("injected interrupt %d\n", irq);
1bc22652 3582 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
ce377af3
JK		 3583 if (ret < 0) {
3584 fprintf(stderr,
3585 "KVM: injection failed, interrupt lost (%s)\n",
3586 strerror(-ret));
3587 }
db1669bc
JK		 3588 }
3589 }
05330448 3590
db1669bc
JK		 3591 /* If we have an interrupt but the guest is not ready to receive an
3592 * interrupt, request an interrupt window exit. This will
3593 * cause a return to userspace as soon as the guest is ready to
3594 * receive interrupts. */
259186a7 3595 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
db1669bc
JK		 3596 run->request_interrupt_window = 1;
3597 } else {
3598 run->request_interrupt_window = 0;
3599 }
3600
3601 DPRINTF("setting tpr\n");
02e51483 3602 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
4b8523ee
JK		 3603
3604 qemu_mutex_unlock_iothread();
db1669bc 3605 }
05330448
AL		 3606}
3607
4c663752 3608MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
05330448 3609{
20d695a9
AF		 3610 X86CPU *x86_cpu = X86_CPU(cpu);
3611 CPUX86State *env = &x86_cpu->env;
3612
fc12d72e
PB		 3613 if (run->flags & KVM_RUN_X86_SMM) {
3614 env->hflags |= HF_SMM_MASK;
3615 } else {
f5c052b9 3616 env->hflags &= ~HF_SMM_MASK;
fc12d72e 3617 }
b9bec74b 3618 if (run->if_flag) {
05330448 3619 env->eflags |= IF_MASK;
b9bec74b 3620 } else {
05330448 3621 env->eflags &= ~IF_MASK;
b9bec74b 3622 }
4b8523ee
JK		 3623
3624 /* We need to protect the apic state against concurrent accesses from
3625 * different threads in case the userspace irqchip is used. */
3626 if (!kvm_irqchip_in_kernel()) {
3627 qemu_mutex_lock_iothread();
3628 }
02e51483
CF		 3629 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
3630 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
4b8523ee
JK		 3631 if (!kvm_irqchip_in_kernel()) {
3632 qemu_mutex_unlock_iothread();
3633 }
f794aa4a 3634 return cpu_get_mem_attrs(env);
05330448
AL		 3635}
3636
20d695a9 3637int kvm_arch_process_async_events(CPUState *cs)
0af691d7 3638{
20d695a9
AF		 3639 X86CPU *cpu = X86_CPU(cs);
3640 CPUX86State *env = &cpu->env;
232fc23b 3641
259186a7 3642 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
ab443475
JK		 3643 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
3644 assert(env->mcg_cap);
3645
259186a7 3646 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
ab443475 3647
dd1750d7 3648 kvm_cpu_synchronize_state(cs);
ab443475
JK		 3649
3650 if (env->exception_injected == EXCP08_DBLE) {
3651 /* this means triple fault */
cf83f140 3652 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
fcd7d003 3653 cs->exit_request = 1;
ab443475
JK		 3654 return 0;
3655 }
3656 env->exception_injected = EXCP12_MCHK;
3657 env->has_error_code = 0;
3658
259186a7 3659 cs->halted = 0;
ab443475
JK		 3660 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
3661 env->mp_state = KVM_MP_STATE_RUNNABLE;
3662 }
3663 }
3664
fc12d72e
PB		 3665 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
3666 !(env->hflags & HF_SMM_MASK)) {
e0723c45
PB		 3667 kvm_cpu_synchronize_state(cs);
3668 do_cpu_init(cpu);
3669 }
3670
db1669bc
JK		 3671 if (kvm_irqchip_in_kernel()) {
3672 return 0;
3673 }
3674
259186a7
AF		 3675 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
3676 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
02e51483 3677 apic_poll_irq(cpu->apic_state);
5d62c43a 3678 }
259186a7 3679 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
4601f7b0 3680 (env->eflags & IF_MASK)) ||
259186a7
AF		 3681 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
3682 cs->halted = 0;
6792a57b 3683 }
259186a7 3684 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
dd1750d7 3685 kvm_cpu_synchronize_state(cs);
232fc23b 3686 do_cpu_sipi(cpu);
0af691d7 3687 }
259186a7
AF		 3688 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
3689 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
dd1750d7 3690 kvm_cpu_synchronize_state(cs);
02e51483 3691 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
d362e757
JK		 3692 env->tpr_access_type);
3693 }
0af691d7 3694
259186a7 3695 return cs->halted;
0af691d7
MT		 3696}
3697
839b5630 3698static int kvm_handle_halt(X86CPU *cpu)
05330448 3699{
259186a7 3700 CPUState *cs = CPU(cpu);
839b5630
AF		 3701 CPUX86State *env = &cpu->env;
3702
259186a7 3703 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
05330448 3704 (env->eflags & IF_MASK)) &&
259186a7
AF		 3705 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
3706 cs->halted = 1;
bb4ea393 3707 return EXCP_HLT;
05330448
AL		 3708 }
3709
bb4ea393 3710 return 0;
05330448
AL		 3711}
3712
f7575c96 3713static int kvm_handle_tpr_access(X86CPU *cpu)
d362e757 3714{
f7575c96
AF		 3715 CPUState *cs = CPU(cpu);
3716 struct kvm_run *run = cs->kvm_run;
d362e757 3717
02e51483 3718 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
d362e757
JK		 3719 run->tpr_access.is_write ? TPR_ACCESS_WRITE
3720 : TPR_ACCESS_READ);
3721 return 1;
3722}
3723
f17ec444 3724int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9 3725{
38972938 3726 static const uint8_t int3 = 0xcc;
64bf3f4e 3727
f17ec444
AF		 3728 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
3729 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
e22a25c9 3730 return -EINVAL;
b9bec74b 3731 }
e22a25c9
AL		 3732 return 0;
3733}
3734
f17ec444 3735int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9
AL		 3736{
3737 uint8_t int3;
3738
f17ec444
AF		 3739 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
3740 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
e22a25c9 3741 return -EINVAL;
b9bec74b 3742 }
e22a25c9
AL		 3743 return 0;
3744}
3745
3746static struct {
3747 target_ulong addr;
3748 int len;
3749 int type;
3750} hw_breakpoint[4];
3751
3752static int nb_hw_breakpoint;
3753
3754static int find_hw_breakpoint(target_ulong addr, int len, int type)
3755{
3756 int n;
3757
b9bec74b 3758 for (n = 0; n < nb_hw_breakpoint; n++) {
e22a25c9 3759 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
b9bec74b 3760 (hw_breakpoint[n].len == len || len == -1)) {
e22a25c9 3761 return n;
b9bec74b
JK		 3762 }
3763 }
e22a25c9
AL		 3764 return -1;
3765}
3766
3767int kvm_arch_insert_hw_breakpoint(target_ulong addr,
3768 target_ulong len, int type)
3769{
3770 switch (type) {
3771 case GDB_BREAKPOINT_HW:
3772 len = 1;
3773 break;
3774 case GDB_WATCHPOINT_WRITE:
3775 case GDB_WATCHPOINT_ACCESS:
3776 switch (len) {
3777 case 1:
3778 break;
3779 case 2:
3780 case 4:
3781 case 8:
b9bec74b 3782 if (addr & (len - 1)) {
e22a25c9 3783 return -EINVAL;
b9bec74b 3784 }
e22a25c9
AL		 3785 break;
3786 default:
3787 return -EINVAL;
3788 }
3789 break;
3790 default:
3791 return -ENOSYS;
3792 }
3793
b9bec74b 3794 if (nb_hw_breakpoint == 4) {
e22a25c9 3795 return -ENOBUFS;
b9bec74b
JK		 3796 }
3797 if (find_hw_breakpoint(addr, len, type) >= 0) {
e22a25c9 3798 return -EEXIST;
b9bec74b 3799 }
e22a25c9
AL		 3800 hw_breakpoint[nb_hw_breakpoint].addr = addr;
3801 hw_breakpoint[nb_hw_breakpoint].len = len;
3802 hw_breakpoint[nb_hw_breakpoint].type = type;
3803 nb_hw_breakpoint++;
3804
3805 return 0;
3806}
3807
3808int kvm_arch_remove_hw_breakpoint(target_ulong addr,
3809 target_ulong len, int type)
3810{
3811 int n;
3812
3813 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
b9bec74b 3814 if (n < 0) {
e22a25c9 3815 return -ENOENT;
b9bec74b 3816 }
e22a25c9
AL		 3817 nb_hw_breakpoint--;
3818 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
3819
3820 return 0;
3821}
3822
3823void kvm_arch_remove_all_hw_breakpoints(void)
3824{
3825 nb_hw_breakpoint = 0;
3826}
3827
3828static CPUWatchpoint hw_watchpoint;
3829
a60f24b5 3830static int kvm_handle_debug(X86CPU *cpu,
48405526 3831 struct kvm_debug_exit_arch *arch_info)
e22a25c9 3832{
ed2803da 3833 CPUState *cs = CPU(cpu);
a60f24b5 3834 CPUX86State *env = &cpu->env;
f2574737 3835 int ret = 0;
e22a25c9
AL		 3836 int n;
3837
3838 if (arch_info->exception == 1) {
3839 if (arch_info->dr6 & (1 << 14)) {
ed2803da 3840 if (cs->singlestep_enabled) {
f2574737 3841 ret = EXCP_DEBUG;
b9bec74b 3842 }
e22a25c9 3843 } else {
b9bec74b
JK		 3844 for (n = 0; n < 4; n++) {
3845 if (arch_info->dr6 & (1 << n)) {
e22a25c9
AL		 3846 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
3847 case 0x0:
f2574737 3848 ret = EXCP_DEBUG;
e22a25c9
AL		 3849 break;
3850 case 0x1:
f2574737 3851 ret = EXCP_DEBUG;
ff4700b0 3852 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 3853 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3854 hw_watchpoint.flags = BP_MEM_WRITE;
3855 break;
3856 case 0x3:
f2574737 3857 ret = EXCP_DEBUG;
ff4700b0 3858 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 3859 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3860 hw_watchpoint.flags = BP_MEM_ACCESS;
3861 break;
3862 }
b9bec74b
JK		 3863 }
3864 }
e22a25c9 3865 }
ff4700b0 3866 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
f2574737 3867 ret = EXCP_DEBUG;
b9bec74b 3868 }
f2574737 3869 if (ret == 0) {
ff4700b0 3870 cpu_synchronize_state(cs);
48405526 3871 assert(env->exception_injected == -1);
b0b1d690 3872
f2574737 3873 /* pass to guest */
48405526
BS		 3874 env->exception_injected = arch_info->exception;
3875 env->has_error_code = 0;
b0b1d690 3876 }
e22a25c9 3877
f2574737 3878 return ret;
e22a25c9
AL		 3879}
3880
20d695a9 3881void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
e22a25c9
AL		 3882{
3883 const uint8_t type_code[] = {
3884 [GDB_BREAKPOINT_HW] = 0x0,
3885 [GDB_WATCHPOINT_WRITE] = 0x1,
3886 [GDB_WATCHPOINT_ACCESS] = 0x3
3887 };
3888 const uint8_t len_code[] = {
3889 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
3890 };
3891 int n;
3892
a60f24b5 3893 if (kvm_sw_breakpoints_active(cpu)) {
e22a25c9 3894 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
b9bec74b 3895 }
e22a25c9
AL		 3896 if (nb_hw_breakpoint > 0) {
3897 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
3898 dbg->arch.debugreg[7] = 0x0600;
3899 for (n = 0; n < nb_hw_breakpoint; n++) {
3900 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
3901 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
3902 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
95c077c9 3903 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
e22a25c9
AL		 3904 }
3905 }
3906}
4513d923 3907
2a4dac83
JK		 3908static bool host_supports_vmx(void)
3909{
3910 uint32_t ecx, unused;
3911
3912 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
3913 return ecx & CPUID_EXT_VMX;
3914}
3915
3916#define VMX_INVALID_GUEST_STATE 0x80000021
3917
20d695a9 3918int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2a4dac83 3919{
20d695a9 3920 X86CPU *cpu = X86_CPU(cs);
2a4dac83
JK		 3921 uint64_t code;
3922 int ret;
3923
3924 switch (run->exit_reason) {
3925 case KVM_EXIT_HLT:
3926 DPRINTF("handle_hlt\n");
4b8523ee 3927 qemu_mutex_lock_iothread();
839b5630 3928 ret = kvm_handle_halt(cpu);
4b8523ee 3929 qemu_mutex_unlock_iothread();
2a4dac83
JK		 3930 break;
3931 case KVM_EXIT_SET_TPR:
3932 ret = 0;
3933 break;
d362e757 3934 case KVM_EXIT_TPR_ACCESS:
4b8523ee 3935 qemu_mutex_lock_iothread();
f7575c96 3936 ret = kvm_handle_tpr_access(cpu);
4b8523ee 3937 qemu_mutex_unlock_iothread();
d362e757 3938 break;
2a4dac83
JK		 3939 case KVM_EXIT_FAIL_ENTRY:
3940 code = run->fail_entry.hardware_entry_failure_reason;
3941 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
3942 code);
3943 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
3944 fprintf(stderr,
12619721 3945 "\nIf you're running a guest on an Intel machine without "
2a4dac83
JK		 3946 "unrestricted mode\n"
3947 "support, the failure can be most likely due to the guest "
3948 "entering an invalid\n"
3949 "state for Intel VT. For example, the guest maybe running "
3950 "in big real mode\n"
3951 "which is not supported on less recent Intel processors."
3952 "\n\n");
3953 }
3954 ret = -1;
3955 break;
3956 case KVM_EXIT_EXCEPTION:
3957 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
3958 run->ex.exception, run->ex.error_code);
3959 ret = -1;
3960 break;
f2574737
JK		 3961 case KVM_EXIT_DEBUG:
3962 DPRINTF("kvm_exit_debug\n");
4b8523ee 3963 qemu_mutex_lock_iothread();
a60f24b5 3964 ret = kvm_handle_debug(cpu, &run->debug.arch);
4b8523ee 3965 qemu_mutex_unlock_iothread();
f2574737 3966 break;
50efe82c
AS		 3967 case KVM_EXIT_HYPERV:
3968 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
3969 break;
15eafc2e
PB		 3970 case KVM_EXIT_IOAPIC_EOI:
3971 ioapic_eoi_broadcast(run->eoi.vector);
3972 ret = 0;
3973 break;
2a4dac83
JK		 3974 default:
3975 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
3976 ret = -1;
3977 break;
3978 }
3979
3980 return ret;
3981}
3982
20d695a9 3983bool kvm_arch_stop_on_emulation_error(CPUState *cs)
4513d923 3984{
20d695a9
AF		 3985 X86CPU *cpu = X86_CPU(cs);
3986 CPUX86State *env = &cpu->env;
3987
dd1750d7 3988 kvm_cpu_synchronize_state(cs);
b9bec74b
JK		 3989 return !(env->cr[0] & CR0_PE_MASK) ||
3990 ((env->segs[R_CS].selector & 3) != 3);
4513d923 3991}
84b058d7
JK		 3992
3993void kvm_arch_init_irq_routing(KVMState *s)
3994{
3995 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
3996 /* If kernel can't do irq routing, interrupt source
3997 * override 0->2 cannot be set up as required by HPET.
3998 * So we have to disable it.
3999 */
4000 no_hpet = 1;
4001 }
cc7e0ddf 4002 /* We know at this point that we're using the in-kernel
614e41bc 4003 * irqchip, so we can use irqfds, and on x86 we know
f3e1bed8 4004 * we can use msi via irqfd and GSI routing.
cc7e0ddf 4005 */
614e41bc 4006 kvm_msi_via_irqfd_allowed = true;
f3e1bed8 4007 kvm_gsi_routing_allowed = true;
15eafc2e
PB		 4008
4009 if (kvm_irqchip_is_split()) {
4010 int i;
4011
4012 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
4013 MSI routes for signaling interrupts to the local apics. */
4014 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
d1f6af6a 4015 if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
15eafc2e
PB		 4016 error_report("Could not enable split IRQ mode.");
4017 exit(1);
4018 }
4019 }
4020 }
4021}
4022
4023int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
4024{
4025 int ret;
4026 if (machine_kernel_irqchip_split(ms)) {
4027 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
4028 if (ret) {
df3c286c 4029 error_report("Could not enable split irqchip mode: %s",
15eafc2e
PB		 4030 strerror(-ret));
4031 exit(1);
4032 } else {
4033 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
4034 kvm_split_irqchip = true;
4035 return 1;
4036 }
4037 } else {
4038 return 0;
4039 }
84b058d7 4040}
b139bd30
JK		 4041
4042/* Classic KVM device assignment interface. Will remain x86 only. */
4043int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
4044 uint32_t flags, uint32_t *dev_id)
4045{
4046 struct kvm_assigned_pci_dev dev_data = {
4047 .segnr = dev_addr->domain,
4048 .busnr = dev_addr->bus,
4049 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
4050 .flags = flags,
4051 };
4052 int ret;
4053
4054 dev_data.assigned_dev_id =
4055 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
4056
4057 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
4058 if (ret < 0) {
4059 return ret;
4060 }
4061
4062 *dev_id = dev_data.assigned_dev_id;
4063
4064 return 0;
4065}
4066
4067int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
4068{
4069 struct kvm_assigned_pci_dev dev_data = {
4070 .assigned_dev_id = dev_id,
4071 };
4072
4073 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
4074}
4075
4076static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
4077 uint32_t irq_type, uint32_t guest_irq)
4078{
4079 struct kvm_assigned_irq assigned_irq = {
4080 .assigned_dev_id = dev_id,
4081 .guest_irq = guest_irq,
4082 .flags = irq_type,
4083 };
4084
4085 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
4086 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
4087 } else {
4088 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
4089 }
4090}
4091
4092int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
4093 uint32_t guest_irq)
4094{
4095 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
4096 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
4097
4098 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
4099}
4100
4101int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
4102{
4103 struct kvm_assigned_pci_dev dev_data = {
4104 .assigned_dev_id = dev_id,
4105 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
4106 };
4107
4108 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
4109}
4110
4111static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
4112 uint32_t type)
4113{
4114 struct kvm_assigned_irq assigned_irq = {
4115 .assigned_dev_id = dev_id,
4116 .flags = type,
4117 };
4118
4119 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
4120}
4121
4122int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
4123{
4124 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
4125 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
4126}
4127
4128int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
4129{
4130 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
4131 KVM_DEV_IRQ_GUEST_MSI, virq);
4132}
4133
4134int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
4135{
4136 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
4137 KVM_DEV_IRQ_HOST_MSI);
4138}
4139
4140bool kvm_device_msix_supported(KVMState *s)
4141{
4142 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
4143 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
4144 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
4145}
4146
4147int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
4148 uint32_t nr_vectors)
4149{
4150 struct kvm_assigned_msix_nr msix_nr = {
4151 .assigned_dev_id = dev_id,
4152 .entry_nr = nr_vectors,
4153 };
4154
4155 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
4156}
4157
4158int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
4159 int virq)
4160{
4161 struct kvm_assigned_msix_entry msix_entry = {
4162 .assigned_dev_id = dev_id,
4163 .gsi = virq,
4164 .entry = vector,
4165 };
4166
4167 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
4168}
4169
4170int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
4171{
4172 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
4173 KVM_DEV_IRQ_GUEST_MSIX, 0);
4174}
4175
4176int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
4177{
4178 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
4179 KVM_DEV_IRQ_HOST_MSIX);
4180}
9e03a040
FB		 4181
4182int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
dc9f06ca 4183 uint64_t address, uint32_t data, PCIDevice *dev)
9e03a040 4184{
8b5ed7df
PX		 4185 X86IOMMUState *iommu = x86_iommu_get_default();
4186
4187 if (iommu) {
4188 int ret;
4189 MSIMessage src, dst;
4190 X86IOMMUClass *class = X86_IOMMU_GET_CLASS(iommu);
4191
0ea1472d
JK		 4192 if (!class->int_remap) {
4193 return 0;
4194 }
4195
8b5ed7df
PX		 4196 src.address = route->u.msi.address_hi;
4197 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
4198 src.address |= route->u.msi.address_lo;
4199 src.data = route->u.msi.data;
4200
4201 ret = class->int_remap(iommu, &src, &dst, dev ? \
4202 pci_requester_id(dev) : \
4203 X86_IOMMU_SID_INVALID);
4204 if (ret) {
4205 trace_kvm_x86_fixup_msi_error(route->gsi);
4206 return 1;
4207 }
4208
4209 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
4210 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
4211 route->u.msi.data = dst.data;
4212 }
4213
9e03a040
FB		 4214 return 0;
4215}
1850b6b7 4216
38d87493
PX		 4217typedef struct MSIRouteEntry MSIRouteEntry;
4218
4219struct MSIRouteEntry {
4220 PCIDevice *dev; /* Device pointer */
4221 int vector; /* MSI/MSIX vector index */
4222 int virq; /* Virtual IRQ index */
4223 QLIST_ENTRY(MSIRouteEntry) list;
4224};
4225
4226/* List of used GSI routes */
4227static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
4228 QLIST_HEAD_INITIALIZER(msi_route_list);
4229
e1d4fb2d
PX		 4230static void kvm_update_msi_routes_all(void *private, bool global,
4231 uint32_t index, uint32_t mask)
4232{
a56de056 4233 int cnt = 0, vector;
e1d4fb2d
PX		 4234 MSIRouteEntry *entry;
4235 MSIMessage msg;
fd563564
PX		 4236 PCIDevice *dev;
4237
e1d4fb2d
PX		 4238 /* TODO: explicit route update */
4239 QLIST_FOREACH(entry, &msi_route_list, list) {
4240 cnt++;
a56de056 4241 vector = entry->vector;
fd563564 4242 dev = entry->dev;
a56de056
PX		 4243 if (msix_enabled(dev) && !msix_is_masked(dev, vector)) {
4244 msg = msix_get_message(dev, vector);
4245 } else if (msi_enabled(dev) && !msi_is_masked(dev, vector)) {
4246 msg = msi_get_message(dev, vector);
4247 } else {
4248 /*
4249 * Either MSI/MSIX is disabled for the device, or the
4250 * specific message was masked out. Skip this one.
4251 */
fd563564
PX		 4252 continue;
4253 }
fd563564 4254 kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev);
e1d4fb2d 4255 }
3f1fea0f 4256 kvm_irqchip_commit_routes(kvm_state);
e1d4fb2d
PX		 4257 trace_kvm_x86_update_msi_routes(cnt);
4258}
4259
38d87493
PX		 4260int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
4261 int vector, PCIDevice *dev)
4262{
e1d4fb2d 4263 static bool notify_list_inited = false;
38d87493
PX		 4264 MSIRouteEntry *entry;
4265
4266 if (!dev) {
4267 /* These are (possibly) IOAPIC routes only used for split
4268 * kernel irqchip mode, while what we are housekeeping are
4269 * PCI devices only. */
4270 return 0;
4271 }
4272
4273 entry = g_new0(MSIRouteEntry, 1);
4274 entry->dev = dev;
4275 entry->vector = vector;
4276 entry->virq = route->gsi;
4277 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
4278
4279 trace_kvm_x86_add_msi_route(route->gsi);
e1d4fb2d
PX		 4280
4281 if (!notify_list_inited) {
4282 /* For the first time we do add route, add ourselves into
4283 * IOMMU's IEC notify list if needed. */
4284 X86IOMMUState *iommu = x86_iommu_get_default();
4285 if (iommu) {
4286 x86_iommu_iec_register_notifier(iommu,
4287 kvm_update_msi_routes_all,
4288 NULL);
4289 }
4290 notify_list_inited = true;
4291 }
38d87493
PX		 4292 return 0;
4293}
4294
4295int kvm_arch_release_virq_post(int virq)
4296{
4297 MSIRouteEntry *entry, *next;
4298 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
4299 if (entry->virq == virq) {
4300 trace_kvm_x86_remove_msi_route(virq);
4301 QLIST_REMOVE(entry, list);
01960e6d 4302 g_free(entry);
38d87493
PX		 4303 break;
4304 }
4305 }
9e03a040
FB		 4306 return 0;
4307}
1850b6b7
EA		 4308
4309int kvm_arch_msi_data_to_gsi(uint32_t data)
4310{
4311 abort();
4312}
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