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kvm-all: kvm_irqchip_create is not expected to fail
[qemu.git] / target-i386 / kvm.c
CommitLineData
05330448
AL		 1/*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <[email protected]>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15#include <sys/types.h>
16#include <sys/ioctl.h>
17#include <sys/mman.h>
25d2e361 18#include <sys/utsname.h>
05330448
AL		 19
20#include <linux/kvm.h>
5802e066 21#include <linux/kvm_para.h>
05330448
AL		 22
23#include "qemu-common.h"
9c17d615
PB		 24#include "sysemu/sysemu.h"
25#include "sysemu/kvm.h"
1d31f66b 26#include "kvm_i386.h"
05330448 27#include "cpu.h"
022c62cb 28#include "exec/gdbstub.h"
1de7afc9
PB		 29#include "qemu/host-utils.h"
30#include "qemu/config-file.h"
0d09e41a
PB		 31#include "hw/i386/pc.h"
32#include "hw/i386/apic.h"
e0723c45
PB		 33#include "hw/i386/apic_internal.h"
34#include "hw/i386/apic-msidef.h"
022c62cb 35#include "exec/ioport.h"
92067bf4 36#include <asm/hyperv.h>
a2cb15b0 37#include "hw/pci/pci.h"
68bfd0ad 38#include "migration/migration.h"
4c663752 39#include "exec/memattrs.h"
05330448
AL		 40
41//#define DEBUG_KVM
42
43#ifdef DEBUG_KVM
8c0d577e 44#define DPRINTF(fmt, ...) \
05330448
AL		 45 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
46#else
8c0d577e 47#define DPRINTF(fmt, ...) \
05330448
AL		 48 do { } while (0)
49#endif
50
1a03675d
GC		 51#define MSR_KVM_WALL_CLOCK 0x11
52#define MSR_KVM_SYSTEM_TIME 0x12
53
c0532a76
MT		 54#ifndef BUS_MCEERR_AR
55#define BUS_MCEERR_AR 4
56#endif
57#ifndef BUS_MCEERR_AO
58#define BUS_MCEERR_AO 5
59#endif
60
94a8d39a
JK		 61const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
62 KVM_CAP_INFO(SET_TSS_ADDR),
63 KVM_CAP_INFO(EXT_CPUID),
64 KVM_CAP_INFO(MP_STATE),
65 KVM_CAP_LAST_INFO
66};
25d2e361 67
c3a3a7d3
JK		 68static bool has_msr_star;
69static bool has_msr_hsave_pa;
f28558d3 70static bool has_msr_tsc_adjust;
aa82ba54 71static bool has_msr_tsc_deadline;
df67696e 72static bool has_msr_feature_control;
c5999bfc 73static bool has_msr_async_pf_en;
bc9a839d 74static bool has_msr_pv_eoi_en;
21e87c46 75static bool has_msr_misc_enable;
fc12d72e 76static bool has_msr_smbase;
79e9ebeb 77static bool has_msr_bndcfgs;
917367aa 78static bool has_msr_kvm_steal_time;
25d2e361 79static int lm_capable_kernel;
7bc3d711
PB		 80static bool has_msr_hv_hypercall;
81static bool has_msr_hv_vapic;
48a5f3bc 82static bool has_msr_hv_tsc;
d1ae67f6 83static bool has_msr_mtrr;
18cd2c17 84static bool has_msr_xss;
b827df58 85
0d894367
PB		 86static bool has_msr_architectural_pmu;
87static uint32_t num_architectural_pmu_counters;
88
1d31f66b
PM		 89bool kvm_allows_irq0_override(void)
90{
91 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
92}
93
b827df58
AK		 94static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
95{
96 struct kvm_cpuid2 *cpuid;
97 int r, size;
98
99 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
e42a92ae 100 cpuid = g_malloc0(size);
b827df58
AK		 101 cpuid->nent = max;
102 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
76ae317f
MM		 103 if (r == 0 && cpuid->nent >= max) {
104 r = -E2BIG;
105 }
b827df58
AK		 106 if (r < 0) {
107 if (r == -E2BIG) {
7267c094 108 g_free(cpuid);
b827df58
AK		 109 return NULL;
110 } else {
111 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
112 strerror(-r));
113 exit(1);
114 }
115 }
116 return cpuid;
117}
118
dd87f8a6
EH		 119/* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
120 * for all entries.
121 */
122static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
123{
124 struct kvm_cpuid2 *cpuid;
125 int max = 1;
126 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
127 max *= 2;
128 }
129 return cpuid;
130}
131
a443bc34 132static const struct kvm_para_features {
0c31b744
GC		 133 int cap;
134 int feature;
135} para_features[] = {
136 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
137 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
138 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
0c31b744 139 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
0c31b744
GC		 140};
141
ba9bc59e 142static int get_para_features(KVMState *s)
0c31b744
GC		 143{
144 int i, features = 0;
145
8e03c100 146 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
ba9bc59e 147 if (kvm_check_extension(s, para_features[i].cap)) {
0c31b744
GC		 148 features |= (1 << para_features[i].feature);
149 }
150 }
151
152 return features;
153}
0c31b744
GC		 154
155
829ae2f9
EH		 156/* Returns the value for a specific register on the cpuid entry
157 */
158static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
159{
160 uint32_t ret = 0;
161 switch (reg) {
162 case R_EAX:
163 ret = entry->eax;
164 break;
165 case R_EBX:
166 ret = entry->ebx;
167 break;
168 case R_ECX:
169 ret = entry->ecx;
170 break;
171 case R_EDX:
172 ret = entry->edx;
173 break;
174 }
175 return ret;
176}
177
4fb73f1d
EH		 178/* Find matching entry for function/index on kvm_cpuid2 struct
179 */
180static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
181 uint32_t function,
182 uint32_t index)
183{
184 int i;
185 for (i = 0; i < cpuid->nent; ++i) {
186 if (cpuid->entries[i].function == function &&
187 cpuid->entries[i].index == index) {
188 return &cpuid->entries[i];
189 }
190 }
191 /* not found: */
192 return NULL;
193}
194
ba9bc59e 195uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
c958a8bd 196 uint32_t index, int reg)
b827df58
AK		 197{
198 struct kvm_cpuid2 *cpuid;
b827df58
AK		 199 uint32_t ret = 0;
200 uint32_t cpuid_1_edx;
8c723b79 201 bool found = false;
b827df58 202
dd87f8a6 203 cpuid = get_supported_cpuid(s);
b827df58 204
4fb73f1d
EH		 205 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
206 if (entry) {
207 found = true;
208 ret = cpuid_entry_get_reg(entry, reg);
b827df58
AK		 209 }
210
7b46e5ce
EH		 211 /* Fixups for the data returned by KVM, below */
212
c2acb022
EH		 213 if (function == 1 && reg == R_EDX) {
214 /* KVM before 2.6.30 misreports the following features */
215 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
84bd945c
EH		 216 } else if (function == 1 && reg == R_ECX) {
217 /* We can set the hypervisor flag, even if KVM does not return it on
218 * GET_SUPPORTED_CPUID
219 */
220 ret |= CPUID_EXT_HYPERVISOR;
ac67ee26
EH		 221 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
222 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
223 * and the irqchip is in the kernel.
224 */
225 if (kvm_irqchip_in_kernel() &&
226 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
227 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
228 }
41e5e76d
EH		 229
230 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
231 * without the in-kernel irqchip
232 */
233 if (!kvm_irqchip_in_kernel()) {
234 ret &= ~CPUID_EXT_X2APIC;
b827df58 235 }
c2acb022
EH		 236 } else if (function == 0x80000001 && reg == R_EDX) {
237 /* On Intel, kvm returns cpuid according to the Intel spec,
238 * so add missing bits according to the AMD spec:
239 */
240 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
241 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
b827df58
AK		 242 }
243
7267c094 244 g_free(cpuid);
b827df58 245
0c31b744 246 /* fallback for older kernels */
8c723b79 247 if ((function == KVM_CPUID_FEATURES) && !found) {
ba9bc59e 248 ret = get_para_features(s);
b9bec74b 249 }
0c31b744
GC		 250
251 return ret;
bb0300dc 252}
bb0300dc 253
3c85e74f
HY		 254typedef struct HWPoisonPage {
255 ram_addr_t ram_addr;
256 QLIST_ENTRY(HWPoisonPage) list;
257} HWPoisonPage;
258
259static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
260 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
261
262static void kvm_unpoison_all(void *param)
263{
264 HWPoisonPage *page, *next_page;
265
266 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
267 QLIST_REMOVE(page, list);
268 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
7267c094 269 g_free(page);
3c85e74f
HY		 270 }
271}
272
3c85e74f
HY		 273static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
274{
275 HWPoisonPage *page;
276
277 QLIST_FOREACH(page, &hwpoison_page_list, list) {
278 if (page->ram_addr == ram_addr) {
279 return;
280 }
281 }
ab3ad07f 282 page = g_new(HWPoisonPage, 1);
3c85e74f
HY		 283 page->ram_addr = ram_addr;
284 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
285}
286
e7701825
MT		 287static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
288 int *max_banks)
289{
290 int r;
291
14a09518 292 r = kvm_check_extension(s, KVM_CAP_MCE);
e7701825
MT		 293 if (r > 0) {
294 *max_banks = r;
295 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
296 }
297 return -ENOSYS;
298}
299
bee615d4 300static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
e7701825 301{
bee615d4 302 CPUX86State *env = &cpu->env;
c34d440a
JK		 303 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
304 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
305 uint64_t mcg_status = MCG_STATUS_MCIP;
e7701825 306
c34d440a
JK		 307 if (code == BUS_MCEERR_AR) {
308 status |= MCI_STATUS_AR | 0x134;
309 mcg_status |= MCG_STATUS_EIPV;
310 } else {
311 status |= 0xc0;
312 mcg_status |= MCG_STATUS_RIPV;
419fb20a 313 }
8c5cf3b6 314 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
c34d440a
JK		 315 (MCM_ADDR_PHYS << 6) | 0xc,
316 cpu_x86_support_mca_broadcast(env) ?
317 MCE_INJECT_BROADCAST : 0);
419fb20a 318}
419fb20a
JK		 319
320static void hardware_memory_error(void)
321{
322 fprintf(stderr, "Hardware memory error!\n");
323 exit(1);
324}
325
20d695a9 326int kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
419fb20a 327{
20d695a9
AF		 328 X86CPU *cpu = X86_CPU(c);
329 CPUX86State *env = &cpu->env;
419fb20a 330 ram_addr_t ram_addr;
a8170e5e 331 hwaddr paddr;
419fb20a
JK		 332
333 if ((env->mcg_cap & MCG_SER_P) && addr
c34d440a 334 && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
1b5ec234 335 if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL ||
a60f24b5 336 !kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
419fb20a
JK		 337 fprintf(stderr, "Hardware memory error for memory used by "
338 "QEMU itself instead of guest system!\n");
339 /* Hope we are lucky for AO MCE */
340 if (code == BUS_MCEERR_AO) {
341 return 0;
342 } else {
343 hardware_memory_error();
344 }
345 }
3c85e74f 346 kvm_hwpoison_page_add(ram_addr);
bee615d4 347 kvm_mce_inject(cpu, paddr, code);
e56ff191 348 } else {
419fb20a
JK		 349 if (code == BUS_MCEERR_AO) {
350 return 0;
351 } else if (code == BUS_MCEERR_AR) {
352 hardware_memory_error();
353 } else {
354 return 1;
355 }
356 }
357 return 0;
358}
359
360int kvm_arch_on_sigbus(int code, void *addr)
361{
182735ef
AF		 362 X86CPU *cpu = X86_CPU(first_cpu);
363
364 if ((cpu->env.mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
419fb20a 365 ram_addr_t ram_addr;
a8170e5e 366 hwaddr paddr;
419fb20a
JK		 367
368 /* Hope we are lucky for AO MCE */
1b5ec234 369 if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL ||
182735ef 370 !kvm_physical_memory_addr_from_host(first_cpu->kvm_state,
a60f24b5 371 addr, &paddr)) {
419fb20a
JK		 372 fprintf(stderr, "Hardware memory error for memory used by "
373 "QEMU itself instead of guest system!: %p\n", addr);
374 return 0;
375 }
3c85e74f 376 kvm_hwpoison_page_add(ram_addr);
182735ef 377 kvm_mce_inject(X86_CPU(first_cpu), paddr, code);
e56ff191 378 } else {
419fb20a
JK		 379 if (code == BUS_MCEERR_AO) {
380 return 0;
381 } else if (code == BUS_MCEERR_AR) {
382 hardware_memory_error();
383 } else {
384 return 1;
385 }
386 }
387 return 0;
388}
e7701825 389
1bc22652 390static int kvm_inject_mce_oldstyle(X86CPU *cpu)
ab443475 391{
1bc22652
AF		 392 CPUX86State *env = &cpu->env;
393
ab443475
JK		 394 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
395 unsigned int bank, bank_num = env->mcg_cap & 0xff;
396 struct kvm_x86_mce mce;
397
398 env->exception_injected = -1;
399
400 /*
401 * There must be at least one bank in use if an MCE is pending.
402 * Find it and use its values for the event injection.
403 */
404 for (bank = 0; bank < bank_num; bank++) {
405 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
406 break;
407 }
408 }
409 assert(bank < bank_num);
410
411 mce.bank = bank;
412 mce.status = env->mce_banks[bank * 4 + 1];
413 mce.mcg_status = env->mcg_status;
414 mce.addr = env->mce_banks[bank * 4 + 2];
415 mce.misc = env->mce_banks[bank * 4 + 3];
416
1bc22652 417 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
ab443475 418 }
ab443475
JK		 419 return 0;
420}
421
1dfb4dd9 422static void cpu_update_state(void *opaque, int running, RunState state)
b8cc45d6 423{
317ac620 424 CPUX86State *env = opaque;
b8cc45d6
GC		 425
426 if (running) {
427 env->tsc_valid = false;
428 }
429}
430
83b17af5 431unsigned long kvm_arch_vcpu_id(CPUState *cs)
b164e48e 432{
83b17af5 433 X86CPU *cpu = X86_CPU(cs);
7e72a45c 434 return cpu->apic_id;
b164e48e
EH		 435}
436
92067bf4
IM		 437#ifndef KVM_CPUID_SIGNATURE_NEXT
438#define KVM_CPUID_SIGNATURE_NEXT 0x40000100
439#endif
440
441static bool hyperv_hypercall_available(X86CPU *cpu)
442{
443 return cpu->hyperv_vapic ||
444 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
445}
446
447static bool hyperv_enabled(X86CPU *cpu)
448{
7bc3d711
PB		 449 CPUState *cs = CPU(cpu);
450 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
451 (hyperv_hypercall_available(cpu) ||
48a5f3bc 452 cpu->hyperv_time ||
7bc3d711 453 cpu->hyperv_relaxed_timing);
92067bf4
IM		 454}
455
68bfd0ad
MT		 456static Error *invtsc_mig_blocker;
457
f8bb0565 458#define KVM_MAX_CPUID_ENTRIES 100
0893d460 459
20d695a9 460int kvm_arch_init_vcpu(CPUState *cs)
05330448
AL		 461{
462 struct {
486bd5a2 463 struct kvm_cpuid2 cpuid;
f8bb0565 464 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
541dc0d4 465 } QEMU_PACKED cpuid_data;
20d695a9
AF		 466 X86CPU *cpu = X86_CPU(cs);
467 CPUX86State *env = &cpu->env;
486bd5a2 468 uint32_t limit, i, j, cpuid_i;
a33609ca 469 uint32_t unused;
bb0300dc 470 struct kvm_cpuid_entry2 *c;
bb0300dc 471 uint32_t signature[3];
234cc647 472 int kvm_base = KVM_CPUID_SIGNATURE;
e7429073 473 int r;
05330448 474
ef4cbe14
SW		 475 memset(&cpuid_data, 0, sizeof(cpuid_data));
476
05330448
AL		 477 cpuid_i = 0;
478
bb0300dc 479 /* Paravirtualization CPUIDs */
234cc647
PB		 480 if (hyperv_enabled(cpu)) {
481 c = &cpuid_data.entries[cpuid_i++];
482 c->function = HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
eab70139
VR		 483 memcpy(signature, "Microsoft Hv", 12);
484 c->eax = HYPERV_CPUID_MIN;
234cc647
PB		 485 c->ebx = signature[0];
486 c->ecx = signature[1];
487 c->edx = signature[2];
0c31b744 488
234cc647
PB		 489 c = &cpuid_data.entries[cpuid_i++];
490 c->function = HYPERV_CPUID_INTERFACE;
eab70139
VR		 491 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
492 c->eax = signature[0];
234cc647
PB		 493 c->ebx = 0;
494 c->ecx = 0;
495 c->edx = 0;
eab70139
VR		 496
497 c = &cpuid_data.entries[cpuid_i++];
eab70139
VR		 498 c->function = HYPERV_CPUID_VERSION;
499 c->eax = 0x00001bbc;
500 c->ebx = 0x00060001;
501
502 c = &cpuid_data.entries[cpuid_i++];
eab70139 503 c->function = HYPERV_CPUID_FEATURES;
92067bf4 504 if (cpu->hyperv_relaxed_timing) {
eab70139
VR		 505 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
506 }
92067bf4 507 if (cpu->hyperv_vapic) {
eab70139
VR		 508 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
509 c->eax |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
7bc3d711 510 has_msr_hv_vapic = true;
eab70139 511 }
48a5f3bc
VR		 512 if (cpu->hyperv_time &&
513 kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) {
514 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
515 c->eax |= HV_X64_MSR_TIME_REF_COUNT_AVAILABLE;
516 c->eax |= 0x200;
517 has_msr_hv_tsc = true;
518 }
eab70139 519 c = &cpuid_data.entries[cpuid_i++];
eab70139 520 c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
92067bf4 521 if (cpu->hyperv_relaxed_timing) {
eab70139
VR		 522 c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
523 }
7bc3d711 524 if (has_msr_hv_vapic) {
eab70139
VR		 525 c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
526 }
92067bf4 527 c->ebx = cpu->hyperv_spinlock_attempts;
eab70139
VR		 528
529 c = &cpuid_data.entries[cpuid_i++];
eab70139
VR		 530 c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
531 c->eax = 0x40;
532 c->ebx = 0x40;
533
234cc647 534 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
7bc3d711 535 has_msr_hv_hypercall = true;
eab70139
VR		 536 }
537
f522d2ac
AW		 538 if (cpu->expose_kvm) {
539 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
540 c = &cpuid_data.entries[cpuid_i++];
541 c->function = KVM_CPUID_SIGNATURE | kvm_base;
79b6f2f6 542 c->eax = KVM_CPUID_FEATURES | kvm_base;
f522d2ac
AW		 543 c->ebx = signature[0];
544 c->ecx = signature[1];
545 c->edx = signature[2];
234cc647 546
f522d2ac
AW		 547 c = &cpuid_data.entries[cpuid_i++];
548 c->function = KVM_CPUID_FEATURES | kvm_base;
549 c->eax = env->features[FEAT_KVM];
234cc647 550
f522d2ac 551 has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF);
bb0300dc 552
f522d2ac 553 has_msr_pv_eoi_en = c->eax & (1 << KVM_FEATURE_PV_EOI);
bc9a839d 554
f522d2ac
AW		 555 has_msr_kvm_steal_time = c->eax & (1 << KVM_FEATURE_STEAL_TIME);
556 }
917367aa 557
a33609ca 558 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
05330448
AL		 559
560 for (i = 0; i <= limit; i++) {
f8bb0565
IM		 561 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
562 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
563 abort();
564 }
bb0300dc 565 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 566
567 switch (i) {
a36b1029
AL		 568 case 2: {
569 /* Keep reading function 2 till all the input is received */
570 int times;
571
a36b1029 572 c->function = i;
a33609ca
AL		 573 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
574 KVM_CPUID_FLAG_STATE_READ_NEXT;
575 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
576 times = c->eax & 0xff;
a36b1029
AL		 577
578 for (j = 1; j < times; ++j) {
f8bb0565
IM		 579 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
580 fprintf(stderr, "cpuid_data is full, no space for "
581 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
582 abort();
583 }
a33609ca 584 c = &cpuid_data.entries[cpuid_i++];
a36b1029 585 c->function = i;
a33609ca
AL		 586 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
587 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
a36b1029
AL		 588 }
589 break;
590 }
486bd5a2
AL		 591 case 4:
592 case 0xb:
593 case 0xd:
594 for (j = 0; ; j++) {
31e8c696
AP		 595 if (i == 0xd && j == 64) {
596 break;
597 }
486bd5a2
AL		 598 c->function = i;
599 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
600 c->index = j;
a33609ca 601 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2 602
b9bec74b 603 if (i == 4 && c->eax == 0) {
486bd5a2 604 break;
b9bec74b
JK		 605 }
606 if (i == 0xb && !(c->ecx & 0xff00)) {
486bd5a2 607 break;
b9bec74b
JK		 608 }
609 if (i == 0xd && c->eax == 0) {
31e8c696 610 continue;
b9bec74b 611 }
f8bb0565
IM		 612 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
613 fprintf(stderr, "cpuid_data is full, no space for "
614 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
615 abort();
616 }
a33609ca 617 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 618 }
619 break;
620 default:
486bd5a2 621 c->function = i;
a33609ca
AL		 622 c->flags = 0;
623 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2
AL		 624 break;
625 }
05330448 626 }
0d894367
PB		 627
628 if (limit >= 0x0a) {
629 uint32_t ver;
630
631 cpu_x86_cpuid(env, 0x0a, 0, &ver, &unused, &unused, &unused);
632 if ((ver & 0xff) > 0) {
633 has_msr_architectural_pmu = true;
634 num_architectural_pmu_counters = (ver & 0xff00) >> 8;
635
636 /* Shouldn't be more than 32, since that's the number of bits
637 * available in EBX to tell us _which_ counters are available.
638 * Play it safe.
639 */
640 if (num_architectural_pmu_counters > MAX_GP_COUNTERS) {
641 num_architectural_pmu_counters = MAX_GP_COUNTERS;
642 }
643 }
644 }
645
a33609ca 646 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
05330448
AL		 647
648 for (i = 0x80000000; i <= limit; i++) {
f8bb0565
IM		 649 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
650 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
651 abort();
652 }
bb0300dc 653 c = &cpuid_data.entries[cpuid_i++];
05330448 654
05330448 655 c->function = i;
a33609ca
AL		 656 c->flags = 0;
657 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
05330448
AL		 658 }
659
b3baa152
BW		 660 /* Call Centaur's CPUID instructions they are supported. */
661 if (env->cpuid_xlevel2 > 0) {
b3baa152
BW		 662 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
663
664 for (i = 0xC0000000; i <= limit; i++) {
f8bb0565
IM		 665 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
666 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
667 abort();
668 }
b3baa152
BW		 669 c = &cpuid_data.entries[cpuid_i++];
670
671 c->function = i;
672 c->flags = 0;
673 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
674 }
675 }
676
05330448
AL		 677 cpuid_data.cpuid.nent = cpuid_i;
678
e7701825 679 if (((env->cpuid_version >> 8)&0xF) >= 6
0514ef2f 680 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
fc7a504c 681 (CPUID_MCE | CPUID_MCA)
a60f24b5 682 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
e7701825
MT		 683 uint64_t mcg_cap;
684 int banks;
32a42024 685 int ret;
e7701825 686
a60f24b5 687 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
75d49497
JK		 688 if (ret < 0) {
689 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
690 return ret;
e7701825 691 }
75d49497
JK		 692
693 if (banks > MCE_BANKS_DEF) {
694 banks = MCE_BANKS_DEF;
695 }
696 mcg_cap &= MCE_CAP_DEF;
697 mcg_cap |= banks;
1bc22652 698 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &mcg_cap);
75d49497
JK		 699 if (ret < 0) {
700 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
701 return ret;
702 }
703
704 env->mcg_cap = mcg_cap;
e7701825 705 }
e7701825 706
b8cc45d6
GC		 707 qemu_add_vm_change_state_handler(cpu_update_state, env);
708
df67696e
LJ		 709 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
710 if (c) {
711 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
712 !!(c->ecx & CPUID_EXT_SMX);
713 }
714
68bfd0ad
MT		 715 c = cpuid_find_entry(&cpuid_data.cpuid, 0x80000007, 0);
716 if (c && (c->edx & 1<<8) && invtsc_mig_blocker == NULL) {
717 /* for migration */
718 error_setg(&invtsc_mig_blocker,
719 "State blocked by non-migratable CPU device"
720 " (invtsc flag)");
721 migrate_add_blocker(invtsc_mig_blocker);
722 /* for savevm */
723 vmstate_x86_cpu.unmigratable = 1;
724 }
725
7e680753 726 cpuid_data.cpuid.padding = 0;
1bc22652 727 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
fdc9c41a
JK		 728 if (r) {
729 return r;
730 }
e7429073 731
a60f24b5 732 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL);
e7429073 733 if (r && env->tsc_khz) {
1bc22652 734 r = kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz);
e7429073
JR		 735 if (r < 0) {
736 fprintf(stderr, "KVM_SET_TSC_KHZ failed\n");
737 return r;
738 }
739 }
e7429073 740
fabacc0f
JK		 741 if (kvm_has_xsave()) {
742 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
743 }
744
d1ae67f6
AW		 745 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
746 has_msr_mtrr = true;
747 }
748
e7429073 749 return 0;
05330448
AL		 750}
751
50a2c6e5 752void kvm_arch_reset_vcpu(X86CPU *cpu)
caa5af0f 753{
20d695a9 754 CPUX86State *env = &cpu->env;
dd673288 755
e73223a5 756 env->exception_injected = -1;
0e607a80 757 env->interrupt_injected = -1;
1a5e9d2f 758 env->xcr0 = 1;
ddced198 759 if (kvm_irqchip_in_kernel()) {
dd673288 760 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
ddced198
MT		 761 KVM_MP_STATE_UNINITIALIZED;
762 } else {
763 env->mp_state = KVM_MP_STATE_RUNNABLE;
764 }
caa5af0f
JK		 765}
766
e0723c45
PB		 767void kvm_arch_do_init_vcpu(X86CPU *cpu)
768{
769 CPUX86State *env = &cpu->env;
770
771 /* APs get directly into wait-for-SIPI state. */
772 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
773 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
774 }
775}
776
c3a3a7d3 777static int kvm_get_supported_msrs(KVMState *s)
05330448 778{
75b10c43 779 static int kvm_supported_msrs;
c3a3a7d3 780 int ret = 0;
05330448
AL		 781
782 /* first time */
75b10c43 783 if (kvm_supported_msrs == 0) {
05330448
AL		 784 struct kvm_msr_list msr_list, *kvm_msr_list;
785
75b10c43 786 kvm_supported_msrs = -1;
05330448
AL		 787
788 /* Obtain MSR list from KVM. These are the MSRs that we must
789 * save/restore */
4c9f7372 790 msr_list.nmsrs = 0;
c3a3a7d3 791 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
6fb6d245 792 if (ret < 0 && ret != -E2BIG) {
c3a3a7d3 793 return ret;
6fb6d245 794 }
d9db889f
JK		 795 /* Old kernel modules had a bug and could write beyond the provided
796 memory. Allocate at least a safe amount of 1K. */
7267c094 797 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
d9db889f
JK		 798 msr_list.nmsrs *
799 sizeof(msr_list.indices[0])));
05330448 800
55308450 801 kvm_msr_list->nmsrs = msr_list.nmsrs;
c3a3a7d3 802 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
05330448
AL		 803 if (ret >= 0) {
804 int i;
805
806 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
807 if (kvm_msr_list->indices[i] == MSR_STAR) {
c3a3a7d3 808 has_msr_star = true;
75b10c43
MT		 809 continue;
810 }
811 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
c3a3a7d3 812 has_msr_hsave_pa = true;
75b10c43 813 continue;
05330448 814 }
f28558d3
WA		 815 if (kvm_msr_list->indices[i] == MSR_TSC_ADJUST) {
816 has_msr_tsc_adjust = true;
817 continue;
818 }
aa82ba54
LJ		 819 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
820 has_msr_tsc_deadline = true;
821 continue;
822 }
fc12d72e
PB		 823 if (kvm_msr_list->indices[i] == MSR_IA32_SMBASE) {
824 has_msr_smbase = true;
825 continue;
826 }
21e87c46
AK		 827 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
828 has_msr_misc_enable = true;
829 continue;
830 }
79e9ebeb
LJ		 831 if (kvm_msr_list->indices[i] == MSR_IA32_BNDCFGS) {
832 has_msr_bndcfgs = true;
833 continue;
834 }
18cd2c17
WL		 835 if (kvm_msr_list->indices[i] == MSR_IA32_XSS) {
836 has_msr_xss = true;
837 continue;
838 }
05330448
AL		 839 }
840 }
841
7267c094 842 g_free(kvm_msr_list);
05330448
AL		 843 }
844
c3a3a7d3 845 return ret;
05330448
AL		 846}
847
b16565b3 848int kvm_arch_init(MachineState *ms, KVMState *s)
20420430 849{
11076198 850 uint64_t identity_base = 0xfffbc000;
39d6960a 851 uint64_t shadow_mem;
20420430 852 int ret;
25d2e361 853 struct utsname utsname;
20420430 854
c3a3a7d3 855 ret = kvm_get_supported_msrs(s);
20420430 856 if (ret < 0) {
20420430
SY		 857 return ret;
858 }
25d2e361
MT		 859
860 uname(&utsname);
861 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
862
4c5b10b7 863 /*
11076198
JK		 864 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
865 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
866 * Since these must be part of guest physical memory, we need to allocate
867 * them, both by setting their start addresses in the kernel and by
868 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
869 *
870 * Older KVM versions may not support setting the identity map base. In
871 * that case we need to stick with the default, i.e. a 256K maximum BIOS
872 * size.
4c5b10b7 873 */
11076198
JK		 874 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
875 /* Allows up to 16M BIOSes. */
876 identity_base = 0xfeffc000;
877
878 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
879 if (ret < 0) {
880 return ret;
881 }
4c5b10b7 882 }
e56ff191 883
11076198
JK		 884 /* Set TSS base one page after EPT identity map. */
885 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
20420430
SY		 886 if (ret < 0) {
887 return ret;
888 }
889
11076198
JK		 890 /* Tell fw_cfg to notify the BIOS to reserve the range. */
891 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
20420430 892 if (ret < 0) {
11076198 893 fprintf(stderr, "e820_add_entry() table is full\n");
20420430
SY		 894 return ret;
895 }
3c85e74f 896 qemu_register_reset(kvm_unpoison_all, NULL);
20420430 897
4689b77b 898 shadow_mem = machine_kvm_shadow_mem(ms);
36ad0e94
MA		 899 if (shadow_mem != -1) {
900 shadow_mem /= 4096;
901 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
902 if (ret < 0) {
903 return ret;
39d6960a
JK		 904 }
905 }
11076198 906 return 0;
05330448 907}
b9bec74b 908
05330448
AL		 909static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
910{
911 lhs->selector = rhs->selector;
912 lhs->base = rhs->base;
913 lhs->limit = rhs->limit;
914 lhs->type = 3;
915 lhs->present = 1;
916 lhs->dpl = 3;
917 lhs->db = 0;
918 lhs->s = 1;
919 lhs->l = 0;
920 lhs->g = 0;
921 lhs->avl = 0;
922 lhs->unusable = 0;
923}
924
925static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
926{
927 unsigned flags = rhs->flags;
928 lhs->selector = rhs->selector;
929 lhs->base = rhs->base;
930 lhs->limit = rhs->limit;
931 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
932 lhs->present = (flags & DESC_P_MASK) != 0;
acaa7550 933 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
05330448
AL		 934 lhs->db = (flags >> DESC_B_SHIFT) & 1;
935 lhs->s = (flags & DESC_S_MASK) != 0;
936 lhs->l = (flags >> DESC_L_SHIFT) & 1;
937 lhs->g = (flags & DESC_G_MASK) != 0;
938 lhs->avl = (flags & DESC_AVL_MASK) != 0;
939 lhs->unusable = 0;
7e680753 940 lhs->padding = 0;
05330448
AL		 941}
942
943static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
944{
945 lhs->selector = rhs->selector;
946 lhs->base = rhs->base;
947 lhs->limit = rhs->limit;
b9bec74b
JK		 948 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
949 (rhs->present * DESC_P_MASK) |
950 (rhs->dpl << DESC_DPL_SHIFT) |
951 (rhs->db << DESC_B_SHIFT) |
952 (rhs->s * DESC_S_MASK) |
953 (rhs->l << DESC_L_SHIFT) |
954 (rhs->g * DESC_G_MASK) |
955 (rhs->avl * DESC_AVL_MASK);
05330448
AL		 956}
957
958static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
959{
b9bec74b 960 if (set) {
05330448 961 *kvm_reg = *qemu_reg;
b9bec74b 962 } else {
05330448 963 *qemu_reg = *kvm_reg;
b9bec74b 964 }
05330448
AL		 965}
966
1bc22652 967static int kvm_getput_regs(X86CPU *cpu, int set)
05330448 968{
1bc22652 969 CPUX86State *env = &cpu->env;
05330448
AL		 970 struct kvm_regs regs;
971 int ret = 0;
972
973 if (!set) {
1bc22652 974 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
b9bec74b 975 if (ret < 0) {
05330448 976 return ret;
b9bec74b 977 }
05330448
AL		 978 }
979
980 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
981 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
982 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
983 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
984 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
985 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
986 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
987 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
988#ifdef TARGET_X86_64
989 kvm_getput_reg(&regs.r8, &env->regs[8], set);
990 kvm_getput_reg(&regs.r9, &env->regs[9], set);
991 kvm_getput_reg(&regs.r10, &env->regs[10], set);
992 kvm_getput_reg(&regs.r11, &env->regs[11], set);
993 kvm_getput_reg(&regs.r12, &env->regs[12], set);
994 kvm_getput_reg(&regs.r13, &env->regs[13], set);
995 kvm_getput_reg(&regs.r14, &env->regs[14], set);
996 kvm_getput_reg(&regs.r15, &env->regs[15], set);
997#endif
998
999 kvm_getput_reg(&regs.rflags, &env->eflags, set);
1000 kvm_getput_reg(&regs.rip, &env->eip, set);
1001
b9bec74b 1002 if (set) {
1bc22652 1003 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
b9bec74b 1004 }
05330448
AL		 1005
1006 return ret;
1007}
1008
1bc22652 1009static int kvm_put_fpu(X86CPU *cpu)
05330448 1010{
1bc22652 1011 CPUX86State *env = &cpu->env;
05330448
AL		 1012 struct kvm_fpu fpu;
1013 int i;
1014
1015 memset(&fpu, 0, sizeof fpu);
1016 fpu.fsw = env->fpus & ~(7 << 11);
1017 fpu.fsw |= (env->fpstt & 7) << 11;
1018 fpu.fcw = env->fpuc;
42cc8fa6
JK		 1019 fpu.last_opcode = env->fpop;
1020 fpu.last_ip = env->fpip;
1021 fpu.last_dp = env->fpdp;
b9bec74b
JK		 1022 for (i = 0; i < 8; ++i) {
1023 fpu.ftwx |= (!env->fptags[i]) << i;
1024 }
05330448 1025 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
bee81887
PB		 1026 for (i = 0; i < CPU_NB_REGS; i++) {
1027 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].XMM_Q(0));
1028 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].XMM_Q(1));
1029 }
05330448
AL		 1030 fpu.mxcsr = env->mxcsr;
1031
1bc22652 1032 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
05330448
AL		 1033}
1034
6b42494b
JK		 1035#define XSAVE_FCW_FSW 0
1036#define XSAVE_FTW_FOP 1
f1665b21
SY		 1037#define XSAVE_CWD_RIP 2
1038#define XSAVE_CWD_RDP 4
1039#define XSAVE_MXCSR 6
1040#define XSAVE_ST_SPACE 8
1041#define XSAVE_XMM_SPACE 40
1042#define XSAVE_XSTATE_BV 128
1043#define XSAVE_YMMH_SPACE 144
79e9ebeb
LJ		 1044#define XSAVE_BNDREGS 240
1045#define XSAVE_BNDCSR 256
9aecd6f8
CP		 1046#define XSAVE_OPMASK 272
1047#define XSAVE_ZMM_Hi256 288
1048#define XSAVE_Hi16_ZMM 416
f1665b21 1049
1bc22652 1050static int kvm_put_xsave(X86CPU *cpu)
f1665b21 1051{
1bc22652 1052 CPUX86State *env = &cpu->env;
fabacc0f 1053 struct kvm_xsave* xsave = env->kvm_xsave_buf;
42cc8fa6 1054 uint16_t cwd, swd, twd;
b7711471 1055 uint8_t *xmm, *ymmh, *zmmh;
fabacc0f 1056 int i, r;
f1665b21 1057
b9bec74b 1058 if (!kvm_has_xsave()) {
1bc22652 1059 return kvm_put_fpu(cpu);
b9bec74b 1060 }
f1665b21 1061
f1665b21 1062 memset(xsave, 0, sizeof(struct kvm_xsave));
6115c0a8 1063 twd = 0;
f1665b21
SY		 1064 swd = env->fpus & ~(7 << 11);
1065 swd |= (env->fpstt & 7) << 11;
1066 cwd = env->fpuc;
b9bec74b 1067 for (i = 0; i < 8; ++i) {
f1665b21 1068 twd |= (!env->fptags[i]) << i;
b9bec74b 1069 }
6b42494b
JK		 1070 xsave->region[XSAVE_FCW_FSW] = (uint32_t)(swd << 16) + cwd;
1071 xsave->region[XSAVE_FTW_FOP] = (uint32_t)(env->fpop << 16) + twd;
42cc8fa6
JK		 1072 memcpy(&xsave->region[XSAVE_CWD_RIP], &env->fpip, sizeof(env->fpip));
1073 memcpy(&xsave->region[XSAVE_CWD_RDP], &env->fpdp, sizeof(env->fpdp));
f1665b21
SY		 1074 memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
1075 sizeof env->fpregs);
f1665b21
SY		 1076 xsave->region[XSAVE_MXCSR] = env->mxcsr;
1077 *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
79e9ebeb
LJ		 1078 memcpy(&xsave->region[XSAVE_BNDREGS], env->bnd_regs,
1079 sizeof env->bnd_regs);
1080 memcpy(&xsave->region[XSAVE_BNDCSR], &env->bndcs_regs,
1081 sizeof(env->bndcs_regs));
9aecd6f8
CP		 1082 memcpy(&xsave->region[XSAVE_OPMASK], env->opmask_regs,
1083 sizeof env->opmask_regs);
bee81887
PB		 1084
1085 xmm = (uint8_t *)&xsave->region[XSAVE_XMM_SPACE];
b7711471
PB		 1086 ymmh = (uint8_t *)&xsave->region[XSAVE_YMMH_SPACE];
1087 zmmh = (uint8_t *)&xsave->region[XSAVE_ZMM_Hi256];
1088 for (i = 0; i < CPU_NB_REGS; i++, xmm += 16, ymmh += 16, zmmh += 32) {
bee81887
PB		 1089 stq_p(xmm, env->xmm_regs[i].XMM_Q(0));
1090 stq_p(xmm+8, env->xmm_regs[i].XMM_Q(1));
b7711471
PB		 1091 stq_p(ymmh, env->xmm_regs[i].XMM_Q(2));
1092 stq_p(ymmh+8, env->xmm_regs[i].XMM_Q(3));
1093 stq_p(zmmh, env->xmm_regs[i].XMM_Q(4));
1094 stq_p(zmmh+8, env->xmm_regs[i].XMM_Q(5));
1095 stq_p(zmmh+16, env->xmm_regs[i].XMM_Q(6));
1096 stq_p(zmmh+24, env->xmm_regs[i].XMM_Q(7));
bee81887
PB		 1097 }
1098
9aecd6f8 1099#ifdef TARGET_X86_64
b7711471
PB		 1100 memcpy(&xsave->region[XSAVE_Hi16_ZMM], &env->xmm_regs[16],
1101 16 * sizeof env->xmm_regs[16]);
9aecd6f8 1102#endif
1bc22652 1103 r = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
0f53994f 1104 return r;
f1665b21
SY		 1105}
1106
1bc22652 1107static int kvm_put_xcrs(X86CPU *cpu)
f1665b21 1108{
1bc22652 1109 CPUX86State *env = &cpu->env;
bdfc8480 1110 struct kvm_xcrs xcrs = {};
f1665b21 1111
b9bec74b 1112 if (!kvm_has_xcrs()) {
f1665b21 1113 return 0;
b9bec74b 1114 }
f1665b21
SY		 1115
1116 xcrs.nr_xcrs = 1;
1117 xcrs.flags = 0;
1118 xcrs.xcrs[0].xcr = 0;
1119 xcrs.xcrs[0].value = env->xcr0;
1bc22652 1120 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
f1665b21
SY		 1121}
1122
1bc22652 1123static int kvm_put_sregs(X86CPU *cpu)
05330448 1124{
1bc22652 1125 CPUX86State *env = &cpu->env;
05330448
AL		 1126 struct kvm_sregs sregs;
1127
0e607a80
JK		 1128 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1129 if (env->interrupt_injected >= 0) {
1130 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1131 (uint64_t)1 << (env->interrupt_injected % 64);
1132 }
05330448
AL		 1133
1134 if ((env->eflags & VM_MASK)) {
b9bec74b
JK		 1135 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1136 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1137 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1138 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1139 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1140 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
05330448 1141 } else {
b9bec74b
JK		 1142 set_seg(&sregs.cs, &env->segs[R_CS]);
1143 set_seg(&sregs.ds, &env->segs[R_DS]);
1144 set_seg(&sregs.es, &env->segs[R_ES]);
1145 set_seg(&sregs.fs, &env->segs[R_FS]);
1146 set_seg(&sregs.gs, &env->segs[R_GS]);
1147 set_seg(&sregs.ss, &env->segs[R_SS]);
05330448
AL		 1148 }
1149
1150 set_seg(&sregs.tr, &env->tr);
1151 set_seg(&sregs.ldt, &env->ldt);
1152
1153 sregs.idt.limit = env->idt.limit;
1154 sregs.idt.base = env->idt.base;
7e680753 1155 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
05330448
AL		 1156 sregs.gdt.limit = env->gdt.limit;
1157 sregs.gdt.base = env->gdt.base;
7e680753 1158 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
05330448
AL		 1159
1160 sregs.cr0 = env->cr[0];
1161 sregs.cr2 = env->cr[2];
1162 sregs.cr3 = env->cr[3];
1163 sregs.cr4 = env->cr[4];
1164
02e51483
CF		 1165 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1166 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
05330448
AL		 1167
1168 sregs.efer = env->efer;
1169
1bc22652 1170 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
05330448
AL		 1171}
1172
1173static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
1174 uint32_t index, uint64_t value)
1175{
1176 entry->index = index;
c7fe4b12 1177 entry->reserved = 0;
05330448
AL		 1178 entry->data = value;
1179}
1180
7477cd38
MT		 1181static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1182{
1183 CPUX86State *env = &cpu->env;
1184 struct {
1185 struct kvm_msrs info;
1186 struct kvm_msr_entry entries[1];
1187 } msr_data;
1188 struct kvm_msr_entry *msrs = msr_data.entries;
1189
1190 if (!has_msr_tsc_deadline) {
1191 return 0;
1192 }
1193
1194 kvm_msr_entry_set(&msrs[0], MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1195
c7fe4b12
CB		 1196 msr_data.info = (struct kvm_msrs) {
1197 .nmsrs = 1,
1198 };
7477cd38
MT		 1199
1200 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1201}
1202
6bdf863d
JK		 1203/*
1204 * Provide a separate write service for the feature control MSR in order to
1205 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1206 * before writing any other state because forcibly leaving nested mode
1207 * invalidates the VCPU state.
1208 */
1209static int kvm_put_msr_feature_control(X86CPU *cpu)
1210{
1211 struct {
1212 struct kvm_msrs info;
1213 struct kvm_msr_entry entry;
1214 } msr_data;
1215
1216 kvm_msr_entry_set(&msr_data.entry, MSR_IA32_FEATURE_CONTROL,
1217 cpu->env.msr_ia32_feature_control);
c7fe4b12
CB		 1218
1219 msr_data.info = (struct kvm_msrs) {
1220 .nmsrs = 1,
1221 };
1222
6bdf863d
JK		 1223 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1224}
1225
1bc22652 1226static int kvm_put_msrs(X86CPU *cpu, int level)
05330448 1227{
1bc22652 1228 CPUX86State *env = &cpu->env;
05330448
AL		 1229 struct {
1230 struct kvm_msrs info;
d1ae67f6 1231 struct kvm_msr_entry entries[150];
05330448
AL		 1232 } msr_data;
1233 struct kvm_msr_entry *msrs = msr_data.entries;
0d894367 1234 int n = 0, i;
05330448
AL		 1235
1236 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1237 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1238 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
0c03266a 1239 kvm_msr_entry_set(&msrs[n++], MSR_PAT, env->pat);
c3a3a7d3 1240 if (has_msr_star) {
b9bec74b
JK		 1241 kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
1242 }
c3a3a7d3 1243 if (has_msr_hsave_pa) {
75b10c43 1244 kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
b9bec74b 1245 }
f28558d3
WA		 1246 if (has_msr_tsc_adjust) {
1247 kvm_msr_entry_set(&msrs[n++], MSR_TSC_ADJUST, env->tsc_adjust);
1248 }
21e87c46
AK		 1249 if (has_msr_misc_enable) {
1250 kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE,
1251 env->msr_ia32_misc_enable);
1252 }
fc12d72e
PB		 1253 if (has_msr_smbase) {
1254 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SMBASE, env->smbase);
1255 }
439d19f2
PB		 1256 if (has_msr_bndcfgs) {
1257 kvm_msr_entry_set(&msrs[n++], MSR_IA32_BNDCFGS, env->msr_bndcfgs);
1258 }
18cd2c17
WL		 1259 if (has_msr_xss) {
1260 kvm_msr_entry_set(&msrs[n++], MSR_IA32_XSS, env->xss);
1261 }
05330448 1262#ifdef TARGET_X86_64
25d2e361
MT		 1263 if (lm_capable_kernel) {
1264 kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
1265 kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
1266 kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
1267 kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
1268 }
05330448 1269#endif
ff5c186b 1270 /*
0d894367
PB		 1271 * The following MSRs have side effects on the guest or are too heavy
1272 * for normal writeback. Limit them to reset or full state updates.
ff5c186b
JK		 1273 */
1274 if (level >= KVM_PUT_RESET_STATE) {
0522604b 1275 kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
ea643051
JK		 1276 kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
1277 env->system_time_msr);
1278 kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
c5999bfc
JK		 1279 if (has_msr_async_pf_en) {
1280 kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN,
1281 env->async_pf_en_msr);
1282 }
bc9a839d
MT		 1283 if (has_msr_pv_eoi_en) {
1284 kvm_msr_entry_set(&msrs[n++], MSR_KVM_PV_EOI_EN,
1285 env->pv_eoi_en_msr);
1286 }
917367aa
MT		 1287 if (has_msr_kvm_steal_time) {
1288 kvm_msr_entry_set(&msrs[n++], MSR_KVM_STEAL_TIME,
1289 env->steal_time_msr);
1290 }
0d894367
PB		 1291 if (has_msr_architectural_pmu) {
1292 /* Stop the counter. */
1293 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1294 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL, 0);
1295
1296 /* Set the counter values. */
1297 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1298 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR0 + i,
1299 env->msr_fixed_counters[i]);
1300 }
1301 for (i = 0; i < num_architectural_pmu_counters; i++) {
1302 kvm_msr_entry_set(&msrs[n++], MSR_P6_PERFCTR0 + i,
1303 env->msr_gp_counters[i]);
1304 kvm_msr_entry_set(&msrs[n++], MSR_P6_EVNTSEL0 + i,
1305 env->msr_gp_evtsel[i]);
1306 }
1307 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_STATUS,
1308 env->msr_global_status);
1309 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1310 env->msr_global_ovf_ctrl);
1311
1312 /* Now start the PMU. */
1313 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL,
1314 env->msr_fixed_ctr_ctrl);
1315 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL,
1316 env->msr_global_ctrl);
1317 }
7bc3d711 1318 if (has_msr_hv_hypercall) {
1c90ef26
VR		 1319 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_GUEST_OS_ID,
1320 env->msr_hv_guest_os_id);
1321 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_HYPERCALL,
1322 env->msr_hv_hypercall);
eab70139 1323 }
7bc3d711 1324 if (has_msr_hv_vapic) {
5ef68987
VR		 1325 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_APIC_ASSIST_PAGE,
1326 env->msr_hv_vapic);
eab70139 1327 }
48a5f3bc
VR		 1328 if (has_msr_hv_tsc) {
1329 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_REFERENCE_TSC,
1330 env->msr_hv_tsc);
1331 }
d1ae67f6
AW		 1332 if (has_msr_mtrr) {
1333 kvm_msr_entry_set(&msrs[n++], MSR_MTRRdefType, env->mtrr_deftype);
1334 kvm_msr_entry_set(&msrs[n++],
1335 MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
1336 kvm_msr_entry_set(&msrs[n++],
1337 MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
1338 kvm_msr_entry_set(&msrs[n++],
1339 MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
1340 kvm_msr_entry_set(&msrs[n++],
1341 MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
1342 kvm_msr_entry_set(&msrs[n++],
1343 MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
1344 kvm_msr_entry_set(&msrs[n++],
1345 MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
1346 kvm_msr_entry_set(&msrs[n++],
1347 MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
1348 kvm_msr_entry_set(&msrs[n++],
1349 MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
1350 kvm_msr_entry_set(&msrs[n++],
1351 MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
1352 kvm_msr_entry_set(&msrs[n++],
1353 MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
1354 kvm_msr_entry_set(&msrs[n++],
1355 MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
1356 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
1357 kvm_msr_entry_set(&msrs[n++],
1358 MSR_MTRRphysBase(i), env->mtrr_var[i].base);
1359 kvm_msr_entry_set(&msrs[n++],
1360 MSR_MTRRphysMask(i), env->mtrr_var[i].mask);
1361 }
1362 }
6bdf863d
JK		 1363
1364 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1365 * kvm_put_msr_feature_control. */
ea643051 1366 }
57780495 1367 if (env->mcg_cap) {
d8da8574 1368 int i;
b9bec74b 1369
c34d440a
JK		 1370 kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
1371 kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl);
1372 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1373 kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]);
57780495
MT		 1374 }
1375 }
1a03675d 1376
c7fe4b12
CB		 1377 msr_data.info = (struct kvm_msrs) {
1378 .nmsrs = n,
1379 };
05330448 1380
1bc22652 1381 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
05330448
AL		 1382
1383}
1384
1385
1bc22652 1386static int kvm_get_fpu(X86CPU *cpu)
05330448 1387{
1bc22652 1388 CPUX86State *env = &cpu->env;
05330448
AL		 1389 struct kvm_fpu fpu;
1390 int i, ret;
1391
1bc22652 1392 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
b9bec74b 1393 if (ret < 0) {
05330448 1394 return ret;
b9bec74b 1395 }
05330448
AL		 1396
1397 env->fpstt = (fpu.fsw >> 11) & 7;
1398 env->fpus = fpu.fsw;
1399 env->fpuc = fpu.fcw;
42cc8fa6
JK		 1400 env->fpop = fpu.last_opcode;
1401 env->fpip = fpu.last_ip;
1402 env->fpdp = fpu.last_dp;
b9bec74b
JK		 1403 for (i = 0; i < 8; ++i) {
1404 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1405 }
05330448 1406 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
bee81887
PB		 1407 for (i = 0; i < CPU_NB_REGS; i++) {
1408 env->xmm_regs[i].XMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
1409 env->xmm_regs[i].XMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
1410 }
05330448
AL		 1411 env->mxcsr = fpu.mxcsr;
1412
1413 return 0;
1414}
1415
1bc22652 1416static int kvm_get_xsave(X86CPU *cpu)
f1665b21 1417{
1bc22652 1418 CPUX86State *env = &cpu->env;
fabacc0f 1419 struct kvm_xsave* xsave = env->kvm_xsave_buf;
f1665b21 1420 int ret, i;
b7711471 1421 const uint8_t *xmm, *ymmh, *zmmh;
42cc8fa6 1422 uint16_t cwd, swd, twd;
f1665b21 1423
b9bec74b 1424 if (!kvm_has_xsave()) {
1bc22652 1425 return kvm_get_fpu(cpu);
b9bec74b 1426 }
f1665b21 1427
1bc22652 1428 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
0f53994f 1429 if (ret < 0) {
f1665b21 1430 return ret;
0f53994f 1431 }
f1665b21 1432
6b42494b
JK		 1433 cwd = (uint16_t)xsave->region[XSAVE_FCW_FSW];
1434 swd = (uint16_t)(xsave->region[XSAVE_FCW_FSW] >> 16);
1435 twd = (uint16_t)xsave->region[XSAVE_FTW_FOP];
1436 env->fpop = (uint16_t)(xsave->region[XSAVE_FTW_FOP] >> 16);
f1665b21
SY		 1437 env->fpstt = (swd >> 11) & 7;
1438 env->fpus = swd;
1439 env->fpuc = cwd;
b9bec74b 1440 for (i = 0; i < 8; ++i) {
f1665b21 1441 env->fptags[i] = !((twd >> i) & 1);
b9bec74b 1442 }
42cc8fa6
JK		 1443 memcpy(&env->fpip, &xsave->region[XSAVE_CWD_RIP], sizeof(env->fpip));
1444 memcpy(&env->fpdp, &xsave->region[XSAVE_CWD_RDP], sizeof(env->fpdp));
f1665b21
SY		 1445 env->mxcsr = xsave->region[XSAVE_MXCSR];
1446 memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
1447 sizeof env->fpregs);
f1665b21 1448 env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
79e9ebeb
LJ		 1449 memcpy(env->bnd_regs, &xsave->region[XSAVE_BNDREGS],
1450 sizeof env->bnd_regs);
1451 memcpy(&env->bndcs_regs, &xsave->region[XSAVE_BNDCSR],
1452 sizeof(env->bndcs_regs));
9aecd6f8
CP		 1453 memcpy(env->opmask_regs, &xsave->region[XSAVE_OPMASK],
1454 sizeof env->opmask_regs);
bee81887
PB		 1455
1456 xmm = (const uint8_t *)&xsave->region[XSAVE_XMM_SPACE];
b7711471
PB		 1457 ymmh = (const uint8_t *)&xsave->region[XSAVE_YMMH_SPACE];
1458 zmmh = (const uint8_t *)&xsave->region[XSAVE_ZMM_Hi256];
1459 for (i = 0; i < CPU_NB_REGS; i++, xmm += 16, ymmh += 16, zmmh += 32) {
bee81887
PB		 1460 env->xmm_regs[i].XMM_Q(0) = ldq_p(xmm);
1461 env->xmm_regs[i].XMM_Q(1) = ldq_p(xmm+8);
b7711471
PB		 1462 env->xmm_regs[i].XMM_Q(2) = ldq_p(ymmh);
1463 env->xmm_regs[i].XMM_Q(3) = ldq_p(ymmh+8);
1464 env->xmm_regs[i].XMM_Q(4) = ldq_p(zmmh);
1465 env->xmm_regs[i].XMM_Q(5) = ldq_p(zmmh+8);
1466 env->xmm_regs[i].XMM_Q(6) = ldq_p(zmmh+16);
1467 env->xmm_regs[i].XMM_Q(7) = ldq_p(zmmh+24);
bee81887
PB		 1468 }
1469
9aecd6f8 1470#ifdef TARGET_X86_64
b7711471
PB		 1471 memcpy(&env->xmm_regs[16], &xsave->region[XSAVE_Hi16_ZMM],
1472 16 * sizeof env->xmm_regs[16]);
9aecd6f8 1473#endif
f1665b21 1474 return 0;
f1665b21
SY		 1475}
1476
1bc22652 1477static int kvm_get_xcrs(X86CPU *cpu)
f1665b21 1478{
1bc22652 1479 CPUX86State *env = &cpu->env;
f1665b21
SY		 1480 int i, ret;
1481 struct kvm_xcrs xcrs;
1482
b9bec74b 1483 if (!kvm_has_xcrs()) {
f1665b21 1484 return 0;
b9bec74b 1485 }
f1665b21 1486
1bc22652 1487 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
b9bec74b 1488 if (ret < 0) {
f1665b21 1489 return ret;
b9bec74b 1490 }
f1665b21 1491
b9bec74b 1492 for (i = 0; i < xcrs.nr_xcrs; i++) {
f1665b21 1493 /* Only support xcr0 now */
0fd53fec
PB		 1494 if (xcrs.xcrs[i].xcr == 0) {
1495 env->xcr0 = xcrs.xcrs[i].value;
f1665b21
SY		 1496 break;
1497 }
b9bec74b 1498 }
f1665b21 1499 return 0;
f1665b21
SY		 1500}
1501
1bc22652 1502static int kvm_get_sregs(X86CPU *cpu)
05330448 1503{
1bc22652 1504 CPUX86State *env = &cpu->env;
05330448
AL		 1505 struct kvm_sregs sregs;
1506 uint32_t hflags;
0e607a80 1507 int bit, i, ret;
05330448 1508
1bc22652 1509 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
b9bec74b 1510 if (ret < 0) {
05330448 1511 return ret;
b9bec74b 1512 }
05330448 1513
0e607a80
JK		 1514 /* There can only be one pending IRQ set in the bitmap at a time, so try
1515 to find it and save its number instead (-1 for none). */
1516 env->interrupt_injected = -1;
1517 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1518 if (sregs.interrupt_bitmap[i]) {
1519 bit = ctz64(sregs.interrupt_bitmap[i]);
1520 env->interrupt_injected = i * 64 + bit;
1521 break;
1522 }
1523 }
05330448
AL		 1524
1525 get_seg(&env->segs[R_CS], &sregs.cs);
1526 get_seg(&env->segs[R_DS], &sregs.ds);
1527 get_seg(&env->segs[R_ES], &sregs.es);
1528 get_seg(&env->segs[R_FS], &sregs.fs);
1529 get_seg(&env->segs[R_GS], &sregs.gs);
1530 get_seg(&env->segs[R_SS], &sregs.ss);
1531
1532 get_seg(&env->tr, &sregs.tr);
1533 get_seg(&env->ldt, &sregs.ldt);
1534
1535 env->idt.limit = sregs.idt.limit;
1536 env->idt.base = sregs.idt.base;
1537 env->gdt.limit = sregs.gdt.limit;
1538 env->gdt.base = sregs.gdt.base;
1539
1540 env->cr[0] = sregs.cr0;
1541 env->cr[2] = sregs.cr2;
1542 env->cr[3] = sregs.cr3;
1543 env->cr[4] = sregs.cr4;
1544
05330448 1545 env->efer = sregs.efer;
cce47516
JK		 1546
1547 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
05330448 1548
b9bec74b
JK		 1549#define HFLAG_COPY_MASK \
1550 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1551 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1552 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1553 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
05330448 1554
7125c937 1555 hflags = (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
05330448
AL		 1556 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1557 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
b9bec74b 1558 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
05330448
AL		 1559 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1560 hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
b9bec74b 1561 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
05330448
AL		 1562
1563 if (env->efer & MSR_EFER_LMA) {
1564 hflags |= HF_LMA_MASK;
1565 }
1566
1567 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1568 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1569 } else {
1570 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
b9bec74b 1571 (DESC_B_SHIFT - HF_CS32_SHIFT);
05330448 1572 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
b9bec74b
JK		 1573 (DESC_B_SHIFT - HF_SS32_SHIFT);
1574 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1575 !(hflags & HF_CS32_MASK)) {
1576 hflags |= HF_ADDSEG_MASK;
1577 } else {
1578 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1579 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1580 }
05330448
AL		 1581 }
1582 env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
05330448
AL		 1583
1584 return 0;
1585}
1586
1bc22652 1587static int kvm_get_msrs(X86CPU *cpu)
05330448 1588{
1bc22652 1589 CPUX86State *env = &cpu->env;
05330448
AL		 1590 struct {
1591 struct kvm_msrs info;
d1ae67f6 1592 struct kvm_msr_entry entries[150];
05330448
AL		 1593 } msr_data;
1594 struct kvm_msr_entry *msrs = msr_data.entries;
1595 int ret, i, n;
1596
1597 n = 0;
1598 msrs[n++].index = MSR_IA32_SYSENTER_CS;
1599 msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1600 msrs[n++].index = MSR_IA32_SYSENTER_EIP;
0c03266a 1601 msrs[n++].index = MSR_PAT;
c3a3a7d3 1602 if (has_msr_star) {
b9bec74b
JK		 1603 msrs[n++].index = MSR_STAR;
1604 }
c3a3a7d3 1605 if (has_msr_hsave_pa) {
75b10c43 1606 msrs[n++].index = MSR_VM_HSAVE_PA;
b9bec74b 1607 }
f28558d3
WA		 1608 if (has_msr_tsc_adjust) {
1609 msrs[n++].index = MSR_TSC_ADJUST;
1610 }
aa82ba54
LJ		 1611 if (has_msr_tsc_deadline) {
1612 msrs[n++].index = MSR_IA32_TSCDEADLINE;
1613 }
21e87c46
AK		 1614 if (has_msr_misc_enable) {
1615 msrs[n++].index = MSR_IA32_MISC_ENABLE;
1616 }
fc12d72e
PB		 1617 if (has_msr_smbase) {
1618 msrs[n++].index = MSR_IA32_SMBASE;
1619 }
df67696e
LJ		 1620 if (has_msr_feature_control) {
1621 msrs[n++].index = MSR_IA32_FEATURE_CONTROL;
1622 }
79e9ebeb
LJ		 1623 if (has_msr_bndcfgs) {
1624 msrs[n++].index = MSR_IA32_BNDCFGS;
1625 }
18cd2c17
WL		 1626 if (has_msr_xss) {
1627 msrs[n++].index = MSR_IA32_XSS;
1628 }
1629
b8cc45d6
GC		 1630
1631 if (!env->tsc_valid) {
1632 msrs[n++].index = MSR_IA32_TSC;
1354869c 1633 env->tsc_valid = !runstate_is_running();
b8cc45d6
GC		 1634 }
1635
05330448 1636#ifdef TARGET_X86_64
25d2e361
MT		 1637 if (lm_capable_kernel) {
1638 msrs[n++].index = MSR_CSTAR;
1639 msrs[n++].index = MSR_KERNELGSBASE;
1640 msrs[n++].index = MSR_FMASK;
1641 msrs[n++].index = MSR_LSTAR;
1642 }
05330448 1643#endif
1a03675d
GC		 1644 msrs[n++].index = MSR_KVM_SYSTEM_TIME;
1645 msrs[n++].index = MSR_KVM_WALL_CLOCK;
c5999bfc
JK		 1646 if (has_msr_async_pf_en) {
1647 msrs[n++].index = MSR_KVM_ASYNC_PF_EN;
1648 }
bc9a839d
MT		 1649 if (has_msr_pv_eoi_en) {
1650 msrs[n++].index = MSR_KVM_PV_EOI_EN;
1651 }
917367aa
MT		 1652 if (has_msr_kvm_steal_time) {
1653 msrs[n++].index = MSR_KVM_STEAL_TIME;
1654 }
0d894367
PB		 1655 if (has_msr_architectural_pmu) {
1656 msrs[n++].index = MSR_CORE_PERF_FIXED_CTR_CTRL;
1657 msrs[n++].index = MSR_CORE_PERF_GLOBAL_CTRL;
1658 msrs[n++].index = MSR_CORE_PERF_GLOBAL_STATUS;
1659 msrs[n++].index = MSR_CORE_PERF_GLOBAL_OVF_CTRL;
1660 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1661 msrs[n++].index = MSR_CORE_PERF_FIXED_CTR0 + i;
1662 }
1663 for (i = 0; i < num_architectural_pmu_counters; i++) {
1664 msrs[n++].index = MSR_P6_PERFCTR0 + i;
1665 msrs[n++].index = MSR_P6_EVNTSEL0 + i;
1666 }
1667 }
1a03675d 1668
57780495
MT		 1669 if (env->mcg_cap) {
1670 msrs[n++].index = MSR_MCG_STATUS;
1671 msrs[n++].index = MSR_MCG_CTL;
b9bec74b 1672 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
57780495 1673 msrs[n++].index = MSR_MC0_CTL + i;
b9bec74b 1674 }
57780495 1675 }
57780495 1676
1c90ef26
VR		 1677 if (has_msr_hv_hypercall) {
1678 msrs[n++].index = HV_X64_MSR_HYPERCALL;
1679 msrs[n++].index = HV_X64_MSR_GUEST_OS_ID;
1680 }
5ef68987
VR		 1681 if (has_msr_hv_vapic) {
1682 msrs[n++].index = HV_X64_MSR_APIC_ASSIST_PAGE;
1683 }
48a5f3bc
VR		 1684 if (has_msr_hv_tsc) {
1685 msrs[n++].index = HV_X64_MSR_REFERENCE_TSC;
1686 }
d1ae67f6
AW		 1687 if (has_msr_mtrr) {
1688 msrs[n++].index = MSR_MTRRdefType;
1689 msrs[n++].index = MSR_MTRRfix64K_00000;
1690 msrs[n++].index = MSR_MTRRfix16K_80000;
1691 msrs[n++].index = MSR_MTRRfix16K_A0000;
1692 msrs[n++].index = MSR_MTRRfix4K_C0000;
1693 msrs[n++].index = MSR_MTRRfix4K_C8000;
1694 msrs[n++].index = MSR_MTRRfix4K_D0000;
1695 msrs[n++].index = MSR_MTRRfix4K_D8000;
1696 msrs[n++].index = MSR_MTRRfix4K_E0000;
1697 msrs[n++].index = MSR_MTRRfix4K_E8000;
1698 msrs[n++].index = MSR_MTRRfix4K_F0000;
1699 msrs[n++].index = MSR_MTRRfix4K_F8000;
1700 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
1701 msrs[n++].index = MSR_MTRRphysBase(i);
1702 msrs[n++].index = MSR_MTRRphysMask(i);
1703 }
1704 }
5ef68987 1705
d19ae73e
CB		 1706 msr_data.info = (struct kvm_msrs) {
1707 .nmsrs = n,
1708 };
1709
1bc22652 1710 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
b9bec74b 1711 if (ret < 0) {
05330448 1712 return ret;
b9bec74b 1713 }
05330448
AL		 1714
1715 for (i = 0; i < ret; i++) {
0d894367
PB		 1716 uint32_t index = msrs[i].index;
1717 switch (index) {
05330448
AL		 1718 case MSR_IA32_SYSENTER_CS:
1719 env->sysenter_cs = msrs[i].data;
1720 break;
1721 case MSR_IA32_SYSENTER_ESP:
1722 env->sysenter_esp = msrs[i].data;
1723 break;
1724 case MSR_IA32_SYSENTER_EIP:
1725 env->sysenter_eip = msrs[i].data;
1726 break;
0c03266a
JK		 1727 case MSR_PAT:
1728 env->pat = msrs[i].data;
1729 break;
05330448
AL		 1730 case MSR_STAR:
1731 env->star = msrs[i].data;
1732 break;
1733#ifdef TARGET_X86_64
1734 case MSR_CSTAR:
1735 env->cstar = msrs[i].data;
1736 break;
1737 case MSR_KERNELGSBASE:
1738 env->kernelgsbase = msrs[i].data;
1739 break;
1740 case MSR_FMASK:
1741 env->fmask = msrs[i].data;
1742 break;
1743 case MSR_LSTAR:
1744 env->lstar = msrs[i].data;
1745 break;
1746#endif
1747 case MSR_IA32_TSC:
1748 env->tsc = msrs[i].data;
1749 break;
f28558d3
WA		 1750 case MSR_TSC_ADJUST:
1751 env->tsc_adjust = msrs[i].data;
1752 break;
aa82ba54
LJ		 1753 case MSR_IA32_TSCDEADLINE:
1754 env->tsc_deadline = msrs[i].data;
1755 break;
aa851e36
MT		 1756 case MSR_VM_HSAVE_PA:
1757 env->vm_hsave = msrs[i].data;
1758 break;
1a03675d
GC		 1759 case MSR_KVM_SYSTEM_TIME:
1760 env->system_time_msr = msrs[i].data;
1761 break;
1762 case MSR_KVM_WALL_CLOCK:
1763 env->wall_clock_msr = msrs[i].data;
1764 break;
57780495
MT		 1765 case MSR_MCG_STATUS:
1766 env->mcg_status = msrs[i].data;
1767 break;
1768 case MSR_MCG_CTL:
1769 env->mcg_ctl = msrs[i].data;
1770 break;
21e87c46
AK		 1771 case MSR_IA32_MISC_ENABLE:
1772 env->msr_ia32_misc_enable = msrs[i].data;
1773 break;
fc12d72e
PB		 1774 case MSR_IA32_SMBASE:
1775 env->smbase = msrs[i].data;
1776 break;
0779caeb
ACL		 1777 case MSR_IA32_FEATURE_CONTROL:
1778 env->msr_ia32_feature_control = msrs[i].data;
df67696e 1779 break;
79e9ebeb
LJ		 1780 case MSR_IA32_BNDCFGS:
1781 env->msr_bndcfgs = msrs[i].data;
1782 break;
18cd2c17
WL		 1783 case MSR_IA32_XSS:
1784 env->xss = msrs[i].data;
1785 break;
57780495 1786 default:
57780495
MT		 1787 if (msrs[i].index >= MSR_MC0_CTL &&
1788 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
1789 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
57780495 1790 }
d8da8574 1791 break;
f6584ee2
GN		 1792 case MSR_KVM_ASYNC_PF_EN:
1793 env->async_pf_en_msr = msrs[i].data;
1794 break;
bc9a839d
MT		 1795 case MSR_KVM_PV_EOI_EN:
1796 env->pv_eoi_en_msr = msrs[i].data;
1797 break;
917367aa
MT		 1798 case MSR_KVM_STEAL_TIME:
1799 env->steal_time_msr = msrs[i].data;
1800 break;
0d894367
PB		 1801 case MSR_CORE_PERF_FIXED_CTR_CTRL:
1802 env->msr_fixed_ctr_ctrl = msrs[i].data;
1803 break;
1804 case MSR_CORE_PERF_GLOBAL_CTRL:
1805 env->msr_global_ctrl = msrs[i].data;
1806 break;
1807 case MSR_CORE_PERF_GLOBAL_STATUS:
1808 env->msr_global_status = msrs[i].data;
1809 break;
1810 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
1811 env->msr_global_ovf_ctrl = msrs[i].data;
1812 break;
1813 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
1814 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
1815 break;
1816 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
1817 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
1818 break;
1819 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
1820 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
1821 break;
1c90ef26
VR		 1822 case HV_X64_MSR_HYPERCALL:
1823 env->msr_hv_hypercall = msrs[i].data;
1824 break;
1825 case HV_X64_MSR_GUEST_OS_ID:
1826 env->msr_hv_guest_os_id = msrs[i].data;
1827 break;
5ef68987
VR		 1828 case HV_X64_MSR_APIC_ASSIST_PAGE:
1829 env->msr_hv_vapic = msrs[i].data;
1830 break;
48a5f3bc
VR		 1831 case HV_X64_MSR_REFERENCE_TSC:
1832 env->msr_hv_tsc = msrs[i].data;
1833 break;
d1ae67f6
AW		 1834 case MSR_MTRRdefType:
1835 env->mtrr_deftype = msrs[i].data;
1836 break;
1837 case MSR_MTRRfix64K_00000:
1838 env->mtrr_fixed[0] = msrs[i].data;
1839 break;
1840 case MSR_MTRRfix16K_80000:
1841 env->mtrr_fixed[1] = msrs[i].data;
1842 break;
1843 case MSR_MTRRfix16K_A0000:
1844 env->mtrr_fixed[2] = msrs[i].data;
1845 break;
1846 case MSR_MTRRfix4K_C0000:
1847 env->mtrr_fixed[3] = msrs[i].data;
1848 break;
1849 case MSR_MTRRfix4K_C8000:
1850 env->mtrr_fixed[4] = msrs[i].data;
1851 break;
1852 case MSR_MTRRfix4K_D0000:
1853 env->mtrr_fixed[5] = msrs[i].data;
1854 break;
1855 case MSR_MTRRfix4K_D8000:
1856 env->mtrr_fixed[6] = msrs[i].data;
1857 break;
1858 case MSR_MTRRfix4K_E0000:
1859 env->mtrr_fixed[7] = msrs[i].data;
1860 break;
1861 case MSR_MTRRfix4K_E8000:
1862 env->mtrr_fixed[8] = msrs[i].data;
1863 break;
1864 case MSR_MTRRfix4K_F0000:
1865 env->mtrr_fixed[9] = msrs[i].data;
1866 break;
1867 case MSR_MTRRfix4K_F8000:
1868 env->mtrr_fixed[10] = msrs[i].data;
1869 break;
1870 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
1871 if (index & 1) {
1872 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data;
1873 } else {
1874 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
1875 }
1876 break;
05330448
AL		 1877 }
1878 }
1879
1880 return 0;
1881}
1882
1bc22652 1883static int kvm_put_mp_state(X86CPU *cpu)
9bdbe550 1884{
1bc22652 1885 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
9bdbe550 1886
1bc22652 1887 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
9bdbe550
HB		 1888}
1889
23d02d9b 1890static int kvm_get_mp_state(X86CPU *cpu)
9bdbe550 1891{
259186a7 1892 CPUState *cs = CPU(cpu);
23d02d9b 1893 CPUX86State *env = &cpu->env;
9bdbe550
HB		 1894 struct kvm_mp_state mp_state;
1895 int ret;
1896
259186a7 1897 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
9bdbe550
HB		 1898 if (ret < 0) {
1899 return ret;
1900 }
1901 env->mp_state = mp_state.mp_state;
c14750e8 1902 if (kvm_irqchip_in_kernel()) {
259186a7 1903 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
c14750e8 1904 }
9bdbe550
HB		 1905 return 0;
1906}
1907
1bc22652 1908static int kvm_get_apic(X86CPU *cpu)
680c1c6f 1909{
02e51483 1910 DeviceState *apic = cpu->apic_state;
680c1c6f
JK		 1911 struct kvm_lapic_state kapic;
1912 int ret;
1913
3d4b2649 1914 if (apic && kvm_irqchip_in_kernel()) {
1bc22652 1915 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
680c1c6f
JK		 1916 if (ret < 0) {
1917 return ret;
1918 }
1919
1920 kvm_get_apic_state(apic, &kapic);
1921 }
1922 return 0;
1923}
1924
1bc22652 1925static int kvm_put_apic(X86CPU *cpu)
680c1c6f 1926{
02e51483 1927 DeviceState *apic = cpu->apic_state;
680c1c6f
JK		 1928 struct kvm_lapic_state kapic;
1929
3d4b2649 1930 if (apic && kvm_irqchip_in_kernel()) {
680c1c6f
JK		 1931 kvm_put_apic_state(apic, &kapic);
1932
1bc22652 1933 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_LAPIC, &kapic);
680c1c6f
JK		 1934 }
1935 return 0;
1936}
1937
1bc22652 1938static int kvm_put_vcpu_events(X86CPU *cpu, int level)
a0fb002c 1939{
fc12d72e 1940 CPUState *cs = CPU(cpu);
1bc22652 1941 CPUX86State *env = &cpu->env;
076796f8 1942 struct kvm_vcpu_events events = {};
a0fb002c
JK		 1943
1944 if (!kvm_has_vcpu_events()) {
1945 return 0;
1946 }
1947
31827373
JK		 1948 events.exception.injected = (env->exception_injected >= 0);
1949 events.exception.nr = env->exception_injected;
a0fb002c
JK		 1950 events.exception.has_error_code = env->has_error_code;
1951 events.exception.error_code = env->error_code;
7e680753 1952 events.exception.pad = 0;
a0fb002c
JK		 1953
1954 events.interrupt.injected = (env->interrupt_injected >= 0);
1955 events.interrupt.nr = env->interrupt_injected;
1956 events.interrupt.soft = env->soft_interrupt;
1957
1958 events.nmi.injected = env->nmi_injected;
1959 events.nmi.pending = env->nmi_pending;
1960 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
7e680753 1961 events.nmi.pad = 0;
a0fb002c
JK		 1962
1963 events.sipi_vector = env->sipi_vector;
1964
fc12d72e
PB		 1965 if (has_msr_smbase) {
1966 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
1967 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
1968 if (kvm_irqchip_in_kernel()) {
1969 /* As soon as these are moved to the kernel, remove them
1970 * from cs->interrupt_request.
1971 */
1972 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
1973 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
1974 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
1975 } else {
1976 /* Keep these in cs->interrupt_request. */
1977 events.smi.pending = 0;
1978 events.smi.latched_init = 0;
1979 }
1980 events.flags |= KVM_VCPUEVENT_VALID_SMM;
1981 }
1982
ea643051
JK		 1983 events.flags = 0;
1984 if (level >= KVM_PUT_RESET_STATE) {
1985 events.flags |=
1986 KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
1987 }
aee028b9 1988
1bc22652 1989 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
a0fb002c
JK		 1990}
1991
1bc22652 1992static int kvm_get_vcpu_events(X86CPU *cpu)
a0fb002c 1993{
1bc22652 1994 CPUX86State *env = &cpu->env;
a0fb002c
JK		 1995 struct kvm_vcpu_events events;
1996 int ret;
1997
1998 if (!kvm_has_vcpu_events()) {
1999 return 0;
2000 }
2001
fc12d72e 2002 memset(&events, 0, sizeof(events));
1bc22652 2003 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
a0fb002c
JK		 2004 if (ret < 0) {
2005 return ret;
2006 }
31827373 2007 env->exception_injected =
a0fb002c
JK		 2008 events.exception.injected ? events.exception.nr : -1;
2009 env->has_error_code = events.exception.has_error_code;
2010 env->error_code = events.exception.error_code;
2011
2012 env->interrupt_injected =
2013 events.interrupt.injected ? events.interrupt.nr : -1;
2014 env->soft_interrupt = events.interrupt.soft;
2015
2016 env->nmi_injected = events.nmi.injected;
2017 env->nmi_pending = events.nmi.pending;
2018 if (events.nmi.masked) {
2019 env->hflags2 |= HF2_NMI_MASK;
2020 } else {
2021 env->hflags2 &= ~HF2_NMI_MASK;
2022 }
2023
fc12d72e
PB		 2024 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2025 if (events.smi.smm) {
2026 env->hflags |= HF_SMM_MASK;
2027 } else {
2028 env->hflags &= ~HF_SMM_MASK;
2029 }
2030 if (events.smi.pending) {
2031 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2032 } else {
2033 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2034 }
2035 if (events.smi.smm_inside_nmi) {
2036 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2037 } else {
2038 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2039 }
2040 if (events.smi.latched_init) {
2041 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2042 } else {
2043 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2044 }
2045 }
2046
a0fb002c 2047 env->sipi_vector = events.sipi_vector;
a0fb002c
JK		 2048
2049 return 0;
2050}
2051
1bc22652 2052static int kvm_guest_debug_workarounds(X86CPU *cpu)
b0b1d690 2053{
ed2803da 2054 CPUState *cs = CPU(cpu);
1bc22652 2055 CPUX86State *env = &cpu->env;
b0b1d690 2056 int ret = 0;
b0b1d690
JK		 2057 unsigned long reinject_trap = 0;
2058
2059 if (!kvm_has_vcpu_events()) {
2060 if (env->exception_injected == 1) {
2061 reinject_trap = KVM_GUESTDBG_INJECT_DB;
2062 } else if (env->exception_injected == 3) {
2063 reinject_trap = KVM_GUESTDBG_INJECT_BP;
2064 }
2065 env->exception_injected = -1;
2066 }
2067
2068 /*
2069 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2070 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2071 * by updating the debug state once again if single-stepping is on.
2072 * Another reason to call kvm_update_guest_debug here is a pending debug
2073 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2074 * reinject them via SET_GUEST_DEBUG.
2075 */
2076 if (reinject_trap ||
ed2803da 2077 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
38e478ec 2078 ret = kvm_update_guest_debug(cs, reinject_trap);
b0b1d690 2079 }
b0b1d690
JK		 2080 return ret;
2081}
2082
1bc22652 2083static int kvm_put_debugregs(X86CPU *cpu)
ff44f1a3 2084{
1bc22652 2085 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 2086 struct kvm_debugregs dbgregs;
2087 int i;
2088
2089 if (!kvm_has_debugregs()) {
2090 return 0;
2091 }
2092
2093 for (i = 0; i < 4; i++) {
2094 dbgregs.db[i] = env->dr[i];
2095 }
2096 dbgregs.dr6 = env->dr[6];
2097 dbgregs.dr7 = env->dr[7];
2098 dbgregs.flags = 0;
2099
1bc22652 2100 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
ff44f1a3
JK		 2101}
2102
1bc22652 2103static int kvm_get_debugregs(X86CPU *cpu)
ff44f1a3 2104{
1bc22652 2105 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 2106 struct kvm_debugregs dbgregs;
2107 int i, ret;
2108
2109 if (!kvm_has_debugregs()) {
2110 return 0;
2111 }
2112
1bc22652 2113 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
ff44f1a3 2114 if (ret < 0) {
b9bec74b 2115 return ret;
ff44f1a3
JK		 2116 }
2117 for (i = 0; i < 4; i++) {
2118 env->dr[i] = dbgregs.db[i];
2119 }
2120 env->dr[4] = env->dr[6] = dbgregs.dr6;
2121 env->dr[5] = env->dr[7] = dbgregs.dr7;
ff44f1a3
JK		 2122
2123 return 0;
2124}
2125
20d695a9 2126int kvm_arch_put_registers(CPUState *cpu, int level)
05330448 2127{
20d695a9 2128 X86CPU *x86_cpu = X86_CPU(cpu);
05330448
AL		 2129 int ret;
2130
2fa45344 2131 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
dbaa07c4 2132
6bdf863d
JK		 2133 if (level >= KVM_PUT_RESET_STATE && has_msr_feature_control) {
2134 ret = kvm_put_msr_feature_control(x86_cpu);
2135 if (ret < 0) {
2136 return ret;
2137 }
2138 }
2139
1bc22652 2140 ret = kvm_getput_regs(x86_cpu, 1);
b9bec74b 2141 if (ret < 0) {
05330448 2142 return ret;
b9bec74b 2143 }
1bc22652 2144 ret = kvm_put_xsave(x86_cpu);
b9bec74b 2145 if (ret < 0) {
f1665b21 2146 return ret;
b9bec74b 2147 }
1bc22652 2148 ret = kvm_put_xcrs(x86_cpu);
b9bec74b 2149 if (ret < 0) {
05330448 2150 return ret;
b9bec74b 2151 }
1bc22652 2152 ret = kvm_put_sregs(x86_cpu);
b9bec74b 2153 if (ret < 0) {
05330448 2154 return ret;
b9bec74b 2155 }
ab443475 2156 /* must be before kvm_put_msrs */
1bc22652 2157 ret = kvm_inject_mce_oldstyle(x86_cpu);
ab443475
JK		 2158 if (ret < 0) {
2159 return ret;
2160 }
1bc22652 2161 ret = kvm_put_msrs(x86_cpu, level);
b9bec74b 2162 if (ret < 0) {
05330448 2163 return ret;
b9bec74b 2164 }
ea643051 2165 if (level >= KVM_PUT_RESET_STATE) {
1bc22652 2166 ret = kvm_put_mp_state(x86_cpu);
b9bec74b 2167 if (ret < 0) {
ea643051 2168 return ret;
b9bec74b 2169 }
1bc22652 2170 ret = kvm_put_apic(x86_cpu);
680c1c6f
JK		 2171 if (ret < 0) {
2172 return ret;
2173 }
ea643051 2174 }
7477cd38
MT		 2175
2176 ret = kvm_put_tscdeadline_msr(x86_cpu);
2177 if (ret < 0) {
2178 return ret;
2179 }
2180
1bc22652 2181 ret = kvm_put_vcpu_events(x86_cpu, level);
b9bec74b 2182 if (ret < 0) {
a0fb002c 2183 return ret;
b9bec74b 2184 }
1bc22652 2185 ret = kvm_put_debugregs(x86_cpu);
b9bec74b 2186 if (ret < 0) {
b0b1d690 2187 return ret;
b9bec74b 2188 }
b0b1d690 2189 /* must be last */
1bc22652 2190 ret = kvm_guest_debug_workarounds(x86_cpu);
b9bec74b 2191 if (ret < 0) {
ff44f1a3 2192 return ret;
b9bec74b 2193 }
05330448
AL		 2194 return 0;
2195}
2196
20d695a9 2197int kvm_arch_get_registers(CPUState *cs)
05330448 2198{
20d695a9 2199 X86CPU *cpu = X86_CPU(cs);
05330448
AL		 2200 int ret;
2201
20d695a9 2202 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
dbaa07c4 2203
1bc22652 2204 ret = kvm_getput_regs(cpu, 0);
b9bec74b 2205 if (ret < 0) {
05330448 2206 return ret;
b9bec74b 2207 }
1bc22652 2208 ret = kvm_get_xsave(cpu);
b9bec74b 2209 if (ret < 0) {
f1665b21 2210 return ret;
b9bec74b 2211 }
1bc22652 2212 ret = kvm_get_xcrs(cpu);
b9bec74b 2213 if (ret < 0) {
05330448 2214 return ret;
b9bec74b 2215 }
1bc22652 2216 ret = kvm_get_sregs(cpu);
b9bec74b 2217 if (ret < 0) {
05330448 2218 return ret;
b9bec74b 2219 }
1bc22652 2220 ret = kvm_get_msrs(cpu);
b9bec74b 2221 if (ret < 0) {
05330448 2222 return ret;
b9bec74b 2223 }
23d02d9b 2224 ret = kvm_get_mp_state(cpu);
b9bec74b 2225 if (ret < 0) {
5a2e3c2e 2226 return ret;
b9bec74b 2227 }
1bc22652 2228 ret = kvm_get_apic(cpu);
680c1c6f
JK		 2229 if (ret < 0) {
2230 return ret;
2231 }
1bc22652 2232 ret = kvm_get_vcpu_events(cpu);
b9bec74b 2233 if (ret < 0) {
a0fb002c 2234 return ret;
b9bec74b 2235 }
1bc22652 2236 ret = kvm_get_debugregs(cpu);
b9bec74b 2237 if (ret < 0) {
ff44f1a3 2238 return ret;
b9bec74b 2239 }
05330448
AL		 2240 return 0;
2241}
2242
20d695a9 2243void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
05330448 2244{
20d695a9
AF		 2245 X86CPU *x86_cpu = X86_CPU(cpu);
2246 CPUX86State *env = &x86_cpu->env;
ce377af3
JK		 2247 int ret;
2248
276ce815 2249 /* Inject NMI */
fc12d72e
PB		 2250 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
2251 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
2252 qemu_mutex_lock_iothread();
2253 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
2254 qemu_mutex_unlock_iothread();
2255 DPRINTF("injected NMI\n");
2256 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
2257 if (ret < 0) {
2258 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
2259 strerror(-ret));
2260 }
2261 }
2262 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
2263 qemu_mutex_lock_iothread();
2264 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
2265 qemu_mutex_unlock_iothread();
2266 DPRINTF("injected SMI\n");
2267 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
2268 if (ret < 0) {
2269 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
2270 strerror(-ret));
2271 }
ce377af3 2272 }
276ce815
LJ		 2273 }
2274
4b8523ee
JK		 2275 if (!kvm_irqchip_in_kernel()) {
2276 qemu_mutex_lock_iothread();
2277 }
2278
e0723c45
PB		 2279 /* Force the VCPU out of its inner loop to process any INIT requests
2280 * or (for userspace APIC, but it is cheap to combine the checks here)
2281 * pending TPR access reports.
2282 */
2283 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
fc12d72e
PB		 2284 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
2285 !(env->hflags & HF_SMM_MASK)) {
2286 cpu->exit_request = 1;
2287 }
2288 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
2289 cpu->exit_request = 1;
2290 }
e0723c45 2291 }
05330448 2292
e0723c45 2293 if (!kvm_irqchip_in_kernel()) {
db1669bc
JK		 2294 /* Try to inject an interrupt if the guest can accept it */
2295 if (run->ready_for_interrupt_injection &&
259186a7 2296 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
db1669bc
JK		 2297 (env->eflags & IF_MASK)) {
2298 int irq;
2299
259186a7 2300 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
db1669bc
JK		 2301 irq = cpu_get_pic_interrupt(env);
2302 if (irq >= 0) {
2303 struct kvm_interrupt intr;
2304
2305 intr.irq = irq;
db1669bc 2306 DPRINTF("injected interrupt %d\n", irq);
1bc22652 2307 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
ce377af3
JK		 2308 if (ret < 0) {
2309 fprintf(stderr,
2310 "KVM: injection failed, interrupt lost (%s)\n",
2311 strerror(-ret));
2312 }
db1669bc
JK		 2313 }
2314 }
05330448 2315
db1669bc
JK		 2316 /* If we have an interrupt but the guest is not ready to receive an
2317 * interrupt, request an interrupt window exit. This will
2318 * cause a return to userspace as soon as the guest is ready to
2319 * receive interrupts. */
259186a7 2320 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
db1669bc
JK		 2321 run->request_interrupt_window = 1;
2322 } else {
2323 run->request_interrupt_window = 0;
2324 }
2325
2326 DPRINTF("setting tpr\n");
02e51483 2327 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
4b8523ee
JK		 2328
2329 qemu_mutex_unlock_iothread();
db1669bc 2330 }
05330448
AL		 2331}
2332
4c663752 2333MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
05330448 2334{
20d695a9
AF		 2335 X86CPU *x86_cpu = X86_CPU(cpu);
2336 CPUX86State *env = &x86_cpu->env;
2337
fc12d72e
PB		 2338 if (run->flags & KVM_RUN_X86_SMM) {
2339 env->hflags |= HF_SMM_MASK;
2340 } else {
2341 env->hflags &= HF_SMM_MASK;
2342 }
b9bec74b 2343 if (run->if_flag) {
05330448 2344 env->eflags |= IF_MASK;
b9bec74b 2345 } else {
05330448 2346 env->eflags &= ~IF_MASK;
b9bec74b 2347 }
4b8523ee
JK		 2348
2349 /* We need to protect the apic state against concurrent accesses from
2350 * different threads in case the userspace irqchip is used. */
2351 if (!kvm_irqchip_in_kernel()) {
2352 qemu_mutex_lock_iothread();
2353 }
02e51483
CF		 2354 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
2355 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
4b8523ee
JK		 2356 if (!kvm_irqchip_in_kernel()) {
2357 qemu_mutex_unlock_iothread();
2358 }
f794aa4a 2359 return cpu_get_mem_attrs(env);
05330448
AL		 2360}
2361
20d695a9 2362int kvm_arch_process_async_events(CPUState *cs)
0af691d7 2363{
20d695a9
AF		 2364 X86CPU *cpu = X86_CPU(cs);
2365 CPUX86State *env = &cpu->env;
232fc23b 2366
259186a7 2367 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
ab443475
JK		 2368 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
2369 assert(env->mcg_cap);
2370
259186a7 2371 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
ab443475 2372
dd1750d7 2373 kvm_cpu_synchronize_state(cs);
ab443475
JK		 2374
2375 if (env->exception_injected == EXCP08_DBLE) {
2376 /* this means triple fault */
2377 qemu_system_reset_request();
fcd7d003 2378 cs->exit_request = 1;
ab443475
JK		 2379 return 0;
2380 }
2381 env->exception_injected = EXCP12_MCHK;
2382 env->has_error_code = 0;
2383
259186a7 2384 cs->halted = 0;
ab443475
JK		 2385 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
2386 env->mp_state = KVM_MP_STATE_RUNNABLE;
2387 }
2388 }
2389
fc12d72e
PB		 2390 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
2391 !(env->hflags & HF_SMM_MASK)) {
e0723c45
PB		 2392 kvm_cpu_synchronize_state(cs);
2393 do_cpu_init(cpu);
2394 }
2395
db1669bc
JK		 2396 if (kvm_irqchip_in_kernel()) {
2397 return 0;
2398 }
2399
259186a7
AF		 2400 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2401 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
02e51483 2402 apic_poll_irq(cpu->apic_state);
5d62c43a 2403 }
259186a7 2404 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
4601f7b0 2405 (env->eflags & IF_MASK)) ||
259186a7
AF		 2406 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2407 cs->halted = 0;
6792a57b 2408 }
259186a7 2409 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
dd1750d7 2410 kvm_cpu_synchronize_state(cs);
232fc23b 2411 do_cpu_sipi(cpu);
0af691d7 2412 }
259186a7
AF		 2413 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
2414 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
dd1750d7 2415 kvm_cpu_synchronize_state(cs);
02e51483 2416 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
d362e757
JK		 2417 env->tpr_access_type);
2418 }
0af691d7 2419
259186a7 2420 return cs->halted;
0af691d7
MT		 2421}
2422
839b5630 2423static int kvm_handle_halt(X86CPU *cpu)
05330448 2424{
259186a7 2425 CPUState *cs = CPU(cpu);
839b5630
AF		 2426 CPUX86State *env = &cpu->env;
2427
259186a7 2428 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
05330448 2429 (env->eflags & IF_MASK)) &&
259186a7
AF		 2430 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2431 cs->halted = 1;
bb4ea393 2432 return EXCP_HLT;
05330448
AL		 2433 }
2434
bb4ea393 2435 return 0;
05330448
AL		 2436}
2437
f7575c96 2438static int kvm_handle_tpr_access(X86CPU *cpu)
d362e757 2439{
f7575c96
AF		 2440 CPUState *cs = CPU(cpu);
2441 struct kvm_run *run = cs->kvm_run;
d362e757 2442
02e51483 2443 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
d362e757
JK		 2444 run->tpr_access.is_write ? TPR_ACCESS_WRITE
2445 : TPR_ACCESS_READ);
2446 return 1;
2447}
2448
f17ec444 2449int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9 2450{
38972938 2451 static const uint8_t int3 = 0xcc;
64bf3f4e 2452
f17ec444
AF		 2453 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
2454 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
e22a25c9 2455 return -EINVAL;
b9bec74b 2456 }
e22a25c9
AL		 2457 return 0;
2458}
2459
f17ec444 2460int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9
AL		 2461{
2462 uint8_t int3;
2463
f17ec444
AF		 2464 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
2465 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
e22a25c9 2466 return -EINVAL;
b9bec74b 2467 }
e22a25c9
AL		 2468 return 0;
2469}
2470
2471static struct {
2472 target_ulong addr;
2473 int len;
2474 int type;
2475} hw_breakpoint[4];
2476
2477static int nb_hw_breakpoint;
2478
2479static int find_hw_breakpoint(target_ulong addr, int len, int type)
2480{
2481 int n;
2482
b9bec74b 2483 for (n = 0; n < nb_hw_breakpoint; n++) {
e22a25c9 2484 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
b9bec74b 2485 (hw_breakpoint[n].len == len || len == -1)) {
e22a25c9 2486 return n;
b9bec74b
JK		 2487 }
2488 }
e22a25c9
AL		 2489 return -1;
2490}
2491
2492int kvm_arch_insert_hw_breakpoint(target_ulong addr,
2493 target_ulong len, int type)
2494{
2495 switch (type) {
2496 case GDB_BREAKPOINT_HW:
2497 len = 1;
2498 break;
2499 case GDB_WATCHPOINT_WRITE:
2500 case GDB_WATCHPOINT_ACCESS:
2501 switch (len) {
2502 case 1:
2503 break;
2504 case 2:
2505 case 4:
2506 case 8:
b9bec74b 2507 if (addr & (len - 1)) {
e22a25c9 2508 return -EINVAL;
b9bec74b 2509 }
e22a25c9
AL		 2510 break;
2511 default:
2512 return -EINVAL;
2513 }
2514 break;
2515 default:
2516 return -ENOSYS;
2517 }
2518
b9bec74b 2519 if (nb_hw_breakpoint == 4) {
e22a25c9 2520 return -ENOBUFS;
b9bec74b
JK		 2521 }
2522 if (find_hw_breakpoint(addr, len, type) >= 0) {
e22a25c9 2523 return -EEXIST;
b9bec74b 2524 }
e22a25c9
AL		 2525 hw_breakpoint[nb_hw_breakpoint].addr = addr;
2526 hw_breakpoint[nb_hw_breakpoint].len = len;
2527 hw_breakpoint[nb_hw_breakpoint].type = type;
2528 nb_hw_breakpoint++;
2529
2530 return 0;
2531}
2532
2533int kvm_arch_remove_hw_breakpoint(target_ulong addr,
2534 target_ulong len, int type)
2535{
2536 int n;
2537
2538 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
b9bec74b 2539 if (n < 0) {
e22a25c9 2540 return -ENOENT;
b9bec74b 2541 }
e22a25c9
AL		 2542 nb_hw_breakpoint--;
2543 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
2544
2545 return 0;
2546}
2547
2548void kvm_arch_remove_all_hw_breakpoints(void)
2549{
2550 nb_hw_breakpoint = 0;
2551}
2552
2553static CPUWatchpoint hw_watchpoint;
2554
a60f24b5 2555static int kvm_handle_debug(X86CPU *cpu,
48405526 2556 struct kvm_debug_exit_arch *arch_info)
e22a25c9 2557{
ed2803da 2558 CPUState *cs = CPU(cpu);
a60f24b5 2559 CPUX86State *env = &cpu->env;
f2574737 2560 int ret = 0;
e22a25c9
AL		 2561 int n;
2562
2563 if (arch_info->exception == 1) {
2564 if (arch_info->dr6 & (1 << 14)) {
ed2803da 2565 if (cs->singlestep_enabled) {
f2574737 2566 ret = EXCP_DEBUG;
b9bec74b 2567 }
e22a25c9 2568 } else {
b9bec74b
JK		 2569 for (n = 0; n < 4; n++) {
2570 if (arch_info->dr6 & (1 << n)) {
e22a25c9
AL		 2571 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
2572 case 0x0:
f2574737 2573 ret = EXCP_DEBUG;
e22a25c9
AL		 2574 break;
2575 case 0x1:
f2574737 2576 ret = EXCP_DEBUG;
ff4700b0 2577 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 2578 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
2579 hw_watchpoint.flags = BP_MEM_WRITE;
2580 break;
2581 case 0x3:
f2574737 2582 ret = EXCP_DEBUG;
ff4700b0 2583 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 2584 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
2585 hw_watchpoint.flags = BP_MEM_ACCESS;
2586 break;
2587 }
b9bec74b
JK		 2588 }
2589 }
e22a25c9 2590 }
ff4700b0 2591 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
f2574737 2592 ret = EXCP_DEBUG;
b9bec74b 2593 }
f2574737 2594 if (ret == 0) {
ff4700b0 2595 cpu_synchronize_state(cs);
48405526 2596 assert(env->exception_injected == -1);
b0b1d690 2597
f2574737 2598 /* pass to guest */
48405526
BS		 2599 env->exception_injected = arch_info->exception;
2600 env->has_error_code = 0;
b0b1d690 2601 }
e22a25c9 2602
f2574737 2603 return ret;
e22a25c9
AL		 2604}
2605
20d695a9 2606void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
e22a25c9
AL		 2607{
2608 const uint8_t type_code[] = {
2609 [GDB_BREAKPOINT_HW] = 0x0,
2610 [GDB_WATCHPOINT_WRITE] = 0x1,
2611 [GDB_WATCHPOINT_ACCESS] = 0x3
2612 };
2613 const uint8_t len_code[] = {
2614 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
2615 };
2616 int n;
2617
a60f24b5 2618 if (kvm_sw_breakpoints_active(cpu)) {
e22a25c9 2619 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
b9bec74b 2620 }
e22a25c9
AL		 2621 if (nb_hw_breakpoint > 0) {
2622 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
2623 dbg->arch.debugreg[7] = 0x0600;
2624 for (n = 0; n < nb_hw_breakpoint; n++) {
2625 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
2626 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
2627 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
95c077c9 2628 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
e22a25c9
AL		 2629 }
2630 }
2631}
4513d923 2632
2a4dac83
JK		 2633static bool host_supports_vmx(void)
2634{
2635 uint32_t ecx, unused;
2636
2637 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
2638 return ecx & CPUID_EXT_VMX;
2639}
2640
2641#define VMX_INVALID_GUEST_STATE 0x80000021
2642
20d695a9 2643int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2a4dac83 2644{
20d695a9 2645 X86CPU *cpu = X86_CPU(cs);
2a4dac83
JK		 2646 uint64_t code;
2647 int ret;
2648
2649 switch (run->exit_reason) {
2650 case KVM_EXIT_HLT:
2651 DPRINTF("handle_hlt\n");
4b8523ee 2652 qemu_mutex_lock_iothread();
839b5630 2653 ret = kvm_handle_halt(cpu);
4b8523ee 2654 qemu_mutex_unlock_iothread();
2a4dac83
JK		 2655 break;
2656 case KVM_EXIT_SET_TPR:
2657 ret = 0;
2658 break;
d362e757 2659 case KVM_EXIT_TPR_ACCESS:
4b8523ee 2660 qemu_mutex_lock_iothread();
f7575c96 2661 ret = kvm_handle_tpr_access(cpu);
4b8523ee 2662 qemu_mutex_unlock_iothread();
d362e757 2663 break;
2a4dac83
JK		 2664 case KVM_EXIT_FAIL_ENTRY:
2665 code = run->fail_entry.hardware_entry_failure_reason;
2666 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
2667 code);
2668 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
2669 fprintf(stderr,
12619721 2670 "\nIf you're running a guest on an Intel machine without "
2a4dac83
JK		 2671 "unrestricted mode\n"
2672 "support, the failure can be most likely due to the guest "
2673 "entering an invalid\n"
2674 "state for Intel VT. For example, the guest maybe running "
2675 "in big real mode\n"
2676 "which is not supported on less recent Intel processors."
2677 "\n\n");
2678 }
2679 ret = -1;
2680 break;
2681 case KVM_EXIT_EXCEPTION:
2682 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
2683 run->ex.exception, run->ex.error_code);
2684 ret = -1;
2685 break;
f2574737
JK		 2686 case KVM_EXIT_DEBUG:
2687 DPRINTF("kvm_exit_debug\n");
4b8523ee 2688 qemu_mutex_lock_iothread();
a60f24b5 2689 ret = kvm_handle_debug(cpu, &run->debug.arch);
4b8523ee 2690 qemu_mutex_unlock_iothread();
f2574737 2691 break;
2a4dac83
JK		 2692 default:
2693 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
2694 ret = -1;
2695 break;
2696 }
2697
2698 return ret;
2699}
2700
20d695a9 2701bool kvm_arch_stop_on_emulation_error(CPUState *cs)
4513d923 2702{
20d695a9
AF		 2703 X86CPU *cpu = X86_CPU(cs);
2704 CPUX86State *env = &cpu->env;
2705
dd1750d7 2706 kvm_cpu_synchronize_state(cs);
b9bec74b
JK		 2707 return !(env->cr[0] & CR0_PE_MASK) ||
2708 ((env->segs[R_CS].selector & 3) != 3);
4513d923 2709}
84b058d7
JK		 2710
2711void kvm_arch_init_irq_routing(KVMState *s)
2712{
2713 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
2714 /* If kernel can't do irq routing, interrupt source
2715 * override 0->2 cannot be set up as required by HPET.
2716 * So we have to disable it.
2717 */
2718 no_hpet = 1;
2719 }
cc7e0ddf 2720 /* We know at this point that we're using the in-kernel
614e41bc 2721 * irqchip, so we can use irqfds, and on x86 we know
f3e1bed8 2722 * we can use msi via irqfd and GSI routing.
cc7e0ddf 2723 */
614e41bc 2724 kvm_msi_via_irqfd_allowed = true;
f3e1bed8 2725 kvm_gsi_routing_allowed = true;
84b058d7 2726}
b139bd30
JK		 2727
2728/* Classic KVM device assignment interface. Will remain x86 only. */
2729int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
2730 uint32_t flags, uint32_t *dev_id)
2731{
2732 struct kvm_assigned_pci_dev dev_data = {
2733 .segnr = dev_addr->domain,
2734 .busnr = dev_addr->bus,
2735 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
2736 .flags = flags,
2737 };
2738 int ret;
2739
2740 dev_data.assigned_dev_id =
2741 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
2742
2743 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
2744 if (ret < 0) {
2745 return ret;
2746 }
2747
2748 *dev_id = dev_data.assigned_dev_id;
2749
2750 return 0;
2751}
2752
2753int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
2754{
2755 struct kvm_assigned_pci_dev dev_data = {
2756 .assigned_dev_id = dev_id,
2757 };
2758
2759 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
2760}
2761
2762static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
2763 uint32_t irq_type, uint32_t guest_irq)
2764{
2765 struct kvm_assigned_irq assigned_irq = {
2766 .assigned_dev_id = dev_id,
2767 .guest_irq = guest_irq,
2768 .flags = irq_type,
2769 };
2770
2771 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
2772 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
2773 } else {
2774 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
2775 }
2776}
2777
2778int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
2779 uint32_t guest_irq)
2780{
2781 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
2782 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
2783
2784 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
2785}
2786
2787int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
2788{
2789 struct kvm_assigned_pci_dev dev_data = {
2790 .assigned_dev_id = dev_id,
2791 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
2792 };
2793
2794 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
2795}
2796
2797static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
2798 uint32_t type)
2799{
2800 struct kvm_assigned_irq assigned_irq = {
2801 .assigned_dev_id = dev_id,
2802 .flags = type,
2803 };
2804
2805 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
2806}
2807
2808int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
2809{
2810 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
2811 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
2812}
2813
2814int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
2815{
2816 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
2817 KVM_DEV_IRQ_GUEST_MSI, virq);
2818}
2819
2820int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
2821{
2822 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
2823 KVM_DEV_IRQ_HOST_MSI);
2824}
2825
2826bool kvm_device_msix_supported(KVMState *s)
2827{
2828 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
2829 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
2830 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
2831}
2832
2833int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
2834 uint32_t nr_vectors)
2835{
2836 struct kvm_assigned_msix_nr msix_nr = {
2837 .assigned_dev_id = dev_id,
2838 .entry_nr = nr_vectors,
2839 };
2840
2841 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
2842}
2843
2844int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
2845 int virq)
2846{
2847 struct kvm_assigned_msix_entry msix_entry = {
2848 .assigned_dev_id = dev_id,
2849 .gsi = virq,
2850 .entry = vector,
2851 };
2852
2853 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
2854}
2855
2856int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
2857{
2858 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
2859 KVM_DEV_IRQ_GUEST_MSIX, 0);
2860}
2861
2862int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
2863{
2864 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
2865 KVM_DEV_IRQ_HOST_MSIX);
2866}
9e03a040
FB		 2867
2868int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
2869 uint64_t address, uint32_t data)
2870{
2871 return 0;
2872}
1850b6b7
EA		 2873
2874int kvm_arch_msi_data_to_gsi(uint32_t data)
2875{
2876 abort();
2877}
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