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x86: optimize EVEX packed integer logical instructions
[binutils.git] / gas / config / tc-i386.c
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b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
82704155 2 Copyright (C) 1989-2019 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
252b5132 20
47926f60
KH		 21/* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus ([email protected]).
3e73aa7c 23 x86_64 support by Jan Hubicka ([email protected])
0f10071e 24 VIA PadLock support by Michal Ludvig ([email protected])
47926f60
KH		 25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
252b5132 27
252b5132 28#include "as.h"
3882b010 29#include "safe-ctype.h"
252b5132 30#include "subsegs.h"
316e2c05 31#include "dwarf2dbg.h"
54cfded0 32#include "dw2gencfi.h"
d2b2c203 33#include "elf/x86-64.h"
40fb9820 34#include "opcodes/i386-init.h"
252b5132 35
41fd2579
L		 36#ifdef HAVE_LIMITS_H
37#include <limits.h>
38#else
39#ifdef HAVE_SYS_PARAM_H
40#include <sys/param.h>
41#endif
42#ifndef INT_MAX
43#define INT_MAX (int) (((unsigned) (-1)) >> 1)
44#endif
45#endif
46
252b5132
RH		 47#ifndef REGISTER_WARNINGS
48#define REGISTER_WARNINGS 1
49#endif
50
c3332e24 51#ifndef INFER_ADDR_PREFIX
eecb386c 52#define INFER_ADDR_PREFIX 1
c3332e24
AM		 53#endif
54
29b0f896
AM		 55#ifndef DEFAULT_ARCH
56#define DEFAULT_ARCH "i386"
246fcdee 57#endif
252b5132 58
edde18a5
AM		 59#ifndef INLINE
60#if __GNUC__ >= 2
61#define INLINE __inline__
62#else
63#define INLINE
64#endif
65#endif
66
6305a203
L		 67/* Prefixes will be emitted in the order defined below.
68 WAIT_PREFIX must be the first prefix since FWAIT is really is an
69 instruction, and so must come before any prefixes.
70 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 71 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 72#define WAIT_PREFIX 0
73#define SEG_PREFIX 1
74#define ADDR_PREFIX 2
75#define DATA_PREFIX 3
c32fa91d 76#define REP_PREFIX 4
42164a71 77#define HLE_PREFIX REP_PREFIX
7e8b059b 78#define BND_PREFIX REP_PREFIX
c32fa91d 79#define LOCK_PREFIX 5
4e9ac44a
L		 80#define REX_PREFIX 6 /* must come last. */
81#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 82
83/* we define the syntax here (modulo base,index,scale syntax) */
84#define REGISTER_PREFIX '%'
85#define IMMEDIATE_PREFIX '$'
86#define ABSOLUTE_PREFIX '*'
87
88/* these are the instruction mnemonic suffixes in AT&T syntax or
89 memory operand size in Intel syntax. */
90#define WORD_MNEM_SUFFIX 'w'
91#define BYTE_MNEM_SUFFIX 'b'
92#define SHORT_MNEM_SUFFIX 's'
93#define LONG_MNEM_SUFFIX 'l'
94#define QWORD_MNEM_SUFFIX 'q'
6305a203
L		 95/* Intel Syntax. Use a non-ascii letter since since it never appears
96 in instructions. */
97#define LONG_DOUBLE_MNEM_SUFFIX '\1'
98
99#define END_OF_INSN '\0'
100
101/*
102 'templates' is for grouping together 'template' structures for opcodes
103 of the same name. This is only used for storing the insns in the grand
104 ole hash table of insns.
105 The templates themselves start at START and range up to (but not including)
106 END.
107 */
108typedef struct
109{
d3ce72d0
NC		 110 const insn_template *start;
111 const insn_template *end;
6305a203
L		 112}
113templates;
114
115/* 386 operand encoding bytes: see 386 book for details of this. */
116typedef struct
117{
118 unsigned int regmem; /* codes register or memory operand */
119 unsigned int reg; /* codes register operand (or extended opcode) */
120 unsigned int mode; /* how to interpret regmem & reg */
121}
122modrm_byte;
123
124/* x86-64 extension prefix. */
125typedef int rex_byte;
126
6305a203
L		 127/* 386 opcode byte to code indirect addressing. */
128typedef struct
129{
130 unsigned base;
131 unsigned index;
132 unsigned scale;
133}
134sib_byte;
135
6305a203
L		 136/* x86 arch names, types and features */
137typedef struct
138{
139 const char *name; /* arch name */
8a2c8fef 140 unsigned int len; /* arch string length */
6305a203
L		 141 enum processor_type type; /* arch type */
142 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 143 unsigned int skip; /* show_arch should skip this. */
6305a203
L		 144}
145arch_entry;
146
293f5f65
L		 147/* Used to turn off indicated flags. */
148typedef struct
149{
150 const char *name; /* arch name */
151 unsigned int len; /* arch string length */
152 i386_cpu_flags flags; /* cpu feature flags */
153}
154noarch_entry;
155
78f12dd3 156static void update_code_flag (int, int);
e3bb37b5
L		 157static void set_code_flag (int);
158static void set_16bit_gcc_code_flag (int);
159static void set_intel_syntax (int);
1efbbeb4 160static void set_intel_mnemonic (int);
db51cc60 161static void set_allow_index_reg (int);
7bab8ab5 162static void set_check (int);
e3bb37b5 163static void set_cpu_arch (int);
6482c264 164#ifdef TE_PE
e3bb37b5 165static void pe_directive_secrel (int);
6482c264 166#endif
e3bb37b5
L		 167static void signed_cons (int);
168static char *output_invalid (int c);
ee86248c
JB		 169static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
170 const char *);
171static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
172 const char *);
a7619375 173static int i386_att_operand (char *);
e3bb37b5 174static int i386_intel_operand (char *, int);
ee86248c
JB		 175static int i386_intel_simplify (expressionS *);
176static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 177static const reg_entry *parse_register (char *, char **);
178static char *parse_insn (char *, char *);
179static char *parse_operands (char *, const char *);
180static void swap_operands (void);
4d456e3d 181static void swap_2_operands (int, int);
e3bb37b5
L		 182static void optimize_imm (void);
183static void optimize_disp (void);
83b16ac6 184static const insn_template *match_template (char);
e3bb37b5
L		 185static int check_string (void);
186static int process_suffix (void);
187static int check_byte_reg (void);
188static int check_long_reg (void);
189static int check_qword_reg (void);
190static int check_word_reg (void);
191static int finalize_imm (void);
192static int process_operands (void);
193static const seg_entry *build_modrm_byte (void);
194static void output_insn (void);
195static void output_imm (fragS *, offsetT);
196static void output_disp (fragS *, offsetT);
29b0f896 197#ifndef I386COFF
e3bb37b5 198static void s_bss (int);
252b5132 199#endif
17d4e2a2
L		 200#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
201static void handle_large_common (int small ATTRIBUTE_UNUSED);
b4a3a7b4
L		 202
203/* GNU_PROPERTY_X86_ISA_1_USED. */
204static unsigned int x86_isa_1_used;
205/* GNU_PROPERTY_X86_FEATURE_2_USED. */
206static unsigned int x86_feature_2_used;
207/* Generate x86 used ISA and feature properties. */
208static unsigned int x86_used_note = DEFAULT_X86_USED_NOTE;
17d4e2a2 209#endif
252b5132 210
a847613f 211static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 212
43234a1e
L		 213/* This struct describes rounding control and SAE in the instruction. */
214struct RC_Operation
215{
216 enum rc_type
217 {
218 rne = 0,
219 rd,
220 ru,
221 rz,
222 saeonly
223 } type;
224 int operand;
225};
226
227static struct RC_Operation rc_op;
228
229/* The struct describes masking, applied to OPERAND in the instruction.
230 MASK is a pointer to the corresponding mask register. ZEROING tells
231 whether merging or zeroing mask is used. */
232struct Mask_Operation
233{
234 const reg_entry *mask;
235 unsigned int zeroing;
236 /* The operand where this operation is associated. */
237 int operand;
238};
239
240static struct Mask_Operation mask_op;
241
242/* The struct describes broadcasting, applied to OPERAND. FACTOR is
243 broadcast factor. */
244struct Broadcast_Operation
245{
8e6e0792 246 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
43234a1e
L		 247 int type;
248
249 /* Index of broadcasted operand. */
250 int operand;
4a1b91ea
L		 251
252 /* Number of bytes to broadcast. */
253 int bytes;
43234a1e
L		 254};
255
256static struct Broadcast_Operation broadcast_op;
257
c0f3af97
L		 258/* VEX prefix. */
259typedef struct
260{
43234a1e
L		 261 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
262 unsigned char bytes[4];
c0f3af97
L		 263 unsigned int length;
264 /* Destination or source register specifier. */
265 const reg_entry *register_specifier;
266} vex_prefix;
267
252b5132 268/* 'md_assemble ()' gathers together information and puts it into a
47926f60 269 i386_insn. */
252b5132 270
520dc8e8
AM		 271union i386_op
272 {
273 expressionS *disps;
274 expressionS *imms;
275 const reg_entry *regs;
276 };
277
a65babc9
L		 278enum i386_error
279 {
86e026a4 280 operand_size_mismatch,
a65babc9
L		 281 operand_type_mismatch,
282 register_type_mismatch,
283 number_of_operands_mismatch,
284 invalid_instruction_suffix,
285 bad_imm4,
a65babc9
L		 286 unsupported_with_intel_mnemonic,
287 unsupported_syntax,
6c30d220
L		 288 unsupported,
289 invalid_vsib_address,
7bab8ab5 290 invalid_vector_register_set,
43234a1e
L		 291 unsupported_vector_index_register,
292 unsupported_broadcast,
43234a1e
L		 293 broadcast_needed,
294 unsupported_masking,
295 mask_not_on_destination,
296 no_default_mask,
297 unsupported_rc_sae,
298 rc_sae_operand_not_last_imm,
299 invalid_register_operand,
a65babc9
L		 300 };
301
252b5132
RH		 302struct _i386_insn
303 {
47926f60 304 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 305 insn_template tm;
252b5132 306
7d5e4556
L		 307 /* SUFFIX holds the instruction size suffix for byte, word, dword
308 or qword, if given. */
252b5132
RH		 309 char suffix;
310
47926f60 311 /* OPERANDS gives the number of given operands. */
252b5132
RH		 312 unsigned int operands;
313
314 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
315 of given register, displacement, memory operands and immediate
47926f60 316 operands. */
252b5132
RH		 317 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
318
319 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 320 use OP[i] for the corresponding operand. */
40fb9820 321 i386_operand_type types[MAX_OPERANDS];
252b5132 322
520dc8e8
AM		 323 /* Displacement expression, immediate expression, or register for each
324 operand. */
325 union i386_op op[MAX_OPERANDS];
252b5132 326
3e73aa7c
JH		 327 /* Flags for operands. */
328 unsigned int flags[MAX_OPERANDS];
329#define Operand_PCrel 1
c48dadc9 330#define Operand_Mem 2
3e73aa7c 331
252b5132 332 /* Relocation type for operand */
f86103b7 333 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 334
252b5132
RH		 335 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
336 the base index byte below. */
337 const reg_entry *base_reg;
338 const reg_entry *index_reg;
339 unsigned int log2_scale_factor;
340
341 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 342 explicit segment overrides are given. */
ce8a8b2f 343 const seg_entry *seg[2];
252b5132 344
8325cc63
JB		 345 /* Copied first memory operand string, for re-checking. */
346 char *memop1_string;
347
252b5132
RH		 348 /* PREFIX holds all the given prefix opcodes (usually null).
349 PREFIXES is the number of prefix opcodes. */
350 unsigned int prefixes;
351 unsigned char prefix[MAX_PREFIXES];
352
b4a3a7b4
L		 353 /* Has MMX register operands. */
354 bfd_boolean has_regmmx;
355
356 /* Has XMM register operands. */
357 bfd_boolean has_regxmm;
358
359 /* Has YMM register operands. */
360 bfd_boolean has_regymm;
361
362 /* Has ZMM register operands. */
363 bfd_boolean has_regzmm;
364
252b5132 365 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 366 addressing modes of this insn are encoded. */
252b5132 367 modrm_byte rm;
3e73aa7c 368 rex_byte rex;
43234a1e 369 rex_byte vrex;
252b5132 370 sib_byte sib;
c0f3af97 371 vex_prefix vex;
b6169b20 372
43234a1e
L		 373 /* Masking attributes. */
374 struct Mask_Operation *mask;
375
376 /* Rounding control and SAE attributes. */
377 struct RC_Operation *rounding;
378
379 /* Broadcasting attributes. */
380 struct Broadcast_Operation *broadcast;
381
382 /* Compressed disp8*N attribute. */
383 unsigned int memshift;
384
86fa6981
L		 385 /* Prefer load or store in encoding. */
386 enum
387 {
388 dir_encoding_default = 0,
389 dir_encoding_load,
64c49ab3
JB		 390 dir_encoding_store,
391 dir_encoding_swap
86fa6981 392 } dir_encoding;
891edac4 393
a501d77e
L		 394 /* Prefer 8bit or 32bit displacement in encoding. */
395 enum
396 {
397 disp_encoding_default = 0,
398 disp_encoding_8bit,
399 disp_encoding_32bit
400 } disp_encoding;
f8a5c266 401
6b6b6807
L		 402 /* Prefer the REX byte in encoding. */
403 bfd_boolean rex_encoding;
404
b6f8c7c4
L		 405 /* Disable instruction size optimization. */
406 bfd_boolean no_optimize;
407
86fa6981
L		 408 /* How to encode vector instructions. */
409 enum
410 {
411 vex_encoding_default = 0,
412 vex_encoding_vex2,
413 vex_encoding_vex3,
414 vex_encoding_evex
415 } vec_encoding;
416
d5de92cf
L		 417 /* REP prefix. */
418 const char *rep_prefix;
419
165de32a
L		 420 /* HLE prefix. */
421 const char *hle_prefix;
42164a71 422
7e8b059b
L		 423 /* Have BND prefix. */
424 const char *bnd_prefix;
425
04ef582a
L		 426 /* Have NOTRACK prefix. */
427 const char *notrack_prefix;
428
891edac4 429 /* Error message. */
a65babc9 430 enum i386_error error;
252b5132
RH		 431 };
432
433typedef struct _i386_insn i386_insn;
434
43234a1e
L		 435/* Link RC type with corresponding string, that'll be looked for in
436 asm. */
437struct RC_name
438{
439 enum rc_type type;
440 const char *name;
441 unsigned int len;
442};
443
444static const struct RC_name RC_NamesTable[] =
445{
446 { rne, STRING_COMMA_LEN ("rn-sae") },
447 { rd, STRING_COMMA_LEN ("rd-sae") },
448 { ru, STRING_COMMA_LEN ("ru-sae") },
449 { rz, STRING_COMMA_LEN ("rz-sae") },
450 { saeonly, STRING_COMMA_LEN ("sae") },
451};
452
252b5132
RH		 453/* List of chars besides those in app.c:symbol_chars that can start an
454 operand. Used to prevent the scrubber eating vital white-space. */
86fa6981 455const char extra_symbol_chars[] = "*%-([{}"
252b5132 456#ifdef LEX_AT
32137342
NC		 457 "@"
458#endif
459#ifdef LEX_QM
460 "?"
252b5132 461#endif
32137342 462 ;
252b5132 463
29b0f896
AM		 464#if (defined (TE_I386AIX) \
465 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 466 && !defined (TE_GNU) \
29b0f896 467 && !defined (TE_LINUX) \
8d63c93e 468 && !defined (TE_NACL) \
29b0f896 469 && !defined (TE_FreeBSD) \
5b806d27 470 && !defined (TE_DragonFly) \
29b0f896 471 && !defined (TE_NetBSD)))
252b5132 472/* This array holds the chars that always start a comment. If the
b3b91714
AM		 473 pre-processor is disabled, these aren't very useful. The option
474 --divide will remove '/' from this list. */
475const char *i386_comment_chars = "#/";
476#define SVR4_COMMENT_CHARS 1
252b5132 477#define PREFIX_SEPARATOR '\\'
252b5132 478
b3b91714
AM		 479#else
480const char *i386_comment_chars = "#";
481#define PREFIX_SEPARATOR '/'
482#endif
483
252b5132
RH		 484/* This array holds the chars that only start a comment at the beginning of
485 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 486 .line and .file directives will appear in the pre-processed output.
487 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 488 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 489 #NO_APP at the beginning of its output.
490 Also note that comments started like this one will always work if
252b5132 491 '/' isn't otherwise defined. */
b3b91714 492const char line_comment_chars[] = "#/";
252b5132 493
63a0b638 494const char line_separator_chars[] = ";";
252b5132 495
ce8a8b2f
AM		 496/* Chars that can be used to separate mant from exp in floating point
497 nums. */
252b5132
RH		 498const char EXP_CHARS[] = "eE";
499
ce8a8b2f
AM		 500/* Chars that mean this number is a floating point constant
501 As in 0f12.456
502 or 0d1.2345e12. */
252b5132
RH		 503const char FLT_CHARS[] = "fFdDxX";
504
ce8a8b2f 505/* Tables for lexical analysis. */
252b5132
RH		 506static char mnemonic_chars[256];
507static char register_chars[256];
508static char operand_chars[256];
509static char identifier_chars[256];
510static char digit_chars[256];
511
ce8a8b2f 512/* Lexical macros. */
252b5132
RH		 513#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
514#define is_operand_char(x) (operand_chars[(unsigned char) x])
515#define is_register_char(x) (register_chars[(unsigned char) x])
516#define is_space_char(x) ((x) == ' ')
517#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
518#define is_digit_char(x) (digit_chars[(unsigned char) x])
519
0234cb7c 520/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 521static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
522
523/* md_assemble() always leaves the strings it's passed unaltered. To
524 effect this we maintain a stack of saved characters that we've smashed
525 with '\0's (indicating end of strings for various sub-fields of the
47926f60 526 assembler instruction). */
252b5132 527static char save_stack[32];
ce8a8b2f 528static char *save_stack_p;
252b5132
RH		 529#define END_STRING_AND_SAVE(s) \
530 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
531#define RESTORE_END_STRING(s) \
532 do { *(s) = *--save_stack_p; } while (0)
533
47926f60 534/* The instruction we're assembling. */
252b5132
RH		 535static i386_insn i;
536
537/* Possible templates for current insn. */
538static const templates *current_templates;
539
31b2323c
L		 540/* Per instruction expressionS buffers: max displacements & immediates. */
541static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
542static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 543
47926f60 544/* Current operand we are working on. */
ee86248c 545static int this_operand = -1;
252b5132 546
3e73aa7c
JH		 547/* We support four different modes. FLAG_CODE variable is used to distinguish
548 these. */
549
550enum flag_code {
551 CODE_32BIT,
552 CODE_16BIT,
553 CODE_64BIT };
554
555static enum flag_code flag_code;
4fa24527 556static unsigned int object_64bit;
862be3fb 557static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 558static int use_rela_relocations = 0;
559
7af8ed2d
NC		 560#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
561 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
562 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
563
351f65ca
L		 564/* The ELF ABI to use. */
565enum x86_elf_abi
566{
567 I386_ABI,
7f56bc95
L		 568 X86_64_ABI,
569 X86_64_X32_ABI
351f65ca
L		 570};
571
572static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 573#endif
351f65ca 574
167ad85b
TG		 575#if defined (TE_PE) || defined (TE_PEP)
576/* Use big object file format. */
577static int use_big_obj = 0;
578#endif
579
8dcea932
L		 580#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
581/* 1 if generating code for a shared library. */
582static int shared = 0;
583#endif
584
47926f60
KH		 585/* 1 for intel syntax,
586 0 if att syntax. */
587static int intel_syntax = 0;
252b5132 588
e89c5eaa
L		 589/* 1 for Intel64 ISA,
590 0 if AMD64 ISA. */
591static int intel64;
592
1efbbeb4
L		 593/* 1 for intel mnemonic,
594 0 if att mnemonic. */
595static int intel_mnemonic = !SYSV386_COMPAT;
596
a60de03c
JB		 597/* 1 if pseudo registers are permitted. */
598static int allow_pseudo_reg = 0;
599
47926f60
KH		 600/* 1 if register prefix % not required. */
601static int allow_naked_reg = 0;
252b5132 602
33eaf5de 603/* 1 if the assembler should add BND prefix for all control-transferring
7e8b059b
L		 604 instructions supporting it, even if this prefix wasn't specified
605 explicitly. */
606static int add_bnd_prefix = 0;
607
ba104c83 608/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 609static int allow_index_reg = 0;
610
d022bddd
IT		 611/* 1 if the assembler should ignore LOCK prefix, even if it was
612 specified explicitly. */
613static int omit_lock_prefix = 0;
614
e4e00185
AS		 615/* 1 if the assembler should encode lfence, mfence, and sfence as
616 "lock addl $0, (%{re}sp)". */
617static int avoid_fence = 0;
618
0cb4071e
L		 619/* 1 if the assembler should generate relax relocations. */
620
621static int generate_relax_relocations
622 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
623
7bab8ab5 624static enum check_kind
daf50ae7 625 {
7bab8ab5
JB		 626 check_none = 0,
627 check_warning,
628 check_error
daf50ae7 629 }
7bab8ab5 630sse_check, operand_check = check_warning;
daf50ae7 631
b6f8c7c4
L		 632/* Optimization:
633 1. Clear the REX_W bit with register operand if possible.
634 2. Above plus use 128bit vector instruction to clear the full vector
635 register.
636 */
637static int optimize = 0;
638
639/* Optimization:
640 1. Clear the REX_W bit with register operand if possible.
641 2. Above plus use 128bit vector instruction to clear the full vector
642 register.
643 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
644 "testb $imm7,%r8".
645 */
646static int optimize_for_space = 0;
647
2ca3ace5
L		 648/* Register prefix used for error message. */
649static const char *register_prefix = "%";
650
47926f60
KH		 651/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
652 leave, push, and pop instructions so that gcc has the same stack
653 frame as in 32 bit mode. */
654static char stackop_size = '\0';
eecb386c 655
12b55ccc
L		 656/* Non-zero to optimize code alignment. */
657int optimize_align_code = 1;
658
47926f60
KH		 659/* Non-zero to quieten some warnings. */
660static int quiet_warnings = 0;
a38cf1db 661
47926f60
KH		 662/* CPU name. */
663static const char *cpu_arch_name = NULL;
6305a203 664static char *cpu_sub_arch_name = NULL;
a38cf1db 665
47926f60 666/* CPU feature flags. */
40fb9820
L		 667static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
668
ccc9c027
L		 669/* If we have selected a cpu we are generating instructions for. */
670static int cpu_arch_tune_set = 0;
671
9103f4f4 672/* Cpu we are generating instructions for. */
fbf3f584 673enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 674
675/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 676static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 677
ccc9c027 678/* CPU instruction set architecture used. */
fbf3f584 679enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 680
9103f4f4 681/* CPU feature flags of instruction set architecture used. */
fbf3f584 682i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 683
fddf5b5b
AM		 684/* If set, conditional jumps are not automatically promoted to handle
685 larger than a byte offset. */
686static unsigned int no_cond_jump_promotion = 0;
687
c0f3af97
L		 688/* Encode SSE instructions with VEX prefix. */
689static unsigned int sse2avx;
690
539f890d
L		 691/* Encode scalar AVX instructions with specific vector length. */
692static enum
693 {
694 vex128 = 0,
695 vex256
696 } avxscalar;
697
03751133
L		 698/* Encode VEX WIG instructions with specific vex.w. */
699static enum
700 {
701 vexw0 = 0,
702 vexw1
703 } vexwig;
704
43234a1e
L		 705/* Encode scalar EVEX LIG instructions with specific vector length. */
706static enum
707 {
708 evexl128 = 0,
709 evexl256,
710 evexl512
711 } evexlig;
712
713/* Encode EVEX WIG instructions with specific evex.w. */
714static enum
715 {
716 evexw0 = 0,
717 evexw1
718 } evexwig;
719
d3d3c6db
IT		 720/* Value to encode in EVEX RC bits, for SAE-only instructions. */
721static enum rc_type evexrcig = rne;
722
29b0f896 723/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 724static symbolS *GOT_symbol;
29b0f896 725
a4447b93
RH		 726/* The dwarf2 return column, adjusted for 32 or 64 bit. */
727unsigned int x86_dwarf2_return_column;
728
729/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
730int x86_cie_data_alignment;
731
252b5132 732/* Interface to relax_segment.
fddf5b5b
AM		 733 There are 3 major relax states for 386 jump insns because the
734 different types of jumps add different sizes to frags when we're
735 figuring out what sort of jump to choose to reach a given label. */
252b5132 736
47926f60 737/* Types. */
93c2a809
AM		 738#define UNCOND_JUMP 0
739#define COND_JUMP 1
740#define COND_JUMP86 2
fddf5b5b 741
47926f60 742/* Sizes. */
252b5132
RH		 743#define CODE16 1
744#define SMALL 0
29b0f896 745#define SMALL16 (SMALL | CODE16)
252b5132 746#define BIG 2
29b0f896 747#define BIG16 (BIG | CODE16)
252b5132
RH		 748
749#ifndef INLINE
750#ifdef __GNUC__
751#define INLINE __inline__
752#else
753#define INLINE
754#endif
755#endif
756
fddf5b5b
AM		 757#define ENCODE_RELAX_STATE(type, size) \
758 ((relax_substateT) (((type) << 2) | (size)))
759#define TYPE_FROM_RELAX_STATE(s) \
760 ((s) >> 2)
761#define DISP_SIZE_FROM_RELAX_STATE(s) \
762 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 763
764/* This table is used by relax_frag to promote short jumps to long
765 ones where necessary. SMALL (short) jumps may be promoted to BIG
766 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
767 don't allow a short jump in a 32 bit code segment to be promoted to
768 a 16 bit offset jump because it's slower (requires data size
769 prefix), and doesn't work, unless the destination is in the bottom
770 64k of the code segment (The top 16 bits of eip are zeroed). */
771
772const relax_typeS md_relax_table[] =
773{
24eab124
AM		 774 /* The fields are:
775 1) most positive reach of this state,
776 2) most negative reach of this state,
93c2a809 777 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 778 4) which index into the table to try if we can't fit into this one. */
252b5132 779
fddf5b5b 780 /* UNCOND_JUMP states. */
93c2a809
AM		 781 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
782 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
783 /* dword jmp adds 4 bytes to frag:
784 0 extra opcode bytes, 4 displacement bytes. */
252b5132 785 {0, 0, 4, 0},
93c2a809
AM		 786 /* word jmp adds 2 byte2 to frag:
787 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 788 {0, 0, 2, 0},
789
93c2a809
AM		 790 /* COND_JUMP states. */
791 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
792 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
793 /* dword conditionals adds 5 bytes to frag:
794 1 extra opcode byte, 4 displacement bytes. */
795 {0, 0, 5, 0},
fddf5b5b 796 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 797 1 extra opcode byte, 2 displacement bytes. */
798 {0, 0, 3, 0},
799
800 /* COND_JUMP86 states. */
801 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
802 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
803 /* dword conditionals adds 5 bytes to frag:
804 1 extra opcode byte, 4 displacement bytes. */
805 {0, 0, 5, 0},
806 /* word conditionals add 4 bytes to frag:
807 1 displacement byte and a 3 byte long branch insn. */
808 {0, 0, 4, 0}
252b5132
RH		 809};
810
9103f4f4
L		 811static const arch_entry cpu_arch[] =
812{
89507696
JB		 813 /* Do not replace the first two entries - i386_target_format()
814 relies on them being there in this order. */
8a2c8fef 815 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
293f5f65 816 CPU_GENERIC32_FLAGS, 0 },
8a2c8fef 817 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
293f5f65 818 CPU_GENERIC64_FLAGS, 0 },
8a2c8fef 819 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
293f5f65 820 CPU_NONE_FLAGS, 0 },
8a2c8fef 821 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
293f5f65 822 CPU_I186_FLAGS, 0 },
8a2c8fef 823 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
293f5f65 824 CPU_I286_FLAGS, 0 },
8a2c8fef 825 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
293f5f65 826 CPU_I386_FLAGS, 0 },
8a2c8fef 827 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
293f5f65 828 CPU_I486_FLAGS, 0 },
8a2c8fef 829 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
293f5f65 830 CPU_I586_FLAGS, 0 },
8a2c8fef 831 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
293f5f65 832 CPU_I686_FLAGS, 0 },
8a2c8fef 833 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
293f5f65 834 CPU_I586_FLAGS, 0 },
8a2c8fef 835 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
293f5f65 836 CPU_PENTIUMPRO_FLAGS, 0 },
8a2c8fef 837 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
293f5f65 838 CPU_P2_FLAGS, 0 },
8a2c8fef 839 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
293f5f65 840 CPU_P3_FLAGS, 0 },
8a2c8fef 841 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
293f5f65 842 CPU_P4_FLAGS, 0 },
8a2c8fef 843 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
293f5f65 844 CPU_CORE_FLAGS, 0 },
8a2c8fef 845 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
293f5f65 846 CPU_NOCONA_FLAGS, 0 },
8a2c8fef 847 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
293f5f65 848 CPU_CORE_FLAGS, 1 },
8a2c8fef 849 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
293f5f65 850 CPU_CORE_FLAGS, 0 },
8a2c8fef 851 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
293f5f65 852 CPU_CORE2_FLAGS, 1 },
8a2c8fef 853 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
293f5f65 854 CPU_CORE2_FLAGS, 0 },
8a2c8fef 855 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
293f5f65 856 CPU_COREI7_FLAGS, 0 },
8a2c8fef 857 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
293f5f65 858 CPU_L1OM_FLAGS, 0 },
7a9068fe 859 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
293f5f65 860 CPU_K1OM_FLAGS, 0 },
81486035 861 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
293f5f65 862 CPU_IAMCU_FLAGS, 0 },
8a2c8fef 863 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
293f5f65 864 CPU_K6_FLAGS, 0 },
8a2c8fef 865 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
293f5f65 866 CPU_K6_2_FLAGS, 0 },
8a2c8fef 867 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
293f5f65 868 CPU_ATHLON_FLAGS, 0 },
8a2c8fef 869 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
293f5f65 870 CPU_K8_FLAGS, 1 },
8a2c8fef 871 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
293f5f65 872 CPU_K8_FLAGS, 0 },
8a2c8fef 873 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
293f5f65 874 CPU_K8_FLAGS, 0 },
8a2c8fef 875 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
293f5f65 876 CPU_AMDFAM10_FLAGS, 0 },
8aedb9fe 877 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
293f5f65 878 CPU_BDVER1_FLAGS, 0 },
8aedb9fe 879 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
293f5f65 880 CPU_BDVER2_FLAGS, 0 },
5e5c50d3 881 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
293f5f65 882 CPU_BDVER3_FLAGS, 0 },
c7b0bd56 883 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
293f5f65 884 CPU_BDVER4_FLAGS, 0 },
029f3522 885 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
293f5f65 886 CPU_ZNVER1_FLAGS, 0 },
a9660a6f
AP		 887 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER,
888 CPU_ZNVER2_FLAGS, 0 },
7b458c12 889 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
293f5f65 890 CPU_BTVER1_FLAGS, 0 },
7b458c12 891 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
293f5f65 892 CPU_BTVER2_FLAGS, 0 },
8a2c8fef 893 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
293f5f65 894 CPU_8087_FLAGS, 0 },
8a2c8fef 895 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
293f5f65 896 CPU_287_FLAGS, 0 },
8a2c8fef 897 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
293f5f65 898 CPU_387_FLAGS, 0 },
1848e567
L		 899 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
900 CPU_687_FLAGS, 0 },
d871f3f4
L		 901 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN,
902 CPU_CMOV_FLAGS, 0 },
903 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN,
904 CPU_FXSR_FLAGS, 0 },
8a2c8fef 905 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
293f5f65 906 CPU_MMX_FLAGS, 0 },
8a2c8fef 907 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
293f5f65 908 CPU_SSE_FLAGS, 0 },
8a2c8fef 909 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
293f5f65 910 CPU_SSE2_FLAGS, 0 },
8a2c8fef 911 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
293f5f65 912 CPU_SSE3_FLAGS, 0 },
8a2c8fef 913 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
293f5f65 914 CPU_SSSE3_FLAGS, 0 },
8a2c8fef 915 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
293f5f65 916 CPU_SSE4_1_FLAGS, 0 },
8a2c8fef 917 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
293f5f65 918 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 919 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
293f5f65 920 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 921 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
293f5f65 922 CPU_AVX_FLAGS, 0 },
6c30d220 923 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
293f5f65 924 CPU_AVX2_FLAGS, 0 },
43234a1e 925 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
293f5f65 926 CPU_AVX512F_FLAGS, 0 },
43234a1e 927 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
293f5f65 928 CPU_AVX512CD_FLAGS, 0 },
43234a1e 929 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
293f5f65 930 CPU_AVX512ER_FLAGS, 0 },
43234a1e 931 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
293f5f65 932 CPU_AVX512PF_FLAGS, 0 },
1dfc6506 933 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
293f5f65 934 CPU_AVX512DQ_FLAGS, 0 },
1dfc6506 935 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
293f5f65 936 CPU_AVX512BW_FLAGS, 0 },
1dfc6506 937 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
293f5f65 938 CPU_AVX512VL_FLAGS, 0 },
8a2c8fef 939 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
293f5f65 940 CPU_VMX_FLAGS, 0 },
8729a6f6 941 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
293f5f65 942 CPU_VMFUNC_FLAGS, 0 },
8a2c8fef 943 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
293f5f65 944 CPU_SMX_FLAGS, 0 },
8a2c8fef 945 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
293f5f65 946 CPU_XSAVE_FLAGS, 0 },
c7b8aa3a 947 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
293f5f65 948 CPU_XSAVEOPT_FLAGS, 0 },
1dfc6506 949 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
293f5f65 950 CPU_XSAVEC_FLAGS, 0 },
1dfc6506 951 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
293f5f65 952 CPU_XSAVES_FLAGS, 0 },
8a2c8fef 953 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
293f5f65 954 CPU_AES_FLAGS, 0 },
8a2c8fef 955 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
293f5f65 956 CPU_PCLMUL_FLAGS, 0 },
8a2c8fef 957 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
293f5f65 958 CPU_PCLMUL_FLAGS, 1 },
c7b8aa3a 959 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
293f5f65 960 CPU_FSGSBASE_FLAGS, 0 },
c7b8aa3a 961 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
293f5f65 962 CPU_RDRND_FLAGS, 0 },
c7b8aa3a 963 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
293f5f65 964 CPU_F16C_FLAGS, 0 },
6c30d220 965 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
293f5f65 966 CPU_BMI2_FLAGS, 0 },
8a2c8fef 967 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
293f5f65 968 CPU_FMA_FLAGS, 0 },
8a2c8fef 969 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
293f5f65 970 CPU_FMA4_FLAGS, 0 },
8a2c8fef 971 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
293f5f65 972 CPU_XOP_FLAGS, 0 },
8a2c8fef 973 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
293f5f65 974 CPU_LWP_FLAGS, 0 },
8a2c8fef 975 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
293f5f65 976 CPU_MOVBE_FLAGS, 0 },
60aa667e 977 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
293f5f65 978 CPU_CX16_FLAGS, 0 },
8a2c8fef 979 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
293f5f65 980 CPU_EPT_FLAGS, 0 },
6c30d220 981 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
293f5f65 982 CPU_LZCNT_FLAGS, 0 },
42164a71 983 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
293f5f65 984 CPU_HLE_FLAGS, 0 },
42164a71 985 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
293f5f65 986 CPU_RTM_FLAGS, 0 },
6c30d220 987 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
293f5f65 988 CPU_INVPCID_FLAGS, 0 },
8a2c8fef 989 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
293f5f65 990 CPU_CLFLUSH_FLAGS, 0 },
22109423 991 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
293f5f65 992 CPU_NOP_FLAGS, 0 },
8a2c8fef 993 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
293f5f65 994 CPU_SYSCALL_FLAGS, 0 },
8a2c8fef 995 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
293f5f65 996 CPU_RDTSCP_FLAGS, 0 },
8a2c8fef 997 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
293f5f65 998 CPU_3DNOW_FLAGS, 0 },
8a2c8fef 999 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
293f5f65 1000 CPU_3DNOWA_FLAGS, 0 },
8a2c8fef 1001 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
293f5f65 1002 CPU_PADLOCK_FLAGS, 0 },
8a2c8fef 1003 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
293f5f65 1004 CPU_SVME_FLAGS, 1 },
8a2c8fef 1005 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
293f5f65 1006 CPU_SVME_FLAGS, 0 },
8a2c8fef 1007 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
293f5f65 1008 CPU_SSE4A_FLAGS, 0 },
8a2c8fef 1009 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
293f5f65 1010 CPU_ABM_FLAGS, 0 },
87973e9f 1011 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
293f5f65 1012 CPU_BMI_FLAGS, 0 },
2a2a0f38 1013 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
293f5f65 1014 CPU_TBM_FLAGS, 0 },
e2e1fcde 1015 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
293f5f65 1016 CPU_ADX_FLAGS, 0 },
e2e1fcde 1017 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
293f5f65 1018 CPU_RDSEED_FLAGS, 0 },
e2e1fcde 1019 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
293f5f65 1020 CPU_PRFCHW_FLAGS, 0 },
5c111e37 1021 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
293f5f65 1022 CPU_SMAP_FLAGS, 0 },
7e8b059b 1023 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
293f5f65 1024 CPU_MPX_FLAGS, 0 },
a0046408 1025 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
293f5f65 1026 CPU_SHA_FLAGS, 0 },
963f3586 1027 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
293f5f65 1028 CPU_CLFLUSHOPT_FLAGS, 0 },
dcf893b5 1029 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
293f5f65 1030 CPU_PREFETCHWT1_FLAGS, 0 },
2cf200a4 1031 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
293f5f65 1032 CPU_SE1_FLAGS, 0 },
c5e7287a 1033 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
293f5f65 1034 CPU_CLWB_FLAGS, 0 },
2cc1b5aa 1035 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
293f5f65 1036 CPU_AVX512IFMA_FLAGS, 0 },
14f195c9 1037 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
293f5f65 1038 CPU_AVX512VBMI_FLAGS, 0 },
920d2ddc
IT		 1039 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
1040 CPU_AVX512_4FMAPS_FLAGS, 0 },
47acf0bd
IT		 1041 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
1042 CPU_AVX512_4VNNIW_FLAGS, 0 },
620214f7
IT		 1043 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
1044 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
53467f57
IT		 1045 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
1046 CPU_AVX512_VBMI2_FLAGS, 0 },
8cfcb765
IT		 1047 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN,
1048 CPU_AVX512_VNNI_FLAGS, 0 },
ee6872be
IT		 1049 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN,
1050 CPU_AVX512_BITALG_FLAGS, 0 },
029f3522 1051 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
293f5f65 1052 CPU_CLZERO_FLAGS, 0 },
9916071f 1053 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
293f5f65 1054 CPU_MWAITX_FLAGS, 0 },
8eab4136 1055 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
293f5f65 1056 CPU_OSPKE_FLAGS, 0 },
8bc52696 1057 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
293f5f65 1058 CPU_RDPID_FLAGS, 0 },
6b40c462
L		 1059 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
1060 CPU_PTWRITE_FLAGS, 0 },
d777820b
IT		 1061 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN,
1062 CPU_IBT_FLAGS, 0 },
1063 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN,
1064 CPU_SHSTK_FLAGS, 0 },
48521003
IT		 1065 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
1066 CPU_GFNI_FLAGS, 0 },
8dcf1fad
IT		 1067 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
1068 CPU_VAES_FLAGS, 0 },
ff1982d5
IT		 1069 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
1070 CPU_VPCLMULQDQ_FLAGS, 0 },
3233d7d0
IT		 1071 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN,
1072 CPU_WBNOINVD_FLAGS, 0 },
be3a8dca
IT		 1073 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN,
1074 CPU_PCONFIG_FLAGS, 0 },
de89d0a3
IT		 1075 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN,
1076 CPU_WAITPKG_FLAGS, 0 },
c48935d7
IT		 1077 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN,
1078 CPU_CLDEMOTE_FLAGS, 0 },
c0a30a9f
L		 1079 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN,
1080 CPU_MOVDIRI_FLAGS, 0 },
1081 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN,
1082 CPU_MOVDIR64B_FLAGS, 0 },
d6aab7a1
XG		 1083 { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN,
1084 CPU_AVX512_BF16_FLAGS, 0 },
9186c494
L		 1085 { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN,
1086 CPU_AVX512_VP2INTERSECT_FLAGS, 0 },
dd455cf5
L		 1087 { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN,
1088 CPU_ENQCMD_FLAGS, 0 },
293f5f65
L		 1089};
1090
1091static const noarch_entry cpu_noarch[] =
1092{
1093 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1848e567
L		 1094 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1095 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1096 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
d871f3f4
L		 1097 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS },
1098 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS },
293f5f65
L		 1099 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1100 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1848e567
L		 1101 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1102 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1103 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1104 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1105 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1106 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
293f5f65 1107 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1848e567 1108 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
144b71e2
L		 1109 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1110 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1111 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1112 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1113 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1114 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1115 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1116 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1117 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
920d2ddc 1118 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
47acf0bd 1119 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
620214f7 1120 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
53467f57 1121 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
8cfcb765 1122 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS },
ee6872be 1123 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS },
d777820b
IT		 1124 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS },
1125 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS },
c0a30a9f
L		 1126 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS },
1127 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS },
d6aab7a1 1128 { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS },
9186c494 1129 { STRING_COMMA_LEN ("noavx512_vp2intersect"), CPU_ANY_SHSTK_FLAGS },
dd455cf5 1130 { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS },
e413e4e9
AM		 1131};
1132
704209c0 1133#ifdef I386COFF
a6c24e68
NC		 1134/* Like s_lcomm_internal in gas/read.c but the alignment string
1135 is allowed to be optional. */
1136
1137static symbolS *
1138pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1139{
1140 addressT align = 0;
1141
1142 SKIP_WHITESPACE ();
1143
7ab9ffdd 1144 if (needs_align
a6c24e68
NC		 1145 && *input_line_pointer == ',')
1146 {
1147 align = parse_align (needs_align - 1);
7ab9ffdd 1148
a6c24e68
NC		 1149 if (align == (addressT) -1)
1150 return NULL;
1151 }
1152 else
1153 {
1154 if (size >= 8)
1155 align = 3;
1156 else if (size >= 4)
1157 align = 2;
1158 else if (size >= 2)
1159 align = 1;
1160 else
1161 align = 0;
1162 }
1163
1164 bss_alloc (symbolP, size, align);
1165 return symbolP;
1166}
1167
704209c0 1168static void
a6c24e68
NC		 1169pe_lcomm (int needs_align)
1170{
1171 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1172}
704209c0 1173#endif
a6c24e68 1174
29b0f896
AM		 1175const pseudo_typeS md_pseudo_table[] =
1176{
1177#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1178 {"align", s_align_bytes, 0},
1179#else
1180 {"align", s_align_ptwo, 0},
1181#endif
1182 {"arch", set_cpu_arch, 0},
1183#ifndef I386COFF
1184 {"bss", s_bss, 0},
a6c24e68
NC		 1185#else
1186 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 1187#endif
1188 {"ffloat", float_cons, 'f'},
1189 {"dfloat", float_cons, 'd'},
1190 {"tfloat", float_cons, 'x'},
1191 {"value", cons, 2},
d182319b 1192 {"slong", signed_cons, 4},
29b0f896
AM		 1193 {"noopt", s_ignore, 0},
1194 {"optim", s_ignore, 0},
1195 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1196 {"code16", set_code_flag, CODE_16BIT},
1197 {"code32", set_code_flag, CODE_32BIT},
da5f19a2 1198#ifdef BFD64
29b0f896 1199 {"code64", set_code_flag, CODE_64BIT},
da5f19a2 1200#endif
29b0f896
AM		 1201 {"intel_syntax", set_intel_syntax, 1},
1202 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 1203 {"intel_mnemonic", set_intel_mnemonic, 1},
1204 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 1205 {"allow_index_reg", set_allow_index_reg, 1},
1206 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 1207 {"sse_check", set_check, 0},
1208 {"operand_check", set_check, 1},
3b22753a
L		 1209#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1210 {"largecomm", handle_large_common, 0},
07a53e5c 1211#else
68d20676 1212 {"file", dwarf2_directive_file, 0},
07a53e5c
RH		 1213 {"loc", dwarf2_directive_loc, 0},
1214 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 1215#endif
6482c264
NC		 1216#ifdef TE_PE
1217 {"secrel32", pe_directive_secrel, 0},
1218#endif
29b0f896
AM		 1219 {0, 0, 0}
1220};
1221
1222/* For interface with expression (). */
1223extern char *input_line_pointer;
1224
1225/* Hash table for instruction mnemonic lookup. */
1226static struct hash_control *op_hash;
1227
1228/* Hash table for register lookup. */
1229static struct hash_control *reg_hash;
1230\f
ce8a8b2f
AM		 1231 /* Various efficient no-op patterns for aligning code labels.
1232 Note: Don't try to assemble the instructions in the comments.
1233 0L and 0w are not legal. */
62a02d25
L		 1234static const unsigned char f32_1[] =
1235 {0x90}; /* nop */
1236static const unsigned char f32_2[] =
1237 {0x66,0x90}; /* xchg %ax,%ax */
1238static const unsigned char f32_3[] =
1239 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1240static const unsigned char f32_4[] =
1241 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
62a02d25
L		 1242static const unsigned char f32_6[] =
1243 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1244static const unsigned char f32_7[] =
1245 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
62a02d25 1246static const unsigned char f16_3[] =
3ae729d5 1247 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
62a02d25 1248static const unsigned char f16_4[] =
3ae729d5
L		 1249 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1250static const unsigned char jump_disp8[] =
1251 {0xeb}; /* jmp disp8 */
1252static const unsigned char jump32_disp32[] =
1253 {0xe9}; /* jmp disp32 */
1254static const unsigned char jump16_disp32[] =
1255 {0x66,0xe9}; /* jmp disp32 */
62a02d25
L		 1256/* 32-bit NOPs patterns. */
1257static const unsigned char *const f32_patt[] = {
3ae729d5 1258 f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7
62a02d25
L		 1259};
1260/* 16-bit NOPs patterns. */
1261static const unsigned char *const f16_patt[] = {
3ae729d5 1262 f32_1, f32_2, f16_3, f16_4
62a02d25
L		 1263};
1264/* nopl (%[re]ax) */
1265static const unsigned char alt_3[] =
1266 {0x0f,0x1f,0x00};
1267/* nopl 0(%[re]ax) */
1268static const unsigned char alt_4[] =
1269 {0x0f,0x1f,0x40,0x00};
1270/* nopl 0(%[re]ax,%[re]ax,1) */
1271static const unsigned char alt_5[] =
1272 {0x0f,0x1f,0x44,0x00,0x00};
1273/* nopw 0(%[re]ax,%[re]ax,1) */
1274static const unsigned char alt_6[] =
1275 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1276/* nopl 0L(%[re]ax) */
1277static const unsigned char alt_7[] =
1278 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1279/* nopl 0L(%[re]ax,%[re]ax,1) */
1280static const unsigned char alt_8[] =
1281 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1282/* nopw 0L(%[re]ax,%[re]ax,1) */
1283static const unsigned char alt_9[] =
1284 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1285/* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1286static const unsigned char alt_10[] =
1287 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
3ae729d5
L		 1288/* data16 nopw %cs:0L(%eax,%eax,1) */
1289static const unsigned char alt_11[] =
1290 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
62a02d25
L		 1291/* 32-bit and 64-bit NOPs patterns. */
1292static const unsigned char *const alt_patt[] = {
1293 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
3ae729d5 1294 alt_9, alt_10, alt_11
62a02d25
L		 1295};
1296
1297/* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1298 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1299
1300static void
1301i386_output_nops (char *where, const unsigned char *const *patt,
1302 int count, int max_single_nop_size)
1303
1304{
3ae729d5
L		 1305 /* Place the longer NOP first. */
1306 int last;
1307 int offset;
3076e594
NC		 1308 const unsigned char *nops;
1309
1310 if (max_single_nop_size < 1)
1311 {
1312 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1313 max_single_nop_size);
1314 return;
1315 }
1316
1317 nops = patt[max_single_nop_size - 1];
3ae729d5
L		 1318
1319 /* Use the smaller one if the requsted one isn't available. */
1320 if (nops == NULL)
62a02d25 1321 {
3ae729d5
L		 1322 max_single_nop_size--;
1323 nops = patt[max_single_nop_size - 1];
62a02d25
L		 1324 }
1325
3ae729d5
L		 1326 last = count % max_single_nop_size;
1327
1328 count -= last;
1329 for (offset = 0; offset < count; offset += max_single_nop_size)
1330 memcpy (where + offset, nops, max_single_nop_size);
1331
1332 if (last)
1333 {
1334 nops = patt[last - 1];
1335 if (nops == NULL)
1336 {
1337 /* Use the smaller one plus one-byte NOP if the needed one
1338 isn't available. */
1339 last--;
1340 nops = patt[last - 1];
1341 memcpy (where + offset, nops, last);
1342 where[offset + last] = *patt[0];
1343 }
1344 else
1345 memcpy (where + offset, nops, last);
1346 }
62a02d25
L		 1347}
1348
3ae729d5
L		 1349static INLINE int
1350fits_in_imm7 (offsetT num)
1351{
1352 return (num & 0x7f) == num;
1353}
1354
1355static INLINE int
1356fits_in_imm31 (offsetT num)
1357{
1358 return (num & 0x7fffffff) == num;
1359}
62a02d25
L		 1360
1361/* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1362 single NOP instruction LIMIT. */
1363
1364void
3ae729d5 1365i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit)
62a02d25 1366{
3ae729d5 1367 const unsigned char *const *patt = NULL;
62a02d25 1368 int max_single_nop_size;
3ae729d5
L		 1369 /* Maximum number of NOPs before switching to jump over NOPs. */
1370 int max_number_of_nops;
62a02d25 1371
3ae729d5 1372 switch (fragP->fr_type)
62a02d25 1373 {
3ae729d5
L		 1374 case rs_fill_nop:
1375 case rs_align_code:
1376 break;
1377 default:
62a02d25
L		 1378 return;
1379 }
1380
ccc9c027
L		 1381 /* We need to decide which NOP sequence to use for 32bit and
1382 64bit. When -mtune= is used:
4eed87de 1383
76bc74dc
L		 1384 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1385 PROCESSOR_GENERIC32, f32_patt will be used.
80b8656c
L		 1386 2. For the rest, alt_patt will be used.
1387
1388 When -mtune= isn't used, alt_patt will be used if
22109423 1389 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1390 be used.
ccc9c027
L		 1391
1392 When -march= or .arch is used, we can't use anything beyond
1393 cpu_arch_isa_flags. */
1394
1395 if (flag_code == CODE_16BIT)
1396 {
3ae729d5
L		 1397 patt = f16_patt;
1398 max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]);
1399 /* Limit number of NOPs to 2 in 16-bit mode. */
1400 max_number_of_nops = 2;
252b5132 1401 }
33fef721 1402 else
ccc9c027 1403 {
fbf3f584 1404 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1405 {
1406 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1407 switch (cpu_arch_tune)
1408 {
1409 case PROCESSOR_UNKNOWN:
1410 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1411 optimize with nops. */
1412 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1413 patt = alt_patt;
ccc9c027
L		 1414 else
1415 patt = f32_patt;
1416 break;
ccc9c027
L		 1417 case PROCESSOR_PENTIUM4:
1418 case PROCESSOR_NOCONA:
ef05d495 1419 case PROCESSOR_CORE:
76bc74dc 1420 case PROCESSOR_CORE2:
bd5295b2 1421 case PROCESSOR_COREI7:
3632d14b 1422 case PROCESSOR_L1OM:
7a9068fe 1423 case PROCESSOR_K1OM:
76bc74dc 1424 case PROCESSOR_GENERIC64:
ccc9c027
L		 1425 case PROCESSOR_K6:
1426 case PROCESSOR_ATHLON:
1427 case PROCESSOR_K8:
4eed87de 1428 case PROCESSOR_AMDFAM10:
8aedb9fe 1429 case PROCESSOR_BD:
029f3522 1430 case PROCESSOR_ZNVER:
7b458c12 1431 case PROCESSOR_BT:
80b8656c 1432 patt = alt_patt;
ccc9c027 1433 break;
76bc74dc 1434 case PROCESSOR_I386:
ccc9c027
L		 1435 case PROCESSOR_I486:
1436 case PROCESSOR_PENTIUM:
2dde1948 1437 case PROCESSOR_PENTIUMPRO:
81486035 1438 case PROCESSOR_IAMCU:
ccc9c027
L		 1439 case PROCESSOR_GENERIC32:
1440 patt = f32_patt;
1441 break;
4eed87de 1442 }
ccc9c027
L		 1443 }
1444 else
1445 {
fbf3f584 1446 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1447 {
1448 case PROCESSOR_UNKNOWN:
e6a14101 1449 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1450 PROCESSOR_UNKNOWN. */
1451 abort ();
1452 break;
1453
76bc74dc 1454 case PROCESSOR_I386:
ccc9c027
L		 1455 case PROCESSOR_I486:
1456 case PROCESSOR_PENTIUM:
81486035 1457 case PROCESSOR_IAMCU:
ccc9c027
L		 1458 case PROCESSOR_K6:
1459 case PROCESSOR_ATHLON:
1460 case PROCESSOR_K8:
4eed87de 1461 case PROCESSOR_AMDFAM10:
8aedb9fe 1462 case PROCESSOR_BD:
029f3522 1463 case PROCESSOR_ZNVER:
7b458c12 1464 case PROCESSOR_BT:
ccc9c027
L		 1465 case PROCESSOR_GENERIC32:
1466 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1467 with nops. */
1468 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1469 patt = alt_patt;
ccc9c027
L		 1470 else
1471 patt = f32_patt;
1472 break;
76bc74dc
L		 1473 case PROCESSOR_PENTIUMPRO:
1474 case PROCESSOR_PENTIUM4:
1475 case PROCESSOR_NOCONA:
1476 case PROCESSOR_CORE:
ef05d495 1477 case PROCESSOR_CORE2:
bd5295b2 1478 case PROCESSOR_COREI7:
3632d14b 1479 case PROCESSOR_L1OM:
7a9068fe 1480 case PROCESSOR_K1OM:
22109423 1481 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1482 patt = alt_patt;
ccc9c027
L		 1483 else
1484 patt = f32_patt;
1485 break;
1486 case PROCESSOR_GENERIC64:
80b8656c 1487 patt = alt_patt;
ccc9c027 1488 break;
4eed87de 1489 }
ccc9c027
L		 1490 }
1491
76bc74dc
L		 1492 if (patt == f32_patt)
1493 {
3ae729d5
L		 1494 max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]);
1495 /* Limit number of NOPs to 2 for older processors. */
1496 max_number_of_nops = 2;
76bc74dc
L		 1497 }
1498 else
1499 {
3ae729d5
L		 1500 max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]);
1501 /* Limit number of NOPs to 7 for newer processors. */
1502 max_number_of_nops = 7;
1503 }
1504 }
1505
1506 if (limit == 0)
1507 limit = max_single_nop_size;
1508
1509 if (fragP->fr_type == rs_fill_nop)
1510 {
1511 /* Output NOPs for .nop directive. */
1512 if (limit > max_single_nop_size)
1513 {
1514 as_bad_where (fragP->fr_file, fragP->fr_line,
1515 _("invalid single nop size: %d "
1516 "(expect within [0, %d])"),
1517 limit, max_single_nop_size);
1518 return;
1519 }
1520 }
1521 else
1522 fragP->fr_var = count;
1523
1524 if ((count / max_single_nop_size) > max_number_of_nops)
1525 {
1526 /* Generate jump over NOPs. */
1527 offsetT disp = count - 2;
1528 if (fits_in_imm7 (disp))
1529 {
1530 /* Use "jmp disp8" if possible. */
1531 count = disp;
1532 where[0] = jump_disp8[0];
1533 where[1] = count;
1534 where += 2;
1535 }
1536 else
1537 {
1538 unsigned int size_of_jump;
1539
1540 if (flag_code == CODE_16BIT)
1541 {
1542 where[0] = jump16_disp32[0];
1543 where[1] = jump16_disp32[1];
1544 size_of_jump = 2;
1545 }
1546 else
1547 {
1548 where[0] = jump32_disp32[0];
1549 size_of_jump = 1;
1550 }
1551
1552 count -= size_of_jump + 4;
1553 if (!fits_in_imm31 (count))
1554 {
1555 as_bad_where (fragP->fr_file, fragP->fr_line,
1556 _("jump over nop padding out of range"));
1557 return;
1558 }
1559
1560 md_number_to_chars (where + size_of_jump, count, 4);
1561 where += size_of_jump + 4;
76bc74dc 1562 }
ccc9c027 1563 }
3ae729d5
L		 1564
1565 /* Generate multiple NOPs. */
1566 i386_output_nops (where, patt, count, limit);
252b5132
RH		 1567}
1568
c6fb90c8 1569static INLINE int
0dfbf9d7 1570operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1571{
0dfbf9d7 1572 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1573 {
1574 case 3:
0dfbf9d7 1575 if (x->array[2])
c6fb90c8 1576 return 0;
1a0670f3 1577 /* Fall through. */
c6fb90c8 1578 case 2:
0dfbf9d7 1579 if (x->array[1])
c6fb90c8 1580 return 0;
1a0670f3 1581 /* Fall through. */
c6fb90c8 1582 case 1:
0dfbf9d7 1583 return !x->array[0];
c6fb90c8
L		 1584 default:
1585 abort ();
1586 }
40fb9820
L		 1587}
1588
c6fb90c8 1589static INLINE void
0dfbf9d7 1590operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1591{
0dfbf9d7 1592 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1593 {
1594 case 3:
0dfbf9d7 1595 x->array[2] = v;
1a0670f3 1596 /* Fall through. */
c6fb90c8 1597 case 2:
0dfbf9d7 1598 x->array[1] = v;
1a0670f3 1599 /* Fall through. */
c6fb90c8 1600 case 1:
0dfbf9d7 1601 x->array[0] = v;
1a0670f3 1602 /* Fall through. */
c6fb90c8
L		 1603 break;
1604 default:
1605 abort ();
1606 }
1607}
40fb9820 1608
c6fb90c8 1609static INLINE int
0dfbf9d7
L		 1610operand_type_equal (const union i386_operand_type *x,
1611 const union i386_operand_type *y)
c6fb90c8 1612{
0dfbf9d7 1613 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1614 {
1615 case 3:
0dfbf9d7 1616 if (x->array[2] != y->array[2])
c6fb90c8 1617 return 0;
1a0670f3 1618 /* Fall through. */
c6fb90c8 1619 case 2:
0dfbf9d7 1620 if (x->array[1] != y->array[1])
c6fb90c8 1621 return 0;
1a0670f3 1622 /* Fall through. */
c6fb90c8 1623 case 1:
0dfbf9d7 1624 return x->array[0] == y->array[0];
c6fb90c8
L		 1625 break;
1626 default:
1627 abort ();
1628 }
1629}
40fb9820 1630
0dfbf9d7
L		 1631static INLINE int
1632cpu_flags_all_zero (const union i386_cpu_flags *x)
1633{
1634 switch (ARRAY_SIZE(x->array))
1635 {
53467f57
IT		 1636 case 4:
1637 if (x->array[3])
1638 return 0;
1639 /* Fall through. */
0dfbf9d7
L		 1640 case 3:
1641 if (x->array[2])
1642 return 0;
1a0670f3 1643 /* Fall through. */
0dfbf9d7
L		 1644 case 2:
1645 if (x->array[1])
1646 return 0;
1a0670f3 1647 /* Fall through. */
0dfbf9d7
L		 1648 case 1:
1649 return !x->array[0];
1650 default:
1651 abort ();
1652 }
1653}
1654
0dfbf9d7
L		 1655static INLINE int
1656cpu_flags_equal (const union i386_cpu_flags *x,
1657 const union i386_cpu_flags *y)
1658{
1659 switch (ARRAY_SIZE(x->array))
1660 {
53467f57
IT		 1661 case 4:
1662 if (x->array[3] != y->array[3])
1663 return 0;
1664 /* Fall through. */
0dfbf9d7
L		 1665 case 3:
1666 if (x->array[2] != y->array[2])
1667 return 0;
1a0670f3 1668 /* Fall through. */
0dfbf9d7
L		 1669 case 2:
1670 if (x->array[1] != y->array[1])
1671 return 0;
1a0670f3 1672 /* Fall through. */
0dfbf9d7
L		 1673 case 1:
1674 return x->array[0] == y->array[0];
1675 break;
1676 default:
1677 abort ();
1678 }
1679}
c6fb90c8
L		 1680
1681static INLINE int
1682cpu_flags_check_cpu64 (i386_cpu_flags f)
1683{
1684 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1685 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1686}
1687
c6fb90c8
L		 1688static INLINE i386_cpu_flags
1689cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1690{
c6fb90c8
L		 1691 switch (ARRAY_SIZE (x.array))
1692 {
53467f57
IT		 1693 case 4:
1694 x.array [3] &= y.array [3];
1695 /* Fall through. */
c6fb90c8
L		 1696 case 3:
1697 x.array [2] &= y.array [2];
1a0670f3 1698 /* Fall through. */
c6fb90c8
L		 1699 case 2:
1700 x.array [1] &= y.array [1];
1a0670f3 1701 /* Fall through. */
c6fb90c8
L		 1702 case 1:
1703 x.array [0] &= y.array [0];
1704 break;
1705 default:
1706 abort ();
1707 }
1708 return x;
1709}
40fb9820 1710
c6fb90c8
L		 1711static INLINE i386_cpu_flags
1712cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1713{
c6fb90c8 1714 switch (ARRAY_SIZE (x.array))
40fb9820 1715 {
53467f57
IT		 1716 case 4:
1717 x.array [3] |= y.array [3];
1718 /* Fall through. */
c6fb90c8
L		 1719 case 3:
1720 x.array [2] |= y.array [2];
1a0670f3 1721 /* Fall through. */
c6fb90c8
L		 1722 case 2:
1723 x.array [1] |= y.array [1];
1a0670f3 1724 /* Fall through. */
c6fb90c8
L		 1725 case 1:
1726 x.array [0] |= y.array [0];
40fb9820
L		 1727 break;
1728 default:
1729 abort ();
1730 }
40fb9820
L		 1731 return x;
1732}
1733
309d3373
JB		 1734static INLINE i386_cpu_flags
1735cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1736{
1737 switch (ARRAY_SIZE (x.array))
1738 {
53467f57
IT		 1739 case 4:
1740 x.array [3] &= ~y.array [3];
1741 /* Fall through. */
309d3373
JB		 1742 case 3:
1743 x.array [2] &= ~y.array [2];
1a0670f3 1744 /* Fall through. */
309d3373
JB		 1745 case 2:
1746 x.array [1] &= ~y.array [1];
1a0670f3 1747 /* Fall through. */
309d3373
JB		 1748 case 1:
1749 x.array [0] &= ~y.array [0];
1750 break;
1751 default:
1752 abort ();
1753 }
1754 return x;
1755}
1756
c0f3af97
L		 1757#define CPU_FLAGS_ARCH_MATCH 0x1
1758#define CPU_FLAGS_64BIT_MATCH 0x2
1759
c0f3af97 1760#define CPU_FLAGS_PERFECT_MATCH \
db12e14e 1761 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
c0f3af97
L		 1762
1763/* Return CPU flags match bits. */
3629bb00 1764
40fb9820 1765static int
d3ce72d0 1766cpu_flags_match (const insn_template *t)
40fb9820 1767{
c0f3af97
L		 1768 i386_cpu_flags x = t->cpu_flags;
1769 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1770
1771 x.bitfield.cpu64 = 0;
1772 x.bitfield.cpuno64 = 0;
1773
0dfbf9d7 1774 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1775 {
1776 /* This instruction is available on all archs. */
db12e14e 1777 match |= CPU_FLAGS_ARCH_MATCH;
c0f3af97 1778 }
3629bb00
L		 1779 else
1780 {
c0f3af97 1781 /* This instruction is available only on some archs. */
3629bb00
L		 1782 i386_cpu_flags cpu = cpu_arch_flags;
1783
ab592e75
JB		 1784 /* AVX512VL is no standalone feature - match it and then strip it. */
1785 if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl)
1786 return match;
1787 x.bitfield.cpuavx512vl = 0;
1788
3629bb00 1789 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1790 if (!cpu_flags_all_zero (&cpu))
1791 {
a5ff0eb2
L		 1792 if (x.bitfield.cpuavx)
1793 {
929f69fa 1794 /* We need to check a few extra flags with AVX. */
b9d49817
JB		 1795 if (cpu.bitfield.cpuavx
1796 && (!t->opcode_modifier.sse2avx || sse2avx)
1797 && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
929f69fa 1798 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
b9d49817
JB		 1799 && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul))
1800 match |= CPU_FLAGS_ARCH_MATCH;
a5ff0eb2 1801 }
929f69fa
JB		 1802 else if (x.bitfield.cpuavx512f)
1803 {
1804 /* We need to check a few extra flags with AVX512F. */
1805 if (cpu.bitfield.cpuavx512f
1806 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1807 && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes)
1808 && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq))
1809 match |= CPU_FLAGS_ARCH_MATCH;
1810 }
a5ff0eb2 1811 else
db12e14e 1812 match |= CPU_FLAGS_ARCH_MATCH;
c0f3af97 1813 }
3629bb00 1814 }
c0f3af97 1815 return match;
40fb9820
L		 1816}
1817
c6fb90c8
L		 1818static INLINE i386_operand_type
1819operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1820{
c6fb90c8
L		 1821 switch (ARRAY_SIZE (x.array))
1822 {
1823 case 3:
1824 x.array [2] &= y.array [2];
1a0670f3 1825 /* Fall through. */
c6fb90c8
L		 1826 case 2:
1827 x.array [1] &= y.array [1];
1a0670f3 1828 /* Fall through. */
c6fb90c8
L		 1829 case 1:
1830 x.array [0] &= y.array [0];
1831 break;
1832 default:
1833 abort ();
1834 }
1835 return x;
40fb9820
L		 1836}
1837
73053c1f
JB		 1838static INLINE i386_operand_type
1839operand_type_and_not (i386_operand_type x, i386_operand_type y)
1840{
1841 switch (ARRAY_SIZE (x.array))
1842 {
1843 case 3:
1844 x.array [2] &= ~y.array [2];
1845 /* Fall through. */
1846 case 2:
1847 x.array [1] &= ~y.array [1];
1848 /* Fall through. */
1849 case 1:
1850 x.array [0] &= ~y.array [0];
1851 break;
1852 default:
1853 abort ();
1854 }
1855 return x;
1856}
1857
c6fb90c8
L		 1858static INLINE i386_operand_type
1859operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1860{
c6fb90c8 1861 switch (ARRAY_SIZE (x.array))
40fb9820 1862 {
c6fb90c8
L		 1863 case 3:
1864 x.array [2] |= y.array [2];
1a0670f3 1865 /* Fall through. */
c6fb90c8
L		 1866 case 2:
1867 x.array [1] |= y.array [1];
1a0670f3 1868 /* Fall through. */
c6fb90c8
L		 1869 case 1:
1870 x.array [0] |= y.array [0];
40fb9820
L		 1871 break;
1872 default:
1873 abort ();
1874 }
c6fb90c8
L		 1875 return x;
1876}
40fb9820 1877
c6fb90c8
L		 1878static INLINE i386_operand_type
1879operand_type_xor (i386_operand_type x, i386_operand_type y)
1880{
1881 switch (ARRAY_SIZE (x.array))
1882 {
1883 case 3:
1884 x.array [2] ^= y.array [2];
1a0670f3 1885 /* Fall through. */
c6fb90c8
L		 1886 case 2:
1887 x.array [1] ^= y.array [1];
1a0670f3 1888 /* Fall through. */
c6fb90c8
L		 1889 case 1:
1890 x.array [0] ^= y.array [0];
1891 break;
1892 default:
1893 abort ();
1894 }
40fb9820
L		 1895 return x;
1896}
1897
40fb9820
L		 1898static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1899static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1900static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1901static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1902static const i386_operand_type anydisp
1903 = OPERAND_TYPE_ANYDISP;
40fb9820 1904static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
43234a1e 1905static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
40fb9820
L		 1906static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1907static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1908static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1909static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1910static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1911static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1912static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1913static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1914static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1915static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1916
1917enum operand_type
1918{
1919 reg,
40fb9820
L		 1920 imm,
1921 disp,
1922 anymem
1923};
1924
c6fb90c8 1925static INLINE int
40fb9820
L		 1926operand_type_check (i386_operand_type t, enum operand_type c)
1927{
1928 switch (c)
1929 {
1930 case reg:
dc821c5f 1931 return t.bitfield.reg;
40fb9820 1932
40fb9820
L		 1933 case imm:
1934 return (t.bitfield.imm8
1935 || t.bitfield.imm8s
1936 || t.bitfield.imm16
1937 || t.bitfield.imm32
1938 || t.bitfield.imm32s
1939 || t.bitfield.imm64);
1940
1941 case disp:
1942 return (t.bitfield.disp8
1943 || t.bitfield.disp16
1944 || t.bitfield.disp32
1945 || t.bitfield.disp32s
1946 || t.bitfield.disp64);
1947
1948 case anymem:
1949 return (t.bitfield.disp8
1950 || t.bitfield.disp16
1951 || t.bitfield.disp32
1952 || t.bitfield.disp32s
1953 || t.bitfield.disp64
1954 || t.bitfield.baseindex);
1955
1956 default:
1957 abort ();
1958 }
2cfe26b6
AM		 1959
1960 return 0;
40fb9820
L		 1961}
1962
7a54636a
L		 1963/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
1964 between operand GIVEN and opeand WANTED for instruction template T. */
5c07affc
L		 1965
1966static INLINE int
7a54636a
L		 1967match_operand_size (const insn_template *t, unsigned int wanted,
1968 unsigned int given)
5c07affc 1969{
3ac21baa
JB		 1970 return !((i.types[given].bitfield.byte
1971 && !t->operand_types[wanted].bitfield.byte)
1972 || (i.types[given].bitfield.word
1973 && !t->operand_types[wanted].bitfield.word)
1974 || (i.types[given].bitfield.dword
1975 && !t->operand_types[wanted].bitfield.dword)
1976 || (i.types[given].bitfield.qword
1977 && !t->operand_types[wanted].bitfield.qword)
1978 || (i.types[given].bitfield.tbyte
1979 && !t->operand_types[wanted].bitfield.tbyte));
5c07affc
L		 1980}
1981
dd40ce22
L		 1982/* Return 1 if there is no conflict in SIMD register between operand
1983 GIVEN and opeand WANTED for instruction template T. */
1b54b8d7
JB		 1984
1985static INLINE int
dd40ce22
L		 1986match_simd_size (const insn_template *t, unsigned int wanted,
1987 unsigned int given)
1b54b8d7 1988{
3ac21baa
JB		 1989 return !((i.types[given].bitfield.xmmword
1990 && !t->operand_types[wanted].bitfield.xmmword)
1991 || (i.types[given].bitfield.ymmword
1992 && !t->operand_types[wanted].bitfield.ymmword)
1993 || (i.types[given].bitfield.zmmword
1994 && !t->operand_types[wanted].bitfield.zmmword));
1b54b8d7
JB		 1995}
1996
7a54636a
L		 1997/* Return 1 if there is no conflict in any size between operand GIVEN
1998 and opeand WANTED for instruction template T. */
5c07affc
L		 1999
2000static INLINE int
dd40ce22
L		 2001match_mem_size (const insn_template *t, unsigned int wanted,
2002 unsigned int given)
5c07affc 2003{
7a54636a 2004 return (match_operand_size (t, wanted, given)
3ac21baa 2005 && !((i.types[given].bitfield.unspecified
af508cb9 2006 && !i.broadcast
3ac21baa
JB		 2007 && !t->operand_types[wanted].bitfield.unspecified)
2008 || (i.types[given].bitfield.fword
2009 && !t->operand_types[wanted].bitfield.fword)
1b54b8d7
JB		 2010 /* For scalar opcode templates to allow register and memory
2011 operands at the same time, some special casing is needed
d6793fa1
JB		 2012 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2013 down-conversion vpmov*. */
3ac21baa 2014 || ((t->operand_types[wanted].bitfield.regsimd
1b54b8d7 2015 && !t->opcode_modifier.broadcast
3ac21baa
JB		 2016 && (t->operand_types[wanted].bitfield.byte
2017 || t->operand_types[wanted].bitfield.word
2018 || t->operand_types[wanted].bitfield.dword
2019 || t->operand_types[wanted].bitfield.qword))
2020 ? (i.types[given].bitfield.xmmword
2021 || i.types[given].bitfield.ymmword
2022 || i.types[given].bitfield.zmmword)
2023 : !match_simd_size(t, wanted, given))));
5c07affc
L		 2024}
2025
3ac21baa
JB		 2026/* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2027 operands for instruction template T, and it has MATCH_REVERSE set if there
2028 is no size conflict on any operands for the template with operands reversed
2029 (and the template allows for reversing in the first place). */
5c07affc 2030
3ac21baa
JB		 2031#define MATCH_STRAIGHT 1
2032#define MATCH_REVERSE 2
2033
2034static INLINE unsigned int
d3ce72d0 2035operand_size_match (const insn_template *t)
5c07affc 2036{
3ac21baa 2037 unsigned int j, match = MATCH_STRAIGHT;
5c07affc
L		 2038
2039 /* Don't check jump instructions. */
2040 if (t->opcode_modifier.jump
2041 || t->opcode_modifier.jumpbyte
2042 || t->opcode_modifier.jumpdword
2043 || t->opcode_modifier.jumpintersegment)
2044 return match;
2045
2046 /* Check memory and accumulator operand size. */
2047 for (j = 0; j < i.operands; j++)
2048 {
1b54b8d7
JB		 2049 if (!i.types[j].bitfield.reg && !i.types[j].bitfield.regsimd
2050 && t->operand_types[j].bitfield.anysize)
5c07affc
L		 2051 continue;
2052
1b54b8d7 2053 if (t->operand_types[j].bitfield.reg
7a54636a 2054 && !match_operand_size (t, j, j))
5c07affc
L		 2055 {
2056 match = 0;
2057 break;
2058 }
2059
1b54b8d7 2060 if (t->operand_types[j].bitfield.regsimd
3ac21baa 2061 && !match_simd_size (t, j, j))
1b54b8d7
JB		 2062 {
2063 match = 0;
2064 break;
2065 }
2066
2067 if (t->operand_types[j].bitfield.acc
7a54636a 2068 && (!match_operand_size (t, j, j) || !match_simd_size (t, j, j)))
1b54b8d7
JB		 2069 {
2070 match = 0;
2071 break;
2072 }
2073
c48dadc9 2074 if ((i.flags[j] & Operand_Mem) && !match_mem_size (t, j, j))
5c07affc
L		 2075 {
2076 match = 0;
2077 break;
2078 }
2079 }
2080
3ac21baa 2081 if (!t->opcode_modifier.d)
891edac4
L		 2082 {
2083mismatch:
3ac21baa
JB		 2084 if (!match)
2085 i.error = operand_size_mismatch;
2086 return match;
891edac4 2087 }
5c07affc
L		 2088
2089 /* Check reverse. */
f5eb1d70 2090 gas_assert (i.operands >= 2 && i.operands <= 3);
5c07affc 2091
f5eb1d70 2092 for (j = 0; j < i.operands; j++)
5c07affc 2093 {
f5eb1d70
JB		 2094 unsigned int given = i.operands - j - 1;
2095
dbbc8b7e 2096 if (t->operand_types[j].bitfield.reg
f5eb1d70 2097 && !match_operand_size (t, j, given))
891edac4 2098 goto mismatch;
5c07affc 2099
dbbc8b7e 2100 if (t->operand_types[j].bitfield.regsimd
f5eb1d70 2101 && !match_simd_size (t, j, given))
dbbc8b7e
JB		 2102 goto mismatch;
2103
2104 if (t->operand_types[j].bitfield.acc
f5eb1d70
JB		 2105 && (!match_operand_size (t, j, given)
2106 || !match_simd_size (t, j, given)))
dbbc8b7e
JB		 2107 goto mismatch;
2108
f5eb1d70 2109 if ((i.flags[given] & Operand_Mem) && !match_mem_size (t, j, given))
891edac4 2110 goto mismatch;
5c07affc
L		 2111 }
2112
3ac21baa 2113 return match | MATCH_REVERSE;
5c07affc
L		 2114}
2115
c6fb90c8 2116static INLINE int
40fb9820
L		 2117operand_type_match (i386_operand_type overlap,
2118 i386_operand_type given)
2119{
2120 i386_operand_type temp = overlap;
2121
2122 temp.bitfield.jumpabsolute = 0;
7d5e4556 2123 temp.bitfield.unspecified = 0;
5c07affc
L		 2124 temp.bitfield.byte = 0;
2125 temp.bitfield.word = 0;
2126 temp.bitfield.dword = 0;
2127 temp.bitfield.fword = 0;
2128 temp.bitfield.qword = 0;
2129 temp.bitfield.tbyte = 0;
2130 temp.bitfield.xmmword = 0;
c0f3af97 2131 temp.bitfield.ymmword = 0;
43234a1e 2132 temp.bitfield.zmmword = 0;
0dfbf9d7 2133 if (operand_type_all_zero (&temp))
891edac4 2134 goto mismatch;
40fb9820 2135
891edac4
L		 2136 if (given.bitfield.baseindex == overlap.bitfield.baseindex
2137 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
2138 return 1;
2139
2140mismatch:
a65babc9 2141 i.error = operand_type_mismatch;
891edac4 2142 return 0;
40fb9820
L		 2143}
2144
7d5e4556 2145/* If given types g0 and g1 are registers they must be of the same type
10c17abd
JB		 2146 unless the expected operand type register overlap is null.
2147 Memory operand size of certain SIMD instructions is also being checked
2148 here. */
40fb9820 2149
c6fb90c8 2150static INLINE int
dc821c5f 2151operand_type_register_match (i386_operand_type g0,
40fb9820 2152 i386_operand_type t0,
40fb9820
L		 2153 i386_operand_type g1,
2154 i386_operand_type t1)
2155{
10c17abd
JB		 2156 if (!g0.bitfield.reg
2157 && !g0.bitfield.regsimd
2158 && (!operand_type_check (g0, anymem)
2159 || g0.bitfield.unspecified
2160 || !t0.bitfield.regsimd))
40fb9820
L		 2161 return 1;
2162
10c17abd
JB		 2163 if (!g1.bitfield.reg
2164 && !g1.bitfield.regsimd
2165 && (!operand_type_check (g1, anymem)
2166 || g1.bitfield.unspecified
2167 || !t1.bitfield.regsimd))
40fb9820
L		 2168 return 1;
2169
dc821c5f
JB		 2170 if (g0.bitfield.byte == g1.bitfield.byte
2171 && g0.bitfield.word == g1.bitfield.word
2172 && g0.bitfield.dword == g1.bitfield.dword
10c17abd
JB		 2173 && g0.bitfield.qword == g1.bitfield.qword
2174 && g0.bitfield.xmmword == g1.bitfield.xmmword
2175 && g0.bitfield.ymmword == g1.bitfield.ymmword
2176 && g0.bitfield.zmmword == g1.bitfield.zmmword)
40fb9820
L		 2177 return 1;
2178
dc821c5f
JB		 2179 if (!(t0.bitfield.byte & t1.bitfield.byte)
2180 && !(t0.bitfield.word & t1.bitfield.word)
2181 && !(t0.bitfield.dword & t1.bitfield.dword)
10c17abd
JB		 2182 && !(t0.bitfield.qword & t1.bitfield.qword)
2183 && !(t0.bitfield.xmmword & t1.bitfield.xmmword)
2184 && !(t0.bitfield.ymmword & t1.bitfield.ymmword)
2185 && !(t0.bitfield.zmmword & t1.bitfield.zmmword))
891edac4
L		 2186 return 1;
2187
a65babc9 2188 i.error = register_type_mismatch;
891edac4
L		 2189
2190 return 0;
40fb9820
L		 2191}
2192
4c692bc7
JB		 2193static INLINE unsigned int
2194register_number (const reg_entry *r)
2195{
2196 unsigned int nr = r->reg_num;
2197
2198 if (r->reg_flags & RegRex)
2199 nr += 8;
2200
200cbe0f
L		 2201 if (r->reg_flags & RegVRex)
2202 nr += 16;
2203
4c692bc7
JB		 2204 return nr;
2205}
2206
252b5132 2207static INLINE unsigned int
40fb9820 2208mode_from_disp_size (i386_operand_type t)
252b5132 2209{
b5014f7a 2210 if (t.bitfield.disp8)
40fb9820
L		 2211 return 1;
2212 else if (t.bitfield.disp16
2213 || t.bitfield.disp32
2214 || t.bitfield.disp32s)
2215 return 2;
2216 else
2217 return 0;
252b5132
RH		 2218}
2219
2220static INLINE int
65879393 2221fits_in_signed_byte (addressT num)
252b5132 2222{
65879393 2223 return num + 0x80 <= 0xff;
47926f60 2224}
252b5132
RH		 2225
2226static INLINE int
65879393 2227fits_in_unsigned_byte (addressT num)
252b5132 2228{
65879393 2229 return num <= 0xff;
47926f60 2230}
252b5132
RH		 2231
2232static INLINE int
65879393 2233fits_in_unsigned_word (addressT num)
252b5132 2234{
65879393 2235 return num <= 0xffff;
47926f60 2236}
252b5132
RH		 2237
2238static INLINE int
65879393 2239fits_in_signed_word (addressT num)
252b5132 2240{
65879393 2241 return num + 0x8000 <= 0xffff;
47926f60 2242}
2a962e6d 2243
3e73aa7c 2244static INLINE int
65879393 2245fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 2246{
2247#ifndef BFD64
2248 return 1;
2249#else
65879393 2250 return num + 0x80000000 <= 0xffffffff;
3e73aa7c
JH		 2251#endif
2252} /* fits_in_signed_long() */
2a962e6d 2253
3e73aa7c 2254static INLINE int
65879393 2255fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 2256{
2257#ifndef BFD64
2258 return 1;
2259#else
65879393 2260 return num <= 0xffffffff;
3e73aa7c
JH		 2261#endif
2262} /* fits_in_unsigned_long() */
252b5132 2263
43234a1e 2264static INLINE int
b5014f7a 2265fits_in_disp8 (offsetT num)
43234a1e
L		 2266{
2267 int shift = i.memshift;
2268 unsigned int mask;
2269
2270 if (shift == -1)
2271 abort ();
2272
2273 mask = (1 << shift) - 1;
2274
2275 /* Return 0 if NUM isn't properly aligned. */
2276 if ((num & mask))
2277 return 0;
2278
2279 /* Check if NUM will fit in 8bit after shift. */
2280 return fits_in_signed_byte (num >> shift);
2281}
2282
a683cc34
SP		 2283static INLINE int
2284fits_in_imm4 (offsetT num)
2285{
2286 return (num & 0xf) == num;
2287}
2288
40fb9820 2289static i386_operand_type
e3bb37b5 2290smallest_imm_type (offsetT num)
252b5132 2291{
40fb9820 2292 i386_operand_type t;
7ab9ffdd 2293
0dfbf9d7 2294 operand_type_set (&t, 0);
40fb9820
L		 2295 t.bitfield.imm64 = 1;
2296
2297 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 2298 {
2299 /* This code is disabled on the 486 because all the Imm1 forms
2300 in the opcode table are slower on the i486. They're the
2301 versions with the implicitly specified single-position
2302 displacement, which has another syntax if you really want to
2303 use that form. */
40fb9820
L		 2304 t.bitfield.imm1 = 1;
2305 t.bitfield.imm8 = 1;
2306 t.bitfield.imm8s = 1;
2307 t.bitfield.imm16 = 1;
2308 t.bitfield.imm32 = 1;
2309 t.bitfield.imm32s = 1;
2310 }
2311 else if (fits_in_signed_byte (num))
2312 {
2313 t.bitfield.imm8 = 1;
2314 t.bitfield.imm8s = 1;
2315 t.bitfield.imm16 = 1;
2316 t.bitfield.imm32 = 1;
2317 t.bitfield.imm32s = 1;
2318 }
2319 else if (fits_in_unsigned_byte (num))
2320 {
2321 t.bitfield.imm8 = 1;
2322 t.bitfield.imm16 = 1;
2323 t.bitfield.imm32 = 1;
2324 t.bitfield.imm32s = 1;
2325 }
2326 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2327 {
2328 t.bitfield.imm16 = 1;
2329 t.bitfield.imm32 = 1;
2330 t.bitfield.imm32s = 1;
2331 }
2332 else if (fits_in_signed_long (num))
2333 {
2334 t.bitfield.imm32 = 1;
2335 t.bitfield.imm32s = 1;
2336 }
2337 else if (fits_in_unsigned_long (num))
2338 t.bitfield.imm32 = 1;
2339
2340 return t;
47926f60 2341}
252b5132 2342
847f7ad4 2343static offsetT
e3bb37b5 2344offset_in_range (offsetT val, int size)
847f7ad4 2345{
508866be 2346 addressT mask;
ba2adb93 2347
847f7ad4
AM		 2348 switch (size)
2349 {
508866be
L		 2350 case 1: mask = ((addressT) 1 << 8) - 1; break;
2351 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 2352 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 2353#ifdef BFD64
2354 case 8: mask = ((addressT) 2 << 63) - 1; break;
2355#endif
47926f60 2356 default: abort ();
847f7ad4
AM		 2357 }
2358
9de868bf
L		 2359#ifdef BFD64
2360 /* If BFD64, sign extend val for 32bit address mode. */
2361 if (flag_code != CODE_64BIT
2362 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 2363 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2364 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 2365#endif
ba2adb93 2366
47926f60 2367 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 2368 {
2369 char buf1[40], buf2[40];
2370
2371 sprint_value (buf1, val);
2372 sprint_value (buf2, val & mask);
2373 as_warn (_("%s shortened to %s"), buf1, buf2);
2374 }
2375 return val & mask;
2376}
2377
c32fa91d
L		 2378enum PREFIX_GROUP
2379{
2380 PREFIX_EXIST = 0,
2381 PREFIX_LOCK,
2382 PREFIX_REP,
04ef582a 2383 PREFIX_DS,
c32fa91d
L		 2384 PREFIX_OTHER
2385};
2386
2387/* Returns
2388 a. PREFIX_EXIST if attempting to add a prefix where one from the
2389 same class already exists.
2390 b. PREFIX_LOCK if lock prefix is added.
2391 c. PREFIX_REP if rep/repne prefix is added.
04ef582a
L		 2392 d. PREFIX_DS if ds prefix is added.
2393 e. PREFIX_OTHER if other prefix is added.
c32fa91d
L		 2394 */
2395
2396static enum PREFIX_GROUP
e3bb37b5 2397add_prefix (unsigned int prefix)
252b5132 2398{
c32fa91d 2399 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 2400 unsigned int q;
252b5132 2401
29b0f896
AM		 2402 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2403 && flag_code == CODE_64BIT)
b1905489 2404 {
161a04f6 2405 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
44846f29
JB		 2406 || (i.prefix[REX_PREFIX] & prefix & REX_R)
2407 || (i.prefix[REX_PREFIX] & prefix & REX_X)
2408 || (i.prefix[REX_PREFIX] & prefix & REX_B))
c32fa91d 2409 ret = PREFIX_EXIST;
b1905489
JB		 2410 q = REX_PREFIX;
2411 }
3e73aa7c 2412 else
b1905489
JB		 2413 {
2414 switch (prefix)
2415 {
2416 default:
2417 abort ();
2418
b1905489 2419 case DS_PREFIX_OPCODE:
04ef582a
L		 2420 ret = PREFIX_DS;
2421 /* Fall through. */
2422 case CS_PREFIX_OPCODE:
b1905489
JB		 2423 case ES_PREFIX_OPCODE:
2424 case FS_PREFIX_OPCODE:
2425 case GS_PREFIX_OPCODE:
2426 case SS_PREFIX_OPCODE:
2427 q = SEG_PREFIX;
2428 break;
2429
2430 case REPNE_PREFIX_OPCODE:
2431 case REPE_PREFIX_OPCODE:
c32fa91d
L		 2432 q = REP_PREFIX;
2433 ret = PREFIX_REP;
2434 break;
2435
b1905489 2436 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 2437 q = LOCK_PREFIX;
2438 ret = PREFIX_LOCK;
b1905489
JB		 2439 break;
2440
2441 case FWAIT_OPCODE:
2442 q = WAIT_PREFIX;
2443 break;
2444
2445 case ADDR_PREFIX_OPCODE:
2446 q = ADDR_PREFIX;
2447 break;
2448
2449 case DATA_PREFIX_OPCODE:
2450 q = DATA_PREFIX;
2451 break;
2452 }
2453 if (i.prefix[q] != 0)
c32fa91d 2454 ret = PREFIX_EXIST;
b1905489 2455 }
252b5132 2456
b1905489 2457 if (ret)
252b5132 2458 {
b1905489
JB		 2459 if (!i.prefix[q])
2460 ++i.prefixes;
2461 i.prefix[q] |= prefix;
252b5132 2462 }
b1905489
JB		 2463 else
2464 as_bad (_("same type of prefix used twice"));
252b5132 2465
252b5132
RH		 2466 return ret;
2467}
2468
2469static void
78f12dd3 2470update_code_flag (int value, int check)
eecb386c 2471{
78f12dd3
L		 2472 PRINTF_LIKE ((*as_error));
2473
1e9cc1c2 2474 flag_code = (enum flag_code) value;
40fb9820
L		 2475 if (flag_code == CODE_64BIT)
2476 {
2477 cpu_arch_flags.bitfield.cpu64 = 1;
2478 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2479 }
2480 else
2481 {
2482 cpu_arch_flags.bitfield.cpu64 = 0;
2483 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2484 }
2485 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2486 {
78f12dd3
L		 2487 if (check)
2488 as_error = as_fatal;
2489 else
2490 as_error = as_bad;
2491 (*as_error) (_("64bit mode not supported on `%s'."),
2492 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2493 }
40fb9820 2494 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2495 {
78f12dd3
L		 2496 if (check)
2497 as_error = as_fatal;
2498 else
2499 as_error = as_bad;
2500 (*as_error) (_("32bit mode not supported on `%s'."),
2501 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2502 }
eecb386c
AM		 2503 stackop_size = '\0';
2504}
2505
78f12dd3
L		 2506static void
2507set_code_flag (int value)
2508{
2509 update_code_flag (value, 0);
2510}
2511
eecb386c 2512static void
e3bb37b5 2513set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2514{
1e9cc1c2 2515 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2516 if (flag_code != CODE_16BIT)
2517 abort ();
2518 cpu_arch_flags.bitfield.cpu64 = 0;
2519 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2520 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2521}
2522
2523static void
e3bb37b5 2524set_intel_syntax (int syntax_flag)
252b5132
RH		 2525{
2526 /* Find out if register prefixing is specified. */
2527 int ask_naked_reg = 0;
2528
2529 SKIP_WHITESPACE ();
29b0f896 2530 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132 2531 {
d02603dc
NC		 2532 char *string;
2533 int e = get_symbol_name (&string);
252b5132 2534
47926f60 2535 if (strcmp (string, "prefix") == 0)
252b5132 2536 ask_naked_reg = 1;
47926f60 2537 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2538 ask_naked_reg = -1;
2539 else
d0b47220 2540 as_bad (_("bad argument to syntax directive."));
d02603dc 2541 (void) restore_line_pointer (e);
252b5132
RH		 2542 }
2543 demand_empty_rest_of_line ();
c3332e24 2544
252b5132
RH		 2545 intel_syntax = syntax_flag;
2546
2547 if (ask_naked_reg == 0)
f86103b7
AM		 2548 allow_naked_reg = (intel_syntax
2549 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2550 else
2551 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2552
ee86248c 2553 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2554
e4a3b5a4 2555 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2556 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2557 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2558}
2559
1efbbeb4
L		 2560static void
2561set_intel_mnemonic (int mnemonic_flag)
2562{
e1d4d893 2563 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2564}
2565
db51cc60
L		 2566static void
2567set_allow_index_reg (int flag)
2568{
2569 allow_index_reg = flag;
2570}
2571
cb19c032 2572static void
7bab8ab5 2573set_check (int what)
cb19c032 2574{
7bab8ab5
JB		 2575 enum check_kind *kind;
2576 const char *str;
2577
2578 if (what)
2579 {
2580 kind = &operand_check;
2581 str = "operand";
2582 }
2583 else
2584 {
2585 kind = &sse_check;
2586 str = "sse";
2587 }
2588
cb19c032
L		 2589 SKIP_WHITESPACE ();
2590
2591 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2592 {
d02603dc
NC		 2593 char *string;
2594 int e = get_symbol_name (&string);
cb19c032
L		 2595
2596 if (strcmp (string, "none") == 0)
7bab8ab5 2597 *kind = check_none;
cb19c032 2598 else if (strcmp (string, "warning") == 0)
7bab8ab5 2599 *kind = check_warning;
cb19c032 2600 else if (strcmp (string, "error") == 0)
7bab8ab5 2601 *kind = check_error;
cb19c032 2602 else
7bab8ab5 2603 as_bad (_("bad argument to %s_check directive."), str);
d02603dc 2604 (void) restore_line_pointer (e);
cb19c032
L		 2605 }
2606 else
7bab8ab5 2607 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2608
2609 demand_empty_rest_of_line ();
2610}
2611
8a9036a4
L		 2612static void
2613check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2614 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2615{
2616#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2617 static const char *arch;
2618
2619 /* Intel LIOM is only supported on ELF. */
2620 if (!IS_ELF)
2621 return;
2622
2623 if (!arch)
2624 {
2625 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2626 use default_arch. */
2627 arch = cpu_arch_name;
2628 if (!arch)
2629 arch = default_arch;
2630 }
2631
81486035
L		 2632 /* If we are targeting Intel MCU, we must enable it. */
2633 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2634 || new_flag.bitfield.cpuiamcu)
2635 return;
2636
3632d14b 2637 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2638 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2639 || new_flag.bitfield.cpul1om)
8a9036a4 2640 return;
76ba9986 2641
7a9068fe
L		 2642 /* If we are targeting Intel K1OM, we must enable it. */
2643 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2644 || new_flag.bitfield.cpuk1om)
2645 return;
2646
8a9036a4
L		 2647 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2648#endif
2649}
2650
e413e4e9 2651static void
e3bb37b5 2652set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2653{
47926f60 2654 SKIP_WHITESPACE ();
e413e4e9 2655
29b0f896 2656 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9 2657 {
d02603dc
NC		 2658 char *string;
2659 int e = get_symbol_name (&string);
91d6fa6a 2660 unsigned int j;
40fb9820 2661 i386_cpu_flags flags;
e413e4e9 2662
91d6fa6a 2663 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2664 {
91d6fa6a 2665 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2666 {
91d6fa6a 2667 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2668
5c6af06e
JB		 2669 if (*string != '.')
2670 {
91d6fa6a 2671 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2672 cpu_sub_arch_name = NULL;
91d6fa6a 2673 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2674 if (flag_code == CODE_64BIT)
2675 {
2676 cpu_arch_flags.bitfield.cpu64 = 1;
2677 cpu_arch_flags.bitfield.cpuno64 = 0;
2678 }
2679 else
2680 {
2681 cpu_arch_flags.bitfield.cpu64 = 0;
2682 cpu_arch_flags.bitfield.cpuno64 = 1;
2683 }
91d6fa6a
NC		 2684 cpu_arch_isa = cpu_arch[j].type;
2685 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2686 if (!cpu_arch_tune_set)
2687 {
2688 cpu_arch_tune = cpu_arch_isa;
2689 cpu_arch_tune_flags = cpu_arch_isa_flags;
2690 }
5c6af06e
JB		 2691 break;
2692 }
40fb9820 2693
293f5f65
L		 2694 flags = cpu_flags_or (cpu_arch_flags,
2695 cpu_arch[j].flags);
81486035 2696
5b64d091 2697 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2698 {
6305a203
L		 2699 if (cpu_sub_arch_name)
2700 {
2701 char *name = cpu_sub_arch_name;
2702 cpu_sub_arch_name = concat (name,
91d6fa6a 2703 cpu_arch[j].name,
1bf57e9f 2704 (const char *) NULL);
6305a203
L		 2705 free (name);
2706 }
2707 else
91d6fa6a 2708 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2709 cpu_arch_flags = flags;
a586129e 2710 cpu_arch_isa_flags = flags;
5c6af06e 2711 }
0089dace
L		 2712 else
2713 cpu_arch_isa_flags
2714 = cpu_flags_or (cpu_arch_isa_flags,
2715 cpu_arch[j].flags);
d02603dc 2716 (void) restore_line_pointer (e);
5c6af06e
JB		 2717 demand_empty_rest_of_line ();
2718 return;
e413e4e9
AM		 2719 }
2720 }
293f5f65
L		 2721
2722 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2723 {
33eaf5de 2724 /* Disable an ISA extension. */
293f5f65
L		 2725 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2726 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2727 {
2728 flags = cpu_flags_and_not (cpu_arch_flags,
2729 cpu_noarch[j].flags);
2730 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2731 {
2732 if (cpu_sub_arch_name)
2733 {
2734 char *name = cpu_sub_arch_name;
2735 cpu_sub_arch_name = concat (name, string,
2736 (const char *) NULL);
2737 free (name);
2738 }
2739 else
2740 cpu_sub_arch_name = xstrdup (string);
2741 cpu_arch_flags = flags;
2742 cpu_arch_isa_flags = flags;
2743 }
2744 (void) restore_line_pointer (e);
2745 demand_empty_rest_of_line ();
2746 return;
2747 }
2748
2749 j = ARRAY_SIZE (cpu_arch);
2750 }
2751
91d6fa6a 2752 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2753 as_bad (_("no such architecture: `%s'"), string);
2754
2755 *input_line_pointer = e;
2756 }
2757 else
2758 as_bad (_("missing cpu architecture"));
2759
fddf5b5b
AM		 2760 no_cond_jump_promotion = 0;
2761 if (*input_line_pointer == ','
29b0f896 2762 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b 2763 {
d02603dc
NC		 2764 char *string;
2765 char e;
2766
2767 ++input_line_pointer;
2768 e = get_symbol_name (&string);
fddf5b5b
AM		 2769
2770 if (strcmp (string, "nojumps") == 0)
2771 no_cond_jump_promotion = 1;
2772 else if (strcmp (string, "jumps") == 0)
2773 ;
2774 else
2775 as_bad (_("no such architecture modifier: `%s'"), string);
2776
d02603dc 2777 (void) restore_line_pointer (e);
fddf5b5b
AM		 2778 }
2779
e413e4e9
AM		 2780 demand_empty_rest_of_line ();
2781}
2782
8a9036a4
L		 2783enum bfd_architecture
2784i386_arch (void)
2785{
3632d14b 2786 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2787 {
2788 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2789 || flag_code != CODE_64BIT)
2790 as_fatal (_("Intel L1OM is 64bit ELF only"));
2791 return bfd_arch_l1om;
2792 }
7a9068fe
L		 2793 else if (cpu_arch_isa == PROCESSOR_K1OM)
2794 {
2795 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2796 || flag_code != CODE_64BIT)
2797 as_fatal (_("Intel K1OM is 64bit ELF only"));
2798 return bfd_arch_k1om;
2799 }
81486035
L		 2800 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2801 {
2802 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2803 || flag_code == CODE_64BIT)
2804 as_fatal (_("Intel MCU is 32bit ELF only"));
2805 return bfd_arch_iamcu;
2806 }
8a9036a4
L		 2807 else
2808 return bfd_arch_i386;
2809}
2810
b9d79e03 2811unsigned long
7016a5d5 2812i386_mach (void)
b9d79e03 2813{
351f65ca 2814 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2815 {
3632d14b 2816 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2817 {
351f65ca
L		 2818 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2819 || default_arch[6] != '\0')
8a9036a4
L		 2820 as_fatal (_("Intel L1OM is 64bit ELF only"));
2821 return bfd_mach_l1om;
2822 }
7a9068fe
L		 2823 else if (cpu_arch_isa == PROCESSOR_K1OM)
2824 {
2825 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2826 || default_arch[6] != '\0')
2827 as_fatal (_("Intel K1OM is 64bit ELF only"));
2828 return bfd_mach_k1om;
2829 }
351f65ca 2830 else if (default_arch[6] == '\0')
8a9036a4 2831 return bfd_mach_x86_64;
351f65ca
L		 2832 else
2833 return bfd_mach_x64_32;
8a9036a4 2834 }
5197d474
L		 2835 else if (!strcmp (default_arch, "i386")
2836 || !strcmp (default_arch, "iamcu"))
81486035
L		 2837 {
2838 if (cpu_arch_isa == PROCESSOR_IAMCU)
2839 {
2840 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2841 as_fatal (_("Intel MCU is 32bit ELF only"));
2842 return bfd_mach_i386_iamcu;
2843 }
2844 else
2845 return bfd_mach_i386_i386;
2846 }
b9d79e03 2847 else
2b5d6a91 2848 as_fatal (_("unknown architecture"));
b9d79e03 2849}
b9d79e03 2850\f
252b5132 2851void
7016a5d5 2852md_begin (void)
252b5132
RH		 2853{
2854 const char *hash_err;
2855
86fa6981
L		 2856 /* Support pseudo prefixes like {disp32}. */
2857 lex_type ['{'] = LEX_BEGIN_NAME;
2858
47926f60 2859 /* Initialize op_hash hash table. */
252b5132
RH		 2860 op_hash = hash_new ();
2861
2862 {
d3ce72d0 2863 const insn_template *optab;
29b0f896 2864 templates *core_optab;
252b5132 2865
47926f60
KH		 2866 /* Setup for loop. */
2867 optab = i386_optab;
add39d23 2868 core_optab = XNEW (templates);
252b5132
RH		 2869 core_optab->start = optab;
2870
2871 while (1)
2872 {
2873 ++optab;
2874 if (optab->name == NULL
2875 || strcmp (optab->name, (optab - 1)->name) != 0)
2876 {
2877 /* different name --> ship out current template list;
47926f60 2878 add to hash table; & begin anew. */
252b5132
RH		 2879 core_optab->end = optab;
2880 hash_err = hash_insert (op_hash,
2881 (optab - 1)->name,
5a49b8ac 2882 (void *) core_optab);
252b5132
RH		 2883 if (hash_err)
2884 {
b37df7c4 2885 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2886 (optab - 1)->name,
2887 hash_err);
2888 }
2889 if (optab->name == NULL)
2890 break;
add39d23 2891 core_optab = XNEW (templates);
252b5132
RH		 2892 core_optab->start = optab;
2893 }
2894 }
2895 }
2896
47926f60 2897 /* Initialize reg_hash hash table. */
252b5132
RH		 2898 reg_hash = hash_new ();
2899 {
29b0f896 2900 const reg_entry *regtab;
c3fe08fa 2901 unsigned int regtab_size = i386_regtab_size;
252b5132 2902
c3fe08fa 2903 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2904 {
5a49b8ac 2905 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2906 if (hash_err)
b37df7c4 2907 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2908 regtab->reg_name,
2909 hash_err);
252b5132
RH		 2910 }
2911 }
2912
47926f60 2913 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2914 {
29b0f896
AM		 2915 int c;
2916 char *p;
252b5132
RH		 2917
2918 for (c = 0; c < 256; c++)
2919 {
3882b010 2920 if (ISDIGIT (c))
252b5132
RH		 2921 {
2922 digit_chars[c] = c;
2923 mnemonic_chars[c] = c;
2924 register_chars[c] = c;
2925 operand_chars[c] = c;
2926 }
3882b010 2927 else if (ISLOWER (c))
252b5132
RH		 2928 {
2929 mnemonic_chars[c] = c;
2930 register_chars[c] = c;
2931 operand_chars[c] = c;
2932 }
3882b010 2933 else if (ISUPPER (c))
252b5132 2934 {
3882b010 2935 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2936 register_chars[c] = mnemonic_chars[c];
2937 operand_chars[c] = c;
2938 }
43234a1e 2939 else if (c == '{' || c == '}')
86fa6981
L		 2940 {
2941 mnemonic_chars[c] = c;
2942 operand_chars[c] = c;
2943 }
252b5132 2944
3882b010 2945 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2946 identifier_chars[c] = c;
2947 else if (c >= 128)
2948 {
2949 identifier_chars[c] = c;
2950 operand_chars[c] = c;
2951 }
2952 }
2953
2954#ifdef LEX_AT
2955 identifier_chars['@'] = '@';
32137342
NC		 2956#endif
2957#ifdef LEX_QM
2958 identifier_chars['?'] = '?';
2959 operand_chars['?'] = '?';
252b5132 2960#endif
252b5132 2961 digit_chars['-'] = '-';
c0f3af97 2962 mnemonic_chars['_'] = '_';
791fe849 2963 mnemonic_chars['-'] = '-';
0003779b 2964 mnemonic_chars['.'] = '.';
252b5132
RH		 2965 identifier_chars['_'] = '_';
2966 identifier_chars['.'] = '.';
2967
2968 for (p = operand_special_chars; *p != '\0'; p++)
2969 operand_chars[(unsigned char) *p] = *p;
2970 }
2971
a4447b93
RH		 2972 if (flag_code == CODE_64BIT)
2973 {
ca19b261
KT		 2974#if defined (OBJ_COFF) && defined (TE_PE)
2975 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2976 ? 32 : 16);
2977#else
a4447b93 2978 x86_dwarf2_return_column = 16;
ca19b261 2979#endif
61ff971f 2980 x86_cie_data_alignment = -8;
a4447b93
RH		 2981 }
2982 else
2983 {
2984 x86_dwarf2_return_column = 8;
2985 x86_cie_data_alignment = -4;
2986 }
252b5132
RH		 2987}
2988
2989void
e3bb37b5 2990i386_print_statistics (FILE *file)
252b5132
RH		 2991{
2992 hash_print_statistics (file, "i386 opcode", op_hash);
2993 hash_print_statistics (file, "i386 register", reg_hash);
2994}
2995\f
252b5132
RH		 2996#ifdef DEBUG386
2997
ce8a8b2f 2998/* Debugging routines for md_assemble. */
d3ce72d0 2999static void pte (insn_template *);
40fb9820 3000static void pt (i386_operand_type);
e3bb37b5
L		 3001static void pe (expressionS *);
3002static void ps (symbolS *);
252b5132
RH		 3003
3004static void
2c703856 3005pi (const char *line, i386_insn *x)
252b5132 3006{
09137c09 3007 unsigned int j;
252b5132
RH		 3008
3009 fprintf (stdout, "%s: template ", line);
3010 pte (&x->tm);
09f131f2
JH		 3011 fprintf (stdout, " address: base %s index %s scale %x\n",
3012 x->base_reg ? x->base_reg->reg_name : "none",
3013 x->index_reg ? x->index_reg->reg_name : "none",
3014 x->log2_scale_factor);
3015 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 3016 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 3017 fprintf (stdout, " sib: base %x index %x scale %x\n",
3018 x->sib.base, x->sib.index, x->sib.scale);
3019 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 3020 (x->rex & REX_W) != 0,
3021 (x->rex & REX_R) != 0,
3022 (x->rex & REX_X) != 0,
3023 (x->rex & REX_B) != 0);
09137c09 3024 for (j = 0; j < x->operands; j++)
252b5132 3025 {
09137c09
SP		 3026 fprintf (stdout, " #%d: ", j + 1);
3027 pt (x->types[j]);
252b5132 3028 fprintf (stdout, "\n");
dc821c5f 3029 if (x->types[j].bitfield.reg
09137c09 3030 || x->types[j].bitfield.regmmx
1b54b8d7 3031 || x->types[j].bitfield.regsimd
09137c09
SP		 3032 || x->types[j].bitfield.sreg2
3033 || x->types[j].bitfield.sreg3
3034 || x->types[j].bitfield.control
3035 || x->types[j].bitfield.debug
3036 || x->types[j].bitfield.test)
3037 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
3038 if (operand_type_check (x->types[j], imm))
3039 pe (x->op[j].imms);
3040 if (operand_type_check (x->types[j], disp))
3041 pe (x->op[j].disps);
252b5132
RH		 3042 }
3043}
3044
3045static void
d3ce72d0 3046pte (insn_template *t)
252b5132 3047{
09137c09 3048 unsigned int j;
252b5132 3049 fprintf (stdout, " %d operands ", t->operands);
47926f60 3050 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 3051 if (t->extension_opcode != None)
3052 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 3053 if (t->opcode_modifier.d)
252b5132 3054 fprintf (stdout, "D");
40fb9820 3055 if (t->opcode_modifier.w)
252b5132
RH		 3056 fprintf (stdout, "W");
3057 fprintf (stdout, "\n");
09137c09 3058 for (j = 0; j < t->operands; j++)
252b5132 3059 {
09137c09
SP		 3060 fprintf (stdout, " #%d type ", j + 1);
3061 pt (t->operand_types[j]);
252b5132
RH		 3062 fprintf (stdout, "\n");
3063 }
3064}
3065
3066static void
e3bb37b5 3067pe (expressionS *e)
252b5132 3068{
24eab124 3069 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 3070 fprintf (stdout, " add_number %ld (%lx)\n",
3071 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 3072 if (e->X_add_symbol)
3073 {
3074 fprintf (stdout, " add_symbol ");
3075 ps (e->X_add_symbol);
3076 fprintf (stdout, "\n");
3077 }
3078 if (e->X_op_symbol)
3079 {
3080 fprintf (stdout, " op_symbol ");
3081 ps (e->X_op_symbol);
3082 fprintf (stdout, "\n");
3083 }
3084}
3085
3086static void
e3bb37b5 3087ps (symbolS *s)
252b5132
RH		 3088{
3089 fprintf (stdout, "%s type %s%s",
3090 S_GET_NAME (s),
3091 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
3092 segment_name (S_GET_SEGMENT (s)));
3093}
3094
7b81dfbb 3095static struct type_name
252b5132 3096 {
40fb9820
L		 3097 i386_operand_type mask;
3098 const char *name;
252b5132 3099 }
7b81dfbb 3100const type_names[] =
252b5132 3101{
40fb9820
L		 3102 { OPERAND_TYPE_REG8, "r8" },
3103 { OPERAND_TYPE_REG16, "r16" },
3104 { OPERAND_TYPE_REG32, "r32" },
3105 { OPERAND_TYPE_REG64, "r64" },
2c703856
JB		 3106 { OPERAND_TYPE_ACC8, "acc8" },
3107 { OPERAND_TYPE_ACC16, "acc16" },
3108 { OPERAND_TYPE_ACC32, "acc32" },
3109 { OPERAND_TYPE_ACC64, "acc64" },
40fb9820
L		 3110 { OPERAND_TYPE_IMM8, "i8" },
3111 { OPERAND_TYPE_IMM8, "i8s" },
3112 { OPERAND_TYPE_IMM16, "i16" },
3113 { OPERAND_TYPE_IMM32, "i32" },
3114 { OPERAND_TYPE_IMM32S, "i32s" },
3115 { OPERAND_TYPE_IMM64, "i64" },
3116 { OPERAND_TYPE_IMM1, "i1" },
3117 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
3118 { OPERAND_TYPE_DISP8, "d8" },
3119 { OPERAND_TYPE_DISP16, "d16" },
3120 { OPERAND_TYPE_DISP32, "d32" },
3121 { OPERAND_TYPE_DISP32S, "d32s" },
3122 { OPERAND_TYPE_DISP64, "d64" },
3123 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
3124 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
3125 { OPERAND_TYPE_CONTROL, "control reg" },
3126 { OPERAND_TYPE_TEST, "test reg" },
3127 { OPERAND_TYPE_DEBUG, "debug reg" },
3128 { OPERAND_TYPE_FLOATREG, "FReg" },
3129 { OPERAND_TYPE_FLOATACC, "FAcc" },
3130 { OPERAND_TYPE_SREG2, "SReg2" },
3131 { OPERAND_TYPE_SREG3, "SReg3" },
40fb9820
L		 3132 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
3133 { OPERAND_TYPE_REGMMX, "rMMX" },
3134 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 3135 { OPERAND_TYPE_REGYMM, "rYMM" },
43234a1e
L		 3136 { OPERAND_TYPE_REGZMM, "rZMM" },
3137 { OPERAND_TYPE_REGMASK, "Mask reg" },
40fb9820 3138 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 3139};
3140
3141static void
40fb9820 3142pt (i386_operand_type t)
252b5132 3143{
40fb9820 3144 unsigned int j;
c6fb90c8 3145 i386_operand_type a;
252b5132 3146
40fb9820 3147 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 3148 {
3149 a = operand_type_and (t, type_names[j].mask);
2c703856 3150 if (operand_type_equal (&a, &type_names[j].mask))
c6fb90c8
L		 3151 fprintf (stdout, "%s, ", type_names[j].name);
3152 }
252b5132
RH		 3153 fflush (stdout);
3154}
3155
3156#endif /* DEBUG386 */
3157\f
252b5132 3158static bfd_reloc_code_real_type
3956db08 3159reloc (unsigned int size,
64e74474
AM		 3160 int pcrel,
3161 int sign,
3162 bfd_reloc_code_real_type other)
252b5132 3163{
47926f60 3164 if (other != NO_RELOC)
3956db08 3165 {
91d6fa6a 3166 reloc_howto_type *rel;
3956db08
JB		 3167
3168 if (size == 8)
3169 switch (other)
3170 {
64e74474
AM		 3171 case BFD_RELOC_X86_64_GOT32:
3172 return BFD_RELOC_X86_64_GOT64;
3173 break;
553d1284
L		 3174 case BFD_RELOC_X86_64_GOTPLT64:
3175 return BFD_RELOC_X86_64_GOTPLT64;
3176 break;
64e74474
AM		 3177 case BFD_RELOC_X86_64_PLTOFF64:
3178 return BFD_RELOC_X86_64_PLTOFF64;
3179 break;
3180 case BFD_RELOC_X86_64_GOTPC32:
3181 other = BFD_RELOC_X86_64_GOTPC64;
3182 break;
3183 case BFD_RELOC_X86_64_GOTPCREL:
3184 other = BFD_RELOC_X86_64_GOTPCREL64;
3185 break;
3186 case BFD_RELOC_X86_64_TPOFF32:
3187 other = BFD_RELOC_X86_64_TPOFF64;
3188 break;
3189 case BFD_RELOC_X86_64_DTPOFF32:
3190 other = BFD_RELOC_X86_64_DTPOFF64;
3191 break;
3192 default:
3193 break;
3956db08 3194 }
e05278af 3195
8ce3d284 3196#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 3197 if (other == BFD_RELOC_SIZE32)
3198 {
3199 if (size == 8)
1ab668bf 3200 other = BFD_RELOC_SIZE64;
8fd4256d 3201 if (pcrel)
1ab668bf
AM		 3202 {
3203 as_bad (_("there are no pc-relative size relocations"));
3204 return NO_RELOC;
3205 }
8fd4256d 3206 }
8ce3d284 3207#endif
8fd4256d 3208
e05278af 3209 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 3210 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 3211 sign = -1;
3212
91d6fa6a
NC		 3213 rel = bfd_reloc_type_lookup (stdoutput, other);
3214 if (!rel)
3956db08 3215 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 3216 else if (size != bfd_get_reloc_size (rel))
3956db08 3217 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 3218 bfd_get_reloc_size (rel),
3956db08 3219 size);
91d6fa6a 3220 else if (pcrel && !rel->pc_relative)
3956db08 3221 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 3222 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 3223 && !sign)
91d6fa6a 3224 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 3225 && sign > 0))
3956db08
JB		 3226 as_bad (_("relocated field and relocation type differ in signedness"));
3227 else
3228 return other;
3229 return NO_RELOC;
3230 }
252b5132
RH		 3231
3232 if (pcrel)
3233 {
3e73aa7c 3234 if (!sign)
3956db08 3235 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 3236 switch (size)
3237 {
3238 case 1: return BFD_RELOC_8_PCREL;
3239 case 2: return BFD_RELOC_16_PCREL;
d258b828 3240 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 3241 case 8: return BFD_RELOC_64_PCREL;
252b5132 3242 }
3956db08 3243 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 3244 }
3245 else
3246 {
3956db08 3247 if (sign > 0)
e5cb08ac 3248 switch (size)
3e73aa7c
JH		 3249 {
3250 case 4: return BFD_RELOC_X86_64_32S;
3251 }
3252 else
3253 switch (size)
3254 {
3255 case 1: return BFD_RELOC_8;
3256 case 2: return BFD_RELOC_16;
3257 case 4: return BFD_RELOC_32;
3258 case 8: return BFD_RELOC_64;
3259 }
3956db08
JB		 3260 as_bad (_("cannot do %s %u byte relocation"),
3261 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 3262 }
3263
0cc9e1d3 3264 return NO_RELOC;
252b5132
RH		 3265}
3266
47926f60
KH		 3267/* Here we decide which fixups can be adjusted to make them relative to
3268 the beginning of the section instead of the symbol. Basically we need
3269 to make sure that the dynamic relocations are done correctly, so in
3270 some cases we force the original symbol to be used. */
3271
252b5132 3272int
e3bb37b5 3273tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 3274{
6d249963 3275#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 3276 if (!IS_ELF)
31312f95
AM		 3277 return 1;
3278
a161fe53
AM		 3279 /* Don't adjust pc-relative references to merge sections in 64-bit
3280 mode. */
3281 if (use_rela_relocations
3282 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3283 && fixP->fx_pcrel)
252b5132 3284 return 0;
31312f95 3285
8d01d9a9
AJ		 3286 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3287 and changed later by validate_fix. */
3288 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3289 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3290 return 0;
3291
8fd4256d
L		 3292 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3293 for size relocations. */
3294 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3295 || fixP->fx_r_type == BFD_RELOC_SIZE64
3296 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 3297 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3298 || fixP->fx_r_type == BFD_RELOC_386_GOT32
02a86693 3299 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
13ae64f3
JJ		 3300 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3301 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3302 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3303 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 3304 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3305 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 3306 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3307 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 3308 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3309 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 3310 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3311 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 3312 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
56ceb5b5
L		 3313 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3314 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
bffbf940
JJ		 3315 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3316 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3317 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 3318 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 3319 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3320 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 3321 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3322 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 3323 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3324 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 3325 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3326 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3327 return 0;
31312f95 3328#endif
252b5132
RH		 3329 return 1;
3330}
252b5132 3331
b4cac588 3332static int
e3bb37b5 3333intel_float_operand (const char *mnemonic)
252b5132 3334{
9306ca4a
JB		 3335 /* Note that the value returned is meaningful only for opcodes with (memory)
3336 operands, hence the code here is free to improperly handle opcodes that
3337 have no operands (for better performance and smaller code). */
3338
3339 if (mnemonic[0] != 'f')
3340 return 0; /* non-math */
3341
3342 switch (mnemonic[1])
3343 {
3344 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3345 the fs segment override prefix not currently handled because no
3346 call path can make opcodes without operands get here */
3347 case 'i':
3348 return 2 /* integer op */;
3349 case 'l':
3350 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3351 return 3; /* fldcw/fldenv */
3352 break;
3353 case 'n':
3354 if (mnemonic[2] != 'o' /* fnop */)
3355 return 3; /* non-waiting control op */
3356 break;
3357 case 'r':
3358 if (mnemonic[2] == 's')
3359 return 3; /* frstor/frstpm */
3360 break;
3361 case 's':
3362 if (mnemonic[2] == 'a')
3363 return 3; /* fsave */
3364 if (mnemonic[2] == 't')
3365 {
3366 switch (mnemonic[3])
3367 {
3368 case 'c': /* fstcw */
3369 case 'd': /* fstdw */
3370 case 'e': /* fstenv */
3371 case 's': /* fsts[gw] */
3372 return 3;
3373 }
3374 }
3375 break;
3376 case 'x':
3377 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3378 return 0; /* fxsave/fxrstor are not really math ops */
3379 break;
3380 }
252b5132 3381
9306ca4a 3382 return 1;
252b5132
RH		 3383}
3384
c0f3af97
L		 3385/* Build the VEX prefix. */
3386
3387static void
d3ce72d0 3388build_vex_prefix (const insn_template *t)
c0f3af97
L		 3389{
3390 unsigned int register_specifier;
3391 unsigned int implied_prefix;
3392 unsigned int vector_length;
03751133 3393 unsigned int w;
c0f3af97
L		 3394
3395 /* Check register specifier. */
3396 if (i.vex.register_specifier)
43234a1e
L		 3397 {
3398 register_specifier =
3399 ~register_number (i.vex.register_specifier) & 0xf;
3400 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3401 }
c0f3af97
L		 3402 else
3403 register_specifier = 0xf;
3404
79f0fa25
L		 3405 /* Use 2-byte VEX prefix by swapping destination and source operand
3406 if there are more than 1 register operand. */
3407 if (i.reg_operands > 1
3408 && i.vec_encoding != vex_encoding_vex3
86fa6981 3409 && i.dir_encoding == dir_encoding_default
fa99fab2 3410 && i.operands == i.reg_operands
dbbc8b7e 3411 && operand_type_equal (&i.types[0], &i.types[i.operands - 1])
7f399153 3412 && i.tm.opcode_modifier.vexopcode == VEX0F
dbbc8b7e 3413 && (i.tm.opcode_modifier.load || i.tm.opcode_modifier.d)
fa99fab2
L		 3414 && i.rex == REX_B)
3415 {
3416 unsigned int xchg = i.operands - 1;
3417 union i386_op temp_op;
3418 i386_operand_type temp_type;
3419
3420 temp_type = i.types[xchg];
3421 i.types[xchg] = i.types[0];
3422 i.types[0] = temp_type;
3423 temp_op = i.op[xchg];
3424 i.op[xchg] = i.op[0];
3425 i.op[0] = temp_op;
3426
9c2799c2 3427 gas_assert (i.rm.mode == 3);
fa99fab2
L		 3428
3429 i.rex = REX_R;
3430 xchg = i.rm.regmem;
3431 i.rm.regmem = i.rm.reg;
3432 i.rm.reg = xchg;
3433
dbbc8b7e
JB		 3434 if (i.tm.opcode_modifier.d)
3435 i.tm.base_opcode ^= (i.tm.base_opcode & 0xee) != 0x6e
3436 ? Opcode_SIMD_FloatD : Opcode_SIMD_IntD;
3437 else /* Use the next insn. */
3438 i.tm = t[1];
fa99fab2
L		 3439 }
3440
539f890d
L		 3441 if (i.tm.opcode_modifier.vex == VEXScalar)
3442 vector_length = avxscalar;
10c17abd
JB		 3443 else if (i.tm.opcode_modifier.vex == VEX256)
3444 vector_length = 1;
539f890d 3445 else
10c17abd 3446 {
56522fc5 3447 unsigned int op;
10c17abd 3448
c7213af9
L		 3449 /* Determine vector length from the last multi-length vector
3450 operand. */
10c17abd 3451 vector_length = 0;
56522fc5 3452 for (op = t->operands; op--;)
10c17abd
JB		 3453 if (t->operand_types[op].bitfield.xmmword
3454 && t->operand_types[op].bitfield.ymmword
3455 && i.types[op].bitfield.ymmword)
3456 {
3457 vector_length = 1;
3458 break;
3459 }
3460 }
c0f3af97
L		 3461
3462 switch ((i.tm.base_opcode >> 8) & 0xff)
3463 {
3464 case 0:
3465 implied_prefix = 0;
3466 break;
3467 case DATA_PREFIX_OPCODE:
3468 implied_prefix = 1;
3469 break;
3470 case REPE_PREFIX_OPCODE:
3471 implied_prefix = 2;
3472 break;
3473 case REPNE_PREFIX_OPCODE:
3474 implied_prefix = 3;
3475 break;
3476 default:
3477 abort ();
3478 }
3479
03751133
L		 3480 /* Check the REX.W bit and VEXW. */
3481 if (i.tm.opcode_modifier.vexw == VEXWIG)
3482 w = (vexwig == vexw1 || (i.rex & REX_W)) ? 1 : 0;
3483 else if (i.tm.opcode_modifier.vexw)
3484 w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0;
3485 else
931d03b7 3486 w = (flag_code == CODE_64BIT ? i.rex & REX_W : vexwig == vexw1) ? 1 : 0;
03751133 3487
c0f3af97 3488 /* Use 2-byte VEX prefix if possible. */
03751133
L		 3489 if (w == 0
3490 && i.vec_encoding != vex_encoding_vex3
86fa6981 3491 && i.tm.opcode_modifier.vexopcode == VEX0F
c0f3af97
L		 3492 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3493 {
3494 /* 2-byte VEX prefix. */
3495 unsigned int r;
3496
3497 i.vex.length = 2;
3498 i.vex.bytes[0] = 0xc5;
3499
3500 /* Check the REX.R bit. */
3501 r = (i.rex & REX_R) ? 0 : 1;
3502 i.vex.bytes[1] = (r << 7
3503 | register_specifier << 3
3504 | vector_length << 2
3505 | implied_prefix);
3506 }
3507 else
3508 {
3509 /* 3-byte VEX prefix. */
03751133 3510 unsigned int m;
c0f3af97 3511
f88c9eb0 3512 i.vex.length = 3;
f88c9eb0 3513
7f399153 3514 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 3515 {
7f399153
L		 3516 case VEX0F:
3517 m = 0x1;
80de6e00 3518 i.vex.bytes[0] = 0xc4;
7f399153
L		 3519 break;
3520 case VEX0F38:
3521 m = 0x2;
80de6e00 3522 i.vex.bytes[0] = 0xc4;
7f399153
L		 3523 break;
3524 case VEX0F3A:
3525 m = 0x3;
80de6e00 3526 i.vex.bytes[0] = 0xc4;
7f399153
L		 3527 break;
3528 case XOP08:
5dd85c99
SP		 3529 m = 0x8;
3530 i.vex.bytes[0] = 0x8f;
7f399153
L		 3531 break;
3532 case XOP09:
f88c9eb0
SP		 3533 m = 0x9;
3534 i.vex.bytes[0] = 0x8f;
7f399153
L		 3535 break;
3536 case XOP0A:
f88c9eb0
SP		 3537 m = 0xa;
3538 i.vex.bytes[0] = 0x8f;
7f399153
L		 3539 break;
3540 default:
3541 abort ();
f88c9eb0 3542 }
c0f3af97 3543
c0f3af97
L		 3544 /* The high 3 bits of the second VEX byte are 1's compliment
3545 of RXB bits from REX. */
3546 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3547
c0f3af97
L		 3548 i.vex.bytes[2] = (w << 7
3549 | register_specifier << 3
3550 | vector_length << 2
3551 | implied_prefix);
3552 }
3553}
3554
e771e7c9
JB		 3555static INLINE bfd_boolean
3556is_evex_encoding (const insn_template *t)
3557{
7091c612 3558 return t->opcode_modifier.evex || t->opcode_modifier.disp8memshift
e771e7c9
JB		 3559 || t->opcode_modifier.broadcast || t->opcode_modifier.masking
3560 || t->opcode_modifier.staticrounding || t->opcode_modifier.sae;
3561}
3562
7a8655d2
JB		 3563static INLINE bfd_boolean
3564is_any_vex_encoding (const insn_template *t)
3565{
3566 return t->opcode_modifier.vex || t->opcode_modifier.vexopcode
3567 || is_evex_encoding (t);
3568}
3569
43234a1e
L		 3570/* Build the EVEX prefix. */
3571
3572static void
3573build_evex_prefix (void)
3574{
3575 unsigned int register_specifier;
3576 unsigned int implied_prefix;
3577 unsigned int m, w;
3578 rex_byte vrex_used = 0;
3579
3580 /* Check register specifier. */
3581 if (i.vex.register_specifier)
3582 {
3583 gas_assert ((i.vrex & REX_X) == 0);
3584
3585 register_specifier = i.vex.register_specifier->reg_num;
3586 if ((i.vex.register_specifier->reg_flags & RegRex))
3587 register_specifier += 8;
3588 /* The upper 16 registers are encoded in the fourth byte of the
3589 EVEX prefix. */
3590 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3591 i.vex.bytes[3] = 0x8;
3592 register_specifier = ~register_specifier & 0xf;
3593 }
3594 else
3595 {
3596 register_specifier = 0xf;
3597
3598 /* Encode upper 16 vector index register in the fourth byte of
3599 the EVEX prefix. */
3600 if (!(i.vrex & REX_X))
3601 i.vex.bytes[3] = 0x8;
3602 else
3603 vrex_used |= REX_X;
3604 }
3605
3606 switch ((i.tm.base_opcode >> 8) & 0xff)
3607 {
3608 case 0:
3609 implied_prefix = 0;
3610 break;
3611 case DATA_PREFIX_OPCODE:
3612 implied_prefix = 1;
3613 break;
3614 case REPE_PREFIX_OPCODE:
3615 implied_prefix = 2;
3616 break;
3617 case REPNE_PREFIX_OPCODE:
3618 implied_prefix = 3;
3619 break;
3620 default:
3621 abort ();
3622 }
3623
3624 /* 4 byte EVEX prefix. */
3625 i.vex.length = 4;
3626 i.vex.bytes[0] = 0x62;
3627
3628 /* mmmm bits. */
3629 switch (i.tm.opcode_modifier.vexopcode)
3630 {
3631 case VEX0F:
3632 m = 1;
3633 break;
3634 case VEX0F38:
3635 m = 2;
3636 break;
3637 case VEX0F3A:
3638 m = 3;
3639 break;
3640 default:
3641 abort ();
3642 break;
3643 }
3644
3645 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3646 bits from REX. */
3647 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3648
3649 /* The fifth bit of the second EVEX byte is 1's compliment of the
3650 REX_R bit in VREX. */
3651 if (!(i.vrex & REX_R))
3652 i.vex.bytes[1] |= 0x10;
3653 else
3654 vrex_used |= REX_R;
3655
3656 if ((i.reg_operands + i.imm_operands) == i.operands)
3657 {
3658 /* When all operands are registers, the REX_X bit in REX is not
3659 used. We reuse it to encode the upper 16 registers, which is
3660 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3661 as 1's compliment. */
3662 if ((i.vrex & REX_B))
3663 {
3664 vrex_used |= REX_B;
3665 i.vex.bytes[1] &= ~0x40;
3666 }
3667 }
3668
3669 /* EVEX instructions shouldn't need the REX prefix. */
3670 i.vrex &= ~vrex_used;
3671 gas_assert (i.vrex == 0);
3672
6865c043
L		 3673 /* Check the REX.W bit and VEXW. */
3674 if (i.tm.opcode_modifier.vexw == VEXWIG)
3675 w = (evexwig == evexw1 || (i.rex & REX_W)) ? 1 : 0;
3676 else if (i.tm.opcode_modifier.vexw)
3677 w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0;
3678 else
931d03b7 3679 w = (flag_code == CODE_64BIT ? i.rex & REX_W : evexwig == evexw1) ? 1 : 0;
43234a1e
L		 3680
3681 /* Encode the U bit. */
3682 implied_prefix |= 0x4;
3683
3684 /* The third byte of the EVEX prefix. */
3685 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3686
3687 /* The fourth byte of the EVEX prefix. */
3688 /* The zeroing-masking bit. */
3689 if (i.mask && i.mask->zeroing)
3690 i.vex.bytes[3] |= 0x80;
3691
3692 /* Don't always set the broadcast bit if there is no RC. */
3693 if (!i.rounding)
3694 {
3695 /* Encode the vector length. */
3696 unsigned int vec_length;
3697
e771e7c9
JB		 3698 if (!i.tm.opcode_modifier.evex
3699 || i.tm.opcode_modifier.evex == EVEXDYN)
3700 {
56522fc5 3701 unsigned int op;
e771e7c9 3702
c7213af9
L		 3703 /* Determine vector length from the last multi-length vector
3704 operand. */
e771e7c9 3705 vec_length = 0;
56522fc5 3706 for (op = i.operands; op--;)
e771e7c9
JB		 3707 if (i.tm.operand_types[op].bitfield.xmmword
3708 + i.tm.operand_types[op].bitfield.ymmword
3709 + i.tm.operand_types[op].bitfield.zmmword > 1)
3710 {
3711 if (i.types[op].bitfield.zmmword)
c7213af9
L		 3712 {
3713 i.tm.opcode_modifier.evex = EVEX512;
3714 break;
3715 }
e771e7c9 3716 else if (i.types[op].bitfield.ymmword)
c7213af9
L		 3717 {
3718 i.tm.opcode_modifier.evex = EVEX256;
3719 break;
3720 }
e771e7c9 3721 else if (i.types[op].bitfield.xmmword)
c7213af9
L		 3722 {
3723 i.tm.opcode_modifier.evex = EVEX128;
3724 break;
3725 }
625cbd7a
JB		 3726 else if (i.broadcast && (int) op == i.broadcast->operand)
3727 {
4a1b91ea 3728 switch (i.broadcast->bytes)
625cbd7a
JB		 3729 {
3730 case 64:
3731 i.tm.opcode_modifier.evex = EVEX512;
3732 break;
3733 case 32:
3734 i.tm.opcode_modifier.evex = EVEX256;
3735 break;
3736 case 16:
3737 i.tm.opcode_modifier.evex = EVEX128;
3738 break;
3739 default:
c7213af9 3740 abort ();
625cbd7a 3741 }
c7213af9 3742 break;
625cbd7a 3743 }
e771e7c9 3744 }
c7213af9 3745
56522fc5 3746 if (op >= MAX_OPERANDS)
c7213af9 3747 abort ();
e771e7c9
JB		 3748 }
3749
43234a1e
L		 3750 switch (i.tm.opcode_modifier.evex)
3751 {
3752 case EVEXLIG: /* LL' is ignored */
3753 vec_length = evexlig << 5;
3754 break;
3755 case EVEX128:
3756 vec_length = 0 << 5;
3757 break;
3758 case EVEX256:
3759 vec_length = 1 << 5;
3760 break;
3761 case EVEX512:
3762 vec_length = 2 << 5;
3763 break;
3764 default:
3765 abort ();
3766 break;
3767 }
3768 i.vex.bytes[3] |= vec_length;
3769 /* Encode the broadcast bit. */
3770 if (i.broadcast)
3771 i.vex.bytes[3] |= 0x10;
3772 }
3773 else
3774 {
3775 if (i.rounding->type != saeonly)
3776 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3777 else
d3d3c6db 3778 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
43234a1e
L		 3779 }
3780
3781 if (i.mask && i.mask->mask)
3782 i.vex.bytes[3] |= i.mask->mask->reg_num;
3783}
3784
65da13b5
L		 3785static void
3786process_immext (void)
3787{
3788 expressionS *exp;
3789
4c692bc7
JB		 3790 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3791 && i.operands > 0)
65da13b5 3792 {
4c692bc7
JB		 3793 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3794 with an opcode suffix which is coded in the same place as an
3795 8-bit immediate field would be.
3796 Here we check those operands and remove them afterwards. */
65da13b5
L		 3797 unsigned int x;
3798
3799 for (x = 0; x < i.operands; x++)
4c692bc7 3800 if (register_number (i.op[x].regs) != x)
65da13b5 3801 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3802 register_prefix, i.op[x].regs->reg_name, x + 1,
3803 i.tm.name);
3804
3805 i.operands = 0;
65da13b5
L		 3806 }
3807
9916071f
AP		 3808 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3809 {
3810 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3811 suffix which is coded in the same place as an 8-bit immediate
3812 field would be.
3813 Here we check those operands and remove them afterwards. */
3814 unsigned int x;
3815
3816 if (i.operands != 3)
3817 abort();
3818
3819 for (x = 0; x < 2; x++)
3820 if (register_number (i.op[x].regs) != x)
3821 goto bad_register_operand;
3822
3823 /* Check for third operand for mwaitx/monitorx insn. */
3824 if (register_number (i.op[x].regs)
3825 != (x + (i.tm.extension_opcode == 0xfb)))
3826 {
3827bad_register_operand:
3828 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3829 register_prefix, i.op[x].regs->reg_name, x+1,
3830 i.tm.name);
3831 }
3832
3833 i.operands = 0;
3834 }
3835
c0f3af97 3836 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3837 which is coded in the same place as an 8-bit immediate field
3838 would be. Here we fake an 8-bit immediate operand from the
3839 opcode suffix stored in tm.extension_opcode.
3840
c1e679ec 3841 AVX instructions also use this encoding, for some of
c0f3af97 3842 3 argument instructions. */
65da13b5 3843
43234a1e 3844 gas_assert (i.imm_operands <= 1
7ab9ffdd 3845 && (i.operands <= 2
7a8655d2 3846 || (is_any_vex_encoding (&i.tm)
7ab9ffdd 3847 && i.operands <= 4)));
65da13b5
L		 3848
3849 exp = &im_expressions[i.imm_operands++];
3850 i.op[i.operands].imms = exp;
3851 i.types[i.operands] = imm8;
3852 i.operands++;
3853 exp->X_op = O_constant;
3854 exp->X_add_number = i.tm.extension_opcode;
3855 i.tm.extension_opcode = None;
3856}
3857
42164a71
L		 3858
3859static int
3860check_hle (void)
3861{
3862 switch (i.tm.opcode_modifier.hleprefixok)
3863 {
3864 default:
3865 abort ();
82c2def5 3866 case HLEPrefixNone:
165de32a
L		 3867 as_bad (_("invalid instruction `%s' after `%s'"),
3868 i.tm.name, i.hle_prefix);
42164a71 3869 return 0;
82c2def5 3870 case HLEPrefixLock:
42164a71
L		 3871 if (i.prefix[LOCK_PREFIX])
3872 return 1;
165de32a 3873 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3874 return 0;
82c2def5 3875 case HLEPrefixAny:
42164a71 3876 return 1;
82c2def5 3877 case HLEPrefixRelease:
42164a71
L		 3878 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3879 {
3880 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3881 i.tm.name);
3882 return 0;
3883 }
3884 if (i.mem_operands == 0
3885 || !operand_type_check (i.types[i.operands - 1], anymem))
3886 {
3887 as_bad (_("memory destination needed for instruction `%s'"
3888 " after `xrelease'"), i.tm.name);
3889 return 0;
3890 }
3891 return 1;
3892 }
3893}
3894
b6f8c7c4
L		 3895/* Try the shortest encoding by shortening operand size. */
3896
3897static void
3898optimize_encoding (void)
3899{
a0a1771e 3900 unsigned int j;
b6f8c7c4
L		 3901
3902 if (optimize_for_space
3903 && i.reg_operands == 1
3904 && i.imm_operands == 1
3905 && !i.types[1].bitfield.byte
3906 && i.op[0].imms->X_op == O_constant
3907 && fits_in_imm7 (i.op[0].imms->X_add_number)
3908 && ((i.tm.base_opcode == 0xa8
3909 && i.tm.extension_opcode == None)
3910 || (i.tm.base_opcode == 0xf6
3911 && i.tm.extension_opcode == 0x0)))
3912 {
3913 /* Optimize: -Os:
3914 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3915 */
3916 unsigned int base_regnum = i.op[1].regs->reg_num;
3917 if (flag_code == CODE_64BIT || base_regnum < 4)
3918 {
3919 i.types[1].bitfield.byte = 1;
3920 /* Ignore the suffix. */
3921 i.suffix = 0;
3922 if (base_regnum >= 4
3923 && !(i.op[1].regs->reg_flags & RegRex))
3924 {
3925 /* Handle SP, BP, SI and DI registers. */
3926 if (i.types[1].bitfield.word)
3927 j = 16;
3928 else if (i.types[1].bitfield.dword)
3929 j = 32;
3930 else
3931 j = 48;
3932 i.op[1].regs -= j;
3933 }
3934 }
3935 }
3936 else if (flag_code == CODE_64BIT
d3d50934
L		 3937 && ((i.types[1].bitfield.qword
3938 && i.reg_operands == 1
b6f8c7c4
L		 3939 && i.imm_operands == 1
3940 && i.op[0].imms->X_op == O_constant
3941 && ((i.tm.base_opcode == 0xb0
3942 && i.tm.extension_opcode == None
3943 && fits_in_unsigned_long (i.op[0].imms->X_add_number))
3944 || (fits_in_imm31 (i.op[0].imms->X_add_number)
3945 && (((i.tm.base_opcode == 0x24
3946 || i.tm.base_opcode == 0xa8)
3947 && i.tm.extension_opcode == None)
3948 || (i.tm.base_opcode == 0x80
3949 && i.tm.extension_opcode == 0x4)
3950 || ((i.tm.base_opcode == 0xf6
3951 || i.tm.base_opcode == 0xc6)
b8364fa7
JB		 3952 && i.tm.extension_opcode == 0x0)))
3953 || (fits_in_imm7 (i.op[0].imms->X_add_number)
3954 && i.tm.base_opcode == 0x83
3955 && i.tm.extension_opcode == 0x4)))
d3d50934
L		 3956 || (i.types[0].bitfield.qword
3957 && ((i.reg_operands == 2
3958 && i.op[0].regs == i.op[1].regs
3959 && ((i.tm.base_opcode == 0x30
3960 || i.tm.base_opcode == 0x28)
3961 && i.tm.extension_opcode == None))
3962 || (i.reg_operands == 1
3963 && i.operands == 1
3964 && i.tm.base_opcode == 0x30
3965 && i.tm.extension_opcode == None)))))
b6f8c7c4
L		 3966 {
3967 /* Optimize: -O:
3968 andq $imm31, %r64 -> andl $imm31, %r32
b8364fa7 3969 andq $imm7, %r64 -> andl $imm7, %r32
b6f8c7c4
L		 3970 testq $imm31, %r64 -> testl $imm31, %r32
3971 xorq %r64, %r64 -> xorl %r32, %r32
3972 subq %r64, %r64 -> subl %r32, %r32
3973 movq $imm31, %r64 -> movl $imm31, %r32
3974 movq $imm32, %r64 -> movl $imm32, %r32
3975 */
3976 i.tm.opcode_modifier.norex64 = 1;
3977 if (i.tm.base_opcode == 0xb0 || i.tm.base_opcode == 0xc6)
3978 {
3979 /* Handle
3980 movq $imm31, %r64 -> movl $imm31, %r32
3981 movq $imm32, %r64 -> movl $imm32, %r32
3982 */
3983 i.tm.operand_types[0].bitfield.imm32 = 1;
3984 i.tm.operand_types[0].bitfield.imm32s = 0;
3985 i.tm.operand_types[0].bitfield.imm64 = 0;
3986 i.types[0].bitfield.imm32 = 1;
3987 i.types[0].bitfield.imm32s = 0;
3988 i.types[0].bitfield.imm64 = 0;
3989 i.types[1].bitfield.dword = 1;
3990 i.types[1].bitfield.qword = 0;
3991 if (i.tm.base_opcode == 0xc6)
3992 {
3993 /* Handle
3994 movq $imm31, %r64 -> movl $imm31, %r32
3995 */
3996 i.tm.base_opcode = 0xb0;
3997 i.tm.extension_opcode = None;
3998 i.tm.opcode_modifier.shortform = 1;
3999 i.tm.opcode_modifier.modrm = 0;
4000 }
4001 }
4002 }
99112332 4003 else if (i.reg_operands == 3
b6f8c7c4
L		 4004 && i.op[0].regs == i.op[1].regs
4005 && !i.types[2].bitfield.xmmword
4006 && (i.tm.opcode_modifier.vex
7a69eac3 4007 || ((!i.mask || i.mask->zeroing)
b6f8c7c4 4008 && !i.rounding
e771e7c9 4009 && is_evex_encoding (&i.tm)
80c34c38 4010 && (i.vec_encoding != vex_encoding_evex
dd22218c 4011 || cpu_arch_isa_flags.bitfield.cpuavx512vl
80c34c38 4012 || i.tm.cpu_flags.bitfield.cpuavx512vl
7091c612 4013 || (i.tm.operand_types[2].bitfield.zmmword
dd22218c 4014 && i.types[2].bitfield.ymmword))))
b6f8c7c4
L		 4015 && ((i.tm.base_opcode == 0x55
4016 || i.tm.base_opcode == 0x6655
4017 || i.tm.base_opcode == 0x66df
4018 || i.tm.base_opcode == 0x57
4019 || i.tm.base_opcode == 0x6657
8305403a
L		 4020 || i.tm.base_opcode == 0x66ef
4021 || i.tm.base_opcode == 0x66f8
4022 || i.tm.base_opcode == 0x66f9
4023 || i.tm.base_opcode == 0x66fa
1424ad86
JB		 4024 || i.tm.base_opcode == 0x66fb
4025 || i.tm.base_opcode == 0x42
4026 || i.tm.base_opcode == 0x6642
4027 || i.tm.base_opcode == 0x47
4028 || i.tm.base_opcode == 0x6647)
b6f8c7c4
L		 4029 && i.tm.extension_opcode == None))
4030 {
99112332 4031 /* Optimize: -O1:
8305403a
L		 4032 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4033 vpsubq and vpsubw:
b6f8c7c4
L		 4034 EVEX VOP %zmmM, %zmmM, %zmmN
4035 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
99112332 4036 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
b6f8c7c4
L		 4037 EVEX VOP %ymmM, %ymmM, %ymmN
4038 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
99112332 4039 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
b6f8c7c4
L		 4040 VEX VOP %ymmM, %ymmM, %ymmN
4041 -> VEX VOP %xmmM, %xmmM, %xmmN
4042 VOP, one of vpandn and vpxor:
4043 VEX VOP %ymmM, %ymmM, %ymmN
4044 -> VEX VOP %xmmM, %xmmM, %xmmN
4045 VOP, one of vpandnd and vpandnq:
4046 EVEX VOP %zmmM, %zmmM, %zmmN
4047 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
99112332 4048 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
b6f8c7c4
L		 4049 EVEX VOP %ymmM, %ymmM, %ymmN
4050 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
99112332 4051 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
b6f8c7c4
L		 4052 VOP, one of vpxord and vpxorq:
4053 EVEX VOP %zmmM, %zmmM, %zmmN
4054 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
99112332 4055 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
b6f8c7c4
L		 4056 EVEX VOP %ymmM, %ymmM, %ymmN
4057 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
99112332 4058 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
1424ad86
JB		 4059 VOP, one of kxord and kxorq:
4060 VEX VOP %kM, %kM, %kN
4061 -> VEX kxorw %kM, %kM, %kN
4062 VOP, one of kandnd and kandnq:
4063 VEX VOP %kM, %kM, %kN
4064 -> VEX kandnw %kM, %kM, %kN
b6f8c7c4 4065 */
e771e7c9 4066 if (is_evex_encoding (&i.tm))
b6f8c7c4 4067 {
7b1d7ca1 4068 if (i.vec_encoding != vex_encoding_evex)
b6f8c7c4
L		 4069 {
4070 i.tm.opcode_modifier.vex = VEX128;
4071 i.tm.opcode_modifier.vexw = VEXW0;
4072 i.tm.opcode_modifier.evex = 0;
4073 }
7b1d7ca1 4074 else if (optimize > 1)
dd22218c
L		 4075 i.tm.opcode_modifier.evex = EVEX128;
4076 else
4077 return;
b6f8c7c4 4078 }
1424ad86
JB		 4079 else if (i.tm.operand_types[0].bitfield.regmask)
4080 {
4081 i.tm.base_opcode &= 0xff;
4082 i.tm.opcode_modifier.vexw = VEXW0;
4083 }
b6f8c7c4
L		 4084 else
4085 i.tm.opcode_modifier.vex = VEX128;
4086
4087 if (i.tm.opcode_modifier.vex)
4088 for (j = 0; j < 3; j++)
4089 {
4090 i.types[j].bitfield.xmmword = 1;
4091 i.types[j].bitfield.ymmword = 0;
4092 }
4093 }
392a5972 4094 else if (i.vec_encoding != vex_encoding_evex
97ed31ae 4095 && !i.types[0].bitfield.zmmword
392a5972 4096 && !i.types[1].bitfield.zmmword
97ed31ae 4097 && !i.mask
a0a1771e 4098 && !i.broadcast
97ed31ae 4099 && is_evex_encoding (&i.tm)
392a5972
L		 4100 && ((i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0x666f
4101 || (i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0xf36f
a0a1771e
JB		 4102 || (i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0xf26f
4103 || (i.tm.base_opcode & ~4) == 0x66db
4104 || (i.tm.base_opcode & ~4) == 0x66eb)
97ed31ae
L		 4105 && i.tm.extension_opcode == None)
4106 {
4107 /* Optimize: -O1:
4108 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4109 vmovdqu32 and vmovdqu64:
4110 EVEX VOP %xmmM, %xmmN
4111 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4112 EVEX VOP %ymmM, %ymmN
4113 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4114 EVEX VOP %xmmM, mem
4115 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4116 EVEX VOP %ymmM, mem
4117 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4118 EVEX VOP mem, %xmmN
4119 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4120 EVEX VOP mem, %ymmN
4121 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
a0a1771e
JB		 4122 VOP, one of vpand, vpandn, vpor, vpxor:
4123 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4124 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4125 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4126 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4127 EVEX VOP{d,q} mem, %xmmM, %xmmN
4128 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4129 EVEX VOP{d,q} mem, %ymmM, %ymmN
4130 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
97ed31ae 4131 */
a0a1771e 4132 for (j = 0; j < i.operands; j++)
392a5972
L		 4133 if (operand_type_check (i.types[j], disp)
4134 && i.op[j].disps->X_op == O_constant)
4135 {
4136 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4137 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4138 bytes, we choose EVEX Disp8 over VEX Disp32. */
4139 int evex_disp8, vex_disp8;
4140 unsigned int memshift = i.memshift;
4141 offsetT n = i.op[j].disps->X_add_number;
4142
4143 evex_disp8 = fits_in_disp8 (n);
4144 i.memshift = 0;
4145 vex_disp8 = fits_in_disp8 (n);
4146 if (evex_disp8 != vex_disp8)
4147 {
4148 i.memshift = memshift;
4149 return;
4150 }
4151
4152 i.types[j].bitfield.disp8 = vex_disp8;
4153 break;
4154 }
4155 if ((i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0xf26f)
4156 i.tm.base_opcode ^= 0xf36f ^ 0xf26f;
97ed31ae
L		 4157 i.tm.opcode_modifier.vex
4158 = i.types[0].bitfield.ymmword ? VEX256 : VEX128;
4159 i.tm.opcode_modifier.vexw = VEXW0;
4160 i.tm.opcode_modifier.evex = 0;
4161 i.tm.opcode_modifier.masking = 0;
a0a1771e 4162 i.tm.opcode_modifier.broadcast = 0;
97ed31ae
L		 4163 i.tm.opcode_modifier.disp8memshift = 0;
4164 i.memshift = 0;
a0a1771e
JB		 4165 if (j < i.operands)
4166 i.types[j].bitfield.disp8
4167 = fits_in_disp8 (i.op[j].disps->X_add_number);
97ed31ae 4168 }
b6f8c7c4
L		 4169}
4170
252b5132
RH		 4171/* This is the guts of the machine-dependent assembler. LINE points to a
4172 machine dependent instruction. This function is supposed to emit
4173 the frags/bytes it assembles to. */
4174
4175void
65da13b5 4176md_assemble (char *line)
252b5132 4177{
40fb9820 4178 unsigned int j;
83b16ac6 4179 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
d3ce72d0 4180 const insn_template *t;
252b5132 4181
47926f60 4182 /* Initialize globals. */
252b5132
RH		 4183 memset (&i, '\0', sizeof (i));
4184 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 4185 i.reloc[j] = NO_RELOC;
252b5132
RH		 4186 memset (disp_expressions, '\0', sizeof (disp_expressions));
4187 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 4188 save_stack_p = save_stack;
252b5132
RH		 4189
4190 /* First parse an instruction mnemonic & call i386_operand for the operands.
4191 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 4192 start of a (possibly prefixed) mnemonic. */
252b5132 4193
29b0f896
AM		 4194 line = parse_insn (line, mnemonic);
4195 if (line == NULL)
4196 return;
83b16ac6 4197 mnem_suffix = i.suffix;
252b5132 4198
29b0f896 4199 line = parse_operands (line, mnemonic);
ee86248c 4200 this_operand = -1;
8325cc63
JB		 4201 xfree (i.memop1_string);
4202 i.memop1_string = NULL;
29b0f896
AM		 4203 if (line == NULL)
4204 return;
252b5132 4205
29b0f896
AM		 4206 /* Now we've parsed the mnemonic into a set of templates, and have the
4207 operands at hand. */
4208
4209 /* All intel opcodes have reversed operands except for "bound" and
4210 "enter". We also don't reverse intersegment "jmp" and "call"
4211 instructions with 2 immediate operands so that the immediate segment
050dfa73 4212 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 4213 if (intel_syntax
4214 && i.operands > 1
29b0f896 4215 && (strcmp (mnemonic, "bound") != 0)
30123838 4216 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 4217 && !(operand_type_check (i.types[0], imm)
4218 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 4219 swap_operands ();
4220
ec56d5c0
JB		 4221 /* The order of the immediates should be reversed
4222 for 2 immediates extrq and insertq instructions */
4223 if (i.imm_operands == 2
4224 && (strcmp (mnemonic, "extrq") == 0
4225 || strcmp (mnemonic, "insertq") == 0))
4226 swap_2_operands (0, 1);
4227
29b0f896
AM		 4228 if (i.imm_operands)
4229 optimize_imm ();
4230
b300c311
L		 4231 /* Don't optimize displacement for movabs since it only takes 64bit
4232 displacement. */
4233 if (i.disp_operands
a501d77e 4234 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 4235 && (flag_code != CODE_64BIT
4236 || strcmp (mnemonic, "movabs") != 0))
4237 optimize_disp ();
29b0f896
AM		 4238
4239 /* Next, we find a template that matches the given insn,
4240 making sure the overlap of the given operands types is consistent
4241 with the template operand types. */
252b5132 4242
83b16ac6 4243 if (!(t = match_template (mnem_suffix)))
29b0f896 4244 return;
252b5132 4245
7bab8ab5 4246 if (sse_check != check_none
81f8a913 4247 && !i.tm.opcode_modifier.noavx
6e3e5c9e 4248 && !i.tm.cpu_flags.bitfield.cpuavx
daf50ae7
L		 4249 && (i.tm.cpu_flags.bitfield.cpusse
4250 || i.tm.cpu_flags.bitfield.cpusse2
4251 || i.tm.cpu_flags.bitfield.cpusse3
4252 || i.tm.cpu_flags.bitfield.cpussse3
4253 || i.tm.cpu_flags.bitfield.cpusse4_1
6e3e5c9e
JB		 4254 || i.tm.cpu_flags.bitfield.cpusse4_2
4255 || i.tm.cpu_flags.bitfield.cpupclmul
4256 || i.tm.cpu_flags.bitfield.cpuaes
4257 || i.tm.cpu_flags.bitfield.cpugfni))
daf50ae7 4258 {
7bab8ab5 4259 (sse_check == check_warning
daf50ae7
L		 4260 ? as_warn
4261 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
4262 }
4263
321fd21e
L		 4264 /* Zap movzx and movsx suffix. The suffix has been set from
4265 "word ptr" or "byte ptr" on the source operand in Intel syntax
4266 or extracted from mnemonic in AT&T syntax. But we'll use
4267 the destination register to choose the suffix for encoding. */
4268 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 4269 {
321fd21e
L		 4270 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4271 there is no suffix, the default will be byte extension. */
4272 if (i.reg_operands != 2
4273 && !i.suffix
7ab9ffdd 4274 && intel_syntax)
321fd21e
L		 4275 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4276
4277 i.suffix = 0;
cd61ebfe 4278 }
24eab124 4279
40fb9820 4280 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 4281 if (!add_prefix (FWAIT_OPCODE))
4282 return;
252b5132 4283
d5de92cf
L		 4284 /* Check if REP prefix is OK. */
4285 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
4286 {
4287 as_bad (_("invalid instruction `%s' after `%s'"),
4288 i.tm.name, i.rep_prefix);
4289 return;
4290 }
4291
c1ba0266
L		 4292 /* Check for lock without a lockable instruction. Destination operand
4293 must be memory unless it is xchg (0x86). */
c32fa91d
L		 4294 if (i.prefix[LOCK_PREFIX]
4295 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 4296 || i.mem_operands == 0
4297 || (i.tm.base_opcode != 0x86
4298 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 4299 {
4300 as_bad (_("expecting lockable instruction after `lock'"));
4301 return;
4302 }
4303
7a8655d2
JB		 4304 /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */
4305 if (i.prefix[DATA_PREFIX] && is_any_vex_encoding (&i.tm))
4306 {
4307 as_bad (_("data size prefix invalid with `%s'"), i.tm.name);
4308 return;
4309 }
4310
42164a71 4311 /* Check if HLE prefix is OK. */
165de32a 4312 if (i.hle_prefix && !check_hle ())
42164a71
L		 4313 return;
4314
7e8b059b
L		 4315 /* Check BND prefix. */
4316 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
4317 as_bad (_("expecting valid branch instruction after `bnd'"));
4318
04ef582a 4319 /* Check NOTRACK prefix. */
9fef80d6
L		 4320 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
4321 as_bad (_("expecting indirect branch instruction after `notrack'"));
04ef582a 4322
327e8c42
JB		 4323 if (i.tm.cpu_flags.bitfield.cpumpx)
4324 {
4325 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
4326 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4327 else if (flag_code != CODE_16BIT
4328 ? i.prefix[ADDR_PREFIX]
4329 : i.mem_operands && !i.prefix[ADDR_PREFIX])
4330 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4331 }
7e8b059b
L		 4332
4333 /* Insert BND prefix. */
76d3a78a
JB		 4334 if (add_bnd_prefix && i.tm.opcode_modifier.bndprefixok)
4335 {
4336 if (!i.prefix[BND_PREFIX])
4337 add_prefix (BND_PREFIX_OPCODE);
4338 else if (i.prefix[BND_PREFIX] != BND_PREFIX_OPCODE)
4339 {
4340 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4341 i.prefix[BND_PREFIX] = BND_PREFIX_OPCODE;
4342 }
4343 }
7e8b059b 4344
29b0f896 4345 /* Check string instruction segment overrides. */
40fb9820 4346 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 4347 {
4348 if (!check_string ())
5dd0794d 4349 return;
fc0763e6 4350 i.disp_operands = 0;
29b0f896 4351 }
5dd0794d 4352
b6f8c7c4
L		 4353 if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize)
4354 optimize_encoding ();
4355
29b0f896
AM		 4356 if (!process_suffix ())
4357 return;
e413e4e9 4358
bc0844ae
L		 4359 /* Update operand types. */
4360 for (j = 0; j < i.operands; j++)
4361 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
4362
29b0f896
AM		 4363 /* Make still unresolved immediate matches conform to size of immediate
4364 given in i.suffix. */
4365 if (!finalize_imm ())
4366 return;
252b5132 4367
40fb9820 4368 if (i.types[0].bitfield.imm1)
29b0f896 4369 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 4370
9afe6eb8
L		 4371 /* We only need to check those implicit registers for instructions
4372 with 3 operands or less. */
4373 if (i.operands <= 3)
4374 for (j = 0; j < i.operands; j++)
4375 if (i.types[j].bitfield.inoutportreg
4376 || i.types[j].bitfield.shiftcount
1b54b8d7 4377 || (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword))
9afe6eb8 4378 i.reg_operands--;
40fb9820 4379
c0f3af97
L		 4380 /* ImmExt should be processed after SSE2AVX. */
4381 if (!i.tm.opcode_modifier.sse2avx
4382 && i.tm.opcode_modifier.immext)
65da13b5 4383 process_immext ();
252b5132 4384
29b0f896
AM		 4385 /* For insns with operands there are more diddles to do to the opcode. */
4386 if (i.operands)
4387 {
4388 if (!process_operands ())
4389 return;
4390 }
40fb9820 4391 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 4392 {
4393 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4394 as_warn (_("translating to `%sp'"), i.tm.name);
4395 }
252b5132 4396
7a8655d2 4397 if (is_any_vex_encoding (&i.tm))
9e5e5283 4398 {
c1dc7af5 4399 if (!cpu_arch_flags.bitfield.cpui286)
9e5e5283 4400 {
c1dc7af5 4401 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
9e5e5283
L		 4402 i.tm.name);
4403 return;
4404 }
c0f3af97 4405
9e5e5283
L		 4406 if (i.tm.opcode_modifier.vex)
4407 build_vex_prefix (t);
4408 else
4409 build_evex_prefix ();
4410 }
43234a1e 4411
5dd85c99
SP		 4412 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4413 instructions may define INT_OPCODE as well, so avoid this corner
4414 case for those instructions that use MODRM. */
4415 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 4416 && !i.tm.opcode_modifier.modrm
4417 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 4418 {
4419 i.tm.base_opcode = INT3_OPCODE;
4420 i.imm_operands = 0;
4421 }
252b5132 4422
40fb9820
L		 4423 if ((i.tm.opcode_modifier.jump
4424 || i.tm.opcode_modifier.jumpbyte
4425 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 4426 && i.op[0].disps->X_op == O_constant)
4427 {
4428 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4429 the absolute address given by the constant. Since ix86 jumps and
4430 calls are pc relative, we need to generate a reloc. */
4431 i.op[0].disps->X_add_symbol = &abs_symbol;
4432 i.op[0].disps->X_op = O_symbol;
4433 }
252b5132 4434
40fb9820 4435 if (i.tm.opcode_modifier.rex64)
161a04f6 4436 i.rex |= REX_W;
252b5132 4437
29b0f896
AM		 4438 /* For 8 bit registers we need an empty rex prefix. Also if the
4439 instruction already has a prefix, we need to convert old
4440 registers to new ones. */
773f551c 4441
dc821c5f 4442 if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte
29b0f896 4443 && (i.op[0].regs->reg_flags & RegRex64) != 0)
dc821c5f 4444 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte
29b0f896 4445 && (i.op[1].regs->reg_flags & RegRex64) != 0)
dc821c5f
JB		 4446 || (((i.types[0].bitfield.reg && i.types[0].bitfield.byte)
4447 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte))
29b0f896
AM		 4448 && i.rex != 0))
4449 {
4450 int x;
726c5dcd 4451
29b0f896
AM		 4452 i.rex |= REX_OPCODE;
4453 for (x = 0; x < 2; x++)
4454 {
4455 /* Look for 8 bit operand that uses old registers. */
dc821c5f 4456 if (i.types[x].bitfield.reg && i.types[x].bitfield.byte
29b0f896 4457 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 4458 {
29b0f896
AM		 4459 /* In case it is "hi" register, give up. */
4460 if (i.op[x].regs->reg_num > 3)
a540244d 4461 as_bad (_("can't encode register '%s%s' in an "
4eed87de 4462 "instruction requiring REX prefix."),
a540244d 4463 register_prefix, i.op[x].regs->reg_name);
773f551c 4464
29b0f896
AM		 4465 /* Otherwise it is equivalent to the extended register.
4466 Since the encoding doesn't change this is merely
4467 cosmetic cleanup for debug output. */
4468
4469 i.op[x].regs = i.op[x].regs + 8;
773f551c 4470 }
29b0f896
AM		 4471 }
4472 }
773f551c 4473
6b6b6807
L		 4474 if (i.rex == 0 && i.rex_encoding)
4475 {
4476 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4477 that uses legacy register. If it is "hi" register, don't add
4478 the REX_OPCODE byte. */
4479 int x;
4480 for (x = 0; x < 2; x++)
4481 if (i.types[x].bitfield.reg
4482 && i.types[x].bitfield.byte
4483 && (i.op[x].regs->reg_flags & RegRex64) == 0
4484 && i.op[x].regs->reg_num > 3)
4485 {
4486 i.rex_encoding = FALSE;
4487 break;
4488 }
4489
4490 if (i.rex_encoding)
4491 i.rex = REX_OPCODE;
4492 }
4493
7ab9ffdd 4494 if (i.rex != 0)
29b0f896
AM		 4495 add_prefix (REX_OPCODE | i.rex);
4496
4497 /* We are ready to output the insn. */
4498 output_insn ();
4499}
4500
4501static char *
e3bb37b5 4502parse_insn (char *line, char *mnemonic)
29b0f896
AM		 4503{
4504 char *l = line;
4505 char *token_start = l;
4506 char *mnem_p;
5c6af06e 4507 int supported;
d3ce72d0 4508 const insn_template *t;
b6169b20 4509 char *dot_p = NULL;
29b0f896 4510
29b0f896
AM		 4511 while (1)
4512 {
4513 mnem_p = mnemonic;
4514 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
4515 {
b6169b20
L		 4516 if (*mnem_p == '.')
4517 dot_p = mnem_p;
29b0f896
AM		 4518 mnem_p++;
4519 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 4520 {
29b0f896
AM		 4521 as_bad (_("no such instruction: `%s'"), token_start);
4522 return NULL;
4523 }
4524 l++;
4525 }
4526 if (!is_space_char (*l)
4527 && *l != END_OF_INSN
e44823cf
JB		 4528 && (intel_syntax
4529 || (*l != PREFIX_SEPARATOR
4530 && *l != ',')))
29b0f896
AM		 4531 {
4532 as_bad (_("invalid character %s in mnemonic"),
4533 output_invalid (*l));
4534 return NULL;
4535 }
4536 if (token_start == l)
4537 {
e44823cf 4538 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 4539 as_bad (_("expecting prefix; got nothing"));
4540 else
4541 as_bad (_("expecting mnemonic; got nothing"));
4542 return NULL;
4543 }
45288df1 4544
29b0f896 4545 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 4546 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 4547
29b0f896
AM		 4548 if (*l != END_OF_INSN
4549 && (!is_space_char (*l) || l[1] != END_OF_INSN)
4550 && current_templates
40fb9820 4551 && current_templates->start->opcode_modifier.isprefix)
29b0f896 4552 {
c6fb90c8 4553 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 4554 {
4555 as_bad ((flag_code != CODE_64BIT
4556 ? _("`%s' is only supported in 64-bit mode")
4557 : _("`%s' is not supported in 64-bit mode")),
4558 current_templates->start->name);
4559 return NULL;
4560 }
29b0f896
AM		 4561 /* If we are in 16-bit mode, do not allow addr16 or data16.
4562 Similarly, in 32-bit mode, do not allow addr32 or data32. */
673fe0f0
JB		 4563 if ((current_templates->start->opcode_modifier.size == SIZE16
4564 || current_templates->start->opcode_modifier.size == SIZE32)
29b0f896 4565 && flag_code != CODE_64BIT
673fe0f0 4566 && ((current_templates->start->opcode_modifier.size == SIZE32)
29b0f896
AM		 4567 ^ (flag_code == CODE_16BIT)))
4568 {
4569 as_bad (_("redundant %s prefix"),
4570 current_templates->start->name);
4571 return NULL;
45288df1 4572 }
86fa6981 4573 if (current_templates->start->opcode_length == 0)
29b0f896 4574 {
86fa6981
L		 4575 /* Handle pseudo prefixes. */
4576 switch (current_templates->start->base_opcode)
4577 {
4578 case 0x0:
4579 /* {disp8} */
4580 i.disp_encoding = disp_encoding_8bit;
4581 break;
4582 case 0x1:
4583 /* {disp32} */
4584 i.disp_encoding = disp_encoding_32bit;
4585 break;
4586 case 0x2:
4587 /* {load} */
4588 i.dir_encoding = dir_encoding_load;
4589 break;
4590 case 0x3:
4591 /* {store} */
4592 i.dir_encoding = dir_encoding_store;
4593 break;
4594 case 0x4:
4595 /* {vex2} */
4596 i.vec_encoding = vex_encoding_vex2;
4597 break;
4598 case 0x5:
4599 /* {vex3} */
4600 i.vec_encoding = vex_encoding_vex3;
4601 break;
4602 case 0x6:
4603 /* {evex} */
4604 i.vec_encoding = vex_encoding_evex;
4605 break;
6b6b6807
L		 4606 case 0x7:
4607 /* {rex} */
4608 i.rex_encoding = TRUE;
4609 break;
b6f8c7c4
L		 4610 case 0x8:
4611 /* {nooptimize} */
4612 i.no_optimize = TRUE;
4613 break;
86fa6981
L		 4614 default:
4615 abort ();
4616 }
4617 }
4618 else
4619 {
4620 /* Add prefix, checking for repeated prefixes. */
4e9ac44a 4621 switch (add_prefix (current_templates->start->base_opcode))
86fa6981 4622 {
4e9ac44a
L		 4623 case PREFIX_EXIST:
4624 return NULL;
4625 case PREFIX_DS:
d777820b 4626 if (current_templates->start->cpu_flags.bitfield.cpuibt)
4e9ac44a
L		 4627 i.notrack_prefix = current_templates->start->name;
4628 break;
4629 case PREFIX_REP:
4630 if (current_templates->start->cpu_flags.bitfield.cpuhle)
4631 i.hle_prefix = current_templates->start->name;
4632 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
4633 i.bnd_prefix = current_templates->start->name;
4634 else
4635 i.rep_prefix = current_templates->start->name;
4636 break;
4637 default:
4638 break;
86fa6981 4639 }
29b0f896
AM		 4640 }
4641 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4642 token_start = ++l;
4643 }
4644 else
4645 break;
4646 }
45288df1 4647
30a55f88 4648 if (!current_templates)
b6169b20 4649 {
07d5e953
JB		 4650 /* Deprecated functionality (new code should use pseudo-prefixes instead):
4651 Check if we should swap operand or force 32bit displacement in
f8a5c266 4652 encoding. */
30a55f88 4653 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
64c49ab3 4654 i.dir_encoding = dir_encoding_swap;
8d63c93e 4655 else if (mnem_p - 3 == dot_p
a501d77e
L		 4656 && dot_p[1] == 'd'
4657 && dot_p[2] == '8')
4658 i.disp_encoding = disp_encoding_8bit;
8d63c93e 4659 else if (mnem_p - 4 == dot_p
f8a5c266
L		 4660 && dot_p[1] == 'd'
4661 && dot_p[2] == '3'
4662 && dot_p[3] == '2')
a501d77e 4663 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 4664 else
4665 goto check_suffix;
4666 mnem_p = dot_p;
4667 *dot_p = '\0';
d3ce72d0 4668 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 4669 }
4670
29b0f896
AM		 4671 if (!current_templates)
4672 {
b6169b20 4673check_suffix:
1c529385 4674 if (mnem_p > mnemonic)
29b0f896 4675 {
1c529385
LH		 4676 /* See if we can get a match by trimming off a suffix. */
4677 switch (mnem_p[-1])
29b0f896 4678 {
1c529385
LH		 4679 case WORD_MNEM_SUFFIX:
4680 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
29b0f896
AM		 4681 i.suffix = SHORT_MNEM_SUFFIX;
4682 else
1c529385
LH		 4683 /* Fall through. */
4684 case BYTE_MNEM_SUFFIX:
4685 case QWORD_MNEM_SUFFIX:
4686 i.suffix = mnem_p[-1];
29b0f896 4687 mnem_p[-1] = '\0';
d3ce72d0 4688 current_templates = (const templates *) hash_find (op_hash,
1c529385
LH		 4689 mnemonic);
4690 break;
4691 case SHORT_MNEM_SUFFIX:
4692 case LONG_MNEM_SUFFIX:
4693 if (!intel_syntax)
4694 {
4695 i.suffix = mnem_p[-1];
4696 mnem_p[-1] = '\0';
4697 current_templates = (const templates *) hash_find (op_hash,
4698 mnemonic);
4699 }
4700 break;
4701
4702 /* Intel Syntax. */
4703 case 'd':
4704 if (intel_syntax)
4705 {
4706 if (intel_float_operand (mnemonic) == 1)
4707 i.suffix = SHORT_MNEM_SUFFIX;
4708 else
4709 i.suffix = LONG_MNEM_SUFFIX;
4710 mnem_p[-1] = '\0';
4711 current_templates = (const templates *) hash_find (op_hash,
4712 mnemonic);
4713 }
4714 break;
29b0f896 4715 }
29b0f896 4716 }
1c529385 4717
29b0f896
AM		 4718 if (!current_templates)
4719 {
4720 as_bad (_("no such instruction: `%s'"), token_start);
4721 return NULL;
4722 }
4723 }
252b5132 4724
40fb9820
L		 4725 if (current_templates->start->opcode_modifier.jump
4726 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 4727 {
4728 /* Check for a branch hint. We allow ",pt" and ",pn" for
4729 predict taken and predict not taken respectively.
4730 I'm not sure that branch hints actually do anything on loop
4731 and jcxz insns (JumpByte) for current Pentium4 chips. They
4732 may work in the future and it doesn't hurt to accept them
4733 now. */
4734 if (l[0] == ',' && l[1] == 'p')
4735 {
4736 if (l[2] == 't')
4737 {
4738 if (!add_prefix (DS_PREFIX_OPCODE))
4739 return NULL;
4740 l += 3;
4741 }
4742 else if (l[2] == 'n')
4743 {
4744 if (!add_prefix (CS_PREFIX_OPCODE))
4745 return NULL;
4746 l += 3;
4747 }
4748 }
4749 }
4750 /* Any other comma loses. */
4751 if (*l == ',')
4752 {
4753 as_bad (_("invalid character %s in mnemonic"),
4754 output_invalid (*l));
4755 return NULL;
4756 }
252b5132 4757
29b0f896 4758 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 4759 supported = 0;
4760 for (t = current_templates->start; t < current_templates->end; ++t)
4761 {
c0f3af97
L		 4762 supported |= cpu_flags_match (t);
4763 if (supported == CPU_FLAGS_PERFECT_MATCH)
548d0ee6
JB		 4764 {
4765 if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT))
4766 as_warn (_("use .code16 to ensure correct addressing mode"));
3629bb00 4767
548d0ee6
JB		 4768 return l;
4769 }
29b0f896 4770 }
3629bb00 4771
548d0ee6
JB		 4772 if (!(supported & CPU_FLAGS_64BIT_MATCH))
4773 as_bad (flag_code == CODE_64BIT
4774 ? _("`%s' is not supported in 64-bit mode")
4775 : _("`%s' is only supported in 64-bit mode"),
4776 current_templates->start->name);
4777 else
4778 as_bad (_("`%s' is not supported on `%s%s'"),
4779 current_templates->start->name,
4780 cpu_arch_name ? cpu_arch_name : default_arch,
4781 cpu_sub_arch_name ? cpu_sub_arch_name : "");
252b5132 4782
548d0ee6 4783 return NULL;
29b0f896 4784}
252b5132 4785
29b0f896 4786static char *
e3bb37b5 4787parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 4788{
4789 char *token_start;
3138f287 4790
29b0f896
AM		 4791 /* 1 if operand is pending after ','. */
4792 unsigned int expecting_operand = 0;
252b5132 4793
29b0f896
AM		 4794 /* Non-zero if operand parens not balanced. */
4795 unsigned int paren_not_balanced;
4796
4797 while (*l != END_OF_INSN)
4798 {
4799 /* Skip optional white space before operand. */
4800 if (is_space_char (*l))
4801 ++l;
d02603dc 4802 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
29b0f896
AM		 4803 {
4804 as_bad (_("invalid character %s before operand %d"),
4805 output_invalid (*l),
4806 i.operands + 1);
4807 return NULL;
4808 }
d02603dc 4809 token_start = l; /* After white space. */
29b0f896
AM		 4810 paren_not_balanced = 0;
4811 while (paren_not_balanced || *l != ',')
4812 {
4813 if (*l == END_OF_INSN)
4814 {
4815 if (paren_not_balanced)
4816 {
4817 if (!intel_syntax)
4818 as_bad (_("unbalanced parenthesis in operand %d."),
4819 i.operands + 1);
4820 else
4821 as_bad (_("unbalanced brackets in operand %d."),
4822 i.operands + 1);
4823 return NULL;
4824 }
4825 else
4826 break; /* we are done */
4827 }
d02603dc 4828 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
29b0f896
AM		 4829 {
4830 as_bad (_("invalid character %s in operand %d"),
4831 output_invalid (*l),
4832 i.operands + 1);
4833 return NULL;
4834 }
4835 if (!intel_syntax)
4836 {
4837 if (*l == '(')
4838 ++paren_not_balanced;
4839 if (*l == ')')
4840 --paren_not_balanced;
4841 }
4842 else
4843 {
4844 if (*l == '[')
4845 ++paren_not_balanced;
4846 if (*l == ']')
4847 --paren_not_balanced;
4848 }
4849 l++;
4850 }
4851 if (l != token_start)
4852 { /* Yes, we've read in another operand. */
4853 unsigned int operand_ok;
4854 this_operand = i.operands++;
4855 if (i.operands > MAX_OPERANDS)
4856 {
4857 as_bad (_("spurious operands; (%d operands/instruction max)"),
4858 MAX_OPERANDS);
4859 return NULL;
4860 }
9d46ce34 4861 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 4862 /* Now parse operand adding info to 'i' as we go along. */
4863 END_STRING_AND_SAVE (l);
4864
1286ab78
L		 4865 if (i.mem_operands > 1)
4866 {
4867 as_bad (_("too many memory references for `%s'"),
4868 mnemonic);
4869 return 0;
4870 }
4871
29b0f896
AM		 4872 if (intel_syntax)
4873 operand_ok =
4874 i386_intel_operand (token_start,
4875 intel_float_operand (mnemonic));
4876 else
a7619375 4877 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 4878
4879 RESTORE_END_STRING (l);
4880 if (!operand_ok)
4881 return NULL;
4882 }
4883 else
4884 {
4885 if (expecting_operand)
4886 {
4887 expecting_operand_after_comma:
4888 as_bad (_("expecting operand after ','; got nothing"));
4889 return NULL;
4890 }
4891 if (*l == ',')
4892 {
4893 as_bad (_("expecting operand before ','; got nothing"));
4894 return NULL;
4895 }
4896 }
7f3f1ea2 4897
29b0f896
AM		 4898 /* Now *l must be either ',' or END_OF_INSN. */
4899 if (*l == ',')
4900 {
4901 if (*++l == END_OF_INSN)
4902 {
4903 /* Just skip it, if it's \n complain. */
4904 goto expecting_operand_after_comma;
4905 }
4906 expecting_operand = 1;
4907 }
4908 }
4909 return l;
4910}
7f3f1ea2 4911
050dfa73 4912static void
4d456e3d 4913swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 4914{
4915 union i386_op temp_op;
40fb9820 4916 i386_operand_type temp_type;
c48dadc9 4917 unsigned int temp_flags;
050dfa73 4918 enum bfd_reloc_code_real temp_reloc;
4eed87de 4919
050dfa73
MM		 4920 temp_type = i.types[xchg2];
4921 i.types[xchg2] = i.types[xchg1];
4922 i.types[xchg1] = temp_type;
c48dadc9
JB		 4923
4924 temp_flags = i.flags[xchg2];
4925 i.flags[xchg2] = i.flags[xchg1];
4926 i.flags[xchg1] = temp_flags;
4927
050dfa73
MM		 4928 temp_op = i.op[xchg2];
4929 i.op[xchg2] = i.op[xchg1];
4930 i.op[xchg1] = temp_op;
c48dadc9 4931
050dfa73
MM		 4932 temp_reloc = i.reloc[xchg2];
4933 i.reloc[xchg2] = i.reloc[xchg1];
4934 i.reloc[xchg1] = temp_reloc;
43234a1e
L		 4935
4936 if (i.mask)
4937 {
4938 if (i.mask->operand == xchg1)
4939 i.mask->operand = xchg2;
4940 else if (i.mask->operand == xchg2)
4941 i.mask->operand = xchg1;
4942 }
4943 if (i.broadcast)
4944 {
4945 if (i.broadcast->operand == xchg1)
4946 i.broadcast->operand = xchg2;
4947 else if (i.broadcast->operand == xchg2)
4948 i.broadcast->operand = xchg1;
4949 }
4950 if (i.rounding)
4951 {
4952 if (i.rounding->operand == xchg1)
4953 i.rounding->operand = xchg2;
4954 else if (i.rounding->operand == xchg2)
4955 i.rounding->operand = xchg1;
4956 }
050dfa73
MM		 4957}
4958
29b0f896 4959static void
e3bb37b5 4960swap_operands (void)
29b0f896 4961{
b7c61d9a 4962 switch (i.operands)
050dfa73 4963 {
c0f3af97 4964 case 5:
b7c61d9a 4965 case 4:
4d456e3d 4966 swap_2_operands (1, i.operands - 2);
1a0670f3 4967 /* Fall through. */
b7c61d9a
L		 4968 case 3:
4969 case 2:
4d456e3d 4970 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 4971 break;
4972 default:
4973 abort ();
29b0f896 4974 }
29b0f896
AM		 4975
4976 if (i.mem_operands == 2)
4977 {
4978 const seg_entry *temp_seg;
4979 temp_seg = i.seg[0];
4980 i.seg[0] = i.seg[1];
4981 i.seg[1] = temp_seg;
4982 }
4983}
252b5132 4984
29b0f896
AM		 4985/* Try to ensure constant immediates are represented in the smallest
4986 opcode possible. */
4987static void
e3bb37b5 4988optimize_imm (void)
29b0f896
AM		 4989{
4990 char guess_suffix = 0;
4991 int op;
252b5132 4992
29b0f896
AM		 4993 if (i.suffix)
4994 guess_suffix = i.suffix;
4995 else if (i.reg_operands)
4996 {
4997 /* Figure out a suffix from the last register operand specified.
4998 We can't do this properly yet, ie. excluding InOutPortReg,
4999 but the following works for instructions with immediates.
5000 In any case, we can't set i.suffix yet. */
5001 for (op = i.operands; --op >= 0;)
dc821c5f 5002 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
7ab9ffdd 5003 {
40fb9820
L		 5004 guess_suffix = BYTE_MNEM_SUFFIX;
5005 break;
5006 }
dc821c5f 5007 else if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
252b5132 5008 {
40fb9820
L		 5009 guess_suffix = WORD_MNEM_SUFFIX;
5010 break;
5011 }
dc821c5f 5012 else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
40fb9820
L		 5013 {
5014 guess_suffix = LONG_MNEM_SUFFIX;
5015 break;
5016 }
dc821c5f 5017 else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
40fb9820
L		 5018 {
5019 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 5020 break;
252b5132 5021 }
29b0f896
AM		 5022 }
5023 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
5024 guess_suffix = WORD_MNEM_SUFFIX;
5025
5026 for (op = i.operands; --op >= 0;)
40fb9820 5027 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 5028 {
5029 switch (i.op[op].imms->X_op)
252b5132 5030 {
29b0f896
AM		 5031 case O_constant:
5032 /* If a suffix is given, this operand may be shortened. */
5033 switch (guess_suffix)
252b5132 5034 {
29b0f896 5035 case LONG_MNEM_SUFFIX:
40fb9820
L		 5036 i.types[op].bitfield.imm32 = 1;
5037 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 5038 break;
5039 case WORD_MNEM_SUFFIX:
40fb9820
L		 5040 i.types[op].bitfield.imm16 = 1;
5041 i.types[op].bitfield.imm32 = 1;
5042 i.types[op].bitfield.imm32s = 1;
5043 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 5044 break;
5045 case BYTE_MNEM_SUFFIX:
40fb9820
L		 5046 i.types[op].bitfield.imm8 = 1;
5047 i.types[op].bitfield.imm8s = 1;
5048 i.types[op].bitfield.imm16 = 1;
5049 i.types[op].bitfield.imm32 = 1;
5050 i.types[op].bitfield.imm32s = 1;
5051 i.types[op].bitfield.imm64 = 1;
29b0f896 5052 break;
252b5132 5053 }
252b5132 5054
29b0f896
AM		 5055 /* If this operand is at most 16 bits, convert it
5056 to a signed 16 bit number before trying to see
5057 whether it will fit in an even smaller size.
5058 This allows a 16-bit operand such as $0xffe0 to
5059 be recognised as within Imm8S range. */
40fb9820 5060 if ((i.types[op].bitfield.imm16)
29b0f896 5061 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 5062 {
29b0f896
AM		 5063 i.op[op].imms->X_add_number =
5064 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
5065 }
a28def75
L		 5066#ifdef BFD64
5067 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
40fb9820 5068 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 5069 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
5070 == 0))
5071 {
5072 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
5073 ^ ((offsetT) 1 << 31))
5074 - ((offsetT) 1 << 31));
5075 }
a28def75 5076#endif
40fb9820 5077 i.types[op]
c6fb90c8
L		 5078 = operand_type_or (i.types[op],
5079 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 5080
29b0f896
AM		 5081 /* We must avoid matching of Imm32 templates when 64bit
5082 only immediate is available. */
5083 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 5084 i.types[op].bitfield.imm32 = 0;
29b0f896 5085 break;
252b5132 5086
29b0f896
AM		 5087 case O_absent:
5088 case O_register:
5089 abort ();
5090
5091 /* Symbols and expressions. */
5092 default:
9cd96992
JB		 5093 /* Convert symbolic operand to proper sizes for matching, but don't
5094 prevent matching a set of insns that only supports sizes other
5095 than those matching the insn suffix. */
5096 {
40fb9820 5097 i386_operand_type mask, allowed;
d3ce72d0 5098 const insn_template *t;
9cd96992 5099
0dfbf9d7
L		 5100 operand_type_set (&mask, 0);
5101 operand_type_set (&allowed, 0);
40fb9820 5102
4eed87de
AM		 5103 for (t = current_templates->start;
5104 t < current_templates->end;
5105 ++t)
c6fb90c8
L		 5106 allowed = operand_type_or (allowed,
5107 t->operand_types[op]);
9cd96992
JB		 5108 switch (guess_suffix)
5109 {
5110 case QWORD_MNEM_SUFFIX:
40fb9820
L		 5111 mask.bitfield.imm64 = 1;
5112 mask.bitfield.imm32s = 1;
9cd96992
JB		 5113 break;
5114 case LONG_MNEM_SUFFIX:
40fb9820 5115 mask.bitfield.imm32 = 1;
9cd96992
JB		 5116 break;
5117 case WORD_MNEM_SUFFIX:
40fb9820 5118 mask.bitfield.imm16 = 1;
9cd96992
JB		 5119 break;
5120 case BYTE_MNEM_SUFFIX:
40fb9820 5121 mask.bitfield.imm8 = 1;
9cd96992
JB		 5122 break;
5123 default:
9cd96992
JB		 5124 break;
5125 }
c6fb90c8 5126 allowed = operand_type_and (mask, allowed);
0dfbf9d7 5127 if (!operand_type_all_zero (&allowed))
c6fb90c8 5128 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 5129 }
29b0f896 5130 break;
252b5132 5131 }
29b0f896
AM		 5132 }
5133}
47926f60 5134
29b0f896
AM		 5135/* Try to use the smallest displacement type too. */
5136static void
e3bb37b5 5137optimize_disp (void)
29b0f896
AM		 5138{
5139 int op;
3e73aa7c 5140
29b0f896 5141 for (op = i.operands; --op >= 0;)
40fb9820 5142 if (operand_type_check (i.types[op], disp))
252b5132 5143 {
b300c311 5144 if (i.op[op].disps->X_op == O_constant)
252b5132 5145 {
91d6fa6a 5146 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 5147
40fb9820 5148 if (i.types[op].bitfield.disp16
91d6fa6a 5149 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 5150 {
5151 /* If this operand is at most 16 bits, convert
5152 to a signed 16 bit number and don't use 64bit
5153 displacement. */
91d6fa6a 5154 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 5155 i.types[op].bitfield.disp64 = 0;
b300c311 5156 }
a28def75
L		 5157#ifdef BFD64
5158 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
40fb9820 5159 if (i.types[op].bitfield.disp32
91d6fa6a 5160 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 5161 {
5162 /* If this operand is at most 32 bits, convert
5163 to a signed 32 bit number and don't use 64bit
5164 displacement. */
91d6fa6a
NC		 5165 op_disp &= (((offsetT) 2 << 31) - 1);
5166 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 5167 i.types[op].bitfield.disp64 = 0;
b300c311 5168 }
a28def75 5169#endif
91d6fa6a 5170 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 5171 {
40fb9820
L		 5172 i.types[op].bitfield.disp8 = 0;
5173 i.types[op].bitfield.disp16 = 0;
5174 i.types[op].bitfield.disp32 = 0;
5175 i.types[op].bitfield.disp32s = 0;
5176 i.types[op].bitfield.disp64 = 0;
b300c311
L		 5177 i.op[op].disps = 0;
5178 i.disp_operands--;
5179 }
5180 else if (flag_code == CODE_64BIT)
5181 {
91d6fa6a 5182 if (fits_in_signed_long (op_disp))
28a9d8f5 5183 {
40fb9820
L		 5184 i.types[op].bitfield.disp64 = 0;
5185 i.types[op].bitfield.disp32s = 1;
28a9d8f5 5186 }
0e1147d9 5187 if (i.prefix[ADDR_PREFIX]
91d6fa6a 5188 && fits_in_unsigned_long (op_disp))
40fb9820 5189 i.types[op].bitfield.disp32 = 1;
b300c311 5190 }
40fb9820
L		 5191 if ((i.types[op].bitfield.disp32
5192 || i.types[op].bitfield.disp32s
5193 || i.types[op].bitfield.disp16)
b5014f7a 5194 && fits_in_disp8 (op_disp))
40fb9820 5195 i.types[op].bitfield.disp8 = 1;
252b5132 5196 }
67a4f2b7
AO		 5197 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
5198 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
5199 {
5200 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
5201 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 5202 i.types[op].bitfield.disp8 = 0;
5203 i.types[op].bitfield.disp16 = 0;
5204 i.types[op].bitfield.disp32 = 0;
5205 i.types[op].bitfield.disp32s = 0;
5206 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 5207 }
5208 else
b300c311 5209 /* We only support 64bit displacement on constants. */
40fb9820 5210 i.types[op].bitfield.disp64 = 0;
252b5132 5211 }
29b0f896
AM		 5212}
5213
4a1b91ea
L		 5214/* Return 1 if there is a match in broadcast bytes between operand
5215 GIVEN and instruction template T. */
5216
5217static INLINE int
5218match_broadcast_size (const insn_template *t, unsigned int given)
5219{
5220 return ((t->opcode_modifier.broadcast == BYTE_BROADCAST
5221 && i.types[given].bitfield.byte)
5222 || (t->opcode_modifier.broadcast == WORD_BROADCAST
5223 && i.types[given].bitfield.word)
5224 || (t->opcode_modifier.broadcast == DWORD_BROADCAST
5225 && i.types[given].bitfield.dword)
5226 || (t->opcode_modifier.broadcast == QWORD_BROADCAST
5227 && i.types[given].bitfield.qword));
5228}
5229
6c30d220
L		 5230/* Check if operands are valid for the instruction. */
5231
5232static int
5233check_VecOperands (const insn_template *t)
5234{
43234a1e 5235 unsigned int op;
e2195274
JB		 5236 i386_cpu_flags cpu;
5237 static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS;
5238
5239 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5240 any one operand are implicity requiring AVX512VL support if the actual
5241 operand size is YMMword or XMMword. Since this function runs after
5242 template matching, there's no need to check for YMMword/XMMword in
5243 the template. */
5244 cpu = cpu_flags_and (t->cpu_flags, avx512);
5245 if (!cpu_flags_all_zero (&cpu)
5246 && !t->cpu_flags.bitfield.cpuavx512vl
5247 && !cpu_arch_flags.bitfield.cpuavx512vl)
5248 {
5249 for (op = 0; op < t->operands; ++op)
5250 {
5251 if (t->operand_types[op].bitfield.zmmword
5252 && (i.types[op].bitfield.ymmword
5253 || i.types[op].bitfield.xmmword))
5254 {
5255 i.error = unsupported;
5256 return 1;
5257 }
5258 }
5259 }
43234a1e 5260
6c30d220
L		 5261 /* Without VSIB byte, we can't have a vector register for index. */
5262 if (!t->opcode_modifier.vecsib
5263 && i.index_reg
1b54b8d7
JB		 5264 && (i.index_reg->reg_type.bitfield.xmmword
5265 || i.index_reg->reg_type.bitfield.ymmword
5266 || i.index_reg->reg_type.bitfield.zmmword))
6c30d220
L		 5267 {
5268 i.error = unsupported_vector_index_register;
5269 return 1;
5270 }
5271
ad8ecc81
MZ		 5272 /* Check if default mask is allowed. */
5273 if (t->opcode_modifier.nodefmask
5274 && (!i.mask || i.mask->mask->reg_num == 0))
5275 {
5276 i.error = no_default_mask;
5277 return 1;
5278 }
5279
7bab8ab5
JB		 5280 /* For VSIB byte, we need a vector register for index, and all vector
5281 registers must be distinct. */
5282 if (t->opcode_modifier.vecsib)
5283 {
5284 if (!i.index_reg
6c30d220 5285 || !((t->opcode_modifier.vecsib == VecSIB128
1b54b8d7 5286 && i.index_reg->reg_type.bitfield.xmmword)
6c30d220 5287 || (t->opcode_modifier.vecsib == VecSIB256
1b54b8d7 5288 && i.index_reg->reg_type.bitfield.ymmword)
43234a1e 5289 || (t->opcode_modifier.vecsib == VecSIB512
1b54b8d7 5290 && i.index_reg->reg_type.bitfield.zmmword)))
7bab8ab5
JB		 5291 {
5292 i.error = invalid_vsib_address;
5293 return 1;
5294 }
5295
43234a1e
L		 5296 gas_assert (i.reg_operands == 2 || i.mask);
5297 if (i.reg_operands == 2 && !i.mask)
5298 {
1b54b8d7
JB		 5299 gas_assert (i.types[0].bitfield.regsimd);
5300 gas_assert (i.types[0].bitfield.xmmword
5301 || i.types[0].bitfield.ymmword);
5302 gas_assert (i.types[2].bitfield.regsimd);
5303 gas_assert (i.types[2].bitfield.xmmword
5304 || i.types[2].bitfield.ymmword);
43234a1e
L		 5305 if (operand_check == check_none)
5306 return 0;
5307 if (register_number (i.op[0].regs)
5308 != register_number (i.index_reg)
5309 && register_number (i.op[2].regs)
5310 != register_number (i.index_reg)
5311 && register_number (i.op[0].regs)
5312 != register_number (i.op[2].regs))
5313 return 0;
5314 if (operand_check == check_error)
5315 {
5316 i.error = invalid_vector_register_set;
5317 return 1;
5318 }
5319 as_warn (_("mask, index, and destination registers should be distinct"));
5320 }
8444f82a
MZ		 5321 else if (i.reg_operands == 1 && i.mask)
5322 {
1b54b8d7
JB		 5323 if (i.types[1].bitfield.regsimd
5324 && (i.types[1].bitfield.xmmword
5325 || i.types[1].bitfield.ymmword
5326 || i.types[1].bitfield.zmmword)
8444f82a
MZ		 5327 && (register_number (i.op[1].regs)
5328 == register_number (i.index_reg)))
5329 {
5330 if (operand_check == check_error)
5331 {
5332 i.error = invalid_vector_register_set;
5333 return 1;
5334 }
5335 if (operand_check != check_none)
5336 as_warn (_("index and destination registers should be distinct"));
5337 }
5338 }
43234a1e 5339 }
7bab8ab5 5340
43234a1e
L		 5341 /* Check if broadcast is supported by the instruction and is applied
5342 to the memory operand. */
5343 if (i.broadcast)
5344 {
8e6e0792 5345 i386_operand_type type, overlap;
43234a1e
L		 5346
5347 /* Check if specified broadcast is supported in this instruction,
4a1b91ea 5348 and its broadcast bytes match the memory operand. */
32546502 5349 op = i.broadcast->operand;
8e6e0792 5350 if (!t->opcode_modifier.broadcast
c48dadc9 5351 || !(i.flags[op] & Operand_Mem)
c39e5b26 5352 || (!i.types[op].bitfield.unspecified
4a1b91ea 5353 && !match_broadcast_size (t, op)))
43234a1e
L		 5354 {
5355 bad_broadcast:
5356 i.error = unsupported_broadcast;
5357 return 1;
5358 }
8e6e0792 5359
4a1b91ea
L		 5360 i.broadcast->bytes = ((1 << (t->opcode_modifier.broadcast - 1))
5361 * i.broadcast->type);
8e6e0792 5362 operand_type_set (&type, 0);
4a1b91ea 5363 switch (i.broadcast->bytes)
8e6e0792 5364 {
4a1b91ea
L		 5365 case 2:
5366 type.bitfield.word = 1;
5367 break;
5368 case 4:
5369 type.bitfield.dword = 1;
5370 break;
8e6e0792
JB		 5371 case 8:
5372 type.bitfield.qword = 1;
5373 break;
5374 case 16:
5375 type.bitfield.xmmword = 1;
5376 break;
5377 case 32:
5378 type.bitfield.ymmword = 1;
5379 break;
5380 case 64:
5381 type.bitfield.zmmword = 1;
5382 break;
5383 default:
5384 goto bad_broadcast;
5385 }
5386
5387 overlap = operand_type_and (type, t->operand_types[op]);
5388 if (operand_type_all_zero (&overlap))
5389 goto bad_broadcast;
5390
5391 if (t->opcode_modifier.checkregsize)
5392 {
5393 unsigned int j;
5394
e2195274 5395 type.bitfield.baseindex = 1;
8e6e0792
JB		 5396 for (j = 0; j < i.operands; ++j)
5397 {
5398 if (j != op
5399 && !operand_type_register_match(i.types[j],
5400 t->operand_types[j],
5401 type,
5402 t->operand_types[op]))
5403 goto bad_broadcast;
5404 }
5405 }
43234a1e
L		 5406 }
5407 /* If broadcast is supported in this instruction, we need to check if
5408 operand of one-element size isn't specified without broadcast. */
5409 else if (t->opcode_modifier.broadcast && i.mem_operands)
5410 {
5411 /* Find memory operand. */
5412 for (op = 0; op < i.operands; op++)
5413 if (operand_type_check (i.types[op], anymem))
5414 break;
5415 gas_assert (op < i.operands);
5416 /* Check size of the memory operand. */
4a1b91ea 5417 if (match_broadcast_size (t, op))
43234a1e
L		 5418 {
5419 i.error = broadcast_needed;
5420 return 1;
5421 }
5422 }
c39e5b26
JB		 5423 else
5424 op = MAX_OPERANDS - 1; /* Avoid uninitialized variable warning. */
43234a1e
L		 5425
5426 /* Check if requested masking is supported. */
ae2387fe 5427 if (i.mask)
43234a1e 5428 {
ae2387fe
JB		 5429 switch (t->opcode_modifier.masking)
5430 {
5431 case BOTH_MASKING:
5432 break;
5433 case MERGING_MASKING:
5434 if (i.mask->zeroing)
5435 {
5436 case 0:
5437 i.error = unsupported_masking;
5438 return 1;
5439 }
5440 break;
5441 case DYNAMIC_MASKING:
5442 /* Memory destinations allow only merging masking. */
5443 if (i.mask->zeroing && i.mem_operands)
5444 {
5445 /* Find memory operand. */
5446 for (op = 0; op < i.operands; op++)
c48dadc9 5447 if (i.flags[op] & Operand_Mem)
ae2387fe
JB		 5448 break;
5449 gas_assert (op < i.operands);
5450 if (op == i.operands - 1)
5451 {
5452 i.error = unsupported_masking;
5453 return 1;
5454 }
5455 }
5456 break;
5457 default:
5458 abort ();
5459 }
43234a1e
L		 5460 }
5461
5462 /* Check if masking is applied to dest operand. */
5463 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
5464 {
5465 i.error = mask_not_on_destination;
5466 return 1;
5467 }
5468
43234a1e
L		 5469 /* Check RC/SAE. */
5470 if (i.rounding)
5471 {
5472 if ((i.rounding->type != saeonly
5473 && !t->opcode_modifier.staticrounding)
5474 || (i.rounding->type == saeonly
5475 && (t->opcode_modifier.staticrounding
5476 || !t->opcode_modifier.sae)))
5477 {
5478 i.error = unsupported_rc_sae;
5479 return 1;
5480 }
5481 /* If the instruction has several immediate operands and one of
5482 them is rounding, the rounding operand should be the last
5483 immediate operand. */
5484 if (i.imm_operands > 1
5485 && i.rounding->operand != (int) (i.imm_operands - 1))
7bab8ab5 5486 {
43234a1e 5487 i.error = rc_sae_operand_not_last_imm;
7bab8ab5
JB		 5488 return 1;
5489 }
6c30d220
L		 5490 }
5491
43234a1e 5492 /* Check vector Disp8 operand. */
b5014f7a
JB		 5493 if (t->opcode_modifier.disp8memshift
5494 && i.disp_encoding != disp_encoding_32bit)
43234a1e
L		 5495 {
5496 if (i.broadcast)
4a1b91ea 5497 i.memshift = t->opcode_modifier.broadcast - 1;
7091c612 5498 else if (t->opcode_modifier.disp8memshift != DISP8_SHIFT_VL)
43234a1e 5499 i.memshift = t->opcode_modifier.disp8memshift;
7091c612
JB		 5500 else
5501 {
5502 const i386_operand_type *type = NULL;
5503
5504 i.memshift = 0;
5505 for (op = 0; op < i.operands; op++)
5506 if (operand_type_check (i.types[op], anymem))
5507 {
4174bfff
JB		 5508 if (t->opcode_modifier.evex == EVEXLIG)
5509 i.memshift = 2 + (i.suffix == QWORD_MNEM_SUFFIX);
5510 else if (t->operand_types[op].bitfield.xmmword
5511 + t->operand_types[op].bitfield.ymmword
5512 + t->operand_types[op].bitfield.zmmword <= 1)
7091c612
JB		 5513 type = &t->operand_types[op];
5514 else if (!i.types[op].bitfield.unspecified)
5515 type = &i.types[op];
5516 }
4174bfff
JB		 5517 else if (i.types[op].bitfield.regsimd
5518 && t->opcode_modifier.evex != EVEXLIG)
7091c612
JB		 5519 {
5520 if (i.types[op].bitfield.zmmword)
5521 i.memshift = 6;
5522 else if (i.types[op].bitfield.ymmword && i.memshift < 5)
5523 i.memshift = 5;
5524 else if (i.types[op].bitfield.xmmword && i.memshift < 4)
5525 i.memshift = 4;
5526 }
5527
5528 if (type)
5529 {
5530 if (type->bitfield.zmmword)
5531 i.memshift = 6;
5532 else if (type->bitfield.ymmword)
5533 i.memshift = 5;
5534 else if (type->bitfield.xmmword)
5535 i.memshift = 4;
5536 }
5537
5538 /* For the check in fits_in_disp8(). */
5539 if (i.memshift == 0)
5540 i.memshift = -1;
5541 }
43234a1e
L		 5542
5543 for (op = 0; op < i.operands; op++)
5544 if (operand_type_check (i.types[op], disp)
5545 && i.op[op].disps->X_op == O_constant)
5546 {
b5014f7a 5547 if (fits_in_disp8 (i.op[op].disps->X_add_number))
43234a1e 5548 {
b5014f7a
JB		 5549 i.types[op].bitfield.disp8 = 1;
5550 return 0;
43234a1e 5551 }
b5014f7a 5552 i.types[op].bitfield.disp8 = 0;
43234a1e
L		 5553 }
5554 }
b5014f7a
JB		 5555
5556 i.memshift = 0;
43234a1e 5557
6c30d220
L		 5558 return 0;
5559}
5560
43f3e2ee 5561/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 5562 operand types. */
5563
5564static int
5565VEX_check_operands (const insn_template *t)
5566{
86fa6981 5567 if (i.vec_encoding == vex_encoding_evex)
43234a1e 5568 {
86fa6981 5569 /* This instruction must be encoded with EVEX prefix. */
e771e7c9 5570 if (!is_evex_encoding (t))
86fa6981
L		 5571 {
5572 i.error = unsupported;
5573 return 1;
5574 }
5575 return 0;
43234a1e
L		 5576 }
5577
a683cc34 5578 if (!t->opcode_modifier.vex)
86fa6981
L		 5579 {
5580 /* This instruction template doesn't have VEX prefix. */
5581 if (i.vec_encoding != vex_encoding_default)
5582 {
5583 i.error = unsupported;
5584 return 1;
5585 }
5586 return 0;
5587 }
a683cc34
SP		 5588
5589 /* Only check VEX_Imm4, which must be the first operand. */
5590 if (t->operand_types[0].bitfield.vec_imm4)
5591 {
5592 if (i.op[0].imms->X_op != O_constant
5593 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 5594 {
a65babc9 5595 i.error = bad_imm4;
891edac4
L		 5596 return 1;
5597 }
a683cc34
SP		 5598
5599 /* Turn off Imm8 so that update_imm won't complain. */
5600 i.types[0] = vec_imm4;
5601 }
5602
5603 return 0;
5604}
5605
d3ce72d0 5606static const insn_template *
83b16ac6 5607match_template (char mnem_suffix)
29b0f896
AM		 5608{
5609 /* Points to template once we've found it. */
d3ce72d0 5610 const insn_template *t;
40fb9820 5611 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 5612 i386_operand_type overlap4;
29b0f896 5613 unsigned int found_reverse_match;
83b16ac6 5614 i386_opcode_modifier suffix_check, mnemsuf_check;
40fb9820 5615 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 5616 int addr_prefix_disp;
a5c311ca 5617 unsigned int j;
3ac21baa 5618 unsigned int found_cpu_match, size_match;
45664ddb 5619 unsigned int check_register;
5614d22c 5620 enum i386_error specific_error = 0;
29b0f896 5621
c0f3af97
L		 5622#if MAX_OPERANDS != 5
5623# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 5624#endif
5625
29b0f896 5626 found_reverse_match = 0;
539e75ad 5627 addr_prefix_disp = -1;
40fb9820
L		 5628
5629 memset (&suffix_check, 0, sizeof (suffix_check));
e2195274
JB		 5630 if (intel_syntax && i.broadcast)
5631 /* nothing */;
5632 else if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 5633 suffix_check.no_bsuf = 1;
5634 else if (i.suffix == WORD_MNEM_SUFFIX)
5635 suffix_check.no_wsuf = 1;
5636 else if (i.suffix == SHORT_MNEM_SUFFIX)
5637 suffix_check.no_ssuf = 1;
5638 else if (i.suffix == LONG_MNEM_SUFFIX)
5639 suffix_check.no_lsuf = 1;
5640 else if (i.suffix == QWORD_MNEM_SUFFIX)
5641 suffix_check.no_qsuf = 1;
5642 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 5643 suffix_check.no_ldsuf = 1;
29b0f896 5644
83b16ac6
JB		 5645 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
5646 if (intel_syntax)
5647 {
5648 switch (mnem_suffix)
5649 {
5650 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
5651 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
5652 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
5653 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
5654 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
5655 }
5656 }
5657
01559ecc
L		 5658 /* Must have right number of operands. */
5659 i.error = number_of_operands_mismatch;
5660
45aa61fe 5661 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 5662 {
539e75ad 5663 addr_prefix_disp = -1;
dbbc8b7e 5664 found_reverse_match = 0;
539e75ad 5665
29b0f896
AM		 5666 if (i.operands != t->operands)
5667 continue;
5668
50aecf8c 5669 /* Check processor support. */
a65babc9 5670 i.error = unsupported;
c0f3af97
L		 5671 found_cpu_match = (cpu_flags_match (t)
5672 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 5673 if (!found_cpu_match)
5674 continue;
5675
e1d4d893 5676 /* Check AT&T mnemonic. */
a65babc9 5677 i.error = unsupported_with_intel_mnemonic;
e1d4d893 5678 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 5679 continue;
5680
e92bae62 5681 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
a65babc9 5682 i.error = unsupported_syntax;
5c07affc 5683 if ((intel_syntax && t->opcode_modifier.attsyntax)
e92bae62
L		 5684 || (!intel_syntax && t->opcode_modifier.intelsyntax)
5685 || (intel64 && t->opcode_modifier.amd64)
5686 || (!intel64 && t->opcode_modifier.intel64))
1efbbeb4
L		 5687 continue;
5688
20592a94 5689 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 5690 i.error = invalid_instruction_suffix;
567e4e96
L		 5691 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
5692 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
5693 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
5694 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
5695 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
5696 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
5697 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896 5698 continue;
83b16ac6
JB		 5699 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5700 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
5701 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
5702 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
5703 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
5704 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
5705 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
5706 continue;
29b0f896 5707
3ac21baa
JB		 5708 size_match = operand_size_match (t);
5709 if (!size_match)
7d5e4556 5710 continue;
539e75ad 5711
5c07affc
L		 5712 for (j = 0; j < MAX_OPERANDS; j++)
5713 operand_types[j] = t->operand_types[j];
5714
45aa61fe
AM		 5715 /* In general, don't allow 64-bit operands in 32-bit mode. */
5716 if (i.suffix == QWORD_MNEM_SUFFIX
5717 && flag_code != CODE_64BIT
5718 && (intel_syntax
40fb9820 5719 ? (!t->opcode_modifier.ignoresize
625cbd7a 5720 && !t->opcode_modifier.broadcast
45aa61fe
AM		 5721 && !intel_float_operand (t->name))
5722 : intel_float_operand (t->name) != 2)
40fb9820 5723 && ((!operand_types[0].bitfield.regmmx
1b54b8d7 5724 && !operand_types[0].bitfield.regsimd)
40fb9820 5725 || (!operand_types[t->operands > 1].bitfield.regmmx
1b54b8d7 5726 && !operand_types[t->operands > 1].bitfield.regsimd))
45aa61fe
AM		 5727 && (t->base_opcode != 0x0fc7
5728 || t->extension_opcode != 1 /* cmpxchg8b */))
5729 continue;
5730
192dc9c6
JB		 5731 /* In general, don't allow 32-bit operands on pre-386. */
5732 else if (i.suffix == LONG_MNEM_SUFFIX
5733 && !cpu_arch_flags.bitfield.cpui386
5734 && (intel_syntax
5735 ? (!t->opcode_modifier.ignoresize
5736 && !intel_float_operand (t->name))
5737 : intel_float_operand (t->name) != 2)
5738 && ((!operand_types[0].bitfield.regmmx
1b54b8d7 5739 && !operand_types[0].bitfield.regsimd)
192dc9c6 5740 || (!operand_types[t->operands > 1].bitfield.regmmx
1b54b8d7 5741 && !operand_types[t->operands > 1].bitfield.regsimd)))
192dc9c6
JB		 5742 continue;
5743
29b0f896 5744 /* Do not verify operands when there are none. */
50aecf8c 5745 else
29b0f896 5746 {
c6fb90c8 5747 if (!t->operands)
2dbab7d5
L		 5748 /* We've found a match; break out of loop. */
5749 break;
29b0f896 5750 }
252b5132 5751
539e75ad
L		 5752 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5753 into Disp32/Disp16/Disp32 operand. */
5754 if (i.prefix[ADDR_PREFIX] != 0)
5755 {
40fb9820 5756 /* There should be only one Disp operand. */
539e75ad
L		 5757 switch (flag_code)
5758 {
5759 case CODE_16BIT:
40fb9820
L		 5760 for (j = 0; j < MAX_OPERANDS; j++)
5761 {
5762 if (operand_types[j].bitfield.disp16)
5763 {
5764 addr_prefix_disp = j;
5765 operand_types[j].bitfield.disp32 = 1;
5766 operand_types[j].bitfield.disp16 = 0;
5767 break;
5768 }
5769 }
539e75ad
L		 5770 break;
5771 case CODE_32BIT:
40fb9820
L		 5772 for (j = 0; j < MAX_OPERANDS; j++)
5773 {
5774 if (operand_types[j].bitfield.disp32)
5775 {
5776 addr_prefix_disp = j;
5777 operand_types[j].bitfield.disp32 = 0;
5778 operand_types[j].bitfield.disp16 = 1;
5779 break;
5780 }
5781 }
539e75ad
L		 5782 break;
5783 case CODE_64BIT:
40fb9820
L		 5784 for (j = 0; j < MAX_OPERANDS; j++)
5785 {
5786 if (operand_types[j].bitfield.disp64)
5787 {
5788 addr_prefix_disp = j;
5789 operand_types[j].bitfield.disp64 = 0;
5790 operand_types[j].bitfield.disp32 = 1;
5791 break;
5792 }
5793 }
539e75ad
L		 5794 break;
5795 }
539e75ad
L		 5796 }
5797
02a86693
L		 5798 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5799 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
5800 continue;
5801
56ffb741 5802 /* We check register size if needed. */
e2195274
JB		 5803 if (t->opcode_modifier.checkregsize)
5804 {
5805 check_register = (1 << t->operands) - 1;
5806 if (i.broadcast)
5807 check_register &= ~(1 << i.broadcast->operand);
5808 }
5809 else
5810 check_register = 0;
5811
c6fb90c8 5812 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 5813 switch (t->operands)
5814 {
5815 case 1:
40fb9820 5816 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 5817 continue;
5818 break;
5819 case 2:
33eaf5de 5820 /* xchg %eax, %eax is a special case. It is an alias for nop
8b38ad71
L		 5821 only in 32bit mode and we can use opcode 0x90. In 64bit
5822 mode, we can't use 0x90 for xchg %eax, %eax since it should
5823 zero-extend %eax to %rax. */
5824 if (flag_code == CODE_64BIT
5825 && t->base_opcode == 0x90
2c703856
JB		 5826 && i.types[0].bitfield.acc && i.types[0].bitfield.dword
5827 && i.types[1].bitfield.acc && i.types[1].bitfield.dword)
8b38ad71 5828 continue;
1212781b
JB		 5829 /* xrelease mov %eax, <disp> is another special case. It must not
5830 match the accumulator-only encoding of mov. */
5831 if (flag_code != CODE_64BIT
5832 && i.hle_prefix
5833 && t->base_opcode == 0xa0
5834 && i.types[0].bitfield.acc
5835 && operand_type_check (i.types[1], anymem))
5836 continue;
f5eb1d70
JB		 5837 /* Fall through. */
5838
5839 case 3:
3ac21baa
JB		 5840 if (!(size_match & MATCH_STRAIGHT))
5841 goto check_reverse;
64c49ab3
JB		 5842 /* Reverse direction of operands if swapping is possible in the first
5843 place (operands need to be symmetric) and
5844 - the load form is requested, and the template is a store form,
5845 - the store form is requested, and the template is a load form,
5846 - the non-default (swapped) form is requested. */
5847 overlap1 = operand_type_and (operand_types[0], operand_types[1]);
f5eb1d70 5848 if (t->opcode_modifier.d && i.reg_operands == i.operands
64c49ab3
JB		 5849 && !operand_type_all_zero (&overlap1))
5850 switch (i.dir_encoding)
5851 {
5852 case dir_encoding_load:
5853 if (operand_type_check (operand_types[i.operands - 1], anymem)
5854 || operand_types[i.operands - 1].bitfield.regmem)
5855 goto check_reverse;
5856 break;
5857
5858 case dir_encoding_store:
5859 if (!operand_type_check (operand_types[i.operands - 1], anymem)
5860 && !operand_types[i.operands - 1].bitfield.regmem)
5861 goto check_reverse;
5862 break;
5863
5864 case dir_encoding_swap:
5865 goto check_reverse;
5866
5867 case dir_encoding_default:
5868 break;
5869 }
86fa6981 5870 /* If we want store form, we skip the current load. */
64c49ab3
JB		 5871 if ((i.dir_encoding == dir_encoding_store
5872 || i.dir_encoding == dir_encoding_swap)
86fa6981
L		 5873 && i.mem_operands == 0
5874 && t->opcode_modifier.load)
fa99fab2 5875 continue;
1a0670f3 5876 /* Fall through. */
f48ff2ae 5877 case 4:
c0f3af97 5878 case 5:
c6fb90c8 5879 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 5880 if (!operand_type_match (overlap0, i.types[0])
5881 || !operand_type_match (overlap1, i.types[1])
e2195274 5882 || ((check_register & 3) == 3
dc821c5f 5883 && !operand_type_register_match (i.types[0],
40fb9820 5884 operand_types[0],
dc821c5f 5885 i.types[1],
40fb9820 5886 operand_types[1])))
29b0f896
AM		 5887 {
5888 /* Check if other direction is valid ... */
38e314eb 5889 if (!t->opcode_modifier.d)
29b0f896
AM		 5890 continue;
5891
b6169b20 5892check_reverse:
3ac21baa
JB		 5893 if (!(size_match & MATCH_REVERSE))
5894 continue;
29b0f896 5895 /* Try reversing direction of operands. */
f5eb1d70
JB		 5896 overlap0 = operand_type_and (i.types[0], operand_types[i.operands - 1]);
5897 overlap1 = operand_type_and (i.types[i.operands - 1], operand_types[0]);
40fb9820 5898 if (!operand_type_match (overlap0, i.types[0])
f5eb1d70 5899 || !operand_type_match (overlap1, i.types[i.operands - 1])
45664ddb 5900 || (check_register
dc821c5f 5901 && !operand_type_register_match (i.types[0],
f5eb1d70
JB		 5902 operand_types[i.operands - 1],
5903 i.types[i.operands - 1],
45664ddb 5904 operand_types[0])))
29b0f896
AM		 5905 {
5906 /* Does not match either direction. */
5907 continue;
5908 }
38e314eb 5909 /* found_reverse_match holds which of D or FloatR
29b0f896 5910 we've found. */
38e314eb
JB		 5911 if (!t->opcode_modifier.d)
5912 found_reverse_match = 0;
5913 else if (operand_types[0].bitfield.tbyte)
8a2ed489 5914 found_reverse_match = Opcode_FloatD;
dbbc8b7e 5915 else if (operand_types[0].bitfield.xmmword
f5eb1d70 5916 || operand_types[i.operands - 1].bitfield.xmmword
dbbc8b7e 5917 || operand_types[0].bitfield.regmmx
f5eb1d70 5918 || operand_types[i.operands - 1].bitfield.regmmx
dbbc8b7e
JB		 5919 || is_any_vex_encoding(t))
5920 found_reverse_match = (t->base_opcode & 0xee) != 0x6e
5921 ? Opcode_SIMD_FloatD : Opcode_SIMD_IntD;
8a2ed489 5922 else
38e314eb 5923 found_reverse_match = Opcode_D;
40fb9820 5924 if (t->opcode_modifier.floatr)
8a2ed489 5925 found_reverse_match |= Opcode_FloatR;
29b0f896 5926 }
f48ff2ae 5927 else
29b0f896 5928 {
f48ff2ae 5929 /* Found a forward 2 operand match here. */
d1cbb4db
L		 5930 switch (t->operands)
5931 {
c0f3af97
L		 5932 case 5:
5933 overlap4 = operand_type_and (i.types[4],
5934 operand_types[4]);
1a0670f3 5935 /* Fall through. */
d1cbb4db 5936 case 4:
c6fb90c8
L		 5937 overlap3 = operand_type_and (i.types[3],
5938 operand_types[3]);
1a0670f3 5939 /* Fall through. */
d1cbb4db 5940 case 3:
c6fb90c8
L		 5941 overlap2 = operand_type_and (i.types[2],
5942 operand_types[2]);
d1cbb4db
L		 5943 break;
5944 }
29b0f896 5945
f48ff2ae
L		 5946 switch (t->operands)
5947 {
c0f3af97
L		 5948 case 5:
5949 if (!operand_type_match (overlap4, i.types[4])
dc821c5f 5950 || !operand_type_register_match (i.types[3],
c0f3af97 5951 operand_types[3],
c0f3af97
L		 5952 i.types[4],
5953 operand_types[4]))
5954 continue;
1a0670f3 5955 /* Fall through. */
f48ff2ae 5956 case 4:
40fb9820 5957 if (!operand_type_match (overlap3, i.types[3])
e2195274
JB		 5958 || ((check_register & 0xa) == 0xa
5959 && !operand_type_register_match (i.types[1],
f7768225
JB		 5960 operand_types[1],
5961 i.types[3],
e2195274
JB		 5962 operand_types[3]))
5963 || ((check_register & 0xc) == 0xc
5964 && !operand_type_register_match (i.types[2],
5965 operand_types[2],
5966 i.types[3],
5967 operand_types[3])))
f48ff2ae 5968 continue;
1a0670f3 5969 /* Fall through. */
f48ff2ae
L		 5970 case 3:
5971 /* Here we make use of the fact that there are no
23e42951 5972 reverse match 3 operand instructions. */
40fb9820 5973 if (!operand_type_match (overlap2, i.types[2])
e2195274
JB		 5974 || ((check_register & 5) == 5
5975 && !operand_type_register_match (i.types[0],
23e42951
JB		 5976 operand_types[0],
5977 i.types[2],
e2195274
JB		 5978 operand_types[2]))
5979 || ((check_register & 6) == 6
5980 && !operand_type_register_match (i.types[1],
5981 operand_types[1],
5982 i.types[2],
5983 operand_types[2])))
f48ff2ae
L		 5984 continue;
5985 break;
5986 }
29b0f896 5987 }
f48ff2ae 5988 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 5989 slip through to break. */
5990 }
3629bb00 5991 if (!found_cpu_match)
dbbc8b7e 5992 continue;
c0f3af97 5993
5614d22c
JB		 5994 /* Check if vector and VEX operands are valid. */
5995 if (check_VecOperands (t) || VEX_check_operands (t))
5996 {
5997 specific_error = i.error;
5998 continue;
5999 }
a683cc34 6000
29b0f896
AM		 6001 /* We've found a match; break out of loop. */
6002 break;
6003 }
6004
6005 if (t == current_templates->end)
6006 {
6007 /* We found no match. */
a65babc9 6008 const char *err_msg;
5614d22c 6009 switch (specific_error ? specific_error : i.error)
a65babc9
L		 6010 {
6011 default:
6012 abort ();
86e026a4 6013 case operand_size_mismatch:
a65babc9
L		 6014 err_msg = _("operand size mismatch");
6015 break;
6016 case operand_type_mismatch:
6017 err_msg = _("operand type mismatch");
6018 break;
6019 case register_type_mismatch:
6020 err_msg = _("register type mismatch");
6021 break;
6022 case number_of_operands_mismatch:
6023 err_msg = _("number of operands mismatch");
6024 break;
6025 case invalid_instruction_suffix:
6026 err_msg = _("invalid instruction suffix");
6027 break;
6028 case bad_imm4:
4a2608e3 6029 err_msg = _("constant doesn't fit in 4 bits");
a65babc9 6030 break;
a65babc9
L		 6031 case unsupported_with_intel_mnemonic:
6032 err_msg = _("unsupported with Intel mnemonic");
6033 break;
6034 case unsupported_syntax:
6035 err_msg = _("unsupported syntax");
6036 break;
6037 case unsupported:
35262a23 6038 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 6039 current_templates->start->name);
6040 return NULL;
6c30d220
L		 6041 case invalid_vsib_address:
6042 err_msg = _("invalid VSIB address");
6043 break;
7bab8ab5
JB		 6044 case invalid_vector_register_set:
6045 err_msg = _("mask, index, and destination registers must be distinct");
6046 break;
6c30d220
L		 6047 case unsupported_vector_index_register:
6048 err_msg = _("unsupported vector index register");
6049 break;
43234a1e
L		 6050 case unsupported_broadcast:
6051 err_msg = _("unsupported broadcast");
6052 break;
43234a1e
L		 6053 case broadcast_needed:
6054 err_msg = _("broadcast is needed for operand of such type");
6055 break;
6056 case unsupported_masking:
6057 err_msg = _("unsupported masking");
6058 break;
6059 case mask_not_on_destination:
6060 err_msg = _("mask not on destination operand");
6061 break;
6062 case no_default_mask:
6063 err_msg = _("default mask isn't allowed");
6064 break;
6065 case unsupported_rc_sae:
6066 err_msg = _("unsupported static rounding/sae");
6067 break;
6068 case rc_sae_operand_not_last_imm:
6069 if (intel_syntax)
6070 err_msg = _("RC/SAE operand must precede immediate operands");
6071 else
6072 err_msg = _("RC/SAE operand must follow immediate operands");
6073 break;
6074 case invalid_register_operand:
6075 err_msg = _("invalid register operand");
6076 break;
a65babc9
L		 6077 }
6078 as_bad (_("%s for `%s'"), err_msg,
891edac4 6079 current_templates->start->name);
fa99fab2 6080 return NULL;
29b0f896 6081 }
252b5132 6082
29b0f896
AM		 6083 if (!quiet_warnings)
6084 {
6085 if (!intel_syntax
40fb9820
L		 6086 && (i.types[0].bitfield.jumpabsolute
6087 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 6088 {
6089 as_warn (_("indirect %s without `*'"), t->name);
6090 }
6091
40fb9820
L		 6092 if (t->opcode_modifier.isprefix
6093 && t->opcode_modifier.ignoresize)
29b0f896
AM		 6094 {
6095 /* Warn them that a data or address size prefix doesn't
6096 affect assembly of the next line of code. */
6097 as_warn (_("stand-alone `%s' prefix"), t->name);
6098 }
6099 }
6100
6101 /* Copy the template we found. */
6102 i.tm = *t;
539e75ad
L		 6103
6104 if (addr_prefix_disp != -1)
6105 i.tm.operand_types[addr_prefix_disp]
6106 = operand_types[addr_prefix_disp];
6107
29b0f896
AM		 6108 if (found_reverse_match)
6109 {
6110 /* If we found a reverse match we must alter the opcode
6111 direction bit. found_reverse_match holds bits to change
6112 (different for int & float insns). */
6113
6114 i.tm.base_opcode ^= found_reverse_match;
6115
f5eb1d70
JB		 6116 i.tm.operand_types[0] = operand_types[i.operands - 1];
6117 i.tm.operand_types[i.operands - 1] = operand_types[0];
29b0f896
AM		 6118 }
6119
fa99fab2 6120 return t;
29b0f896
AM		 6121}
6122
6123static int
e3bb37b5 6124check_string (void)
29b0f896 6125{
40fb9820
L		 6126 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
6127 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 6128 {
6129 if (i.seg[0] != NULL && i.seg[0] != &es)
6130 {
a87af027 6131 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 6132 i.tm.name,
a87af027
JB		 6133 mem_op + 1,
6134 register_prefix);
29b0f896
AM		 6135 return 0;
6136 }
6137 /* There's only ever one segment override allowed per instruction.
6138 This instruction possibly has a legal segment override on the
6139 second operand, so copy the segment to where non-string
6140 instructions store it, allowing common code. */
6141 i.seg[0] = i.seg[1];
6142 }
40fb9820 6143 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 6144 {
6145 if (i.seg[1] != NULL && i.seg[1] != &es)
6146 {
a87af027 6147 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 6148 i.tm.name,
a87af027
JB		 6149 mem_op + 2,
6150 register_prefix);
29b0f896
AM		 6151 return 0;
6152 }
6153 }
6154 return 1;
6155}
6156
6157static int
543613e9 6158process_suffix (void)
29b0f896
AM		 6159{
6160 /* If matched instruction specifies an explicit instruction mnemonic
6161 suffix, use it. */
673fe0f0 6162 if (i.tm.opcode_modifier.size == SIZE16)
40fb9820 6163 i.suffix = WORD_MNEM_SUFFIX;
673fe0f0 6164 else if (i.tm.opcode_modifier.size == SIZE32)
40fb9820 6165 i.suffix = LONG_MNEM_SUFFIX;
673fe0f0 6166 else if (i.tm.opcode_modifier.size == SIZE64)
40fb9820 6167 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 6168 else if (i.reg_operands)
6169 {
6170 /* If there's no instruction mnemonic suffix we try to invent one
6171 based on register operands. */
6172 if (!i.suffix)
6173 {
6174 /* We take i.suffix from the last register operand specified,
6175 Destination register type is more significant than source
381d071f
L		 6176 register type. crc32 in SSE4.2 prefers source register
6177 type. */
556059dd 6178 if (i.tm.base_opcode == 0xf20f38f0 && i.types[0].bitfield.reg)
381d071f 6179 {
556059dd
JB		 6180 if (i.types[0].bitfield.byte)
6181 i.suffix = BYTE_MNEM_SUFFIX;
6182 else if (i.types[0].bitfield.word)
40fb9820 6183 i.suffix = WORD_MNEM_SUFFIX;
556059dd 6184 else if (i.types[0].bitfield.dword)
40fb9820 6185 i.suffix = LONG_MNEM_SUFFIX;
556059dd 6186 else if (i.types[0].bitfield.qword)
40fb9820 6187 i.suffix = QWORD_MNEM_SUFFIX;
381d071f
L		 6188 }
6189
6190 if (!i.suffix)
6191 {
6192 int op;
6193
556059dd 6194 if (i.tm.base_opcode == 0xf20f38f0)
20592a94
L		 6195 {
6196 /* We have to know the operand size for crc32. */
6197 as_bad (_("ambiguous memory operand size for `%s`"),
6198 i.tm.name);
6199 return 0;
6200 }
6201
381d071f 6202 for (op = i.operands; --op >= 0;)
b76bc5d5
JB		 6203 if (!i.tm.operand_types[op].bitfield.inoutportreg
6204 && !i.tm.operand_types[op].bitfield.shiftcount)
381d071f 6205 {
8819ada6
JB		 6206 if (!i.types[op].bitfield.reg)
6207 continue;
6208 if (i.types[op].bitfield.byte)
6209 i.suffix = BYTE_MNEM_SUFFIX;
6210 else if (i.types[op].bitfield.word)
6211 i.suffix = WORD_MNEM_SUFFIX;
6212 else if (i.types[op].bitfield.dword)
6213 i.suffix = LONG_MNEM_SUFFIX;
6214 else if (i.types[op].bitfield.qword)
6215 i.suffix = QWORD_MNEM_SUFFIX;
6216 else
6217 continue;
6218 break;
381d071f
L		 6219 }
6220 }
29b0f896
AM		 6221 }
6222 else if (i.suffix == BYTE_MNEM_SUFFIX)
6223 {
2eb952a4
L		 6224 if (intel_syntax
6225 && i.tm.opcode_modifier.ignoresize
6226 && i.tm.opcode_modifier.no_bsuf)
6227 i.suffix = 0;
6228 else if (!check_byte_reg ())
29b0f896
AM		 6229 return 0;
6230 }
6231 else if (i.suffix == LONG_MNEM_SUFFIX)
6232 {
2eb952a4
L		 6233 if (intel_syntax
6234 && i.tm.opcode_modifier.ignoresize
9f123b91
JB		 6235 && i.tm.opcode_modifier.no_lsuf
6236 && !i.tm.opcode_modifier.todword
6237 && !i.tm.opcode_modifier.toqword)
2eb952a4
L		 6238 i.suffix = 0;
6239 else if (!check_long_reg ())
29b0f896
AM		 6240 return 0;
6241 }
6242 else if (i.suffix == QWORD_MNEM_SUFFIX)
6243 {
955e1e6a
L		 6244 if (intel_syntax
6245 && i.tm.opcode_modifier.ignoresize
9f123b91
JB		 6246 && i.tm.opcode_modifier.no_qsuf
6247 && !i.tm.opcode_modifier.todword
6248 && !i.tm.opcode_modifier.toqword)
955e1e6a
L		 6249 i.suffix = 0;
6250 else if (!check_qword_reg ())
29b0f896
AM		 6251 return 0;
6252 }
6253 else if (i.suffix == WORD_MNEM_SUFFIX)
6254 {
2eb952a4
L		 6255 if (intel_syntax
6256 && i.tm.opcode_modifier.ignoresize
6257 && i.tm.opcode_modifier.no_wsuf)
6258 i.suffix = 0;
6259 else if (!check_word_reg ())
29b0f896
AM		 6260 return 0;
6261 }
40fb9820 6262 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 6263 /* Do nothing if the instruction is going to ignore the prefix. */
6264 ;
6265 else
6266 abort ();
6267 }
40fb9820 6268 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 6269 && !i.suffix
6270 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 6271 && i.tm.opcode_modifier.no_ssuf)
29b0f896 6272 {
06f74c5c
L		 6273 if (stackop_size == LONG_MNEM_SUFFIX
6274 && i.tm.base_opcode == 0xcf)
6275 {
6276 /* stackop_size is set to LONG_MNEM_SUFFIX for the
6277 .code16gcc directive to support 16-bit mode with
6278 32-bit address. For IRET without a suffix, generate
6279 16-bit IRET (opcode 0xcf) to return from an interrupt
6280 handler. */
6281 i.suffix = WORD_MNEM_SUFFIX;
6282 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
6283 }
6284 else
6285 i.suffix = stackop_size;
29b0f896 6286 }
9306ca4a
JB		 6287 else if (intel_syntax
6288 && !i.suffix
40fb9820
L		 6289 && (i.tm.operand_types[0].bitfield.jumpabsolute
6290 || i.tm.opcode_modifier.jumpbyte
6291 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 6292 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
6293 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 6294 {
6295 switch (flag_code)
6296 {
6297 case CODE_64BIT:
40fb9820 6298 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 6299 {
6300 i.suffix = QWORD_MNEM_SUFFIX;
6301 break;
6302 }
1a0670f3 6303 /* Fall through. */
9306ca4a 6304 case CODE_32BIT:
40fb9820 6305 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 6306 i.suffix = LONG_MNEM_SUFFIX;
6307 break;
6308 case CODE_16BIT:
40fb9820 6309 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 6310 i.suffix = WORD_MNEM_SUFFIX;
6311 break;
6312 }
6313 }
252b5132 6314
9306ca4a 6315 if (!i.suffix)
29b0f896 6316 {
9306ca4a
JB		 6317 if (!intel_syntax)
6318 {
40fb9820 6319 if (i.tm.opcode_modifier.w)
9306ca4a 6320 {
4eed87de
AM		 6321 as_bad (_("no instruction mnemonic suffix given and "
6322 "no register operands; can't size instruction"));
9306ca4a
JB		 6323 return 0;
6324 }
6325 }
6326 else
6327 {
40fb9820 6328 unsigned int suffixes;
7ab9ffdd 6329
40fb9820
L		 6330 suffixes = !i.tm.opcode_modifier.no_bsuf;
6331 if (!i.tm.opcode_modifier.no_wsuf)
6332 suffixes |= 1 << 1;
6333 if (!i.tm.opcode_modifier.no_lsuf)
6334 suffixes |= 1 << 2;
fc4adea1 6335 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 6336 suffixes |= 1 << 3;
6337 if (!i.tm.opcode_modifier.no_ssuf)
6338 suffixes |= 1 << 4;
c2b9da16 6339 if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
40fb9820
L		 6340 suffixes |= 1 << 5;
6341
6342 /* There are more than suffix matches. */
6343 if (i.tm.opcode_modifier.w
9306ca4a 6344 || ((suffixes & (suffixes - 1))
40fb9820
L		 6345 && !i.tm.opcode_modifier.defaultsize
6346 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 6347 {
6348 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
6349 return 0;
6350 }
6351 }
29b0f896 6352 }
252b5132 6353
d2224064
JB		 6354 /* Change the opcode based on the operand size given by i.suffix. */
6355 switch (i.suffix)
29b0f896 6356 {
d2224064
JB		 6357 /* Size floating point instruction. */
6358 case LONG_MNEM_SUFFIX:
6359 if (i.tm.opcode_modifier.floatmf)
6360 {
6361 i.tm.base_opcode ^= 4;
6362 break;
6363 }
6364 /* fall through */
6365 case WORD_MNEM_SUFFIX:
6366 case QWORD_MNEM_SUFFIX:
29b0f896 6367 /* It's not a byte, select word/dword operation. */
40fb9820 6368 if (i.tm.opcode_modifier.w)
29b0f896 6369 {
40fb9820 6370 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 6371 i.tm.base_opcode |= 8;
6372 else
6373 i.tm.base_opcode |= 1;
6374 }
d2224064
JB		 6375 /* fall through */
6376 case SHORT_MNEM_SUFFIX:
29b0f896
AM		 6377 /* Now select between word & dword operations via the operand
6378 size prefix, except for instructions that will ignore this
6379 prefix anyway. */
75c0a438
L		 6380 if (i.reg_operands > 0
6381 && i.types[0].bitfield.reg
6382 && i.tm.opcode_modifier.addrprefixopreg
6383 && (i.tm.opcode_modifier.immext
6384 || i.operands == 1))
cb712a9e 6385 {
ca61edf2
L		 6386 /* The address size override prefix changes the size of the
6387 first operand. */
40fb9820 6388 if ((flag_code == CODE_32BIT
75c0a438 6389 && i.op[0].regs->reg_type.bitfield.word)
40fb9820 6390 || (flag_code != CODE_32BIT
75c0a438 6391 && i.op[0].regs->reg_type.bitfield.dword))
cb712a9e
L		 6392 if (!add_prefix (ADDR_PREFIX_OPCODE))
6393 return 0;
6394 }
6395 else if (i.suffix != QWORD_MNEM_SUFFIX
40fb9820
L		 6396 && !i.tm.opcode_modifier.ignoresize
6397 && !i.tm.opcode_modifier.floatmf
a38d7118 6398 && !is_any_vex_encoding (&i.tm)
cb712a9e
L		 6399 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
6400 || (flag_code == CODE_64BIT
40fb9820 6401 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 6402 {
6403 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 6404
40fb9820 6405 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 6406 prefix = ADDR_PREFIX_OPCODE;
252b5132 6407
29b0f896
AM		 6408 if (!add_prefix (prefix))
6409 return 0;
24eab124 6410 }
252b5132 6411
29b0f896
AM		 6412 /* Set mode64 for an operand. */
6413 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 6414 && flag_code == CODE_64BIT
d2224064 6415 && !i.tm.opcode_modifier.norex64
46e883c5 6416 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d2224064
JB		 6417 need rex64. */
6418 && ! (i.operands == 2
6419 && i.tm.base_opcode == 0x90
6420 && i.tm.extension_opcode == None
2c703856
JB		 6421 && i.types[0].bitfield.acc && i.types[0].bitfield.qword
6422 && i.types[1].bitfield.acc && i.types[1].bitfield.qword))
d2224064 6423 i.rex |= REX_W;
3e73aa7c 6424
d2224064 6425 break;
29b0f896 6426 }
7ecd2f8b 6427
c0a30a9f
L		 6428 if (i.reg_operands != 0
6429 && i.operands > 1
6430 && i.tm.opcode_modifier.addrprefixopreg
6431 && !i.tm.opcode_modifier.immext)
6432 {
6433 /* Check invalid register operand when the address size override
6434 prefix changes the size of register operands. */
6435 unsigned int op;
6436 enum { need_word, need_dword, need_qword } need;
6437
6438 if (flag_code == CODE_32BIT)
6439 need = i.prefix[ADDR_PREFIX] ? need_word : need_dword;
6440 else
6441 {
6442 if (i.prefix[ADDR_PREFIX])
6443 need = need_dword;
6444 else
6445 need = flag_code == CODE_64BIT ? need_qword : need_word;
6446 }
6447
6448 for (op = 0; op < i.operands; op++)
6449 if (i.types[op].bitfield.reg
6450 && ((need == need_word
6451 && !i.op[op].regs->reg_type.bitfield.word)
6452 || (need == need_dword
6453 && !i.op[op].regs->reg_type.bitfield.dword)
6454 || (need == need_qword
6455 && !i.op[op].regs->reg_type.bitfield.qword)))
6456 {
6457 as_bad (_("invalid register operand size for `%s'"),
6458 i.tm.name);
6459 return 0;
6460 }
6461 }
6462
29b0f896
AM		 6463 return 1;
6464}
3e73aa7c 6465
29b0f896 6466static int
543613e9 6467check_byte_reg (void)
29b0f896
AM		 6468{
6469 int op;
543613e9 6470
29b0f896
AM		 6471 for (op = i.operands; --op >= 0;)
6472 {
dc821c5f
JB		 6473 /* Skip non-register operands. */
6474 if (!i.types[op].bitfield.reg)
6475 continue;
6476
29b0f896
AM		 6477 /* If this is an eight bit register, it's OK. If it's the 16 or
6478 32 bit version of an eight bit register, we will just use the
6479 low portion, and that's OK too. */
dc821c5f 6480 if (i.types[op].bitfield.byte)
29b0f896
AM		 6481 continue;
6482
5a819eb9
JB		 6483 /* I/O port address operands are OK too. */
6484 if (i.tm.operand_types[op].bitfield.inoutportreg)
6485 continue;
6486
9344ff29
L		 6487 /* crc32 doesn't generate this warning. */
6488 if (i.tm.base_opcode == 0xf20f38f0)
6489 continue;
6490
dc821c5f
JB		 6491 if ((i.types[op].bitfield.word
6492 || i.types[op].bitfield.dword
6493 || i.types[op].bitfield.qword)
5a819eb9
JB		 6494 && i.op[op].regs->reg_num < 4
6495 /* Prohibit these changes in 64bit mode, since the lowering
6496 would be more complicated. */
6497 && flag_code != CODE_64BIT)
29b0f896 6498 {
29b0f896 6499#if REGISTER_WARNINGS
5a819eb9 6500 if (!quiet_warnings)
a540244d
L		 6501 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6502 register_prefix,
dc821c5f 6503 (i.op[op].regs + (i.types[op].bitfield.word
29b0f896
AM		 6504 ? REGNAM_AL - REGNAM_AX
6505 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 6506 register_prefix,
29b0f896
AM		 6507 i.op[op].regs->reg_name,
6508 i.suffix);
6509#endif
6510 continue;
6511 }
6512 /* Any other register is bad. */
dc821c5f 6513 if (i.types[op].bitfield.reg
40fb9820 6514 || i.types[op].bitfield.regmmx
1b54b8d7 6515 || i.types[op].bitfield.regsimd
40fb9820
L		 6516 || i.types[op].bitfield.sreg2
6517 || i.types[op].bitfield.sreg3
6518 || i.types[op].bitfield.control
6519 || i.types[op].bitfield.debug
ca0d63fe 6520 || i.types[op].bitfield.test)
29b0f896 6521 {
a540244d
L		 6522 as_bad (_("`%s%s' not allowed with `%s%c'"),
6523 register_prefix,
29b0f896
AM		 6524 i.op[op].regs->reg_name,
6525 i.tm.name,
6526 i.suffix);
6527 return 0;
6528 }
6529 }
6530 return 1;
6531}
6532
6533static int
e3bb37b5 6534check_long_reg (void)
29b0f896
AM		 6535{
6536 int op;
6537
6538 for (op = i.operands; --op >= 0;)
dc821c5f
JB		 6539 /* Skip non-register operands. */
6540 if (!i.types[op].bitfield.reg)
6541 continue;
29b0f896
AM		 6542 /* Reject eight bit registers, except where the template requires
6543 them. (eg. movzb) */
dc821c5f
JB		 6544 else if (i.types[op].bitfield.byte
6545 && (i.tm.operand_types[op].bitfield.reg
6546 || i.tm.operand_types[op].bitfield.acc)
6547 && (i.tm.operand_types[op].bitfield.word
6548 || i.tm.operand_types[op].bitfield.dword))
29b0f896 6549 {
a540244d
L		 6550 as_bad (_("`%s%s' not allowed with `%s%c'"),
6551 register_prefix,
29b0f896
AM		 6552 i.op[op].regs->reg_name,
6553 i.tm.name,
6554 i.suffix);
6555 return 0;
6556 }
e4630f71 6557 /* Warn if the e prefix on a general reg is missing. */
29b0f896 6558 else if ((!quiet_warnings || flag_code == CODE_64BIT)
dc821c5f
JB		 6559 && i.types[op].bitfield.word
6560 && (i.tm.operand_types[op].bitfield.reg
6561 || i.tm.operand_types[op].bitfield.acc)
6562 && i.tm.operand_types[op].bitfield.dword)
29b0f896
AM		 6563 {
6564 /* Prohibit these changes in the 64bit mode, since the
6565 lowering is more complicated. */
6566 if (flag_code == CODE_64BIT)
252b5132 6567 {
2b5d6a91 6568 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 6569 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 6570 i.suffix);
6571 return 0;
252b5132 6572 }
29b0f896 6573#if REGISTER_WARNINGS
cecf1424
JB		 6574 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6575 register_prefix,
6576 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
6577 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896 6578#endif
252b5132 6579 }
e4630f71 6580 /* Warn if the r prefix on a general reg is present. */
dc821c5f
JB		 6581 else if (i.types[op].bitfield.qword
6582 && (i.tm.operand_types[op].bitfield.reg
6583 || i.tm.operand_types[op].bitfield.acc)
6584 && i.tm.operand_types[op].bitfield.dword)
252b5132 6585 {
34828aad 6586 if (intel_syntax
ca61edf2 6587 && i.tm.opcode_modifier.toqword
1b54b8d7 6588 && !i.types[0].bitfield.regsimd)
34828aad 6589 {
ca61edf2 6590 /* Convert to QWORD. We want REX byte. */
34828aad
L		 6591 i.suffix = QWORD_MNEM_SUFFIX;
6592 }
6593 else
6594 {
2b5d6a91 6595 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 6596 register_prefix, i.op[op].regs->reg_name,
6597 i.suffix);
6598 return 0;
6599 }
29b0f896
AM		 6600 }
6601 return 1;
6602}
252b5132 6603
29b0f896 6604static int
e3bb37b5 6605check_qword_reg (void)
29b0f896
AM		 6606{
6607 int op;
252b5132 6608
29b0f896 6609 for (op = i.operands; --op >= 0; )
dc821c5f
JB		 6610 /* Skip non-register operands. */
6611 if (!i.types[op].bitfield.reg)
6612 continue;
29b0f896
AM		 6613 /* Reject eight bit registers, except where the template requires
6614 them. (eg. movzb) */
dc821c5f
JB		 6615 else if (i.types[op].bitfield.byte
6616 && (i.tm.operand_types[op].bitfield.reg
6617 || i.tm.operand_types[op].bitfield.acc)
6618 && (i.tm.operand_types[op].bitfield.word
6619 || i.tm.operand_types[op].bitfield.dword))
29b0f896 6620 {
a540244d
L		 6621 as_bad (_("`%s%s' not allowed with `%s%c'"),
6622 register_prefix,
29b0f896
AM		 6623 i.op[op].regs->reg_name,
6624 i.tm.name,
6625 i.suffix);
6626 return 0;
6627 }
e4630f71 6628 /* Warn if the r prefix on a general reg is missing. */
dc821c5f
JB		 6629 else if ((i.types[op].bitfield.word
6630 || i.types[op].bitfield.dword)
6631 && (i.tm.operand_types[op].bitfield.reg
6632 || i.tm.operand_types[op].bitfield.acc)
6633 && i.tm.operand_types[op].bitfield.qword)
29b0f896
AM		 6634 {
6635 /* Prohibit these changes in the 64bit mode, since the
6636 lowering is more complicated. */
34828aad 6637 if (intel_syntax
ca61edf2 6638 && i.tm.opcode_modifier.todword
1b54b8d7 6639 && !i.types[0].bitfield.regsimd)
34828aad 6640 {
ca61edf2 6641 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 6642 i.suffix = LONG_MNEM_SUFFIX;
6643 }
6644 else
6645 {
2b5d6a91 6646 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 6647 register_prefix, i.op[op].regs->reg_name,
6648 i.suffix);
6649 return 0;
6650 }
252b5132 6651 }
29b0f896
AM		 6652 return 1;
6653}
252b5132 6654
29b0f896 6655static int
e3bb37b5 6656check_word_reg (void)
29b0f896
AM		 6657{
6658 int op;
6659 for (op = i.operands; --op >= 0;)
dc821c5f
JB		 6660 /* Skip non-register operands. */
6661 if (!i.types[op].bitfield.reg)
6662 continue;
29b0f896
AM		 6663 /* Reject eight bit registers, except where the template requires
6664 them. (eg. movzb) */
dc821c5f
JB		 6665 else if (i.types[op].bitfield.byte
6666 && (i.tm.operand_types[op].bitfield.reg
6667 || i.tm.operand_types[op].bitfield.acc)
6668 && (i.tm.operand_types[op].bitfield.word
6669 || i.tm.operand_types[op].bitfield.dword))
29b0f896 6670 {
a540244d
L		 6671 as_bad (_("`%s%s' not allowed with `%s%c'"),
6672 register_prefix,
29b0f896
AM		 6673 i.op[op].regs->reg_name,
6674 i.tm.name,
6675 i.suffix);
6676 return 0;
6677 }
e4630f71 6678 /* Warn if the e or r prefix on a general reg is present. */
29b0f896 6679 else if ((!quiet_warnings || flag_code == CODE_64BIT)
dc821c5f
JB		 6680 && (i.types[op].bitfield.dword
6681 || i.types[op].bitfield.qword)
6682 && (i.tm.operand_types[op].bitfield.reg
6683 || i.tm.operand_types[op].bitfield.acc)
6684 && i.tm.operand_types[op].bitfield.word)
252b5132 6685 {
29b0f896
AM		 6686 /* Prohibit these changes in the 64bit mode, since the
6687 lowering is more complicated. */
6688 if (flag_code == CODE_64BIT)
252b5132 6689 {
2b5d6a91 6690 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 6691 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 6692 i.suffix);
6693 return 0;
252b5132 6694 }
29b0f896 6695#if REGISTER_WARNINGS
cecf1424
JB		 6696 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6697 register_prefix,
6698 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
6699 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896
AM		 6700#endif
6701 }
6702 return 1;
6703}
252b5132 6704
29b0f896 6705static int
40fb9820 6706update_imm (unsigned int j)
29b0f896 6707{
bc0844ae 6708 i386_operand_type overlap = i.types[j];
40fb9820
L		 6709 if ((overlap.bitfield.imm8
6710 || overlap.bitfield.imm8s
6711 || overlap.bitfield.imm16
6712 || overlap.bitfield.imm32
6713 || overlap.bitfield.imm32s
6714 || overlap.bitfield.imm64)
0dfbf9d7
L		 6715 && !operand_type_equal (&overlap, &imm8)
6716 && !operand_type_equal (&overlap, &imm8s)
6717 && !operand_type_equal (&overlap, &imm16)
6718 && !operand_type_equal (&overlap, &imm32)
6719 && !operand_type_equal (&overlap, &imm32s)
6720 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 6721 {
6722 if (i.suffix)
6723 {
40fb9820
L		 6724 i386_operand_type temp;
6725
0dfbf9d7 6726 operand_type_set (&temp, 0);
7ab9ffdd 6727 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 6728 {
6729 temp.bitfield.imm8 = overlap.bitfield.imm8;
6730 temp.bitfield.imm8s = overlap.bitfield.imm8s;
6731 }
6732 else if (i.suffix == WORD_MNEM_SUFFIX)
6733 temp.bitfield.imm16 = overlap.bitfield.imm16;
6734 else if (i.suffix == QWORD_MNEM_SUFFIX)
6735 {
6736 temp.bitfield.imm64 = overlap.bitfield.imm64;
6737 temp.bitfield.imm32s = overlap.bitfield.imm32s;
6738 }
6739 else
6740 temp.bitfield.imm32 = overlap.bitfield.imm32;
6741 overlap = temp;
29b0f896 6742 }
0dfbf9d7
L		 6743 else if (operand_type_equal (&overlap, &imm16_32_32s)
6744 || operand_type_equal (&overlap, &imm16_32)
6745 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 6746 {
40fb9820 6747 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 6748 overlap = imm16;
40fb9820 6749 else
65da13b5 6750 overlap = imm32s;
29b0f896 6751 }
0dfbf9d7
L		 6752 if (!operand_type_equal (&overlap, &imm8)
6753 && !operand_type_equal (&overlap, &imm8s)
6754 && !operand_type_equal (&overlap, &imm16)
6755 && !operand_type_equal (&overlap, &imm32)
6756 && !operand_type_equal (&overlap, &imm32s)
6757 && !operand_type_equal (&overlap, &imm64))
29b0f896 6758 {
4eed87de
AM		 6759 as_bad (_("no instruction mnemonic suffix given; "
6760 "can't determine immediate size"));
29b0f896
AM		 6761 return 0;
6762 }
6763 }
40fb9820 6764 i.types[j] = overlap;
29b0f896 6765
40fb9820
L		 6766 return 1;
6767}
6768
6769static int
6770finalize_imm (void)
6771{
bc0844ae 6772 unsigned int j, n;
29b0f896 6773
bc0844ae
L		 6774 /* Update the first 2 immediate operands. */
6775 n = i.operands > 2 ? 2 : i.operands;
6776 if (n)
6777 {
6778 for (j = 0; j < n; j++)
6779 if (update_imm (j) == 0)
6780 return 0;
40fb9820 6781
bc0844ae
L		 6782 /* The 3rd operand can't be immediate operand. */
6783 gas_assert (operand_type_check (i.types[2], imm) == 0);
6784 }
29b0f896
AM		 6785
6786 return 1;
6787}
6788
6789static int
e3bb37b5 6790process_operands (void)
29b0f896
AM		 6791{
6792 /* Default segment register this instruction will use for memory
6793 accesses. 0 means unknown. This is only for optimizing out
6794 unnecessary segment overrides. */
6795 const seg_entry *default_seg = 0;
6796
2426c15f 6797 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 6798 {
91d6fa6a
NC		 6799 unsigned int dupl = i.operands;
6800 unsigned int dest = dupl - 1;
9fcfb3d7
L		 6801 unsigned int j;
6802
c0f3af97 6803 /* The destination must be an xmm register. */
9c2799c2 6804 gas_assert (i.reg_operands
91d6fa6a 6805 && MAX_OPERANDS > dupl
7ab9ffdd 6806 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97 6807
1b54b8d7
JB		 6808 if (i.tm.operand_types[0].bitfield.acc
6809 && i.tm.operand_types[0].bitfield.xmmword)
e2ec9d29 6810 {
8cd7925b 6811 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 6812 {
6813 /* Keep xmm0 for instructions with VEX prefix and 3
6814 sources. */
1b54b8d7
JB		 6815 i.tm.operand_types[0].bitfield.acc = 0;
6816 i.tm.operand_types[0].bitfield.regsimd = 1;
c0f3af97
L		 6817 goto duplicate;
6818 }
e2ec9d29 6819 else
c0f3af97
L		 6820 {
6821 /* We remove the first xmm0 and keep the number of
6822 operands unchanged, which in fact duplicates the
6823 destination. */
6824 for (j = 1; j < i.operands; j++)
6825 {
6826 i.op[j - 1] = i.op[j];
6827 i.types[j - 1] = i.types[j];
6828 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
6829 }
6830 }
6831 }
6832 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 6833 {
91d6fa6a 6834 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 6835 && (i.tm.opcode_modifier.vexsources
6836 == VEX3SOURCES));
c0f3af97
L		 6837
6838 /* Add the implicit xmm0 for instructions with VEX prefix
6839 and 3 sources. */
6840 for (j = i.operands; j > 0; j--)
6841 {
6842 i.op[j] = i.op[j - 1];
6843 i.types[j] = i.types[j - 1];
6844 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
6845 }
6846 i.op[0].regs
6847 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 6848 i.types[0] = regxmm;
c0f3af97
L		 6849 i.tm.operand_types[0] = regxmm;
6850
6851 i.operands += 2;
6852 i.reg_operands += 2;
6853 i.tm.operands += 2;
6854
91d6fa6a 6855 dupl++;
c0f3af97 6856 dest++;
91d6fa6a
NC		 6857 i.op[dupl] = i.op[dest];
6858 i.types[dupl] = i.types[dest];
6859 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 6860 }
c0f3af97
L		 6861 else
6862 {
6863duplicate:
6864 i.operands++;
6865 i.reg_operands++;
6866 i.tm.operands++;
6867
91d6fa6a
NC		 6868 i.op[dupl] = i.op[dest];
6869 i.types[dupl] = i.types[dest];
6870 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 6871 }
6872
6873 if (i.tm.opcode_modifier.immext)
6874 process_immext ();
6875 }
1b54b8d7
JB		 6876 else if (i.tm.operand_types[0].bitfield.acc
6877 && i.tm.operand_types[0].bitfield.xmmword)
c0f3af97
L		 6878 {
6879 unsigned int j;
6880
9fcfb3d7
L		 6881 for (j = 1; j < i.operands; j++)
6882 {
6883 i.op[j - 1] = i.op[j];
6884 i.types[j - 1] = i.types[j];
6885
6886 /* We need to adjust fields in i.tm since they are used by
6887 build_modrm_byte. */
6888 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
6889 }
6890
e2ec9d29
L		 6891 i.operands--;
6892 i.reg_operands--;
e2ec9d29
L		 6893 i.tm.operands--;
6894 }
920d2ddc
IT		 6895 else if (i.tm.opcode_modifier.implicitquadgroup)
6896 {
a477a8c4
JB		 6897 unsigned int regnum, first_reg_in_group, last_reg_in_group;
6898
920d2ddc 6899 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
10c17abd 6900 gas_assert (i.operands >= 2 && i.types[1].bitfield.regsimd);
a477a8c4
JB		 6901 regnum = register_number (i.op[1].regs);
6902 first_reg_in_group = regnum & ~3;
6903 last_reg_in_group = first_reg_in_group + 3;
6904 if (regnum != first_reg_in_group)
6905 as_warn (_("source register `%s%s' implicitly denotes"
6906 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6907 register_prefix, i.op[1].regs->reg_name,
6908 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
6909 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
6910 i.tm.name);
6911 }
e2ec9d29
L		 6912 else if (i.tm.opcode_modifier.regkludge)
6913 {
6914 /* The imul $imm, %reg instruction is converted into
6915 imul $imm, %reg, %reg, and the clr %reg instruction
6916 is converted into xor %reg, %reg. */
6917
6918 unsigned int first_reg_op;
6919
6920 if (operand_type_check (i.types[0], reg))
6921 first_reg_op = 0;
6922 else
6923 first_reg_op = 1;
6924 /* Pretend we saw the extra register operand. */
9c2799c2 6925 gas_assert (i.reg_operands == 1
7ab9ffdd 6926 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 6927 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
6928 i.types[first_reg_op + 1] = i.types[first_reg_op];
6929 i.operands++;
6930 i.reg_operands++;
29b0f896
AM		 6931 }
6932
40fb9820 6933 if (i.tm.opcode_modifier.shortform)
29b0f896 6934 {
40fb9820
L		 6935 if (i.types[0].bitfield.sreg2
6936 || i.types[0].bitfield.sreg3)
29b0f896 6937 {
4eed87de
AM		 6938 if (i.tm.base_opcode == POP_SEG_SHORT
6939 && i.op[0].regs->reg_num == 1)
29b0f896 6940 {
a87af027 6941 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 6942 return 0;
29b0f896 6943 }
4eed87de
AM		 6944 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
6945 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 6946 i.rex |= REX_B;
4eed87de
AM		 6947 }
6948 else
6949 {
7ab9ffdd 6950 /* The register or float register operand is in operand
85f10a01 6951 0 or 1. */
40fb9820 6952 unsigned int op;
7ab9ffdd 6953
ca0d63fe 6954 if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte)
7ab9ffdd
L		 6955 || operand_type_check (i.types[0], reg))
6956 op = 0;
6957 else
6958 op = 1;
4eed87de
AM		 6959 /* Register goes in low 3 bits of opcode. */
6960 i.tm.base_opcode |= i.op[op].regs->reg_num;
6961 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 6962 i.rex |= REX_B;
40fb9820 6963 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 6964 {
4eed87de
AM		 6965 /* Warn about some common errors, but press on regardless.
6966 The first case can be generated by gcc (<= 2.8.1). */
6967 if (i.operands == 2)
6968 {
6969 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 6970 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 6971 register_prefix, i.op[!intel_syntax].regs->reg_name,
6972 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 6973 }
6974 else
6975 {
6976 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 6977 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6978 register_prefix, i.op[0].regs->reg_name);
4eed87de 6979 }
29b0f896
AM		 6980 }
6981 }
6982 }
40fb9820 6983 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 6984 {
6985 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 6986 must be put into the modrm byte). Now, we make the modrm and
6987 index base bytes based on all the info we've collected. */
29b0f896
AM		 6988
6989 default_seg = build_modrm_byte ();
6990 }
8a2ed489 6991 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 6992 {
6993 default_seg = &ds;
6994 }
40fb9820 6995 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 6996 {
6997 /* For the string instructions that allow a segment override
6998 on one of their operands, the default segment is ds. */
6999 default_seg = &ds;
7000 }
7001
75178d9d
L		 7002 if (i.tm.base_opcode == 0x8d /* lea */
7003 && i.seg[0]
7004 && !quiet_warnings)
30123838 7005 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 7006
7007 /* If a segment was explicitly specified, and the specified segment
7008 is not the default, use an opcode prefix to select it. If we
7009 never figured out what the default segment is, then default_seg
7010 will be zero at this point, and the specified segment prefix will
7011 always be used. */
29b0f896
AM		 7012 if ((i.seg[0]) && (i.seg[0] != default_seg))
7013 {
7014 if (!add_prefix (i.seg[0]->seg_prefix))
7015 return 0;
7016 }
7017 return 1;
7018}
7019
7020static const seg_entry *
e3bb37b5 7021build_modrm_byte (void)
29b0f896
AM		 7022{
7023 const seg_entry *default_seg = 0;
c0f3af97 7024 unsigned int source, dest;
8cd7925b 7025 int vex_3_sources;
c0f3af97 7026
8cd7925b 7027 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 7028 if (vex_3_sources)
7029 {
91d6fa6a 7030 unsigned int nds, reg_slot;
4c2c6516 7031 expressionS *exp;
c0f3af97 7032
6b8d3588 7033 dest = i.operands - 1;
c0f3af97 7034 nds = dest - 1;
922d8de8 7035
a683cc34 7036 /* There are 2 kinds of instructions:
bed3d976
JB		 7037 1. 5 operands: 4 register operands or 3 register operands
7038 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
7039 VexW0 or VexW1. The destination must be either XMM, YMM or
43234a1e 7040 ZMM register.
bed3d976 7041 2. 4 operands: 4 register operands or 3 register operands
2f1bada2 7042 plus 1 memory operand, with VexXDS. */
922d8de8 7043 gas_assert ((i.reg_operands == 4
bed3d976
JB		 7044 || (i.reg_operands == 3 && i.mem_operands == 1))
7045 && i.tm.opcode_modifier.vexvvvv == VEXXDS
dcd7e323
JB		 7046 && i.tm.opcode_modifier.vexw
7047 && i.tm.operand_types[dest].bitfield.regsimd);
a683cc34 7048
48db9223
JB		 7049 /* If VexW1 is set, the first non-immediate operand is the source and
7050 the second non-immediate one is encoded in the immediate operand. */
7051 if (i.tm.opcode_modifier.vexw == VEXW1)
7052 {
7053 source = i.imm_operands;
7054 reg_slot = i.imm_operands + 1;
7055 }
7056 else
7057 {
7058 source = i.imm_operands + 1;
7059 reg_slot = i.imm_operands;
7060 }
7061
a683cc34 7062 if (i.imm_operands == 0)
bed3d976
JB		 7063 {
7064 /* When there is no immediate operand, generate an 8bit
7065 immediate operand to encode the first operand. */
7066 exp = &im_expressions[i.imm_operands++];
7067 i.op[i.operands].imms = exp;
7068 i.types[i.operands] = imm8;
7069 i.operands++;
7070
7071 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
7072 exp->X_op = O_constant;
7073 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
43234a1e
L		 7074 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
7075 }
922d8de8 7076 else
bed3d976
JB		 7077 {
7078 unsigned int imm_slot;
a683cc34 7079
2f1bada2
JB		 7080 gas_assert (i.imm_operands == 1 && i.types[0].bitfield.vec_imm4);
7081
bed3d976
JB		 7082 if (i.tm.opcode_modifier.immext)
7083 {
7084 /* When ImmExt is set, the immediate byte is the last
7085 operand. */
7086 imm_slot = i.operands - 1;
7087 source--;
7088 reg_slot--;
7089 }
7090 else
7091 {
7092 imm_slot = 0;
7093
7094 /* Turn on Imm8 so that output_imm will generate it. */
7095 i.types[imm_slot].bitfield.imm8 = 1;
7096 }
7097
7098 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
7099 i.op[imm_slot].imms->X_add_number
7100 |= register_number (i.op[reg_slot].regs) << 4;
43234a1e 7101 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
bed3d976 7102 }
a683cc34 7103
10c17abd 7104 gas_assert (i.tm.operand_types[nds].bitfield.regsimd);
dae39acc 7105 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 7106 }
7107 else
7108 source = dest = 0;
29b0f896
AM		 7109
7110 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 7111 implicit registers do not count. If there are 3 register
7112 operands, it must be a instruction with VexNDS. For a
7113 instruction with VexNDD, the destination register is encoded
7114 in VEX prefix. If there are 4 register operands, it must be
7115 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 7116 if (i.mem_operands == 0
7117 && ((i.reg_operands == 2
2426c15f 7118 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 7119 || (i.reg_operands == 3
2426c15f 7120 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 7121 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 7122 {
cab737b9
L		 7123 switch (i.operands)
7124 {
7125 case 2:
7126 source = 0;
7127 break;
7128 case 3:
c81128dc
L		 7129 /* When there are 3 operands, one of them may be immediate,
7130 which may be the first or the last operand. Otherwise,
c0f3af97
L		 7131 the first operand must be shift count register (cl) or it
7132 is an instruction with VexNDS. */
9c2799c2 7133 gas_assert (i.imm_operands == 1
7ab9ffdd 7134 || (i.imm_operands == 0
2426c15f 7135 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 7136 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 7137 if (operand_type_check (i.types[0], imm)
7138 || i.types[0].bitfield.shiftcount)
7139 source = 1;
7140 else
7141 source = 0;
cab737b9
L		 7142 break;
7143 case 4:
368d64cc
L		 7144 /* When there are 4 operands, the first two must be 8bit
7145 immediate operands. The source operand will be the 3rd
c0f3af97
L		 7146 one.
7147
7148 For instructions with VexNDS, if the first operand
7149 an imm8, the source operand is the 2nd one. If the last
7150 operand is imm8, the source operand is the first one. */
9c2799c2 7151 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 7152 && i.types[0].bitfield.imm8
7153 && i.types[1].bitfield.imm8)
2426c15f 7154 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 7155 && i.imm_operands == 1
7156 && (i.types[0].bitfield.imm8
43234a1e
L		 7157 || i.types[i.operands - 1].bitfield.imm8
7158 || i.rounding)));
9f2670f2
L		 7159 if (i.imm_operands == 2)
7160 source = 2;
7161 else
c0f3af97
L		 7162 {
7163 if (i.types[0].bitfield.imm8)
7164 source = 1;
7165 else
7166 source = 0;
7167 }
c0f3af97
L		 7168 break;
7169 case 5:
e771e7c9 7170 if (is_evex_encoding (&i.tm))
43234a1e
L		 7171 {
7172 /* For EVEX instructions, when there are 5 operands, the
7173 first one must be immediate operand. If the second one
7174 is immediate operand, the source operand is the 3th
7175 one. If the last one is immediate operand, the source
7176 operand is the 2nd one. */
7177 gas_assert (i.imm_operands == 2
7178 && i.tm.opcode_modifier.sae
7179 && operand_type_check (i.types[0], imm));
7180 if (operand_type_check (i.types[1], imm))
7181 source = 2;
7182 else if (operand_type_check (i.types[4], imm))
7183 source = 1;
7184 else
7185 abort ();
7186 }
cab737b9
L		 7187 break;
7188 default:
7189 abort ();
7190 }
7191
c0f3af97
L		 7192 if (!vex_3_sources)
7193 {
7194 dest = source + 1;
7195
43234a1e
L		 7196 /* RC/SAE operand could be between DEST and SRC. That happens
7197 when one operand is GPR and the other one is XMM/YMM/ZMM
7198 register. */
7199 if (i.rounding && i.rounding->operand == (int) dest)
7200 dest++;
7201
2426c15f 7202 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97 7203 {
43234a1e 7204 /* For instructions with VexNDS, the register-only source
c5d0745b 7205 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
43234a1e
L		 7206 register. It is encoded in VEX prefix. We need to
7207 clear RegMem bit before calling operand_type_equal. */
f12dc422
L		 7208
7209 i386_operand_type op;
7210 unsigned int vvvv;
7211
7212 /* Check register-only source operand when two source
7213 operands are swapped. */
7214 if (!i.tm.operand_types[source].bitfield.baseindex
7215 && i.tm.operand_types[dest].bitfield.baseindex)
7216 {
7217 vvvv = source;
7218 source = dest;
7219 }
7220 else
7221 vvvv = dest;
7222
7223 op = i.tm.operand_types[vvvv];
fa99fab2 7224 op.bitfield.regmem = 0;
c0f3af97 7225 if ((dest + 1) >= i.operands
dc821c5f
JB		 7226 || ((!op.bitfield.reg
7227 || (!op.bitfield.dword && !op.bitfield.qword))
10c17abd 7228 && !op.bitfield.regsimd
43234a1e 7229 && !operand_type_equal (&op, &regmask)))
c0f3af97 7230 abort ();
f12dc422 7231 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 7232 dest++;
7233 }
7234 }
29b0f896
AM		 7235
7236 i.rm.mode = 3;
7237 /* One of the register operands will be encoded in the i.tm.reg
7238 field, the other in the combined i.tm.mode and i.tm.regmem
7239 fields. If no form of this instruction supports a memory
7240 destination operand, then we assume the source operand may
7241 sometimes be a memory operand and so we need to store the
7242 destination in the i.rm.reg field. */
40fb9820
L		 7243 if (!i.tm.operand_types[dest].bitfield.regmem
7244 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 7245 {
7246 i.rm.reg = i.op[dest].regs->reg_num;
7247 i.rm.regmem = i.op[source].regs->reg_num;
b4a3a7b4
L		 7248 if (i.op[dest].regs->reg_type.bitfield.regmmx
7249 || i.op[source].regs->reg_type.bitfield.regmmx)
7250 i.has_regmmx = TRUE;
7251 else if (i.op[dest].regs->reg_type.bitfield.regsimd
7252 || i.op[source].regs->reg_type.bitfield.regsimd)
7253 {
7254 if (i.types[dest].bitfield.zmmword
7255 || i.types[source].bitfield.zmmword)
7256 i.has_regzmm = TRUE;
7257 else if (i.types[dest].bitfield.ymmword
7258 || i.types[source].bitfield.ymmword)
7259 i.has_regymm = TRUE;
7260 else
7261 i.has_regxmm = TRUE;
7262 }
29b0f896 7263 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 7264 i.rex |= REX_R;
43234a1e
L		 7265 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
7266 i.vrex |= REX_R;
29b0f896 7267 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 7268 i.rex |= REX_B;
43234a1e
L		 7269 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
7270 i.vrex |= REX_B;
29b0f896
AM		 7271 }
7272 else
7273 {
7274 i.rm.reg = i.op[source].regs->reg_num;
7275 i.rm.regmem = i.op[dest].regs->reg_num;
7276 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 7277 i.rex |= REX_B;
43234a1e
L		 7278 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
7279 i.vrex |= REX_B;
29b0f896 7280 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 7281 i.rex |= REX_R;
43234a1e
L		 7282 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
7283 i.vrex |= REX_R;
29b0f896 7284 }
e0c7f900 7285 if (flag_code != CODE_64BIT && (i.rex & REX_R))
c4a530c5 7286 {
e0c7f900 7287 if (!i.types[i.tm.operand_types[0].bitfield.regmem].bitfield.control)
c4a530c5 7288 abort ();
e0c7f900 7289 i.rex &= ~REX_R;
c4a530c5
JB		 7290 add_prefix (LOCK_PREFIX_OPCODE);
7291 }
29b0f896
AM		 7292 }
7293 else
7294 { /* If it's not 2 reg operands... */
c0f3af97
L		 7295 unsigned int mem;
7296
29b0f896
AM		 7297 if (i.mem_operands)
7298 {
7299 unsigned int fake_zero_displacement = 0;
99018f42 7300 unsigned int op;
4eed87de 7301
7ab9ffdd
L		 7302 for (op = 0; op < i.operands; op++)
7303 if (operand_type_check (i.types[op], anymem))
7304 break;
7ab9ffdd 7305 gas_assert (op < i.operands);
29b0f896 7306
6c30d220
L		 7307 if (i.tm.opcode_modifier.vecsib)
7308 {
e968fc9b 7309 if (i.index_reg->reg_num == RegIZ)
6c30d220
L		 7310 abort ();
7311
7312 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7313 if (!i.base_reg)
7314 {
7315 i.sib.base = NO_BASE_REGISTER;
7316 i.sib.scale = i.log2_scale_factor;
7317 i.types[op].bitfield.disp8 = 0;
7318 i.types[op].bitfield.disp16 = 0;
7319 i.types[op].bitfield.disp64 = 0;
43083a50 7320 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
6c30d220
L		 7321 {
7322 /* Must be 32 bit */
7323 i.types[op].bitfield.disp32 = 1;
7324 i.types[op].bitfield.disp32s = 0;
7325 }
7326 else
7327 {
7328 i.types[op].bitfield.disp32 = 0;
7329 i.types[op].bitfield.disp32s = 1;
7330 }
7331 }
7332 i.sib.index = i.index_reg->reg_num;
7333 if ((i.index_reg->reg_flags & RegRex) != 0)
7334 i.rex |= REX_X;
43234a1e
L		 7335 if ((i.index_reg->reg_flags & RegVRex) != 0)
7336 i.vrex |= REX_X;
6c30d220
L		 7337 }
7338
29b0f896
AM		 7339 default_seg = &ds;
7340
7341 if (i.base_reg == 0)
7342 {
7343 i.rm.mode = 0;
7344 if (!i.disp_operands)
9bb129e8 7345 fake_zero_displacement = 1;
29b0f896
AM		 7346 if (i.index_reg == 0)
7347 {
73053c1f
JB		 7348 i386_operand_type newdisp;
7349
6c30d220 7350 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 7351 /* Operand is just <disp> */
20f0a1fc 7352 if (flag_code == CODE_64BIT)
29b0f896
AM		 7353 {
7354 /* 64bit mode overwrites the 32bit absolute
7355 addressing by RIP relative addressing and
7356 absolute addressing is encoded by one of the
7357 redundant SIB forms. */
7358 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7359 i.sib.base = NO_BASE_REGISTER;
7360 i.sib.index = NO_INDEX_REGISTER;
73053c1f 7361 newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32);
20f0a1fc 7362 }
fc225355
L		 7363 else if ((flag_code == CODE_16BIT)
7364 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 7365 {
7366 i.rm.regmem = NO_BASE_REGISTER_16;
73053c1f 7367 newdisp = disp16;
20f0a1fc
NC		 7368 }
7369 else
7370 {
7371 i.rm.regmem = NO_BASE_REGISTER;
73053c1f 7372 newdisp = disp32;
29b0f896 7373 }
73053c1f
JB		 7374 i.types[op] = operand_type_and_not (i.types[op], anydisp);
7375 i.types[op] = operand_type_or (i.types[op], newdisp);
29b0f896 7376 }
6c30d220 7377 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 7378 {
6c30d220 7379 /* !i.base_reg && i.index_reg */
e968fc9b 7380 if (i.index_reg->reg_num == RegIZ)
db51cc60
L		 7381 i.sib.index = NO_INDEX_REGISTER;
7382 else
7383 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 7384 i.sib.base = NO_BASE_REGISTER;
7385 i.sib.scale = i.log2_scale_factor;
7386 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 7387 i.types[op].bitfield.disp8 = 0;
7388 i.types[op].bitfield.disp16 = 0;
7389 i.types[op].bitfield.disp64 = 0;
43083a50 7390 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
40fb9820
L		 7391 {
7392 /* Must be 32 bit */
7393 i.types[op].bitfield.disp32 = 1;
7394 i.types[op].bitfield.disp32s = 0;
7395 }
29b0f896 7396 else
40fb9820
L		 7397 {
7398 i.types[op].bitfield.disp32 = 0;
7399 i.types[op].bitfield.disp32s = 1;
7400 }
29b0f896 7401 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 7402 i.rex |= REX_X;
29b0f896
AM		 7403 }
7404 }
7405 /* RIP addressing for 64bit mode. */
e968fc9b 7406 else if (i.base_reg->reg_num == RegIP)
29b0f896 7407 {
6c30d220 7408 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 7409 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 7410 i.types[op].bitfield.disp8 = 0;
7411 i.types[op].bitfield.disp16 = 0;
7412 i.types[op].bitfield.disp32 = 0;
7413 i.types[op].bitfield.disp32s = 1;
7414 i.types[op].bitfield.disp64 = 0;
71903a11 7415 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 7416 if (! i.disp_operands)
7417 fake_zero_displacement = 1;
29b0f896 7418 }
dc821c5f 7419 else if (i.base_reg->reg_type.bitfield.word)
29b0f896 7420 {
6c30d220 7421 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 7422 switch (i.base_reg->reg_num)
7423 {
7424 case 3: /* (%bx) */
7425 if (i.index_reg == 0)
7426 i.rm.regmem = 7;
7427 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7428 i.rm.regmem = i.index_reg->reg_num - 6;
7429 break;
7430 case 5: /* (%bp) */
7431 default_seg = &ss;
7432 if (i.index_reg == 0)
7433 {
7434 i.rm.regmem = 6;
40fb9820 7435 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 7436 {
7437 /* fake (%bp) into 0(%bp) */
b5014f7a 7438 i.types[op].bitfield.disp8 = 1;
252b5132 7439 fake_zero_displacement = 1;
29b0f896
AM		 7440 }
7441 }
7442 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7443 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
7444 break;
7445 default: /* (%si) -> 4 or (%di) -> 5 */
7446 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
7447 }
7448 i.rm.mode = mode_from_disp_size (i.types[op]);
7449 }
7450 else /* i.base_reg and 32/64 bit mode */
7451 {
7452 if (flag_code == CODE_64BIT
40fb9820
L		 7453 && operand_type_check (i.types[op], disp))
7454 {
73053c1f
JB		 7455 i.types[op].bitfield.disp16 = 0;
7456 i.types[op].bitfield.disp64 = 0;
40fb9820 7457 if (i.prefix[ADDR_PREFIX] == 0)
73053c1f
JB		 7458 {
7459 i.types[op].bitfield.disp32 = 0;
7460 i.types[op].bitfield.disp32s = 1;
7461 }
40fb9820 7462 else
73053c1f
JB		 7463 {
7464 i.types[op].bitfield.disp32 = 1;
7465 i.types[op].bitfield.disp32s = 0;
7466 }
40fb9820 7467 }
20f0a1fc 7468
6c30d220
L		 7469 if (!i.tm.opcode_modifier.vecsib)
7470 i.rm.regmem = i.base_reg->reg_num;
29b0f896 7471 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 7472 i.rex |= REX_B;
29b0f896
AM		 7473 i.sib.base = i.base_reg->reg_num;
7474 /* x86-64 ignores REX prefix bit here to avoid decoder
7475 complications. */
848930b2
JB		 7476 if (!(i.base_reg->reg_flags & RegRex)
7477 && (i.base_reg->reg_num == EBP_REG_NUM
7478 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 7479 default_seg = &ss;
848930b2 7480 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 7481 {
848930b2 7482 fake_zero_displacement = 1;
b5014f7a 7483 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 7484 }
7485 i.sib.scale = i.log2_scale_factor;
7486 if (i.index_reg == 0)
7487 {
6c30d220 7488 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 7489 /* <disp>(%esp) becomes two byte modrm with no index
7490 register. We've already stored the code for esp
7491 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7492 Any base register besides %esp will not use the
7493 extra modrm byte. */
7494 i.sib.index = NO_INDEX_REGISTER;
29b0f896 7495 }
6c30d220 7496 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 7497 {
e968fc9b 7498 if (i.index_reg->reg_num == RegIZ)
db51cc60
L		 7499 i.sib.index = NO_INDEX_REGISTER;
7500 else
7501 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 7502 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7503 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 7504 i.rex |= REX_X;
29b0f896 7505 }
67a4f2b7
AO		 7506
7507 if (i.disp_operands
7508 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
7509 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
7510 i.rm.mode = 0;
7511 else
a501d77e
L		 7512 {
7513 if (!fake_zero_displacement
7514 && !i.disp_operands
7515 && i.disp_encoding)
7516 {
7517 fake_zero_displacement = 1;
7518 if (i.disp_encoding == disp_encoding_8bit)
7519 i.types[op].bitfield.disp8 = 1;
7520 else
7521 i.types[op].bitfield.disp32 = 1;
7522 }
7523 i.rm.mode = mode_from_disp_size (i.types[op]);
7524 }
29b0f896 7525 }
252b5132 7526
29b0f896
AM		 7527 if (fake_zero_displacement)
7528 {
7529 /* Fakes a zero displacement assuming that i.types[op]
7530 holds the correct displacement size. */
7531 expressionS *exp;
7532
9c2799c2 7533 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 7534 exp = &disp_expressions[i.disp_operands++];
7535 i.op[op].disps = exp;
7536 exp->X_op = O_constant;
7537 exp->X_add_number = 0;
7538 exp->X_add_symbol = (symbolS *) 0;
7539 exp->X_op_symbol = (symbolS *) 0;
7540 }
c0f3af97
L		 7541
7542 mem = op;
29b0f896 7543 }
c0f3af97
L		 7544 else
7545 mem = ~0;
252b5132 7546
8c43a48b 7547 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 7548 {
7549 if (operand_type_check (i.types[0], imm))
7550 i.vex.register_specifier = NULL;
7551 else
7552 {
7553 /* VEX.vvvv encodes one of the sources when the first
7554 operand is not an immediate. */
1ef99a7b 7555 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 7556 i.vex.register_specifier = i.op[0].regs;
7557 else
7558 i.vex.register_specifier = i.op[1].regs;
7559 }
7560
7561 /* Destination is a XMM register encoded in the ModRM.reg
7562 and VEX.R bit. */
7563 i.rm.reg = i.op[2].regs->reg_num;
7564 if ((i.op[2].regs->reg_flags & RegRex) != 0)
7565 i.rex |= REX_R;
7566
7567 /* ModRM.rm and VEX.B encodes the other source. */
7568 if (!i.mem_operands)
7569 {
7570 i.rm.mode = 3;
7571
1ef99a7b 7572 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 7573 i.rm.regmem = i.op[1].regs->reg_num;
7574 else
7575 i.rm.regmem = i.op[0].regs->reg_num;
7576
7577 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7578 i.rex |= REX_B;
7579 }
7580 }
2426c15f 7581 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 7582 {
7583 i.vex.register_specifier = i.op[2].regs;
7584 if (!i.mem_operands)
7585 {
7586 i.rm.mode = 3;
7587 i.rm.regmem = i.op[1].regs->reg_num;
7588 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7589 i.rex |= REX_B;
7590 }
7591 }
29b0f896
AM		 7592 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7593 (if any) based on i.tm.extension_opcode. Again, we must be
7594 careful to make sure that segment/control/debug/test/MMX
7595 registers are coded into the i.rm.reg field. */
f88c9eb0 7596 else if (i.reg_operands)
29b0f896 7597 {
99018f42 7598 unsigned int op;
7ab9ffdd
L		 7599 unsigned int vex_reg = ~0;
7600
7601 for (op = 0; op < i.operands; op++)
b4a3a7b4
L		 7602 {
7603 if (i.types[op].bitfield.reg
7604 || i.types[op].bitfield.regbnd
7605 || i.types[op].bitfield.regmask
7606 || i.types[op].bitfield.sreg2
7607 || i.types[op].bitfield.sreg3
7608 || i.types[op].bitfield.control
7609 || i.types[op].bitfield.debug
7610 || i.types[op].bitfield.test)
7611 break;
7612 if (i.types[op].bitfield.regsimd)
7613 {
7614 if (i.types[op].bitfield.zmmword)
7615 i.has_regzmm = TRUE;
7616 else if (i.types[op].bitfield.ymmword)
7617 i.has_regymm = TRUE;
7618 else
7619 i.has_regxmm = TRUE;
7620 break;
7621 }
7622 if (i.types[op].bitfield.regmmx)
7623 {
7624 i.has_regmmx = TRUE;
7625 break;
7626 }
7627 }
c0209578 7628
7ab9ffdd
L		 7629 if (vex_3_sources)
7630 op = dest;
2426c15f 7631 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 7632 {
7633 /* For instructions with VexNDS, the register-only
7634 source operand is encoded in VEX prefix. */
7635 gas_assert (mem != (unsigned int) ~0);
c0f3af97 7636
7ab9ffdd 7637 if (op > mem)
c0f3af97 7638 {
7ab9ffdd
L		 7639 vex_reg = op++;
7640 gas_assert (op < i.operands);
c0f3af97
L		 7641 }
7642 else
c0f3af97 7643 {
f12dc422
L		 7644 /* Check register-only source operand when two source
7645 operands are swapped. */
7646 if (!i.tm.operand_types[op].bitfield.baseindex
7647 && i.tm.operand_types[op + 1].bitfield.baseindex)
7648 {
7649 vex_reg = op;
7650 op += 2;
7651 gas_assert (mem == (vex_reg + 1)
7652 && op < i.operands);
7653 }
7654 else
7655 {
7656 vex_reg = op + 1;
7657 gas_assert (vex_reg < i.operands);
7658 }
c0f3af97 7659 }
7ab9ffdd 7660 }
2426c15f 7661 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 7662 {
f12dc422 7663 /* For instructions with VexNDD, the register destination
7ab9ffdd 7664 is encoded in VEX prefix. */
f12dc422
L		 7665 if (i.mem_operands == 0)
7666 {
7667 /* There is no memory operand. */
7668 gas_assert ((op + 2) == i.operands);
7669 vex_reg = op + 1;
7670 }
7671 else
8d63c93e 7672 {
ed438a93
JB		 7673 /* There are only 2 non-immediate operands. */
7674 gas_assert (op < i.imm_operands + 2
7675 && i.operands == i.imm_operands + 2);
7676 vex_reg = i.imm_operands + 1;
f12dc422 7677 }
7ab9ffdd
L		 7678 }
7679 else
7680 gas_assert (op < i.operands);
99018f42 7681
7ab9ffdd
L		 7682 if (vex_reg != (unsigned int) ~0)
7683 {
f12dc422 7684 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 7685
dc821c5f
JB		 7686 if ((!type->bitfield.reg
7687 || (!type->bitfield.dword && !type->bitfield.qword))
10c17abd 7688 && !type->bitfield.regsimd
43234a1e 7689 && !operand_type_equal (type, &regmask))
7ab9ffdd 7690 abort ();
f88c9eb0 7691
7ab9ffdd
L		 7692 i.vex.register_specifier = i.op[vex_reg].regs;
7693 }
7694
1b9f0c97
L		 7695 /* Don't set OP operand twice. */
7696 if (vex_reg != op)
7ab9ffdd 7697 {
1b9f0c97
L		 7698 /* If there is an extension opcode to put here, the
7699 register number must be put into the regmem field. */
7700 if (i.tm.extension_opcode != None)
7701 {
7702 i.rm.regmem = i.op[op].regs->reg_num;
7703 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7704 i.rex |= REX_B;
43234a1e
L		 7705 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7706 i.vrex |= REX_B;
1b9f0c97
L		 7707 }
7708 else
7709 {
7710 i.rm.reg = i.op[op].regs->reg_num;
7711 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7712 i.rex |= REX_R;
43234a1e
L		 7713 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7714 i.vrex |= REX_R;
1b9f0c97 7715 }
7ab9ffdd 7716 }
252b5132 7717
29b0f896
AM		 7718 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7719 must set it to 3 to indicate this is a register operand
7720 in the regmem field. */
7721 if (!i.mem_operands)
7722 i.rm.mode = 3;
7723 }
252b5132 7724
29b0f896 7725 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 7726 if (i.tm.extension_opcode != None)
29b0f896
AM		 7727 i.rm.reg = i.tm.extension_opcode;
7728 }
7729 return default_seg;
7730}
252b5132 7731
29b0f896 7732static void
e3bb37b5 7733output_branch (void)
29b0f896
AM		 7734{
7735 char *p;
f8a5c266 7736 int size;
29b0f896
AM		 7737 int code16;
7738 int prefix;
7739 relax_substateT subtype;
7740 symbolS *sym;
7741 offsetT off;
7742
f8a5c266 7743 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 7744 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 7745
7746 prefix = 0;
7747 if (i.prefix[DATA_PREFIX] != 0)
252b5132 7748 {
29b0f896
AM		 7749 prefix = 1;
7750 i.prefixes -= 1;
7751 code16 ^= CODE16;
252b5132 7752 }
29b0f896
AM		 7753 /* Pentium4 branch hints. */
7754 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7755 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 7756 {
29b0f896
AM		 7757 prefix++;
7758 i.prefixes--;
7759 }
7760 if (i.prefix[REX_PREFIX] != 0)
7761 {
7762 prefix++;
7763 i.prefixes--;
2f66722d
AM		 7764 }
7765
7e8b059b
L		 7766 /* BND prefixed jump. */
7767 if (i.prefix[BND_PREFIX] != 0)
7768 {
7769 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7770 i.prefixes -= 1;
7771 }
7772
29b0f896
AM		 7773 if (i.prefixes != 0 && !intel_syntax)
7774 as_warn (_("skipping prefixes on this instruction"));
7775
7776 /* It's always a symbol; End frag & setup for relax.
7777 Make sure there is enough room in this frag for the largest
7778 instruction we may generate in md_convert_frag. This is 2
7779 bytes for the opcode and room for the prefix and largest
7780 displacement. */
7781 frag_grow (prefix + 2 + 4);
7782 /* Prefix and 1 opcode byte go in fr_fix. */
7783 p = frag_more (prefix + 1);
7784 if (i.prefix[DATA_PREFIX] != 0)
7785 *p++ = DATA_PREFIX_OPCODE;
7786 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
7787 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
7788 *p++ = i.prefix[SEG_PREFIX];
7789 if (i.prefix[REX_PREFIX] != 0)
7790 *p++ = i.prefix[REX_PREFIX];
7791 *p = i.tm.base_opcode;
7792
7793 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 7794 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 7795 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 7796 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 7797 else
f8a5c266 7798 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 7799 subtype |= code16;
3e73aa7c 7800
29b0f896
AM		 7801 sym = i.op[0].disps->X_add_symbol;
7802 off = i.op[0].disps->X_add_number;
3e73aa7c 7803
29b0f896
AM		 7804 if (i.op[0].disps->X_op != O_constant
7805 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 7806 {
29b0f896
AM		 7807 /* Handle complex expressions. */
7808 sym = make_expr_symbol (i.op[0].disps);
7809 off = 0;
7810 }
3e73aa7c 7811
29b0f896
AM		 7812 /* 1 possible extra opcode + 4 byte displacement go in var part.
7813 Pass reloc in fr_var. */
d258b828 7814 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
29b0f896 7815}
3e73aa7c 7816
bd7ab16b
L		 7817#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7818/* Return TRUE iff PLT32 relocation should be used for branching to
7819 symbol S. */
7820
7821static bfd_boolean
7822need_plt32_p (symbolS *s)
7823{
7824 /* PLT32 relocation is ELF only. */
7825 if (!IS_ELF)
7826 return FALSE;
7827
a5def729
RO		 7828#ifdef TE_SOLARIS
7829 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
7830 krtld support it. */
7831 return FALSE;
7832#endif
7833
bd7ab16b
L		 7834 /* Since there is no need to prepare for PLT branch on x86-64, we
7835 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7836 be used as a marker for 32-bit PC-relative branches. */
7837 if (!object_64bit)
7838 return FALSE;
7839
7840 /* Weak or undefined symbol need PLT32 relocation. */
7841 if (S_IS_WEAK (s) || !S_IS_DEFINED (s))
7842 return TRUE;
7843
7844 /* Non-global symbol doesn't need PLT32 relocation. */
7845 if (! S_IS_EXTERNAL (s))
7846 return FALSE;
7847
7848 /* Other global symbols need PLT32 relocation. NB: Symbol with
7849 non-default visibilities are treated as normal global symbol
7850 so that PLT32 relocation can be used as a marker for 32-bit
7851 PC-relative branches. It is useful for linker relaxation. */
7852 return TRUE;
7853}
7854#endif
7855
29b0f896 7856static void
e3bb37b5 7857output_jump (void)
29b0f896
AM		 7858{
7859 char *p;
7860 int size;
3e02c1cc 7861 fixS *fixP;
bd7ab16b 7862 bfd_reloc_code_real_type jump_reloc = i.reloc[0];
29b0f896 7863
40fb9820 7864 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 7865 {
7866 /* This is a loop or jecxz type instruction. */
7867 size = 1;
7868 if (i.prefix[ADDR_PREFIX] != 0)
7869 {
7870 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
7871 i.prefixes -= 1;
7872 }
7873 /* Pentium4 branch hints. */
7874 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7875 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7876 {
7877 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
7878 i.prefixes--;
3e73aa7c
JH		 7879 }
7880 }
29b0f896
AM		 7881 else
7882 {
7883 int code16;
3e73aa7c 7884
29b0f896
AM		 7885 code16 = 0;
7886 if (flag_code == CODE_16BIT)
7887 code16 = CODE16;
3e73aa7c 7888
29b0f896
AM		 7889 if (i.prefix[DATA_PREFIX] != 0)
7890 {
7891 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
7892 i.prefixes -= 1;
7893 code16 ^= CODE16;
7894 }
252b5132 7895
29b0f896
AM		 7896 size = 4;
7897 if (code16)
7898 size = 2;
7899 }
9fcc94b6 7900
29b0f896
AM		 7901 if (i.prefix[REX_PREFIX] != 0)
7902 {
7903 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
7904 i.prefixes -= 1;
7905 }
252b5132 7906
7e8b059b
L		 7907 /* BND prefixed jump. */
7908 if (i.prefix[BND_PREFIX] != 0)
7909 {
7910 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7911 i.prefixes -= 1;
7912 }
7913
29b0f896
AM		 7914 if (i.prefixes != 0 && !intel_syntax)
7915 as_warn (_("skipping prefixes on this instruction"));
e0890092 7916
42164a71
L		 7917 p = frag_more (i.tm.opcode_length + size);
7918 switch (i.tm.opcode_length)
7919 {
7920 case 2:
7921 *p++ = i.tm.base_opcode >> 8;
1a0670f3 7922 /* Fall through. */
42164a71
L		 7923 case 1:
7924 *p++ = i.tm.base_opcode;
7925 break;
7926 default:
7927 abort ();
7928 }
e0890092 7929
bd7ab16b
L		 7930#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7931 if (size == 4
7932 && jump_reloc == NO_RELOC
7933 && need_plt32_p (i.op[0].disps->X_add_symbol))
7934 jump_reloc = BFD_RELOC_X86_64_PLT32;
7935#endif
7936
7937 jump_reloc = reloc (size, 1, 1, jump_reloc);
7938
3e02c1cc 7939 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
bd7ab16b 7940 i.op[0].disps, 1, jump_reloc);
3e02c1cc
AM		 7941
7942 /* All jumps handled here are signed, but don't use a signed limit
7943 check for 32 and 16 bit jumps as we want to allow wrap around at
7944 4G and 64k respectively. */
7945 if (size == 1)
7946 fixP->fx_signed = 1;
29b0f896 7947}
e0890092 7948
29b0f896 7949static void
e3bb37b5 7950output_interseg_jump (void)
29b0f896
AM		 7951{
7952 char *p;
7953 int size;
7954 int prefix;
7955 int code16;
252b5132 7956
29b0f896
AM		 7957 code16 = 0;
7958 if (flag_code == CODE_16BIT)
7959 code16 = CODE16;
a217f122 7960
29b0f896
AM		 7961 prefix = 0;
7962 if (i.prefix[DATA_PREFIX] != 0)
7963 {
7964 prefix = 1;
7965 i.prefixes -= 1;
7966 code16 ^= CODE16;
7967 }
7968 if (i.prefix[REX_PREFIX] != 0)
7969 {
7970 prefix++;
7971 i.prefixes -= 1;
7972 }
252b5132 7973
29b0f896
AM		 7974 size = 4;
7975 if (code16)
7976 size = 2;
252b5132 7977
29b0f896
AM		 7978 if (i.prefixes != 0 && !intel_syntax)
7979 as_warn (_("skipping prefixes on this instruction"));
252b5132 7980
29b0f896
AM		 7981 /* 1 opcode; 2 segment; offset */
7982 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 7983
29b0f896
AM		 7984 if (i.prefix[DATA_PREFIX] != 0)
7985 *p++ = DATA_PREFIX_OPCODE;
252b5132 7986
29b0f896
AM		 7987 if (i.prefix[REX_PREFIX] != 0)
7988 *p++ = i.prefix[REX_PREFIX];
252b5132 7989
29b0f896
AM		 7990 *p++ = i.tm.base_opcode;
7991 if (i.op[1].imms->X_op == O_constant)
7992 {
7993 offsetT n = i.op[1].imms->X_add_number;
252b5132 7994
29b0f896
AM		 7995 if (size == 2
7996 && !fits_in_unsigned_word (n)
7997 && !fits_in_signed_word (n))
7998 {
7999 as_bad (_("16-bit jump out of range"));
8000 return;
8001 }
8002 md_number_to_chars (p, n, size);
8003 }
8004 else
8005 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 8006 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
29b0f896
AM		 8007 if (i.op[0].imms->X_op != O_constant)
8008 as_bad (_("can't handle non absolute segment in `%s'"),
8009 i.tm.name);
8010 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
8011}
a217f122 8012
b4a3a7b4
L		 8013#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8014void
8015x86_cleanup (void)
8016{
8017 char *p;
8018 asection *seg = now_seg;
8019 subsegT subseg = now_subseg;
8020 asection *sec;
8021 unsigned int alignment, align_size_1;
8022 unsigned int isa_1_descsz, feature_2_descsz, descsz;
8023 unsigned int isa_1_descsz_raw, feature_2_descsz_raw;
8024 unsigned int padding;
8025
8026 if (!IS_ELF || !x86_used_note)
8027 return;
8028
b4a3a7b4
L		 8029 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X86;
8030
8031 /* The .note.gnu.property section layout:
8032
8033 Field Length Contents
8034 ---- ---- ----
8035 n_namsz 4 4
8036 n_descsz 4 The note descriptor size
8037 n_type 4 NT_GNU_PROPERTY_TYPE_0
8038 n_name 4 "GNU"
8039 n_desc n_descsz The program property array
8040 .... .... ....
8041 */
8042
8043 /* Create the .note.gnu.property section. */
8044 sec = subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME, 0);
8045 bfd_set_section_flags (stdoutput, sec,
8046 (SEC_ALLOC
8047 | SEC_LOAD
8048 | SEC_DATA
8049 | SEC_HAS_CONTENTS
8050 | SEC_READONLY));
8051
8052 if (get_elf_backend_data (stdoutput)->s->elfclass == ELFCLASS64)
8053 {
8054 align_size_1 = 7;
8055 alignment = 3;
8056 }
8057 else
8058 {
8059 align_size_1 = 3;
8060 alignment = 2;
8061 }
8062
8063 bfd_set_section_alignment (stdoutput, sec, alignment);
8064 elf_section_type (sec) = SHT_NOTE;
8065
8066 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
8067 + 4-byte data */
8068 isa_1_descsz_raw = 4 + 4 + 4;
8069 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
8070 isa_1_descsz = (isa_1_descsz_raw + align_size_1) & ~align_size_1;
8071
8072 feature_2_descsz_raw = isa_1_descsz;
8073 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
8074 + 4-byte data */
8075 feature_2_descsz_raw += 4 + 4 + 4;
8076 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
8077 feature_2_descsz = ((feature_2_descsz_raw + align_size_1)
8078 & ~align_size_1);
8079
8080 descsz = feature_2_descsz;
8081 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
8082 p = frag_more (4 + 4 + 4 + 4 + descsz);
8083
8084 /* Write n_namsz. */
8085 md_number_to_chars (p, (valueT) 4, 4);
8086
8087 /* Write n_descsz. */
8088 md_number_to_chars (p + 4, (valueT) descsz, 4);
8089
8090 /* Write n_type. */
8091 md_number_to_chars (p + 4 * 2, (valueT) NT_GNU_PROPERTY_TYPE_0, 4);
8092
8093 /* Write n_name. */
8094 memcpy (p + 4 * 3, "GNU", 4);
8095
8096 /* Write 4-byte type. */
8097 md_number_to_chars (p + 4 * 4,
8098 (valueT) GNU_PROPERTY_X86_ISA_1_USED, 4);
8099
8100 /* Write 4-byte data size. */
8101 md_number_to_chars (p + 4 * 5, (valueT) 4, 4);
8102
8103 /* Write 4-byte data. */
8104 md_number_to_chars (p + 4 * 6, (valueT) x86_isa_1_used, 4);
8105
8106 /* Zero out paddings. */
8107 padding = isa_1_descsz - isa_1_descsz_raw;
8108 if (padding)
8109 memset (p + 4 * 7, 0, padding);
8110
8111 /* Write 4-byte type. */
8112 md_number_to_chars (p + isa_1_descsz + 4 * 4,
8113 (valueT) GNU_PROPERTY_X86_FEATURE_2_USED, 4);
8114
8115 /* Write 4-byte data size. */
8116 md_number_to_chars (p + isa_1_descsz + 4 * 5, (valueT) 4, 4);
8117
8118 /* Write 4-byte data. */
8119 md_number_to_chars (p + isa_1_descsz + 4 * 6,
8120 (valueT) x86_feature_2_used, 4);
8121
8122 /* Zero out paddings. */
8123 padding = feature_2_descsz - feature_2_descsz_raw;
8124 if (padding)
8125 memset (p + isa_1_descsz + 4 * 7, 0, padding);
8126
8127 /* We probably can't restore the current segment, for there likely
8128 isn't one yet... */
8129 if (seg && subseg)
8130 subseg_set (seg, subseg);
8131}
8132#endif
8133
9c33702b
JB		 8134static unsigned int
8135encoding_length (const fragS *start_frag, offsetT start_off,
8136 const char *frag_now_ptr)
8137{
8138 unsigned int len = 0;
8139
8140 if (start_frag != frag_now)
8141 {
8142 const fragS *fr = start_frag;
8143
8144 do {
8145 len += fr->fr_fix;
8146 fr = fr->fr_next;
8147 } while (fr && fr != frag_now);
8148 }
8149
8150 return len - start_off + (frag_now_ptr - frag_now->fr_literal);
8151}
8152
29b0f896 8153static void
e3bb37b5 8154output_insn (void)
29b0f896 8155{
2bbd9c25
JJ		 8156 fragS *insn_start_frag;
8157 offsetT insn_start_off;
8158
b4a3a7b4
L		 8159#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8160 if (IS_ELF && x86_used_note)
8161 {
8162 if (i.tm.cpu_flags.bitfield.cpucmov)
8163 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_CMOV;
8164 if (i.tm.cpu_flags.bitfield.cpusse)
8165 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE;
8166 if (i.tm.cpu_flags.bitfield.cpusse2)
8167 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE2;
8168 if (i.tm.cpu_flags.bitfield.cpusse3)
8169 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE3;
8170 if (i.tm.cpu_flags.bitfield.cpussse3)
8171 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSSE3;
8172 if (i.tm.cpu_flags.bitfield.cpusse4_1)
8173 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE4_1;
8174 if (i.tm.cpu_flags.bitfield.cpusse4_2)
8175 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE4_2;
8176 if (i.tm.cpu_flags.bitfield.cpuavx)
8177 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX;
8178 if (i.tm.cpu_flags.bitfield.cpuavx2)
8179 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX2;
8180 if (i.tm.cpu_flags.bitfield.cpufma)
8181 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_FMA;
8182 if (i.tm.cpu_flags.bitfield.cpuavx512f)
8183 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512F;
8184 if (i.tm.cpu_flags.bitfield.cpuavx512cd)
8185 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512CD;
8186 if (i.tm.cpu_flags.bitfield.cpuavx512er)
8187 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512ER;
8188 if (i.tm.cpu_flags.bitfield.cpuavx512pf)
8189 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512PF;
8190 if (i.tm.cpu_flags.bitfield.cpuavx512vl)
8191 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512VL;
8192 if (i.tm.cpu_flags.bitfield.cpuavx512dq)
8193 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512DQ;
8194 if (i.tm.cpu_flags.bitfield.cpuavx512bw)
8195 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512BW;
8196 if (i.tm.cpu_flags.bitfield.cpuavx512_4fmaps)
8197 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS;
8198 if (i.tm.cpu_flags.bitfield.cpuavx512_4vnniw)
8199 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW;
8200 if (i.tm.cpu_flags.bitfield.cpuavx512_bitalg)
8201 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG;
8202 if (i.tm.cpu_flags.bitfield.cpuavx512ifma)
8203 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA;
8204 if (i.tm.cpu_flags.bitfield.cpuavx512vbmi)
8205 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI;
8206 if (i.tm.cpu_flags.bitfield.cpuavx512_vbmi2)
8207 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2;
8208 if (i.tm.cpu_flags.bitfield.cpuavx512_vnni)
8209 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI;
462cac58
L		 8210 if (i.tm.cpu_flags.bitfield.cpuavx512_bf16)
8211 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_BF16;
b4a3a7b4
L		 8212
8213 if (i.tm.cpu_flags.bitfield.cpu8087
8214 || i.tm.cpu_flags.bitfield.cpu287
8215 || i.tm.cpu_flags.bitfield.cpu387
8216 || i.tm.cpu_flags.bitfield.cpu687
8217 || i.tm.cpu_flags.bitfield.cpufisttp)
8218 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X87;
8219 /* Don't set GNU_PROPERTY_X86_FEATURE_2_MMX for prefetchtXXX nor
8220 Xfence instructions. */
8221 if (i.tm.base_opcode != 0xf18
8222 && i.tm.base_opcode != 0xf0d
8223 && i.tm.base_opcode != 0xfae
8224 && (i.has_regmmx
8225 || i.tm.cpu_flags.bitfield.cpummx
8226 || i.tm.cpu_flags.bitfield.cpua3dnow
8227 || i.tm.cpu_flags.bitfield.cpua3dnowa))
8228 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_MMX;
8229 if (i.has_regxmm)
8230 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XMM;
8231 if (i.has_regymm)
8232 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_YMM;
8233 if (i.has_regzmm)
8234 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_ZMM;
8235 if (i.tm.cpu_flags.bitfield.cpufxsr)
8236 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_FXSR;
8237 if (i.tm.cpu_flags.bitfield.cpuxsave)
8238 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVE;
8239 if (i.tm.cpu_flags.bitfield.cpuxsaveopt)
8240 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT;
8241 if (i.tm.cpu_flags.bitfield.cpuxsavec)
8242 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEC;
8243 }
8244#endif
8245
29b0f896
AM		 8246 /* Tie dwarf2 debug info to the address at the start of the insn.
8247 We can't do this after the insn has been output as the current
8248 frag may have been closed off. eg. by frag_var. */
8249 dwarf2_emit_insn (0);
8250
2bbd9c25
JJ		 8251 insn_start_frag = frag_now;
8252 insn_start_off = frag_now_fix ();
8253
29b0f896 8254 /* Output jumps. */
40fb9820 8255 if (i.tm.opcode_modifier.jump)
29b0f896 8256 output_branch ();
40fb9820
L		 8257 else if (i.tm.opcode_modifier.jumpbyte
8258 || i.tm.opcode_modifier.jumpdword)
29b0f896 8259 output_jump ();
40fb9820 8260 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 8261 output_interseg_jump ();
8262 else
8263 {
8264 /* Output normal instructions here. */
8265 char *p;
8266 unsigned char *q;
47465058 8267 unsigned int j;
331d2d0d 8268 unsigned int prefix;
4dffcebc 8269
e4e00185
AS		 8270 if (avoid_fence
8271 && i.tm.base_opcode == 0xfae
8272 && i.operands == 1
8273 && i.imm_operands == 1
8274 && (i.op[0].imms->X_add_number == 0xe8
8275 || i.op[0].imms->X_add_number == 0xf0
8276 || i.op[0].imms->X_add_number == 0xf8))
8277 {
8278 /* Encode lfence, mfence, and sfence as
8279 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
8280 offsetT val = 0x240483f0ULL;
8281 p = frag_more (5);
8282 md_number_to_chars (p, val, 5);
8283 return;
8284 }
8285
d022bddd
IT		 8286 /* Some processors fail on LOCK prefix. This options makes
8287 assembler ignore LOCK prefix and serves as a workaround. */
8288 if (omit_lock_prefix)
8289 {
8290 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
8291 return;
8292 i.prefix[LOCK_PREFIX] = 0;
8293 }
8294
43234a1e
L		 8295 /* Since the VEX/EVEX prefix contains the implicit prefix, we
8296 don't need the explicit prefix. */
8297 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
bc4bd9ab 8298 {
c0f3af97 8299 switch (i.tm.opcode_length)
bc4bd9ab 8300 {
c0f3af97
L		 8301 case 3:
8302 if (i.tm.base_opcode & 0xff000000)
4dffcebc 8303 {
c0f3af97 8304 prefix = (i.tm.base_opcode >> 24) & 0xff;
bd59a631 8305 add_prefix (prefix);
c0f3af97
L		 8306 }
8307 break;
8308 case 2:
8309 if ((i.tm.base_opcode & 0xff0000) != 0)
8310 {
8311 prefix = (i.tm.base_opcode >> 16) & 0xff;
bd59a631
JB		 8312 if (!i.tm.cpu_flags.bitfield.cpupadlock
8313 || prefix != REPE_PREFIX_OPCODE
8314 || (i.prefix[REP_PREFIX] != REPE_PREFIX_OPCODE))
4dffcebc
L		 8315 add_prefix (prefix);
8316 }
c0f3af97
L		 8317 break;
8318 case 1:
8319 break;
390c91cf
L		 8320 case 0:
8321 /* Check for pseudo prefixes. */
8322 as_bad_where (insn_start_frag->fr_file,
8323 insn_start_frag->fr_line,
8324 _("pseudo prefix without instruction"));
8325 return;
c0f3af97
L		 8326 default:
8327 abort ();
bc4bd9ab 8328 }
c0f3af97 8329
6d19a37a 8330#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
cf61b747
L		 8331 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
8332 R_X86_64_GOTTPOFF relocation so that linker can safely
8333 perform IE->LE optimization. */
8334 if (x86_elf_abi == X86_64_X32_ABI
8335 && i.operands == 2
8336 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
8337 && i.prefix[REX_PREFIX] == 0)
8338 add_prefix (REX_OPCODE);
6d19a37a 8339#endif
cf61b747 8340
c0f3af97
L		 8341 /* The prefix bytes. */
8342 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
8343 if (*q)
8344 FRAG_APPEND_1_CHAR (*q);
0f10071e 8345 }
ae5c1c7b 8346 else
c0f3af97
L		 8347 {
8348 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
8349 if (*q)
8350 switch (j)
8351 {
8352 case REX_PREFIX:
8353 /* REX byte is encoded in VEX prefix. */
8354 break;
8355 case SEG_PREFIX:
8356 case ADDR_PREFIX:
8357 FRAG_APPEND_1_CHAR (*q);
8358 break;
8359 default:
8360 /* There should be no other prefixes for instructions
8361 with VEX prefix. */
8362 abort ();
8363 }
8364
43234a1e
L		 8365 /* For EVEX instructions i.vrex should become 0 after
8366 build_evex_prefix. For VEX instructions upper 16 registers
8367 aren't available, so VREX should be 0. */
8368 if (i.vrex)
8369 abort ();
c0f3af97
L		 8370 /* Now the VEX prefix. */
8371 p = frag_more (i.vex.length);
8372 for (j = 0; j < i.vex.length; j++)
8373 p[j] = i.vex.bytes[j];
8374 }
252b5132 8375
29b0f896 8376 /* Now the opcode; be careful about word order here! */
4dffcebc 8377 if (i.tm.opcode_length == 1)
29b0f896
AM		 8378 {
8379 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
8380 }
8381 else
8382 {
4dffcebc 8383 switch (i.tm.opcode_length)
331d2d0d 8384 {
43234a1e
L		 8385 case 4:
8386 p = frag_more (4);
8387 *p++ = (i.tm.base_opcode >> 24) & 0xff;
8388 *p++ = (i.tm.base_opcode >> 16) & 0xff;
8389 break;
4dffcebc 8390 case 3:
331d2d0d
L		 8391 p = frag_more (3);
8392 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 8393 break;
8394 case 2:
8395 p = frag_more (2);
8396 break;
8397 default:
8398 abort ();
8399 break;
331d2d0d 8400 }
0f10071e 8401
29b0f896
AM		 8402 /* Put out high byte first: can't use md_number_to_chars! */
8403 *p++ = (i.tm.base_opcode >> 8) & 0xff;
8404 *p = i.tm.base_opcode & 0xff;
8405 }
3e73aa7c 8406
29b0f896 8407 /* Now the modrm byte and sib byte (if present). */
40fb9820 8408 if (i.tm.opcode_modifier.modrm)
29b0f896 8409 {
4a3523fa
L		 8410 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
8411 | i.rm.reg << 3
8412 | i.rm.mode << 6));
29b0f896
AM		 8413 /* If i.rm.regmem == ESP (4)
8414 && i.rm.mode != (Register mode)
8415 && not 16 bit
8416 ==> need second modrm byte. */
8417 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
8418 && i.rm.mode != 3
dc821c5f 8419 && !(i.base_reg && i.base_reg->reg_type.bitfield.word))
4a3523fa
L		 8420 FRAG_APPEND_1_CHAR ((i.sib.base << 0
8421 | i.sib.index << 3
8422 | i.sib.scale << 6));
29b0f896 8423 }
3e73aa7c 8424
29b0f896 8425 if (i.disp_operands)
2bbd9c25 8426 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 8427
29b0f896 8428 if (i.imm_operands)
2bbd9c25 8429 output_imm (insn_start_frag, insn_start_off);
9c33702b
JB		 8430
8431 /*
8432 * frag_now_fix () returning plain abs_section_offset when we're in the
8433 * absolute section, and abs_section_offset not getting updated as data
8434 * gets added to the frag breaks the logic below.
8435 */
8436 if (now_seg != absolute_section)
8437 {
8438 j = encoding_length (insn_start_frag, insn_start_off, frag_more (0));
8439 if (j > 15)
8440 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
8441 j);
8442 }
29b0f896 8443 }
252b5132 8444
29b0f896
AM		 8445#ifdef DEBUG386
8446 if (flag_debug)
8447 {
7b81dfbb 8448 pi ("" /*line*/, &i);
29b0f896
AM		 8449 }
8450#endif /* DEBUG386 */
8451}
252b5132 8452
e205caa7
L		 8453/* Return the size of the displacement operand N. */
8454
8455static int
8456disp_size (unsigned int n)
8457{
8458 int size = 4;
43234a1e 8459
b5014f7a 8460 if (i.types[n].bitfield.disp64)
40fb9820
L		 8461 size = 8;
8462 else if (i.types[n].bitfield.disp8)
8463 size = 1;
8464 else if (i.types[n].bitfield.disp16)
8465 size = 2;
e205caa7
L		 8466 return size;
8467}
8468
8469/* Return the size of the immediate operand N. */
8470
8471static int
8472imm_size (unsigned int n)
8473{
8474 int size = 4;
40fb9820
L		 8475 if (i.types[n].bitfield.imm64)
8476 size = 8;
8477 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
8478 size = 1;
8479 else if (i.types[n].bitfield.imm16)
8480 size = 2;
e205caa7
L		 8481 return size;
8482}
8483
29b0f896 8484static void
64e74474 8485output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 8486{
8487 char *p;
8488 unsigned int n;
252b5132 8489
29b0f896
AM		 8490 for (n = 0; n < i.operands; n++)
8491 {
b5014f7a 8492 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 8493 {
8494 if (i.op[n].disps->X_op == O_constant)
8495 {
e205caa7 8496 int size = disp_size (n);
43234a1e 8497 offsetT val = i.op[n].disps->X_add_number;
252b5132 8498
629cfaf1
JB		 8499 val = offset_in_range (val >> (size == 1 ? i.memshift : 0),
8500 size);
29b0f896
AM		 8501 p = frag_more (size);
8502 md_number_to_chars (p, val, size);
8503 }
8504 else
8505 {
f86103b7 8506 enum bfd_reloc_code_real reloc_type;
e205caa7 8507 int size = disp_size (n);
40fb9820 8508 int sign = i.types[n].bitfield.disp32s;
29b0f896 8509 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
02a86693 8510 fixS *fixP;
29b0f896 8511
e205caa7 8512 /* We can't have 8 bit displacement here. */
9c2799c2 8513 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 8514
29b0f896
AM		 8515 /* The PC relative address is computed relative
8516 to the instruction boundary, so in case immediate
8517 fields follows, we need to adjust the value. */
8518 if (pcrel && i.imm_operands)
8519 {
29b0f896 8520 unsigned int n1;
e205caa7 8521 int sz = 0;
252b5132 8522
29b0f896 8523 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 8524 if (operand_type_check (i.types[n1], imm))
252b5132 8525 {
e205caa7
L		 8526 /* Only one immediate is allowed for PC
8527 relative address. */
9c2799c2 8528 gas_assert (sz == 0);
e205caa7
L		 8529 sz = imm_size (n1);
8530 i.op[n].disps->X_add_number -= sz;
252b5132 8531 }
29b0f896 8532 /* We should find the immediate. */
9c2799c2 8533 gas_assert (sz != 0);
29b0f896 8534 }
520dc8e8 8535
29b0f896 8536 p = frag_more (size);
d258b828 8537 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 8538 if (GOT_symbol
2bbd9c25 8539 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 8540 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 8541 || reloc_type == BFD_RELOC_X86_64_32S
8542 || (reloc_type == BFD_RELOC_64
8543 && object_64bit))
d6ab8113
JB		 8544 && (i.op[n].disps->X_op == O_symbol
8545 || (i.op[n].disps->X_op == O_add
8546 && ((symbol_get_value_expression
8547 (i.op[n].disps->X_op_symbol)->X_op)
8548 == O_subtract))))
8549 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25 8550 {
4fa24527 8551 if (!object_64bit)
7b81dfbb
AJ		 8552 {
8553 reloc_type = BFD_RELOC_386_GOTPC;
d583596c
JB		 8554 i.op[n].imms->X_add_number +=
8555 encoding_length (insn_start_frag, insn_start_off, p);
7b81dfbb
AJ		 8556 }
8557 else if (reloc_type == BFD_RELOC_64)
8558 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 8559 else
7b81dfbb
AJ		 8560 /* Don't do the adjustment for x86-64, as there
8561 the pcrel addressing is relative to the _next_
8562 insn, and that is taken care of in other code. */
d6ab8113 8563 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 8564 }
02a86693
L		 8565 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
8566 size, i.op[n].disps, pcrel,
8567 reloc_type);
8568 /* Check for "call/jmp *mem", "mov mem, %reg",
8569 "test %reg, mem" and "binop mem, %reg" where binop
8570 is one of adc, add, and, cmp, or, sbb, sub, xor
e60f4d3b
L		 8571 instructions without data prefix. Always generate
8572 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
8573 if (i.prefix[DATA_PREFIX] == 0
8574 && (generate_relax_relocations
8575 || (!object_64bit
8576 && i.rm.mode == 0
8577 && i.rm.regmem == 5))
0cb4071e
L		 8578 && (i.rm.mode == 2
8579 || (i.rm.mode == 0 && i.rm.regmem == 5))
02a86693
L		 8580 && ((i.operands == 1
8581 && i.tm.base_opcode == 0xff
8582 && (i.rm.reg == 2 || i.rm.reg == 4))
8583 || (i.operands == 2
8584 && (i.tm.base_opcode == 0x8b
8585 || i.tm.base_opcode == 0x85
8586 || (i.tm.base_opcode & 0xc7) == 0x03))))
8587 {
8588 if (object_64bit)
8589 {
8590 fixP->fx_tcbit = i.rex != 0;
8591 if (i.base_reg
e968fc9b 8592 && (i.base_reg->reg_num == RegIP))
02a86693
L		 8593 fixP->fx_tcbit2 = 1;
8594 }
8595 else
8596 fixP->fx_tcbit2 = 1;
8597 }
29b0f896
AM		 8598 }
8599 }
8600 }
8601}
252b5132 8602
29b0f896 8603static void
64e74474 8604output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 8605{
8606 char *p;
8607 unsigned int n;
252b5132 8608
29b0f896
AM		 8609 for (n = 0; n < i.operands; n++)
8610 {
43234a1e
L		 8611 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
8612 if (i.rounding && (int) n == i.rounding->operand)
8613 continue;
8614
40fb9820 8615 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 8616 {
8617 if (i.op[n].imms->X_op == O_constant)
8618 {
e205caa7 8619 int size = imm_size (n);
29b0f896 8620 offsetT val;
b4cac588 8621
29b0f896
AM		 8622 val = offset_in_range (i.op[n].imms->X_add_number,
8623 size);
8624 p = frag_more (size);
8625 md_number_to_chars (p, val, size);
8626 }
8627 else
8628 {
8629 /* Not absolute_section.
8630 Need a 32-bit fixup (don't support 8bit
8631 non-absolute imms). Try to support other
8632 sizes ... */
f86103b7 8633 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 8634 int size = imm_size (n);
8635 int sign;
29b0f896 8636
40fb9820 8637 if (i.types[n].bitfield.imm32s
a7d61044 8638 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 8639 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 8640 sign = 1;
e205caa7
L		 8641 else
8642 sign = 0;
520dc8e8 8643
29b0f896 8644 p = frag_more (size);
d258b828 8645 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 8646
2bbd9c25
JJ		 8647 /* This is tough to explain. We end up with this one if we
8648 * have operands that look like
8649 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
8650 * obtain the absolute address of the GOT, and it is strongly
8651 * preferable from a performance point of view to avoid using
8652 * a runtime relocation for this. The actual sequence of
8653 * instructions often look something like:
8654 *
8655 * call .L66
8656 * .L66:
8657 * popl %ebx
8658 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
8659 *
8660 * The call and pop essentially return the absolute address
8661 * of the label .L66 and store it in %ebx. The linker itself
8662 * will ultimately change the first operand of the addl so
8663 * that %ebx points to the GOT, but to keep things simple, the
8664 * .o file must have this operand set so that it generates not
8665 * the absolute address of .L66, but the absolute address of
8666 * itself. This allows the linker itself simply treat a GOTPC
8667 * relocation as asking for a pcrel offset to the GOT to be
8668 * added in, and the addend of the relocation is stored in the
8669 * operand field for the instruction itself.
8670 *
8671 * Our job here is to fix the operand so that it would add
8672 * the correct offset so that %ebx would point to itself. The
8673 * thing that is tricky is that .-.L66 will point to the
8674 * beginning of the instruction, so we need to further modify
8675 * the operand so that it will point to itself. There are
8676 * other cases where you have something like:
8677 *
8678 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
8679 *
8680 * and here no correction would be required. Internally in
8681 * the assembler we treat operands of this form as not being
8682 * pcrel since the '.' is explicitly mentioned, and I wonder
8683 * whether it would simplify matters to do it this way. Who
8684 * knows. In earlier versions of the PIC patches, the
8685 * pcrel_adjust field was used to store the correction, but
8686 * since the expression is not pcrel, I felt it would be
8687 * confusing to do it this way. */
8688
d6ab8113 8689 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 8690 || reloc_type == BFD_RELOC_X86_64_32S
8691 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 8692 && GOT_symbol
8693 && GOT_symbol == i.op[n].imms->X_add_symbol
8694 && (i.op[n].imms->X_op == O_symbol
8695 || (i.op[n].imms->X_op == O_add
8696 && ((symbol_get_value_expression
8697 (i.op[n].imms->X_op_symbol)->X_op)
8698 == O_subtract))))
8699 {
4fa24527 8700 if (!object_64bit)
d6ab8113 8701 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 8702 else if (size == 4)
d6ab8113 8703 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 8704 else if (size == 8)
8705 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d583596c
JB		 8706 i.op[n].imms->X_add_number +=
8707 encoding_length (insn_start_frag, insn_start_off, p);
29b0f896 8708 }
29b0f896
AM		 8709 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
8710 i.op[n].imms, 0, reloc_type);
8711 }
8712 }
8713 }
252b5132
RH		 8714}
8715\f
d182319b
JB		 8716/* x86_cons_fix_new is called via the expression parsing code when a
8717 reloc is needed. We use this hook to get the correct .got reloc. */
d182319b
JB		 8718static int cons_sign = -1;
8719
8720void
e3bb37b5 8721x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
62ebcb5c 8722 expressionS *exp, bfd_reloc_code_real_type r)
d182319b 8723{
d258b828 8724 r = reloc (len, 0, cons_sign, r);
d182319b
JB		 8725
8726#ifdef TE_PE
8727 if (exp->X_op == O_secrel)
8728 {
8729 exp->X_op = O_symbol;
8730 r = BFD_RELOC_32_SECREL;
8731 }
8732#endif
8733
8734 fix_new_exp (frag, off, len, exp, 0, r);
8735}
8736
357d1bd8
L		 8737/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8738 purpose of the `.dc.a' internal pseudo-op. */
8739
8740int
8741x86_address_bytes (void)
8742{
8743 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
8744 return 4;
8745 return stdoutput->arch_info->bits_per_address / 8;
8746}
8747
d382c579
TG		 8748#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8749 || defined (LEX_AT)
d258b828 8750# define lex_got(reloc, adjust, types) NULL
718ddfc0 8751#else
f3c180ae
AM		 8752/* Parse operands of the form
8753 <symbol>@GOTOFF+<nnn>
8754 and similar .plt or .got references.
8755
8756 If we find one, set up the correct relocation in RELOC and copy the
8757 input string, minus the `@GOTOFF' into a malloc'd buffer for
8758 parsing by the calling routine. Return this buffer, and if ADJUST
8759 is non-null set it to the length of the string we removed from the
8760 input line. Otherwise return NULL. */
8761static char *
91d6fa6a 8762lex_got (enum bfd_reloc_code_real *rel,
64e74474 8763 int *adjust,
d258b828 8764 i386_operand_type *types)
f3c180ae 8765{
7b81dfbb
AJ		 8766 /* Some of the relocations depend on the size of what field is to
8767 be relocated. But in our callers i386_immediate and i386_displacement
8768 we don't yet know the operand size (this will be set by insn
8769 matching). Hence we record the word32 relocation here,
8770 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 8771 static const struct {
8772 const char *str;
cff8d58a 8773 int len;
4fa24527 8774 const enum bfd_reloc_code_real rel[2];
40fb9820 8775 const i386_operand_type types64;
f3c180ae 8776 } gotrel[] = {
8ce3d284 8777#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 8778 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
8779 BFD_RELOC_SIZE32 },
8780 OPERAND_TYPE_IMM32_64 },
8ce3d284 8781#endif
cff8d58a
L		 8782 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
8783 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 8784 OPERAND_TYPE_IMM64 },
cff8d58a
L		 8785 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
8786 BFD_RELOC_X86_64_PLT32 },
40fb9820 8787 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8788 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
8789 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 8790 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 8791 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
8792 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 8793 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 8794 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
8795 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 8796 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8797 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
8798 BFD_RELOC_X86_64_TLSGD },
40fb9820 8799 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8800 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
8801 _dummy_first_bfd_reloc_code_real },
40fb9820 8802 OPERAND_TYPE_NONE },
cff8d58a
L		 8803 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
8804 BFD_RELOC_X86_64_TLSLD },
40fb9820 8805 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8806 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
8807 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 8808 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8809 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
8810 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 8811 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 8812 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
8813 _dummy_first_bfd_reloc_code_real },
40fb9820 8814 OPERAND_TYPE_NONE },
cff8d58a
L		 8815 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
8816 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 8817 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 8818 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
8819 _dummy_first_bfd_reloc_code_real },
40fb9820 8820 OPERAND_TYPE_NONE },
cff8d58a
L		 8821 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
8822 _dummy_first_bfd_reloc_code_real },
40fb9820 8823 OPERAND_TYPE_NONE },
cff8d58a
L		 8824 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
8825 BFD_RELOC_X86_64_GOT32 },
40fb9820 8826 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 8827 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
8828 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 8829 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8830 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
8831 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 8832 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 8833 };
8834 char *cp;
8835 unsigned int j;
8836
d382c579 8837#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 8838 if (!IS_ELF)
8839 return NULL;
d382c579 8840#endif
718ddfc0 8841
f3c180ae 8842 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 8843 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 8844 return NULL;
8845
47465058 8846 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 8847 {
cff8d58a 8848 int len = gotrel[j].len;
28f81592 8849 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 8850 {
4fa24527 8851 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 8852 {
28f81592
AM		 8853 int first, second;
8854 char *tmpbuf, *past_reloc;
f3c180ae 8855
91d6fa6a 8856 *rel = gotrel[j].rel[object_64bit];
f3c180ae 8857
3956db08
JB		 8858 if (types)
8859 {
8860 if (flag_code != CODE_64BIT)
40fb9820
L		 8861 {
8862 types->bitfield.imm32 = 1;
8863 types->bitfield.disp32 = 1;
8864 }
3956db08
JB		 8865 else
8866 *types = gotrel[j].types64;
8867 }
8868
8fd4256d 8869 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 8870 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
8871
28f81592 8872 /* The length of the first part of our input line. */
f3c180ae 8873 first = cp - input_line_pointer;
28f81592
AM		 8874
8875 /* The second part goes from after the reloc token until
67c11a9b 8876 (and including) an end_of_line char or comma. */
28f81592 8877 past_reloc = cp + 1 + len;
67c11a9b
AM		 8878 cp = past_reloc;
8879 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8880 ++cp;
8881 second = cp + 1 - past_reloc;
28f81592
AM		 8882
8883 /* Allocate and copy string. The trailing NUL shouldn't
8884 be necessary, but be safe. */
add39d23 8885 tmpbuf = XNEWVEC (char, first + second + 2);
f3c180ae 8886 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 8887 if (second != 0 && *past_reloc != ' ')
8888 /* Replace the relocation token with ' ', so that
8889 errors like foo@GOTOFF1 will be detected. */
8890 tmpbuf[first++] = ' ';
af89796a
L		 8891 else
8892 /* Increment length by 1 if the relocation token is
8893 removed. */
8894 len++;
8895 if (adjust)
8896 *adjust = len;
0787a12d
AM		 8897 memcpy (tmpbuf + first, past_reloc, second);
8898 tmpbuf[first + second] = '\0';
f3c180ae
AM		 8899 return tmpbuf;
8900 }
8901
4fa24527
JB		 8902 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8903 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 8904 return NULL;
8905 }
8906 }
8907
8908 /* Might be a symbol version string. Don't as_bad here. */
8909 return NULL;
8910}
4e4f7c87 8911#endif
f3c180ae 8912
a988325c
NC		 8913#ifdef TE_PE
8914#ifdef lex_got
8915#undef lex_got
8916#endif
8917/* Parse operands of the form
8918 <symbol>@SECREL32+<nnn>
8919
8920 If we find one, set up the correct relocation in RELOC and copy the
8921 input string, minus the `@SECREL32' into a malloc'd buffer for
8922 parsing by the calling routine. Return this buffer, and if ADJUST
8923 is non-null set it to the length of the string we removed from the
34bca508
L		 8924 input line. Otherwise return NULL.
8925
a988325c
NC		 8926 This function is copied from the ELF version above adjusted for PE targets. */
8927
8928static char *
8929lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
8930 int *adjust ATTRIBUTE_UNUSED,
d258b828 8931 i386_operand_type *types)
a988325c
NC		 8932{
8933 static const struct
8934 {
8935 const char *str;
8936 int len;
8937 const enum bfd_reloc_code_real rel[2];
8938 const i386_operand_type types64;
8939 }
8940 gotrel[] =
8941 {
8942 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
8943 BFD_RELOC_32_SECREL },
8944 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8945 };
8946
8947 char *cp;
8948 unsigned j;
8949
8950 for (cp = input_line_pointer; *cp != '@'; cp++)
8951 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8952 return NULL;
8953
8954 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8955 {
8956 int len = gotrel[j].len;
8957
8958 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8959 {
8960 if (gotrel[j].rel[object_64bit] != 0)
8961 {
8962 int first, second;
8963 char *tmpbuf, *past_reloc;
8964
8965 *rel = gotrel[j].rel[object_64bit];
8966 if (adjust)
8967 *adjust = len;
8968
8969 if (types)
8970 {
8971 if (flag_code != CODE_64BIT)
8972 {
8973 types->bitfield.imm32 = 1;
8974 types->bitfield.disp32 = 1;
8975 }
8976 else
8977 *types = gotrel[j].types64;
8978 }
8979
8980 /* The length of the first part of our input line. */
8981 first = cp - input_line_pointer;
8982
8983 /* The second part goes from after the reloc token until
8984 (and including) an end_of_line char or comma. */
8985 past_reloc = cp + 1 + len;
8986 cp = past_reloc;
8987 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8988 ++cp;
8989 second = cp + 1 - past_reloc;
8990
8991 /* Allocate and copy string. The trailing NUL shouldn't
8992 be necessary, but be safe. */
add39d23 8993 tmpbuf = XNEWVEC (char, first + second + 2);
a988325c
NC		 8994 memcpy (tmpbuf, input_line_pointer, first);
8995 if (second != 0 && *past_reloc != ' ')
8996 /* Replace the relocation token with ' ', so that
8997 errors like foo@SECLREL321 will be detected. */
8998 tmpbuf[first++] = ' ';
8999 memcpy (tmpbuf + first, past_reloc, second);
9000 tmpbuf[first + second] = '\0';
9001 return tmpbuf;
9002 }
9003
9004 as_bad (_("@%s reloc is not supported with %d-bit output format"),
9005 gotrel[j].str, 1 << (5 + object_64bit));
9006 return NULL;
9007 }
9008 }
9009
9010 /* Might be a symbol version string. Don't as_bad here. */
9011 return NULL;
9012}
9013
9014#endif /* TE_PE */
9015
62ebcb5c 9016bfd_reloc_code_real_type
e3bb37b5 9017x86_cons (expressionS *exp, int size)
f3c180ae 9018{
62ebcb5c
AM		 9019 bfd_reloc_code_real_type got_reloc = NO_RELOC;
9020
ee86248c
JB		 9021 intel_syntax = -intel_syntax;
9022
3c7b9c2c 9023 exp->X_md = 0;
4fa24527 9024 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 9025 {
9026 /* Handle @GOTOFF and the like in an expression. */
9027 char *save;
9028 char *gotfree_input_line;
4a57f2cf 9029 int adjust = 0;
f3c180ae
AM		 9030
9031 save = input_line_pointer;
d258b828 9032 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 9033 if (gotfree_input_line)
9034 input_line_pointer = gotfree_input_line;
9035
9036 expression (exp);
9037
9038 if (gotfree_input_line)
9039 {
9040 /* expression () has merrily parsed up to the end of line,
9041 or a comma - in the wrong buffer. Transfer how far
9042 input_line_pointer has moved to the right buffer. */
9043 input_line_pointer = (save
9044 + (input_line_pointer - gotfree_input_line)
9045 + adjust);
9046 free (gotfree_input_line);
3992d3b7
AM		 9047 if (exp->X_op == O_constant
9048 || exp->X_op == O_absent
9049 || exp->X_op == O_illegal
0398aac5 9050 || exp->X_op == O_register
3992d3b7
AM		 9051 || exp->X_op == O_big)
9052 {
9053 char c = *input_line_pointer;
9054 *input_line_pointer = 0;
9055 as_bad (_("missing or invalid expression `%s'"), save);
9056 *input_line_pointer = c;
9057 }
b9519cfe
L		 9058 else if ((got_reloc == BFD_RELOC_386_PLT32
9059 || got_reloc == BFD_RELOC_X86_64_PLT32)
9060 && exp->X_op != O_symbol)
9061 {
9062 char c = *input_line_pointer;
9063 *input_line_pointer = 0;
9064 as_bad (_("invalid PLT expression `%s'"), save);
9065 *input_line_pointer = c;
9066 }
f3c180ae
AM		 9067 }
9068 }
9069 else
9070 expression (exp);
ee86248c
JB		 9071
9072 intel_syntax = -intel_syntax;
9073
9074 if (intel_syntax)
9075 i386_intel_simplify (exp);
62ebcb5c
AM		 9076
9077 return got_reloc;
f3c180ae 9078}
f3c180ae 9079
9f32dd5b
L		 9080static void
9081signed_cons (int size)
6482c264 9082{
d182319b
JB		 9083 if (flag_code == CODE_64BIT)
9084 cons_sign = 1;
9085 cons (size);
9086 cons_sign = -1;
6482c264
NC		 9087}
9088
d182319b 9089#ifdef TE_PE
6482c264 9090static void
7016a5d5 9091pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 9092{
9093 expressionS exp;
9094
9095 do
9096 {
9097 expression (&exp);
9098 if (exp.X_op == O_symbol)
9099 exp.X_op = O_secrel;
9100
9101 emit_expr (&exp, 4);
9102 }
9103 while (*input_line_pointer++ == ',');
9104
9105 input_line_pointer--;
9106 demand_empty_rest_of_line ();
9107}
6482c264
NC		 9108#endif
9109
43234a1e
L		 9110/* Handle Vector operations. */
9111
9112static char *
9113check_VecOperations (char *op_string, char *op_end)
9114{
9115 const reg_entry *mask;
9116 const char *saved;
9117 char *end_op;
9118
9119 while (*op_string
9120 && (op_end == NULL || op_string < op_end))
9121 {
9122 saved = op_string;
9123 if (*op_string == '{')
9124 {
9125 op_string++;
9126
9127 /* Check broadcasts. */
9128 if (strncmp (op_string, "1to", 3) == 0)
9129 {
9130 int bcst_type;
9131
9132 if (i.broadcast)
9133 goto duplicated_vec_op;
9134
9135 op_string += 3;
9136 if (*op_string == '8')
8e6e0792 9137 bcst_type = 8;
b28d1bda 9138 else if (*op_string == '4')
8e6e0792 9139 bcst_type = 4;
b28d1bda 9140 else if (*op_string == '2')
8e6e0792 9141 bcst_type = 2;
43234a1e
L		 9142 else if (*op_string == '1'
9143 && *(op_string+1) == '6')
9144 {
8e6e0792 9145 bcst_type = 16;
43234a1e
L		 9146 op_string++;
9147 }
9148 else
9149 {
9150 as_bad (_("Unsupported broadcast: `%s'"), saved);
9151 return NULL;
9152 }
9153 op_string++;
9154
9155 broadcast_op.type = bcst_type;
9156 broadcast_op.operand = this_operand;
1f75763a 9157 broadcast_op.bytes = 0;
43234a1e
L		 9158 i.broadcast = &broadcast_op;
9159 }
9160 /* Check masking operation. */
9161 else if ((mask = parse_register (op_string, &end_op)) != NULL)
9162 {
9163 /* k0 can't be used for write mask. */
6d2cd6b2 9164 if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0)
43234a1e 9165 {
6d2cd6b2
JB		 9166 as_bad (_("`%s%s' can't be used for write mask"),
9167 register_prefix, mask->reg_name);
43234a1e
L		 9168 return NULL;
9169 }
9170
9171 if (!i.mask)
9172 {
9173 mask_op.mask = mask;
9174 mask_op.zeroing = 0;
9175 mask_op.operand = this_operand;
9176 i.mask = &mask_op;
9177 }
9178 else
9179 {
9180 if (i.mask->mask)
9181 goto duplicated_vec_op;
9182
9183 i.mask->mask = mask;
9184
9185 /* Only "{z}" is allowed here. No need to check
9186 zeroing mask explicitly. */
9187 if (i.mask->operand != this_operand)
9188 {
9189 as_bad (_("invalid write mask `%s'"), saved);
9190 return NULL;
9191 }
9192 }
9193
9194 op_string = end_op;
9195 }
9196 /* Check zeroing-flag for masking operation. */
9197 else if (*op_string == 'z')
9198 {
9199 if (!i.mask)
9200 {
9201 mask_op.mask = NULL;
9202 mask_op.zeroing = 1;
9203 mask_op.operand = this_operand;
9204 i.mask = &mask_op;
9205 }
9206 else
9207 {
9208 if (i.mask->zeroing)
9209 {
9210 duplicated_vec_op:
9211 as_bad (_("duplicated `%s'"), saved);
9212 return NULL;
9213 }
9214
9215 i.mask->zeroing = 1;
9216
9217 /* Only "{%k}" is allowed here. No need to check mask
9218 register explicitly. */
9219 if (i.mask->operand != this_operand)
9220 {
9221 as_bad (_("invalid zeroing-masking `%s'"),
9222 saved);
9223 return NULL;
9224 }
9225 }
9226
9227 op_string++;
9228 }
9229 else
9230 goto unknown_vec_op;
9231
9232 if (*op_string != '}')
9233 {
9234 as_bad (_("missing `}' in `%s'"), saved);
9235 return NULL;
9236 }
9237 op_string++;
0ba3a731
L		 9238
9239 /* Strip whitespace since the addition of pseudo prefixes
9240 changed how the scrubber treats '{'. */
9241 if (is_space_char (*op_string))
9242 ++op_string;
9243
43234a1e
L		 9244 continue;
9245 }
9246 unknown_vec_op:
9247 /* We don't know this one. */
9248 as_bad (_("unknown vector operation: `%s'"), saved);
9249 return NULL;
9250 }
9251
6d2cd6b2
JB		 9252 if (i.mask && i.mask->zeroing && !i.mask->mask)
9253 {
9254 as_bad (_("zeroing-masking only allowed with write mask"));
9255 return NULL;
9256 }
9257
43234a1e
L		 9258 return op_string;
9259}
9260
252b5132 9261static int
70e41ade 9262i386_immediate (char *imm_start)
252b5132
RH		 9263{
9264 char *save_input_line_pointer;
f3c180ae 9265 char *gotfree_input_line;
252b5132 9266 segT exp_seg = 0;
47926f60 9267 expressionS *exp;
40fb9820
L		 9268 i386_operand_type types;
9269
0dfbf9d7 9270 operand_type_set (&types, ~0);
252b5132
RH		 9271
9272 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
9273 {
31b2323c
L		 9274 as_bad (_("at most %d immediate operands are allowed"),
9275 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 9276 return 0;
9277 }
9278
9279 exp = &im_expressions[i.imm_operands++];
520dc8e8 9280 i.op[this_operand].imms = exp;
252b5132
RH		 9281
9282 if (is_space_char (*imm_start))
9283 ++imm_start;
9284
9285 save_input_line_pointer = input_line_pointer;
9286 input_line_pointer = imm_start;
9287
d258b828 9288 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 9289 if (gotfree_input_line)
9290 input_line_pointer = gotfree_input_line;
252b5132
RH		 9291
9292 exp_seg = expression (exp);
9293
83183c0c 9294 SKIP_WHITESPACE ();
43234a1e
L		 9295
9296 /* Handle vector operations. */
9297 if (*input_line_pointer == '{')
9298 {
9299 input_line_pointer = check_VecOperations (input_line_pointer,
9300 NULL);
9301 if (input_line_pointer == NULL)
9302 return 0;
9303 }
9304
252b5132 9305 if (*input_line_pointer)
f3c180ae 9306 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 9307
9308 input_line_pointer = save_input_line_pointer;
f3c180ae 9309 if (gotfree_input_line)
ee86248c
JB		 9310 {
9311 free (gotfree_input_line);
9312
9313 if (exp->X_op == O_constant || exp->X_op == O_register)
9314 exp->X_op = O_illegal;
9315 }
9316
9317 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
9318}
252b5132 9319
ee86248c
JB		 9320static int
9321i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
9322 i386_operand_type types, const char *imm_start)
9323{
9324 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 9325 {
313c53d1
L		 9326 if (imm_start)
9327 as_bad (_("missing or invalid immediate expression `%s'"),
9328 imm_start);
3992d3b7 9329 return 0;
252b5132 9330 }
3e73aa7c 9331 else if (exp->X_op == O_constant)
252b5132 9332 {
47926f60 9333 /* Size it properly later. */
40fb9820 9334 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 9335 /* If not 64bit, sign extend val. */
9336 if (flag_code != CODE_64BIT
4eed87de
AM		 9337 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
9338 exp->X_add_number
9339 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 9340 }
4c63da97 9341#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 9342 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 9343 && exp_seg != absolute_section
47926f60 9344 && exp_seg != text_section
24eab124
AM		 9345 && exp_seg != data_section
9346 && exp_seg != bss_section
9347 && exp_seg != undefined_section
f86103b7 9348 && !bfd_is_com_section (exp_seg))
252b5132 9349 {
d0b47220 9350 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 9351 return 0;
9352 }
9353#endif
a841bdf5 9354 else if (!intel_syntax && exp_seg == reg_section)
bb8f5920 9355 {
313c53d1
L		 9356 if (imm_start)
9357 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 9358 return 0;
9359 }
252b5132
RH		 9360 else
9361 {
9362 /* This is an address. The size of the address will be
24eab124 9363 determined later, depending on destination register,
3e73aa7c 9364 suffix, or the default for the section. */
40fb9820
L		 9365 i.types[this_operand].bitfield.imm8 = 1;
9366 i.types[this_operand].bitfield.imm16 = 1;
9367 i.types[this_operand].bitfield.imm32 = 1;
9368 i.types[this_operand].bitfield.imm32s = 1;
9369 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 9370 i.types[this_operand] = operand_type_and (i.types[this_operand],
9371 types);
252b5132
RH		 9372 }
9373
9374 return 1;
9375}
9376
551c1ca1 9377static char *
e3bb37b5 9378i386_scale (char *scale)
252b5132 9379{
551c1ca1
AM		 9380 offsetT val;
9381 char *save = input_line_pointer;
252b5132 9382
551c1ca1
AM		 9383 input_line_pointer = scale;
9384 val = get_absolute_expression ();
9385
9386 switch (val)
252b5132 9387 {
551c1ca1 9388 case 1:
252b5132
RH		 9389 i.log2_scale_factor = 0;
9390 break;
551c1ca1 9391 case 2:
252b5132
RH		 9392 i.log2_scale_factor = 1;
9393 break;
551c1ca1 9394 case 4:
252b5132
RH		 9395 i.log2_scale_factor = 2;
9396 break;
551c1ca1 9397 case 8:
252b5132
RH		 9398 i.log2_scale_factor = 3;
9399 break;
9400 default:
a724f0f4
JB		 9401 {
9402 char sep = *input_line_pointer;
9403
9404 *input_line_pointer = '\0';
9405 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
9406 scale);
9407 *input_line_pointer = sep;
9408 input_line_pointer = save;
9409 return NULL;
9410 }
252b5132 9411 }
29b0f896 9412 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 9413 {
9414 as_warn (_("scale factor of %d without an index register"),
24eab124 9415 1 << i.log2_scale_factor);
252b5132 9416 i.log2_scale_factor = 0;
252b5132 9417 }
551c1ca1
AM		 9418 scale = input_line_pointer;
9419 input_line_pointer = save;
9420 return scale;
252b5132
RH		 9421}
9422
252b5132 9423static int
e3bb37b5 9424i386_displacement (char *disp_start, char *disp_end)
252b5132 9425{
29b0f896 9426 expressionS *exp;
252b5132
RH		 9427 segT exp_seg = 0;
9428 char *save_input_line_pointer;
f3c180ae 9429 char *gotfree_input_line;
40fb9820
L		 9430 int override;
9431 i386_operand_type bigdisp, types = anydisp;
3992d3b7 9432 int ret;
252b5132 9433
31b2323c
L		 9434 if (i.disp_operands == MAX_MEMORY_OPERANDS)
9435 {
9436 as_bad (_("at most %d displacement operands are allowed"),
9437 MAX_MEMORY_OPERANDS);
9438 return 0;
9439 }
9440
0dfbf9d7 9441 operand_type_set (&bigdisp, 0);
40fb9820
L		 9442 if ((i.types[this_operand].bitfield.jumpabsolute)
9443 || (!current_templates->start->opcode_modifier.jump
9444 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 9445 {
40fb9820 9446 bigdisp.bitfield.disp32 = 1;
e05278af 9447 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 9448 if (flag_code == CODE_64BIT)
9449 {
9450 if (!override)
9451 {
9452 bigdisp.bitfield.disp32s = 1;
9453 bigdisp.bitfield.disp64 = 1;
9454 }
9455 }
9456 else if ((flag_code == CODE_16BIT) ^ override)
9457 {
9458 bigdisp.bitfield.disp32 = 0;
9459 bigdisp.bitfield.disp16 = 1;
9460 }
e05278af
JB		 9461 }
9462 else
9463 {
9464 /* For PC-relative branches, the width of the displacement
9465 is dependent upon data size, not address size. */
e05278af 9466 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 9467 if (flag_code == CODE_64BIT)
9468 {
9469 if (override || i.suffix == WORD_MNEM_SUFFIX)
9470 bigdisp.bitfield.disp16 = 1;
9471 else
9472 {
9473 bigdisp.bitfield.disp32 = 1;
9474 bigdisp.bitfield.disp32s = 1;
9475 }
9476 }
9477 else
e05278af
JB		 9478 {
9479 if (!override)
9480 override = (i.suffix == (flag_code != CODE_16BIT
9481 ? WORD_MNEM_SUFFIX
9482 : LONG_MNEM_SUFFIX));
40fb9820
L		 9483 bigdisp.bitfield.disp32 = 1;
9484 if ((flag_code == CODE_16BIT) ^ override)
9485 {
9486 bigdisp.bitfield.disp32 = 0;
9487 bigdisp.bitfield.disp16 = 1;
9488 }
e05278af 9489 }
e05278af 9490 }
c6fb90c8
L		 9491 i.types[this_operand] = operand_type_or (i.types[this_operand],
9492 bigdisp);
252b5132
RH		 9493
9494 exp = &disp_expressions[i.disp_operands];
520dc8e8 9495 i.op[this_operand].disps = exp;
252b5132
RH		 9496 i.disp_operands++;
9497 save_input_line_pointer = input_line_pointer;
9498 input_line_pointer = disp_start;
9499 END_STRING_AND_SAVE (disp_end);
9500
9501#ifndef GCC_ASM_O_HACK
9502#define GCC_ASM_O_HACK 0
9503#endif
9504#if GCC_ASM_O_HACK
9505 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 9506 if (i.types[this_operand].bitfield.baseIndex
24eab124 9507 && displacement_string_end[-1] == '+')
252b5132
RH		 9508 {
9509 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 9510 constraint within gcc asm statements.
9511 For instance:
9512
9513 #define _set_tssldt_desc(n,addr,limit,type) \
9514 __asm__ __volatile__ ( \
9515 "movw %w2,%0\n\t" \
9516 "movw %w1,2+%0\n\t" \
9517 "rorl $16,%1\n\t" \
9518 "movb %b1,4+%0\n\t" \
9519 "movb %4,5+%0\n\t" \
9520 "movb $0,6+%0\n\t" \
9521 "movb %h1,7+%0\n\t" \
9522 "rorl $16,%1" \
9523 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
9524
9525 This works great except that the output assembler ends
9526 up looking a bit weird if it turns out that there is
9527 no offset. You end up producing code that looks like:
9528
9529 #APP
9530 movw $235,(%eax)
9531 movw %dx,2+(%eax)
9532 rorl $16,%edx
9533 movb %dl,4+(%eax)
9534 movb $137,5+(%eax)
9535 movb $0,6+(%eax)
9536 movb %dh,7+(%eax)
9537 rorl $16,%edx
9538 #NO_APP
9539
47926f60 9540 So here we provide the missing zero. */
24eab124
AM		 9541
9542 *displacement_string_end = '0';
252b5132
RH		 9543 }
9544#endif
d258b828 9545 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 9546 if (gotfree_input_line)
9547 input_line_pointer = gotfree_input_line;
252b5132 9548
24eab124 9549 exp_seg = expression (exp);
252b5132 9550
636c26b0
AM		 9551 SKIP_WHITESPACE ();
9552 if (*input_line_pointer)
9553 as_bad (_("junk `%s' after expression"), input_line_pointer);
9554#if GCC_ASM_O_HACK
9555 RESTORE_END_STRING (disp_end + 1);
9556#endif
636c26b0 9557 input_line_pointer = save_input_line_pointer;
636c26b0 9558 if (gotfree_input_line)
ee86248c
JB		 9559 {
9560 free (gotfree_input_line);
9561
9562 if (exp->X_op == O_constant || exp->X_op == O_register)
9563 exp->X_op = O_illegal;
9564 }
9565
9566 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
9567
9568 RESTORE_END_STRING (disp_end);
9569
9570 return ret;
9571}
9572
9573static int
9574i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
9575 i386_operand_type types, const char *disp_start)
9576{
9577 i386_operand_type bigdisp;
9578 int ret = 1;
636c26b0 9579
24eab124
AM		 9580 /* We do this to make sure that the section symbol is in
9581 the symbol table. We will ultimately change the relocation
47926f60 9582 to be relative to the beginning of the section. */
1ae12ab7 9583 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 9584 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
9585 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 9586 {
636c26b0 9587 if (exp->X_op != O_symbol)
3992d3b7 9588 goto inv_disp;
636c26b0 9589
e5cb08ac 9590 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 9591 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
9592 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 9593 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 9594 exp->X_op = O_subtract;
9595 exp->X_op_symbol = GOT_symbol;
1ae12ab7 9596 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 9597 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 9598 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
9599 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 9600 else
29b0f896 9601 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 9602 }
252b5132 9603
3992d3b7
AM		 9604 else if (exp->X_op == O_absent
9605 || exp->X_op == O_illegal
ee86248c 9606 || exp->X_op == O_big)
2daf4fd8 9607 {
3992d3b7
AM		 9608 inv_disp:
9609 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 9610 disp_start);
3992d3b7 9611 ret = 0;
2daf4fd8
AM		 9612 }
9613
0e1147d9
L		 9614 else if (flag_code == CODE_64BIT
9615 && !i.prefix[ADDR_PREFIX]
9616 && exp->X_op == O_constant)
9617 {
9618 /* Since displacement is signed extended to 64bit, don't allow
9619 disp32 and turn off disp32s if they are out of range. */
9620 i.types[this_operand].bitfield.disp32 = 0;
9621 if (!fits_in_signed_long (exp->X_add_number))
9622 {
9623 i.types[this_operand].bitfield.disp32s = 0;
9624 if (i.types[this_operand].bitfield.baseindex)
9625 {
9626 as_bad (_("0x%lx out range of signed 32bit displacement"),
9627 (long) exp->X_add_number);
9628 ret = 0;
9629 }
9630 }
9631 }
9632
4c63da97 9633#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 9634 else if (exp->X_op != O_constant
9635 && OUTPUT_FLAVOR == bfd_target_aout_flavour
9636 && exp_seg != absolute_section
9637 && exp_seg != text_section
9638 && exp_seg != data_section
9639 && exp_seg != bss_section
9640 && exp_seg != undefined_section
9641 && !bfd_is_com_section (exp_seg))
24eab124 9642 {
d0b47220 9643 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 9644 ret = 0;
24eab124 9645 }
252b5132 9646#endif
3956db08 9647
40fb9820
L		 9648 /* Check if this is a displacement only operand. */
9649 bigdisp = i.types[this_operand];
9650 bigdisp.bitfield.disp8 = 0;
9651 bigdisp.bitfield.disp16 = 0;
9652 bigdisp.bitfield.disp32 = 0;
9653 bigdisp.bitfield.disp32s = 0;
9654 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 9655 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 9656 i.types[this_operand] = operand_type_and (i.types[this_operand],
9657 types);
3956db08 9658
3992d3b7 9659 return ret;
252b5132
RH		 9660}
9661
2abc2bec
JB		 9662/* Return the active addressing mode, taking address override and
9663 registers forming the address into consideration. Update the
9664 address override prefix if necessary. */
47926f60 9665
2abc2bec
JB		 9666static enum flag_code
9667i386_addressing_mode (void)
252b5132 9668{
be05d201
L		 9669 enum flag_code addr_mode;
9670
9671 if (i.prefix[ADDR_PREFIX])
9672 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
9673 else
9674 {
9675 addr_mode = flag_code;
9676
24eab124 9677#if INFER_ADDR_PREFIX
be05d201
L		 9678 if (i.mem_operands == 0)
9679 {
9680 /* Infer address prefix from the first memory operand. */
9681 const reg_entry *addr_reg = i.base_reg;
9682
9683 if (addr_reg == NULL)
9684 addr_reg = i.index_reg;
eecb386c 9685
be05d201
L		 9686 if (addr_reg)
9687 {
e968fc9b 9688 if (addr_reg->reg_type.bitfield.dword)
be05d201
L		 9689 addr_mode = CODE_32BIT;
9690 else if (flag_code != CODE_64BIT
dc821c5f 9691 && addr_reg->reg_type.bitfield.word)
be05d201
L		 9692 addr_mode = CODE_16BIT;
9693
9694 if (addr_mode != flag_code)
9695 {
9696 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
9697 i.prefixes += 1;
9698 /* Change the size of any displacement too. At most one
9699 of Disp16 or Disp32 is set.
9700 FIXME. There doesn't seem to be any real need for
9701 separate Disp16 and Disp32 flags. The same goes for
9702 Imm16 and Imm32. Removing them would probably clean
9703 up the code quite a lot. */
9704 if (flag_code != CODE_64BIT
9705 && (i.types[this_operand].bitfield.disp16
9706 || i.types[this_operand].bitfield.disp32))
9707 i.types[this_operand]
9708 = operand_type_xor (i.types[this_operand], disp16_32);
9709 }
9710 }
9711 }
24eab124 9712#endif
be05d201
L		 9713 }
9714
2abc2bec
JB		 9715 return addr_mode;
9716}
9717
9718/* Make sure the memory operand we've been dealt is valid.
9719 Return 1 on success, 0 on a failure. */
9720
9721static int
9722i386_index_check (const char *operand_string)
9723{
9724 const char *kind = "base/index";
9725 enum flag_code addr_mode = i386_addressing_mode ();
9726
fc0763e6
JB		 9727 if (current_templates->start->opcode_modifier.isstring
9728 && !current_templates->start->opcode_modifier.immext
9729 && (current_templates->end[-1].opcode_modifier.isstring
9730 || i.mem_operands))
9731 {
9732 /* Memory operands of string insns are special in that they only allow
9733 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 9734 const reg_entry *expected_reg;
9735 static const char *di_si[][2] =
9736 {
9737 { "esi", "edi" },
9738 { "si", "di" },
9739 { "rsi", "rdi" }
9740 };
9741 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 9742
9743 kind = "string address";
9744
8325cc63 9745 if (current_templates->start->opcode_modifier.repprefixok)
fc0763e6
JB		 9746 {
9747 i386_operand_type type = current_templates->end[-1].operand_types[0];
9748
9749 if (!type.bitfield.baseindex
9750 || ((!i.mem_operands != !intel_syntax)
9751 && current_templates->end[-1].operand_types[1]
9752 .bitfield.baseindex))
9753 type = current_templates->end[-1].operand_types[1];
be05d201
L		 9754 expected_reg = hash_find (reg_hash,
9755 di_si[addr_mode][type.bitfield.esseg]);
9756
fc0763e6
JB		 9757 }
9758 else
be05d201 9759 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 9760
be05d201
L		 9761 if (i.base_reg != expected_reg
9762 || i.index_reg
fc0763e6 9763 || operand_type_check (i.types[this_operand], disp))
fc0763e6 9764 {
be05d201
L		 9765 /* The second memory operand must have the same size as
9766 the first one. */
9767 if (i.mem_operands
9768 && i.base_reg
9769 && !((addr_mode == CODE_64BIT
dc821c5f 9770 && i.base_reg->reg_type.bitfield.qword)
be05d201 9771 || (addr_mode == CODE_32BIT
dc821c5f
JB		 9772 ? i.base_reg->reg_type.bitfield.dword
9773 : i.base_reg->reg_type.bitfield.word)))
be05d201
L		 9774 goto bad_address;
9775
fc0763e6
JB		 9776 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9777 operand_string,
9778 intel_syntax ? '[' : '(',
9779 register_prefix,
be05d201 9780 expected_reg->reg_name,
fc0763e6 9781 intel_syntax ? ']' : ')');
be05d201 9782 return 1;
fc0763e6 9783 }
be05d201
L		 9784 else
9785 return 1;
9786
9787bad_address:
9788 as_bad (_("`%s' is not a valid %s expression"),
9789 operand_string, kind);
9790 return 0;
3e73aa7c
JH		 9791 }
9792 else
9793 {
be05d201
L		 9794 if (addr_mode != CODE_16BIT)
9795 {
9796 /* 32-bit/64-bit checks. */
9797 if ((i.base_reg
e968fc9b
JB		 9798 && ((addr_mode == CODE_64BIT
9799 ? !i.base_reg->reg_type.bitfield.qword
9800 : !i.base_reg->reg_type.bitfield.dword)
9801 || (i.index_reg && i.base_reg->reg_num == RegIP)
9802 || i.base_reg->reg_num == RegIZ))
be05d201 9803 || (i.index_reg
1b54b8d7
JB		 9804 && !i.index_reg->reg_type.bitfield.xmmword
9805 && !i.index_reg->reg_type.bitfield.ymmword
9806 && !i.index_reg->reg_type.bitfield.zmmword
be05d201 9807 && ((addr_mode == CODE_64BIT
e968fc9b
JB		 9808 ? !i.index_reg->reg_type.bitfield.qword
9809 : !i.index_reg->reg_type.bitfield.dword)
be05d201
L		 9810 || !i.index_reg->reg_type.bitfield.baseindex)))
9811 goto bad_address;
8178be5b
JB		 9812
9813 /* bndmk, bndldx, and bndstx have special restrictions. */
9814 if (current_templates->start->base_opcode == 0xf30f1b
9815 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
9816 {
9817 /* They cannot use RIP-relative addressing. */
e968fc9b 9818 if (i.base_reg && i.base_reg->reg_num == RegIP)
8178be5b
JB		 9819 {
9820 as_bad (_("`%s' cannot be used here"), operand_string);
9821 return 0;
9822 }
9823
9824 /* bndldx and bndstx ignore their scale factor. */
9825 if (current_templates->start->base_opcode != 0xf30f1b
9826 && i.log2_scale_factor)
9827 as_warn (_("register scaling is being ignored here"));
9828 }
be05d201
L		 9829 }
9830 else
3e73aa7c 9831 {
be05d201 9832 /* 16-bit checks. */
3e73aa7c 9833 if ((i.base_reg
dc821c5f 9834 && (!i.base_reg->reg_type.bitfield.word
40fb9820 9835 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 9836 || (i.index_reg
dc821c5f 9837 && (!i.index_reg->reg_type.bitfield.word
40fb9820 9838 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 9839 || !(i.base_reg
9840 && i.base_reg->reg_num < 6
9841 && i.index_reg->reg_num >= 6
9842 && i.log2_scale_factor == 0))))
be05d201 9843 goto bad_address;
3e73aa7c
JH		 9844 }
9845 }
be05d201 9846 return 1;
24eab124 9847}
252b5132 9848
43234a1e
L		 9849/* Handle vector immediates. */
9850
9851static int
9852RC_SAE_immediate (const char *imm_start)
9853{
9854 unsigned int match_found, j;
9855 const char *pstr = imm_start;
9856 expressionS *exp;
9857
9858 if (*pstr != '{')
9859 return 0;
9860
9861 pstr++;
9862 match_found = 0;
9863 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
9864 {
9865 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
9866 {
9867 if (!i.rounding)
9868 {
9869 rc_op.type = RC_NamesTable[j].type;
9870 rc_op.operand = this_operand;
9871 i.rounding = &rc_op;
9872 }
9873 else
9874 {
9875 as_bad (_("duplicated `%s'"), imm_start);
9876 return 0;
9877 }
9878 pstr += RC_NamesTable[j].len;
9879 match_found = 1;
9880 break;
9881 }
9882 }
9883 if (!match_found)
9884 return 0;
9885
9886 if (*pstr++ != '}')
9887 {
9888 as_bad (_("Missing '}': '%s'"), imm_start);
9889 return 0;
9890 }
9891 /* RC/SAE immediate string should contain nothing more. */;
9892 if (*pstr != 0)
9893 {
9894 as_bad (_("Junk after '}': '%s'"), imm_start);
9895 return 0;
9896 }
9897
9898 exp = &im_expressions[i.imm_operands++];
9899 i.op[this_operand].imms = exp;
9900
9901 exp->X_op = O_constant;
9902 exp->X_add_number = 0;
9903 exp->X_add_symbol = (symbolS *) 0;
9904 exp->X_op_symbol = (symbolS *) 0;
9905
9906 i.types[this_operand].bitfield.imm8 = 1;
9907 return 1;
9908}
9909
8325cc63
JB		 9910/* Only string instructions can have a second memory operand, so
9911 reduce current_templates to just those if it contains any. */
9912static int
9913maybe_adjust_templates (void)
9914{
9915 const insn_template *t;
9916
9917 gas_assert (i.mem_operands == 1);
9918
9919 for (t = current_templates->start; t < current_templates->end; ++t)
9920 if (t->opcode_modifier.isstring)
9921 break;
9922
9923 if (t < current_templates->end)
9924 {
9925 static templates aux_templates;
9926 bfd_boolean recheck;
9927
9928 aux_templates.start = t;
9929 for (; t < current_templates->end; ++t)
9930 if (!t->opcode_modifier.isstring)
9931 break;
9932 aux_templates.end = t;
9933
9934 /* Determine whether to re-check the first memory operand. */
9935 recheck = (aux_templates.start != current_templates->start
9936 || t != current_templates->end);
9937
9938 current_templates = &aux_templates;
9939
9940 if (recheck)
9941 {
9942 i.mem_operands = 0;
9943 if (i.memop1_string != NULL
9944 && i386_index_check (i.memop1_string) == 0)
9945 return 0;
9946 i.mem_operands = 1;
9947 }
9948 }
9949
9950 return 1;
9951}
9952
fc0763e6 9953/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 9954 on error. */
252b5132 9955
252b5132 9956static int
a7619375 9957i386_att_operand (char *operand_string)
252b5132 9958{
af6bdddf
AM		 9959 const reg_entry *r;
9960 char *end_op;
24eab124 9961 char *op_string = operand_string;
252b5132 9962
24eab124 9963 if (is_space_char (*op_string))
252b5132
RH		 9964 ++op_string;
9965
24eab124 9966 /* We check for an absolute prefix (differentiating,
47926f60 9967 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 9968 if (*op_string == ABSOLUTE_PREFIX)
9969 {
9970 ++op_string;
9971 if (is_space_char (*op_string))
9972 ++op_string;
40fb9820 9973 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 9974 }
252b5132 9975
47926f60 9976 /* Check if operand is a register. */
4d1bb795 9977 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 9978 {
40fb9820
L		 9979 i386_operand_type temp;
9980
24eab124
AM		 9981 /* Check for a segment override by searching for ':' after a
9982 segment register. */
9983 op_string = end_op;
9984 if (is_space_char (*op_string))
9985 ++op_string;
40fb9820
L		 9986 if (*op_string == ':'
9987 && (r->reg_type.bitfield.sreg2
9988 || r->reg_type.bitfield.sreg3))
24eab124
AM		 9989 {
9990 switch (r->reg_num)
9991 {
9992 case 0:
9993 i.seg[i.mem_operands] = &es;
9994 break;
9995 case 1:
9996 i.seg[i.mem_operands] = &cs;
9997 break;
9998 case 2:
9999 i.seg[i.mem_operands] = &ss;
10000 break;
10001 case 3:
10002 i.seg[i.mem_operands] = &ds;
10003 break;
10004 case 4:
10005 i.seg[i.mem_operands] = &fs;
10006 break;
10007 case 5:
10008 i.seg[i.mem_operands] = &gs;
10009 break;
10010 }
252b5132 10011
24eab124 10012 /* Skip the ':' and whitespace. */
252b5132
RH		 10013 ++op_string;
10014 if (is_space_char (*op_string))
24eab124 10015 ++op_string;
252b5132 10016
24eab124
AM		 10017 if (!is_digit_char (*op_string)
10018 && !is_identifier_char (*op_string)
10019 && *op_string != '('
10020 && *op_string != ABSOLUTE_PREFIX)
10021 {
10022 as_bad (_("bad memory operand `%s'"), op_string);
10023 return 0;
10024 }
47926f60 10025 /* Handle case of %es:*foo. */
24eab124
AM		 10026 if (*op_string == ABSOLUTE_PREFIX)
10027 {
10028 ++op_string;
10029 if (is_space_char (*op_string))
10030 ++op_string;
40fb9820 10031 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 10032 }
10033 goto do_memory_reference;
10034 }
43234a1e
L		 10035
10036 /* Handle vector operations. */
10037 if (*op_string == '{')
10038 {
10039 op_string = check_VecOperations (op_string, NULL);
10040 if (op_string == NULL)
10041 return 0;
10042 }
10043
24eab124
AM		 10044 if (*op_string)
10045 {
d0b47220 10046 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 10047 return 0;
10048 }
40fb9820
L		 10049 temp = r->reg_type;
10050 temp.bitfield.baseindex = 0;
c6fb90c8
L		 10051 i.types[this_operand] = operand_type_or (i.types[this_operand],
10052 temp);
7d5e4556 10053 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 10054 i.op[this_operand].regs = r;
24eab124
AM		 10055 i.reg_operands++;
10056 }
af6bdddf
AM		 10057 else if (*op_string == REGISTER_PREFIX)
10058 {
10059 as_bad (_("bad register name `%s'"), op_string);
10060 return 0;
10061 }
24eab124 10062 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 10063 {
24eab124 10064 ++op_string;
40fb9820 10065 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 10066 {
d0b47220 10067 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 10068 return 0;
10069 }
10070 if (!i386_immediate (op_string))
10071 return 0;
10072 }
43234a1e
L		 10073 else if (RC_SAE_immediate (operand_string))
10074 {
10075 /* If it is a RC or SAE immediate, do nothing. */
10076 ;
10077 }
24eab124
AM		 10078 else if (is_digit_char (*op_string)
10079 || is_identifier_char (*op_string)
d02603dc 10080 || *op_string == '"'
e5cb08ac 10081 || *op_string == '(')
24eab124 10082 {
47926f60 10083 /* This is a memory reference of some sort. */
af6bdddf 10084 char *base_string;
252b5132 10085
47926f60 10086 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 10087 char *displacement_string_start;
10088 char *displacement_string_end;
43234a1e 10089 char *vop_start;
252b5132 10090
24eab124 10091 do_memory_reference:
8325cc63
JB		 10092 if (i.mem_operands == 1 && !maybe_adjust_templates ())
10093 return 0;
24eab124 10094 if ((i.mem_operands == 1
40fb9820 10095 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 10096 || i.mem_operands == 2)
10097 {
10098 as_bad (_("too many memory references for `%s'"),
10099 current_templates->start->name);
10100 return 0;
10101 }
252b5132 10102
24eab124
AM		 10103 /* Check for base index form. We detect the base index form by
10104 looking for an ')' at the end of the operand, searching
10105 for the '(' matching it, and finding a REGISTER_PREFIX or ','
10106 after the '('. */
af6bdddf 10107 base_string = op_string + strlen (op_string);
c3332e24 10108
43234a1e
L		 10109 /* Handle vector operations. */
10110 vop_start = strchr (op_string, '{');
10111 if (vop_start && vop_start < base_string)
10112 {
10113 if (check_VecOperations (vop_start, base_string) == NULL)
10114 return 0;
10115 base_string = vop_start;
10116 }
10117
af6bdddf
AM		 10118 --base_string;
10119 if (is_space_char (*base_string))
10120 --base_string;
252b5132 10121
47926f60 10122 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 10123 displacement_string_start = op_string;
10124 displacement_string_end = base_string + 1;
252b5132 10125
24eab124
AM		 10126 if (*base_string == ')')
10127 {
af6bdddf 10128 char *temp_string;
24eab124
AM		 10129 unsigned int parens_balanced = 1;
10130 /* We've already checked that the number of left & right ()'s are
47926f60 10131 equal, so this loop will not be infinite. */
24eab124
AM		 10132 do
10133 {
10134 base_string--;
10135 if (*base_string == ')')
10136 parens_balanced++;
10137 if (*base_string == '(')
10138 parens_balanced--;
10139 }
10140 while (parens_balanced);
c3332e24 10141
af6bdddf 10142 temp_string = base_string;
c3332e24 10143
24eab124 10144 /* Skip past '(' and whitespace. */
252b5132
RH		 10145 ++base_string;
10146 if (is_space_char (*base_string))
24eab124 10147 ++base_string;
252b5132 10148
af6bdddf 10149 if (*base_string == ','
4eed87de
AM		 10150 || ((i.base_reg = parse_register (base_string, &end_op))
10151 != NULL))
252b5132 10152 {
af6bdddf 10153 displacement_string_end = temp_string;
252b5132 10154
40fb9820 10155 i.types[this_operand].bitfield.baseindex = 1;
252b5132 10156
af6bdddf 10157 if (i.base_reg)
24eab124 10158 {
24eab124
AM		 10159 base_string = end_op;
10160 if (is_space_char (*base_string))
10161 ++base_string;
af6bdddf
AM		 10162 }
10163
10164 /* There may be an index reg or scale factor here. */
10165 if (*base_string == ',')
10166 {
10167 ++base_string;
10168 if (is_space_char (*base_string))
10169 ++base_string;
10170
4eed87de
AM		 10171 if ((i.index_reg = parse_register (base_string, &end_op))
10172 != NULL)
24eab124 10173 {
af6bdddf 10174 base_string = end_op;
24eab124
AM		 10175 if (is_space_char (*base_string))
10176 ++base_string;
af6bdddf
AM		 10177 if (*base_string == ',')
10178 {
10179 ++base_string;
10180 if (is_space_char (*base_string))
10181 ++base_string;
10182 }
e5cb08ac 10183 else if (*base_string != ')')
af6bdddf 10184 {
4eed87de
AM		 10185 as_bad (_("expecting `,' or `)' "
10186 "after index register in `%s'"),
af6bdddf
AM		 10187 operand_string);
10188 return 0;
10189 }
24eab124 10190 }
af6bdddf 10191 else if (*base_string == REGISTER_PREFIX)
24eab124 10192 {
f76bf5e0
L		 10193 end_op = strchr (base_string, ',');
10194 if (end_op)
10195 *end_op = '\0';
af6bdddf 10196 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 10197 return 0;
10198 }
252b5132 10199
47926f60 10200 /* Check for scale factor. */
551c1ca1 10201 if (*base_string != ')')
af6bdddf 10202 {
551c1ca1
AM		 10203 char *end_scale = i386_scale (base_string);
10204
10205 if (!end_scale)
af6bdddf 10206 return 0;
24eab124 10207
551c1ca1 10208 base_string = end_scale;
af6bdddf
AM		 10209 if (is_space_char (*base_string))
10210 ++base_string;
10211 if (*base_string != ')')
10212 {
4eed87de
AM		 10213 as_bad (_("expecting `)' "
10214 "after scale factor in `%s'"),
af6bdddf
AM		 10215 operand_string);
10216 return 0;
10217 }
10218 }
10219 else if (!i.index_reg)
24eab124 10220 {
4eed87de
AM		 10221 as_bad (_("expecting index register or scale factor "
10222 "after `,'; got '%c'"),
af6bdddf 10223 *base_string);
24eab124
AM		 10224 return 0;
10225 }
10226 }
af6bdddf 10227 else if (*base_string != ')')
24eab124 10228 {
4eed87de
AM		 10229 as_bad (_("expecting `,' or `)' "
10230 "after base register in `%s'"),
af6bdddf 10231 operand_string);
24eab124
AM		 10232 return 0;
10233 }
c3332e24 10234 }
af6bdddf 10235 else if (*base_string == REGISTER_PREFIX)
c3332e24 10236 {
f76bf5e0
L		 10237 end_op = strchr (base_string, ',');
10238 if (end_op)
10239 *end_op = '\0';
af6bdddf 10240 as_bad (_("bad register name `%s'"), base_string);
24eab124 10241 return 0;
c3332e24 10242 }
24eab124
AM		 10243 }
10244
10245 /* If there's an expression beginning the operand, parse it,
10246 assuming displacement_string_start and
10247 displacement_string_end are meaningful. */
10248 if (displacement_string_start != displacement_string_end)
10249 {
10250 if (!i386_displacement (displacement_string_start,
10251 displacement_string_end))
10252 return 0;
10253 }
10254
10255 /* Special case for (%dx) while doing input/output op. */
10256 if (i.base_reg
2fb5be8d 10257 && i.base_reg->reg_type.bitfield.inoutportreg
24eab124
AM		 10258 && i.index_reg == 0
10259 && i.log2_scale_factor == 0
10260 && i.seg[i.mem_operands] == 0
40fb9820 10261 && !operand_type_check (i.types[this_operand], disp))
24eab124 10262 {
2fb5be8d 10263 i.types[this_operand] = i.base_reg->reg_type;
24eab124
AM		 10264 return 1;
10265 }
10266
eecb386c
AM		 10267 if (i386_index_check (operand_string) == 0)
10268 return 0;
c48dadc9 10269 i.flags[this_operand] |= Operand_Mem;
8325cc63
JB		 10270 if (i.mem_operands == 0)
10271 i.memop1_string = xstrdup (operand_string);
24eab124
AM		 10272 i.mem_operands++;
10273 }
10274 else
ce8a8b2f
AM		 10275 {
10276 /* It's not a memory operand; argh! */
24eab124
AM		 10277 as_bad (_("invalid char %s beginning operand %d `%s'"),
10278 output_invalid (*op_string),
10279 this_operand + 1,
10280 op_string);
10281 return 0;
10282 }
47926f60 10283 return 1; /* Normal return. */
252b5132
RH		 10284}
10285\f
fa94de6b
RM		 10286/* Calculate the maximum variable size (i.e., excluding fr_fix)
10287 that an rs_machine_dependent frag may reach. */
10288
10289unsigned int
10290i386_frag_max_var (fragS *frag)
10291{
10292 /* The only relaxable frags are for jumps.
10293 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
10294 gas_assert (frag->fr_type == rs_machine_dependent);
10295 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
10296}
10297
b084df0b
L		 10298#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10299static int
8dcea932 10300elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
b084df0b
L		 10301{
10302 /* STT_GNU_IFUNC symbol must go through PLT. */
10303 if ((symbol_get_bfdsym (fr_symbol)->flags
10304 & BSF_GNU_INDIRECT_FUNCTION) != 0)
10305 return 0;
10306
10307 if (!S_IS_EXTERNAL (fr_symbol))
10308 /* Symbol may be weak or local. */
10309 return !S_IS_WEAK (fr_symbol);
10310
8dcea932
L		 10311 /* Global symbols with non-default visibility can't be preempted. */
10312 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
10313 return 1;
10314
10315 if (fr_var != NO_RELOC)
10316 switch ((enum bfd_reloc_code_real) fr_var)
10317 {
10318 case BFD_RELOC_386_PLT32:
10319 case BFD_RELOC_X86_64_PLT32:
33eaf5de 10320 /* Symbol with PLT relocation may be preempted. */
8dcea932
L		 10321 return 0;
10322 default:
10323 abort ();
10324 }
10325
b084df0b
L		 10326 /* Global symbols with default visibility in a shared library may be
10327 preempted by another definition. */
8dcea932 10328 return !shared;
b084df0b
L		 10329}
10330#endif
10331
ee7fcc42
AM		 10332/* md_estimate_size_before_relax()
10333
10334 Called just before relax() for rs_machine_dependent frags. The x86
10335 assembler uses these frags to handle variable size jump
10336 instructions.
10337
10338 Any symbol that is now undefined will not become defined.
10339 Return the correct fr_subtype in the frag.
10340 Return the initial "guess for variable size of frag" to caller.
10341 The guess is actually the growth beyond the fixed part. Whatever
10342 we do to grow the fixed or variable part contributes to our
10343 returned value. */
10344
252b5132 10345int
7016a5d5 10346md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 10347{
252b5132 10348 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 10349 check for un-relaxable symbols. On an ELF system, we can't relax
10350 an externally visible symbol, because it may be overridden by a
10351 shared library. */
10352 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 10353#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 10354 || (IS_ELF
8dcea932
L		 10355 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
10356 fragP->fr_var))
fbeb56a4
DK		 10357#endif
10358#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 10359 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 10360 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 10361#endif
10362 )
252b5132 10363 {
b98ef147
AM		 10364 /* Symbol is undefined in this segment, or we need to keep a
10365 reloc so that weak symbols can be overridden. */
10366 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 10367 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 10368 unsigned char *opcode;
10369 int old_fr_fix;
f6af82bd 10370
ee7fcc42 10371 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 10372 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 10373 else if (size == 2)
f6af82bd 10374 reloc_type = BFD_RELOC_16_PCREL;
bd7ab16b
L		 10375#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10376 else if (need_plt32_p (fragP->fr_symbol))
10377 reloc_type = BFD_RELOC_X86_64_PLT32;
10378#endif
f6af82bd
AM		 10379 else
10380 reloc_type = BFD_RELOC_32_PCREL;
252b5132 10381
ee7fcc42
AM		 10382 old_fr_fix = fragP->fr_fix;
10383 opcode = (unsigned char *) fragP->fr_opcode;
10384
fddf5b5b 10385 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 10386 {
fddf5b5b
AM		 10387 case UNCOND_JUMP:
10388 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 10389 opcode[0] = 0xe9;
252b5132 10390 fragP->fr_fix += size;
062cd5e7
AS		 10391 fix_new (fragP, old_fr_fix, size,
10392 fragP->fr_symbol,
10393 fragP->fr_offset, 1,
10394 reloc_type);
252b5132
RH		 10395 break;
10396
fddf5b5b 10397 case COND_JUMP86:
412167cb
AM		 10398 if (size == 2
10399 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 10400 {
10401 /* Negate the condition, and branch past an
10402 unconditional jump. */
10403 opcode[0] ^= 1;
10404 opcode[1] = 3;
10405 /* Insert an unconditional jump. */
10406 opcode[2] = 0xe9;
10407 /* We added two extra opcode bytes, and have a two byte
10408 offset. */
10409 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 10410 fix_new (fragP, old_fr_fix + 2, 2,
10411 fragP->fr_symbol,
10412 fragP->fr_offset, 1,
10413 reloc_type);
fddf5b5b
AM		 10414 break;
10415 }
10416 /* Fall through. */
10417
10418 case COND_JUMP:
412167cb
AM		 10419 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
10420 {
3e02c1cc
AM		 10421 fixS *fixP;
10422
412167cb 10423 fragP->fr_fix += 1;
3e02c1cc
AM		 10424 fixP = fix_new (fragP, old_fr_fix, 1,
10425 fragP->fr_symbol,
10426 fragP->fr_offset, 1,
10427 BFD_RELOC_8_PCREL);
10428 fixP->fx_signed = 1;
412167cb
AM		 10429 break;
10430 }
93c2a809 10431
24eab124 10432 /* This changes the byte-displacement jump 0x7N
fddf5b5b 10433 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 10434 opcode[1] = opcode[0] + 0x10;
f6af82bd 10435 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 10436 /* We've added an opcode byte. */
10437 fragP->fr_fix += 1 + size;
062cd5e7
AS		 10438 fix_new (fragP, old_fr_fix + 1, size,
10439 fragP->fr_symbol,
10440 fragP->fr_offset, 1,
10441 reloc_type);
252b5132 10442 break;
fddf5b5b
AM		 10443
10444 default:
10445 BAD_CASE (fragP->fr_subtype);
10446 break;
252b5132
RH		 10447 }
10448 frag_wane (fragP);
ee7fcc42 10449 return fragP->fr_fix - old_fr_fix;
252b5132 10450 }
93c2a809 10451
93c2a809
AM		 10452 /* Guess size depending on current relax state. Initially the relax
10453 state will correspond to a short jump and we return 1, because
10454 the variable part of the frag (the branch offset) is one byte
10455 long. However, we can relax a section more than once and in that
10456 case we must either set fr_subtype back to the unrelaxed state,
10457 or return the value for the appropriate branch. */
10458 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 10459}
10460
47926f60
KH		 10461/* Called after relax() is finished.
10462
10463 In: Address of frag.
10464 fr_type == rs_machine_dependent.
10465 fr_subtype is what the address relaxed to.
10466
10467 Out: Any fixSs and constants are set up.
10468 Caller will turn frag into a ".space 0". */
10469
252b5132 10470void
7016a5d5
TG		 10471md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
10472 fragS *fragP)
252b5132 10473{
29b0f896 10474 unsigned char *opcode;
252b5132 10475 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 10476 offsetT target_address;
10477 offsetT opcode_address;
252b5132 10478 unsigned int extension = 0;
847f7ad4 10479 offsetT displacement_from_opcode_start;
252b5132
RH		 10480
10481 opcode = (unsigned char *) fragP->fr_opcode;
10482
47926f60 10483 /* Address we want to reach in file space. */
252b5132 10484 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 10485
47926f60 10486 /* Address opcode resides at in file space. */
252b5132
RH		 10487 opcode_address = fragP->fr_address + fragP->fr_fix;
10488
47926f60 10489 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 10490 displacement_from_opcode_start = target_address - opcode_address;
10491
fddf5b5b 10492 if ((fragP->fr_subtype & BIG) == 0)
252b5132 10493 {
47926f60
KH		 10494 /* Don't have to change opcode. */
10495 extension = 1; /* 1 opcode + 1 displacement */
252b5132 10496 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 10497 }
10498 else
10499 {
10500 if (no_cond_jump_promotion
10501 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 10502 as_warn_where (fragP->fr_file, fragP->fr_line,
10503 _("long jump required"));
252b5132 10504
fddf5b5b
AM		 10505 switch (fragP->fr_subtype)
10506 {
10507 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
10508 extension = 4; /* 1 opcode + 4 displacement */
10509 opcode[0] = 0xe9;
10510 where_to_put_displacement = &opcode[1];
10511 break;
252b5132 10512
fddf5b5b
AM		 10513 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
10514 extension = 2; /* 1 opcode + 2 displacement */
10515 opcode[0] = 0xe9;
10516 where_to_put_displacement = &opcode[1];
10517 break;
252b5132 10518
fddf5b5b
AM		 10519 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
10520 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
10521 extension = 5; /* 2 opcode + 4 displacement */
10522 opcode[1] = opcode[0] + 0x10;
10523 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
10524 where_to_put_displacement = &opcode[2];
10525 break;
252b5132 10526
fddf5b5b
AM		 10527 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
10528 extension = 3; /* 2 opcode + 2 displacement */
10529 opcode[1] = opcode[0] + 0x10;
10530 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
10531 where_to_put_displacement = &opcode[2];
10532 break;
252b5132 10533
fddf5b5b
AM		 10534 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
10535 extension = 4;
10536 opcode[0] ^= 1;
10537 opcode[1] = 3;
10538 opcode[2] = 0xe9;
10539 where_to_put_displacement = &opcode[3];
10540 break;
10541
10542 default:
10543 BAD_CASE (fragP->fr_subtype);
10544 break;
10545 }
252b5132 10546 }
fddf5b5b 10547
7b81dfbb
AJ		 10548 /* If size if less then four we are sure that the operand fits,
10549 but if it's 4, then it could be that the displacement is larger
10550 then -/+ 2GB. */
10551 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
10552 && object_64bit
10553 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 10554 + ((addressT) 1 << 31))
10555 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 10556 {
10557 as_bad_where (fragP->fr_file, fragP->fr_line,
10558 _("jump target out of range"));
10559 /* Make us emit 0. */
10560 displacement_from_opcode_start = extension;
10561 }
47926f60 10562 /* Now put displacement after opcode. */
252b5132
RH		 10563 md_number_to_chars ((char *) where_to_put_displacement,
10564 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 10565 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 10566 fragP->fr_fix += extension;
10567}
10568\f
7016a5d5 10569/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 10570 by our caller that we have all the info we need to fix it up.
10571
7016a5d5
TG		 10572 Parameter valP is the pointer to the value of the bits.
10573
252b5132
RH		 10574 On the 386, immediates, displacements, and data pointers are all in
10575 the same (little-endian) format, so we don't need to care about which
10576 we are handling. */
10577
94f592af 10578void
7016a5d5 10579md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 10580{
94f592af 10581 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 10582 valueT value = *valP;
252b5132 10583
f86103b7 10584#if !defined (TE_Mach)
93382f6d
AM		 10585 if (fixP->fx_pcrel)
10586 {
10587 switch (fixP->fx_r_type)
10588 {
5865bb77
ILT		 10589 default:
10590 break;
10591
d6ab8113
JB		 10592 case BFD_RELOC_64:
10593 fixP->fx_r_type = BFD_RELOC_64_PCREL;
10594 break;
93382f6d 10595 case BFD_RELOC_32:
ae8887b5 10596 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 10597 fixP->fx_r_type = BFD_RELOC_32_PCREL;
10598 break;
10599 case BFD_RELOC_16:
10600 fixP->fx_r_type = BFD_RELOC_16_PCREL;
10601 break;
10602 case BFD_RELOC_8:
10603 fixP->fx_r_type = BFD_RELOC_8_PCREL;
10604 break;
10605 }
10606 }
252b5132 10607
a161fe53 10608 if (fixP->fx_addsy != NULL
31312f95 10609 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 10610 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95 10611 || fixP->fx_r_type == BFD_RELOC_16_PCREL
d258b828 10612 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
31312f95 10613 && !use_rela_relocations)
252b5132 10614 {
31312f95
AM		 10615 /* This is a hack. There should be a better way to handle this.
10616 This covers for the fact that bfd_install_relocation will
10617 subtract the current location (for partial_inplace, PC relative
10618 relocations); see more below. */
252b5132 10619#ifndef OBJ_AOUT
718ddfc0 10620 if (IS_ELF
252b5132
RH		 10621#ifdef TE_PE
10622 || OUTPUT_FLAVOR == bfd_target_coff_flavour
10623#endif
10624 )
10625 value += fixP->fx_where + fixP->fx_frag->fr_address;
10626#endif
10627#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 10628 if (IS_ELF)
252b5132 10629 {
6539b54b 10630 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 10631
6539b54b 10632 if ((sym_seg == seg
2f66722d 10633 || (symbol_section_p (fixP->fx_addsy)
6539b54b 10634 && sym_seg != absolute_section))
af65af87 10635 && !generic_force_reloc (fixP))
2f66722d
AM		 10636 {
10637 /* Yes, we add the values in twice. This is because
6539b54b
AM		 10638 bfd_install_relocation subtracts them out again. I think
10639 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 10640 it. FIXME. */
10641 value += fixP->fx_where + fixP->fx_frag->fr_address;
10642 }
252b5132
RH		 10643 }
10644#endif
10645#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 10646 /* For some reason, the PE format does not store a
10647 section address offset for a PC relative symbol. */
10648 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 10649 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 10650 value += md_pcrel_from (fixP);
10651#endif
10652 }
fbeb56a4 10653#if defined (OBJ_COFF) && defined (TE_PE)
f01c1a09
NC		 10654 if (fixP->fx_addsy != NULL
10655 && S_IS_WEAK (fixP->fx_addsy)
10656 /* PR 16858: Do not modify weak function references. */
10657 && ! fixP->fx_pcrel)
fbeb56a4 10658 {
296a8689
NC		 10659#if !defined (TE_PEP)
10660 /* For x86 PE weak function symbols are neither PC-relative
10661 nor do they set S_IS_FUNCTION. So the only reliable way
10662 to detect them is to check the flags of their containing
10663 section. */
10664 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
10665 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
10666 ;
10667 else
10668#endif
fbeb56a4
DK		 10669 value -= S_GET_VALUE (fixP->fx_addsy);
10670 }
10671#endif
252b5132
RH		 10672
10673 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 10674 and we must not disappoint it. */
252b5132 10675#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 10676 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 10677 switch (fixP->fx_r_type)
10678 {
10679 case BFD_RELOC_386_PLT32:
3e73aa7c 10680 case BFD_RELOC_X86_64_PLT32:
b9519cfe
L		 10681 /* Make the jump instruction point to the address of the operand.
10682 At runtime we merely add the offset to the actual PLT entry.
10683 NB: Subtract the offset size only for jump instructions. */
10684 if (fixP->fx_pcrel)
10685 value = -4;
47926f60 10686 break;
31312f95 10687
13ae64f3
JJ		 10688 case BFD_RELOC_386_TLS_GD:
10689 case BFD_RELOC_386_TLS_LDM:
13ae64f3 10690 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 10691 case BFD_RELOC_386_TLS_IE:
10692 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 10693 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 10694 case BFD_RELOC_X86_64_TLSGD:
10695 case BFD_RELOC_X86_64_TLSLD:
10696 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 10697 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 10698 value = 0; /* Fully resolved at runtime. No addend. */
10699 /* Fallthrough */
10700 case BFD_RELOC_386_TLS_LE:
10701 case BFD_RELOC_386_TLS_LDO_32:
10702 case BFD_RELOC_386_TLS_LE_32:
10703 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 10704 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 10705 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 10706 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 10707 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10708 break;
10709
67a4f2b7
AO		 10710 case BFD_RELOC_386_TLS_DESC_CALL:
10711 case BFD_RELOC_X86_64_TLSDESC_CALL:
10712 value = 0; /* Fully resolved at runtime. No addend. */
10713 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10714 fixP->fx_done = 0;
10715 return;
10716
47926f60
KH		 10717 case BFD_RELOC_VTABLE_INHERIT:
10718 case BFD_RELOC_VTABLE_ENTRY:
10719 fixP->fx_done = 0;
94f592af 10720 return;
47926f60
KH		 10721
10722 default:
10723 break;
10724 }
10725#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 10726 *valP = value;
f86103b7 10727#endif /* !defined (TE_Mach) */
3e73aa7c 10728
3e73aa7c 10729 /* Are we finished with this relocation now? */
c6682705 10730 if (fixP->fx_addsy == NULL)
3e73aa7c 10731 fixP->fx_done = 1;
fbeb56a4
DK		 10732#if defined (OBJ_COFF) && defined (TE_PE)
10733 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
10734 {
10735 fixP->fx_done = 0;
10736 /* Remember value for tc_gen_reloc. */
10737 fixP->fx_addnumber = value;
10738 /* Clear out the frag for now. */
10739 value = 0;
10740 }
10741#endif
3e73aa7c
JH		 10742 else if (use_rela_relocations)
10743 {
10744 fixP->fx_no_overflow = 1;
062cd5e7
AS		 10745 /* Remember value for tc_gen_reloc. */
10746 fixP->fx_addnumber = value;
3e73aa7c
JH		 10747 value = 0;
10748 }
f86103b7 10749
94f592af 10750 md_number_to_chars (p, value, fixP->fx_size);
252b5132 10751}
252b5132 10752\f
6d4af3c2 10753const char *
499ac353 10754md_atof (int type, char *litP, int *sizeP)
252b5132 10755{
499ac353
NC		 10756 /* This outputs the LITTLENUMs in REVERSE order;
10757 in accord with the bigendian 386. */
10758 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 10759}
10760\f
2d545b82 10761static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 10762
252b5132 10763static char *
e3bb37b5 10764output_invalid (int c)
252b5132 10765{
3882b010 10766 if (ISPRINT (c))
f9f21a03
L		 10767 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10768 "'%c'", c);
252b5132 10769 else
f9f21a03 10770 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 10771 "(0x%x)", (unsigned char) c);
252b5132
RH		 10772 return output_invalid_buf;
10773}
10774
af6bdddf 10775/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 10776
10777static const reg_entry *
4d1bb795 10778parse_real_register (char *reg_string, char **end_op)
252b5132 10779{
af6bdddf
AM		 10780 char *s = reg_string;
10781 char *p;
252b5132
RH		 10782 char reg_name_given[MAX_REG_NAME_SIZE + 1];
10783 const reg_entry *r;
10784
10785 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10786 if (*s == REGISTER_PREFIX)
10787 ++s;
10788
10789 if (is_space_char (*s))
10790 ++s;
10791
10792 p = reg_name_given;
af6bdddf 10793 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 10794 {
10795 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 10796 return (const reg_entry *) NULL;
10797 s++;
252b5132
RH		 10798 }
10799
6588847e
DN		 10800 /* For naked regs, make sure that we are not dealing with an identifier.
10801 This prevents confusing an identifier like `eax_var' with register
10802 `eax'. */
10803 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
10804 return (const reg_entry *) NULL;
10805
af6bdddf 10806 *end_op = s;
252b5132
RH		 10807
10808 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
10809
5f47d35b 10810 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 10811 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 10812 {
0e0eea78
JB		 10813 if (!cpu_arch_flags.bitfield.cpu8087
10814 && !cpu_arch_flags.bitfield.cpu287
10815 && !cpu_arch_flags.bitfield.cpu387)
10816 return (const reg_entry *) NULL;
10817
5f47d35b
AM		 10818 if (is_space_char (*s))
10819 ++s;
10820 if (*s == '(')
10821 {
af6bdddf 10822 ++s;
5f47d35b
AM		 10823 if (is_space_char (*s))
10824 ++s;
10825 if (*s >= '0' && *s <= '7')
10826 {
db557034 10827 int fpr = *s - '0';
af6bdddf 10828 ++s;
5f47d35b
AM		 10829 if (is_space_char (*s))
10830 ++s;
10831 if (*s == ')')
10832 {
10833 *end_op = s + 1;
1e9cc1c2 10834 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 10835 know (r);
10836 return r + fpr;
5f47d35b 10837 }
5f47d35b 10838 }
47926f60 10839 /* We have "%st(" then garbage. */
5f47d35b
AM		 10840 return (const reg_entry *) NULL;
10841 }
10842 }
10843
a60de03c
JB		 10844 if (r == NULL || allow_pseudo_reg)
10845 return r;
10846
0dfbf9d7 10847 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 10848 return (const reg_entry *) NULL;
10849
dc821c5f 10850 if ((r->reg_type.bitfield.dword
192dc9c6
JB		 10851 || r->reg_type.bitfield.sreg3
10852 || r->reg_type.bitfield.control
10853 || r->reg_type.bitfield.debug
10854 || r->reg_type.bitfield.test)
10855 && !cpu_arch_flags.bitfield.cpui386)
10856 return (const reg_entry *) NULL;
10857
6e041cf4 10858 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
192dc9c6
JB		 10859 return (const reg_entry *) NULL;
10860
6e041cf4
JB		 10861 if (!cpu_arch_flags.bitfield.cpuavx512f)
10862 {
10863 if (r->reg_type.bitfield.zmmword || r->reg_type.bitfield.regmask)
10864 return (const reg_entry *) NULL;
40f12533 10865
6e041cf4
JB		 10866 if (!cpu_arch_flags.bitfield.cpuavx)
10867 {
10868 if (r->reg_type.bitfield.ymmword)
10869 return (const reg_entry *) NULL;
1848e567 10870
6e041cf4
JB		 10871 if (!cpu_arch_flags.bitfield.cpusse && r->reg_type.bitfield.xmmword)
10872 return (const reg_entry *) NULL;
10873 }
10874 }
43234a1e 10875
1adf7f56
JB		 10876 if (r->reg_type.bitfield.regbnd && !cpu_arch_flags.bitfield.cpumpx)
10877 return (const reg_entry *) NULL;
10878
db51cc60 10879 /* Don't allow fake index register unless allow_index_reg isn't 0. */
e968fc9b 10880 if (!allow_index_reg && r->reg_num == RegIZ)
db51cc60
L		 10881 return (const reg_entry *) NULL;
10882
1d3f8286
JB		 10883 /* Upper 16 vector registers are only available with VREX in 64bit
10884 mode, and require EVEX encoding. */
10885 if (r->reg_flags & RegVRex)
43234a1e 10886 {
e951d5ca 10887 if (!cpu_arch_flags.bitfield.cpuavx512f
43234a1e
L		 10888 || flag_code != CODE_64BIT)
10889 return (const reg_entry *) NULL;
1d3f8286
JB		 10890
10891 i.vec_encoding = vex_encoding_evex;
43234a1e
L		 10892 }
10893
4787f4a5
JB		 10894 if (((r->reg_flags & (RegRex64 | RegRex)) || r->reg_type.bitfield.qword)
10895 && (!cpu_arch_flags.bitfield.cpulm || !r->reg_type.bitfield.control)
1ae00879 10896 && flag_code != CODE_64BIT)
20f0a1fc 10897 return (const reg_entry *) NULL;
1ae00879 10898
b7240065
JB		 10899 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
10900 return (const reg_entry *) NULL;
10901
252b5132
RH		 10902 return r;
10903}
4d1bb795
JB		 10904
10905/* REG_STRING starts *before* REGISTER_PREFIX. */
10906
10907static const reg_entry *
10908parse_register (char *reg_string, char **end_op)
10909{
10910 const reg_entry *r;
10911
10912 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
10913 r = parse_real_register (reg_string, end_op);
10914 else
10915 r = NULL;
10916 if (!r)
10917 {
10918 char *save = input_line_pointer;
10919 char c;
10920 symbolS *symbolP;
10921
10922 input_line_pointer = reg_string;
d02603dc 10923 c = get_symbol_name (&reg_string);
4d1bb795
JB		 10924 symbolP = symbol_find (reg_string);
10925 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
10926 {
10927 const expressionS *e = symbol_get_value_expression (symbolP);
10928
0398aac5 10929 know (e->X_op == O_register);
4eed87de 10930 know (e->X_add_number >= 0
c3fe08fa 10931 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795 10932 r = i386_regtab + e->X_add_number;
d3bb6b49 10933 if ((r->reg_flags & RegVRex))
86fa6981 10934 i.vec_encoding = vex_encoding_evex;
4d1bb795
JB		 10935 *end_op = input_line_pointer;
10936 }
10937 *input_line_pointer = c;
10938 input_line_pointer = save;
10939 }
10940 return r;
10941}
10942
10943int
10944i386_parse_name (char *name, expressionS *e, char *nextcharP)
10945{
10946 const reg_entry *r;
10947 char *end = input_line_pointer;
10948
10949 *end = *nextcharP;
10950 r = parse_register (name, &input_line_pointer);
10951 if (r && end <= input_line_pointer)
10952 {
10953 *nextcharP = *input_line_pointer;
10954 *input_line_pointer = 0;
10955 e->X_op = O_register;
10956 e->X_add_number = r - i386_regtab;
10957 return 1;
10958 }
10959 input_line_pointer = end;
10960 *end = 0;
ee86248c 10961 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 10962}
10963
10964void
10965md_operand (expressionS *e)
10966{
ee86248c
JB		 10967 char *end;
10968 const reg_entry *r;
4d1bb795 10969
ee86248c
JB		 10970 switch (*input_line_pointer)
10971 {
10972 case REGISTER_PREFIX:
10973 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 10974 if (r)
10975 {
10976 e->X_op = O_register;
10977 e->X_add_number = r - i386_regtab;
10978 input_line_pointer = end;
10979 }
ee86248c
JB		 10980 break;
10981
10982 case '[':
9c2799c2 10983 gas_assert (intel_syntax);
ee86248c
JB		 10984 end = input_line_pointer++;
10985 expression (e);
10986 if (*input_line_pointer == ']')
10987 {
10988 ++input_line_pointer;
10989 e->X_op_symbol = make_expr_symbol (e);
10990 e->X_add_symbol = NULL;
10991 e->X_add_number = 0;
10992 e->X_op = O_index;
10993 }
10994 else
10995 {
10996 e->X_op = O_absent;
10997 input_line_pointer = end;
10998 }
10999 break;
4d1bb795
JB		 11000 }
11001}
11002
252b5132 11003\f
4cc782b5 11004#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
b6f8c7c4 11005const char *md_shortopts = "kVQ:sqnO::";
252b5132 11006#else
b6f8c7c4 11007const char *md_shortopts = "qnO::";
252b5132 11008#endif
6e0b89ee 11009
3e73aa7c 11010#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 11011#define OPTION_64 (OPTION_MD_BASE + 1)
11012#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 11013#define OPTION_MARCH (OPTION_MD_BASE + 3)
11014#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 11015#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
11016#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
11017#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
11018#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
bd5dea88 11019#define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
c0f3af97 11020#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 11021#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 11022#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
11023#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
11024#define OPTION_X32 (OPTION_MD_BASE + 14)
7e8b059b 11025#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
43234a1e
L		 11026#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
11027#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
167ad85b 11028#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
d1982f93 11029#define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
d3d3c6db 11030#define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
8dcea932 11031#define OPTION_MSHARED (OPTION_MD_BASE + 21)
5db04b09
L		 11032#define OPTION_MAMD64 (OPTION_MD_BASE + 22)
11033#define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
e4e00185 11034#define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
b4a3a7b4 11035#define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
03751133 11036#define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
b3b91714 11037
99ad8390
NC		 11038struct option md_longopts[] =
11039{
3e73aa7c 11040 {"32", no_argument, NULL, OPTION_32},
321098a5 11041#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 11042 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 11043 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 11044#endif
11045#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 11046 {"x32", no_argument, NULL, OPTION_X32},
8dcea932 11047 {"mshared", no_argument, NULL, OPTION_MSHARED},
b4a3a7b4 11048 {"mx86-used-note", required_argument, NULL, OPTION_X86_USED_NOTE},
6e0b89ee 11049#endif
b3b91714 11050 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 11051 {"march", required_argument, NULL, OPTION_MARCH},
11052 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 11053 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
11054 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
11055 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
11056 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
c0f3af97 11057 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 11058 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 11059 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 11060 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
03751133 11061 {"mvexwig", required_argument, NULL, OPTION_MVEXWIG},
7e8b059b 11062 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
43234a1e
L		 11063 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
11064 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
167ad85b
TG		 11065# if defined (TE_PE) || defined (TE_PEP)
11066 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
11067#endif
d1982f93 11068 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
e4e00185 11069 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
0cb4071e 11070 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
d3d3c6db 11071 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
5db04b09
L		 11072 {"mamd64", no_argument, NULL, OPTION_MAMD64},
11073 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
252b5132
RH		 11074 {NULL, no_argument, NULL, 0}
11075};
11076size_t md_longopts_size = sizeof (md_longopts);
11077
11078int
17b9d67d 11079md_parse_option (int c, const char *arg)
252b5132 11080{
91d6fa6a 11081 unsigned int j;
293f5f65 11082 char *arch, *next, *saved;
9103f4f4 11083
252b5132
RH		 11084 switch (c)
11085 {
12b55ccc
L		 11086 case 'n':
11087 optimize_align_code = 0;
11088 break;
11089
a38cf1db
AM		 11090 case 'q':
11091 quiet_warnings = 1;
252b5132
RH		 11092 break;
11093
11094#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 11095 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
11096 should be emitted or not. FIXME: Not implemented. */
11097 case 'Q':
252b5132
RH		 11098 break;
11099
11100 /* -V: SVR4 argument to print version ID. */
11101 case 'V':
11102 print_version_id ();
11103 break;
11104
a38cf1db
AM		 11105 /* -k: Ignore for FreeBSD compatibility. */
11106 case 'k':
252b5132 11107 break;
4cc782b5
ILT		 11108
11109 case 's':
11110 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 11111 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 11112 break;
8dcea932
L		 11113
11114 case OPTION_MSHARED:
11115 shared = 1;
11116 break;
b4a3a7b4
L		 11117
11118 case OPTION_X86_USED_NOTE:
11119 if (strcasecmp (arg, "yes") == 0)
11120 x86_used_note = 1;
11121 else if (strcasecmp (arg, "no") == 0)
11122 x86_used_note = 0;
11123 else
11124 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg);
11125 break;
11126
11127
99ad8390 11128#endif
321098a5 11129#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 11130 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 11131 case OPTION_64:
11132 {
11133 const char **list, **l;
11134
3e73aa7c
JH		 11135 list = bfd_target_list ();
11136 for (l = list; *l != NULL; l++)
8620418b 11137 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 11138 || strcmp (*l, "coff-x86-64") == 0
11139 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 11140 || strcmp (*l, "pei-x86-64") == 0
11141 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 11142 {
11143 default_arch = "x86_64";
11144 break;
11145 }
3e73aa7c 11146 if (*l == NULL)
2b5d6a91 11147 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 11148 free (list);
11149 }
11150 break;
11151#endif
252b5132 11152
351f65ca 11153#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 11154 case OPTION_X32:
351f65ca
L		 11155 if (IS_ELF)
11156 {
11157 const char **list, **l;
11158
11159 list = bfd_target_list ();
11160 for (l = list; *l != NULL; l++)
11161 if (CONST_STRNEQ (*l, "elf32-x86-64"))
11162 {
11163 default_arch = "x86_64:32";
11164 break;
11165 }
11166 if (*l == NULL)
2b5d6a91 11167 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 11168 free (list);
11169 }
11170 else
11171 as_fatal (_("32bit x86_64 is only supported for ELF"));
11172 break;
11173#endif
11174
6e0b89ee
AM		 11175 case OPTION_32:
11176 default_arch = "i386";
11177 break;
11178
b3b91714
AM		 11179 case OPTION_DIVIDE:
11180#ifdef SVR4_COMMENT_CHARS
11181 {
11182 char *n, *t;
11183 const char *s;
11184
add39d23 11185 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
b3b91714
AM		 11186 t = n;
11187 for (s = i386_comment_chars; *s != '\0'; s++)
11188 if (*s != '/')
11189 *t++ = *s;
11190 *t = '\0';
11191 i386_comment_chars = n;
11192 }
11193#endif
11194 break;
11195
9103f4f4 11196 case OPTION_MARCH:
293f5f65
L		 11197 saved = xstrdup (arg);
11198 arch = saved;
11199 /* Allow -march=+nosse. */
11200 if (*arch == '+')
11201 arch++;
6305a203 11202 do
9103f4f4 11203 {
6305a203 11204 if (*arch == '.')
2b5d6a91 11205 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 11206 next = strchr (arch, '+');
11207 if (next)
11208 *next++ = '\0';
91d6fa6a 11209 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 11210 {
91d6fa6a 11211 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 11212 {
6305a203 11213 /* Processor. */
1ded5609
JB		 11214 if (! cpu_arch[j].flags.bitfield.cpui386)
11215 continue;
11216
91d6fa6a 11217 cpu_arch_name = cpu_arch[j].name;
6305a203 11218 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 11219 cpu_arch_flags = cpu_arch[j].flags;
11220 cpu_arch_isa = cpu_arch[j].type;
11221 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 11222 if (!cpu_arch_tune_set)
11223 {
11224 cpu_arch_tune = cpu_arch_isa;
11225 cpu_arch_tune_flags = cpu_arch_isa_flags;
11226 }
11227 break;
11228 }
91d6fa6a
NC		 11229 else if (*cpu_arch [j].name == '.'
11230 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203 11231 {
33eaf5de 11232 /* ISA extension. */
6305a203 11233 i386_cpu_flags flags;
309d3373 11234
293f5f65
L		 11235 flags = cpu_flags_or (cpu_arch_flags,
11236 cpu_arch[j].flags);
81486035 11237
5b64d091 11238 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 11239 {
11240 if (cpu_sub_arch_name)
11241 {
11242 char *name = cpu_sub_arch_name;
11243 cpu_sub_arch_name = concat (name,
91d6fa6a 11244 cpu_arch[j].name,
1bf57e9f 11245 (const char *) NULL);
6305a203
L		 11246 free (name);
11247 }
11248 else
91d6fa6a 11249 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 11250 cpu_arch_flags = flags;
a586129e 11251 cpu_arch_isa_flags = flags;
6305a203 11252 }
0089dace
L		 11253 else
11254 cpu_arch_isa_flags
11255 = cpu_flags_or (cpu_arch_isa_flags,
11256 cpu_arch[j].flags);
6305a203 11257 break;
ccc9c027 11258 }
9103f4f4 11259 }
6305a203 11260
293f5f65
L		 11261 if (j >= ARRAY_SIZE (cpu_arch))
11262 {
33eaf5de 11263 /* Disable an ISA extension. */
293f5f65
L		 11264 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
11265 if (strcmp (arch, cpu_noarch [j].name) == 0)
11266 {
11267 i386_cpu_flags flags;
11268
11269 flags = cpu_flags_and_not (cpu_arch_flags,
11270 cpu_noarch[j].flags);
11271 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
11272 {
11273 if (cpu_sub_arch_name)
11274 {
11275 char *name = cpu_sub_arch_name;
11276 cpu_sub_arch_name = concat (arch,
11277 (const char *) NULL);
11278 free (name);
11279 }
11280 else
11281 cpu_sub_arch_name = xstrdup (arch);
11282 cpu_arch_flags = flags;
11283 cpu_arch_isa_flags = flags;
11284 }
11285 break;
11286 }
11287
11288 if (j >= ARRAY_SIZE (cpu_noarch))
11289 j = ARRAY_SIZE (cpu_arch);
11290 }
11291
91d6fa6a 11292 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 11293 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 11294
11295 arch = next;
9103f4f4 11296 }
293f5f65
L		 11297 while (next != NULL);
11298 free (saved);
9103f4f4
L		 11299 break;
11300
11301 case OPTION_MTUNE:
11302 if (*arg == '.')
2b5d6a91 11303 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 11304 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 11305 {
91d6fa6a 11306 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 11307 {
ccc9c027 11308 cpu_arch_tune_set = 1;
91d6fa6a
NC		 11309 cpu_arch_tune = cpu_arch [j].type;
11310 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 11311 break;
11312 }
11313 }
91d6fa6a 11314 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 11315 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 11316 break;
11317
1efbbeb4
L		 11318 case OPTION_MMNEMONIC:
11319 if (strcasecmp (arg, "att") == 0)
11320 intel_mnemonic = 0;
11321 else if (strcasecmp (arg, "intel") == 0)
11322 intel_mnemonic = 1;
11323 else
2b5d6a91 11324 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 11325 break;
11326
11327 case OPTION_MSYNTAX:
11328 if (strcasecmp (arg, "att") == 0)
11329 intel_syntax = 0;
11330 else if (strcasecmp (arg, "intel") == 0)
11331 intel_syntax = 1;
11332 else
2b5d6a91 11333 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 11334 break;
11335
11336 case OPTION_MINDEX_REG:
11337 allow_index_reg = 1;
11338 break;
11339
11340 case OPTION_MNAKED_REG:
11341 allow_naked_reg = 1;
11342 break;
11343
c0f3af97
L		 11344 case OPTION_MSSE2AVX:
11345 sse2avx = 1;
11346 break;
11347
daf50ae7
L		 11348 case OPTION_MSSE_CHECK:
11349 if (strcasecmp (arg, "error") == 0)
7bab8ab5 11350 sse_check = check_error;
daf50ae7 11351 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 11352 sse_check = check_warning;
daf50ae7 11353 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 11354 sse_check = check_none;
daf50ae7 11355 else
2b5d6a91 11356 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 11357 break;
11358
7bab8ab5
JB		 11359 case OPTION_MOPERAND_CHECK:
11360 if (strcasecmp (arg, "error") == 0)
11361 operand_check = check_error;
11362 else if (strcasecmp (arg, "warning") == 0)
11363 operand_check = check_warning;
11364 else if (strcasecmp (arg, "none") == 0)
11365 operand_check = check_none;
11366 else
11367 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
11368 break;
11369
539f890d
L		 11370 case OPTION_MAVXSCALAR:
11371 if (strcasecmp (arg, "128") == 0)
11372 avxscalar = vex128;
11373 else if (strcasecmp (arg, "256") == 0)
11374 avxscalar = vex256;
11375 else
2b5d6a91 11376 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 11377 break;
11378
03751133
L		 11379 case OPTION_MVEXWIG:
11380 if (strcmp (arg, "0") == 0)
11381 vexwig = evexw0;
11382 else if (strcmp (arg, "1") == 0)
11383 vexwig = evexw1;
11384 else
11385 as_fatal (_("invalid -mvexwig= option: `%s'"), arg);
11386 break;
11387
7e8b059b
L		 11388 case OPTION_MADD_BND_PREFIX:
11389 add_bnd_prefix = 1;
11390 break;
11391
43234a1e
L		 11392 case OPTION_MEVEXLIG:
11393 if (strcmp (arg, "128") == 0)
11394 evexlig = evexl128;
11395 else if (strcmp (arg, "256") == 0)
11396 evexlig = evexl256;
11397 else if (strcmp (arg, "512") == 0)
11398 evexlig = evexl512;
11399 else
11400 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
11401 break;
11402
d3d3c6db
IT		 11403 case OPTION_MEVEXRCIG:
11404 if (strcmp (arg, "rne") == 0)
11405 evexrcig = rne;
11406 else if (strcmp (arg, "rd") == 0)
11407 evexrcig = rd;
11408 else if (strcmp (arg, "ru") == 0)
11409 evexrcig = ru;
11410 else if (strcmp (arg, "rz") == 0)
11411 evexrcig = rz;
11412 else
11413 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
11414 break;
11415
43234a1e
L		 11416 case OPTION_MEVEXWIG:
11417 if (strcmp (arg, "0") == 0)
11418 evexwig = evexw0;
11419 else if (strcmp (arg, "1") == 0)
11420 evexwig = evexw1;
11421 else
11422 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
11423 break;
11424
167ad85b
TG		 11425# if defined (TE_PE) || defined (TE_PEP)
11426 case OPTION_MBIG_OBJ:
11427 use_big_obj = 1;
11428 break;
11429#endif
11430
d1982f93 11431 case OPTION_MOMIT_LOCK_PREFIX:
d022bddd
IT		 11432 if (strcasecmp (arg, "yes") == 0)
11433 omit_lock_prefix = 1;
11434 else if (strcasecmp (arg, "no") == 0)
11435 omit_lock_prefix = 0;
11436 else
11437 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
11438 break;
11439
e4e00185
AS		 11440 case OPTION_MFENCE_AS_LOCK_ADD:
11441 if (strcasecmp (arg, "yes") == 0)
11442 avoid_fence = 1;
11443 else if (strcasecmp (arg, "no") == 0)
11444 avoid_fence = 0;
11445 else
11446 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
11447 break;
11448
0cb4071e
L		 11449 case OPTION_MRELAX_RELOCATIONS:
11450 if (strcasecmp (arg, "yes") == 0)
11451 generate_relax_relocations = 1;
11452 else if (strcasecmp (arg, "no") == 0)
11453 generate_relax_relocations = 0;
11454 else
11455 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
11456 break;
11457
5db04b09 11458 case OPTION_MAMD64:
e89c5eaa 11459 intel64 = 0;
5db04b09
L		 11460 break;
11461
11462 case OPTION_MINTEL64:
e89c5eaa 11463 intel64 = 1;
5db04b09
L		 11464 break;
11465
b6f8c7c4
L		 11466 case 'O':
11467 if (arg == NULL)
11468 {
11469 optimize = 1;
11470 /* Turn off -Os. */
11471 optimize_for_space = 0;
11472 }
11473 else if (*arg == 's')
11474 {
11475 optimize_for_space = 1;
11476 /* Turn on all encoding optimizations. */
41fd2579 11477 optimize = INT_MAX;
b6f8c7c4
L		 11478 }
11479 else
11480 {
11481 optimize = atoi (arg);
11482 /* Turn off -Os. */
11483 optimize_for_space = 0;
11484 }
11485 break;
11486
252b5132
RH		 11487 default:
11488 return 0;
11489 }
11490 return 1;
11491}
11492
8a2c8fef
L		 11493#define MESSAGE_TEMPLATE \
11494" "
11495
293f5f65
L		 11496static char *
11497output_message (FILE *stream, char *p, char *message, char *start,
11498 int *left_p, const char *name, int len)
11499{
11500 int size = sizeof (MESSAGE_TEMPLATE);
11501 int left = *left_p;
11502
11503 /* Reserve 2 spaces for ", " or ",\0" */
11504 left -= len + 2;
11505
11506 /* Check if there is any room. */
11507 if (left >= 0)
11508 {
11509 if (p != start)
11510 {
11511 *p++ = ',';
11512 *p++ = ' ';
11513 }
11514 p = mempcpy (p, name, len);
11515 }
11516 else
11517 {
11518 /* Output the current message now and start a new one. */
11519 *p++ = ',';
11520 *p = '\0';
11521 fprintf (stream, "%s\n", message);
11522 p = start;
11523 left = size - (start - message) - len - 2;
11524
11525 gas_assert (left >= 0);
11526
11527 p = mempcpy (p, name, len);
11528 }
11529
11530 *left_p = left;
11531 return p;
11532}
11533
8a2c8fef 11534static void
1ded5609 11535show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 11536{
11537 static char message[] = MESSAGE_TEMPLATE;
11538 char *start = message + 27;
11539 char *p;
11540 int size = sizeof (MESSAGE_TEMPLATE);
11541 int left;
11542 const char *name;
11543 int len;
11544 unsigned int j;
11545
11546 p = start;
11547 left = size - (start - message);
11548 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
11549 {
11550 /* Should it be skipped? */
11551 if (cpu_arch [j].skip)
11552 continue;
11553
11554 name = cpu_arch [j].name;
11555 len = cpu_arch [j].len;
11556 if (*name == '.')
11557 {
11558 /* It is an extension. Skip if we aren't asked to show it. */
11559 if (ext)
11560 {
11561 name++;
11562 len--;
11563 }
11564 else
11565 continue;
11566 }
11567 else if (ext)
11568 {
11569 /* It is an processor. Skip if we show only extension. */
11570 continue;
11571 }
1ded5609
JB		 11572 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
11573 {
11574 /* It is an impossible processor - skip. */
11575 continue;
11576 }
8a2c8fef 11577
293f5f65 11578 p = output_message (stream, p, message, start, &left, name, len);
8a2c8fef
L		 11579 }
11580
293f5f65
L		 11581 /* Display disabled extensions. */
11582 if (ext)
11583 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
11584 {
11585 name = cpu_noarch [j].name;
11586 len = cpu_noarch [j].len;
11587 p = output_message (stream, p, message, start, &left, name,
11588 len);
11589 }
11590
8a2c8fef
L		 11591 *p = '\0';
11592 fprintf (stream, "%s\n", message);
11593}
11594
252b5132 11595void
8a2c8fef 11596md_show_usage (FILE *stream)
252b5132 11597{
4cc782b5
ILT		 11598#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11599 fprintf (stream, _("\
a38cf1db
AM		 11600 -Q ignored\n\
11601 -V print assembler version number\n\
b3b91714
AM		 11602 -k ignored\n"));
11603#endif
11604 fprintf (stream, _("\
12b55ccc 11605 -n Do not optimize code alignment\n\
b3b91714
AM		 11606 -q quieten some warnings\n"));
11607#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11608 fprintf (stream, _("\
a38cf1db 11609 -s ignored\n"));
b3b91714 11610#endif
d7f449c0
L		 11611#if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11612 || defined (TE_PE) || defined (TE_PEP))
751d281c 11613 fprintf (stream, _("\
570561f7 11614 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 11615#endif
b3b91714
AM		 11616#ifdef SVR4_COMMENT_CHARS
11617 fprintf (stream, _("\
11618 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 11619#else
11620 fprintf (stream, _("\
b3b91714 11621 --divide ignored\n"));
4cc782b5 11622#endif
9103f4f4 11623 fprintf (stream, _("\
6305a203 11624 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 11625 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 11626 show_arch (stream, 0, 1);
8a2c8fef
L		 11627 fprintf (stream, _("\
11628 EXTENSION is combination of:\n"));
1ded5609 11629 show_arch (stream, 1, 0);
6305a203 11630 fprintf (stream, _("\
8a2c8fef 11631 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 11632 show_arch (stream, 0, 0);
ba104c83 11633 fprintf (stream, _("\
c0f3af97
L		 11634 -msse2avx encode SSE instructions with VEX prefix\n"));
11635 fprintf (stream, _("\
7c5c05ef 11636 -msse-check=[none|error|warning] (default: warning)\n\
daf50ae7
L		 11637 check SSE instructions\n"));
11638 fprintf (stream, _("\
7c5c05ef 11639 -moperand-check=[none|error|warning] (default: warning)\n\
7bab8ab5
JB		 11640 check operand combinations for validity\n"));
11641 fprintf (stream, _("\
7c5c05ef
L		 11642 -mavxscalar=[128|256] (default: 128)\n\
11643 encode scalar AVX instructions with specific vector\n\
539f890d
L		 11644 length\n"));
11645 fprintf (stream, _("\
03751133
L		 11646 -mvexwig=[0|1] (default: 0)\n\
11647 encode VEX instructions with specific VEX.W value\n\
11648 for VEX.W bit ignored instructions\n"));
11649 fprintf (stream, _("\
7c5c05ef
L		 11650 -mevexlig=[128|256|512] (default: 128)\n\
11651 encode scalar EVEX instructions with specific vector\n\
43234a1e
L		 11652 length\n"));
11653 fprintf (stream, _("\
7c5c05ef
L		 11654 -mevexwig=[0|1] (default: 0)\n\
11655 encode EVEX instructions with specific EVEX.W value\n\
43234a1e
L		 11656 for EVEX.W bit ignored instructions\n"));
11657 fprintf (stream, _("\
7c5c05ef 11658 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
d3d3c6db
IT		 11659 encode EVEX instructions with specific EVEX.RC value\n\
11660 for SAE-only ignored instructions\n"));
11661 fprintf (stream, _("\
7c5c05ef
L		 11662 -mmnemonic=[att|intel] "));
11663 if (SYSV386_COMPAT)
11664 fprintf (stream, _("(default: att)\n"));
11665 else
11666 fprintf (stream, _("(default: intel)\n"));
11667 fprintf (stream, _("\
11668 use AT&T/Intel mnemonic\n"));
ba104c83 11669 fprintf (stream, _("\
7c5c05ef
L		 11670 -msyntax=[att|intel] (default: att)\n\
11671 use AT&T/Intel syntax\n"));
ba104c83
L		 11672 fprintf (stream, _("\
11673 -mindex-reg support pseudo index registers\n"));
11674 fprintf (stream, _("\
11675 -mnaked-reg don't require `%%' prefix for registers\n"));
11676 fprintf (stream, _("\
7e8b059b 11677 -madd-bnd-prefix add BND prefix for all valid branches\n"));
b4a3a7b4 11678#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8dcea932
L		 11679 fprintf (stream, _("\
11680 -mshared disable branch optimization for shared code\n"));
b4a3a7b4
L		 11681 fprintf (stream, _("\
11682 -mx86-used-note=[no|yes] "));
11683 if (DEFAULT_X86_USED_NOTE)
11684 fprintf (stream, _("(default: yes)\n"));
11685 else
11686 fprintf (stream, _("(default: no)\n"));
11687 fprintf (stream, _("\
11688 generate x86 used ISA and feature properties\n"));
11689#endif
11690#if defined (TE_PE) || defined (TE_PEP)
167ad85b
TG		 11691 fprintf (stream, _("\
11692 -mbig-obj generate big object files\n"));
11693#endif
d022bddd 11694 fprintf (stream, _("\
7c5c05ef 11695 -momit-lock-prefix=[no|yes] (default: no)\n\
d022bddd 11696 strip all lock prefixes\n"));
5db04b09 11697 fprintf (stream, _("\
7c5c05ef 11698 -mfence-as-lock-add=[no|yes] (default: no)\n\
e4e00185
AS		 11699 encode lfence, mfence and sfence as\n\
11700 lock addl $0x0, (%%{re}sp)\n"));
11701 fprintf (stream, _("\
7c5c05ef
L		 11702 -mrelax-relocations=[no|yes] "));
11703 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS)
11704 fprintf (stream, _("(default: yes)\n"));
11705 else
11706 fprintf (stream, _("(default: no)\n"));
11707 fprintf (stream, _("\
0cb4071e
L		 11708 generate relax relocations\n"));
11709 fprintf (stream, _("\
7c5c05ef 11710 -mamd64 accept only AMD64 ISA [default]\n"));
5db04b09
L		 11711 fprintf (stream, _("\
11712 -mintel64 accept only Intel64 ISA\n"));
252b5132
RH		 11713}
11714
3e73aa7c 11715#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 11716 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 11717 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 11718
11719/* Pick the target format to use. */
11720
47926f60 11721const char *
e3bb37b5 11722i386_target_format (void)
252b5132 11723{
351f65ca
L		 11724 if (!strncmp (default_arch, "x86_64", 6))
11725 {
11726 update_code_flag (CODE_64BIT, 1);
11727 if (default_arch[6] == '\0')
7f56bc95 11728 x86_elf_abi = X86_64_ABI;
351f65ca 11729 else
7f56bc95 11730 x86_elf_abi = X86_64_X32_ABI;
351f65ca 11731 }
3e73aa7c 11732 else if (!strcmp (default_arch, "i386"))
78f12dd3 11733 update_code_flag (CODE_32BIT, 1);
5197d474
L		 11734 else if (!strcmp (default_arch, "iamcu"))
11735 {
11736 update_code_flag (CODE_32BIT, 1);
11737 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
11738 {
11739 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
11740 cpu_arch_name = "iamcu";
11741 cpu_sub_arch_name = NULL;
11742 cpu_arch_flags = iamcu_flags;
11743 cpu_arch_isa = PROCESSOR_IAMCU;
11744 cpu_arch_isa_flags = iamcu_flags;
11745 if (!cpu_arch_tune_set)
11746 {
11747 cpu_arch_tune = cpu_arch_isa;
11748 cpu_arch_tune_flags = cpu_arch_isa_flags;
11749 }
11750 }
8d471ec1 11751 else if (cpu_arch_isa != PROCESSOR_IAMCU)
5197d474
L		 11752 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11753 cpu_arch_name);
11754 }
3e73aa7c 11755 else
2b5d6a91 11756 as_fatal (_("unknown architecture"));
89507696
JB		 11757
11758 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
11759 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11760 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
11761 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11762
252b5132
RH		 11763 switch (OUTPUT_FLAVOR)
11764 {
9384f2ff 11765#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 11766 case bfd_target_aout_flavour:
47926f60 11767 return AOUT_TARGET_FORMAT;
4c63da97 11768#endif
9384f2ff
AM		 11769#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11770# if defined (TE_PE) || defined (TE_PEP)
11771 case bfd_target_coff_flavour:
167ad85b
TG		 11772 if (flag_code == CODE_64BIT)
11773 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
11774 else
11775 return "pe-i386";
9384f2ff 11776# elif defined (TE_GO32)
0561d57c
JK		 11777 case bfd_target_coff_flavour:
11778 return "coff-go32";
9384f2ff 11779# else
252b5132
RH		 11780 case bfd_target_coff_flavour:
11781 return "coff-i386";
9384f2ff 11782# endif
4c63da97 11783#endif
3e73aa7c 11784#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 11785 case bfd_target_elf_flavour:
3e73aa7c 11786 {
351f65ca
L		 11787 const char *format;
11788
11789 switch (x86_elf_abi)
4fa24527 11790 {
351f65ca
L		 11791 default:
11792 format = ELF_TARGET_FORMAT;
11793 break;
7f56bc95 11794 case X86_64_ABI:
351f65ca 11795 use_rela_relocations = 1;
4fa24527 11796 object_64bit = 1;
351f65ca
L		 11797 format = ELF_TARGET_FORMAT64;
11798 break;
7f56bc95 11799 case X86_64_X32_ABI:
4fa24527 11800 use_rela_relocations = 1;
351f65ca 11801 object_64bit = 1;
862be3fb 11802 disallow_64bit_reloc = 1;
351f65ca
L		 11803 format = ELF_TARGET_FORMAT32;
11804 break;
4fa24527 11805 }
3632d14b 11806 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 11807 {
7f56bc95 11808 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 11809 as_fatal (_("Intel L1OM is 64bit only"));
11810 return ELF_TARGET_L1OM_FORMAT;
11811 }
b49f93f6 11812 else if (cpu_arch_isa == PROCESSOR_K1OM)
7a9068fe
L		 11813 {
11814 if (x86_elf_abi != X86_64_ABI)
11815 as_fatal (_("Intel K1OM is 64bit only"));
11816 return ELF_TARGET_K1OM_FORMAT;
11817 }
81486035
L		 11818 else if (cpu_arch_isa == PROCESSOR_IAMCU)
11819 {
11820 if (x86_elf_abi != I386_ABI)
11821 as_fatal (_("Intel MCU is 32bit only"));
11822 return ELF_TARGET_IAMCU_FORMAT;
11823 }
8a9036a4 11824 else
351f65ca 11825 return format;
3e73aa7c 11826 }
e57f8c65
TG		 11827#endif
11828#if defined (OBJ_MACH_O)
11829 case bfd_target_mach_o_flavour:
d382c579
TG		 11830 if (flag_code == CODE_64BIT)
11831 {
11832 use_rela_relocations = 1;
11833 object_64bit = 1;
11834 return "mach-o-x86-64";
11835 }
11836 else
11837 return "mach-o-i386";
4c63da97 11838#endif
252b5132
RH		 11839 default:
11840 abort ();
11841 return NULL;
11842 }
11843}
11844
47926f60 11845#endif /* OBJ_MAYBE_ more than one */
252b5132 11846\f
252b5132 11847symbolS *
7016a5d5 11848md_undefined_symbol (char *name)
252b5132 11849{
18dc2407
ILT		 11850 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
11851 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
11852 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
11853 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 11854 {
11855 if (!GOT_symbol)
11856 {
11857 if (symbol_find (name))
11858 as_bad (_("GOT already in symbol table"));
11859 GOT_symbol = symbol_new (name, undefined_section,
11860 (valueT) 0, &zero_address_frag);
11861 };
11862 return GOT_symbol;
11863 }
252b5132
RH		 11864 return 0;
11865}
11866
11867/* Round up a section size to the appropriate boundary. */
47926f60 11868
252b5132 11869valueT
7016a5d5 11870md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 11871{
4c63da97
AM		 11872#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11873 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
11874 {
11875 /* For a.out, force the section size to be aligned. If we don't do
11876 this, BFD will align it for us, but it will not write out the
11877 final bytes of the section. This may be a bug in BFD, but it is
11878 easier to fix it here since that is how the other a.out targets
11879 work. */
11880 int align;
11881
11882 align = bfd_get_section_alignment (stdoutput, segment);
8d3842cd 11883 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
4c63da97 11884 }
252b5132
RH		 11885#endif
11886
11887 return size;
11888}
11889
11890/* On the i386, PC-relative offsets are relative to the start of the
11891 next instruction. That is, the address of the offset, plus its
11892 size, since the offset is always the last part of the insn. */
11893
11894long
e3bb37b5 11895md_pcrel_from (fixS *fixP)
252b5132
RH		 11896{
11897 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
11898}
11899
11900#ifndef I386COFF
11901
11902static void
e3bb37b5 11903s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 11904{
29b0f896 11905 int temp;
252b5132 11906
8a75718c
JB		 11907#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11908 if (IS_ELF)
11909 obj_elf_section_change_hook ();
11910#endif
252b5132
RH		 11911 temp = get_absolute_expression ();
11912 subseg_set (bss_section, (subsegT) temp);
11913 demand_empty_rest_of_line ();
11914}
11915
11916#endif
11917
252b5132 11918void
e3bb37b5 11919i386_validate_fix (fixS *fixp)
252b5132 11920{
02a86693 11921 if (fixp->fx_subsy)
252b5132 11922 {
02a86693 11923 if (fixp->fx_subsy == GOT_symbol)
23df1078 11924 {
02a86693
L		 11925 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
11926 {
11927 if (!object_64bit)
11928 abort ();
11929#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11930 if (fixp->fx_tcbit2)
56ceb5b5
L		 11931 fixp->fx_r_type = (fixp->fx_tcbit
11932 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11933 : BFD_RELOC_X86_64_GOTPCRELX);
02a86693
L		 11934 else
11935#endif
11936 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
11937 }
d6ab8113 11938 else
02a86693
L		 11939 {
11940 if (!object_64bit)
11941 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
11942 else
11943 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
11944 }
11945 fixp->fx_subsy = 0;
23df1078 11946 }
252b5132 11947 }
02a86693
L		 11948#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11949 else if (!object_64bit)
11950 {
11951 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
11952 && fixp->fx_tcbit2)
11953 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
11954 }
11955#endif
252b5132
RH		 11956}
11957
252b5132 11958arelent *
7016a5d5 11959tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 11960{
11961 arelent *rel;
11962 bfd_reloc_code_real_type code;
11963
11964 switch (fixp->fx_r_type)
11965 {
8ce3d284 11966#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 11967 case BFD_RELOC_SIZE32:
11968 case BFD_RELOC_SIZE64:
11969 if (S_IS_DEFINED (fixp->fx_addsy)
11970 && !S_IS_EXTERNAL (fixp->fx_addsy))
11971 {
11972 /* Resolve size relocation against local symbol to size of
11973 the symbol plus addend. */
11974 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
11975 if (fixp->fx_r_type == BFD_RELOC_SIZE32
11976 && !fits_in_unsigned_long (value))
11977 as_bad_where (fixp->fx_file, fixp->fx_line,
11978 _("symbol size computation overflow"));
11979 fixp->fx_addsy = NULL;
11980 fixp->fx_subsy = NULL;
11981 md_apply_fix (fixp, (valueT *) &value, NULL);
11982 return NULL;
11983 }
8ce3d284 11984#endif
1a0670f3 11985 /* Fall through. */
8fd4256d 11986
3e73aa7c
JH		 11987 case BFD_RELOC_X86_64_PLT32:
11988 case BFD_RELOC_X86_64_GOT32:
11989 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 11990 case BFD_RELOC_X86_64_GOTPCRELX:
11991 case BFD_RELOC_X86_64_REX_GOTPCRELX:
252b5132
RH		 11992 case BFD_RELOC_386_PLT32:
11993 case BFD_RELOC_386_GOT32:
02a86693 11994 case BFD_RELOC_386_GOT32X:
252b5132
RH		 11995 case BFD_RELOC_386_GOTOFF:
11996 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 11997 case BFD_RELOC_386_TLS_GD:
11998 case BFD_RELOC_386_TLS_LDM:
11999 case BFD_RELOC_386_TLS_LDO_32:
12000 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 12001 case BFD_RELOC_386_TLS_IE:
12002 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 12003 case BFD_RELOC_386_TLS_LE_32:
12004 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 12005 case BFD_RELOC_386_TLS_GOTDESC:
12006 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 12007 case BFD_RELOC_X86_64_TLSGD:
12008 case BFD_RELOC_X86_64_TLSLD:
12009 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 12010 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 12011 case BFD_RELOC_X86_64_GOTTPOFF:
12012 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 12013 case BFD_RELOC_X86_64_TPOFF64:
12014 case BFD_RELOC_X86_64_GOTOFF64:
12015 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 12016 case BFD_RELOC_X86_64_GOT64:
12017 case BFD_RELOC_X86_64_GOTPCREL64:
12018 case BFD_RELOC_X86_64_GOTPC64:
12019 case BFD_RELOC_X86_64_GOTPLT64:
12020 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 12021 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
12022 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 12023 case BFD_RELOC_RVA:
12024 case BFD_RELOC_VTABLE_ENTRY:
12025 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 12026#ifdef TE_PE
12027 case BFD_RELOC_32_SECREL:
12028#endif
252b5132
RH		 12029 code = fixp->fx_r_type;
12030 break;
dbbaec26
L		 12031 case BFD_RELOC_X86_64_32S:
12032 if (!fixp->fx_pcrel)
12033 {
12034 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
12035 code = fixp->fx_r_type;
12036 break;
12037 }
1a0670f3 12038 /* Fall through. */
252b5132 12039 default:
93382f6d 12040 if (fixp->fx_pcrel)
252b5132 12041 {
93382f6d
AM		 12042 switch (fixp->fx_size)
12043 {
12044 default:
b091f402
AM		 12045 as_bad_where (fixp->fx_file, fixp->fx_line,
12046 _("can not do %d byte pc-relative relocation"),
12047 fixp->fx_size);
93382f6d
AM		 12048 code = BFD_RELOC_32_PCREL;
12049 break;
12050 case 1: code = BFD_RELOC_8_PCREL; break;
12051 case 2: code = BFD_RELOC_16_PCREL; break;
d258b828 12052 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 12053#ifdef BFD64
12054 case 8: code = BFD_RELOC_64_PCREL; break;
12055#endif
93382f6d
AM		 12056 }
12057 }
12058 else
12059 {
12060 switch (fixp->fx_size)
12061 {
12062 default:
b091f402
AM		 12063 as_bad_where (fixp->fx_file, fixp->fx_line,
12064 _("can not do %d byte relocation"),
12065 fixp->fx_size);
93382f6d
AM		 12066 code = BFD_RELOC_32;
12067 break;
12068 case 1: code = BFD_RELOC_8; break;
12069 case 2: code = BFD_RELOC_16; break;
12070 case 4: code = BFD_RELOC_32; break;
937149dd 12071#ifdef BFD64
3e73aa7c 12072 case 8: code = BFD_RELOC_64; break;
937149dd 12073#endif
93382f6d 12074 }
252b5132
RH		 12075 }
12076 break;
12077 }
252b5132 12078
d182319b
JB		 12079 if ((code == BFD_RELOC_32
12080 || code == BFD_RELOC_32_PCREL
12081 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 12082 && GOT_symbol
12083 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 12084 {
4fa24527 12085 if (!object_64bit)
d6ab8113
JB		 12086 code = BFD_RELOC_386_GOTPC;
12087 else
12088 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 12089 }
7b81dfbb
AJ		 12090 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
12091 && GOT_symbol
12092 && fixp->fx_addsy == GOT_symbol)
12093 {
12094 code = BFD_RELOC_X86_64_GOTPC64;
12095 }
252b5132 12096
add39d23
TS		 12097 rel = XNEW (arelent);
12098 rel->sym_ptr_ptr = XNEW (asymbol *);
49309057 12099 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 12100
12101 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 12102
3e73aa7c
JH		 12103 if (!use_rela_relocations)
12104 {
12105 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
12106 vtable entry to be used in the relocation's section offset. */
12107 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
12108 rel->address = fixp->fx_offset;
fbeb56a4
DK		 12109#if defined (OBJ_COFF) && defined (TE_PE)
12110 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
12111 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
12112 else
12113#endif
c6682705 12114 rel->addend = 0;
3e73aa7c
JH		 12115 }
12116 /* Use the rela in 64bit mode. */
252b5132 12117 else
3e73aa7c 12118 {
862be3fb
L		 12119 if (disallow_64bit_reloc)
12120 switch (code)
12121 {
862be3fb
L		 12122 case BFD_RELOC_X86_64_DTPOFF64:
12123 case BFD_RELOC_X86_64_TPOFF64:
12124 case BFD_RELOC_64_PCREL:
12125 case BFD_RELOC_X86_64_GOTOFF64:
12126 case BFD_RELOC_X86_64_GOT64:
12127 case BFD_RELOC_X86_64_GOTPCREL64:
12128 case BFD_RELOC_X86_64_GOTPC64:
12129 case BFD_RELOC_X86_64_GOTPLT64:
12130 case BFD_RELOC_X86_64_PLTOFF64:
12131 as_bad_where (fixp->fx_file, fixp->fx_line,
12132 _("cannot represent relocation type %s in x32 mode"),
12133 bfd_get_reloc_code_name (code));
12134 break;
12135 default:
12136 break;
12137 }
12138
062cd5e7
AS		 12139 if (!fixp->fx_pcrel)
12140 rel->addend = fixp->fx_offset;
12141 else
12142 switch (code)
12143 {
12144 case BFD_RELOC_X86_64_PLT32:
12145 case BFD_RELOC_X86_64_GOT32:
12146 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 12147 case BFD_RELOC_X86_64_GOTPCRELX:
12148 case BFD_RELOC_X86_64_REX_GOTPCRELX:
bffbf940
JJ		 12149 case BFD_RELOC_X86_64_TLSGD:
12150 case BFD_RELOC_X86_64_TLSLD:
12151 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 12152 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
12153 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 12154 rel->addend = fixp->fx_offset - fixp->fx_size;
12155 break;
12156 default:
12157 rel->addend = (section->vma
12158 - fixp->fx_size
12159 + fixp->fx_addnumber
12160 + md_pcrel_from (fixp));
12161 break;
12162 }
3e73aa7c
JH		 12163 }
12164
252b5132
RH		 12165 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
12166 if (rel->howto == NULL)
12167 {
12168 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 12169 _("cannot represent relocation type %s"),
252b5132
RH		 12170 bfd_get_reloc_code_name (code));
12171 /* Set howto to a garbage value so that we can keep going. */
12172 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 12173 gas_assert (rel->howto != NULL);
252b5132
RH		 12174 }
12175
12176 return rel;
12177}
12178
ee86248c 12179#include "tc-i386-intel.c"
54cfded0 12180
a60de03c
JB		 12181void
12182tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 12183{
a60de03c
JB		 12184 int saved_naked_reg;
12185 char saved_register_dot;
54cfded0 12186
a60de03c
JB		 12187 saved_naked_reg = allow_naked_reg;
12188 allow_naked_reg = 1;
12189 saved_register_dot = register_chars['.'];
12190 register_chars['.'] = '.';
12191 allow_pseudo_reg = 1;
12192 expression_and_evaluate (exp);
12193 allow_pseudo_reg = 0;
12194 register_chars['.'] = saved_register_dot;
12195 allow_naked_reg = saved_naked_reg;
12196
e96d56a1 12197 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 12198 {
a60de03c
JB		 12199 if ((addressT) exp->X_add_number < i386_regtab_size)
12200 {
12201 exp->X_op = O_constant;
12202 exp->X_add_number = i386_regtab[exp->X_add_number]
12203 .dw2_regnum[flag_code >> 1];
12204 }
12205 else
12206 exp->X_op = O_illegal;
54cfded0 12207 }
54cfded0
AM		 12208}
12209
12210void
12211tc_x86_frame_initial_instructions (void)
12212{
a60de03c
JB		 12213 static unsigned int sp_regno[2];
12214
12215 if (!sp_regno[flag_code >> 1])
12216 {
12217 char *saved_input = input_line_pointer;
12218 char sp[][4] = {"esp", "rsp"};
12219 expressionS exp;
a4447b93 12220
a60de03c
JB		 12221 input_line_pointer = sp[flag_code >> 1];
12222 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 12223 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 12224 sp_regno[flag_code >> 1] = exp.X_add_number;
12225 input_line_pointer = saved_input;
12226 }
a4447b93 12227
61ff971f
L		 12228 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
12229 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 12230}
d2b2c203 12231
d7921315
L		 12232int
12233x86_dwarf2_addr_size (void)
12234{
12235#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
12236 if (x86_elf_abi == X86_64_X32_ABI)
12237 return 4;
12238#endif
12239 return bfd_arch_bits_per_address (stdoutput) / 8;
12240}
12241
d2b2c203
DJ		 12242int
12243i386_elf_section_type (const char *str, size_t len)
12244{
12245 if (flag_code == CODE_64BIT
12246 && len == sizeof ("unwind") - 1
12247 && strncmp (str, "unwind", 6) == 0)
12248 return SHT_X86_64_UNWIND;
12249
12250 return -1;
12251}
bb41ade5 12252
ad5fec3b
EB		 12253#ifdef TE_SOLARIS
12254void
12255i386_solaris_fix_up_eh_frame (segT sec)
12256{
12257 if (flag_code == CODE_64BIT)
12258 elf_section_type (sec) = SHT_X86_64_UNWIND;
12259}
12260#endif
12261
bb41ade5
AM		 12262#ifdef TE_PE
12263void
12264tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
12265{
91d6fa6a 12266 expressionS exp;
bb41ade5 12267
91d6fa6a
NC		 12268 exp.X_op = O_secrel;
12269 exp.X_add_symbol = symbol;
12270 exp.X_add_number = 0;
12271 emit_expr (&exp, size);
bb41ade5
AM		 12272}
12273#endif
3b22753a
L		 12274
12275#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12276/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
12277
01e1a5bc 12278bfd_vma
6d4af3c2 12279x86_64_section_letter (int letter, const char **ptr_msg)
3b22753a
L		 12280{
12281 if (flag_code == CODE_64BIT)
12282 {
12283 if (letter == 'l')
12284 return SHF_X86_64_LARGE;
12285
8f3bae45 12286 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 12287 }
3b22753a 12288 else
8f3bae45 12289 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 12290 return -1;
12291}
12292
01e1a5bc 12293bfd_vma
3b22753a
L		 12294x86_64_section_word (char *str, size_t len)
12295{
8620418b 12296 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 12297 return SHF_X86_64_LARGE;
12298
12299 return -1;
12300}
12301
12302static void
12303handle_large_common (int small ATTRIBUTE_UNUSED)
12304{
12305 if (flag_code != CODE_64BIT)
12306 {
12307 s_comm_internal (0, elf_common_parse);
12308 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
12309 }
12310 else
12311 {
12312 static segT lbss_section;
12313 asection *saved_com_section_ptr = elf_com_section_ptr;
12314 asection *saved_bss_section = bss_section;
12315
12316 if (lbss_section == NULL)
12317 {
12318 flagword applicable;
12319 segT seg = now_seg;
12320 subsegT subseg = now_subseg;
12321
12322 /* The .lbss section is for local .largecomm symbols. */
12323 lbss_section = subseg_new (".lbss", 0);
12324 applicable = bfd_applicable_section_flags (stdoutput);
12325 bfd_set_section_flags (stdoutput, lbss_section,
12326 applicable & SEC_ALLOC);
12327 seg_info (lbss_section)->bss = 1;
12328
12329 subseg_set (seg, subseg);
12330 }
12331
12332 elf_com_section_ptr = &_bfd_elf_large_com_section;
12333 bss_section = lbss_section;
12334
12335 s_comm_internal (0, elf_common_parse);
12336
12337 elf_com_section_ptr = saved_com_section_ptr;
12338 bss_section = saved_bss_section;
12339 }
12340}
12341#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
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