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Rename PR ld/22842 run-time test to "Run pr22842"
[binutils.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
219d1afa 2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
252b5132 20
47926f60
KH		 21/* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus ([email protected]).
3e73aa7c 23 x86_64 support by Jan Hubicka ([email protected])
0f10071e 24 VIA PadLock support by Michal Ludvig ([email protected])
47926f60
KH		 25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
252b5132 27
252b5132 28#include "as.h"
3882b010 29#include "safe-ctype.h"
252b5132 30#include "subsegs.h"
316e2c05 31#include "dwarf2dbg.h"
54cfded0 32#include "dw2gencfi.h"
d2b2c203 33#include "elf/x86-64.h"
40fb9820 34#include "opcodes/i386-init.h"
252b5132 35
252b5132
RH		 36#ifndef REGISTER_WARNINGS
37#define REGISTER_WARNINGS 1
38#endif
39
c3332e24 40#ifndef INFER_ADDR_PREFIX
eecb386c 41#define INFER_ADDR_PREFIX 1
c3332e24
AM		 42#endif
43
29b0f896
AM		 44#ifndef DEFAULT_ARCH
45#define DEFAULT_ARCH "i386"
246fcdee 46#endif
252b5132 47
edde18a5
AM		 48#ifndef INLINE
49#if __GNUC__ >= 2
50#define INLINE __inline__
51#else
52#define INLINE
53#endif
54#endif
55
6305a203
L		 56/* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 61#define WAIT_PREFIX 0
62#define SEG_PREFIX 1
63#define ADDR_PREFIX 2
64#define DATA_PREFIX 3
c32fa91d 65#define REP_PREFIX 4
42164a71 66#define HLE_PREFIX REP_PREFIX
7e8b059b 67#define BND_PREFIX REP_PREFIX
c32fa91d 68#define LOCK_PREFIX 5
4e9ac44a
L		 69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
6305a203
L		 84/* Intel Syntax. Use a non-ascii letter since since it never appears
85 in instructions. */
86#define LONG_DOUBLE_MNEM_SUFFIX '\1'
87
88#define END_OF_INSN '\0'
89
90/*
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
95 END.
96 */
97typedef struct
98{
d3ce72d0
NC		 99 const insn_template *start;
100 const insn_template *end;
6305a203
L		 101}
102templates;
103
104/* 386 operand encoding bytes: see 386 book for details of this. */
105typedef struct
106{
107 unsigned int regmem; /* codes register or memory operand */
108 unsigned int reg; /* codes register operand (or extended opcode) */
109 unsigned int mode; /* how to interpret regmem & reg */
110}
111modrm_byte;
112
113/* x86-64 extension prefix. */
114typedef int rex_byte;
115
6305a203
L		 116/* 386 opcode byte to code indirect addressing. */
117typedef struct
118{
119 unsigned base;
120 unsigned index;
121 unsigned scale;
122}
123sib_byte;
124
6305a203
L		 125/* x86 arch names, types and features */
126typedef struct
127{
128 const char *name; /* arch name */
8a2c8fef 129 unsigned int len; /* arch string length */
6305a203
L		 130 enum processor_type type; /* arch type */
131 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 132 unsigned int skip; /* show_arch should skip this. */
6305a203
L		 133}
134arch_entry;
135
293f5f65
L		 136/* Used to turn off indicated flags. */
137typedef struct
138{
139 const char *name; /* arch name */
140 unsigned int len; /* arch string length */
141 i386_cpu_flags flags; /* cpu feature flags */
142}
143noarch_entry;
144
78f12dd3 145static void update_code_flag (int, int);
e3bb37b5
L		 146static void set_code_flag (int);
147static void set_16bit_gcc_code_flag (int);
148static void set_intel_syntax (int);
1efbbeb4 149static void set_intel_mnemonic (int);
db51cc60 150static void set_allow_index_reg (int);
7bab8ab5 151static void set_check (int);
e3bb37b5 152static void set_cpu_arch (int);
6482c264 153#ifdef TE_PE
e3bb37b5 154static void pe_directive_secrel (int);
6482c264 155#endif
e3bb37b5
L		 156static void signed_cons (int);
157static char *output_invalid (int c);
ee86248c
JB		 158static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
159 const char *);
160static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
161 const char *);
a7619375 162static int i386_att_operand (char *);
e3bb37b5 163static int i386_intel_operand (char *, int);
ee86248c
JB		 164static int i386_intel_simplify (expressionS *);
165static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 166static const reg_entry *parse_register (char *, char **);
167static char *parse_insn (char *, char *);
168static char *parse_operands (char *, const char *);
169static void swap_operands (void);
4d456e3d 170static void swap_2_operands (int, int);
e3bb37b5
L		 171static void optimize_imm (void);
172static void optimize_disp (void);
83b16ac6 173static const insn_template *match_template (char);
e3bb37b5
L		 174static int check_string (void);
175static int process_suffix (void);
176static int check_byte_reg (void);
177static int check_long_reg (void);
178static int check_qword_reg (void);
179static int check_word_reg (void);
180static int finalize_imm (void);
181static int process_operands (void);
182static const seg_entry *build_modrm_byte (void);
183static void output_insn (void);
184static void output_imm (fragS *, offsetT);
185static void output_disp (fragS *, offsetT);
29b0f896 186#ifndef I386COFF
e3bb37b5 187static void s_bss (int);
252b5132 188#endif
17d4e2a2
L		 189#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
190static void handle_large_common (int small ATTRIBUTE_UNUSED);
b4a3a7b4
L		 191
192/* GNU_PROPERTY_X86_ISA_1_USED. */
193static unsigned int x86_isa_1_used;
194/* GNU_PROPERTY_X86_FEATURE_2_USED. */
195static unsigned int x86_feature_2_used;
196/* Generate x86 used ISA and feature properties. */
197static unsigned int x86_used_note = DEFAULT_X86_USED_NOTE;
17d4e2a2 198#endif
252b5132 199
a847613f 200static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 201
43234a1e
L		 202/* This struct describes rounding control and SAE in the instruction. */
203struct RC_Operation
204{
205 enum rc_type
206 {
207 rne = 0,
208 rd,
209 ru,
210 rz,
211 saeonly
212 } type;
213 int operand;
214};
215
216static struct RC_Operation rc_op;
217
218/* The struct describes masking, applied to OPERAND in the instruction.
219 MASK is a pointer to the corresponding mask register. ZEROING tells
220 whether merging or zeroing mask is used. */
221struct Mask_Operation
222{
223 const reg_entry *mask;
224 unsigned int zeroing;
225 /* The operand where this operation is associated. */
226 int operand;
227};
228
229static struct Mask_Operation mask_op;
230
231/* The struct describes broadcasting, applied to OPERAND. FACTOR is
232 broadcast factor. */
233struct Broadcast_Operation
234{
8e6e0792 235 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
43234a1e
L		 236 int type;
237
238 /* Index of broadcasted operand. */
239 int operand;
4a1b91ea
L		 240
241 /* Number of bytes to broadcast. */
242 int bytes;
43234a1e
L		 243};
244
245static struct Broadcast_Operation broadcast_op;
246
c0f3af97
L		 247/* VEX prefix. */
248typedef struct
249{
43234a1e
L		 250 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
251 unsigned char bytes[4];
c0f3af97
L		 252 unsigned int length;
253 /* Destination or source register specifier. */
254 const reg_entry *register_specifier;
255} vex_prefix;
256
252b5132 257/* 'md_assemble ()' gathers together information and puts it into a
47926f60 258 i386_insn. */
252b5132 259
520dc8e8
AM		 260union i386_op
261 {
262 expressionS *disps;
263 expressionS *imms;
264 const reg_entry *regs;
265 };
266
a65babc9
L		 267enum i386_error
268 {
86e026a4 269 operand_size_mismatch,
a65babc9
L		 270 operand_type_mismatch,
271 register_type_mismatch,
272 number_of_operands_mismatch,
273 invalid_instruction_suffix,
274 bad_imm4,
a65babc9
L		 275 unsupported_with_intel_mnemonic,
276 unsupported_syntax,
6c30d220
L		 277 unsupported,
278 invalid_vsib_address,
7bab8ab5 279 invalid_vector_register_set,
43234a1e
L		 280 unsupported_vector_index_register,
281 unsupported_broadcast,
43234a1e
L		 282 broadcast_needed,
283 unsupported_masking,
284 mask_not_on_destination,
285 no_default_mask,
286 unsupported_rc_sae,
287 rc_sae_operand_not_last_imm,
288 invalid_register_operand,
a65babc9
L		 289 };
290
252b5132
RH		 291struct _i386_insn
292 {
47926f60 293 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 294 insn_template tm;
252b5132 295
7d5e4556
L		 296 /* SUFFIX holds the instruction size suffix for byte, word, dword
297 or qword, if given. */
252b5132
RH		 298 char suffix;
299
47926f60 300 /* OPERANDS gives the number of given operands. */
252b5132
RH		 301 unsigned int operands;
302
303 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
304 of given register, displacement, memory operands and immediate
47926f60 305 operands. */
252b5132
RH		 306 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
307
308 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 309 use OP[i] for the corresponding operand. */
40fb9820 310 i386_operand_type types[MAX_OPERANDS];
252b5132 311
520dc8e8
AM		 312 /* Displacement expression, immediate expression, or register for each
313 operand. */
314 union i386_op op[MAX_OPERANDS];
252b5132 315
3e73aa7c
JH		 316 /* Flags for operands. */
317 unsigned int flags[MAX_OPERANDS];
318#define Operand_PCrel 1
c48dadc9 319#define Operand_Mem 2
3e73aa7c 320
252b5132 321 /* Relocation type for operand */
f86103b7 322 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 323
252b5132
RH		 324 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
325 the base index byte below. */
326 const reg_entry *base_reg;
327 const reg_entry *index_reg;
328 unsigned int log2_scale_factor;
329
330 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 331 explicit segment overrides are given. */
ce8a8b2f 332 const seg_entry *seg[2];
252b5132 333
8325cc63
JB		 334 /* Copied first memory operand string, for re-checking. */
335 char *memop1_string;
336
252b5132
RH		 337 /* PREFIX holds all the given prefix opcodes (usually null).
338 PREFIXES is the number of prefix opcodes. */
339 unsigned int prefixes;
340 unsigned char prefix[MAX_PREFIXES];
341
b4a3a7b4
L		 342 /* Has MMX register operands. */
343 bfd_boolean has_regmmx;
344
345 /* Has XMM register operands. */
346 bfd_boolean has_regxmm;
347
348 /* Has YMM register operands. */
349 bfd_boolean has_regymm;
350
351 /* Has ZMM register operands. */
352 bfd_boolean has_regzmm;
353
252b5132 354 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 355 addressing modes of this insn are encoded. */
252b5132 356 modrm_byte rm;
3e73aa7c 357 rex_byte rex;
43234a1e 358 rex_byte vrex;
252b5132 359 sib_byte sib;
c0f3af97 360 vex_prefix vex;
b6169b20 361
43234a1e
L		 362 /* Masking attributes. */
363 struct Mask_Operation *mask;
364
365 /* Rounding control and SAE attributes. */
366 struct RC_Operation *rounding;
367
368 /* Broadcasting attributes. */
369 struct Broadcast_Operation *broadcast;
370
371 /* Compressed disp8*N attribute. */
372 unsigned int memshift;
373
86fa6981
L		 374 /* Prefer load or store in encoding. */
375 enum
376 {
377 dir_encoding_default = 0,
378 dir_encoding_load,
64c49ab3
JB		 379 dir_encoding_store,
380 dir_encoding_swap
86fa6981 381 } dir_encoding;
891edac4 382
a501d77e
L		 383 /* Prefer 8bit or 32bit displacement in encoding. */
384 enum
385 {
386 disp_encoding_default = 0,
387 disp_encoding_8bit,
388 disp_encoding_32bit
389 } disp_encoding;
f8a5c266 390
6b6b6807
L		 391 /* Prefer the REX byte in encoding. */
392 bfd_boolean rex_encoding;
393
b6f8c7c4
L		 394 /* Disable instruction size optimization. */
395 bfd_boolean no_optimize;
396
86fa6981
L		 397 /* How to encode vector instructions. */
398 enum
399 {
400 vex_encoding_default = 0,
401 vex_encoding_vex2,
402 vex_encoding_vex3,
403 vex_encoding_evex
404 } vec_encoding;
405
d5de92cf
L		 406 /* REP prefix. */
407 const char *rep_prefix;
408
165de32a
L		 409 /* HLE prefix. */
410 const char *hle_prefix;
42164a71 411
7e8b059b
L		 412 /* Have BND prefix. */
413 const char *bnd_prefix;
414
04ef582a
L		 415 /* Have NOTRACK prefix. */
416 const char *notrack_prefix;
417
891edac4 418 /* Error message. */
a65babc9 419 enum i386_error error;
252b5132
RH		 420 };
421
422typedef struct _i386_insn i386_insn;
423
43234a1e
L		 424/* Link RC type with corresponding string, that'll be looked for in
425 asm. */
426struct RC_name
427{
428 enum rc_type type;
429 const char *name;
430 unsigned int len;
431};
432
433static const struct RC_name RC_NamesTable[] =
434{
435 { rne, STRING_COMMA_LEN ("rn-sae") },
436 { rd, STRING_COMMA_LEN ("rd-sae") },
437 { ru, STRING_COMMA_LEN ("ru-sae") },
438 { rz, STRING_COMMA_LEN ("rz-sae") },
439 { saeonly, STRING_COMMA_LEN ("sae") },
440};
441
252b5132
RH		 442/* List of chars besides those in app.c:symbol_chars that can start an
443 operand. Used to prevent the scrubber eating vital white-space. */
86fa6981 444const char extra_symbol_chars[] = "*%-([{}"
252b5132 445#ifdef LEX_AT
32137342
NC		 446 "@"
447#endif
448#ifdef LEX_QM
449 "?"
252b5132 450#endif
32137342 451 ;
252b5132 452
29b0f896
AM		 453#if (defined (TE_I386AIX) \
454 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 455 && !defined (TE_GNU) \
29b0f896 456 && !defined (TE_LINUX) \
8d63c93e 457 && !defined (TE_NACL) \
29b0f896 458 && !defined (TE_FreeBSD) \
5b806d27 459 && !defined (TE_DragonFly) \
29b0f896 460 && !defined (TE_NetBSD)))
252b5132 461/* This array holds the chars that always start a comment. If the
b3b91714
AM		 462 pre-processor is disabled, these aren't very useful. The option
463 --divide will remove '/' from this list. */
464const char *i386_comment_chars = "#/";
465#define SVR4_COMMENT_CHARS 1
252b5132 466#define PREFIX_SEPARATOR '\\'
252b5132 467
b3b91714
AM		 468#else
469const char *i386_comment_chars = "#";
470#define PREFIX_SEPARATOR '/'
471#endif
472
252b5132
RH		 473/* This array holds the chars that only start a comment at the beginning of
474 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 475 .line and .file directives will appear in the pre-processed output.
476 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 477 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 478 #NO_APP at the beginning of its output.
479 Also note that comments started like this one will always work if
252b5132 480 '/' isn't otherwise defined. */
b3b91714 481const char line_comment_chars[] = "#/";
252b5132 482
63a0b638 483const char line_separator_chars[] = ";";
252b5132 484
ce8a8b2f
AM		 485/* Chars that can be used to separate mant from exp in floating point
486 nums. */
252b5132
RH		 487const char EXP_CHARS[] = "eE";
488
ce8a8b2f
AM		 489/* Chars that mean this number is a floating point constant
490 As in 0f12.456
491 or 0d1.2345e12. */
252b5132
RH		 492const char FLT_CHARS[] = "fFdDxX";
493
ce8a8b2f 494/* Tables for lexical analysis. */
252b5132
RH		 495static char mnemonic_chars[256];
496static char register_chars[256];
497static char operand_chars[256];
498static char identifier_chars[256];
499static char digit_chars[256];
500
ce8a8b2f 501/* Lexical macros. */
252b5132
RH		 502#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
503#define is_operand_char(x) (operand_chars[(unsigned char) x])
504#define is_register_char(x) (register_chars[(unsigned char) x])
505#define is_space_char(x) ((x) == ' ')
506#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
507#define is_digit_char(x) (digit_chars[(unsigned char) x])
508
0234cb7c 509/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 510static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
511
512/* md_assemble() always leaves the strings it's passed unaltered. To
513 effect this we maintain a stack of saved characters that we've smashed
514 with '\0's (indicating end of strings for various sub-fields of the
47926f60 515 assembler instruction). */
252b5132 516static char save_stack[32];
ce8a8b2f 517static char *save_stack_p;
252b5132
RH		 518#define END_STRING_AND_SAVE(s) \
519 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
520#define RESTORE_END_STRING(s) \
521 do { *(s) = *--save_stack_p; } while (0)
522
47926f60 523/* The instruction we're assembling. */
252b5132
RH		 524static i386_insn i;
525
526/* Possible templates for current insn. */
527static const templates *current_templates;
528
31b2323c
L		 529/* Per instruction expressionS buffers: max displacements & immediates. */
530static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
531static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 532
47926f60 533/* Current operand we are working on. */
ee86248c 534static int this_operand = -1;
252b5132 535
3e73aa7c
JH		 536/* We support four different modes. FLAG_CODE variable is used to distinguish
537 these. */
538
539enum flag_code {
540 CODE_32BIT,
541 CODE_16BIT,
542 CODE_64BIT };
543
544static enum flag_code flag_code;
4fa24527 545static unsigned int object_64bit;
862be3fb 546static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 547static int use_rela_relocations = 0;
548
7af8ed2d
NC		 549#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
550 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
551 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
552
351f65ca
L		 553/* The ELF ABI to use. */
554enum x86_elf_abi
555{
556 I386_ABI,
7f56bc95
L		 557 X86_64_ABI,
558 X86_64_X32_ABI
351f65ca
L		 559};
560
561static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 562#endif
351f65ca 563
167ad85b
TG		 564#if defined (TE_PE) || defined (TE_PEP)
565/* Use big object file format. */
566static int use_big_obj = 0;
567#endif
568
8dcea932
L		 569#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570/* 1 if generating code for a shared library. */
571static int shared = 0;
572#endif
573
47926f60
KH		 574/* 1 for intel syntax,
575 0 if att syntax. */
576static int intel_syntax = 0;
252b5132 577
e89c5eaa
L		 578/* 1 for Intel64 ISA,
579 0 if AMD64 ISA. */
580static int intel64;
581
1efbbeb4
L		 582/* 1 for intel mnemonic,
583 0 if att mnemonic. */
584static int intel_mnemonic = !SYSV386_COMPAT;
585
a60de03c
JB		 586/* 1 if pseudo registers are permitted. */
587static int allow_pseudo_reg = 0;
588
47926f60
KH		 589/* 1 if register prefix % not required. */
590static int allow_naked_reg = 0;
252b5132 591
33eaf5de 592/* 1 if the assembler should add BND prefix for all control-transferring
7e8b059b
L		 593 instructions supporting it, even if this prefix wasn't specified
594 explicitly. */
595static int add_bnd_prefix = 0;
596
ba104c83 597/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 598static int allow_index_reg = 0;
599
d022bddd
IT		 600/* 1 if the assembler should ignore LOCK prefix, even if it was
601 specified explicitly. */
602static int omit_lock_prefix = 0;
603
e4e00185
AS		 604/* 1 if the assembler should encode lfence, mfence, and sfence as
605 "lock addl $0, (%{re}sp)". */
606static int avoid_fence = 0;
607
0cb4071e
L		 608/* 1 if the assembler should generate relax relocations. */
609
610static int generate_relax_relocations
611 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
612
7bab8ab5 613static enum check_kind
daf50ae7 614 {
7bab8ab5
JB		 615 check_none = 0,
616 check_warning,
617 check_error
daf50ae7 618 }
7bab8ab5 619sse_check, operand_check = check_warning;
daf50ae7 620
b6f8c7c4
L		 621/* Optimization:
622 1. Clear the REX_W bit with register operand if possible.
623 2. Above plus use 128bit vector instruction to clear the full vector
624 register.
625 */
626static int optimize = 0;
627
628/* Optimization:
629 1. Clear the REX_W bit with register operand if possible.
630 2. Above plus use 128bit vector instruction to clear the full vector
631 register.
632 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
633 "testb $imm7,%r8".
634 */
635static int optimize_for_space = 0;
636
2ca3ace5
L		 637/* Register prefix used for error message. */
638static const char *register_prefix = "%";
639
47926f60
KH		 640/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
641 leave, push, and pop instructions so that gcc has the same stack
642 frame as in 32 bit mode. */
643static char stackop_size = '\0';
eecb386c 644
12b55ccc
L		 645/* Non-zero to optimize code alignment. */
646int optimize_align_code = 1;
647
47926f60
KH		 648/* Non-zero to quieten some warnings. */
649static int quiet_warnings = 0;
a38cf1db 650
47926f60
KH		 651/* CPU name. */
652static const char *cpu_arch_name = NULL;
6305a203 653static char *cpu_sub_arch_name = NULL;
a38cf1db 654
47926f60 655/* CPU feature flags. */
40fb9820
L		 656static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
657
ccc9c027
L		 658/* If we have selected a cpu we are generating instructions for. */
659static int cpu_arch_tune_set = 0;
660
9103f4f4 661/* Cpu we are generating instructions for. */
fbf3f584 662enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 663
664/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 665static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 666
ccc9c027 667/* CPU instruction set architecture used. */
fbf3f584 668enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 669
9103f4f4 670/* CPU feature flags of instruction set architecture used. */
fbf3f584 671i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 672
fddf5b5b
AM		 673/* If set, conditional jumps are not automatically promoted to handle
674 larger than a byte offset. */
675static unsigned int no_cond_jump_promotion = 0;
676
c0f3af97
L		 677/* Encode SSE instructions with VEX prefix. */
678static unsigned int sse2avx;
679
539f890d
L		 680/* Encode scalar AVX instructions with specific vector length. */
681static enum
682 {
683 vex128 = 0,
684 vex256
685 } avxscalar;
686
03751133
L		 687/* Encode VEX WIG instructions with specific vex.w. */
688static enum
689 {
690 vexw0 = 0,
691 vexw1
692 } vexwig;
693
43234a1e
L		 694/* Encode scalar EVEX LIG instructions with specific vector length. */
695static enum
696 {
697 evexl128 = 0,
698 evexl256,
699 evexl512
700 } evexlig;
701
702/* Encode EVEX WIG instructions with specific evex.w. */
703static enum
704 {
705 evexw0 = 0,
706 evexw1
707 } evexwig;
708
d3d3c6db
IT		 709/* Value to encode in EVEX RC bits, for SAE-only instructions. */
710static enum rc_type evexrcig = rne;
711
29b0f896 712/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 713static symbolS *GOT_symbol;
29b0f896 714
a4447b93
RH		 715/* The dwarf2 return column, adjusted for 32 or 64 bit. */
716unsigned int x86_dwarf2_return_column;
717
718/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
719int x86_cie_data_alignment;
720
252b5132 721/* Interface to relax_segment.
fddf5b5b
AM		 722 There are 3 major relax states for 386 jump insns because the
723 different types of jumps add different sizes to frags when we're
724 figuring out what sort of jump to choose to reach a given label. */
252b5132 725
47926f60 726/* Types. */
93c2a809
AM		 727#define UNCOND_JUMP 0
728#define COND_JUMP 1
729#define COND_JUMP86 2
fddf5b5b 730
47926f60 731/* Sizes. */
252b5132
RH		 732#define CODE16 1
733#define SMALL 0
29b0f896 734#define SMALL16 (SMALL | CODE16)
252b5132 735#define BIG 2
29b0f896 736#define BIG16 (BIG | CODE16)
252b5132
RH		 737
738#ifndef INLINE
739#ifdef __GNUC__
740#define INLINE __inline__
741#else
742#define INLINE
743#endif
744#endif
745
fddf5b5b
AM		 746#define ENCODE_RELAX_STATE(type, size) \
747 ((relax_substateT) (((type) << 2) | (size)))
748#define TYPE_FROM_RELAX_STATE(s) \
749 ((s) >> 2)
750#define DISP_SIZE_FROM_RELAX_STATE(s) \
751 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 752
753/* This table is used by relax_frag to promote short jumps to long
754 ones where necessary. SMALL (short) jumps may be promoted to BIG
755 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
756 don't allow a short jump in a 32 bit code segment to be promoted to
757 a 16 bit offset jump because it's slower (requires data size
758 prefix), and doesn't work, unless the destination is in the bottom
759 64k of the code segment (The top 16 bits of eip are zeroed). */
760
761const relax_typeS md_relax_table[] =
762{
24eab124
AM		 763 /* The fields are:
764 1) most positive reach of this state,
765 2) most negative reach of this state,
93c2a809 766 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 767 4) which index into the table to try if we can't fit into this one. */
252b5132 768
fddf5b5b 769 /* UNCOND_JUMP states. */
93c2a809
AM		 770 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
771 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
772 /* dword jmp adds 4 bytes to frag:
773 0 extra opcode bytes, 4 displacement bytes. */
252b5132 774 {0, 0, 4, 0},
93c2a809
AM		 775 /* word jmp adds 2 byte2 to frag:
776 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 777 {0, 0, 2, 0},
778
93c2a809
AM		 779 /* COND_JUMP states. */
780 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
781 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
782 /* dword conditionals adds 5 bytes to frag:
783 1 extra opcode byte, 4 displacement bytes. */
784 {0, 0, 5, 0},
fddf5b5b 785 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 786 1 extra opcode byte, 2 displacement bytes. */
787 {0, 0, 3, 0},
788
789 /* COND_JUMP86 states. */
790 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
791 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
792 /* dword conditionals adds 5 bytes to frag:
793 1 extra opcode byte, 4 displacement bytes. */
794 {0, 0, 5, 0},
795 /* word conditionals add 4 bytes to frag:
796 1 displacement byte and a 3 byte long branch insn. */
797 {0, 0, 4, 0}
252b5132
RH		 798};
799
9103f4f4
L		 800static const arch_entry cpu_arch[] =
801{
89507696
JB		 802 /* Do not replace the first two entries - i386_target_format()
803 relies on them being there in this order. */
8a2c8fef 804 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
293f5f65 805 CPU_GENERIC32_FLAGS, 0 },
8a2c8fef 806 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
293f5f65 807 CPU_GENERIC64_FLAGS, 0 },
8a2c8fef 808 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
293f5f65 809 CPU_NONE_FLAGS, 0 },
8a2c8fef 810 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
293f5f65 811 CPU_I186_FLAGS, 0 },
8a2c8fef 812 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
293f5f65 813 CPU_I286_FLAGS, 0 },
8a2c8fef 814 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
293f5f65 815 CPU_I386_FLAGS, 0 },
8a2c8fef 816 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
293f5f65 817 CPU_I486_FLAGS, 0 },
8a2c8fef 818 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
293f5f65 819 CPU_I586_FLAGS, 0 },
8a2c8fef 820 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
293f5f65 821 CPU_I686_FLAGS, 0 },
8a2c8fef 822 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
293f5f65 823 CPU_I586_FLAGS, 0 },
8a2c8fef 824 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
293f5f65 825 CPU_PENTIUMPRO_FLAGS, 0 },
8a2c8fef 826 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
293f5f65 827 CPU_P2_FLAGS, 0 },
8a2c8fef 828 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
293f5f65 829 CPU_P3_FLAGS, 0 },
8a2c8fef 830 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
293f5f65 831 CPU_P4_FLAGS, 0 },
8a2c8fef 832 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
293f5f65 833 CPU_CORE_FLAGS, 0 },
8a2c8fef 834 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
293f5f65 835 CPU_NOCONA_FLAGS, 0 },
8a2c8fef 836 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
293f5f65 837 CPU_CORE_FLAGS, 1 },
8a2c8fef 838 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
293f5f65 839 CPU_CORE_FLAGS, 0 },
8a2c8fef 840 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
293f5f65 841 CPU_CORE2_FLAGS, 1 },
8a2c8fef 842 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
293f5f65 843 CPU_CORE2_FLAGS, 0 },
8a2c8fef 844 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
293f5f65 845 CPU_COREI7_FLAGS, 0 },
8a2c8fef 846 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
293f5f65 847 CPU_L1OM_FLAGS, 0 },
7a9068fe 848 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
293f5f65 849 CPU_K1OM_FLAGS, 0 },
81486035 850 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
293f5f65 851 CPU_IAMCU_FLAGS, 0 },
8a2c8fef 852 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
293f5f65 853 CPU_K6_FLAGS, 0 },
8a2c8fef 854 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
293f5f65 855 CPU_K6_2_FLAGS, 0 },
8a2c8fef 856 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
293f5f65 857 CPU_ATHLON_FLAGS, 0 },
8a2c8fef 858 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
293f5f65 859 CPU_K8_FLAGS, 1 },
8a2c8fef 860 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
293f5f65 861 CPU_K8_FLAGS, 0 },
8a2c8fef 862 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
293f5f65 863 CPU_K8_FLAGS, 0 },
8a2c8fef 864 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
293f5f65 865 CPU_AMDFAM10_FLAGS, 0 },
8aedb9fe 866 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
293f5f65 867 CPU_BDVER1_FLAGS, 0 },
8aedb9fe 868 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
293f5f65 869 CPU_BDVER2_FLAGS, 0 },
5e5c50d3 870 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
293f5f65 871 CPU_BDVER3_FLAGS, 0 },
c7b0bd56 872 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
293f5f65 873 CPU_BDVER4_FLAGS, 0 },
029f3522 874 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
293f5f65 875 CPU_ZNVER1_FLAGS, 0 },
a9660a6f
AP		 876 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER,
877 CPU_ZNVER2_FLAGS, 0 },
7b458c12 878 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
293f5f65 879 CPU_BTVER1_FLAGS, 0 },
7b458c12 880 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
293f5f65 881 CPU_BTVER2_FLAGS, 0 },
8a2c8fef 882 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
293f5f65 883 CPU_8087_FLAGS, 0 },
8a2c8fef 884 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
293f5f65 885 CPU_287_FLAGS, 0 },
8a2c8fef 886 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
293f5f65 887 CPU_387_FLAGS, 0 },
1848e567
L		 888 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
889 CPU_687_FLAGS, 0 },
d871f3f4
L		 890 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN,
891 CPU_CMOV_FLAGS, 0 },
892 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN,
893 CPU_FXSR_FLAGS, 0 },
8a2c8fef 894 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
293f5f65 895 CPU_MMX_FLAGS, 0 },
8a2c8fef 896 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
293f5f65 897 CPU_SSE_FLAGS, 0 },
8a2c8fef 898 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
293f5f65 899 CPU_SSE2_FLAGS, 0 },
8a2c8fef 900 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
293f5f65 901 CPU_SSE3_FLAGS, 0 },
8a2c8fef 902 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
293f5f65 903 CPU_SSSE3_FLAGS, 0 },
8a2c8fef 904 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
293f5f65 905 CPU_SSE4_1_FLAGS, 0 },
8a2c8fef 906 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
293f5f65 907 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 908 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
293f5f65 909 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 910 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
293f5f65 911 CPU_AVX_FLAGS, 0 },
6c30d220 912 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
293f5f65 913 CPU_AVX2_FLAGS, 0 },
43234a1e 914 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
293f5f65 915 CPU_AVX512F_FLAGS, 0 },
43234a1e 916 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
293f5f65 917 CPU_AVX512CD_FLAGS, 0 },
43234a1e 918 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
293f5f65 919 CPU_AVX512ER_FLAGS, 0 },
43234a1e 920 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
293f5f65 921 CPU_AVX512PF_FLAGS, 0 },
1dfc6506 922 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
293f5f65 923 CPU_AVX512DQ_FLAGS, 0 },
1dfc6506 924 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
293f5f65 925 CPU_AVX512BW_FLAGS, 0 },
1dfc6506 926 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
293f5f65 927 CPU_AVX512VL_FLAGS, 0 },
8a2c8fef 928 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
293f5f65 929 CPU_VMX_FLAGS, 0 },
8729a6f6 930 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
293f5f65 931 CPU_VMFUNC_FLAGS, 0 },
8a2c8fef 932 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
293f5f65 933 CPU_SMX_FLAGS, 0 },
8a2c8fef 934 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
293f5f65 935 CPU_XSAVE_FLAGS, 0 },
c7b8aa3a 936 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
293f5f65 937 CPU_XSAVEOPT_FLAGS, 0 },
1dfc6506 938 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
293f5f65 939 CPU_XSAVEC_FLAGS, 0 },
1dfc6506 940 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
293f5f65 941 CPU_XSAVES_FLAGS, 0 },
8a2c8fef 942 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
293f5f65 943 CPU_AES_FLAGS, 0 },
8a2c8fef 944 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
293f5f65 945 CPU_PCLMUL_FLAGS, 0 },
8a2c8fef 946 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
293f5f65 947 CPU_PCLMUL_FLAGS, 1 },
c7b8aa3a 948 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
293f5f65 949 CPU_FSGSBASE_FLAGS, 0 },
c7b8aa3a 950 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
293f5f65 951 CPU_RDRND_FLAGS, 0 },
c7b8aa3a 952 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
293f5f65 953 CPU_F16C_FLAGS, 0 },
6c30d220 954 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
293f5f65 955 CPU_BMI2_FLAGS, 0 },
8a2c8fef 956 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
293f5f65 957 CPU_FMA_FLAGS, 0 },
8a2c8fef 958 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
293f5f65 959 CPU_FMA4_FLAGS, 0 },
8a2c8fef 960 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
293f5f65 961 CPU_XOP_FLAGS, 0 },
8a2c8fef 962 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
293f5f65 963 CPU_LWP_FLAGS, 0 },
8a2c8fef 964 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
293f5f65 965 CPU_MOVBE_FLAGS, 0 },
60aa667e 966 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
293f5f65 967 CPU_CX16_FLAGS, 0 },
8a2c8fef 968 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
293f5f65 969 CPU_EPT_FLAGS, 0 },
6c30d220 970 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
293f5f65 971 CPU_LZCNT_FLAGS, 0 },
42164a71 972 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
293f5f65 973 CPU_HLE_FLAGS, 0 },
42164a71 974 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
293f5f65 975 CPU_RTM_FLAGS, 0 },
6c30d220 976 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
293f5f65 977 CPU_INVPCID_FLAGS, 0 },
8a2c8fef 978 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
293f5f65 979 CPU_CLFLUSH_FLAGS, 0 },
22109423 980 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
293f5f65 981 CPU_NOP_FLAGS, 0 },
8a2c8fef 982 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
293f5f65 983 CPU_SYSCALL_FLAGS, 0 },
8a2c8fef 984 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
293f5f65 985 CPU_RDTSCP_FLAGS, 0 },
8a2c8fef 986 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
293f5f65 987 CPU_3DNOW_FLAGS, 0 },
8a2c8fef 988 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
293f5f65 989 CPU_3DNOWA_FLAGS, 0 },
8a2c8fef 990 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
293f5f65 991 CPU_PADLOCK_FLAGS, 0 },
8a2c8fef 992 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
293f5f65 993 CPU_SVME_FLAGS, 1 },
8a2c8fef 994 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
293f5f65 995 CPU_SVME_FLAGS, 0 },
8a2c8fef 996 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
293f5f65 997 CPU_SSE4A_FLAGS, 0 },
8a2c8fef 998 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
293f5f65 999 CPU_ABM_FLAGS, 0 },
87973e9f 1000 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
293f5f65 1001 CPU_BMI_FLAGS, 0 },
2a2a0f38 1002 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
293f5f65 1003 CPU_TBM_FLAGS, 0 },
e2e1fcde 1004 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
293f5f65 1005 CPU_ADX_FLAGS, 0 },
e2e1fcde 1006 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
293f5f65 1007 CPU_RDSEED_FLAGS, 0 },
e2e1fcde 1008 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
293f5f65 1009 CPU_PRFCHW_FLAGS, 0 },
5c111e37 1010 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
293f5f65 1011 CPU_SMAP_FLAGS, 0 },
7e8b059b 1012 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
293f5f65 1013 CPU_MPX_FLAGS, 0 },
a0046408 1014 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
293f5f65 1015 CPU_SHA_FLAGS, 0 },
963f3586 1016 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
293f5f65 1017 CPU_CLFLUSHOPT_FLAGS, 0 },
dcf893b5 1018 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
293f5f65 1019 CPU_PREFETCHWT1_FLAGS, 0 },
2cf200a4 1020 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
293f5f65 1021 CPU_SE1_FLAGS, 0 },
c5e7287a 1022 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
293f5f65 1023 CPU_CLWB_FLAGS, 0 },
2cc1b5aa 1024 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
293f5f65 1025 CPU_AVX512IFMA_FLAGS, 0 },
14f195c9 1026 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
293f5f65 1027 CPU_AVX512VBMI_FLAGS, 0 },
920d2ddc
IT		 1028 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
1029 CPU_AVX512_4FMAPS_FLAGS, 0 },
47acf0bd
IT		 1030 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
1031 CPU_AVX512_4VNNIW_FLAGS, 0 },
620214f7
IT		 1032 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
1033 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
53467f57
IT		 1034 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
1035 CPU_AVX512_VBMI2_FLAGS, 0 },
8cfcb765
IT		 1036 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN,
1037 CPU_AVX512_VNNI_FLAGS, 0 },
ee6872be
IT		 1038 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN,
1039 CPU_AVX512_BITALG_FLAGS, 0 },
029f3522 1040 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
293f5f65 1041 CPU_CLZERO_FLAGS, 0 },
9916071f 1042 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
293f5f65 1043 CPU_MWAITX_FLAGS, 0 },
8eab4136 1044 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
293f5f65 1045 CPU_OSPKE_FLAGS, 0 },
8bc52696 1046 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
293f5f65 1047 CPU_RDPID_FLAGS, 0 },
6b40c462
L		 1048 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
1049 CPU_PTWRITE_FLAGS, 0 },
d777820b
IT		 1050 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN,
1051 CPU_IBT_FLAGS, 0 },
1052 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN,
1053 CPU_SHSTK_FLAGS, 0 },
48521003
IT		 1054 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
1055 CPU_GFNI_FLAGS, 0 },
8dcf1fad
IT		 1056 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
1057 CPU_VAES_FLAGS, 0 },
ff1982d5
IT		 1058 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
1059 CPU_VPCLMULQDQ_FLAGS, 0 },
3233d7d0
IT		 1060 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN,
1061 CPU_WBNOINVD_FLAGS, 0 },
be3a8dca
IT		 1062 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN,
1063 CPU_PCONFIG_FLAGS, 0 },
de89d0a3
IT		 1064 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN,
1065 CPU_WAITPKG_FLAGS, 0 },
c48935d7
IT		 1066 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN,
1067 CPU_CLDEMOTE_FLAGS, 0 },
c0a30a9f
L		 1068 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN,
1069 CPU_MOVDIRI_FLAGS, 0 },
1070 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN,
1071 CPU_MOVDIR64B_FLAGS, 0 },
293f5f65
L		 1072};
1073
1074static const noarch_entry cpu_noarch[] =
1075{
1076 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1848e567
L		 1077 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1078 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1079 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
d871f3f4
L		 1080 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS },
1081 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS },
293f5f65
L		 1082 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1083 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1848e567
L		 1084 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1085 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1086 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1087 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1088 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1089 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
293f5f65 1090 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1848e567 1091 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
144b71e2
L		 1092 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1093 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1094 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1095 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1096 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1097 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1098 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1099 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1100 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
920d2ddc 1101 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
47acf0bd 1102 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
620214f7 1103 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
53467f57 1104 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
8cfcb765 1105 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS },
ee6872be 1106 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS },
d777820b
IT		 1107 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS },
1108 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS },
c0a30a9f
L		 1109 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS },
1110 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS },
e413e4e9
AM		 1111};
1112
704209c0 1113#ifdef I386COFF
a6c24e68
NC		 1114/* Like s_lcomm_internal in gas/read.c but the alignment string
1115 is allowed to be optional. */
1116
1117static symbolS *
1118pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1119{
1120 addressT align = 0;
1121
1122 SKIP_WHITESPACE ();
1123
7ab9ffdd 1124 if (needs_align
a6c24e68
NC		 1125 && *input_line_pointer == ',')
1126 {
1127 align = parse_align (needs_align - 1);
7ab9ffdd 1128
a6c24e68
NC		 1129 if (align == (addressT) -1)
1130 return NULL;
1131 }
1132 else
1133 {
1134 if (size >= 8)
1135 align = 3;
1136 else if (size >= 4)
1137 align = 2;
1138 else if (size >= 2)
1139 align = 1;
1140 else
1141 align = 0;
1142 }
1143
1144 bss_alloc (symbolP, size, align);
1145 return symbolP;
1146}
1147
704209c0 1148static void
a6c24e68
NC		 1149pe_lcomm (int needs_align)
1150{
1151 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1152}
704209c0 1153#endif
a6c24e68 1154
29b0f896
AM		 1155const pseudo_typeS md_pseudo_table[] =
1156{
1157#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1158 {"align", s_align_bytes, 0},
1159#else
1160 {"align", s_align_ptwo, 0},
1161#endif
1162 {"arch", set_cpu_arch, 0},
1163#ifndef I386COFF
1164 {"bss", s_bss, 0},
a6c24e68
NC		 1165#else
1166 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 1167#endif
1168 {"ffloat", float_cons, 'f'},
1169 {"dfloat", float_cons, 'd'},
1170 {"tfloat", float_cons, 'x'},
1171 {"value", cons, 2},
d182319b 1172 {"slong", signed_cons, 4},
29b0f896
AM		 1173 {"noopt", s_ignore, 0},
1174 {"optim", s_ignore, 0},
1175 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1176 {"code16", set_code_flag, CODE_16BIT},
1177 {"code32", set_code_flag, CODE_32BIT},
da5f19a2 1178#ifdef BFD64
29b0f896 1179 {"code64", set_code_flag, CODE_64BIT},
da5f19a2 1180#endif
29b0f896
AM		 1181 {"intel_syntax", set_intel_syntax, 1},
1182 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 1183 {"intel_mnemonic", set_intel_mnemonic, 1},
1184 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 1185 {"allow_index_reg", set_allow_index_reg, 1},
1186 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 1187 {"sse_check", set_check, 0},
1188 {"operand_check", set_check, 1},
3b22753a
L		 1189#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1190 {"largecomm", handle_large_common, 0},
07a53e5c 1191#else
68d20676 1192 {"file", dwarf2_directive_file, 0},
07a53e5c
RH		 1193 {"loc", dwarf2_directive_loc, 0},
1194 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 1195#endif
6482c264
NC		 1196#ifdef TE_PE
1197 {"secrel32", pe_directive_secrel, 0},
1198#endif
29b0f896
AM		 1199 {0, 0, 0}
1200};
1201
1202/* For interface with expression (). */
1203extern char *input_line_pointer;
1204
1205/* Hash table for instruction mnemonic lookup. */
1206static struct hash_control *op_hash;
1207
1208/* Hash table for register lookup. */
1209static struct hash_control *reg_hash;
1210\f
ce8a8b2f
AM		 1211 /* Various efficient no-op patterns for aligning code labels.
1212 Note: Don't try to assemble the instructions in the comments.
1213 0L and 0w are not legal. */
62a02d25
L		 1214static const unsigned char f32_1[] =
1215 {0x90}; /* nop */
1216static const unsigned char f32_2[] =
1217 {0x66,0x90}; /* xchg %ax,%ax */
1218static const unsigned char f32_3[] =
1219 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1220static const unsigned char f32_4[] =
1221 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
62a02d25
L		 1222static const unsigned char f32_6[] =
1223 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1224static const unsigned char f32_7[] =
1225 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
62a02d25 1226static const unsigned char f16_3[] =
3ae729d5 1227 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
62a02d25 1228static const unsigned char f16_4[] =
3ae729d5
L		 1229 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1230static const unsigned char jump_disp8[] =
1231 {0xeb}; /* jmp disp8 */
1232static const unsigned char jump32_disp32[] =
1233 {0xe9}; /* jmp disp32 */
1234static const unsigned char jump16_disp32[] =
1235 {0x66,0xe9}; /* jmp disp32 */
62a02d25
L		 1236/* 32-bit NOPs patterns. */
1237static const unsigned char *const f32_patt[] = {
3ae729d5 1238 f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7
62a02d25
L		 1239};
1240/* 16-bit NOPs patterns. */
1241static const unsigned char *const f16_patt[] = {
3ae729d5 1242 f32_1, f32_2, f16_3, f16_4
62a02d25
L		 1243};
1244/* nopl (%[re]ax) */
1245static const unsigned char alt_3[] =
1246 {0x0f,0x1f,0x00};
1247/* nopl 0(%[re]ax) */
1248static const unsigned char alt_4[] =
1249 {0x0f,0x1f,0x40,0x00};
1250/* nopl 0(%[re]ax,%[re]ax,1) */
1251static const unsigned char alt_5[] =
1252 {0x0f,0x1f,0x44,0x00,0x00};
1253/* nopw 0(%[re]ax,%[re]ax,1) */
1254static const unsigned char alt_6[] =
1255 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1256/* nopl 0L(%[re]ax) */
1257static const unsigned char alt_7[] =
1258 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1259/* nopl 0L(%[re]ax,%[re]ax,1) */
1260static const unsigned char alt_8[] =
1261 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1262/* nopw 0L(%[re]ax,%[re]ax,1) */
1263static const unsigned char alt_9[] =
1264 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1265/* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1266static const unsigned char alt_10[] =
1267 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
3ae729d5
L		 1268/* data16 nopw %cs:0L(%eax,%eax,1) */
1269static const unsigned char alt_11[] =
1270 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
62a02d25
L		 1271/* 32-bit and 64-bit NOPs patterns. */
1272static const unsigned char *const alt_patt[] = {
1273 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
3ae729d5 1274 alt_9, alt_10, alt_11
62a02d25
L		 1275};
1276
1277/* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1278 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1279
1280static void
1281i386_output_nops (char *where, const unsigned char *const *patt,
1282 int count, int max_single_nop_size)
1283
1284{
3ae729d5
L		 1285 /* Place the longer NOP first. */
1286 int last;
1287 int offset;
1288 const unsigned char *nops = patt[max_single_nop_size - 1];
1289
1290 /* Use the smaller one if the requsted one isn't available. */
1291 if (nops == NULL)
62a02d25 1292 {
3ae729d5
L		 1293 max_single_nop_size--;
1294 nops = patt[max_single_nop_size - 1];
62a02d25
L		 1295 }
1296
3ae729d5
L		 1297 last = count % max_single_nop_size;
1298
1299 count -= last;
1300 for (offset = 0; offset < count; offset += max_single_nop_size)
1301 memcpy (where + offset, nops, max_single_nop_size);
1302
1303 if (last)
1304 {
1305 nops = patt[last - 1];
1306 if (nops == NULL)
1307 {
1308 /* Use the smaller one plus one-byte NOP if the needed one
1309 isn't available. */
1310 last--;
1311 nops = patt[last - 1];
1312 memcpy (where + offset, nops, last);
1313 where[offset + last] = *patt[0];
1314 }
1315 else
1316 memcpy (where + offset, nops, last);
1317 }
62a02d25
L		 1318}
1319
3ae729d5
L		 1320static INLINE int
1321fits_in_imm7 (offsetT num)
1322{
1323 return (num & 0x7f) == num;
1324}
1325
1326static INLINE int
1327fits_in_imm31 (offsetT num)
1328{
1329 return (num & 0x7fffffff) == num;
1330}
62a02d25
L		 1331
1332/* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1333 single NOP instruction LIMIT. */
1334
1335void
3ae729d5 1336i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit)
62a02d25 1337{
3ae729d5 1338 const unsigned char *const *patt = NULL;
62a02d25 1339 int max_single_nop_size;
3ae729d5
L		 1340 /* Maximum number of NOPs before switching to jump over NOPs. */
1341 int max_number_of_nops;
62a02d25 1342
3ae729d5 1343 switch (fragP->fr_type)
62a02d25 1344 {
3ae729d5
L		 1345 case rs_fill_nop:
1346 case rs_align_code:
1347 break;
1348 default:
62a02d25
L		 1349 return;
1350 }
1351
ccc9c027
L		 1352 /* We need to decide which NOP sequence to use for 32bit and
1353 64bit. When -mtune= is used:
4eed87de 1354
76bc74dc
L		 1355 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1356 PROCESSOR_GENERIC32, f32_patt will be used.
80b8656c
L		 1357 2. For the rest, alt_patt will be used.
1358
1359 When -mtune= isn't used, alt_patt will be used if
22109423 1360 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1361 be used.
ccc9c027
L		 1362
1363 When -march= or .arch is used, we can't use anything beyond
1364 cpu_arch_isa_flags. */
1365
1366 if (flag_code == CODE_16BIT)
1367 {
3ae729d5
L		 1368 patt = f16_patt;
1369 max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]);
1370 /* Limit number of NOPs to 2 in 16-bit mode. */
1371 max_number_of_nops = 2;
252b5132 1372 }
33fef721 1373 else
ccc9c027 1374 {
fbf3f584 1375 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1376 {
1377 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1378 switch (cpu_arch_tune)
1379 {
1380 case PROCESSOR_UNKNOWN:
1381 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1382 optimize with nops. */
1383 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1384 patt = alt_patt;
ccc9c027
L		 1385 else
1386 patt = f32_patt;
1387 break;
ccc9c027
L		 1388 case PROCESSOR_PENTIUM4:
1389 case PROCESSOR_NOCONA:
ef05d495 1390 case PROCESSOR_CORE:
76bc74dc 1391 case PROCESSOR_CORE2:
bd5295b2 1392 case PROCESSOR_COREI7:
3632d14b 1393 case PROCESSOR_L1OM:
7a9068fe 1394 case PROCESSOR_K1OM:
76bc74dc 1395 case PROCESSOR_GENERIC64:
ccc9c027
L		 1396 case PROCESSOR_K6:
1397 case PROCESSOR_ATHLON:
1398 case PROCESSOR_K8:
4eed87de 1399 case PROCESSOR_AMDFAM10:
8aedb9fe 1400 case PROCESSOR_BD:
029f3522 1401 case PROCESSOR_ZNVER:
7b458c12 1402 case PROCESSOR_BT:
80b8656c 1403 patt = alt_patt;
ccc9c027 1404 break;
76bc74dc 1405 case PROCESSOR_I386:
ccc9c027
L		 1406 case PROCESSOR_I486:
1407 case PROCESSOR_PENTIUM:
2dde1948 1408 case PROCESSOR_PENTIUMPRO:
81486035 1409 case PROCESSOR_IAMCU:
ccc9c027
L		 1410 case PROCESSOR_GENERIC32:
1411 patt = f32_patt;
1412 break;
4eed87de 1413 }
ccc9c027
L		 1414 }
1415 else
1416 {
fbf3f584 1417 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1418 {
1419 case PROCESSOR_UNKNOWN:
e6a14101 1420 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1421 PROCESSOR_UNKNOWN. */
1422 abort ();
1423 break;
1424
76bc74dc 1425 case PROCESSOR_I386:
ccc9c027
L		 1426 case PROCESSOR_I486:
1427 case PROCESSOR_PENTIUM:
81486035 1428 case PROCESSOR_IAMCU:
ccc9c027
L		 1429 case PROCESSOR_K6:
1430 case PROCESSOR_ATHLON:
1431 case PROCESSOR_K8:
4eed87de 1432 case PROCESSOR_AMDFAM10:
8aedb9fe 1433 case PROCESSOR_BD:
029f3522 1434 case PROCESSOR_ZNVER:
7b458c12 1435 case PROCESSOR_BT:
ccc9c027
L		 1436 case PROCESSOR_GENERIC32:
1437 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1438 with nops. */
1439 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1440 patt = alt_patt;
ccc9c027
L		 1441 else
1442 patt = f32_patt;
1443 break;
76bc74dc
L		 1444 case PROCESSOR_PENTIUMPRO:
1445 case PROCESSOR_PENTIUM4:
1446 case PROCESSOR_NOCONA:
1447 case PROCESSOR_CORE:
ef05d495 1448 case PROCESSOR_CORE2:
bd5295b2 1449 case PROCESSOR_COREI7:
3632d14b 1450 case PROCESSOR_L1OM:
7a9068fe 1451 case PROCESSOR_K1OM:
22109423 1452 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1453 patt = alt_patt;
ccc9c027
L		 1454 else
1455 patt = f32_patt;
1456 break;
1457 case PROCESSOR_GENERIC64:
80b8656c 1458 patt = alt_patt;
ccc9c027 1459 break;
4eed87de 1460 }
ccc9c027
L		 1461 }
1462
76bc74dc
L		 1463 if (patt == f32_patt)
1464 {
3ae729d5
L		 1465 max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]);
1466 /* Limit number of NOPs to 2 for older processors. */
1467 max_number_of_nops = 2;
76bc74dc
L		 1468 }
1469 else
1470 {
3ae729d5
L		 1471 max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]);
1472 /* Limit number of NOPs to 7 for newer processors. */
1473 max_number_of_nops = 7;
1474 }
1475 }
1476
1477 if (limit == 0)
1478 limit = max_single_nop_size;
1479
1480 if (fragP->fr_type == rs_fill_nop)
1481 {
1482 /* Output NOPs for .nop directive. */
1483 if (limit > max_single_nop_size)
1484 {
1485 as_bad_where (fragP->fr_file, fragP->fr_line,
1486 _("invalid single nop size: %d "
1487 "(expect within [0, %d])"),
1488 limit, max_single_nop_size);
1489 return;
1490 }
1491 }
1492 else
1493 fragP->fr_var = count;
1494
1495 if ((count / max_single_nop_size) > max_number_of_nops)
1496 {
1497 /* Generate jump over NOPs. */
1498 offsetT disp = count - 2;
1499 if (fits_in_imm7 (disp))
1500 {
1501 /* Use "jmp disp8" if possible. */
1502 count = disp;
1503 where[0] = jump_disp8[0];
1504 where[1] = count;
1505 where += 2;
1506 }
1507 else
1508 {
1509 unsigned int size_of_jump;
1510
1511 if (flag_code == CODE_16BIT)
1512 {
1513 where[0] = jump16_disp32[0];
1514 where[1] = jump16_disp32[1];
1515 size_of_jump = 2;
1516 }
1517 else
1518 {
1519 where[0] = jump32_disp32[0];
1520 size_of_jump = 1;
1521 }
1522
1523 count -= size_of_jump + 4;
1524 if (!fits_in_imm31 (count))
1525 {
1526 as_bad_where (fragP->fr_file, fragP->fr_line,
1527 _("jump over nop padding out of range"));
1528 return;
1529 }
1530
1531 md_number_to_chars (where + size_of_jump, count, 4);
1532 where += size_of_jump + 4;
76bc74dc 1533 }
ccc9c027 1534 }
3ae729d5
L		 1535
1536 /* Generate multiple NOPs. */
1537 i386_output_nops (where, patt, count, limit);
252b5132
RH		 1538}
1539
c6fb90c8 1540static INLINE int
0dfbf9d7 1541operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1542{
0dfbf9d7 1543 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1544 {
1545 case 3:
0dfbf9d7 1546 if (x->array[2])
c6fb90c8 1547 return 0;
1a0670f3 1548 /* Fall through. */
c6fb90c8 1549 case 2:
0dfbf9d7 1550 if (x->array[1])
c6fb90c8 1551 return 0;
1a0670f3 1552 /* Fall through. */
c6fb90c8 1553 case 1:
0dfbf9d7 1554 return !x->array[0];
c6fb90c8
L		 1555 default:
1556 abort ();
1557 }
40fb9820
L		 1558}
1559
c6fb90c8 1560static INLINE void
0dfbf9d7 1561operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1562{
0dfbf9d7 1563 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1564 {
1565 case 3:
0dfbf9d7 1566 x->array[2] = v;
1a0670f3 1567 /* Fall through. */
c6fb90c8 1568 case 2:
0dfbf9d7 1569 x->array[1] = v;
1a0670f3 1570 /* Fall through. */
c6fb90c8 1571 case 1:
0dfbf9d7 1572 x->array[0] = v;
1a0670f3 1573 /* Fall through. */
c6fb90c8
L		 1574 break;
1575 default:
1576 abort ();
1577 }
1578}
40fb9820 1579
c6fb90c8 1580static INLINE int
0dfbf9d7
L		 1581operand_type_equal (const union i386_operand_type *x,
1582 const union i386_operand_type *y)
c6fb90c8 1583{
0dfbf9d7 1584 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1585 {
1586 case 3:
0dfbf9d7 1587 if (x->array[2] != y->array[2])
c6fb90c8 1588 return 0;
1a0670f3 1589 /* Fall through. */
c6fb90c8 1590 case 2:
0dfbf9d7 1591 if (x->array[1] != y->array[1])
c6fb90c8 1592 return 0;
1a0670f3 1593 /* Fall through. */
c6fb90c8 1594 case 1:
0dfbf9d7 1595 return x->array[0] == y->array[0];
c6fb90c8
L		 1596 break;
1597 default:
1598 abort ();
1599 }
1600}
40fb9820 1601
0dfbf9d7
L		 1602static INLINE int
1603cpu_flags_all_zero (const union i386_cpu_flags *x)
1604{
1605 switch (ARRAY_SIZE(x->array))
1606 {
53467f57
IT		 1607 case 4:
1608 if (x->array[3])
1609 return 0;
1610 /* Fall through. */
0dfbf9d7
L		 1611 case 3:
1612 if (x->array[2])
1613 return 0;
1a0670f3 1614 /* Fall through. */
0dfbf9d7
L		 1615 case 2:
1616 if (x->array[1])
1617 return 0;
1a0670f3 1618 /* Fall through. */
0dfbf9d7
L		 1619 case 1:
1620 return !x->array[0];
1621 default:
1622 abort ();
1623 }
1624}
1625
0dfbf9d7
L		 1626static INLINE int
1627cpu_flags_equal (const union i386_cpu_flags *x,
1628 const union i386_cpu_flags *y)
1629{
1630 switch (ARRAY_SIZE(x->array))
1631 {
53467f57
IT		 1632 case 4:
1633 if (x->array[3] != y->array[3])
1634 return 0;
1635 /* Fall through. */
0dfbf9d7
L		 1636 case 3:
1637 if (x->array[2] != y->array[2])
1638 return 0;
1a0670f3 1639 /* Fall through. */
0dfbf9d7
L		 1640 case 2:
1641 if (x->array[1] != y->array[1])
1642 return 0;
1a0670f3 1643 /* Fall through. */
0dfbf9d7
L		 1644 case 1:
1645 return x->array[0] == y->array[0];
1646 break;
1647 default:
1648 abort ();
1649 }
1650}
c6fb90c8
L		 1651
1652static INLINE int
1653cpu_flags_check_cpu64 (i386_cpu_flags f)
1654{
1655 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1656 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1657}
1658
c6fb90c8
L		 1659static INLINE i386_cpu_flags
1660cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1661{
c6fb90c8
L		 1662 switch (ARRAY_SIZE (x.array))
1663 {
53467f57
IT		 1664 case 4:
1665 x.array [3] &= y.array [3];
1666 /* Fall through. */
c6fb90c8
L		 1667 case 3:
1668 x.array [2] &= y.array [2];
1a0670f3 1669 /* Fall through. */
c6fb90c8
L		 1670 case 2:
1671 x.array [1] &= y.array [1];
1a0670f3 1672 /* Fall through. */
c6fb90c8
L		 1673 case 1:
1674 x.array [0] &= y.array [0];
1675 break;
1676 default:
1677 abort ();
1678 }
1679 return x;
1680}
40fb9820 1681
c6fb90c8
L		 1682static INLINE i386_cpu_flags
1683cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1684{
c6fb90c8 1685 switch (ARRAY_SIZE (x.array))
40fb9820 1686 {
53467f57
IT		 1687 case 4:
1688 x.array [3] |= y.array [3];
1689 /* Fall through. */
c6fb90c8
L		 1690 case 3:
1691 x.array [2] |= y.array [2];
1a0670f3 1692 /* Fall through. */
c6fb90c8
L		 1693 case 2:
1694 x.array [1] |= y.array [1];
1a0670f3 1695 /* Fall through. */
c6fb90c8
L		 1696 case 1:
1697 x.array [0] |= y.array [0];
40fb9820
L		 1698 break;
1699 default:
1700 abort ();
1701 }
40fb9820
L		 1702 return x;
1703}
1704
309d3373
JB		 1705static INLINE i386_cpu_flags
1706cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1707{
1708 switch (ARRAY_SIZE (x.array))
1709 {
53467f57
IT		 1710 case 4:
1711 x.array [3] &= ~y.array [3];
1712 /* Fall through. */
309d3373
JB		 1713 case 3:
1714 x.array [2] &= ~y.array [2];
1a0670f3 1715 /* Fall through. */
309d3373
JB		 1716 case 2:
1717 x.array [1] &= ~y.array [1];
1a0670f3 1718 /* Fall through. */
309d3373
JB		 1719 case 1:
1720 x.array [0] &= ~y.array [0];
1721 break;
1722 default:
1723 abort ();
1724 }
1725 return x;
1726}
1727
c0f3af97
L		 1728#define CPU_FLAGS_ARCH_MATCH 0x1
1729#define CPU_FLAGS_64BIT_MATCH 0x2
1730
c0f3af97 1731#define CPU_FLAGS_PERFECT_MATCH \
db12e14e 1732 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
c0f3af97
L		 1733
1734/* Return CPU flags match bits. */
3629bb00 1735
40fb9820 1736static int
d3ce72d0 1737cpu_flags_match (const insn_template *t)
40fb9820 1738{
c0f3af97
L		 1739 i386_cpu_flags x = t->cpu_flags;
1740 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1741
1742 x.bitfield.cpu64 = 0;
1743 x.bitfield.cpuno64 = 0;
1744
0dfbf9d7 1745 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1746 {
1747 /* This instruction is available on all archs. */
db12e14e 1748 match |= CPU_FLAGS_ARCH_MATCH;
c0f3af97 1749 }
3629bb00
L		 1750 else
1751 {
c0f3af97 1752 /* This instruction is available only on some archs. */
3629bb00
L		 1753 i386_cpu_flags cpu = cpu_arch_flags;
1754
ab592e75
JB		 1755 /* AVX512VL is no standalone feature - match it and then strip it. */
1756 if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl)
1757 return match;
1758 x.bitfield.cpuavx512vl = 0;
1759
3629bb00 1760 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1761 if (!cpu_flags_all_zero (&cpu))
1762 {
a5ff0eb2
L		 1763 if (x.bitfield.cpuavx)
1764 {
929f69fa 1765 /* We need to check a few extra flags with AVX. */
b9d49817
JB		 1766 if (cpu.bitfield.cpuavx
1767 && (!t->opcode_modifier.sse2avx || sse2avx)
1768 && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
929f69fa 1769 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
b9d49817
JB		 1770 && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul))
1771 match |= CPU_FLAGS_ARCH_MATCH;
a5ff0eb2 1772 }
929f69fa
JB		 1773 else if (x.bitfield.cpuavx512f)
1774 {
1775 /* We need to check a few extra flags with AVX512F. */
1776 if (cpu.bitfield.cpuavx512f
1777 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1778 && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes)
1779 && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq))
1780 match |= CPU_FLAGS_ARCH_MATCH;
1781 }
a5ff0eb2 1782 else
db12e14e 1783 match |= CPU_FLAGS_ARCH_MATCH;
c0f3af97 1784 }
3629bb00 1785 }
c0f3af97 1786 return match;
40fb9820
L		 1787}
1788
c6fb90c8
L		 1789static INLINE i386_operand_type
1790operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1791{
c6fb90c8
L		 1792 switch (ARRAY_SIZE (x.array))
1793 {
1794 case 3:
1795 x.array [2] &= y.array [2];
1a0670f3 1796 /* Fall through. */
c6fb90c8
L		 1797 case 2:
1798 x.array [1] &= y.array [1];
1a0670f3 1799 /* Fall through. */
c6fb90c8
L		 1800 case 1:
1801 x.array [0] &= y.array [0];
1802 break;
1803 default:
1804 abort ();
1805 }
1806 return x;
40fb9820
L		 1807}
1808
73053c1f
JB		 1809static INLINE i386_operand_type
1810operand_type_and_not (i386_operand_type x, i386_operand_type y)
1811{
1812 switch (ARRAY_SIZE (x.array))
1813 {
1814 case 3:
1815 x.array [2] &= ~y.array [2];
1816 /* Fall through. */
1817 case 2:
1818 x.array [1] &= ~y.array [1];
1819 /* Fall through. */
1820 case 1:
1821 x.array [0] &= ~y.array [0];
1822 break;
1823 default:
1824 abort ();
1825 }
1826 return x;
1827}
1828
c6fb90c8
L		 1829static INLINE i386_operand_type
1830operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1831{
c6fb90c8 1832 switch (ARRAY_SIZE (x.array))
40fb9820 1833 {
c6fb90c8
L		 1834 case 3:
1835 x.array [2] |= y.array [2];
1a0670f3 1836 /* Fall through. */
c6fb90c8
L		 1837 case 2:
1838 x.array [1] |= y.array [1];
1a0670f3 1839 /* Fall through. */
c6fb90c8
L		 1840 case 1:
1841 x.array [0] |= y.array [0];
40fb9820
L		 1842 break;
1843 default:
1844 abort ();
1845 }
c6fb90c8
L		 1846 return x;
1847}
40fb9820 1848
c6fb90c8
L		 1849static INLINE i386_operand_type
1850operand_type_xor (i386_operand_type x, i386_operand_type y)
1851{
1852 switch (ARRAY_SIZE (x.array))
1853 {
1854 case 3:
1855 x.array [2] ^= y.array [2];
1a0670f3 1856 /* Fall through. */
c6fb90c8
L		 1857 case 2:
1858 x.array [1] ^= y.array [1];
1a0670f3 1859 /* Fall through. */
c6fb90c8
L		 1860 case 1:
1861 x.array [0] ^= y.array [0];
1862 break;
1863 default:
1864 abort ();
1865 }
40fb9820
L		 1866 return x;
1867}
1868
1869static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1870static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
40fb9820
L		 1871static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1872static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1873static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1874static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1875static const i386_operand_type anydisp
1876 = OPERAND_TYPE_ANYDISP;
40fb9820 1877static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
43234a1e 1878static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
40fb9820
L		 1879static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1880static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1881static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1882static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1883static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1884static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1885static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1886static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1887static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1888static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1889
1890enum operand_type
1891{
1892 reg,
40fb9820
L		 1893 imm,
1894 disp,
1895 anymem
1896};
1897
c6fb90c8 1898static INLINE int
40fb9820
L		 1899operand_type_check (i386_operand_type t, enum operand_type c)
1900{
1901 switch (c)
1902 {
1903 case reg:
dc821c5f 1904 return t.bitfield.reg;
40fb9820 1905
40fb9820
L		 1906 case imm:
1907 return (t.bitfield.imm8
1908 || t.bitfield.imm8s
1909 || t.bitfield.imm16
1910 || t.bitfield.imm32
1911 || t.bitfield.imm32s
1912 || t.bitfield.imm64);
1913
1914 case disp:
1915 return (t.bitfield.disp8
1916 || t.bitfield.disp16
1917 || t.bitfield.disp32
1918 || t.bitfield.disp32s
1919 || t.bitfield.disp64);
1920
1921 case anymem:
1922 return (t.bitfield.disp8
1923 || t.bitfield.disp16
1924 || t.bitfield.disp32
1925 || t.bitfield.disp32s
1926 || t.bitfield.disp64
1927 || t.bitfield.baseindex);
1928
1929 default:
1930 abort ();
1931 }
2cfe26b6
AM		 1932
1933 return 0;
40fb9820
L		 1934}
1935
7a54636a
L		 1936/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
1937 between operand GIVEN and opeand WANTED for instruction template T. */
5c07affc
L		 1938
1939static INLINE int
7a54636a
L		 1940match_operand_size (const insn_template *t, unsigned int wanted,
1941 unsigned int given)
5c07affc 1942{
3ac21baa
JB		 1943 return !((i.types[given].bitfield.byte
1944 && !t->operand_types[wanted].bitfield.byte)
1945 || (i.types[given].bitfield.word
1946 && !t->operand_types[wanted].bitfield.word)
1947 || (i.types[given].bitfield.dword
1948 && !t->operand_types[wanted].bitfield.dword)
1949 || (i.types[given].bitfield.qword
1950 && !t->operand_types[wanted].bitfield.qword)
1951 || (i.types[given].bitfield.tbyte
1952 && !t->operand_types[wanted].bitfield.tbyte));
5c07affc
L		 1953}
1954
dd40ce22
L		 1955/* Return 1 if there is no conflict in SIMD register between operand
1956 GIVEN and opeand WANTED for instruction template T. */
1b54b8d7
JB		 1957
1958static INLINE int
dd40ce22
L		 1959match_simd_size (const insn_template *t, unsigned int wanted,
1960 unsigned int given)
1b54b8d7 1961{
3ac21baa
JB		 1962 return !((i.types[given].bitfield.xmmword
1963 && !t->operand_types[wanted].bitfield.xmmword)
1964 || (i.types[given].bitfield.ymmword
1965 && !t->operand_types[wanted].bitfield.ymmword)
1966 || (i.types[given].bitfield.zmmword
1967 && !t->operand_types[wanted].bitfield.zmmword));
1b54b8d7
JB		 1968}
1969
7a54636a
L		 1970/* Return 1 if there is no conflict in any size between operand GIVEN
1971 and opeand WANTED for instruction template T. */
5c07affc
L		 1972
1973static INLINE int
dd40ce22
L		 1974match_mem_size (const insn_template *t, unsigned int wanted,
1975 unsigned int given)
5c07affc 1976{
7a54636a 1977 return (match_operand_size (t, wanted, given)
3ac21baa 1978 && !((i.types[given].bitfield.unspecified
af508cb9 1979 && !i.broadcast
3ac21baa
JB		 1980 && !t->operand_types[wanted].bitfield.unspecified)
1981 || (i.types[given].bitfield.fword
1982 && !t->operand_types[wanted].bitfield.fword)
1b54b8d7
JB		 1983 /* For scalar opcode templates to allow register and memory
1984 operands at the same time, some special casing is needed
d6793fa1
JB		 1985 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
1986 down-conversion vpmov*. */
3ac21baa 1987 || ((t->operand_types[wanted].bitfield.regsimd
1b54b8d7 1988 && !t->opcode_modifier.broadcast
3ac21baa
JB		 1989 && (t->operand_types[wanted].bitfield.byte
1990 || t->operand_types[wanted].bitfield.word
1991 || t->operand_types[wanted].bitfield.dword
1992 || t->operand_types[wanted].bitfield.qword))
1993 ? (i.types[given].bitfield.xmmword
1994 || i.types[given].bitfield.ymmword
1995 || i.types[given].bitfield.zmmword)
1996 : !match_simd_size(t, wanted, given))));
5c07affc
L		 1997}
1998
3ac21baa
JB		 1999/* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2000 operands for instruction template T, and it has MATCH_REVERSE set if there
2001 is no size conflict on any operands for the template with operands reversed
2002 (and the template allows for reversing in the first place). */
5c07affc 2003
3ac21baa
JB		 2004#define MATCH_STRAIGHT 1
2005#define MATCH_REVERSE 2
2006
2007static INLINE unsigned int
d3ce72d0 2008operand_size_match (const insn_template *t)
5c07affc 2009{
3ac21baa 2010 unsigned int j, match = MATCH_STRAIGHT;
5c07affc
L		 2011
2012 /* Don't check jump instructions. */
2013 if (t->opcode_modifier.jump
2014 || t->opcode_modifier.jumpbyte
2015 || t->opcode_modifier.jumpdword
2016 || t->opcode_modifier.jumpintersegment)
2017 return match;
2018
2019 /* Check memory and accumulator operand size. */
2020 for (j = 0; j < i.operands; j++)
2021 {
1b54b8d7
JB		 2022 if (!i.types[j].bitfield.reg && !i.types[j].bitfield.regsimd
2023 && t->operand_types[j].bitfield.anysize)
5c07affc
L		 2024 continue;
2025
1b54b8d7 2026 if (t->operand_types[j].bitfield.reg
7a54636a 2027 && !match_operand_size (t, j, j))
5c07affc
L		 2028 {
2029 match = 0;
2030 break;
2031 }
2032
1b54b8d7 2033 if (t->operand_types[j].bitfield.regsimd
3ac21baa 2034 && !match_simd_size (t, j, j))
1b54b8d7
JB		 2035 {
2036 match = 0;
2037 break;
2038 }
2039
2040 if (t->operand_types[j].bitfield.acc
7a54636a 2041 && (!match_operand_size (t, j, j) || !match_simd_size (t, j, j)))
1b54b8d7
JB		 2042 {
2043 match = 0;
2044 break;
2045 }
2046
c48dadc9 2047 if ((i.flags[j] & Operand_Mem) && !match_mem_size (t, j, j))
5c07affc
L		 2048 {
2049 match = 0;
2050 break;
2051 }
2052 }
2053
3ac21baa 2054 if (!t->opcode_modifier.d)
891edac4
L		 2055 {
2056mismatch:
3ac21baa
JB		 2057 if (!match)
2058 i.error = operand_size_mismatch;
2059 return match;
891edac4 2060 }
5c07affc
L		 2061
2062 /* Check reverse. */
f5eb1d70 2063 gas_assert (i.operands >= 2 && i.operands <= 3);
5c07affc 2064
f5eb1d70 2065 for (j = 0; j < i.operands; j++)
5c07affc 2066 {
f5eb1d70
JB		 2067 unsigned int given = i.operands - j - 1;
2068
dbbc8b7e 2069 if (t->operand_types[j].bitfield.reg
f5eb1d70 2070 && !match_operand_size (t, j, given))
891edac4 2071 goto mismatch;
5c07affc 2072
dbbc8b7e 2073 if (t->operand_types[j].bitfield.regsimd
f5eb1d70 2074 && !match_simd_size (t, j, given))
dbbc8b7e
JB		 2075 goto mismatch;
2076
2077 if (t->operand_types[j].bitfield.acc
f5eb1d70
JB		 2078 && (!match_operand_size (t, j, given)
2079 || !match_simd_size (t, j, given)))
dbbc8b7e
JB		 2080 goto mismatch;
2081
f5eb1d70 2082 if ((i.flags[given] & Operand_Mem) && !match_mem_size (t, j, given))
891edac4 2083 goto mismatch;
5c07affc
L		 2084 }
2085
3ac21baa 2086 return match | MATCH_REVERSE;
5c07affc
L		 2087}
2088
c6fb90c8 2089static INLINE int
40fb9820
L		 2090operand_type_match (i386_operand_type overlap,
2091 i386_operand_type given)
2092{
2093 i386_operand_type temp = overlap;
2094
2095 temp.bitfield.jumpabsolute = 0;
7d5e4556 2096 temp.bitfield.unspecified = 0;
5c07affc
L		 2097 temp.bitfield.byte = 0;
2098 temp.bitfield.word = 0;
2099 temp.bitfield.dword = 0;
2100 temp.bitfield.fword = 0;
2101 temp.bitfield.qword = 0;
2102 temp.bitfield.tbyte = 0;
2103 temp.bitfield.xmmword = 0;
c0f3af97 2104 temp.bitfield.ymmword = 0;
43234a1e 2105 temp.bitfield.zmmword = 0;
0dfbf9d7 2106 if (operand_type_all_zero (&temp))
891edac4 2107 goto mismatch;
40fb9820 2108
891edac4
L		 2109 if (given.bitfield.baseindex == overlap.bitfield.baseindex
2110 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
2111 return 1;
2112
2113mismatch:
a65babc9 2114 i.error = operand_type_mismatch;
891edac4 2115 return 0;
40fb9820
L		 2116}
2117
7d5e4556 2118/* If given types g0 and g1 are registers they must be of the same type
10c17abd
JB		 2119 unless the expected operand type register overlap is null.
2120 Memory operand size of certain SIMD instructions is also being checked
2121 here. */
40fb9820 2122
c6fb90c8 2123static INLINE int
dc821c5f 2124operand_type_register_match (i386_operand_type g0,
40fb9820 2125 i386_operand_type t0,
40fb9820
L		 2126 i386_operand_type g1,
2127 i386_operand_type t1)
2128{
10c17abd
JB		 2129 if (!g0.bitfield.reg
2130 && !g0.bitfield.regsimd
2131 && (!operand_type_check (g0, anymem)
2132 || g0.bitfield.unspecified
2133 || !t0.bitfield.regsimd))
40fb9820
L		 2134 return 1;
2135
10c17abd
JB		 2136 if (!g1.bitfield.reg
2137 && !g1.bitfield.regsimd
2138 && (!operand_type_check (g1, anymem)
2139 || g1.bitfield.unspecified
2140 || !t1.bitfield.regsimd))
40fb9820
L		 2141 return 1;
2142
dc821c5f
JB		 2143 if (g0.bitfield.byte == g1.bitfield.byte
2144 && g0.bitfield.word == g1.bitfield.word
2145 && g0.bitfield.dword == g1.bitfield.dword
10c17abd
JB		 2146 && g0.bitfield.qword == g1.bitfield.qword
2147 && g0.bitfield.xmmword == g1.bitfield.xmmword
2148 && g0.bitfield.ymmword == g1.bitfield.ymmword
2149 && g0.bitfield.zmmword == g1.bitfield.zmmword)
40fb9820
L		 2150 return 1;
2151
dc821c5f
JB		 2152 if (!(t0.bitfield.byte & t1.bitfield.byte)
2153 && !(t0.bitfield.word & t1.bitfield.word)
2154 && !(t0.bitfield.dword & t1.bitfield.dword)
10c17abd
JB		 2155 && !(t0.bitfield.qword & t1.bitfield.qword)
2156 && !(t0.bitfield.xmmword & t1.bitfield.xmmword)
2157 && !(t0.bitfield.ymmword & t1.bitfield.ymmword)
2158 && !(t0.bitfield.zmmword & t1.bitfield.zmmword))
891edac4
L		 2159 return 1;
2160
a65babc9 2161 i.error = register_type_mismatch;
891edac4
L		 2162
2163 return 0;
40fb9820
L		 2164}
2165
4c692bc7
JB		 2166static INLINE unsigned int
2167register_number (const reg_entry *r)
2168{
2169 unsigned int nr = r->reg_num;
2170
2171 if (r->reg_flags & RegRex)
2172 nr += 8;
2173
200cbe0f
L		 2174 if (r->reg_flags & RegVRex)
2175 nr += 16;
2176
4c692bc7
JB		 2177 return nr;
2178}
2179
252b5132 2180static INLINE unsigned int
40fb9820 2181mode_from_disp_size (i386_operand_type t)
252b5132 2182{
b5014f7a 2183 if (t.bitfield.disp8)
40fb9820
L		 2184 return 1;
2185 else if (t.bitfield.disp16
2186 || t.bitfield.disp32
2187 || t.bitfield.disp32s)
2188 return 2;
2189 else
2190 return 0;
252b5132
RH		 2191}
2192
2193static INLINE int
65879393 2194fits_in_signed_byte (addressT num)
252b5132 2195{
65879393 2196 return num + 0x80 <= 0xff;
47926f60 2197}
252b5132
RH		 2198
2199static INLINE int
65879393 2200fits_in_unsigned_byte (addressT num)
252b5132 2201{
65879393 2202 return num <= 0xff;
47926f60 2203}
252b5132
RH		 2204
2205static INLINE int
65879393 2206fits_in_unsigned_word (addressT num)
252b5132 2207{
65879393 2208 return num <= 0xffff;
47926f60 2209}
252b5132
RH		 2210
2211static INLINE int
65879393 2212fits_in_signed_word (addressT num)
252b5132 2213{
65879393 2214 return num + 0x8000 <= 0xffff;
47926f60 2215}
2a962e6d 2216
3e73aa7c 2217static INLINE int
65879393 2218fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 2219{
2220#ifndef BFD64
2221 return 1;
2222#else
65879393 2223 return num + 0x80000000 <= 0xffffffff;
3e73aa7c
JH		 2224#endif
2225} /* fits_in_signed_long() */
2a962e6d 2226
3e73aa7c 2227static INLINE int
65879393 2228fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 2229{
2230#ifndef BFD64
2231 return 1;
2232#else
65879393 2233 return num <= 0xffffffff;
3e73aa7c
JH		 2234#endif
2235} /* fits_in_unsigned_long() */
252b5132 2236
43234a1e 2237static INLINE int
b5014f7a 2238fits_in_disp8 (offsetT num)
43234a1e
L		 2239{
2240 int shift = i.memshift;
2241 unsigned int mask;
2242
2243 if (shift == -1)
2244 abort ();
2245
2246 mask = (1 << shift) - 1;
2247
2248 /* Return 0 if NUM isn't properly aligned. */
2249 if ((num & mask))
2250 return 0;
2251
2252 /* Check if NUM will fit in 8bit after shift. */
2253 return fits_in_signed_byte (num >> shift);
2254}
2255
a683cc34
SP		 2256static INLINE int
2257fits_in_imm4 (offsetT num)
2258{
2259 return (num & 0xf) == num;
2260}
2261
40fb9820 2262static i386_operand_type
e3bb37b5 2263smallest_imm_type (offsetT num)
252b5132 2264{
40fb9820 2265 i386_operand_type t;
7ab9ffdd 2266
0dfbf9d7 2267 operand_type_set (&t, 0);
40fb9820
L		 2268 t.bitfield.imm64 = 1;
2269
2270 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 2271 {
2272 /* This code is disabled on the 486 because all the Imm1 forms
2273 in the opcode table are slower on the i486. They're the
2274 versions with the implicitly specified single-position
2275 displacement, which has another syntax if you really want to
2276 use that form. */
40fb9820
L		 2277 t.bitfield.imm1 = 1;
2278 t.bitfield.imm8 = 1;
2279 t.bitfield.imm8s = 1;
2280 t.bitfield.imm16 = 1;
2281 t.bitfield.imm32 = 1;
2282 t.bitfield.imm32s = 1;
2283 }
2284 else if (fits_in_signed_byte (num))
2285 {
2286 t.bitfield.imm8 = 1;
2287 t.bitfield.imm8s = 1;
2288 t.bitfield.imm16 = 1;
2289 t.bitfield.imm32 = 1;
2290 t.bitfield.imm32s = 1;
2291 }
2292 else if (fits_in_unsigned_byte (num))
2293 {
2294 t.bitfield.imm8 = 1;
2295 t.bitfield.imm16 = 1;
2296 t.bitfield.imm32 = 1;
2297 t.bitfield.imm32s = 1;
2298 }
2299 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2300 {
2301 t.bitfield.imm16 = 1;
2302 t.bitfield.imm32 = 1;
2303 t.bitfield.imm32s = 1;
2304 }
2305 else if (fits_in_signed_long (num))
2306 {
2307 t.bitfield.imm32 = 1;
2308 t.bitfield.imm32s = 1;
2309 }
2310 else if (fits_in_unsigned_long (num))
2311 t.bitfield.imm32 = 1;
2312
2313 return t;
47926f60 2314}
252b5132 2315
847f7ad4 2316static offsetT
e3bb37b5 2317offset_in_range (offsetT val, int size)
847f7ad4 2318{
508866be 2319 addressT mask;
ba2adb93 2320
847f7ad4
AM		 2321 switch (size)
2322 {
508866be
L		 2323 case 1: mask = ((addressT) 1 << 8) - 1; break;
2324 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 2325 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 2326#ifdef BFD64
2327 case 8: mask = ((addressT) 2 << 63) - 1; break;
2328#endif
47926f60 2329 default: abort ();
847f7ad4
AM		 2330 }
2331
9de868bf
L		 2332#ifdef BFD64
2333 /* If BFD64, sign extend val for 32bit address mode. */
2334 if (flag_code != CODE_64BIT
2335 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 2336 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2337 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 2338#endif
ba2adb93 2339
47926f60 2340 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 2341 {
2342 char buf1[40], buf2[40];
2343
2344 sprint_value (buf1, val);
2345 sprint_value (buf2, val & mask);
2346 as_warn (_("%s shortened to %s"), buf1, buf2);
2347 }
2348 return val & mask;
2349}
2350
c32fa91d
L		 2351enum PREFIX_GROUP
2352{
2353 PREFIX_EXIST = 0,
2354 PREFIX_LOCK,
2355 PREFIX_REP,
04ef582a 2356 PREFIX_DS,
c32fa91d
L		 2357 PREFIX_OTHER
2358};
2359
2360/* Returns
2361 a. PREFIX_EXIST if attempting to add a prefix where one from the
2362 same class already exists.
2363 b. PREFIX_LOCK if lock prefix is added.
2364 c. PREFIX_REP if rep/repne prefix is added.
04ef582a
L		 2365 d. PREFIX_DS if ds prefix is added.
2366 e. PREFIX_OTHER if other prefix is added.
c32fa91d
L		 2367 */
2368
2369static enum PREFIX_GROUP
e3bb37b5 2370add_prefix (unsigned int prefix)
252b5132 2371{
c32fa91d 2372 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 2373 unsigned int q;
252b5132 2374
29b0f896
AM		 2375 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2376 && flag_code == CODE_64BIT)
b1905489 2377 {
161a04f6 2378 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
44846f29
JB		 2379 || (i.prefix[REX_PREFIX] & prefix & REX_R)
2380 || (i.prefix[REX_PREFIX] & prefix & REX_X)
2381 || (i.prefix[REX_PREFIX] & prefix & REX_B))
c32fa91d 2382 ret = PREFIX_EXIST;
b1905489
JB		 2383 q = REX_PREFIX;
2384 }
3e73aa7c 2385 else
b1905489
JB		 2386 {
2387 switch (prefix)
2388 {
2389 default:
2390 abort ();
2391
b1905489 2392 case DS_PREFIX_OPCODE:
04ef582a
L		 2393 ret = PREFIX_DS;
2394 /* Fall through. */
2395 case CS_PREFIX_OPCODE:
b1905489
JB		 2396 case ES_PREFIX_OPCODE:
2397 case FS_PREFIX_OPCODE:
2398 case GS_PREFIX_OPCODE:
2399 case SS_PREFIX_OPCODE:
2400 q = SEG_PREFIX;
2401 break;
2402
2403 case REPNE_PREFIX_OPCODE:
2404 case REPE_PREFIX_OPCODE:
c32fa91d
L		 2405 q = REP_PREFIX;
2406 ret = PREFIX_REP;
2407 break;
2408
b1905489 2409 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 2410 q = LOCK_PREFIX;
2411 ret = PREFIX_LOCK;
b1905489
JB		 2412 break;
2413
2414 case FWAIT_OPCODE:
2415 q = WAIT_PREFIX;
2416 break;
2417
2418 case ADDR_PREFIX_OPCODE:
2419 q = ADDR_PREFIX;
2420 break;
2421
2422 case DATA_PREFIX_OPCODE:
2423 q = DATA_PREFIX;
2424 break;
2425 }
2426 if (i.prefix[q] != 0)
c32fa91d 2427 ret = PREFIX_EXIST;
b1905489 2428 }
252b5132 2429
b1905489 2430 if (ret)
252b5132 2431 {
b1905489
JB		 2432 if (!i.prefix[q])
2433 ++i.prefixes;
2434 i.prefix[q] |= prefix;
252b5132 2435 }
b1905489
JB		 2436 else
2437 as_bad (_("same type of prefix used twice"));
252b5132 2438
252b5132
RH		 2439 return ret;
2440}
2441
2442static void
78f12dd3 2443update_code_flag (int value, int check)
eecb386c 2444{
78f12dd3
L		 2445 PRINTF_LIKE ((*as_error));
2446
1e9cc1c2 2447 flag_code = (enum flag_code) value;
40fb9820
L		 2448 if (flag_code == CODE_64BIT)
2449 {
2450 cpu_arch_flags.bitfield.cpu64 = 1;
2451 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2452 }
2453 else
2454 {
2455 cpu_arch_flags.bitfield.cpu64 = 0;
2456 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2457 }
2458 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2459 {
78f12dd3
L		 2460 if (check)
2461 as_error = as_fatal;
2462 else
2463 as_error = as_bad;
2464 (*as_error) (_("64bit mode not supported on `%s'."),
2465 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2466 }
40fb9820 2467 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2468 {
78f12dd3
L		 2469 if (check)
2470 as_error = as_fatal;
2471 else
2472 as_error = as_bad;
2473 (*as_error) (_("32bit mode not supported on `%s'."),
2474 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2475 }
eecb386c
AM		 2476 stackop_size = '\0';
2477}
2478
78f12dd3
L		 2479static void
2480set_code_flag (int value)
2481{
2482 update_code_flag (value, 0);
2483}
2484
eecb386c 2485static void
e3bb37b5 2486set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2487{
1e9cc1c2 2488 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2489 if (flag_code != CODE_16BIT)
2490 abort ();
2491 cpu_arch_flags.bitfield.cpu64 = 0;
2492 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2493 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2494}
2495
2496static void
e3bb37b5 2497set_intel_syntax (int syntax_flag)
252b5132
RH		 2498{
2499 /* Find out if register prefixing is specified. */
2500 int ask_naked_reg = 0;
2501
2502 SKIP_WHITESPACE ();
29b0f896 2503 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132 2504 {
d02603dc
NC		 2505 char *string;
2506 int e = get_symbol_name (&string);
252b5132 2507
47926f60 2508 if (strcmp (string, "prefix") == 0)
252b5132 2509 ask_naked_reg = 1;
47926f60 2510 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2511 ask_naked_reg = -1;
2512 else
d0b47220 2513 as_bad (_("bad argument to syntax directive."));
d02603dc 2514 (void) restore_line_pointer (e);
252b5132
RH		 2515 }
2516 demand_empty_rest_of_line ();
c3332e24 2517
252b5132
RH		 2518 intel_syntax = syntax_flag;
2519
2520 if (ask_naked_reg == 0)
f86103b7
AM		 2521 allow_naked_reg = (intel_syntax
2522 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2523 else
2524 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2525
ee86248c 2526 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2527
e4a3b5a4 2528 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2529 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2530 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2531}
2532
1efbbeb4
L		 2533static void
2534set_intel_mnemonic (int mnemonic_flag)
2535{
e1d4d893 2536 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2537}
2538
db51cc60
L		 2539static void
2540set_allow_index_reg (int flag)
2541{
2542 allow_index_reg = flag;
2543}
2544
cb19c032 2545static void
7bab8ab5 2546set_check (int what)
cb19c032 2547{
7bab8ab5
JB		 2548 enum check_kind *kind;
2549 const char *str;
2550
2551 if (what)
2552 {
2553 kind = &operand_check;
2554 str = "operand";
2555 }
2556 else
2557 {
2558 kind = &sse_check;
2559 str = "sse";
2560 }
2561
cb19c032
L		 2562 SKIP_WHITESPACE ();
2563
2564 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2565 {
d02603dc
NC		 2566 char *string;
2567 int e = get_symbol_name (&string);
cb19c032
L		 2568
2569 if (strcmp (string, "none") == 0)
7bab8ab5 2570 *kind = check_none;
cb19c032 2571 else if (strcmp (string, "warning") == 0)
7bab8ab5 2572 *kind = check_warning;
cb19c032 2573 else if (strcmp (string, "error") == 0)
7bab8ab5 2574 *kind = check_error;
cb19c032 2575 else
7bab8ab5 2576 as_bad (_("bad argument to %s_check directive."), str);
d02603dc 2577 (void) restore_line_pointer (e);
cb19c032
L		 2578 }
2579 else
7bab8ab5 2580 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2581
2582 demand_empty_rest_of_line ();
2583}
2584
8a9036a4
L		 2585static void
2586check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2587 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2588{
2589#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2590 static const char *arch;
2591
2592 /* Intel LIOM is only supported on ELF. */
2593 if (!IS_ELF)
2594 return;
2595
2596 if (!arch)
2597 {
2598 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2599 use default_arch. */
2600 arch = cpu_arch_name;
2601 if (!arch)
2602 arch = default_arch;
2603 }
2604
81486035
L		 2605 /* If we are targeting Intel MCU, we must enable it. */
2606 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2607 || new_flag.bitfield.cpuiamcu)
2608 return;
2609
3632d14b 2610 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2611 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2612 || new_flag.bitfield.cpul1om)
8a9036a4 2613 return;
76ba9986 2614
7a9068fe
L		 2615 /* If we are targeting Intel K1OM, we must enable it. */
2616 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2617 || new_flag.bitfield.cpuk1om)
2618 return;
2619
8a9036a4
L		 2620 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2621#endif
2622}
2623
e413e4e9 2624static void
e3bb37b5 2625set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2626{
47926f60 2627 SKIP_WHITESPACE ();
e413e4e9 2628
29b0f896 2629 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9 2630 {
d02603dc
NC		 2631 char *string;
2632 int e = get_symbol_name (&string);
91d6fa6a 2633 unsigned int j;
40fb9820 2634 i386_cpu_flags flags;
e413e4e9 2635
91d6fa6a 2636 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2637 {
91d6fa6a 2638 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2639 {
91d6fa6a 2640 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2641
5c6af06e
JB		 2642 if (*string != '.')
2643 {
91d6fa6a 2644 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2645 cpu_sub_arch_name = NULL;
91d6fa6a 2646 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2647 if (flag_code == CODE_64BIT)
2648 {
2649 cpu_arch_flags.bitfield.cpu64 = 1;
2650 cpu_arch_flags.bitfield.cpuno64 = 0;
2651 }
2652 else
2653 {
2654 cpu_arch_flags.bitfield.cpu64 = 0;
2655 cpu_arch_flags.bitfield.cpuno64 = 1;
2656 }
91d6fa6a
NC		 2657 cpu_arch_isa = cpu_arch[j].type;
2658 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2659 if (!cpu_arch_tune_set)
2660 {
2661 cpu_arch_tune = cpu_arch_isa;
2662 cpu_arch_tune_flags = cpu_arch_isa_flags;
2663 }
5c6af06e
JB		 2664 break;
2665 }
40fb9820 2666
293f5f65
L		 2667 flags = cpu_flags_or (cpu_arch_flags,
2668 cpu_arch[j].flags);
81486035 2669
5b64d091 2670 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2671 {
6305a203
L		 2672 if (cpu_sub_arch_name)
2673 {
2674 char *name = cpu_sub_arch_name;
2675 cpu_sub_arch_name = concat (name,
91d6fa6a 2676 cpu_arch[j].name,
1bf57e9f 2677 (const char *) NULL);
6305a203
L		 2678 free (name);
2679 }
2680 else
91d6fa6a 2681 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2682 cpu_arch_flags = flags;
a586129e 2683 cpu_arch_isa_flags = flags;
5c6af06e 2684 }
0089dace
L		 2685 else
2686 cpu_arch_isa_flags
2687 = cpu_flags_or (cpu_arch_isa_flags,
2688 cpu_arch[j].flags);
d02603dc 2689 (void) restore_line_pointer (e);
5c6af06e
JB		 2690 demand_empty_rest_of_line ();
2691 return;
e413e4e9
AM		 2692 }
2693 }
293f5f65
L		 2694
2695 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2696 {
33eaf5de 2697 /* Disable an ISA extension. */
293f5f65
L		 2698 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2699 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2700 {
2701 flags = cpu_flags_and_not (cpu_arch_flags,
2702 cpu_noarch[j].flags);
2703 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2704 {
2705 if (cpu_sub_arch_name)
2706 {
2707 char *name = cpu_sub_arch_name;
2708 cpu_sub_arch_name = concat (name, string,
2709 (const char *) NULL);
2710 free (name);
2711 }
2712 else
2713 cpu_sub_arch_name = xstrdup (string);
2714 cpu_arch_flags = flags;
2715 cpu_arch_isa_flags = flags;
2716 }
2717 (void) restore_line_pointer (e);
2718 demand_empty_rest_of_line ();
2719 return;
2720 }
2721
2722 j = ARRAY_SIZE (cpu_arch);
2723 }
2724
91d6fa6a 2725 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2726 as_bad (_("no such architecture: `%s'"), string);
2727
2728 *input_line_pointer = e;
2729 }
2730 else
2731 as_bad (_("missing cpu architecture"));
2732
fddf5b5b
AM		 2733 no_cond_jump_promotion = 0;
2734 if (*input_line_pointer == ','
29b0f896 2735 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b 2736 {
d02603dc
NC		 2737 char *string;
2738 char e;
2739
2740 ++input_line_pointer;
2741 e = get_symbol_name (&string);
fddf5b5b
AM		 2742
2743 if (strcmp (string, "nojumps") == 0)
2744 no_cond_jump_promotion = 1;
2745 else if (strcmp (string, "jumps") == 0)
2746 ;
2747 else
2748 as_bad (_("no such architecture modifier: `%s'"), string);
2749
d02603dc 2750 (void) restore_line_pointer (e);
fddf5b5b
AM		 2751 }
2752
e413e4e9
AM		 2753 demand_empty_rest_of_line ();
2754}
2755
8a9036a4
L		 2756enum bfd_architecture
2757i386_arch (void)
2758{
3632d14b 2759 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2760 {
2761 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2762 || flag_code != CODE_64BIT)
2763 as_fatal (_("Intel L1OM is 64bit ELF only"));
2764 return bfd_arch_l1om;
2765 }
7a9068fe
L		 2766 else if (cpu_arch_isa == PROCESSOR_K1OM)
2767 {
2768 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2769 || flag_code != CODE_64BIT)
2770 as_fatal (_("Intel K1OM is 64bit ELF only"));
2771 return bfd_arch_k1om;
2772 }
81486035
L		 2773 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2774 {
2775 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2776 || flag_code == CODE_64BIT)
2777 as_fatal (_("Intel MCU is 32bit ELF only"));
2778 return bfd_arch_iamcu;
2779 }
8a9036a4
L		 2780 else
2781 return bfd_arch_i386;
2782}
2783
b9d79e03 2784unsigned long
7016a5d5 2785i386_mach (void)
b9d79e03 2786{
351f65ca 2787 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2788 {
3632d14b 2789 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2790 {
351f65ca
L		 2791 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2792 || default_arch[6] != '\0')
8a9036a4
L		 2793 as_fatal (_("Intel L1OM is 64bit ELF only"));
2794 return bfd_mach_l1om;
2795 }
7a9068fe
L		 2796 else if (cpu_arch_isa == PROCESSOR_K1OM)
2797 {
2798 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2799 || default_arch[6] != '\0')
2800 as_fatal (_("Intel K1OM is 64bit ELF only"));
2801 return bfd_mach_k1om;
2802 }
351f65ca 2803 else if (default_arch[6] == '\0')
8a9036a4 2804 return bfd_mach_x86_64;
351f65ca
L		 2805 else
2806 return bfd_mach_x64_32;
8a9036a4 2807 }
5197d474
L		 2808 else if (!strcmp (default_arch, "i386")
2809 || !strcmp (default_arch, "iamcu"))
81486035
L		 2810 {
2811 if (cpu_arch_isa == PROCESSOR_IAMCU)
2812 {
2813 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2814 as_fatal (_("Intel MCU is 32bit ELF only"));
2815 return bfd_mach_i386_iamcu;
2816 }
2817 else
2818 return bfd_mach_i386_i386;
2819 }
b9d79e03 2820 else
2b5d6a91 2821 as_fatal (_("unknown architecture"));
b9d79e03 2822}
b9d79e03 2823\f
252b5132 2824void
7016a5d5 2825md_begin (void)
252b5132
RH		 2826{
2827 const char *hash_err;
2828
86fa6981
L		 2829 /* Support pseudo prefixes like {disp32}. */
2830 lex_type ['{'] = LEX_BEGIN_NAME;
2831
47926f60 2832 /* Initialize op_hash hash table. */
252b5132
RH		 2833 op_hash = hash_new ();
2834
2835 {
d3ce72d0 2836 const insn_template *optab;
29b0f896 2837 templates *core_optab;
252b5132 2838
47926f60
KH		 2839 /* Setup for loop. */
2840 optab = i386_optab;
add39d23 2841 core_optab = XNEW (templates);
252b5132
RH		 2842 core_optab->start = optab;
2843
2844 while (1)
2845 {
2846 ++optab;
2847 if (optab->name == NULL
2848 || strcmp (optab->name, (optab - 1)->name) != 0)
2849 {
2850 /* different name --> ship out current template list;
47926f60 2851 add to hash table; & begin anew. */
252b5132
RH		 2852 core_optab->end = optab;
2853 hash_err = hash_insert (op_hash,
2854 (optab - 1)->name,
5a49b8ac 2855 (void *) core_optab);
252b5132
RH		 2856 if (hash_err)
2857 {
b37df7c4 2858 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2859 (optab - 1)->name,
2860 hash_err);
2861 }
2862 if (optab->name == NULL)
2863 break;
add39d23 2864 core_optab = XNEW (templates);
252b5132
RH		 2865 core_optab->start = optab;
2866 }
2867 }
2868 }
2869
47926f60 2870 /* Initialize reg_hash hash table. */
252b5132
RH		 2871 reg_hash = hash_new ();
2872 {
29b0f896 2873 const reg_entry *regtab;
c3fe08fa 2874 unsigned int regtab_size = i386_regtab_size;
252b5132 2875
c3fe08fa 2876 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2877 {
5a49b8ac 2878 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2879 if (hash_err)
b37df7c4 2880 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2881 regtab->reg_name,
2882 hash_err);
252b5132
RH		 2883 }
2884 }
2885
47926f60 2886 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2887 {
29b0f896
AM		 2888 int c;
2889 char *p;
252b5132
RH		 2890
2891 for (c = 0; c < 256; c++)
2892 {
3882b010 2893 if (ISDIGIT (c))
252b5132
RH		 2894 {
2895 digit_chars[c] = c;
2896 mnemonic_chars[c] = c;
2897 register_chars[c] = c;
2898 operand_chars[c] = c;
2899 }
3882b010 2900 else if (ISLOWER (c))
252b5132
RH		 2901 {
2902 mnemonic_chars[c] = c;
2903 register_chars[c] = c;
2904 operand_chars[c] = c;
2905 }
3882b010 2906 else if (ISUPPER (c))
252b5132 2907 {
3882b010 2908 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2909 register_chars[c] = mnemonic_chars[c];
2910 operand_chars[c] = c;
2911 }
43234a1e 2912 else if (c == '{' || c == '}')
86fa6981
L		 2913 {
2914 mnemonic_chars[c] = c;
2915 operand_chars[c] = c;
2916 }
252b5132 2917
3882b010 2918 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2919 identifier_chars[c] = c;
2920 else if (c >= 128)
2921 {
2922 identifier_chars[c] = c;
2923 operand_chars[c] = c;
2924 }
2925 }
2926
2927#ifdef LEX_AT
2928 identifier_chars['@'] = '@';
32137342
NC		 2929#endif
2930#ifdef LEX_QM
2931 identifier_chars['?'] = '?';
2932 operand_chars['?'] = '?';
252b5132 2933#endif
252b5132 2934 digit_chars['-'] = '-';
c0f3af97 2935 mnemonic_chars['_'] = '_';
791fe849 2936 mnemonic_chars['-'] = '-';
0003779b 2937 mnemonic_chars['.'] = '.';
252b5132
RH		 2938 identifier_chars['_'] = '_';
2939 identifier_chars['.'] = '.';
2940
2941 for (p = operand_special_chars; *p != '\0'; p++)
2942 operand_chars[(unsigned char) *p] = *p;
2943 }
2944
a4447b93
RH		 2945 if (flag_code == CODE_64BIT)
2946 {
ca19b261
KT		 2947#if defined (OBJ_COFF) && defined (TE_PE)
2948 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2949 ? 32 : 16);
2950#else
a4447b93 2951 x86_dwarf2_return_column = 16;
ca19b261 2952#endif
61ff971f 2953 x86_cie_data_alignment = -8;
a4447b93
RH		 2954 }
2955 else
2956 {
2957 x86_dwarf2_return_column = 8;
2958 x86_cie_data_alignment = -4;
2959 }
252b5132
RH		 2960}
2961
2962void
e3bb37b5 2963i386_print_statistics (FILE *file)
252b5132
RH		 2964{
2965 hash_print_statistics (file, "i386 opcode", op_hash);
2966 hash_print_statistics (file, "i386 register", reg_hash);
2967}
2968\f
252b5132
RH		 2969#ifdef DEBUG386
2970
ce8a8b2f 2971/* Debugging routines for md_assemble. */
d3ce72d0 2972static void pte (insn_template *);
40fb9820 2973static void pt (i386_operand_type);
e3bb37b5
L		 2974static void pe (expressionS *);
2975static void ps (symbolS *);
252b5132
RH		 2976
2977static void
e3bb37b5 2978pi (char *line, i386_insn *x)
252b5132 2979{
09137c09 2980 unsigned int j;
252b5132
RH		 2981
2982 fprintf (stdout, "%s: template ", line);
2983 pte (&x->tm);
09f131f2
JH		 2984 fprintf (stdout, " address: base %s index %s scale %x\n",
2985 x->base_reg ? x->base_reg->reg_name : "none",
2986 x->index_reg ? x->index_reg->reg_name : "none",
2987 x->log2_scale_factor);
2988 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2989 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2990 fprintf (stdout, " sib: base %x index %x scale %x\n",
2991 x->sib.base, x->sib.index, x->sib.scale);
2992 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2993 (x->rex & REX_W) != 0,
2994 (x->rex & REX_R) != 0,
2995 (x->rex & REX_X) != 0,
2996 (x->rex & REX_B) != 0);
09137c09 2997 for (j = 0; j < x->operands; j++)
252b5132 2998 {
09137c09
SP		 2999 fprintf (stdout, " #%d: ", j + 1);
3000 pt (x->types[j]);
252b5132 3001 fprintf (stdout, "\n");
dc821c5f 3002 if (x->types[j].bitfield.reg
09137c09 3003 || x->types[j].bitfield.regmmx
1b54b8d7 3004 || x->types[j].bitfield.regsimd
09137c09
SP		 3005 || x->types[j].bitfield.sreg2
3006 || x->types[j].bitfield.sreg3
3007 || x->types[j].bitfield.control
3008 || x->types[j].bitfield.debug
3009 || x->types[j].bitfield.test)
3010 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
3011 if (operand_type_check (x->types[j], imm))
3012 pe (x->op[j].imms);
3013 if (operand_type_check (x->types[j], disp))
3014 pe (x->op[j].disps);
252b5132
RH		 3015 }
3016}
3017
3018static void
d3ce72d0 3019pte (insn_template *t)
252b5132 3020{
09137c09 3021 unsigned int j;
252b5132 3022 fprintf (stdout, " %d operands ", t->operands);
47926f60 3023 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 3024 if (t->extension_opcode != None)
3025 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 3026 if (t->opcode_modifier.d)
252b5132 3027 fprintf (stdout, "D");
40fb9820 3028 if (t->opcode_modifier.w)
252b5132
RH		 3029 fprintf (stdout, "W");
3030 fprintf (stdout, "\n");
09137c09 3031 for (j = 0; j < t->operands; j++)
252b5132 3032 {
09137c09
SP		 3033 fprintf (stdout, " #%d type ", j + 1);
3034 pt (t->operand_types[j]);
252b5132
RH		 3035 fprintf (stdout, "\n");
3036 }
3037}
3038
3039static void
e3bb37b5 3040pe (expressionS *e)
252b5132 3041{
24eab124 3042 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 3043 fprintf (stdout, " add_number %ld (%lx)\n",
3044 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 3045 if (e->X_add_symbol)
3046 {
3047 fprintf (stdout, " add_symbol ");
3048 ps (e->X_add_symbol);
3049 fprintf (stdout, "\n");
3050 }
3051 if (e->X_op_symbol)
3052 {
3053 fprintf (stdout, " op_symbol ");
3054 ps (e->X_op_symbol);
3055 fprintf (stdout, "\n");
3056 }
3057}
3058
3059static void
e3bb37b5 3060ps (symbolS *s)
252b5132
RH		 3061{
3062 fprintf (stdout, "%s type %s%s",
3063 S_GET_NAME (s),
3064 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
3065 segment_name (S_GET_SEGMENT (s)));
3066}
3067
7b81dfbb 3068static struct type_name
252b5132 3069 {
40fb9820
L		 3070 i386_operand_type mask;
3071 const char *name;
252b5132 3072 }
7b81dfbb 3073const type_names[] =
252b5132 3074{
40fb9820
L		 3075 { OPERAND_TYPE_REG8, "r8" },
3076 { OPERAND_TYPE_REG16, "r16" },
3077 { OPERAND_TYPE_REG32, "r32" },
3078 { OPERAND_TYPE_REG64, "r64" },
3079 { OPERAND_TYPE_IMM8, "i8" },
3080 { OPERAND_TYPE_IMM8, "i8s" },
3081 { OPERAND_TYPE_IMM16, "i16" },
3082 { OPERAND_TYPE_IMM32, "i32" },
3083 { OPERAND_TYPE_IMM32S, "i32s" },
3084 { OPERAND_TYPE_IMM64, "i64" },
3085 { OPERAND_TYPE_IMM1, "i1" },
3086 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
3087 { OPERAND_TYPE_DISP8, "d8" },
3088 { OPERAND_TYPE_DISP16, "d16" },
3089 { OPERAND_TYPE_DISP32, "d32" },
3090 { OPERAND_TYPE_DISP32S, "d32s" },
3091 { OPERAND_TYPE_DISP64, "d64" },
3092 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
3093 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
3094 { OPERAND_TYPE_CONTROL, "control reg" },
3095 { OPERAND_TYPE_TEST, "test reg" },
3096 { OPERAND_TYPE_DEBUG, "debug reg" },
3097 { OPERAND_TYPE_FLOATREG, "FReg" },
3098 { OPERAND_TYPE_FLOATACC, "FAcc" },
3099 { OPERAND_TYPE_SREG2, "SReg2" },
3100 { OPERAND_TYPE_SREG3, "SReg3" },
3101 { OPERAND_TYPE_ACC, "Acc" },
3102 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
3103 { OPERAND_TYPE_REGMMX, "rMMX" },
3104 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 3105 { OPERAND_TYPE_REGYMM, "rYMM" },
43234a1e
L		 3106 { OPERAND_TYPE_REGZMM, "rZMM" },
3107 { OPERAND_TYPE_REGMASK, "Mask reg" },
40fb9820 3108 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 3109};
3110
3111static void
40fb9820 3112pt (i386_operand_type t)
252b5132 3113{
40fb9820 3114 unsigned int j;
c6fb90c8 3115 i386_operand_type a;
252b5132 3116
40fb9820 3117 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 3118 {
3119 a = operand_type_and (t, type_names[j].mask);
0349dc08 3120 if (!operand_type_all_zero (&a))
c6fb90c8
L		 3121 fprintf (stdout, "%s, ", type_names[j].name);
3122 }
252b5132
RH		 3123 fflush (stdout);
3124}
3125
3126#endif /* DEBUG386 */
3127\f
252b5132 3128static bfd_reloc_code_real_type
3956db08 3129reloc (unsigned int size,
64e74474
AM		 3130 int pcrel,
3131 int sign,
3132 bfd_reloc_code_real_type other)
252b5132 3133{
47926f60 3134 if (other != NO_RELOC)
3956db08 3135 {
91d6fa6a 3136 reloc_howto_type *rel;
3956db08
JB		 3137
3138 if (size == 8)
3139 switch (other)
3140 {
64e74474
AM		 3141 case BFD_RELOC_X86_64_GOT32:
3142 return BFD_RELOC_X86_64_GOT64;
3143 break;
553d1284
L		 3144 case BFD_RELOC_X86_64_GOTPLT64:
3145 return BFD_RELOC_X86_64_GOTPLT64;
3146 break;
64e74474
AM		 3147 case BFD_RELOC_X86_64_PLTOFF64:
3148 return BFD_RELOC_X86_64_PLTOFF64;
3149 break;
3150 case BFD_RELOC_X86_64_GOTPC32:
3151 other = BFD_RELOC_X86_64_GOTPC64;
3152 break;
3153 case BFD_RELOC_X86_64_GOTPCREL:
3154 other = BFD_RELOC_X86_64_GOTPCREL64;
3155 break;
3156 case BFD_RELOC_X86_64_TPOFF32:
3157 other = BFD_RELOC_X86_64_TPOFF64;
3158 break;
3159 case BFD_RELOC_X86_64_DTPOFF32:
3160 other = BFD_RELOC_X86_64_DTPOFF64;
3161 break;
3162 default:
3163 break;
3956db08 3164 }
e05278af 3165
8ce3d284 3166#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 3167 if (other == BFD_RELOC_SIZE32)
3168 {
3169 if (size == 8)
1ab668bf 3170 other = BFD_RELOC_SIZE64;
8fd4256d 3171 if (pcrel)
1ab668bf
AM		 3172 {
3173 as_bad (_("there are no pc-relative size relocations"));
3174 return NO_RELOC;
3175 }
8fd4256d 3176 }
8ce3d284 3177#endif
8fd4256d 3178
e05278af 3179 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 3180 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 3181 sign = -1;
3182
91d6fa6a
NC		 3183 rel = bfd_reloc_type_lookup (stdoutput, other);
3184 if (!rel)
3956db08 3185 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 3186 else if (size != bfd_get_reloc_size (rel))
3956db08 3187 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 3188 bfd_get_reloc_size (rel),
3956db08 3189 size);
91d6fa6a 3190 else if (pcrel && !rel->pc_relative)
3956db08 3191 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 3192 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 3193 && !sign)
91d6fa6a 3194 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 3195 && sign > 0))
3956db08
JB		 3196 as_bad (_("relocated field and relocation type differ in signedness"));
3197 else
3198 return other;
3199 return NO_RELOC;
3200 }
252b5132
RH		 3201
3202 if (pcrel)
3203 {
3e73aa7c 3204 if (!sign)
3956db08 3205 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 3206 switch (size)
3207 {
3208 case 1: return BFD_RELOC_8_PCREL;
3209 case 2: return BFD_RELOC_16_PCREL;
d258b828 3210 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 3211 case 8: return BFD_RELOC_64_PCREL;
252b5132 3212 }
3956db08 3213 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 3214 }
3215 else
3216 {
3956db08 3217 if (sign > 0)
e5cb08ac 3218 switch (size)
3e73aa7c
JH		 3219 {
3220 case 4: return BFD_RELOC_X86_64_32S;
3221 }
3222 else
3223 switch (size)
3224 {
3225 case 1: return BFD_RELOC_8;
3226 case 2: return BFD_RELOC_16;
3227 case 4: return BFD_RELOC_32;
3228 case 8: return BFD_RELOC_64;
3229 }
3956db08
JB		 3230 as_bad (_("cannot do %s %u byte relocation"),
3231 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 3232 }
3233
0cc9e1d3 3234 return NO_RELOC;
252b5132
RH		 3235}
3236
47926f60
KH		 3237/* Here we decide which fixups can be adjusted to make them relative to
3238 the beginning of the section instead of the symbol. Basically we need
3239 to make sure that the dynamic relocations are done correctly, so in
3240 some cases we force the original symbol to be used. */
3241
252b5132 3242int
e3bb37b5 3243tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 3244{
6d249963 3245#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 3246 if (!IS_ELF)
31312f95
AM		 3247 return 1;
3248
a161fe53
AM		 3249 /* Don't adjust pc-relative references to merge sections in 64-bit
3250 mode. */
3251 if (use_rela_relocations
3252 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3253 && fixP->fx_pcrel)
252b5132 3254 return 0;
31312f95 3255
8d01d9a9
AJ		 3256 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3257 and changed later by validate_fix. */
3258 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3259 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3260 return 0;
3261
8fd4256d
L		 3262 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3263 for size relocations. */
3264 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3265 || fixP->fx_r_type == BFD_RELOC_SIZE64
3266 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 3267 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3268 || fixP->fx_r_type == BFD_RELOC_386_GOT32
02a86693 3269 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
13ae64f3
JJ		 3270 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3271 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3272 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3273 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 3274 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3275 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 3276 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3277 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 3278 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3279 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 3280 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3281 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 3282 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
56ceb5b5
L		 3283 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3284 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
bffbf940
JJ		 3285 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3286 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3287 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 3288 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 3289 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3290 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 3291 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3292 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 3293 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3294 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 3295 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3296 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3297 return 0;
31312f95 3298#endif
252b5132
RH		 3299 return 1;
3300}
252b5132 3301
b4cac588 3302static int
e3bb37b5 3303intel_float_operand (const char *mnemonic)
252b5132 3304{
9306ca4a
JB		 3305 /* Note that the value returned is meaningful only for opcodes with (memory)
3306 operands, hence the code here is free to improperly handle opcodes that
3307 have no operands (for better performance and smaller code). */
3308
3309 if (mnemonic[0] != 'f')
3310 return 0; /* non-math */
3311
3312 switch (mnemonic[1])
3313 {
3314 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3315 the fs segment override prefix not currently handled because no
3316 call path can make opcodes without operands get here */
3317 case 'i':
3318 return 2 /* integer op */;
3319 case 'l':
3320 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3321 return 3; /* fldcw/fldenv */
3322 break;
3323 case 'n':
3324 if (mnemonic[2] != 'o' /* fnop */)
3325 return 3; /* non-waiting control op */
3326 break;
3327 case 'r':
3328 if (mnemonic[2] == 's')
3329 return 3; /* frstor/frstpm */
3330 break;
3331 case 's':
3332 if (mnemonic[2] == 'a')
3333 return 3; /* fsave */
3334 if (mnemonic[2] == 't')
3335 {
3336 switch (mnemonic[3])
3337 {
3338 case 'c': /* fstcw */
3339 case 'd': /* fstdw */
3340 case 'e': /* fstenv */
3341 case 's': /* fsts[gw] */
3342 return 3;
3343 }
3344 }
3345 break;
3346 case 'x':
3347 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3348 return 0; /* fxsave/fxrstor are not really math ops */
3349 break;
3350 }
252b5132 3351
9306ca4a 3352 return 1;
252b5132
RH		 3353}
3354
c0f3af97
L		 3355/* Build the VEX prefix. */
3356
3357static void
d3ce72d0 3358build_vex_prefix (const insn_template *t)
c0f3af97
L		 3359{
3360 unsigned int register_specifier;
3361 unsigned int implied_prefix;
3362 unsigned int vector_length;
03751133 3363 unsigned int w;
c0f3af97
L		 3364
3365 /* Check register specifier. */
3366 if (i.vex.register_specifier)
43234a1e
L		 3367 {
3368 register_specifier =
3369 ~register_number (i.vex.register_specifier) & 0xf;
3370 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3371 }
c0f3af97
L		 3372 else
3373 register_specifier = 0xf;
3374
79f0fa25
L		 3375 /* Use 2-byte VEX prefix by swapping destination and source operand
3376 if there are more than 1 register operand. */
3377 if (i.reg_operands > 1
3378 && i.vec_encoding != vex_encoding_vex3
86fa6981 3379 && i.dir_encoding == dir_encoding_default
fa99fab2 3380 && i.operands == i.reg_operands
dbbc8b7e 3381 && operand_type_equal (&i.types[0], &i.types[i.operands - 1])
7f399153 3382 && i.tm.opcode_modifier.vexopcode == VEX0F
dbbc8b7e 3383 && (i.tm.opcode_modifier.load || i.tm.opcode_modifier.d)
fa99fab2
L		 3384 && i.rex == REX_B)
3385 {
3386 unsigned int xchg = i.operands - 1;
3387 union i386_op temp_op;
3388 i386_operand_type temp_type;
3389
3390 temp_type = i.types[xchg];
3391 i.types[xchg] = i.types[0];
3392 i.types[0] = temp_type;
3393 temp_op = i.op[xchg];
3394 i.op[xchg] = i.op[0];
3395 i.op[0] = temp_op;
3396
9c2799c2 3397 gas_assert (i.rm.mode == 3);
fa99fab2
L		 3398
3399 i.rex = REX_R;
3400 xchg = i.rm.regmem;
3401 i.rm.regmem = i.rm.reg;
3402 i.rm.reg = xchg;
3403
dbbc8b7e
JB		 3404 if (i.tm.opcode_modifier.d)
3405 i.tm.base_opcode ^= (i.tm.base_opcode & 0xee) != 0x6e
3406 ? Opcode_SIMD_FloatD : Opcode_SIMD_IntD;
3407 else /* Use the next insn. */
3408 i.tm = t[1];
fa99fab2
L		 3409 }
3410
539f890d
L		 3411 if (i.tm.opcode_modifier.vex == VEXScalar)
3412 vector_length = avxscalar;
10c17abd
JB		 3413 else if (i.tm.opcode_modifier.vex == VEX256)
3414 vector_length = 1;
539f890d 3415 else
10c17abd 3416 {
56522fc5 3417 unsigned int op;
10c17abd 3418
c7213af9
L		 3419 /* Determine vector length from the last multi-length vector
3420 operand. */
10c17abd 3421 vector_length = 0;
56522fc5 3422 for (op = t->operands; op--;)
10c17abd
JB		 3423 if (t->operand_types[op].bitfield.xmmword
3424 && t->operand_types[op].bitfield.ymmword
3425 && i.types[op].bitfield.ymmword)
3426 {
3427 vector_length = 1;
3428 break;
3429 }
3430 }
c0f3af97
L		 3431
3432 switch ((i.tm.base_opcode >> 8) & 0xff)
3433 {
3434 case 0:
3435 implied_prefix = 0;
3436 break;
3437 case DATA_PREFIX_OPCODE:
3438 implied_prefix = 1;
3439 break;
3440 case REPE_PREFIX_OPCODE:
3441 implied_prefix = 2;
3442 break;
3443 case REPNE_PREFIX_OPCODE:
3444 implied_prefix = 3;
3445 break;
3446 default:
3447 abort ();
3448 }
3449
03751133
L		 3450 /* Check the REX.W bit and VEXW. */
3451 if (i.tm.opcode_modifier.vexw == VEXWIG)
3452 w = (vexwig == vexw1 || (i.rex & REX_W)) ? 1 : 0;
3453 else if (i.tm.opcode_modifier.vexw)
3454 w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0;
3455 else
931d03b7 3456 w = (flag_code == CODE_64BIT ? i.rex & REX_W : vexwig == vexw1) ? 1 : 0;
03751133 3457
c0f3af97 3458 /* Use 2-byte VEX prefix if possible. */
03751133
L		 3459 if (w == 0
3460 && i.vec_encoding != vex_encoding_vex3
86fa6981 3461 && i.tm.opcode_modifier.vexopcode == VEX0F
c0f3af97
L		 3462 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3463 {
3464 /* 2-byte VEX prefix. */
3465 unsigned int r;
3466
3467 i.vex.length = 2;
3468 i.vex.bytes[0] = 0xc5;
3469
3470 /* Check the REX.R bit. */
3471 r = (i.rex & REX_R) ? 0 : 1;
3472 i.vex.bytes[1] = (r << 7
3473 | register_specifier << 3
3474 | vector_length << 2
3475 | implied_prefix);
3476 }
3477 else
3478 {
3479 /* 3-byte VEX prefix. */
03751133 3480 unsigned int m;
c0f3af97 3481
f88c9eb0 3482 i.vex.length = 3;
f88c9eb0 3483
7f399153 3484 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 3485 {
7f399153
L		 3486 case VEX0F:
3487 m = 0x1;
80de6e00 3488 i.vex.bytes[0] = 0xc4;
7f399153
L		 3489 break;
3490 case VEX0F38:
3491 m = 0x2;
80de6e00 3492 i.vex.bytes[0] = 0xc4;
7f399153
L		 3493 break;
3494 case VEX0F3A:
3495 m = 0x3;
80de6e00 3496 i.vex.bytes[0] = 0xc4;
7f399153
L		 3497 break;
3498 case XOP08:
5dd85c99
SP		 3499 m = 0x8;
3500 i.vex.bytes[0] = 0x8f;
7f399153
L		 3501 break;
3502 case XOP09:
f88c9eb0
SP		 3503 m = 0x9;
3504 i.vex.bytes[0] = 0x8f;
7f399153
L		 3505 break;
3506 case XOP0A:
f88c9eb0
SP		 3507 m = 0xa;
3508 i.vex.bytes[0] = 0x8f;
7f399153
L		 3509 break;
3510 default:
3511 abort ();
f88c9eb0 3512 }
c0f3af97 3513
c0f3af97
L		 3514 /* The high 3 bits of the second VEX byte are 1's compliment
3515 of RXB bits from REX. */
3516 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3517
c0f3af97
L		 3518 i.vex.bytes[2] = (w << 7
3519 | register_specifier << 3
3520 | vector_length << 2
3521 | implied_prefix);
3522 }
3523}
3524
e771e7c9
JB		 3525static INLINE bfd_boolean
3526is_evex_encoding (const insn_template *t)
3527{
7091c612 3528 return t->opcode_modifier.evex || t->opcode_modifier.disp8memshift
e771e7c9
JB		 3529 || t->opcode_modifier.broadcast || t->opcode_modifier.masking
3530 || t->opcode_modifier.staticrounding || t->opcode_modifier.sae;
3531}
3532
7a8655d2
JB		 3533static INLINE bfd_boolean
3534is_any_vex_encoding (const insn_template *t)
3535{
3536 return t->opcode_modifier.vex || t->opcode_modifier.vexopcode
3537 || is_evex_encoding (t);
3538}
3539
43234a1e
L		 3540/* Build the EVEX prefix. */
3541
3542static void
3543build_evex_prefix (void)
3544{
3545 unsigned int register_specifier;
3546 unsigned int implied_prefix;
3547 unsigned int m, w;
3548 rex_byte vrex_used = 0;
3549
3550 /* Check register specifier. */
3551 if (i.vex.register_specifier)
3552 {
3553 gas_assert ((i.vrex & REX_X) == 0);
3554
3555 register_specifier = i.vex.register_specifier->reg_num;
3556 if ((i.vex.register_specifier->reg_flags & RegRex))
3557 register_specifier += 8;
3558 /* The upper 16 registers are encoded in the fourth byte of the
3559 EVEX prefix. */
3560 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3561 i.vex.bytes[3] = 0x8;
3562 register_specifier = ~register_specifier & 0xf;
3563 }
3564 else
3565 {
3566 register_specifier = 0xf;
3567
3568 /* Encode upper 16 vector index register in the fourth byte of
3569 the EVEX prefix. */
3570 if (!(i.vrex & REX_X))
3571 i.vex.bytes[3] = 0x8;
3572 else
3573 vrex_used |= REX_X;
3574 }
3575
3576 switch ((i.tm.base_opcode >> 8) & 0xff)
3577 {
3578 case 0:
3579 implied_prefix = 0;
3580 break;
3581 case DATA_PREFIX_OPCODE:
3582 implied_prefix = 1;
3583 break;
3584 case REPE_PREFIX_OPCODE:
3585 implied_prefix = 2;
3586 break;
3587 case REPNE_PREFIX_OPCODE:
3588 implied_prefix = 3;
3589 break;
3590 default:
3591 abort ();
3592 }
3593
3594 /* 4 byte EVEX prefix. */
3595 i.vex.length = 4;
3596 i.vex.bytes[0] = 0x62;
3597
3598 /* mmmm bits. */
3599 switch (i.tm.opcode_modifier.vexopcode)
3600 {
3601 case VEX0F:
3602 m = 1;
3603 break;
3604 case VEX0F38:
3605 m = 2;
3606 break;
3607 case VEX0F3A:
3608 m = 3;
3609 break;
3610 default:
3611 abort ();
3612 break;
3613 }
3614
3615 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3616 bits from REX. */
3617 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3618
3619 /* The fifth bit of the second EVEX byte is 1's compliment of the
3620 REX_R bit in VREX. */
3621 if (!(i.vrex & REX_R))
3622 i.vex.bytes[1] |= 0x10;
3623 else
3624 vrex_used |= REX_R;
3625
3626 if ((i.reg_operands + i.imm_operands) == i.operands)
3627 {
3628 /* When all operands are registers, the REX_X bit in REX is not
3629 used. We reuse it to encode the upper 16 registers, which is
3630 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3631 as 1's compliment. */
3632 if ((i.vrex & REX_B))
3633 {
3634 vrex_used |= REX_B;
3635 i.vex.bytes[1] &= ~0x40;
3636 }
3637 }
3638
3639 /* EVEX instructions shouldn't need the REX prefix. */
3640 i.vrex &= ~vrex_used;
3641 gas_assert (i.vrex == 0);
3642
6865c043
L		 3643 /* Check the REX.W bit and VEXW. */
3644 if (i.tm.opcode_modifier.vexw == VEXWIG)
3645 w = (evexwig == evexw1 || (i.rex & REX_W)) ? 1 : 0;
3646 else if (i.tm.opcode_modifier.vexw)
3647 w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0;
3648 else
931d03b7 3649 w = (flag_code == CODE_64BIT ? i.rex & REX_W : evexwig == evexw1) ? 1 : 0;
43234a1e
L		 3650
3651 /* Encode the U bit. */
3652 implied_prefix |= 0x4;
3653
3654 /* The third byte of the EVEX prefix. */
3655 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3656
3657 /* The fourth byte of the EVEX prefix. */
3658 /* The zeroing-masking bit. */
3659 if (i.mask && i.mask->zeroing)
3660 i.vex.bytes[3] |= 0x80;
3661
3662 /* Don't always set the broadcast bit if there is no RC. */
3663 if (!i.rounding)
3664 {
3665 /* Encode the vector length. */
3666 unsigned int vec_length;
3667
e771e7c9
JB		 3668 if (!i.tm.opcode_modifier.evex
3669 || i.tm.opcode_modifier.evex == EVEXDYN)
3670 {
56522fc5 3671 unsigned int op;
e771e7c9 3672
c7213af9
L		 3673 /* Determine vector length from the last multi-length vector
3674 operand. */
e771e7c9 3675 vec_length = 0;
56522fc5 3676 for (op = i.operands; op--;)
e771e7c9
JB		 3677 if (i.tm.operand_types[op].bitfield.xmmword
3678 + i.tm.operand_types[op].bitfield.ymmword
3679 + i.tm.operand_types[op].bitfield.zmmword > 1)
3680 {
3681 if (i.types[op].bitfield.zmmword)
c7213af9
L		 3682 {
3683 i.tm.opcode_modifier.evex = EVEX512;
3684 break;
3685 }
e771e7c9 3686 else if (i.types[op].bitfield.ymmword)
c7213af9
L		 3687 {
3688 i.tm.opcode_modifier.evex = EVEX256;
3689 break;
3690 }
e771e7c9 3691 else if (i.types[op].bitfield.xmmword)
c7213af9
L		 3692 {
3693 i.tm.opcode_modifier.evex = EVEX128;
3694 break;
3695 }
625cbd7a
JB		 3696 else if (i.broadcast && (int) op == i.broadcast->operand)
3697 {
4a1b91ea 3698 switch (i.broadcast->bytes)
625cbd7a
JB		 3699 {
3700 case 64:
3701 i.tm.opcode_modifier.evex = EVEX512;
3702 break;
3703 case 32:
3704 i.tm.opcode_modifier.evex = EVEX256;
3705 break;
3706 case 16:
3707 i.tm.opcode_modifier.evex = EVEX128;
3708 break;
3709 default:
c7213af9 3710 abort ();
625cbd7a 3711 }
c7213af9 3712 break;
625cbd7a 3713 }
e771e7c9 3714 }
c7213af9 3715
56522fc5 3716 if (op >= MAX_OPERANDS)
c7213af9 3717 abort ();
e771e7c9
JB		 3718 }
3719
43234a1e
L		 3720 switch (i.tm.opcode_modifier.evex)
3721 {
3722 case EVEXLIG: /* LL' is ignored */
3723 vec_length = evexlig << 5;
3724 break;
3725 case EVEX128:
3726 vec_length = 0 << 5;
3727 break;
3728 case EVEX256:
3729 vec_length = 1 << 5;
3730 break;
3731 case EVEX512:
3732 vec_length = 2 << 5;
3733 break;
3734 default:
3735 abort ();
3736 break;
3737 }
3738 i.vex.bytes[3] |= vec_length;
3739 /* Encode the broadcast bit. */
3740 if (i.broadcast)
3741 i.vex.bytes[3] |= 0x10;
3742 }
3743 else
3744 {
3745 if (i.rounding->type != saeonly)
3746 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3747 else
d3d3c6db 3748 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
43234a1e
L		 3749 }
3750
3751 if (i.mask && i.mask->mask)
3752 i.vex.bytes[3] |= i.mask->mask->reg_num;
3753}
3754
65da13b5
L		 3755static void
3756process_immext (void)
3757{
3758 expressionS *exp;
3759
4c692bc7
JB		 3760 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3761 && i.operands > 0)
65da13b5 3762 {
4c692bc7
JB		 3763 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3764 with an opcode suffix which is coded in the same place as an
3765 8-bit immediate field would be.
3766 Here we check those operands and remove them afterwards. */
65da13b5
L		 3767 unsigned int x;
3768
3769 for (x = 0; x < i.operands; x++)
4c692bc7 3770 if (register_number (i.op[x].regs) != x)
65da13b5 3771 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3772 register_prefix, i.op[x].regs->reg_name, x + 1,
3773 i.tm.name);
3774
3775 i.operands = 0;
65da13b5
L		 3776 }
3777
9916071f
AP		 3778 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3779 {
3780 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3781 suffix which is coded in the same place as an 8-bit immediate
3782 field would be.
3783 Here we check those operands and remove them afterwards. */
3784 unsigned int x;
3785
3786 if (i.operands != 3)
3787 abort();
3788
3789 for (x = 0; x < 2; x++)
3790 if (register_number (i.op[x].regs) != x)
3791 goto bad_register_operand;
3792
3793 /* Check for third operand for mwaitx/monitorx insn. */
3794 if (register_number (i.op[x].regs)
3795 != (x + (i.tm.extension_opcode == 0xfb)))
3796 {
3797bad_register_operand:
3798 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3799 register_prefix, i.op[x].regs->reg_name, x+1,
3800 i.tm.name);
3801 }
3802
3803 i.operands = 0;
3804 }
3805
c0f3af97 3806 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3807 which is coded in the same place as an 8-bit immediate field
3808 would be. Here we fake an 8-bit immediate operand from the
3809 opcode suffix stored in tm.extension_opcode.
3810
c1e679ec 3811 AVX instructions also use this encoding, for some of
c0f3af97 3812 3 argument instructions. */
65da13b5 3813
43234a1e 3814 gas_assert (i.imm_operands <= 1
7ab9ffdd 3815 && (i.operands <= 2
7a8655d2 3816 || (is_any_vex_encoding (&i.tm)
7ab9ffdd 3817 && i.operands <= 4)));
65da13b5
L		 3818
3819 exp = &im_expressions[i.imm_operands++];
3820 i.op[i.operands].imms = exp;
3821 i.types[i.operands] = imm8;
3822 i.operands++;
3823 exp->X_op = O_constant;
3824 exp->X_add_number = i.tm.extension_opcode;
3825 i.tm.extension_opcode = None;
3826}
3827
42164a71
L		 3828
3829static int
3830check_hle (void)
3831{
3832 switch (i.tm.opcode_modifier.hleprefixok)
3833 {
3834 default:
3835 abort ();
82c2def5 3836 case HLEPrefixNone:
165de32a
L		 3837 as_bad (_("invalid instruction `%s' after `%s'"),
3838 i.tm.name, i.hle_prefix);
42164a71 3839 return 0;
82c2def5 3840 case HLEPrefixLock:
42164a71
L		 3841 if (i.prefix[LOCK_PREFIX])
3842 return 1;
165de32a 3843 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3844 return 0;
82c2def5 3845 case HLEPrefixAny:
42164a71 3846 return 1;
82c2def5 3847 case HLEPrefixRelease:
42164a71
L		 3848 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3849 {
3850 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3851 i.tm.name);
3852 return 0;
3853 }
3854 if (i.mem_operands == 0
3855 || !operand_type_check (i.types[i.operands - 1], anymem))
3856 {
3857 as_bad (_("memory destination needed for instruction `%s'"
3858 " after `xrelease'"), i.tm.name);
3859 return 0;
3860 }
3861 return 1;
3862 }
3863}
3864
b6f8c7c4
L		 3865/* Try the shortest encoding by shortening operand size. */
3866
3867static void
3868optimize_encoding (void)
3869{
3870 int j;
3871
3872 if (optimize_for_space
3873 && i.reg_operands == 1
3874 && i.imm_operands == 1
3875 && !i.types[1].bitfield.byte
3876 && i.op[0].imms->X_op == O_constant
3877 && fits_in_imm7 (i.op[0].imms->X_add_number)
3878 && ((i.tm.base_opcode == 0xa8
3879 && i.tm.extension_opcode == None)
3880 || (i.tm.base_opcode == 0xf6
3881 && i.tm.extension_opcode == 0x0)))
3882 {
3883 /* Optimize: -Os:
3884 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3885 */
3886 unsigned int base_regnum = i.op[1].regs->reg_num;
3887 if (flag_code == CODE_64BIT || base_regnum < 4)
3888 {
3889 i.types[1].bitfield.byte = 1;
3890 /* Ignore the suffix. */
3891 i.suffix = 0;
3892 if (base_regnum >= 4
3893 && !(i.op[1].regs->reg_flags & RegRex))
3894 {
3895 /* Handle SP, BP, SI and DI registers. */
3896 if (i.types[1].bitfield.word)
3897 j = 16;
3898 else if (i.types[1].bitfield.dword)
3899 j = 32;
3900 else
3901 j = 48;
3902 i.op[1].regs -= j;
3903 }
3904 }
3905 }
3906 else if (flag_code == CODE_64BIT
d3d50934
L		 3907 && ((i.types[1].bitfield.qword
3908 && i.reg_operands == 1
b6f8c7c4
L		 3909 && i.imm_operands == 1
3910 && i.op[0].imms->X_op == O_constant
3911 && ((i.tm.base_opcode == 0xb0
3912 && i.tm.extension_opcode == None
3913 && fits_in_unsigned_long (i.op[0].imms->X_add_number))
3914 || (fits_in_imm31 (i.op[0].imms->X_add_number)
3915 && (((i.tm.base_opcode == 0x24
3916 || i.tm.base_opcode == 0xa8)
3917 && i.tm.extension_opcode == None)
3918 || (i.tm.base_opcode == 0x80
3919 && i.tm.extension_opcode == 0x4)
3920 || ((i.tm.base_opcode == 0xf6
3921 || i.tm.base_opcode == 0xc6)
3922 && i.tm.extension_opcode == 0x0)))))
d3d50934
L		 3923 || (i.types[0].bitfield.qword
3924 && ((i.reg_operands == 2
3925 && i.op[0].regs == i.op[1].regs
3926 && ((i.tm.base_opcode == 0x30
3927 || i.tm.base_opcode == 0x28)
3928 && i.tm.extension_opcode == None))
3929 || (i.reg_operands == 1
3930 && i.operands == 1
3931 && i.tm.base_opcode == 0x30
3932 && i.tm.extension_opcode == None)))))
b6f8c7c4
L		 3933 {
3934 /* Optimize: -O:
3935 andq $imm31, %r64 -> andl $imm31, %r32
3936 testq $imm31, %r64 -> testl $imm31, %r32
3937 xorq %r64, %r64 -> xorl %r32, %r32
3938 subq %r64, %r64 -> subl %r32, %r32
3939 movq $imm31, %r64 -> movl $imm31, %r32
3940 movq $imm32, %r64 -> movl $imm32, %r32
3941 */
3942 i.tm.opcode_modifier.norex64 = 1;
3943 if (i.tm.base_opcode == 0xb0 || i.tm.base_opcode == 0xc6)
3944 {
3945 /* Handle
3946 movq $imm31, %r64 -> movl $imm31, %r32
3947 movq $imm32, %r64 -> movl $imm32, %r32
3948 */
3949 i.tm.operand_types[0].bitfield.imm32 = 1;
3950 i.tm.operand_types[0].bitfield.imm32s = 0;
3951 i.tm.operand_types[0].bitfield.imm64 = 0;
3952 i.types[0].bitfield.imm32 = 1;
3953 i.types[0].bitfield.imm32s = 0;
3954 i.types[0].bitfield.imm64 = 0;
3955 i.types[1].bitfield.dword = 1;
3956 i.types[1].bitfield.qword = 0;
3957 if (i.tm.base_opcode == 0xc6)
3958 {
3959 /* Handle
3960 movq $imm31, %r64 -> movl $imm31, %r32
3961 */
3962 i.tm.base_opcode = 0xb0;
3963 i.tm.extension_opcode = None;
3964 i.tm.opcode_modifier.shortform = 1;
3965 i.tm.opcode_modifier.modrm = 0;
3966 }
3967 }
3968 }
3969 else if (optimize > 1
3970 && i.reg_operands == 3
3971 && i.op[0].regs == i.op[1].regs
3972 && !i.types[2].bitfield.xmmword
3973 && (i.tm.opcode_modifier.vex
7a69eac3 3974 || ((!i.mask || i.mask->zeroing)
b6f8c7c4 3975 && !i.rounding
e771e7c9 3976 && is_evex_encoding (&i.tm)
80c34c38
L		 3977 && (i.vec_encoding != vex_encoding_evex
3978 || i.tm.cpu_flags.bitfield.cpuavx512vl
7091c612
JB		 3979 || (i.tm.operand_types[2].bitfield.zmmword
3980 && i.types[2].bitfield.ymmword)
0089dace 3981 || cpu_arch_isa_flags.bitfield.cpuavx512vl)))
b6f8c7c4
L		 3982 && ((i.tm.base_opcode == 0x55
3983 || i.tm.base_opcode == 0x6655
3984 || i.tm.base_opcode == 0x66df
3985 || i.tm.base_opcode == 0x57
3986 || i.tm.base_opcode == 0x6657
8305403a
L		 3987 || i.tm.base_opcode == 0x66ef
3988 || i.tm.base_opcode == 0x66f8
3989 || i.tm.base_opcode == 0x66f9
3990 || i.tm.base_opcode == 0x66fa
1424ad86
JB		 3991 || i.tm.base_opcode == 0x66fb
3992 || i.tm.base_opcode == 0x42
3993 || i.tm.base_opcode == 0x6642
3994 || i.tm.base_opcode == 0x47
3995 || i.tm.base_opcode == 0x6647)
b6f8c7c4
L		 3996 && i.tm.extension_opcode == None))
3997 {
3998 /* Optimize: -O2:
8305403a
L		 3999 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4000 vpsubq and vpsubw:
b6f8c7c4
L		 4001 EVEX VOP %zmmM, %zmmM, %zmmN
4002 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4003 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
4004 EVEX VOP %ymmM, %ymmM, %ymmN
4005 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4006 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
4007 VEX VOP %ymmM, %ymmM, %ymmN
4008 -> VEX VOP %xmmM, %xmmM, %xmmN
4009 VOP, one of vpandn and vpxor:
4010 VEX VOP %ymmM, %ymmM, %ymmN
4011 -> VEX VOP %xmmM, %xmmM, %xmmN
4012 VOP, one of vpandnd and vpandnq:
4013 EVEX VOP %zmmM, %zmmM, %zmmN
4014 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4015 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
4016 EVEX VOP %ymmM, %ymmM, %ymmN
4017 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4018 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
4019 VOP, one of vpxord and vpxorq:
4020 EVEX VOP %zmmM, %zmmM, %zmmN
4021 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4022 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
4023 EVEX VOP %ymmM, %ymmM, %ymmN
4024 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4025 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
1424ad86
JB		 4026 VOP, one of kxord and kxorq:
4027 VEX VOP %kM, %kM, %kN
4028 -> VEX kxorw %kM, %kM, %kN
4029 VOP, one of kandnd and kandnq:
4030 VEX VOP %kM, %kM, %kN
4031 -> VEX kandnw %kM, %kM, %kN
b6f8c7c4 4032 */
e771e7c9 4033 if (is_evex_encoding (&i.tm))
b6f8c7c4 4034 {
0089dace 4035 if (i.vec_encoding == vex_encoding_evex)
b6f8c7c4
L		 4036 i.tm.opcode_modifier.evex = EVEX128;
4037 else
4038 {
4039 i.tm.opcode_modifier.vex = VEX128;
4040 i.tm.opcode_modifier.vexw = VEXW0;
4041 i.tm.opcode_modifier.evex = 0;
4042 }
4043 }
1424ad86
JB		 4044 else if (i.tm.operand_types[0].bitfield.regmask)
4045 {
4046 i.tm.base_opcode &= 0xff;
4047 i.tm.opcode_modifier.vexw = VEXW0;
4048 }
b6f8c7c4
L		 4049 else
4050 i.tm.opcode_modifier.vex = VEX128;
4051
4052 if (i.tm.opcode_modifier.vex)
4053 for (j = 0; j < 3; j++)
4054 {
4055 i.types[j].bitfield.xmmword = 1;
4056 i.types[j].bitfield.ymmword = 0;
4057 }
4058 }
4059}
4060
252b5132
RH		 4061/* This is the guts of the machine-dependent assembler. LINE points to a
4062 machine dependent instruction. This function is supposed to emit
4063 the frags/bytes it assembles to. */
4064
4065void
65da13b5 4066md_assemble (char *line)
252b5132 4067{
40fb9820 4068 unsigned int j;
83b16ac6 4069 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
d3ce72d0 4070 const insn_template *t;
252b5132 4071
47926f60 4072 /* Initialize globals. */
252b5132
RH		 4073 memset (&i, '\0', sizeof (i));
4074 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 4075 i.reloc[j] = NO_RELOC;
252b5132
RH		 4076 memset (disp_expressions, '\0', sizeof (disp_expressions));
4077 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 4078 save_stack_p = save_stack;
252b5132
RH		 4079
4080 /* First parse an instruction mnemonic & call i386_operand for the operands.
4081 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 4082 start of a (possibly prefixed) mnemonic. */
252b5132 4083
29b0f896
AM		 4084 line = parse_insn (line, mnemonic);
4085 if (line == NULL)
4086 return;
83b16ac6 4087 mnem_suffix = i.suffix;
252b5132 4088
29b0f896 4089 line = parse_operands (line, mnemonic);
ee86248c 4090 this_operand = -1;
8325cc63
JB		 4091 xfree (i.memop1_string);
4092 i.memop1_string = NULL;
29b0f896
AM		 4093 if (line == NULL)
4094 return;
252b5132 4095
29b0f896
AM		 4096 /* Now we've parsed the mnemonic into a set of templates, and have the
4097 operands at hand. */
4098
4099 /* All intel opcodes have reversed operands except for "bound" and
4100 "enter". We also don't reverse intersegment "jmp" and "call"
4101 instructions with 2 immediate operands so that the immediate segment
050dfa73 4102 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 4103 if (intel_syntax
4104 && i.operands > 1
29b0f896 4105 && (strcmp (mnemonic, "bound") != 0)
30123838 4106 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 4107 && !(operand_type_check (i.types[0], imm)
4108 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 4109 swap_operands ();
4110
ec56d5c0
JB		 4111 /* The order of the immediates should be reversed
4112 for 2 immediates extrq and insertq instructions */
4113 if (i.imm_operands == 2
4114 && (strcmp (mnemonic, "extrq") == 0
4115 || strcmp (mnemonic, "insertq") == 0))
4116 swap_2_operands (0, 1);
4117
29b0f896
AM		 4118 if (i.imm_operands)
4119 optimize_imm ();
4120
b300c311
L		 4121 /* Don't optimize displacement for movabs since it only takes 64bit
4122 displacement. */
4123 if (i.disp_operands
a501d77e 4124 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 4125 && (flag_code != CODE_64BIT
4126 || strcmp (mnemonic, "movabs") != 0))
4127 optimize_disp ();
29b0f896
AM		 4128
4129 /* Next, we find a template that matches the given insn,
4130 making sure the overlap of the given operands types is consistent
4131 with the template operand types. */
252b5132 4132
83b16ac6 4133 if (!(t = match_template (mnem_suffix)))
29b0f896 4134 return;
252b5132 4135
7bab8ab5 4136 if (sse_check != check_none
81f8a913 4137 && !i.tm.opcode_modifier.noavx
6e3e5c9e 4138 && !i.tm.cpu_flags.bitfield.cpuavx
daf50ae7
L		 4139 && (i.tm.cpu_flags.bitfield.cpusse
4140 || i.tm.cpu_flags.bitfield.cpusse2
4141 || i.tm.cpu_flags.bitfield.cpusse3
4142 || i.tm.cpu_flags.bitfield.cpussse3
4143 || i.tm.cpu_flags.bitfield.cpusse4_1
6e3e5c9e
JB		 4144 || i.tm.cpu_flags.bitfield.cpusse4_2
4145 || i.tm.cpu_flags.bitfield.cpupclmul
4146 || i.tm.cpu_flags.bitfield.cpuaes
4147 || i.tm.cpu_flags.bitfield.cpugfni))
daf50ae7 4148 {
7bab8ab5 4149 (sse_check == check_warning
daf50ae7
L		 4150 ? as_warn
4151 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
4152 }
4153
321fd21e
L		 4154 /* Zap movzx and movsx suffix. The suffix has been set from
4155 "word ptr" or "byte ptr" on the source operand in Intel syntax
4156 or extracted from mnemonic in AT&T syntax. But we'll use
4157 the destination register to choose the suffix for encoding. */
4158 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 4159 {
321fd21e
L		 4160 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4161 there is no suffix, the default will be byte extension. */
4162 if (i.reg_operands != 2
4163 && !i.suffix
7ab9ffdd 4164 && intel_syntax)
321fd21e
L		 4165 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4166
4167 i.suffix = 0;
cd61ebfe 4168 }
24eab124 4169
40fb9820 4170 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 4171 if (!add_prefix (FWAIT_OPCODE))
4172 return;
252b5132 4173
d5de92cf
L		 4174 /* Check if REP prefix is OK. */
4175 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
4176 {
4177 as_bad (_("invalid instruction `%s' after `%s'"),
4178 i.tm.name, i.rep_prefix);
4179 return;
4180 }
4181
c1ba0266
L		 4182 /* Check for lock without a lockable instruction. Destination operand
4183 must be memory unless it is xchg (0x86). */
c32fa91d
L		 4184 if (i.prefix[LOCK_PREFIX]
4185 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 4186 || i.mem_operands == 0
4187 || (i.tm.base_opcode != 0x86
4188 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 4189 {
4190 as_bad (_("expecting lockable instruction after `lock'"));
4191 return;
4192 }
4193
7a8655d2
JB		 4194 /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */
4195 if (i.prefix[DATA_PREFIX] && is_any_vex_encoding (&i.tm))
4196 {
4197 as_bad (_("data size prefix invalid with `%s'"), i.tm.name);
4198 return;
4199 }
4200
42164a71 4201 /* Check if HLE prefix is OK. */
165de32a 4202 if (i.hle_prefix && !check_hle ())
42164a71
L		 4203 return;
4204
7e8b059b
L		 4205 /* Check BND prefix. */
4206 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
4207 as_bad (_("expecting valid branch instruction after `bnd'"));
4208
04ef582a 4209 /* Check NOTRACK prefix. */
9fef80d6
L		 4210 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
4211 as_bad (_("expecting indirect branch instruction after `notrack'"));
04ef582a 4212
327e8c42
JB		 4213 if (i.tm.cpu_flags.bitfield.cpumpx)
4214 {
4215 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
4216 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4217 else if (flag_code != CODE_16BIT
4218 ? i.prefix[ADDR_PREFIX]
4219 : i.mem_operands && !i.prefix[ADDR_PREFIX])
4220 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4221 }
7e8b059b
L		 4222
4223 /* Insert BND prefix. */
76d3a78a
JB		 4224 if (add_bnd_prefix && i.tm.opcode_modifier.bndprefixok)
4225 {
4226 if (!i.prefix[BND_PREFIX])
4227 add_prefix (BND_PREFIX_OPCODE);
4228 else if (i.prefix[BND_PREFIX] != BND_PREFIX_OPCODE)
4229 {
4230 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4231 i.prefix[BND_PREFIX] = BND_PREFIX_OPCODE;
4232 }
4233 }
7e8b059b 4234
29b0f896 4235 /* Check string instruction segment overrides. */
40fb9820 4236 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 4237 {
4238 if (!check_string ())
5dd0794d 4239 return;
fc0763e6 4240 i.disp_operands = 0;
29b0f896 4241 }
5dd0794d 4242
b6f8c7c4
L		 4243 if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize)
4244 optimize_encoding ();
4245
29b0f896
AM		 4246 if (!process_suffix ())
4247 return;
e413e4e9 4248
bc0844ae
L		 4249 /* Update operand types. */
4250 for (j = 0; j < i.operands; j++)
4251 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
4252
29b0f896
AM		 4253 /* Make still unresolved immediate matches conform to size of immediate
4254 given in i.suffix. */
4255 if (!finalize_imm ())
4256 return;
252b5132 4257
40fb9820 4258 if (i.types[0].bitfield.imm1)
29b0f896 4259 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 4260
9afe6eb8
L		 4261 /* We only need to check those implicit registers for instructions
4262 with 3 operands or less. */
4263 if (i.operands <= 3)
4264 for (j = 0; j < i.operands; j++)
4265 if (i.types[j].bitfield.inoutportreg
4266 || i.types[j].bitfield.shiftcount
1b54b8d7 4267 || (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword))
9afe6eb8 4268 i.reg_operands--;
40fb9820 4269
c0f3af97
L		 4270 /* ImmExt should be processed after SSE2AVX. */
4271 if (!i.tm.opcode_modifier.sse2avx
4272 && i.tm.opcode_modifier.immext)
65da13b5 4273 process_immext ();
252b5132 4274
29b0f896
AM		 4275 /* For insns with operands there are more diddles to do to the opcode. */
4276 if (i.operands)
4277 {
4278 if (!process_operands ())
4279 return;
4280 }
40fb9820 4281 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 4282 {
4283 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4284 as_warn (_("translating to `%sp'"), i.tm.name);
4285 }
252b5132 4286
7a8655d2 4287 if (is_any_vex_encoding (&i.tm))
9e5e5283
L		 4288 {
4289 if (flag_code == CODE_16BIT)
4290 {
4291 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4292 i.tm.name);
4293 return;
4294 }
c0f3af97 4295
9e5e5283
L		 4296 if (i.tm.opcode_modifier.vex)
4297 build_vex_prefix (t);
4298 else
4299 build_evex_prefix ();
4300 }
43234a1e 4301
5dd85c99
SP		 4302 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4303 instructions may define INT_OPCODE as well, so avoid this corner
4304 case for those instructions that use MODRM. */
4305 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 4306 && !i.tm.opcode_modifier.modrm
4307 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 4308 {
4309 i.tm.base_opcode = INT3_OPCODE;
4310 i.imm_operands = 0;
4311 }
252b5132 4312
40fb9820
L		 4313 if ((i.tm.opcode_modifier.jump
4314 || i.tm.opcode_modifier.jumpbyte
4315 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 4316 && i.op[0].disps->X_op == O_constant)
4317 {
4318 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4319 the absolute address given by the constant. Since ix86 jumps and
4320 calls are pc relative, we need to generate a reloc. */
4321 i.op[0].disps->X_add_symbol = &abs_symbol;
4322 i.op[0].disps->X_op = O_symbol;
4323 }
252b5132 4324
40fb9820 4325 if (i.tm.opcode_modifier.rex64)
161a04f6 4326 i.rex |= REX_W;
252b5132 4327
29b0f896
AM		 4328 /* For 8 bit registers we need an empty rex prefix. Also if the
4329 instruction already has a prefix, we need to convert old
4330 registers to new ones. */
773f551c 4331
dc821c5f 4332 if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte
29b0f896 4333 && (i.op[0].regs->reg_flags & RegRex64) != 0)
dc821c5f 4334 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte
29b0f896 4335 && (i.op[1].regs->reg_flags & RegRex64) != 0)
dc821c5f
JB		 4336 || (((i.types[0].bitfield.reg && i.types[0].bitfield.byte)
4337 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte))
29b0f896
AM		 4338 && i.rex != 0))
4339 {
4340 int x;
726c5dcd 4341
29b0f896
AM		 4342 i.rex |= REX_OPCODE;
4343 for (x = 0; x < 2; x++)
4344 {
4345 /* Look for 8 bit operand that uses old registers. */
dc821c5f 4346 if (i.types[x].bitfield.reg && i.types[x].bitfield.byte
29b0f896 4347 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 4348 {
29b0f896
AM		 4349 /* In case it is "hi" register, give up. */
4350 if (i.op[x].regs->reg_num > 3)
a540244d 4351 as_bad (_("can't encode register '%s%s' in an "
4eed87de 4352 "instruction requiring REX prefix."),
a540244d 4353 register_prefix, i.op[x].regs->reg_name);
773f551c 4354
29b0f896
AM		 4355 /* Otherwise it is equivalent to the extended register.
4356 Since the encoding doesn't change this is merely
4357 cosmetic cleanup for debug output. */
4358
4359 i.op[x].regs = i.op[x].regs + 8;
773f551c 4360 }
29b0f896
AM		 4361 }
4362 }
773f551c 4363
6b6b6807
L		 4364 if (i.rex == 0 && i.rex_encoding)
4365 {
4366 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4367 that uses legacy register. If it is "hi" register, don't add
4368 the REX_OPCODE byte. */
4369 int x;
4370 for (x = 0; x < 2; x++)
4371 if (i.types[x].bitfield.reg
4372 && i.types[x].bitfield.byte
4373 && (i.op[x].regs->reg_flags & RegRex64) == 0
4374 && i.op[x].regs->reg_num > 3)
4375 {
4376 i.rex_encoding = FALSE;
4377 break;
4378 }
4379
4380 if (i.rex_encoding)
4381 i.rex = REX_OPCODE;
4382 }
4383
7ab9ffdd 4384 if (i.rex != 0)
29b0f896
AM		 4385 add_prefix (REX_OPCODE | i.rex);
4386
4387 /* We are ready to output the insn. */
4388 output_insn ();
4389}
4390
4391static char *
e3bb37b5 4392parse_insn (char *line, char *mnemonic)
29b0f896
AM		 4393{
4394 char *l = line;
4395 char *token_start = l;
4396 char *mnem_p;
5c6af06e 4397 int supported;
d3ce72d0 4398 const insn_template *t;
b6169b20 4399 char *dot_p = NULL;
29b0f896 4400
29b0f896
AM		 4401 while (1)
4402 {
4403 mnem_p = mnemonic;
4404 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
4405 {
b6169b20
L		 4406 if (*mnem_p == '.')
4407 dot_p = mnem_p;
29b0f896
AM		 4408 mnem_p++;
4409 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 4410 {
29b0f896
AM		 4411 as_bad (_("no such instruction: `%s'"), token_start);
4412 return NULL;
4413 }
4414 l++;
4415 }
4416 if (!is_space_char (*l)
4417 && *l != END_OF_INSN
e44823cf
JB		 4418 && (intel_syntax
4419 || (*l != PREFIX_SEPARATOR
4420 && *l != ',')))
29b0f896
AM		 4421 {
4422 as_bad (_("invalid character %s in mnemonic"),
4423 output_invalid (*l));
4424 return NULL;
4425 }
4426 if (token_start == l)
4427 {
e44823cf 4428 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 4429 as_bad (_("expecting prefix; got nothing"));
4430 else
4431 as_bad (_("expecting mnemonic; got nothing"));
4432 return NULL;
4433 }
45288df1 4434
29b0f896 4435 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 4436 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 4437
29b0f896
AM		 4438 if (*l != END_OF_INSN
4439 && (!is_space_char (*l) || l[1] != END_OF_INSN)
4440 && current_templates
40fb9820 4441 && current_templates->start->opcode_modifier.isprefix)
29b0f896 4442 {
c6fb90c8 4443 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 4444 {
4445 as_bad ((flag_code != CODE_64BIT
4446 ? _("`%s' is only supported in 64-bit mode")
4447 : _("`%s' is not supported in 64-bit mode")),
4448 current_templates->start->name);
4449 return NULL;
4450 }
29b0f896
AM		 4451 /* If we are in 16-bit mode, do not allow addr16 or data16.
4452 Similarly, in 32-bit mode, do not allow addr32 or data32. */
673fe0f0
JB		 4453 if ((current_templates->start->opcode_modifier.size == SIZE16
4454 || current_templates->start->opcode_modifier.size == SIZE32)
29b0f896 4455 && flag_code != CODE_64BIT
673fe0f0 4456 && ((current_templates->start->opcode_modifier.size == SIZE32)
29b0f896
AM		 4457 ^ (flag_code == CODE_16BIT)))
4458 {
4459 as_bad (_("redundant %s prefix"),
4460 current_templates->start->name);
4461 return NULL;
45288df1 4462 }
86fa6981 4463 if (current_templates->start->opcode_length == 0)
29b0f896 4464 {
86fa6981
L		 4465 /* Handle pseudo prefixes. */
4466 switch (current_templates->start->base_opcode)
4467 {
4468 case 0x0:
4469 /* {disp8} */
4470 i.disp_encoding = disp_encoding_8bit;
4471 break;
4472 case 0x1:
4473 /* {disp32} */
4474 i.disp_encoding = disp_encoding_32bit;
4475 break;
4476 case 0x2:
4477 /* {load} */
4478 i.dir_encoding = dir_encoding_load;
4479 break;
4480 case 0x3:
4481 /* {store} */
4482 i.dir_encoding = dir_encoding_store;
4483 break;
4484 case 0x4:
4485 /* {vex2} */
4486 i.vec_encoding = vex_encoding_vex2;
4487 break;
4488 case 0x5:
4489 /* {vex3} */
4490 i.vec_encoding = vex_encoding_vex3;
4491 break;
4492 case 0x6:
4493 /* {evex} */
4494 i.vec_encoding = vex_encoding_evex;
4495 break;
6b6b6807
L		 4496 case 0x7:
4497 /* {rex} */
4498 i.rex_encoding = TRUE;
4499 break;
b6f8c7c4
L		 4500 case 0x8:
4501 /* {nooptimize} */
4502 i.no_optimize = TRUE;
4503 break;
86fa6981
L		 4504 default:
4505 abort ();
4506 }
4507 }
4508 else
4509 {
4510 /* Add prefix, checking for repeated prefixes. */
4e9ac44a 4511 switch (add_prefix (current_templates->start->base_opcode))
86fa6981 4512 {
4e9ac44a
L		 4513 case PREFIX_EXIST:
4514 return NULL;
4515 case PREFIX_DS:
d777820b 4516 if (current_templates->start->cpu_flags.bitfield.cpuibt)
4e9ac44a
L		 4517 i.notrack_prefix = current_templates->start->name;
4518 break;
4519 case PREFIX_REP:
4520 if (current_templates->start->cpu_flags.bitfield.cpuhle)
4521 i.hle_prefix = current_templates->start->name;
4522 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
4523 i.bnd_prefix = current_templates->start->name;
4524 else
4525 i.rep_prefix = current_templates->start->name;
4526 break;
4527 default:
4528 break;
86fa6981 4529 }
29b0f896
AM		 4530 }
4531 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4532 token_start = ++l;
4533 }
4534 else
4535 break;
4536 }
45288df1 4537
30a55f88 4538 if (!current_templates)
b6169b20 4539 {
07d5e953
JB		 4540 /* Deprecated functionality (new code should use pseudo-prefixes instead):
4541 Check if we should swap operand or force 32bit displacement in
f8a5c266 4542 encoding. */
30a55f88 4543 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
64c49ab3 4544 i.dir_encoding = dir_encoding_swap;
8d63c93e 4545 else if (mnem_p - 3 == dot_p
a501d77e
L		 4546 && dot_p[1] == 'd'
4547 && dot_p[2] == '8')
4548 i.disp_encoding = disp_encoding_8bit;
8d63c93e 4549 else if (mnem_p - 4 == dot_p
f8a5c266
L		 4550 && dot_p[1] == 'd'
4551 && dot_p[2] == '3'
4552 && dot_p[3] == '2')
a501d77e 4553 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 4554 else
4555 goto check_suffix;
4556 mnem_p = dot_p;
4557 *dot_p = '\0';
d3ce72d0 4558 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 4559 }
4560
29b0f896
AM		 4561 if (!current_templates)
4562 {
b6169b20 4563check_suffix:
29b0f896
AM		 4564 /* See if we can get a match by trimming off a suffix. */
4565 switch (mnem_p[-1])
4566 {
4567 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 4568 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
4569 i.suffix = SHORT_MNEM_SUFFIX;
4570 else
1a0670f3 4571 /* Fall through. */
29b0f896
AM		 4572 case BYTE_MNEM_SUFFIX:
4573 case QWORD_MNEM_SUFFIX:
4574 i.suffix = mnem_p[-1];
4575 mnem_p[-1] = '\0';
d3ce72d0
NC		 4576 current_templates = (const templates *) hash_find (op_hash,
4577 mnemonic);
29b0f896
AM		 4578 break;
4579 case SHORT_MNEM_SUFFIX:
4580 case LONG_MNEM_SUFFIX:
4581 if (!intel_syntax)
4582 {
4583 i.suffix = mnem_p[-1];
4584 mnem_p[-1] = '\0';
d3ce72d0
NC		 4585 current_templates = (const templates *) hash_find (op_hash,
4586 mnemonic);
29b0f896
AM		 4587 }
4588 break;
252b5132 4589
29b0f896
AM		 4590 /* Intel Syntax. */
4591 case 'd':
4592 if (intel_syntax)
4593 {
9306ca4a 4594 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 4595 i.suffix = SHORT_MNEM_SUFFIX;
4596 else
4597 i.suffix = LONG_MNEM_SUFFIX;
4598 mnem_p[-1] = '\0';
d3ce72d0
NC		 4599 current_templates = (const templates *) hash_find (op_hash,
4600 mnemonic);
29b0f896
AM		 4601 }
4602 break;
4603 }
4604 if (!current_templates)
4605 {
4606 as_bad (_("no such instruction: `%s'"), token_start);
4607 return NULL;
4608 }
4609 }
252b5132 4610
40fb9820
L		 4611 if (current_templates->start->opcode_modifier.jump
4612 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 4613 {
4614 /* Check for a branch hint. We allow ",pt" and ",pn" for
4615 predict taken and predict not taken respectively.
4616 I'm not sure that branch hints actually do anything on loop
4617 and jcxz insns (JumpByte) for current Pentium4 chips. They
4618 may work in the future and it doesn't hurt to accept them
4619 now. */
4620 if (l[0] == ',' && l[1] == 'p')
4621 {
4622 if (l[2] == 't')
4623 {
4624 if (!add_prefix (DS_PREFIX_OPCODE))
4625 return NULL;
4626 l += 3;
4627 }
4628 else if (l[2] == 'n')
4629 {
4630 if (!add_prefix (CS_PREFIX_OPCODE))
4631 return NULL;
4632 l += 3;
4633 }
4634 }
4635 }
4636 /* Any other comma loses. */
4637 if (*l == ',')
4638 {
4639 as_bad (_("invalid character %s in mnemonic"),
4640 output_invalid (*l));
4641 return NULL;
4642 }
252b5132 4643
29b0f896 4644 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 4645 supported = 0;
4646 for (t = current_templates->start; t < current_templates->end; ++t)
4647 {
c0f3af97
L		 4648 supported |= cpu_flags_match (t);
4649 if (supported == CPU_FLAGS_PERFECT_MATCH)
548d0ee6
JB		 4650 {
4651 if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT))
4652 as_warn (_("use .code16 to ensure correct addressing mode"));
3629bb00 4653
548d0ee6
JB		 4654 return l;
4655 }
29b0f896 4656 }
3629bb00 4657
548d0ee6
JB		 4658 if (!(supported & CPU_FLAGS_64BIT_MATCH))
4659 as_bad (flag_code == CODE_64BIT
4660 ? _("`%s' is not supported in 64-bit mode")
4661 : _("`%s' is only supported in 64-bit mode"),
4662 current_templates->start->name);
4663 else
4664 as_bad (_("`%s' is not supported on `%s%s'"),
4665 current_templates->start->name,
4666 cpu_arch_name ? cpu_arch_name : default_arch,
4667 cpu_sub_arch_name ? cpu_sub_arch_name : "");
252b5132 4668
548d0ee6 4669 return NULL;
29b0f896 4670}
252b5132 4671
29b0f896 4672static char *
e3bb37b5 4673parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 4674{
4675 char *token_start;
3138f287 4676
29b0f896
AM		 4677 /* 1 if operand is pending after ','. */
4678 unsigned int expecting_operand = 0;
252b5132 4679
29b0f896
AM		 4680 /* Non-zero if operand parens not balanced. */
4681 unsigned int paren_not_balanced;
4682
4683 while (*l != END_OF_INSN)
4684 {
4685 /* Skip optional white space before operand. */
4686 if (is_space_char (*l))
4687 ++l;
d02603dc 4688 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
29b0f896
AM		 4689 {
4690 as_bad (_("invalid character %s before operand %d"),
4691 output_invalid (*l),
4692 i.operands + 1);
4693 return NULL;
4694 }
d02603dc 4695 token_start = l; /* After white space. */
29b0f896
AM		 4696 paren_not_balanced = 0;
4697 while (paren_not_balanced || *l != ',')
4698 {
4699 if (*l == END_OF_INSN)
4700 {
4701 if (paren_not_balanced)
4702 {
4703 if (!intel_syntax)
4704 as_bad (_("unbalanced parenthesis in operand %d."),
4705 i.operands + 1);
4706 else
4707 as_bad (_("unbalanced brackets in operand %d."),
4708 i.operands + 1);
4709 return NULL;
4710 }
4711 else
4712 break; /* we are done */
4713 }
d02603dc 4714 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
29b0f896
AM		 4715 {
4716 as_bad (_("invalid character %s in operand %d"),
4717 output_invalid (*l),
4718 i.operands + 1);
4719 return NULL;
4720 }
4721 if (!intel_syntax)
4722 {
4723 if (*l == '(')
4724 ++paren_not_balanced;
4725 if (*l == ')')
4726 --paren_not_balanced;
4727 }
4728 else
4729 {
4730 if (*l == '[')
4731 ++paren_not_balanced;
4732 if (*l == ']')
4733 --paren_not_balanced;
4734 }
4735 l++;
4736 }
4737 if (l != token_start)
4738 { /* Yes, we've read in another operand. */
4739 unsigned int operand_ok;
4740 this_operand = i.operands++;
4741 if (i.operands > MAX_OPERANDS)
4742 {
4743 as_bad (_("spurious operands; (%d operands/instruction max)"),
4744 MAX_OPERANDS);
4745 return NULL;
4746 }
9d46ce34 4747 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 4748 /* Now parse operand adding info to 'i' as we go along. */
4749 END_STRING_AND_SAVE (l);
4750
1286ab78
L		 4751 if (i.mem_operands > 1)
4752 {
4753 as_bad (_("too many memory references for `%s'"),
4754 mnemonic);
4755 return 0;
4756 }
4757
29b0f896
AM		 4758 if (intel_syntax)
4759 operand_ok =
4760 i386_intel_operand (token_start,
4761 intel_float_operand (mnemonic));
4762 else
a7619375 4763 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 4764
4765 RESTORE_END_STRING (l);
4766 if (!operand_ok)
4767 return NULL;
4768 }
4769 else
4770 {
4771 if (expecting_operand)
4772 {
4773 expecting_operand_after_comma:
4774 as_bad (_("expecting operand after ','; got nothing"));
4775 return NULL;
4776 }
4777 if (*l == ',')
4778 {
4779 as_bad (_("expecting operand before ','; got nothing"));
4780 return NULL;
4781 }
4782 }
7f3f1ea2 4783
29b0f896
AM		 4784 /* Now *l must be either ',' or END_OF_INSN. */
4785 if (*l == ',')
4786 {
4787 if (*++l == END_OF_INSN)
4788 {
4789 /* Just skip it, if it's \n complain. */
4790 goto expecting_operand_after_comma;
4791 }
4792 expecting_operand = 1;
4793 }
4794 }
4795 return l;
4796}
7f3f1ea2 4797
050dfa73 4798static void
4d456e3d 4799swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 4800{
4801 union i386_op temp_op;
40fb9820 4802 i386_operand_type temp_type;
c48dadc9 4803 unsigned int temp_flags;
050dfa73 4804 enum bfd_reloc_code_real temp_reloc;
4eed87de 4805
050dfa73
MM		 4806 temp_type = i.types[xchg2];
4807 i.types[xchg2] = i.types[xchg1];
4808 i.types[xchg1] = temp_type;
c48dadc9
JB		 4809
4810 temp_flags = i.flags[xchg2];
4811 i.flags[xchg2] = i.flags[xchg1];
4812 i.flags[xchg1] = temp_flags;
4813
050dfa73
MM		 4814 temp_op = i.op[xchg2];
4815 i.op[xchg2] = i.op[xchg1];
4816 i.op[xchg1] = temp_op;
c48dadc9 4817
050dfa73
MM		 4818 temp_reloc = i.reloc[xchg2];
4819 i.reloc[xchg2] = i.reloc[xchg1];
4820 i.reloc[xchg1] = temp_reloc;
43234a1e
L		 4821
4822 if (i.mask)
4823 {
4824 if (i.mask->operand == xchg1)
4825 i.mask->operand = xchg2;
4826 else if (i.mask->operand == xchg2)
4827 i.mask->operand = xchg1;
4828 }
4829 if (i.broadcast)
4830 {
4831 if (i.broadcast->operand == xchg1)
4832 i.broadcast->operand = xchg2;
4833 else if (i.broadcast->operand == xchg2)
4834 i.broadcast->operand = xchg1;
4835 }
4836 if (i.rounding)
4837 {
4838 if (i.rounding->operand == xchg1)
4839 i.rounding->operand = xchg2;
4840 else if (i.rounding->operand == xchg2)
4841 i.rounding->operand = xchg1;
4842 }
050dfa73
MM		 4843}
4844
29b0f896 4845static void
e3bb37b5 4846swap_operands (void)
29b0f896 4847{
b7c61d9a 4848 switch (i.operands)
050dfa73 4849 {
c0f3af97 4850 case 5:
b7c61d9a 4851 case 4:
4d456e3d 4852 swap_2_operands (1, i.operands - 2);
1a0670f3 4853 /* Fall through. */
b7c61d9a
L		 4854 case 3:
4855 case 2:
4d456e3d 4856 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 4857 break;
4858 default:
4859 abort ();
29b0f896 4860 }
29b0f896
AM		 4861
4862 if (i.mem_operands == 2)
4863 {
4864 const seg_entry *temp_seg;
4865 temp_seg = i.seg[0];
4866 i.seg[0] = i.seg[1];
4867 i.seg[1] = temp_seg;
4868 }
4869}
252b5132 4870
29b0f896
AM		 4871/* Try to ensure constant immediates are represented in the smallest
4872 opcode possible. */
4873static void
e3bb37b5 4874optimize_imm (void)
29b0f896
AM		 4875{
4876 char guess_suffix = 0;
4877 int op;
252b5132 4878
29b0f896
AM		 4879 if (i.suffix)
4880 guess_suffix = i.suffix;
4881 else if (i.reg_operands)
4882 {
4883 /* Figure out a suffix from the last register operand specified.
4884 We can't do this properly yet, ie. excluding InOutPortReg,
4885 but the following works for instructions with immediates.
4886 In any case, we can't set i.suffix yet. */
4887 for (op = i.operands; --op >= 0;)
dc821c5f 4888 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
7ab9ffdd 4889 {
40fb9820
L		 4890 guess_suffix = BYTE_MNEM_SUFFIX;
4891 break;
4892 }
dc821c5f 4893 else if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
252b5132 4894 {
40fb9820
L		 4895 guess_suffix = WORD_MNEM_SUFFIX;
4896 break;
4897 }
dc821c5f 4898 else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
40fb9820
L		 4899 {
4900 guess_suffix = LONG_MNEM_SUFFIX;
4901 break;
4902 }
dc821c5f 4903 else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
40fb9820
L		 4904 {
4905 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 4906 break;
252b5132 4907 }
29b0f896
AM		 4908 }
4909 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4910 guess_suffix = WORD_MNEM_SUFFIX;
4911
4912 for (op = i.operands; --op >= 0;)
40fb9820 4913 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 4914 {
4915 switch (i.op[op].imms->X_op)
252b5132 4916 {
29b0f896
AM		 4917 case O_constant:
4918 /* If a suffix is given, this operand may be shortened. */
4919 switch (guess_suffix)
252b5132 4920 {
29b0f896 4921 case LONG_MNEM_SUFFIX:
40fb9820
L		 4922 i.types[op].bitfield.imm32 = 1;
4923 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4924 break;
4925 case WORD_MNEM_SUFFIX:
40fb9820
L		 4926 i.types[op].bitfield.imm16 = 1;
4927 i.types[op].bitfield.imm32 = 1;
4928 i.types[op].bitfield.imm32s = 1;
4929 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4930 break;
4931 case BYTE_MNEM_SUFFIX:
40fb9820
L		 4932 i.types[op].bitfield.imm8 = 1;
4933 i.types[op].bitfield.imm8s = 1;
4934 i.types[op].bitfield.imm16 = 1;
4935 i.types[op].bitfield.imm32 = 1;
4936 i.types[op].bitfield.imm32s = 1;
4937 i.types[op].bitfield.imm64 = 1;
29b0f896 4938 break;
252b5132 4939 }
252b5132 4940
29b0f896
AM		 4941 /* If this operand is at most 16 bits, convert it
4942 to a signed 16 bit number before trying to see
4943 whether it will fit in an even smaller size.
4944 This allows a 16-bit operand such as $0xffe0 to
4945 be recognised as within Imm8S range. */
40fb9820 4946 if ((i.types[op].bitfield.imm16)
29b0f896 4947 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 4948 {
29b0f896
AM		 4949 i.op[op].imms->X_add_number =
4950 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4951 }
a28def75
L		 4952#ifdef BFD64
4953 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
40fb9820 4954 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 4955 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4956 == 0))
4957 {
4958 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4959 ^ ((offsetT) 1 << 31))
4960 - ((offsetT) 1 << 31));
4961 }
a28def75 4962#endif
40fb9820 4963 i.types[op]
c6fb90c8
L		 4964 = operand_type_or (i.types[op],
4965 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 4966
29b0f896
AM		 4967 /* We must avoid matching of Imm32 templates when 64bit
4968 only immediate is available. */
4969 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 4970 i.types[op].bitfield.imm32 = 0;
29b0f896 4971 break;
252b5132 4972
29b0f896
AM		 4973 case O_absent:
4974 case O_register:
4975 abort ();
4976
4977 /* Symbols and expressions. */
4978 default:
9cd96992
JB		 4979 /* Convert symbolic operand to proper sizes for matching, but don't
4980 prevent matching a set of insns that only supports sizes other
4981 than those matching the insn suffix. */
4982 {
40fb9820 4983 i386_operand_type mask, allowed;
d3ce72d0 4984 const insn_template *t;
9cd96992 4985
0dfbf9d7
L		 4986 operand_type_set (&mask, 0);
4987 operand_type_set (&allowed, 0);
40fb9820 4988
4eed87de
AM		 4989 for (t = current_templates->start;
4990 t < current_templates->end;
4991 ++t)
c6fb90c8
L		 4992 allowed = operand_type_or (allowed,
4993 t->operand_types[op]);
9cd96992
JB		 4994 switch (guess_suffix)
4995 {
4996 case QWORD_MNEM_SUFFIX:
40fb9820
L		 4997 mask.bitfield.imm64 = 1;
4998 mask.bitfield.imm32s = 1;
9cd96992
JB		 4999 break;
5000 case LONG_MNEM_SUFFIX:
40fb9820 5001 mask.bitfield.imm32 = 1;
9cd96992
JB		 5002 break;
5003 case WORD_MNEM_SUFFIX:
40fb9820 5004 mask.bitfield.imm16 = 1;
9cd96992
JB		 5005 break;
5006 case BYTE_MNEM_SUFFIX:
40fb9820 5007 mask.bitfield.imm8 = 1;
9cd96992
JB		 5008 break;
5009 default:
9cd96992
JB		 5010 break;
5011 }
c6fb90c8 5012 allowed = operand_type_and (mask, allowed);
0dfbf9d7 5013 if (!operand_type_all_zero (&allowed))
c6fb90c8 5014 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 5015 }
29b0f896 5016 break;
252b5132 5017 }
29b0f896
AM		 5018 }
5019}
47926f60 5020
29b0f896
AM		 5021/* Try to use the smallest displacement type too. */
5022static void
e3bb37b5 5023optimize_disp (void)
29b0f896
AM		 5024{
5025 int op;
3e73aa7c 5026
29b0f896 5027 for (op = i.operands; --op >= 0;)
40fb9820 5028 if (operand_type_check (i.types[op], disp))
252b5132 5029 {
b300c311 5030 if (i.op[op].disps->X_op == O_constant)
252b5132 5031 {
91d6fa6a 5032 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 5033
40fb9820 5034 if (i.types[op].bitfield.disp16
91d6fa6a 5035 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 5036 {
5037 /* If this operand is at most 16 bits, convert
5038 to a signed 16 bit number and don't use 64bit
5039 displacement. */
91d6fa6a 5040 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 5041 i.types[op].bitfield.disp64 = 0;
b300c311 5042 }
a28def75
L		 5043#ifdef BFD64
5044 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
40fb9820 5045 if (i.types[op].bitfield.disp32
91d6fa6a 5046 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 5047 {
5048 /* If this operand is at most 32 bits, convert
5049 to a signed 32 bit number and don't use 64bit
5050 displacement. */
91d6fa6a
NC		 5051 op_disp &= (((offsetT) 2 << 31) - 1);
5052 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 5053 i.types[op].bitfield.disp64 = 0;
b300c311 5054 }
a28def75 5055#endif
91d6fa6a 5056 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 5057 {
40fb9820
L		 5058 i.types[op].bitfield.disp8 = 0;
5059 i.types[op].bitfield.disp16 = 0;
5060 i.types[op].bitfield.disp32 = 0;
5061 i.types[op].bitfield.disp32s = 0;
5062 i.types[op].bitfield.disp64 = 0;
b300c311
L		 5063 i.op[op].disps = 0;
5064 i.disp_operands--;
5065 }
5066 else if (flag_code == CODE_64BIT)
5067 {
91d6fa6a 5068 if (fits_in_signed_long (op_disp))
28a9d8f5 5069 {
40fb9820
L		 5070 i.types[op].bitfield.disp64 = 0;
5071 i.types[op].bitfield.disp32s = 1;
28a9d8f5 5072 }
0e1147d9 5073 if (i.prefix[ADDR_PREFIX]
91d6fa6a 5074 && fits_in_unsigned_long (op_disp))
40fb9820 5075 i.types[op].bitfield.disp32 = 1;
b300c311 5076 }
40fb9820
L		 5077 if ((i.types[op].bitfield.disp32
5078 || i.types[op].bitfield.disp32s
5079 || i.types[op].bitfield.disp16)
b5014f7a 5080 && fits_in_disp8 (op_disp))
40fb9820 5081 i.types[op].bitfield.disp8 = 1;
252b5132 5082 }
67a4f2b7
AO		 5083 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
5084 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
5085 {
5086 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
5087 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 5088 i.types[op].bitfield.disp8 = 0;
5089 i.types[op].bitfield.disp16 = 0;
5090 i.types[op].bitfield.disp32 = 0;
5091 i.types[op].bitfield.disp32s = 0;
5092 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 5093 }
5094 else
b300c311 5095 /* We only support 64bit displacement on constants. */
40fb9820 5096 i.types[op].bitfield.disp64 = 0;
252b5132 5097 }
29b0f896
AM		 5098}
5099
4a1b91ea
L		 5100/* Return 1 if there is a match in broadcast bytes between operand
5101 GIVEN and instruction template T. */
5102
5103static INLINE int
5104match_broadcast_size (const insn_template *t, unsigned int given)
5105{
5106 return ((t->opcode_modifier.broadcast == BYTE_BROADCAST
5107 && i.types[given].bitfield.byte)
5108 || (t->opcode_modifier.broadcast == WORD_BROADCAST
5109 && i.types[given].bitfield.word)
5110 || (t->opcode_modifier.broadcast == DWORD_BROADCAST
5111 && i.types[given].bitfield.dword)
5112 || (t->opcode_modifier.broadcast == QWORD_BROADCAST
5113 && i.types[given].bitfield.qword));
5114}
5115
6c30d220
L		 5116/* Check if operands are valid for the instruction. */
5117
5118static int
5119check_VecOperands (const insn_template *t)
5120{
43234a1e 5121 unsigned int op;
e2195274
JB		 5122 i386_cpu_flags cpu;
5123 static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS;
5124
5125 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5126 any one operand are implicity requiring AVX512VL support if the actual
5127 operand size is YMMword or XMMword. Since this function runs after
5128 template matching, there's no need to check for YMMword/XMMword in
5129 the template. */
5130 cpu = cpu_flags_and (t->cpu_flags, avx512);
5131 if (!cpu_flags_all_zero (&cpu)
5132 && !t->cpu_flags.bitfield.cpuavx512vl
5133 && !cpu_arch_flags.bitfield.cpuavx512vl)
5134 {
5135 for (op = 0; op < t->operands; ++op)
5136 {
5137 if (t->operand_types[op].bitfield.zmmword
5138 && (i.types[op].bitfield.ymmword
5139 || i.types[op].bitfield.xmmword))
5140 {
5141 i.error = unsupported;
5142 return 1;
5143 }
5144 }
5145 }
43234a1e 5146
6c30d220
L		 5147 /* Without VSIB byte, we can't have a vector register for index. */
5148 if (!t->opcode_modifier.vecsib
5149 && i.index_reg
1b54b8d7
JB		 5150 && (i.index_reg->reg_type.bitfield.xmmword
5151 || i.index_reg->reg_type.bitfield.ymmword
5152 || i.index_reg->reg_type.bitfield.zmmword))
6c30d220
L		 5153 {
5154 i.error = unsupported_vector_index_register;
5155 return 1;
5156 }
5157
ad8ecc81
MZ		 5158 /* Check if default mask is allowed. */
5159 if (t->opcode_modifier.nodefmask
5160 && (!i.mask || i.mask->mask->reg_num == 0))
5161 {
5162 i.error = no_default_mask;
5163 return 1;
5164 }
5165
7bab8ab5
JB		 5166 /* For VSIB byte, we need a vector register for index, and all vector
5167 registers must be distinct. */
5168 if (t->opcode_modifier.vecsib)
5169 {
5170 if (!i.index_reg
6c30d220 5171 || !((t->opcode_modifier.vecsib == VecSIB128
1b54b8d7 5172 && i.index_reg->reg_type.bitfield.xmmword)
6c30d220 5173 || (t->opcode_modifier.vecsib == VecSIB256
1b54b8d7 5174 && i.index_reg->reg_type.bitfield.ymmword)
43234a1e 5175 || (t->opcode_modifier.vecsib == VecSIB512
1b54b8d7 5176 && i.index_reg->reg_type.bitfield.zmmword)))
7bab8ab5
JB		 5177 {
5178 i.error = invalid_vsib_address;
5179 return 1;
5180 }
5181
43234a1e
L		 5182 gas_assert (i.reg_operands == 2 || i.mask);
5183 if (i.reg_operands == 2 && !i.mask)
5184 {
1b54b8d7
JB		 5185 gas_assert (i.types[0].bitfield.regsimd);
5186 gas_assert (i.types[0].bitfield.xmmword
5187 || i.types[0].bitfield.ymmword);
5188 gas_assert (i.types[2].bitfield.regsimd);
5189 gas_assert (i.types[2].bitfield.xmmword
5190 || i.types[2].bitfield.ymmword);
43234a1e
L		 5191 if (operand_check == check_none)
5192 return 0;
5193 if (register_number (i.op[0].regs)
5194 != register_number (i.index_reg)
5195 && register_number (i.op[2].regs)
5196 != register_number (i.index_reg)
5197 && register_number (i.op[0].regs)
5198 != register_number (i.op[2].regs))
5199 return 0;
5200 if (operand_check == check_error)
5201 {
5202 i.error = invalid_vector_register_set;
5203 return 1;
5204 }
5205 as_warn (_("mask, index, and destination registers should be distinct"));
5206 }
8444f82a
MZ		 5207 else if (i.reg_operands == 1 && i.mask)
5208 {
1b54b8d7
JB		 5209 if (i.types[1].bitfield.regsimd
5210 && (i.types[1].bitfield.xmmword
5211 || i.types[1].bitfield.ymmword
5212 || i.types[1].bitfield.zmmword)
8444f82a
MZ		 5213 && (register_number (i.op[1].regs)
5214 == register_number (i.index_reg)))
5215 {
5216 if (operand_check == check_error)
5217 {
5218 i.error = invalid_vector_register_set;
5219 return 1;
5220 }
5221 if (operand_check != check_none)
5222 as_warn (_("index and destination registers should be distinct"));
5223 }
5224 }
43234a1e 5225 }
7bab8ab5 5226
43234a1e
L		 5227 /* Check if broadcast is supported by the instruction and is applied
5228 to the memory operand. */
5229 if (i.broadcast)
5230 {
8e6e0792 5231 i386_operand_type type, overlap;
43234a1e
L		 5232
5233 /* Check if specified broadcast is supported in this instruction,
4a1b91ea 5234 and its broadcast bytes match the memory operand. */
32546502 5235 op = i.broadcast->operand;
8e6e0792 5236 if (!t->opcode_modifier.broadcast
c48dadc9 5237 || !(i.flags[op] & Operand_Mem)
c39e5b26 5238 || (!i.types[op].bitfield.unspecified
4a1b91ea 5239 && !match_broadcast_size (t, op)))
43234a1e
L		 5240 {
5241 bad_broadcast:
5242 i.error = unsupported_broadcast;
5243 return 1;
5244 }
8e6e0792 5245
4a1b91ea
L		 5246 i.broadcast->bytes = ((1 << (t->opcode_modifier.broadcast - 1))
5247 * i.broadcast->type);
8e6e0792 5248 operand_type_set (&type, 0);
4a1b91ea 5249 switch (i.broadcast->bytes)
8e6e0792 5250 {
4a1b91ea
L		 5251 case 2:
5252 type.bitfield.word = 1;
5253 break;
5254 case 4:
5255 type.bitfield.dword = 1;
5256 break;
8e6e0792
JB		 5257 case 8:
5258 type.bitfield.qword = 1;
5259 break;
5260 case 16:
5261 type.bitfield.xmmword = 1;
5262 break;
5263 case 32:
5264 type.bitfield.ymmword = 1;
5265 break;
5266 case 64:
5267 type.bitfield.zmmword = 1;
5268 break;
5269 default:
5270 goto bad_broadcast;
5271 }
5272
5273 overlap = operand_type_and (type, t->operand_types[op]);
5274 if (operand_type_all_zero (&overlap))
5275 goto bad_broadcast;
5276
5277 if (t->opcode_modifier.checkregsize)
5278 {
5279 unsigned int j;
5280
e2195274 5281 type.bitfield.baseindex = 1;
8e6e0792
JB		 5282 for (j = 0; j < i.operands; ++j)
5283 {
5284 if (j != op
5285 && !operand_type_register_match(i.types[j],
5286 t->operand_types[j],
5287 type,
5288 t->operand_types[op]))
5289 goto bad_broadcast;
5290 }
5291 }
43234a1e
L		 5292 }
5293 /* If broadcast is supported in this instruction, we need to check if
5294 operand of one-element size isn't specified without broadcast. */
5295 else if (t->opcode_modifier.broadcast && i.mem_operands)
5296 {
5297 /* Find memory operand. */
5298 for (op = 0; op < i.operands; op++)
5299 if (operand_type_check (i.types[op], anymem))
5300 break;
5301 gas_assert (op < i.operands);
5302 /* Check size of the memory operand. */
4a1b91ea 5303 if (match_broadcast_size (t, op))
43234a1e
L		 5304 {
5305 i.error = broadcast_needed;
5306 return 1;
5307 }
5308 }
c39e5b26
JB		 5309 else
5310 op = MAX_OPERANDS - 1; /* Avoid uninitialized variable warning. */
43234a1e
L		 5311
5312 /* Check if requested masking is supported. */
ae2387fe 5313 if (i.mask)
43234a1e 5314 {
ae2387fe
JB		 5315 switch (t->opcode_modifier.masking)
5316 {
5317 case BOTH_MASKING:
5318 break;
5319 case MERGING_MASKING:
5320 if (i.mask->zeroing)
5321 {
5322 case 0:
5323 i.error = unsupported_masking;
5324 return 1;
5325 }
5326 break;
5327 case DYNAMIC_MASKING:
5328 /* Memory destinations allow only merging masking. */
5329 if (i.mask->zeroing && i.mem_operands)
5330 {
5331 /* Find memory operand. */
5332 for (op = 0; op < i.operands; op++)
c48dadc9 5333 if (i.flags[op] & Operand_Mem)
ae2387fe
JB		 5334 break;
5335 gas_assert (op < i.operands);
5336 if (op == i.operands - 1)
5337 {
5338 i.error = unsupported_masking;
5339 return 1;
5340 }
5341 }
5342 break;
5343 default:
5344 abort ();
5345 }
43234a1e
L		 5346 }
5347
5348 /* Check if masking is applied to dest operand. */
5349 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
5350 {
5351 i.error = mask_not_on_destination;
5352 return 1;
5353 }
5354
43234a1e
L		 5355 /* Check RC/SAE. */
5356 if (i.rounding)
5357 {
5358 if ((i.rounding->type != saeonly
5359 && !t->opcode_modifier.staticrounding)
5360 || (i.rounding->type == saeonly
5361 && (t->opcode_modifier.staticrounding
5362 || !t->opcode_modifier.sae)))
5363 {
5364 i.error = unsupported_rc_sae;
5365 return 1;
5366 }
5367 /* If the instruction has several immediate operands and one of
5368 them is rounding, the rounding operand should be the last
5369 immediate operand. */
5370 if (i.imm_operands > 1
5371 && i.rounding->operand != (int) (i.imm_operands - 1))
7bab8ab5 5372 {
43234a1e 5373 i.error = rc_sae_operand_not_last_imm;
7bab8ab5
JB		 5374 return 1;
5375 }
6c30d220
L		 5376 }
5377
43234a1e 5378 /* Check vector Disp8 operand. */
b5014f7a
JB		 5379 if (t->opcode_modifier.disp8memshift
5380 && i.disp_encoding != disp_encoding_32bit)
43234a1e
L		 5381 {
5382 if (i.broadcast)
4a1b91ea 5383 i.memshift = t->opcode_modifier.broadcast - 1;
7091c612 5384 else if (t->opcode_modifier.disp8memshift != DISP8_SHIFT_VL)
43234a1e 5385 i.memshift = t->opcode_modifier.disp8memshift;
7091c612
JB		 5386 else
5387 {
5388 const i386_operand_type *type = NULL;
5389
5390 i.memshift = 0;
5391 for (op = 0; op < i.operands; op++)
5392 if (operand_type_check (i.types[op], anymem))
5393 {
4174bfff
JB		 5394 if (t->opcode_modifier.evex == EVEXLIG)
5395 i.memshift = 2 + (i.suffix == QWORD_MNEM_SUFFIX);
5396 else if (t->operand_types[op].bitfield.xmmword
5397 + t->operand_types[op].bitfield.ymmword
5398 + t->operand_types[op].bitfield.zmmword <= 1)
7091c612
JB		 5399 type = &t->operand_types[op];
5400 else if (!i.types[op].bitfield.unspecified)
5401 type = &i.types[op];
5402 }
4174bfff
JB		 5403 else if (i.types[op].bitfield.regsimd
5404 && t->opcode_modifier.evex != EVEXLIG)
7091c612
JB		 5405 {
5406 if (i.types[op].bitfield.zmmword)
5407 i.memshift = 6;
5408 else if (i.types[op].bitfield.ymmword && i.memshift < 5)
5409 i.memshift = 5;
5410 else if (i.types[op].bitfield.xmmword && i.memshift < 4)
5411 i.memshift = 4;
5412 }
5413
5414 if (type)
5415 {
5416 if (type->bitfield.zmmword)
5417 i.memshift = 6;
5418 else if (type->bitfield.ymmword)
5419 i.memshift = 5;
5420 else if (type->bitfield.xmmword)
5421 i.memshift = 4;
5422 }
5423
5424 /* For the check in fits_in_disp8(). */
5425 if (i.memshift == 0)
5426 i.memshift = -1;
5427 }
43234a1e
L		 5428
5429 for (op = 0; op < i.operands; op++)
5430 if (operand_type_check (i.types[op], disp)
5431 && i.op[op].disps->X_op == O_constant)
5432 {
b5014f7a 5433 if (fits_in_disp8 (i.op[op].disps->X_add_number))
43234a1e 5434 {
b5014f7a
JB		 5435 i.types[op].bitfield.disp8 = 1;
5436 return 0;
43234a1e 5437 }
b5014f7a 5438 i.types[op].bitfield.disp8 = 0;
43234a1e
L		 5439 }
5440 }
b5014f7a
JB		 5441
5442 i.memshift = 0;
43234a1e 5443
6c30d220
L		 5444 return 0;
5445}
5446
43f3e2ee 5447/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 5448 operand types. */
5449
5450static int
5451VEX_check_operands (const insn_template *t)
5452{
86fa6981 5453 if (i.vec_encoding == vex_encoding_evex)
43234a1e 5454 {
86fa6981 5455 /* This instruction must be encoded with EVEX prefix. */
e771e7c9 5456 if (!is_evex_encoding (t))
86fa6981
L		 5457 {
5458 i.error = unsupported;
5459 return 1;
5460 }
5461 return 0;
43234a1e
L		 5462 }
5463
a683cc34 5464 if (!t->opcode_modifier.vex)
86fa6981
L		 5465 {
5466 /* This instruction template doesn't have VEX prefix. */
5467 if (i.vec_encoding != vex_encoding_default)
5468 {
5469 i.error = unsupported;
5470 return 1;
5471 }
5472 return 0;
5473 }
a683cc34
SP		 5474
5475 /* Only check VEX_Imm4, which must be the first operand. */
5476 if (t->operand_types[0].bitfield.vec_imm4)
5477 {
5478 if (i.op[0].imms->X_op != O_constant
5479 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 5480 {
a65babc9 5481 i.error = bad_imm4;
891edac4
L		 5482 return 1;
5483 }
a683cc34
SP		 5484
5485 /* Turn off Imm8 so that update_imm won't complain. */
5486 i.types[0] = vec_imm4;
5487 }
5488
5489 return 0;
5490}
5491
d3ce72d0 5492static const insn_template *
83b16ac6 5493match_template (char mnem_suffix)
29b0f896
AM		 5494{
5495 /* Points to template once we've found it. */
d3ce72d0 5496 const insn_template *t;
40fb9820 5497 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 5498 i386_operand_type overlap4;
29b0f896 5499 unsigned int found_reverse_match;
83b16ac6 5500 i386_opcode_modifier suffix_check, mnemsuf_check;
40fb9820 5501 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 5502 int addr_prefix_disp;
a5c311ca 5503 unsigned int j;
3ac21baa 5504 unsigned int found_cpu_match, size_match;
45664ddb 5505 unsigned int check_register;
5614d22c 5506 enum i386_error specific_error = 0;
29b0f896 5507
c0f3af97
L		 5508#if MAX_OPERANDS != 5
5509# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 5510#endif
5511
29b0f896 5512 found_reverse_match = 0;
539e75ad 5513 addr_prefix_disp = -1;
40fb9820
L		 5514
5515 memset (&suffix_check, 0, sizeof (suffix_check));
e2195274
JB		 5516 if (intel_syntax && i.broadcast)
5517 /* nothing */;
5518 else if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 5519 suffix_check.no_bsuf = 1;
5520 else if (i.suffix == WORD_MNEM_SUFFIX)
5521 suffix_check.no_wsuf = 1;
5522 else if (i.suffix == SHORT_MNEM_SUFFIX)
5523 suffix_check.no_ssuf = 1;
5524 else if (i.suffix == LONG_MNEM_SUFFIX)
5525 suffix_check.no_lsuf = 1;
5526 else if (i.suffix == QWORD_MNEM_SUFFIX)
5527 suffix_check.no_qsuf = 1;
5528 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 5529 suffix_check.no_ldsuf = 1;
29b0f896 5530
83b16ac6
JB		 5531 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
5532 if (intel_syntax)
5533 {
5534 switch (mnem_suffix)
5535 {
5536 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
5537 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
5538 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
5539 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
5540 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
5541 }
5542 }
5543
01559ecc
L		 5544 /* Must have right number of operands. */
5545 i.error = number_of_operands_mismatch;
5546
45aa61fe 5547 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 5548 {
539e75ad 5549 addr_prefix_disp = -1;
dbbc8b7e 5550 found_reverse_match = 0;
539e75ad 5551
29b0f896
AM		 5552 if (i.operands != t->operands)
5553 continue;
5554
50aecf8c 5555 /* Check processor support. */
a65babc9 5556 i.error = unsupported;
c0f3af97
L		 5557 found_cpu_match = (cpu_flags_match (t)
5558 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 5559 if (!found_cpu_match)
5560 continue;
5561
e1d4d893 5562 /* Check AT&T mnemonic. */
a65babc9 5563 i.error = unsupported_with_intel_mnemonic;
e1d4d893 5564 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 5565 continue;
5566
e92bae62 5567 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
a65babc9 5568 i.error = unsupported_syntax;
5c07affc 5569 if ((intel_syntax && t->opcode_modifier.attsyntax)
e92bae62
L		 5570 || (!intel_syntax && t->opcode_modifier.intelsyntax)
5571 || (intel64 && t->opcode_modifier.amd64)
5572 || (!intel64 && t->opcode_modifier.intel64))
1efbbeb4
L		 5573 continue;
5574
20592a94 5575 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 5576 i.error = invalid_instruction_suffix;
567e4e96
L		 5577 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
5578 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
5579 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
5580 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
5581 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
5582 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
5583 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896 5584 continue;
83b16ac6
JB		 5585 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5586 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
5587 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
5588 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
5589 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
5590 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
5591 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
5592 continue;
29b0f896 5593
3ac21baa
JB		 5594 size_match = operand_size_match (t);
5595 if (!size_match)
7d5e4556 5596 continue;
539e75ad 5597
5c07affc
L		 5598 for (j = 0; j < MAX_OPERANDS; j++)
5599 operand_types[j] = t->operand_types[j];
5600
45aa61fe
AM		 5601 /* In general, don't allow 64-bit operands in 32-bit mode. */
5602 if (i.suffix == QWORD_MNEM_SUFFIX
5603 && flag_code != CODE_64BIT
5604 && (intel_syntax
40fb9820 5605 ? (!t->opcode_modifier.ignoresize
625cbd7a 5606 && !t->opcode_modifier.broadcast
45aa61fe
AM		 5607 && !intel_float_operand (t->name))
5608 : intel_float_operand (t->name) != 2)
40fb9820 5609 && ((!operand_types[0].bitfield.regmmx
1b54b8d7 5610 && !operand_types[0].bitfield.regsimd)
40fb9820 5611 || (!operand_types[t->operands > 1].bitfield.regmmx
1b54b8d7 5612 && !operand_types[t->operands > 1].bitfield.regsimd))
45aa61fe
AM		 5613 && (t->base_opcode != 0x0fc7
5614 || t->extension_opcode != 1 /* cmpxchg8b */))
5615 continue;
5616
192dc9c6
JB		 5617 /* In general, don't allow 32-bit operands on pre-386. */
5618 else if (i.suffix == LONG_MNEM_SUFFIX
5619 && !cpu_arch_flags.bitfield.cpui386
5620 && (intel_syntax
5621 ? (!t->opcode_modifier.ignoresize
5622 && !intel_float_operand (t->name))
5623 : intel_float_operand (t->name) != 2)
5624 && ((!operand_types[0].bitfield.regmmx
1b54b8d7 5625 && !operand_types[0].bitfield.regsimd)
192dc9c6 5626 || (!operand_types[t->operands > 1].bitfield.regmmx
1b54b8d7 5627 && !operand_types[t->operands > 1].bitfield.regsimd)))
192dc9c6
JB		 5628 continue;
5629
29b0f896 5630 /* Do not verify operands when there are none. */
50aecf8c 5631 else
29b0f896 5632 {
c6fb90c8 5633 if (!t->operands)
2dbab7d5
L		 5634 /* We've found a match; break out of loop. */
5635 break;
29b0f896 5636 }
252b5132 5637
539e75ad
L		 5638 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5639 into Disp32/Disp16/Disp32 operand. */
5640 if (i.prefix[ADDR_PREFIX] != 0)
5641 {
40fb9820 5642 /* There should be only one Disp operand. */
539e75ad
L		 5643 switch (flag_code)
5644 {
5645 case CODE_16BIT:
40fb9820
L		 5646 for (j = 0; j < MAX_OPERANDS; j++)
5647 {
5648 if (operand_types[j].bitfield.disp16)
5649 {
5650 addr_prefix_disp = j;
5651 operand_types[j].bitfield.disp32 = 1;
5652 operand_types[j].bitfield.disp16 = 0;
5653 break;
5654 }
5655 }
539e75ad
L		 5656 break;
5657 case CODE_32BIT:
40fb9820
L		 5658 for (j = 0; j < MAX_OPERANDS; j++)
5659 {
5660 if (operand_types[j].bitfield.disp32)
5661 {
5662 addr_prefix_disp = j;
5663 operand_types[j].bitfield.disp32 = 0;
5664 operand_types[j].bitfield.disp16 = 1;
5665 break;
5666 }
5667 }
539e75ad
L		 5668 break;
5669 case CODE_64BIT:
40fb9820
L		 5670 for (j = 0; j < MAX_OPERANDS; j++)
5671 {
5672 if (operand_types[j].bitfield.disp64)
5673 {
5674 addr_prefix_disp = j;
5675 operand_types[j].bitfield.disp64 = 0;
5676 operand_types[j].bitfield.disp32 = 1;
5677 break;
5678 }
5679 }
539e75ad
L		 5680 break;
5681 }
539e75ad
L		 5682 }
5683
02a86693
L		 5684 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5685 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
5686 continue;
5687
56ffb741 5688 /* We check register size if needed. */
e2195274
JB		 5689 if (t->opcode_modifier.checkregsize)
5690 {
5691 check_register = (1 << t->operands) - 1;
5692 if (i.broadcast)
5693 check_register &= ~(1 << i.broadcast->operand);
5694 }
5695 else
5696 check_register = 0;
5697
c6fb90c8 5698 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 5699 switch (t->operands)
5700 {
5701 case 1:
40fb9820 5702 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 5703 continue;
5704 break;
5705 case 2:
33eaf5de 5706 /* xchg %eax, %eax is a special case. It is an alias for nop
8b38ad71
L		 5707 only in 32bit mode and we can use opcode 0x90. In 64bit
5708 mode, we can't use 0x90 for xchg %eax, %eax since it should
5709 zero-extend %eax to %rax. */
5710 if (flag_code == CODE_64BIT
5711 && t->base_opcode == 0x90
0dfbf9d7
L		 5712 && operand_type_equal (&i.types [0], &acc32)
5713 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 5714 continue;
1212781b
JB		 5715 /* xrelease mov %eax, <disp> is another special case. It must not
5716 match the accumulator-only encoding of mov. */
5717 if (flag_code != CODE_64BIT
5718 && i.hle_prefix
5719 && t->base_opcode == 0xa0
5720 && i.types[0].bitfield.acc
5721 && operand_type_check (i.types[1], anymem))
5722 continue;
f5eb1d70
JB		 5723 /* Fall through. */
5724
5725 case 3:
3ac21baa
JB		 5726 if (!(size_match & MATCH_STRAIGHT))
5727 goto check_reverse;
64c49ab3
JB		 5728 /* Reverse direction of operands if swapping is possible in the first
5729 place (operands need to be symmetric) and
5730 - the load form is requested, and the template is a store form,
5731 - the store form is requested, and the template is a load form,
5732 - the non-default (swapped) form is requested. */
5733 overlap1 = operand_type_and (operand_types[0], operand_types[1]);
f5eb1d70 5734 if (t->opcode_modifier.d && i.reg_operands == i.operands
64c49ab3
JB		 5735 && !operand_type_all_zero (&overlap1))
5736 switch (i.dir_encoding)
5737 {
5738 case dir_encoding_load:
5739 if (operand_type_check (operand_types[i.operands - 1], anymem)
5740 || operand_types[i.operands - 1].bitfield.regmem)
5741 goto check_reverse;
5742 break;
5743
5744 case dir_encoding_store:
5745 if (!operand_type_check (operand_types[i.operands - 1], anymem)
5746 && !operand_types[i.operands - 1].bitfield.regmem)
5747 goto check_reverse;
5748 break;
5749
5750 case dir_encoding_swap:
5751 goto check_reverse;
5752
5753 case dir_encoding_default:
5754 break;
5755 }
86fa6981 5756 /* If we want store form, we skip the current load. */
64c49ab3
JB		 5757 if ((i.dir_encoding == dir_encoding_store
5758 || i.dir_encoding == dir_encoding_swap)
86fa6981
L		 5759 && i.mem_operands == 0
5760 && t->opcode_modifier.load)
fa99fab2 5761 continue;
1a0670f3 5762 /* Fall through. */
f48ff2ae 5763 case 4:
c0f3af97 5764 case 5:
c6fb90c8 5765 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 5766 if (!operand_type_match (overlap0, i.types[0])
5767 || !operand_type_match (overlap1, i.types[1])
e2195274 5768 || ((check_register & 3) == 3
dc821c5f 5769 && !operand_type_register_match (i.types[0],
40fb9820 5770 operand_types[0],
dc821c5f 5771 i.types[1],
40fb9820 5772 operand_types[1])))
29b0f896
AM		 5773 {
5774 /* Check if other direction is valid ... */
38e314eb 5775 if (!t->opcode_modifier.d)
29b0f896
AM		 5776 continue;
5777
b6169b20 5778check_reverse:
3ac21baa
JB		 5779 if (!(size_match & MATCH_REVERSE))
5780 continue;
29b0f896 5781 /* Try reversing direction of operands. */
f5eb1d70
JB		 5782 overlap0 = operand_type_and (i.types[0], operand_types[i.operands - 1]);
5783 overlap1 = operand_type_and (i.types[i.operands - 1], operand_types[0]);
40fb9820 5784 if (!operand_type_match (overlap0, i.types[0])
f5eb1d70 5785 || !operand_type_match (overlap1, i.types[i.operands - 1])
45664ddb 5786 || (check_register
dc821c5f 5787 && !operand_type_register_match (i.types[0],
f5eb1d70
JB		 5788 operand_types[i.operands - 1],
5789 i.types[i.operands - 1],
45664ddb 5790 operand_types[0])))
29b0f896
AM		 5791 {
5792 /* Does not match either direction. */
5793 continue;
5794 }
38e314eb 5795 /* found_reverse_match holds which of D or FloatR
29b0f896 5796 we've found. */
38e314eb
JB		 5797 if (!t->opcode_modifier.d)
5798 found_reverse_match = 0;
5799 else if (operand_types[0].bitfield.tbyte)
8a2ed489 5800 found_reverse_match = Opcode_FloatD;
dbbc8b7e 5801 else if (operand_types[0].bitfield.xmmword
f5eb1d70 5802 || operand_types[i.operands - 1].bitfield.xmmword
dbbc8b7e 5803 || operand_types[0].bitfield.regmmx
f5eb1d70 5804 || operand_types[i.operands - 1].bitfield.regmmx
dbbc8b7e
JB		 5805 || is_any_vex_encoding(t))
5806 found_reverse_match = (t->base_opcode & 0xee) != 0x6e
5807 ? Opcode_SIMD_FloatD : Opcode_SIMD_IntD;
8a2ed489 5808 else
38e314eb 5809 found_reverse_match = Opcode_D;
40fb9820 5810 if (t->opcode_modifier.floatr)
8a2ed489 5811 found_reverse_match |= Opcode_FloatR;
29b0f896 5812 }
f48ff2ae 5813 else
29b0f896 5814 {
f48ff2ae 5815 /* Found a forward 2 operand match here. */
d1cbb4db
L		 5816 switch (t->operands)
5817 {
c0f3af97
L		 5818 case 5:
5819 overlap4 = operand_type_and (i.types[4],
5820 operand_types[4]);
1a0670f3 5821 /* Fall through. */
d1cbb4db 5822 case 4:
c6fb90c8
L		 5823 overlap3 = operand_type_and (i.types[3],
5824 operand_types[3]);
1a0670f3 5825 /* Fall through. */
d1cbb4db 5826 case 3:
c6fb90c8
L		 5827 overlap2 = operand_type_and (i.types[2],
5828 operand_types[2]);
d1cbb4db
L		 5829 break;
5830 }
29b0f896 5831
f48ff2ae
L		 5832 switch (t->operands)
5833 {
c0f3af97
L		 5834 case 5:
5835 if (!operand_type_match (overlap4, i.types[4])
dc821c5f 5836 || !operand_type_register_match (i.types[3],
c0f3af97 5837 operand_types[3],
c0f3af97
L		 5838 i.types[4],
5839 operand_types[4]))
5840 continue;
1a0670f3 5841 /* Fall through. */
f48ff2ae 5842 case 4:
40fb9820 5843 if (!operand_type_match (overlap3, i.types[3])
e2195274
JB		 5844 || ((check_register & 0xa) == 0xa
5845 && !operand_type_register_match (i.types[1],
f7768225
JB		 5846 operand_types[1],
5847 i.types[3],
e2195274
JB		 5848 operand_types[3]))
5849 || ((check_register & 0xc) == 0xc
5850 && !operand_type_register_match (i.types[2],
5851 operand_types[2],
5852 i.types[3],
5853 operand_types[3])))
f48ff2ae 5854 continue;
1a0670f3 5855 /* Fall through. */
f48ff2ae
L		 5856 case 3:
5857 /* Here we make use of the fact that there are no
23e42951 5858 reverse match 3 operand instructions. */
40fb9820 5859 if (!operand_type_match (overlap2, i.types[2])
e2195274
JB		 5860 || ((check_register & 5) == 5
5861 && !operand_type_register_match (i.types[0],
23e42951
JB		 5862 operand_types[0],
5863 i.types[2],
e2195274
JB		 5864 operand_types[2]))
5865 || ((check_register & 6) == 6
5866 && !operand_type_register_match (i.types[1],
5867 operand_types[1],
5868 i.types[2],
5869 operand_types[2])))
f48ff2ae
L		 5870 continue;
5871 break;
5872 }
29b0f896 5873 }
f48ff2ae 5874 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 5875 slip through to break. */
5876 }
3629bb00 5877 if (!found_cpu_match)
dbbc8b7e 5878 continue;
c0f3af97 5879
5614d22c
JB		 5880 /* Check if vector and VEX operands are valid. */
5881 if (check_VecOperands (t) || VEX_check_operands (t))
5882 {
5883 specific_error = i.error;
5884 continue;
5885 }
a683cc34 5886
29b0f896
AM		 5887 /* We've found a match; break out of loop. */
5888 break;
5889 }
5890
5891 if (t == current_templates->end)
5892 {
5893 /* We found no match. */
a65babc9 5894 const char *err_msg;
5614d22c 5895 switch (specific_error ? specific_error : i.error)
a65babc9
L		 5896 {
5897 default:
5898 abort ();
86e026a4 5899 case operand_size_mismatch:
a65babc9
L		 5900 err_msg = _("operand size mismatch");
5901 break;
5902 case operand_type_mismatch:
5903 err_msg = _("operand type mismatch");
5904 break;
5905 case register_type_mismatch:
5906 err_msg = _("register type mismatch");
5907 break;
5908 case number_of_operands_mismatch:
5909 err_msg = _("number of operands mismatch");
5910 break;
5911 case invalid_instruction_suffix:
5912 err_msg = _("invalid instruction suffix");
5913 break;
5914 case bad_imm4:
4a2608e3 5915 err_msg = _("constant doesn't fit in 4 bits");
a65babc9 5916 break;
a65babc9
L		 5917 case unsupported_with_intel_mnemonic:
5918 err_msg = _("unsupported with Intel mnemonic");
5919 break;
5920 case unsupported_syntax:
5921 err_msg = _("unsupported syntax");
5922 break;
5923 case unsupported:
35262a23 5924 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 5925 current_templates->start->name);
5926 return NULL;
6c30d220
L		 5927 case invalid_vsib_address:
5928 err_msg = _("invalid VSIB address");
5929 break;
7bab8ab5
JB		 5930 case invalid_vector_register_set:
5931 err_msg = _("mask, index, and destination registers must be distinct");
5932 break;
6c30d220
L		 5933 case unsupported_vector_index_register:
5934 err_msg = _("unsupported vector index register");
5935 break;
43234a1e
L		 5936 case unsupported_broadcast:
5937 err_msg = _("unsupported broadcast");
5938 break;
43234a1e
L		 5939 case broadcast_needed:
5940 err_msg = _("broadcast is needed for operand of such type");
5941 break;
5942 case unsupported_masking:
5943 err_msg = _("unsupported masking");
5944 break;
5945 case mask_not_on_destination:
5946 err_msg = _("mask not on destination operand");
5947 break;
5948 case no_default_mask:
5949 err_msg = _("default mask isn't allowed");
5950 break;
5951 case unsupported_rc_sae:
5952 err_msg = _("unsupported static rounding/sae");
5953 break;
5954 case rc_sae_operand_not_last_imm:
5955 if (intel_syntax)
5956 err_msg = _("RC/SAE operand must precede immediate operands");
5957 else
5958 err_msg = _("RC/SAE operand must follow immediate operands");
5959 break;
5960 case invalid_register_operand:
5961 err_msg = _("invalid register operand");
5962 break;
a65babc9
L		 5963 }
5964 as_bad (_("%s for `%s'"), err_msg,
891edac4 5965 current_templates->start->name);
fa99fab2 5966 return NULL;
29b0f896 5967 }
252b5132 5968
29b0f896
AM		 5969 if (!quiet_warnings)
5970 {
5971 if (!intel_syntax
40fb9820
L		 5972 && (i.types[0].bitfield.jumpabsolute
5973 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 5974 {
5975 as_warn (_("indirect %s without `*'"), t->name);
5976 }
5977
40fb9820
L		 5978 if (t->opcode_modifier.isprefix
5979 && t->opcode_modifier.ignoresize)
29b0f896
AM		 5980 {
5981 /* Warn them that a data or address size prefix doesn't
5982 affect assembly of the next line of code. */
5983 as_warn (_("stand-alone `%s' prefix"), t->name);
5984 }
5985 }
5986
5987 /* Copy the template we found. */
5988 i.tm = *t;
539e75ad
L		 5989
5990 if (addr_prefix_disp != -1)
5991 i.tm.operand_types[addr_prefix_disp]
5992 = operand_types[addr_prefix_disp];
5993
29b0f896
AM		 5994 if (found_reverse_match)
5995 {
5996 /* If we found a reverse match we must alter the opcode
5997 direction bit. found_reverse_match holds bits to change
5998 (different for int & float insns). */
5999
6000 i.tm.base_opcode ^= found_reverse_match;
6001
f5eb1d70
JB		 6002 i.tm.operand_types[0] = operand_types[i.operands - 1];
6003 i.tm.operand_types[i.operands - 1] = operand_types[0];
29b0f896
AM		 6004 }
6005
fa99fab2 6006 return t;
29b0f896
AM		 6007}
6008
6009static int
e3bb37b5 6010check_string (void)
29b0f896 6011{
40fb9820
L		 6012 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
6013 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 6014 {
6015 if (i.seg[0] != NULL && i.seg[0] != &es)
6016 {
a87af027 6017 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 6018 i.tm.name,
a87af027
JB		 6019 mem_op + 1,
6020 register_prefix);
29b0f896
AM		 6021 return 0;
6022 }
6023 /* There's only ever one segment override allowed per instruction.
6024 This instruction possibly has a legal segment override on the
6025 second operand, so copy the segment to where non-string
6026 instructions store it, allowing common code. */
6027 i.seg[0] = i.seg[1];
6028 }
40fb9820 6029 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 6030 {
6031 if (i.seg[1] != NULL && i.seg[1] != &es)
6032 {
a87af027 6033 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 6034 i.tm.name,
a87af027
JB		 6035 mem_op + 2,
6036 register_prefix);
29b0f896
AM		 6037 return 0;
6038 }
6039 }
6040 return 1;
6041}
6042
6043static int
543613e9 6044process_suffix (void)
29b0f896
AM		 6045{
6046 /* If matched instruction specifies an explicit instruction mnemonic
6047 suffix, use it. */
673fe0f0 6048 if (i.tm.opcode_modifier.size == SIZE16)
40fb9820 6049 i.suffix = WORD_MNEM_SUFFIX;
673fe0f0 6050 else if (i.tm.opcode_modifier.size == SIZE32)
40fb9820 6051 i.suffix = LONG_MNEM_SUFFIX;
673fe0f0 6052 else if (i.tm.opcode_modifier.size == SIZE64)
40fb9820 6053 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 6054 else if (i.reg_operands)
6055 {
6056 /* If there's no instruction mnemonic suffix we try to invent one
6057 based on register operands. */
6058 if (!i.suffix)
6059 {
6060 /* We take i.suffix from the last register operand specified,
6061 Destination register type is more significant than source
381d071f
L		 6062 register type. crc32 in SSE4.2 prefers source register
6063 type. */
556059dd 6064 if (i.tm.base_opcode == 0xf20f38f0 && i.types[0].bitfield.reg)
381d071f 6065 {
556059dd
JB		 6066 if (i.types[0].bitfield.byte)
6067 i.suffix = BYTE_MNEM_SUFFIX;
6068 else if (i.types[0].bitfield.word)
40fb9820 6069 i.suffix = WORD_MNEM_SUFFIX;
556059dd 6070 else if (i.types[0].bitfield.dword)
40fb9820 6071 i.suffix = LONG_MNEM_SUFFIX;
556059dd 6072 else if (i.types[0].bitfield.qword)
40fb9820 6073 i.suffix = QWORD_MNEM_SUFFIX;
381d071f
L		 6074 }
6075
6076 if (!i.suffix)
6077 {
6078 int op;
6079
556059dd 6080 if (i.tm.base_opcode == 0xf20f38f0)
20592a94
L		 6081 {
6082 /* We have to know the operand size for crc32. */
6083 as_bad (_("ambiguous memory operand size for `%s`"),
6084 i.tm.name);
6085 return 0;
6086 }
6087
381d071f 6088 for (op = i.operands; --op >= 0;)
b76bc5d5
JB		 6089 if (!i.tm.operand_types[op].bitfield.inoutportreg
6090 && !i.tm.operand_types[op].bitfield.shiftcount)
381d071f 6091 {
8819ada6
JB		 6092 if (!i.types[op].bitfield.reg)
6093 continue;
6094 if (i.types[op].bitfield.byte)
6095 i.suffix = BYTE_MNEM_SUFFIX;
6096 else if (i.types[op].bitfield.word)
6097 i.suffix = WORD_MNEM_SUFFIX;
6098 else if (i.types[op].bitfield.dword)
6099 i.suffix = LONG_MNEM_SUFFIX;
6100 else if (i.types[op].bitfield.qword)
6101 i.suffix = QWORD_MNEM_SUFFIX;
6102 else
6103 continue;
6104 break;
381d071f
L		 6105 }
6106 }
29b0f896
AM		 6107 }
6108 else if (i.suffix == BYTE_MNEM_SUFFIX)
6109 {
2eb952a4
L		 6110 if (intel_syntax
6111 && i.tm.opcode_modifier.ignoresize
6112 && i.tm.opcode_modifier.no_bsuf)
6113 i.suffix = 0;
6114 else if (!check_byte_reg ())
29b0f896
AM		 6115 return 0;
6116 }
6117 else if (i.suffix == LONG_MNEM_SUFFIX)
6118 {
2eb952a4
L		 6119 if (intel_syntax
6120 && i.tm.opcode_modifier.ignoresize
9f123b91
JB		 6121 && i.tm.opcode_modifier.no_lsuf
6122 && !i.tm.opcode_modifier.todword
6123 && !i.tm.opcode_modifier.toqword)
2eb952a4
L		 6124 i.suffix = 0;
6125 else if (!check_long_reg ())
29b0f896
AM		 6126 return 0;
6127 }
6128 else if (i.suffix == QWORD_MNEM_SUFFIX)
6129 {
955e1e6a
L		 6130 if (intel_syntax
6131 && i.tm.opcode_modifier.ignoresize
9f123b91
JB		 6132 && i.tm.opcode_modifier.no_qsuf
6133 && !i.tm.opcode_modifier.todword
6134 && !i.tm.opcode_modifier.toqword)
955e1e6a
L		 6135 i.suffix = 0;
6136 else if (!check_qword_reg ())
29b0f896
AM		 6137 return 0;
6138 }
6139 else if (i.suffix == WORD_MNEM_SUFFIX)
6140 {
2eb952a4
L		 6141 if (intel_syntax
6142 && i.tm.opcode_modifier.ignoresize
6143 && i.tm.opcode_modifier.no_wsuf)
6144 i.suffix = 0;
6145 else if (!check_word_reg ())
29b0f896
AM		 6146 return 0;
6147 }
40fb9820 6148 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 6149 /* Do nothing if the instruction is going to ignore the prefix. */
6150 ;
6151 else
6152 abort ();
6153 }
40fb9820 6154 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 6155 && !i.suffix
6156 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 6157 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 6158 {
6159 i.suffix = stackop_size;
6160 }
9306ca4a
JB		 6161 else if (intel_syntax
6162 && !i.suffix
40fb9820
L		 6163 && (i.tm.operand_types[0].bitfield.jumpabsolute
6164 || i.tm.opcode_modifier.jumpbyte
6165 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 6166 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
6167 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 6168 {
6169 switch (flag_code)
6170 {
6171 case CODE_64BIT:
40fb9820 6172 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 6173 {
6174 i.suffix = QWORD_MNEM_SUFFIX;
6175 break;
6176 }
1a0670f3 6177 /* Fall through. */
9306ca4a 6178 case CODE_32BIT:
40fb9820 6179 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 6180 i.suffix = LONG_MNEM_SUFFIX;
6181 break;
6182 case CODE_16BIT:
40fb9820 6183 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 6184 i.suffix = WORD_MNEM_SUFFIX;
6185 break;
6186 }
6187 }
252b5132 6188
9306ca4a 6189 if (!i.suffix)
29b0f896 6190 {
9306ca4a
JB		 6191 if (!intel_syntax)
6192 {
40fb9820 6193 if (i.tm.opcode_modifier.w)
9306ca4a 6194 {
4eed87de
AM		 6195 as_bad (_("no instruction mnemonic suffix given and "
6196 "no register operands; can't size instruction"));
9306ca4a
JB		 6197 return 0;
6198 }
6199 }
6200 else
6201 {
40fb9820 6202 unsigned int suffixes;
7ab9ffdd 6203
40fb9820
L		 6204 suffixes = !i.tm.opcode_modifier.no_bsuf;
6205 if (!i.tm.opcode_modifier.no_wsuf)
6206 suffixes |= 1 << 1;
6207 if (!i.tm.opcode_modifier.no_lsuf)
6208 suffixes |= 1 << 2;
fc4adea1 6209 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 6210 suffixes |= 1 << 3;
6211 if (!i.tm.opcode_modifier.no_ssuf)
6212 suffixes |= 1 << 4;
c2b9da16 6213 if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
40fb9820
L		 6214 suffixes |= 1 << 5;
6215
6216 /* There are more than suffix matches. */
6217 if (i.tm.opcode_modifier.w
9306ca4a 6218 || ((suffixes & (suffixes - 1))
40fb9820
L		 6219 && !i.tm.opcode_modifier.defaultsize
6220 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 6221 {
6222 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
6223 return 0;
6224 }
6225 }
29b0f896 6226 }
252b5132 6227
d2224064
JB		 6228 /* Change the opcode based on the operand size given by i.suffix. */
6229 switch (i.suffix)
29b0f896 6230 {
d2224064
JB		 6231 /* Size floating point instruction. */
6232 case LONG_MNEM_SUFFIX:
6233 if (i.tm.opcode_modifier.floatmf)
6234 {
6235 i.tm.base_opcode ^= 4;
6236 break;
6237 }
6238 /* fall through */
6239 case WORD_MNEM_SUFFIX:
6240 case QWORD_MNEM_SUFFIX:
29b0f896 6241 /* It's not a byte, select word/dword operation. */
40fb9820 6242 if (i.tm.opcode_modifier.w)
29b0f896 6243 {
40fb9820 6244 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 6245 i.tm.base_opcode |= 8;
6246 else
6247 i.tm.base_opcode |= 1;
6248 }
d2224064
JB		 6249 /* fall through */
6250 case SHORT_MNEM_SUFFIX:
29b0f896
AM		 6251 /* Now select between word & dword operations via the operand
6252 size prefix, except for instructions that will ignore this
6253 prefix anyway. */
75c0a438
L		 6254 if (i.reg_operands > 0
6255 && i.types[0].bitfield.reg
6256 && i.tm.opcode_modifier.addrprefixopreg
6257 && (i.tm.opcode_modifier.immext
6258 || i.operands == 1))
cb712a9e 6259 {
ca61edf2
L		 6260 /* The address size override prefix changes the size of the
6261 first operand. */
40fb9820 6262 if ((flag_code == CODE_32BIT
75c0a438 6263 && i.op[0].regs->reg_type.bitfield.word)
40fb9820 6264 || (flag_code != CODE_32BIT
75c0a438 6265 && i.op[0].regs->reg_type.bitfield.dword))
cb712a9e
L		 6266 if (!add_prefix (ADDR_PREFIX_OPCODE))
6267 return 0;
6268 }
6269 else if (i.suffix != QWORD_MNEM_SUFFIX
40fb9820
L		 6270 && !i.tm.opcode_modifier.ignoresize
6271 && !i.tm.opcode_modifier.floatmf
7a8655d2
JB		 6272 && !i.tm.opcode_modifier.vex
6273 && !i.tm.opcode_modifier.vexopcode
6274 && !is_evex_encoding (&i.tm)
cb712a9e
L		 6275 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
6276 || (flag_code == CODE_64BIT
40fb9820 6277 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 6278 {
6279 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 6280
40fb9820 6281 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 6282 prefix = ADDR_PREFIX_OPCODE;
252b5132 6283
29b0f896
AM		 6284 if (!add_prefix (prefix))
6285 return 0;
24eab124 6286 }
252b5132 6287
29b0f896
AM		 6288 /* Set mode64 for an operand. */
6289 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 6290 && flag_code == CODE_64BIT
d2224064 6291 && !i.tm.opcode_modifier.norex64
46e883c5 6292 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d2224064
JB		 6293 need rex64. */
6294 && ! (i.operands == 2
6295 && i.tm.base_opcode == 0x90
6296 && i.tm.extension_opcode == None
6297 && operand_type_equal (&i.types [0], &acc64)
6298 && operand_type_equal (&i.types [1], &acc64)))
6299 i.rex |= REX_W;
3e73aa7c 6300
d2224064 6301 break;
29b0f896 6302 }
7ecd2f8b 6303
c0a30a9f
L		 6304 if (i.reg_operands != 0
6305 && i.operands > 1
6306 && i.tm.opcode_modifier.addrprefixopreg
6307 && !i.tm.opcode_modifier.immext)
6308 {
6309 /* Check invalid register operand when the address size override
6310 prefix changes the size of register operands. */
6311 unsigned int op;
6312 enum { need_word, need_dword, need_qword } need;
6313
6314 if (flag_code == CODE_32BIT)
6315 need = i.prefix[ADDR_PREFIX] ? need_word : need_dword;
6316 else
6317 {
6318 if (i.prefix[ADDR_PREFIX])
6319 need = need_dword;
6320 else
6321 need = flag_code == CODE_64BIT ? need_qword : need_word;
6322 }
6323
6324 for (op = 0; op < i.operands; op++)
6325 if (i.types[op].bitfield.reg
6326 && ((need == need_word
6327 && !i.op[op].regs->reg_type.bitfield.word)
6328 || (need == need_dword
6329 && !i.op[op].regs->reg_type.bitfield.dword)
6330 || (need == need_qword
6331 && !i.op[op].regs->reg_type.bitfield.qword)))
6332 {
6333 as_bad (_("invalid register operand size for `%s'"),
6334 i.tm.name);
6335 return 0;
6336 }
6337 }
6338
29b0f896
AM		 6339 return 1;
6340}
3e73aa7c 6341
29b0f896 6342static int
543613e9 6343check_byte_reg (void)
29b0f896
AM		 6344{
6345 int op;
543613e9 6346
29b0f896
AM		 6347 for (op = i.operands; --op >= 0;)
6348 {
dc821c5f
JB		 6349 /* Skip non-register operands. */
6350 if (!i.types[op].bitfield.reg)
6351 continue;
6352
29b0f896
AM		 6353 /* If this is an eight bit register, it's OK. If it's the 16 or
6354 32 bit version of an eight bit register, we will just use the
6355 low portion, and that's OK too. */
dc821c5f 6356 if (i.types[op].bitfield.byte)
29b0f896
AM		 6357 continue;
6358
5a819eb9
JB		 6359 /* I/O port address operands are OK too. */
6360 if (i.tm.operand_types[op].bitfield.inoutportreg)
6361 continue;
6362
9344ff29
L		 6363 /* crc32 doesn't generate this warning. */
6364 if (i.tm.base_opcode == 0xf20f38f0)
6365 continue;
6366
dc821c5f
JB		 6367 if ((i.types[op].bitfield.word
6368 || i.types[op].bitfield.dword
6369 || i.types[op].bitfield.qword)
5a819eb9
JB		 6370 && i.op[op].regs->reg_num < 4
6371 /* Prohibit these changes in 64bit mode, since the lowering
6372 would be more complicated. */
6373 && flag_code != CODE_64BIT)
29b0f896 6374 {
29b0f896 6375#if REGISTER_WARNINGS
5a819eb9 6376 if (!quiet_warnings)
a540244d
L		 6377 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6378 register_prefix,
dc821c5f 6379 (i.op[op].regs + (i.types[op].bitfield.word
29b0f896
AM		 6380 ? REGNAM_AL - REGNAM_AX
6381 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 6382 register_prefix,
29b0f896
AM		 6383 i.op[op].regs->reg_name,
6384 i.suffix);
6385#endif
6386 continue;
6387 }
6388 /* Any other register is bad. */
dc821c5f 6389 if (i.types[op].bitfield.reg
40fb9820 6390 || i.types[op].bitfield.regmmx
1b54b8d7 6391 || i.types[op].bitfield.regsimd
40fb9820
L		 6392 || i.types[op].bitfield.sreg2
6393 || i.types[op].bitfield.sreg3
6394 || i.types[op].bitfield.control
6395 || i.types[op].bitfield.debug
ca0d63fe 6396 || i.types[op].bitfield.test)
29b0f896 6397 {
a540244d
L		 6398 as_bad (_("`%s%s' not allowed with `%s%c'"),
6399 register_prefix,
29b0f896
AM		 6400 i.op[op].regs->reg_name,
6401 i.tm.name,
6402 i.suffix);
6403 return 0;
6404 }
6405 }
6406 return 1;
6407}
6408
6409static int
e3bb37b5 6410check_long_reg (void)
29b0f896
AM		 6411{
6412 int op;
6413
6414 for (op = i.operands; --op >= 0;)
dc821c5f
JB		 6415 /* Skip non-register operands. */
6416 if (!i.types[op].bitfield.reg)
6417 continue;
29b0f896
AM		 6418 /* Reject eight bit registers, except where the template requires
6419 them. (eg. movzb) */
dc821c5f
JB		 6420 else if (i.types[op].bitfield.byte
6421 && (i.tm.operand_types[op].bitfield.reg
6422 || i.tm.operand_types[op].bitfield.acc)
6423 && (i.tm.operand_types[op].bitfield.word
6424 || i.tm.operand_types[op].bitfield.dword))
29b0f896 6425 {
a540244d
L		 6426 as_bad (_("`%s%s' not allowed with `%s%c'"),
6427 register_prefix,
29b0f896
AM		 6428 i.op[op].regs->reg_name,
6429 i.tm.name,
6430 i.suffix);
6431 return 0;
6432 }
e4630f71 6433 /* Warn if the e prefix on a general reg is missing. */
29b0f896 6434 else if ((!quiet_warnings || flag_code == CODE_64BIT)
dc821c5f
JB		 6435 && i.types[op].bitfield.word
6436 && (i.tm.operand_types[op].bitfield.reg
6437 || i.tm.operand_types[op].bitfield.acc)
6438 && i.tm.operand_types[op].bitfield.dword)
29b0f896
AM		 6439 {
6440 /* Prohibit these changes in the 64bit mode, since the
6441 lowering is more complicated. */
6442 if (flag_code == CODE_64BIT)
252b5132 6443 {
2b5d6a91 6444 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 6445 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 6446 i.suffix);
6447 return 0;
252b5132 6448 }
29b0f896 6449#if REGISTER_WARNINGS
cecf1424
JB		 6450 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6451 register_prefix,
6452 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
6453 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896 6454#endif
252b5132 6455 }
e4630f71 6456 /* Warn if the r prefix on a general reg is present. */
dc821c5f
JB		 6457 else if (i.types[op].bitfield.qword
6458 && (i.tm.operand_types[op].bitfield.reg
6459 || i.tm.operand_types[op].bitfield.acc)
6460 && i.tm.operand_types[op].bitfield.dword)
252b5132 6461 {
34828aad 6462 if (intel_syntax
ca61edf2 6463 && i.tm.opcode_modifier.toqword
1b54b8d7 6464 && !i.types[0].bitfield.regsimd)
34828aad 6465 {
ca61edf2 6466 /* Convert to QWORD. We want REX byte. */
34828aad
L		 6467 i.suffix = QWORD_MNEM_SUFFIX;
6468 }
6469 else
6470 {
2b5d6a91 6471 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 6472 register_prefix, i.op[op].regs->reg_name,
6473 i.suffix);
6474 return 0;
6475 }
29b0f896
AM		 6476 }
6477 return 1;
6478}
252b5132 6479
29b0f896 6480static int
e3bb37b5 6481check_qword_reg (void)
29b0f896
AM		 6482{
6483 int op;
252b5132 6484
29b0f896 6485 for (op = i.operands; --op >= 0; )
dc821c5f
JB		 6486 /* Skip non-register operands. */
6487 if (!i.types[op].bitfield.reg)
6488 continue;
29b0f896
AM		 6489 /* Reject eight bit registers, except where the template requires
6490 them. (eg. movzb) */
dc821c5f
JB		 6491 else if (i.types[op].bitfield.byte
6492 && (i.tm.operand_types[op].bitfield.reg
6493 || i.tm.operand_types[op].bitfield.acc)
6494 && (i.tm.operand_types[op].bitfield.word
6495 || i.tm.operand_types[op].bitfield.dword))
29b0f896 6496 {
a540244d
L		 6497 as_bad (_("`%s%s' not allowed with `%s%c'"),
6498 register_prefix,
29b0f896
AM		 6499 i.op[op].regs->reg_name,
6500 i.tm.name,
6501 i.suffix);
6502 return 0;
6503 }
e4630f71 6504 /* Warn if the r prefix on a general reg is missing. */
dc821c5f
JB		 6505 else if ((i.types[op].bitfield.word
6506 || i.types[op].bitfield.dword)
6507 && (i.tm.operand_types[op].bitfield.reg
6508 || i.tm.operand_types[op].bitfield.acc)
6509 && i.tm.operand_types[op].bitfield.qword)
29b0f896
AM		 6510 {
6511 /* Prohibit these changes in the 64bit mode, since the
6512 lowering is more complicated. */
34828aad 6513 if (intel_syntax
ca61edf2 6514 && i.tm.opcode_modifier.todword
1b54b8d7 6515 && !i.types[0].bitfield.regsimd)
34828aad 6516 {
ca61edf2 6517 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 6518 i.suffix = LONG_MNEM_SUFFIX;
6519 }
6520 else
6521 {
2b5d6a91 6522 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 6523 register_prefix, i.op[op].regs->reg_name,
6524 i.suffix);
6525 return 0;
6526 }
252b5132 6527 }
29b0f896
AM		 6528 return 1;
6529}
252b5132 6530
29b0f896 6531static int
e3bb37b5 6532check_word_reg (void)
29b0f896
AM		 6533{
6534 int op;
6535 for (op = i.operands; --op >= 0;)
dc821c5f
JB		 6536 /* Skip non-register operands. */
6537 if (!i.types[op].bitfield.reg)
6538 continue;
29b0f896
AM		 6539 /* Reject eight bit registers, except where the template requires
6540 them. (eg. movzb) */
dc821c5f
JB		 6541 else if (i.types[op].bitfield.byte
6542 && (i.tm.operand_types[op].bitfield.reg
6543 || i.tm.operand_types[op].bitfield.acc)
6544 && (i.tm.operand_types[op].bitfield.word
6545 || i.tm.operand_types[op].bitfield.dword))
29b0f896 6546 {
a540244d
L		 6547 as_bad (_("`%s%s' not allowed with `%s%c'"),
6548 register_prefix,
29b0f896
AM		 6549 i.op[op].regs->reg_name,
6550 i.tm.name,
6551 i.suffix);
6552 return 0;
6553 }
e4630f71 6554 /* Warn if the e or r prefix on a general reg is present. */
29b0f896 6555 else if ((!quiet_warnings || flag_code == CODE_64BIT)
dc821c5f
JB		 6556 && (i.types[op].bitfield.dword
6557 || i.types[op].bitfield.qword)
6558 && (i.tm.operand_types[op].bitfield.reg
6559 || i.tm.operand_types[op].bitfield.acc)
6560 && i.tm.operand_types[op].bitfield.word)
252b5132 6561 {
29b0f896
AM		 6562 /* Prohibit these changes in the 64bit mode, since the
6563 lowering is more complicated. */
6564 if (flag_code == CODE_64BIT)
252b5132 6565 {
2b5d6a91 6566 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 6567 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 6568 i.suffix);
6569 return 0;
252b5132 6570 }
29b0f896 6571#if REGISTER_WARNINGS
cecf1424
JB		 6572 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6573 register_prefix,
6574 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
6575 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896
AM		 6576#endif
6577 }
6578 return 1;
6579}
252b5132 6580
29b0f896 6581static int
40fb9820 6582update_imm (unsigned int j)
29b0f896 6583{
bc0844ae 6584 i386_operand_type overlap = i.types[j];
40fb9820
L		 6585 if ((overlap.bitfield.imm8
6586 || overlap.bitfield.imm8s
6587 || overlap.bitfield.imm16
6588 || overlap.bitfield.imm32
6589 || overlap.bitfield.imm32s
6590 || overlap.bitfield.imm64)
0dfbf9d7
L		 6591 && !operand_type_equal (&overlap, &imm8)
6592 && !operand_type_equal (&overlap, &imm8s)
6593 && !operand_type_equal (&overlap, &imm16)
6594 && !operand_type_equal (&overlap, &imm32)
6595 && !operand_type_equal (&overlap, &imm32s)
6596 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 6597 {
6598 if (i.suffix)
6599 {
40fb9820
L		 6600 i386_operand_type temp;
6601
0dfbf9d7 6602 operand_type_set (&temp, 0);
7ab9ffdd 6603 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 6604 {
6605 temp.bitfield.imm8 = overlap.bitfield.imm8;
6606 temp.bitfield.imm8s = overlap.bitfield.imm8s;
6607 }
6608 else if (i.suffix == WORD_MNEM_SUFFIX)
6609 temp.bitfield.imm16 = overlap.bitfield.imm16;
6610 else if (i.suffix == QWORD_MNEM_SUFFIX)
6611 {
6612 temp.bitfield.imm64 = overlap.bitfield.imm64;
6613 temp.bitfield.imm32s = overlap.bitfield.imm32s;
6614 }
6615 else
6616 temp.bitfield.imm32 = overlap.bitfield.imm32;
6617 overlap = temp;
29b0f896 6618 }
0dfbf9d7
L		 6619 else if (operand_type_equal (&overlap, &imm16_32_32s)
6620 || operand_type_equal (&overlap, &imm16_32)
6621 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 6622 {
40fb9820 6623 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 6624 overlap = imm16;
40fb9820 6625 else
65da13b5 6626 overlap = imm32s;
29b0f896 6627 }
0dfbf9d7
L		 6628 if (!operand_type_equal (&overlap, &imm8)
6629 && !operand_type_equal (&overlap, &imm8s)
6630 && !operand_type_equal (&overlap, &imm16)
6631 && !operand_type_equal (&overlap, &imm32)
6632 && !operand_type_equal (&overlap, &imm32s)
6633 && !operand_type_equal (&overlap, &imm64))
29b0f896 6634 {
4eed87de
AM		 6635 as_bad (_("no instruction mnemonic suffix given; "
6636 "can't determine immediate size"));
29b0f896
AM		 6637 return 0;
6638 }
6639 }
40fb9820 6640 i.types[j] = overlap;
29b0f896 6641
40fb9820
L		 6642 return 1;
6643}
6644
6645static int
6646finalize_imm (void)
6647{
bc0844ae 6648 unsigned int j, n;
29b0f896 6649
bc0844ae
L		 6650 /* Update the first 2 immediate operands. */
6651 n = i.operands > 2 ? 2 : i.operands;
6652 if (n)
6653 {
6654 for (j = 0; j < n; j++)
6655 if (update_imm (j) == 0)
6656 return 0;
40fb9820 6657
bc0844ae
L		 6658 /* The 3rd operand can't be immediate operand. */
6659 gas_assert (operand_type_check (i.types[2], imm) == 0);
6660 }
29b0f896
AM		 6661
6662 return 1;
6663}
6664
6665static int
e3bb37b5 6666process_operands (void)
29b0f896
AM		 6667{
6668 /* Default segment register this instruction will use for memory
6669 accesses. 0 means unknown. This is only for optimizing out
6670 unnecessary segment overrides. */
6671 const seg_entry *default_seg = 0;
6672
2426c15f 6673 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 6674 {
91d6fa6a
NC		 6675 unsigned int dupl = i.operands;
6676 unsigned int dest = dupl - 1;
9fcfb3d7
L		 6677 unsigned int j;
6678
c0f3af97 6679 /* The destination must be an xmm register. */
9c2799c2 6680 gas_assert (i.reg_operands
91d6fa6a 6681 && MAX_OPERANDS > dupl
7ab9ffdd 6682 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97 6683
1b54b8d7
JB		 6684 if (i.tm.operand_types[0].bitfield.acc
6685 && i.tm.operand_types[0].bitfield.xmmword)
e2ec9d29 6686 {
8cd7925b 6687 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 6688 {
6689 /* Keep xmm0 for instructions with VEX prefix and 3
6690 sources. */
1b54b8d7
JB		 6691 i.tm.operand_types[0].bitfield.acc = 0;
6692 i.tm.operand_types[0].bitfield.regsimd = 1;
c0f3af97
L		 6693 goto duplicate;
6694 }
e2ec9d29 6695 else
c0f3af97
L		 6696 {
6697 /* We remove the first xmm0 and keep the number of
6698 operands unchanged, which in fact duplicates the
6699 destination. */
6700 for (j = 1; j < i.operands; j++)
6701 {
6702 i.op[j - 1] = i.op[j];
6703 i.types[j - 1] = i.types[j];
6704 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
6705 }
6706 }
6707 }
6708 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 6709 {
91d6fa6a 6710 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 6711 && (i.tm.opcode_modifier.vexsources
6712 == VEX3SOURCES));
c0f3af97
L		 6713
6714 /* Add the implicit xmm0 for instructions with VEX prefix
6715 and 3 sources. */
6716 for (j = i.operands; j > 0; j--)
6717 {
6718 i.op[j] = i.op[j - 1];
6719 i.types[j] = i.types[j - 1];
6720 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
6721 }
6722 i.op[0].regs
6723 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 6724 i.types[0] = regxmm;
c0f3af97
L		 6725 i.tm.operand_types[0] = regxmm;
6726
6727 i.operands += 2;
6728 i.reg_operands += 2;
6729 i.tm.operands += 2;
6730
91d6fa6a 6731 dupl++;
c0f3af97 6732 dest++;
91d6fa6a
NC		 6733 i.op[dupl] = i.op[dest];
6734 i.types[dupl] = i.types[dest];
6735 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 6736 }
c0f3af97
L		 6737 else
6738 {
6739duplicate:
6740 i.operands++;
6741 i.reg_operands++;
6742 i.tm.operands++;
6743
91d6fa6a
NC		 6744 i.op[dupl] = i.op[dest];
6745 i.types[dupl] = i.types[dest];
6746 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 6747 }
6748
6749 if (i.tm.opcode_modifier.immext)
6750 process_immext ();
6751 }
1b54b8d7
JB		 6752 else if (i.tm.operand_types[0].bitfield.acc
6753 && i.tm.operand_types[0].bitfield.xmmword)
c0f3af97
L		 6754 {
6755 unsigned int j;
6756
9fcfb3d7
L		 6757 for (j = 1; j < i.operands; j++)
6758 {
6759 i.op[j - 1] = i.op[j];
6760 i.types[j - 1] = i.types[j];
6761
6762 /* We need to adjust fields in i.tm since they are used by
6763 build_modrm_byte. */
6764 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
6765 }
6766
e2ec9d29
L		 6767 i.operands--;
6768 i.reg_operands--;
e2ec9d29
L		 6769 i.tm.operands--;
6770 }
920d2ddc
IT		 6771 else if (i.tm.opcode_modifier.implicitquadgroup)
6772 {
a477a8c4
JB		 6773 unsigned int regnum, first_reg_in_group, last_reg_in_group;
6774
920d2ddc 6775 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
10c17abd 6776 gas_assert (i.operands >= 2 && i.types[1].bitfield.regsimd);
a477a8c4
JB		 6777 regnum = register_number (i.op[1].regs);
6778 first_reg_in_group = regnum & ~3;
6779 last_reg_in_group = first_reg_in_group + 3;
6780 if (regnum != first_reg_in_group)
6781 as_warn (_("source register `%s%s' implicitly denotes"
6782 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6783 register_prefix, i.op[1].regs->reg_name,
6784 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
6785 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
6786 i.tm.name);
6787 }
e2ec9d29
L		 6788 else if (i.tm.opcode_modifier.regkludge)
6789 {
6790 /* The imul $imm, %reg instruction is converted into
6791 imul $imm, %reg, %reg, and the clr %reg instruction
6792 is converted into xor %reg, %reg. */
6793
6794 unsigned int first_reg_op;
6795
6796 if (operand_type_check (i.types[0], reg))
6797 first_reg_op = 0;
6798 else
6799 first_reg_op = 1;
6800 /* Pretend we saw the extra register operand. */
9c2799c2 6801 gas_assert (i.reg_operands == 1
7ab9ffdd 6802 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 6803 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
6804 i.types[first_reg_op + 1] = i.types[first_reg_op];
6805 i.operands++;
6806 i.reg_operands++;
29b0f896
AM		 6807 }
6808
40fb9820 6809 if (i.tm.opcode_modifier.shortform)
29b0f896 6810 {
40fb9820
L		 6811 if (i.types[0].bitfield.sreg2
6812 || i.types[0].bitfield.sreg3)
29b0f896 6813 {
4eed87de
AM		 6814 if (i.tm.base_opcode == POP_SEG_SHORT
6815 && i.op[0].regs->reg_num == 1)
29b0f896 6816 {
a87af027 6817 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 6818 return 0;
29b0f896 6819 }
4eed87de
AM		 6820 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
6821 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 6822 i.rex |= REX_B;
4eed87de
AM		 6823 }
6824 else
6825 {
7ab9ffdd 6826 /* The register or float register operand is in operand
85f10a01 6827 0 or 1. */
40fb9820 6828 unsigned int op;
7ab9ffdd 6829
ca0d63fe 6830 if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte)
7ab9ffdd
L		 6831 || operand_type_check (i.types[0], reg))
6832 op = 0;
6833 else
6834 op = 1;
4eed87de
AM		 6835 /* Register goes in low 3 bits of opcode. */
6836 i.tm.base_opcode |= i.op[op].regs->reg_num;
6837 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 6838 i.rex |= REX_B;
40fb9820 6839 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 6840 {
4eed87de
AM		 6841 /* Warn about some common errors, but press on regardless.
6842 The first case can be generated by gcc (<= 2.8.1). */
6843 if (i.operands == 2)
6844 {
6845 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 6846 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 6847 register_prefix, i.op[!intel_syntax].regs->reg_name,
6848 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 6849 }
6850 else
6851 {
6852 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 6853 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6854 register_prefix, i.op[0].regs->reg_name);
4eed87de 6855 }
29b0f896
AM		 6856 }
6857 }
6858 }
40fb9820 6859 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 6860 {
6861 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 6862 must be put into the modrm byte). Now, we make the modrm and
6863 index base bytes based on all the info we've collected. */
29b0f896
AM		 6864
6865 default_seg = build_modrm_byte ();
6866 }
8a2ed489 6867 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 6868 {
6869 default_seg = &ds;
6870 }
40fb9820 6871 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 6872 {
6873 /* For the string instructions that allow a segment override
6874 on one of their operands, the default segment is ds. */
6875 default_seg = &ds;
6876 }
6877
75178d9d
L		 6878 if (i.tm.base_opcode == 0x8d /* lea */
6879 && i.seg[0]
6880 && !quiet_warnings)
30123838 6881 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 6882
6883 /* If a segment was explicitly specified, and the specified segment
6884 is not the default, use an opcode prefix to select it. If we
6885 never figured out what the default segment is, then default_seg
6886 will be zero at this point, and the specified segment prefix will
6887 always be used. */
29b0f896
AM		 6888 if ((i.seg[0]) && (i.seg[0] != default_seg))
6889 {
6890 if (!add_prefix (i.seg[0]->seg_prefix))
6891 return 0;
6892 }
6893 return 1;
6894}
6895
6896static const seg_entry *
e3bb37b5 6897build_modrm_byte (void)
29b0f896
AM		 6898{
6899 const seg_entry *default_seg = 0;
c0f3af97 6900 unsigned int source, dest;
8cd7925b 6901 int vex_3_sources;
c0f3af97 6902
8cd7925b 6903 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 6904 if (vex_3_sources)
6905 {
91d6fa6a 6906 unsigned int nds, reg_slot;
4c2c6516 6907 expressionS *exp;
c0f3af97 6908
6b8d3588 6909 dest = i.operands - 1;
c0f3af97 6910 nds = dest - 1;
922d8de8 6911
a683cc34 6912 /* There are 2 kinds of instructions:
bed3d976
JB		 6913 1. 5 operands: 4 register operands or 3 register operands
6914 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6915 VexW0 or VexW1. The destination must be either XMM, YMM or
43234a1e 6916 ZMM register.
bed3d976 6917 2. 4 operands: 4 register operands or 3 register operands
2f1bada2 6918 plus 1 memory operand, with VexXDS. */
922d8de8 6919 gas_assert ((i.reg_operands == 4
bed3d976
JB		 6920 || (i.reg_operands == 3 && i.mem_operands == 1))
6921 && i.tm.opcode_modifier.vexvvvv == VEXXDS
dcd7e323
JB		 6922 && i.tm.opcode_modifier.vexw
6923 && i.tm.operand_types[dest].bitfield.regsimd);
a683cc34 6924
48db9223
JB		 6925 /* If VexW1 is set, the first non-immediate operand is the source and
6926 the second non-immediate one is encoded in the immediate operand. */
6927 if (i.tm.opcode_modifier.vexw == VEXW1)
6928 {
6929 source = i.imm_operands;
6930 reg_slot = i.imm_operands + 1;
6931 }
6932 else
6933 {
6934 source = i.imm_operands + 1;
6935 reg_slot = i.imm_operands;
6936 }
6937
a683cc34 6938 if (i.imm_operands == 0)
bed3d976
JB		 6939 {
6940 /* When there is no immediate operand, generate an 8bit
6941 immediate operand to encode the first operand. */
6942 exp = &im_expressions[i.imm_operands++];
6943 i.op[i.operands].imms = exp;
6944 i.types[i.operands] = imm8;
6945 i.operands++;
6946
6947 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6948 exp->X_op = O_constant;
6949 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
43234a1e
L		 6950 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6951 }
922d8de8 6952 else
bed3d976
JB		 6953 {
6954 unsigned int imm_slot;
a683cc34 6955
2f1bada2
JB		 6956 gas_assert (i.imm_operands == 1 && i.types[0].bitfield.vec_imm4);
6957
bed3d976
JB		 6958 if (i.tm.opcode_modifier.immext)
6959 {
6960 /* When ImmExt is set, the immediate byte is the last
6961 operand. */
6962 imm_slot = i.operands - 1;
6963 source--;
6964 reg_slot--;
6965 }
6966 else
6967 {
6968 imm_slot = 0;
6969
6970 /* Turn on Imm8 so that output_imm will generate it. */
6971 i.types[imm_slot].bitfield.imm8 = 1;
6972 }
6973
6974 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6975 i.op[imm_slot].imms->X_add_number
6976 |= register_number (i.op[reg_slot].regs) << 4;
43234a1e 6977 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
bed3d976 6978 }
a683cc34 6979
10c17abd 6980 gas_assert (i.tm.operand_types[nds].bitfield.regsimd);
dae39acc 6981 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 6982 }
6983 else
6984 source = dest = 0;
29b0f896
AM		 6985
6986 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 6987 implicit registers do not count. If there are 3 register
6988 operands, it must be a instruction with VexNDS. For a
6989 instruction with VexNDD, the destination register is encoded
6990 in VEX prefix. If there are 4 register operands, it must be
6991 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 6992 if (i.mem_operands == 0
6993 && ((i.reg_operands == 2
2426c15f 6994 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 6995 || (i.reg_operands == 3
2426c15f 6996 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 6997 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 6998 {
cab737b9
L		 6999 switch (i.operands)
7000 {
7001 case 2:
7002 source = 0;
7003 break;
7004 case 3:
c81128dc
L		 7005 /* When there are 3 operands, one of them may be immediate,
7006 which may be the first or the last operand. Otherwise,
c0f3af97
L		 7007 the first operand must be shift count register (cl) or it
7008 is an instruction with VexNDS. */
9c2799c2 7009 gas_assert (i.imm_operands == 1
7ab9ffdd 7010 || (i.imm_operands == 0
2426c15f 7011 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 7012 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 7013 if (operand_type_check (i.types[0], imm)
7014 || i.types[0].bitfield.shiftcount)
7015 source = 1;
7016 else
7017 source = 0;
cab737b9
L		 7018 break;
7019 case 4:
368d64cc
L		 7020 /* When there are 4 operands, the first two must be 8bit
7021 immediate operands. The source operand will be the 3rd
c0f3af97
L		 7022 one.
7023
7024 For instructions with VexNDS, if the first operand
7025 an imm8, the source operand is the 2nd one. If the last
7026 operand is imm8, the source operand is the first one. */
9c2799c2 7027 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 7028 && i.types[0].bitfield.imm8
7029 && i.types[1].bitfield.imm8)
2426c15f 7030 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 7031 && i.imm_operands == 1
7032 && (i.types[0].bitfield.imm8
43234a1e
L		 7033 || i.types[i.operands - 1].bitfield.imm8
7034 || i.rounding)));
9f2670f2
L		 7035 if (i.imm_operands == 2)
7036 source = 2;
7037 else
c0f3af97
L		 7038 {
7039 if (i.types[0].bitfield.imm8)
7040 source = 1;
7041 else
7042 source = 0;
7043 }
c0f3af97
L		 7044 break;
7045 case 5:
e771e7c9 7046 if (is_evex_encoding (&i.tm))
43234a1e
L		 7047 {
7048 /* For EVEX instructions, when there are 5 operands, the
7049 first one must be immediate operand. If the second one
7050 is immediate operand, the source operand is the 3th
7051 one. If the last one is immediate operand, the source
7052 operand is the 2nd one. */
7053 gas_assert (i.imm_operands == 2
7054 && i.tm.opcode_modifier.sae
7055 && operand_type_check (i.types[0], imm));
7056 if (operand_type_check (i.types[1], imm))
7057 source = 2;
7058 else if (operand_type_check (i.types[4], imm))
7059 source = 1;
7060 else
7061 abort ();
7062 }
cab737b9
L		 7063 break;
7064 default:
7065 abort ();
7066 }
7067
c0f3af97
L		 7068 if (!vex_3_sources)
7069 {
7070 dest = source + 1;
7071
43234a1e
L		 7072 /* RC/SAE operand could be between DEST and SRC. That happens
7073 when one operand is GPR and the other one is XMM/YMM/ZMM
7074 register. */
7075 if (i.rounding && i.rounding->operand == (int) dest)
7076 dest++;
7077
2426c15f 7078 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97 7079 {
43234a1e 7080 /* For instructions with VexNDS, the register-only source
c5d0745b 7081 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
43234a1e
L		 7082 register. It is encoded in VEX prefix. We need to
7083 clear RegMem bit before calling operand_type_equal. */
f12dc422
L		 7084
7085 i386_operand_type op;
7086 unsigned int vvvv;
7087
7088 /* Check register-only source operand when two source
7089 operands are swapped. */
7090 if (!i.tm.operand_types[source].bitfield.baseindex
7091 && i.tm.operand_types[dest].bitfield.baseindex)
7092 {
7093 vvvv = source;
7094 source = dest;
7095 }
7096 else
7097 vvvv = dest;
7098
7099 op = i.tm.operand_types[vvvv];
fa99fab2 7100 op.bitfield.regmem = 0;
c0f3af97 7101 if ((dest + 1) >= i.operands
dc821c5f
JB		 7102 || ((!op.bitfield.reg
7103 || (!op.bitfield.dword && !op.bitfield.qword))
10c17abd 7104 && !op.bitfield.regsimd
43234a1e 7105 && !operand_type_equal (&op, &regmask)))
c0f3af97 7106 abort ();
f12dc422 7107 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 7108 dest++;
7109 }
7110 }
29b0f896
AM		 7111
7112 i.rm.mode = 3;
7113 /* One of the register operands will be encoded in the i.tm.reg
7114 field, the other in the combined i.tm.mode and i.tm.regmem
7115 fields. If no form of this instruction supports a memory
7116 destination operand, then we assume the source operand may
7117 sometimes be a memory operand and so we need to store the
7118 destination in the i.rm.reg field. */
40fb9820
L		 7119 if (!i.tm.operand_types[dest].bitfield.regmem
7120 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 7121 {
7122 i.rm.reg = i.op[dest].regs->reg_num;
7123 i.rm.regmem = i.op[source].regs->reg_num;
b4a3a7b4
L		 7124 if (i.op[dest].regs->reg_type.bitfield.regmmx
7125 || i.op[source].regs->reg_type.bitfield.regmmx)
7126 i.has_regmmx = TRUE;
7127 else if (i.op[dest].regs->reg_type.bitfield.regsimd
7128 || i.op[source].regs->reg_type.bitfield.regsimd)
7129 {
7130 if (i.types[dest].bitfield.zmmword
7131 || i.types[source].bitfield.zmmword)
7132 i.has_regzmm = TRUE;
7133 else if (i.types[dest].bitfield.ymmword
7134 || i.types[source].bitfield.ymmword)
7135 i.has_regymm = TRUE;
7136 else
7137 i.has_regxmm = TRUE;
7138 }
29b0f896 7139 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 7140 i.rex |= REX_R;
43234a1e
L		 7141 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
7142 i.vrex |= REX_R;
29b0f896 7143 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 7144 i.rex |= REX_B;
43234a1e
L		 7145 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
7146 i.vrex |= REX_B;
29b0f896
AM		 7147 }
7148 else
7149 {
7150 i.rm.reg = i.op[source].regs->reg_num;
7151 i.rm.regmem = i.op[dest].regs->reg_num;
7152 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 7153 i.rex |= REX_B;
43234a1e
L		 7154 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
7155 i.vrex |= REX_B;
29b0f896 7156 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 7157 i.rex |= REX_R;
43234a1e
L		 7158 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
7159 i.vrex |= REX_R;
29b0f896 7160 }
e0c7f900 7161 if (flag_code != CODE_64BIT && (i.rex & REX_R))
c4a530c5 7162 {
e0c7f900 7163 if (!i.types[i.tm.operand_types[0].bitfield.regmem].bitfield.control)
c4a530c5 7164 abort ();
e0c7f900 7165 i.rex &= ~REX_R;
c4a530c5
JB		 7166 add_prefix (LOCK_PREFIX_OPCODE);
7167 }
29b0f896
AM		 7168 }
7169 else
7170 { /* If it's not 2 reg operands... */
c0f3af97
L		 7171 unsigned int mem;
7172
29b0f896
AM		 7173 if (i.mem_operands)
7174 {
7175 unsigned int fake_zero_displacement = 0;
99018f42 7176 unsigned int op;
4eed87de 7177
7ab9ffdd
L		 7178 for (op = 0; op < i.operands; op++)
7179 if (operand_type_check (i.types[op], anymem))
7180 break;
7ab9ffdd 7181 gas_assert (op < i.operands);
29b0f896 7182
6c30d220
L		 7183 if (i.tm.opcode_modifier.vecsib)
7184 {
e968fc9b 7185 if (i.index_reg->reg_num == RegIZ)
6c30d220
L		 7186 abort ();
7187
7188 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7189 if (!i.base_reg)
7190 {
7191 i.sib.base = NO_BASE_REGISTER;
7192 i.sib.scale = i.log2_scale_factor;
7193 i.types[op].bitfield.disp8 = 0;
7194 i.types[op].bitfield.disp16 = 0;
7195 i.types[op].bitfield.disp64 = 0;
43083a50 7196 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
6c30d220
L		 7197 {
7198 /* Must be 32 bit */
7199 i.types[op].bitfield.disp32 = 1;
7200 i.types[op].bitfield.disp32s = 0;
7201 }
7202 else
7203 {
7204 i.types[op].bitfield.disp32 = 0;
7205 i.types[op].bitfield.disp32s = 1;
7206 }
7207 }
7208 i.sib.index = i.index_reg->reg_num;
7209 if ((i.index_reg->reg_flags & RegRex) != 0)
7210 i.rex |= REX_X;
43234a1e
L		 7211 if ((i.index_reg->reg_flags & RegVRex) != 0)
7212 i.vrex |= REX_X;
6c30d220
L		 7213 }
7214
29b0f896
AM		 7215 default_seg = &ds;
7216
7217 if (i.base_reg == 0)
7218 {
7219 i.rm.mode = 0;
7220 if (!i.disp_operands)
9bb129e8 7221 fake_zero_displacement = 1;
29b0f896
AM		 7222 if (i.index_reg == 0)
7223 {
73053c1f
JB		 7224 i386_operand_type newdisp;
7225
6c30d220 7226 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 7227 /* Operand is just <disp> */
20f0a1fc 7228 if (flag_code == CODE_64BIT)
29b0f896
AM		 7229 {
7230 /* 64bit mode overwrites the 32bit absolute
7231 addressing by RIP relative addressing and
7232 absolute addressing is encoded by one of the
7233 redundant SIB forms. */
7234 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7235 i.sib.base = NO_BASE_REGISTER;
7236 i.sib.index = NO_INDEX_REGISTER;
73053c1f 7237 newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32);
20f0a1fc 7238 }
fc225355
L		 7239 else if ((flag_code == CODE_16BIT)
7240 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 7241 {
7242 i.rm.regmem = NO_BASE_REGISTER_16;
73053c1f 7243 newdisp = disp16;
20f0a1fc
NC		 7244 }
7245 else
7246 {
7247 i.rm.regmem = NO_BASE_REGISTER;
73053c1f 7248 newdisp = disp32;
29b0f896 7249 }
73053c1f
JB		 7250 i.types[op] = operand_type_and_not (i.types[op], anydisp);
7251 i.types[op] = operand_type_or (i.types[op], newdisp);
29b0f896 7252 }
6c30d220 7253 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 7254 {
6c30d220 7255 /* !i.base_reg && i.index_reg */
e968fc9b 7256 if (i.index_reg->reg_num == RegIZ)
db51cc60
L		 7257 i.sib.index = NO_INDEX_REGISTER;
7258 else
7259 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 7260 i.sib.base = NO_BASE_REGISTER;
7261 i.sib.scale = i.log2_scale_factor;
7262 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 7263 i.types[op].bitfield.disp8 = 0;
7264 i.types[op].bitfield.disp16 = 0;
7265 i.types[op].bitfield.disp64 = 0;
43083a50 7266 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
40fb9820
L		 7267 {
7268 /* Must be 32 bit */
7269 i.types[op].bitfield.disp32 = 1;
7270 i.types[op].bitfield.disp32s = 0;
7271 }
29b0f896 7272 else
40fb9820
L		 7273 {
7274 i.types[op].bitfield.disp32 = 0;
7275 i.types[op].bitfield.disp32s = 1;
7276 }
29b0f896 7277 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 7278 i.rex |= REX_X;
29b0f896
AM		 7279 }
7280 }
7281 /* RIP addressing for 64bit mode. */
e968fc9b 7282 else if (i.base_reg->reg_num == RegIP)
29b0f896 7283 {
6c30d220 7284 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 7285 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 7286 i.types[op].bitfield.disp8 = 0;
7287 i.types[op].bitfield.disp16 = 0;
7288 i.types[op].bitfield.disp32 = 0;
7289 i.types[op].bitfield.disp32s = 1;
7290 i.types[op].bitfield.disp64 = 0;
71903a11 7291 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 7292 if (! i.disp_operands)
7293 fake_zero_displacement = 1;
29b0f896 7294 }
dc821c5f 7295 else if (i.base_reg->reg_type.bitfield.word)
29b0f896 7296 {
6c30d220 7297 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 7298 switch (i.base_reg->reg_num)
7299 {
7300 case 3: /* (%bx) */
7301 if (i.index_reg == 0)
7302 i.rm.regmem = 7;
7303 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7304 i.rm.regmem = i.index_reg->reg_num - 6;
7305 break;
7306 case 5: /* (%bp) */
7307 default_seg = &ss;
7308 if (i.index_reg == 0)
7309 {
7310 i.rm.regmem = 6;
40fb9820 7311 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 7312 {
7313 /* fake (%bp) into 0(%bp) */
b5014f7a 7314 i.types[op].bitfield.disp8 = 1;
252b5132 7315 fake_zero_displacement = 1;
29b0f896
AM		 7316 }
7317 }
7318 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7319 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
7320 break;
7321 default: /* (%si) -> 4 or (%di) -> 5 */
7322 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
7323 }
7324 i.rm.mode = mode_from_disp_size (i.types[op]);
7325 }
7326 else /* i.base_reg and 32/64 bit mode */
7327 {
7328 if (flag_code == CODE_64BIT
40fb9820
L		 7329 && operand_type_check (i.types[op], disp))
7330 {
73053c1f
JB		 7331 i.types[op].bitfield.disp16 = 0;
7332 i.types[op].bitfield.disp64 = 0;
40fb9820 7333 if (i.prefix[ADDR_PREFIX] == 0)
73053c1f
JB		 7334 {
7335 i.types[op].bitfield.disp32 = 0;
7336 i.types[op].bitfield.disp32s = 1;
7337 }
40fb9820 7338 else
73053c1f
JB		 7339 {
7340 i.types[op].bitfield.disp32 = 1;
7341 i.types[op].bitfield.disp32s = 0;
7342 }
40fb9820 7343 }
20f0a1fc 7344
6c30d220
L		 7345 if (!i.tm.opcode_modifier.vecsib)
7346 i.rm.regmem = i.base_reg->reg_num;
29b0f896 7347 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 7348 i.rex |= REX_B;
29b0f896
AM		 7349 i.sib.base = i.base_reg->reg_num;
7350 /* x86-64 ignores REX prefix bit here to avoid decoder
7351 complications. */
848930b2
JB		 7352 if (!(i.base_reg->reg_flags & RegRex)
7353 && (i.base_reg->reg_num == EBP_REG_NUM
7354 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 7355 default_seg = &ss;
848930b2 7356 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 7357 {
848930b2 7358 fake_zero_displacement = 1;
b5014f7a 7359 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 7360 }
7361 i.sib.scale = i.log2_scale_factor;
7362 if (i.index_reg == 0)
7363 {
6c30d220 7364 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 7365 /* <disp>(%esp) becomes two byte modrm with no index
7366 register. We've already stored the code for esp
7367 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7368 Any base register besides %esp will not use the
7369 extra modrm byte. */
7370 i.sib.index = NO_INDEX_REGISTER;
29b0f896 7371 }
6c30d220 7372 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 7373 {
e968fc9b 7374 if (i.index_reg->reg_num == RegIZ)
db51cc60
L		 7375 i.sib.index = NO_INDEX_REGISTER;
7376 else
7377 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 7378 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7379 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 7380 i.rex |= REX_X;
29b0f896 7381 }
67a4f2b7
AO		 7382
7383 if (i.disp_operands
7384 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
7385 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
7386 i.rm.mode = 0;
7387 else
a501d77e
L		 7388 {
7389 if (!fake_zero_displacement
7390 && !i.disp_operands
7391 && i.disp_encoding)
7392 {
7393 fake_zero_displacement = 1;
7394 if (i.disp_encoding == disp_encoding_8bit)
7395 i.types[op].bitfield.disp8 = 1;
7396 else
7397 i.types[op].bitfield.disp32 = 1;
7398 }
7399 i.rm.mode = mode_from_disp_size (i.types[op]);
7400 }
29b0f896 7401 }
252b5132 7402
29b0f896
AM		 7403 if (fake_zero_displacement)
7404 {
7405 /* Fakes a zero displacement assuming that i.types[op]
7406 holds the correct displacement size. */
7407 expressionS *exp;
7408
9c2799c2 7409 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 7410 exp = &disp_expressions[i.disp_operands++];
7411 i.op[op].disps = exp;
7412 exp->X_op = O_constant;
7413 exp->X_add_number = 0;
7414 exp->X_add_symbol = (symbolS *) 0;
7415 exp->X_op_symbol = (symbolS *) 0;
7416 }
c0f3af97
L		 7417
7418 mem = op;
29b0f896 7419 }
c0f3af97
L		 7420 else
7421 mem = ~0;
252b5132 7422
8c43a48b 7423 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 7424 {
7425 if (operand_type_check (i.types[0], imm))
7426 i.vex.register_specifier = NULL;
7427 else
7428 {
7429 /* VEX.vvvv encodes one of the sources when the first
7430 operand is not an immediate. */
1ef99a7b 7431 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 7432 i.vex.register_specifier = i.op[0].regs;
7433 else
7434 i.vex.register_specifier = i.op[1].regs;
7435 }
7436
7437 /* Destination is a XMM register encoded in the ModRM.reg
7438 and VEX.R bit. */
7439 i.rm.reg = i.op[2].regs->reg_num;
7440 if ((i.op[2].regs->reg_flags & RegRex) != 0)
7441 i.rex |= REX_R;
7442
7443 /* ModRM.rm and VEX.B encodes the other source. */
7444 if (!i.mem_operands)
7445 {
7446 i.rm.mode = 3;
7447
1ef99a7b 7448 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 7449 i.rm.regmem = i.op[1].regs->reg_num;
7450 else
7451 i.rm.regmem = i.op[0].regs->reg_num;
7452
7453 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7454 i.rex |= REX_B;
7455 }
7456 }
2426c15f 7457 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 7458 {
7459 i.vex.register_specifier = i.op[2].regs;
7460 if (!i.mem_operands)
7461 {
7462 i.rm.mode = 3;
7463 i.rm.regmem = i.op[1].regs->reg_num;
7464 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7465 i.rex |= REX_B;
7466 }
7467 }
29b0f896
AM		 7468 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7469 (if any) based on i.tm.extension_opcode. Again, we must be
7470 careful to make sure that segment/control/debug/test/MMX
7471 registers are coded into the i.rm.reg field. */
f88c9eb0 7472 else if (i.reg_operands)
29b0f896 7473 {
99018f42 7474 unsigned int op;
7ab9ffdd
L		 7475 unsigned int vex_reg = ~0;
7476
7477 for (op = 0; op < i.operands; op++)
b4a3a7b4
L		 7478 {
7479 if (i.types[op].bitfield.reg
7480 || i.types[op].bitfield.regbnd
7481 || i.types[op].bitfield.regmask
7482 || i.types[op].bitfield.sreg2
7483 || i.types[op].bitfield.sreg3
7484 || i.types[op].bitfield.control
7485 || i.types[op].bitfield.debug
7486 || i.types[op].bitfield.test)
7487 break;
7488 if (i.types[op].bitfield.regsimd)
7489 {
7490 if (i.types[op].bitfield.zmmword)
7491 i.has_regzmm = TRUE;
7492 else if (i.types[op].bitfield.ymmword)
7493 i.has_regymm = TRUE;
7494 else
7495 i.has_regxmm = TRUE;
7496 break;
7497 }
7498 if (i.types[op].bitfield.regmmx)
7499 {
7500 i.has_regmmx = TRUE;
7501 break;
7502 }
7503 }
c0209578 7504
7ab9ffdd
L		 7505 if (vex_3_sources)
7506 op = dest;
2426c15f 7507 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 7508 {
7509 /* For instructions with VexNDS, the register-only
7510 source operand is encoded in VEX prefix. */
7511 gas_assert (mem != (unsigned int) ~0);
c0f3af97 7512
7ab9ffdd 7513 if (op > mem)
c0f3af97 7514 {
7ab9ffdd
L		 7515 vex_reg = op++;
7516 gas_assert (op < i.operands);
c0f3af97
L		 7517 }
7518 else
c0f3af97 7519 {
f12dc422
L		 7520 /* Check register-only source operand when two source
7521 operands are swapped. */
7522 if (!i.tm.operand_types[op].bitfield.baseindex
7523 && i.tm.operand_types[op + 1].bitfield.baseindex)
7524 {
7525 vex_reg = op;
7526 op += 2;
7527 gas_assert (mem == (vex_reg + 1)
7528 && op < i.operands);
7529 }
7530 else
7531 {
7532 vex_reg = op + 1;
7533 gas_assert (vex_reg < i.operands);
7534 }
c0f3af97 7535 }
7ab9ffdd 7536 }
2426c15f 7537 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 7538 {
f12dc422 7539 /* For instructions with VexNDD, the register destination
7ab9ffdd 7540 is encoded in VEX prefix. */
f12dc422
L		 7541 if (i.mem_operands == 0)
7542 {
7543 /* There is no memory operand. */
7544 gas_assert ((op + 2) == i.operands);
7545 vex_reg = op + 1;
7546 }
7547 else
8d63c93e 7548 {
ed438a93
JB		 7549 /* There are only 2 non-immediate operands. */
7550 gas_assert (op < i.imm_operands + 2
7551 && i.operands == i.imm_operands + 2);
7552 vex_reg = i.imm_operands + 1;
f12dc422 7553 }
7ab9ffdd
L		 7554 }
7555 else
7556 gas_assert (op < i.operands);
99018f42 7557
7ab9ffdd
L		 7558 if (vex_reg != (unsigned int) ~0)
7559 {
f12dc422 7560 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 7561
dc821c5f
JB		 7562 if ((!type->bitfield.reg
7563 || (!type->bitfield.dword && !type->bitfield.qword))
10c17abd 7564 && !type->bitfield.regsimd
43234a1e 7565 && !operand_type_equal (type, &regmask))
7ab9ffdd 7566 abort ();
f88c9eb0 7567
7ab9ffdd
L		 7568 i.vex.register_specifier = i.op[vex_reg].regs;
7569 }
7570
1b9f0c97
L		 7571 /* Don't set OP operand twice. */
7572 if (vex_reg != op)
7ab9ffdd 7573 {
1b9f0c97
L		 7574 /* If there is an extension opcode to put here, the
7575 register number must be put into the regmem field. */
7576 if (i.tm.extension_opcode != None)
7577 {
7578 i.rm.regmem = i.op[op].regs->reg_num;
7579 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7580 i.rex |= REX_B;
43234a1e
L		 7581 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7582 i.vrex |= REX_B;
1b9f0c97
L		 7583 }
7584 else
7585 {
7586 i.rm.reg = i.op[op].regs->reg_num;
7587 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7588 i.rex |= REX_R;
43234a1e
L		 7589 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7590 i.vrex |= REX_R;
1b9f0c97 7591 }
7ab9ffdd 7592 }
252b5132 7593
29b0f896
AM		 7594 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7595 must set it to 3 to indicate this is a register operand
7596 in the regmem field. */
7597 if (!i.mem_operands)
7598 i.rm.mode = 3;
7599 }
252b5132 7600
29b0f896 7601 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 7602 if (i.tm.extension_opcode != None)
29b0f896
AM		 7603 i.rm.reg = i.tm.extension_opcode;
7604 }
7605 return default_seg;
7606}
252b5132 7607
29b0f896 7608static void
e3bb37b5 7609output_branch (void)
29b0f896
AM		 7610{
7611 char *p;
f8a5c266 7612 int size;
29b0f896
AM		 7613 int code16;
7614 int prefix;
7615 relax_substateT subtype;
7616 symbolS *sym;
7617 offsetT off;
7618
f8a5c266 7619 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 7620 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 7621
7622 prefix = 0;
7623 if (i.prefix[DATA_PREFIX] != 0)
252b5132 7624 {
29b0f896
AM		 7625 prefix = 1;
7626 i.prefixes -= 1;
7627 code16 ^= CODE16;
252b5132 7628 }
29b0f896
AM		 7629 /* Pentium4 branch hints. */
7630 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7631 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 7632 {
29b0f896
AM		 7633 prefix++;
7634 i.prefixes--;
7635 }
7636 if (i.prefix[REX_PREFIX] != 0)
7637 {
7638 prefix++;
7639 i.prefixes--;
2f66722d
AM		 7640 }
7641
7e8b059b
L		 7642 /* BND prefixed jump. */
7643 if (i.prefix[BND_PREFIX] != 0)
7644 {
7645 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7646 i.prefixes -= 1;
7647 }
7648
29b0f896
AM		 7649 if (i.prefixes != 0 && !intel_syntax)
7650 as_warn (_("skipping prefixes on this instruction"));
7651
7652 /* It's always a symbol; End frag & setup for relax.
7653 Make sure there is enough room in this frag for the largest
7654 instruction we may generate in md_convert_frag. This is 2
7655 bytes for the opcode and room for the prefix and largest
7656 displacement. */
7657 frag_grow (prefix + 2 + 4);
7658 /* Prefix and 1 opcode byte go in fr_fix. */
7659 p = frag_more (prefix + 1);
7660 if (i.prefix[DATA_PREFIX] != 0)
7661 *p++ = DATA_PREFIX_OPCODE;
7662 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
7663 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
7664 *p++ = i.prefix[SEG_PREFIX];
7665 if (i.prefix[REX_PREFIX] != 0)
7666 *p++ = i.prefix[REX_PREFIX];
7667 *p = i.tm.base_opcode;
7668
7669 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 7670 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 7671 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 7672 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 7673 else
f8a5c266 7674 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 7675 subtype |= code16;
3e73aa7c 7676
29b0f896
AM		 7677 sym = i.op[0].disps->X_add_symbol;
7678 off = i.op[0].disps->X_add_number;
3e73aa7c 7679
29b0f896
AM		 7680 if (i.op[0].disps->X_op != O_constant
7681 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 7682 {
29b0f896
AM		 7683 /* Handle complex expressions. */
7684 sym = make_expr_symbol (i.op[0].disps);
7685 off = 0;
7686 }
3e73aa7c 7687
29b0f896
AM		 7688 /* 1 possible extra opcode + 4 byte displacement go in var part.
7689 Pass reloc in fr_var. */
d258b828 7690 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
29b0f896 7691}
3e73aa7c 7692
bd7ab16b
L		 7693#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7694/* Return TRUE iff PLT32 relocation should be used for branching to
7695 symbol S. */
7696
7697static bfd_boolean
7698need_plt32_p (symbolS *s)
7699{
7700 /* PLT32 relocation is ELF only. */
7701 if (!IS_ELF)
7702 return FALSE;
7703
7704 /* Since there is no need to prepare for PLT branch on x86-64, we
7705 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7706 be used as a marker for 32-bit PC-relative branches. */
7707 if (!object_64bit)
7708 return FALSE;
7709
7710 /* Weak or undefined symbol need PLT32 relocation. */
7711 if (S_IS_WEAK (s) || !S_IS_DEFINED (s))
7712 return TRUE;
7713
7714 /* Non-global symbol doesn't need PLT32 relocation. */
7715 if (! S_IS_EXTERNAL (s))
7716 return FALSE;
7717
7718 /* Other global symbols need PLT32 relocation. NB: Symbol with
7719 non-default visibilities are treated as normal global symbol
7720 so that PLT32 relocation can be used as a marker for 32-bit
7721 PC-relative branches. It is useful for linker relaxation. */
7722 return TRUE;
7723}
7724#endif
7725
29b0f896 7726static void
e3bb37b5 7727output_jump (void)
29b0f896
AM		 7728{
7729 char *p;
7730 int size;
3e02c1cc 7731 fixS *fixP;
bd7ab16b 7732 bfd_reloc_code_real_type jump_reloc = i.reloc[0];
29b0f896 7733
40fb9820 7734 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 7735 {
7736 /* This is a loop or jecxz type instruction. */
7737 size = 1;
7738 if (i.prefix[ADDR_PREFIX] != 0)
7739 {
7740 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
7741 i.prefixes -= 1;
7742 }
7743 /* Pentium4 branch hints. */
7744 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7745 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7746 {
7747 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
7748 i.prefixes--;
3e73aa7c
JH		 7749 }
7750 }
29b0f896
AM		 7751 else
7752 {
7753 int code16;
3e73aa7c 7754
29b0f896
AM		 7755 code16 = 0;
7756 if (flag_code == CODE_16BIT)
7757 code16 = CODE16;
3e73aa7c 7758
29b0f896
AM		 7759 if (i.prefix[DATA_PREFIX] != 0)
7760 {
7761 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
7762 i.prefixes -= 1;
7763 code16 ^= CODE16;
7764 }
252b5132 7765
29b0f896
AM		 7766 size = 4;
7767 if (code16)
7768 size = 2;
7769 }
9fcc94b6 7770
29b0f896
AM		 7771 if (i.prefix[REX_PREFIX] != 0)
7772 {
7773 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
7774 i.prefixes -= 1;
7775 }
252b5132 7776
7e8b059b
L		 7777 /* BND prefixed jump. */
7778 if (i.prefix[BND_PREFIX] != 0)
7779 {
7780 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7781 i.prefixes -= 1;
7782 }
7783
29b0f896
AM		 7784 if (i.prefixes != 0 && !intel_syntax)
7785 as_warn (_("skipping prefixes on this instruction"));
e0890092 7786
42164a71
L		 7787 p = frag_more (i.tm.opcode_length + size);
7788 switch (i.tm.opcode_length)
7789 {
7790 case 2:
7791 *p++ = i.tm.base_opcode >> 8;
1a0670f3 7792 /* Fall through. */
42164a71
L		 7793 case 1:
7794 *p++ = i.tm.base_opcode;
7795 break;
7796 default:
7797 abort ();
7798 }
e0890092 7799
bd7ab16b
L		 7800#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7801 if (size == 4
7802 && jump_reloc == NO_RELOC
7803 && need_plt32_p (i.op[0].disps->X_add_symbol))
7804 jump_reloc = BFD_RELOC_X86_64_PLT32;
7805#endif
7806
7807 jump_reloc = reloc (size, 1, 1, jump_reloc);
7808
3e02c1cc 7809 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
bd7ab16b 7810 i.op[0].disps, 1, jump_reloc);
3e02c1cc
AM		 7811
7812 /* All jumps handled here are signed, but don't use a signed limit
7813 check for 32 and 16 bit jumps as we want to allow wrap around at
7814 4G and 64k respectively. */
7815 if (size == 1)
7816 fixP->fx_signed = 1;
29b0f896 7817}
e0890092 7818
29b0f896 7819static void
e3bb37b5 7820output_interseg_jump (void)
29b0f896
AM		 7821{
7822 char *p;
7823 int size;
7824 int prefix;
7825 int code16;
252b5132 7826
29b0f896
AM		 7827 code16 = 0;
7828 if (flag_code == CODE_16BIT)
7829 code16 = CODE16;
a217f122 7830
29b0f896
AM		 7831 prefix = 0;
7832 if (i.prefix[DATA_PREFIX] != 0)
7833 {
7834 prefix = 1;
7835 i.prefixes -= 1;
7836 code16 ^= CODE16;
7837 }
7838 if (i.prefix[REX_PREFIX] != 0)
7839 {
7840 prefix++;
7841 i.prefixes -= 1;
7842 }
252b5132 7843
29b0f896
AM		 7844 size = 4;
7845 if (code16)
7846 size = 2;
252b5132 7847
29b0f896
AM		 7848 if (i.prefixes != 0 && !intel_syntax)
7849 as_warn (_("skipping prefixes on this instruction"));
252b5132 7850
29b0f896
AM		 7851 /* 1 opcode; 2 segment; offset */
7852 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 7853
29b0f896
AM		 7854 if (i.prefix[DATA_PREFIX] != 0)
7855 *p++ = DATA_PREFIX_OPCODE;
252b5132 7856
29b0f896
AM		 7857 if (i.prefix[REX_PREFIX] != 0)
7858 *p++ = i.prefix[REX_PREFIX];
252b5132 7859
29b0f896
AM		 7860 *p++ = i.tm.base_opcode;
7861 if (i.op[1].imms->X_op == O_constant)
7862 {
7863 offsetT n = i.op[1].imms->X_add_number;
252b5132 7864
29b0f896
AM		 7865 if (size == 2
7866 && !fits_in_unsigned_word (n)
7867 && !fits_in_signed_word (n))
7868 {
7869 as_bad (_("16-bit jump out of range"));
7870 return;
7871 }
7872 md_number_to_chars (p, n, size);
7873 }
7874 else
7875 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 7876 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
29b0f896
AM		 7877 if (i.op[0].imms->X_op != O_constant)
7878 as_bad (_("can't handle non absolute segment in `%s'"),
7879 i.tm.name);
7880 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7881}
a217f122 7882
b4a3a7b4
L		 7883#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7884void
7885x86_cleanup (void)
7886{
7887 char *p;
7888 asection *seg = now_seg;
7889 subsegT subseg = now_subseg;
7890 asection *sec;
7891 unsigned int alignment, align_size_1;
7892 unsigned int isa_1_descsz, feature_2_descsz, descsz;
7893 unsigned int isa_1_descsz_raw, feature_2_descsz_raw;
7894 unsigned int padding;
7895
7896 if (!IS_ELF || !x86_used_note)
7897 return;
7898
b4a3a7b4
L		 7899 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X86;
7900
7901 /* The .note.gnu.property section layout:
7902
7903 Field Length Contents
7904 ---- ---- ----
7905 n_namsz 4 4
7906 n_descsz 4 The note descriptor size
7907 n_type 4 NT_GNU_PROPERTY_TYPE_0
7908 n_name 4 "GNU"
7909 n_desc n_descsz The program property array
7910 .... .... ....
7911 */
7912
7913 /* Create the .note.gnu.property section. */
7914 sec = subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME, 0);
7915 bfd_set_section_flags (stdoutput, sec,
7916 (SEC_ALLOC
7917 | SEC_LOAD
7918 | SEC_DATA
7919 | SEC_HAS_CONTENTS
7920 | SEC_READONLY));
7921
7922 if (get_elf_backend_data (stdoutput)->s->elfclass == ELFCLASS64)
7923 {
7924 align_size_1 = 7;
7925 alignment = 3;
7926 }
7927 else
7928 {
7929 align_size_1 = 3;
7930 alignment = 2;
7931 }
7932
7933 bfd_set_section_alignment (stdoutput, sec, alignment);
7934 elf_section_type (sec) = SHT_NOTE;
7935
7936 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
7937 + 4-byte data */
7938 isa_1_descsz_raw = 4 + 4 + 4;
7939 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
7940 isa_1_descsz = (isa_1_descsz_raw + align_size_1) & ~align_size_1;
7941
7942 feature_2_descsz_raw = isa_1_descsz;
7943 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
7944 + 4-byte data */
7945 feature_2_descsz_raw += 4 + 4 + 4;
7946 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
7947 feature_2_descsz = ((feature_2_descsz_raw + align_size_1)
7948 & ~align_size_1);
7949
7950 descsz = feature_2_descsz;
7951 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
7952 p = frag_more (4 + 4 + 4 + 4 + descsz);
7953
7954 /* Write n_namsz. */
7955 md_number_to_chars (p, (valueT) 4, 4);
7956
7957 /* Write n_descsz. */
7958 md_number_to_chars (p + 4, (valueT) descsz, 4);
7959
7960 /* Write n_type. */
7961 md_number_to_chars (p + 4 * 2, (valueT) NT_GNU_PROPERTY_TYPE_0, 4);
7962
7963 /* Write n_name. */
7964 memcpy (p + 4 * 3, "GNU", 4);
7965
7966 /* Write 4-byte type. */
7967 md_number_to_chars (p + 4 * 4,
7968 (valueT) GNU_PROPERTY_X86_ISA_1_USED, 4);
7969
7970 /* Write 4-byte data size. */
7971 md_number_to_chars (p + 4 * 5, (valueT) 4, 4);
7972
7973 /* Write 4-byte data. */
7974 md_number_to_chars (p + 4 * 6, (valueT) x86_isa_1_used, 4);
7975
7976 /* Zero out paddings. */
7977 padding = isa_1_descsz - isa_1_descsz_raw;
7978 if (padding)
7979 memset (p + 4 * 7, 0, padding);
7980
7981 /* Write 4-byte type. */
7982 md_number_to_chars (p + isa_1_descsz + 4 * 4,
7983 (valueT) GNU_PROPERTY_X86_FEATURE_2_USED, 4);
7984
7985 /* Write 4-byte data size. */
7986 md_number_to_chars (p + isa_1_descsz + 4 * 5, (valueT) 4, 4);
7987
7988 /* Write 4-byte data. */
7989 md_number_to_chars (p + isa_1_descsz + 4 * 6,
7990 (valueT) x86_feature_2_used, 4);
7991
7992 /* Zero out paddings. */
7993 padding = feature_2_descsz - feature_2_descsz_raw;
7994 if (padding)
7995 memset (p + isa_1_descsz + 4 * 7, 0, padding);
7996
7997 /* We probably can't restore the current segment, for there likely
7998 isn't one yet... */
7999 if (seg && subseg)
8000 subseg_set (seg, subseg);
8001}
8002#endif
8003
29b0f896 8004static void
e3bb37b5 8005output_insn (void)
29b0f896 8006{
2bbd9c25
JJ		 8007 fragS *insn_start_frag;
8008 offsetT insn_start_off;
8009
b4a3a7b4
L		 8010#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8011 if (IS_ELF && x86_used_note)
8012 {
8013 if (i.tm.cpu_flags.bitfield.cpucmov)
8014 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_CMOV;
8015 if (i.tm.cpu_flags.bitfield.cpusse)
8016 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE;
8017 if (i.tm.cpu_flags.bitfield.cpusse2)
8018 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE2;
8019 if (i.tm.cpu_flags.bitfield.cpusse3)
8020 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE3;
8021 if (i.tm.cpu_flags.bitfield.cpussse3)
8022 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSSE3;
8023 if (i.tm.cpu_flags.bitfield.cpusse4_1)
8024 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE4_1;
8025 if (i.tm.cpu_flags.bitfield.cpusse4_2)
8026 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE4_2;
8027 if (i.tm.cpu_flags.bitfield.cpuavx)
8028 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX;
8029 if (i.tm.cpu_flags.bitfield.cpuavx2)
8030 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX2;
8031 if (i.tm.cpu_flags.bitfield.cpufma)
8032 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_FMA;
8033 if (i.tm.cpu_flags.bitfield.cpuavx512f)
8034 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512F;
8035 if (i.tm.cpu_flags.bitfield.cpuavx512cd)
8036 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512CD;
8037 if (i.tm.cpu_flags.bitfield.cpuavx512er)
8038 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512ER;
8039 if (i.tm.cpu_flags.bitfield.cpuavx512pf)
8040 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512PF;
8041 if (i.tm.cpu_flags.bitfield.cpuavx512vl)
8042 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512VL;
8043 if (i.tm.cpu_flags.bitfield.cpuavx512dq)
8044 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512DQ;
8045 if (i.tm.cpu_flags.bitfield.cpuavx512bw)
8046 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512BW;
8047 if (i.tm.cpu_flags.bitfield.cpuavx512_4fmaps)
8048 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS;
8049 if (i.tm.cpu_flags.bitfield.cpuavx512_4vnniw)
8050 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW;
8051 if (i.tm.cpu_flags.bitfield.cpuavx512_bitalg)
8052 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG;
8053 if (i.tm.cpu_flags.bitfield.cpuavx512ifma)
8054 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA;
8055 if (i.tm.cpu_flags.bitfield.cpuavx512vbmi)
8056 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI;
8057 if (i.tm.cpu_flags.bitfield.cpuavx512_vbmi2)
8058 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2;
8059 if (i.tm.cpu_flags.bitfield.cpuavx512_vnni)
8060 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI;
8061
8062 if (i.tm.cpu_flags.bitfield.cpu8087
8063 || i.tm.cpu_flags.bitfield.cpu287
8064 || i.tm.cpu_flags.bitfield.cpu387
8065 || i.tm.cpu_flags.bitfield.cpu687
8066 || i.tm.cpu_flags.bitfield.cpufisttp)
8067 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X87;
8068 /* Don't set GNU_PROPERTY_X86_FEATURE_2_MMX for prefetchtXXX nor
8069 Xfence instructions. */
8070 if (i.tm.base_opcode != 0xf18
8071 && i.tm.base_opcode != 0xf0d
8072 && i.tm.base_opcode != 0xfae
8073 && (i.has_regmmx
8074 || i.tm.cpu_flags.bitfield.cpummx
8075 || i.tm.cpu_flags.bitfield.cpua3dnow
8076 || i.tm.cpu_flags.bitfield.cpua3dnowa))
8077 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_MMX;
8078 if (i.has_regxmm)
8079 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XMM;
8080 if (i.has_regymm)
8081 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_YMM;
8082 if (i.has_regzmm)
8083 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_ZMM;
8084 if (i.tm.cpu_flags.bitfield.cpufxsr)
8085 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_FXSR;
8086 if (i.tm.cpu_flags.bitfield.cpuxsave)
8087 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVE;
8088 if (i.tm.cpu_flags.bitfield.cpuxsaveopt)
8089 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT;
8090 if (i.tm.cpu_flags.bitfield.cpuxsavec)
8091 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEC;
8092 }
8093#endif
8094
29b0f896
AM		 8095 /* Tie dwarf2 debug info to the address at the start of the insn.
8096 We can't do this after the insn has been output as the current
8097 frag may have been closed off. eg. by frag_var. */
8098 dwarf2_emit_insn (0);
8099
2bbd9c25
JJ		 8100 insn_start_frag = frag_now;
8101 insn_start_off = frag_now_fix ();
8102
29b0f896 8103 /* Output jumps. */
40fb9820 8104 if (i.tm.opcode_modifier.jump)
29b0f896 8105 output_branch ();
40fb9820
L		 8106 else if (i.tm.opcode_modifier.jumpbyte
8107 || i.tm.opcode_modifier.jumpdword)
29b0f896 8108 output_jump ();
40fb9820 8109 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 8110 output_interseg_jump ();
8111 else
8112 {
8113 /* Output normal instructions here. */
8114 char *p;
8115 unsigned char *q;
47465058 8116 unsigned int j;
331d2d0d 8117 unsigned int prefix;
4dffcebc 8118
e4e00185
AS		 8119 if (avoid_fence
8120 && i.tm.base_opcode == 0xfae
8121 && i.operands == 1
8122 && i.imm_operands == 1
8123 && (i.op[0].imms->X_add_number == 0xe8
8124 || i.op[0].imms->X_add_number == 0xf0
8125 || i.op[0].imms->X_add_number == 0xf8))
8126 {
8127 /* Encode lfence, mfence, and sfence as
8128 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
8129 offsetT val = 0x240483f0ULL;
8130 p = frag_more (5);
8131 md_number_to_chars (p, val, 5);
8132 return;
8133 }
8134
d022bddd
IT		 8135 /* Some processors fail on LOCK prefix. This options makes
8136 assembler ignore LOCK prefix and serves as a workaround. */
8137 if (omit_lock_prefix)
8138 {
8139 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
8140 return;
8141 i.prefix[LOCK_PREFIX] = 0;
8142 }
8143
43234a1e
L		 8144 /* Since the VEX/EVEX prefix contains the implicit prefix, we
8145 don't need the explicit prefix. */
8146 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
bc4bd9ab 8147 {
c0f3af97 8148 switch (i.tm.opcode_length)
bc4bd9ab 8149 {
c0f3af97
L		 8150 case 3:
8151 if (i.tm.base_opcode & 0xff000000)
4dffcebc 8152 {
c0f3af97 8153 prefix = (i.tm.base_opcode >> 24) & 0xff;
bd59a631 8154 add_prefix (prefix);
c0f3af97
L		 8155 }
8156 break;
8157 case 2:
8158 if ((i.tm.base_opcode & 0xff0000) != 0)
8159 {
8160 prefix = (i.tm.base_opcode >> 16) & 0xff;
bd59a631
JB		 8161 if (!i.tm.cpu_flags.bitfield.cpupadlock
8162 || prefix != REPE_PREFIX_OPCODE
8163 || (i.prefix[REP_PREFIX] != REPE_PREFIX_OPCODE))
4dffcebc
L		 8164 add_prefix (prefix);
8165 }
c0f3af97
L		 8166 break;
8167 case 1:
8168 break;
390c91cf
L		 8169 case 0:
8170 /* Check for pseudo prefixes. */
8171 as_bad_where (insn_start_frag->fr_file,
8172 insn_start_frag->fr_line,
8173 _("pseudo prefix without instruction"));
8174 return;
c0f3af97
L		 8175 default:
8176 abort ();
bc4bd9ab 8177 }
c0f3af97 8178
6d19a37a 8179#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
cf61b747
L		 8180 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
8181 R_X86_64_GOTTPOFF relocation so that linker can safely
8182 perform IE->LE optimization. */
8183 if (x86_elf_abi == X86_64_X32_ABI
8184 && i.operands == 2
8185 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
8186 && i.prefix[REX_PREFIX] == 0)
8187 add_prefix (REX_OPCODE);
6d19a37a 8188#endif
cf61b747 8189
c0f3af97
L		 8190 /* The prefix bytes. */
8191 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
8192 if (*q)
8193 FRAG_APPEND_1_CHAR (*q);
0f10071e 8194 }
ae5c1c7b 8195 else
c0f3af97
L		 8196 {
8197 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
8198 if (*q)
8199 switch (j)
8200 {
8201 case REX_PREFIX:
8202 /* REX byte is encoded in VEX prefix. */
8203 break;
8204 case SEG_PREFIX:
8205 case ADDR_PREFIX:
8206 FRAG_APPEND_1_CHAR (*q);
8207 break;
8208 default:
8209 /* There should be no other prefixes for instructions
8210 with VEX prefix. */
8211 abort ();
8212 }
8213
43234a1e
L		 8214 /* For EVEX instructions i.vrex should become 0 after
8215 build_evex_prefix. For VEX instructions upper 16 registers
8216 aren't available, so VREX should be 0. */
8217 if (i.vrex)
8218 abort ();
c0f3af97
L		 8219 /* Now the VEX prefix. */
8220 p = frag_more (i.vex.length);
8221 for (j = 0; j < i.vex.length; j++)
8222 p[j] = i.vex.bytes[j];
8223 }
252b5132 8224
29b0f896 8225 /* Now the opcode; be careful about word order here! */
4dffcebc 8226 if (i.tm.opcode_length == 1)
29b0f896
AM		 8227 {
8228 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
8229 }
8230 else
8231 {
4dffcebc 8232 switch (i.tm.opcode_length)
331d2d0d 8233 {
43234a1e
L		 8234 case 4:
8235 p = frag_more (4);
8236 *p++ = (i.tm.base_opcode >> 24) & 0xff;
8237 *p++ = (i.tm.base_opcode >> 16) & 0xff;
8238 break;
4dffcebc 8239 case 3:
331d2d0d
L		 8240 p = frag_more (3);
8241 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 8242 break;
8243 case 2:
8244 p = frag_more (2);
8245 break;
8246 default:
8247 abort ();
8248 break;
331d2d0d 8249 }
0f10071e 8250
29b0f896
AM		 8251 /* Put out high byte first: can't use md_number_to_chars! */
8252 *p++ = (i.tm.base_opcode >> 8) & 0xff;
8253 *p = i.tm.base_opcode & 0xff;
8254 }
3e73aa7c 8255
29b0f896 8256 /* Now the modrm byte and sib byte (if present). */
40fb9820 8257 if (i.tm.opcode_modifier.modrm)
29b0f896 8258 {
4a3523fa
L		 8259 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
8260 | i.rm.reg << 3
8261 | i.rm.mode << 6));
29b0f896
AM		 8262 /* If i.rm.regmem == ESP (4)
8263 && i.rm.mode != (Register mode)
8264 && not 16 bit
8265 ==> need second modrm byte. */
8266 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
8267 && i.rm.mode != 3
dc821c5f 8268 && !(i.base_reg && i.base_reg->reg_type.bitfield.word))
4a3523fa
L		 8269 FRAG_APPEND_1_CHAR ((i.sib.base << 0
8270 | i.sib.index << 3
8271 | i.sib.scale << 6));
29b0f896 8272 }
3e73aa7c 8273
29b0f896 8274 if (i.disp_operands)
2bbd9c25 8275 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 8276
29b0f896 8277 if (i.imm_operands)
2bbd9c25 8278 output_imm (insn_start_frag, insn_start_off);
29b0f896 8279 }
252b5132 8280
29b0f896
AM		 8281#ifdef DEBUG386
8282 if (flag_debug)
8283 {
7b81dfbb 8284 pi ("" /*line*/, &i);
29b0f896
AM		 8285 }
8286#endif /* DEBUG386 */
8287}
252b5132 8288
e205caa7
L		 8289/* Return the size of the displacement operand N. */
8290
8291static int
8292disp_size (unsigned int n)
8293{
8294 int size = 4;
43234a1e 8295
b5014f7a 8296 if (i.types[n].bitfield.disp64)
40fb9820
L		 8297 size = 8;
8298 else if (i.types[n].bitfield.disp8)
8299 size = 1;
8300 else if (i.types[n].bitfield.disp16)
8301 size = 2;
e205caa7
L		 8302 return size;
8303}
8304
8305/* Return the size of the immediate operand N. */
8306
8307static int
8308imm_size (unsigned int n)
8309{
8310 int size = 4;
40fb9820
L		 8311 if (i.types[n].bitfield.imm64)
8312 size = 8;
8313 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
8314 size = 1;
8315 else if (i.types[n].bitfield.imm16)
8316 size = 2;
e205caa7
L		 8317 return size;
8318}
8319
29b0f896 8320static void
64e74474 8321output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 8322{
8323 char *p;
8324 unsigned int n;
252b5132 8325
29b0f896
AM		 8326 for (n = 0; n < i.operands; n++)
8327 {
b5014f7a 8328 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 8329 {
8330 if (i.op[n].disps->X_op == O_constant)
8331 {
e205caa7 8332 int size = disp_size (n);
43234a1e 8333 offsetT val = i.op[n].disps->X_add_number;
252b5132 8334
629cfaf1
JB		 8335 val = offset_in_range (val >> (size == 1 ? i.memshift : 0),
8336 size);
29b0f896
AM		 8337 p = frag_more (size);
8338 md_number_to_chars (p, val, size);
8339 }
8340 else
8341 {
f86103b7 8342 enum bfd_reloc_code_real reloc_type;
e205caa7 8343 int size = disp_size (n);
40fb9820 8344 int sign = i.types[n].bitfield.disp32s;
29b0f896 8345 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
02a86693 8346 fixS *fixP;
29b0f896 8347
e205caa7 8348 /* We can't have 8 bit displacement here. */
9c2799c2 8349 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 8350
29b0f896
AM		 8351 /* The PC relative address is computed relative
8352 to the instruction boundary, so in case immediate
8353 fields follows, we need to adjust the value. */
8354 if (pcrel && i.imm_operands)
8355 {
29b0f896 8356 unsigned int n1;
e205caa7 8357 int sz = 0;
252b5132 8358
29b0f896 8359 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 8360 if (operand_type_check (i.types[n1], imm))
252b5132 8361 {
e205caa7
L		 8362 /* Only one immediate is allowed for PC
8363 relative address. */
9c2799c2 8364 gas_assert (sz == 0);
e205caa7
L		 8365 sz = imm_size (n1);
8366 i.op[n].disps->X_add_number -= sz;
252b5132 8367 }
29b0f896 8368 /* We should find the immediate. */
9c2799c2 8369 gas_assert (sz != 0);
29b0f896 8370 }
520dc8e8 8371
29b0f896 8372 p = frag_more (size);
d258b828 8373 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 8374 if (GOT_symbol
2bbd9c25 8375 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 8376 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 8377 || reloc_type == BFD_RELOC_X86_64_32S
8378 || (reloc_type == BFD_RELOC_64
8379 && object_64bit))
d6ab8113
JB		 8380 && (i.op[n].disps->X_op == O_symbol
8381 || (i.op[n].disps->X_op == O_add
8382 && ((symbol_get_value_expression
8383 (i.op[n].disps->X_op_symbol)->X_op)
8384 == O_subtract))))
8385 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 8386 {
8387 offsetT add;
8388
8389 if (insn_start_frag == frag_now)
8390 add = (p - frag_now->fr_literal) - insn_start_off;
8391 else
8392 {
8393 fragS *fr;
8394
8395 add = insn_start_frag->fr_fix - insn_start_off;
8396 for (fr = insn_start_frag->fr_next;
8397 fr && fr != frag_now; fr = fr->fr_next)
8398 add += fr->fr_fix;
8399 add += p - frag_now->fr_literal;
8400 }
8401
4fa24527 8402 if (!object_64bit)
7b81dfbb
AJ		 8403 {
8404 reloc_type = BFD_RELOC_386_GOTPC;
8405 i.op[n].imms->X_add_number += add;
8406 }
8407 else if (reloc_type == BFD_RELOC_64)
8408 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 8409 else
7b81dfbb
AJ		 8410 /* Don't do the adjustment for x86-64, as there
8411 the pcrel addressing is relative to the _next_
8412 insn, and that is taken care of in other code. */
d6ab8113 8413 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 8414 }
02a86693
L		 8415 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
8416 size, i.op[n].disps, pcrel,
8417 reloc_type);
8418 /* Check for "call/jmp *mem", "mov mem, %reg",
8419 "test %reg, mem" and "binop mem, %reg" where binop
8420 is one of adc, add, and, cmp, or, sbb, sub, xor
e60f4d3b
L		 8421 instructions without data prefix. Always generate
8422 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
8423 if (i.prefix[DATA_PREFIX] == 0
8424 && (generate_relax_relocations
8425 || (!object_64bit
8426 && i.rm.mode == 0
8427 && i.rm.regmem == 5))
0cb4071e
L		 8428 && (i.rm.mode == 2
8429 || (i.rm.mode == 0 && i.rm.regmem == 5))
02a86693
L		 8430 && ((i.operands == 1
8431 && i.tm.base_opcode == 0xff
8432 && (i.rm.reg == 2 || i.rm.reg == 4))
8433 || (i.operands == 2
8434 && (i.tm.base_opcode == 0x8b
8435 || i.tm.base_opcode == 0x85
8436 || (i.tm.base_opcode & 0xc7) == 0x03))))
8437 {
8438 if (object_64bit)
8439 {
8440 fixP->fx_tcbit = i.rex != 0;
8441 if (i.base_reg
e968fc9b 8442 && (i.base_reg->reg_num == RegIP))
02a86693
L		 8443 fixP->fx_tcbit2 = 1;
8444 }
8445 else
8446 fixP->fx_tcbit2 = 1;
8447 }
29b0f896
AM		 8448 }
8449 }
8450 }
8451}
252b5132 8452
29b0f896 8453static void
64e74474 8454output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 8455{
8456 char *p;
8457 unsigned int n;
252b5132 8458
29b0f896
AM		 8459 for (n = 0; n < i.operands; n++)
8460 {
43234a1e
L		 8461 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
8462 if (i.rounding && (int) n == i.rounding->operand)
8463 continue;
8464
40fb9820 8465 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 8466 {
8467 if (i.op[n].imms->X_op == O_constant)
8468 {
e205caa7 8469 int size = imm_size (n);
29b0f896 8470 offsetT val;
b4cac588 8471
29b0f896
AM		 8472 val = offset_in_range (i.op[n].imms->X_add_number,
8473 size);
8474 p = frag_more (size);
8475 md_number_to_chars (p, val, size);
8476 }
8477 else
8478 {
8479 /* Not absolute_section.
8480 Need a 32-bit fixup (don't support 8bit
8481 non-absolute imms). Try to support other
8482 sizes ... */
f86103b7 8483 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 8484 int size = imm_size (n);
8485 int sign;
29b0f896 8486
40fb9820 8487 if (i.types[n].bitfield.imm32s
a7d61044 8488 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 8489 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 8490 sign = 1;
e205caa7
L		 8491 else
8492 sign = 0;
520dc8e8 8493
29b0f896 8494 p = frag_more (size);
d258b828 8495 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 8496
2bbd9c25
JJ		 8497 /* This is tough to explain. We end up with this one if we
8498 * have operands that look like
8499 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
8500 * obtain the absolute address of the GOT, and it is strongly
8501 * preferable from a performance point of view to avoid using
8502 * a runtime relocation for this. The actual sequence of
8503 * instructions often look something like:
8504 *
8505 * call .L66
8506 * .L66:
8507 * popl %ebx
8508 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
8509 *
8510 * The call and pop essentially return the absolute address
8511 * of the label .L66 and store it in %ebx. The linker itself
8512 * will ultimately change the first operand of the addl so
8513 * that %ebx points to the GOT, but to keep things simple, the
8514 * .o file must have this operand set so that it generates not
8515 * the absolute address of .L66, but the absolute address of
8516 * itself. This allows the linker itself simply treat a GOTPC
8517 * relocation as asking for a pcrel offset to the GOT to be
8518 * added in, and the addend of the relocation is stored in the
8519 * operand field for the instruction itself.
8520 *
8521 * Our job here is to fix the operand so that it would add
8522 * the correct offset so that %ebx would point to itself. The
8523 * thing that is tricky is that .-.L66 will point to the
8524 * beginning of the instruction, so we need to further modify
8525 * the operand so that it will point to itself. There are
8526 * other cases where you have something like:
8527 *
8528 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
8529 *
8530 * and here no correction would be required. Internally in
8531 * the assembler we treat operands of this form as not being
8532 * pcrel since the '.' is explicitly mentioned, and I wonder
8533 * whether it would simplify matters to do it this way. Who
8534 * knows. In earlier versions of the PIC patches, the
8535 * pcrel_adjust field was used to store the correction, but
8536 * since the expression is not pcrel, I felt it would be
8537 * confusing to do it this way. */
8538
d6ab8113 8539 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 8540 || reloc_type == BFD_RELOC_X86_64_32S
8541 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 8542 && GOT_symbol
8543 && GOT_symbol == i.op[n].imms->X_add_symbol
8544 && (i.op[n].imms->X_op == O_symbol
8545 || (i.op[n].imms->X_op == O_add
8546 && ((symbol_get_value_expression
8547 (i.op[n].imms->X_op_symbol)->X_op)
8548 == O_subtract))))
8549 {
2bbd9c25
JJ		 8550 offsetT add;
8551
8552 if (insn_start_frag == frag_now)
8553 add = (p - frag_now->fr_literal) - insn_start_off;
8554 else
8555 {
8556 fragS *fr;
8557
8558 add = insn_start_frag->fr_fix - insn_start_off;
8559 for (fr = insn_start_frag->fr_next;
8560 fr && fr != frag_now; fr = fr->fr_next)
8561 add += fr->fr_fix;
8562 add += p - frag_now->fr_literal;
8563 }
8564
4fa24527 8565 if (!object_64bit)
d6ab8113 8566 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 8567 else if (size == 4)
d6ab8113 8568 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 8569 else if (size == 8)
8570 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 8571 i.op[n].imms->X_add_number += add;
29b0f896 8572 }
29b0f896
AM		 8573 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
8574 i.op[n].imms, 0, reloc_type);
8575 }
8576 }
8577 }
252b5132
RH		 8578}
8579\f
d182319b
JB		 8580/* x86_cons_fix_new is called via the expression parsing code when a
8581 reloc is needed. We use this hook to get the correct .got reloc. */
d182319b
JB		 8582static int cons_sign = -1;
8583
8584void
e3bb37b5 8585x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
62ebcb5c 8586 expressionS *exp, bfd_reloc_code_real_type r)
d182319b 8587{
d258b828 8588 r = reloc (len, 0, cons_sign, r);
d182319b
JB		 8589
8590#ifdef TE_PE
8591 if (exp->X_op == O_secrel)
8592 {
8593 exp->X_op = O_symbol;
8594 r = BFD_RELOC_32_SECREL;
8595 }
8596#endif
8597
8598 fix_new_exp (frag, off, len, exp, 0, r);
8599}
8600
357d1bd8
L		 8601/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8602 purpose of the `.dc.a' internal pseudo-op. */
8603
8604int
8605x86_address_bytes (void)
8606{
8607 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
8608 return 4;
8609 return stdoutput->arch_info->bits_per_address / 8;
8610}
8611
d382c579
TG		 8612#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8613 || defined (LEX_AT)
d258b828 8614# define lex_got(reloc, adjust, types) NULL
718ddfc0 8615#else
f3c180ae
AM		 8616/* Parse operands of the form
8617 <symbol>@GOTOFF+<nnn>
8618 and similar .plt or .got references.
8619
8620 If we find one, set up the correct relocation in RELOC and copy the
8621 input string, minus the `@GOTOFF' into a malloc'd buffer for
8622 parsing by the calling routine. Return this buffer, and if ADJUST
8623 is non-null set it to the length of the string we removed from the
8624 input line. Otherwise return NULL. */
8625static char *
91d6fa6a 8626lex_got (enum bfd_reloc_code_real *rel,
64e74474 8627 int *adjust,
d258b828 8628 i386_operand_type *types)
f3c180ae 8629{
7b81dfbb
AJ		 8630 /* Some of the relocations depend on the size of what field is to
8631 be relocated. But in our callers i386_immediate and i386_displacement
8632 we don't yet know the operand size (this will be set by insn
8633 matching). Hence we record the word32 relocation here,
8634 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 8635 static const struct {
8636 const char *str;
cff8d58a 8637 int len;
4fa24527 8638 const enum bfd_reloc_code_real rel[2];
40fb9820 8639 const i386_operand_type types64;
f3c180ae 8640 } gotrel[] = {
8ce3d284 8641#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 8642 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
8643 BFD_RELOC_SIZE32 },
8644 OPERAND_TYPE_IMM32_64 },
8ce3d284 8645#endif
cff8d58a
L		 8646 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
8647 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 8648 OPERAND_TYPE_IMM64 },
cff8d58a
L		 8649 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
8650 BFD_RELOC_X86_64_PLT32 },
40fb9820 8651 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8652 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
8653 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 8654 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 8655 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
8656 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 8657 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 8658 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
8659 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 8660 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8661 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
8662 BFD_RELOC_X86_64_TLSGD },
40fb9820 8663 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8664 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
8665 _dummy_first_bfd_reloc_code_real },
40fb9820 8666 OPERAND_TYPE_NONE },
cff8d58a
L		 8667 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
8668 BFD_RELOC_X86_64_TLSLD },
40fb9820 8669 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8670 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
8671 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 8672 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8673 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
8674 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 8675 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 8676 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
8677 _dummy_first_bfd_reloc_code_real },
40fb9820 8678 OPERAND_TYPE_NONE },
cff8d58a
L		 8679 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
8680 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 8681 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 8682 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
8683 _dummy_first_bfd_reloc_code_real },
40fb9820 8684 OPERAND_TYPE_NONE },
cff8d58a
L		 8685 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
8686 _dummy_first_bfd_reloc_code_real },
40fb9820 8687 OPERAND_TYPE_NONE },
cff8d58a
L		 8688 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
8689 BFD_RELOC_X86_64_GOT32 },
40fb9820 8690 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 8691 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
8692 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 8693 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8694 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
8695 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 8696 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 8697 };
8698 char *cp;
8699 unsigned int j;
8700
d382c579 8701#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 8702 if (!IS_ELF)
8703 return NULL;
d382c579 8704#endif
718ddfc0 8705
f3c180ae 8706 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 8707 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 8708 return NULL;
8709
47465058 8710 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 8711 {
cff8d58a 8712 int len = gotrel[j].len;
28f81592 8713 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 8714 {
4fa24527 8715 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 8716 {
28f81592
AM		 8717 int first, second;
8718 char *tmpbuf, *past_reloc;
f3c180ae 8719
91d6fa6a 8720 *rel = gotrel[j].rel[object_64bit];
f3c180ae 8721
3956db08
JB		 8722 if (types)
8723 {
8724 if (flag_code != CODE_64BIT)
40fb9820
L		 8725 {
8726 types->bitfield.imm32 = 1;
8727 types->bitfield.disp32 = 1;
8728 }
3956db08
JB		 8729 else
8730 *types = gotrel[j].types64;
8731 }
8732
8fd4256d 8733 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 8734 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
8735
28f81592 8736 /* The length of the first part of our input line. */
f3c180ae 8737 first = cp - input_line_pointer;
28f81592
AM		 8738
8739 /* The second part goes from after the reloc token until
67c11a9b 8740 (and including) an end_of_line char or comma. */
28f81592 8741 past_reloc = cp + 1 + len;
67c11a9b
AM		 8742 cp = past_reloc;
8743 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8744 ++cp;
8745 second = cp + 1 - past_reloc;
28f81592
AM		 8746
8747 /* Allocate and copy string. The trailing NUL shouldn't
8748 be necessary, but be safe. */
add39d23 8749 tmpbuf = XNEWVEC (char, first + second + 2);
f3c180ae 8750 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 8751 if (second != 0 && *past_reloc != ' ')
8752 /* Replace the relocation token with ' ', so that
8753 errors like foo@GOTOFF1 will be detected. */
8754 tmpbuf[first++] = ' ';
af89796a
L		 8755 else
8756 /* Increment length by 1 if the relocation token is
8757 removed. */
8758 len++;
8759 if (adjust)
8760 *adjust = len;
0787a12d
AM		 8761 memcpy (tmpbuf + first, past_reloc, second);
8762 tmpbuf[first + second] = '\0';
f3c180ae
AM		 8763 return tmpbuf;
8764 }
8765
4fa24527
JB		 8766 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8767 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 8768 return NULL;
8769 }
8770 }
8771
8772 /* Might be a symbol version string. Don't as_bad here. */
8773 return NULL;
8774}
4e4f7c87 8775#endif
f3c180ae 8776
a988325c
NC		 8777#ifdef TE_PE
8778#ifdef lex_got
8779#undef lex_got
8780#endif
8781/* Parse operands of the form
8782 <symbol>@SECREL32+<nnn>
8783
8784 If we find one, set up the correct relocation in RELOC and copy the
8785 input string, minus the `@SECREL32' into a malloc'd buffer for
8786 parsing by the calling routine. Return this buffer, and if ADJUST
8787 is non-null set it to the length of the string we removed from the
34bca508
L		 8788 input line. Otherwise return NULL.
8789
a988325c
NC		 8790 This function is copied from the ELF version above adjusted for PE targets. */
8791
8792static char *
8793lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
8794 int *adjust ATTRIBUTE_UNUSED,
d258b828 8795 i386_operand_type *types)
a988325c
NC		 8796{
8797 static const struct
8798 {
8799 const char *str;
8800 int len;
8801 const enum bfd_reloc_code_real rel[2];
8802 const i386_operand_type types64;
8803 }
8804 gotrel[] =
8805 {
8806 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
8807 BFD_RELOC_32_SECREL },
8808 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8809 };
8810
8811 char *cp;
8812 unsigned j;
8813
8814 for (cp = input_line_pointer; *cp != '@'; cp++)
8815 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8816 return NULL;
8817
8818 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8819 {
8820 int len = gotrel[j].len;
8821
8822 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8823 {
8824 if (gotrel[j].rel[object_64bit] != 0)
8825 {
8826 int first, second;
8827 char *tmpbuf, *past_reloc;
8828
8829 *rel = gotrel[j].rel[object_64bit];
8830 if (adjust)
8831 *adjust = len;
8832
8833 if (types)
8834 {
8835 if (flag_code != CODE_64BIT)
8836 {
8837 types->bitfield.imm32 = 1;
8838 types->bitfield.disp32 = 1;
8839 }
8840 else
8841 *types = gotrel[j].types64;
8842 }
8843
8844 /* The length of the first part of our input line. */
8845 first = cp - input_line_pointer;
8846
8847 /* The second part goes from after the reloc token until
8848 (and including) an end_of_line char or comma. */
8849 past_reloc = cp + 1 + len;
8850 cp = past_reloc;
8851 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8852 ++cp;
8853 second = cp + 1 - past_reloc;
8854
8855 /* Allocate and copy string. The trailing NUL shouldn't
8856 be necessary, but be safe. */
add39d23 8857 tmpbuf = XNEWVEC (char, first + second + 2);
a988325c
NC		 8858 memcpy (tmpbuf, input_line_pointer, first);
8859 if (second != 0 && *past_reloc != ' ')
8860 /* Replace the relocation token with ' ', so that
8861 errors like foo@SECLREL321 will be detected. */
8862 tmpbuf[first++] = ' ';
8863 memcpy (tmpbuf + first, past_reloc, second);
8864 tmpbuf[first + second] = '\0';
8865 return tmpbuf;
8866 }
8867
8868 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8869 gotrel[j].str, 1 << (5 + object_64bit));
8870 return NULL;
8871 }
8872 }
8873
8874 /* Might be a symbol version string. Don't as_bad here. */
8875 return NULL;
8876}
8877
8878#endif /* TE_PE */
8879
62ebcb5c 8880bfd_reloc_code_real_type
e3bb37b5 8881x86_cons (expressionS *exp, int size)
f3c180ae 8882{
62ebcb5c
AM		 8883 bfd_reloc_code_real_type got_reloc = NO_RELOC;
8884
ee86248c
JB		 8885 intel_syntax = -intel_syntax;
8886
3c7b9c2c 8887 exp->X_md = 0;
4fa24527 8888 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 8889 {
8890 /* Handle @GOTOFF and the like in an expression. */
8891 char *save;
8892 char *gotfree_input_line;
4a57f2cf 8893 int adjust = 0;
f3c180ae
AM		 8894
8895 save = input_line_pointer;
d258b828 8896 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 8897 if (gotfree_input_line)
8898 input_line_pointer = gotfree_input_line;
8899
8900 expression (exp);
8901
8902 if (gotfree_input_line)
8903 {
8904 /* expression () has merrily parsed up to the end of line,
8905 or a comma - in the wrong buffer. Transfer how far
8906 input_line_pointer has moved to the right buffer. */
8907 input_line_pointer = (save
8908 + (input_line_pointer - gotfree_input_line)
8909 + adjust);
8910 free (gotfree_input_line);
3992d3b7
AM		 8911 if (exp->X_op == O_constant
8912 || exp->X_op == O_absent
8913 || exp->X_op == O_illegal
0398aac5 8914 || exp->X_op == O_register
3992d3b7
AM		 8915 || exp->X_op == O_big)
8916 {
8917 char c = *input_line_pointer;
8918 *input_line_pointer = 0;
8919 as_bad (_("missing or invalid expression `%s'"), save);
8920 *input_line_pointer = c;
8921 }
f3c180ae
AM		 8922 }
8923 }
8924 else
8925 expression (exp);
ee86248c
JB		 8926
8927 intel_syntax = -intel_syntax;
8928
8929 if (intel_syntax)
8930 i386_intel_simplify (exp);
62ebcb5c
AM		 8931
8932 return got_reloc;
f3c180ae 8933}
f3c180ae 8934
9f32dd5b
L		 8935static void
8936signed_cons (int size)
6482c264 8937{
d182319b
JB		 8938 if (flag_code == CODE_64BIT)
8939 cons_sign = 1;
8940 cons (size);
8941 cons_sign = -1;
6482c264
NC		 8942}
8943
d182319b 8944#ifdef TE_PE
6482c264 8945static void
7016a5d5 8946pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 8947{
8948 expressionS exp;
8949
8950 do
8951 {
8952 expression (&exp);
8953 if (exp.X_op == O_symbol)
8954 exp.X_op = O_secrel;
8955
8956 emit_expr (&exp, 4);
8957 }
8958 while (*input_line_pointer++ == ',');
8959
8960 input_line_pointer--;
8961 demand_empty_rest_of_line ();
8962}
6482c264
NC		 8963#endif
8964
43234a1e
L		 8965/* Handle Vector operations. */
8966
8967static char *
8968check_VecOperations (char *op_string, char *op_end)
8969{
8970 const reg_entry *mask;
8971 const char *saved;
8972 char *end_op;
8973
8974 while (*op_string
8975 && (op_end == NULL || op_string < op_end))
8976 {
8977 saved = op_string;
8978 if (*op_string == '{')
8979 {
8980 op_string++;
8981
8982 /* Check broadcasts. */
8983 if (strncmp (op_string, "1to", 3) == 0)
8984 {
8985 int bcst_type;
8986
8987 if (i.broadcast)
8988 goto duplicated_vec_op;
8989
8990 op_string += 3;
8991 if (*op_string == '8')
8e6e0792 8992 bcst_type = 8;
b28d1bda 8993 else if (*op_string == '4')
8e6e0792 8994 bcst_type = 4;
b28d1bda 8995 else if (*op_string == '2')
8e6e0792 8996 bcst_type = 2;
43234a1e
L		 8997 else if (*op_string == '1'
8998 && *(op_string+1) == '6')
8999 {
8e6e0792 9000 bcst_type = 16;
43234a1e
L		 9001 op_string++;
9002 }
9003 else
9004 {
9005 as_bad (_("Unsupported broadcast: `%s'"), saved);
9006 return NULL;
9007 }
9008 op_string++;
9009
9010 broadcast_op.type = bcst_type;
9011 broadcast_op.operand = this_operand;
1f75763a 9012 broadcast_op.bytes = 0;
43234a1e
L		 9013 i.broadcast = &broadcast_op;
9014 }
9015 /* Check masking operation. */
9016 else if ((mask = parse_register (op_string, &end_op)) != NULL)
9017 {
9018 /* k0 can't be used for write mask. */
6d2cd6b2 9019 if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0)
43234a1e 9020 {
6d2cd6b2
JB		 9021 as_bad (_("`%s%s' can't be used for write mask"),
9022 register_prefix, mask->reg_name);
43234a1e
L		 9023 return NULL;
9024 }
9025
9026 if (!i.mask)
9027 {
9028 mask_op.mask = mask;
9029 mask_op.zeroing = 0;
9030 mask_op.operand = this_operand;
9031 i.mask = &mask_op;
9032 }
9033 else
9034 {
9035 if (i.mask->mask)
9036 goto duplicated_vec_op;
9037
9038 i.mask->mask = mask;
9039
9040 /* Only "{z}" is allowed here. No need to check
9041 zeroing mask explicitly. */
9042 if (i.mask->operand != this_operand)
9043 {
9044 as_bad (_("invalid write mask `%s'"), saved);
9045 return NULL;
9046 }
9047 }
9048
9049 op_string = end_op;
9050 }
9051 /* Check zeroing-flag for masking operation. */
9052 else if (*op_string == 'z')
9053 {
9054 if (!i.mask)
9055 {
9056 mask_op.mask = NULL;
9057 mask_op.zeroing = 1;
9058 mask_op.operand = this_operand;
9059 i.mask = &mask_op;
9060 }
9061 else
9062 {
9063 if (i.mask->zeroing)
9064 {
9065 duplicated_vec_op:
9066 as_bad (_("duplicated `%s'"), saved);
9067 return NULL;
9068 }
9069
9070 i.mask->zeroing = 1;
9071
9072 /* Only "{%k}" is allowed here. No need to check mask
9073 register explicitly. */
9074 if (i.mask->operand != this_operand)
9075 {
9076 as_bad (_("invalid zeroing-masking `%s'"),
9077 saved);
9078 return NULL;
9079 }
9080 }
9081
9082 op_string++;
9083 }
9084 else
9085 goto unknown_vec_op;
9086
9087 if (*op_string != '}')
9088 {
9089 as_bad (_("missing `}' in `%s'"), saved);
9090 return NULL;
9091 }
9092 op_string++;
0ba3a731
L		 9093
9094 /* Strip whitespace since the addition of pseudo prefixes
9095 changed how the scrubber treats '{'. */
9096 if (is_space_char (*op_string))
9097 ++op_string;
9098
43234a1e
L		 9099 continue;
9100 }
9101 unknown_vec_op:
9102 /* We don't know this one. */
9103 as_bad (_("unknown vector operation: `%s'"), saved);
9104 return NULL;
9105 }
9106
6d2cd6b2
JB		 9107 if (i.mask && i.mask->zeroing && !i.mask->mask)
9108 {
9109 as_bad (_("zeroing-masking only allowed with write mask"));
9110 return NULL;
9111 }
9112
43234a1e
L		 9113 return op_string;
9114}
9115
252b5132 9116static int
70e41ade 9117i386_immediate (char *imm_start)
252b5132
RH		 9118{
9119 char *save_input_line_pointer;
f3c180ae 9120 char *gotfree_input_line;
252b5132 9121 segT exp_seg = 0;
47926f60 9122 expressionS *exp;
40fb9820
L		 9123 i386_operand_type types;
9124
0dfbf9d7 9125 operand_type_set (&types, ~0);
252b5132
RH		 9126
9127 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
9128 {
31b2323c
L		 9129 as_bad (_("at most %d immediate operands are allowed"),
9130 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 9131 return 0;
9132 }
9133
9134 exp = &im_expressions[i.imm_operands++];
520dc8e8 9135 i.op[this_operand].imms = exp;
252b5132
RH		 9136
9137 if (is_space_char (*imm_start))
9138 ++imm_start;
9139
9140 save_input_line_pointer = input_line_pointer;
9141 input_line_pointer = imm_start;
9142
d258b828 9143 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 9144 if (gotfree_input_line)
9145 input_line_pointer = gotfree_input_line;
252b5132
RH		 9146
9147 exp_seg = expression (exp);
9148
83183c0c 9149 SKIP_WHITESPACE ();
43234a1e
L		 9150
9151 /* Handle vector operations. */
9152 if (*input_line_pointer == '{')
9153 {
9154 input_line_pointer = check_VecOperations (input_line_pointer,
9155 NULL);
9156 if (input_line_pointer == NULL)
9157 return 0;
9158 }
9159
252b5132 9160 if (*input_line_pointer)
f3c180ae 9161 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 9162
9163 input_line_pointer = save_input_line_pointer;
f3c180ae 9164 if (gotfree_input_line)
ee86248c
JB		 9165 {
9166 free (gotfree_input_line);
9167
9168 if (exp->X_op == O_constant || exp->X_op == O_register)
9169 exp->X_op = O_illegal;
9170 }
9171
9172 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
9173}
252b5132 9174
ee86248c
JB		 9175static int
9176i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
9177 i386_operand_type types, const char *imm_start)
9178{
9179 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 9180 {
313c53d1
L		 9181 if (imm_start)
9182 as_bad (_("missing or invalid immediate expression `%s'"),
9183 imm_start);
3992d3b7 9184 return 0;
252b5132 9185 }
3e73aa7c 9186 else if (exp->X_op == O_constant)
252b5132 9187 {
47926f60 9188 /* Size it properly later. */
40fb9820 9189 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 9190 /* If not 64bit, sign extend val. */
9191 if (flag_code != CODE_64BIT
4eed87de
AM		 9192 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
9193 exp->X_add_number
9194 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 9195 }
4c63da97 9196#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 9197 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 9198 && exp_seg != absolute_section
47926f60 9199 && exp_seg != text_section
24eab124
AM		 9200 && exp_seg != data_section
9201 && exp_seg != bss_section
9202 && exp_seg != undefined_section
f86103b7 9203 && !bfd_is_com_section (exp_seg))
252b5132 9204 {
d0b47220 9205 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 9206 return 0;
9207 }
9208#endif
a841bdf5 9209 else if (!intel_syntax && exp_seg == reg_section)
bb8f5920 9210 {
313c53d1
L		 9211 if (imm_start)
9212 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 9213 return 0;
9214 }
252b5132
RH		 9215 else
9216 {
9217 /* This is an address. The size of the address will be
24eab124 9218 determined later, depending on destination register,
3e73aa7c 9219 suffix, or the default for the section. */
40fb9820
L		 9220 i.types[this_operand].bitfield.imm8 = 1;
9221 i.types[this_operand].bitfield.imm16 = 1;
9222 i.types[this_operand].bitfield.imm32 = 1;
9223 i.types[this_operand].bitfield.imm32s = 1;
9224 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 9225 i.types[this_operand] = operand_type_and (i.types[this_operand],
9226 types);
252b5132
RH		 9227 }
9228
9229 return 1;
9230}
9231
551c1ca1 9232static char *
e3bb37b5 9233i386_scale (char *scale)
252b5132 9234{
551c1ca1
AM		 9235 offsetT val;
9236 char *save = input_line_pointer;
252b5132 9237
551c1ca1
AM		 9238 input_line_pointer = scale;
9239 val = get_absolute_expression ();
9240
9241 switch (val)
252b5132 9242 {
551c1ca1 9243 case 1:
252b5132
RH		 9244 i.log2_scale_factor = 0;
9245 break;
551c1ca1 9246 case 2:
252b5132
RH		 9247 i.log2_scale_factor = 1;
9248 break;
551c1ca1 9249 case 4:
252b5132
RH		 9250 i.log2_scale_factor = 2;
9251 break;
551c1ca1 9252 case 8:
252b5132
RH		 9253 i.log2_scale_factor = 3;
9254 break;
9255 default:
a724f0f4
JB		 9256 {
9257 char sep = *input_line_pointer;
9258
9259 *input_line_pointer = '\0';
9260 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
9261 scale);
9262 *input_line_pointer = sep;
9263 input_line_pointer = save;
9264 return NULL;
9265 }
252b5132 9266 }
29b0f896 9267 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 9268 {
9269 as_warn (_("scale factor of %d without an index register"),
24eab124 9270 1 << i.log2_scale_factor);
252b5132 9271 i.log2_scale_factor = 0;
252b5132 9272 }
551c1ca1
AM		 9273 scale = input_line_pointer;
9274 input_line_pointer = save;
9275 return scale;
252b5132
RH		 9276}
9277
252b5132 9278static int
e3bb37b5 9279i386_displacement (char *disp_start, char *disp_end)
252b5132 9280{
29b0f896 9281 expressionS *exp;
252b5132
RH		 9282 segT exp_seg = 0;
9283 char *save_input_line_pointer;
f3c180ae 9284 char *gotfree_input_line;
40fb9820
L		 9285 int override;
9286 i386_operand_type bigdisp, types = anydisp;
3992d3b7 9287 int ret;
252b5132 9288
31b2323c
L		 9289 if (i.disp_operands == MAX_MEMORY_OPERANDS)
9290 {
9291 as_bad (_("at most %d displacement operands are allowed"),
9292 MAX_MEMORY_OPERANDS);
9293 return 0;
9294 }
9295
0dfbf9d7 9296 operand_type_set (&bigdisp, 0);
40fb9820
L		 9297 if ((i.types[this_operand].bitfield.jumpabsolute)
9298 || (!current_templates->start->opcode_modifier.jump
9299 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 9300 {
40fb9820 9301 bigdisp.bitfield.disp32 = 1;
e05278af 9302 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 9303 if (flag_code == CODE_64BIT)
9304 {
9305 if (!override)
9306 {
9307 bigdisp.bitfield.disp32s = 1;
9308 bigdisp.bitfield.disp64 = 1;
9309 }
9310 }
9311 else if ((flag_code == CODE_16BIT) ^ override)
9312 {
9313 bigdisp.bitfield.disp32 = 0;
9314 bigdisp.bitfield.disp16 = 1;
9315 }
e05278af
JB		 9316 }
9317 else
9318 {
9319 /* For PC-relative branches, the width of the displacement
9320 is dependent upon data size, not address size. */
e05278af 9321 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 9322 if (flag_code == CODE_64BIT)
9323 {
9324 if (override || i.suffix == WORD_MNEM_SUFFIX)
9325 bigdisp.bitfield.disp16 = 1;
9326 else
9327 {
9328 bigdisp.bitfield.disp32 = 1;
9329 bigdisp.bitfield.disp32s = 1;
9330 }
9331 }
9332 else
e05278af
JB		 9333 {
9334 if (!override)
9335 override = (i.suffix == (flag_code != CODE_16BIT
9336 ? WORD_MNEM_SUFFIX
9337 : LONG_MNEM_SUFFIX));
40fb9820
L		 9338 bigdisp.bitfield.disp32 = 1;
9339 if ((flag_code == CODE_16BIT) ^ override)
9340 {
9341 bigdisp.bitfield.disp32 = 0;
9342 bigdisp.bitfield.disp16 = 1;
9343 }
e05278af 9344 }
e05278af 9345 }
c6fb90c8
L		 9346 i.types[this_operand] = operand_type_or (i.types[this_operand],
9347 bigdisp);
252b5132
RH		 9348
9349 exp = &disp_expressions[i.disp_operands];
520dc8e8 9350 i.op[this_operand].disps = exp;
252b5132
RH		 9351 i.disp_operands++;
9352 save_input_line_pointer = input_line_pointer;
9353 input_line_pointer = disp_start;
9354 END_STRING_AND_SAVE (disp_end);
9355
9356#ifndef GCC_ASM_O_HACK
9357#define GCC_ASM_O_HACK 0
9358#endif
9359#if GCC_ASM_O_HACK
9360 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 9361 if (i.types[this_operand].bitfield.baseIndex
24eab124 9362 && displacement_string_end[-1] == '+')
252b5132
RH		 9363 {
9364 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 9365 constraint within gcc asm statements.
9366 For instance:
9367
9368 #define _set_tssldt_desc(n,addr,limit,type) \
9369 __asm__ __volatile__ ( \
9370 "movw %w2,%0\n\t" \
9371 "movw %w1,2+%0\n\t" \
9372 "rorl $16,%1\n\t" \
9373 "movb %b1,4+%0\n\t" \
9374 "movb %4,5+%0\n\t" \
9375 "movb $0,6+%0\n\t" \
9376 "movb %h1,7+%0\n\t" \
9377 "rorl $16,%1" \
9378 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
9379
9380 This works great except that the output assembler ends
9381 up looking a bit weird if it turns out that there is
9382 no offset. You end up producing code that looks like:
9383
9384 #APP
9385 movw $235,(%eax)
9386 movw %dx,2+(%eax)
9387 rorl $16,%edx
9388 movb %dl,4+(%eax)
9389 movb $137,5+(%eax)
9390 movb $0,6+(%eax)
9391 movb %dh,7+(%eax)
9392 rorl $16,%edx
9393 #NO_APP
9394
47926f60 9395 So here we provide the missing zero. */
24eab124
AM		 9396
9397 *displacement_string_end = '0';
252b5132
RH		 9398 }
9399#endif
d258b828 9400 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 9401 if (gotfree_input_line)
9402 input_line_pointer = gotfree_input_line;
252b5132 9403
24eab124 9404 exp_seg = expression (exp);
252b5132 9405
636c26b0
AM		 9406 SKIP_WHITESPACE ();
9407 if (*input_line_pointer)
9408 as_bad (_("junk `%s' after expression"), input_line_pointer);
9409#if GCC_ASM_O_HACK
9410 RESTORE_END_STRING (disp_end + 1);
9411#endif
636c26b0 9412 input_line_pointer = save_input_line_pointer;
636c26b0 9413 if (gotfree_input_line)
ee86248c
JB		 9414 {
9415 free (gotfree_input_line);
9416
9417 if (exp->X_op == O_constant || exp->X_op == O_register)
9418 exp->X_op = O_illegal;
9419 }
9420
9421 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
9422
9423 RESTORE_END_STRING (disp_end);
9424
9425 return ret;
9426}
9427
9428static int
9429i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
9430 i386_operand_type types, const char *disp_start)
9431{
9432 i386_operand_type bigdisp;
9433 int ret = 1;
636c26b0 9434
24eab124
AM		 9435 /* We do this to make sure that the section symbol is in
9436 the symbol table. We will ultimately change the relocation
47926f60 9437 to be relative to the beginning of the section. */
1ae12ab7 9438 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 9439 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
9440 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 9441 {
636c26b0 9442 if (exp->X_op != O_symbol)
3992d3b7 9443 goto inv_disp;
636c26b0 9444
e5cb08ac 9445 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 9446 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
9447 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 9448 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 9449 exp->X_op = O_subtract;
9450 exp->X_op_symbol = GOT_symbol;
1ae12ab7 9451 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 9452 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 9453 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
9454 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 9455 else
29b0f896 9456 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 9457 }
252b5132 9458
3992d3b7
AM		 9459 else if (exp->X_op == O_absent
9460 || exp->X_op == O_illegal
ee86248c 9461 || exp->X_op == O_big)
2daf4fd8 9462 {
3992d3b7
AM		 9463 inv_disp:
9464 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 9465 disp_start);
3992d3b7 9466 ret = 0;
2daf4fd8
AM		 9467 }
9468
0e1147d9
L		 9469 else if (flag_code == CODE_64BIT
9470 && !i.prefix[ADDR_PREFIX]
9471 && exp->X_op == O_constant)
9472 {
9473 /* Since displacement is signed extended to 64bit, don't allow
9474 disp32 and turn off disp32s if they are out of range. */
9475 i.types[this_operand].bitfield.disp32 = 0;
9476 if (!fits_in_signed_long (exp->X_add_number))
9477 {
9478 i.types[this_operand].bitfield.disp32s = 0;
9479 if (i.types[this_operand].bitfield.baseindex)
9480 {
9481 as_bad (_("0x%lx out range of signed 32bit displacement"),
9482 (long) exp->X_add_number);
9483 ret = 0;
9484 }
9485 }
9486 }
9487
4c63da97 9488#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 9489 else if (exp->X_op != O_constant
9490 && OUTPUT_FLAVOR == bfd_target_aout_flavour
9491 && exp_seg != absolute_section
9492 && exp_seg != text_section
9493 && exp_seg != data_section
9494 && exp_seg != bss_section
9495 && exp_seg != undefined_section
9496 && !bfd_is_com_section (exp_seg))
24eab124 9497 {
d0b47220 9498 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 9499 ret = 0;
24eab124 9500 }
252b5132 9501#endif
3956db08 9502
40fb9820
L		 9503 /* Check if this is a displacement only operand. */
9504 bigdisp = i.types[this_operand];
9505 bigdisp.bitfield.disp8 = 0;
9506 bigdisp.bitfield.disp16 = 0;
9507 bigdisp.bitfield.disp32 = 0;
9508 bigdisp.bitfield.disp32s = 0;
9509 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 9510 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 9511 i.types[this_operand] = operand_type_and (i.types[this_operand],
9512 types);
3956db08 9513
3992d3b7 9514 return ret;
252b5132
RH		 9515}
9516
2abc2bec
JB		 9517/* Return the active addressing mode, taking address override and
9518 registers forming the address into consideration. Update the
9519 address override prefix if necessary. */
47926f60 9520
2abc2bec
JB		 9521static enum flag_code
9522i386_addressing_mode (void)
252b5132 9523{
be05d201
L		 9524 enum flag_code addr_mode;
9525
9526 if (i.prefix[ADDR_PREFIX])
9527 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
9528 else
9529 {
9530 addr_mode = flag_code;
9531
24eab124 9532#if INFER_ADDR_PREFIX
be05d201
L		 9533 if (i.mem_operands == 0)
9534 {
9535 /* Infer address prefix from the first memory operand. */
9536 const reg_entry *addr_reg = i.base_reg;
9537
9538 if (addr_reg == NULL)
9539 addr_reg = i.index_reg;
eecb386c 9540
be05d201
L		 9541 if (addr_reg)
9542 {
e968fc9b 9543 if (addr_reg->reg_type.bitfield.dword)
be05d201
L		 9544 addr_mode = CODE_32BIT;
9545 else if (flag_code != CODE_64BIT
dc821c5f 9546 && addr_reg->reg_type.bitfield.word)
be05d201
L		 9547 addr_mode = CODE_16BIT;
9548
9549 if (addr_mode != flag_code)
9550 {
9551 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
9552 i.prefixes += 1;
9553 /* Change the size of any displacement too. At most one
9554 of Disp16 or Disp32 is set.
9555 FIXME. There doesn't seem to be any real need for
9556 separate Disp16 and Disp32 flags. The same goes for
9557 Imm16 and Imm32. Removing them would probably clean
9558 up the code quite a lot. */
9559 if (flag_code != CODE_64BIT
9560 && (i.types[this_operand].bitfield.disp16
9561 || i.types[this_operand].bitfield.disp32))
9562 i.types[this_operand]
9563 = operand_type_xor (i.types[this_operand], disp16_32);
9564 }
9565 }
9566 }
24eab124 9567#endif
be05d201
L		 9568 }
9569
2abc2bec
JB		 9570 return addr_mode;
9571}
9572
9573/* Make sure the memory operand we've been dealt is valid.
9574 Return 1 on success, 0 on a failure. */
9575
9576static int
9577i386_index_check (const char *operand_string)
9578{
9579 const char *kind = "base/index";
9580 enum flag_code addr_mode = i386_addressing_mode ();
9581
fc0763e6
JB		 9582 if (current_templates->start->opcode_modifier.isstring
9583 && !current_templates->start->opcode_modifier.immext
9584 && (current_templates->end[-1].opcode_modifier.isstring
9585 || i.mem_operands))
9586 {
9587 /* Memory operands of string insns are special in that they only allow
9588 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 9589 const reg_entry *expected_reg;
9590 static const char *di_si[][2] =
9591 {
9592 { "esi", "edi" },
9593 { "si", "di" },
9594 { "rsi", "rdi" }
9595 };
9596 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 9597
9598 kind = "string address";
9599
8325cc63 9600 if (current_templates->start->opcode_modifier.repprefixok)
fc0763e6
JB		 9601 {
9602 i386_operand_type type = current_templates->end[-1].operand_types[0];
9603
9604 if (!type.bitfield.baseindex
9605 || ((!i.mem_operands != !intel_syntax)
9606 && current_templates->end[-1].operand_types[1]
9607 .bitfield.baseindex))
9608 type = current_templates->end[-1].operand_types[1];
be05d201
L		 9609 expected_reg = hash_find (reg_hash,
9610 di_si[addr_mode][type.bitfield.esseg]);
9611
fc0763e6
JB		 9612 }
9613 else
be05d201 9614 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 9615
be05d201
L		 9616 if (i.base_reg != expected_reg
9617 || i.index_reg
fc0763e6 9618 || operand_type_check (i.types[this_operand], disp))
fc0763e6 9619 {
be05d201
L		 9620 /* The second memory operand must have the same size as
9621 the first one. */
9622 if (i.mem_operands
9623 && i.base_reg
9624 && !((addr_mode == CODE_64BIT
dc821c5f 9625 && i.base_reg->reg_type.bitfield.qword)
be05d201 9626 || (addr_mode == CODE_32BIT
dc821c5f
JB		 9627 ? i.base_reg->reg_type.bitfield.dword
9628 : i.base_reg->reg_type.bitfield.word)))
be05d201
L		 9629 goto bad_address;
9630
fc0763e6
JB		 9631 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9632 operand_string,
9633 intel_syntax ? '[' : '(',
9634 register_prefix,
be05d201 9635 expected_reg->reg_name,
fc0763e6 9636 intel_syntax ? ']' : ')');
be05d201 9637 return 1;
fc0763e6 9638 }
be05d201
L		 9639 else
9640 return 1;
9641
9642bad_address:
9643 as_bad (_("`%s' is not a valid %s expression"),
9644 operand_string, kind);
9645 return 0;
3e73aa7c
JH		 9646 }
9647 else
9648 {
be05d201
L		 9649 if (addr_mode != CODE_16BIT)
9650 {
9651 /* 32-bit/64-bit checks. */
9652 if ((i.base_reg
e968fc9b
JB		 9653 && ((addr_mode == CODE_64BIT
9654 ? !i.base_reg->reg_type.bitfield.qword
9655 : !i.base_reg->reg_type.bitfield.dword)
9656 || (i.index_reg && i.base_reg->reg_num == RegIP)
9657 || i.base_reg->reg_num == RegIZ))
be05d201 9658 || (i.index_reg
1b54b8d7
JB		 9659 && !i.index_reg->reg_type.bitfield.xmmword
9660 && !i.index_reg->reg_type.bitfield.ymmword
9661 && !i.index_reg->reg_type.bitfield.zmmword
be05d201 9662 && ((addr_mode == CODE_64BIT
e968fc9b
JB		 9663 ? !i.index_reg->reg_type.bitfield.qword
9664 : !i.index_reg->reg_type.bitfield.dword)
be05d201
L		 9665 || !i.index_reg->reg_type.bitfield.baseindex)))
9666 goto bad_address;
8178be5b
JB		 9667
9668 /* bndmk, bndldx, and bndstx have special restrictions. */
9669 if (current_templates->start->base_opcode == 0xf30f1b
9670 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
9671 {
9672 /* They cannot use RIP-relative addressing. */
e968fc9b 9673 if (i.base_reg && i.base_reg->reg_num == RegIP)
8178be5b
JB		 9674 {
9675 as_bad (_("`%s' cannot be used here"), operand_string);
9676 return 0;
9677 }
9678
9679 /* bndldx and bndstx ignore their scale factor. */
9680 if (current_templates->start->base_opcode != 0xf30f1b
9681 && i.log2_scale_factor)
9682 as_warn (_("register scaling is being ignored here"));
9683 }
be05d201
L		 9684 }
9685 else
3e73aa7c 9686 {
be05d201 9687 /* 16-bit checks. */
3e73aa7c 9688 if ((i.base_reg
dc821c5f 9689 && (!i.base_reg->reg_type.bitfield.word
40fb9820 9690 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 9691 || (i.index_reg
dc821c5f 9692 && (!i.index_reg->reg_type.bitfield.word
40fb9820 9693 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 9694 || !(i.base_reg
9695 && i.base_reg->reg_num < 6
9696 && i.index_reg->reg_num >= 6
9697 && i.log2_scale_factor == 0))))
be05d201 9698 goto bad_address;
3e73aa7c
JH		 9699 }
9700 }
be05d201 9701 return 1;
24eab124 9702}
252b5132 9703
43234a1e
L		 9704/* Handle vector immediates. */
9705
9706static int
9707RC_SAE_immediate (const char *imm_start)
9708{
9709 unsigned int match_found, j;
9710 const char *pstr = imm_start;
9711 expressionS *exp;
9712
9713 if (*pstr != '{')
9714 return 0;
9715
9716 pstr++;
9717 match_found = 0;
9718 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
9719 {
9720 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
9721 {
9722 if (!i.rounding)
9723 {
9724 rc_op.type = RC_NamesTable[j].type;
9725 rc_op.operand = this_operand;
9726 i.rounding = &rc_op;
9727 }
9728 else
9729 {
9730 as_bad (_("duplicated `%s'"), imm_start);
9731 return 0;
9732 }
9733 pstr += RC_NamesTable[j].len;
9734 match_found = 1;
9735 break;
9736 }
9737 }
9738 if (!match_found)
9739 return 0;
9740
9741 if (*pstr++ != '}')
9742 {
9743 as_bad (_("Missing '}': '%s'"), imm_start);
9744 return 0;
9745 }
9746 /* RC/SAE immediate string should contain nothing more. */;
9747 if (*pstr != 0)
9748 {
9749 as_bad (_("Junk after '}': '%s'"), imm_start);
9750 return 0;
9751 }
9752
9753 exp = &im_expressions[i.imm_operands++];
9754 i.op[this_operand].imms = exp;
9755
9756 exp->X_op = O_constant;
9757 exp->X_add_number = 0;
9758 exp->X_add_symbol = (symbolS *) 0;
9759 exp->X_op_symbol = (symbolS *) 0;
9760
9761 i.types[this_operand].bitfield.imm8 = 1;
9762 return 1;
9763}
9764
8325cc63
JB		 9765/* Only string instructions can have a second memory operand, so
9766 reduce current_templates to just those if it contains any. */
9767static int
9768maybe_adjust_templates (void)
9769{
9770 const insn_template *t;
9771
9772 gas_assert (i.mem_operands == 1);
9773
9774 for (t = current_templates->start; t < current_templates->end; ++t)
9775 if (t->opcode_modifier.isstring)
9776 break;
9777
9778 if (t < current_templates->end)
9779 {
9780 static templates aux_templates;
9781 bfd_boolean recheck;
9782
9783 aux_templates.start = t;
9784 for (; t < current_templates->end; ++t)
9785 if (!t->opcode_modifier.isstring)
9786 break;
9787 aux_templates.end = t;
9788
9789 /* Determine whether to re-check the first memory operand. */
9790 recheck = (aux_templates.start != current_templates->start
9791 || t != current_templates->end);
9792
9793 current_templates = &aux_templates;
9794
9795 if (recheck)
9796 {
9797 i.mem_operands = 0;
9798 if (i.memop1_string != NULL
9799 && i386_index_check (i.memop1_string) == 0)
9800 return 0;
9801 i.mem_operands = 1;
9802 }
9803 }
9804
9805 return 1;
9806}
9807
fc0763e6 9808/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 9809 on error. */
252b5132 9810
252b5132 9811static int
a7619375 9812i386_att_operand (char *operand_string)
252b5132 9813{
af6bdddf
AM		 9814 const reg_entry *r;
9815 char *end_op;
24eab124 9816 char *op_string = operand_string;
252b5132 9817
24eab124 9818 if (is_space_char (*op_string))
252b5132
RH		 9819 ++op_string;
9820
24eab124 9821 /* We check for an absolute prefix (differentiating,
47926f60 9822 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 9823 if (*op_string == ABSOLUTE_PREFIX)
9824 {
9825 ++op_string;
9826 if (is_space_char (*op_string))
9827 ++op_string;
40fb9820 9828 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 9829 }
252b5132 9830
47926f60 9831 /* Check if operand is a register. */
4d1bb795 9832 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 9833 {
40fb9820
L		 9834 i386_operand_type temp;
9835
24eab124
AM		 9836 /* Check for a segment override by searching for ':' after a
9837 segment register. */
9838 op_string = end_op;
9839 if (is_space_char (*op_string))
9840 ++op_string;
40fb9820
L		 9841 if (*op_string == ':'
9842 && (r->reg_type.bitfield.sreg2
9843 || r->reg_type.bitfield.sreg3))
24eab124
AM		 9844 {
9845 switch (r->reg_num)
9846 {
9847 case 0:
9848 i.seg[i.mem_operands] = &es;
9849 break;
9850 case 1:
9851 i.seg[i.mem_operands] = &cs;
9852 break;
9853 case 2:
9854 i.seg[i.mem_operands] = &ss;
9855 break;
9856 case 3:
9857 i.seg[i.mem_operands] = &ds;
9858 break;
9859 case 4:
9860 i.seg[i.mem_operands] = &fs;
9861 break;
9862 case 5:
9863 i.seg[i.mem_operands] = &gs;
9864 break;
9865 }
252b5132 9866
24eab124 9867 /* Skip the ':' and whitespace. */
252b5132
RH		 9868 ++op_string;
9869 if (is_space_char (*op_string))
24eab124 9870 ++op_string;
252b5132 9871
24eab124
AM		 9872 if (!is_digit_char (*op_string)
9873 && !is_identifier_char (*op_string)
9874 && *op_string != '('
9875 && *op_string != ABSOLUTE_PREFIX)
9876 {
9877 as_bad (_("bad memory operand `%s'"), op_string);
9878 return 0;
9879 }
47926f60 9880 /* Handle case of %es:*foo. */
24eab124
AM		 9881 if (*op_string == ABSOLUTE_PREFIX)
9882 {
9883 ++op_string;
9884 if (is_space_char (*op_string))
9885 ++op_string;
40fb9820 9886 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 9887 }
9888 goto do_memory_reference;
9889 }
43234a1e
L		 9890
9891 /* Handle vector operations. */
9892 if (*op_string == '{')
9893 {
9894 op_string = check_VecOperations (op_string, NULL);
9895 if (op_string == NULL)
9896 return 0;
9897 }
9898
24eab124
AM		 9899 if (*op_string)
9900 {
d0b47220 9901 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 9902 return 0;
9903 }
40fb9820
L		 9904 temp = r->reg_type;
9905 temp.bitfield.baseindex = 0;
c6fb90c8
L		 9906 i.types[this_operand] = operand_type_or (i.types[this_operand],
9907 temp);
7d5e4556 9908 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 9909 i.op[this_operand].regs = r;
24eab124
AM		 9910 i.reg_operands++;
9911 }
af6bdddf
AM		 9912 else if (*op_string == REGISTER_PREFIX)
9913 {
9914 as_bad (_("bad register name `%s'"), op_string);
9915 return 0;
9916 }
24eab124 9917 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 9918 {
24eab124 9919 ++op_string;
40fb9820 9920 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 9921 {
d0b47220 9922 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 9923 return 0;
9924 }
9925 if (!i386_immediate (op_string))
9926 return 0;
9927 }
43234a1e
L		 9928 else if (RC_SAE_immediate (operand_string))
9929 {
9930 /* If it is a RC or SAE immediate, do nothing. */
9931 ;
9932 }
24eab124
AM		 9933 else if (is_digit_char (*op_string)
9934 || is_identifier_char (*op_string)
d02603dc 9935 || *op_string == '"'
e5cb08ac 9936 || *op_string == '(')
24eab124 9937 {
47926f60 9938 /* This is a memory reference of some sort. */
af6bdddf 9939 char *base_string;
252b5132 9940
47926f60 9941 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 9942 char *displacement_string_start;
9943 char *displacement_string_end;
43234a1e 9944 char *vop_start;
252b5132 9945
24eab124 9946 do_memory_reference:
8325cc63
JB		 9947 if (i.mem_operands == 1 && !maybe_adjust_templates ())
9948 return 0;
24eab124 9949 if ((i.mem_operands == 1
40fb9820 9950 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 9951 || i.mem_operands == 2)
9952 {
9953 as_bad (_("too many memory references for `%s'"),
9954 current_templates->start->name);
9955 return 0;
9956 }
252b5132 9957
24eab124
AM		 9958 /* Check for base index form. We detect the base index form by
9959 looking for an ')' at the end of the operand, searching
9960 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9961 after the '('. */
af6bdddf 9962 base_string = op_string + strlen (op_string);
c3332e24 9963
43234a1e
L		 9964 /* Handle vector operations. */
9965 vop_start = strchr (op_string, '{');
9966 if (vop_start && vop_start < base_string)
9967 {
9968 if (check_VecOperations (vop_start, base_string) == NULL)
9969 return 0;
9970 base_string = vop_start;
9971 }
9972
af6bdddf
AM		 9973 --base_string;
9974 if (is_space_char (*base_string))
9975 --base_string;
252b5132 9976
47926f60 9977 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 9978 displacement_string_start = op_string;
9979 displacement_string_end = base_string + 1;
252b5132 9980
24eab124
AM		 9981 if (*base_string == ')')
9982 {
af6bdddf 9983 char *temp_string;
24eab124
AM		 9984 unsigned int parens_balanced = 1;
9985 /* We've already checked that the number of left & right ()'s are
47926f60 9986 equal, so this loop will not be infinite. */
24eab124
AM		 9987 do
9988 {
9989 base_string--;
9990 if (*base_string == ')')
9991 parens_balanced++;
9992 if (*base_string == '(')
9993 parens_balanced--;
9994 }
9995 while (parens_balanced);
c3332e24 9996
af6bdddf 9997 temp_string = base_string;
c3332e24 9998
24eab124 9999 /* Skip past '(' and whitespace. */
252b5132
RH		 10000 ++base_string;
10001 if (is_space_char (*base_string))
24eab124 10002 ++base_string;
252b5132 10003
af6bdddf 10004 if (*base_string == ','
4eed87de
AM		 10005 || ((i.base_reg = parse_register (base_string, &end_op))
10006 != NULL))
252b5132 10007 {
af6bdddf 10008 displacement_string_end = temp_string;
252b5132 10009
40fb9820 10010 i.types[this_operand].bitfield.baseindex = 1;
252b5132 10011
af6bdddf 10012 if (i.base_reg)
24eab124 10013 {
24eab124
AM		 10014 base_string = end_op;
10015 if (is_space_char (*base_string))
10016 ++base_string;
af6bdddf
AM		 10017 }
10018
10019 /* There may be an index reg or scale factor here. */
10020 if (*base_string == ',')
10021 {
10022 ++base_string;
10023 if (is_space_char (*base_string))
10024 ++base_string;
10025
4eed87de
AM		 10026 if ((i.index_reg = parse_register (base_string, &end_op))
10027 != NULL)
24eab124 10028 {
af6bdddf 10029 base_string = end_op;
24eab124
AM		 10030 if (is_space_char (*base_string))
10031 ++base_string;
af6bdddf
AM		 10032 if (*base_string == ',')
10033 {
10034 ++base_string;
10035 if (is_space_char (*base_string))
10036 ++base_string;
10037 }
e5cb08ac 10038 else if (*base_string != ')')
af6bdddf 10039 {
4eed87de
AM		 10040 as_bad (_("expecting `,' or `)' "
10041 "after index register in `%s'"),
af6bdddf
AM		 10042 operand_string);
10043 return 0;
10044 }
24eab124 10045 }
af6bdddf 10046 else if (*base_string == REGISTER_PREFIX)
24eab124 10047 {
f76bf5e0
L		 10048 end_op = strchr (base_string, ',');
10049 if (end_op)
10050 *end_op = '\0';
af6bdddf 10051 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 10052 return 0;
10053 }
252b5132 10054
47926f60 10055 /* Check for scale factor. */
551c1ca1 10056 if (*base_string != ')')
af6bdddf 10057 {
551c1ca1
AM		 10058 char *end_scale = i386_scale (base_string);
10059
10060 if (!end_scale)
af6bdddf 10061 return 0;
24eab124 10062
551c1ca1 10063 base_string = end_scale;
af6bdddf
AM		 10064 if (is_space_char (*base_string))
10065 ++base_string;
10066 if (*base_string != ')')
10067 {
4eed87de
AM		 10068 as_bad (_("expecting `)' "
10069 "after scale factor in `%s'"),
af6bdddf
AM		 10070 operand_string);
10071 return 0;
10072 }
10073 }
10074 else if (!i.index_reg)
24eab124 10075 {
4eed87de
AM		 10076 as_bad (_("expecting index register or scale factor "
10077 "after `,'; got '%c'"),
af6bdddf 10078 *base_string);
24eab124
AM		 10079 return 0;
10080 }
10081 }
af6bdddf 10082 else if (*base_string != ')')
24eab124 10083 {
4eed87de
AM		 10084 as_bad (_("expecting `,' or `)' "
10085 "after base register in `%s'"),
af6bdddf 10086 operand_string);
24eab124
AM		 10087 return 0;
10088 }
c3332e24 10089 }
af6bdddf 10090 else if (*base_string == REGISTER_PREFIX)
c3332e24 10091 {
f76bf5e0
L		 10092 end_op = strchr (base_string, ',');
10093 if (end_op)
10094 *end_op = '\0';
af6bdddf 10095 as_bad (_("bad register name `%s'"), base_string);
24eab124 10096 return 0;
c3332e24 10097 }
24eab124
AM		 10098 }
10099
10100 /* If there's an expression beginning the operand, parse it,
10101 assuming displacement_string_start and
10102 displacement_string_end are meaningful. */
10103 if (displacement_string_start != displacement_string_end)
10104 {
10105 if (!i386_displacement (displacement_string_start,
10106 displacement_string_end))
10107 return 0;
10108 }
10109
10110 /* Special case for (%dx) while doing input/output op. */
10111 if (i.base_reg
2fb5be8d 10112 && i.base_reg->reg_type.bitfield.inoutportreg
24eab124
AM		 10113 && i.index_reg == 0
10114 && i.log2_scale_factor == 0
10115 && i.seg[i.mem_operands] == 0
40fb9820 10116 && !operand_type_check (i.types[this_operand], disp))
24eab124 10117 {
2fb5be8d 10118 i.types[this_operand] = i.base_reg->reg_type;
24eab124
AM		 10119 return 1;
10120 }
10121
eecb386c
AM		 10122 if (i386_index_check (operand_string) == 0)
10123 return 0;
c48dadc9 10124 i.flags[this_operand] |= Operand_Mem;
8325cc63
JB		 10125 if (i.mem_operands == 0)
10126 i.memop1_string = xstrdup (operand_string);
24eab124
AM		 10127 i.mem_operands++;
10128 }
10129 else
ce8a8b2f
AM		 10130 {
10131 /* It's not a memory operand; argh! */
24eab124
AM		 10132 as_bad (_("invalid char %s beginning operand %d `%s'"),
10133 output_invalid (*op_string),
10134 this_operand + 1,
10135 op_string);
10136 return 0;
10137 }
47926f60 10138 return 1; /* Normal return. */
252b5132
RH		 10139}
10140\f
fa94de6b
RM		 10141/* Calculate the maximum variable size (i.e., excluding fr_fix)
10142 that an rs_machine_dependent frag may reach. */
10143
10144unsigned int
10145i386_frag_max_var (fragS *frag)
10146{
10147 /* The only relaxable frags are for jumps.
10148 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
10149 gas_assert (frag->fr_type == rs_machine_dependent);
10150 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
10151}
10152
b084df0b
L		 10153#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10154static int
8dcea932 10155elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
b084df0b
L		 10156{
10157 /* STT_GNU_IFUNC symbol must go through PLT. */
10158 if ((symbol_get_bfdsym (fr_symbol)->flags
10159 & BSF_GNU_INDIRECT_FUNCTION) != 0)
10160 return 0;
10161
10162 if (!S_IS_EXTERNAL (fr_symbol))
10163 /* Symbol may be weak or local. */
10164 return !S_IS_WEAK (fr_symbol);
10165
8dcea932
L		 10166 /* Global symbols with non-default visibility can't be preempted. */
10167 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
10168 return 1;
10169
10170 if (fr_var != NO_RELOC)
10171 switch ((enum bfd_reloc_code_real) fr_var)
10172 {
10173 case BFD_RELOC_386_PLT32:
10174 case BFD_RELOC_X86_64_PLT32:
33eaf5de 10175 /* Symbol with PLT relocation may be preempted. */
8dcea932
L		 10176 return 0;
10177 default:
10178 abort ();
10179 }
10180
b084df0b
L		 10181 /* Global symbols with default visibility in a shared library may be
10182 preempted by another definition. */
8dcea932 10183 return !shared;
b084df0b
L		 10184}
10185#endif
10186
ee7fcc42
AM		 10187/* md_estimate_size_before_relax()
10188
10189 Called just before relax() for rs_machine_dependent frags. The x86
10190 assembler uses these frags to handle variable size jump
10191 instructions.
10192
10193 Any symbol that is now undefined will not become defined.
10194 Return the correct fr_subtype in the frag.
10195 Return the initial "guess for variable size of frag" to caller.
10196 The guess is actually the growth beyond the fixed part. Whatever
10197 we do to grow the fixed or variable part contributes to our
10198 returned value. */
10199
252b5132 10200int
7016a5d5 10201md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 10202{
252b5132 10203 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 10204 check for un-relaxable symbols. On an ELF system, we can't relax
10205 an externally visible symbol, because it may be overridden by a
10206 shared library. */
10207 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 10208#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 10209 || (IS_ELF
8dcea932
L		 10210 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
10211 fragP->fr_var))
fbeb56a4
DK		 10212#endif
10213#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 10214 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 10215 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 10216#endif
10217 )
252b5132 10218 {
b98ef147
AM		 10219 /* Symbol is undefined in this segment, or we need to keep a
10220 reloc so that weak symbols can be overridden. */
10221 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 10222 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 10223 unsigned char *opcode;
10224 int old_fr_fix;
f6af82bd 10225
ee7fcc42 10226 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 10227 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 10228 else if (size == 2)
f6af82bd 10229 reloc_type = BFD_RELOC_16_PCREL;
bd7ab16b
L		 10230#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10231 else if (need_plt32_p (fragP->fr_symbol))
10232 reloc_type = BFD_RELOC_X86_64_PLT32;
10233#endif
f6af82bd
AM		 10234 else
10235 reloc_type = BFD_RELOC_32_PCREL;
252b5132 10236
ee7fcc42
AM		 10237 old_fr_fix = fragP->fr_fix;
10238 opcode = (unsigned char *) fragP->fr_opcode;
10239
fddf5b5b 10240 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 10241 {
fddf5b5b
AM		 10242 case UNCOND_JUMP:
10243 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 10244 opcode[0] = 0xe9;
252b5132 10245 fragP->fr_fix += size;
062cd5e7
AS		 10246 fix_new (fragP, old_fr_fix, size,
10247 fragP->fr_symbol,
10248 fragP->fr_offset, 1,
10249 reloc_type);
252b5132
RH		 10250 break;
10251
fddf5b5b 10252 case COND_JUMP86:
412167cb
AM		 10253 if (size == 2
10254 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 10255 {
10256 /* Negate the condition, and branch past an
10257 unconditional jump. */
10258 opcode[0] ^= 1;
10259 opcode[1] = 3;
10260 /* Insert an unconditional jump. */
10261 opcode[2] = 0xe9;
10262 /* We added two extra opcode bytes, and have a two byte
10263 offset. */
10264 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 10265 fix_new (fragP, old_fr_fix + 2, 2,
10266 fragP->fr_symbol,
10267 fragP->fr_offset, 1,
10268 reloc_type);
fddf5b5b
AM		 10269 break;
10270 }
10271 /* Fall through. */
10272
10273 case COND_JUMP:
412167cb
AM		 10274 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
10275 {
3e02c1cc
AM		 10276 fixS *fixP;
10277
412167cb 10278 fragP->fr_fix += 1;
3e02c1cc
AM		 10279 fixP = fix_new (fragP, old_fr_fix, 1,
10280 fragP->fr_symbol,
10281 fragP->fr_offset, 1,
10282 BFD_RELOC_8_PCREL);
10283 fixP->fx_signed = 1;
412167cb
AM		 10284 break;
10285 }
93c2a809 10286
24eab124 10287 /* This changes the byte-displacement jump 0x7N
fddf5b5b 10288 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 10289 opcode[1] = opcode[0] + 0x10;
f6af82bd 10290 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 10291 /* We've added an opcode byte. */
10292 fragP->fr_fix += 1 + size;
062cd5e7
AS		 10293 fix_new (fragP, old_fr_fix + 1, size,
10294 fragP->fr_symbol,
10295 fragP->fr_offset, 1,
10296 reloc_type);
252b5132 10297 break;
fddf5b5b
AM		 10298
10299 default:
10300 BAD_CASE (fragP->fr_subtype);
10301 break;
252b5132
RH		 10302 }
10303 frag_wane (fragP);
ee7fcc42 10304 return fragP->fr_fix - old_fr_fix;
252b5132 10305 }
93c2a809 10306
93c2a809
AM		 10307 /* Guess size depending on current relax state. Initially the relax
10308 state will correspond to a short jump and we return 1, because
10309 the variable part of the frag (the branch offset) is one byte
10310 long. However, we can relax a section more than once and in that
10311 case we must either set fr_subtype back to the unrelaxed state,
10312 or return the value for the appropriate branch. */
10313 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 10314}
10315
47926f60
KH		 10316/* Called after relax() is finished.
10317
10318 In: Address of frag.
10319 fr_type == rs_machine_dependent.
10320 fr_subtype is what the address relaxed to.
10321
10322 Out: Any fixSs and constants are set up.
10323 Caller will turn frag into a ".space 0". */
10324
252b5132 10325void
7016a5d5
TG		 10326md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
10327 fragS *fragP)
252b5132 10328{
29b0f896 10329 unsigned char *opcode;
252b5132 10330 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 10331 offsetT target_address;
10332 offsetT opcode_address;
252b5132 10333 unsigned int extension = 0;
847f7ad4 10334 offsetT displacement_from_opcode_start;
252b5132
RH		 10335
10336 opcode = (unsigned char *) fragP->fr_opcode;
10337
47926f60 10338 /* Address we want to reach in file space. */
252b5132 10339 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 10340
47926f60 10341 /* Address opcode resides at in file space. */
252b5132
RH		 10342 opcode_address = fragP->fr_address + fragP->fr_fix;
10343
47926f60 10344 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 10345 displacement_from_opcode_start = target_address - opcode_address;
10346
fddf5b5b 10347 if ((fragP->fr_subtype & BIG) == 0)
252b5132 10348 {
47926f60
KH		 10349 /* Don't have to change opcode. */
10350 extension = 1; /* 1 opcode + 1 displacement */
252b5132 10351 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 10352 }
10353 else
10354 {
10355 if (no_cond_jump_promotion
10356 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 10357 as_warn_where (fragP->fr_file, fragP->fr_line,
10358 _("long jump required"));
252b5132 10359
fddf5b5b
AM		 10360 switch (fragP->fr_subtype)
10361 {
10362 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
10363 extension = 4; /* 1 opcode + 4 displacement */
10364 opcode[0] = 0xe9;
10365 where_to_put_displacement = &opcode[1];
10366 break;
252b5132 10367
fddf5b5b
AM		 10368 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
10369 extension = 2; /* 1 opcode + 2 displacement */
10370 opcode[0] = 0xe9;
10371 where_to_put_displacement = &opcode[1];
10372 break;
252b5132 10373
fddf5b5b
AM		 10374 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
10375 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
10376 extension = 5; /* 2 opcode + 4 displacement */
10377 opcode[1] = opcode[0] + 0x10;
10378 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
10379 where_to_put_displacement = &opcode[2];
10380 break;
252b5132 10381
fddf5b5b
AM		 10382 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
10383 extension = 3; /* 2 opcode + 2 displacement */
10384 opcode[1] = opcode[0] + 0x10;
10385 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
10386 where_to_put_displacement = &opcode[2];
10387 break;
252b5132 10388
fddf5b5b
AM		 10389 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
10390 extension = 4;
10391 opcode[0] ^= 1;
10392 opcode[1] = 3;
10393 opcode[2] = 0xe9;
10394 where_to_put_displacement = &opcode[3];
10395 break;
10396
10397 default:
10398 BAD_CASE (fragP->fr_subtype);
10399 break;
10400 }
252b5132 10401 }
fddf5b5b 10402
7b81dfbb
AJ		 10403 /* If size if less then four we are sure that the operand fits,
10404 but if it's 4, then it could be that the displacement is larger
10405 then -/+ 2GB. */
10406 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
10407 && object_64bit
10408 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 10409 + ((addressT) 1 << 31))
10410 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 10411 {
10412 as_bad_where (fragP->fr_file, fragP->fr_line,
10413 _("jump target out of range"));
10414 /* Make us emit 0. */
10415 displacement_from_opcode_start = extension;
10416 }
47926f60 10417 /* Now put displacement after opcode. */
252b5132
RH		 10418 md_number_to_chars ((char *) where_to_put_displacement,
10419 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 10420 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 10421 fragP->fr_fix += extension;
10422}
10423\f
7016a5d5 10424/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 10425 by our caller that we have all the info we need to fix it up.
10426
7016a5d5
TG		 10427 Parameter valP is the pointer to the value of the bits.
10428
252b5132
RH		 10429 On the 386, immediates, displacements, and data pointers are all in
10430 the same (little-endian) format, so we don't need to care about which
10431 we are handling. */
10432
94f592af 10433void
7016a5d5 10434md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 10435{
94f592af 10436 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 10437 valueT value = *valP;
252b5132 10438
f86103b7 10439#if !defined (TE_Mach)
93382f6d
AM		 10440 if (fixP->fx_pcrel)
10441 {
10442 switch (fixP->fx_r_type)
10443 {
5865bb77
ILT		 10444 default:
10445 break;
10446
d6ab8113
JB		 10447 case BFD_RELOC_64:
10448 fixP->fx_r_type = BFD_RELOC_64_PCREL;
10449 break;
93382f6d 10450 case BFD_RELOC_32:
ae8887b5 10451 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 10452 fixP->fx_r_type = BFD_RELOC_32_PCREL;
10453 break;
10454 case BFD_RELOC_16:
10455 fixP->fx_r_type = BFD_RELOC_16_PCREL;
10456 break;
10457 case BFD_RELOC_8:
10458 fixP->fx_r_type = BFD_RELOC_8_PCREL;
10459 break;
10460 }
10461 }
252b5132 10462
a161fe53 10463 if (fixP->fx_addsy != NULL
31312f95 10464 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 10465 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95 10466 || fixP->fx_r_type == BFD_RELOC_16_PCREL
d258b828 10467 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
31312f95 10468 && !use_rela_relocations)
252b5132 10469 {
31312f95
AM		 10470 /* This is a hack. There should be a better way to handle this.
10471 This covers for the fact that bfd_install_relocation will
10472 subtract the current location (for partial_inplace, PC relative
10473 relocations); see more below. */
252b5132 10474#ifndef OBJ_AOUT
718ddfc0 10475 if (IS_ELF
252b5132
RH		 10476#ifdef TE_PE
10477 || OUTPUT_FLAVOR == bfd_target_coff_flavour
10478#endif
10479 )
10480 value += fixP->fx_where + fixP->fx_frag->fr_address;
10481#endif
10482#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 10483 if (IS_ELF)
252b5132 10484 {
6539b54b 10485 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 10486
6539b54b 10487 if ((sym_seg == seg
2f66722d 10488 || (symbol_section_p (fixP->fx_addsy)
6539b54b 10489 && sym_seg != absolute_section))
af65af87 10490 && !generic_force_reloc (fixP))
2f66722d
AM		 10491 {
10492 /* Yes, we add the values in twice. This is because
6539b54b
AM		 10493 bfd_install_relocation subtracts them out again. I think
10494 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 10495 it. FIXME. */
10496 value += fixP->fx_where + fixP->fx_frag->fr_address;
10497 }
252b5132
RH		 10498 }
10499#endif
10500#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 10501 /* For some reason, the PE format does not store a
10502 section address offset for a PC relative symbol. */
10503 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 10504 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 10505 value += md_pcrel_from (fixP);
10506#endif
10507 }
fbeb56a4 10508#if defined (OBJ_COFF) && defined (TE_PE)
f01c1a09
NC		 10509 if (fixP->fx_addsy != NULL
10510 && S_IS_WEAK (fixP->fx_addsy)
10511 /* PR 16858: Do not modify weak function references. */
10512 && ! fixP->fx_pcrel)
fbeb56a4 10513 {
296a8689
NC		 10514#if !defined (TE_PEP)
10515 /* For x86 PE weak function symbols are neither PC-relative
10516 nor do they set S_IS_FUNCTION. So the only reliable way
10517 to detect them is to check the flags of their containing
10518 section. */
10519 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
10520 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
10521 ;
10522 else
10523#endif
fbeb56a4
DK		 10524 value -= S_GET_VALUE (fixP->fx_addsy);
10525 }
10526#endif
252b5132
RH		 10527
10528 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 10529 and we must not disappoint it. */
252b5132 10530#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 10531 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 10532 switch (fixP->fx_r_type)
10533 {
10534 case BFD_RELOC_386_PLT32:
3e73aa7c 10535 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 10536 /* Make the jump instruction point to the address of the operand. At
10537 runtime we merely add the offset to the actual PLT entry. */
10538 value = -4;
10539 break;
31312f95 10540
13ae64f3
JJ		 10541 case BFD_RELOC_386_TLS_GD:
10542 case BFD_RELOC_386_TLS_LDM:
13ae64f3 10543 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 10544 case BFD_RELOC_386_TLS_IE:
10545 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 10546 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 10547 case BFD_RELOC_X86_64_TLSGD:
10548 case BFD_RELOC_X86_64_TLSLD:
10549 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 10550 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 10551 value = 0; /* Fully resolved at runtime. No addend. */
10552 /* Fallthrough */
10553 case BFD_RELOC_386_TLS_LE:
10554 case BFD_RELOC_386_TLS_LDO_32:
10555 case BFD_RELOC_386_TLS_LE_32:
10556 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 10557 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 10558 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 10559 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 10560 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10561 break;
10562
67a4f2b7
AO		 10563 case BFD_RELOC_386_TLS_DESC_CALL:
10564 case BFD_RELOC_X86_64_TLSDESC_CALL:
10565 value = 0; /* Fully resolved at runtime. No addend. */
10566 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10567 fixP->fx_done = 0;
10568 return;
10569
47926f60
KH		 10570 case BFD_RELOC_VTABLE_INHERIT:
10571 case BFD_RELOC_VTABLE_ENTRY:
10572 fixP->fx_done = 0;
94f592af 10573 return;
47926f60
KH		 10574
10575 default:
10576 break;
10577 }
10578#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 10579 *valP = value;
f86103b7 10580#endif /* !defined (TE_Mach) */
3e73aa7c 10581
3e73aa7c 10582 /* Are we finished with this relocation now? */
c6682705 10583 if (fixP->fx_addsy == NULL)
3e73aa7c 10584 fixP->fx_done = 1;
fbeb56a4
DK		 10585#if defined (OBJ_COFF) && defined (TE_PE)
10586 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
10587 {
10588 fixP->fx_done = 0;
10589 /* Remember value for tc_gen_reloc. */
10590 fixP->fx_addnumber = value;
10591 /* Clear out the frag for now. */
10592 value = 0;
10593 }
10594#endif
3e73aa7c
JH		 10595 else if (use_rela_relocations)
10596 {
10597 fixP->fx_no_overflow = 1;
062cd5e7
AS		 10598 /* Remember value for tc_gen_reloc. */
10599 fixP->fx_addnumber = value;
3e73aa7c
JH		 10600 value = 0;
10601 }
f86103b7 10602
94f592af 10603 md_number_to_chars (p, value, fixP->fx_size);
252b5132 10604}
252b5132 10605\f
6d4af3c2 10606const char *
499ac353 10607md_atof (int type, char *litP, int *sizeP)
252b5132 10608{
499ac353
NC		 10609 /* This outputs the LITTLENUMs in REVERSE order;
10610 in accord with the bigendian 386. */
10611 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 10612}
10613\f
2d545b82 10614static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 10615
252b5132 10616static char *
e3bb37b5 10617output_invalid (int c)
252b5132 10618{
3882b010 10619 if (ISPRINT (c))
f9f21a03
L		 10620 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10621 "'%c'", c);
252b5132 10622 else
f9f21a03 10623 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 10624 "(0x%x)", (unsigned char) c);
252b5132
RH		 10625 return output_invalid_buf;
10626}
10627
af6bdddf 10628/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 10629
10630static const reg_entry *
4d1bb795 10631parse_real_register (char *reg_string, char **end_op)
252b5132 10632{
af6bdddf
AM		 10633 char *s = reg_string;
10634 char *p;
252b5132
RH		 10635 char reg_name_given[MAX_REG_NAME_SIZE + 1];
10636 const reg_entry *r;
10637
10638 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10639 if (*s == REGISTER_PREFIX)
10640 ++s;
10641
10642 if (is_space_char (*s))
10643 ++s;
10644
10645 p = reg_name_given;
af6bdddf 10646 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 10647 {
10648 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 10649 return (const reg_entry *) NULL;
10650 s++;
252b5132
RH		 10651 }
10652
6588847e
DN		 10653 /* For naked regs, make sure that we are not dealing with an identifier.
10654 This prevents confusing an identifier like `eax_var' with register
10655 `eax'. */
10656 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
10657 return (const reg_entry *) NULL;
10658
af6bdddf 10659 *end_op = s;
252b5132
RH		 10660
10661 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
10662
5f47d35b 10663 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 10664 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 10665 {
0e0eea78
JB		 10666 if (!cpu_arch_flags.bitfield.cpu8087
10667 && !cpu_arch_flags.bitfield.cpu287
10668 && !cpu_arch_flags.bitfield.cpu387)
10669 return (const reg_entry *) NULL;
10670
5f47d35b
AM		 10671 if (is_space_char (*s))
10672 ++s;
10673 if (*s == '(')
10674 {
af6bdddf 10675 ++s;
5f47d35b
AM		 10676 if (is_space_char (*s))
10677 ++s;
10678 if (*s >= '0' && *s <= '7')
10679 {
db557034 10680 int fpr = *s - '0';
af6bdddf 10681 ++s;
5f47d35b
AM		 10682 if (is_space_char (*s))
10683 ++s;
10684 if (*s == ')')
10685 {
10686 *end_op = s + 1;
1e9cc1c2 10687 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 10688 know (r);
10689 return r + fpr;
5f47d35b 10690 }
5f47d35b 10691 }
47926f60 10692 /* We have "%st(" then garbage. */
5f47d35b
AM		 10693 return (const reg_entry *) NULL;
10694 }
10695 }
10696
a60de03c
JB		 10697 if (r == NULL || allow_pseudo_reg)
10698 return r;
10699
0dfbf9d7 10700 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 10701 return (const reg_entry *) NULL;
10702
dc821c5f 10703 if ((r->reg_type.bitfield.dword
192dc9c6
JB		 10704 || r->reg_type.bitfield.sreg3
10705 || r->reg_type.bitfield.control
10706 || r->reg_type.bitfield.debug
10707 || r->reg_type.bitfield.test)
10708 && !cpu_arch_flags.bitfield.cpui386)
10709 return (const reg_entry *) NULL;
10710
6e041cf4 10711 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
192dc9c6
JB		 10712 return (const reg_entry *) NULL;
10713
6e041cf4
JB		 10714 if (!cpu_arch_flags.bitfield.cpuavx512f)
10715 {
10716 if (r->reg_type.bitfield.zmmword || r->reg_type.bitfield.regmask)
10717 return (const reg_entry *) NULL;
40f12533 10718
6e041cf4
JB		 10719 if (!cpu_arch_flags.bitfield.cpuavx)
10720 {
10721 if (r->reg_type.bitfield.ymmword)
10722 return (const reg_entry *) NULL;
1848e567 10723
6e041cf4
JB		 10724 if (!cpu_arch_flags.bitfield.cpusse && r->reg_type.bitfield.xmmword)
10725 return (const reg_entry *) NULL;
10726 }
10727 }
43234a1e 10728
1adf7f56
JB		 10729 if (r->reg_type.bitfield.regbnd && !cpu_arch_flags.bitfield.cpumpx)
10730 return (const reg_entry *) NULL;
10731
db51cc60 10732 /* Don't allow fake index register unless allow_index_reg isn't 0. */
e968fc9b 10733 if (!allow_index_reg && r->reg_num == RegIZ)
db51cc60
L		 10734 return (const reg_entry *) NULL;
10735
1d3f8286
JB		 10736 /* Upper 16 vector registers are only available with VREX in 64bit
10737 mode, and require EVEX encoding. */
10738 if (r->reg_flags & RegVRex)
43234a1e 10739 {
e951d5ca 10740 if (!cpu_arch_flags.bitfield.cpuavx512f
43234a1e
L		 10741 || flag_code != CODE_64BIT)
10742 return (const reg_entry *) NULL;
1d3f8286
JB		 10743
10744 i.vec_encoding = vex_encoding_evex;
43234a1e
L		 10745 }
10746
4787f4a5
JB		 10747 if (((r->reg_flags & (RegRex64 | RegRex)) || r->reg_type.bitfield.qword)
10748 && (!cpu_arch_flags.bitfield.cpulm || !r->reg_type.bitfield.control)
1ae00879 10749 && flag_code != CODE_64BIT)
20f0a1fc 10750 return (const reg_entry *) NULL;
1ae00879 10751
b7240065
JB		 10752 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
10753 return (const reg_entry *) NULL;
10754
252b5132
RH		 10755 return r;
10756}
4d1bb795
JB		 10757
10758/* REG_STRING starts *before* REGISTER_PREFIX. */
10759
10760static const reg_entry *
10761parse_register (char *reg_string, char **end_op)
10762{
10763 const reg_entry *r;
10764
10765 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
10766 r = parse_real_register (reg_string, end_op);
10767 else
10768 r = NULL;
10769 if (!r)
10770 {
10771 char *save = input_line_pointer;
10772 char c;
10773 symbolS *symbolP;
10774
10775 input_line_pointer = reg_string;
d02603dc 10776 c = get_symbol_name (&reg_string);
4d1bb795
JB		 10777 symbolP = symbol_find (reg_string);
10778 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
10779 {
10780 const expressionS *e = symbol_get_value_expression (symbolP);
10781
0398aac5 10782 know (e->X_op == O_register);
4eed87de 10783 know (e->X_add_number >= 0
c3fe08fa 10784 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795 10785 r = i386_regtab + e->X_add_number;
d3bb6b49 10786 if ((r->reg_flags & RegVRex))
86fa6981 10787 i.vec_encoding = vex_encoding_evex;
4d1bb795
JB		 10788 *end_op = input_line_pointer;
10789 }
10790 *input_line_pointer = c;
10791 input_line_pointer = save;
10792 }
10793 return r;
10794}
10795
10796int
10797i386_parse_name (char *name, expressionS *e, char *nextcharP)
10798{
10799 const reg_entry *r;
10800 char *end = input_line_pointer;
10801
10802 *end = *nextcharP;
10803 r = parse_register (name, &input_line_pointer);
10804 if (r && end <= input_line_pointer)
10805 {
10806 *nextcharP = *input_line_pointer;
10807 *input_line_pointer = 0;
10808 e->X_op = O_register;
10809 e->X_add_number = r - i386_regtab;
10810 return 1;
10811 }
10812 input_line_pointer = end;
10813 *end = 0;
ee86248c 10814 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 10815}
10816
10817void
10818md_operand (expressionS *e)
10819{
ee86248c
JB		 10820 char *end;
10821 const reg_entry *r;
4d1bb795 10822
ee86248c
JB		 10823 switch (*input_line_pointer)
10824 {
10825 case REGISTER_PREFIX:
10826 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 10827 if (r)
10828 {
10829 e->X_op = O_register;
10830 e->X_add_number = r - i386_regtab;
10831 input_line_pointer = end;
10832 }
ee86248c
JB		 10833 break;
10834
10835 case '[':
9c2799c2 10836 gas_assert (intel_syntax);
ee86248c
JB		 10837 end = input_line_pointer++;
10838 expression (e);
10839 if (*input_line_pointer == ']')
10840 {
10841 ++input_line_pointer;
10842 e->X_op_symbol = make_expr_symbol (e);
10843 e->X_add_symbol = NULL;
10844 e->X_add_number = 0;
10845 e->X_op = O_index;
10846 }
10847 else
10848 {
10849 e->X_op = O_absent;
10850 input_line_pointer = end;
10851 }
10852 break;
4d1bb795
JB		 10853 }
10854}
10855
252b5132 10856\f
4cc782b5 10857#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
b6f8c7c4 10858const char *md_shortopts = "kVQ:sqnO::";
252b5132 10859#else
b6f8c7c4 10860const char *md_shortopts = "qnO::";
252b5132 10861#endif
6e0b89ee 10862
3e73aa7c 10863#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 10864#define OPTION_64 (OPTION_MD_BASE + 1)
10865#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 10866#define OPTION_MARCH (OPTION_MD_BASE + 3)
10867#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 10868#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10869#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10870#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10871#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
bd5dea88 10872#define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
c0f3af97 10873#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 10874#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 10875#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10876#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10877#define OPTION_X32 (OPTION_MD_BASE + 14)
7e8b059b 10878#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
43234a1e
L		 10879#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10880#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
167ad85b 10881#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
d1982f93 10882#define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
d3d3c6db 10883#define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
8dcea932 10884#define OPTION_MSHARED (OPTION_MD_BASE + 21)
5db04b09
L		 10885#define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10886#define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
e4e00185 10887#define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
b4a3a7b4 10888#define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
03751133 10889#define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
b3b91714 10890
99ad8390
NC		 10891struct option md_longopts[] =
10892{
3e73aa7c 10893 {"32", no_argument, NULL, OPTION_32},
321098a5 10894#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 10895 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 10896 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 10897#endif
10898#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 10899 {"x32", no_argument, NULL, OPTION_X32},
8dcea932 10900 {"mshared", no_argument, NULL, OPTION_MSHARED},
b4a3a7b4 10901 {"mx86-used-note", required_argument, NULL, OPTION_X86_USED_NOTE},
6e0b89ee 10902#endif
b3b91714 10903 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 10904 {"march", required_argument, NULL, OPTION_MARCH},
10905 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 10906 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
10907 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
10908 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
10909 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
c0f3af97 10910 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 10911 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 10912 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 10913 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
03751133 10914 {"mvexwig", required_argument, NULL, OPTION_MVEXWIG},
7e8b059b 10915 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
43234a1e
L		 10916 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
10917 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
167ad85b
TG		 10918# if defined (TE_PE) || defined (TE_PEP)
10919 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
10920#endif
d1982f93 10921 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
e4e00185 10922 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
0cb4071e 10923 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
d3d3c6db 10924 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
5db04b09
L		 10925 {"mamd64", no_argument, NULL, OPTION_MAMD64},
10926 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
252b5132
RH		 10927 {NULL, no_argument, NULL, 0}
10928};
10929size_t md_longopts_size = sizeof (md_longopts);
10930
10931int
17b9d67d 10932md_parse_option (int c, const char *arg)
252b5132 10933{
91d6fa6a 10934 unsigned int j;
293f5f65 10935 char *arch, *next, *saved;
9103f4f4 10936
252b5132
RH		 10937 switch (c)
10938 {
12b55ccc
L		 10939 case 'n':
10940 optimize_align_code = 0;
10941 break;
10942
a38cf1db
AM		 10943 case 'q':
10944 quiet_warnings = 1;
252b5132
RH		 10945 break;
10946
10947#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 10948 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10949 should be emitted or not. FIXME: Not implemented. */
10950 case 'Q':
252b5132
RH		 10951 break;
10952
10953 /* -V: SVR4 argument to print version ID. */
10954 case 'V':
10955 print_version_id ();
10956 break;
10957
a38cf1db
AM		 10958 /* -k: Ignore for FreeBSD compatibility. */
10959 case 'k':
252b5132 10960 break;
4cc782b5
ILT		 10961
10962 case 's':
10963 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 10964 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 10965 break;
8dcea932
L		 10966
10967 case OPTION_MSHARED:
10968 shared = 1;
10969 break;
b4a3a7b4
L		 10970
10971 case OPTION_X86_USED_NOTE:
10972 if (strcasecmp (arg, "yes") == 0)
10973 x86_used_note = 1;
10974 else if (strcasecmp (arg, "no") == 0)
10975 x86_used_note = 0;
10976 else
10977 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg);
10978 break;
10979
10980
99ad8390 10981#endif
321098a5 10982#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 10983 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 10984 case OPTION_64:
10985 {
10986 const char **list, **l;
10987
3e73aa7c
JH		 10988 list = bfd_target_list ();
10989 for (l = list; *l != NULL; l++)
8620418b 10990 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 10991 || strcmp (*l, "coff-x86-64") == 0
10992 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 10993 || strcmp (*l, "pei-x86-64") == 0
10994 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 10995 {
10996 default_arch = "x86_64";
10997 break;
10998 }
3e73aa7c 10999 if (*l == NULL)
2b5d6a91 11000 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 11001 free (list);
11002 }
11003 break;
11004#endif
252b5132 11005
351f65ca 11006#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 11007 case OPTION_X32:
351f65ca
L		 11008 if (IS_ELF)
11009 {
11010 const char **list, **l;
11011
11012 list = bfd_target_list ();
11013 for (l = list; *l != NULL; l++)
11014 if (CONST_STRNEQ (*l, "elf32-x86-64"))
11015 {
11016 default_arch = "x86_64:32";
11017 break;
11018 }
11019 if (*l == NULL)
2b5d6a91 11020 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 11021 free (list);
11022 }
11023 else
11024 as_fatal (_("32bit x86_64 is only supported for ELF"));
11025 break;
11026#endif
11027
6e0b89ee
AM		 11028 case OPTION_32:
11029 default_arch = "i386";
11030 break;
11031
b3b91714
AM		 11032 case OPTION_DIVIDE:
11033#ifdef SVR4_COMMENT_CHARS
11034 {
11035 char *n, *t;
11036 const char *s;
11037
add39d23 11038 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
b3b91714
AM		 11039 t = n;
11040 for (s = i386_comment_chars; *s != '\0'; s++)
11041 if (*s != '/')
11042 *t++ = *s;
11043 *t = '\0';
11044 i386_comment_chars = n;
11045 }
11046#endif
11047 break;
11048
9103f4f4 11049 case OPTION_MARCH:
293f5f65
L		 11050 saved = xstrdup (arg);
11051 arch = saved;
11052 /* Allow -march=+nosse. */
11053 if (*arch == '+')
11054 arch++;
6305a203 11055 do
9103f4f4 11056 {
6305a203 11057 if (*arch == '.')
2b5d6a91 11058 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 11059 next = strchr (arch, '+');
11060 if (next)
11061 *next++ = '\0';
91d6fa6a 11062 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 11063 {
91d6fa6a 11064 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 11065 {
6305a203 11066 /* Processor. */
1ded5609
JB		 11067 if (! cpu_arch[j].flags.bitfield.cpui386)
11068 continue;
11069
91d6fa6a 11070 cpu_arch_name = cpu_arch[j].name;
6305a203 11071 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 11072 cpu_arch_flags = cpu_arch[j].flags;
11073 cpu_arch_isa = cpu_arch[j].type;
11074 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 11075 if (!cpu_arch_tune_set)
11076 {
11077 cpu_arch_tune = cpu_arch_isa;
11078 cpu_arch_tune_flags = cpu_arch_isa_flags;
11079 }
11080 break;
11081 }
91d6fa6a
NC		 11082 else if (*cpu_arch [j].name == '.'
11083 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203 11084 {
33eaf5de 11085 /* ISA extension. */
6305a203 11086 i386_cpu_flags flags;
309d3373 11087
293f5f65
L		 11088 flags = cpu_flags_or (cpu_arch_flags,
11089 cpu_arch[j].flags);
81486035 11090
5b64d091 11091 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 11092 {
11093 if (cpu_sub_arch_name)
11094 {
11095 char *name = cpu_sub_arch_name;
11096 cpu_sub_arch_name = concat (name,
91d6fa6a 11097 cpu_arch[j].name,
1bf57e9f 11098 (const char *) NULL);
6305a203
L		 11099 free (name);
11100 }
11101 else
91d6fa6a 11102 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 11103 cpu_arch_flags = flags;
a586129e 11104 cpu_arch_isa_flags = flags;
6305a203 11105 }
0089dace
L		 11106 else
11107 cpu_arch_isa_flags
11108 = cpu_flags_or (cpu_arch_isa_flags,
11109 cpu_arch[j].flags);
6305a203 11110 break;
ccc9c027 11111 }
9103f4f4 11112 }
6305a203 11113
293f5f65
L		 11114 if (j >= ARRAY_SIZE (cpu_arch))
11115 {
33eaf5de 11116 /* Disable an ISA extension. */
293f5f65
L		 11117 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
11118 if (strcmp (arch, cpu_noarch [j].name) == 0)
11119 {
11120 i386_cpu_flags flags;
11121
11122 flags = cpu_flags_and_not (cpu_arch_flags,
11123 cpu_noarch[j].flags);
11124 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
11125 {
11126 if (cpu_sub_arch_name)
11127 {
11128 char *name = cpu_sub_arch_name;
11129 cpu_sub_arch_name = concat (arch,
11130 (const char *) NULL);
11131 free (name);
11132 }
11133 else
11134 cpu_sub_arch_name = xstrdup (arch);
11135 cpu_arch_flags = flags;
11136 cpu_arch_isa_flags = flags;
11137 }
11138 break;
11139 }
11140
11141 if (j >= ARRAY_SIZE (cpu_noarch))
11142 j = ARRAY_SIZE (cpu_arch);
11143 }
11144
91d6fa6a 11145 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 11146 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 11147
11148 arch = next;
9103f4f4 11149 }
293f5f65
L		 11150 while (next != NULL);
11151 free (saved);
9103f4f4
L		 11152 break;
11153
11154 case OPTION_MTUNE:
11155 if (*arg == '.')
2b5d6a91 11156 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 11157 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 11158 {
91d6fa6a 11159 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 11160 {
ccc9c027 11161 cpu_arch_tune_set = 1;
91d6fa6a
NC		 11162 cpu_arch_tune = cpu_arch [j].type;
11163 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 11164 break;
11165 }
11166 }
91d6fa6a 11167 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 11168 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 11169 break;
11170
1efbbeb4
L		 11171 case OPTION_MMNEMONIC:
11172 if (strcasecmp (arg, "att") == 0)
11173 intel_mnemonic = 0;
11174 else if (strcasecmp (arg, "intel") == 0)
11175 intel_mnemonic = 1;
11176 else
2b5d6a91 11177 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 11178 break;
11179
11180 case OPTION_MSYNTAX:
11181 if (strcasecmp (arg, "att") == 0)
11182 intel_syntax = 0;
11183 else if (strcasecmp (arg, "intel") == 0)
11184 intel_syntax = 1;
11185 else
2b5d6a91 11186 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 11187 break;
11188
11189 case OPTION_MINDEX_REG:
11190 allow_index_reg = 1;
11191 break;
11192
11193 case OPTION_MNAKED_REG:
11194 allow_naked_reg = 1;
11195 break;
11196
c0f3af97
L		 11197 case OPTION_MSSE2AVX:
11198 sse2avx = 1;
11199 break;
11200
daf50ae7
L		 11201 case OPTION_MSSE_CHECK:
11202 if (strcasecmp (arg, "error") == 0)
7bab8ab5 11203 sse_check = check_error;
daf50ae7 11204 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 11205 sse_check = check_warning;
daf50ae7 11206 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 11207 sse_check = check_none;
daf50ae7 11208 else
2b5d6a91 11209 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 11210 break;
11211
7bab8ab5
JB		 11212 case OPTION_MOPERAND_CHECK:
11213 if (strcasecmp (arg, "error") == 0)
11214 operand_check = check_error;
11215 else if (strcasecmp (arg, "warning") == 0)
11216 operand_check = check_warning;
11217 else if (strcasecmp (arg, "none") == 0)
11218 operand_check = check_none;
11219 else
11220 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
11221 break;
11222
539f890d
L		 11223 case OPTION_MAVXSCALAR:
11224 if (strcasecmp (arg, "128") == 0)
11225 avxscalar = vex128;
11226 else if (strcasecmp (arg, "256") == 0)
11227 avxscalar = vex256;
11228 else
2b5d6a91 11229 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 11230 break;
11231
03751133
L		 11232 case OPTION_MVEXWIG:
11233 if (strcmp (arg, "0") == 0)
11234 vexwig = evexw0;
11235 else if (strcmp (arg, "1") == 0)
11236 vexwig = evexw1;
11237 else
11238 as_fatal (_("invalid -mvexwig= option: `%s'"), arg);
11239 break;
11240
7e8b059b
L		 11241 case OPTION_MADD_BND_PREFIX:
11242 add_bnd_prefix = 1;
11243 break;
11244
43234a1e
L		 11245 case OPTION_MEVEXLIG:
11246 if (strcmp (arg, "128") == 0)
11247 evexlig = evexl128;
11248 else if (strcmp (arg, "256") == 0)
11249 evexlig = evexl256;
11250 else if (strcmp (arg, "512") == 0)
11251 evexlig = evexl512;
11252 else
11253 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
11254 break;
11255
d3d3c6db
IT		 11256 case OPTION_MEVEXRCIG:
11257 if (strcmp (arg, "rne") == 0)
11258 evexrcig = rne;
11259 else if (strcmp (arg, "rd") == 0)
11260 evexrcig = rd;
11261 else if (strcmp (arg, "ru") == 0)
11262 evexrcig = ru;
11263 else if (strcmp (arg, "rz") == 0)
11264 evexrcig = rz;
11265 else
11266 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
11267 break;
11268
43234a1e
L		 11269 case OPTION_MEVEXWIG:
11270 if (strcmp (arg, "0") == 0)
11271 evexwig = evexw0;
11272 else if (strcmp (arg, "1") == 0)
11273 evexwig = evexw1;
11274 else
11275 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
11276 break;
11277
167ad85b
TG		 11278# if defined (TE_PE) || defined (TE_PEP)
11279 case OPTION_MBIG_OBJ:
11280 use_big_obj = 1;
11281 break;
11282#endif
11283
d1982f93 11284 case OPTION_MOMIT_LOCK_PREFIX:
d022bddd
IT		 11285 if (strcasecmp (arg, "yes") == 0)
11286 omit_lock_prefix = 1;
11287 else if (strcasecmp (arg, "no") == 0)
11288 omit_lock_prefix = 0;
11289 else
11290 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
11291 break;
11292
e4e00185
AS		 11293 case OPTION_MFENCE_AS_LOCK_ADD:
11294 if (strcasecmp (arg, "yes") == 0)
11295 avoid_fence = 1;
11296 else if (strcasecmp (arg, "no") == 0)
11297 avoid_fence = 0;
11298 else
11299 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
11300 break;
11301
0cb4071e
L		 11302 case OPTION_MRELAX_RELOCATIONS:
11303 if (strcasecmp (arg, "yes") == 0)
11304 generate_relax_relocations = 1;
11305 else if (strcasecmp (arg, "no") == 0)
11306 generate_relax_relocations = 0;
11307 else
11308 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
11309 break;
11310
5db04b09 11311 case OPTION_MAMD64:
e89c5eaa 11312 intel64 = 0;
5db04b09
L		 11313 break;
11314
11315 case OPTION_MINTEL64:
e89c5eaa 11316 intel64 = 1;
5db04b09
L		 11317 break;
11318
b6f8c7c4
L		 11319 case 'O':
11320 if (arg == NULL)
11321 {
11322 optimize = 1;
11323 /* Turn off -Os. */
11324 optimize_for_space = 0;
11325 }
11326 else if (*arg == 's')
11327 {
11328 optimize_for_space = 1;
11329 /* Turn on all encoding optimizations. */
11330 optimize = -1;
11331 }
11332 else
11333 {
11334 optimize = atoi (arg);
11335 /* Turn off -Os. */
11336 optimize_for_space = 0;
11337 }
11338 break;
11339
252b5132
RH		 11340 default:
11341 return 0;
11342 }
11343 return 1;
11344}
11345
8a2c8fef
L		 11346#define MESSAGE_TEMPLATE \
11347" "
11348
293f5f65
L		 11349static char *
11350output_message (FILE *stream, char *p, char *message, char *start,
11351 int *left_p, const char *name, int len)
11352{
11353 int size = sizeof (MESSAGE_TEMPLATE);
11354 int left = *left_p;
11355
11356 /* Reserve 2 spaces for ", " or ",\0" */
11357 left -= len + 2;
11358
11359 /* Check if there is any room. */
11360 if (left >= 0)
11361 {
11362 if (p != start)
11363 {
11364 *p++ = ',';
11365 *p++ = ' ';
11366 }
11367 p = mempcpy (p, name, len);
11368 }
11369 else
11370 {
11371 /* Output the current message now and start a new one. */
11372 *p++ = ',';
11373 *p = '\0';
11374 fprintf (stream, "%s\n", message);
11375 p = start;
11376 left = size - (start - message) - len - 2;
11377
11378 gas_assert (left >= 0);
11379
11380 p = mempcpy (p, name, len);
11381 }
11382
11383 *left_p = left;
11384 return p;
11385}
11386
8a2c8fef 11387static void
1ded5609 11388show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 11389{
11390 static char message[] = MESSAGE_TEMPLATE;
11391 char *start = message + 27;
11392 char *p;
11393 int size = sizeof (MESSAGE_TEMPLATE);
11394 int left;
11395 const char *name;
11396 int len;
11397 unsigned int j;
11398
11399 p = start;
11400 left = size - (start - message);
11401 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
11402 {
11403 /* Should it be skipped? */
11404 if (cpu_arch [j].skip)
11405 continue;
11406
11407 name = cpu_arch [j].name;
11408 len = cpu_arch [j].len;
11409 if (*name == '.')
11410 {
11411 /* It is an extension. Skip if we aren't asked to show it. */
11412 if (ext)
11413 {
11414 name++;
11415 len--;
11416 }
11417 else
11418 continue;
11419 }
11420 else if (ext)
11421 {
11422 /* It is an processor. Skip if we show only extension. */
11423 continue;
11424 }
1ded5609
JB		 11425 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
11426 {
11427 /* It is an impossible processor - skip. */
11428 continue;
11429 }
8a2c8fef 11430
293f5f65 11431 p = output_message (stream, p, message, start, &left, name, len);
8a2c8fef
L		 11432 }
11433
293f5f65
L		 11434 /* Display disabled extensions. */
11435 if (ext)
11436 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
11437 {
11438 name = cpu_noarch [j].name;
11439 len = cpu_noarch [j].len;
11440 p = output_message (stream, p, message, start, &left, name,
11441 len);
11442 }
11443
8a2c8fef
L		 11444 *p = '\0';
11445 fprintf (stream, "%s\n", message);
11446}
11447
252b5132 11448void
8a2c8fef 11449md_show_usage (FILE *stream)
252b5132 11450{
4cc782b5
ILT		 11451#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11452 fprintf (stream, _("\
a38cf1db
AM		 11453 -Q ignored\n\
11454 -V print assembler version number\n\
b3b91714
AM		 11455 -k ignored\n"));
11456#endif
11457 fprintf (stream, _("\
12b55ccc 11458 -n Do not optimize code alignment\n\
b3b91714
AM		 11459 -q quieten some warnings\n"));
11460#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11461 fprintf (stream, _("\
a38cf1db 11462 -s ignored\n"));
b3b91714 11463#endif
d7f449c0
L		 11464#if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11465 || defined (TE_PE) || defined (TE_PEP))
751d281c 11466 fprintf (stream, _("\
570561f7 11467 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 11468#endif
b3b91714
AM		 11469#ifdef SVR4_COMMENT_CHARS
11470 fprintf (stream, _("\
11471 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 11472#else
11473 fprintf (stream, _("\
b3b91714 11474 --divide ignored\n"));
4cc782b5 11475#endif
9103f4f4 11476 fprintf (stream, _("\
6305a203 11477 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 11478 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 11479 show_arch (stream, 0, 1);
8a2c8fef
L		 11480 fprintf (stream, _("\
11481 EXTENSION is combination of:\n"));
1ded5609 11482 show_arch (stream, 1, 0);
6305a203 11483 fprintf (stream, _("\
8a2c8fef 11484 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 11485 show_arch (stream, 0, 0);
ba104c83 11486 fprintf (stream, _("\
c0f3af97
L		 11487 -msse2avx encode SSE instructions with VEX prefix\n"));
11488 fprintf (stream, _("\
7c5c05ef 11489 -msse-check=[none|error|warning] (default: warning)\n\
daf50ae7
L		 11490 check SSE instructions\n"));
11491 fprintf (stream, _("\
7c5c05ef 11492 -moperand-check=[none|error|warning] (default: warning)\n\
7bab8ab5
JB		 11493 check operand combinations for validity\n"));
11494 fprintf (stream, _("\
7c5c05ef
L		 11495 -mavxscalar=[128|256] (default: 128)\n\
11496 encode scalar AVX instructions with specific vector\n\
539f890d
L		 11497 length\n"));
11498 fprintf (stream, _("\
03751133
L		 11499 -mvexwig=[0|1] (default: 0)\n\
11500 encode VEX instructions with specific VEX.W value\n\
11501 for VEX.W bit ignored instructions\n"));
11502 fprintf (stream, _("\
7c5c05ef
L		 11503 -mevexlig=[128|256|512] (default: 128)\n\
11504 encode scalar EVEX instructions with specific vector\n\
43234a1e
L		 11505 length\n"));
11506 fprintf (stream, _("\
7c5c05ef
L		 11507 -mevexwig=[0|1] (default: 0)\n\
11508 encode EVEX instructions with specific EVEX.W value\n\
43234a1e
L		 11509 for EVEX.W bit ignored instructions\n"));
11510 fprintf (stream, _("\
7c5c05ef 11511 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
d3d3c6db
IT		 11512 encode EVEX instructions with specific EVEX.RC value\n\
11513 for SAE-only ignored instructions\n"));
11514 fprintf (stream, _("\
7c5c05ef
L		 11515 -mmnemonic=[att|intel] "));
11516 if (SYSV386_COMPAT)
11517 fprintf (stream, _("(default: att)\n"));
11518 else
11519 fprintf (stream, _("(default: intel)\n"));
11520 fprintf (stream, _("\
11521 use AT&T/Intel mnemonic\n"));
ba104c83 11522 fprintf (stream, _("\
7c5c05ef
L		 11523 -msyntax=[att|intel] (default: att)\n\
11524 use AT&T/Intel syntax\n"));
ba104c83
L		 11525 fprintf (stream, _("\
11526 -mindex-reg support pseudo index registers\n"));
11527 fprintf (stream, _("\
11528 -mnaked-reg don't require `%%' prefix for registers\n"));
11529 fprintf (stream, _("\
7e8b059b 11530 -madd-bnd-prefix add BND prefix for all valid branches\n"));
b4a3a7b4 11531#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8dcea932
L		 11532 fprintf (stream, _("\
11533 -mshared disable branch optimization for shared code\n"));
b4a3a7b4
L		 11534 fprintf (stream, _("\
11535 -mx86-used-note=[no|yes] "));
11536 if (DEFAULT_X86_USED_NOTE)
11537 fprintf (stream, _("(default: yes)\n"));
11538 else
11539 fprintf (stream, _("(default: no)\n"));
11540 fprintf (stream, _("\
11541 generate x86 used ISA and feature properties\n"));
11542#endif
11543#if defined (TE_PE) || defined (TE_PEP)
167ad85b
TG		 11544 fprintf (stream, _("\
11545 -mbig-obj generate big object files\n"));
11546#endif
d022bddd 11547 fprintf (stream, _("\
7c5c05ef 11548 -momit-lock-prefix=[no|yes] (default: no)\n\
d022bddd 11549 strip all lock prefixes\n"));
5db04b09 11550 fprintf (stream, _("\
7c5c05ef 11551 -mfence-as-lock-add=[no|yes] (default: no)\n\
e4e00185
AS		 11552 encode lfence, mfence and sfence as\n\
11553 lock addl $0x0, (%%{re}sp)\n"));
11554 fprintf (stream, _("\
7c5c05ef
L		 11555 -mrelax-relocations=[no|yes] "));
11556 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS)
11557 fprintf (stream, _("(default: yes)\n"));
11558 else
11559 fprintf (stream, _("(default: no)\n"));
11560 fprintf (stream, _("\
0cb4071e
L		 11561 generate relax relocations\n"));
11562 fprintf (stream, _("\
7c5c05ef 11563 -mamd64 accept only AMD64 ISA [default]\n"));
5db04b09
L		 11564 fprintf (stream, _("\
11565 -mintel64 accept only Intel64 ISA\n"));
252b5132
RH		 11566}
11567
3e73aa7c 11568#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 11569 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 11570 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 11571
11572/* Pick the target format to use. */
11573
47926f60 11574const char *
e3bb37b5 11575i386_target_format (void)
252b5132 11576{
351f65ca
L		 11577 if (!strncmp (default_arch, "x86_64", 6))
11578 {
11579 update_code_flag (CODE_64BIT, 1);
11580 if (default_arch[6] == '\0')
7f56bc95 11581 x86_elf_abi = X86_64_ABI;
351f65ca 11582 else
7f56bc95 11583 x86_elf_abi = X86_64_X32_ABI;
351f65ca 11584 }
3e73aa7c 11585 else if (!strcmp (default_arch, "i386"))
78f12dd3 11586 update_code_flag (CODE_32BIT, 1);
5197d474
L		 11587 else if (!strcmp (default_arch, "iamcu"))
11588 {
11589 update_code_flag (CODE_32BIT, 1);
11590 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
11591 {
11592 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
11593 cpu_arch_name = "iamcu";
11594 cpu_sub_arch_name = NULL;
11595 cpu_arch_flags = iamcu_flags;
11596 cpu_arch_isa = PROCESSOR_IAMCU;
11597 cpu_arch_isa_flags = iamcu_flags;
11598 if (!cpu_arch_tune_set)
11599 {
11600 cpu_arch_tune = cpu_arch_isa;
11601 cpu_arch_tune_flags = cpu_arch_isa_flags;
11602 }
11603 }
8d471ec1 11604 else if (cpu_arch_isa != PROCESSOR_IAMCU)
5197d474
L		 11605 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11606 cpu_arch_name);
11607 }
3e73aa7c 11608 else
2b5d6a91 11609 as_fatal (_("unknown architecture"));
89507696
JB		 11610
11611 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
11612 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11613 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
11614 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11615
252b5132
RH		 11616 switch (OUTPUT_FLAVOR)
11617 {
9384f2ff 11618#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 11619 case bfd_target_aout_flavour:
47926f60 11620 return AOUT_TARGET_FORMAT;
4c63da97 11621#endif
9384f2ff
AM		 11622#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11623# if defined (TE_PE) || defined (TE_PEP)
11624 case bfd_target_coff_flavour:
167ad85b
TG		 11625 if (flag_code == CODE_64BIT)
11626 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
11627 else
11628 return "pe-i386";
9384f2ff 11629# elif defined (TE_GO32)
0561d57c
JK		 11630 case bfd_target_coff_flavour:
11631 return "coff-go32";
9384f2ff 11632# else
252b5132
RH		 11633 case bfd_target_coff_flavour:
11634 return "coff-i386";
9384f2ff 11635# endif
4c63da97 11636#endif
3e73aa7c 11637#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 11638 case bfd_target_elf_flavour:
3e73aa7c 11639 {
351f65ca
L		 11640 const char *format;
11641
11642 switch (x86_elf_abi)
4fa24527 11643 {
351f65ca
L		 11644 default:
11645 format = ELF_TARGET_FORMAT;
11646 break;
7f56bc95 11647 case X86_64_ABI:
351f65ca 11648 use_rela_relocations = 1;
4fa24527 11649 object_64bit = 1;
351f65ca
L		 11650 format = ELF_TARGET_FORMAT64;
11651 break;
7f56bc95 11652 case X86_64_X32_ABI:
4fa24527 11653 use_rela_relocations = 1;
351f65ca 11654 object_64bit = 1;
862be3fb 11655 disallow_64bit_reloc = 1;
351f65ca
L		 11656 format = ELF_TARGET_FORMAT32;
11657 break;
4fa24527 11658 }
3632d14b 11659 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 11660 {
7f56bc95 11661 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 11662 as_fatal (_("Intel L1OM is 64bit only"));
11663 return ELF_TARGET_L1OM_FORMAT;
11664 }
b49f93f6 11665 else if (cpu_arch_isa == PROCESSOR_K1OM)
7a9068fe
L		 11666 {
11667 if (x86_elf_abi != X86_64_ABI)
11668 as_fatal (_("Intel K1OM is 64bit only"));
11669 return ELF_TARGET_K1OM_FORMAT;
11670 }
81486035
L		 11671 else if (cpu_arch_isa == PROCESSOR_IAMCU)
11672 {
11673 if (x86_elf_abi != I386_ABI)
11674 as_fatal (_("Intel MCU is 32bit only"));
11675 return ELF_TARGET_IAMCU_FORMAT;
11676 }
8a9036a4 11677 else
351f65ca 11678 return format;
3e73aa7c 11679 }
e57f8c65
TG		 11680#endif
11681#if defined (OBJ_MACH_O)
11682 case bfd_target_mach_o_flavour:
d382c579
TG		 11683 if (flag_code == CODE_64BIT)
11684 {
11685 use_rela_relocations = 1;
11686 object_64bit = 1;
11687 return "mach-o-x86-64";
11688 }
11689 else
11690 return "mach-o-i386";
4c63da97 11691#endif
252b5132
RH		 11692 default:
11693 abort ();
11694 return NULL;
11695 }
11696}
11697
47926f60 11698#endif /* OBJ_MAYBE_ more than one */
252b5132 11699\f
252b5132 11700symbolS *
7016a5d5 11701md_undefined_symbol (char *name)
252b5132 11702{
18dc2407
ILT		 11703 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
11704 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
11705 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
11706 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 11707 {
11708 if (!GOT_symbol)
11709 {
11710 if (symbol_find (name))
11711 as_bad (_("GOT already in symbol table"));
11712 GOT_symbol = symbol_new (name, undefined_section,
11713 (valueT) 0, &zero_address_frag);
11714 };
11715 return GOT_symbol;
11716 }
252b5132
RH		 11717 return 0;
11718}
11719
11720/* Round up a section size to the appropriate boundary. */
47926f60 11721
252b5132 11722valueT
7016a5d5 11723md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 11724{
4c63da97
AM		 11725#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11726 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
11727 {
11728 /* For a.out, force the section size to be aligned. If we don't do
11729 this, BFD will align it for us, but it will not write out the
11730 final bytes of the section. This may be a bug in BFD, but it is
11731 easier to fix it here since that is how the other a.out targets
11732 work. */
11733 int align;
11734
11735 align = bfd_get_section_alignment (stdoutput, segment);
8d3842cd 11736 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
4c63da97 11737 }
252b5132
RH		 11738#endif
11739
11740 return size;
11741}
11742
11743/* On the i386, PC-relative offsets are relative to the start of the
11744 next instruction. That is, the address of the offset, plus its
11745 size, since the offset is always the last part of the insn. */
11746
11747long
e3bb37b5 11748md_pcrel_from (fixS *fixP)
252b5132
RH		 11749{
11750 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
11751}
11752
11753#ifndef I386COFF
11754
11755static void
e3bb37b5 11756s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 11757{
29b0f896 11758 int temp;
252b5132 11759
8a75718c
JB		 11760#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11761 if (IS_ELF)
11762 obj_elf_section_change_hook ();
11763#endif
252b5132
RH		 11764 temp = get_absolute_expression ();
11765 subseg_set (bss_section, (subsegT) temp);
11766 demand_empty_rest_of_line ();
11767}
11768
11769#endif
11770
252b5132 11771void
e3bb37b5 11772i386_validate_fix (fixS *fixp)
252b5132 11773{
02a86693 11774 if (fixp->fx_subsy)
252b5132 11775 {
02a86693 11776 if (fixp->fx_subsy == GOT_symbol)
23df1078 11777 {
02a86693
L		 11778 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
11779 {
11780 if (!object_64bit)
11781 abort ();
11782#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11783 if (fixp->fx_tcbit2)
56ceb5b5
L		 11784 fixp->fx_r_type = (fixp->fx_tcbit
11785 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11786 : BFD_RELOC_X86_64_GOTPCRELX);
02a86693
L		 11787 else
11788#endif
11789 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
11790 }
d6ab8113 11791 else
02a86693
L		 11792 {
11793 if (!object_64bit)
11794 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
11795 else
11796 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
11797 }
11798 fixp->fx_subsy = 0;
23df1078 11799 }
252b5132 11800 }
02a86693
L		 11801#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11802 else if (!object_64bit)
11803 {
11804 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
11805 && fixp->fx_tcbit2)
11806 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
11807 }
11808#endif
252b5132
RH		 11809}
11810
252b5132 11811arelent *
7016a5d5 11812tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 11813{
11814 arelent *rel;
11815 bfd_reloc_code_real_type code;
11816
11817 switch (fixp->fx_r_type)
11818 {
8ce3d284 11819#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 11820 case BFD_RELOC_SIZE32:
11821 case BFD_RELOC_SIZE64:
11822 if (S_IS_DEFINED (fixp->fx_addsy)
11823 && !S_IS_EXTERNAL (fixp->fx_addsy))
11824 {
11825 /* Resolve size relocation against local symbol to size of
11826 the symbol plus addend. */
11827 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
11828 if (fixp->fx_r_type == BFD_RELOC_SIZE32
11829 && !fits_in_unsigned_long (value))
11830 as_bad_where (fixp->fx_file, fixp->fx_line,
11831 _("symbol size computation overflow"));
11832 fixp->fx_addsy = NULL;
11833 fixp->fx_subsy = NULL;
11834 md_apply_fix (fixp, (valueT *) &value, NULL);
11835 return NULL;
11836 }
8ce3d284 11837#endif
1a0670f3 11838 /* Fall through. */
8fd4256d 11839
3e73aa7c
JH		 11840 case BFD_RELOC_X86_64_PLT32:
11841 case BFD_RELOC_X86_64_GOT32:
11842 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 11843 case BFD_RELOC_X86_64_GOTPCRELX:
11844 case BFD_RELOC_X86_64_REX_GOTPCRELX:
252b5132
RH		 11845 case BFD_RELOC_386_PLT32:
11846 case BFD_RELOC_386_GOT32:
02a86693 11847 case BFD_RELOC_386_GOT32X:
252b5132
RH		 11848 case BFD_RELOC_386_GOTOFF:
11849 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 11850 case BFD_RELOC_386_TLS_GD:
11851 case BFD_RELOC_386_TLS_LDM:
11852 case BFD_RELOC_386_TLS_LDO_32:
11853 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 11854 case BFD_RELOC_386_TLS_IE:
11855 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 11856 case BFD_RELOC_386_TLS_LE_32:
11857 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 11858 case BFD_RELOC_386_TLS_GOTDESC:
11859 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 11860 case BFD_RELOC_X86_64_TLSGD:
11861 case BFD_RELOC_X86_64_TLSLD:
11862 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 11863 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 11864 case BFD_RELOC_X86_64_GOTTPOFF:
11865 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 11866 case BFD_RELOC_X86_64_TPOFF64:
11867 case BFD_RELOC_X86_64_GOTOFF64:
11868 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 11869 case BFD_RELOC_X86_64_GOT64:
11870 case BFD_RELOC_X86_64_GOTPCREL64:
11871 case BFD_RELOC_X86_64_GOTPC64:
11872 case BFD_RELOC_X86_64_GOTPLT64:
11873 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 11874 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11875 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 11876 case BFD_RELOC_RVA:
11877 case BFD_RELOC_VTABLE_ENTRY:
11878 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 11879#ifdef TE_PE
11880 case BFD_RELOC_32_SECREL:
11881#endif
252b5132
RH		 11882 code = fixp->fx_r_type;
11883 break;
dbbaec26
L		 11884 case BFD_RELOC_X86_64_32S:
11885 if (!fixp->fx_pcrel)
11886 {
11887 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11888 code = fixp->fx_r_type;
11889 break;
11890 }
1a0670f3 11891 /* Fall through. */
252b5132 11892 default:
93382f6d 11893 if (fixp->fx_pcrel)
252b5132 11894 {
93382f6d
AM		 11895 switch (fixp->fx_size)
11896 {
11897 default:
b091f402
AM		 11898 as_bad_where (fixp->fx_file, fixp->fx_line,
11899 _("can not do %d byte pc-relative relocation"),
11900 fixp->fx_size);
93382f6d
AM		 11901 code = BFD_RELOC_32_PCREL;
11902 break;
11903 case 1: code = BFD_RELOC_8_PCREL; break;
11904 case 2: code = BFD_RELOC_16_PCREL; break;
d258b828 11905 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 11906#ifdef BFD64
11907 case 8: code = BFD_RELOC_64_PCREL; break;
11908#endif
93382f6d
AM		 11909 }
11910 }
11911 else
11912 {
11913 switch (fixp->fx_size)
11914 {
11915 default:
b091f402
AM		 11916 as_bad_where (fixp->fx_file, fixp->fx_line,
11917 _("can not do %d byte relocation"),
11918 fixp->fx_size);
93382f6d
AM		 11919 code = BFD_RELOC_32;
11920 break;
11921 case 1: code = BFD_RELOC_8; break;
11922 case 2: code = BFD_RELOC_16; break;
11923 case 4: code = BFD_RELOC_32; break;
937149dd 11924#ifdef BFD64
3e73aa7c 11925 case 8: code = BFD_RELOC_64; break;
937149dd 11926#endif
93382f6d 11927 }
252b5132
RH		 11928 }
11929 break;
11930 }
252b5132 11931
d182319b
JB		 11932 if ((code == BFD_RELOC_32
11933 || code == BFD_RELOC_32_PCREL
11934 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 11935 && GOT_symbol
11936 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 11937 {
4fa24527 11938 if (!object_64bit)
d6ab8113
JB		 11939 code = BFD_RELOC_386_GOTPC;
11940 else
11941 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 11942 }
7b81dfbb
AJ		 11943 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
11944 && GOT_symbol
11945 && fixp->fx_addsy == GOT_symbol)
11946 {
11947 code = BFD_RELOC_X86_64_GOTPC64;
11948 }
252b5132 11949
add39d23
TS		 11950 rel = XNEW (arelent);
11951 rel->sym_ptr_ptr = XNEW (asymbol *);
49309057 11952 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 11953
11954 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 11955
3e73aa7c
JH		 11956 if (!use_rela_relocations)
11957 {
11958 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11959 vtable entry to be used in the relocation's section offset. */
11960 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
11961 rel->address = fixp->fx_offset;
fbeb56a4
DK		 11962#if defined (OBJ_COFF) && defined (TE_PE)
11963 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
11964 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
11965 else
11966#endif
c6682705 11967 rel->addend = 0;
3e73aa7c
JH		 11968 }
11969 /* Use the rela in 64bit mode. */
252b5132 11970 else
3e73aa7c 11971 {
862be3fb
L		 11972 if (disallow_64bit_reloc)
11973 switch (code)
11974 {
862be3fb
L		 11975 case BFD_RELOC_X86_64_DTPOFF64:
11976 case BFD_RELOC_X86_64_TPOFF64:
11977 case BFD_RELOC_64_PCREL:
11978 case BFD_RELOC_X86_64_GOTOFF64:
11979 case BFD_RELOC_X86_64_GOT64:
11980 case BFD_RELOC_X86_64_GOTPCREL64:
11981 case BFD_RELOC_X86_64_GOTPC64:
11982 case BFD_RELOC_X86_64_GOTPLT64:
11983 case BFD_RELOC_X86_64_PLTOFF64:
11984 as_bad_where (fixp->fx_file, fixp->fx_line,
11985 _("cannot represent relocation type %s in x32 mode"),
11986 bfd_get_reloc_code_name (code));
11987 break;
11988 default:
11989 break;
11990 }
11991
062cd5e7
AS		 11992 if (!fixp->fx_pcrel)
11993 rel->addend = fixp->fx_offset;
11994 else
11995 switch (code)
11996 {
11997 case BFD_RELOC_X86_64_PLT32:
11998 case BFD_RELOC_X86_64_GOT32:
11999 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 12000 case BFD_RELOC_X86_64_GOTPCRELX:
12001 case BFD_RELOC_X86_64_REX_GOTPCRELX:
bffbf940
JJ		 12002 case BFD_RELOC_X86_64_TLSGD:
12003 case BFD_RELOC_X86_64_TLSLD:
12004 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 12005 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
12006 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 12007 rel->addend = fixp->fx_offset - fixp->fx_size;
12008 break;
12009 default:
12010 rel->addend = (section->vma
12011 - fixp->fx_size
12012 + fixp->fx_addnumber
12013 + md_pcrel_from (fixp));
12014 break;
12015 }
3e73aa7c
JH		 12016 }
12017
252b5132
RH		 12018 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
12019 if (rel->howto == NULL)
12020 {
12021 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 12022 _("cannot represent relocation type %s"),
252b5132
RH		 12023 bfd_get_reloc_code_name (code));
12024 /* Set howto to a garbage value so that we can keep going. */
12025 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 12026 gas_assert (rel->howto != NULL);
252b5132
RH		 12027 }
12028
12029 return rel;
12030}
12031
ee86248c 12032#include "tc-i386-intel.c"
54cfded0 12033
a60de03c
JB		 12034void
12035tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 12036{
a60de03c
JB		 12037 int saved_naked_reg;
12038 char saved_register_dot;
54cfded0 12039
a60de03c
JB		 12040 saved_naked_reg = allow_naked_reg;
12041 allow_naked_reg = 1;
12042 saved_register_dot = register_chars['.'];
12043 register_chars['.'] = '.';
12044 allow_pseudo_reg = 1;
12045 expression_and_evaluate (exp);
12046 allow_pseudo_reg = 0;
12047 register_chars['.'] = saved_register_dot;
12048 allow_naked_reg = saved_naked_reg;
12049
e96d56a1 12050 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 12051 {
a60de03c
JB		 12052 if ((addressT) exp->X_add_number < i386_regtab_size)
12053 {
12054 exp->X_op = O_constant;
12055 exp->X_add_number = i386_regtab[exp->X_add_number]
12056 .dw2_regnum[flag_code >> 1];
12057 }
12058 else
12059 exp->X_op = O_illegal;
54cfded0 12060 }
54cfded0
AM		 12061}
12062
12063void
12064tc_x86_frame_initial_instructions (void)
12065{
a60de03c
JB		 12066 static unsigned int sp_regno[2];
12067
12068 if (!sp_regno[flag_code >> 1])
12069 {
12070 char *saved_input = input_line_pointer;
12071 char sp[][4] = {"esp", "rsp"};
12072 expressionS exp;
a4447b93 12073
a60de03c
JB		 12074 input_line_pointer = sp[flag_code >> 1];
12075 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 12076 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 12077 sp_regno[flag_code >> 1] = exp.X_add_number;
12078 input_line_pointer = saved_input;
12079 }
a4447b93 12080
61ff971f
L		 12081 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
12082 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 12083}
d2b2c203 12084
d7921315
L		 12085int
12086x86_dwarf2_addr_size (void)
12087{
12088#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
12089 if (x86_elf_abi == X86_64_X32_ABI)
12090 return 4;
12091#endif
12092 return bfd_arch_bits_per_address (stdoutput) / 8;
12093}
12094
d2b2c203
DJ		 12095int
12096i386_elf_section_type (const char *str, size_t len)
12097{
12098 if (flag_code == CODE_64BIT
12099 && len == sizeof ("unwind") - 1
12100 && strncmp (str, "unwind", 6) == 0)
12101 return SHT_X86_64_UNWIND;
12102
12103 return -1;
12104}
bb41ade5 12105
ad5fec3b
EB		 12106#ifdef TE_SOLARIS
12107void
12108i386_solaris_fix_up_eh_frame (segT sec)
12109{
12110 if (flag_code == CODE_64BIT)
12111 elf_section_type (sec) = SHT_X86_64_UNWIND;
12112}
12113#endif
12114
bb41ade5
AM		 12115#ifdef TE_PE
12116void
12117tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
12118{
91d6fa6a 12119 expressionS exp;
bb41ade5 12120
91d6fa6a
NC		 12121 exp.X_op = O_secrel;
12122 exp.X_add_symbol = symbol;
12123 exp.X_add_number = 0;
12124 emit_expr (&exp, size);
bb41ade5
AM		 12125}
12126#endif
3b22753a
L		 12127
12128#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12129/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
12130
01e1a5bc 12131bfd_vma
6d4af3c2 12132x86_64_section_letter (int letter, const char **ptr_msg)
3b22753a
L		 12133{
12134 if (flag_code == CODE_64BIT)
12135 {
12136 if (letter == 'l')
12137 return SHF_X86_64_LARGE;
12138
8f3bae45 12139 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 12140 }
3b22753a 12141 else
8f3bae45 12142 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 12143 return -1;
12144}
12145
01e1a5bc 12146bfd_vma
3b22753a
L		 12147x86_64_section_word (char *str, size_t len)
12148{
8620418b 12149 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 12150 return SHF_X86_64_LARGE;
12151
12152 return -1;
12153}
12154
12155static void
12156handle_large_common (int small ATTRIBUTE_UNUSED)
12157{
12158 if (flag_code != CODE_64BIT)
12159 {
12160 s_comm_internal (0, elf_common_parse);
12161 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
12162 }
12163 else
12164 {
12165 static segT lbss_section;
12166 asection *saved_com_section_ptr = elf_com_section_ptr;
12167 asection *saved_bss_section = bss_section;
12168
12169 if (lbss_section == NULL)
12170 {
12171 flagword applicable;
12172 segT seg = now_seg;
12173 subsegT subseg = now_subseg;
12174
12175 /* The .lbss section is for local .largecomm symbols. */
12176 lbss_section = subseg_new (".lbss", 0);
12177 applicable = bfd_applicable_section_flags (stdoutput);
12178 bfd_set_section_flags (stdoutput, lbss_section,
12179 applicable & SEC_ALLOC);
12180 seg_info (lbss_section)->bss = 1;
12181
12182 subseg_set (seg, subseg);
12183 }
12184
12185 elf_com_section_ptr = &_bfd_elf_large_com_section;
12186 bss_section = lbss_section;
12187
12188 s_comm_internal (0, elf_common_parse);
12189
12190 elf_com_section_ptr = saved_com_section_ptr;
12191 bss_section = saved_bss_section;
12192 }
12193}
12194#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
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