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* Makefile.in (install-python): Add DESTDIR.
[binutils.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
c75ef631 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus ([email protected]).
3e73aa7c 25 x86_64 support by Jan Hubicka ([email protected])
0f10071e 26 VIA PadLock support by Michal Ludvig ([email protected])
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
40fb9820 36#include "opcodes/i386-init.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
29b0f896
AM		 46#ifndef DEFAULT_ARCH
47#define DEFAULT_ARCH "i386"
246fcdee 48#endif
252b5132 49
edde18a5
AM		 50#ifndef INLINE
51#if __GNUC__ >= 2
52#define INLINE __inline__
53#else
54#define INLINE
55#endif
56#endif
57
6305a203
L		 58/* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
c32fa91d 62 REP_PREFIX, LOCK_PREFIX. */
6305a203
L		 63#define WAIT_PREFIX 0
64#define SEG_PREFIX 1
65#define ADDR_PREFIX 2
66#define DATA_PREFIX 3
c32fa91d
L		 67#define REP_PREFIX 4
68#define LOCK_PREFIX 5
69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
84#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 85#define YMMWORD_MNEM_SUFFIX 'y'
6305a203
L		 86/* Intel Syntax. Use a non-ascii letter since since it never appears
87 in instructions. */
88#define LONG_DOUBLE_MNEM_SUFFIX '\1'
89
90#define END_OF_INSN '\0'
91
92/*
93 'templates' is for grouping together 'template' structures for opcodes
94 of the same name. This is only used for storing the insns in the grand
95 ole hash table of insns.
96 The templates themselves start at START and range up to (but not including)
97 END.
98 */
99typedef struct
100{
d3ce72d0
NC		 101 const insn_template *start;
102 const insn_template *end;
6305a203
L		 103}
104templates;
105
106/* 386 operand encoding bytes: see 386 book for details of this. */
107typedef struct
108{
109 unsigned int regmem; /* codes register or memory operand */
110 unsigned int reg; /* codes register operand (or extended opcode) */
111 unsigned int mode; /* how to interpret regmem & reg */
112}
113modrm_byte;
114
115/* x86-64 extension prefix. */
116typedef int rex_byte;
117
6305a203
L		 118/* 386 opcode byte to code indirect addressing. */
119typedef struct
120{
121 unsigned base;
122 unsigned index;
123 unsigned scale;
124}
125sib_byte;
126
6305a203
L		 127/* x86 arch names, types and features */
128typedef struct
129{
130 const char *name; /* arch name */
8a2c8fef 131 unsigned int len; /* arch string length */
6305a203
L		 132 enum processor_type type; /* arch type */
133 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 134 unsigned int skip; /* show_arch should skip this. */
22109423 135 unsigned int negated; /* turn off indicated flags. */
6305a203
L		 136}
137arch_entry;
138
78f12dd3 139static void update_code_flag (int, int);
e3bb37b5
L		 140static void set_code_flag (int);
141static void set_16bit_gcc_code_flag (int);
142static void set_intel_syntax (int);
1efbbeb4 143static void set_intel_mnemonic (int);
db51cc60 144static void set_allow_index_reg (int);
cb19c032 145static void set_sse_check (int);
e3bb37b5 146static void set_cpu_arch (int);
6482c264 147#ifdef TE_PE
e3bb37b5 148static void pe_directive_secrel (int);
6482c264 149#endif
e3bb37b5
L		 150static void signed_cons (int);
151static char *output_invalid (int c);
ee86248c
JB		 152static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
153 const char *);
154static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
155 const char *);
a7619375 156static int i386_att_operand (char *);
e3bb37b5 157static int i386_intel_operand (char *, int);
ee86248c
JB		 158static int i386_intel_simplify (expressionS *);
159static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 160static const reg_entry *parse_register (char *, char **);
161static char *parse_insn (char *, char *);
162static char *parse_operands (char *, const char *);
163static void swap_operands (void);
4d456e3d 164static void swap_2_operands (int, int);
e3bb37b5
L		 165static void optimize_imm (void);
166static void optimize_disp (void);
d3ce72d0 167static const insn_template *match_template (void);
e3bb37b5
L		 168static int check_string (void);
169static int process_suffix (void);
170static int check_byte_reg (void);
171static int check_long_reg (void);
172static int check_qword_reg (void);
173static int check_word_reg (void);
174static int finalize_imm (void);
175static int process_operands (void);
176static const seg_entry *build_modrm_byte (void);
177static void output_insn (void);
178static void output_imm (fragS *, offsetT);
179static void output_disp (fragS *, offsetT);
29b0f896 180#ifndef I386COFF
e3bb37b5 181static void s_bss (int);
252b5132 182#endif
17d4e2a2
L		 183#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
184static void handle_large_common (int small ATTRIBUTE_UNUSED);
185#endif
252b5132 186
a847613f 187static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 188
c0f3af97
L		 189/* VEX prefix. */
190typedef struct
191{
192 /* VEX prefix is either 2 byte or 3 byte. */
193 unsigned char bytes[3];
194 unsigned int length;
195 /* Destination or source register specifier. */
196 const reg_entry *register_specifier;
197} vex_prefix;
198
252b5132 199/* 'md_assemble ()' gathers together information and puts it into a
47926f60 200 i386_insn. */
252b5132 201
520dc8e8
AM		 202union i386_op
203 {
204 expressionS *disps;
205 expressionS *imms;
206 const reg_entry *regs;
207 };
208
a65babc9
L		 209enum i386_error
210 {
86e026a4 211 operand_size_mismatch,
a65babc9
L		 212 operand_type_mismatch,
213 register_type_mismatch,
214 number_of_operands_mismatch,
215 invalid_instruction_suffix,
216 bad_imm4,
217 old_gcc_only,
218 unsupported_with_intel_mnemonic,
219 unsupported_syntax,
220 unsupported
221 };
222
252b5132
RH		 223struct _i386_insn
224 {
47926f60 225 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 226 insn_template tm;
252b5132 227
7d5e4556
L		 228 /* SUFFIX holds the instruction size suffix for byte, word, dword
229 or qword, if given. */
252b5132
RH		 230 char suffix;
231
47926f60 232 /* OPERANDS gives the number of given operands. */
252b5132
RH		 233 unsigned int operands;
234
235 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
236 of given register, displacement, memory operands and immediate
47926f60 237 operands. */
252b5132
RH		 238 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
239
240 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 241 use OP[i] for the corresponding operand. */
40fb9820 242 i386_operand_type types[MAX_OPERANDS];
252b5132 243
520dc8e8
AM		 244 /* Displacement expression, immediate expression, or register for each
245 operand. */
246 union i386_op op[MAX_OPERANDS];
252b5132 247
3e73aa7c
JH		 248 /* Flags for operands. */
249 unsigned int flags[MAX_OPERANDS];
250#define Operand_PCrel 1
251
252b5132 252 /* Relocation type for operand */
f86103b7 253 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 254
252b5132
RH		 255 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
256 the base index byte below. */
257 const reg_entry *base_reg;
258 const reg_entry *index_reg;
259 unsigned int log2_scale_factor;
260
261 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 262 explicit segment overrides are given. */
ce8a8b2f 263 const seg_entry *seg[2];
252b5132
RH		 264
265 /* PREFIX holds all the given prefix opcodes (usually null).
266 PREFIXES is the number of prefix opcodes. */
267 unsigned int prefixes;
268 unsigned char prefix[MAX_PREFIXES];
269
270 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 271 addressing modes of this insn are encoded. */
252b5132 272 modrm_byte rm;
3e73aa7c 273 rex_byte rex;
252b5132 274 sib_byte sib;
c0f3af97 275 vex_prefix vex;
b6169b20
L		 276
277 /* Swap operand in encoding. */
4473e004 278 unsigned int swap_operand;
891edac4
L		 279
280 /* Error message. */
a65babc9 281 enum i386_error error;
252b5132
RH		 282 };
283
284typedef struct _i386_insn i386_insn;
285
286/* List of chars besides those in app.c:symbol_chars that can start an
287 operand. Used to prevent the scrubber eating vital white-space. */
32137342 288const char extra_symbol_chars[] = "*%-(["
252b5132 289#ifdef LEX_AT
32137342
NC		 290 "@"
291#endif
292#ifdef LEX_QM
293 "?"
252b5132 294#endif
32137342 295 ;
252b5132 296
29b0f896
AM		 297#if (defined (TE_I386AIX) \
298 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 299 && !defined (TE_GNU) \
29b0f896 300 && !defined (TE_LINUX) \
32137342 301 && !defined (TE_NETWARE) \
29b0f896
AM		 302 && !defined (TE_FreeBSD) \
303 && !defined (TE_NetBSD)))
252b5132 304/* This array holds the chars that always start a comment. If the
b3b91714
AM		 305 pre-processor is disabled, these aren't very useful. The option
306 --divide will remove '/' from this list. */
307const char *i386_comment_chars = "#/";
308#define SVR4_COMMENT_CHARS 1
252b5132 309#define PREFIX_SEPARATOR '\\'
252b5132 310
b3b91714
AM		 311#else
312const char *i386_comment_chars = "#";
313#define PREFIX_SEPARATOR '/'
314#endif
315
252b5132
RH		 316/* This array holds the chars that only start a comment at the beginning of
317 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 318 .line and .file directives will appear in the pre-processed output.
319 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 320 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 321 #NO_APP at the beginning of its output.
322 Also note that comments started like this one will always work if
252b5132 323 '/' isn't otherwise defined. */
b3b91714 324const char line_comment_chars[] = "#/";
252b5132 325
63a0b638 326const char line_separator_chars[] = ";";
252b5132 327
ce8a8b2f
AM		 328/* Chars that can be used to separate mant from exp in floating point
329 nums. */
252b5132
RH		 330const char EXP_CHARS[] = "eE";
331
ce8a8b2f
AM		 332/* Chars that mean this number is a floating point constant
333 As in 0f12.456
334 or 0d1.2345e12. */
252b5132
RH		 335const char FLT_CHARS[] = "fFdDxX";
336
ce8a8b2f 337/* Tables for lexical analysis. */
252b5132
RH		 338static char mnemonic_chars[256];
339static char register_chars[256];
340static char operand_chars[256];
341static char identifier_chars[256];
342static char digit_chars[256];
343
ce8a8b2f 344/* Lexical macros. */
252b5132
RH		 345#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
346#define is_operand_char(x) (operand_chars[(unsigned char) x])
347#define is_register_char(x) (register_chars[(unsigned char) x])
348#define is_space_char(x) ((x) == ' ')
349#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
350#define is_digit_char(x) (digit_chars[(unsigned char) x])
351
0234cb7c 352/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 353static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
354
355/* md_assemble() always leaves the strings it's passed unaltered. To
356 effect this we maintain a stack of saved characters that we've smashed
357 with '\0's (indicating end of strings for various sub-fields of the
47926f60 358 assembler instruction). */
252b5132 359static char save_stack[32];
ce8a8b2f 360static char *save_stack_p;
252b5132
RH		 361#define END_STRING_AND_SAVE(s) \
362 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
363#define RESTORE_END_STRING(s) \
364 do { *(s) = *--save_stack_p; } while (0)
365
47926f60 366/* The instruction we're assembling. */
252b5132
RH		 367static i386_insn i;
368
369/* Possible templates for current insn. */
370static const templates *current_templates;
371
31b2323c
L		 372/* Per instruction expressionS buffers: max displacements & immediates. */
373static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
374static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 375
47926f60 376/* Current operand we are working on. */
ee86248c 377static int this_operand = -1;
252b5132 378
3e73aa7c
JH		 379/* We support four different modes. FLAG_CODE variable is used to distinguish
380 these. */
381
382enum flag_code {
383 CODE_32BIT,
384 CODE_16BIT,
385 CODE_64BIT };
386
387static enum flag_code flag_code;
4fa24527 388static unsigned int object_64bit;
3e73aa7c
JH		 389static int use_rela_relocations = 0;
390
391/* The names used to print error messages. */
b77a7acd 392static const char *flag_code_names[] =
3e73aa7c
JH		 393 {
394 "32",
395 "16",
396 "64"
397 };
252b5132 398
47926f60
KH		 399/* 1 for intel syntax,
400 0 if att syntax. */
401static int intel_syntax = 0;
252b5132 402
1efbbeb4
L		 403/* 1 for intel mnemonic,
404 0 if att mnemonic. */
405static int intel_mnemonic = !SYSV386_COMPAT;
406
5209009a 407/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 408static int old_gcc = OLDGCC_COMPAT;
409
a60de03c
JB		 410/* 1 if pseudo registers are permitted. */
411static int allow_pseudo_reg = 0;
412
47926f60
KH		 413/* 1 if register prefix % not required. */
414static int allow_naked_reg = 0;
252b5132 415
ba104c83 416/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 417static int allow_index_reg = 0;
418
daf50ae7
L		 419static enum
420 {
421 sse_check_none = 0,
422 sse_check_warning,
423 sse_check_error
424 }
425sse_check;
426
2ca3ace5
L		 427/* Register prefix used for error message. */
428static const char *register_prefix = "%";
429
47926f60
KH		 430/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
431 leave, push, and pop instructions so that gcc has the same stack
432 frame as in 32 bit mode. */
433static char stackop_size = '\0';
eecb386c 434
12b55ccc
L		 435/* Non-zero to optimize code alignment. */
436int optimize_align_code = 1;
437
47926f60
KH		 438/* Non-zero to quieten some warnings. */
439static int quiet_warnings = 0;
a38cf1db 440
47926f60
KH		 441/* CPU name. */
442static const char *cpu_arch_name = NULL;
6305a203 443static char *cpu_sub_arch_name = NULL;
a38cf1db 444
47926f60 445/* CPU feature flags. */
40fb9820
L		 446static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
447
ccc9c027
L		 448/* If we have selected a cpu we are generating instructions for. */
449static int cpu_arch_tune_set = 0;
450
9103f4f4 451/* Cpu we are generating instructions for. */
fbf3f584 452enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 453
454/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 455static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 456
ccc9c027 457/* CPU instruction set architecture used. */
fbf3f584 458enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 459
9103f4f4 460/* CPU feature flags of instruction set architecture used. */
fbf3f584 461i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 462
fddf5b5b
AM		 463/* If set, conditional jumps are not automatically promoted to handle
464 larger than a byte offset. */
465static unsigned int no_cond_jump_promotion = 0;
466
c0f3af97
L		 467/* Encode SSE instructions with VEX prefix. */
468static unsigned int sse2avx;
469
539f890d
L		 470/* Encode scalar AVX instructions with specific vector length. */
471static enum
472 {
473 vex128 = 0,
474 vex256
475 } avxscalar;
476
29b0f896 477/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 478static symbolS *GOT_symbol;
29b0f896 479
a4447b93
RH		 480/* The dwarf2 return column, adjusted for 32 or 64 bit. */
481unsigned int x86_dwarf2_return_column;
482
483/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
484int x86_cie_data_alignment;
485
252b5132 486/* Interface to relax_segment.
fddf5b5b
AM		 487 There are 3 major relax states for 386 jump insns because the
488 different types of jumps add different sizes to frags when we're
489 figuring out what sort of jump to choose to reach a given label. */
252b5132 490
47926f60 491/* Types. */
93c2a809
AM		 492#define UNCOND_JUMP 0
493#define COND_JUMP 1
494#define COND_JUMP86 2
fddf5b5b 495
47926f60 496/* Sizes. */
252b5132
RH		 497#define CODE16 1
498#define SMALL 0
29b0f896 499#define SMALL16 (SMALL | CODE16)
252b5132 500#define BIG 2
29b0f896 501#define BIG16 (BIG | CODE16)
252b5132
RH		 502
503#ifndef INLINE
504#ifdef __GNUC__
505#define INLINE __inline__
506#else
507#define INLINE
508#endif
509#endif
510
fddf5b5b
AM		 511#define ENCODE_RELAX_STATE(type, size) \
512 ((relax_substateT) (((type) << 2) | (size)))
513#define TYPE_FROM_RELAX_STATE(s) \
514 ((s) >> 2)
515#define DISP_SIZE_FROM_RELAX_STATE(s) \
516 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 517
518/* This table is used by relax_frag to promote short jumps to long
519 ones where necessary. SMALL (short) jumps may be promoted to BIG
520 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
521 don't allow a short jump in a 32 bit code segment to be promoted to
522 a 16 bit offset jump because it's slower (requires data size
523 prefix), and doesn't work, unless the destination is in the bottom
524 64k of the code segment (The top 16 bits of eip are zeroed). */
525
526const relax_typeS md_relax_table[] =
527{
24eab124
AM		 528 /* The fields are:
529 1) most positive reach of this state,
530 2) most negative reach of this state,
93c2a809 531 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 532 4) which index into the table to try if we can't fit into this one. */
252b5132 533
fddf5b5b 534 /* UNCOND_JUMP states. */
93c2a809
AM		 535 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
536 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
537 /* dword jmp adds 4 bytes to frag:
538 0 extra opcode bytes, 4 displacement bytes. */
252b5132 539 {0, 0, 4, 0},
93c2a809
AM		 540 /* word jmp adds 2 byte2 to frag:
541 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 542 {0, 0, 2, 0},
543
93c2a809
AM		 544 /* COND_JUMP states. */
545 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
546 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
547 /* dword conditionals adds 5 bytes to frag:
548 1 extra opcode byte, 4 displacement bytes. */
549 {0, 0, 5, 0},
fddf5b5b 550 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 551 1 extra opcode byte, 2 displacement bytes. */
552 {0, 0, 3, 0},
553
554 /* COND_JUMP86 states. */
555 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
556 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
557 /* dword conditionals adds 5 bytes to frag:
558 1 extra opcode byte, 4 displacement bytes. */
559 {0, 0, 5, 0},
560 /* word conditionals add 4 bytes to frag:
561 1 displacement byte and a 3 byte long branch insn. */
562 {0, 0, 4, 0}
252b5132
RH		 563};
564
9103f4f4
L		 565static const arch_entry cpu_arch[] =
566{
89507696
JB		 567 /* Do not replace the first two entries - i386_target_format()
568 relies on them being there in this order. */
8a2c8fef 569 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
22109423 570 CPU_GENERIC32_FLAGS, 0, 0 },
8a2c8fef 571 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
22109423 572 CPU_GENERIC64_FLAGS, 0, 0 },
8a2c8fef 573 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
22109423 574 CPU_NONE_FLAGS, 0, 0 },
8a2c8fef 575 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
22109423 576 CPU_I186_FLAGS, 0, 0 },
8a2c8fef 577 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
22109423 578 CPU_I286_FLAGS, 0, 0 },
8a2c8fef 579 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
22109423 580 CPU_I386_FLAGS, 0, 0 },
8a2c8fef 581 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
22109423 582 CPU_I486_FLAGS, 0, 0 },
8a2c8fef 583 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
22109423 584 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 585 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
22109423 586 CPU_I686_FLAGS, 0, 0 },
8a2c8fef 587 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
22109423 588 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 589 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
22109423 590 CPU_PENTIUMPRO_FLAGS, 0, 0 },
8a2c8fef 591 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
22109423 592 CPU_P2_FLAGS, 0, 0 },
8a2c8fef 593 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
22109423 594 CPU_P3_FLAGS, 0, 0 },
8a2c8fef 595 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
22109423 596 CPU_P4_FLAGS, 0, 0 },
8a2c8fef 597 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
22109423 598 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 599 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
22109423 600 CPU_NOCONA_FLAGS, 0, 0 },
8a2c8fef 601 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
22109423 602 CPU_CORE_FLAGS, 1, 0 },
8a2c8fef 603 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
22109423 604 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 605 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
22109423 606 CPU_CORE2_FLAGS, 1, 0 },
8a2c8fef 607 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
22109423 608 CPU_CORE2_FLAGS, 0, 0 },
8a2c8fef 609 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
22109423 610 CPU_COREI7_FLAGS, 0, 0 },
8a2c8fef 611 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
22109423 612 CPU_L1OM_FLAGS, 0, 0 },
8a2c8fef 613 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
22109423 614 CPU_K6_FLAGS, 0, 0 },
8a2c8fef 615 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
22109423 616 CPU_K6_2_FLAGS, 0, 0 },
8a2c8fef 617 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
22109423 618 CPU_ATHLON_FLAGS, 0, 0 },
8a2c8fef 619 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
22109423 620 CPU_K8_FLAGS, 1, 0 },
8a2c8fef 621 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
22109423 622 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 623 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
22109423 624 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 625 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
22109423 626 CPU_AMDFAM10_FLAGS, 0, 0 },
68339fdf 627 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BDVER1,
22109423 628 CPU_BDVER1_FLAGS, 0, 0 },
8a2c8fef 629 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
22109423 630 CPU_8087_FLAGS, 0, 0 },
8a2c8fef 631 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
22109423 632 CPU_287_FLAGS, 0, 0 },
8a2c8fef 633 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
22109423 634 CPU_387_FLAGS, 0, 0 },
8a2c8fef 635 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
22109423 636 CPU_ANY87_FLAGS, 0, 1 },
8a2c8fef 637 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
22109423 638 CPU_MMX_FLAGS, 0, 0 },
8a2c8fef 639 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
22109423 640 CPU_3DNOWA_FLAGS, 0, 1 },
8a2c8fef 641 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
22109423 642 CPU_SSE_FLAGS, 0, 0 },
8a2c8fef 643 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
22109423 644 CPU_SSE2_FLAGS, 0, 0 },
8a2c8fef 645 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
22109423 646 CPU_SSE3_FLAGS, 0, 0 },
8a2c8fef 647 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
22109423 648 CPU_SSSE3_FLAGS, 0, 0 },
8a2c8fef 649 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
22109423 650 CPU_SSE4_1_FLAGS, 0, 0 },
8a2c8fef 651 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
22109423 652 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 653 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
22109423 654 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 655 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
22109423 656 CPU_ANY_SSE_FLAGS, 0, 1 },
8a2c8fef 657 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
22109423 658 CPU_AVX_FLAGS, 0, 0 },
8a2c8fef 659 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
22109423 660 CPU_ANY_AVX_FLAGS, 0, 1 },
8a2c8fef 661 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
22109423 662 CPU_VMX_FLAGS, 0, 0 },
8a2c8fef 663 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
22109423 664 CPU_SMX_FLAGS, 0, 0 },
8a2c8fef 665 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
22109423 666 CPU_XSAVE_FLAGS, 0, 0 },
c7b8aa3a 667 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
22109423 668 CPU_XSAVEOPT_FLAGS, 0, 0 },
8a2c8fef 669 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
22109423 670 CPU_AES_FLAGS, 0, 0 },
8a2c8fef 671 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
22109423 672 CPU_PCLMUL_FLAGS, 0, 0 },
8a2c8fef 673 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
22109423 674 CPU_PCLMUL_FLAGS, 1, 0 },
c7b8aa3a 675 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
22109423 676 CPU_FSGSBASE_FLAGS, 0, 0 },
c7b8aa3a 677 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
22109423 678 CPU_RDRND_FLAGS, 0, 0 },
c7b8aa3a 679 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
22109423 680 CPU_F16C_FLAGS, 0, 0 },
8a2c8fef 681 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
22109423 682 CPU_FMA_FLAGS, 0, 0 },
8a2c8fef 683 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
22109423 684 CPU_FMA4_FLAGS, 0, 0 },
8a2c8fef 685 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
22109423 686 CPU_XOP_FLAGS, 0, 0 },
8a2c8fef 687 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
22109423 688 CPU_LWP_FLAGS, 0, 0 },
8a2c8fef 689 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
22109423 690 CPU_MOVBE_FLAGS, 0, 0 },
8a2c8fef 691 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
22109423 692 CPU_EPT_FLAGS, 0, 0 },
8a2c8fef 693 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
22109423
L		 694 CPU_CLFLUSH_FLAGS, 0, 0 },
695 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
696 CPU_NOP_FLAGS, 0, 0 },
8a2c8fef 697 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
22109423 698 CPU_SYSCALL_FLAGS, 0, 0 },
8a2c8fef 699 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
22109423 700 CPU_RDTSCP_FLAGS, 0, 0 },
8a2c8fef 701 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
22109423 702 CPU_3DNOW_FLAGS, 0, 0 },
8a2c8fef 703 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
22109423 704 CPU_3DNOWA_FLAGS, 0, 0 },
8a2c8fef 705 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
22109423 706 CPU_PADLOCK_FLAGS, 0, 0 },
8a2c8fef 707 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
22109423 708 CPU_SVME_FLAGS, 1, 0 },
8a2c8fef 709 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
22109423 710 CPU_SVME_FLAGS, 0, 0 },
8a2c8fef 711 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
22109423 712 CPU_SSE4A_FLAGS, 0, 0 },
8a2c8fef 713 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
22109423 714 CPU_ABM_FLAGS, 0, 0 },
e413e4e9
AM		 715};
716
704209c0 717#ifdef I386COFF
a6c24e68
NC		 718/* Like s_lcomm_internal in gas/read.c but the alignment string
719 is allowed to be optional. */
720
721static symbolS *
722pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
723{
724 addressT align = 0;
725
726 SKIP_WHITESPACE ();
727
7ab9ffdd 728 if (needs_align
a6c24e68
NC		 729 && *input_line_pointer == ',')
730 {
731 align = parse_align (needs_align - 1);
7ab9ffdd 732
a6c24e68
NC		 733 if (align == (addressT) -1)
734 return NULL;
735 }
736 else
737 {
738 if (size >= 8)
739 align = 3;
740 else if (size >= 4)
741 align = 2;
742 else if (size >= 2)
743 align = 1;
744 else
745 align = 0;
746 }
747
748 bss_alloc (symbolP, size, align);
749 return symbolP;
750}
751
704209c0 752static void
a6c24e68
NC		 753pe_lcomm (int needs_align)
754{
755 s_comm_internal (needs_align * 2, pe_lcomm_internal);
756}
704209c0 757#endif
a6c24e68 758
29b0f896
AM		 759const pseudo_typeS md_pseudo_table[] =
760{
761#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
762 {"align", s_align_bytes, 0},
763#else
764 {"align", s_align_ptwo, 0},
765#endif
766 {"arch", set_cpu_arch, 0},
767#ifndef I386COFF
768 {"bss", s_bss, 0},
a6c24e68
NC		 769#else
770 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 771#endif
772 {"ffloat", float_cons, 'f'},
773 {"dfloat", float_cons, 'd'},
774 {"tfloat", float_cons, 'x'},
775 {"value", cons, 2},
d182319b 776 {"slong", signed_cons, 4},
29b0f896
AM		 777 {"noopt", s_ignore, 0},
778 {"optim", s_ignore, 0},
779 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
780 {"code16", set_code_flag, CODE_16BIT},
781 {"code32", set_code_flag, CODE_32BIT},
782 {"code64", set_code_flag, CODE_64BIT},
783 {"intel_syntax", set_intel_syntax, 1},
784 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 785 {"intel_mnemonic", set_intel_mnemonic, 1},
786 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 787 {"allow_index_reg", set_allow_index_reg, 1},
788 {"disallow_index_reg", set_allow_index_reg, 0},
cb19c032 789 {"sse_check", set_sse_check, 0},
3b22753a
L		 790#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
791 {"largecomm", handle_large_common, 0},
07a53e5c 792#else
e3bb37b5 793 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 794 {"loc", dwarf2_directive_loc, 0},
795 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 796#endif
6482c264
NC		 797#ifdef TE_PE
798 {"secrel32", pe_directive_secrel, 0},
799#endif
29b0f896
AM		 800 {0, 0, 0}
801};
802
803/* For interface with expression (). */
804extern char *input_line_pointer;
805
806/* Hash table for instruction mnemonic lookup. */
807static struct hash_control *op_hash;
808
809/* Hash table for register lookup. */
810static struct hash_control *reg_hash;
811\f
252b5132 812void
e3bb37b5 813i386_align_code (fragS *fragP, int count)
252b5132 814{
ce8a8b2f
AM		 815 /* Various efficient no-op patterns for aligning code labels.
816 Note: Don't try to assemble the instructions in the comments.
817 0L and 0w are not legal. */
252b5132
RH		 818 static const char f32_1[] =
819 {0x90}; /* nop */
820 static const char f32_2[] =
ccc9c027 821 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 822 static const char f32_3[] =
823 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
824 static const char f32_4[] =
825 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
826 static const char f32_5[] =
827 {0x90, /* nop */
828 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
829 static const char f32_6[] =
830 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
831 static const char f32_7[] =
832 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
833 static const char f32_8[] =
834 {0x90, /* nop */
835 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
836 static const char f32_9[] =
837 {0x89,0xf6, /* movl %esi,%esi */
838 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
839 static const char f32_10[] =
840 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
841 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
842 static const char f32_11[] =
843 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
844 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
845 static const char f32_12[] =
846 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
847 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
848 static const char f32_13[] =
849 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
850 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
851 static const char f32_14[] =
852 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
853 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 854 static const char f16_3[] =
855 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 856 static const char f16_4[] =
857 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
858 static const char f16_5[] =
859 {0x90, /* nop */
860 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
861 static const char f16_6[] =
862 {0x89,0xf6, /* mov %si,%si */
863 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
864 static const char f16_7[] =
865 {0x8d,0x74,0x00, /* lea 0(%si),%si */
866 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
867 static const char f16_8[] =
868 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
869 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 870 static const char jump_31[] =
871 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
872 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
873 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
874 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 875 static const char *const f32_patt[] = {
876 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 877 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 878 };
879 static const char *const f16_patt[] = {
76bc74dc 880 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 881 };
ccc9c027
L		 882 /* nopl (%[re]ax) */
883 static const char alt_3[] =
884 {0x0f,0x1f,0x00};
885 /* nopl 0(%[re]ax) */
886 static const char alt_4[] =
887 {0x0f,0x1f,0x40,0x00};
888 /* nopl 0(%[re]ax,%[re]ax,1) */
889 static const char alt_5[] =
890 {0x0f,0x1f,0x44,0x00,0x00};
891 /* nopw 0(%[re]ax,%[re]ax,1) */
892 static const char alt_6[] =
893 {0x66,0x0f,0x1f,0x44,0x00,0x00};
894 /* nopl 0L(%[re]ax) */
895 static const char alt_7[] =
896 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
897 /* nopl 0L(%[re]ax,%[re]ax,1) */
898 static const char alt_8[] =
899 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
900 /* nopw 0L(%[re]ax,%[re]ax,1) */
901 static const char alt_9[] =
902 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
903 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
904 static const char alt_10[] =
905 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
906 /* data16
907 nopw %cs:0L(%[re]ax,%[re]ax,1) */
908 static const char alt_long_11[] =
909 {0x66,
910 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
911 /* data16
912 data16
913 nopw %cs:0L(%[re]ax,%[re]ax,1) */
914 static const char alt_long_12[] =
915 {0x66,
916 0x66,
917 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
918 /* data16
919 data16
920 data16
921 nopw %cs:0L(%[re]ax,%[re]ax,1) */
922 static const char alt_long_13[] =
923 {0x66,
924 0x66,
925 0x66,
926 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
927 /* data16
928 data16
929 data16
930 data16
931 nopw %cs:0L(%[re]ax,%[re]ax,1) */
932 static const char alt_long_14[] =
933 {0x66,
934 0x66,
935 0x66,
936 0x66,
937 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
938 /* data16
939 data16
940 data16
941 data16
942 data16
943 nopw %cs:0L(%[re]ax,%[re]ax,1) */
944 static const char alt_long_15[] =
945 {0x66,
946 0x66,
947 0x66,
948 0x66,
949 0x66,
950 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
951 /* nopl 0(%[re]ax,%[re]ax,1)
952 nopw 0(%[re]ax,%[re]ax,1) */
953 static const char alt_short_11[] =
954 {0x0f,0x1f,0x44,0x00,0x00,
955 0x66,0x0f,0x1f,0x44,0x00,0x00};
956 /* nopw 0(%[re]ax,%[re]ax,1)
957 nopw 0(%[re]ax,%[re]ax,1) */
958 static const char alt_short_12[] =
959 {0x66,0x0f,0x1f,0x44,0x00,0x00,
960 0x66,0x0f,0x1f,0x44,0x00,0x00};
961 /* nopw 0(%[re]ax,%[re]ax,1)
962 nopl 0L(%[re]ax) */
963 static const char alt_short_13[] =
964 {0x66,0x0f,0x1f,0x44,0x00,0x00,
965 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
966 /* nopl 0L(%[re]ax)
967 nopl 0L(%[re]ax) */
968 static const char alt_short_14[] =
969 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
970 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
971 /* nopl 0L(%[re]ax)
972 nopl 0L(%[re]ax,%[re]ax,1) */
973 static const char alt_short_15[] =
974 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
975 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
976 static const char *const alt_short_patt[] = {
977 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
978 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
979 alt_short_14, alt_short_15
980 };
981 static const char *const alt_long_patt[] = {
982 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
983 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
984 alt_long_14, alt_long_15
985 };
252b5132 986
76bc74dc
L		 987 /* Only align for at least a positive non-zero boundary. */
988 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 989 return;
3e73aa7c 990
ccc9c027
L		 991 /* We need to decide which NOP sequence to use for 32bit and
992 64bit. When -mtune= is used:
4eed87de 993
76bc74dc
L		 994 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
995 PROCESSOR_GENERIC32, f32_patt will be used.
996 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
bd5295b2
L		 997 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
998 PROCESSOR_GENERIC64, alt_long_patt will be used.
76bc74dc 999 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
68339fdf 1000 PROCESSOR_AMDFAM10, and PROCESSOR_BDVER1, alt_short_patt
69dd9865 1001 will be used.
ccc9c027 1002
76bc74dc 1003 When -mtune= isn't used, alt_long_patt will be used if
22109423 1004 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1005 be used.
ccc9c027
L		 1006
1007 When -march= or .arch is used, we can't use anything beyond
1008 cpu_arch_isa_flags. */
1009
1010 if (flag_code == CODE_16BIT)
1011 {
ccc9c027 1012 if (count > 8)
33fef721 1013 {
76bc74dc
L		 1014 memcpy (fragP->fr_literal + fragP->fr_fix,
1015 jump_31, count);
1016 /* Adjust jump offset. */
1017 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1018 }
76bc74dc
L		 1019 else
1020 memcpy (fragP->fr_literal + fragP->fr_fix,
1021 f16_patt[count - 1], count);
252b5132 1022 }
33fef721 1023 else
ccc9c027
L		 1024 {
1025 const char *const *patt = NULL;
1026
fbf3f584 1027 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1028 {
1029 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1030 switch (cpu_arch_tune)
1031 {
1032 case PROCESSOR_UNKNOWN:
1033 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1034 optimize with nops. */
1035 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
76bc74dc 1036 patt = alt_long_patt;
ccc9c027
L		 1037 else
1038 patt = f32_patt;
1039 break;
ccc9c027
L		 1040 case PROCESSOR_PENTIUMPRO:
1041 case PROCESSOR_PENTIUM4:
1042 case PROCESSOR_NOCONA:
ef05d495 1043 case PROCESSOR_CORE:
76bc74dc 1044 case PROCESSOR_CORE2:
bd5295b2 1045 case PROCESSOR_COREI7:
3632d14b 1046 case PROCESSOR_L1OM:
76bc74dc
L		 1047 case PROCESSOR_GENERIC64:
1048 patt = alt_long_patt;
1049 break;
ccc9c027
L		 1050 case PROCESSOR_K6:
1051 case PROCESSOR_ATHLON:
1052 case PROCESSOR_K8:
4eed87de 1053 case PROCESSOR_AMDFAM10:
68339fdf 1054 case PROCESSOR_BDVER1:
ccc9c027
L		 1055 patt = alt_short_patt;
1056 break;
76bc74dc 1057 case PROCESSOR_I386:
ccc9c027
L		 1058 case PROCESSOR_I486:
1059 case PROCESSOR_PENTIUM:
1060 case PROCESSOR_GENERIC32:
1061 patt = f32_patt;
1062 break;
4eed87de 1063 }
ccc9c027
L		 1064 }
1065 else
1066 {
fbf3f584 1067 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1068 {
1069 case PROCESSOR_UNKNOWN:
e6a14101 1070 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1071 PROCESSOR_UNKNOWN. */
1072 abort ();
1073 break;
1074
76bc74dc 1075 case PROCESSOR_I386:
ccc9c027
L		 1076 case PROCESSOR_I486:
1077 case PROCESSOR_PENTIUM:
ccc9c027
L		 1078 case PROCESSOR_K6:
1079 case PROCESSOR_ATHLON:
1080 case PROCESSOR_K8:
4eed87de 1081 case PROCESSOR_AMDFAM10:
68339fdf 1082 case PROCESSOR_BDVER1:
ccc9c027
L		 1083 case PROCESSOR_GENERIC32:
1084 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1085 with nops. */
1086 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1087 patt = alt_short_patt;
1088 else
1089 patt = f32_patt;
1090 break;
76bc74dc
L		 1091 case PROCESSOR_PENTIUMPRO:
1092 case PROCESSOR_PENTIUM4:
1093 case PROCESSOR_NOCONA:
1094 case PROCESSOR_CORE:
ef05d495 1095 case PROCESSOR_CORE2:
bd5295b2 1096 case PROCESSOR_COREI7:
3632d14b 1097 case PROCESSOR_L1OM:
22109423 1098 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1099 patt = alt_long_patt;
1100 else
1101 patt = f32_patt;
1102 break;
1103 case PROCESSOR_GENERIC64:
76bc74dc 1104 patt = alt_long_patt;
ccc9c027 1105 break;
4eed87de 1106 }
ccc9c027
L		 1107 }
1108
76bc74dc
L		 1109 if (patt == f32_patt)
1110 {
1111 /* If the padding is less than 15 bytes, we use the normal
1112 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1113 its offset. */
1114 int limit;
76ba9986 1115
711eedef
L		 1116 /* For 64bit, the limit is 3 bytes. */
1117 if (flag_code == CODE_64BIT
1118 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1119 limit = 3;
1120 else
1121 limit = 15;
1122 if (count < limit)
76bc74dc
L		 1123 memcpy (fragP->fr_literal + fragP->fr_fix,
1124 patt[count - 1], count);
1125 else
1126 {
1127 memcpy (fragP->fr_literal + fragP->fr_fix,
1128 jump_31, count);
1129 /* Adjust jump offset. */
1130 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1131 }
1132 }
1133 else
1134 {
1135 /* Maximum length of an instruction is 15 byte. If the
1136 padding is greater than 15 bytes and we don't use jump,
1137 we have to break it into smaller pieces. */
1138 int padding = count;
1139 while (padding > 15)
1140 {
1141 padding -= 15;
1142 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1143 patt [14], 15);
1144 }
1145
1146 if (padding)
1147 memcpy (fragP->fr_literal + fragP->fr_fix,
1148 patt [padding - 1], padding);
1149 }
ccc9c027 1150 }
33fef721 1151 fragP->fr_var = count;
252b5132
RH		 1152}
1153
c6fb90c8 1154static INLINE int
0dfbf9d7 1155operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1156{
0dfbf9d7 1157 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1158 {
1159 case 3:
0dfbf9d7 1160 if (x->array[2])
c6fb90c8
L		 1161 return 0;
1162 case 2:
0dfbf9d7 1163 if (x->array[1])
c6fb90c8
L		 1164 return 0;
1165 case 1:
0dfbf9d7 1166 return !x->array[0];
c6fb90c8
L		 1167 default:
1168 abort ();
1169 }
40fb9820
L		 1170}
1171
c6fb90c8 1172static INLINE void
0dfbf9d7 1173operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1174{
0dfbf9d7 1175 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1176 {
1177 case 3:
0dfbf9d7 1178 x->array[2] = v;
c6fb90c8 1179 case 2:
0dfbf9d7 1180 x->array[1] = v;
c6fb90c8 1181 case 1:
0dfbf9d7 1182 x->array[0] = v;
c6fb90c8
L		 1183 break;
1184 default:
1185 abort ();
1186 }
1187}
40fb9820 1188
c6fb90c8 1189static INLINE int
0dfbf9d7
L		 1190operand_type_equal (const union i386_operand_type *x,
1191 const union i386_operand_type *y)
c6fb90c8 1192{
0dfbf9d7 1193 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1194 {
1195 case 3:
0dfbf9d7 1196 if (x->array[2] != y->array[2])
c6fb90c8
L		 1197 return 0;
1198 case 2:
0dfbf9d7 1199 if (x->array[1] != y->array[1])
c6fb90c8
L		 1200 return 0;
1201 case 1:
0dfbf9d7 1202 return x->array[0] == y->array[0];
c6fb90c8
L		 1203 break;
1204 default:
1205 abort ();
1206 }
1207}
40fb9820 1208
0dfbf9d7
L		 1209static INLINE int
1210cpu_flags_all_zero (const union i386_cpu_flags *x)
1211{
1212 switch (ARRAY_SIZE(x->array))
1213 {
1214 case 3:
1215 if (x->array[2])
1216 return 0;
1217 case 2:
1218 if (x->array[1])
1219 return 0;
1220 case 1:
1221 return !x->array[0];
1222 default:
1223 abort ();
1224 }
1225}
1226
1227static INLINE void
1228cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1229{
1230 switch (ARRAY_SIZE(x->array))
1231 {
1232 case 3:
1233 x->array[2] = v;
1234 case 2:
1235 x->array[1] = v;
1236 case 1:
1237 x->array[0] = v;
1238 break;
1239 default:
1240 abort ();
1241 }
1242}
1243
1244static INLINE int
1245cpu_flags_equal (const union i386_cpu_flags *x,
1246 const union i386_cpu_flags *y)
1247{
1248 switch (ARRAY_SIZE(x->array))
1249 {
1250 case 3:
1251 if (x->array[2] != y->array[2])
1252 return 0;
1253 case 2:
1254 if (x->array[1] != y->array[1])
1255 return 0;
1256 case 1:
1257 return x->array[0] == y->array[0];
1258 break;
1259 default:
1260 abort ();
1261 }
1262}
c6fb90c8
L		 1263
1264static INLINE int
1265cpu_flags_check_cpu64 (i386_cpu_flags f)
1266{
1267 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1268 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1269}
1270
c6fb90c8
L		 1271static INLINE i386_cpu_flags
1272cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1273{
c6fb90c8
L		 1274 switch (ARRAY_SIZE (x.array))
1275 {
1276 case 3:
1277 x.array [2] &= y.array [2];
1278 case 2:
1279 x.array [1] &= y.array [1];
1280 case 1:
1281 x.array [0] &= y.array [0];
1282 break;
1283 default:
1284 abort ();
1285 }
1286 return x;
1287}
40fb9820 1288
c6fb90c8
L		 1289static INLINE i386_cpu_flags
1290cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1291{
c6fb90c8 1292 switch (ARRAY_SIZE (x.array))
40fb9820 1293 {
c6fb90c8
L		 1294 case 3:
1295 x.array [2] |= y.array [2];
1296 case 2:
1297 x.array [1] |= y.array [1];
1298 case 1:
1299 x.array [0] |= y.array [0];
40fb9820
L		 1300 break;
1301 default:
1302 abort ();
1303 }
40fb9820
L		 1304 return x;
1305}
1306
309d3373
JB		 1307static INLINE i386_cpu_flags
1308cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1309{
1310 switch (ARRAY_SIZE (x.array))
1311 {
1312 case 3:
1313 x.array [2] &= ~y.array [2];
1314 case 2:
1315 x.array [1] &= ~y.array [1];
1316 case 1:
1317 x.array [0] &= ~y.array [0];
1318 break;
1319 default:
1320 abort ();
1321 }
1322 return x;
1323}
1324
c0f3af97
L		 1325#define CPU_FLAGS_ARCH_MATCH 0x1
1326#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1327#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1328#define CPU_FLAGS_PCLMUL_MATCH 0x8
1329#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1330
a5ff0eb2 1331#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1332 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1333 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1334#define CPU_FLAGS_PERFECT_MATCH \
1335 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1336
1337/* Return CPU flags match bits. */
3629bb00 1338
40fb9820 1339static int
d3ce72d0 1340cpu_flags_match (const insn_template *t)
40fb9820 1341{
c0f3af97
L		 1342 i386_cpu_flags x = t->cpu_flags;
1343 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1344
1345 x.bitfield.cpu64 = 0;
1346 x.bitfield.cpuno64 = 0;
1347
0dfbf9d7 1348 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1349 {
1350 /* This instruction is available on all archs. */
1351 match |= CPU_FLAGS_32BIT_MATCH;
1352 }
3629bb00
L		 1353 else
1354 {
c0f3af97 1355 /* This instruction is available only on some archs. */
3629bb00
L		 1356 i386_cpu_flags cpu = cpu_arch_flags;
1357
1358 cpu.bitfield.cpu64 = 0;
1359 cpu.bitfield.cpuno64 = 0;
1360 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1361 if (!cpu_flags_all_zero (&cpu))
1362 {
a5ff0eb2
L		 1363 if (x.bitfield.cpuavx)
1364 {
ce2f5b3c 1365 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1366 if (cpu.bitfield.cpuavx)
1367 {
1368 /* Check SSE2AVX. */
1369 if (!t->opcode_modifier.sse2avx|| sse2avx)
1370 {
1371 match |= (CPU_FLAGS_ARCH_MATCH
1372 | CPU_FLAGS_AVX_MATCH);
1373 /* Check AES. */
1374 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1375 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1376 /* Check PCLMUL. */
1377 if (!x.bitfield.cpupclmul
1378 || cpu.bitfield.cpupclmul)
1379 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1380 }
1381 }
1382 else
1383 match |= CPU_FLAGS_ARCH_MATCH;
1384 }
1385 else
c0f3af97
L		 1386 match |= CPU_FLAGS_32BIT_MATCH;
1387 }
3629bb00 1388 }
c0f3af97 1389 return match;
40fb9820
L		 1390}
1391
c6fb90c8
L		 1392static INLINE i386_operand_type
1393operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1394{
c6fb90c8
L		 1395 switch (ARRAY_SIZE (x.array))
1396 {
1397 case 3:
1398 x.array [2] &= y.array [2];
1399 case 2:
1400 x.array [1] &= y.array [1];
1401 case 1:
1402 x.array [0] &= y.array [0];
1403 break;
1404 default:
1405 abort ();
1406 }
1407 return x;
40fb9820
L		 1408}
1409
c6fb90c8
L		 1410static INLINE i386_operand_type
1411operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1412{
c6fb90c8 1413 switch (ARRAY_SIZE (x.array))
40fb9820 1414 {
c6fb90c8
L		 1415 case 3:
1416 x.array [2] |= y.array [2];
1417 case 2:
1418 x.array [1] |= y.array [1];
1419 case 1:
1420 x.array [0] |= y.array [0];
40fb9820
L		 1421 break;
1422 default:
1423 abort ();
1424 }
c6fb90c8
L		 1425 return x;
1426}
40fb9820 1427
c6fb90c8
L		 1428static INLINE i386_operand_type
1429operand_type_xor (i386_operand_type x, i386_operand_type y)
1430{
1431 switch (ARRAY_SIZE (x.array))
1432 {
1433 case 3:
1434 x.array [2] ^= y.array [2];
1435 case 2:
1436 x.array [1] ^= y.array [1];
1437 case 1:
1438 x.array [0] ^= y.array [0];
1439 break;
1440 default:
1441 abort ();
1442 }
40fb9820
L		 1443 return x;
1444}
1445
1446static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1447static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1448static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1449static const i386_operand_type inoutportreg
1450 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1451static const i386_operand_type reg16_inoutportreg
1452 = OPERAND_TYPE_REG16_INOUTPORTREG;
1453static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1454static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1455static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1456static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1457static const i386_operand_type anydisp
1458 = OPERAND_TYPE_ANYDISP;
40fb9820 1459static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1460static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
40fb9820
L		 1461static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1462static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1463static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1464static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1465static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1466static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1467static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1468static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1469static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1470static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1471
1472enum operand_type
1473{
1474 reg,
40fb9820
L		 1475 imm,
1476 disp,
1477 anymem
1478};
1479
c6fb90c8 1480static INLINE int
40fb9820
L		 1481operand_type_check (i386_operand_type t, enum operand_type c)
1482{
1483 switch (c)
1484 {
1485 case reg:
1486 return (t.bitfield.reg8
1487 || t.bitfield.reg16
1488 || t.bitfield.reg32
1489 || t.bitfield.reg64);
1490
40fb9820
L		 1491 case imm:
1492 return (t.bitfield.imm8
1493 || t.bitfield.imm8s
1494 || t.bitfield.imm16
1495 || t.bitfield.imm32
1496 || t.bitfield.imm32s
1497 || t.bitfield.imm64);
1498
1499 case disp:
1500 return (t.bitfield.disp8
1501 || t.bitfield.disp16
1502 || t.bitfield.disp32
1503 || t.bitfield.disp32s
1504 || t.bitfield.disp64);
1505
1506 case anymem:
1507 return (t.bitfield.disp8
1508 || t.bitfield.disp16
1509 || t.bitfield.disp32
1510 || t.bitfield.disp32s
1511 || t.bitfield.disp64
1512 || t.bitfield.baseindex);
1513
1514 default:
1515 abort ();
1516 }
2cfe26b6
AM		 1517
1518 return 0;
40fb9820
L		 1519}
1520
5c07affc
L		 1521/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1522 operand J for instruction template T. */
1523
1524static INLINE int
d3ce72d0 1525match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1526{
1527 return !((i.types[j].bitfield.byte
1528 && !t->operand_types[j].bitfield.byte)
1529 || (i.types[j].bitfield.word
1530 && !t->operand_types[j].bitfield.word)
1531 || (i.types[j].bitfield.dword
1532 && !t->operand_types[j].bitfield.dword)
1533 || (i.types[j].bitfield.qword
1534 && !t->operand_types[j].bitfield.qword));
1535}
1536
1537/* Return 1 if there is no conflict in any size on operand J for
1538 instruction template T. */
1539
1540static INLINE int
d3ce72d0 1541match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1542{
1543 return (match_reg_size (t, j)
1544 && !((i.types[j].bitfield.unspecified
1545 && !t->operand_types[j].bitfield.unspecified)
1546 || (i.types[j].bitfield.fword
1547 && !t->operand_types[j].bitfield.fword)
1548 || (i.types[j].bitfield.tbyte
1549 && !t->operand_types[j].bitfield.tbyte)
1550 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1551 && !t->operand_types[j].bitfield.xmmword)
1552 || (i.types[j].bitfield.ymmword
1553 && !t->operand_types[j].bitfield.ymmword)));
5c07affc
L		 1554}
1555
1556/* Return 1 if there is no size conflict on any operands for
1557 instruction template T. */
1558
1559static INLINE int
d3ce72d0 1560operand_size_match (const insn_template *t)
5c07affc
L		 1561{
1562 unsigned int j;
1563 int match = 1;
1564
1565 /* Don't check jump instructions. */
1566 if (t->opcode_modifier.jump
1567 || t->opcode_modifier.jumpbyte
1568 || t->opcode_modifier.jumpdword
1569 || t->opcode_modifier.jumpintersegment)
1570 return match;
1571
1572 /* Check memory and accumulator operand size. */
1573 for (j = 0; j < i.operands; j++)
1574 {
1575 if (t->operand_types[j].bitfield.anysize)
1576 continue;
1577
1578 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1579 {
1580 match = 0;
1581 break;
1582 }
1583
1584 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1585 {
1586 match = 0;
1587 break;
1588 }
1589 }
1590
891edac4 1591 if (match)
5c07affc 1592 return match;
891edac4
L		 1593 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1594 {
1595mismatch:
86e026a4 1596 i.error = operand_size_mismatch;
891edac4
L		 1597 return 0;
1598 }
5c07affc
L		 1599
1600 /* Check reverse. */
9c2799c2 1601 gas_assert (i.operands == 2);
5c07affc
L		 1602
1603 match = 1;
1604 for (j = 0; j < 2; j++)
1605 {
1606 if (t->operand_types[j].bitfield.acc
1607 && !match_reg_size (t, j ? 0 : 1))
891edac4 1608 goto mismatch;
5c07affc
L		 1609
1610 if (i.types[j].bitfield.mem
1611 && !match_mem_size (t, j ? 0 : 1))
891edac4 1612 goto mismatch;
5c07affc
L		 1613 }
1614
1615 return match;
1616}
1617
c6fb90c8 1618static INLINE int
40fb9820
L		 1619operand_type_match (i386_operand_type overlap,
1620 i386_operand_type given)
1621{
1622 i386_operand_type temp = overlap;
1623
1624 temp.bitfield.jumpabsolute = 0;
7d5e4556 1625 temp.bitfield.unspecified = 0;
5c07affc
L		 1626 temp.bitfield.byte = 0;
1627 temp.bitfield.word = 0;
1628 temp.bitfield.dword = 0;
1629 temp.bitfield.fword = 0;
1630 temp.bitfield.qword = 0;
1631 temp.bitfield.tbyte = 0;
1632 temp.bitfield.xmmword = 0;
c0f3af97 1633 temp.bitfield.ymmword = 0;
0dfbf9d7 1634 if (operand_type_all_zero (&temp))
891edac4 1635 goto mismatch;
40fb9820 1636
891edac4
L		 1637 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1638 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1639 return 1;
1640
1641mismatch:
a65babc9 1642 i.error = operand_type_mismatch;
891edac4 1643 return 0;
40fb9820
L		 1644}
1645
7d5e4556 1646/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1647 unless the expected operand type register overlap is null.
1648 Note that Acc in a template matches every size of reg. */
1649
c6fb90c8 1650static INLINE int
40fb9820
L		 1651operand_type_register_match (i386_operand_type m0,
1652 i386_operand_type g0,
1653 i386_operand_type t0,
1654 i386_operand_type m1,
1655 i386_operand_type g1,
1656 i386_operand_type t1)
1657{
1658 if (!operand_type_check (g0, reg))
1659 return 1;
1660
1661 if (!operand_type_check (g1, reg))
1662 return 1;
1663
1664 if (g0.bitfield.reg8 == g1.bitfield.reg8
1665 && g0.bitfield.reg16 == g1.bitfield.reg16
1666 && g0.bitfield.reg32 == g1.bitfield.reg32
1667 && g0.bitfield.reg64 == g1.bitfield.reg64)
1668 return 1;
1669
1670 if (m0.bitfield.acc)
1671 {
1672 t0.bitfield.reg8 = 1;
1673 t0.bitfield.reg16 = 1;
1674 t0.bitfield.reg32 = 1;
1675 t0.bitfield.reg64 = 1;
1676 }
1677
1678 if (m1.bitfield.acc)
1679 {
1680 t1.bitfield.reg8 = 1;
1681 t1.bitfield.reg16 = 1;
1682 t1.bitfield.reg32 = 1;
1683 t1.bitfield.reg64 = 1;
1684 }
1685
891edac4
L		 1686 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1687 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1688 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1689 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1690 return 1;
1691
a65babc9 1692 i.error = register_type_mismatch;
891edac4
L		 1693
1694 return 0;
40fb9820
L		 1695}
1696
252b5132 1697static INLINE unsigned int
40fb9820 1698mode_from_disp_size (i386_operand_type t)
252b5132 1699{
40fb9820
L		 1700 if (t.bitfield.disp8)
1701 return 1;
1702 else if (t.bitfield.disp16
1703 || t.bitfield.disp32
1704 || t.bitfield.disp32s)
1705 return 2;
1706 else
1707 return 0;
252b5132
RH		 1708}
1709
1710static INLINE int
e3bb37b5 1711fits_in_signed_byte (offsetT num)
252b5132
RH		 1712{
1713 return (num >= -128) && (num <= 127);
47926f60 1714}
252b5132
RH		 1715
1716static INLINE int
e3bb37b5 1717fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1718{
1719 return (num & 0xff) == num;
47926f60 1720}
252b5132
RH		 1721
1722static INLINE int
e3bb37b5 1723fits_in_unsigned_word (offsetT num)
252b5132
RH		 1724{
1725 return (num & 0xffff) == num;
47926f60 1726}
252b5132
RH		 1727
1728static INLINE int
e3bb37b5 1729fits_in_signed_word (offsetT num)
252b5132
RH		 1730{
1731 return (-32768 <= num) && (num <= 32767);
47926f60 1732}
2a962e6d 1733
3e73aa7c 1734static INLINE int
e3bb37b5 1735fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1736{
1737#ifndef BFD64
1738 return 1;
1739#else
1740 return (!(((offsetT) -1 << 31) & num)
1741 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1742#endif
1743} /* fits_in_signed_long() */
2a962e6d 1744
3e73aa7c 1745static INLINE int
e3bb37b5 1746fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1747{
1748#ifndef BFD64
1749 return 1;
1750#else
1751 return (num & (((offsetT) 2 << 31) - 1)) == num;
1752#endif
1753} /* fits_in_unsigned_long() */
252b5132 1754
a683cc34
SP		 1755static INLINE int
1756fits_in_imm4 (offsetT num)
1757{
1758 return (num & 0xf) == num;
1759}
1760
40fb9820 1761static i386_operand_type
e3bb37b5 1762smallest_imm_type (offsetT num)
252b5132 1763{
40fb9820 1764 i386_operand_type t;
7ab9ffdd 1765
0dfbf9d7 1766 operand_type_set (&t, 0);
40fb9820
L		 1767 t.bitfield.imm64 = 1;
1768
1769 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1770 {
1771 /* This code is disabled on the 486 because all the Imm1 forms
1772 in the opcode table are slower on the i486. They're the
1773 versions with the implicitly specified single-position
1774 displacement, which has another syntax if you really want to
1775 use that form. */
40fb9820
L		 1776 t.bitfield.imm1 = 1;
1777 t.bitfield.imm8 = 1;
1778 t.bitfield.imm8s = 1;
1779 t.bitfield.imm16 = 1;
1780 t.bitfield.imm32 = 1;
1781 t.bitfield.imm32s = 1;
1782 }
1783 else if (fits_in_signed_byte (num))
1784 {
1785 t.bitfield.imm8 = 1;
1786 t.bitfield.imm8s = 1;
1787 t.bitfield.imm16 = 1;
1788 t.bitfield.imm32 = 1;
1789 t.bitfield.imm32s = 1;
1790 }
1791 else if (fits_in_unsigned_byte (num))
1792 {
1793 t.bitfield.imm8 = 1;
1794 t.bitfield.imm16 = 1;
1795 t.bitfield.imm32 = 1;
1796 t.bitfield.imm32s = 1;
1797 }
1798 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1799 {
1800 t.bitfield.imm16 = 1;
1801 t.bitfield.imm32 = 1;
1802 t.bitfield.imm32s = 1;
1803 }
1804 else if (fits_in_signed_long (num))
1805 {
1806 t.bitfield.imm32 = 1;
1807 t.bitfield.imm32s = 1;
1808 }
1809 else if (fits_in_unsigned_long (num))
1810 t.bitfield.imm32 = 1;
1811
1812 return t;
47926f60 1813}
252b5132 1814
847f7ad4 1815static offsetT
e3bb37b5 1816offset_in_range (offsetT val, int size)
847f7ad4 1817{
508866be 1818 addressT mask;
ba2adb93 1819
847f7ad4
AM		 1820 switch (size)
1821 {
508866be
L		 1822 case 1: mask = ((addressT) 1 << 8) - 1; break;
1823 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1824 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1825#ifdef BFD64
1826 case 8: mask = ((addressT) 2 << 63) - 1; break;
1827#endif
47926f60 1828 default: abort ();
847f7ad4
AM		 1829 }
1830
9de868bf
L		 1831#ifdef BFD64
1832 /* If BFD64, sign extend val for 32bit address mode. */
1833 if (flag_code != CODE_64BIT
1834 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 1835 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1836 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 1837#endif
ba2adb93 1838
47926f60 1839 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1840 {
1841 char buf1[40], buf2[40];
1842
1843 sprint_value (buf1, val);
1844 sprint_value (buf2, val & mask);
1845 as_warn (_("%s shortened to %s"), buf1, buf2);
1846 }
1847 return val & mask;
1848}
1849
c32fa91d
L		 1850enum PREFIX_GROUP
1851{
1852 PREFIX_EXIST = 0,
1853 PREFIX_LOCK,
1854 PREFIX_REP,
1855 PREFIX_OTHER
1856};
1857
1858/* Returns
1859 a. PREFIX_EXIST if attempting to add a prefix where one from the
1860 same class already exists.
1861 b. PREFIX_LOCK if lock prefix is added.
1862 c. PREFIX_REP if rep/repne prefix is added.
1863 d. PREFIX_OTHER if other prefix is added.
1864 */
1865
1866static enum PREFIX_GROUP
e3bb37b5 1867add_prefix (unsigned int prefix)
252b5132 1868{
c32fa91d 1869 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 1870 unsigned int q;
252b5132 1871
29b0f896
AM		 1872 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1873 && flag_code == CODE_64BIT)
b1905489 1874 {
161a04f6
L		 1875 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1876 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1877 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 1878 ret = PREFIX_EXIST;
b1905489
JB		 1879 q = REX_PREFIX;
1880 }
3e73aa7c 1881 else
b1905489
JB		 1882 {
1883 switch (prefix)
1884 {
1885 default:
1886 abort ();
1887
1888 case CS_PREFIX_OPCODE:
1889 case DS_PREFIX_OPCODE:
1890 case ES_PREFIX_OPCODE:
1891 case FS_PREFIX_OPCODE:
1892 case GS_PREFIX_OPCODE:
1893 case SS_PREFIX_OPCODE:
1894 q = SEG_PREFIX;
1895 break;
1896
1897 case REPNE_PREFIX_OPCODE:
1898 case REPE_PREFIX_OPCODE:
c32fa91d
L		 1899 q = REP_PREFIX;
1900 ret = PREFIX_REP;
1901 break;
1902
b1905489 1903 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 1904 q = LOCK_PREFIX;
1905 ret = PREFIX_LOCK;
b1905489
JB		 1906 break;
1907
1908 case FWAIT_OPCODE:
1909 q = WAIT_PREFIX;
1910 break;
1911
1912 case ADDR_PREFIX_OPCODE:
1913 q = ADDR_PREFIX;
1914 break;
1915
1916 case DATA_PREFIX_OPCODE:
1917 q = DATA_PREFIX;
1918 break;
1919 }
1920 if (i.prefix[q] != 0)
c32fa91d 1921 ret = PREFIX_EXIST;
b1905489 1922 }
252b5132 1923
b1905489 1924 if (ret)
252b5132 1925 {
b1905489
JB		 1926 if (!i.prefix[q])
1927 ++i.prefixes;
1928 i.prefix[q] |= prefix;
252b5132 1929 }
b1905489
JB		 1930 else
1931 as_bad (_("same type of prefix used twice"));
252b5132 1932
252b5132
RH		 1933 return ret;
1934}
1935
1936static void
78f12dd3 1937update_code_flag (int value, int check)
eecb386c 1938{
78f12dd3
L		 1939 PRINTF_LIKE ((*as_error));
1940
1e9cc1c2 1941 flag_code = (enum flag_code) value;
40fb9820
L		 1942 if (flag_code == CODE_64BIT)
1943 {
1944 cpu_arch_flags.bitfield.cpu64 = 1;
1945 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 1946 }
1947 else
1948 {
1949 cpu_arch_flags.bitfield.cpu64 = 0;
1950 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 1951 }
1952 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 1953 {
78f12dd3
L		 1954 if (check)
1955 as_error = as_fatal;
1956 else
1957 as_error = as_bad;
1958 (*as_error) (_("64bit mode not supported on `%s'."),
1959 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 1960 }
40fb9820 1961 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 1962 {
78f12dd3
L		 1963 if (check)
1964 as_error = as_fatal;
1965 else
1966 as_error = as_bad;
1967 (*as_error) (_("32bit mode not supported on `%s'."),
1968 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 1969 }
eecb386c
AM		 1970 stackop_size = '\0';
1971}
1972
78f12dd3
L		 1973static void
1974set_code_flag (int value)
1975{
1976 update_code_flag (value, 0);
1977}
1978
eecb386c 1979static void
e3bb37b5 1980set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1981{
1e9cc1c2 1982 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 1983 if (flag_code != CODE_16BIT)
1984 abort ();
1985 cpu_arch_flags.bitfield.cpu64 = 0;
1986 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 1987 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1988}
1989
1990static void
e3bb37b5 1991set_intel_syntax (int syntax_flag)
252b5132
RH		 1992{
1993 /* Find out if register prefixing is specified. */
1994 int ask_naked_reg = 0;
1995
1996 SKIP_WHITESPACE ();
29b0f896 1997 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1998 {
1999 char *string = input_line_pointer;
2000 int e = get_symbol_end ();
2001
47926f60 2002 if (strcmp (string, "prefix") == 0)
252b5132 2003 ask_naked_reg = 1;
47926f60 2004 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2005 ask_naked_reg = -1;
2006 else
d0b47220 2007 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 2008 *input_line_pointer = e;
2009 }
2010 demand_empty_rest_of_line ();
c3332e24 2011
252b5132
RH		 2012 intel_syntax = syntax_flag;
2013
2014 if (ask_naked_reg == 0)
f86103b7
AM		 2015 allow_naked_reg = (intel_syntax
2016 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2017 else
2018 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2019
ee86248c 2020 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2021
e4a3b5a4 2022 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2023 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2024 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2025}
2026
1efbbeb4
L		 2027static void
2028set_intel_mnemonic (int mnemonic_flag)
2029{
e1d4d893 2030 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2031}
2032
db51cc60
L		 2033static void
2034set_allow_index_reg (int flag)
2035{
2036 allow_index_reg = flag;
2037}
2038
cb19c032
L		 2039static void
2040set_sse_check (int dummy ATTRIBUTE_UNUSED)
2041{
2042 SKIP_WHITESPACE ();
2043
2044 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2045 {
2046 char *string = input_line_pointer;
2047 int e = get_symbol_end ();
2048
2049 if (strcmp (string, "none") == 0)
2050 sse_check = sse_check_none;
2051 else if (strcmp (string, "warning") == 0)
2052 sse_check = sse_check_warning;
2053 else if (strcmp (string, "error") == 0)
2054 sse_check = sse_check_error;
2055 else
2056 as_bad (_("bad argument to sse_check directive."));
2057 *input_line_pointer = e;
2058 }
2059 else
2060 as_bad (_("missing argument for sse_check directive"));
2061
2062 demand_empty_rest_of_line ();
2063}
2064
8a9036a4
L		 2065static void
2066check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2067 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2068{
2069#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2070 static const char *arch;
2071
2072 /* Intel LIOM is only supported on ELF. */
2073 if (!IS_ELF)
2074 return;
2075
2076 if (!arch)
2077 {
2078 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2079 use default_arch. */
2080 arch = cpu_arch_name;
2081 if (!arch)
2082 arch = default_arch;
2083 }
2084
3632d14b 2085 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2086 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2087 || new_flag.bitfield.cpul1om)
8a9036a4 2088 return;
76ba9986 2089
8a9036a4
L		 2090 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2091#endif
2092}
2093
e413e4e9 2094static void
e3bb37b5 2095set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2096{
47926f60 2097 SKIP_WHITESPACE ();
e413e4e9 2098
29b0f896 2099 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 2100 {
2101 char *string = input_line_pointer;
2102 int e = get_symbol_end ();
91d6fa6a 2103 unsigned int j;
40fb9820 2104 i386_cpu_flags flags;
e413e4e9 2105
91d6fa6a 2106 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2107 {
91d6fa6a 2108 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2109 {
91d6fa6a 2110 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2111
5c6af06e
JB		 2112 if (*string != '.')
2113 {
91d6fa6a 2114 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2115 cpu_sub_arch_name = NULL;
91d6fa6a 2116 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2117 if (flag_code == CODE_64BIT)
2118 {
2119 cpu_arch_flags.bitfield.cpu64 = 1;
2120 cpu_arch_flags.bitfield.cpuno64 = 0;
2121 }
2122 else
2123 {
2124 cpu_arch_flags.bitfield.cpu64 = 0;
2125 cpu_arch_flags.bitfield.cpuno64 = 1;
2126 }
91d6fa6a
NC		 2127 cpu_arch_isa = cpu_arch[j].type;
2128 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2129 if (!cpu_arch_tune_set)
2130 {
2131 cpu_arch_tune = cpu_arch_isa;
2132 cpu_arch_tune_flags = cpu_arch_isa_flags;
2133 }
5c6af06e
JB		 2134 break;
2135 }
40fb9820 2136
22109423 2137 if (!cpu_arch[j].negated)
309d3373 2138 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 2139 cpu_arch[j].flags);
309d3373
JB		 2140 else
2141 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 2142 cpu_arch[j].flags);
0dfbf9d7 2143 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2144 {
6305a203
L		 2145 if (cpu_sub_arch_name)
2146 {
2147 char *name = cpu_sub_arch_name;
2148 cpu_sub_arch_name = concat (name,
91d6fa6a 2149 cpu_arch[j].name,
1bf57e9f 2150 (const char *) NULL);
6305a203
L		 2151 free (name);
2152 }
2153 else
91d6fa6a 2154 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2155 cpu_arch_flags = flags;
5c6af06e
JB		 2156 }
2157 *input_line_pointer = e;
2158 demand_empty_rest_of_line ();
2159 return;
e413e4e9
AM		 2160 }
2161 }
91d6fa6a 2162 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2163 as_bad (_("no such architecture: `%s'"), string);
2164
2165 *input_line_pointer = e;
2166 }
2167 else
2168 as_bad (_("missing cpu architecture"));
2169
fddf5b5b
AM		 2170 no_cond_jump_promotion = 0;
2171 if (*input_line_pointer == ','
29b0f896 2172 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 2173 {
2174 char *string = ++input_line_pointer;
2175 int e = get_symbol_end ();
2176
2177 if (strcmp (string, "nojumps") == 0)
2178 no_cond_jump_promotion = 1;
2179 else if (strcmp (string, "jumps") == 0)
2180 ;
2181 else
2182 as_bad (_("no such architecture modifier: `%s'"), string);
2183
2184 *input_line_pointer = e;
2185 }
2186
e413e4e9
AM		 2187 demand_empty_rest_of_line ();
2188}
2189
8a9036a4
L		 2190enum bfd_architecture
2191i386_arch (void)
2192{
3632d14b 2193 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2194 {
2195 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2196 || flag_code != CODE_64BIT)
2197 as_fatal (_("Intel L1OM is 64bit ELF only"));
2198 return bfd_arch_l1om;
2199 }
2200 else
2201 return bfd_arch_i386;
2202}
2203
b9d79e03
JH		 2204unsigned long
2205i386_mach ()
2206{
2207 if (!strcmp (default_arch, "x86_64"))
8a9036a4 2208 {
3632d14b 2209 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2210 {
2211 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2212 as_fatal (_("Intel L1OM is 64bit ELF only"));
2213 return bfd_mach_l1om;
2214 }
2215 else
2216 return bfd_mach_x86_64;
2217 }
b9d79e03
JH		 2218 else if (!strcmp (default_arch, "i386"))
2219 return bfd_mach_i386_i386;
2220 else
2221 as_fatal (_("Unknown architecture"));
2222}
b9d79e03 2223\f
252b5132
RH		 2224void
2225md_begin ()
2226{
2227 const char *hash_err;
2228
47926f60 2229 /* Initialize op_hash hash table. */
252b5132
RH		 2230 op_hash = hash_new ();
2231
2232 {
d3ce72d0 2233 const insn_template *optab;
29b0f896 2234 templates *core_optab;
252b5132 2235
47926f60
KH		 2236 /* Setup for loop. */
2237 optab = i386_optab;
252b5132
RH		 2238 core_optab = (templates *) xmalloc (sizeof (templates));
2239 core_optab->start = optab;
2240
2241 while (1)
2242 {
2243 ++optab;
2244 if (optab->name == NULL
2245 || strcmp (optab->name, (optab - 1)->name) != 0)
2246 {
2247 /* different name --> ship out current template list;
47926f60 2248 add to hash table; & begin anew. */
252b5132
RH		 2249 core_optab->end = optab;
2250 hash_err = hash_insert (op_hash,
2251 (optab - 1)->name,
5a49b8ac 2252 (void *) core_optab);
252b5132
RH		 2253 if (hash_err)
2254 {
252b5132
RH		 2255 as_fatal (_("Internal Error: Can't hash %s: %s"),
2256 (optab - 1)->name,
2257 hash_err);
2258 }
2259 if (optab->name == NULL)
2260 break;
2261 core_optab = (templates *) xmalloc (sizeof (templates));
2262 core_optab->start = optab;
2263 }
2264 }
2265 }
2266
47926f60 2267 /* Initialize reg_hash hash table. */
252b5132
RH		 2268 reg_hash = hash_new ();
2269 {
29b0f896 2270 const reg_entry *regtab;
c3fe08fa 2271 unsigned int regtab_size = i386_regtab_size;
252b5132 2272
c3fe08fa 2273 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2274 {
5a49b8ac 2275 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2276 if (hash_err)
3e73aa7c
JH		 2277 as_fatal (_("Internal Error: Can't hash %s: %s"),
2278 regtab->reg_name,
2279 hash_err);
252b5132
RH		 2280 }
2281 }
2282
47926f60 2283 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2284 {
29b0f896
AM		 2285 int c;
2286 char *p;
252b5132
RH		 2287
2288 for (c = 0; c < 256; c++)
2289 {
3882b010 2290 if (ISDIGIT (c))
252b5132
RH		 2291 {
2292 digit_chars[c] = c;
2293 mnemonic_chars[c] = c;
2294 register_chars[c] = c;
2295 operand_chars[c] = c;
2296 }
3882b010 2297 else if (ISLOWER (c))
252b5132
RH		 2298 {
2299 mnemonic_chars[c] = c;
2300 register_chars[c] = c;
2301 operand_chars[c] = c;
2302 }
3882b010 2303 else if (ISUPPER (c))
252b5132 2304 {
3882b010 2305 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2306 register_chars[c] = mnemonic_chars[c];
2307 operand_chars[c] = c;
2308 }
2309
3882b010 2310 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2311 identifier_chars[c] = c;
2312 else if (c >= 128)
2313 {
2314 identifier_chars[c] = c;
2315 operand_chars[c] = c;
2316 }
2317 }
2318
2319#ifdef LEX_AT
2320 identifier_chars['@'] = '@';
32137342
NC		 2321#endif
2322#ifdef LEX_QM
2323 identifier_chars['?'] = '?';
2324 operand_chars['?'] = '?';
252b5132 2325#endif
252b5132 2326 digit_chars['-'] = '-';
c0f3af97 2327 mnemonic_chars['_'] = '_';
791fe849 2328 mnemonic_chars['-'] = '-';
0003779b 2329 mnemonic_chars['.'] = '.';
252b5132
RH		 2330 identifier_chars['_'] = '_';
2331 identifier_chars['.'] = '.';
2332
2333 for (p = operand_special_chars; *p != '\0'; p++)
2334 operand_chars[(unsigned char) *p] = *p;
2335 }
2336
2337#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2338 if (IS_ELF)
252b5132
RH		 2339 {
2340 record_alignment (text_section, 2);
2341 record_alignment (data_section, 2);
2342 record_alignment (bss_section, 2);
2343 }
2344#endif
a4447b93
RH		 2345
2346 if (flag_code == CODE_64BIT)
2347 {
2348 x86_dwarf2_return_column = 16;
2349 x86_cie_data_alignment = -8;
2350 }
2351 else
2352 {
2353 x86_dwarf2_return_column = 8;
2354 x86_cie_data_alignment = -4;
2355 }
252b5132
RH		 2356}
2357
2358void
e3bb37b5 2359i386_print_statistics (FILE *file)
252b5132
RH		 2360{
2361 hash_print_statistics (file, "i386 opcode", op_hash);
2362 hash_print_statistics (file, "i386 register", reg_hash);
2363}
2364\f
252b5132
RH		 2365#ifdef DEBUG386
2366
ce8a8b2f 2367/* Debugging routines for md_assemble. */
d3ce72d0 2368static void pte (insn_template *);
40fb9820 2369static void pt (i386_operand_type);
e3bb37b5
L		 2370static void pe (expressionS *);
2371static void ps (symbolS *);
252b5132
RH		 2372
2373static void
e3bb37b5 2374pi (char *line, i386_insn *x)
252b5132 2375{
09137c09 2376 unsigned int j;
252b5132
RH		 2377
2378 fprintf (stdout, "%s: template ", line);
2379 pte (&x->tm);
09f131f2
JH		 2380 fprintf (stdout, " address: base %s index %s scale %x\n",
2381 x->base_reg ? x->base_reg->reg_name : "none",
2382 x->index_reg ? x->index_reg->reg_name : "none",
2383 x->log2_scale_factor);
2384 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2385 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2386 fprintf (stdout, " sib: base %x index %x scale %x\n",
2387 x->sib.base, x->sib.index, x->sib.scale);
2388 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2389 (x->rex & REX_W) != 0,
2390 (x->rex & REX_R) != 0,
2391 (x->rex & REX_X) != 0,
2392 (x->rex & REX_B) != 0);
09137c09 2393 for (j = 0; j < x->operands; j++)
252b5132 2394 {
09137c09
SP		 2395 fprintf (stdout, " #%d: ", j + 1);
2396 pt (x->types[j]);
252b5132 2397 fprintf (stdout, "\n");
09137c09
SP		 2398 if (x->types[j].bitfield.reg8
2399 || x->types[j].bitfield.reg16
2400 || x->types[j].bitfield.reg32
2401 || x->types[j].bitfield.reg64
2402 || x->types[j].bitfield.regmmx
2403 || x->types[j].bitfield.regxmm
2404 || x->types[j].bitfield.regymm
2405 || x->types[j].bitfield.sreg2
2406 || x->types[j].bitfield.sreg3
2407 || x->types[j].bitfield.control
2408 || x->types[j].bitfield.debug
2409 || x->types[j].bitfield.test)
2410 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2411 if (operand_type_check (x->types[j], imm))
2412 pe (x->op[j].imms);
2413 if (operand_type_check (x->types[j], disp))
2414 pe (x->op[j].disps);
252b5132
RH		 2415 }
2416}
2417
2418static void
d3ce72d0 2419pte (insn_template *t)
252b5132 2420{
09137c09 2421 unsigned int j;
252b5132 2422 fprintf (stdout, " %d operands ", t->operands);
47926f60 2423 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2424 if (t->extension_opcode != None)
2425 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2426 if (t->opcode_modifier.d)
252b5132 2427 fprintf (stdout, "D");
40fb9820 2428 if (t->opcode_modifier.w)
252b5132
RH		 2429 fprintf (stdout, "W");
2430 fprintf (stdout, "\n");
09137c09 2431 for (j = 0; j < t->operands; j++)
252b5132 2432 {
09137c09
SP		 2433 fprintf (stdout, " #%d type ", j + 1);
2434 pt (t->operand_types[j]);
252b5132
RH		 2435 fprintf (stdout, "\n");
2436 }
2437}
2438
2439static void
e3bb37b5 2440pe (expressionS *e)
252b5132 2441{
24eab124 2442 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2443 fprintf (stdout, " add_number %ld (%lx)\n",
2444 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2445 if (e->X_add_symbol)
2446 {
2447 fprintf (stdout, " add_symbol ");
2448 ps (e->X_add_symbol);
2449 fprintf (stdout, "\n");
2450 }
2451 if (e->X_op_symbol)
2452 {
2453 fprintf (stdout, " op_symbol ");
2454 ps (e->X_op_symbol);
2455 fprintf (stdout, "\n");
2456 }
2457}
2458
2459static void
e3bb37b5 2460ps (symbolS *s)
252b5132
RH		 2461{
2462 fprintf (stdout, "%s type %s%s",
2463 S_GET_NAME (s),
2464 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2465 segment_name (S_GET_SEGMENT (s)));
2466}
2467
7b81dfbb 2468static struct type_name
252b5132 2469 {
40fb9820
L		 2470 i386_operand_type mask;
2471 const char *name;
252b5132 2472 }
7b81dfbb 2473const type_names[] =
252b5132 2474{
40fb9820
L		 2475 { OPERAND_TYPE_REG8, "r8" },
2476 { OPERAND_TYPE_REG16, "r16" },
2477 { OPERAND_TYPE_REG32, "r32" },
2478 { OPERAND_TYPE_REG64, "r64" },
2479 { OPERAND_TYPE_IMM8, "i8" },
2480 { OPERAND_TYPE_IMM8, "i8s" },
2481 { OPERAND_TYPE_IMM16, "i16" },
2482 { OPERAND_TYPE_IMM32, "i32" },
2483 { OPERAND_TYPE_IMM32S, "i32s" },
2484 { OPERAND_TYPE_IMM64, "i64" },
2485 { OPERAND_TYPE_IMM1, "i1" },
2486 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2487 { OPERAND_TYPE_DISP8, "d8" },
2488 { OPERAND_TYPE_DISP16, "d16" },
2489 { OPERAND_TYPE_DISP32, "d32" },
2490 { OPERAND_TYPE_DISP32S, "d32s" },
2491 { OPERAND_TYPE_DISP64, "d64" },
2492 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2493 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2494 { OPERAND_TYPE_CONTROL, "control reg" },
2495 { OPERAND_TYPE_TEST, "test reg" },
2496 { OPERAND_TYPE_DEBUG, "debug reg" },
2497 { OPERAND_TYPE_FLOATREG, "FReg" },
2498 { OPERAND_TYPE_FLOATACC, "FAcc" },
2499 { OPERAND_TYPE_SREG2, "SReg2" },
2500 { OPERAND_TYPE_SREG3, "SReg3" },
2501 { OPERAND_TYPE_ACC, "Acc" },
2502 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2503 { OPERAND_TYPE_REGMMX, "rMMX" },
2504 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2505 { OPERAND_TYPE_REGYMM, "rYMM" },
40fb9820 2506 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2507};
2508
2509static void
40fb9820 2510pt (i386_operand_type t)
252b5132 2511{
40fb9820 2512 unsigned int j;
c6fb90c8 2513 i386_operand_type a;
252b5132 2514
40fb9820 2515 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2516 {
2517 a = operand_type_and (t, type_names[j].mask);
0349dc08 2518 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2519 fprintf (stdout, "%s, ", type_names[j].name);
2520 }
252b5132
RH		 2521 fflush (stdout);
2522}
2523
2524#endif /* DEBUG386 */
2525\f
252b5132 2526static bfd_reloc_code_real_type
3956db08 2527reloc (unsigned int size,
64e74474
AM		 2528 int pcrel,
2529 int sign,
2530 bfd_reloc_code_real_type other)
252b5132 2531{
47926f60 2532 if (other != NO_RELOC)
3956db08 2533 {
91d6fa6a 2534 reloc_howto_type *rel;
3956db08
JB		 2535
2536 if (size == 8)
2537 switch (other)
2538 {
64e74474
AM		 2539 case BFD_RELOC_X86_64_GOT32:
2540 return BFD_RELOC_X86_64_GOT64;
2541 break;
2542 case BFD_RELOC_X86_64_PLTOFF64:
2543 return BFD_RELOC_X86_64_PLTOFF64;
2544 break;
2545 case BFD_RELOC_X86_64_GOTPC32:
2546 other = BFD_RELOC_X86_64_GOTPC64;
2547 break;
2548 case BFD_RELOC_X86_64_GOTPCREL:
2549 other = BFD_RELOC_X86_64_GOTPCREL64;
2550 break;
2551 case BFD_RELOC_X86_64_TPOFF32:
2552 other = BFD_RELOC_X86_64_TPOFF64;
2553 break;
2554 case BFD_RELOC_X86_64_DTPOFF32:
2555 other = BFD_RELOC_X86_64_DTPOFF64;
2556 break;
2557 default:
2558 break;
3956db08 2559 }
e05278af
JB		 2560
2561 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2562 if (size == 4 && flag_code != CODE_64BIT)
2563 sign = -1;
2564
91d6fa6a
NC		 2565 rel = bfd_reloc_type_lookup (stdoutput, other);
2566 if (!rel)
3956db08 2567 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2568 else if (size != bfd_get_reloc_size (rel))
3956db08 2569 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2570 bfd_get_reloc_size (rel),
3956db08 2571 size);
91d6fa6a 2572 else if (pcrel && !rel->pc_relative)
3956db08 2573 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2574 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2575 && !sign)
91d6fa6a 2576 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2577 && sign > 0))
3956db08
JB		 2578 as_bad (_("relocated field and relocation type differ in signedness"));
2579 else
2580 return other;
2581 return NO_RELOC;
2582 }
252b5132
RH		 2583
2584 if (pcrel)
2585 {
3e73aa7c 2586 if (!sign)
3956db08 2587 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2588 switch (size)
2589 {
2590 case 1: return BFD_RELOC_8_PCREL;
2591 case 2: return BFD_RELOC_16_PCREL;
2592 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2593 case 8: return BFD_RELOC_64_PCREL;
252b5132 2594 }
3956db08 2595 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2596 }
2597 else
2598 {
3956db08 2599 if (sign > 0)
e5cb08ac 2600 switch (size)
3e73aa7c
JH		 2601 {
2602 case 4: return BFD_RELOC_X86_64_32S;
2603 }
2604 else
2605 switch (size)
2606 {
2607 case 1: return BFD_RELOC_8;
2608 case 2: return BFD_RELOC_16;
2609 case 4: return BFD_RELOC_32;
2610 case 8: return BFD_RELOC_64;
2611 }
3956db08
JB		 2612 as_bad (_("cannot do %s %u byte relocation"),
2613 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2614 }
2615
0cc9e1d3 2616 return NO_RELOC;
252b5132
RH		 2617}
2618
47926f60
KH		 2619/* Here we decide which fixups can be adjusted to make them relative to
2620 the beginning of the section instead of the symbol. Basically we need
2621 to make sure that the dynamic relocations are done correctly, so in
2622 some cases we force the original symbol to be used. */
2623
252b5132 2624int
e3bb37b5 2625tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2626{
6d249963 2627#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2628 if (!IS_ELF)
31312f95
AM		 2629 return 1;
2630
a161fe53
AM		 2631 /* Don't adjust pc-relative references to merge sections in 64-bit
2632 mode. */
2633 if (use_rela_relocations
2634 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2635 && fixP->fx_pcrel)
252b5132 2636 return 0;
31312f95 2637
8d01d9a9
AJ		 2638 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2639 and changed later by validate_fix. */
2640 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2641 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2642 return 0;
2643
ce8a8b2f 2644 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 2645 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2646 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2647 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2648 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2649 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2650 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2651 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2652 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2653 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2654 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2655 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2656 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2657 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2658 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2659 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2660 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2661 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2662 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2663 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2664 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2665 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2666 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2667 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2668 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2669 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2670 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2671 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2672 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2673 return 0;
31312f95 2674#endif
252b5132
RH		 2675 return 1;
2676}
252b5132 2677
b4cac588 2678static int
e3bb37b5 2679intel_float_operand (const char *mnemonic)
252b5132 2680{
9306ca4a
JB		 2681 /* Note that the value returned is meaningful only for opcodes with (memory)
2682 operands, hence the code here is free to improperly handle opcodes that
2683 have no operands (for better performance and smaller code). */
2684
2685 if (mnemonic[0] != 'f')
2686 return 0; /* non-math */
2687
2688 switch (mnemonic[1])
2689 {
2690 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2691 the fs segment override prefix not currently handled because no
2692 call path can make opcodes without operands get here */
2693 case 'i':
2694 return 2 /* integer op */;
2695 case 'l':
2696 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2697 return 3; /* fldcw/fldenv */
2698 break;
2699 case 'n':
2700 if (mnemonic[2] != 'o' /* fnop */)
2701 return 3; /* non-waiting control op */
2702 break;
2703 case 'r':
2704 if (mnemonic[2] == 's')
2705 return 3; /* frstor/frstpm */
2706 break;
2707 case 's':
2708 if (mnemonic[2] == 'a')
2709 return 3; /* fsave */
2710 if (mnemonic[2] == 't')
2711 {
2712 switch (mnemonic[3])
2713 {
2714 case 'c': /* fstcw */
2715 case 'd': /* fstdw */
2716 case 'e': /* fstenv */
2717 case 's': /* fsts[gw] */
2718 return 3;
2719 }
2720 }
2721 break;
2722 case 'x':
2723 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2724 return 0; /* fxsave/fxrstor are not really math ops */
2725 break;
2726 }
252b5132 2727
9306ca4a 2728 return 1;
252b5132
RH		 2729}
2730
c0f3af97
L		 2731/* Build the VEX prefix. */
2732
2733static void
d3ce72d0 2734build_vex_prefix (const insn_template *t)
c0f3af97
L		 2735{
2736 unsigned int register_specifier;
2737 unsigned int implied_prefix;
2738 unsigned int vector_length;
2739
2740 /* Check register specifier. */
2741 if (i.vex.register_specifier)
2742 {
2743 register_specifier = i.vex.register_specifier->reg_num;
2744 if ((i.vex.register_specifier->reg_flags & RegRex))
2745 register_specifier += 8;
2746 register_specifier = ~register_specifier & 0xf;
2747 }
2748 else
2749 register_specifier = 0xf;
2750
fa99fab2
L		 2751 /* Use 2-byte VEX prefix by swappping destination and source
2752 operand. */
2753 if (!i.swap_operand
2754 && i.operands == i.reg_operands
7f399153 2755 && i.tm.opcode_modifier.vexopcode == VEX0F
fa99fab2
L		 2756 && i.tm.opcode_modifier.s
2757 && i.rex == REX_B)
2758 {
2759 unsigned int xchg = i.operands - 1;
2760 union i386_op temp_op;
2761 i386_operand_type temp_type;
2762
2763 temp_type = i.types[xchg];
2764 i.types[xchg] = i.types[0];
2765 i.types[0] = temp_type;
2766 temp_op = i.op[xchg];
2767 i.op[xchg] = i.op[0];
2768 i.op[0] = temp_op;
2769
9c2799c2 2770 gas_assert (i.rm.mode == 3);
fa99fab2
L		 2771
2772 i.rex = REX_R;
2773 xchg = i.rm.regmem;
2774 i.rm.regmem = i.rm.reg;
2775 i.rm.reg = xchg;
2776
2777 /* Use the next insn. */
2778 i.tm = t[1];
2779 }
2780
539f890d
L		 2781 if (i.tm.opcode_modifier.vex == VEXScalar)
2782 vector_length = avxscalar;
2783 else
2784 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 2785
2786 switch ((i.tm.base_opcode >> 8) & 0xff)
2787 {
2788 case 0:
2789 implied_prefix = 0;
2790 break;
2791 case DATA_PREFIX_OPCODE:
2792 implied_prefix = 1;
2793 break;
2794 case REPE_PREFIX_OPCODE:
2795 implied_prefix = 2;
2796 break;
2797 case REPNE_PREFIX_OPCODE:
2798 implied_prefix = 3;
2799 break;
2800 default:
2801 abort ();
2802 }
2803
2804 /* Use 2-byte VEX prefix if possible. */
7f399153 2805 if (i.tm.opcode_modifier.vexopcode == VEX0F
c0f3af97
L		 2806 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
2807 {
2808 /* 2-byte VEX prefix. */
2809 unsigned int r;
2810
2811 i.vex.length = 2;
2812 i.vex.bytes[0] = 0xc5;
2813
2814 /* Check the REX.R bit. */
2815 r = (i.rex & REX_R) ? 0 : 1;
2816 i.vex.bytes[1] = (r << 7
2817 | register_specifier << 3
2818 | vector_length << 2
2819 | implied_prefix);
2820 }
2821 else
2822 {
2823 /* 3-byte VEX prefix. */
2824 unsigned int m, w;
2825
f88c9eb0 2826 i.vex.length = 3;
f88c9eb0 2827
7f399153 2828 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 2829 {
7f399153
L		 2830 case VEX0F:
2831 m = 0x1;
80de6e00 2832 i.vex.bytes[0] = 0xc4;
7f399153
L		 2833 break;
2834 case VEX0F38:
2835 m = 0x2;
80de6e00 2836 i.vex.bytes[0] = 0xc4;
7f399153
L		 2837 break;
2838 case VEX0F3A:
2839 m = 0x3;
80de6e00 2840 i.vex.bytes[0] = 0xc4;
7f399153
L		 2841 break;
2842 case XOP08:
5dd85c99
SP		 2843 m = 0x8;
2844 i.vex.bytes[0] = 0x8f;
7f399153
L		 2845 break;
2846 case XOP09:
f88c9eb0
SP		 2847 m = 0x9;
2848 i.vex.bytes[0] = 0x8f;
7f399153
L		 2849 break;
2850 case XOP0A:
f88c9eb0
SP		 2851 m = 0xa;
2852 i.vex.bytes[0] = 0x8f;
7f399153
L		 2853 break;
2854 default:
2855 abort ();
f88c9eb0 2856 }
c0f3af97 2857
c0f3af97
L		 2858 /* The high 3 bits of the second VEX byte are 1's compliment
2859 of RXB bits from REX. */
2860 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
2861
2862 /* Check the REX.W bit. */
2863 w = (i.rex & REX_W) ? 1 : 0;
1ef99a7b 2864 if (i.tm.opcode_modifier.vexw)
c0f3af97
L		 2865 {
2866 if (w)
2867 abort ();
2868
1ef99a7b 2869 if (i.tm.opcode_modifier.vexw == VEXW1)
c0f3af97
L		 2870 w = 1;
2871 }
2872
2873 i.vex.bytes[2] = (w << 7
2874 | register_specifier << 3
2875 | vector_length << 2
2876 | implied_prefix);
2877 }
2878}
2879
65da13b5
L		 2880static void
2881process_immext (void)
2882{
2883 expressionS *exp;
2884
2885 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2886 {
1fed0ba1
L		 2887 /* SSE3 Instructions have the fixed operands with an opcode
2888 suffix which is coded in the same place as an 8-bit immediate
2889 field would be. Here we check those operands and remove them
2890 afterwards. */
65da13b5
L		 2891 unsigned int x;
2892
2893 for (x = 0; x < i.operands; x++)
2894 if (i.op[x].regs->reg_num != x)
2895 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 2896 register_prefix, i.op[x].regs->reg_name, x + 1,
2897 i.tm.name);
2898
2899 i.operands = 0;
65da13b5
L		 2900 }
2901
c0f3af97 2902 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 2903 which is coded in the same place as an 8-bit immediate field
2904 would be. Here we fake an 8-bit immediate operand from the
2905 opcode suffix stored in tm.extension_opcode.
2906
c1e679ec 2907 AVX instructions also use this encoding, for some of
c0f3af97 2908 3 argument instructions. */
65da13b5 2909
9c2799c2 2910 gas_assert (i.imm_operands == 0
7ab9ffdd
L		 2911 && (i.operands <= 2
2912 || (i.tm.opcode_modifier.vex
2913 && i.operands <= 4)));
65da13b5
L		 2914
2915 exp = &im_expressions[i.imm_operands++];
2916 i.op[i.operands].imms = exp;
2917 i.types[i.operands] = imm8;
2918 i.operands++;
2919 exp->X_op = O_constant;
2920 exp->X_add_number = i.tm.extension_opcode;
2921 i.tm.extension_opcode = None;
2922}
2923
252b5132
RH		 2924/* This is the guts of the machine-dependent assembler. LINE points to a
2925 machine dependent instruction. This function is supposed to emit
2926 the frags/bytes it assembles to. */
2927
2928void
65da13b5 2929md_assemble (char *line)
252b5132 2930{
40fb9820 2931 unsigned int j;
252b5132 2932 char mnemonic[MAX_MNEM_SIZE];
d3ce72d0 2933 const insn_template *t;
252b5132 2934
47926f60 2935 /* Initialize globals. */
252b5132
RH		 2936 memset (&i, '\0', sizeof (i));
2937 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 2938 i.reloc[j] = NO_RELOC;
252b5132
RH		 2939 memset (disp_expressions, '\0', sizeof (disp_expressions));
2940 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 2941 save_stack_p = save_stack;
252b5132
RH		 2942
2943 /* First parse an instruction mnemonic & call i386_operand for the operands.
2944 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 2945 start of a (possibly prefixed) mnemonic. */
252b5132 2946
29b0f896
AM		 2947 line = parse_insn (line, mnemonic);
2948 if (line == NULL)
2949 return;
252b5132 2950
29b0f896 2951 line = parse_operands (line, mnemonic);
ee86248c 2952 this_operand = -1;
29b0f896
AM		 2953 if (line == NULL)
2954 return;
252b5132 2955
29b0f896
AM		 2956 /* Now we've parsed the mnemonic into a set of templates, and have the
2957 operands at hand. */
2958
2959 /* All intel opcodes have reversed operands except for "bound" and
2960 "enter". We also don't reverse intersegment "jmp" and "call"
2961 instructions with 2 immediate operands so that the immediate segment
050dfa73 2962 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 2963 if (intel_syntax
2964 && i.operands > 1
29b0f896 2965 && (strcmp (mnemonic, "bound") != 0)
30123838 2966 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 2967 && !(operand_type_check (i.types[0], imm)
2968 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 2969 swap_operands ();
2970
ec56d5c0
JB		 2971 /* The order of the immediates should be reversed
2972 for 2 immediates extrq and insertq instructions */
2973 if (i.imm_operands == 2
2974 && (strcmp (mnemonic, "extrq") == 0
2975 || strcmp (mnemonic, "insertq") == 0))
2976 swap_2_operands (0, 1);
2977
29b0f896
AM		 2978 if (i.imm_operands)
2979 optimize_imm ();
2980
b300c311
L		 2981 /* Don't optimize displacement for movabs since it only takes 64bit
2982 displacement. */
2983 if (i.disp_operands
2984 && (flag_code != CODE_64BIT
2985 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 2986 optimize_disp ();
2987
2988 /* Next, we find a template that matches the given insn,
2989 making sure the overlap of the given operands types is consistent
2990 with the template operand types. */
252b5132 2991
fa99fab2 2992 if (!(t = match_template ()))
29b0f896 2993 return;
252b5132 2994
daf50ae7 2995 if (sse_check != sse_check_none
81f8a913 2996 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 2997 && (i.tm.cpu_flags.bitfield.cpusse
2998 || i.tm.cpu_flags.bitfield.cpusse2
2999 || i.tm.cpu_flags.bitfield.cpusse3
3000 || i.tm.cpu_flags.bitfield.cpussse3
3001 || i.tm.cpu_flags.bitfield.cpusse4_1
3002 || i.tm.cpu_flags.bitfield.cpusse4_2))
3003 {
3004 (sse_check == sse_check_warning
3005 ? as_warn
3006 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3007 }
3008
321fd21e
L		 3009 /* Zap movzx and movsx suffix. The suffix has been set from
3010 "word ptr" or "byte ptr" on the source operand in Intel syntax
3011 or extracted from mnemonic in AT&T syntax. But we'll use
3012 the destination register to choose the suffix for encoding. */
3013 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3014 {
321fd21e
L		 3015 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3016 there is no suffix, the default will be byte extension. */
3017 if (i.reg_operands != 2
3018 && !i.suffix
7ab9ffdd 3019 && intel_syntax)
321fd21e
L		 3020 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3021
3022 i.suffix = 0;
cd61ebfe 3023 }
24eab124 3024
40fb9820 3025 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3026 if (!add_prefix (FWAIT_OPCODE))
3027 return;
252b5132 3028
c1ba0266
L		 3029 /* Check for lock without a lockable instruction. Destination operand
3030 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3031 if (i.prefix[LOCK_PREFIX]
3032 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3033 || i.mem_operands == 0
3034 || (i.tm.base_opcode != 0x86
3035 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3036 {
3037 as_bad (_("expecting lockable instruction after `lock'"));
3038 return;
3039 }
3040
29b0f896 3041 /* Check string instruction segment overrides. */
40fb9820 3042 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3043 {
3044 if (!check_string ())
5dd0794d 3045 return;
fc0763e6 3046 i.disp_operands = 0;
29b0f896 3047 }
5dd0794d 3048
29b0f896
AM		 3049 if (!process_suffix ())
3050 return;
e413e4e9 3051
bc0844ae
L		 3052 /* Update operand types. */
3053 for (j = 0; j < i.operands; j++)
3054 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3055
29b0f896
AM		 3056 /* Make still unresolved immediate matches conform to size of immediate
3057 given in i.suffix. */
3058 if (!finalize_imm ())
3059 return;
252b5132 3060
40fb9820 3061 if (i.types[0].bitfield.imm1)
29b0f896 3062 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3063
9afe6eb8
L		 3064 /* We only need to check those implicit registers for instructions
3065 with 3 operands or less. */
3066 if (i.operands <= 3)
3067 for (j = 0; j < i.operands; j++)
3068 if (i.types[j].bitfield.inoutportreg
3069 || i.types[j].bitfield.shiftcount
3070 || i.types[j].bitfield.acc
3071 || i.types[j].bitfield.floatacc)
3072 i.reg_operands--;
40fb9820 3073
c0f3af97
L		 3074 /* ImmExt should be processed after SSE2AVX. */
3075 if (!i.tm.opcode_modifier.sse2avx
3076 && i.tm.opcode_modifier.immext)
65da13b5 3077 process_immext ();
252b5132 3078
29b0f896
AM		 3079 /* For insns with operands there are more diddles to do to the opcode. */
3080 if (i.operands)
3081 {
3082 if (!process_operands ())
3083 return;
3084 }
40fb9820 3085 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3086 {
3087 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3088 as_warn (_("translating to `%sp'"), i.tm.name);
3089 }
252b5132 3090
c0f3af97 3091 if (i.tm.opcode_modifier.vex)
fa99fab2 3092 build_vex_prefix (t);
c0f3af97 3093
5dd85c99
SP		 3094 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3095 instructions may define INT_OPCODE as well, so avoid this corner
3096 case for those instructions that use MODRM. */
3097 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3098 && !i.tm.opcode_modifier.modrm
3099 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3100 {
3101 i.tm.base_opcode = INT3_OPCODE;
3102 i.imm_operands = 0;
3103 }
252b5132 3104
40fb9820
L		 3105 if ((i.tm.opcode_modifier.jump
3106 || i.tm.opcode_modifier.jumpbyte
3107 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3108 && i.op[0].disps->X_op == O_constant)
3109 {
3110 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3111 the absolute address given by the constant. Since ix86 jumps and
3112 calls are pc relative, we need to generate a reloc. */
3113 i.op[0].disps->X_add_symbol = &abs_symbol;
3114 i.op[0].disps->X_op = O_symbol;
3115 }
252b5132 3116
40fb9820 3117 if (i.tm.opcode_modifier.rex64)
161a04f6 3118 i.rex |= REX_W;
252b5132 3119
29b0f896
AM		 3120 /* For 8 bit registers we need an empty rex prefix. Also if the
3121 instruction already has a prefix, we need to convert old
3122 registers to new ones. */
773f551c 3123
40fb9820 3124 if ((i.types[0].bitfield.reg8
29b0f896 3125 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3126 || (i.types[1].bitfield.reg8
29b0f896 3127 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3128 || ((i.types[0].bitfield.reg8
3129 || i.types[1].bitfield.reg8)
29b0f896
AM		 3130 && i.rex != 0))
3131 {
3132 int x;
726c5dcd 3133
29b0f896
AM		 3134 i.rex |= REX_OPCODE;
3135 for (x = 0; x < 2; x++)
3136 {
3137 /* Look for 8 bit operand that uses old registers. */
40fb9820 3138 if (i.types[x].bitfield.reg8
29b0f896 3139 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3140 {
29b0f896
AM		 3141 /* In case it is "hi" register, give up. */
3142 if (i.op[x].regs->reg_num > 3)
a540244d 3143 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3144 "instruction requiring REX prefix."),
a540244d 3145 register_prefix, i.op[x].regs->reg_name);
773f551c 3146
29b0f896
AM		 3147 /* Otherwise it is equivalent to the extended register.
3148 Since the encoding doesn't change this is merely
3149 cosmetic cleanup for debug output. */
3150
3151 i.op[x].regs = i.op[x].regs + 8;
773f551c 3152 }
29b0f896
AM		 3153 }
3154 }
773f551c 3155
7ab9ffdd 3156 if (i.rex != 0)
29b0f896
AM		 3157 add_prefix (REX_OPCODE | i.rex);
3158
3159 /* We are ready to output the insn. */
3160 output_insn ();
3161}
3162
3163static char *
e3bb37b5 3164parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3165{
3166 char *l = line;
3167 char *token_start = l;
3168 char *mnem_p;
5c6af06e 3169 int supported;
d3ce72d0 3170 const insn_template *t;
b6169b20 3171 char *dot_p = NULL;
29b0f896
AM		 3172
3173 /* Non-zero if we found a prefix only acceptable with string insns. */
3174 const char *expecting_string_instruction = NULL;
45288df1 3175
29b0f896
AM		 3176 while (1)
3177 {
3178 mnem_p = mnemonic;
3179 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3180 {
b6169b20
L		 3181 if (*mnem_p == '.')
3182 dot_p = mnem_p;
29b0f896
AM		 3183 mnem_p++;
3184 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3185 {
29b0f896
AM		 3186 as_bad (_("no such instruction: `%s'"), token_start);
3187 return NULL;
3188 }
3189 l++;
3190 }
3191 if (!is_space_char (*l)
3192 && *l != END_OF_INSN
e44823cf
JB		 3193 && (intel_syntax
3194 || (*l != PREFIX_SEPARATOR
3195 && *l != ',')))
29b0f896
AM		 3196 {
3197 as_bad (_("invalid character %s in mnemonic"),
3198 output_invalid (*l));
3199 return NULL;
3200 }
3201 if (token_start == l)
3202 {
e44823cf 3203 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3204 as_bad (_("expecting prefix; got nothing"));
3205 else
3206 as_bad (_("expecting mnemonic; got nothing"));
3207 return NULL;
3208 }
45288df1 3209
29b0f896 3210 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3211 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3212
29b0f896
AM		 3213 if (*l != END_OF_INSN
3214 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3215 && current_templates
40fb9820 3216 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3217 {
c6fb90c8 3218 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3219 {
3220 as_bad ((flag_code != CODE_64BIT
3221 ? _("`%s' is only supported in 64-bit mode")
3222 : _("`%s' is not supported in 64-bit mode")),
3223 current_templates->start->name);
3224 return NULL;
3225 }
29b0f896
AM		 3226 /* If we are in 16-bit mode, do not allow addr16 or data16.
3227 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3228 if ((current_templates->start->opcode_modifier.size16
3229 || current_templates->start->opcode_modifier.size32)
29b0f896 3230 && flag_code != CODE_64BIT
40fb9820 3231 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3232 ^ (flag_code == CODE_16BIT)))
3233 {
3234 as_bad (_("redundant %s prefix"),
3235 current_templates->start->name);
3236 return NULL;
45288df1 3237 }
29b0f896
AM		 3238 /* Add prefix, checking for repeated prefixes. */
3239 switch (add_prefix (current_templates->start->base_opcode))
3240 {
c32fa91d 3241 case PREFIX_EXIST:
29b0f896 3242 return NULL;
c32fa91d 3243 case PREFIX_REP:
29b0f896
AM		 3244 expecting_string_instruction = current_templates->start->name;
3245 break;
c32fa91d
L		 3246 default:
3247 break;
29b0f896
AM		 3248 }
3249 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3250 token_start = ++l;
3251 }
3252 else
3253 break;
3254 }
45288df1 3255
30a55f88 3256 if (!current_templates)
b6169b20 3257 {
30a55f88
L		 3258 /* Check if we should swap operand in encoding. */
3259 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3260 i.swap_operand = 1;
3261 else
3262 goto check_suffix;
3263 mnem_p = dot_p;
3264 *dot_p = '\0';
d3ce72d0 3265 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3266 }
3267
29b0f896
AM		 3268 if (!current_templates)
3269 {
b6169b20 3270check_suffix:
29b0f896
AM		 3271 /* See if we can get a match by trimming off a suffix. */
3272 switch (mnem_p[-1])
3273 {
3274 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3275 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3276 i.suffix = SHORT_MNEM_SUFFIX;
3277 else
29b0f896
AM		 3278 case BYTE_MNEM_SUFFIX:
3279 case QWORD_MNEM_SUFFIX:
3280 i.suffix = mnem_p[-1];
3281 mnem_p[-1] = '\0';
d3ce72d0
NC		 3282 current_templates = (const templates *) hash_find (op_hash,
3283 mnemonic);
29b0f896
AM		 3284 break;
3285 case SHORT_MNEM_SUFFIX:
3286 case LONG_MNEM_SUFFIX:
3287 if (!intel_syntax)
3288 {
3289 i.suffix = mnem_p[-1];
3290 mnem_p[-1] = '\0';
d3ce72d0
NC		 3291 current_templates = (const templates *) hash_find (op_hash,
3292 mnemonic);
29b0f896
AM		 3293 }
3294 break;
252b5132 3295
29b0f896
AM		 3296 /* Intel Syntax. */
3297 case 'd':
3298 if (intel_syntax)
3299 {
9306ca4a 3300 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3301 i.suffix = SHORT_MNEM_SUFFIX;
3302 else
3303 i.suffix = LONG_MNEM_SUFFIX;
3304 mnem_p[-1] = '\0';
d3ce72d0
NC		 3305 current_templates = (const templates *) hash_find (op_hash,
3306 mnemonic);
29b0f896
AM		 3307 }
3308 break;
3309 }
3310 if (!current_templates)
3311 {
3312 as_bad (_("no such instruction: `%s'"), token_start);
3313 return NULL;
3314 }
3315 }
252b5132 3316
40fb9820
L		 3317 if (current_templates->start->opcode_modifier.jump
3318 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3319 {
3320 /* Check for a branch hint. We allow ",pt" and ",pn" for
3321 predict taken and predict not taken respectively.
3322 I'm not sure that branch hints actually do anything on loop
3323 and jcxz insns (JumpByte) for current Pentium4 chips. They
3324 may work in the future and it doesn't hurt to accept them
3325 now. */
3326 if (l[0] == ',' && l[1] == 'p')
3327 {
3328 if (l[2] == 't')
3329 {
3330 if (!add_prefix (DS_PREFIX_OPCODE))
3331 return NULL;
3332 l += 3;
3333 }
3334 else if (l[2] == 'n')
3335 {
3336 if (!add_prefix (CS_PREFIX_OPCODE))
3337 return NULL;
3338 l += 3;
3339 }
3340 }
3341 }
3342 /* Any other comma loses. */
3343 if (*l == ',')
3344 {
3345 as_bad (_("invalid character %s in mnemonic"),
3346 output_invalid (*l));
3347 return NULL;
3348 }
252b5132 3349
29b0f896 3350 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3351 supported = 0;
3352 for (t = current_templates->start; t < current_templates->end; ++t)
3353 {
c0f3af97
L		 3354 supported |= cpu_flags_match (t);
3355 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3356 goto skip;
5c6af06e 3357 }
3629bb00 3358
c0f3af97 3359 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3360 {
3361 as_bad (flag_code == CODE_64BIT
3362 ? _("`%s' is not supported in 64-bit mode")
3363 : _("`%s' is only supported in 64-bit mode"),
3364 current_templates->start->name);
3365 return NULL;
3366 }
c0f3af97 3367 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3368 {
3629bb00 3369 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 3370 current_templates->start->name,
41aacd83 3371 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3372 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3373 return NULL;
29b0f896 3374 }
3629bb00
L		 3375
3376skip:
3377 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3378 && (flag_code != CODE_16BIT))
29b0f896
AM		 3379 {
3380 as_warn (_("use .code16 to ensure correct addressing mode"));
3381 }
252b5132 3382
29b0f896 3383 /* Check for rep/repne without a string instruction. */
f41bbced 3384 if (expecting_string_instruction)
29b0f896 3385 {
f41bbced
JB		 3386 static templates override;
3387
3388 for (t = current_templates->start; t < current_templates->end; ++t)
40fb9820 3389 if (t->opcode_modifier.isstring)
f41bbced
JB		 3390 break;
3391 if (t >= current_templates->end)
3392 {
3393 as_bad (_("expecting string instruction after `%s'"),
64e74474 3394 expecting_string_instruction);
f41bbced
JB		 3395 return NULL;
3396 }
3397 for (override.start = t; t < current_templates->end; ++t)
40fb9820 3398 if (!t->opcode_modifier.isstring)
f41bbced
JB		 3399 break;
3400 override.end = t;
3401 current_templates = &override;
29b0f896 3402 }
252b5132 3403
29b0f896
AM		 3404 return l;
3405}
252b5132 3406
29b0f896 3407static char *
e3bb37b5 3408parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3409{
3410 char *token_start;
3138f287 3411
29b0f896
AM		 3412 /* 1 if operand is pending after ','. */
3413 unsigned int expecting_operand = 0;
252b5132 3414
29b0f896
AM		 3415 /* Non-zero if operand parens not balanced. */
3416 unsigned int paren_not_balanced;
3417
3418 while (*l != END_OF_INSN)
3419 {
3420 /* Skip optional white space before operand. */
3421 if (is_space_char (*l))
3422 ++l;
3423 if (!is_operand_char (*l) && *l != END_OF_INSN)
3424 {
3425 as_bad (_("invalid character %s before operand %d"),
3426 output_invalid (*l),
3427 i.operands + 1);
3428 return NULL;
3429 }
3430 token_start = l; /* after white space */
3431 paren_not_balanced = 0;
3432 while (paren_not_balanced || *l != ',')
3433 {
3434 if (*l == END_OF_INSN)
3435 {
3436 if (paren_not_balanced)
3437 {
3438 if (!intel_syntax)
3439 as_bad (_("unbalanced parenthesis in operand %d."),
3440 i.operands + 1);
3441 else
3442 as_bad (_("unbalanced brackets in operand %d."),
3443 i.operands + 1);
3444 return NULL;
3445 }
3446 else
3447 break; /* we are done */
3448 }
3449 else if (!is_operand_char (*l) && !is_space_char (*l))
3450 {
3451 as_bad (_("invalid character %s in operand %d"),
3452 output_invalid (*l),
3453 i.operands + 1);
3454 return NULL;
3455 }
3456 if (!intel_syntax)
3457 {
3458 if (*l == '(')
3459 ++paren_not_balanced;
3460 if (*l == ')')
3461 --paren_not_balanced;
3462 }
3463 else
3464 {
3465 if (*l == '[')
3466 ++paren_not_balanced;
3467 if (*l == ']')
3468 --paren_not_balanced;
3469 }
3470 l++;
3471 }
3472 if (l != token_start)
3473 { /* Yes, we've read in another operand. */
3474 unsigned int operand_ok;
3475 this_operand = i.operands++;
7d5e4556 3476 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 3477 if (i.operands > MAX_OPERANDS)
3478 {
3479 as_bad (_("spurious operands; (%d operands/instruction max)"),
3480 MAX_OPERANDS);
3481 return NULL;
3482 }
3483 /* Now parse operand adding info to 'i' as we go along. */
3484 END_STRING_AND_SAVE (l);
3485
3486 if (intel_syntax)
3487 operand_ok =
3488 i386_intel_operand (token_start,
3489 intel_float_operand (mnemonic));
3490 else
a7619375 3491 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 3492
3493 RESTORE_END_STRING (l);
3494 if (!operand_ok)
3495 return NULL;
3496 }
3497 else
3498 {
3499 if (expecting_operand)
3500 {
3501 expecting_operand_after_comma:
3502 as_bad (_("expecting operand after ','; got nothing"));
3503 return NULL;
3504 }
3505 if (*l == ',')
3506 {
3507 as_bad (_("expecting operand before ','; got nothing"));
3508 return NULL;
3509 }
3510 }
7f3f1ea2 3511
29b0f896
AM		 3512 /* Now *l must be either ',' or END_OF_INSN. */
3513 if (*l == ',')
3514 {
3515 if (*++l == END_OF_INSN)
3516 {
3517 /* Just skip it, if it's \n complain. */
3518 goto expecting_operand_after_comma;
3519 }
3520 expecting_operand = 1;
3521 }
3522 }
3523 return l;
3524}
7f3f1ea2 3525
050dfa73 3526static void
4d456e3d 3527swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 3528{
3529 union i386_op temp_op;
40fb9820 3530 i386_operand_type temp_type;
050dfa73 3531 enum bfd_reloc_code_real temp_reloc;
4eed87de 3532
050dfa73
MM		 3533 temp_type = i.types[xchg2];
3534 i.types[xchg2] = i.types[xchg1];
3535 i.types[xchg1] = temp_type;
3536 temp_op = i.op[xchg2];
3537 i.op[xchg2] = i.op[xchg1];
3538 i.op[xchg1] = temp_op;
3539 temp_reloc = i.reloc[xchg2];
3540 i.reloc[xchg2] = i.reloc[xchg1];
3541 i.reloc[xchg1] = temp_reloc;
3542}
3543
29b0f896 3544static void
e3bb37b5 3545swap_operands (void)
29b0f896 3546{
b7c61d9a 3547 switch (i.operands)
050dfa73 3548 {
c0f3af97 3549 case 5:
b7c61d9a 3550 case 4:
4d456e3d 3551 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 3552 case 3:
3553 case 2:
4d456e3d 3554 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 3555 break;
3556 default:
3557 abort ();
29b0f896 3558 }
29b0f896
AM		 3559
3560 if (i.mem_operands == 2)
3561 {
3562 const seg_entry *temp_seg;
3563 temp_seg = i.seg[0];
3564 i.seg[0] = i.seg[1];
3565 i.seg[1] = temp_seg;
3566 }
3567}
252b5132 3568
29b0f896
AM		 3569/* Try to ensure constant immediates are represented in the smallest
3570 opcode possible. */
3571static void
e3bb37b5 3572optimize_imm (void)
29b0f896
AM		 3573{
3574 char guess_suffix = 0;
3575 int op;
252b5132 3576
29b0f896
AM		 3577 if (i.suffix)
3578 guess_suffix = i.suffix;
3579 else if (i.reg_operands)
3580 {
3581 /* Figure out a suffix from the last register operand specified.
3582 We can't do this properly yet, ie. excluding InOutPortReg,
3583 but the following works for instructions with immediates.
3584 In any case, we can't set i.suffix yet. */
3585 for (op = i.operands; --op >= 0;)
40fb9820 3586 if (i.types[op].bitfield.reg8)
7ab9ffdd 3587 {
40fb9820
L		 3588 guess_suffix = BYTE_MNEM_SUFFIX;
3589 break;
3590 }
3591 else if (i.types[op].bitfield.reg16)
252b5132 3592 {
40fb9820
L		 3593 guess_suffix = WORD_MNEM_SUFFIX;
3594 break;
3595 }
3596 else if (i.types[op].bitfield.reg32)
3597 {
3598 guess_suffix = LONG_MNEM_SUFFIX;
3599 break;
3600 }
3601 else if (i.types[op].bitfield.reg64)
3602 {
3603 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 3604 break;
252b5132 3605 }
29b0f896
AM		 3606 }
3607 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3608 guess_suffix = WORD_MNEM_SUFFIX;
3609
3610 for (op = i.operands; --op >= 0;)
40fb9820 3611 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 3612 {
3613 switch (i.op[op].imms->X_op)
252b5132 3614 {
29b0f896
AM		 3615 case O_constant:
3616 /* If a suffix is given, this operand may be shortened. */
3617 switch (guess_suffix)
252b5132 3618 {
29b0f896 3619 case LONG_MNEM_SUFFIX:
40fb9820
L		 3620 i.types[op].bitfield.imm32 = 1;
3621 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3622 break;
3623 case WORD_MNEM_SUFFIX:
40fb9820
L		 3624 i.types[op].bitfield.imm16 = 1;
3625 i.types[op].bitfield.imm32 = 1;
3626 i.types[op].bitfield.imm32s = 1;
3627 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3628 break;
3629 case BYTE_MNEM_SUFFIX:
40fb9820
L		 3630 i.types[op].bitfield.imm8 = 1;
3631 i.types[op].bitfield.imm8s = 1;
3632 i.types[op].bitfield.imm16 = 1;
3633 i.types[op].bitfield.imm32 = 1;
3634 i.types[op].bitfield.imm32s = 1;
3635 i.types[op].bitfield.imm64 = 1;
29b0f896 3636 break;
252b5132 3637 }
252b5132 3638
29b0f896
AM		 3639 /* If this operand is at most 16 bits, convert it
3640 to a signed 16 bit number before trying to see
3641 whether it will fit in an even smaller size.
3642 This allows a 16-bit operand such as $0xffe0 to
3643 be recognised as within Imm8S range. */
40fb9820 3644 if ((i.types[op].bitfield.imm16)
29b0f896 3645 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 3646 {
29b0f896
AM		 3647 i.op[op].imms->X_add_number =
3648 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3649 }
40fb9820 3650 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 3651 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3652 == 0))
3653 {
3654 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3655 ^ ((offsetT) 1 << 31))
3656 - ((offsetT) 1 << 31));
3657 }
40fb9820 3658 i.types[op]
c6fb90c8
L		 3659 = operand_type_or (i.types[op],
3660 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 3661
29b0f896
AM		 3662 /* We must avoid matching of Imm32 templates when 64bit
3663 only immediate is available. */
3664 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 3665 i.types[op].bitfield.imm32 = 0;
29b0f896 3666 break;
252b5132 3667
29b0f896
AM		 3668 case O_absent:
3669 case O_register:
3670 abort ();
3671
3672 /* Symbols and expressions. */
3673 default:
9cd96992
JB		 3674 /* Convert symbolic operand to proper sizes for matching, but don't
3675 prevent matching a set of insns that only supports sizes other
3676 than those matching the insn suffix. */
3677 {
40fb9820 3678 i386_operand_type mask, allowed;
d3ce72d0 3679 const insn_template *t;
9cd96992 3680
0dfbf9d7
L		 3681 operand_type_set (&mask, 0);
3682 operand_type_set (&allowed, 0);
40fb9820 3683
4eed87de
AM		 3684 for (t = current_templates->start;
3685 t < current_templates->end;
3686 ++t)
c6fb90c8
L		 3687 allowed = operand_type_or (allowed,
3688 t->operand_types[op]);
9cd96992
JB		 3689 switch (guess_suffix)
3690 {
3691 case QWORD_MNEM_SUFFIX:
40fb9820
L		 3692 mask.bitfield.imm64 = 1;
3693 mask.bitfield.imm32s = 1;
9cd96992
JB		 3694 break;
3695 case LONG_MNEM_SUFFIX:
40fb9820 3696 mask.bitfield.imm32 = 1;
9cd96992
JB		 3697 break;
3698 case WORD_MNEM_SUFFIX:
40fb9820 3699 mask.bitfield.imm16 = 1;
9cd96992
JB		 3700 break;
3701 case BYTE_MNEM_SUFFIX:
40fb9820 3702 mask.bitfield.imm8 = 1;
9cd96992
JB		 3703 break;
3704 default:
9cd96992
JB		 3705 break;
3706 }
c6fb90c8 3707 allowed = operand_type_and (mask, allowed);
0dfbf9d7 3708 if (!operand_type_all_zero (&allowed))
c6fb90c8 3709 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 3710 }
29b0f896 3711 break;
252b5132 3712 }
29b0f896
AM		 3713 }
3714}
47926f60 3715
29b0f896
AM		 3716/* Try to use the smallest displacement type too. */
3717static void
e3bb37b5 3718optimize_disp (void)
29b0f896
AM		 3719{
3720 int op;
3e73aa7c 3721
29b0f896 3722 for (op = i.operands; --op >= 0;)
40fb9820 3723 if (operand_type_check (i.types[op], disp))
252b5132 3724 {
b300c311 3725 if (i.op[op].disps->X_op == O_constant)
252b5132 3726 {
91d6fa6a 3727 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 3728
40fb9820 3729 if (i.types[op].bitfield.disp16
91d6fa6a 3730 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 3731 {
3732 /* If this operand is at most 16 bits, convert
3733 to a signed 16 bit number and don't use 64bit
3734 displacement. */
91d6fa6a 3735 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 3736 i.types[op].bitfield.disp64 = 0;
b300c311 3737 }
40fb9820 3738 if (i.types[op].bitfield.disp32
91d6fa6a 3739 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 3740 {
3741 /* If this operand is at most 32 bits, convert
3742 to a signed 32 bit number and don't use 64bit
3743 displacement. */
91d6fa6a
NC		 3744 op_disp &= (((offsetT) 2 << 31) - 1);
3745 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 3746 i.types[op].bitfield.disp64 = 0;
b300c311 3747 }
91d6fa6a 3748 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 3749 {
40fb9820
L		 3750 i.types[op].bitfield.disp8 = 0;
3751 i.types[op].bitfield.disp16 = 0;
3752 i.types[op].bitfield.disp32 = 0;
3753 i.types[op].bitfield.disp32s = 0;
3754 i.types[op].bitfield.disp64 = 0;
b300c311
L		 3755 i.op[op].disps = 0;
3756 i.disp_operands--;
3757 }
3758 else if (flag_code == CODE_64BIT)
3759 {
91d6fa6a 3760 if (fits_in_signed_long (op_disp))
28a9d8f5 3761 {
40fb9820
L		 3762 i.types[op].bitfield.disp64 = 0;
3763 i.types[op].bitfield.disp32s = 1;
28a9d8f5 3764 }
0e1147d9 3765 if (i.prefix[ADDR_PREFIX]
91d6fa6a 3766 && fits_in_unsigned_long (op_disp))
40fb9820 3767 i.types[op].bitfield.disp32 = 1;
b300c311 3768 }
40fb9820
L		 3769 if ((i.types[op].bitfield.disp32
3770 || i.types[op].bitfield.disp32s
3771 || i.types[op].bitfield.disp16)
91d6fa6a 3772 && fits_in_signed_byte (op_disp))
40fb9820 3773 i.types[op].bitfield.disp8 = 1;
252b5132 3774 }
67a4f2b7
AO		 3775 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3776 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3777 {
3778 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3779 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 3780 i.types[op].bitfield.disp8 = 0;
3781 i.types[op].bitfield.disp16 = 0;
3782 i.types[op].bitfield.disp32 = 0;
3783 i.types[op].bitfield.disp32s = 0;
3784 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 3785 }
3786 else
b300c311 3787 /* We only support 64bit displacement on constants. */
40fb9820 3788 i.types[op].bitfield.disp64 = 0;
252b5132 3789 }
29b0f896
AM		 3790}
3791
a683cc34
SP		 3792/* Check if operands are valid for the instrucrtion. Update VEX
3793 operand types. */
3794
3795static int
3796VEX_check_operands (const insn_template *t)
3797{
3798 if (!t->opcode_modifier.vex)
3799 return 0;
3800
3801 /* Only check VEX_Imm4, which must be the first operand. */
3802 if (t->operand_types[0].bitfield.vec_imm4)
3803 {
3804 if (i.op[0].imms->X_op != O_constant
3805 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 3806 {
a65babc9 3807 i.error = bad_imm4;
891edac4
L		 3808 return 1;
3809 }
a683cc34
SP		 3810
3811 /* Turn off Imm8 so that update_imm won't complain. */
3812 i.types[0] = vec_imm4;
3813 }
3814
3815 return 0;
3816}
3817
d3ce72d0 3818static const insn_template *
e3bb37b5 3819match_template (void)
29b0f896
AM		 3820{
3821 /* Points to template once we've found it. */
d3ce72d0 3822 const insn_template *t;
40fb9820 3823 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 3824 i386_operand_type overlap4;
29b0f896 3825 unsigned int found_reverse_match;
40fb9820
L		 3826 i386_opcode_modifier suffix_check;
3827 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 3828 int addr_prefix_disp;
a5c311ca 3829 unsigned int j;
3629bb00 3830 unsigned int found_cpu_match;
45664ddb 3831 unsigned int check_register;
29b0f896 3832
c0f3af97
L		 3833#if MAX_OPERANDS != 5
3834# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 3835#endif
3836
29b0f896 3837 found_reverse_match = 0;
539e75ad 3838 addr_prefix_disp = -1;
40fb9820
L		 3839
3840 memset (&suffix_check, 0, sizeof (suffix_check));
3841 if (i.suffix == BYTE_MNEM_SUFFIX)
3842 suffix_check.no_bsuf = 1;
3843 else if (i.suffix == WORD_MNEM_SUFFIX)
3844 suffix_check.no_wsuf = 1;
3845 else if (i.suffix == SHORT_MNEM_SUFFIX)
3846 suffix_check.no_ssuf = 1;
3847 else if (i.suffix == LONG_MNEM_SUFFIX)
3848 suffix_check.no_lsuf = 1;
3849 else if (i.suffix == QWORD_MNEM_SUFFIX)
3850 suffix_check.no_qsuf = 1;
3851 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 3852 suffix_check.no_ldsuf = 1;
29b0f896 3853
01559ecc
L		 3854 /* Must have right number of operands. */
3855 i.error = number_of_operands_mismatch;
3856
45aa61fe 3857 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 3858 {
539e75ad
L		 3859 addr_prefix_disp = -1;
3860
29b0f896
AM		 3861 if (i.operands != t->operands)
3862 continue;
3863
50aecf8c 3864 /* Check processor support. */
a65babc9 3865 i.error = unsupported;
c0f3af97
L		 3866 found_cpu_match = (cpu_flags_match (t)
3867 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 3868 if (!found_cpu_match)
3869 continue;
3870
e1d4d893 3871 /* Check old gcc support. */
a65babc9 3872 i.error = old_gcc_only;
e1d4d893
L		 3873 if (!old_gcc && t->opcode_modifier.oldgcc)
3874 continue;
3875
3876 /* Check AT&T mnemonic. */
a65babc9 3877 i.error = unsupported_with_intel_mnemonic;
e1d4d893 3878 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 3879 continue;
3880
891edac4 3881 /* Check AT&T/Intel syntax. */
a65babc9 3882 i.error = unsupported_syntax;
5c07affc
L		 3883 if ((intel_syntax && t->opcode_modifier.attsyntax)
3884 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 3885 continue;
3886
20592a94 3887 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 3888 i.error = invalid_instruction_suffix;
567e4e96
L		 3889 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3890 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3891 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3892 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3893 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3894 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3895 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 3896 continue;
3897
5c07affc 3898 if (!operand_size_match (t))
7d5e4556 3899 continue;
539e75ad 3900
5c07affc
L		 3901 for (j = 0; j < MAX_OPERANDS; j++)
3902 operand_types[j] = t->operand_types[j];
3903
45aa61fe
AM		 3904 /* In general, don't allow 64-bit operands in 32-bit mode. */
3905 if (i.suffix == QWORD_MNEM_SUFFIX
3906 && flag_code != CODE_64BIT
3907 && (intel_syntax
40fb9820 3908 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 3909 && !intel_float_operand (t->name))
3910 : intel_float_operand (t->name) != 2)
40fb9820 3911 && ((!operand_types[0].bitfield.regmmx
c0f3af97
L		 3912 && !operand_types[0].bitfield.regxmm
3913 && !operand_types[0].bitfield.regymm)
40fb9820 3914 || (!operand_types[t->operands > 1].bitfield.regmmx
c0f3af97
L		 3915 && !!operand_types[t->operands > 1].bitfield.regxmm
3916 && !!operand_types[t->operands > 1].bitfield.regymm))
45aa61fe
AM		 3917 && (t->base_opcode != 0x0fc7
3918 || t->extension_opcode != 1 /* cmpxchg8b */))
3919 continue;
3920
192dc9c6
JB		 3921 /* In general, don't allow 32-bit operands on pre-386. */
3922 else if (i.suffix == LONG_MNEM_SUFFIX
3923 && !cpu_arch_flags.bitfield.cpui386
3924 && (intel_syntax
3925 ? (!t->opcode_modifier.ignoresize
3926 && !intel_float_operand (t->name))
3927 : intel_float_operand (t->name) != 2)
3928 && ((!operand_types[0].bitfield.regmmx
3929 && !operand_types[0].bitfield.regxmm)
3930 || (!operand_types[t->operands > 1].bitfield.regmmx
3931 && !!operand_types[t->operands > 1].bitfield.regxmm)))
3932 continue;
3933
29b0f896 3934 /* Do not verify operands when there are none. */
50aecf8c 3935 else
29b0f896 3936 {
c6fb90c8 3937 if (!t->operands)
2dbab7d5
L		 3938 /* We've found a match; break out of loop. */
3939 break;
29b0f896 3940 }
252b5132 3941
539e75ad
L		 3942 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3943 into Disp32/Disp16/Disp32 operand. */
3944 if (i.prefix[ADDR_PREFIX] != 0)
3945 {
40fb9820 3946 /* There should be only one Disp operand. */
539e75ad
L		 3947 switch (flag_code)
3948 {
3949 case CODE_16BIT:
40fb9820
L		 3950 for (j = 0; j < MAX_OPERANDS; j++)
3951 {
3952 if (operand_types[j].bitfield.disp16)
3953 {
3954 addr_prefix_disp = j;
3955 operand_types[j].bitfield.disp32 = 1;
3956 operand_types[j].bitfield.disp16 = 0;
3957 break;
3958 }
3959 }
539e75ad
L		 3960 break;
3961 case CODE_32BIT:
40fb9820
L		 3962 for (j = 0; j < MAX_OPERANDS; j++)
3963 {
3964 if (operand_types[j].bitfield.disp32)
3965 {
3966 addr_prefix_disp = j;
3967 operand_types[j].bitfield.disp32 = 0;
3968 operand_types[j].bitfield.disp16 = 1;
3969 break;
3970 }
3971 }
539e75ad
L		 3972 break;
3973 case CODE_64BIT:
40fb9820
L		 3974 for (j = 0; j < MAX_OPERANDS; j++)
3975 {
3976 if (operand_types[j].bitfield.disp64)
3977 {
3978 addr_prefix_disp = j;
3979 operand_types[j].bitfield.disp64 = 0;
3980 operand_types[j].bitfield.disp32 = 1;
3981 break;
3982 }
3983 }
539e75ad
L		 3984 break;
3985 }
539e75ad
L		 3986 }
3987
45664ddb
L		 3988 /* We check register size only if size of operands can be
3989 encoded the canonical way. */
3990 check_register = t->opcode_modifier.w;
c6fb90c8 3991 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 3992 switch (t->operands)
3993 {
3994 case 1:
40fb9820 3995 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 3996 continue;
3997 break;
3998 case 2:
8b38ad71
L		 3999 /* xchg %eax, %eax is a special case. It is an aliase for nop
4000 only in 32bit mode and we can use opcode 0x90. In 64bit
4001 mode, we can't use 0x90 for xchg %eax, %eax since it should
4002 zero-extend %eax to %rax. */
4003 if (flag_code == CODE_64BIT
4004 && t->base_opcode == 0x90
0dfbf9d7
L		 4005 && operand_type_equal (&i.types [0], &acc32)
4006 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 4007 continue;
b6169b20
L		 4008 if (i.swap_operand)
4009 {
4010 /* If we swap operand in encoding, we either match
4011 the next one or reverse direction of operands. */
4012 if (t->opcode_modifier.s)
4013 continue;
4014 else if (t->opcode_modifier.d)
4015 goto check_reverse;
4016 }
4017
29b0f896 4018 case 3:
fa99fab2
L		 4019 /* If we swap operand in encoding, we match the next one. */
4020 if (i.swap_operand && t->opcode_modifier.s)
4021 continue;
f48ff2ae 4022 case 4:
c0f3af97 4023 case 5:
c6fb90c8 4024 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 4025 if (!operand_type_match (overlap0, i.types[0])
4026 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4027 || (check_register
4028 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 4029 operand_types[0],
4030 overlap1, i.types[1],
4031 operand_types[1])))
29b0f896
AM		 4032 {
4033 /* Check if other direction is valid ... */
40fb9820 4034 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 4035 continue;
4036
b6169b20 4037check_reverse:
29b0f896 4038 /* Try reversing direction of operands. */
c6fb90c8
L		 4039 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4040 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 4041 if (!operand_type_match (overlap0, i.types[0])
4042 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4043 || (check_register
4044 && !operand_type_register_match (overlap0,
4045 i.types[0],
4046 operand_types[1],
4047 overlap1,
4048 i.types[1],
4049 operand_types[0])))
29b0f896
AM		 4050 {
4051 /* Does not match either direction. */
4052 continue;
4053 }
4054 /* found_reverse_match holds which of D or FloatDR
4055 we've found. */
40fb9820 4056 if (t->opcode_modifier.d)
8a2ed489 4057 found_reverse_match = Opcode_D;
40fb9820 4058 else if (t->opcode_modifier.floatd)
8a2ed489
L		 4059 found_reverse_match = Opcode_FloatD;
4060 else
4061 found_reverse_match = 0;
40fb9820 4062 if (t->opcode_modifier.floatr)
8a2ed489 4063 found_reverse_match |= Opcode_FloatR;
29b0f896 4064 }
f48ff2ae 4065 else
29b0f896 4066 {
f48ff2ae 4067 /* Found a forward 2 operand match here. */
d1cbb4db
L		 4068 switch (t->operands)
4069 {
c0f3af97
L		 4070 case 5:
4071 overlap4 = operand_type_and (i.types[4],
4072 operand_types[4]);
d1cbb4db 4073 case 4:
c6fb90c8
L		 4074 overlap3 = operand_type_and (i.types[3],
4075 operand_types[3]);
d1cbb4db 4076 case 3:
c6fb90c8
L		 4077 overlap2 = operand_type_and (i.types[2],
4078 operand_types[2]);
d1cbb4db
L		 4079 break;
4080 }
29b0f896 4081
f48ff2ae
L		 4082 switch (t->operands)
4083 {
c0f3af97
L		 4084 case 5:
4085 if (!operand_type_match (overlap4, i.types[4])
4086 || !operand_type_register_match (overlap3,
4087 i.types[3],
4088 operand_types[3],
4089 overlap4,
4090 i.types[4],
4091 operand_types[4]))
4092 continue;
f48ff2ae 4093 case 4:
40fb9820 4094 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 4095 || (check_register
4096 && !operand_type_register_match (overlap2,
4097 i.types[2],
4098 operand_types[2],
4099 overlap3,
4100 i.types[3],
4101 operand_types[3])))
f48ff2ae
L		 4102 continue;
4103 case 3:
4104 /* Here we make use of the fact that there are no
4105 reverse match 3 operand instructions, and all 3
4106 operand instructions only need to be checked for
4107 register consistency between operands 2 and 3. */
40fb9820 4108 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 4109 || (check_register
4110 && !operand_type_register_match (overlap1,
4111 i.types[1],
4112 operand_types[1],
4113 overlap2,
4114 i.types[2],
4115 operand_types[2])))
f48ff2ae
L		 4116 continue;
4117 break;
4118 }
29b0f896 4119 }
f48ff2ae 4120 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 4121 slip through to break. */
4122 }
3629bb00 4123 if (!found_cpu_match)
29b0f896
AM		 4124 {
4125 found_reverse_match = 0;
4126 continue;
4127 }
c0f3af97 4128
a683cc34
SP		 4129 /* Check if VEX operands are valid. */
4130 if (VEX_check_operands (t))
4131 continue;
4132
29b0f896
AM		 4133 /* We've found a match; break out of loop. */
4134 break;
4135 }
4136
4137 if (t == current_templates->end)
4138 {
4139 /* We found no match. */
a65babc9
L		 4140 const char *err_msg;
4141 switch (i.error)
4142 {
4143 default:
4144 abort ();
86e026a4 4145 case operand_size_mismatch:
a65babc9
L		 4146 err_msg = _("operand size mismatch");
4147 break;
4148 case operand_type_mismatch:
4149 err_msg = _("operand type mismatch");
4150 break;
4151 case register_type_mismatch:
4152 err_msg = _("register type mismatch");
4153 break;
4154 case number_of_operands_mismatch:
4155 err_msg = _("number of operands mismatch");
4156 break;
4157 case invalid_instruction_suffix:
4158 err_msg = _("invalid instruction suffix");
4159 break;
4160 case bad_imm4:
4161 err_msg = _("Imm4 isn't the first operand");
4162 break;
4163 case old_gcc_only:
4164 err_msg = _("only supported with old gcc");
4165 break;
4166 case unsupported_with_intel_mnemonic:
4167 err_msg = _("unsupported with Intel mnemonic");
4168 break;
4169 case unsupported_syntax:
4170 err_msg = _("unsupported syntax");
4171 break;
4172 case unsupported:
4173 err_msg = _("unsupported");
4174 break;
4175 }
4176 as_bad (_("%s for `%s'"), err_msg,
891edac4 4177 current_templates->start->name);
fa99fab2 4178 return NULL;
29b0f896 4179 }
252b5132 4180
29b0f896
AM		 4181 if (!quiet_warnings)
4182 {
4183 if (!intel_syntax
40fb9820
L		 4184 && (i.types[0].bitfield.jumpabsolute
4185 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 4186 {
4187 as_warn (_("indirect %s without `*'"), t->name);
4188 }
4189
40fb9820
L		 4190 if (t->opcode_modifier.isprefix
4191 && t->opcode_modifier.ignoresize)
29b0f896
AM		 4192 {
4193 /* Warn them that a data or address size prefix doesn't
4194 affect assembly of the next line of code. */
4195 as_warn (_("stand-alone `%s' prefix"), t->name);
4196 }
4197 }
4198
4199 /* Copy the template we found. */
4200 i.tm = *t;
539e75ad
L		 4201
4202 if (addr_prefix_disp != -1)
4203 i.tm.operand_types[addr_prefix_disp]
4204 = operand_types[addr_prefix_disp];
4205
29b0f896
AM		 4206 if (found_reverse_match)
4207 {
4208 /* If we found a reverse match we must alter the opcode
4209 direction bit. found_reverse_match holds bits to change
4210 (different for int & float insns). */
4211
4212 i.tm.base_opcode ^= found_reverse_match;
4213
539e75ad
L		 4214 i.tm.operand_types[0] = operand_types[1];
4215 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 4216 }
4217
fa99fab2 4218 return t;
29b0f896
AM		 4219}
4220
4221static int
e3bb37b5 4222check_string (void)
29b0f896 4223{
40fb9820
L		 4224 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
4225 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 4226 {
4227 if (i.seg[0] != NULL && i.seg[0] != &es)
4228 {
a87af027 4229 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 4230 i.tm.name,
a87af027
JB		 4231 mem_op + 1,
4232 register_prefix);
29b0f896
AM		 4233 return 0;
4234 }
4235 /* There's only ever one segment override allowed per instruction.
4236 This instruction possibly has a legal segment override on the
4237 second operand, so copy the segment to where non-string
4238 instructions store it, allowing common code. */
4239 i.seg[0] = i.seg[1];
4240 }
40fb9820 4241 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 4242 {
4243 if (i.seg[1] != NULL && i.seg[1] != &es)
4244 {
a87af027 4245 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 4246 i.tm.name,
a87af027
JB		 4247 mem_op + 2,
4248 register_prefix);
29b0f896
AM		 4249 return 0;
4250 }
4251 }
4252 return 1;
4253}
4254
4255static int
543613e9 4256process_suffix (void)
29b0f896
AM		 4257{
4258 /* If matched instruction specifies an explicit instruction mnemonic
4259 suffix, use it. */
40fb9820
L		 4260 if (i.tm.opcode_modifier.size16)
4261 i.suffix = WORD_MNEM_SUFFIX;
4262 else if (i.tm.opcode_modifier.size32)
4263 i.suffix = LONG_MNEM_SUFFIX;
4264 else if (i.tm.opcode_modifier.size64)
4265 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 4266 else if (i.reg_operands)
4267 {
4268 /* If there's no instruction mnemonic suffix we try to invent one
4269 based on register operands. */
4270 if (!i.suffix)
4271 {
4272 /* We take i.suffix from the last register operand specified,
4273 Destination register type is more significant than source
381d071f
L		 4274 register type. crc32 in SSE4.2 prefers source register
4275 type. */
4276 if (i.tm.base_opcode == 0xf20f38f1)
4277 {
40fb9820
L		 4278 if (i.types[0].bitfield.reg16)
4279 i.suffix = WORD_MNEM_SUFFIX;
4280 else if (i.types[0].bitfield.reg32)
4281 i.suffix = LONG_MNEM_SUFFIX;
4282 else if (i.types[0].bitfield.reg64)
4283 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 4284 }
9344ff29 4285 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 4286 {
40fb9820 4287 if (i.types[0].bitfield.reg8)
20592a94
L		 4288 i.suffix = BYTE_MNEM_SUFFIX;
4289 }
381d071f
L		 4290
4291 if (!i.suffix)
4292 {
4293 int op;
4294
20592a94
L		 4295 if (i.tm.base_opcode == 0xf20f38f1
4296 || i.tm.base_opcode == 0xf20f38f0)
4297 {
4298 /* We have to know the operand size for crc32. */
4299 as_bad (_("ambiguous memory operand size for `%s`"),
4300 i.tm.name);
4301 return 0;
4302 }
4303
381d071f 4304 for (op = i.operands; --op >= 0;)
40fb9820 4305 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 4306 {
40fb9820
L		 4307 if (i.types[op].bitfield.reg8)
4308 {
4309 i.suffix = BYTE_MNEM_SUFFIX;
4310 break;
4311 }
4312 else if (i.types[op].bitfield.reg16)
4313 {
4314 i.suffix = WORD_MNEM_SUFFIX;
4315 break;
4316 }
4317 else if (i.types[op].bitfield.reg32)
4318 {
4319 i.suffix = LONG_MNEM_SUFFIX;
4320 break;
4321 }
4322 else if (i.types[op].bitfield.reg64)
4323 {
4324 i.suffix = QWORD_MNEM_SUFFIX;
4325 break;
4326 }
381d071f
L		 4327 }
4328 }
29b0f896
AM		 4329 }
4330 else if (i.suffix == BYTE_MNEM_SUFFIX)
4331 {
2eb952a4
L		 4332 if (intel_syntax
4333 && i.tm.opcode_modifier.ignoresize
4334 && i.tm.opcode_modifier.no_bsuf)
4335 i.suffix = 0;
4336 else if (!check_byte_reg ())
29b0f896
AM		 4337 return 0;
4338 }
4339 else if (i.suffix == LONG_MNEM_SUFFIX)
4340 {
2eb952a4
L		 4341 if (intel_syntax
4342 && i.tm.opcode_modifier.ignoresize
4343 && i.tm.opcode_modifier.no_lsuf)
4344 i.suffix = 0;
4345 else if (!check_long_reg ())
29b0f896
AM		 4346 return 0;
4347 }
4348 else if (i.suffix == QWORD_MNEM_SUFFIX)
4349 {
955e1e6a
L		 4350 if (intel_syntax
4351 && i.tm.opcode_modifier.ignoresize
4352 && i.tm.opcode_modifier.no_qsuf)
4353 i.suffix = 0;
4354 else if (!check_qword_reg ())
29b0f896
AM		 4355 return 0;
4356 }
4357 else if (i.suffix == WORD_MNEM_SUFFIX)
4358 {
2eb952a4
L		 4359 if (intel_syntax
4360 && i.tm.opcode_modifier.ignoresize
4361 && i.tm.opcode_modifier.no_wsuf)
4362 i.suffix = 0;
4363 else if (!check_word_reg ())
29b0f896
AM		 4364 return 0;
4365 }
c0f3af97
L		 4366 else if (i.suffix == XMMWORD_MNEM_SUFFIX
4367 || i.suffix == YMMWORD_MNEM_SUFFIX)
582d5edd 4368 {
c0f3af97 4369 /* Skip if the instruction has x/y suffix. match_template
582d5edd
L		 4370 should check if it is a valid suffix. */
4371 }
40fb9820 4372 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 4373 /* Do nothing if the instruction is going to ignore the prefix. */
4374 ;
4375 else
4376 abort ();
4377 }
40fb9820 4378 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 4379 && !i.suffix
4380 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 4381 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 4382 {
4383 i.suffix = stackop_size;
4384 }
9306ca4a
JB		 4385 else if (intel_syntax
4386 && !i.suffix
40fb9820
L		 4387 && (i.tm.operand_types[0].bitfield.jumpabsolute
4388 || i.tm.opcode_modifier.jumpbyte
4389 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 4390 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
4391 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 4392 {
4393 switch (flag_code)
4394 {
4395 case CODE_64BIT:
40fb9820 4396 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 4397 {
4398 i.suffix = QWORD_MNEM_SUFFIX;
4399 break;
4400 }
4401 case CODE_32BIT:
40fb9820 4402 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 4403 i.suffix = LONG_MNEM_SUFFIX;
4404 break;
4405 case CODE_16BIT:
40fb9820 4406 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 4407 i.suffix = WORD_MNEM_SUFFIX;
4408 break;
4409 }
4410 }
252b5132 4411
9306ca4a 4412 if (!i.suffix)
29b0f896 4413 {
9306ca4a
JB		 4414 if (!intel_syntax)
4415 {
40fb9820 4416 if (i.tm.opcode_modifier.w)
9306ca4a 4417 {
4eed87de
AM		 4418 as_bad (_("no instruction mnemonic suffix given and "
4419 "no register operands; can't size instruction"));
9306ca4a
JB		 4420 return 0;
4421 }
4422 }
4423 else
4424 {
40fb9820 4425 unsigned int suffixes;
7ab9ffdd 4426
40fb9820
L		 4427 suffixes = !i.tm.opcode_modifier.no_bsuf;
4428 if (!i.tm.opcode_modifier.no_wsuf)
4429 suffixes |= 1 << 1;
4430 if (!i.tm.opcode_modifier.no_lsuf)
4431 suffixes |= 1 << 2;
fc4adea1 4432 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 4433 suffixes |= 1 << 3;
4434 if (!i.tm.opcode_modifier.no_ssuf)
4435 suffixes |= 1 << 4;
4436 if (!i.tm.opcode_modifier.no_qsuf)
4437 suffixes |= 1 << 5;
4438
4439 /* There are more than suffix matches. */
4440 if (i.tm.opcode_modifier.w
9306ca4a 4441 || ((suffixes & (suffixes - 1))
40fb9820
L		 4442 && !i.tm.opcode_modifier.defaultsize
4443 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 4444 {
4445 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4446 return 0;
4447 }
4448 }
29b0f896 4449 }
252b5132 4450
9306ca4a
JB		 4451 /* Change the opcode based on the operand size given by i.suffix;
4452 We don't need to change things for byte insns. */
4453
582d5edd
L		 4454 if (i.suffix
4455 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97
L		 4456 && i.suffix != XMMWORD_MNEM_SUFFIX
4457 && i.suffix != YMMWORD_MNEM_SUFFIX)
29b0f896
AM		 4458 {
4459 /* It's not a byte, select word/dword operation. */
40fb9820 4460 if (i.tm.opcode_modifier.w)
29b0f896 4461 {
40fb9820 4462 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 4463 i.tm.base_opcode |= 8;
4464 else
4465 i.tm.base_opcode |= 1;
4466 }
0f3f3d8b 4467
29b0f896
AM		 4468 /* Now select between word & dword operations via the operand
4469 size prefix, except for instructions that will ignore this
4470 prefix anyway. */
ca61edf2 4471 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 4472 {
ca61edf2
L		 4473 /* The address size override prefix changes the size of the
4474 first operand. */
40fb9820
L		 4475 if ((flag_code == CODE_32BIT
4476 && i.op->regs[0].reg_type.bitfield.reg16)
4477 || (flag_code != CODE_32BIT
4478 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 4479 if (!add_prefix (ADDR_PREFIX_OPCODE))
4480 return 0;
4481 }
4482 else if (i.suffix != QWORD_MNEM_SUFFIX
4483 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 4484 && !i.tm.opcode_modifier.ignoresize
4485 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 4486 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
4487 || (flag_code == CODE_64BIT
40fb9820 4488 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 4489 {
4490 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 4491
40fb9820 4492 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 4493 prefix = ADDR_PREFIX_OPCODE;
252b5132 4494
29b0f896
AM		 4495 if (!add_prefix (prefix))
4496 return 0;
24eab124 4497 }
252b5132 4498
29b0f896
AM		 4499 /* Set mode64 for an operand. */
4500 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 4501 && flag_code == CODE_64BIT
40fb9820 4502 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 4503 {
4504 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 4505 need rex64. cmpxchg8b is also a special case. */
4506 if (! (i.operands == 2
4507 && i.tm.base_opcode == 0x90
4508 && i.tm.extension_opcode == None
0dfbf9d7
L		 4509 && operand_type_equal (&i.types [0], &acc64)
4510 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 4511 && ! (i.operands == 1
4512 && i.tm.base_opcode == 0xfc7
4513 && i.tm.extension_opcode == 1
40fb9820
L		 4514 && !operand_type_check (i.types [0], reg)
4515 && operand_type_check (i.types [0], anymem)))
f6bee062 4516 i.rex |= REX_W;
46e883c5 4517 }
3e73aa7c 4518
29b0f896
AM		 4519 /* Size floating point instruction. */
4520 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 4521 if (i.tm.opcode_modifier.floatmf)
543613e9 4522 i.tm.base_opcode ^= 4;
29b0f896 4523 }
7ecd2f8b 4524
29b0f896
AM		 4525 return 1;
4526}
3e73aa7c 4527
29b0f896 4528static int
543613e9 4529check_byte_reg (void)
29b0f896
AM		 4530{
4531 int op;
543613e9 4532
29b0f896
AM		 4533 for (op = i.operands; --op >= 0;)
4534 {
4535 /* If this is an eight bit register, it's OK. If it's the 16 or
4536 32 bit version of an eight bit register, we will just use the
4537 low portion, and that's OK too. */
40fb9820 4538 if (i.types[op].bitfield.reg8)
29b0f896
AM		 4539 continue;
4540
9344ff29
L		 4541 /* crc32 doesn't generate this warning. */
4542 if (i.tm.base_opcode == 0xf20f38f0)
4543 continue;
4544
40fb9820
L		 4545 if ((i.types[op].bitfield.reg16
4546 || i.types[op].bitfield.reg32
4547 || i.types[op].bitfield.reg64)
4548 && i.op[op].regs->reg_num < 4)
29b0f896
AM		 4549 {
4550 /* Prohibit these changes in the 64bit mode, since the
4551 lowering is more complicated. */
4552 if (flag_code == CODE_64BIT
40fb9820 4553 && !i.tm.operand_types[op].bitfield.inoutportreg)
29b0f896 4554 {
2ca3ace5
L		 4555 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4556 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4557 i.suffix);
4558 return 0;
4559 }
4560#if REGISTER_WARNINGS
4561 if (!quiet_warnings
40fb9820 4562 && !i.tm.operand_types[op].bitfield.inoutportreg)
a540244d
L		 4563 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4564 register_prefix,
40fb9820 4565 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 4566 ? REGNAM_AL - REGNAM_AX
4567 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 4568 register_prefix,
29b0f896
AM		 4569 i.op[op].regs->reg_name,
4570 i.suffix);
4571#endif
4572 continue;
4573 }
4574 /* Any other register is bad. */
40fb9820
L		 4575 if (i.types[op].bitfield.reg16
4576 || i.types[op].bitfield.reg32
4577 || i.types[op].bitfield.reg64
4578 || i.types[op].bitfield.regmmx
4579 || i.types[op].bitfield.regxmm
c0f3af97 4580 || i.types[op].bitfield.regymm
40fb9820
L		 4581 || i.types[op].bitfield.sreg2
4582 || i.types[op].bitfield.sreg3
4583 || i.types[op].bitfield.control
4584 || i.types[op].bitfield.debug
4585 || i.types[op].bitfield.test
4586 || i.types[op].bitfield.floatreg
4587 || i.types[op].bitfield.floatacc)
29b0f896 4588 {
a540244d
L		 4589 as_bad (_("`%s%s' not allowed with `%s%c'"),
4590 register_prefix,
29b0f896
AM		 4591 i.op[op].regs->reg_name,
4592 i.tm.name,
4593 i.suffix);
4594 return 0;
4595 }
4596 }
4597 return 1;
4598}
4599
4600static int
e3bb37b5 4601check_long_reg (void)
29b0f896
AM		 4602{
4603 int op;
4604
4605 for (op = i.operands; --op >= 0;)
4606 /* Reject eight bit registers, except where the template requires
4607 them. (eg. movzb) */
40fb9820
L		 4608 if (i.types[op].bitfield.reg8
4609 && (i.tm.operand_types[op].bitfield.reg16
4610 || i.tm.operand_types[op].bitfield.reg32
4611 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4612 {
a540244d
L		 4613 as_bad (_("`%s%s' not allowed with `%s%c'"),
4614 register_prefix,
29b0f896
AM		 4615 i.op[op].regs->reg_name,
4616 i.tm.name,
4617 i.suffix);
4618 return 0;
4619 }
4620 /* Warn if the e prefix on a general reg is missing. */
4621 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4622 && i.types[op].bitfield.reg16
4623 && (i.tm.operand_types[op].bitfield.reg32
4624 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4625 {
4626 /* Prohibit these changes in the 64bit mode, since the
4627 lowering is more complicated. */
4628 if (flag_code == CODE_64BIT)
252b5132 4629 {
2ca3ace5
L		 4630 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4631 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4632 i.suffix);
4633 return 0;
252b5132 4634 }
29b0f896
AM		 4635#if REGISTER_WARNINGS
4636 else
a540244d
L		 4637 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4638 register_prefix,
29b0f896 4639 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 4640 register_prefix,
29b0f896
AM		 4641 i.op[op].regs->reg_name,
4642 i.suffix);
4643#endif
252b5132 4644 }
29b0f896 4645 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 4646 else if (i.types[op].bitfield.reg64
4647 && (i.tm.operand_types[op].bitfield.reg32
4648 || i.tm.operand_types[op].bitfield.acc))
252b5132 4649 {
34828aad 4650 if (intel_syntax
ca61edf2 4651 && i.tm.opcode_modifier.toqword
40fb9820 4652 && !i.types[0].bitfield.regxmm)
34828aad 4653 {
ca61edf2 4654 /* Convert to QWORD. We want REX byte. */
34828aad
L		 4655 i.suffix = QWORD_MNEM_SUFFIX;
4656 }
4657 else
4658 {
4659 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4660 register_prefix, i.op[op].regs->reg_name,
4661 i.suffix);
4662 return 0;
4663 }
29b0f896
AM		 4664 }
4665 return 1;
4666}
252b5132 4667
29b0f896 4668static int
e3bb37b5 4669check_qword_reg (void)
29b0f896
AM		 4670{
4671 int op;
252b5132 4672
29b0f896
AM		 4673 for (op = i.operands; --op >= 0; )
4674 /* Reject eight bit registers, except where the template requires
4675 them. (eg. movzb) */
40fb9820
L		 4676 if (i.types[op].bitfield.reg8
4677 && (i.tm.operand_types[op].bitfield.reg16
4678 || i.tm.operand_types[op].bitfield.reg32
4679 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4680 {
a540244d
L		 4681 as_bad (_("`%s%s' not allowed with `%s%c'"),
4682 register_prefix,
29b0f896
AM		 4683 i.op[op].regs->reg_name,
4684 i.tm.name,
4685 i.suffix);
4686 return 0;
4687 }
4688 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 4689 else if ((i.types[op].bitfield.reg16
4690 || i.types[op].bitfield.reg32)
4691 && (i.tm.operand_types[op].bitfield.reg32
4692 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4693 {
4694 /* Prohibit these changes in the 64bit mode, since the
4695 lowering is more complicated. */
34828aad 4696 if (intel_syntax
ca61edf2 4697 && i.tm.opcode_modifier.todword
40fb9820 4698 && !i.types[0].bitfield.regxmm)
34828aad 4699 {
ca61edf2 4700 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 4701 i.suffix = LONG_MNEM_SUFFIX;
4702 }
4703 else
4704 {
4705 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4706 register_prefix, i.op[op].regs->reg_name,
4707 i.suffix);
4708 return 0;
4709 }
252b5132 4710 }
29b0f896
AM		 4711 return 1;
4712}
252b5132 4713
29b0f896 4714static int
e3bb37b5 4715check_word_reg (void)
29b0f896
AM		 4716{
4717 int op;
4718 for (op = i.operands; --op >= 0;)
4719 /* Reject eight bit registers, except where the template requires
4720 them. (eg. movzb) */
40fb9820
L		 4721 if (i.types[op].bitfield.reg8
4722 && (i.tm.operand_types[op].bitfield.reg16
4723 || i.tm.operand_types[op].bitfield.reg32
4724 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4725 {
a540244d
L		 4726 as_bad (_("`%s%s' not allowed with `%s%c'"),
4727 register_prefix,
29b0f896
AM		 4728 i.op[op].regs->reg_name,
4729 i.tm.name,
4730 i.suffix);
4731 return 0;
4732 }
4733 /* Warn if the e prefix on a general reg is present. */
4734 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4735 && i.types[op].bitfield.reg32
4736 && (i.tm.operand_types[op].bitfield.reg16
4737 || i.tm.operand_types[op].bitfield.acc))
252b5132 4738 {
29b0f896
AM		 4739 /* Prohibit these changes in the 64bit mode, since the
4740 lowering is more complicated. */
4741 if (flag_code == CODE_64BIT)
252b5132 4742 {
2ca3ace5
L		 4743 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4744 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4745 i.suffix);
4746 return 0;
252b5132 4747 }
29b0f896
AM		 4748 else
4749#if REGISTER_WARNINGS
a540244d
L		 4750 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4751 register_prefix,
29b0f896 4752 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 4753 register_prefix,
29b0f896
AM		 4754 i.op[op].regs->reg_name,
4755 i.suffix);
4756#endif
4757 }
4758 return 1;
4759}
252b5132 4760
29b0f896 4761static int
40fb9820 4762update_imm (unsigned int j)
29b0f896 4763{
bc0844ae 4764 i386_operand_type overlap = i.types[j];
40fb9820
L		 4765 if ((overlap.bitfield.imm8
4766 || overlap.bitfield.imm8s
4767 || overlap.bitfield.imm16
4768 || overlap.bitfield.imm32
4769 || overlap.bitfield.imm32s
4770 || overlap.bitfield.imm64)
0dfbf9d7
L		 4771 && !operand_type_equal (&overlap, &imm8)
4772 && !operand_type_equal (&overlap, &imm8s)
4773 && !operand_type_equal (&overlap, &imm16)
4774 && !operand_type_equal (&overlap, &imm32)
4775 && !operand_type_equal (&overlap, &imm32s)
4776 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 4777 {
4778 if (i.suffix)
4779 {
40fb9820
L		 4780 i386_operand_type temp;
4781
0dfbf9d7 4782 operand_type_set (&temp, 0);
7ab9ffdd 4783 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 4784 {
4785 temp.bitfield.imm8 = overlap.bitfield.imm8;
4786 temp.bitfield.imm8s = overlap.bitfield.imm8s;
4787 }
4788 else if (i.suffix == WORD_MNEM_SUFFIX)
4789 temp.bitfield.imm16 = overlap.bitfield.imm16;
4790 else if (i.suffix == QWORD_MNEM_SUFFIX)
4791 {
4792 temp.bitfield.imm64 = overlap.bitfield.imm64;
4793 temp.bitfield.imm32s = overlap.bitfield.imm32s;
4794 }
4795 else
4796 temp.bitfield.imm32 = overlap.bitfield.imm32;
4797 overlap = temp;
29b0f896 4798 }
0dfbf9d7
L		 4799 else if (operand_type_equal (&overlap, &imm16_32_32s)
4800 || operand_type_equal (&overlap, &imm16_32)
4801 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 4802 {
40fb9820 4803 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 4804 overlap = imm16;
40fb9820 4805 else
65da13b5 4806 overlap = imm32s;
29b0f896 4807 }
0dfbf9d7
L		 4808 if (!operand_type_equal (&overlap, &imm8)
4809 && !operand_type_equal (&overlap, &imm8s)
4810 && !operand_type_equal (&overlap, &imm16)
4811 && !operand_type_equal (&overlap, &imm32)
4812 && !operand_type_equal (&overlap, &imm32s)
4813 && !operand_type_equal (&overlap, &imm64))
29b0f896 4814 {
4eed87de
AM		 4815 as_bad (_("no instruction mnemonic suffix given; "
4816 "can't determine immediate size"));
29b0f896
AM		 4817 return 0;
4818 }
4819 }
40fb9820 4820 i.types[j] = overlap;
29b0f896 4821
40fb9820
L		 4822 return 1;
4823}
4824
4825static int
4826finalize_imm (void)
4827{
bc0844ae 4828 unsigned int j, n;
29b0f896 4829
bc0844ae
L		 4830 /* Update the first 2 immediate operands. */
4831 n = i.operands > 2 ? 2 : i.operands;
4832 if (n)
4833 {
4834 for (j = 0; j < n; j++)
4835 if (update_imm (j) == 0)
4836 return 0;
40fb9820 4837
bc0844ae
L		 4838 /* The 3rd operand can't be immediate operand. */
4839 gas_assert (operand_type_check (i.types[2], imm) == 0);
4840 }
29b0f896
AM		 4841
4842 return 1;
4843}
4844
c0f3af97
L		 4845static int
4846bad_implicit_operand (int xmm)
4847{
91d6fa6a
NC		 4848 const char *ireg = xmm ? "xmm0" : "ymm0";
4849
c0f3af97
L		 4850 if (intel_syntax)
4851 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 4852 i.tm.name, register_prefix, ireg);
c0f3af97
L		 4853 else
4854 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 4855 i.tm.name, register_prefix, ireg);
c0f3af97
L		 4856 return 0;
4857}
4858
29b0f896 4859static int
e3bb37b5 4860process_operands (void)
29b0f896
AM		 4861{
4862 /* Default segment register this instruction will use for memory
4863 accesses. 0 means unknown. This is only for optimizing out
4864 unnecessary segment overrides. */
4865 const seg_entry *default_seg = 0;
4866
2426c15f 4867 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 4868 {
91d6fa6a
NC		 4869 unsigned int dupl = i.operands;
4870 unsigned int dest = dupl - 1;
9fcfb3d7
L		 4871 unsigned int j;
4872
c0f3af97 4873 /* The destination must be an xmm register. */
9c2799c2 4874 gas_assert (i.reg_operands
91d6fa6a 4875 && MAX_OPERANDS > dupl
7ab9ffdd 4876 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 4877
4878 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 4879 {
c0f3af97 4880 /* The first operand is implicit and must be xmm0. */
9c2799c2 4881 gas_assert (operand_type_equal (&i.types[0], &regxmm));
c0f3af97
L		 4882 if (i.op[0].regs->reg_num != 0)
4883 return bad_implicit_operand (1);
4884
8cd7925b 4885 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 4886 {
4887 /* Keep xmm0 for instructions with VEX prefix and 3
4888 sources. */
4889 goto duplicate;
4890 }
e2ec9d29 4891 else
c0f3af97
L		 4892 {
4893 /* We remove the first xmm0 and keep the number of
4894 operands unchanged, which in fact duplicates the
4895 destination. */
4896 for (j = 1; j < i.operands; j++)
4897 {
4898 i.op[j - 1] = i.op[j];
4899 i.types[j - 1] = i.types[j];
4900 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
4901 }
4902 }
4903 }
4904 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 4905 {
91d6fa6a 4906 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 4907 && (i.tm.opcode_modifier.vexsources
4908 == VEX3SOURCES));
c0f3af97
L		 4909
4910 /* Add the implicit xmm0 for instructions with VEX prefix
4911 and 3 sources. */
4912 for (j = i.operands; j > 0; j--)
4913 {
4914 i.op[j] = i.op[j - 1];
4915 i.types[j] = i.types[j - 1];
4916 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
4917 }
4918 i.op[0].regs
4919 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 4920 i.types[0] = regxmm;
c0f3af97
L		 4921 i.tm.operand_types[0] = regxmm;
4922
4923 i.operands += 2;
4924 i.reg_operands += 2;
4925 i.tm.operands += 2;
4926
91d6fa6a 4927 dupl++;
c0f3af97 4928 dest++;
91d6fa6a
NC		 4929 i.op[dupl] = i.op[dest];
4930 i.types[dupl] = i.types[dest];
4931 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 4932 }
c0f3af97
L		 4933 else
4934 {
4935duplicate:
4936 i.operands++;
4937 i.reg_operands++;
4938 i.tm.operands++;
4939
91d6fa6a
NC		 4940 i.op[dupl] = i.op[dest];
4941 i.types[dupl] = i.types[dest];
4942 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 4943 }
4944
4945 if (i.tm.opcode_modifier.immext)
4946 process_immext ();
4947 }
4948 else if (i.tm.opcode_modifier.firstxmm0)
4949 {
4950 unsigned int j;
4951
4952 /* The first operand is implicit and must be xmm0/ymm0. */
9c2799c2 4953 gas_assert (i.reg_operands
7ab9ffdd
L		 4954 && (operand_type_equal (&i.types[0], &regxmm)
4955 || operand_type_equal (&i.types[0], &regymm)));
c0f3af97
L		 4956 if (i.op[0].regs->reg_num != 0)
4957 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 4958
4959 for (j = 1; j < i.operands; j++)
4960 {
4961 i.op[j - 1] = i.op[j];
4962 i.types[j - 1] = i.types[j];
4963
4964 /* We need to adjust fields in i.tm since they are used by
4965 build_modrm_byte. */
4966 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
4967 }
4968
e2ec9d29
L		 4969 i.operands--;
4970 i.reg_operands--;
e2ec9d29
L		 4971 i.tm.operands--;
4972 }
4973 else if (i.tm.opcode_modifier.regkludge)
4974 {
4975 /* The imul $imm, %reg instruction is converted into
4976 imul $imm, %reg, %reg, and the clr %reg instruction
4977 is converted into xor %reg, %reg. */
4978
4979 unsigned int first_reg_op;
4980
4981 if (operand_type_check (i.types[0], reg))
4982 first_reg_op = 0;
4983 else
4984 first_reg_op = 1;
4985 /* Pretend we saw the extra register operand. */
9c2799c2 4986 gas_assert (i.reg_operands == 1
7ab9ffdd 4987 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 4988 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
4989 i.types[first_reg_op + 1] = i.types[first_reg_op];
4990 i.operands++;
4991 i.reg_operands++;
29b0f896
AM		 4992 }
4993
40fb9820 4994 if (i.tm.opcode_modifier.shortform)
29b0f896 4995 {
40fb9820
L		 4996 if (i.types[0].bitfield.sreg2
4997 || i.types[0].bitfield.sreg3)
29b0f896 4998 {
4eed87de
AM		 4999 if (i.tm.base_opcode == POP_SEG_SHORT
5000 && i.op[0].regs->reg_num == 1)
29b0f896 5001 {
a87af027 5002 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 5003 return 0;
29b0f896 5004 }
4eed87de
AM		 5005 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5006 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 5007 i.rex |= REX_B;
4eed87de
AM		 5008 }
5009 else
5010 {
7ab9ffdd 5011 /* The register or float register operand is in operand
85f10a01 5012 0 or 1. */
40fb9820 5013 unsigned int op;
7ab9ffdd
L		 5014
5015 if (i.types[0].bitfield.floatreg
5016 || operand_type_check (i.types[0], reg))
5017 op = 0;
5018 else
5019 op = 1;
4eed87de
AM		 5020 /* Register goes in low 3 bits of opcode. */
5021 i.tm.base_opcode |= i.op[op].regs->reg_num;
5022 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 5023 i.rex |= REX_B;
40fb9820 5024 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 5025 {
4eed87de
AM		 5026 /* Warn about some common errors, but press on regardless.
5027 The first case can be generated by gcc (<= 2.8.1). */
5028 if (i.operands == 2)
5029 {
5030 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 5031 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 5032 register_prefix, i.op[!intel_syntax].regs->reg_name,
5033 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 5034 }
5035 else
5036 {
5037 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 5038 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5039 register_prefix, i.op[0].regs->reg_name);
4eed87de 5040 }
29b0f896
AM		 5041 }
5042 }
5043 }
40fb9820 5044 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5045 {
5046 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 5047 must be put into the modrm byte). Now, we make the modrm and
5048 index base bytes based on all the info we've collected. */
29b0f896
AM		 5049
5050 default_seg = build_modrm_byte ();
5051 }
8a2ed489 5052 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 5053 {
5054 default_seg = &ds;
5055 }
40fb9820 5056 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 5057 {
5058 /* For the string instructions that allow a segment override
5059 on one of their operands, the default segment is ds. */
5060 default_seg = &ds;
5061 }
5062
75178d9d
L		 5063 if (i.tm.base_opcode == 0x8d /* lea */
5064 && i.seg[0]
5065 && !quiet_warnings)
30123838 5066 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 5067
5068 /* If a segment was explicitly specified, and the specified segment
5069 is not the default, use an opcode prefix to select it. If we
5070 never figured out what the default segment is, then default_seg
5071 will be zero at this point, and the specified segment prefix will
5072 always be used. */
29b0f896
AM		 5073 if ((i.seg[0]) && (i.seg[0] != default_seg))
5074 {
5075 if (!add_prefix (i.seg[0]->seg_prefix))
5076 return 0;
5077 }
5078 return 1;
5079}
5080
5081static const seg_entry *
e3bb37b5 5082build_modrm_byte (void)
29b0f896
AM		 5083{
5084 const seg_entry *default_seg = 0;
c0f3af97 5085 unsigned int source, dest;
8cd7925b 5086 int vex_3_sources;
c0f3af97
L		 5087
5088 /* The first operand of instructions with VEX prefix and 3 sources
5089 must be VEX_Imm4. */
8cd7925b 5090 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 5091 if (vex_3_sources)
5092 {
91d6fa6a 5093 unsigned int nds, reg_slot;
4c2c6516 5094 expressionS *exp;
c0f3af97 5095
922d8de8 5096 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 5097 && i.tm.opcode_modifier.immext)
5098 {
5099 dest = i.operands - 2;
5100 gas_assert (dest == 3);
5101 }
922d8de8 5102 else
a683cc34 5103 dest = i.operands - 1;
c0f3af97 5104 nds = dest - 1;
922d8de8 5105
a683cc34
SP		 5106 /* There are 2 kinds of instructions:
5107 1. 5 operands: 4 register operands or 3 register operands
5108 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5109 VexW0 or VexW1. The destination must be either XMM or YMM
5110 register.
5111 2. 4 operands: 4 register operands or 3 register operands
5112 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 5113 gas_assert ((i.reg_operands == 4
a683cc34
SP		 5114 || (i.reg_operands == 3 && i.mem_operands == 1))
5115 && i.tm.opcode_modifier.vexvvvv == VEXXDS
5116 && (i.tm.opcode_modifier.veximmext
5117 || (i.imm_operands == 1
5118 && i.types[0].bitfield.vec_imm4
5119 && (i.tm.opcode_modifier.vexw == VEXW0
5120 || i.tm.opcode_modifier.vexw == VEXW1)
5121 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
5122 || operand_type_equal (&i.tm.operand_types[dest], &regymm)))));
5123
5124 if (i.imm_operands == 0)
5125 {
5126 /* When there is no immediate operand, generate an 8bit
5127 immediate operand to encode the first operand. */
5128 exp = &im_expressions[i.imm_operands++];
5129 i.op[i.operands].imms = exp;
5130 i.types[i.operands] = imm8;
5131 i.operands++;
5132 /* If VexW1 is set, the first operand is the source and
5133 the second operand is encoded in the immediate operand. */
5134 if (i.tm.opcode_modifier.vexw == VEXW1)
5135 {
5136 source = 0;
5137 reg_slot = 1;
5138 }
5139 else
5140 {
5141 source = 1;
5142 reg_slot = 0;
5143 }
5144
5145 /* FMA swaps REG and NDS. */
5146 if (i.tm.cpu_flags.bitfield.cpufma)
5147 {
5148 unsigned int tmp;
5149 tmp = reg_slot;
5150 reg_slot = nds;
5151 nds = tmp;
5152 }
5153
24981e7b
L		 5154 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5155 &regxmm)
a683cc34
SP		 5156 || operand_type_equal (&i.tm.operand_types[reg_slot],
5157 &regymm));
5158 exp->X_op = O_constant;
5159 exp->X_add_number
5160 = ((i.op[reg_slot].regs->reg_num
24981e7b
L		 5161 + ((i.op[reg_slot].regs->reg_flags & RegRex) ? 8 : 0))
5162 << 4);
a683cc34 5163 }
922d8de8 5164 else
a683cc34
SP		 5165 {
5166 unsigned int imm_slot;
5167
5168 if (i.tm.opcode_modifier.vexw == VEXW0)
5169 {
5170 /* If VexW0 is set, the third operand is the source and
5171 the second operand is encoded in the immediate
5172 operand. */
5173 source = 2;
5174 reg_slot = 1;
5175 }
5176 else
5177 {
5178 /* VexW1 is set, the second operand is the source and
5179 the third operand is encoded in the immediate
5180 operand. */
5181 source = 1;
5182 reg_slot = 2;
5183 }
5184
5185 if (i.tm.opcode_modifier.immext)
5186 {
5187 /* When ImmExt is set, the immdiate byte is the last
5188 operand. */
5189 imm_slot = i.operands - 1;
5190 source--;
5191 reg_slot--;
5192 }
5193 else
5194 {
5195 imm_slot = 0;
5196
5197 /* Turn on Imm8 so that output_imm will generate it. */
5198 i.types[imm_slot].bitfield.imm8 = 1;
5199 }
5200
24981e7b
L		 5201 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5202 &regxmm)
5203 || operand_type_equal (&i.tm.operand_types[reg_slot],
5204 &regymm));
a683cc34
SP		 5205 i.op[imm_slot].imms->X_add_number
5206 |= ((i.op[reg_slot].regs->reg_num
24981e7b
L		 5207 + ((i.op[reg_slot].regs->reg_flags & RegRex) ? 8 : 0))
5208 << 4);
a683cc34
SP		 5209 }
5210
5211 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
5212 || operand_type_equal (&i.tm.operand_types[nds],
5213 &regymm));
dae39acc 5214 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 5215 }
5216 else
5217 source = dest = 0;
29b0f896
AM		 5218
5219 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 5220 implicit registers do not count. If there are 3 register
5221 operands, it must be a instruction with VexNDS. For a
5222 instruction with VexNDD, the destination register is encoded
5223 in VEX prefix. If there are 4 register operands, it must be
5224 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 5225 if (i.mem_operands == 0
5226 && ((i.reg_operands == 2
2426c15f 5227 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 5228 || (i.reg_operands == 3
2426c15f 5229 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 5230 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 5231 {
cab737b9
L		 5232 switch (i.operands)
5233 {
5234 case 2:
5235 source = 0;
5236 break;
5237 case 3:
c81128dc
L		 5238 /* When there are 3 operands, one of them may be immediate,
5239 which may be the first or the last operand. Otherwise,
c0f3af97
L		 5240 the first operand must be shift count register (cl) or it
5241 is an instruction with VexNDS. */
9c2799c2 5242 gas_assert (i.imm_operands == 1
7ab9ffdd 5243 || (i.imm_operands == 0
2426c15f 5244 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 5245 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 5246 if (operand_type_check (i.types[0], imm)
5247 || i.types[0].bitfield.shiftcount)
5248 source = 1;
5249 else
5250 source = 0;
cab737b9
L		 5251 break;
5252 case 4:
368d64cc
L		 5253 /* When there are 4 operands, the first two must be 8bit
5254 immediate operands. The source operand will be the 3rd
c0f3af97
L		 5255 one.
5256
5257 For instructions with VexNDS, if the first operand
5258 an imm8, the source operand is the 2nd one. If the last
5259 operand is imm8, the source operand is the first one. */
9c2799c2 5260 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 5261 && i.types[0].bitfield.imm8
5262 && i.types[1].bitfield.imm8)
2426c15f 5263 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 5264 && i.imm_operands == 1
5265 && (i.types[0].bitfield.imm8
5266 || i.types[i.operands - 1].bitfield.imm8)));
9f2670f2
L		 5267 if (i.imm_operands == 2)
5268 source = 2;
5269 else
c0f3af97
L		 5270 {
5271 if (i.types[0].bitfield.imm8)
5272 source = 1;
5273 else
5274 source = 0;
5275 }
c0f3af97
L		 5276 break;
5277 case 5:
cab737b9
L		 5278 break;
5279 default:
5280 abort ();
5281 }
5282
c0f3af97
L		 5283 if (!vex_3_sources)
5284 {
5285 dest = source + 1;
5286
2426c15f 5287 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97
L		 5288 {
5289 /* For instructions with VexNDS, the register-only
5290 source operand must be XMM or YMM register. It is
fa99fab2
L		 5291 encoded in VEX prefix. We need to clear RegMem bit
5292 before calling operand_type_equal. */
5293 i386_operand_type op = i.tm.operand_types[dest];
5294 op.bitfield.regmem = 0;
c0f3af97 5295 if ((dest + 1) >= i.operands
fa99fab2
L		 5296 || (!operand_type_equal (&op, &regxmm)
5297 && !operand_type_equal (&op, &regymm)))
c0f3af97
L		 5298 abort ();
5299 i.vex.register_specifier = i.op[dest].regs;
5300 dest++;
5301 }
5302 }
29b0f896
AM		 5303
5304 i.rm.mode = 3;
5305 /* One of the register operands will be encoded in the i.tm.reg
5306 field, the other in the combined i.tm.mode and i.tm.regmem
5307 fields. If no form of this instruction supports a memory
5308 destination operand, then we assume the source operand may
5309 sometimes be a memory operand and so we need to store the
5310 destination in the i.rm.reg field. */
40fb9820
L		 5311 if (!i.tm.operand_types[dest].bitfield.regmem
5312 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 5313 {
5314 i.rm.reg = i.op[dest].regs->reg_num;
5315 i.rm.regmem = i.op[source].regs->reg_num;
5316 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5317 i.rex |= REX_R;
29b0f896 5318 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5319 i.rex |= REX_B;
29b0f896
AM		 5320 }
5321 else
5322 {
5323 i.rm.reg = i.op[source].regs->reg_num;
5324 i.rm.regmem = i.op[dest].regs->reg_num;
5325 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5326 i.rex |= REX_B;
29b0f896 5327 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5328 i.rex |= REX_R;
29b0f896 5329 }
161a04f6 5330 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 5331 {
40fb9820
L		 5332 if (!i.types[0].bitfield.control
5333 && !i.types[1].bitfield.control)
c4a530c5 5334 abort ();
161a04f6 5335 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 5336 add_prefix (LOCK_PREFIX_OPCODE);
5337 }
29b0f896
AM		 5338 }
5339 else
5340 { /* If it's not 2 reg operands... */
c0f3af97
L		 5341 unsigned int mem;
5342
29b0f896
AM		 5343 if (i.mem_operands)
5344 {
5345 unsigned int fake_zero_displacement = 0;
99018f42 5346 unsigned int op;
4eed87de 5347
7ab9ffdd
L		 5348 for (op = 0; op < i.operands; op++)
5349 if (operand_type_check (i.types[op], anymem))
5350 break;
7ab9ffdd 5351 gas_assert (op < i.operands);
29b0f896
AM		 5352
5353 default_seg = &ds;
5354
5355 if (i.base_reg == 0)
5356 {
5357 i.rm.mode = 0;
5358 if (!i.disp_operands)
5359 fake_zero_displacement = 1;
5360 if (i.index_reg == 0)
5361 {
5362 /* Operand is just <disp> */
20f0a1fc 5363 if (flag_code == CODE_64BIT)
29b0f896
AM		 5364 {
5365 /* 64bit mode overwrites the 32bit absolute
5366 addressing by RIP relative addressing and
5367 absolute addressing is encoded by one of the
5368 redundant SIB forms. */
5369 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5370 i.sib.base = NO_BASE_REGISTER;
5371 i.sib.index = NO_INDEX_REGISTER;
fc225355 5372 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 5373 ? disp32s : disp32);
20f0a1fc 5374 }
fc225355
L		 5375 else if ((flag_code == CODE_16BIT)
5376 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 5377 {
5378 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 5379 i.types[op] = disp16;
20f0a1fc
NC		 5380 }
5381 else
5382 {
5383 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 5384 i.types[op] = disp32;
29b0f896
AM		 5385 }
5386 }
5387 else /* !i.base_reg && i.index_reg */
5388 {
db51cc60
L		 5389 if (i.index_reg->reg_num == RegEiz
5390 || i.index_reg->reg_num == RegRiz)
5391 i.sib.index = NO_INDEX_REGISTER;
5392 else
5393 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5394 i.sib.base = NO_BASE_REGISTER;
5395 i.sib.scale = i.log2_scale_factor;
5396 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 5397 i.types[op].bitfield.disp8 = 0;
5398 i.types[op].bitfield.disp16 = 0;
5399 i.types[op].bitfield.disp64 = 0;
29b0f896 5400 if (flag_code != CODE_64BIT)
40fb9820
L		 5401 {
5402 /* Must be 32 bit */
5403 i.types[op].bitfield.disp32 = 1;
5404 i.types[op].bitfield.disp32s = 0;
5405 }
29b0f896 5406 else
40fb9820
L		 5407 {
5408 i.types[op].bitfield.disp32 = 0;
5409 i.types[op].bitfield.disp32s = 1;
5410 }
29b0f896 5411 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5412 i.rex |= REX_X;
29b0f896
AM		 5413 }
5414 }
5415 /* RIP addressing for 64bit mode. */
9a04903e
JB		 5416 else if (i.base_reg->reg_num == RegRip ||
5417 i.base_reg->reg_num == RegEip)
29b0f896
AM		 5418 {
5419 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 5420 i.types[op].bitfield.disp8 = 0;
5421 i.types[op].bitfield.disp16 = 0;
5422 i.types[op].bitfield.disp32 = 0;
5423 i.types[op].bitfield.disp32s = 1;
5424 i.types[op].bitfield.disp64 = 0;
71903a11 5425 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 5426 if (! i.disp_operands)
5427 fake_zero_displacement = 1;
29b0f896 5428 }
40fb9820 5429 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896
AM		 5430 {
5431 switch (i.base_reg->reg_num)
5432 {
5433 case 3: /* (%bx) */
5434 if (i.index_reg == 0)
5435 i.rm.regmem = 7;
5436 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5437 i.rm.regmem = i.index_reg->reg_num - 6;
5438 break;
5439 case 5: /* (%bp) */
5440 default_seg = &ss;
5441 if (i.index_reg == 0)
5442 {
5443 i.rm.regmem = 6;
40fb9820 5444 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 5445 {
5446 /* fake (%bp) into 0(%bp) */
40fb9820 5447 i.types[op].bitfield.disp8 = 1;
252b5132 5448 fake_zero_displacement = 1;
29b0f896
AM		 5449 }
5450 }
5451 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5452 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
5453 break;
5454 default: /* (%si) -> 4 or (%di) -> 5 */
5455 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
5456 }
5457 i.rm.mode = mode_from_disp_size (i.types[op]);
5458 }
5459 else /* i.base_reg and 32/64 bit mode */
5460 {
5461 if (flag_code == CODE_64BIT
40fb9820
L		 5462 && operand_type_check (i.types[op], disp))
5463 {
5464 i386_operand_type temp;
0dfbf9d7 5465 operand_type_set (&temp, 0);
40fb9820
L		 5466 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
5467 i.types[op] = temp;
5468 if (i.prefix[ADDR_PREFIX] == 0)
5469 i.types[op].bitfield.disp32s = 1;
5470 else
5471 i.types[op].bitfield.disp32 = 1;
5472 }
20f0a1fc 5473
29b0f896
AM		 5474 i.rm.regmem = i.base_reg->reg_num;
5475 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 5476 i.rex |= REX_B;
29b0f896
AM		 5477 i.sib.base = i.base_reg->reg_num;
5478 /* x86-64 ignores REX prefix bit here to avoid decoder
5479 complications. */
5480 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
5481 {
5482 default_seg = &ss;
5483 if (i.disp_operands == 0)
5484 {
5485 fake_zero_displacement = 1;
40fb9820 5486 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 5487 }
5488 }
5489 else if (i.base_reg->reg_num == ESP_REG_NUM)
5490 {
5491 default_seg = &ss;
5492 }
5493 i.sib.scale = i.log2_scale_factor;
5494 if (i.index_reg == 0)
5495 {
5496 /* <disp>(%esp) becomes two byte modrm with no index
5497 register. We've already stored the code for esp
5498 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5499 Any base register besides %esp will not use the
5500 extra modrm byte. */
5501 i.sib.index = NO_INDEX_REGISTER;
29b0f896
AM		 5502 }
5503 else
5504 {
db51cc60
L		 5505 if (i.index_reg->reg_num == RegEiz
5506 || i.index_reg->reg_num == RegRiz)
5507 i.sib.index = NO_INDEX_REGISTER;
5508 else
5509 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5510 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5511 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5512 i.rex |= REX_X;
29b0f896 5513 }
67a4f2b7
AO		 5514
5515 if (i.disp_operands
5516 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
5517 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
5518 i.rm.mode = 0;
5519 else
5520 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 5521 }
252b5132 5522
29b0f896
AM		 5523 if (fake_zero_displacement)
5524 {
5525 /* Fakes a zero displacement assuming that i.types[op]
5526 holds the correct displacement size. */
5527 expressionS *exp;
5528
9c2799c2 5529 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 5530 exp = &disp_expressions[i.disp_operands++];
5531 i.op[op].disps = exp;
5532 exp->X_op = O_constant;
5533 exp->X_add_number = 0;
5534 exp->X_add_symbol = (symbolS *) 0;
5535 exp->X_op_symbol = (symbolS *) 0;
5536 }
c0f3af97
L		 5537
5538 mem = op;
29b0f896 5539 }
c0f3af97
L		 5540 else
5541 mem = ~0;
252b5132 5542
8c43a48b 5543 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 5544 {
5545 if (operand_type_check (i.types[0], imm))
5546 i.vex.register_specifier = NULL;
5547 else
5548 {
5549 /* VEX.vvvv encodes one of the sources when the first
5550 operand is not an immediate. */
1ef99a7b 5551 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 5552 i.vex.register_specifier = i.op[0].regs;
5553 else
5554 i.vex.register_specifier = i.op[1].regs;
5555 }
5556
5557 /* Destination is a XMM register encoded in the ModRM.reg
5558 and VEX.R bit. */
5559 i.rm.reg = i.op[2].regs->reg_num;
5560 if ((i.op[2].regs->reg_flags & RegRex) != 0)
5561 i.rex |= REX_R;
5562
5563 /* ModRM.rm and VEX.B encodes the other source. */
5564 if (!i.mem_operands)
5565 {
5566 i.rm.mode = 3;
5567
1ef99a7b 5568 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 5569 i.rm.regmem = i.op[1].regs->reg_num;
5570 else
5571 i.rm.regmem = i.op[0].regs->reg_num;
5572
5573 if ((i.op[1].regs->reg_flags & RegRex) != 0)
5574 i.rex |= REX_B;
5575 }
5576 }
2426c15f 5577 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 5578 {
5579 i.vex.register_specifier = i.op[2].regs;
5580 if (!i.mem_operands)
5581 {
5582 i.rm.mode = 3;
5583 i.rm.regmem = i.op[1].regs->reg_num;
5584 if ((i.op[1].regs->reg_flags & RegRex) != 0)
5585 i.rex |= REX_B;
5586 }
5587 }
29b0f896
AM		 5588 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5589 (if any) based on i.tm.extension_opcode. Again, we must be
5590 careful to make sure that segment/control/debug/test/MMX
5591 registers are coded into the i.rm.reg field. */
f88c9eb0 5592 else if (i.reg_operands)
29b0f896 5593 {
99018f42 5594 unsigned int op;
7ab9ffdd
L		 5595 unsigned int vex_reg = ~0;
5596
5597 for (op = 0; op < i.operands; op++)
5598 if (i.types[op].bitfield.reg8
5599 || i.types[op].bitfield.reg16
5600 || i.types[op].bitfield.reg32
5601 || i.types[op].bitfield.reg64
5602 || i.types[op].bitfield.regmmx
5603 || i.types[op].bitfield.regxmm
5604 || i.types[op].bitfield.regymm
5605 || i.types[op].bitfield.sreg2
5606 || i.types[op].bitfield.sreg3
5607 || i.types[op].bitfield.control
5608 || i.types[op].bitfield.debug
5609 || i.types[op].bitfield.test)
5610 break;
c0209578 5611
7ab9ffdd
L		 5612 if (vex_3_sources)
5613 op = dest;
2426c15f 5614 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 5615 {
5616 /* For instructions with VexNDS, the register-only
5617 source operand is encoded in VEX prefix. */
5618 gas_assert (mem != (unsigned int) ~0);
c0f3af97 5619
7ab9ffdd 5620 if (op > mem)
c0f3af97 5621 {
7ab9ffdd
L		 5622 vex_reg = op++;
5623 gas_assert (op < i.operands);
c0f3af97
L		 5624 }
5625 else
c0f3af97 5626 {
7ab9ffdd
L		 5627 vex_reg = op + 1;
5628 gas_assert (vex_reg < i.operands);
c0f3af97 5629 }
7ab9ffdd 5630 }
2426c15f 5631 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd
L		 5632 {
5633 /* For instructions with VexNDD, there should be
5634 no memory operand and the register destination
5635 is encoded in VEX prefix. */
5636 gas_assert (i.mem_operands == 0
5637 && (op + 2) == i.operands);
5638 vex_reg = op + 1;
5639 }
5640 else
5641 gas_assert (op < i.operands);
99018f42 5642
7ab9ffdd
L		 5643 if (vex_reg != (unsigned int) ~0)
5644 {
5645 gas_assert (i.reg_operands == 2);
5646
5647 if (!operand_type_equal (&i.tm.operand_types[vex_reg],
76ba9986 5648 &regxmm)
7ab9ffdd
L		 5649 && !operand_type_equal (&i.tm.operand_types[vex_reg],
5650 &regymm))
5651 abort ();
f88c9eb0 5652
7ab9ffdd
L		 5653 i.vex.register_specifier = i.op[vex_reg].regs;
5654 }
5655
1b9f0c97
L		 5656 /* Don't set OP operand twice. */
5657 if (vex_reg != op)
7ab9ffdd 5658 {
1b9f0c97
L		 5659 /* If there is an extension opcode to put here, the
5660 register number must be put into the regmem field. */
5661 if (i.tm.extension_opcode != None)
5662 {
5663 i.rm.regmem = i.op[op].regs->reg_num;
5664 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5665 i.rex |= REX_B;
5666 }
5667 else
5668 {
5669 i.rm.reg = i.op[op].regs->reg_num;
5670 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5671 i.rex |= REX_R;
5672 }
7ab9ffdd 5673 }
252b5132 5674
29b0f896
AM		 5675 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5676 must set it to 3 to indicate this is a register operand
5677 in the regmem field. */
5678 if (!i.mem_operands)
5679 i.rm.mode = 3;
5680 }
252b5132 5681
29b0f896 5682 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 5683 if (i.tm.extension_opcode != None)
29b0f896
AM		 5684 i.rm.reg = i.tm.extension_opcode;
5685 }
5686 return default_seg;
5687}
252b5132 5688
29b0f896 5689static void
e3bb37b5 5690output_branch (void)
29b0f896
AM		 5691{
5692 char *p;
5693 int code16;
5694 int prefix;
5695 relax_substateT subtype;
5696 symbolS *sym;
5697 offsetT off;
5698
5699 code16 = 0;
5700 if (flag_code == CODE_16BIT)
5701 code16 = CODE16;
5702
5703 prefix = 0;
5704 if (i.prefix[DATA_PREFIX] != 0)
252b5132 5705 {
29b0f896
AM		 5706 prefix = 1;
5707 i.prefixes -= 1;
5708 code16 ^= CODE16;
252b5132 5709 }
29b0f896
AM		 5710 /* Pentium4 branch hints. */
5711 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5712 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 5713 {
29b0f896
AM		 5714 prefix++;
5715 i.prefixes--;
5716 }
5717 if (i.prefix[REX_PREFIX] != 0)
5718 {
5719 prefix++;
5720 i.prefixes--;
2f66722d
AM		 5721 }
5722
29b0f896
AM		 5723 if (i.prefixes != 0 && !intel_syntax)
5724 as_warn (_("skipping prefixes on this instruction"));
5725
5726 /* It's always a symbol; End frag & setup for relax.
5727 Make sure there is enough room in this frag for the largest
5728 instruction we may generate in md_convert_frag. This is 2
5729 bytes for the opcode and room for the prefix and largest
5730 displacement. */
5731 frag_grow (prefix + 2 + 4);
5732 /* Prefix and 1 opcode byte go in fr_fix. */
5733 p = frag_more (prefix + 1);
5734 if (i.prefix[DATA_PREFIX] != 0)
5735 *p++ = DATA_PREFIX_OPCODE;
5736 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
5737 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
5738 *p++ = i.prefix[SEG_PREFIX];
5739 if (i.prefix[REX_PREFIX] != 0)
5740 *p++ = i.prefix[REX_PREFIX];
5741 *p = i.tm.base_opcode;
5742
5743 if ((unsigned char) *p == JUMP_PC_RELATIVE)
5744 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
40fb9820 5745 else if (cpu_arch_flags.bitfield.cpui386)
29b0f896
AM		 5746 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
5747 else
5748 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
5749 subtype |= code16;
3e73aa7c 5750
29b0f896
AM		 5751 sym = i.op[0].disps->X_add_symbol;
5752 off = i.op[0].disps->X_add_number;
3e73aa7c 5753
29b0f896
AM		 5754 if (i.op[0].disps->X_op != O_constant
5755 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 5756 {
29b0f896
AM		 5757 /* Handle complex expressions. */
5758 sym = make_expr_symbol (i.op[0].disps);
5759 off = 0;
5760 }
3e73aa7c 5761
29b0f896
AM		 5762 /* 1 possible extra opcode + 4 byte displacement go in var part.
5763 Pass reloc in fr_var. */
5764 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
5765}
3e73aa7c 5766
29b0f896 5767static void
e3bb37b5 5768output_jump (void)
29b0f896
AM		 5769{
5770 char *p;
5771 int size;
3e02c1cc 5772 fixS *fixP;
29b0f896 5773
40fb9820 5774 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 5775 {
5776 /* This is a loop or jecxz type instruction. */
5777 size = 1;
5778 if (i.prefix[ADDR_PREFIX] != 0)
5779 {
5780 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
5781 i.prefixes -= 1;
5782 }
5783 /* Pentium4 branch hints. */
5784 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5785 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5786 {
5787 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
5788 i.prefixes--;
3e73aa7c
JH		 5789 }
5790 }
29b0f896
AM		 5791 else
5792 {
5793 int code16;
3e73aa7c 5794
29b0f896
AM		 5795 code16 = 0;
5796 if (flag_code == CODE_16BIT)
5797 code16 = CODE16;
3e73aa7c 5798
29b0f896
AM		 5799 if (i.prefix[DATA_PREFIX] != 0)
5800 {
5801 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
5802 i.prefixes -= 1;
5803 code16 ^= CODE16;
5804 }
252b5132 5805
29b0f896
AM		 5806 size = 4;
5807 if (code16)
5808 size = 2;
5809 }
9fcc94b6 5810
29b0f896
AM		 5811 if (i.prefix[REX_PREFIX] != 0)
5812 {
5813 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
5814 i.prefixes -= 1;
5815 }
252b5132 5816
29b0f896
AM		 5817 if (i.prefixes != 0 && !intel_syntax)
5818 as_warn (_("skipping prefixes on this instruction"));
e0890092 5819
29b0f896
AM		 5820 p = frag_more (1 + size);
5821 *p++ = i.tm.base_opcode;
e0890092 5822
3e02c1cc
AM		 5823 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5824 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
5825
5826 /* All jumps handled here are signed, but don't use a signed limit
5827 check for 32 and 16 bit jumps as we want to allow wrap around at
5828 4G and 64k respectively. */
5829 if (size == 1)
5830 fixP->fx_signed = 1;
29b0f896 5831}
e0890092 5832
29b0f896 5833static void
e3bb37b5 5834output_interseg_jump (void)
29b0f896
AM		 5835{
5836 char *p;
5837 int size;
5838 int prefix;
5839 int code16;
252b5132 5840
29b0f896
AM		 5841 code16 = 0;
5842 if (flag_code == CODE_16BIT)
5843 code16 = CODE16;
a217f122 5844
29b0f896
AM		 5845 prefix = 0;
5846 if (i.prefix[DATA_PREFIX] != 0)
5847 {
5848 prefix = 1;
5849 i.prefixes -= 1;
5850 code16 ^= CODE16;
5851 }
5852 if (i.prefix[REX_PREFIX] != 0)
5853 {
5854 prefix++;
5855 i.prefixes -= 1;
5856 }
252b5132 5857
29b0f896
AM		 5858 size = 4;
5859 if (code16)
5860 size = 2;
252b5132 5861
29b0f896
AM		 5862 if (i.prefixes != 0 && !intel_syntax)
5863 as_warn (_("skipping prefixes on this instruction"));
252b5132 5864
29b0f896
AM		 5865 /* 1 opcode; 2 segment; offset */
5866 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 5867
29b0f896
AM		 5868 if (i.prefix[DATA_PREFIX] != 0)
5869 *p++ = DATA_PREFIX_OPCODE;
252b5132 5870
29b0f896
AM		 5871 if (i.prefix[REX_PREFIX] != 0)
5872 *p++ = i.prefix[REX_PREFIX];
252b5132 5873
29b0f896
AM		 5874 *p++ = i.tm.base_opcode;
5875 if (i.op[1].imms->X_op == O_constant)
5876 {
5877 offsetT n = i.op[1].imms->X_add_number;
252b5132 5878
29b0f896
AM		 5879 if (size == 2
5880 && !fits_in_unsigned_word (n)
5881 && !fits_in_signed_word (n))
5882 {
5883 as_bad (_("16-bit jump out of range"));
5884 return;
5885 }
5886 md_number_to_chars (p, n, size);
5887 }
5888 else
5889 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5890 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
5891 if (i.op[0].imms->X_op != O_constant)
5892 as_bad (_("can't handle non absolute segment in `%s'"),
5893 i.tm.name);
5894 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
5895}
a217f122 5896
29b0f896 5897static void
e3bb37b5 5898output_insn (void)
29b0f896 5899{
2bbd9c25
JJ		 5900 fragS *insn_start_frag;
5901 offsetT insn_start_off;
5902
29b0f896
AM		 5903 /* Tie dwarf2 debug info to the address at the start of the insn.
5904 We can't do this after the insn has been output as the current
5905 frag may have been closed off. eg. by frag_var. */
5906 dwarf2_emit_insn (0);
5907
2bbd9c25
JJ		 5908 insn_start_frag = frag_now;
5909 insn_start_off = frag_now_fix ();
5910
29b0f896 5911 /* Output jumps. */
40fb9820 5912 if (i.tm.opcode_modifier.jump)
29b0f896 5913 output_branch ();
40fb9820
L		 5914 else if (i.tm.opcode_modifier.jumpbyte
5915 || i.tm.opcode_modifier.jumpdword)
29b0f896 5916 output_jump ();
40fb9820 5917 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 5918 output_interseg_jump ();
5919 else
5920 {
5921 /* Output normal instructions here. */
5922 char *p;
5923 unsigned char *q;
47465058 5924 unsigned int j;
331d2d0d 5925 unsigned int prefix;
4dffcebc 5926
c0f3af97
L		 5927 /* Since the VEX prefix contains the implicit prefix, we don't
5928 need the explicit prefix. */
5929 if (!i.tm.opcode_modifier.vex)
bc4bd9ab 5930 {
c0f3af97 5931 switch (i.tm.opcode_length)
bc4bd9ab 5932 {
c0f3af97
L		 5933 case 3:
5934 if (i.tm.base_opcode & 0xff000000)
4dffcebc 5935 {
c0f3af97
L		 5936 prefix = (i.tm.base_opcode >> 24) & 0xff;
5937 goto check_prefix;
5938 }
5939 break;
5940 case 2:
5941 if ((i.tm.base_opcode & 0xff0000) != 0)
5942 {
5943 prefix = (i.tm.base_opcode >> 16) & 0xff;
5944 if (i.tm.cpu_flags.bitfield.cpupadlock)
5945 {
4dffcebc 5946check_prefix:
c0f3af97 5947 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 5948 || (i.prefix[REP_PREFIX]
c0f3af97
L		 5949 != REPE_PREFIX_OPCODE))
5950 add_prefix (prefix);
5951 }
5952 else
4dffcebc
L		 5953 add_prefix (prefix);
5954 }
c0f3af97
L		 5955 break;
5956 case 1:
5957 break;
5958 default:
5959 abort ();
bc4bd9ab 5960 }
c0f3af97
L		 5961
5962 /* The prefix bytes. */
5963 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
5964 if (*q)
5965 FRAG_APPEND_1_CHAR (*q);
0f10071e 5966 }
252b5132 5967
c0f3af97
L		 5968 if (i.tm.opcode_modifier.vex)
5969 {
5970 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
5971 if (*q)
5972 switch (j)
5973 {
5974 case REX_PREFIX:
5975 /* REX byte is encoded in VEX prefix. */
5976 break;
5977 case SEG_PREFIX:
5978 case ADDR_PREFIX:
5979 FRAG_APPEND_1_CHAR (*q);
5980 break;
5981 default:
5982 /* There should be no other prefixes for instructions
5983 with VEX prefix. */
5984 abort ();
5985 }
5986
5987 /* Now the VEX prefix. */
5988 p = frag_more (i.vex.length);
5989 for (j = 0; j < i.vex.length; j++)
5990 p[j] = i.vex.bytes[j];
5991 }
252b5132 5992
29b0f896 5993 /* Now the opcode; be careful about word order here! */
4dffcebc 5994 if (i.tm.opcode_length == 1)
29b0f896
AM		 5995 {
5996 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5997 }
5998 else
5999 {
4dffcebc 6000 switch (i.tm.opcode_length)
331d2d0d 6001 {
4dffcebc 6002 case 3:
331d2d0d
L		 6003 p = frag_more (3);
6004 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 6005 break;
6006 case 2:
6007 p = frag_more (2);
6008 break;
6009 default:
6010 abort ();
6011 break;
331d2d0d 6012 }
0f10071e 6013
29b0f896
AM		 6014 /* Put out high byte first: can't use md_number_to_chars! */
6015 *p++ = (i.tm.base_opcode >> 8) & 0xff;
6016 *p = i.tm.base_opcode & 0xff;
6017 }
3e73aa7c 6018
29b0f896 6019 /* Now the modrm byte and sib byte (if present). */
40fb9820 6020 if (i.tm.opcode_modifier.modrm)
29b0f896 6021 {
4a3523fa
L		 6022 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
6023 | i.rm.reg << 3
6024 | i.rm.mode << 6));
29b0f896
AM		 6025 /* If i.rm.regmem == ESP (4)
6026 && i.rm.mode != (Register mode)
6027 && not 16 bit
6028 ==> need second modrm byte. */
6029 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
6030 && i.rm.mode != 3
40fb9820 6031 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 6032 FRAG_APPEND_1_CHAR ((i.sib.base << 0
6033 | i.sib.index << 3
6034 | i.sib.scale << 6));
29b0f896 6035 }
3e73aa7c 6036
29b0f896 6037 if (i.disp_operands)
2bbd9c25 6038 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 6039
29b0f896 6040 if (i.imm_operands)
2bbd9c25 6041 output_imm (insn_start_frag, insn_start_off);
29b0f896 6042 }
252b5132 6043
29b0f896
AM		 6044#ifdef DEBUG386
6045 if (flag_debug)
6046 {
7b81dfbb 6047 pi ("" /*line*/, &i);
29b0f896
AM		 6048 }
6049#endif /* DEBUG386 */
6050}
252b5132 6051
e205caa7
L		 6052/* Return the size of the displacement operand N. */
6053
6054static int
6055disp_size (unsigned int n)
6056{
6057 int size = 4;
40fb9820
L		 6058 if (i.types[n].bitfield.disp64)
6059 size = 8;
6060 else if (i.types[n].bitfield.disp8)
6061 size = 1;
6062 else if (i.types[n].bitfield.disp16)
6063 size = 2;
e205caa7
L		 6064 return size;
6065}
6066
6067/* Return the size of the immediate operand N. */
6068
6069static int
6070imm_size (unsigned int n)
6071{
6072 int size = 4;
40fb9820
L		 6073 if (i.types[n].bitfield.imm64)
6074 size = 8;
6075 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
6076 size = 1;
6077 else if (i.types[n].bitfield.imm16)
6078 size = 2;
e205caa7
L		 6079 return size;
6080}
6081
29b0f896 6082static void
64e74474 6083output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 6084{
6085 char *p;
6086 unsigned int n;
252b5132 6087
29b0f896
AM		 6088 for (n = 0; n < i.operands; n++)
6089 {
40fb9820 6090 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 6091 {
6092 if (i.op[n].disps->X_op == O_constant)
6093 {
e205caa7 6094 int size = disp_size (n);
29b0f896 6095 offsetT val;
252b5132 6096
29b0f896
AM		 6097 val = offset_in_range (i.op[n].disps->X_add_number,
6098 size);
6099 p = frag_more (size);
6100 md_number_to_chars (p, val, size);
6101 }
6102 else
6103 {
f86103b7 6104 enum bfd_reloc_code_real reloc_type;
e205caa7 6105 int size = disp_size (n);
40fb9820 6106 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 6107 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
6108
e205caa7 6109 /* We can't have 8 bit displacement here. */
9c2799c2 6110 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 6111
29b0f896
AM		 6112 /* The PC relative address is computed relative
6113 to the instruction boundary, so in case immediate
6114 fields follows, we need to adjust the value. */
6115 if (pcrel && i.imm_operands)
6116 {
29b0f896 6117 unsigned int n1;
e205caa7 6118 int sz = 0;
252b5132 6119
29b0f896 6120 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 6121 if (operand_type_check (i.types[n1], imm))
252b5132 6122 {
e205caa7
L		 6123 /* Only one immediate is allowed for PC
6124 relative address. */
9c2799c2 6125 gas_assert (sz == 0);
e205caa7
L		 6126 sz = imm_size (n1);
6127 i.op[n].disps->X_add_number -= sz;
252b5132 6128 }
29b0f896 6129 /* We should find the immediate. */
9c2799c2 6130 gas_assert (sz != 0);
29b0f896 6131 }
520dc8e8 6132
29b0f896 6133 p = frag_more (size);
2bbd9c25 6134 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 6135 if (GOT_symbol
2bbd9c25 6136 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 6137 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6138 || reloc_type == BFD_RELOC_X86_64_32S
6139 || (reloc_type == BFD_RELOC_64
6140 && object_64bit))
d6ab8113
JB		 6141 && (i.op[n].disps->X_op == O_symbol
6142 || (i.op[n].disps->X_op == O_add
6143 && ((symbol_get_value_expression
6144 (i.op[n].disps->X_op_symbol)->X_op)
6145 == O_subtract))))
6146 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 6147 {
6148 offsetT add;
6149
6150 if (insn_start_frag == frag_now)
6151 add = (p - frag_now->fr_literal) - insn_start_off;
6152 else
6153 {
6154 fragS *fr;
6155
6156 add = insn_start_frag->fr_fix - insn_start_off;
6157 for (fr = insn_start_frag->fr_next;
6158 fr && fr != frag_now; fr = fr->fr_next)
6159 add += fr->fr_fix;
6160 add += p - frag_now->fr_literal;
6161 }
6162
4fa24527 6163 if (!object_64bit)
7b81dfbb
AJ		 6164 {
6165 reloc_type = BFD_RELOC_386_GOTPC;
6166 i.op[n].imms->X_add_number += add;
6167 }
6168 else if (reloc_type == BFD_RELOC_64)
6169 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 6170 else
7b81dfbb
AJ		 6171 /* Don't do the adjustment for x86-64, as there
6172 the pcrel addressing is relative to the _next_
6173 insn, and that is taken care of in other code. */
d6ab8113 6174 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 6175 }
062cd5e7 6176 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 6177 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 6178 }
6179 }
6180 }
6181}
252b5132 6182
29b0f896 6183static void
64e74474 6184output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 6185{
6186 char *p;
6187 unsigned int n;
252b5132 6188
29b0f896
AM		 6189 for (n = 0; n < i.operands; n++)
6190 {
40fb9820 6191 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 6192 {
6193 if (i.op[n].imms->X_op == O_constant)
6194 {
e205caa7 6195 int size = imm_size (n);
29b0f896 6196 offsetT val;
b4cac588 6197
29b0f896
AM		 6198 val = offset_in_range (i.op[n].imms->X_add_number,
6199 size);
6200 p = frag_more (size);
6201 md_number_to_chars (p, val, size);
6202 }
6203 else
6204 {
6205 /* Not absolute_section.
6206 Need a 32-bit fixup (don't support 8bit
6207 non-absolute imms). Try to support other
6208 sizes ... */
f86103b7 6209 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 6210 int size = imm_size (n);
6211 int sign;
29b0f896 6212
40fb9820 6213 if (i.types[n].bitfield.imm32s
a7d61044 6214 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 6215 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 6216 sign = 1;
e205caa7
L		 6217 else
6218 sign = 0;
520dc8e8 6219
29b0f896
AM		 6220 p = frag_more (size);
6221 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 6222
2bbd9c25
JJ		 6223 /* This is tough to explain. We end up with this one if we
6224 * have operands that look like
6225 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6226 * obtain the absolute address of the GOT, and it is strongly
6227 * preferable from a performance point of view to avoid using
6228 * a runtime relocation for this. The actual sequence of
6229 * instructions often look something like:
6230 *
6231 * call .L66
6232 * .L66:
6233 * popl %ebx
6234 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6235 *
6236 * The call and pop essentially return the absolute address
6237 * of the label .L66 and store it in %ebx. The linker itself
6238 * will ultimately change the first operand of the addl so
6239 * that %ebx points to the GOT, but to keep things simple, the
6240 * .o file must have this operand set so that it generates not
6241 * the absolute address of .L66, but the absolute address of
6242 * itself. This allows the linker itself simply treat a GOTPC
6243 * relocation as asking for a pcrel offset to the GOT to be
6244 * added in, and the addend of the relocation is stored in the
6245 * operand field for the instruction itself.
6246 *
6247 * Our job here is to fix the operand so that it would add
6248 * the correct offset so that %ebx would point to itself. The
6249 * thing that is tricky is that .-.L66 will point to the
6250 * beginning of the instruction, so we need to further modify
6251 * the operand so that it will point to itself. There are
6252 * other cases where you have something like:
6253 *
6254 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6255 *
6256 * and here no correction would be required. Internally in
6257 * the assembler we treat operands of this form as not being
6258 * pcrel since the '.' is explicitly mentioned, and I wonder
6259 * whether it would simplify matters to do it this way. Who
6260 * knows. In earlier versions of the PIC patches, the
6261 * pcrel_adjust field was used to store the correction, but
6262 * since the expression is not pcrel, I felt it would be
6263 * confusing to do it this way. */
6264
d6ab8113 6265 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6266 || reloc_type == BFD_RELOC_X86_64_32S
6267 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 6268 && GOT_symbol
6269 && GOT_symbol == i.op[n].imms->X_add_symbol
6270 && (i.op[n].imms->X_op == O_symbol
6271 || (i.op[n].imms->X_op == O_add
6272 && ((symbol_get_value_expression
6273 (i.op[n].imms->X_op_symbol)->X_op)
6274 == O_subtract))))
6275 {
2bbd9c25
JJ		 6276 offsetT add;
6277
6278 if (insn_start_frag == frag_now)
6279 add = (p - frag_now->fr_literal) - insn_start_off;
6280 else
6281 {
6282 fragS *fr;
6283
6284 add = insn_start_frag->fr_fix - insn_start_off;
6285 for (fr = insn_start_frag->fr_next;
6286 fr && fr != frag_now; fr = fr->fr_next)
6287 add += fr->fr_fix;
6288 add += p - frag_now->fr_literal;
6289 }
6290
4fa24527 6291 if (!object_64bit)
d6ab8113 6292 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 6293 else if (size == 4)
d6ab8113 6294 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 6295 else if (size == 8)
6296 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 6297 i.op[n].imms->X_add_number += add;
29b0f896 6298 }
29b0f896
AM		 6299 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6300 i.op[n].imms, 0, reloc_type);
6301 }
6302 }
6303 }
252b5132
RH		 6304}
6305\f
d182319b
JB		 6306/* x86_cons_fix_new is called via the expression parsing code when a
6307 reloc is needed. We use this hook to get the correct .got reloc. */
6308static enum bfd_reloc_code_real got_reloc = NO_RELOC;
6309static int cons_sign = -1;
6310
6311void
e3bb37b5 6312x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 6313 expressionS *exp)
d182319b
JB		 6314{
6315 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
6316
6317 got_reloc = NO_RELOC;
6318
6319#ifdef TE_PE
6320 if (exp->X_op == O_secrel)
6321 {
6322 exp->X_op = O_symbol;
6323 r = BFD_RELOC_32_SECREL;
6324 }
6325#endif
6326
6327 fix_new_exp (frag, off, len, exp, 0, r);
6328}
6329
718ddfc0
JB		 6330#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6331# define lex_got(reloc, adjust, types) NULL
6332#else
f3c180ae
AM		 6333/* Parse operands of the form
6334 <symbol>@GOTOFF+<nnn>
6335 and similar .plt or .got references.
6336
6337 If we find one, set up the correct relocation in RELOC and copy the
6338 input string, minus the `@GOTOFF' into a malloc'd buffer for
6339 parsing by the calling routine. Return this buffer, and if ADJUST
6340 is non-null set it to the length of the string we removed from the
6341 input line. Otherwise return NULL. */
6342static char *
91d6fa6a 6343lex_got (enum bfd_reloc_code_real *rel,
64e74474 6344 int *adjust,
40fb9820 6345 i386_operand_type *types)
f3c180ae 6346{
7b81dfbb
AJ		 6347 /* Some of the relocations depend on the size of what field is to
6348 be relocated. But in our callers i386_immediate and i386_displacement
6349 we don't yet know the operand size (this will be set by insn
6350 matching). Hence we record the word32 relocation here,
6351 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 6352 static const struct {
6353 const char *str;
cff8d58a 6354 int len;
4fa24527 6355 const enum bfd_reloc_code_real rel[2];
40fb9820 6356 const i386_operand_type types64;
f3c180ae 6357 } gotrel[] = {
cff8d58a
L		 6358 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
6359 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 6360 OPERAND_TYPE_IMM64 },
cff8d58a
L		 6361 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
6362 BFD_RELOC_X86_64_PLT32 },
40fb9820 6363 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6364 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
6365 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 6366 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 6367 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
6368 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 6369 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 6370 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
6371 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 6372 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6373 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
6374 BFD_RELOC_X86_64_TLSGD },
40fb9820 6375 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6376 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
6377 _dummy_first_bfd_reloc_code_real },
40fb9820 6378 OPERAND_TYPE_NONE },
cff8d58a
L		 6379 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
6380 BFD_RELOC_X86_64_TLSLD },
40fb9820 6381 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6382 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
6383 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 6384 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6385 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
6386 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 6387 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 6388 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
6389 _dummy_first_bfd_reloc_code_real },
40fb9820 6390 OPERAND_TYPE_NONE },
cff8d58a
L		 6391 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
6392 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 6393 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 6394 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
6395 _dummy_first_bfd_reloc_code_real },
40fb9820 6396 OPERAND_TYPE_NONE },
cff8d58a
L		 6397 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
6398 _dummy_first_bfd_reloc_code_real },
40fb9820 6399 OPERAND_TYPE_NONE },
cff8d58a
L		 6400 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
6401 BFD_RELOC_X86_64_GOT32 },
40fb9820 6402 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 6403 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
6404 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 6405 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6406 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
6407 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 6408 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 6409 };
6410 char *cp;
6411 unsigned int j;
6412
718ddfc0
JB		 6413 if (!IS_ELF)
6414 return NULL;
6415
f3c180ae 6416 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 6417 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 6418 return NULL;
6419
47465058 6420 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 6421 {
cff8d58a 6422 int len = gotrel[j].len;
28f81592 6423 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 6424 {
4fa24527 6425 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 6426 {
28f81592
AM		 6427 int first, second;
6428 char *tmpbuf, *past_reloc;
f3c180ae 6429
91d6fa6a 6430 *rel = gotrel[j].rel[object_64bit];
28f81592
AM		 6431 if (adjust)
6432 *adjust = len;
f3c180ae 6433
3956db08
JB		 6434 if (types)
6435 {
6436 if (flag_code != CODE_64BIT)
40fb9820
L		 6437 {
6438 types->bitfield.imm32 = 1;
6439 types->bitfield.disp32 = 1;
6440 }
3956db08
JB		 6441 else
6442 *types = gotrel[j].types64;
6443 }
6444
f3c180ae
AM		 6445 if (GOT_symbol == NULL)
6446 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
6447
28f81592 6448 /* The length of the first part of our input line. */
f3c180ae 6449 first = cp - input_line_pointer;
28f81592
AM		 6450
6451 /* The second part goes from after the reloc token until
67c11a9b 6452 (and including) an end_of_line char or comma. */
28f81592 6453 past_reloc = cp + 1 + len;
67c11a9b
AM		 6454 cp = past_reloc;
6455 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
6456 ++cp;
6457 second = cp + 1 - past_reloc;
28f81592
AM		 6458
6459 /* Allocate and copy string. The trailing NUL shouldn't
6460 be necessary, but be safe. */
1e9cc1c2 6461 tmpbuf = (char *) xmalloc (first + second + 2);
f3c180ae 6462 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 6463 if (second != 0 && *past_reloc != ' ')
6464 /* Replace the relocation token with ' ', so that
6465 errors like foo@GOTOFF1 will be detected. */
6466 tmpbuf[first++] = ' ';
6467 memcpy (tmpbuf + first, past_reloc, second);
6468 tmpbuf[first + second] = '\0';
f3c180ae
AM		 6469 return tmpbuf;
6470 }
6471
4fa24527
JB		 6472 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6473 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 6474 return NULL;
6475 }
6476 }
6477
6478 /* Might be a symbol version string. Don't as_bad here. */
6479 return NULL;
6480}
6481
f3c180ae 6482void
e3bb37b5 6483x86_cons (expressionS *exp, int size)
f3c180ae 6484{
ee86248c
JB		 6485 intel_syntax = -intel_syntax;
6486
3c7b9c2c 6487 exp->X_md = 0;
4fa24527 6488 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 6489 {
6490 /* Handle @GOTOFF and the like in an expression. */
6491 char *save;
6492 char *gotfree_input_line;
6493 int adjust;
6494
6495 save = input_line_pointer;
3956db08 6496 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 6497 if (gotfree_input_line)
6498 input_line_pointer = gotfree_input_line;
6499
6500 expression (exp);
6501
6502 if (gotfree_input_line)
6503 {
6504 /* expression () has merrily parsed up to the end of line,
6505 or a comma - in the wrong buffer. Transfer how far
6506 input_line_pointer has moved to the right buffer. */
6507 input_line_pointer = (save
6508 + (input_line_pointer - gotfree_input_line)
6509 + adjust);
6510 free (gotfree_input_line);
3992d3b7
AM		 6511 if (exp->X_op == O_constant
6512 || exp->X_op == O_absent
6513 || exp->X_op == O_illegal
0398aac5 6514 || exp->X_op == O_register
3992d3b7
AM		 6515 || exp->X_op == O_big)
6516 {
6517 char c = *input_line_pointer;
6518 *input_line_pointer = 0;
6519 as_bad (_("missing or invalid expression `%s'"), save);
6520 *input_line_pointer = c;
6521 }
f3c180ae
AM		 6522 }
6523 }
6524 else
6525 expression (exp);
ee86248c
JB		 6526
6527 intel_syntax = -intel_syntax;
6528
6529 if (intel_syntax)
6530 i386_intel_simplify (exp);
f3c180ae
AM		 6531}
6532#endif
6533
9f32dd5b
L		 6534static void
6535signed_cons (int size)
6482c264 6536{
d182319b
JB		 6537 if (flag_code == CODE_64BIT)
6538 cons_sign = 1;
6539 cons (size);
6540 cons_sign = -1;
6482c264
NC		 6541}
6542
d182319b 6543#ifdef TE_PE
6482c264
NC		 6544static void
6545pe_directive_secrel (dummy)
6546 int dummy ATTRIBUTE_UNUSED;
6547{
6548 expressionS exp;
6549
6550 do
6551 {
6552 expression (&exp);
6553 if (exp.X_op == O_symbol)
6554 exp.X_op = O_secrel;
6555
6556 emit_expr (&exp, 4);
6557 }
6558 while (*input_line_pointer++ == ',');
6559
6560 input_line_pointer--;
6561 demand_empty_rest_of_line ();
6562}
6482c264
NC		 6563#endif
6564
252b5132 6565static int
70e41ade 6566i386_immediate (char *imm_start)
252b5132
RH		 6567{
6568 char *save_input_line_pointer;
f3c180ae 6569 char *gotfree_input_line;
252b5132 6570 segT exp_seg = 0;
47926f60 6571 expressionS *exp;
40fb9820
L		 6572 i386_operand_type types;
6573
0dfbf9d7 6574 operand_type_set (&types, ~0);
252b5132
RH		 6575
6576 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
6577 {
31b2323c
L		 6578 as_bad (_("at most %d immediate operands are allowed"),
6579 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 6580 return 0;
6581 }
6582
6583 exp = &im_expressions[i.imm_operands++];
520dc8e8 6584 i.op[this_operand].imms = exp;
252b5132
RH		 6585
6586 if (is_space_char (*imm_start))
6587 ++imm_start;
6588
6589 save_input_line_pointer = input_line_pointer;
6590 input_line_pointer = imm_start;
6591
3956db08 6592 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6593 if (gotfree_input_line)
6594 input_line_pointer = gotfree_input_line;
252b5132
RH		 6595
6596 exp_seg = expression (exp);
6597
83183c0c 6598 SKIP_WHITESPACE ();
252b5132 6599 if (*input_line_pointer)
f3c180ae 6600 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 6601
6602 input_line_pointer = save_input_line_pointer;
f3c180ae 6603 if (gotfree_input_line)
ee86248c
JB		 6604 {
6605 free (gotfree_input_line);
6606
6607 if (exp->X_op == O_constant || exp->X_op == O_register)
6608 exp->X_op = O_illegal;
6609 }
6610
6611 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
6612}
252b5132 6613
ee86248c
JB		 6614static int
6615i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6616 i386_operand_type types, const char *imm_start)
6617{
6618 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 6619 {
313c53d1
L		 6620 if (imm_start)
6621 as_bad (_("missing or invalid immediate expression `%s'"),
6622 imm_start);
3992d3b7 6623 return 0;
252b5132 6624 }
3e73aa7c 6625 else if (exp->X_op == O_constant)
252b5132 6626 {
47926f60 6627 /* Size it properly later. */
40fb9820 6628 i.types[this_operand].bitfield.imm64 = 1;
3e73aa7c 6629 /* If BFD64, sign extend val. */
4eed87de
AM		 6630 if (!use_rela_relocations
6631 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
6632 exp->X_add_number
6633 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 6634 }
4c63da97 6635#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 6636 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 6637 && exp_seg != absolute_section
47926f60 6638 && exp_seg != text_section
24eab124
AM		 6639 && exp_seg != data_section
6640 && exp_seg != bss_section
6641 && exp_seg != undefined_section
f86103b7 6642 && !bfd_is_com_section (exp_seg))
252b5132 6643 {
d0b47220 6644 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 6645 return 0;
6646 }
6647#endif
bb8f5920
L		 6648 else if (!intel_syntax && exp->X_op == O_register)
6649 {
313c53d1
L		 6650 if (imm_start)
6651 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 6652 return 0;
6653 }
252b5132
RH		 6654 else
6655 {
6656 /* This is an address. The size of the address will be
24eab124 6657 determined later, depending on destination register,
3e73aa7c 6658 suffix, or the default for the section. */
40fb9820
L		 6659 i.types[this_operand].bitfield.imm8 = 1;
6660 i.types[this_operand].bitfield.imm16 = 1;
6661 i.types[this_operand].bitfield.imm32 = 1;
6662 i.types[this_operand].bitfield.imm32s = 1;
6663 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 6664 i.types[this_operand] = operand_type_and (i.types[this_operand],
6665 types);
252b5132
RH		 6666 }
6667
6668 return 1;
6669}
6670
551c1ca1 6671static char *
e3bb37b5 6672i386_scale (char *scale)
252b5132 6673{
551c1ca1
AM		 6674 offsetT val;
6675 char *save = input_line_pointer;
252b5132 6676
551c1ca1
AM		 6677 input_line_pointer = scale;
6678 val = get_absolute_expression ();
6679
6680 switch (val)
252b5132 6681 {
551c1ca1 6682 case 1:
252b5132
RH		 6683 i.log2_scale_factor = 0;
6684 break;
551c1ca1 6685 case 2:
252b5132
RH		 6686 i.log2_scale_factor = 1;
6687 break;
551c1ca1 6688 case 4:
252b5132
RH		 6689 i.log2_scale_factor = 2;
6690 break;
551c1ca1 6691 case 8:
252b5132
RH		 6692 i.log2_scale_factor = 3;
6693 break;
6694 default:
a724f0f4
JB		 6695 {
6696 char sep = *input_line_pointer;
6697
6698 *input_line_pointer = '\0';
6699 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6700 scale);
6701 *input_line_pointer = sep;
6702 input_line_pointer = save;
6703 return NULL;
6704 }
252b5132 6705 }
29b0f896 6706 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 6707 {
6708 as_warn (_("scale factor of %d without an index register"),
24eab124 6709 1 << i.log2_scale_factor);
252b5132 6710 i.log2_scale_factor = 0;
252b5132 6711 }
551c1ca1
AM		 6712 scale = input_line_pointer;
6713 input_line_pointer = save;
6714 return scale;
252b5132
RH		 6715}
6716
252b5132 6717static int
e3bb37b5 6718i386_displacement (char *disp_start, char *disp_end)
252b5132 6719{
29b0f896 6720 expressionS *exp;
252b5132
RH		 6721 segT exp_seg = 0;
6722 char *save_input_line_pointer;
f3c180ae 6723 char *gotfree_input_line;
40fb9820
L		 6724 int override;
6725 i386_operand_type bigdisp, types = anydisp;
3992d3b7 6726 int ret;
252b5132 6727
31b2323c
L		 6728 if (i.disp_operands == MAX_MEMORY_OPERANDS)
6729 {
6730 as_bad (_("at most %d displacement operands are allowed"),
6731 MAX_MEMORY_OPERANDS);
6732 return 0;
6733 }
6734
0dfbf9d7 6735 operand_type_set (&bigdisp, 0);
40fb9820
L		 6736 if ((i.types[this_operand].bitfield.jumpabsolute)
6737 || (!current_templates->start->opcode_modifier.jump
6738 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 6739 {
40fb9820 6740 bigdisp.bitfield.disp32 = 1;
e05278af 6741 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 6742 if (flag_code == CODE_64BIT)
6743 {
6744 if (!override)
6745 {
6746 bigdisp.bitfield.disp32s = 1;
6747 bigdisp.bitfield.disp64 = 1;
6748 }
6749 }
6750 else if ((flag_code == CODE_16BIT) ^ override)
6751 {
6752 bigdisp.bitfield.disp32 = 0;
6753 bigdisp.bitfield.disp16 = 1;
6754 }
e05278af
JB		 6755 }
6756 else
6757 {
6758 /* For PC-relative branches, the width of the displacement
6759 is dependent upon data size, not address size. */
e05278af 6760 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 6761 if (flag_code == CODE_64BIT)
6762 {
6763 if (override || i.suffix == WORD_MNEM_SUFFIX)
6764 bigdisp.bitfield.disp16 = 1;
6765 else
6766 {
6767 bigdisp.bitfield.disp32 = 1;
6768 bigdisp.bitfield.disp32s = 1;
6769 }
6770 }
6771 else
e05278af
JB		 6772 {
6773 if (!override)
6774 override = (i.suffix == (flag_code != CODE_16BIT
6775 ? WORD_MNEM_SUFFIX
6776 : LONG_MNEM_SUFFIX));
40fb9820
L		 6777 bigdisp.bitfield.disp32 = 1;
6778 if ((flag_code == CODE_16BIT) ^ override)
6779 {
6780 bigdisp.bitfield.disp32 = 0;
6781 bigdisp.bitfield.disp16 = 1;
6782 }
e05278af 6783 }
e05278af 6784 }
c6fb90c8
L		 6785 i.types[this_operand] = operand_type_or (i.types[this_operand],
6786 bigdisp);
252b5132
RH		 6787
6788 exp = &disp_expressions[i.disp_operands];
520dc8e8 6789 i.op[this_operand].disps = exp;
252b5132
RH		 6790 i.disp_operands++;
6791 save_input_line_pointer = input_line_pointer;
6792 input_line_pointer = disp_start;
6793 END_STRING_AND_SAVE (disp_end);
6794
6795#ifndef GCC_ASM_O_HACK
6796#define GCC_ASM_O_HACK 0
6797#endif
6798#if GCC_ASM_O_HACK
6799 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 6800 if (i.types[this_operand].bitfield.baseIndex
24eab124 6801 && displacement_string_end[-1] == '+')
252b5132
RH		 6802 {
6803 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 6804 constraint within gcc asm statements.
6805 For instance:
6806
6807 #define _set_tssldt_desc(n,addr,limit,type) \
6808 __asm__ __volatile__ ( \
6809 "movw %w2,%0\n\t" \
6810 "movw %w1,2+%0\n\t" \
6811 "rorl $16,%1\n\t" \
6812 "movb %b1,4+%0\n\t" \
6813 "movb %4,5+%0\n\t" \
6814 "movb $0,6+%0\n\t" \
6815 "movb %h1,7+%0\n\t" \
6816 "rorl $16,%1" \
6817 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6818
6819 This works great except that the output assembler ends
6820 up looking a bit weird if it turns out that there is
6821 no offset. You end up producing code that looks like:
6822
6823 #APP
6824 movw $235,(%eax)
6825 movw %dx,2+(%eax)
6826 rorl $16,%edx
6827 movb %dl,4+(%eax)
6828 movb $137,5+(%eax)
6829 movb $0,6+(%eax)
6830 movb %dh,7+(%eax)
6831 rorl $16,%edx
6832 #NO_APP
6833
47926f60 6834 So here we provide the missing zero. */
24eab124
AM		 6835
6836 *displacement_string_end = '0';
252b5132
RH		 6837 }
6838#endif
3956db08 6839 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6840 if (gotfree_input_line)
6841 input_line_pointer = gotfree_input_line;
252b5132 6842
24eab124 6843 exp_seg = expression (exp);
252b5132 6844
636c26b0
AM		 6845 SKIP_WHITESPACE ();
6846 if (*input_line_pointer)
6847 as_bad (_("junk `%s' after expression"), input_line_pointer);
6848#if GCC_ASM_O_HACK
6849 RESTORE_END_STRING (disp_end + 1);
6850#endif
636c26b0 6851 input_line_pointer = save_input_line_pointer;
636c26b0 6852 if (gotfree_input_line)
ee86248c
JB		 6853 {
6854 free (gotfree_input_line);
6855
6856 if (exp->X_op == O_constant || exp->X_op == O_register)
6857 exp->X_op = O_illegal;
6858 }
6859
6860 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
6861
6862 RESTORE_END_STRING (disp_end);
6863
6864 return ret;
6865}
6866
6867static int
6868i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6869 i386_operand_type types, const char *disp_start)
6870{
6871 i386_operand_type bigdisp;
6872 int ret = 1;
636c26b0 6873
24eab124
AM		 6874 /* We do this to make sure that the section symbol is in
6875 the symbol table. We will ultimately change the relocation
47926f60 6876 to be relative to the beginning of the section. */
1ae12ab7 6877 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 6878 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
6879 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 6880 {
636c26b0 6881 if (exp->X_op != O_symbol)
3992d3b7 6882 goto inv_disp;
636c26b0 6883
e5cb08ac 6884 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 6885 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
6886 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 6887 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 6888 exp->X_op = O_subtract;
6889 exp->X_op_symbol = GOT_symbol;
1ae12ab7 6890 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 6891 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 6892 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6893 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 6894 else
29b0f896 6895 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 6896 }
252b5132 6897
3992d3b7
AM		 6898 else if (exp->X_op == O_absent
6899 || exp->X_op == O_illegal
ee86248c 6900 || exp->X_op == O_big)
2daf4fd8 6901 {
3992d3b7
AM		 6902 inv_disp:
6903 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 6904 disp_start);
3992d3b7 6905 ret = 0;
2daf4fd8
AM		 6906 }
6907
0e1147d9
L		 6908 else if (flag_code == CODE_64BIT
6909 && !i.prefix[ADDR_PREFIX]
6910 && exp->X_op == O_constant)
6911 {
6912 /* Since displacement is signed extended to 64bit, don't allow
6913 disp32 and turn off disp32s if they are out of range. */
6914 i.types[this_operand].bitfield.disp32 = 0;
6915 if (!fits_in_signed_long (exp->X_add_number))
6916 {
6917 i.types[this_operand].bitfield.disp32s = 0;
6918 if (i.types[this_operand].bitfield.baseindex)
6919 {
6920 as_bad (_("0x%lx out range of signed 32bit displacement"),
6921 (long) exp->X_add_number);
6922 ret = 0;
6923 }
6924 }
6925 }
6926
4c63da97 6927#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 6928 else if (exp->X_op != O_constant
6929 && OUTPUT_FLAVOR == bfd_target_aout_flavour
6930 && exp_seg != absolute_section
6931 && exp_seg != text_section
6932 && exp_seg != data_section
6933 && exp_seg != bss_section
6934 && exp_seg != undefined_section
6935 && !bfd_is_com_section (exp_seg))
24eab124 6936 {
d0b47220 6937 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 6938 ret = 0;
24eab124 6939 }
252b5132 6940#endif
3956db08 6941
40fb9820
L		 6942 /* Check if this is a displacement only operand. */
6943 bigdisp = i.types[this_operand];
6944 bigdisp.bitfield.disp8 = 0;
6945 bigdisp.bitfield.disp16 = 0;
6946 bigdisp.bitfield.disp32 = 0;
6947 bigdisp.bitfield.disp32s = 0;
6948 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 6949 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 6950 i.types[this_operand] = operand_type_and (i.types[this_operand],
6951 types);
3956db08 6952
3992d3b7 6953 return ret;
252b5132
RH		 6954}
6955
eecb386c 6956/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 6957 Return 1 on success, 0 on a failure. */
6958
252b5132 6959static int
e3bb37b5 6960i386_index_check (const char *operand_string)
252b5132 6961{
3e73aa7c 6962 int ok;
fc0763e6 6963 const char *kind = "base/index";
24eab124 6964#if INFER_ADDR_PREFIX
eecb386c
AM		 6965 int fudged = 0;
6966
24eab124
AM		 6967 tryprefix:
6968#endif
3e73aa7c 6969 ok = 1;
fc0763e6
JB		 6970 if (current_templates->start->opcode_modifier.isstring
6971 && !current_templates->start->opcode_modifier.immext
6972 && (current_templates->end[-1].opcode_modifier.isstring
6973 || i.mem_operands))
6974 {
6975 /* Memory operands of string insns are special in that they only allow
6976 a single register (rDI, rSI, or rBX) as their memory address. */
6977 unsigned int expected;
6978
6979 kind = "string address";
6980
6981 if (current_templates->start->opcode_modifier.w)
6982 {
6983 i386_operand_type type = current_templates->end[-1].operand_types[0];
6984
6985 if (!type.bitfield.baseindex
6986 || ((!i.mem_operands != !intel_syntax)
6987 && current_templates->end[-1].operand_types[1]
6988 .bitfield.baseindex))
6989 type = current_templates->end[-1].operand_types[1];
6990 expected = type.bitfield.esseg ? 7 /* rDI */ : 6 /* rSI */;
6991 }
6992 else
6993 expected = 3 /* rBX */;
6994
6995 if (!i.base_reg || i.index_reg
6996 || operand_type_check (i.types[this_operand], disp))
6997 ok = -1;
6998 else if (!(flag_code == CODE_64BIT
6999 ? i.prefix[ADDR_PREFIX]
7000 ? i.base_reg->reg_type.bitfield.reg32
7001 : i.base_reg->reg_type.bitfield.reg64
7002 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
7003 ? i.base_reg->reg_type.bitfield.reg32
7004 : i.base_reg->reg_type.bitfield.reg16))
7005 ok = 0;
7006 else if (i.base_reg->reg_num != expected)
7007 ok = -1;
7008
7009 if (ok < 0)
7010 {
7011 unsigned int j;
7012
7013 for (j = 0; j < i386_regtab_size; ++j)
7014 if ((flag_code == CODE_64BIT
7015 ? i.prefix[ADDR_PREFIX]
7016 ? i386_regtab[j].reg_type.bitfield.reg32
7017 : i386_regtab[j].reg_type.bitfield.reg64
7018 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
7019 ? i386_regtab[j].reg_type.bitfield.reg32
7020 : i386_regtab[j].reg_type.bitfield.reg16)
7021 && i386_regtab[j].reg_num == expected)
7022 break;
9c2799c2 7023 gas_assert (j < i386_regtab_size);
fc0763e6
JB		 7024 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
7025 operand_string,
7026 intel_syntax ? '[' : '(',
7027 register_prefix,
7028 i386_regtab[j].reg_name,
7029 intel_syntax ? ']' : ')');
7030 ok = 1;
7031 }
7032 }
7033 else if (flag_code == CODE_64BIT)
64e74474 7034 {
64e74474 7035 if ((i.base_reg
40fb9820
L		 7036 && ((i.prefix[ADDR_PREFIX] == 0
7037 && !i.base_reg->reg_type.bitfield.reg64)
7038 || (i.prefix[ADDR_PREFIX]
7039 && !i.base_reg->reg_type.bitfield.reg32))
7040 && (i.index_reg
9a04903e
JB		 7041 || i.base_reg->reg_num !=
7042 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
64e74474 7043 || (i.index_reg
40fb9820
L		 7044 && (!i.index_reg->reg_type.bitfield.baseindex
7045 || (i.prefix[ADDR_PREFIX] == 0
db51cc60
L		 7046 && i.index_reg->reg_num != RegRiz
7047 && !i.index_reg->reg_type.bitfield.reg64
7048 )
40fb9820 7049 || (i.prefix[ADDR_PREFIX]
db51cc60 7050 && i.index_reg->reg_num != RegEiz
40fb9820 7051 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 7052 ok = 0;
3e73aa7c
JH		 7053 }
7054 else
7055 {
7056 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
7057 {
7058 /* 16bit checks. */
7059 if ((i.base_reg
40fb9820
L		 7060 && (!i.base_reg->reg_type.bitfield.reg16
7061 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 7062 || (i.index_reg
40fb9820
L		 7063 && (!i.index_reg->reg_type.bitfield.reg16
7064 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 7065 || !(i.base_reg
7066 && i.base_reg->reg_num < 6
7067 && i.index_reg->reg_num >= 6
7068 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 7069 ok = 0;
7070 }
7071 else
e5cb08ac 7072 {
3e73aa7c
JH		 7073 /* 32bit checks. */
7074 if ((i.base_reg
40fb9820 7075 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 7076 || (i.index_reg
db51cc60
L		 7077 && ((!i.index_reg->reg_type.bitfield.reg32
7078 && i.index_reg->reg_num != RegEiz)
40fb9820 7079 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 7080 ok = 0;
3e73aa7c
JH		 7081 }
7082 }
7083 if (!ok)
24eab124
AM		 7084 {
7085#if INFER_ADDR_PREFIX
fc0763e6 7086 if (!i.mem_operands && !i.prefix[ADDR_PREFIX])
24eab124
AM		 7087 {
7088 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
7089 i.prefixes += 1;
b23bac36
AM		 7090 /* Change the size of any displacement too. At most one of
7091 Disp16 or Disp32 is set.
7092 FIXME. There doesn't seem to be any real need for separate
7093 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 7094 Removing them would probably clean up the code quite a lot. */
4eed87de 7095 if (flag_code != CODE_64BIT
40fb9820
L		 7096 && (i.types[this_operand].bitfield.disp16
7097 || i.types[this_operand].bitfield.disp32))
7098 i.types[this_operand]
c6fb90c8 7099 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 7100 fudged = 1;
24eab124
AM		 7101 goto tryprefix;
7102 }
eecb386c 7103 if (fudged)
fc0763e6
JB		 7104 as_bad (_("`%s' is not a valid %s expression"),
7105 operand_string,
7106 kind);
eecb386c 7107 else
c388dee8 7108#endif
fc0763e6 7109 as_bad (_("`%s' is not a valid %s-bit %s expression"),
eecb386c 7110 operand_string,
fc0763e6
JB		 7111 flag_code_names[i.prefix[ADDR_PREFIX]
7112 ? flag_code == CODE_32BIT
7113 ? CODE_16BIT
7114 : CODE_32BIT
7115 : flag_code],
7116 kind);
24eab124 7117 }
20f0a1fc 7118 return ok;
24eab124 7119}
252b5132 7120
fc0763e6 7121/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 7122 on error. */
252b5132 7123
252b5132 7124static int
a7619375 7125i386_att_operand (char *operand_string)
252b5132 7126{
af6bdddf
AM		 7127 const reg_entry *r;
7128 char *end_op;
24eab124 7129 char *op_string = operand_string;
252b5132 7130
24eab124 7131 if (is_space_char (*op_string))
252b5132
RH		 7132 ++op_string;
7133
24eab124 7134 /* We check for an absolute prefix (differentiating,
47926f60 7135 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 7136 if (*op_string == ABSOLUTE_PREFIX)
7137 {
7138 ++op_string;
7139 if (is_space_char (*op_string))
7140 ++op_string;
40fb9820 7141 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 7142 }
252b5132 7143
47926f60 7144 /* Check if operand is a register. */
4d1bb795 7145 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 7146 {
40fb9820
L		 7147 i386_operand_type temp;
7148
24eab124
AM		 7149 /* Check for a segment override by searching for ':' after a
7150 segment register. */
7151 op_string = end_op;
7152 if (is_space_char (*op_string))
7153 ++op_string;
40fb9820
L		 7154 if (*op_string == ':'
7155 && (r->reg_type.bitfield.sreg2
7156 || r->reg_type.bitfield.sreg3))
24eab124
AM		 7157 {
7158 switch (r->reg_num)
7159 {
7160 case 0:
7161 i.seg[i.mem_operands] = &es;
7162 break;
7163 case 1:
7164 i.seg[i.mem_operands] = &cs;
7165 break;
7166 case 2:
7167 i.seg[i.mem_operands] = &ss;
7168 break;
7169 case 3:
7170 i.seg[i.mem_operands] = &ds;
7171 break;
7172 case 4:
7173 i.seg[i.mem_operands] = &fs;
7174 break;
7175 case 5:
7176 i.seg[i.mem_operands] = &gs;
7177 break;
7178 }
252b5132 7179
24eab124 7180 /* Skip the ':' and whitespace. */
252b5132
RH		 7181 ++op_string;
7182 if (is_space_char (*op_string))
24eab124 7183 ++op_string;
252b5132 7184
24eab124
AM		 7185 if (!is_digit_char (*op_string)
7186 && !is_identifier_char (*op_string)
7187 && *op_string != '('
7188 && *op_string != ABSOLUTE_PREFIX)
7189 {
7190 as_bad (_("bad memory operand `%s'"), op_string);
7191 return 0;
7192 }
47926f60 7193 /* Handle case of %es:*foo. */
24eab124
AM		 7194 if (*op_string == ABSOLUTE_PREFIX)
7195 {
7196 ++op_string;
7197 if (is_space_char (*op_string))
7198 ++op_string;
40fb9820 7199 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 7200 }
7201 goto do_memory_reference;
7202 }
7203 if (*op_string)
7204 {
d0b47220 7205 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 7206 return 0;
7207 }
40fb9820
L		 7208 temp = r->reg_type;
7209 temp.bitfield.baseindex = 0;
c6fb90c8
L		 7210 i.types[this_operand] = operand_type_or (i.types[this_operand],
7211 temp);
7d5e4556 7212 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 7213 i.op[this_operand].regs = r;
24eab124
AM		 7214 i.reg_operands++;
7215 }
af6bdddf
AM		 7216 else if (*op_string == REGISTER_PREFIX)
7217 {
7218 as_bad (_("bad register name `%s'"), op_string);
7219 return 0;
7220 }
24eab124 7221 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 7222 {
24eab124 7223 ++op_string;
40fb9820 7224 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 7225 {
d0b47220 7226 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 7227 return 0;
7228 }
7229 if (!i386_immediate (op_string))
7230 return 0;
7231 }
7232 else if (is_digit_char (*op_string)
7233 || is_identifier_char (*op_string)
e5cb08ac 7234 || *op_string == '(')
24eab124 7235 {
47926f60 7236 /* This is a memory reference of some sort. */
af6bdddf 7237 char *base_string;
252b5132 7238
47926f60 7239 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 7240 char *displacement_string_start;
7241 char *displacement_string_end;
252b5132 7242
24eab124 7243 do_memory_reference:
24eab124 7244 if ((i.mem_operands == 1
40fb9820 7245 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 7246 || i.mem_operands == 2)
7247 {
7248 as_bad (_("too many memory references for `%s'"),
7249 current_templates->start->name);
7250 return 0;
7251 }
252b5132 7252
24eab124
AM		 7253 /* Check for base index form. We detect the base index form by
7254 looking for an ')' at the end of the operand, searching
7255 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7256 after the '('. */
af6bdddf 7257 base_string = op_string + strlen (op_string);
c3332e24 7258
af6bdddf
AM		 7259 --base_string;
7260 if (is_space_char (*base_string))
7261 --base_string;
252b5132 7262
47926f60 7263 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 7264 displacement_string_start = op_string;
7265 displacement_string_end = base_string + 1;
252b5132 7266
24eab124
AM		 7267 if (*base_string == ')')
7268 {
af6bdddf 7269 char *temp_string;
24eab124
AM		 7270 unsigned int parens_balanced = 1;
7271 /* We've already checked that the number of left & right ()'s are
47926f60 7272 equal, so this loop will not be infinite. */
24eab124
AM		 7273 do
7274 {
7275 base_string--;
7276 if (*base_string == ')')
7277 parens_balanced++;
7278 if (*base_string == '(')
7279 parens_balanced--;
7280 }
7281 while (parens_balanced);
c3332e24 7282
af6bdddf 7283 temp_string = base_string;
c3332e24 7284
24eab124 7285 /* Skip past '(' and whitespace. */
252b5132
RH		 7286 ++base_string;
7287 if (is_space_char (*base_string))
24eab124 7288 ++base_string;
252b5132 7289
af6bdddf 7290 if (*base_string == ','
4eed87de
AM		 7291 || ((i.base_reg = parse_register (base_string, &end_op))
7292 != NULL))
252b5132 7293 {
af6bdddf 7294 displacement_string_end = temp_string;
252b5132 7295
40fb9820 7296 i.types[this_operand].bitfield.baseindex = 1;
252b5132 7297
af6bdddf 7298 if (i.base_reg)
24eab124 7299 {
24eab124
AM		 7300 base_string = end_op;
7301 if (is_space_char (*base_string))
7302 ++base_string;
af6bdddf
AM		 7303 }
7304
7305 /* There may be an index reg or scale factor here. */
7306 if (*base_string == ',')
7307 {
7308 ++base_string;
7309 if (is_space_char (*base_string))
7310 ++base_string;
7311
4eed87de
AM		 7312 if ((i.index_reg = parse_register (base_string, &end_op))
7313 != NULL)
24eab124 7314 {
af6bdddf 7315 base_string = end_op;
24eab124
AM		 7316 if (is_space_char (*base_string))
7317 ++base_string;
af6bdddf
AM		 7318 if (*base_string == ',')
7319 {
7320 ++base_string;
7321 if (is_space_char (*base_string))
7322 ++base_string;
7323 }
e5cb08ac 7324 else if (*base_string != ')')
af6bdddf 7325 {
4eed87de
AM		 7326 as_bad (_("expecting `,' or `)' "
7327 "after index register in `%s'"),
af6bdddf
AM		 7328 operand_string);
7329 return 0;
7330 }
24eab124 7331 }
af6bdddf 7332 else if (*base_string == REGISTER_PREFIX)
24eab124 7333 {
af6bdddf 7334 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 7335 return 0;
7336 }
252b5132 7337
47926f60 7338 /* Check for scale factor. */
551c1ca1 7339 if (*base_string != ')')
af6bdddf 7340 {
551c1ca1
AM		 7341 char *end_scale = i386_scale (base_string);
7342
7343 if (!end_scale)
af6bdddf 7344 return 0;
24eab124 7345
551c1ca1 7346 base_string = end_scale;
af6bdddf
AM		 7347 if (is_space_char (*base_string))
7348 ++base_string;
7349 if (*base_string != ')')
7350 {
4eed87de
AM		 7351 as_bad (_("expecting `)' "
7352 "after scale factor in `%s'"),
af6bdddf
AM		 7353 operand_string);
7354 return 0;
7355 }
7356 }
7357 else if (!i.index_reg)
24eab124 7358 {
4eed87de
AM		 7359 as_bad (_("expecting index register or scale factor "
7360 "after `,'; got '%c'"),
af6bdddf 7361 *base_string);
24eab124
AM		 7362 return 0;
7363 }
7364 }
af6bdddf 7365 else if (*base_string != ')')
24eab124 7366 {
4eed87de
AM		 7367 as_bad (_("expecting `,' or `)' "
7368 "after base register in `%s'"),
af6bdddf 7369 operand_string);
24eab124
AM		 7370 return 0;
7371 }
c3332e24 7372 }
af6bdddf 7373 else if (*base_string == REGISTER_PREFIX)
c3332e24 7374 {
af6bdddf 7375 as_bad (_("bad register name `%s'"), base_string);
24eab124 7376 return 0;
c3332e24 7377 }
24eab124
AM		 7378 }
7379
7380 /* If there's an expression beginning the operand, parse it,
7381 assuming displacement_string_start and
7382 displacement_string_end are meaningful. */
7383 if (displacement_string_start != displacement_string_end)
7384 {
7385 if (!i386_displacement (displacement_string_start,
7386 displacement_string_end))
7387 return 0;
7388 }
7389
7390 /* Special case for (%dx) while doing input/output op. */
7391 if (i.base_reg
0dfbf9d7
L		 7392 && operand_type_equal (&i.base_reg->reg_type,
7393 &reg16_inoutportreg)
24eab124
AM		 7394 && i.index_reg == 0
7395 && i.log2_scale_factor == 0
7396 && i.seg[i.mem_operands] == 0
40fb9820 7397 && !operand_type_check (i.types[this_operand], disp))
24eab124 7398 {
65da13b5 7399 i.types[this_operand] = inoutportreg;
24eab124
AM		 7400 return 1;
7401 }
7402
eecb386c
AM		 7403 if (i386_index_check (operand_string) == 0)
7404 return 0;
5c07affc 7405 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 7406 i.mem_operands++;
7407 }
7408 else
ce8a8b2f
AM		 7409 {
7410 /* It's not a memory operand; argh! */
24eab124
AM		 7411 as_bad (_("invalid char %s beginning operand %d `%s'"),
7412 output_invalid (*op_string),
7413 this_operand + 1,
7414 op_string);
7415 return 0;
7416 }
47926f60 7417 return 1; /* Normal return. */
252b5132
RH		 7418}
7419\f
ee7fcc42
AM		 7420/* md_estimate_size_before_relax()
7421
7422 Called just before relax() for rs_machine_dependent frags. The x86
7423 assembler uses these frags to handle variable size jump
7424 instructions.
7425
7426 Any symbol that is now undefined will not become defined.
7427 Return the correct fr_subtype in the frag.
7428 Return the initial "guess for variable size of frag" to caller.
7429 The guess is actually the growth beyond the fixed part. Whatever
7430 we do to grow the fixed or variable part contributes to our
7431 returned value. */
7432
252b5132
RH		 7433int
7434md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 7435 fragS *fragP;
7436 segT segment;
252b5132 7437{
252b5132 7438 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 7439 check for un-relaxable symbols. On an ELF system, we can't relax
7440 an externally visible symbol, because it may be overridden by a
7441 shared library. */
7442 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 7443#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7444 || (IS_ELF
31312f95 7445 && (S_IS_EXTERNAL (fragP->fr_symbol)
915bcca5
L		 7446 || S_IS_WEAK (fragP->fr_symbol)
7447 || ((symbol_get_bfdsym (fragP->fr_symbol)->flags
7448 & BSF_GNU_INDIRECT_FUNCTION))))
fbeb56a4
DK		 7449#endif
7450#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 7451 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 7452 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 7453#endif
7454 )
252b5132 7455 {
b98ef147
AM		 7456 /* Symbol is undefined in this segment, or we need to keep a
7457 reloc so that weak symbols can be overridden. */
7458 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 7459 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 7460 unsigned char *opcode;
7461 int old_fr_fix;
f6af82bd 7462
ee7fcc42 7463 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 7464 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 7465 else if (size == 2)
f6af82bd
AM		 7466 reloc_type = BFD_RELOC_16_PCREL;
7467 else
7468 reloc_type = BFD_RELOC_32_PCREL;
252b5132 7469
ee7fcc42
AM		 7470 old_fr_fix = fragP->fr_fix;
7471 opcode = (unsigned char *) fragP->fr_opcode;
7472
fddf5b5b 7473 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 7474 {
fddf5b5b
AM		 7475 case UNCOND_JUMP:
7476 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 7477 opcode[0] = 0xe9;
252b5132 7478 fragP->fr_fix += size;
062cd5e7
AS		 7479 fix_new (fragP, old_fr_fix, size,
7480 fragP->fr_symbol,
7481 fragP->fr_offset, 1,
7482 reloc_type);
252b5132
RH		 7483 break;
7484
fddf5b5b 7485 case COND_JUMP86:
412167cb
AM		 7486 if (size == 2
7487 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 7488 {
7489 /* Negate the condition, and branch past an
7490 unconditional jump. */
7491 opcode[0] ^= 1;
7492 opcode[1] = 3;
7493 /* Insert an unconditional jump. */
7494 opcode[2] = 0xe9;
7495 /* We added two extra opcode bytes, and have a two byte
7496 offset. */
7497 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 7498 fix_new (fragP, old_fr_fix + 2, 2,
7499 fragP->fr_symbol,
7500 fragP->fr_offset, 1,
7501 reloc_type);
fddf5b5b
AM		 7502 break;
7503 }
7504 /* Fall through. */
7505
7506 case COND_JUMP:
412167cb
AM		 7507 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
7508 {
3e02c1cc
AM		 7509 fixS *fixP;
7510
412167cb 7511 fragP->fr_fix += 1;
3e02c1cc
AM		 7512 fixP = fix_new (fragP, old_fr_fix, 1,
7513 fragP->fr_symbol,
7514 fragP->fr_offset, 1,
7515 BFD_RELOC_8_PCREL);
7516 fixP->fx_signed = 1;
412167cb
AM		 7517 break;
7518 }
93c2a809 7519
24eab124 7520 /* This changes the byte-displacement jump 0x7N
fddf5b5b 7521 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 7522 opcode[1] = opcode[0] + 0x10;
f6af82bd 7523 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 7524 /* We've added an opcode byte. */
7525 fragP->fr_fix += 1 + size;
062cd5e7
AS		 7526 fix_new (fragP, old_fr_fix + 1, size,
7527 fragP->fr_symbol,
7528 fragP->fr_offset, 1,
7529 reloc_type);
252b5132 7530 break;
fddf5b5b
AM		 7531
7532 default:
7533 BAD_CASE (fragP->fr_subtype);
7534 break;
252b5132
RH		 7535 }
7536 frag_wane (fragP);
ee7fcc42 7537 return fragP->fr_fix - old_fr_fix;
252b5132 7538 }
93c2a809 7539
93c2a809
AM		 7540 /* Guess size depending on current relax state. Initially the relax
7541 state will correspond to a short jump and we return 1, because
7542 the variable part of the frag (the branch offset) is one byte
7543 long. However, we can relax a section more than once and in that
7544 case we must either set fr_subtype back to the unrelaxed state,
7545 or return the value for the appropriate branch. */
7546 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 7547}
7548
47926f60
KH		 7549/* Called after relax() is finished.
7550
7551 In: Address of frag.
7552 fr_type == rs_machine_dependent.
7553 fr_subtype is what the address relaxed to.
7554
7555 Out: Any fixSs and constants are set up.
7556 Caller will turn frag into a ".space 0". */
7557
252b5132
RH		 7558void
7559md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 7560 bfd *abfd ATTRIBUTE_UNUSED;
7561 segT sec ATTRIBUTE_UNUSED;
29b0f896 7562 fragS *fragP;
252b5132 7563{
29b0f896 7564 unsigned char *opcode;
252b5132 7565 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 7566 offsetT target_address;
7567 offsetT opcode_address;
252b5132 7568 unsigned int extension = 0;
847f7ad4 7569 offsetT displacement_from_opcode_start;
252b5132
RH		 7570
7571 opcode = (unsigned char *) fragP->fr_opcode;
7572
47926f60 7573 /* Address we want to reach in file space. */
252b5132 7574 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 7575
47926f60 7576 /* Address opcode resides at in file space. */
252b5132
RH		 7577 opcode_address = fragP->fr_address + fragP->fr_fix;
7578
47926f60 7579 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 7580 displacement_from_opcode_start = target_address - opcode_address;
7581
fddf5b5b 7582 if ((fragP->fr_subtype & BIG) == 0)
252b5132 7583 {
47926f60
KH		 7584 /* Don't have to change opcode. */
7585 extension = 1; /* 1 opcode + 1 displacement */
252b5132 7586 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 7587 }
7588 else
7589 {
7590 if (no_cond_jump_promotion
7591 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 7592 as_warn_where (fragP->fr_file, fragP->fr_line,
7593 _("long jump required"));
252b5132 7594
fddf5b5b
AM		 7595 switch (fragP->fr_subtype)
7596 {
7597 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
7598 extension = 4; /* 1 opcode + 4 displacement */
7599 opcode[0] = 0xe9;
7600 where_to_put_displacement = &opcode[1];
7601 break;
252b5132 7602
fddf5b5b
AM		 7603 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
7604 extension = 2; /* 1 opcode + 2 displacement */
7605 opcode[0] = 0xe9;
7606 where_to_put_displacement = &opcode[1];
7607 break;
252b5132 7608
fddf5b5b
AM		 7609 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
7610 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
7611 extension = 5; /* 2 opcode + 4 displacement */
7612 opcode[1] = opcode[0] + 0x10;
7613 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7614 where_to_put_displacement = &opcode[2];
7615 break;
252b5132 7616
fddf5b5b
AM		 7617 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
7618 extension = 3; /* 2 opcode + 2 displacement */
7619 opcode[1] = opcode[0] + 0x10;
7620 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7621 where_to_put_displacement = &opcode[2];
7622 break;
252b5132 7623
fddf5b5b
AM		 7624 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
7625 extension = 4;
7626 opcode[0] ^= 1;
7627 opcode[1] = 3;
7628 opcode[2] = 0xe9;
7629 where_to_put_displacement = &opcode[3];
7630 break;
7631
7632 default:
7633 BAD_CASE (fragP->fr_subtype);
7634 break;
7635 }
252b5132 7636 }
fddf5b5b 7637
7b81dfbb
AJ		 7638 /* If size if less then four we are sure that the operand fits,
7639 but if it's 4, then it could be that the displacement is larger
7640 then -/+ 2GB. */
7641 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
7642 && object_64bit
7643 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 7644 + ((addressT) 1 << 31))
7645 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 7646 {
7647 as_bad_where (fragP->fr_file, fragP->fr_line,
7648 _("jump target out of range"));
7649 /* Make us emit 0. */
7650 displacement_from_opcode_start = extension;
7651 }
47926f60 7652 /* Now put displacement after opcode. */
252b5132
RH		 7653 md_number_to_chars ((char *) where_to_put_displacement,
7654 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 7655 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 7656 fragP->fr_fix += extension;
7657}
7658\f
252b5132
RH		 7659/* Apply a fixup (fixS) to segment data, once it has been determined
7660 by our caller that we have all the info we need to fix it up.
7661
7662 On the 386, immediates, displacements, and data pointers are all in
7663 the same (little-endian) format, so we don't need to care about which
7664 we are handling. */
7665
94f592af 7666void
55cf6793 7667md_apply_fix (fixP, valP, seg)
47926f60
KH		 7668 /* The fix we're to put in. */
7669 fixS *fixP;
47926f60 7670 /* Pointer to the value of the bits. */
c6682705 7671 valueT *valP;
47926f60
KH		 7672 /* Segment fix is from. */
7673 segT seg ATTRIBUTE_UNUSED;
252b5132 7674{
94f592af 7675 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 7676 valueT value = *valP;
252b5132 7677
f86103b7 7678#if !defined (TE_Mach)
93382f6d
AM		 7679 if (fixP->fx_pcrel)
7680 {
7681 switch (fixP->fx_r_type)
7682 {
5865bb77
ILT		 7683 default:
7684 break;
7685
d6ab8113
JB		 7686 case BFD_RELOC_64:
7687 fixP->fx_r_type = BFD_RELOC_64_PCREL;
7688 break;
93382f6d 7689 case BFD_RELOC_32:
ae8887b5 7690 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 7691 fixP->fx_r_type = BFD_RELOC_32_PCREL;
7692 break;
7693 case BFD_RELOC_16:
7694 fixP->fx_r_type = BFD_RELOC_16_PCREL;
7695 break;
7696 case BFD_RELOC_8:
7697 fixP->fx_r_type = BFD_RELOC_8_PCREL;
7698 break;
7699 }
7700 }
252b5132 7701
a161fe53 7702 if (fixP->fx_addsy != NULL
31312f95 7703 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 7704 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 7705 || fixP->fx_r_type == BFD_RELOC_16_PCREL
7706 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
7707 && !use_rela_relocations)
252b5132 7708 {
31312f95
AM		 7709 /* This is a hack. There should be a better way to handle this.
7710 This covers for the fact that bfd_install_relocation will
7711 subtract the current location (for partial_inplace, PC relative
7712 relocations); see more below. */
252b5132 7713#ifndef OBJ_AOUT
718ddfc0 7714 if (IS_ELF
252b5132
RH		 7715#ifdef TE_PE
7716 || OUTPUT_FLAVOR == bfd_target_coff_flavour
7717#endif
7718 )
7719 value += fixP->fx_where + fixP->fx_frag->fr_address;
7720#endif
7721#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7722 if (IS_ELF)
252b5132 7723 {
6539b54b 7724 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 7725
6539b54b 7726 if ((sym_seg == seg
2f66722d 7727 || (symbol_section_p (fixP->fx_addsy)
6539b54b 7728 && sym_seg != absolute_section))
af65af87 7729 && !generic_force_reloc (fixP))
2f66722d
AM		 7730 {
7731 /* Yes, we add the values in twice. This is because
6539b54b
AM		 7732 bfd_install_relocation subtracts them out again. I think
7733 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 7734 it. FIXME. */
7735 value += fixP->fx_where + fixP->fx_frag->fr_address;
7736 }
252b5132
RH		 7737 }
7738#endif
7739#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 7740 /* For some reason, the PE format does not store a
7741 section address offset for a PC relative symbol. */
7742 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 7743 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 7744 value += md_pcrel_from (fixP);
7745#endif
7746 }
fbeb56a4
DK		 7747#if defined (OBJ_COFF) && defined (TE_PE)
7748 if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
7749 {
7750 value -= S_GET_VALUE (fixP->fx_addsy);
7751 }
7752#endif
252b5132
RH		 7753
7754 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 7755 and we must not disappoint it. */
252b5132 7756#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7757 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 7758 switch (fixP->fx_r_type)
7759 {
7760 case BFD_RELOC_386_PLT32:
3e73aa7c 7761 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 7762 /* Make the jump instruction point to the address of the operand. At
7763 runtime we merely add the offset to the actual PLT entry. */
7764 value = -4;
7765 break;
31312f95 7766
13ae64f3
JJ		 7767 case BFD_RELOC_386_TLS_GD:
7768 case BFD_RELOC_386_TLS_LDM:
13ae64f3 7769 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 7770 case BFD_RELOC_386_TLS_IE:
7771 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 7772 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 7773 case BFD_RELOC_X86_64_TLSGD:
7774 case BFD_RELOC_X86_64_TLSLD:
7775 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 7776 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 7777 value = 0; /* Fully resolved at runtime. No addend. */
7778 /* Fallthrough */
7779 case BFD_RELOC_386_TLS_LE:
7780 case BFD_RELOC_386_TLS_LDO_32:
7781 case BFD_RELOC_386_TLS_LE_32:
7782 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 7783 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 7784 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 7785 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 7786 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7787 break;
7788
67a4f2b7
AO		 7789 case BFD_RELOC_386_TLS_DESC_CALL:
7790 case BFD_RELOC_X86_64_TLSDESC_CALL:
7791 value = 0; /* Fully resolved at runtime. No addend. */
7792 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7793 fixP->fx_done = 0;
7794 return;
7795
00f7efb6
JJ		 7796 case BFD_RELOC_386_GOT32:
7797 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 7798 value = 0; /* Fully resolved at runtime. No addend. */
7799 break;
47926f60
KH		 7800
7801 case BFD_RELOC_VTABLE_INHERIT:
7802 case BFD_RELOC_VTABLE_ENTRY:
7803 fixP->fx_done = 0;
94f592af 7804 return;
47926f60
KH		 7805
7806 default:
7807 break;
7808 }
7809#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 7810 *valP = value;
f86103b7 7811#endif /* !defined (TE_Mach) */
3e73aa7c 7812
3e73aa7c 7813 /* Are we finished with this relocation now? */
c6682705 7814 if (fixP->fx_addsy == NULL)
3e73aa7c 7815 fixP->fx_done = 1;
fbeb56a4
DK		 7816#if defined (OBJ_COFF) && defined (TE_PE)
7817 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
7818 {
7819 fixP->fx_done = 0;
7820 /* Remember value for tc_gen_reloc. */
7821 fixP->fx_addnumber = value;
7822 /* Clear out the frag for now. */
7823 value = 0;
7824 }
7825#endif
3e73aa7c
JH		 7826 else if (use_rela_relocations)
7827 {
7828 fixP->fx_no_overflow = 1;
062cd5e7
AS		 7829 /* Remember value for tc_gen_reloc. */
7830 fixP->fx_addnumber = value;
3e73aa7c
JH		 7831 value = 0;
7832 }
f86103b7 7833
94f592af 7834 md_number_to_chars (p, value, fixP->fx_size);
252b5132 7835}
252b5132 7836\f
252b5132 7837char *
499ac353 7838md_atof (int type, char *litP, int *sizeP)
252b5132 7839{
499ac353
NC		 7840 /* This outputs the LITTLENUMs in REVERSE order;
7841 in accord with the bigendian 386. */
7842 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 7843}
7844\f
2d545b82 7845static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 7846
252b5132 7847static char *
e3bb37b5 7848output_invalid (int c)
252b5132 7849{
3882b010 7850 if (ISPRINT (c))
f9f21a03
L		 7851 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
7852 "'%c'", c);
252b5132 7853 else
f9f21a03 7854 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 7855 "(0x%x)", (unsigned char) c);
252b5132
RH		 7856 return output_invalid_buf;
7857}
7858
af6bdddf 7859/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 7860
7861static const reg_entry *
4d1bb795 7862parse_real_register (char *reg_string, char **end_op)
252b5132 7863{
af6bdddf
AM		 7864 char *s = reg_string;
7865 char *p;
252b5132
RH		 7866 char reg_name_given[MAX_REG_NAME_SIZE + 1];
7867 const reg_entry *r;
7868
7869 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7870 if (*s == REGISTER_PREFIX)
7871 ++s;
7872
7873 if (is_space_char (*s))
7874 ++s;
7875
7876 p = reg_name_given;
af6bdddf 7877 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 7878 {
7879 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 7880 return (const reg_entry *) NULL;
7881 s++;
252b5132
RH		 7882 }
7883
6588847e
DN		 7884 /* For naked regs, make sure that we are not dealing with an identifier.
7885 This prevents confusing an identifier like `eax_var' with register
7886 `eax'. */
7887 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
7888 return (const reg_entry *) NULL;
7889
af6bdddf 7890 *end_op = s;
252b5132
RH		 7891
7892 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
7893
5f47d35b 7894 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 7895 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 7896 {
5f47d35b
AM		 7897 if (is_space_char (*s))
7898 ++s;
7899 if (*s == '(')
7900 {
af6bdddf 7901 ++s;
5f47d35b
AM		 7902 if (is_space_char (*s))
7903 ++s;
7904 if (*s >= '0' && *s <= '7')
7905 {
db557034 7906 int fpr = *s - '0';
af6bdddf 7907 ++s;
5f47d35b
AM		 7908 if (is_space_char (*s))
7909 ++s;
7910 if (*s == ')')
7911 {
7912 *end_op = s + 1;
1e9cc1c2 7913 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 7914 know (r);
7915 return r + fpr;
5f47d35b 7916 }
5f47d35b 7917 }
47926f60 7918 /* We have "%st(" then garbage. */
5f47d35b
AM		 7919 return (const reg_entry *) NULL;
7920 }
7921 }
7922
a60de03c
JB		 7923 if (r == NULL || allow_pseudo_reg)
7924 return r;
7925
0dfbf9d7 7926 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 7927 return (const reg_entry *) NULL;
7928
192dc9c6
JB		 7929 if ((r->reg_type.bitfield.reg32
7930 || r->reg_type.bitfield.sreg3
7931 || r->reg_type.bitfield.control
7932 || r->reg_type.bitfield.debug
7933 || r->reg_type.bitfield.test)
7934 && !cpu_arch_flags.bitfield.cpui386)
7935 return (const reg_entry *) NULL;
7936
309d3373
JB		 7937 if (r->reg_type.bitfield.floatreg
7938 && !cpu_arch_flags.bitfield.cpu8087
7939 && !cpu_arch_flags.bitfield.cpu287
7940 && !cpu_arch_flags.bitfield.cpu387)
7941 return (const reg_entry *) NULL;
7942
192dc9c6
JB		 7943 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
7944 return (const reg_entry *) NULL;
7945
7946 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
7947 return (const reg_entry *) NULL;
7948
40f12533
L		 7949 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
7950 return (const reg_entry *) NULL;
7951
db51cc60 7952 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 7953 if (!allow_index_reg
db51cc60
L		 7954 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
7955 return (const reg_entry *) NULL;
7956
a60de03c
JB		 7957 if (((r->reg_flags & (RegRex64 | RegRex))
7958 || r->reg_type.bitfield.reg64)
40fb9820 7959 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 7960 || !operand_type_equal (&r->reg_type, &control))
1ae00879 7961 && flag_code != CODE_64BIT)
20f0a1fc 7962 return (const reg_entry *) NULL;
1ae00879 7963
b7240065
JB		 7964 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
7965 return (const reg_entry *) NULL;
7966
252b5132
RH		 7967 return r;
7968}
4d1bb795
JB		 7969
7970/* REG_STRING starts *before* REGISTER_PREFIX. */
7971
7972static const reg_entry *
7973parse_register (char *reg_string, char **end_op)
7974{
7975 const reg_entry *r;
7976
7977 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
7978 r = parse_real_register (reg_string, end_op);
7979 else
7980 r = NULL;
7981 if (!r)
7982 {
7983 char *save = input_line_pointer;
7984 char c;
7985 symbolS *symbolP;
7986
7987 input_line_pointer = reg_string;
7988 c = get_symbol_end ();
7989 symbolP = symbol_find (reg_string);
7990 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
7991 {
7992 const expressionS *e = symbol_get_value_expression (symbolP);
7993
0398aac5 7994 know (e->X_op == O_register);
4eed87de 7995 know (e->X_add_number >= 0
c3fe08fa 7996 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 7997 r = i386_regtab + e->X_add_number;
7998 *end_op = input_line_pointer;
7999 }
8000 *input_line_pointer = c;
8001 input_line_pointer = save;
8002 }
8003 return r;
8004}
8005
8006int
8007i386_parse_name (char *name, expressionS *e, char *nextcharP)
8008{
8009 const reg_entry *r;
8010 char *end = input_line_pointer;
8011
8012 *end = *nextcharP;
8013 r = parse_register (name, &input_line_pointer);
8014 if (r && end <= input_line_pointer)
8015 {
8016 *nextcharP = *input_line_pointer;
8017 *input_line_pointer = 0;
8018 e->X_op = O_register;
8019 e->X_add_number = r - i386_regtab;
8020 return 1;
8021 }
8022 input_line_pointer = end;
8023 *end = 0;
ee86248c 8024 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 8025}
8026
8027void
8028md_operand (expressionS *e)
8029{
ee86248c
JB		 8030 char *end;
8031 const reg_entry *r;
4d1bb795 8032
ee86248c
JB		 8033 switch (*input_line_pointer)
8034 {
8035 case REGISTER_PREFIX:
8036 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 8037 if (r)
8038 {
8039 e->X_op = O_register;
8040 e->X_add_number = r - i386_regtab;
8041 input_line_pointer = end;
8042 }
ee86248c
JB		 8043 break;
8044
8045 case '[':
9c2799c2 8046 gas_assert (intel_syntax);
ee86248c
JB		 8047 end = input_line_pointer++;
8048 expression (e);
8049 if (*input_line_pointer == ']')
8050 {
8051 ++input_line_pointer;
8052 e->X_op_symbol = make_expr_symbol (e);
8053 e->X_add_symbol = NULL;
8054 e->X_add_number = 0;
8055 e->X_op = O_index;
8056 }
8057 else
8058 {
8059 e->X_op = O_absent;
8060 input_line_pointer = end;
8061 }
8062 break;
4d1bb795
JB		 8063 }
8064}
8065
252b5132 8066\f
4cc782b5 8067#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 8068const char *md_shortopts = "kVQ:sqn";
252b5132 8069#else
12b55ccc 8070const char *md_shortopts = "qn";
252b5132 8071#endif
6e0b89ee 8072
3e73aa7c 8073#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 8074#define OPTION_64 (OPTION_MD_BASE + 1)
8075#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 8076#define OPTION_MARCH (OPTION_MD_BASE + 3)
8077#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 8078#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
8079#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
8080#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
8081#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
8082#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 8083#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 8084#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
40a9833c 8085#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 12)
b3b91714 8086
99ad8390
NC		 8087struct option md_longopts[] =
8088{
3e73aa7c 8089 {"32", no_argument, NULL, OPTION_32},
321098a5
L		 8090#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8091 || defined (TE_PE) || defined (TE_PEP))
3e73aa7c 8092 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 8093#endif
b3b91714 8094 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 8095 {"march", required_argument, NULL, OPTION_MARCH},
8096 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 8097 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
8098 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
8099 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
8100 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
8101 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 8102 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 8103 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
539f890d 8104 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
252b5132
RH		 8105 {NULL, no_argument, NULL, 0}
8106};
8107size_t md_longopts_size = sizeof (md_longopts);
8108
8109int
9103f4f4 8110md_parse_option (int c, char *arg)
252b5132 8111{
91d6fa6a 8112 unsigned int j;
6305a203 8113 char *arch, *next;
9103f4f4 8114
252b5132
RH		 8115 switch (c)
8116 {
12b55ccc
L		 8117 case 'n':
8118 optimize_align_code = 0;
8119 break;
8120
a38cf1db
AM		 8121 case 'q':
8122 quiet_warnings = 1;
252b5132
RH		 8123 break;
8124
8125#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 8126 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
8127 should be emitted or not. FIXME: Not implemented. */
8128 case 'Q':
252b5132
RH		 8129 break;
8130
8131 /* -V: SVR4 argument to print version ID. */
8132 case 'V':
8133 print_version_id ();
8134 break;
8135
a38cf1db
AM		 8136 /* -k: Ignore for FreeBSD compatibility. */
8137 case 'k':
252b5132 8138 break;
4cc782b5
ILT		 8139
8140 case 's':
8141 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 8142 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 8143 break;
99ad8390 8144#endif
321098a5
L		 8145#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8146 || defined (TE_PE) || defined (TE_PEP))
3e73aa7c
JH		 8147 case OPTION_64:
8148 {
8149 const char **list, **l;
8150
3e73aa7c
JH		 8151 list = bfd_target_list ();
8152 for (l = list; *l != NULL; l++)
8620418b 8153 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 8154 || strcmp (*l, "coff-x86-64") == 0
8155 || strcmp (*l, "pe-x86-64") == 0
8156 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 8157 {
8158 default_arch = "x86_64";
8159 break;
8160 }
3e73aa7c 8161 if (*l == NULL)
6e0b89ee 8162 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 8163 free (list);
8164 }
8165 break;
8166#endif
252b5132 8167
6e0b89ee
AM		 8168 case OPTION_32:
8169 default_arch = "i386";
8170 break;
8171
b3b91714
AM		 8172 case OPTION_DIVIDE:
8173#ifdef SVR4_COMMENT_CHARS
8174 {
8175 char *n, *t;
8176 const char *s;
8177
8178 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
8179 t = n;
8180 for (s = i386_comment_chars; *s != '\0'; s++)
8181 if (*s != '/')
8182 *t++ = *s;
8183 *t = '\0';
8184 i386_comment_chars = n;
8185 }
8186#endif
8187 break;
8188
9103f4f4 8189 case OPTION_MARCH:
6305a203
L		 8190 arch = xstrdup (arg);
8191 do
9103f4f4 8192 {
6305a203
L		 8193 if (*arch == '.')
8194 as_fatal (_("Invalid -march= option: `%s'"), arg);
8195 next = strchr (arch, '+');
8196 if (next)
8197 *next++ = '\0';
91d6fa6a 8198 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 8199 {
91d6fa6a 8200 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 8201 {
6305a203 8202 /* Processor. */
1ded5609
JB		 8203 if (! cpu_arch[j].flags.bitfield.cpui386)
8204 continue;
8205
91d6fa6a 8206 cpu_arch_name = cpu_arch[j].name;
6305a203 8207 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 8208 cpu_arch_flags = cpu_arch[j].flags;
8209 cpu_arch_isa = cpu_arch[j].type;
8210 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 8211 if (!cpu_arch_tune_set)
8212 {
8213 cpu_arch_tune = cpu_arch_isa;
8214 cpu_arch_tune_flags = cpu_arch_isa_flags;
8215 }
8216 break;
8217 }
91d6fa6a
NC		 8218 else if (*cpu_arch [j].name == '.'
8219 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203
L		 8220 {
8221 /* ISA entension. */
8222 i386_cpu_flags flags;
309d3373 8223
49021df2 8224 if (!cpu_arch[j].negated)
309d3373 8225 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 8226 cpu_arch[j].flags);
309d3373
JB		 8227 else
8228 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 8229 cpu_arch[j].flags);
0dfbf9d7 8230 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 8231 {
8232 if (cpu_sub_arch_name)
8233 {
8234 char *name = cpu_sub_arch_name;
8235 cpu_sub_arch_name = concat (name,
91d6fa6a 8236 cpu_arch[j].name,
1bf57e9f 8237 (const char *) NULL);
6305a203
L		 8238 free (name);
8239 }
8240 else
91d6fa6a 8241 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203
L		 8242 cpu_arch_flags = flags;
8243 }
8244 break;
ccc9c027 8245 }
9103f4f4 8246 }
6305a203 8247
91d6fa6a 8248 if (j >= ARRAY_SIZE (cpu_arch))
6305a203
L		 8249 as_fatal (_("Invalid -march= option: `%s'"), arg);
8250
8251 arch = next;
9103f4f4 8252 }
6305a203 8253 while (next != NULL );
9103f4f4
L		 8254 break;
8255
8256 case OPTION_MTUNE:
8257 if (*arg == '.')
8258 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
91d6fa6a 8259 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 8260 {
91d6fa6a 8261 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 8262 {
ccc9c027 8263 cpu_arch_tune_set = 1;
91d6fa6a
NC		 8264 cpu_arch_tune = cpu_arch [j].type;
8265 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 8266 break;
8267 }
8268 }
91d6fa6a 8269 if (j >= ARRAY_SIZE (cpu_arch))
9103f4f4
L		 8270 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
8271 break;
8272
1efbbeb4
L		 8273 case OPTION_MMNEMONIC:
8274 if (strcasecmp (arg, "att") == 0)
8275 intel_mnemonic = 0;
8276 else if (strcasecmp (arg, "intel") == 0)
8277 intel_mnemonic = 1;
8278 else
8279 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
8280 break;
8281
8282 case OPTION_MSYNTAX:
8283 if (strcasecmp (arg, "att") == 0)
8284 intel_syntax = 0;
8285 else if (strcasecmp (arg, "intel") == 0)
8286 intel_syntax = 1;
8287 else
8288 as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
8289 break;
8290
8291 case OPTION_MINDEX_REG:
8292 allow_index_reg = 1;
8293 break;
8294
8295 case OPTION_MNAKED_REG:
8296 allow_naked_reg = 1;
8297 break;
8298
8299 case OPTION_MOLD_GCC:
8300 old_gcc = 1;
1efbbeb4
L		 8301 break;
8302
c0f3af97
L		 8303 case OPTION_MSSE2AVX:
8304 sse2avx = 1;
8305 break;
8306
daf50ae7
L		 8307 case OPTION_MSSE_CHECK:
8308 if (strcasecmp (arg, "error") == 0)
8309 sse_check = sse_check_error;
8310 else if (strcasecmp (arg, "warning") == 0)
8311 sse_check = sse_check_warning;
8312 else if (strcasecmp (arg, "none") == 0)
8313 sse_check = sse_check_none;
8314 else
8315 as_fatal (_("Invalid -msse-check= option: `%s'"), arg);
8316 break;
8317
539f890d
L		 8318 case OPTION_MAVXSCALAR:
8319 if (strcasecmp (arg, "128") == 0)
8320 avxscalar = vex128;
8321 else if (strcasecmp (arg, "256") == 0)
8322 avxscalar = vex256;
8323 else
8324 as_fatal (_("Invalid -mavxscalar= option: `%s'"), arg);
8325 break;
8326
252b5132
RH		 8327 default:
8328 return 0;
8329 }
8330 return 1;
8331}
8332
8a2c8fef
L		 8333#define MESSAGE_TEMPLATE \
8334" "
8335
8336static void
1ded5609 8337show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 8338{
8339 static char message[] = MESSAGE_TEMPLATE;
8340 char *start = message + 27;
8341 char *p;
8342 int size = sizeof (MESSAGE_TEMPLATE);
8343 int left;
8344 const char *name;
8345 int len;
8346 unsigned int j;
8347
8348 p = start;
8349 left = size - (start - message);
8350 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
8351 {
8352 /* Should it be skipped? */
8353 if (cpu_arch [j].skip)
8354 continue;
8355
8356 name = cpu_arch [j].name;
8357 len = cpu_arch [j].len;
8358 if (*name == '.')
8359 {
8360 /* It is an extension. Skip if we aren't asked to show it. */
8361 if (ext)
8362 {
8363 name++;
8364 len--;
8365 }
8366 else
8367 continue;
8368 }
8369 else if (ext)
8370 {
8371 /* It is an processor. Skip if we show only extension. */
8372 continue;
8373 }
1ded5609
JB		 8374 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
8375 {
8376 /* It is an impossible processor - skip. */
8377 continue;
8378 }
8a2c8fef
L		 8379
8380 /* Reserve 2 spaces for ", " or ",\0" */
8381 left -= len + 2;
8382
8383 /* Check if there is any room. */
8384 if (left >= 0)
8385 {
8386 if (p != start)
8387 {
8388 *p++ = ',';
8389 *p++ = ' ';
8390 }
8391 p = mempcpy (p, name, len);
8392 }
8393 else
8394 {
8395 /* Output the current message now and start a new one. */
8396 *p++ = ',';
8397 *p = '\0';
8398 fprintf (stream, "%s\n", message);
8399 p = start;
8400 left = size - (start - message) - len - 2;
8401
8402 gas_assert (left >= 0);
8403
8404 p = mempcpy (p, name, len);
8405 }
8406 }
8407
8408 *p = '\0';
8409 fprintf (stream, "%s\n", message);
8410}
8411
252b5132 8412void
8a2c8fef 8413md_show_usage (FILE *stream)
252b5132 8414{
4cc782b5
ILT		 8415#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8416 fprintf (stream, _("\
a38cf1db
AM		 8417 -Q ignored\n\
8418 -V print assembler version number\n\
b3b91714
AM		 8419 -k ignored\n"));
8420#endif
8421 fprintf (stream, _("\
12b55ccc 8422 -n Do not optimize code alignment\n\
b3b91714
AM		 8423 -q quieten some warnings\n"));
8424#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8425 fprintf (stream, _("\
a38cf1db 8426 -s ignored\n"));
b3b91714 8427#endif
321098a5
L		 8428#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8429 || defined (TE_PE) || defined (TE_PEP))
751d281c
L		 8430 fprintf (stream, _("\
8431 --32/--64 generate 32bit/64bit code\n"));
8432#endif
b3b91714
AM		 8433#ifdef SVR4_COMMENT_CHARS
8434 fprintf (stream, _("\
8435 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 8436#else
8437 fprintf (stream, _("\
b3b91714 8438 --divide ignored\n"));
4cc782b5 8439#endif
9103f4f4 8440 fprintf (stream, _("\
6305a203 8441 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 8442 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 8443 show_arch (stream, 0, 1);
8a2c8fef
L		 8444 fprintf (stream, _("\
8445 EXTENSION is combination of:\n"));
1ded5609 8446 show_arch (stream, 1, 0);
6305a203 8447 fprintf (stream, _("\
8a2c8fef 8448 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 8449 show_arch (stream, 0, 0);
ba104c83 8450 fprintf (stream, _("\
c0f3af97
L		 8451 -msse2avx encode SSE instructions with VEX prefix\n"));
8452 fprintf (stream, _("\
daf50ae7
L		 8453 -msse-check=[none|error|warning]\n\
8454 check SSE instructions\n"));
8455 fprintf (stream, _("\
539f890d
L		 8456 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
8457 length\n"));
8458 fprintf (stream, _("\
ba104c83
L		 8459 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8460 fprintf (stream, _("\
8461 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8462 fprintf (stream, _("\
8463 -mindex-reg support pseudo index registers\n"));
8464 fprintf (stream, _("\
8465 -mnaked-reg don't require `%%' prefix for registers\n"));
8466 fprintf (stream, _("\
8467 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
252b5132
RH		 8468}
8469
3e73aa7c 8470#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 8471 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 8472 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 8473
8474/* Pick the target format to use. */
8475
47926f60 8476const char *
e3bb37b5 8477i386_target_format (void)
252b5132 8478{
3e73aa7c 8479 if (!strcmp (default_arch, "x86_64"))
78f12dd3 8480 update_code_flag (CODE_64BIT, 1);
3e73aa7c 8481 else if (!strcmp (default_arch, "i386"))
78f12dd3 8482 update_code_flag (CODE_32BIT, 1);
3e73aa7c
JH		 8483 else
8484 as_fatal (_("Unknown architecture"));
89507696
JB		 8485
8486 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
8487 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
8488 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
8489 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
8490
252b5132
RH		 8491 switch (OUTPUT_FLAVOR)
8492 {
9384f2ff 8493#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 8494 case bfd_target_aout_flavour:
47926f60 8495 return AOUT_TARGET_FORMAT;
4c63da97 8496#endif
9384f2ff
AM		 8497#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
8498# if defined (TE_PE) || defined (TE_PEP)
8499 case bfd_target_coff_flavour:
8500 return flag_code == CODE_64BIT ? "pe-x86-64" : "pe-i386";
8501# elif defined (TE_GO32)
0561d57c
JK		 8502 case bfd_target_coff_flavour:
8503 return "coff-go32";
9384f2ff 8504# else
252b5132
RH		 8505 case bfd_target_coff_flavour:
8506 return "coff-i386";
9384f2ff 8507# endif
4c63da97 8508#endif
3e73aa7c 8509#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 8510 case bfd_target_elf_flavour:
3e73aa7c 8511 {
e5cb08ac 8512 if (flag_code == CODE_64BIT)
4fa24527
JB		 8513 {
8514 object_64bit = 1;
8515 use_rela_relocations = 1;
8516 }
3632d14b 8517 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 8518 {
8519 if (flag_code != CODE_64BIT)
8520 as_fatal (_("Intel L1OM is 64bit only"));
8521 return ELF_TARGET_L1OM_FORMAT;
8522 }
8523 else
8524 return (flag_code == CODE_64BIT
8525 ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT);
3e73aa7c 8526 }
e57f8c65
TG		 8527#endif
8528#if defined (OBJ_MACH_O)
8529 case bfd_target_mach_o_flavour:
8530 return flag_code == CODE_64BIT ? "mach-o-x86-64" : "mach-o-i386";
4c63da97 8531#endif
252b5132
RH		 8532 default:
8533 abort ();
8534 return NULL;
8535 }
8536}
8537
47926f60 8538#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 8539
8540#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 8541void
8542i386_elf_emit_arch_note (void)
a847613f 8543{
718ddfc0 8544 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 8545 {
8546 char *p;
8547 asection *seg = now_seg;
8548 subsegT subseg = now_subseg;
8549 Elf_Internal_Note i_note;
8550 Elf_External_Note e_note;
8551 asection *note_secp;
8552 int len;
8553
8554 /* Create the .note section. */
8555 note_secp = subseg_new (".note", 0);
8556 bfd_set_section_flags (stdoutput,
8557 note_secp,
8558 SEC_HAS_CONTENTS | SEC_READONLY);
8559
8560 /* Process the arch string. */
8561 len = strlen (cpu_arch_name);
8562
8563 i_note.namesz = len + 1;
8564 i_note.descsz = 0;
8565 i_note.type = NT_ARCH;
8566 p = frag_more (sizeof (e_note.namesz));
8567 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
8568 p = frag_more (sizeof (e_note.descsz));
8569 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
8570 p = frag_more (sizeof (e_note.type));
8571 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
8572 p = frag_more (len + 1);
8573 strcpy (p, cpu_arch_name);
8574
8575 frag_align (2, 0, 0);
8576
8577 subseg_set (seg, subseg);
8578 }
8579}
8580#endif
252b5132 8581\f
252b5132
RH		 8582symbolS *
8583md_undefined_symbol (name)
8584 char *name;
8585{
18dc2407
ILT		 8586 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
8587 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
8588 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
8589 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 8590 {
8591 if (!GOT_symbol)
8592 {
8593 if (symbol_find (name))
8594 as_bad (_("GOT already in symbol table"));
8595 GOT_symbol = symbol_new (name, undefined_section,
8596 (valueT) 0, &zero_address_frag);
8597 };
8598 return GOT_symbol;
8599 }
252b5132
RH		 8600 return 0;
8601}
8602
8603/* Round up a section size to the appropriate boundary. */
47926f60 8604
252b5132
RH		 8605valueT
8606md_section_align (segment, size)
ab9da554 8607 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 8608 valueT size;
8609{
4c63da97
AM		 8610#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8611 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
8612 {
8613 /* For a.out, force the section size to be aligned. If we don't do
8614 this, BFD will align it for us, but it will not write out the
8615 final bytes of the section. This may be a bug in BFD, but it is
8616 easier to fix it here since that is how the other a.out targets
8617 work. */
8618 int align;
8619
8620 align = bfd_get_section_alignment (stdoutput, segment);
8621 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
8622 }
252b5132
RH		 8623#endif
8624
8625 return size;
8626}
8627
8628/* On the i386, PC-relative offsets are relative to the start of the
8629 next instruction. That is, the address of the offset, plus its
8630 size, since the offset is always the last part of the insn. */
8631
8632long
e3bb37b5 8633md_pcrel_from (fixS *fixP)
252b5132
RH		 8634{
8635 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
8636}
8637
8638#ifndef I386COFF
8639
8640static void
e3bb37b5 8641s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 8642{
29b0f896 8643 int temp;
252b5132 8644
8a75718c
JB		 8645#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8646 if (IS_ELF)
8647 obj_elf_section_change_hook ();
8648#endif
252b5132
RH		 8649 temp = get_absolute_expression ();
8650 subseg_set (bss_section, (subsegT) temp);
8651 demand_empty_rest_of_line ();
8652}
8653
8654#endif
8655
252b5132 8656void
e3bb37b5 8657i386_validate_fix (fixS *fixp)
252b5132
RH		 8658{
8659 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
8660 {
23df1078
JH		 8661 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
8662 {
4fa24527 8663 if (!object_64bit)
23df1078
JH		 8664 abort ();
8665 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
8666 }
8667 else
8668 {
4fa24527 8669 if (!object_64bit)
d6ab8113
JB		 8670 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
8671 else
8672 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 8673 }
252b5132
RH		 8674 fixp->fx_subsy = 0;
8675 }
8676}
8677
252b5132
RH		 8678arelent *
8679tc_gen_reloc (section, fixp)
ab9da554 8680 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 8681 fixS *fixp;
8682{
8683 arelent *rel;
8684 bfd_reloc_code_real_type code;
8685
8686 switch (fixp->fx_r_type)
8687 {
3e73aa7c
JH		 8688 case BFD_RELOC_X86_64_PLT32:
8689 case BFD_RELOC_X86_64_GOT32:
8690 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 8691 case BFD_RELOC_386_PLT32:
8692 case BFD_RELOC_386_GOT32:
8693 case BFD_RELOC_386_GOTOFF:
8694 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 8695 case BFD_RELOC_386_TLS_GD:
8696 case BFD_RELOC_386_TLS_LDM:
8697 case BFD_RELOC_386_TLS_LDO_32:
8698 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 8699 case BFD_RELOC_386_TLS_IE:
8700 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 8701 case BFD_RELOC_386_TLS_LE_32:
8702 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 8703 case BFD_RELOC_386_TLS_GOTDESC:
8704 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 8705 case BFD_RELOC_X86_64_TLSGD:
8706 case BFD_RELOC_X86_64_TLSLD:
8707 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 8708 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 8709 case BFD_RELOC_X86_64_GOTTPOFF:
8710 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 8711 case BFD_RELOC_X86_64_TPOFF64:
8712 case BFD_RELOC_X86_64_GOTOFF64:
8713 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 8714 case BFD_RELOC_X86_64_GOT64:
8715 case BFD_RELOC_X86_64_GOTPCREL64:
8716 case BFD_RELOC_X86_64_GOTPC64:
8717 case BFD_RELOC_X86_64_GOTPLT64:
8718 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 8719 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8720 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 8721 case BFD_RELOC_RVA:
8722 case BFD_RELOC_VTABLE_ENTRY:
8723 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 8724#ifdef TE_PE
8725 case BFD_RELOC_32_SECREL:
8726#endif
252b5132
RH		 8727 code = fixp->fx_r_type;
8728 break;
dbbaec26
L		 8729 case BFD_RELOC_X86_64_32S:
8730 if (!fixp->fx_pcrel)
8731 {
8732 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8733 code = fixp->fx_r_type;
8734 break;
8735 }
252b5132 8736 default:
93382f6d 8737 if (fixp->fx_pcrel)
252b5132 8738 {
93382f6d
AM		 8739 switch (fixp->fx_size)
8740 {
8741 default:
b091f402
AM		 8742 as_bad_where (fixp->fx_file, fixp->fx_line,
8743 _("can not do %d byte pc-relative relocation"),
8744 fixp->fx_size);
93382f6d
AM		 8745 code = BFD_RELOC_32_PCREL;
8746 break;
8747 case 1: code = BFD_RELOC_8_PCREL; break;
8748 case 2: code = BFD_RELOC_16_PCREL; break;
8749 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 8750#ifdef BFD64
8751 case 8: code = BFD_RELOC_64_PCREL; break;
8752#endif
93382f6d
AM		 8753 }
8754 }
8755 else
8756 {
8757 switch (fixp->fx_size)
8758 {
8759 default:
b091f402
AM		 8760 as_bad_where (fixp->fx_file, fixp->fx_line,
8761 _("can not do %d byte relocation"),
8762 fixp->fx_size);
93382f6d
AM		 8763 code = BFD_RELOC_32;
8764 break;
8765 case 1: code = BFD_RELOC_8; break;
8766 case 2: code = BFD_RELOC_16; break;
8767 case 4: code = BFD_RELOC_32; break;
937149dd 8768#ifdef BFD64
3e73aa7c 8769 case 8: code = BFD_RELOC_64; break;
937149dd 8770#endif
93382f6d 8771 }
252b5132
RH		 8772 }
8773 break;
8774 }
252b5132 8775
d182319b
JB		 8776 if ((code == BFD_RELOC_32
8777 || code == BFD_RELOC_32_PCREL
8778 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 8779 && GOT_symbol
8780 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 8781 {
4fa24527 8782 if (!object_64bit)
d6ab8113
JB		 8783 code = BFD_RELOC_386_GOTPC;
8784 else
8785 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 8786 }
7b81dfbb
AJ		 8787 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
8788 && GOT_symbol
8789 && fixp->fx_addsy == GOT_symbol)
8790 {
8791 code = BFD_RELOC_X86_64_GOTPC64;
8792 }
252b5132
RH		 8793
8794 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 8795 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
8796 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 8797
8798 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 8799
3e73aa7c
JH		 8800 if (!use_rela_relocations)
8801 {
8802 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8803 vtable entry to be used in the relocation's section offset. */
8804 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
8805 rel->address = fixp->fx_offset;
fbeb56a4
DK		 8806#if defined (OBJ_COFF) && defined (TE_PE)
8807 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
8808 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
8809 else
8810#endif
c6682705 8811 rel->addend = 0;
3e73aa7c
JH		 8812 }
8813 /* Use the rela in 64bit mode. */
252b5132 8814 else
3e73aa7c 8815 {
062cd5e7
AS		 8816 if (!fixp->fx_pcrel)
8817 rel->addend = fixp->fx_offset;
8818 else
8819 switch (code)
8820 {
8821 case BFD_RELOC_X86_64_PLT32:
8822 case BFD_RELOC_X86_64_GOT32:
8823 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 8824 case BFD_RELOC_X86_64_TLSGD:
8825 case BFD_RELOC_X86_64_TLSLD:
8826 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 8827 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8828 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 8829 rel->addend = fixp->fx_offset - fixp->fx_size;
8830 break;
8831 default:
8832 rel->addend = (section->vma
8833 - fixp->fx_size
8834 + fixp->fx_addnumber
8835 + md_pcrel_from (fixp));
8836 break;
8837 }
3e73aa7c
JH		 8838 }
8839
252b5132
RH		 8840 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
8841 if (rel->howto == NULL)
8842 {
8843 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 8844 _("cannot represent relocation type %s"),
252b5132
RH		 8845 bfd_get_reloc_code_name (code));
8846 /* Set howto to a garbage value so that we can keep going. */
8847 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 8848 gas_assert (rel->howto != NULL);
252b5132
RH		 8849 }
8850
8851 return rel;
8852}
8853
ee86248c 8854#include "tc-i386-intel.c"
54cfded0 8855
a60de03c
JB		 8856void
8857tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 8858{
a60de03c
JB		 8859 int saved_naked_reg;
8860 char saved_register_dot;
54cfded0 8861
a60de03c
JB		 8862 saved_naked_reg = allow_naked_reg;
8863 allow_naked_reg = 1;
8864 saved_register_dot = register_chars['.'];
8865 register_chars['.'] = '.';
8866 allow_pseudo_reg = 1;
8867 expression_and_evaluate (exp);
8868 allow_pseudo_reg = 0;
8869 register_chars['.'] = saved_register_dot;
8870 allow_naked_reg = saved_naked_reg;
8871
e96d56a1 8872 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 8873 {
a60de03c
JB		 8874 if ((addressT) exp->X_add_number < i386_regtab_size)
8875 {
8876 exp->X_op = O_constant;
8877 exp->X_add_number = i386_regtab[exp->X_add_number]
8878 .dw2_regnum[flag_code >> 1];
8879 }
8880 else
8881 exp->X_op = O_illegal;
54cfded0 8882 }
54cfded0
AM		 8883}
8884
8885void
8886tc_x86_frame_initial_instructions (void)
8887{
a60de03c
JB		 8888 static unsigned int sp_regno[2];
8889
8890 if (!sp_regno[flag_code >> 1])
8891 {
8892 char *saved_input = input_line_pointer;
8893 char sp[][4] = {"esp", "rsp"};
8894 expressionS exp;
a4447b93 8895
a60de03c
JB		 8896 input_line_pointer = sp[flag_code >> 1];
8897 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 8898 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 8899 sp_regno[flag_code >> 1] = exp.X_add_number;
8900 input_line_pointer = saved_input;
8901 }
a4447b93 8902
a60de03c 8903 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
a4447b93 8904 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 8905}
d2b2c203
DJ		 8906
8907int
8908i386_elf_section_type (const char *str, size_t len)
8909{
8910 if (flag_code == CODE_64BIT
8911 && len == sizeof ("unwind") - 1
8912 && strncmp (str, "unwind", 6) == 0)
8913 return SHT_X86_64_UNWIND;
8914
8915 return -1;
8916}
bb41ade5 8917
ad5fec3b
EB		 8918#ifdef TE_SOLARIS
8919void
8920i386_solaris_fix_up_eh_frame (segT sec)
8921{
8922 if (flag_code == CODE_64BIT)
8923 elf_section_type (sec) = SHT_X86_64_UNWIND;
8924}
8925#endif
8926
bb41ade5
AM		 8927#ifdef TE_PE
8928void
8929tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
8930{
91d6fa6a 8931 expressionS exp;
bb41ade5 8932
91d6fa6a
NC		 8933 exp.X_op = O_secrel;
8934 exp.X_add_symbol = symbol;
8935 exp.X_add_number = 0;
8936 emit_expr (&exp, size);
bb41ade5
AM		 8937}
8938#endif
3b22753a
L		 8939
8940#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8941/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8942
01e1a5bc 8943bfd_vma
3b22753a
L		 8944x86_64_section_letter (int letter, char **ptr_msg)
8945{
8946 if (flag_code == CODE_64BIT)
8947 {
8948 if (letter == 'l')
8949 return SHF_X86_64_LARGE;
8950
8951 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 8952 }
3b22753a 8953 else
64e74474 8954 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 8955 return -1;
8956}
8957
01e1a5bc 8958bfd_vma
3b22753a
L		 8959x86_64_section_word (char *str, size_t len)
8960{
8620418b 8961 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 8962 return SHF_X86_64_LARGE;
8963
8964 return -1;
8965}
8966
8967static void
8968handle_large_common (int small ATTRIBUTE_UNUSED)
8969{
8970 if (flag_code != CODE_64BIT)
8971 {
8972 s_comm_internal (0, elf_common_parse);
8973 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
8974 }
8975 else
8976 {
8977 static segT lbss_section;
8978 asection *saved_com_section_ptr = elf_com_section_ptr;
8979 asection *saved_bss_section = bss_section;
8980
8981 if (lbss_section == NULL)
8982 {
8983 flagword applicable;
8984 segT seg = now_seg;
8985 subsegT subseg = now_subseg;
8986
8987 /* The .lbss section is for local .largecomm symbols. */
8988 lbss_section = subseg_new (".lbss", 0);
8989 applicable = bfd_applicable_section_flags (stdoutput);
8990 bfd_set_section_flags (stdoutput, lbss_section,
8991 applicable & SEC_ALLOC);
8992 seg_info (lbss_section)->bss = 1;
8993
8994 subseg_set (seg, subseg);
8995 }
8996
8997 elf_com_section_ptr = &_bfd_elf_large_com_section;
8998 bss_section = lbss_section;
8999
9000 s_comm_internal (0, elf_common_parse);
9001
9002 elf_com_section_ptr = saved_com_section_ptr;
9003 bss_section = saved_bss_section;
9004 }
9005}
9006#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
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