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2009-12-10 Michael Snyder <[email protected]>
[binutils.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
0bfee649 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus ([email protected]).
3e73aa7c 25 x86_64 support by Jan Hubicka ([email protected])
0f10071e 26 VIA PadLock support by Michal Ludvig ([email protected])
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
40fb9820 36#include "opcodes/i386-init.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
29b0f896
AM		 46#ifndef DEFAULT_ARCH
47#define DEFAULT_ARCH "i386"
246fcdee 48#endif
252b5132 49
edde18a5
AM		 50#ifndef INLINE
51#if __GNUC__ >= 2
52#define INLINE __inline__
53#else
54#define INLINE
55#endif
56#endif
57
6305a203
L		 58/* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
c32fa91d 62 REP_PREFIX, LOCK_PREFIX. */
6305a203
L		 63#define WAIT_PREFIX 0
64#define SEG_PREFIX 1
65#define ADDR_PREFIX 2
66#define DATA_PREFIX 3
c32fa91d
L		 67#define REP_PREFIX 4
68#define LOCK_PREFIX 5
69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
84#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 85#define YMMWORD_MNEM_SUFFIX 'y'
6305a203
L		 86/* Intel Syntax. Use a non-ascii letter since since it never appears
87 in instructions. */
88#define LONG_DOUBLE_MNEM_SUFFIX '\1'
89
90#define END_OF_INSN '\0'
91
92/*
93 'templates' is for grouping together 'template' structures for opcodes
94 of the same name. This is only used for storing the insns in the grand
95 ole hash table of insns.
96 The templates themselves start at START and range up to (but not including)
97 END.
98 */
99typedef struct
100{
d3ce72d0
NC		 101 const insn_template *start;
102 const insn_template *end;
6305a203
L		 103}
104templates;
105
106/* 386 operand encoding bytes: see 386 book for details of this. */
107typedef struct
108{
109 unsigned int regmem; /* codes register or memory operand */
110 unsigned int reg; /* codes register operand (or extended opcode) */
111 unsigned int mode; /* how to interpret regmem & reg */
112}
113modrm_byte;
114
115/* x86-64 extension prefix. */
116typedef int rex_byte;
117
6305a203
L		 118/* 386 opcode byte to code indirect addressing. */
119typedef struct
120{
121 unsigned base;
122 unsigned index;
123 unsigned scale;
124}
125sib_byte;
126
6305a203
L		 127/* x86 arch names, types and features */
128typedef struct
129{
130 const char *name; /* arch name */
8a2c8fef 131 unsigned int len; /* arch string length */
6305a203
L		 132 enum processor_type type; /* arch type */
133 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 134 unsigned int skip; /* show_arch should skip this. */
6305a203
L		 135}
136arch_entry;
137
e3bb37b5
L		 138static void set_code_flag (int);
139static void set_16bit_gcc_code_flag (int);
140static void set_intel_syntax (int);
1efbbeb4 141static void set_intel_mnemonic (int);
db51cc60 142static void set_allow_index_reg (int);
cb19c032 143static void set_sse_check (int);
e3bb37b5 144static void set_cpu_arch (int);
6482c264 145#ifdef TE_PE
e3bb37b5 146static void pe_directive_secrel (int);
6482c264 147#endif
e3bb37b5
L		 148static void signed_cons (int);
149static char *output_invalid (int c);
ee86248c
JB		 150static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
151 const char *);
152static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
153 const char *);
a7619375 154static int i386_att_operand (char *);
e3bb37b5 155static int i386_intel_operand (char *, int);
ee86248c
JB		 156static int i386_intel_simplify (expressionS *);
157static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 158static const reg_entry *parse_register (char *, char **);
159static char *parse_insn (char *, char *);
160static char *parse_operands (char *, const char *);
161static void swap_operands (void);
4d456e3d 162static void swap_2_operands (int, int);
e3bb37b5
L		 163static void optimize_imm (void);
164static void optimize_disp (void);
d3ce72d0 165static const insn_template *match_template (void);
e3bb37b5
L		 166static int check_string (void);
167static int process_suffix (void);
168static int check_byte_reg (void);
169static int check_long_reg (void);
170static int check_qword_reg (void);
171static int check_word_reg (void);
172static int finalize_imm (void);
173static int process_operands (void);
174static const seg_entry *build_modrm_byte (void);
175static void output_insn (void);
176static void output_imm (fragS *, offsetT);
177static void output_disp (fragS *, offsetT);
29b0f896 178#ifndef I386COFF
e3bb37b5 179static void s_bss (int);
252b5132 180#endif
17d4e2a2
L		 181#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
182static void handle_large_common (int small ATTRIBUTE_UNUSED);
183#endif
252b5132 184
a847613f 185static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 186
c0f3af97
L		 187/* VEX prefix. */
188typedef struct
189{
190 /* VEX prefix is either 2 byte or 3 byte. */
191 unsigned char bytes[3];
192 unsigned int length;
193 /* Destination or source register specifier. */
194 const reg_entry *register_specifier;
195} vex_prefix;
196
252b5132 197/* 'md_assemble ()' gathers together information and puts it into a
47926f60 198 i386_insn. */
252b5132 199
520dc8e8
AM		 200union i386_op
201 {
202 expressionS *disps;
203 expressionS *imms;
204 const reg_entry *regs;
205 };
206
252b5132
RH		 207struct _i386_insn
208 {
47926f60 209 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 210 insn_template tm;
252b5132 211
7d5e4556
L		 212 /* SUFFIX holds the instruction size suffix for byte, word, dword
213 or qword, if given. */
252b5132
RH		 214 char suffix;
215
47926f60 216 /* OPERANDS gives the number of given operands. */
252b5132
RH		 217 unsigned int operands;
218
219 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
220 of given register, displacement, memory operands and immediate
47926f60 221 operands. */
252b5132
RH		 222 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
223
224 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 225 use OP[i] for the corresponding operand. */
40fb9820 226 i386_operand_type types[MAX_OPERANDS];
252b5132 227
520dc8e8
AM		 228 /* Displacement expression, immediate expression, or register for each
229 operand. */
230 union i386_op op[MAX_OPERANDS];
252b5132 231
3e73aa7c
JH		 232 /* Flags for operands. */
233 unsigned int flags[MAX_OPERANDS];
234#define Operand_PCrel 1
235
252b5132 236 /* Relocation type for operand */
f86103b7 237 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 238
252b5132
RH		 239 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
240 the base index byte below. */
241 const reg_entry *base_reg;
242 const reg_entry *index_reg;
243 unsigned int log2_scale_factor;
244
245 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 246 explicit segment overrides are given. */
ce8a8b2f 247 const seg_entry *seg[2];
252b5132
RH		 248
249 /* PREFIX holds all the given prefix opcodes (usually null).
250 PREFIXES is the number of prefix opcodes. */
251 unsigned int prefixes;
252 unsigned char prefix[MAX_PREFIXES];
253
254 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 255 addressing modes of this insn are encoded. */
252b5132 256 modrm_byte rm;
3e73aa7c 257 rex_byte rex;
252b5132 258 sib_byte sib;
c0f3af97 259 vex_prefix vex;
b6169b20
L		 260
261 /* Swap operand in encoding. */
4473e004 262 unsigned int swap_operand;
252b5132
RH		 263 };
264
265typedef struct _i386_insn i386_insn;
266
267/* List of chars besides those in app.c:symbol_chars that can start an
268 operand. Used to prevent the scrubber eating vital white-space. */
32137342 269const char extra_symbol_chars[] = "*%-(["
252b5132 270#ifdef LEX_AT
32137342
NC		 271 "@"
272#endif
273#ifdef LEX_QM
274 "?"
252b5132 275#endif
32137342 276 ;
252b5132 277
29b0f896
AM		 278#if (defined (TE_I386AIX) \
279 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 280 && !defined (TE_GNU) \
29b0f896 281 && !defined (TE_LINUX) \
32137342 282 && !defined (TE_NETWARE) \
29b0f896
AM		 283 && !defined (TE_FreeBSD) \
284 && !defined (TE_NetBSD)))
252b5132 285/* This array holds the chars that always start a comment. If the
b3b91714
AM		 286 pre-processor is disabled, these aren't very useful. The option
287 --divide will remove '/' from this list. */
288const char *i386_comment_chars = "#/";
289#define SVR4_COMMENT_CHARS 1
252b5132 290#define PREFIX_SEPARATOR '\\'
252b5132 291
b3b91714
AM		 292#else
293const char *i386_comment_chars = "#";
294#define PREFIX_SEPARATOR '/'
295#endif
296
252b5132
RH		 297/* This array holds the chars that only start a comment at the beginning of
298 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 299 .line and .file directives will appear in the pre-processed output.
300 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 301 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 302 #NO_APP at the beginning of its output.
303 Also note that comments started like this one will always work if
252b5132 304 '/' isn't otherwise defined. */
b3b91714 305const char line_comment_chars[] = "#/";
252b5132 306
63a0b638 307const char line_separator_chars[] = ";";
252b5132 308
ce8a8b2f
AM		 309/* Chars that can be used to separate mant from exp in floating point
310 nums. */
252b5132
RH		 311const char EXP_CHARS[] = "eE";
312
ce8a8b2f
AM		 313/* Chars that mean this number is a floating point constant
314 As in 0f12.456
315 or 0d1.2345e12. */
252b5132
RH		 316const char FLT_CHARS[] = "fFdDxX";
317
ce8a8b2f 318/* Tables for lexical analysis. */
252b5132
RH		 319static char mnemonic_chars[256];
320static char register_chars[256];
321static char operand_chars[256];
322static char identifier_chars[256];
323static char digit_chars[256];
324
ce8a8b2f 325/* Lexical macros. */
252b5132
RH		 326#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
327#define is_operand_char(x) (operand_chars[(unsigned char) x])
328#define is_register_char(x) (register_chars[(unsigned char) x])
329#define is_space_char(x) ((x) == ' ')
330#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
331#define is_digit_char(x) (digit_chars[(unsigned char) x])
332
0234cb7c 333/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 334static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
335
336/* md_assemble() always leaves the strings it's passed unaltered. To
337 effect this we maintain a stack of saved characters that we've smashed
338 with '\0's (indicating end of strings for various sub-fields of the
47926f60 339 assembler instruction). */
252b5132 340static char save_stack[32];
ce8a8b2f 341static char *save_stack_p;
252b5132
RH		 342#define END_STRING_AND_SAVE(s) \
343 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
344#define RESTORE_END_STRING(s) \
345 do { *(s) = *--save_stack_p; } while (0)
346
47926f60 347/* The instruction we're assembling. */
252b5132
RH		 348static i386_insn i;
349
350/* Possible templates for current insn. */
351static const templates *current_templates;
352
31b2323c
L		 353/* Per instruction expressionS buffers: max displacements & immediates. */
354static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
355static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 356
47926f60 357/* Current operand we are working on. */
ee86248c 358static int this_operand = -1;
252b5132 359
3e73aa7c
JH		 360/* We support four different modes. FLAG_CODE variable is used to distinguish
361 these. */
362
363enum flag_code {
364 CODE_32BIT,
365 CODE_16BIT,
366 CODE_64BIT };
367
368static enum flag_code flag_code;
4fa24527 369static unsigned int object_64bit;
3e73aa7c
JH		 370static int use_rela_relocations = 0;
371
372/* The names used to print error messages. */
b77a7acd 373static const char *flag_code_names[] =
3e73aa7c
JH		 374 {
375 "32",
376 "16",
377 "64"
378 };
252b5132 379
47926f60
KH		 380/* 1 for intel syntax,
381 0 if att syntax. */
382static int intel_syntax = 0;
252b5132 383
1efbbeb4
L		 384/* 1 for intel mnemonic,
385 0 if att mnemonic. */
386static int intel_mnemonic = !SYSV386_COMPAT;
387
5209009a 388/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 389static int old_gcc = OLDGCC_COMPAT;
390
a60de03c
JB		 391/* 1 if pseudo registers are permitted. */
392static int allow_pseudo_reg = 0;
393
47926f60
KH		 394/* 1 if register prefix % not required. */
395static int allow_naked_reg = 0;
252b5132 396
ba104c83 397/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 398static int allow_index_reg = 0;
399
daf50ae7
L		 400static enum
401 {
402 sse_check_none = 0,
403 sse_check_warning,
404 sse_check_error
405 }
406sse_check;
407
2ca3ace5
L		 408/* Register prefix used for error message. */
409static const char *register_prefix = "%";
410
47926f60
KH		 411/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
412 leave, push, and pop instructions so that gcc has the same stack
413 frame as in 32 bit mode. */
414static char stackop_size = '\0';
eecb386c 415
12b55ccc
L		 416/* Non-zero to optimize code alignment. */
417int optimize_align_code = 1;
418
47926f60
KH		 419/* Non-zero to quieten some warnings. */
420static int quiet_warnings = 0;
a38cf1db 421
47926f60
KH		 422/* CPU name. */
423static const char *cpu_arch_name = NULL;
6305a203 424static char *cpu_sub_arch_name = NULL;
a38cf1db 425
47926f60 426/* CPU feature flags. */
40fb9820
L		 427static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
428
ccc9c027
L		 429/* If we have selected a cpu we are generating instructions for. */
430static int cpu_arch_tune_set = 0;
431
9103f4f4 432/* Cpu we are generating instructions for. */
fbf3f584 433enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 434
435/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 436static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 437
ccc9c027 438/* CPU instruction set architecture used. */
fbf3f584 439enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 440
9103f4f4 441/* CPU feature flags of instruction set architecture used. */
fbf3f584 442i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 443
fddf5b5b
AM		 444/* If set, conditional jumps are not automatically promoted to handle
445 larger than a byte offset. */
446static unsigned int no_cond_jump_promotion = 0;
447
c0f3af97
L		 448/* Encode SSE instructions with VEX prefix. */
449static unsigned int sse2avx;
450
29b0f896 451/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 452static symbolS *GOT_symbol;
29b0f896 453
a4447b93
RH		 454/* The dwarf2 return column, adjusted for 32 or 64 bit. */
455unsigned int x86_dwarf2_return_column;
456
457/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
458int x86_cie_data_alignment;
459
252b5132 460/* Interface to relax_segment.
fddf5b5b
AM		 461 There are 3 major relax states for 386 jump insns because the
462 different types of jumps add different sizes to frags when we're
463 figuring out what sort of jump to choose to reach a given label. */
252b5132 464
47926f60 465/* Types. */
93c2a809
AM		 466#define UNCOND_JUMP 0
467#define COND_JUMP 1
468#define COND_JUMP86 2
fddf5b5b 469
47926f60 470/* Sizes. */
252b5132
RH		 471#define CODE16 1
472#define SMALL 0
29b0f896 473#define SMALL16 (SMALL | CODE16)
252b5132 474#define BIG 2
29b0f896 475#define BIG16 (BIG | CODE16)
252b5132
RH		 476
477#ifndef INLINE
478#ifdef __GNUC__
479#define INLINE __inline__
480#else
481#define INLINE
482#endif
483#endif
484
fddf5b5b
AM		 485#define ENCODE_RELAX_STATE(type, size) \
486 ((relax_substateT) (((type) << 2) | (size)))
487#define TYPE_FROM_RELAX_STATE(s) \
488 ((s) >> 2)
489#define DISP_SIZE_FROM_RELAX_STATE(s) \
490 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 491
492/* This table is used by relax_frag to promote short jumps to long
493 ones where necessary. SMALL (short) jumps may be promoted to BIG
494 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
495 don't allow a short jump in a 32 bit code segment to be promoted to
496 a 16 bit offset jump because it's slower (requires data size
497 prefix), and doesn't work, unless the destination is in the bottom
498 64k of the code segment (The top 16 bits of eip are zeroed). */
499
500const relax_typeS md_relax_table[] =
501{
24eab124
AM		 502 /* The fields are:
503 1) most positive reach of this state,
504 2) most negative reach of this state,
93c2a809 505 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 506 4) which index into the table to try if we can't fit into this one. */
252b5132 507
fddf5b5b 508 /* UNCOND_JUMP states. */
93c2a809
AM		 509 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
510 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
511 /* dword jmp adds 4 bytes to frag:
512 0 extra opcode bytes, 4 displacement bytes. */
252b5132 513 {0, 0, 4, 0},
93c2a809
AM		 514 /* word jmp adds 2 byte2 to frag:
515 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 516 {0, 0, 2, 0},
517
93c2a809
AM		 518 /* COND_JUMP states. */
519 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
520 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
521 /* dword conditionals adds 5 bytes to frag:
522 1 extra opcode byte, 4 displacement bytes. */
523 {0, 0, 5, 0},
fddf5b5b 524 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 525 1 extra opcode byte, 2 displacement bytes. */
526 {0, 0, 3, 0},
527
528 /* COND_JUMP86 states. */
529 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
530 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
531 /* dword conditionals adds 5 bytes to frag:
532 1 extra opcode byte, 4 displacement bytes. */
533 {0, 0, 5, 0},
534 /* word conditionals add 4 bytes to frag:
535 1 displacement byte and a 3 byte long branch insn. */
536 {0, 0, 4, 0}
252b5132
RH		 537};
538
9103f4f4
L		 539static const arch_entry cpu_arch[] =
540{
8a2c8fef
L		 541 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
542 CPU_GENERIC32_FLAGS, 0 },
543 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
544 CPU_GENERIC64_FLAGS, 0 },
545 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
546 CPU_NONE_FLAGS, 0 },
547 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
548 CPU_I186_FLAGS, 0 },
549 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
550 CPU_I286_FLAGS, 0 },
551 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
552 CPU_I386_FLAGS, 0 },
553 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
554 CPU_I486_FLAGS, 0 },
555 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
556 CPU_I586_FLAGS, 0 },
557 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
558 CPU_I686_FLAGS, 0 },
559 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
560 CPU_I586_FLAGS, 0 },
561 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
562 CPU_I686_FLAGS, 0 },
563 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
564 CPU_P2_FLAGS, 0 },
565 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
566 CPU_P3_FLAGS, 0 },
567 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
568 CPU_P4_FLAGS, 0 },
569 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
570 CPU_CORE_FLAGS, 0 },
571 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
572 CPU_NOCONA_FLAGS, 0 },
573 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
574 CPU_CORE_FLAGS, 1 },
575 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
576 CPU_CORE_FLAGS, 0 },
577 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
578 CPU_CORE2_FLAGS, 1 },
579 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
580 CPU_CORE2_FLAGS, 0 },
581 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
582 CPU_COREI7_FLAGS, 0 },
583 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
584 CPU_L1OM_FLAGS, 0 },
585 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
586 CPU_K6_FLAGS, 0 },
587 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
588 CPU_K6_2_FLAGS, 0 },
589 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
590 CPU_ATHLON_FLAGS, 0 },
591 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
592 CPU_K8_FLAGS, 1 },
593 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
594 CPU_K8_FLAGS, 0 },
595 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
596 CPU_K8_FLAGS, 0 },
597 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
598 CPU_AMDFAM10_FLAGS, 0 },
599 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
600 CPU_8087_FLAGS, 0 },
601 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
602 CPU_287_FLAGS, 0 },
603 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
604 CPU_387_FLAGS, 0 },
605 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
606 CPU_ANY87_FLAGS, 0 },
607 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
608 CPU_MMX_FLAGS, 0 },
609 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
610 CPU_3DNOWA_FLAGS, 0 },
611 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
612 CPU_SSE_FLAGS, 0 },
613 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
614 CPU_SSE2_FLAGS, 0 },
615 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
616 CPU_SSE3_FLAGS, 0 },
617 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
618 CPU_SSSE3_FLAGS, 0 },
619 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
620 CPU_SSE4_1_FLAGS, 0 },
621 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
622 CPU_SSE4_2_FLAGS, 0 },
623 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
624 CPU_SSE4_2_FLAGS, 0 },
625 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
626 CPU_ANY_SSE_FLAGS, 0 },
627 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
628 CPU_AVX_FLAGS, 0 },
629 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
630 CPU_ANY_AVX_FLAGS, 0 },
631 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
632 CPU_VMX_FLAGS, 0 },
633 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
634 CPU_SMX_FLAGS, 0 },
635 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
636 CPU_XSAVE_FLAGS, 0 },
637 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
638 CPU_AES_FLAGS, 0 },
639 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
640 CPU_PCLMUL_FLAGS, 0 },
641 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
642 CPU_PCLMUL_FLAGS, 1 },
643 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
644 CPU_FMA_FLAGS, 0 },
645 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
646 CPU_FMA4_FLAGS, 0 },
647 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
648 CPU_XOP_FLAGS, 0 },
649 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
650 CPU_LWP_FLAGS, 0 },
651 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
652 CPU_MOVBE_FLAGS, 0 },
653 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
654 CPU_EPT_FLAGS, 0 },
655 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
656 CPU_CLFLUSH_FLAGS, 0 },
657 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
658 CPU_SYSCALL_FLAGS, 0 },
659 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
660 CPU_RDTSCP_FLAGS, 0 },
661 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
662 CPU_3DNOW_FLAGS, 0 },
663 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
664 CPU_3DNOWA_FLAGS, 0 },
665 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
666 CPU_PADLOCK_FLAGS, 0 },
667 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
668 CPU_SVME_FLAGS, 1 },
669 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
670 CPU_SVME_FLAGS, 0 },
671 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
672 CPU_SSE4A_FLAGS, 0 },
673 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
674 CPU_ABM_FLAGS, 0 },
e413e4e9
AM		 675};
676
704209c0 677#ifdef I386COFF
a6c24e68
NC		 678/* Like s_lcomm_internal in gas/read.c but the alignment string
679 is allowed to be optional. */
680
681static symbolS *
682pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
683{
684 addressT align = 0;
685
686 SKIP_WHITESPACE ();
687
7ab9ffdd 688 if (needs_align
a6c24e68
NC		 689 && *input_line_pointer == ',')
690 {
691 align = parse_align (needs_align - 1);
7ab9ffdd 692
a6c24e68
NC		 693 if (align == (addressT) -1)
694 return NULL;
695 }
696 else
697 {
698 if (size >= 8)
699 align = 3;
700 else if (size >= 4)
701 align = 2;
702 else if (size >= 2)
703 align = 1;
704 else
705 align = 0;
706 }
707
708 bss_alloc (symbolP, size, align);
709 return symbolP;
710}
711
704209c0 712static void
a6c24e68
NC		 713pe_lcomm (int needs_align)
714{
715 s_comm_internal (needs_align * 2, pe_lcomm_internal);
716}
704209c0 717#endif
a6c24e68 718
29b0f896
AM		 719const pseudo_typeS md_pseudo_table[] =
720{
721#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
722 {"align", s_align_bytes, 0},
723#else
724 {"align", s_align_ptwo, 0},
725#endif
726 {"arch", set_cpu_arch, 0},
727#ifndef I386COFF
728 {"bss", s_bss, 0},
a6c24e68
NC		 729#else
730 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 731#endif
732 {"ffloat", float_cons, 'f'},
733 {"dfloat", float_cons, 'd'},
734 {"tfloat", float_cons, 'x'},
735 {"value", cons, 2},
d182319b 736 {"slong", signed_cons, 4},
29b0f896
AM		 737 {"noopt", s_ignore, 0},
738 {"optim", s_ignore, 0},
739 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
740 {"code16", set_code_flag, CODE_16BIT},
741 {"code32", set_code_flag, CODE_32BIT},
742 {"code64", set_code_flag, CODE_64BIT},
743 {"intel_syntax", set_intel_syntax, 1},
744 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 745 {"intel_mnemonic", set_intel_mnemonic, 1},
746 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 747 {"allow_index_reg", set_allow_index_reg, 1},
748 {"disallow_index_reg", set_allow_index_reg, 0},
cb19c032 749 {"sse_check", set_sse_check, 0},
3b22753a
L		 750#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
751 {"largecomm", handle_large_common, 0},
07a53e5c 752#else
e3bb37b5 753 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 754 {"loc", dwarf2_directive_loc, 0},
755 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 756#endif
6482c264
NC		 757#ifdef TE_PE
758 {"secrel32", pe_directive_secrel, 0},
759#endif
29b0f896
AM		 760 {0, 0, 0}
761};
762
763/* For interface with expression (). */
764extern char *input_line_pointer;
765
766/* Hash table for instruction mnemonic lookup. */
767static struct hash_control *op_hash;
768
769/* Hash table for register lookup. */
770static struct hash_control *reg_hash;
771\f
252b5132 772void
e3bb37b5 773i386_align_code (fragS *fragP, int count)
252b5132 774{
ce8a8b2f
AM		 775 /* Various efficient no-op patterns for aligning code labels.
776 Note: Don't try to assemble the instructions in the comments.
777 0L and 0w are not legal. */
252b5132
RH		 778 static const char f32_1[] =
779 {0x90}; /* nop */
780 static const char f32_2[] =
ccc9c027 781 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 782 static const char f32_3[] =
783 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
784 static const char f32_4[] =
785 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
786 static const char f32_5[] =
787 {0x90, /* nop */
788 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
789 static const char f32_6[] =
790 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
791 static const char f32_7[] =
792 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
793 static const char f32_8[] =
794 {0x90, /* nop */
795 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
796 static const char f32_9[] =
797 {0x89,0xf6, /* movl %esi,%esi */
798 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
799 static const char f32_10[] =
800 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
801 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
802 static const char f32_11[] =
803 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
804 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
805 static const char f32_12[] =
806 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
807 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
808 static const char f32_13[] =
809 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
810 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
811 static const char f32_14[] =
812 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
813 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 814 static const char f16_3[] =
815 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 816 static const char f16_4[] =
817 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
818 static const char f16_5[] =
819 {0x90, /* nop */
820 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
821 static const char f16_6[] =
822 {0x89,0xf6, /* mov %si,%si */
823 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
824 static const char f16_7[] =
825 {0x8d,0x74,0x00, /* lea 0(%si),%si */
826 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
827 static const char f16_8[] =
828 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
829 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 830 static const char jump_31[] =
831 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
832 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
833 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
834 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 835 static const char *const f32_patt[] = {
836 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 837 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 838 };
839 static const char *const f16_patt[] = {
76bc74dc 840 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 841 };
ccc9c027
L		 842 /* nopl (%[re]ax) */
843 static const char alt_3[] =
844 {0x0f,0x1f,0x00};
845 /* nopl 0(%[re]ax) */
846 static const char alt_4[] =
847 {0x0f,0x1f,0x40,0x00};
848 /* nopl 0(%[re]ax,%[re]ax,1) */
849 static const char alt_5[] =
850 {0x0f,0x1f,0x44,0x00,0x00};
851 /* nopw 0(%[re]ax,%[re]ax,1) */
852 static const char alt_6[] =
853 {0x66,0x0f,0x1f,0x44,0x00,0x00};
854 /* nopl 0L(%[re]ax) */
855 static const char alt_7[] =
856 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
857 /* nopl 0L(%[re]ax,%[re]ax,1) */
858 static const char alt_8[] =
859 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
860 /* nopw 0L(%[re]ax,%[re]ax,1) */
861 static const char alt_9[] =
862 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
863 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
864 static const char alt_10[] =
865 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
866 /* data16
867 nopw %cs:0L(%[re]ax,%[re]ax,1) */
868 static const char alt_long_11[] =
869 {0x66,
870 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
871 /* data16
872 data16
873 nopw %cs:0L(%[re]ax,%[re]ax,1) */
874 static const char alt_long_12[] =
875 {0x66,
876 0x66,
877 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
878 /* data16
879 data16
880 data16
881 nopw %cs:0L(%[re]ax,%[re]ax,1) */
882 static const char alt_long_13[] =
883 {0x66,
884 0x66,
885 0x66,
886 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
887 /* data16
888 data16
889 data16
890 data16
891 nopw %cs:0L(%[re]ax,%[re]ax,1) */
892 static const char alt_long_14[] =
893 {0x66,
894 0x66,
895 0x66,
896 0x66,
897 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
898 /* data16
899 data16
900 data16
901 data16
902 data16
903 nopw %cs:0L(%[re]ax,%[re]ax,1) */
904 static const char alt_long_15[] =
905 {0x66,
906 0x66,
907 0x66,
908 0x66,
909 0x66,
910 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
911 /* nopl 0(%[re]ax,%[re]ax,1)
912 nopw 0(%[re]ax,%[re]ax,1) */
913 static const char alt_short_11[] =
914 {0x0f,0x1f,0x44,0x00,0x00,
915 0x66,0x0f,0x1f,0x44,0x00,0x00};
916 /* nopw 0(%[re]ax,%[re]ax,1)
917 nopw 0(%[re]ax,%[re]ax,1) */
918 static const char alt_short_12[] =
919 {0x66,0x0f,0x1f,0x44,0x00,0x00,
920 0x66,0x0f,0x1f,0x44,0x00,0x00};
921 /* nopw 0(%[re]ax,%[re]ax,1)
922 nopl 0L(%[re]ax) */
923 static const char alt_short_13[] =
924 {0x66,0x0f,0x1f,0x44,0x00,0x00,
925 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
926 /* nopl 0L(%[re]ax)
927 nopl 0L(%[re]ax) */
928 static const char alt_short_14[] =
929 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
930 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
931 /* nopl 0L(%[re]ax)
932 nopl 0L(%[re]ax,%[re]ax,1) */
933 static const char alt_short_15[] =
934 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
935 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
936 static const char *const alt_short_patt[] = {
937 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
938 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
939 alt_short_14, alt_short_15
940 };
941 static const char *const alt_long_patt[] = {
942 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
943 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
944 alt_long_14, alt_long_15
945 };
252b5132 946
76bc74dc
L		 947 /* Only align for at least a positive non-zero boundary. */
948 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 949 return;
3e73aa7c 950
ccc9c027
L		 951 /* We need to decide which NOP sequence to use for 32bit and
952 64bit. When -mtune= is used:
4eed87de 953
76bc74dc
L		 954 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
955 PROCESSOR_GENERIC32, f32_patt will be used.
956 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
bd5295b2
L		 957 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
958 PROCESSOR_GENERIC64, alt_long_patt will be used.
76bc74dc
L		 959 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
960 PROCESSOR_AMDFAM10, alt_short_patt will be used.
ccc9c027 961
76bc74dc
L		 962 When -mtune= isn't used, alt_long_patt will be used if
963 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
964 be used.
ccc9c027
L		 965
966 When -march= or .arch is used, we can't use anything beyond
967 cpu_arch_isa_flags. */
968
969 if (flag_code == CODE_16BIT)
970 {
ccc9c027 971 if (count > 8)
33fef721 972 {
76bc74dc
L		 973 memcpy (fragP->fr_literal + fragP->fr_fix,
974 jump_31, count);
975 /* Adjust jump offset. */
976 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 977 }
76bc74dc
L		 978 else
979 memcpy (fragP->fr_literal + fragP->fr_fix,
980 f16_patt[count - 1], count);
252b5132 981 }
33fef721 982 else
ccc9c027
L		 983 {
984 const char *const *patt = NULL;
985
fbf3f584 986 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 987 {
988 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
989 switch (cpu_arch_tune)
990 {
991 case PROCESSOR_UNKNOWN:
992 /* We use cpu_arch_isa_flags to check if we SHOULD
993 optimize for Cpu686. */
fbf3f584 994 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
76bc74dc 995 patt = alt_long_patt;
ccc9c027
L		 996 else
997 patt = f32_patt;
998 break;
ccc9c027
L		 999 case PROCESSOR_PENTIUMPRO:
1000 case PROCESSOR_PENTIUM4:
1001 case PROCESSOR_NOCONA:
ef05d495 1002 case PROCESSOR_CORE:
76bc74dc 1003 case PROCESSOR_CORE2:
bd5295b2 1004 case PROCESSOR_COREI7:
3632d14b 1005 case PROCESSOR_L1OM:
76bc74dc
L		 1006 case PROCESSOR_GENERIC64:
1007 patt = alt_long_patt;
1008 break;
ccc9c027
L		 1009 case PROCESSOR_K6:
1010 case PROCESSOR_ATHLON:
1011 case PROCESSOR_K8:
4eed87de 1012 case PROCESSOR_AMDFAM10:
ccc9c027
L		 1013 patt = alt_short_patt;
1014 break;
76bc74dc 1015 case PROCESSOR_I386:
ccc9c027
L		 1016 case PROCESSOR_I486:
1017 case PROCESSOR_PENTIUM:
1018 case PROCESSOR_GENERIC32:
1019 patt = f32_patt;
1020 break;
4eed87de 1021 }
ccc9c027
L		 1022 }
1023 else
1024 {
fbf3f584 1025 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1026 {
1027 case PROCESSOR_UNKNOWN:
e6a14101 1028 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1029 PROCESSOR_UNKNOWN. */
1030 abort ();
1031 break;
1032
76bc74dc 1033 case PROCESSOR_I386:
ccc9c027
L		 1034 case PROCESSOR_I486:
1035 case PROCESSOR_PENTIUM:
ccc9c027
L		 1036 case PROCESSOR_K6:
1037 case PROCESSOR_ATHLON:
1038 case PROCESSOR_K8:
4eed87de 1039 case PROCESSOR_AMDFAM10:
ccc9c027
L		 1040 case PROCESSOR_GENERIC32:
1041 /* We use cpu_arch_isa_flags to check if we CAN optimize
1042 for Cpu686. */
fbf3f584 1043 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
ccc9c027
L		 1044 patt = alt_short_patt;
1045 else
1046 patt = f32_patt;
1047 break;
76bc74dc
L		 1048 case PROCESSOR_PENTIUMPRO:
1049 case PROCESSOR_PENTIUM4:
1050 case PROCESSOR_NOCONA:
1051 case PROCESSOR_CORE:
ef05d495 1052 case PROCESSOR_CORE2:
bd5295b2 1053 case PROCESSOR_COREI7:
3632d14b 1054 case PROCESSOR_L1OM:
fbf3f584 1055 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
ccc9c027
L		 1056 patt = alt_long_patt;
1057 else
1058 patt = f32_patt;
1059 break;
1060 case PROCESSOR_GENERIC64:
76bc74dc 1061 patt = alt_long_patt;
ccc9c027 1062 break;
4eed87de 1063 }
ccc9c027
L		 1064 }
1065
76bc74dc
L		 1066 if (patt == f32_patt)
1067 {
1068 /* If the padding is less than 15 bytes, we use the normal
1069 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1070 its offset. */
1071 int limit;
76ba9986 1072
711eedef
L		 1073 /* For 64bit, the limit is 3 bytes. */
1074 if (flag_code == CODE_64BIT
1075 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1076 limit = 3;
1077 else
1078 limit = 15;
1079 if (count < limit)
76bc74dc
L		 1080 memcpy (fragP->fr_literal + fragP->fr_fix,
1081 patt[count - 1], count);
1082 else
1083 {
1084 memcpy (fragP->fr_literal + fragP->fr_fix,
1085 jump_31, count);
1086 /* Adjust jump offset. */
1087 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1088 }
1089 }
1090 else
1091 {
1092 /* Maximum length of an instruction is 15 byte. If the
1093 padding is greater than 15 bytes and we don't use jump,
1094 we have to break it into smaller pieces. */
1095 int padding = count;
1096 while (padding > 15)
1097 {
1098 padding -= 15;
1099 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1100 patt [14], 15);
1101 }
1102
1103 if (padding)
1104 memcpy (fragP->fr_literal + fragP->fr_fix,
1105 patt [padding - 1], padding);
1106 }
ccc9c027 1107 }
33fef721 1108 fragP->fr_var = count;
252b5132
RH		 1109}
1110
c6fb90c8 1111static INLINE int
0dfbf9d7 1112operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1113{
0dfbf9d7 1114 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1115 {
1116 case 3:
0dfbf9d7 1117 if (x->array[2])
c6fb90c8
L		 1118 return 0;
1119 case 2:
0dfbf9d7 1120 if (x->array[1])
c6fb90c8
L		 1121 return 0;
1122 case 1:
0dfbf9d7 1123 return !x->array[0];
c6fb90c8
L		 1124 default:
1125 abort ();
1126 }
40fb9820
L		 1127}
1128
c6fb90c8 1129static INLINE void
0dfbf9d7 1130operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1131{
0dfbf9d7 1132 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1133 {
1134 case 3:
0dfbf9d7 1135 x->array[2] = v;
c6fb90c8 1136 case 2:
0dfbf9d7 1137 x->array[1] = v;
c6fb90c8 1138 case 1:
0dfbf9d7 1139 x->array[0] = v;
c6fb90c8
L		 1140 break;
1141 default:
1142 abort ();
1143 }
1144}
40fb9820 1145
c6fb90c8 1146static INLINE int
0dfbf9d7
L		 1147operand_type_equal (const union i386_operand_type *x,
1148 const union i386_operand_type *y)
c6fb90c8 1149{
0dfbf9d7 1150 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1151 {
1152 case 3:
0dfbf9d7 1153 if (x->array[2] != y->array[2])
c6fb90c8
L		 1154 return 0;
1155 case 2:
0dfbf9d7 1156 if (x->array[1] != y->array[1])
c6fb90c8
L		 1157 return 0;
1158 case 1:
0dfbf9d7 1159 return x->array[0] == y->array[0];
c6fb90c8
L		 1160 break;
1161 default:
1162 abort ();
1163 }
1164}
40fb9820 1165
0dfbf9d7
L		 1166static INLINE int
1167cpu_flags_all_zero (const union i386_cpu_flags *x)
1168{
1169 switch (ARRAY_SIZE(x->array))
1170 {
1171 case 3:
1172 if (x->array[2])
1173 return 0;
1174 case 2:
1175 if (x->array[1])
1176 return 0;
1177 case 1:
1178 return !x->array[0];
1179 default:
1180 abort ();
1181 }
1182}
1183
1184static INLINE void
1185cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1186{
1187 switch (ARRAY_SIZE(x->array))
1188 {
1189 case 3:
1190 x->array[2] = v;
1191 case 2:
1192 x->array[1] = v;
1193 case 1:
1194 x->array[0] = v;
1195 break;
1196 default:
1197 abort ();
1198 }
1199}
1200
1201static INLINE int
1202cpu_flags_equal (const union i386_cpu_flags *x,
1203 const union i386_cpu_flags *y)
1204{
1205 switch (ARRAY_SIZE(x->array))
1206 {
1207 case 3:
1208 if (x->array[2] != y->array[2])
1209 return 0;
1210 case 2:
1211 if (x->array[1] != y->array[1])
1212 return 0;
1213 case 1:
1214 return x->array[0] == y->array[0];
1215 break;
1216 default:
1217 abort ();
1218 }
1219}
c6fb90c8
L		 1220
1221static INLINE int
1222cpu_flags_check_cpu64 (i386_cpu_flags f)
1223{
1224 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1225 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1226}
1227
c6fb90c8
L		 1228static INLINE i386_cpu_flags
1229cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1230{
c6fb90c8
L		 1231 switch (ARRAY_SIZE (x.array))
1232 {
1233 case 3:
1234 x.array [2] &= y.array [2];
1235 case 2:
1236 x.array [1] &= y.array [1];
1237 case 1:
1238 x.array [0] &= y.array [0];
1239 break;
1240 default:
1241 abort ();
1242 }
1243 return x;
1244}
40fb9820 1245
c6fb90c8
L		 1246static INLINE i386_cpu_flags
1247cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1248{
c6fb90c8 1249 switch (ARRAY_SIZE (x.array))
40fb9820 1250 {
c6fb90c8
L		 1251 case 3:
1252 x.array [2] |= y.array [2];
1253 case 2:
1254 x.array [1] |= y.array [1];
1255 case 1:
1256 x.array [0] |= y.array [0];
40fb9820
L		 1257 break;
1258 default:
1259 abort ();
1260 }
40fb9820
L		 1261 return x;
1262}
1263
309d3373
JB		 1264static INLINE i386_cpu_flags
1265cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1266{
1267 switch (ARRAY_SIZE (x.array))
1268 {
1269 case 3:
1270 x.array [2] &= ~y.array [2];
1271 case 2:
1272 x.array [1] &= ~y.array [1];
1273 case 1:
1274 x.array [0] &= ~y.array [0];
1275 break;
1276 default:
1277 abort ();
1278 }
1279 return x;
1280}
1281
c0f3af97
L		 1282#define CPU_FLAGS_ARCH_MATCH 0x1
1283#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1284#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1285#define CPU_FLAGS_PCLMUL_MATCH 0x8
1286#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1287
a5ff0eb2 1288#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1289 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1290 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1291#define CPU_FLAGS_PERFECT_MATCH \
1292 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1293
1294/* Return CPU flags match bits. */
3629bb00 1295
40fb9820 1296static int
d3ce72d0 1297cpu_flags_match (const insn_template *t)
40fb9820 1298{
c0f3af97
L		 1299 i386_cpu_flags x = t->cpu_flags;
1300 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1301
1302 x.bitfield.cpu64 = 0;
1303 x.bitfield.cpuno64 = 0;
1304
0dfbf9d7 1305 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1306 {
1307 /* This instruction is available on all archs. */
1308 match |= CPU_FLAGS_32BIT_MATCH;
1309 }
3629bb00
L		 1310 else
1311 {
c0f3af97 1312 /* This instruction is available only on some archs. */
3629bb00
L		 1313 i386_cpu_flags cpu = cpu_arch_flags;
1314
1315 cpu.bitfield.cpu64 = 0;
1316 cpu.bitfield.cpuno64 = 0;
1317 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1318 if (!cpu_flags_all_zero (&cpu))
1319 {
a5ff0eb2
L		 1320 if (x.bitfield.cpuavx)
1321 {
ce2f5b3c 1322 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1323 if (cpu.bitfield.cpuavx)
1324 {
1325 /* Check SSE2AVX. */
1326 if (!t->opcode_modifier.sse2avx|| sse2avx)
1327 {
1328 match |= (CPU_FLAGS_ARCH_MATCH
1329 | CPU_FLAGS_AVX_MATCH);
1330 /* Check AES. */
1331 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1332 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1333 /* Check PCLMUL. */
1334 if (!x.bitfield.cpupclmul
1335 || cpu.bitfield.cpupclmul)
1336 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1337 }
1338 }
1339 else
1340 match |= CPU_FLAGS_ARCH_MATCH;
1341 }
1342 else
c0f3af97
L		 1343 match |= CPU_FLAGS_32BIT_MATCH;
1344 }
3629bb00 1345 }
c0f3af97 1346 return match;
40fb9820
L		 1347}
1348
c6fb90c8
L		 1349static INLINE i386_operand_type
1350operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1351{
c6fb90c8
L		 1352 switch (ARRAY_SIZE (x.array))
1353 {
1354 case 3:
1355 x.array [2] &= y.array [2];
1356 case 2:
1357 x.array [1] &= y.array [1];
1358 case 1:
1359 x.array [0] &= y.array [0];
1360 break;
1361 default:
1362 abort ();
1363 }
1364 return x;
40fb9820
L		 1365}
1366
c6fb90c8
L		 1367static INLINE i386_operand_type
1368operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1369{
c6fb90c8 1370 switch (ARRAY_SIZE (x.array))
40fb9820 1371 {
c6fb90c8
L		 1372 case 3:
1373 x.array [2] |= y.array [2];
1374 case 2:
1375 x.array [1] |= y.array [1];
1376 case 1:
1377 x.array [0] |= y.array [0];
40fb9820
L		 1378 break;
1379 default:
1380 abort ();
1381 }
c6fb90c8
L		 1382 return x;
1383}
40fb9820 1384
c6fb90c8
L		 1385static INLINE i386_operand_type
1386operand_type_xor (i386_operand_type x, i386_operand_type y)
1387{
1388 switch (ARRAY_SIZE (x.array))
1389 {
1390 case 3:
1391 x.array [2] ^= y.array [2];
1392 case 2:
1393 x.array [1] ^= y.array [1];
1394 case 1:
1395 x.array [0] ^= y.array [0];
1396 break;
1397 default:
1398 abort ();
1399 }
40fb9820
L		 1400 return x;
1401}
1402
1403static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1404static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1405static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1406static const i386_operand_type inoutportreg
1407 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1408static const i386_operand_type reg16_inoutportreg
1409 = OPERAND_TYPE_REG16_INOUTPORTREG;
1410static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1411static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1412static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1413static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1414static const i386_operand_type anydisp
1415 = OPERAND_TYPE_ANYDISP;
40fb9820 1416static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1417static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
40fb9820
L		 1418static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1419static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1420static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1421static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1422static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1423static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1424static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1425static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1426static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1427
1428enum operand_type
1429{
1430 reg,
40fb9820
L		 1431 imm,
1432 disp,
1433 anymem
1434};
1435
c6fb90c8 1436static INLINE int
40fb9820
L		 1437operand_type_check (i386_operand_type t, enum operand_type c)
1438{
1439 switch (c)
1440 {
1441 case reg:
1442 return (t.bitfield.reg8
1443 || t.bitfield.reg16
1444 || t.bitfield.reg32
1445 || t.bitfield.reg64);
1446
40fb9820
L		 1447 case imm:
1448 return (t.bitfield.imm8
1449 || t.bitfield.imm8s
1450 || t.bitfield.imm16
1451 || t.bitfield.imm32
1452 || t.bitfield.imm32s
1453 || t.bitfield.imm64);
1454
1455 case disp:
1456 return (t.bitfield.disp8
1457 || t.bitfield.disp16
1458 || t.bitfield.disp32
1459 || t.bitfield.disp32s
1460 || t.bitfield.disp64);
1461
1462 case anymem:
1463 return (t.bitfield.disp8
1464 || t.bitfield.disp16
1465 || t.bitfield.disp32
1466 || t.bitfield.disp32s
1467 || t.bitfield.disp64
1468 || t.bitfield.baseindex);
1469
1470 default:
1471 abort ();
1472 }
2cfe26b6
AM		 1473
1474 return 0;
40fb9820
L		 1475}
1476
5c07affc
L		 1477/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1478 operand J for instruction template T. */
1479
1480static INLINE int
d3ce72d0 1481match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1482{
1483 return !((i.types[j].bitfield.byte
1484 && !t->operand_types[j].bitfield.byte)
1485 || (i.types[j].bitfield.word
1486 && !t->operand_types[j].bitfield.word)
1487 || (i.types[j].bitfield.dword
1488 && !t->operand_types[j].bitfield.dword)
1489 || (i.types[j].bitfield.qword
1490 && !t->operand_types[j].bitfield.qword));
1491}
1492
1493/* Return 1 if there is no conflict in any size on operand J for
1494 instruction template T. */
1495
1496static INLINE int
d3ce72d0 1497match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1498{
1499 return (match_reg_size (t, j)
1500 && !((i.types[j].bitfield.unspecified
1501 && !t->operand_types[j].bitfield.unspecified)
1502 || (i.types[j].bitfield.fword
1503 && !t->operand_types[j].bitfield.fword)
1504 || (i.types[j].bitfield.tbyte
1505 && !t->operand_types[j].bitfield.tbyte)
1506 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1507 && !t->operand_types[j].bitfield.xmmword)
1508 || (i.types[j].bitfield.ymmword
1509 && !t->operand_types[j].bitfield.ymmword)));
5c07affc
L		 1510}
1511
1512/* Return 1 if there is no size conflict on any operands for
1513 instruction template T. */
1514
1515static INLINE int
d3ce72d0 1516operand_size_match (const insn_template *t)
5c07affc
L		 1517{
1518 unsigned int j;
1519 int match = 1;
1520
1521 /* Don't check jump instructions. */
1522 if (t->opcode_modifier.jump
1523 || t->opcode_modifier.jumpbyte
1524 || t->opcode_modifier.jumpdword
1525 || t->opcode_modifier.jumpintersegment)
1526 return match;
1527
1528 /* Check memory and accumulator operand size. */
1529 for (j = 0; j < i.operands; j++)
1530 {
1531 if (t->operand_types[j].bitfield.anysize)
1532 continue;
1533
1534 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1535 {
1536 match = 0;
1537 break;
1538 }
1539
1540 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1541 {
1542 match = 0;
1543 break;
1544 }
1545 }
1546
1547 if (match
1548 || (!t->opcode_modifier.d && !t->opcode_modifier.floatd))
1549 return match;
1550
1551 /* Check reverse. */
9c2799c2 1552 gas_assert (i.operands == 2);
5c07affc
L		 1553
1554 match = 1;
1555 for (j = 0; j < 2; j++)
1556 {
1557 if (t->operand_types[j].bitfield.acc
1558 && !match_reg_size (t, j ? 0 : 1))
1559 {
1560 match = 0;
1561 break;
1562 }
1563
1564 if (i.types[j].bitfield.mem
1565 && !match_mem_size (t, j ? 0 : 1))
1566 {
1567 match = 0;
1568 break;
1569 }
1570 }
1571
1572 return match;
1573}
1574
c6fb90c8 1575static INLINE int
40fb9820
L		 1576operand_type_match (i386_operand_type overlap,
1577 i386_operand_type given)
1578{
1579 i386_operand_type temp = overlap;
1580
1581 temp.bitfield.jumpabsolute = 0;
7d5e4556 1582 temp.bitfield.unspecified = 0;
5c07affc
L		 1583 temp.bitfield.byte = 0;
1584 temp.bitfield.word = 0;
1585 temp.bitfield.dword = 0;
1586 temp.bitfield.fword = 0;
1587 temp.bitfield.qword = 0;
1588 temp.bitfield.tbyte = 0;
1589 temp.bitfield.xmmword = 0;
c0f3af97 1590 temp.bitfield.ymmword = 0;
0dfbf9d7 1591 if (operand_type_all_zero (&temp))
40fb9820
L		 1592 return 0;
1593
1594 return (given.bitfield.baseindex == overlap.bitfield.baseindex
1595 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1596}
1597
7d5e4556 1598/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1599 unless the expected operand type register overlap is null.
1600 Note that Acc in a template matches every size of reg. */
1601
c6fb90c8 1602static INLINE int
40fb9820
L		 1603operand_type_register_match (i386_operand_type m0,
1604 i386_operand_type g0,
1605 i386_operand_type t0,
1606 i386_operand_type m1,
1607 i386_operand_type g1,
1608 i386_operand_type t1)
1609{
1610 if (!operand_type_check (g0, reg))
1611 return 1;
1612
1613 if (!operand_type_check (g1, reg))
1614 return 1;
1615
1616 if (g0.bitfield.reg8 == g1.bitfield.reg8
1617 && g0.bitfield.reg16 == g1.bitfield.reg16
1618 && g0.bitfield.reg32 == g1.bitfield.reg32
1619 && g0.bitfield.reg64 == g1.bitfield.reg64)
1620 return 1;
1621
1622 if (m0.bitfield.acc)
1623 {
1624 t0.bitfield.reg8 = 1;
1625 t0.bitfield.reg16 = 1;
1626 t0.bitfield.reg32 = 1;
1627 t0.bitfield.reg64 = 1;
1628 }
1629
1630 if (m1.bitfield.acc)
1631 {
1632 t1.bitfield.reg8 = 1;
1633 t1.bitfield.reg16 = 1;
1634 t1.bitfield.reg32 = 1;
1635 t1.bitfield.reg64 = 1;
1636 }
1637
1638 return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1639 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1640 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1641 && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1642}
1643
252b5132 1644static INLINE unsigned int
40fb9820 1645mode_from_disp_size (i386_operand_type t)
252b5132 1646{
40fb9820
L		 1647 if (t.bitfield.disp8)
1648 return 1;
1649 else if (t.bitfield.disp16
1650 || t.bitfield.disp32
1651 || t.bitfield.disp32s)
1652 return 2;
1653 else
1654 return 0;
252b5132
RH		 1655}
1656
1657static INLINE int
e3bb37b5 1658fits_in_signed_byte (offsetT num)
252b5132
RH		 1659{
1660 return (num >= -128) && (num <= 127);
47926f60 1661}
252b5132
RH		 1662
1663static INLINE int
e3bb37b5 1664fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1665{
1666 return (num & 0xff) == num;
47926f60 1667}
252b5132
RH		 1668
1669static INLINE int
e3bb37b5 1670fits_in_unsigned_word (offsetT num)
252b5132
RH		 1671{
1672 return (num & 0xffff) == num;
47926f60 1673}
252b5132
RH		 1674
1675static INLINE int
e3bb37b5 1676fits_in_signed_word (offsetT num)
252b5132
RH		 1677{
1678 return (-32768 <= num) && (num <= 32767);
47926f60 1679}
2a962e6d 1680
3e73aa7c 1681static INLINE int
e3bb37b5 1682fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1683{
1684#ifndef BFD64
1685 return 1;
1686#else
1687 return (!(((offsetT) -1 << 31) & num)
1688 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1689#endif
1690} /* fits_in_signed_long() */
2a962e6d 1691
3e73aa7c 1692static INLINE int
e3bb37b5 1693fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1694{
1695#ifndef BFD64
1696 return 1;
1697#else
1698 return (num & (((offsetT) 2 << 31) - 1)) == num;
1699#endif
1700} /* fits_in_unsigned_long() */
252b5132 1701
40fb9820 1702static i386_operand_type
e3bb37b5 1703smallest_imm_type (offsetT num)
252b5132 1704{
40fb9820 1705 i386_operand_type t;
7ab9ffdd 1706
0dfbf9d7 1707 operand_type_set (&t, 0);
40fb9820
L		 1708 t.bitfield.imm64 = 1;
1709
1710 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1711 {
1712 /* This code is disabled on the 486 because all the Imm1 forms
1713 in the opcode table are slower on the i486. They're the
1714 versions with the implicitly specified single-position
1715 displacement, which has another syntax if you really want to
1716 use that form. */
40fb9820
L		 1717 t.bitfield.imm1 = 1;
1718 t.bitfield.imm8 = 1;
1719 t.bitfield.imm8s = 1;
1720 t.bitfield.imm16 = 1;
1721 t.bitfield.imm32 = 1;
1722 t.bitfield.imm32s = 1;
1723 }
1724 else if (fits_in_signed_byte (num))
1725 {
1726 t.bitfield.imm8 = 1;
1727 t.bitfield.imm8s = 1;
1728 t.bitfield.imm16 = 1;
1729 t.bitfield.imm32 = 1;
1730 t.bitfield.imm32s = 1;
1731 }
1732 else if (fits_in_unsigned_byte (num))
1733 {
1734 t.bitfield.imm8 = 1;
1735 t.bitfield.imm16 = 1;
1736 t.bitfield.imm32 = 1;
1737 t.bitfield.imm32s = 1;
1738 }
1739 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1740 {
1741 t.bitfield.imm16 = 1;
1742 t.bitfield.imm32 = 1;
1743 t.bitfield.imm32s = 1;
1744 }
1745 else if (fits_in_signed_long (num))
1746 {
1747 t.bitfield.imm32 = 1;
1748 t.bitfield.imm32s = 1;
1749 }
1750 else if (fits_in_unsigned_long (num))
1751 t.bitfield.imm32 = 1;
1752
1753 return t;
47926f60 1754}
252b5132 1755
847f7ad4 1756static offsetT
e3bb37b5 1757offset_in_range (offsetT val, int size)
847f7ad4 1758{
508866be 1759 addressT mask;
ba2adb93 1760
847f7ad4
AM		 1761 switch (size)
1762 {
508866be
L		 1763 case 1: mask = ((addressT) 1 << 8) - 1; break;
1764 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1765 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1766#ifdef BFD64
1767 case 8: mask = ((addressT) 2 << 63) - 1; break;
1768#endif
47926f60 1769 default: abort ();
847f7ad4
AM		 1770 }
1771
9de868bf
L		 1772#ifdef BFD64
1773 /* If BFD64, sign extend val for 32bit address mode. */
1774 if (flag_code != CODE_64BIT
1775 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 1776 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1777 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 1778#endif
ba2adb93 1779
47926f60 1780 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1781 {
1782 char buf1[40], buf2[40];
1783
1784 sprint_value (buf1, val);
1785 sprint_value (buf2, val & mask);
1786 as_warn (_("%s shortened to %s"), buf1, buf2);
1787 }
1788 return val & mask;
1789}
1790
c32fa91d
L		 1791enum PREFIX_GROUP
1792{
1793 PREFIX_EXIST = 0,
1794 PREFIX_LOCK,
1795 PREFIX_REP,
1796 PREFIX_OTHER
1797};
1798
1799/* Returns
1800 a. PREFIX_EXIST if attempting to add a prefix where one from the
1801 same class already exists.
1802 b. PREFIX_LOCK if lock prefix is added.
1803 c. PREFIX_REP if rep/repne prefix is added.
1804 d. PREFIX_OTHER if other prefix is added.
1805 */
1806
1807static enum PREFIX_GROUP
e3bb37b5 1808add_prefix (unsigned int prefix)
252b5132 1809{
c32fa91d 1810 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 1811 unsigned int q;
252b5132 1812
29b0f896
AM		 1813 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1814 && flag_code == CODE_64BIT)
b1905489 1815 {
161a04f6
L		 1816 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1817 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1818 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 1819 ret = PREFIX_EXIST;
b1905489
JB		 1820 q = REX_PREFIX;
1821 }
3e73aa7c 1822 else
b1905489
JB		 1823 {
1824 switch (prefix)
1825 {
1826 default:
1827 abort ();
1828
1829 case CS_PREFIX_OPCODE:
1830 case DS_PREFIX_OPCODE:
1831 case ES_PREFIX_OPCODE:
1832 case FS_PREFIX_OPCODE:
1833 case GS_PREFIX_OPCODE:
1834 case SS_PREFIX_OPCODE:
1835 q = SEG_PREFIX;
1836 break;
1837
1838 case REPNE_PREFIX_OPCODE:
1839 case REPE_PREFIX_OPCODE:
c32fa91d
L		 1840 q = REP_PREFIX;
1841 ret = PREFIX_REP;
1842 break;
1843
b1905489 1844 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 1845 q = LOCK_PREFIX;
1846 ret = PREFIX_LOCK;
b1905489
JB		 1847 break;
1848
1849 case FWAIT_OPCODE:
1850 q = WAIT_PREFIX;
1851 break;
1852
1853 case ADDR_PREFIX_OPCODE:
1854 q = ADDR_PREFIX;
1855 break;
1856
1857 case DATA_PREFIX_OPCODE:
1858 q = DATA_PREFIX;
1859 break;
1860 }
1861 if (i.prefix[q] != 0)
c32fa91d 1862 ret = PREFIX_EXIST;
b1905489 1863 }
252b5132 1864
b1905489 1865 if (ret)
252b5132 1866 {
b1905489
JB		 1867 if (!i.prefix[q])
1868 ++i.prefixes;
1869 i.prefix[q] |= prefix;
252b5132 1870 }
b1905489
JB		 1871 else
1872 as_bad (_("same type of prefix used twice"));
252b5132 1873
252b5132
RH		 1874 return ret;
1875}
1876
1877static void
e3bb37b5 1878set_code_flag (int value)
eecb386c 1879{
1e9cc1c2 1880 flag_code = (enum flag_code) value;
40fb9820
L		 1881 if (flag_code == CODE_64BIT)
1882 {
1883 cpu_arch_flags.bitfield.cpu64 = 1;
1884 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 1885 }
1886 else
1887 {
1888 cpu_arch_flags.bitfield.cpu64 = 0;
1889 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 1890 }
1891 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c
JH		 1892 {
1893 as_bad (_("64bit mode not supported on this CPU."));
1894 }
40fb9820 1895 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c
JH		 1896 {
1897 as_bad (_("32bit mode not supported on this CPU."));
1898 }
eecb386c
AM		 1899 stackop_size = '\0';
1900}
1901
1902static void
e3bb37b5 1903set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1904{
1e9cc1c2 1905 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 1906 if (flag_code != CODE_16BIT)
1907 abort ();
1908 cpu_arch_flags.bitfield.cpu64 = 0;
1909 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 1910 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1911}
1912
1913static void
e3bb37b5 1914set_intel_syntax (int syntax_flag)
252b5132
RH		 1915{
1916 /* Find out if register prefixing is specified. */
1917 int ask_naked_reg = 0;
1918
1919 SKIP_WHITESPACE ();
29b0f896 1920 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1921 {
1922 char *string = input_line_pointer;
1923 int e = get_symbol_end ();
1924
47926f60 1925 if (strcmp (string, "prefix") == 0)
252b5132 1926 ask_naked_reg = 1;
47926f60 1927 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1928 ask_naked_reg = -1;
1929 else
d0b47220 1930 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1931 *input_line_pointer = e;
1932 }
1933 demand_empty_rest_of_line ();
c3332e24 1934
252b5132
RH		 1935 intel_syntax = syntax_flag;
1936
1937 if (ask_naked_reg == 0)
f86103b7
AM		 1938 allow_naked_reg = (intel_syntax
1939 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1940 else
1941 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 1942
ee86248c 1943 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 1944
e4a3b5a4 1945 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 1946 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 1947 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 1948}
1949
1efbbeb4
L		 1950static void
1951set_intel_mnemonic (int mnemonic_flag)
1952{
e1d4d893 1953 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 1954}
1955
db51cc60
L		 1956static void
1957set_allow_index_reg (int flag)
1958{
1959 allow_index_reg = flag;
1960}
1961
cb19c032
L		 1962static void
1963set_sse_check (int dummy ATTRIBUTE_UNUSED)
1964{
1965 SKIP_WHITESPACE ();
1966
1967 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1968 {
1969 char *string = input_line_pointer;
1970 int e = get_symbol_end ();
1971
1972 if (strcmp (string, "none") == 0)
1973 sse_check = sse_check_none;
1974 else if (strcmp (string, "warning") == 0)
1975 sse_check = sse_check_warning;
1976 else if (strcmp (string, "error") == 0)
1977 sse_check = sse_check_error;
1978 else
1979 as_bad (_("bad argument to sse_check directive."));
1980 *input_line_pointer = e;
1981 }
1982 else
1983 as_bad (_("missing argument for sse_check directive"));
1984
1985 demand_empty_rest_of_line ();
1986}
1987
8a9036a4
L		 1988static void
1989check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 1990 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 1991{
1992#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1993 static const char *arch;
1994
1995 /* Intel LIOM is only supported on ELF. */
1996 if (!IS_ELF)
1997 return;
1998
1999 if (!arch)
2000 {
2001 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2002 use default_arch. */
2003 arch = cpu_arch_name;
2004 if (!arch)
2005 arch = default_arch;
2006 }
2007
3632d14b 2008 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2009 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2010 || new_flag.bitfield.cpul1om)
8a9036a4 2011 return;
76ba9986 2012
8a9036a4
L		 2013 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2014#endif
2015}
2016
e413e4e9 2017static void
e3bb37b5 2018set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2019{
47926f60 2020 SKIP_WHITESPACE ();
e413e4e9 2021
29b0f896 2022 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 2023 {
2024 char *string = input_line_pointer;
2025 int e = get_symbol_end ();
9103f4f4 2026 unsigned int i;
40fb9820 2027 i386_cpu_flags flags;
e413e4e9 2028
9103f4f4 2029 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM		 2030 {
2031 if (strcmp (string, cpu_arch[i].name) == 0)
2032 {
8a9036a4
L		 2033 check_cpu_arch_compatible (string, cpu_arch[i].flags);
2034
5c6af06e
JB		 2035 if (*string != '.')
2036 {
2037 cpu_arch_name = cpu_arch[i].name;
2038 cpu_sub_arch_name = NULL;
40fb9820
L		 2039 cpu_arch_flags = cpu_arch[i].flags;
2040 if (flag_code == CODE_64BIT)
2041 {
2042 cpu_arch_flags.bitfield.cpu64 = 1;
2043 cpu_arch_flags.bitfield.cpuno64 = 0;
2044 }
2045 else
2046 {
2047 cpu_arch_flags.bitfield.cpu64 = 0;
2048 cpu_arch_flags.bitfield.cpuno64 = 1;
2049 }
ccc9c027 2050 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 2051 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 2052 if (!cpu_arch_tune_set)
2053 {
2054 cpu_arch_tune = cpu_arch_isa;
2055 cpu_arch_tune_flags = cpu_arch_isa_flags;
2056 }
5c6af06e
JB		 2057 break;
2058 }
40fb9820 2059
309d3373
JB		 2060 if (strncmp (string + 1, "no", 2))
2061 flags = cpu_flags_or (cpu_arch_flags,
2062 cpu_arch[i].flags);
2063 else
2064 flags = cpu_flags_and_not (cpu_arch_flags,
2065 cpu_arch[i].flags);
0dfbf9d7 2066 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2067 {
6305a203
L		 2068 if (cpu_sub_arch_name)
2069 {
2070 char *name = cpu_sub_arch_name;
2071 cpu_sub_arch_name = concat (name,
2072 cpu_arch[i].name,
1bf57e9f 2073 (const char *) NULL);
6305a203
L		 2074 free (name);
2075 }
2076 else
2077 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
40fb9820 2078 cpu_arch_flags = flags;
5c6af06e
JB		 2079 }
2080 *input_line_pointer = e;
2081 demand_empty_rest_of_line ();
2082 return;
e413e4e9
AM		 2083 }
2084 }
9103f4f4 2085 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2086 as_bad (_("no such architecture: `%s'"), string);
2087
2088 *input_line_pointer = e;
2089 }
2090 else
2091 as_bad (_("missing cpu architecture"));
2092
fddf5b5b
AM		 2093 no_cond_jump_promotion = 0;
2094 if (*input_line_pointer == ','
29b0f896 2095 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 2096 {
2097 char *string = ++input_line_pointer;
2098 int e = get_symbol_end ();
2099
2100 if (strcmp (string, "nojumps") == 0)
2101 no_cond_jump_promotion = 1;
2102 else if (strcmp (string, "jumps") == 0)
2103 ;
2104 else
2105 as_bad (_("no such architecture modifier: `%s'"), string);
2106
2107 *input_line_pointer = e;
2108 }
2109
e413e4e9
AM		 2110 demand_empty_rest_of_line ();
2111}
2112
8a9036a4
L		 2113enum bfd_architecture
2114i386_arch (void)
2115{
3632d14b 2116 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2117 {
2118 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2119 || flag_code != CODE_64BIT)
2120 as_fatal (_("Intel L1OM is 64bit ELF only"));
2121 return bfd_arch_l1om;
2122 }
2123 else
2124 return bfd_arch_i386;
2125}
2126
b9d79e03
JH		 2127unsigned long
2128i386_mach ()
2129{
2130 if (!strcmp (default_arch, "x86_64"))
8a9036a4 2131 {
3632d14b 2132 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2133 {
2134 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2135 as_fatal (_("Intel L1OM is 64bit ELF only"));
2136 return bfd_mach_l1om;
2137 }
2138 else
2139 return bfd_mach_x86_64;
2140 }
b9d79e03
JH		 2141 else if (!strcmp (default_arch, "i386"))
2142 return bfd_mach_i386_i386;
2143 else
2144 as_fatal (_("Unknown architecture"));
2145}
b9d79e03 2146\f
252b5132
RH		 2147void
2148md_begin ()
2149{
2150 const char *hash_err;
2151
47926f60 2152 /* Initialize op_hash hash table. */
252b5132
RH		 2153 op_hash = hash_new ();
2154
2155 {
d3ce72d0 2156 const insn_template *optab;
29b0f896 2157 templates *core_optab;
252b5132 2158
47926f60
KH		 2159 /* Setup for loop. */
2160 optab = i386_optab;
252b5132
RH		 2161 core_optab = (templates *) xmalloc (sizeof (templates));
2162 core_optab->start = optab;
2163
2164 while (1)
2165 {
2166 ++optab;
2167 if (optab->name == NULL
2168 || strcmp (optab->name, (optab - 1)->name) != 0)
2169 {
2170 /* different name --> ship out current template list;
47926f60 2171 add to hash table; & begin anew. */
252b5132
RH		 2172 core_optab->end = optab;
2173 hash_err = hash_insert (op_hash,
2174 (optab - 1)->name,
5a49b8ac 2175 (void *) core_optab);
252b5132
RH		 2176 if (hash_err)
2177 {
252b5132
RH		 2178 as_fatal (_("Internal Error: Can't hash %s: %s"),
2179 (optab - 1)->name,
2180 hash_err);
2181 }
2182 if (optab->name == NULL)
2183 break;
2184 core_optab = (templates *) xmalloc (sizeof (templates));
2185 core_optab->start = optab;
2186 }
2187 }
2188 }
2189
47926f60 2190 /* Initialize reg_hash hash table. */
252b5132
RH		 2191 reg_hash = hash_new ();
2192 {
29b0f896 2193 const reg_entry *regtab;
c3fe08fa 2194 unsigned int regtab_size = i386_regtab_size;
252b5132 2195
c3fe08fa 2196 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2197 {
5a49b8ac 2198 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2199 if (hash_err)
3e73aa7c
JH		 2200 as_fatal (_("Internal Error: Can't hash %s: %s"),
2201 regtab->reg_name,
2202 hash_err);
252b5132
RH		 2203 }
2204 }
2205
47926f60 2206 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2207 {
29b0f896
AM		 2208 int c;
2209 char *p;
252b5132
RH		 2210
2211 for (c = 0; c < 256; c++)
2212 {
3882b010 2213 if (ISDIGIT (c))
252b5132
RH		 2214 {
2215 digit_chars[c] = c;
2216 mnemonic_chars[c] = c;
2217 register_chars[c] = c;
2218 operand_chars[c] = c;
2219 }
3882b010 2220 else if (ISLOWER (c))
252b5132
RH		 2221 {
2222 mnemonic_chars[c] = c;
2223 register_chars[c] = c;
2224 operand_chars[c] = c;
2225 }
3882b010 2226 else if (ISUPPER (c))
252b5132 2227 {
3882b010 2228 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2229 register_chars[c] = mnemonic_chars[c];
2230 operand_chars[c] = c;
2231 }
2232
3882b010 2233 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2234 identifier_chars[c] = c;
2235 else if (c >= 128)
2236 {
2237 identifier_chars[c] = c;
2238 operand_chars[c] = c;
2239 }
2240 }
2241
2242#ifdef LEX_AT
2243 identifier_chars['@'] = '@';
32137342
NC		 2244#endif
2245#ifdef LEX_QM
2246 identifier_chars['?'] = '?';
2247 operand_chars['?'] = '?';
252b5132 2248#endif
252b5132 2249 digit_chars['-'] = '-';
c0f3af97 2250 mnemonic_chars['_'] = '_';
791fe849 2251 mnemonic_chars['-'] = '-';
0003779b 2252 mnemonic_chars['.'] = '.';
252b5132
RH		 2253 identifier_chars['_'] = '_';
2254 identifier_chars['.'] = '.';
2255
2256 for (p = operand_special_chars; *p != '\0'; p++)
2257 operand_chars[(unsigned char) *p] = *p;
2258 }
2259
2260#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2261 if (IS_ELF)
252b5132
RH		 2262 {
2263 record_alignment (text_section, 2);
2264 record_alignment (data_section, 2);
2265 record_alignment (bss_section, 2);
2266 }
2267#endif
a4447b93
RH		 2268
2269 if (flag_code == CODE_64BIT)
2270 {
2271 x86_dwarf2_return_column = 16;
2272 x86_cie_data_alignment = -8;
2273 }
2274 else
2275 {
2276 x86_dwarf2_return_column = 8;
2277 x86_cie_data_alignment = -4;
2278 }
252b5132
RH		 2279}
2280
2281void
e3bb37b5 2282i386_print_statistics (FILE *file)
252b5132
RH		 2283{
2284 hash_print_statistics (file, "i386 opcode", op_hash);
2285 hash_print_statistics (file, "i386 register", reg_hash);
2286}
2287\f
252b5132
RH		 2288#ifdef DEBUG386
2289
ce8a8b2f 2290/* Debugging routines for md_assemble. */
d3ce72d0 2291static void pte (insn_template *);
40fb9820 2292static void pt (i386_operand_type);
e3bb37b5
L		 2293static void pe (expressionS *);
2294static void ps (symbolS *);
252b5132
RH		 2295
2296static void
e3bb37b5 2297pi (char *line, i386_insn *x)
252b5132 2298{
09f131f2 2299 unsigned int i;
252b5132
RH		 2300
2301 fprintf (stdout, "%s: template ", line);
2302 pte (&x->tm);
09f131f2
JH		 2303 fprintf (stdout, " address: base %s index %s scale %x\n",
2304 x->base_reg ? x->base_reg->reg_name : "none",
2305 x->index_reg ? x->index_reg->reg_name : "none",
2306 x->log2_scale_factor);
2307 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2308 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2309 fprintf (stdout, " sib: base %x index %x scale %x\n",
2310 x->sib.base, x->sib.index, x->sib.scale);
2311 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2312 (x->rex & REX_W) != 0,
2313 (x->rex & REX_R) != 0,
2314 (x->rex & REX_X) != 0,
2315 (x->rex & REX_B) != 0);
252b5132
RH		 2316 for (i = 0; i < x->operands; i++)
2317 {
2318 fprintf (stdout, " #%d: ", i + 1);
2319 pt (x->types[i]);
2320 fprintf (stdout, "\n");
40fb9820
L		 2321 if (x->types[i].bitfield.reg8
2322 || x->types[i].bitfield.reg16
2323 || x->types[i].bitfield.reg32
2324 || x->types[i].bitfield.reg64
2325 || x->types[i].bitfield.regmmx
2326 || x->types[i].bitfield.regxmm
c0f3af97 2327 || x->types[i].bitfield.regymm
40fb9820
L		 2328 || x->types[i].bitfield.sreg2
2329 || x->types[i].bitfield.sreg3
2330 || x->types[i].bitfield.control
2331 || x->types[i].bitfield.debug
2332 || x->types[i].bitfield.test)
520dc8e8 2333 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
40fb9820 2334 if (operand_type_check (x->types[i], imm))
520dc8e8 2335 pe (x->op[i].imms);
40fb9820 2336 if (operand_type_check (x->types[i], disp))
520dc8e8 2337 pe (x->op[i].disps);
252b5132
RH		 2338 }
2339}
2340
2341static void
d3ce72d0 2342pte (insn_template *t)
252b5132 2343{
09f131f2 2344 unsigned int i;
252b5132 2345 fprintf (stdout, " %d operands ", t->operands);
47926f60 2346 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2347 if (t->extension_opcode != None)
2348 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2349 if (t->opcode_modifier.d)
252b5132 2350 fprintf (stdout, "D");
40fb9820 2351 if (t->opcode_modifier.w)
252b5132
RH		 2352 fprintf (stdout, "W");
2353 fprintf (stdout, "\n");
2354 for (i = 0; i < t->operands; i++)
2355 {
2356 fprintf (stdout, " #%d type ", i + 1);
2357 pt (t->operand_types[i]);
2358 fprintf (stdout, "\n");
2359 }
2360}
2361
2362static void
e3bb37b5 2363pe (expressionS *e)
252b5132 2364{
24eab124 2365 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2366 fprintf (stdout, " add_number %ld (%lx)\n",
2367 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2368 if (e->X_add_symbol)
2369 {
2370 fprintf (stdout, " add_symbol ");
2371 ps (e->X_add_symbol);
2372 fprintf (stdout, "\n");
2373 }
2374 if (e->X_op_symbol)
2375 {
2376 fprintf (stdout, " op_symbol ");
2377 ps (e->X_op_symbol);
2378 fprintf (stdout, "\n");
2379 }
2380}
2381
2382static void
e3bb37b5 2383ps (symbolS *s)
252b5132
RH		 2384{
2385 fprintf (stdout, "%s type %s%s",
2386 S_GET_NAME (s),
2387 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2388 segment_name (S_GET_SEGMENT (s)));
2389}
2390
7b81dfbb 2391static struct type_name
252b5132 2392 {
40fb9820
L		 2393 i386_operand_type mask;
2394 const char *name;
252b5132 2395 }
7b81dfbb 2396const type_names[] =
252b5132 2397{
40fb9820
L		 2398 { OPERAND_TYPE_REG8, "r8" },
2399 { OPERAND_TYPE_REG16, "r16" },
2400 { OPERAND_TYPE_REG32, "r32" },
2401 { OPERAND_TYPE_REG64, "r64" },
2402 { OPERAND_TYPE_IMM8, "i8" },
2403 { OPERAND_TYPE_IMM8, "i8s" },
2404 { OPERAND_TYPE_IMM16, "i16" },
2405 { OPERAND_TYPE_IMM32, "i32" },
2406 { OPERAND_TYPE_IMM32S, "i32s" },
2407 { OPERAND_TYPE_IMM64, "i64" },
2408 { OPERAND_TYPE_IMM1, "i1" },
2409 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2410 { OPERAND_TYPE_DISP8, "d8" },
2411 { OPERAND_TYPE_DISP16, "d16" },
2412 { OPERAND_TYPE_DISP32, "d32" },
2413 { OPERAND_TYPE_DISP32S, "d32s" },
2414 { OPERAND_TYPE_DISP64, "d64" },
2415 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2416 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2417 { OPERAND_TYPE_CONTROL, "control reg" },
2418 { OPERAND_TYPE_TEST, "test reg" },
2419 { OPERAND_TYPE_DEBUG, "debug reg" },
2420 { OPERAND_TYPE_FLOATREG, "FReg" },
2421 { OPERAND_TYPE_FLOATACC, "FAcc" },
2422 { OPERAND_TYPE_SREG2, "SReg2" },
2423 { OPERAND_TYPE_SREG3, "SReg3" },
2424 { OPERAND_TYPE_ACC, "Acc" },
2425 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2426 { OPERAND_TYPE_REGMMX, "rMMX" },
2427 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2428 { OPERAND_TYPE_REGYMM, "rYMM" },
40fb9820 2429 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2430};
2431
2432static void
40fb9820 2433pt (i386_operand_type t)
252b5132 2434{
40fb9820 2435 unsigned int j;
c6fb90c8 2436 i386_operand_type a;
252b5132 2437
40fb9820 2438 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2439 {
2440 a = operand_type_and (t, type_names[j].mask);
0349dc08 2441 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2442 fprintf (stdout, "%s, ", type_names[j].name);
2443 }
252b5132
RH		 2444 fflush (stdout);
2445}
2446
2447#endif /* DEBUG386 */
2448\f
252b5132 2449static bfd_reloc_code_real_type
3956db08 2450reloc (unsigned int size,
64e74474
AM		 2451 int pcrel,
2452 int sign,
2453 bfd_reloc_code_real_type other)
252b5132 2454{
47926f60 2455 if (other != NO_RELOC)
3956db08
JB		 2456 {
2457 reloc_howto_type *reloc;
2458
2459 if (size == 8)
2460 switch (other)
2461 {
64e74474
AM		 2462 case BFD_RELOC_X86_64_GOT32:
2463 return BFD_RELOC_X86_64_GOT64;
2464 break;
2465 case BFD_RELOC_X86_64_PLTOFF64:
2466 return BFD_RELOC_X86_64_PLTOFF64;
2467 break;
2468 case BFD_RELOC_X86_64_GOTPC32:
2469 other = BFD_RELOC_X86_64_GOTPC64;
2470 break;
2471 case BFD_RELOC_X86_64_GOTPCREL:
2472 other = BFD_RELOC_X86_64_GOTPCREL64;
2473 break;
2474 case BFD_RELOC_X86_64_TPOFF32:
2475 other = BFD_RELOC_X86_64_TPOFF64;
2476 break;
2477 case BFD_RELOC_X86_64_DTPOFF32:
2478 other = BFD_RELOC_X86_64_DTPOFF64;
2479 break;
2480 default:
2481 break;
3956db08 2482 }
e05278af
JB		 2483
2484 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2485 if (size == 4 && flag_code != CODE_64BIT)
2486 sign = -1;
2487
3956db08
JB		 2488 reloc = bfd_reloc_type_lookup (stdoutput, other);
2489 if (!reloc)
2490 as_bad (_("unknown relocation (%u)"), other);
2491 else if (size != bfd_get_reloc_size (reloc))
2492 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2493 bfd_get_reloc_size (reloc),
2494 size);
2495 else if (pcrel && !reloc->pc_relative)
2496 as_bad (_("non-pc-relative relocation for pc-relative field"));
2497 else if ((reloc->complain_on_overflow == complain_overflow_signed
2498 && !sign)
2499 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 2500 && sign > 0))
3956db08
JB		 2501 as_bad (_("relocated field and relocation type differ in signedness"));
2502 else
2503 return other;
2504 return NO_RELOC;
2505 }
252b5132
RH		 2506
2507 if (pcrel)
2508 {
3e73aa7c 2509 if (!sign)
3956db08 2510 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2511 switch (size)
2512 {
2513 case 1: return BFD_RELOC_8_PCREL;
2514 case 2: return BFD_RELOC_16_PCREL;
2515 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2516 case 8: return BFD_RELOC_64_PCREL;
252b5132 2517 }
3956db08 2518 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2519 }
2520 else
2521 {
3956db08 2522 if (sign > 0)
e5cb08ac 2523 switch (size)
3e73aa7c
JH		 2524 {
2525 case 4: return BFD_RELOC_X86_64_32S;
2526 }
2527 else
2528 switch (size)
2529 {
2530 case 1: return BFD_RELOC_8;
2531 case 2: return BFD_RELOC_16;
2532 case 4: return BFD_RELOC_32;
2533 case 8: return BFD_RELOC_64;
2534 }
3956db08
JB		 2535 as_bad (_("cannot do %s %u byte relocation"),
2536 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2537 }
2538
0cc9e1d3 2539 return NO_RELOC;
252b5132
RH		 2540}
2541
47926f60
KH		 2542/* Here we decide which fixups can be adjusted to make them relative to
2543 the beginning of the section instead of the symbol. Basically we need
2544 to make sure that the dynamic relocations are done correctly, so in
2545 some cases we force the original symbol to be used. */
2546
252b5132 2547int
e3bb37b5 2548tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2549{
6d249963 2550#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2551 if (!IS_ELF)
31312f95
AM		 2552 return 1;
2553
a161fe53
AM		 2554 /* Don't adjust pc-relative references to merge sections in 64-bit
2555 mode. */
2556 if (use_rela_relocations
2557 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2558 && fixP->fx_pcrel)
252b5132 2559 return 0;
31312f95 2560
8d01d9a9
AJ		 2561 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2562 and changed later by validate_fix. */
2563 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2564 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2565 return 0;
2566
ce8a8b2f 2567 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 2568 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2569 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2570 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2571 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2572 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2573 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2574 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2575 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2576 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2577 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2578 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2579 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2580 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2581 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2582 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2583 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2584 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2585 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2586 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2587 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2588 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2589 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2590 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2591 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2592 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2593 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2594 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2595 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2596 return 0;
31312f95 2597#endif
252b5132
RH		 2598 return 1;
2599}
252b5132 2600
b4cac588 2601static int
e3bb37b5 2602intel_float_operand (const char *mnemonic)
252b5132 2603{
9306ca4a
JB		 2604 /* Note that the value returned is meaningful only for opcodes with (memory)
2605 operands, hence the code here is free to improperly handle opcodes that
2606 have no operands (for better performance and smaller code). */
2607
2608 if (mnemonic[0] != 'f')
2609 return 0; /* non-math */
2610
2611 switch (mnemonic[1])
2612 {
2613 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2614 the fs segment override prefix not currently handled because no
2615 call path can make opcodes without operands get here */
2616 case 'i':
2617 return 2 /* integer op */;
2618 case 'l':
2619 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2620 return 3; /* fldcw/fldenv */
2621 break;
2622 case 'n':
2623 if (mnemonic[2] != 'o' /* fnop */)
2624 return 3; /* non-waiting control op */
2625 break;
2626 case 'r':
2627 if (mnemonic[2] == 's')
2628 return 3; /* frstor/frstpm */
2629 break;
2630 case 's':
2631 if (mnemonic[2] == 'a')
2632 return 3; /* fsave */
2633 if (mnemonic[2] == 't')
2634 {
2635 switch (mnemonic[3])
2636 {
2637 case 'c': /* fstcw */
2638 case 'd': /* fstdw */
2639 case 'e': /* fstenv */
2640 case 's': /* fsts[gw] */
2641 return 3;
2642 }
2643 }
2644 break;
2645 case 'x':
2646 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2647 return 0; /* fxsave/fxrstor are not really math ops */
2648 break;
2649 }
252b5132 2650
9306ca4a 2651 return 1;
252b5132
RH		 2652}
2653
c0f3af97
L		 2654/* Build the VEX prefix. */
2655
2656static void
d3ce72d0 2657build_vex_prefix (const insn_template *t)
c0f3af97
L		 2658{
2659 unsigned int register_specifier;
2660 unsigned int implied_prefix;
2661 unsigned int vector_length;
2662
2663 /* Check register specifier. */
2664 if (i.vex.register_specifier)
2665 {
2666 register_specifier = i.vex.register_specifier->reg_num;
2667 if ((i.vex.register_specifier->reg_flags & RegRex))
2668 register_specifier += 8;
2669 register_specifier = ~register_specifier & 0xf;
2670 }
2671 else
2672 register_specifier = 0xf;
2673
fa99fab2
L		 2674 /* Use 2-byte VEX prefix by swappping destination and source
2675 operand. */
2676 if (!i.swap_operand
2677 && i.operands == i.reg_operands
2678 && i.tm.opcode_modifier.vex0f
2679 && i.tm.opcode_modifier.s
2680 && i.rex == REX_B)
2681 {
2682 unsigned int xchg = i.operands - 1;
2683 union i386_op temp_op;
2684 i386_operand_type temp_type;
2685
2686 temp_type = i.types[xchg];
2687 i.types[xchg] = i.types[0];
2688 i.types[0] = temp_type;
2689 temp_op = i.op[xchg];
2690 i.op[xchg] = i.op[0];
2691 i.op[0] = temp_op;
2692
9c2799c2 2693 gas_assert (i.rm.mode == 3);
fa99fab2
L		 2694
2695 i.rex = REX_R;
2696 xchg = i.rm.regmem;
2697 i.rm.regmem = i.rm.reg;
2698 i.rm.reg = xchg;
2699
2700 /* Use the next insn. */
2701 i.tm = t[1];
2702 }
2703
2bf05e57 2704 vector_length = i.tm.opcode_modifier.vex == 2 ? 1 : 0;
c0f3af97
L		 2705
2706 switch ((i.tm.base_opcode >> 8) & 0xff)
2707 {
2708 case 0:
2709 implied_prefix = 0;
2710 break;
2711 case DATA_PREFIX_OPCODE:
2712 implied_prefix = 1;
2713 break;
2714 case REPE_PREFIX_OPCODE:
2715 implied_prefix = 2;
2716 break;
2717 case REPNE_PREFIX_OPCODE:
2718 implied_prefix = 3;
2719 break;
2720 default:
2721 abort ();
2722 }
2723
2724 /* Use 2-byte VEX prefix if possible. */
2725 if (i.tm.opcode_modifier.vex0f
2726 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
2727 {
2728 /* 2-byte VEX prefix. */
2729 unsigned int r;
2730
2731 i.vex.length = 2;
2732 i.vex.bytes[0] = 0xc5;
2733
2734 /* Check the REX.R bit. */
2735 r = (i.rex & REX_R) ? 0 : 1;
2736 i.vex.bytes[1] = (r << 7
2737 | register_specifier << 3
2738 | vector_length << 2
2739 | implied_prefix);
2740 }
2741 else
2742 {
2743 /* 3-byte VEX prefix. */
2744 unsigned int m, w;
2745
f88c9eb0
SP		 2746 i.vex.length = 3;
2747 i.vex.bytes[0] = 0xc4;
2748
c0f3af97
L		 2749 if (i.tm.opcode_modifier.vex0f)
2750 m = 0x1;
2751 else if (i.tm.opcode_modifier.vex0f38)
2752 m = 0x2;
2753 else if (i.tm.opcode_modifier.vex0f3a)
2754 m = 0x3;
5dd85c99
SP		 2755 else if (i.tm.opcode_modifier.xop08)
2756 {
2757 m = 0x8;
2758 i.vex.bytes[0] = 0x8f;
2759 }
f88c9eb0
SP		 2760 else if (i.tm.opcode_modifier.xop09)
2761 {
2762 m = 0x9;
2763 i.vex.bytes[0] = 0x8f;
2764 }
2765 else if (i.tm.opcode_modifier.xop0a)
2766 {
2767 m = 0xa;
2768 i.vex.bytes[0] = 0x8f;
2769 }
c0f3af97
L		 2770 else
2771 abort ();
2772
c0f3af97
L		 2773 /* The high 3 bits of the second VEX byte are 1's compliment
2774 of RXB bits from REX. */
2775 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
2776
2777 /* Check the REX.W bit. */
2778 w = (i.rex & REX_W) ? 1 : 0;
2779 if (i.tm.opcode_modifier.vexw0 || i.tm.opcode_modifier.vexw1)
2780 {
2781 if (w)
2782 abort ();
2783
2784 if (i.tm.opcode_modifier.vexw1)
2785 w = 1;
2786 }
2787
2788 i.vex.bytes[2] = (w << 7
2789 | register_specifier << 3
2790 | vector_length << 2
2791 | implied_prefix);
2792 }
2793}
2794
65da13b5
L		 2795static void
2796process_immext (void)
2797{
2798 expressionS *exp;
2799
2800 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2801 {
1fed0ba1
L		 2802 /* SSE3 Instructions have the fixed operands with an opcode
2803 suffix which is coded in the same place as an 8-bit immediate
2804 field would be. Here we check those operands and remove them
2805 afterwards. */
65da13b5
L		 2806 unsigned int x;
2807
2808 for (x = 0; x < i.operands; x++)
2809 if (i.op[x].regs->reg_num != x)
2810 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 2811 register_prefix, i.op[x].regs->reg_name, x + 1,
2812 i.tm.name);
2813
2814 i.operands = 0;
65da13b5
L		 2815 }
2816
c0f3af97 2817 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 2818 which is coded in the same place as an 8-bit immediate field
2819 would be. Here we fake an 8-bit immediate operand from the
2820 opcode suffix stored in tm.extension_opcode.
2821
c1e679ec 2822 AVX instructions also use this encoding, for some of
c0f3af97 2823 3 argument instructions. */
65da13b5 2824
9c2799c2 2825 gas_assert (i.imm_operands == 0
7ab9ffdd
L		 2826 && (i.operands <= 2
2827 || (i.tm.opcode_modifier.vex
2828 && i.operands <= 4)));
65da13b5
L		 2829
2830 exp = &im_expressions[i.imm_operands++];
2831 i.op[i.operands].imms = exp;
2832 i.types[i.operands] = imm8;
2833 i.operands++;
2834 exp->X_op = O_constant;
2835 exp->X_add_number = i.tm.extension_opcode;
2836 i.tm.extension_opcode = None;
2837}
2838
252b5132
RH		 2839/* This is the guts of the machine-dependent assembler. LINE points to a
2840 machine dependent instruction. This function is supposed to emit
2841 the frags/bytes it assembles to. */
2842
2843void
65da13b5 2844md_assemble (char *line)
252b5132 2845{
40fb9820 2846 unsigned int j;
252b5132 2847 char mnemonic[MAX_MNEM_SIZE];
d3ce72d0 2848 const insn_template *t;
252b5132 2849
47926f60 2850 /* Initialize globals. */
252b5132
RH		 2851 memset (&i, '\0', sizeof (i));
2852 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 2853 i.reloc[j] = NO_RELOC;
252b5132
RH		 2854 memset (disp_expressions, '\0', sizeof (disp_expressions));
2855 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 2856 save_stack_p = save_stack;
252b5132
RH		 2857
2858 /* First parse an instruction mnemonic & call i386_operand for the operands.
2859 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 2860 start of a (possibly prefixed) mnemonic. */
252b5132 2861
29b0f896
AM		 2862 line = parse_insn (line, mnemonic);
2863 if (line == NULL)
2864 return;
252b5132 2865
29b0f896 2866 line = parse_operands (line, mnemonic);
ee86248c 2867 this_operand = -1;
29b0f896
AM		 2868 if (line == NULL)
2869 return;
252b5132 2870
29b0f896
AM		 2871 /* Now we've parsed the mnemonic into a set of templates, and have the
2872 operands at hand. */
2873
2874 /* All intel opcodes have reversed operands except for "bound" and
2875 "enter". We also don't reverse intersegment "jmp" and "call"
2876 instructions with 2 immediate operands so that the immediate segment
050dfa73 2877 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 2878 if (intel_syntax
2879 && i.operands > 1
29b0f896 2880 && (strcmp (mnemonic, "bound") != 0)
30123838 2881 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 2882 && !(operand_type_check (i.types[0], imm)
2883 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 2884 swap_operands ();
2885
ec56d5c0
JB		 2886 /* The order of the immediates should be reversed
2887 for 2 immediates extrq and insertq instructions */
2888 if (i.imm_operands == 2
2889 && (strcmp (mnemonic, "extrq") == 0
2890 || strcmp (mnemonic, "insertq") == 0))
2891 swap_2_operands (0, 1);
2892
29b0f896
AM		 2893 if (i.imm_operands)
2894 optimize_imm ();
2895
b300c311
L		 2896 /* Don't optimize displacement for movabs since it only takes 64bit
2897 displacement. */
2898 if (i.disp_operands
2899 && (flag_code != CODE_64BIT
2900 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 2901 optimize_disp ();
2902
2903 /* Next, we find a template that matches the given insn,
2904 making sure the overlap of the given operands types is consistent
2905 with the template operand types. */
252b5132 2906
fa99fab2 2907 if (!(t = match_template ()))
29b0f896 2908 return;
252b5132 2909
daf50ae7 2910 if (sse_check != sse_check_none
81f8a913 2911 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 2912 && (i.tm.cpu_flags.bitfield.cpusse
2913 || i.tm.cpu_flags.bitfield.cpusse2
2914 || i.tm.cpu_flags.bitfield.cpusse3
2915 || i.tm.cpu_flags.bitfield.cpussse3
2916 || i.tm.cpu_flags.bitfield.cpusse4_1
2917 || i.tm.cpu_flags.bitfield.cpusse4_2))
2918 {
2919 (sse_check == sse_check_warning
2920 ? as_warn
2921 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
2922 }
2923
321fd21e
L		 2924 /* Zap movzx and movsx suffix. The suffix has been set from
2925 "word ptr" or "byte ptr" on the source operand in Intel syntax
2926 or extracted from mnemonic in AT&T syntax. But we'll use
2927 the destination register to choose the suffix for encoding. */
2928 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 2929 {
321fd21e
L		 2930 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2931 there is no suffix, the default will be byte extension. */
2932 if (i.reg_operands != 2
2933 && !i.suffix
7ab9ffdd 2934 && intel_syntax)
321fd21e
L		 2935 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2936
2937 i.suffix = 0;
cd61ebfe 2938 }
24eab124 2939
40fb9820 2940 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 2941 if (!add_prefix (FWAIT_OPCODE))
2942 return;
252b5132 2943
c1ba0266
L		 2944 /* Check for lock without a lockable instruction. Destination operand
2945 must be memory unless it is xchg (0x86). */
c32fa91d
L		 2946 if (i.prefix[LOCK_PREFIX]
2947 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 2948 || i.mem_operands == 0
2949 || (i.tm.base_opcode != 0x86
2950 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 2951 {
2952 as_bad (_("expecting lockable instruction after `lock'"));
2953 return;
2954 }
2955
29b0f896 2956 /* Check string instruction segment overrides. */
40fb9820 2957 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 2958 {
2959 if (!check_string ())
5dd0794d 2960 return;
fc0763e6 2961 i.disp_operands = 0;
29b0f896 2962 }
5dd0794d 2963
29b0f896
AM		 2964 if (!process_suffix ())
2965 return;
e413e4e9 2966
bc0844ae
L		 2967 /* Update operand types. */
2968 for (j = 0; j < i.operands; j++)
2969 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
2970
29b0f896
AM		 2971 /* Make still unresolved immediate matches conform to size of immediate
2972 given in i.suffix. */
2973 if (!finalize_imm ())
2974 return;
252b5132 2975
40fb9820 2976 if (i.types[0].bitfield.imm1)
29b0f896 2977 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 2978
9afe6eb8
L		 2979 /* We only need to check those implicit registers for instructions
2980 with 3 operands or less. */
2981 if (i.operands <= 3)
2982 for (j = 0; j < i.operands; j++)
2983 if (i.types[j].bitfield.inoutportreg
2984 || i.types[j].bitfield.shiftcount
2985 || i.types[j].bitfield.acc
2986 || i.types[j].bitfield.floatacc)
2987 i.reg_operands--;
40fb9820 2988
c0f3af97
L		 2989 /* ImmExt should be processed after SSE2AVX. */
2990 if (!i.tm.opcode_modifier.sse2avx
2991 && i.tm.opcode_modifier.immext)
65da13b5 2992 process_immext ();
252b5132 2993
29b0f896
AM		 2994 /* For insns with operands there are more diddles to do to the opcode. */
2995 if (i.operands)
2996 {
2997 if (!process_operands ())
2998 return;
2999 }
40fb9820 3000 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3001 {
3002 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3003 as_warn (_("translating to `%sp'"), i.tm.name);
3004 }
252b5132 3005
c0f3af97 3006 if (i.tm.opcode_modifier.vex)
fa99fab2 3007 build_vex_prefix (t);
c0f3af97 3008
5dd85c99
SP		 3009 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3010 instructions may define INT_OPCODE as well, so avoid this corner
3011 case for those instructions that use MODRM. */
3012 if (i.tm.base_opcode == INT_OPCODE
3013 && i.op[0].imms->X_add_number == 3
3014 && !i.tm.opcode_modifier.modrm)
29b0f896
AM		 3015 {
3016 i.tm.base_opcode = INT3_OPCODE;
3017 i.imm_operands = 0;
3018 }
252b5132 3019
40fb9820
L		 3020 if ((i.tm.opcode_modifier.jump
3021 || i.tm.opcode_modifier.jumpbyte
3022 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3023 && i.op[0].disps->X_op == O_constant)
3024 {
3025 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3026 the absolute address given by the constant. Since ix86 jumps and
3027 calls are pc relative, we need to generate a reloc. */
3028 i.op[0].disps->X_add_symbol = &abs_symbol;
3029 i.op[0].disps->X_op = O_symbol;
3030 }
252b5132 3031
40fb9820 3032 if (i.tm.opcode_modifier.rex64)
161a04f6 3033 i.rex |= REX_W;
252b5132 3034
29b0f896
AM		 3035 /* For 8 bit registers we need an empty rex prefix. Also if the
3036 instruction already has a prefix, we need to convert old
3037 registers to new ones. */
773f551c 3038
40fb9820 3039 if ((i.types[0].bitfield.reg8
29b0f896 3040 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3041 || (i.types[1].bitfield.reg8
29b0f896 3042 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3043 || ((i.types[0].bitfield.reg8
3044 || i.types[1].bitfield.reg8)
29b0f896
AM		 3045 && i.rex != 0))
3046 {
3047 int x;
726c5dcd 3048
29b0f896
AM		 3049 i.rex |= REX_OPCODE;
3050 for (x = 0; x < 2; x++)
3051 {
3052 /* Look for 8 bit operand that uses old registers. */
40fb9820 3053 if (i.types[x].bitfield.reg8
29b0f896 3054 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3055 {
29b0f896
AM		 3056 /* In case it is "hi" register, give up. */
3057 if (i.op[x].regs->reg_num > 3)
a540244d 3058 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3059 "instruction requiring REX prefix."),
a540244d 3060 register_prefix, i.op[x].regs->reg_name);
773f551c 3061
29b0f896
AM		 3062 /* Otherwise it is equivalent to the extended register.
3063 Since the encoding doesn't change this is merely
3064 cosmetic cleanup for debug output. */
3065
3066 i.op[x].regs = i.op[x].regs + 8;
773f551c 3067 }
29b0f896
AM		 3068 }
3069 }
773f551c 3070
7ab9ffdd 3071 if (i.rex != 0)
29b0f896
AM		 3072 add_prefix (REX_OPCODE | i.rex);
3073
3074 /* We are ready to output the insn. */
3075 output_insn ();
3076}
3077
3078static char *
e3bb37b5 3079parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3080{
3081 char *l = line;
3082 char *token_start = l;
3083 char *mnem_p;
5c6af06e 3084 int supported;
d3ce72d0 3085 const insn_template *t;
b6169b20 3086 char *dot_p = NULL;
29b0f896
AM		 3087
3088 /* Non-zero if we found a prefix only acceptable with string insns. */
3089 const char *expecting_string_instruction = NULL;
45288df1 3090
29b0f896
AM		 3091 while (1)
3092 {
3093 mnem_p = mnemonic;
3094 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3095 {
b6169b20
L		 3096 if (*mnem_p == '.')
3097 dot_p = mnem_p;
29b0f896
AM		 3098 mnem_p++;
3099 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3100 {
29b0f896
AM		 3101 as_bad (_("no such instruction: `%s'"), token_start);
3102 return NULL;
3103 }
3104 l++;
3105 }
3106 if (!is_space_char (*l)
3107 && *l != END_OF_INSN
e44823cf
JB		 3108 && (intel_syntax
3109 || (*l != PREFIX_SEPARATOR
3110 && *l != ',')))
29b0f896
AM		 3111 {
3112 as_bad (_("invalid character %s in mnemonic"),
3113 output_invalid (*l));
3114 return NULL;
3115 }
3116 if (token_start == l)
3117 {
e44823cf 3118 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3119 as_bad (_("expecting prefix; got nothing"));
3120 else
3121 as_bad (_("expecting mnemonic; got nothing"));
3122 return NULL;
3123 }
45288df1 3124
29b0f896 3125 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3126 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3127
29b0f896
AM		 3128 if (*l != END_OF_INSN
3129 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3130 && current_templates
40fb9820 3131 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3132 {
c6fb90c8 3133 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3134 {
3135 as_bad ((flag_code != CODE_64BIT
3136 ? _("`%s' is only supported in 64-bit mode")
3137 : _("`%s' is not supported in 64-bit mode")),
3138 current_templates->start->name);
3139 return NULL;
3140 }
29b0f896
AM		 3141 /* If we are in 16-bit mode, do not allow addr16 or data16.
3142 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3143 if ((current_templates->start->opcode_modifier.size16
3144 || current_templates->start->opcode_modifier.size32)
29b0f896 3145 && flag_code != CODE_64BIT
40fb9820 3146 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3147 ^ (flag_code == CODE_16BIT)))
3148 {
3149 as_bad (_("redundant %s prefix"),
3150 current_templates->start->name);
3151 return NULL;
45288df1 3152 }
29b0f896
AM		 3153 /* Add prefix, checking for repeated prefixes. */
3154 switch (add_prefix (current_templates->start->base_opcode))
3155 {
c32fa91d 3156 case PREFIX_EXIST:
29b0f896 3157 return NULL;
c32fa91d 3158 case PREFIX_REP:
29b0f896
AM		 3159 expecting_string_instruction = current_templates->start->name;
3160 break;
c32fa91d
L		 3161 default:
3162 break;
29b0f896
AM		 3163 }
3164 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3165 token_start = ++l;
3166 }
3167 else
3168 break;
3169 }
45288df1 3170
30a55f88 3171 if (!current_templates)
b6169b20 3172 {
30a55f88
L		 3173 /* Check if we should swap operand in encoding. */
3174 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3175 i.swap_operand = 1;
3176 else
3177 goto check_suffix;
3178 mnem_p = dot_p;
3179 *dot_p = '\0';
d3ce72d0 3180 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3181 }
3182
29b0f896
AM		 3183 if (!current_templates)
3184 {
b6169b20 3185check_suffix:
29b0f896
AM		 3186 /* See if we can get a match by trimming off a suffix. */
3187 switch (mnem_p[-1])
3188 {
3189 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3190 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3191 i.suffix = SHORT_MNEM_SUFFIX;
3192 else
29b0f896
AM		 3193 case BYTE_MNEM_SUFFIX:
3194 case QWORD_MNEM_SUFFIX:
3195 i.suffix = mnem_p[-1];
3196 mnem_p[-1] = '\0';
d3ce72d0
NC		 3197 current_templates = (const templates *) hash_find (op_hash,
3198 mnemonic);
29b0f896
AM		 3199 break;
3200 case SHORT_MNEM_SUFFIX:
3201 case LONG_MNEM_SUFFIX:
3202 if (!intel_syntax)
3203 {
3204 i.suffix = mnem_p[-1];
3205 mnem_p[-1] = '\0';
d3ce72d0
NC		 3206 current_templates = (const templates *) hash_find (op_hash,
3207 mnemonic);
29b0f896
AM		 3208 }
3209 break;
252b5132 3210
29b0f896
AM		 3211 /* Intel Syntax. */
3212 case 'd':
3213 if (intel_syntax)
3214 {
9306ca4a 3215 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3216 i.suffix = SHORT_MNEM_SUFFIX;
3217 else
3218 i.suffix = LONG_MNEM_SUFFIX;
3219 mnem_p[-1] = '\0';
d3ce72d0
NC		 3220 current_templates = (const templates *) hash_find (op_hash,
3221 mnemonic);
29b0f896
AM		 3222 }
3223 break;
3224 }
3225 if (!current_templates)
3226 {
3227 as_bad (_("no such instruction: `%s'"), token_start);
3228 return NULL;
3229 }
3230 }
252b5132 3231
40fb9820
L		 3232 if (current_templates->start->opcode_modifier.jump
3233 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3234 {
3235 /* Check for a branch hint. We allow ",pt" and ",pn" for
3236 predict taken and predict not taken respectively.
3237 I'm not sure that branch hints actually do anything on loop
3238 and jcxz insns (JumpByte) for current Pentium4 chips. They
3239 may work in the future and it doesn't hurt to accept them
3240 now. */
3241 if (l[0] == ',' && l[1] == 'p')
3242 {
3243 if (l[2] == 't')
3244 {
3245 if (!add_prefix (DS_PREFIX_OPCODE))
3246 return NULL;
3247 l += 3;
3248 }
3249 else if (l[2] == 'n')
3250 {
3251 if (!add_prefix (CS_PREFIX_OPCODE))
3252 return NULL;
3253 l += 3;
3254 }
3255 }
3256 }
3257 /* Any other comma loses. */
3258 if (*l == ',')
3259 {
3260 as_bad (_("invalid character %s in mnemonic"),
3261 output_invalid (*l));
3262 return NULL;
3263 }
252b5132 3264
29b0f896 3265 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3266 supported = 0;
3267 for (t = current_templates->start; t < current_templates->end; ++t)
3268 {
c0f3af97
L		 3269 supported |= cpu_flags_match (t);
3270 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3271 goto skip;
5c6af06e 3272 }
3629bb00 3273
c0f3af97 3274 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3275 {
3276 as_bad (flag_code == CODE_64BIT
3277 ? _("`%s' is not supported in 64-bit mode")
3278 : _("`%s' is only supported in 64-bit mode"),
3279 current_templates->start->name);
3280 return NULL;
3281 }
c0f3af97 3282 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3283 {
3629bb00 3284 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 3285 current_templates->start->name,
41aacd83 3286 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3287 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3288 return NULL;
29b0f896 3289 }
3629bb00
L		 3290
3291skip:
3292 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3293 && (flag_code != CODE_16BIT))
29b0f896
AM		 3294 {
3295 as_warn (_("use .code16 to ensure correct addressing mode"));
3296 }
252b5132 3297
29b0f896 3298 /* Check for rep/repne without a string instruction. */
f41bbced 3299 if (expecting_string_instruction)
29b0f896 3300 {
f41bbced
JB		 3301 static templates override;
3302
3303 for (t = current_templates->start; t < current_templates->end; ++t)
40fb9820 3304 if (t->opcode_modifier.isstring)
f41bbced
JB		 3305 break;
3306 if (t >= current_templates->end)
3307 {
3308 as_bad (_("expecting string instruction after `%s'"),
64e74474 3309 expecting_string_instruction);
f41bbced
JB		 3310 return NULL;
3311 }
3312 for (override.start = t; t < current_templates->end; ++t)
40fb9820 3313 if (!t->opcode_modifier.isstring)
f41bbced
JB		 3314 break;
3315 override.end = t;
3316 current_templates = &override;
29b0f896 3317 }
252b5132 3318
29b0f896
AM		 3319 return l;
3320}
252b5132 3321
29b0f896 3322static char *
e3bb37b5 3323parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3324{
3325 char *token_start;
3138f287 3326
29b0f896
AM		 3327 /* 1 if operand is pending after ','. */
3328 unsigned int expecting_operand = 0;
252b5132 3329
29b0f896
AM		 3330 /* Non-zero if operand parens not balanced. */
3331 unsigned int paren_not_balanced;
3332
3333 while (*l != END_OF_INSN)
3334 {
3335 /* Skip optional white space before operand. */
3336 if (is_space_char (*l))
3337 ++l;
3338 if (!is_operand_char (*l) && *l != END_OF_INSN)
3339 {
3340 as_bad (_("invalid character %s before operand %d"),
3341 output_invalid (*l),
3342 i.operands + 1);
3343 return NULL;
3344 }
3345 token_start = l; /* after white space */
3346 paren_not_balanced = 0;
3347 while (paren_not_balanced || *l != ',')
3348 {
3349 if (*l == END_OF_INSN)
3350 {
3351 if (paren_not_balanced)
3352 {
3353 if (!intel_syntax)
3354 as_bad (_("unbalanced parenthesis in operand %d."),
3355 i.operands + 1);
3356 else
3357 as_bad (_("unbalanced brackets in operand %d."),
3358 i.operands + 1);
3359 return NULL;
3360 }
3361 else
3362 break; /* we are done */
3363 }
3364 else if (!is_operand_char (*l) && !is_space_char (*l))
3365 {
3366 as_bad (_("invalid character %s in operand %d"),
3367 output_invalid (*l),
3368 i.operands + 1);
3369 return NULL;
3370 }
3371 if (!intel_syntax)
3372 {
3373 if (*l == '(')
3374 ++paren_not_balanced;
3375 if (*l == ')')
3376 --paren_not_balanced;
3377 }
3378 else
3379 {
3380 if (*l == '[')
3381 ++paren_not_balanced;
3382 if (*l == ']')
3383 --paren_not_balanced;
3384 }
3385 l++;
3386 }
3387 if (l != token_start)
3388 { /* Yes, we've read in another operand. */
3389 unsigned int operand_ok;
3390 this_operand = i.operands++;
7d5e4556 3391 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 3392 if (i.operands > MAX_OPERANDS)
3393 {
3394 as_bad (_("spurious operands; (%d operands/instruction max)"),
3395 MAX_OPERANDS);
3396 return NULL;
3397 }
3398 /* Now parse operand adding info to 'i' as we go along. */
3399 END_STRING_AND_SAVE (l);
3400
3401 if (intel_syntax)
3402 operand_ok =
3403 i386_intel_operand (token_start,
3404 intel_float_operand (mnemonic));
3405 else
a7619375 3406 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 3407
3408 RESTORE_END_STRING (l);
3409 if (!operand_ok)
3410 return NULL;
3411 }
3412 else
3413 {
3414 if (expecting_operand)
3415 {
3416 expecting_operand_after_comma:
3417 as_bad (_("expecting operand after ','; got nothing"));
3418 return NULL;
3419 }
3420 if (*l == ',')
3421 {
3422 as_bad (_("expecting operand before ','; got nothing"));
3423 return NULL;
3424 }
3425 }
7f3f1ea2 3426
29b0f896
AM		 3427 /* Now *l must be either ',' or END_OF_INSN. */
3428 if (*l == ',')
3429 {
3430 if (*++l == END_OF_INSN)
3431 {
3432 /* Just skip it, if it's \n complain. */
3433 goto expecting_operand_after_comma;
3434 }
3435 expecting_operand = 1;
3436 }
3437 }
3438 return l;
3439}
7f3f1ea2 3440
050dfa73 3441static void
4d456e3d 3442swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 3443{
3444 union i386_op temp_op;
40fb9820 3445 i386_operand_type temp_type;
050dfa73 3446 enum bfd_reloc_code_real temp_reloc;
4eed87de 3447
050dfa73
MM		 3448 temp_type = i.types[xchg2];
3449 i.types[xchg2] = i.types[xchg1];
3450 i.types[xchg1] = temp_type;
3451 temp_op = i.op[xchg2];
3452 i.op[xchg2] = i.op[xchg1];
3453 i.op[xchg1] = temp_op;
3454 temp_reloc = i.reloc[xchg2];
3455 i.reloc[xchg2] = i.reloc[xchg1];
3456 i.reloc[xchg1] = temp_reloc;
3457}
3458
29b0f896 3459static void
e3bb37b5 3460swap_operands (void)
29b0f896 3461{
b7c61d9a 3462 switch (i.operands)
050dfa73 3463 {
c0f3af97 3464 case 5:
b7c61d9a 3465 case 4:
4d456e3d 3466 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 3467 case 3:
3468 case 2:
4d456e3d 3469 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 3470 break;
3471 default:
3472 abort ();
29b0f896 3473 }
29b0f896
AM		 3474
3475 if (i.mem_operands == 2)
3476 {
3477 const seg_entry *temp_seg;
3478 temp_seg = i.seg[0];
3479 i.seg[0] = i.seg[1];
3480 i.seg[1] = temp_seg;
3481 }
3482}
252b5132 3483
29b0f896
AM		 3484/* Try to ensure constant immediates are represented in the smallest
3485 opcode possible. */
3486static void
e3bb37b5 3487optimize_imm (void)
29b0f896
AM		 3488{
3489 char guess_suffix = 0;
3490 int op;
252b5132 3491
29b0f896
AM		 3492 if (i.suffix)
3493 guess_suffix = i.suffix;
3494 else if (i.reg_operands)
3495 {
3496 /* Figure out a suffix from the last register operand specified.
3497 We can't do this properly yet, ie. excluding InOutPortReg,
3498 but the following works for instructions with immediates.
3499 In any case, we can't set i.suffix yet. */
3500 for (op = i.operands; --op >= 0;)
40fb9820 3501 if (i.types[op].bitfield.reg8)
7ab9ffdd 3502 {
40fb9820
L		 3503 guess_suffix = BYTE_MNEM_SUFFIX;
3504 break;
3505 }
3506 else if (i.types[op].bitfield.reg16)
252b5132 3507 {
40fb9820
L		 3508 guess_suffix = WORD_MNEM_SUFFIX;
3509 break;
3510 }
3511 else if (i.types[op].bitfield.reg32)
3512 {
3513 guess_suffix = LONG_MNEM_SUFFIX;
3514 break;
3515 }
3516 else if (i.types[op].bitfield.reg64)
3517 {
3518 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 3519 break;
252b5132 3520 }
29b0f896
AM		 3521 }
3522 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3523 guess_suffix = WORD_MNEM_SUFFIX;
3524
3525 for (op = i.operands; --op >= 0;)
40fb9820 3526 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 3527 {
3528 switch (i.op[op].imms->X_op)
252b5132 3529 {
29b0f896
AM		 3530 case O_constant:
3531 /* If a suffix is given, this operand may be shortened. */
3532 switch (guess_suffix)
252b5132 3533 {
29b0f896 3534 case LONG_MNEM_SUFFIX:
40fb9820
L		 3535 i.types[op].bitfield.imm32 = 1;
3536 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3537 break;
3538 case WORD_MNEM_SUFFIX:
40fb9820
L		 3539 i.types[op].bitfield.imm16 = 1;
3540 i.types[op].bitfield.imm32 = 1;
3541 i.types[op].bitfield.imm32s = 1;
3542 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3543 break;
3544 case BYTE_MNEM_SUFFIX:
40fb9820
L		 3545 i.types[op].bitfield.imm8 = 1;
3546 i.types[op].bitfield.imm8s = 1;
3547 i.types[op].bitfield.imm16 = 1;
3548 i.types[op].bitfield.imm32 = 1;
3549 i.types[op].bitfield.imm32s = 1;
3550 i.types[op].bitfield.imm64 = 1;
29b0f896 3551 break;
252b5132 3552 }
252b5132 3553
29b0f896
AM		 3554 /* If this operand is at most 16 bits, convert it
3555 to a signed 16 bit number before trying to see
3556 whether it will fit in an even smaller size.
3557 This allows a 16-bit operand such as $0xffe0 to
3558 be recognised as within Imm8S range. */
40fb9820 3559 if ((i.types[op].bitfield.imm16)
29b0f896 3560 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 3561 {
29b0f896
AM		 3562 i.op[op].imms->X_add_number =
3563 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3564 }
40fb9820 3565 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 3566 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3567 == 0))
3568 {
3569 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3570 ^ ((offsetT) 1 << 31))
3571 - ((offsetT) 1 << 31));
3572 }
40fb9820 3573 i.types[op]
c6fb90c8
L		 3574 = operand_type_or (i.types[op],
3575 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 3576
29b0f896
AM		 3577 /* We must avoid matching of Imm32 templates when 64bit
3578 only immediate is available. */
3579 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 3580 i.types[op].bitfield.imm32 = 0;
29b0f896 3581 break;
252b5132 3582
29b0f896
AM		 3583 case O_absent:
3584 case O_register:
3585 abort ();
3586
3587 /* Symbols and expressions. */
3588 default:
9cd96992
JB		 3589 /* Convert symbolic operand to proper sizes for matching, but don't
3590 prevent matching a set of insns that only supports sizes other
3591 than those matching the insn suffix. */
3592 {
40fb9820 3593 i386_operand_type mask, allowed;
d3ce72d0 3594 const insn_template *t;
9cd96992 3595
0dfbf9d7
L		 3596 operand_type_set (&mask, 0);
3597 operand_type_set (&allowed, 0);
40fb9820 3598
4eed87de
AM		 3599 for (t = current_templates->start;
3600 t < current_templates->end;
3601 ++t)
c6fb90c8
L		 3602 allowed = operand_type_or (allowed,
3603 t->operand_types[op]);
9cd96992
JB		 3604 switch (guess_suffix)
3605 {
3606 case QWORD_MNEM_SUFFIX:
40fb9820
L		 3607 mask.bitfield.imm64 = 1;
3608 mask.bitfield.imm32s = 1;
9cd96992
JB		 3609 break;
3610 case LONG_MNEM_SUFFIX:
40fb9820 3611 mask.bitfield.imm32 = 1;
9cd96992
JB		 3612 break;
3613 case WORD_MNEM_SUFFIX:
40fb9820 3614 mask.bitfield.imm16 = 1;
9cd96992
JB		 3615 break;
3616 case BYTE_MNEM_SUFFIX:
40fb9820 3617 mask.bitfield.imm8 = 1;
9cd96992
JB		 3618 break;
3619 default:
9cd96992
JB		 3620 break;
3621 }
c6fb90c8 3622 allowed = operand_type_and (mask, allowed);
0dfbf9d7 3623 if (!operand_type_all_zero (&allowed))
c6fb90c8 3624 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 3625 }
29b0f896 3626 break;
252b5132 3627 }
29b0f896
AM		 3628 }
3629}
47926f60 3630
29b0f896
AM		 3631/* Try to use the smallest displacement type too. */
3632static void
e3bb37b5 3633optimize_disp (void)
29b0f896
AM		 3634{
3635 int op;
3e73aa7c 3636
29b0f896 3637 for (op = i.operands; --op >= 0;)
40fb9820 3638 if (operand_type_check (i.types[op], disp))
252b5132 3639 {
b300c311 3640 if (i.op[op].disps->X_op == O_constant)
252b5132 3641 {
b300c311 3642 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 3643
40fb9820 3644 if (i.types[op].bitfield.disp16
b300c311
L		 3645 && (disp & ~(offsetT) 0xffff) == 0)
3646 {
3647 /* If this operand is at most 16 bits, convert
3648 to a signed 16 bit number and don't use 64bit
3649 displacement. */
3650 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 3651 i.types[op].bitfield.disp64 = 0;
b300c311 3652 }
40fb9820 3653 if (i.types[op].bitfield.disp32
b300c311
L		 3654 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
3655 {
3656 /* If this operand is at most 32 bits, convert
3657 to a signed 32 bit number and don't use 64bit
3658 displacement. */
3659 disp &= (((offsetT) 2 << 31) - 1);
3660 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 3661 i.types[op].bitfield.disp64 = 0;
b300c311 3662 }
40fb9820 3663 if (!disp && i.types[op].bitfield.baseindex)
b300c311 3664 {
40fb9820
L		 3665 i.types[op].bitfield.disp8 = 0;
3666 i.types[op].bitfield.disp16 = 0;
3667 i.types[op].bitfield.disp32 = 0;
3668 i.types[op].bitfield.disp32s = 0;
3669 i.types[op].bitfield.disp64 = 0;
b300c311
L		 3670 i.op[op].disps = 0;
3671 i.disp_operands--;
3672 }
3673 else if (flag_code == CODE_64BIT)
3674 {
3675 if (fits_in_signed_long (disp))
28a9d8f5 3676 {
40fb9820
L		 3677 i.types[op].bitfield.disp64 = 0;
3678 i.types[op].bitfield.disp32s = 1;
28a9d8f5 3679 }
0e1147d9
L		 3680 if (i.prefix[ADDR_PREFIX]
3681 && fits_in_unsigned_long (disp))
40fb9820 3682 i.types[op].bitfield.disp32 = 1;
b300c311 3683 }
40fb9820
L		 3684 if ((i.types[op].bitfield.disp32
3685 || i.types[op].bitfield.disp32s
3686 || i.types[op].bitfield.disp16)
b300c311 3687 && fits_in_signed_byte (disp))
40fb9820 3688 i.types[op].bitfield.disp8 = 1;
252b5132 3689 }
67a4f2b7
AO		 3690 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3691 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3692 {
3693 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3694 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 3695 i.types[op].bitfield.disp8 = 0;
3696 i.types[op].bitfield.disp16 = 0;
3697 i.types[op].bitfield.disp32 = 0;
3698 i.types[op].bitfield.disp32s = 0;
3699 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 3700 }
3701 else
b300c311 3702 /* We only support 64bit displacement on constants. */
40fb9820 3703 i.types[op].bitfield.disp64 = 0;
252b5132 3704 }
29b0f896
AM		 3705}
3706
d3ce72d0 3707static const insn_template *
e3bb37b5 3708match_template (void)
29b0f896
AM		 3709{
3710 /* Points to template once we've found it. */
d3ce72d0 3711 const insn_template *t;
40fb9820 3712 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 3713 i386_operand_type overlap4;
29b0f896 3714 unsigned int found_reverse_match;
40fb9820
L		 3715 i386_opcode_modifier suffix_check;
3716 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 3717 int addr_prefix_disp;
a5c311ca 3718 unsigned int j;
3629bb00 3719 unsigned int found_cpu_match;
45664ddb 3720 unsigned int check_register;
29b0f896 3721
c0f3af97
L		 3722#if MAX_OPERANDS != 5
3723# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 3724#endif
3725
29b0f896 3726 found_reverse_match = 0;
539e75ad 3727 addr_prefix_disp = -1;
40fb9820
L		 3728
3729 memset (&suffix_check, 0, sizeof (suffix_check));
3730 if (i.suffix == BYTE_MNEM_SUFFIX)
3731 suffix_check.no_bsuf = 1;
3732 else if (i.suffix == WORD_MNEM_SUFFIX)
3733 suffix_check.no_wsuf = 1;
3734 else if (i.suffix == SHORT_MNEM_SUFFIX)
3735 suffix_check.no_ssuf = 1;
3736 else if (i.suffix == LONG_MNEM_SUFFIX)
3737 suffix_check.no_lsuf = 1;
3738 else if (i.suffix == QWORD_MNEM_SUFFIX)
3739 suffix_check.no_qsuf = 1;
3740 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 3741 suffix_check.no_ldsuf = 1;
29b0f896 3742
45aa61fe 3743 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 3744 {
539e75ad
L		 3745 addr_prefix_disp = -1;
3746
29b0f896
AM		 3747 /* Must have right number of operands. */
3748 if (i.operands != t->operands)
3749 continue;
3750
50aecf8c 3751 /* Check processor support. */
c0f3af97
L		 3752 found_cpu_match = (cpu_flags_match (t)
3753 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 3754 if (!found_cpu_match)
3755 continue;
3756
e1d4d893
L		 3757 /* Check old gcc support. */
3758 if (!old_gcc && t->opcode_modifier.oldgcc)
3759 continue;
3760
3761 /* Check AT&T mnemonic. */
3762 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 3763 continue;
3764
5c07affc
L		 3765 /* Check AT&T syntax Intel syntax. */
3766 if ((intel_syntax && t->opcode_modifier.attsyntax)
3767 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 3768 continue;
3769
20592a94 3770 /* Check the suffix, except for some instructions in intel mode. */
567e4e96
L		 3771 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3772 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3773 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3774 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3775 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3776 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3777 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 3778 continue;
3779
5c07affc 3780 if (!operand_size_match (t))
7d5e4556 3781 continue;
539e75ad 3782
5c07affc
L		 3783 for (j = 0; j < MAX_OPERANDS; j++)
3784 operand_types[j] = t->operand_types[j];
3785
45aa61fe
AM		 3786 /* In general, don't allow 64-bit operands in 32-bit mode. */
3787 if (i.suffix == QWORD_MNEM_SUFFIX
3788 && flag_code != CODE_64BIT
3789 && (intel_syntax
40fb9820 3790 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 3791 && !intel_float_operand (t->name))
3792 : intel_float_operand (t->name) != 2)
40fb9820 3793 && ((!operand_types[0].bitfield.regmmx
c0f3af97
L		 3794 && !operand_types[0].bitfield.regxmm
3795 && !operand_types[0].bitfield.regymm)
40fb9820 3796 || (!operand_types[t->operands > 1].bitfield.regmmx
c0f3af97
L		 3797 && !!operand_types[t->operands > 1].bitfield.regxmm
3798 && !!operand_types[t->operands > 1].bitfield.regymm))
45aa61fe
AM		 3799 && (t->base_opcode != 0x0fc7
3800 || t->extension_opcode != 1 /* cmpxchg8b */))
3801 continue;
3802
192dc9c6
JB		 3803 /* In general, don't allow 32-bit operands on pre-386. */
3804 else if (i.suffix == LONG_MNEM_SUFFIX
3805 && !cpu_arch_flags.bitfield.cpui386
3806 && (intel_syntax
3807 ? (!t->opcode_modifier.ignoresize
3808 && !intel_float_operand (t->name))
3809 : intel_float_operand (t->name) != 2)
3810 && ((!operand_types[0].bitfield.regmmx
3811 && !operand_types[0].bitfield.regxmm)
3812 || (!operand_types[t->operands > 1].bitfield.regmmx
3813 && !!operand_types[t->operands > 1].bitfield.regxmm)))
3814 continue;
3815
29b0f896 3816 /* Do not verify operands when there are none. */
50aecf8c 3817 else
29b0f896 3818 {
c6fb90c8 3819 if (!t->operands)
2dbab7d5
L		 3820 /* We've found a match; break out of loop. */
3821 break;
29b0f896 3822 }
252b5132 3823
539e75ad
L		 3824 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3825 into Disp32/Disp16/Disp32 operand. */
3826 if (i.prefix[ADDR_PREFIX] != 0)
3827 {
40fb9820 3828 /* There should be only one Disp operand. */
539e75ad
L		 3829 switch (flag_code)
3830 {
3831 case CODE_16BIT:
40fb9820
L		 3832 for (j = 0; j < MAX_OPERANDS; j++)
3833 {
3834 if (operand_types[j].bitfield.disp16)
3835 {
3836 addr_prefix_disp = j;
3837 operand_types[j].bitfield.disp32 = 1;
3838 operand_types[j].bitfield.disp16 = 0;
3839 break;
3840 }
3841 }
539e75ad
L		 3842 break;
3843 case CODE_32BIT:
40fb9820
L		 3844 for (j = 0; j < MAX_OPERANDS; j++)
3845 {
3846 if (operand_types[j].bitfield.disp32)
3847 {
3848 addr_prefix_disp = j;
3849 operand_types[j].bitfield.disp32 = 0;
3850 operand_types[j].bitfield.disp16 = 1;
3851 break;
3852 }
3853 }
539e75ad
L		 3854 break;
3855 case CODE_64BIT:
40fb9820
L		 3856 for (j = 0; j < MAX_OPERANDS; j++)
3857 {
3858 if (operand_types[j].bitfield.disp64)
3859 {
3860 addr_prefix_disp = j;
3861 operand_types[j].bitfield.disp64 = 0;
3862 operand_types[j].bitfield.disp32 = 1;
3863 break;
3864 }
3865 }
539e75ad
L		 3866 break;
3867 }
539e75ad
L		 3868 }
3869
45664ddb
L		 3870 /* We check register size only if size of operands can be
3871 encoded the canonical way. */
3872 check_register = t->opcode_modifier.w;
c6fb90c8 3873 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 3874 switch (t->operands)
3875 {
3876 case 1:
40fb9820 3877 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 3878 continue;
3879 break;
3880 case 2:
8b38ad71
L		 3881 /* xchg %eax, %eax is a special case. It is an aliase for nop
3882 only in 32bit mode and we can use opcode 0x90. In 64bit
3883 mode, we can't use 0x90 for xchg %eax, %eax since it should
3884 zero-extend %eax to %rax. */
3885 if (flag_code == CODE_64BIT
3886 && t->base_opcode == 0x90
0dfbf9d7
L		 3887 && operand_type_equal (&i.types [0], &acc32)
3888 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 3889 continue;
b6169b20
L		 3890 if (i.swap_operand)
3891 {
3892 /* If we swap operand in encoding, we either match
3893 the next one or reverse direction of operands. */
3894 if (t->opcode_modifier.s)
3895 continue;
3896 else if (t->opcode_modifier.d)
3897 goto check_reverse;
3898 }
3899
29b0f896 3900 case 3:
fa99fab2
L		 3901 /* If we swap operand in encoding, we match the next one. */
3902 if (i.swap_operand && t->opcode_modifier.s)
3903 continue;
f48ff2ae 3904 case 4:
c0f3af97 3905 case 5:
c6fb90c8 3906 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 3907 if (!operand_type_match (overlap0, i.types[0])
3908 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3909 || (check_register
3910 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 3911 operand_types[0],
3912 overlap1, i.types[1],
3913 operand_types[1])))
29b0f896
AM		 3914 {
3915 /* Check if other direction is valid ... */
40fb9820 3916 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 3917 continue;
3918
b6169b20 3919check_reverse:
29b0f896 3920 /* Try reversing direction of operands. */
c6fb90c8
L		 3921 overlap0 = operand_type_and (i.types[0], operand_types[1]);
3922 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 3923 if (!operand_type_match (overlap0, i.types[0])
3924 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3925 || (check_register
3926 && !operand_type_register_match (overlap0,
3927 i.types[0],
3928 operand_types[1],
3929 overlap1,
3930 i.types[1],
3931 operand_types[0])))
29b0f896
AM		 3932 {
3933 /* Does not match either direction. */
3934 continue;
3935 }
3936 /* found_reverse_match holds which of D or FloatDR
3937 we've found. */
40fb9820 3938 if (t->opcode_modifier.d)
8a2ed489 3939 found_reverse_match = Opcode_D;
40fb9820 3940 else if (t->opcode_modifier.floatd)
8a2ed489
L		 3941 found_reverse_match = Opcode_FloatD;
3942 else
3943 found_reverse_match = 0;
40fb9820 3944 if (t->opcode_modifier.floatr)
8a2ed489 3945 found_reverse_match |= Opcode_FloatR;
29b0f896 3946 }
f48ff2ae 3947 else
29b0f896 3948 {
f48ff2ae 3949 /* Found a forward 2 operand match here. */
d1cbb4db
L		 3950 switch (t->operands)
3951 {
c0f3af97
L		 3952 case 5:
3953 overlap4 = operand_type_and (i.types[4],
3954 operand_types[4]);
d1cbb4db 3955 case 4:
c6fb90c8
L		 3956 overlap3 = operand_type_and (i.types[3],
3957 operand_types[3]);
d1cbb4db 3958 case 3:
c6fb90c8
L		 3959 overlap2 = operand_type_and (i.types[2],
3960 operand_types[2]);
d1cbb4db
L		 3961 break;
3962 }
29b0f896 3963
f48ff2ae
L		 3964 switch (t->operands)
3965 {
c0f3af97
L		 3966 case 5:
3967 if (!operand_type_match (overlap4, i.types[4])
3968 || !operand_type_register_match (overlap3,
3969 i.types[3],
3970 operand_types[3],
3971 overlap4,
3972 i.types[4],
3973 operand_types[4]))
3974 continue;
f48ff2ae 3975 case 4:
40fb9820 3976 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 3977 || (check_register
3978 && !operand_type_register_match (overlap2,
3979 i.types[2],
3980 operand_types[2],
3981 overlap3,
3982 i.types[3],
3983 operand_types[3])))
f48ff2ae
L		 3984 continue;
3985 case 3:
3986 /* Here we make use of the fact that there are no
3987 reverse match 3 operand instructions, and all 3
3988 operand instructions only need to be checked for
3989 register consistency between operands 2 and 3. */
40fb9820 3990 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 3991 || (check_register
3992 && !operand_type_register_match (overlap1,
3993 i.types[1],
3994 operand_types[1],
3995 overlap2,
3996 i.types[2],
3997 operand_types[2])))
f48ff2ae
L		 3998 continue;
3999 break;
4000 }
29b0f896 4001 }
f48ff2ae 4002 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 4003 slip through to break. */
4004 }
3629bb00 4005 if (!found_cpu_match)
29b0f896
AM		 4006 {
4007 found_reverse_match = 0;
4008 continue;
4009 }
c0f3af97 4010
29b0f896
AM		 4011 /* We've found a match; break out of loop. */
4012 break;
4013 }
4014
4015 if (t == current_templates->end)
4016 {
4017 /* We found no match. */
95f283e8
L		 4018 if (intel_syntax)
4019 as_bad (_("ambiguous operand size or operands invalid for `%s'"),
4020 current_templates->start->name);
4021 else
4022 as_bad (_("suffix or operands invalid for `%s'"),
4023 current_templates->start->name);
fa99fab2 4024 return NULL;
29b0f896 4025 }
252b5132 4026
29b0f896
AM		 4027 if (!quiet_warnings)
4028 {
4029 if (!intel_syntax
40fb9820
L		 4030 && (i.types[0].bitfield.jumpabsolute
4031 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 4032 {
4033 as_warn (_("indirect %s without `*'"), t->name);
4034 }
4035
40fb9820
L		 4036 if (t->opcode_modifier.isprefix
4037 && t->opcode_modifier.ignoresize)
29b0f896
AM		 4038 {
4039 /* Warn them that a data or address size prefix doesn't
4040 affect assembly of the next line of code. */
4041 as_warn (_("stand-alone `%s' prefix"), t->name);
4042 }
4043 }
4044
4045 /* Copy the template we found. */
4046 i.tm = *t;
539e75ad
L		 4047
4048 if (addr_prefix_disp != -1)
4049 i.tm.operand_types[addr_prefix_disp]
4050 = operand_types[addr_prefix_disp];
4051
29b0f896
AM		 4052 if (found_reverse_match)
4053 {
4054 /* If we found a reverse match we must alter the opcode
4055 direction bit. found_reverse_match holds bits to change
4056 (different for int & float insns). */
4057
4058 i.tm.base_opcode ^= found_reverse_match;
4059
539e75ad
L		 4060 i.tm.operand_types[0] = operand_types[1];
4061 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 4062 }
4063
fa99fab2 4064 return t;
29b0f896
AM		 4065}
4066
4067static int
e3bb37b5 4068check_string (void)
29b0f896 4069{
40fb9820
L		 4070 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
4071 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 4072 {
4073 if (i.seg[0] != NULL && i.seg[0] != &es)
4074 {
a87af027 4075 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 4076 i.tm.name,
a87af027
JB		 4077 mem_op + 1,
4078 register_prefix);
29b0f896
AM		 4079 return 0;
4080 }
4081 /* There's only ever one segment override allowed per instruction.
4082 This instruction possibly has a legal segment override on the
4083 second operand, so copy the segment to where non-string
4084 instructions store it, allowing common code. */
4085 i.seg[0] = i.seg[1];
4086 }
40fb9820 4087 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 4088 {
4089 if (i.seg[1] != NULL && i.seg[1] != &es)
4090 {
a87af027 4091 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 4092 i.tm.name,
a87af027
JB		 4093 mem_op + 2,
4094 register_prefix);
29b0f896
AM		 4095 return 0;
4096 }
4097 }
4098 return 1;
4099}
4100
4101static int
543613e9 4102process_suffix (void)
29b0f896
AM		 4103{
4104 /* If matched instruction specifies an explicit instruction mnemonic
4105 suffix, use it. */
40fb9820
L		 4106 if (i.tm.opcode_modifier.size16)
4107 i.suffix = WORD_MNEM_SUFFIX;
4108 else if (i.tm.opcode_modifier.size32)
4109 i.suffix = LONG_MNEM_SUFFIX;
4110 else if (i.tm.opcode_modifier.size64)
4111 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 4112 else if (i.reg_operands)
4113 {
4114 /* If there's no instruction mnemonic suffix we try to invent one
4115 based on register operands. */
4116 if (!i.suffix)
4117 {
4118 /* We take i.suffix from the last register operand specified,
4119 Destination register type is more significant than source
381d071f
L		 4120 register type. crc32 in SSE4.2 prefers source register
4121 type. */
4122 if (i.tm.base_opcode == 0xf20f38f1)
4123 {
40fb9820
L		 4124 if (i.types[0].bitfield.reg16)
4125 i.suffix = WORD_MNEM_SUFFIX;
4126 else if (i.types[0].bitfield.reg32)
4127 i.suffix = LONG_MNEM_SUFFIX;
4128 else if (i.types[0].bitfield.reg64)
4129 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 4130 }
9344ff29 4131 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 4132 {
40fb9820 4133 if (i.types[0].bitfield.reg8)
20592a94
L		 4134 i.suffix = BYTE_MNEM_SUFFIX;
4135 }
381d071f
L		 4136
4137 if (!i.suffix)
4138 {
4139 int op;
4140
20592a94
L		 4141 if (i.tm.base_opcode == 0xf20f38f1
4142 || i.tm.base_opcode == 0xf20f38f0)
4143 {
4144 /* We have to know the operand size for crc32. */
4145 as_bad (_("ambiguous memory operand size for `%s`"),
4146 i.tm.name);
4147 return 0;
4148 }
4149
381d071f 4150 for (op = i.operands; --op >= 0;)
40fb9820 4151 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 4152 {
40fb9820
L		 4153 if (i.types[op].bitfield.reg8)
4154 {
4155 i.suffix = BYTE_MNEM_SUFFIX;
4156 break;
4157 }
4158 else if (i.types[op].bitfield.reg16)
4159 {
4160 i.suffix = WORD_MNEM_SUFFIX;
4161 break;
4162 }
4163 else if (i.types[op].bitfield.reg32)
4164 {
4165 i.suffix = LONG_MNEM_SUFFIX;
4166 break;
4167 }
4168 else if (i.types[op].bitfield.reg64)
4169 {
4170 i.suffix = QWORD_MNEM_SUFFIX;
4171 break;
4172 }
381d071f
L		 4173 }
4174 }
29b0f896
AM		 4175 }
4176 else if (i.suffix == BYTE_MNEM_SUFFIX)
4177 {
4178 if (!check_byte_reg ())
4179 return 0;
4180 }
4181 else if (i.suffix == LONG_MNEM_SUFFIX)
4182 {
4183 if (!check_long_reg ())
4184 return 0;
4185 }
4186 else if (i.suffix == QWORD_MNEM_SUFFIX)
4187 {
955e1e6a
L		 4188 if (intel_syntax
4189 && i.tm.opcode_modifier.ignoresize
4190 && i.tm.opcode_modifier.no_qsuf)
4191 i.suffix = 0;
4192 else if (!check_qword_reg ())
29b0f896
AM		 4193 return 0;
4194 }
4195 else if (i.suffix == WORD_MNEM_SUFFIX)
4196 {
4197 if (!check_word_reg ())
4198 return 0;
4199 }
c0f3af97
L		 4200 else if (i.suffix == XMMWORD_MNEM_SUFFIX
4201 || i.suffix == YMMWORD_MNEM_SUFFIX)
582d5edd 4202 {
c0f3af97 4203 /* Skip if the instruction has x/y suffix. match_template
582d5edd
L		 4204 should check if it is a valid suffix. */
4205 }
40fb9820 4206 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 4207 /* Do nothing if the instruction is going to ignore the prefix. */
4208 ;
4209 else
4210 abort ();
4211 }
40fb9820 4212 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 4213 && !i.suffix
4214 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 4215 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 4216 {
4217 i.suffix = stackop_size;
4218 }
9306ca4a
JB		 4219 else if (intel_syntax
4220 && !i.suffix
40fb9820
L		 4221 && (i.tm.operand_types[0].bitfield.jumpabsolute
4222 || i.tm.opcode_modifier.jumpbyte
4223 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 4224 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
4225 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 4226 {
4227 switch (flag_code)
4228 {
4229 case CODE_64BIT:
40fb9820 4230 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 4231 {
4232 i.suffix = QWORD_MNEM_SUFFIX;
4233 break;
4234 }
4235 case CODE_32BIT:
40fb9820 4236 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 4237 i.suffix = LONG_MNEM_SUFFIX;
4238 break;
4239 case CODE_16BIT:
40fb9820 4240 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 4241 i.suffix = WORD_MNEM_SUFFIX;
4242 break;
4243 }
4244 }
252b5132 4245
9306ca4a 4246 if (!i.suffix)
29b0f896 4247 {
9306ca4a
JB		 4248 if (!intel_syntax)
4249 {
40fb9820 4250 if (i.tm.opcode_modifier.w)
9306ca4a 4251 {
4eed87de
AM		 4252 as_bad (_("no instruction mnemonic suffix given and "
4253 "no register operands; can't size instruction"));
9306ca4a
JB		 4254 return 0;
4255 }
4256 }
4257 else
4258 {
40fb9820 4259 unsigned int suffixes;
7ab9ffdd 4260
40fb9820
L		 4261 suffixes = !i.tm.opcode_modifier.no_bsuf;
4262 if (!i.tm.opcode_modifier.no_wsuf)
4263 suffixes |= 1 << 1;
4264 if (!i.tm.opcode_modifier.no_lsuf)
4265 suffixes |= 1 << 2;
fc4adea1 4266 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 4267 suffixes |= 1 << 3;
4268 if (!i.tm.opcode_modifier.no_ssuf)
4269 suffixes |= 1 << 4;
4270 if (!i.tm.opcode_modifier.no_qsuf)
4271 suffixes |= 1 << 5;
4272
4273 /* There are more than suffix matches. */
4274 if (i.tm.opcode_modifier.w
9306ca4a 4275 || ((suffixes & (suffixes - 1))
40fb9820
L		 4276 && !i.tm.opcode_modifier.defaultsize
4277 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 4278 {
4279 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4280 return 0;
4281 }
4282 }
29b0f896 4283 }
252b5132 4284
9306ca4a
JB		 4285 /* Change the opcode based on the operand size given by i.suffix;
4286 We don't need to change things for byte insns. */
4287
582d5edd
L		 4288 if (i.suffix
4289 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97
L		 4290 && i.suffix != XMMWORD_MNEM_SUFFIX
4291 && i.suffix != YMMWORD_MNEM_SUFFIX)
29b0f896
AM		 4292 {
4293 /* It's not a byte, select word/dword operation. */
40fb9820 4294 if (i.tm.opcode_modifier.w)
29b0f896 4295 {
40fb9820 4296 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 4297 i.tm.base_opcode |= 8;
4298 else
4299 i.tm.base_opcode |= 1;
4300 }
0f3f3d8b 4301
29b0f896
AM		 4302 /* Now select between word & dword operations via the operand
4303 size prefix, except for instructions that will ignore this
4304 prefix anyway. */
ca61edf2 4305 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 4306 {
ca61edf2
L		 4307 /* The address size override prefix changes the size of the
4308 first operand. */
40fb9820
L		 4309 if ((flag_code == CODE_32BIT
4310 && i.op->regs[0].reg_type.bitfield.reg16)
4311 || (flag_code != CODE_32BIT
4312 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 4313 if (!add_prefix (ADDR_PREFIX_OPCODE))
4314 return 0;
4315 }
4316 else if (i.suffix != QWORD_MNEM_SUFFIX
4317 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 4318 && !i.tm.opcode_modifier.ignoresize
4319 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 4320 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
4321 || (flag_code == CODE_64BIT
40fb9820 4322 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 4323 {
4324 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 4325
40fb9820 4326 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 4327 prefix = ADDR_PREFIX_OPCODE;
252b5132 4328
29b0f896
AM		 4329 if (!add_prefix (prefix))
4330 return 0;
24eab124 4331 }
252b5132 4332
29b0f896
AM		 4333 /* Set mode64 for an operand. */
4334 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 4335 && flag_code == CODE_64BIT
40fb9820 4336 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 4337 {
4338 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 4339 need rex64. cmpxchg8b is also a special case. */
4340 if (! (i.operands == 2
4341 && i.tm.base_opcode == 0x90
4342 && i.tm.extension_opcode == None
0dfbf9d7
L		 4343 && operand_type_equal (&i.types [0], &acc64)
4344 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 4345 && ! (i.operands == 1
4346 && i.tm.base_opcode == 0xfc7
4347 && i.tm.extension_opcode == 1
40fb9820
L		 4348 && !operand_type_check (i.types [0], reg)
4349 && operand_type_check (i.types [0], anymem)))
f6bee062 4350 i.rex |= REX_W;
46e883c5 4351 }
3e73aa7c 4352
29b0f896
AM		 4353 /* Size floating point instruction. */
4354 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 4355 if (i.tm.opcode_modifier.floatmf)
543613e9 4356 i.tm.base_opcode ^= 4;
29b0f896 4357 }
7ecd2f8b 4358
29b0f896
AM		 4359 return 1;
4360}
3e73aa7c 4361
29b0f896 4362static int
543613e9 4363check_byte_reg (void)
29b0f896
AM		 4364{
4365 int op;
543613e9 4366
29b0f896
AM		 4367 for (op = i.operands; --op >= 0;)
4368 {
4369 /* If this is an eight bit register, it's OK. If it's the 16 or
4370 32 bit version of an eight bit register, we will just use the
4371 low portion, and that's OK too. */
40fb9820 4372 if (i.types[op].bitfield.reg8)
29b0f896
AM		 4373 continue;
4374
ca61edf2
L		 4375 /* Don't generate this warning if not needed. */
4376 if (intel_syntax && i.tm.opcode_modifier.byteokintel)
29b0f896
AM		 4377 continue;
4378
9344ff29
L		 4379 /* crc32 doesn't generate this warning. */
4380 if (i.tm.base_opcode == 0xf20f38f0)
4381 continue;
4382
40fb9820
L		 4383 if ((i.types[op].bitfield.reg16
4384 || i.types[op].bitfield.reg32
4385 || i.types[op].bitfield.reg64)
4386 && i.op[op].regs->reg_num < 4)
29b0f896
AM		 4387 {
4388 /* Prohibit these changes in the 64bit mode, since the
4389 lowering is more complicated. */
4390 if (flag_code == CODE_64BIT
40fb9820 4391 && !i.tm.operand_types[op].bitfield.inoutportreg)
29b0f896 4392 {
2ca3ace5
L		 4393 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4394 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4395 i.suffix);
4396 return 0;
4397 }
4398#if REGISTER_WARNINGS
4399 if (!quiet_warnings
40fb9820 4400 && !i.tm.operand_types[op].bitfield.inoutportreg)
a540244d
L		 4401 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4402 register_prefix,
40fb9820 4403 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 4404 ? REGNAM_AL - REGNAM_AX
4405 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 4406 register_prefix,
29b0f896
AM		 4407 i.op[op].regs->reg_name,
4408 i.suffix);
4409#endif
4410 continue;
4411 }
4412 /* Any other register is bad. */
40fb9820
L		 4413 if (i.types[op].bitfield.reg16
4414 || i.types[op].bitfield.reg32
4415 || i.types[op].bitfield.reg64
4416 || i.types[op].bitfield.regmmx
4417 || i.types[op].bitfield.regxmm
c0f3af97 4418 || i.types[op].bitfield.regymm
40fb9820
L		 4419 || i.types[op].bitfield.sreg2
4420 || i.types[op].bitfield.sreg3
4421 || i.types[op].bitfield.control
4422 || i.types[op].bitfield.debug
4423 || i.types[op].bitfield.test
4424 || i.types[op].bitfield.floatreg
4425 || i.types[op].bitfield.floatacc)
29b0f896 4426 {
a540244d
L		 4427 as_bad (_("`%s%s' not allowed with `%s%c'"),
4428 register_prefix,
29b0f896
AM		 4429 i.op[op].regs->reg_name,
4430 i.tm.name,
4431 i.suffix);
4432 return 0;
4433 }
4434 }
4435 return 1;
4436}
4437
4438static int
e3bb37b5 4439check_long_reg (void)
29b0f896
AM		 4440{
4441 int op;
4442
4443 for (op = i.operands; --op >= 0;)
4444 /* Reject eight bit registers, except where the template requires
4445 them. (eg. movzb) */
40fb9820
L		 4446 if (i.types[op].bitfield.reg8
4447 && (i.tm.operand_types[op].bitfield.reg16
4448 || i.tm.operand_types[op].bitfield.reg32
4449 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4450 {
a540244d
L		 4451 as_bad (_("`%s%s' not allowed with `%s%c'"),
4452 register_prefix,
29b0f896
AM		 4453 i.op[op].regs->reg_name,
4454 i.tm.name,
4455 i.suffix);
4456 return 0;
4457 }
4458 /* Warn if the e prefix on a general reg is missing. */
4459 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4460 && i.types[op].bitfield.reg16
4461 && (i.tm.operand_types[op].bitfield.reg32
4462 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4463 {
4464 /* Prohibit these changes in the 64bit mode, since the
4465 lowering is more complicated. */
4466 if (flag_code == CODE_64BIT)
252b5132 4467 {
2ca3ace5
L		 4468 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4469 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4470 i.suffix);
4471 return 0;
252b5132 4472 }
29b0f896
AM		 4473#if REGISTER_WARNINGS
4474 else
a540244d
L		 4475 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4476 register_prefix,
29b0f896 4477 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 4478 register_prefix,
29b0f896
AM		 4479 i.op[op].regs->reg_name,
4480 i.suffix);
4481#endif
252b5132 4482 }
29b0f896 4483 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 4484 else if (i.types[op].bitfield.reg64
4485 && (i.tm.operand_types[op].bitfield.reg32
4486 || i.tm.operand_types[op].bitfield.acc))
252b5132 4487 {
34828aad 4488 if (intel_syntax
ca61edf2 4489 && i.tm.opcode_modifier.toqword
40fb9820 4490 && !i.types[0].bitfield.regxmm)
34828aad 4491 {
ca61edf2 4492 /* Convert to QWORD. We want REX byte. */
34828aad
L		 4493 i.suffix = QWORD_MNEM_SUFFIX;
4494 }
4495 else
4496 {
4497 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4498 register_prefix, i.op[op].regs->reg_name,
4499 i.suffix);
4500 return 0;
4501 }
29b0f896
AM		 4502 }
4503 return 1;
4504}
252b5132 4505
29b0f896 4506static int
e3bb37b5 4507check_qword_reg (void)
29b0f896
AM		 4508{
4509 int op;
252b5132 4510
29b0f896
AM		 4511 for (op = i.operands; --op >= 0; )
4512 /* Reject eight bit registers, except where the template requires
4513 them. (eg. movzb) */
40fb9820
L		 4514 if (i.types[op].bitfield.reg8
4515 && (i.tm.operand_types[op].bitfield.reg16
4516 || i.tm.operand_types[op].bitfield.reg32
4517 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4518 {
a540244d
L		 4519 as_bad (_("`%s%s' not allowed with `%s%c'"),
4520 register_prefix,
29b0f896
AM		 4521 i.op[op].regs->reg_name,
4522 i.tm.name,
4523 i.suffix);
4524 return 0;
4525 }
4526 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 4527 else if ((i.types[op].bitfield.reg16
4528 || i.types[op].bitfield.reg32)
4529 && (i.tm.operand_types[op].bitfield.reg32
4530 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4531 {
4532 /* Prohibit these changes in the 64bit mode, since the
4533 lowering is more complicated. */
34828aad 4534 if (intel_syntax
ca61edf2 4535 && i.tm.opcode_modifier.todword
40fb9820 4536 && !i.types[0].bitfield.regxmm)
34828aad 4537 {
ca61edf2 4538 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 4539 i.suffix = LONG_MNEM_SUFFIX;
4540 }
4541 else
4542 {
4543 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4544 register_prefix, i.op[op].regs->reg_name,
4545 i.suffix);
4546 return 0;
4547 }
252b5132 4548 }
29b0f896
AM		 4549 return 1;
4550}
252b5132 4551
29b0f896 4552static int
e3bb37b5 4553check_word_reg (void)
29b0f896
AM		 4554{
4555 int op;
4556 for (op = i.operands; --op >= 0;)
4557 /* Reject eight bit registers, except where the template requires
4558 them. (eg. movzb) */
40fb9820
L		 4559 if (i.types[op].bitfield.reg8
4560 && (i.tm.operand_types[op].bitfield.reg16
4561 || i.tm.operand_types[op].bitfield.reg32
4562 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4563 {
a540244d
L		 4564 as_bad (_("`%s%s' not allowed with `%s%c'"),
4565 register_prefix,
29b0f896
AM		 4566 i.op[op].regs->reg_name,
4567 i.tm.name,
4568 i.suffix);
4569 return 0;
4570 }
4571 /* Warn if the e prefix on a general reg is present. */
4572 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4573 && i.types[op].bitfield.reg32
4574 && (i.tm.operand_types[op].bitfield.reg16
4575 || i.tm.operand_types[op].bitfield.acc))
252b5132 4576 {
29b0f896
AM		 4577 /* Prohibit these changes in the 64bit mode, since the
4578 lowering is more complicated. */
4579 if (flag_code == CODE_64BIT)
252b5132 4580 {
2ca3ace5
L		 4581 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4582 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4583 i.suffix);
4584 return 0;
252b5132 4585 }
29b0f896
AM		 4586 else
4587#if REGISTER_WARNINGS
a540244d
L		 4588 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4589 register_prefix,
29b0f896 4590 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 4591 register_prefix,
29b0f896
AM		 4592 i.op[op].regs->reg_name,
4593 i.suffix);
4594#endif
4595 }
4596 return 1;
4597}
252b5132 4598
29b0f896 4599static int
40fb9820 4600update_imm (unsigned int j)
29b0f896 4601{
bc0844ae 4602 i386_operand_type overlap = i.types[j];
40fb9820
L		 4603 if ((overlap.bitfield.imm8
4604 || overlap.bitfield.imm8s
4605 || overlap.bitfield.imm16
4606 || overlap.bitfield.imm32
4607 || overlap.bitfield.imm32s
4608 || overlap.bitfield.imm64)
0dfbf9d7
L		 4609 && !operand_type_equal (&overlap, &imm8)
4610 && !operand_type_equal (&overlap, &imm8s)
4611 && !operand_type_equal (&overlap, &imm16)
4612 && !operand_type_equal (&overlap, &imm32)
4613 && !operand_type_equal (&overlap, &imm32s)
4614 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 4615 {
4616 if (i.suffix)
4617 {
40fb9820
L		 4618 i386_operand_type temp;
4619
0dfbf9d7 4620 operand_type_set (&temp, 0);
7ab9ffdd 4621 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 4622 {
4623 temp.bitfield.imm8 = overlap.bitfield.imm8;
4624 temp.bitfield.imm8s = overlap.bitfield.imm8s;
4625 }
4626 else if (i.suffix == WORD_MNEM_SUFFIX)
4627 temp.bitfield.imm16 = overlap.bitfield.imm16;
4628 else if (i.suffix == QWORD_MNEM_SUFFIX)
4629 {
4630 temp.bitfield.imm64 = overlap.bitfield.imm64;
4631 temp.bitfield.imm32s = overlap.bitfield.imm32s;
4632 }
4633 else
4634 temp.bitfield.imm32 = overlap.bitfield.imm32;
4635 overlap = temp;
29b0f896 4636 }
0dfbf9d7
L		 4637 else if (operand_type_equal (&overlap, &imm16_32_32s)
4638 || operand_type_equal (&overlap, &imm16_32)
4639 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 4640 {
40fb9820 4641 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 4642 overlap = imm16;
40fb9820 4643 else
65da13b5 4644 overlap = imm32s;
29b0f896 4645 }
0dfbf9d7
L		 4646 if (!operand_type_equal (&overlap, &imm8)
4647 && !operand_type_equal (&overlap, &imm8s)
4648 && !operand_type_equal (&overlap, &imm16)
4649 && !operand_type_equal (&overlap, &imm32)
4650 && !operand_type_equal (&overlap, &imm32s)
4651 && !operand_type_equal (&overlap, &imm64))
29b0f896 4652 {
4eed87de
AM		 4653 as_bad (_("no instruction mnemonic suffix given; "
4654 "can't determine immediate size"));
29b0f896
AM		 4655 return 0;
4656 }
4657 }
40fb9820 4658 i.types[j] = overlap;
29b0f896 4659
40fb9820
L		 4660 return 1;
4661}
4662
4663static int
4664finalize_imm (void)
4665{
bc0844ae 4666 unsigned int j, n;
29b0f896 4667
bc0844ae
L		 4668 /* Update the first 2 immediate operands. */
4669 n = i.operands > 2 ? 2 : i.operands;
4670 if (n)
4671 {
4672 for (j = 0; j < n; j++)
4673 if (update_imm (j) == 0)
4674 return 0;
40fb9820 4675
bc0844ae
L		 4676 /* The 3rd operand can't be immediate operand. */
4677 gas_assert (operand_type_check (i.types[2], imm) == 0);
4678 }
29b0f896
AM		 4679
4680 return 1;
4681}
4682
c0f3af97
L		 4683static int
4684bad_implicit_operand (int xmm)
4685{
4686 const char *reg = xmm ? "xmm0" : "ymm0";
4687 if (intel_syntax)
4688 as_bad (_("the last operand of `%s' must be `%s%s'"),
4689 i.tm.name, register_prefix, reg);
4690 else
4691 as_bad (_("the first operand of `%s' must be `%s%s'"),
4692 i.tm.name, register_prefix, reg);
4693 return 0;
4694}
4695
29b0f896 4696static int
e3bb37b5 4697process_operands (void)
29b0f896
AM		 4698{
4699 /* Default segment register this instruction will use for memory
4700 accesses. 0 means unknown. This is only for optimizing out
4701 unnecessary segment overrides. */
4702 const seg_entry *default_seg = 0;
4703
c0f3af97
L		 4704 if (i.tm.opcode_modifier.sse2avx
4705 && (i.tm.opcode_modifier.vexnds
4706 || i.tm.opcode_modifier.vexndd))
29b0f896 4707 {
c0f3af97
L		 4708 unsigned int dup = i.operands;
4709 unsigned int dest = dup - 1;
9fcfb3d7
L		 4710 unsigned int j;
4711
c0f3af97 4712 /* The destination must be an xmm register. */
9c2799c2 4713 gas_assert (i.reg_operands
7ab9ffdd
L		 4714 && MAX_OPERANDS > dup
4715 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 4716
4717 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 4718 {
c0f3af97 4719 /* The first operand is implicit and must be xmm0. */
9c2799c2 4720 gas_assert (operand_type_equal (&i.types[0], &regxmm));
c0f3af97
L		 4721 if (i.op[0].regs->reg_num != 0)
4722 return bad_implicit_operand (1);
4723
4724 if (i.tm.opcode_modifier.vex3sources)
4725 {
4726 /* Keep xmm0 for instructions with VEX prefix and 3
4727 sources. */
4728 goto duplicate;
4729 }
e2ec9d29 4730 else
c0f3af97
L		 4731 {
4732 /* We remove the first xmm0 and keep the number of
4733 operands unchanged, which in fact duplicates the
4734 destination. */
4735 for (j = 1; j < i.operands; j++)
4736 {
4737 i.op[j - 1] = i.op[j];
4738 i.types[j - 1] = i.types[j];
4739 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
4740 }
4741 }
4742 }
4743 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 4744 {
9c2799c2 4745 gas_assert ((MAX_OPERANDS - 1) > dup
7ab9ffdd 4746 && i.tm.opcode_modifier.vex3sources);
c0f3af97
L		 4747
4748 /* Add the implicit xmm0 for instructions with VEX prefix
4749 and 3 sources. */
4750 for (j = i.operands; j > 0; j--)
4751 {
4752 i.op[j] = i.op[j - 1];
4753 i.types[j] = i.types[j - 1];
4754 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
4755 }
4756 i.op[0].regs
4757 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 4758 i.types[0] = regxmm;
c0f3af97
L		 4759 i.tm.operand_types[0] = regxmm;
4760
4761 i.operands += 2;
4762 i.reg_operands += 2;
4763 i.tm.operands += 2;
4764
4765 dup++;
4766 dest++;
4767 i.op[dup] = i.op[dest];
4768 i.types[dup] = i.types[dest];
4769 i.tm.operand_types[dup] = i.tm.operand_types[dest];
e2ec9d29 4770 }
c0f3af97
L		 4771 else
4772 {
4773duplicate:
4774 i.operands++;
4775 i.reg_operands++;
4776 i.tm.operands++;
4777
4778 i.op[dup] = i.op[dest];
4779 i.types[dup] = i.types[dest];
4780 i.tm.operand_types[dup] = i.tm.operand_types[dest];
4781 }
4782
4783 if (i.tm.opcode_modifier.immext)
4784 process_immext ();
4785 }
4786 else if (i.tm.opcode_modifier.firstxmm0)
4787 {
4788 unsigned int j;
4789
4790 /* The first operand is implicit and must be xmm0/ymm0. */
9c2799c2 4791 gas_assert (i.reg_operands
7ab9ffdd
L		 4792 && (operand_type_equal (&i.types[0], &regxmm)
4793 || operand_type_equal (&i.types[0], &regymm)));
c0f3af97
L		 4794 if (i.op[0].regs->reg_num != 0)
4795 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 4796
4797 for (j = 1; j < i.operands; j++)
4798 {
4799 i.op[j - 1] = i.op[j];
4800 i.types[j - 1] = i.types[j];
4801
4802 /* We need to adjust fields in i.tm since they are used by
4803 build_modrm_byte. */
4804 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
4805 }
4806
e2ec9d29
L		 4807 i.operands--;
4808 i.reg_operands--;
e2ec9d29
L		 4809 i.tm.operands--;
4810 }
4811 else if (i.tm.opcode_modifier.regkludge)
4812 {
4813 /* The imul $imm, %reg instruction is converted into
4814 imul $imm, %reg, %reg, and the clr %reg instruction
4815 is converted into xor %reg, %reg. */
4816
4817 unsigned int first_reg_op;
4818
4819 if (operand_type_check (i.types[0], reg))
4820 first_reg_op = 0;
4821 else
4822 first_reg_op = 1;
4823 /* Pretend we saw the extra register operand. */
9c2799c2 4824 gas_assert (i.reg_operands == 1
7ab9ffdd 4825 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 4826 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
4827 i.types[first_reg_op + 1] = i.types[first_reg_op];
4828 i.operands++;
4829 i.reg_operands++;
29b0f896
AM		 4830 }
4831
40fb9820 4832 if (i.tm.opcode_modifier.shortform)
29b0f896 4833 {
40fb9820
L		 4834 if (i.types[0].bitfield.sreg2
4835 || i.types[0].bitfield.sreg3)
29b0f896 4836 {
4eed87de
AM		 4837 if (i.tm.base_opcode == POP_SEG_SHORT
4838 && i.op[0].regs->reg_num == 1)
29b0f896 4839 {
a87af027 4840 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 4841 return 0;
29b0f896 4842 }
4eed87de
AM		 4843 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
4844 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 4845 i.rex |= REX_B;
4eed87de
AM		 4846 }
4847 else
4848 {
7ab9ffdd 4849 /* The register or float register operand is in operand
85f10a01 4850 0 or 1. */
40fb9820 4851 unsigned int op;
7ab9ffdd
L		 4852
4853 if (i.types[0].bitfield.floatreg
4854 || operand_type_check (i.types[0], reg))
4855 op = 0;
4856 else
4857 op = 1;
4eed87de
AM		 4858 /* Register goes in low 3 bits of opcode. */
4859 i.tm.base_opcode |= i.op[op].regs->reg_num;
4860 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 4861 i.rex |= REX_B;
40fb9820 4862 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 4863 {
4eed87de
AM		 4864 /* Warn about some common errors, but press on regardless.
4865 The first case can be generated by gcc (<= 2.8.1). */
4866 if (i.operands == 2)
4867 {
4868 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 4869 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 4870 register_prefix, i.op[!intel_syntax].regs->reg_name,
4871 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 4872 }
4873 else
4874 {
4875 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 4876 as_warn (_("translating to `%s %s%s'"), i.tm.name,
4877 register_prefix, i.op[0].regs->reg_name);
4eed87de 4878 }
29b0f896
AM		 4879 }
4880 }
4881 }
40fb9820 4882 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 4883 {
4884 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 4885 must be put into the modrm byte). Now, we make the modrm and
4886 index base bytes based on all the info we've collected. */
29b0f896
AM		 4887
4888 default_seg = build_modrm_byte ();
4889 }
8a2ed489 4890 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 4891 {
4892 default_seg = &ds;
4893 }
40fb9820 4894 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 4895 {
4896 /* For the string instructions that allow a segment override
4897 on one of their operands, the default segment is ds. */
4898 default_seg = &ds;
4899 }
4900
75178d9d
L		 4901 if (i.tm.base_opcode == 0x8d /* lea */
4902 && i.seg[0]
4903 && !quiet_warnings)
30123838 4904 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 4905
4906 /* If a segment was explicitly specified, and the specified segment
4907 is not the default, use an opcode prefix to select it. If we
4908 never figured out what the default segment is, then default_seg
4909 will be zero at this point, and the specified segment prefix will
4910 always be used. */
29b0f896
AM		 4911 if ((i.seg[0]) && (i.seg[0] != default_seg))
4912 {
4913 if (!add_prefix (i.seg[0]->seg_prefix))
4914 return 0;
4915 }
4916 return 1;
4917}
4918
4919static const seg_entry *
e3bb37b5 4920build_modrm_byte (void)
29b0f896
AM		 4921{
4922 const seg_entry *default_seg = 0;
c0f3af97 4923 unsigned int source, dest;
5dd85c99 4924 int vex_3_sources, vex_2_sources;
c0f3af97
L		 4925
4926 /* The first operand of instructions with VEX prefix and 3 sources
4927 must be VEX_Imm4. */
4928 vex_3_sources = i.tm.opcode_modifier.vex3sources;
5dd85c99 4929 vex_2_sources = i.tm.opcode_modifier.vex2sources;
c0f3af97
L		 4930 if (vex_3_sources)
4931 {
4932 unsigned int nds, reg;
4c2c6516 4933 expressionS *exp;
c0f3af97 4934
922d8de8
DR		 4935 if (i.tm.opcode_modifier.veximmext
4936 && i.tm.opcode_modifier.immext)
4937 {
4938 dest = i.operands - 2;
4939 gas_assert (dest == 3);
4940 }
4941 else
0bfee649 4942 dest = i.operands - 1;
c0f3af97 4943 nds = dest - 1;
922d8de8 4944
76ba9986
L		 4945 /* This instruction must have 4 register operands
4946 or 3 register operands plus 1 memory operand.
922d8de8
DR		 4947 It must have VexNDS and VexImmExt. */
4948 gas_assert ((i.reg_operands == 4
7ab9ffdd
L		 4949 || (i.reg_operands == 3 && i.mem_operands == 1))
4950 && i.tm.opcode_modifier.vexnds
4951 && i.tm.opcode_modifier.veximmext
922d8de8
DR		 4952 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
4953 || operand_type_equal (&i.tm.operand_types[dest], &regymm)));
c0f3af97 4954
0bfee649
L		 4955 /* Generate an 8bit immediate operand to encode the register
4956 operand. */
4c2c6516 4957 exp = &im_expressions[i.imm_operands++];
0bfee649
L		 4958 i.op[i.operands].imms = exp;
4959 i.types[i.operands] = imm8;
4960 i.operands++;
922d8de8
DR		 4961 /* If VexW1 is set, the first operand is the source and
4962 the second operand is encoded in the immediate operand. */
4963 if (i.tm.opcode_modifier.vexw1)
4964 {
4965 source = 0;
4966 reg = 1;
4967 }
4968 else
4969 {
4970 source = 1;
4971 reg = 0;
76ba9986 4972 }
922d8de8
DR		 4973 gas_assert ((operand_type_equal (&i.tm.operand_types[reg], &regxmm)
4974 || operand_type_equal (&i.tm.operand_types[reg],
76ba9986 4975 &regymm))
922d8de8 4976 && (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
76ba9986 4977 || operand_type_equal (&i.tm.operand_types[nds],
922d8de8 4978 &regymm)));
0bfee649
L		 4979 exp->X_op = O_constant;
4980 exp->X_add_number
922d8de8 4981 = ((i.op[reg].regs->reg_num
76ba9986 4982 + ((i.op[reg].regs->reg_flags & RegRex) ? 8 : 0)) << 4);
dae39acc 4983 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 4984 }
4985 else
4986 source = dest = 0;
29b0f896
AM		 4987
4988 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 4989 implicit registers do not count. If there are 3 register
4990 operands, it must be a instruction with VexNDS. For a
4991 instruction with VexNDD, the destination register is encoded
4992 in VEX prefix. If there are 4 register operands, it must be
4993 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 4994 if (i.mem_operands == 0
4995 && ((i.reg_operands == 2
f88c9eb0
SP		 4996 && !i.tm.opcode_modifier.vexndd
4997 && !i.tm.opcode_modifier.vexlwp)
7ab9ffdd
L		 4998 || (i.reg_operands == 3
4999 && i.tm.opcode_modifier.vexnds)
5000 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 5001 {
cab737b9
L		 5002 switch (i.operands)
5003 {
5004 case 2:
5005 source = 0;
5006 break;
5007 case 3:
c81128dc
L		 5008 /* When there are 3 operands, one of them may be immediate,
5009 which may be the first or the last operand. Otherwise,
c0f3af97
L		 5010 the first operand must be shift count register (cl) or it
5011 is an instruction with VexNDS. */
9c2799c2 5012 gas_assert (i.imm_operands == 1
7ab9ffdd
L		 5013 || (i.imm_operands == 0
5014 && (i.tm.opcode_modifier.vexnds
5015 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 5016 if (operand_type_check (i.types[0], imm)
5017 || i.types[0].bitfield.shiftcount)
5018 source = 1;
5019 else
5020 source = 0;
cab737b9
L		 5021 break;
5022 case 4:
368d64cc
L		 5023 /* When there are 4 operands, the first two must be 8bit
5024 immediate operands. The source operand will be the 3rd
c0f3af97
L		 5025 one.
5026
5027 For instructions with VexNDS, if the first operand
5028 an imm8, the source operand is the 2nd one. If the last
5029 operand is imm8, the source operand is the first one. */
9c2799c2 5030 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 5031 && i.types[0].bitfield.imm8
5032 && i.types[1].bitfield.imm8)
5033 || (i.tm.opcode_modifier.vexnds
5034 && i.imm_operands == 1
5035 && (i.types[0].bitfield.imm8
5036 || i.types[i.operands - 1].bitfield.imm8)));
c0f3af97
L		 5037 if (i.tm.opcode_modifier.vexnds)
5038 {
5039 if (i.types[0].bitfield.imm8)
5040 source = 1;
5041 else
5042 source = 0;
5043 }
5044 else
5045 source = 2;
5046 break;
5047 case 5:
cab737b9
L		 5048 break;
5049 default:
5050 abort ();
5051 }
5052
c0f3af97
L		 5053 if (!vex_3_sources)
5054 {
5055 dest = source + 1;
5056
5057 if (i.tm.opcode_modifier.vexnds)
5058 {
5059 /* For instructions with VexNDS, the register-only
5060 source operand must be XMM or YMM register. It is
fa99fab2
L		 5061 encoded in VEX prefix. We need to clear RegMem bit
5062 before calling operand_type_equal. */
5063 i386_operand_type op = i.tm.operand_types[dest];
5064 op.bitfield.regmem = 0;
c0f3af97 5065 if ((dest + 1) >= i.operands
fa99fab2
L		 5066 || (!operand_type_equal (&op, &regxmm)
5067 && !operand_type_equal (&op, &regymm)))
c0f3af97
L		 5068 abort ();
5069 i.vex.register_specifier = i.op[dest].regs;
5070 dest++;
5071 }
5072 }
29b0f896
AM		 5073
5074 i.rm.mode = 3;
5075 /* One of the register operands will be encoded in the i.tm.reg
5076 field, the other in the combined i.tm.mode and i.tm.regmem
5077 fields. If no form of this instruction supports a memory
5078 destination operand, then we assume the source operand may
5079 sometimes be a memory operand and so we need to store the
5080 destination in the i.rm.reg field. */
40fb9820
L		 5081 if (!i.tm.operand_types[dest].bitfield.regmem
5082 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 5083 {
5084 i.rm.reg = i.op[dest].regs->reg_num;
5085 i.rm.regmem = i.op[source].regs->reg_num;
5086 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5087 i.rex |= REX_R;
29b0f896 5088 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5089 i.rex |= REX_B;
29b0f896
AM		 5090 }
5091 else
5092 {
5093 i.rm.reg = i.op[source].regs->reg_num;
5094 i.rm.regmem = i.op[dest].regs->reg_num;
5095 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5096 i.rex |= REX_B;
29b0f896 5097 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5098 i.rex |= REX_R;
29b0f896 5099 }
161a04f6 5100 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 5101 {
40fb9820
L		 5102 if (!i.types[0].bitfield.control
5103 && !i.types[1].bitfield.control)
c4a530c5 5104 abort ();
161a04f6 5105 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 5106 add_prefix (LOCK_PREFIX_OPCODE);
5107 }
29b0f896
AM		 5108 }
5109 else
5110 { /* If it's not 2 reg operands... */
c0f3af97
L		 5111 unsigned int mem;
5112
29b0f896
AM		 5113 if (i.mem_operands)
5114 {
5115 unsigned int fake_zero_displacement = 0;
99018f42 5116 unsigned int op;
4eed87de 5117
7ab9ffdd
L		 5118 for (op = 0; op < i.operands; op++)
5119 if (operand_type_check (i.types[op], anymem))
5120 break;
7ab9ffdd 5121 gas_assert (op < i.operands);
29b0f896
AM		 5122
5123 default_seg = &ds;
5124
5125 if (i.base_reg == 0)
5126 {
5127 i.rm.mode = 0;
5128 if (!i.disp_operands)
5129 fake_zero_displacement = 1;
5130 if (i.index_reg == 0)
5131 {
5132 /* Operand is just <disp> */
20f0a1fc 5133 if (flag_code == CODE_64BIT)
29b0f896
AM		 5134 {
5135 /* 64bit mode overwrites the 32bit absolute
5136 addressing by RIP relative addressing and
5137 absolute addressing is encoded by one of the
5138 redundant SIB forms. */
5139 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5140 i.sib.base = NO_BASE_REGISTER;
5141 i.sib.index = NO_INDEX_REGISTER;
fc225355 5142 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 5143 ? disp32s : disp32);
20f0a1fc 5144 }
fc225355
L		 5145 else if ((flag_code == CODE_16BIT)
5146 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 5147 {
5148 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 5149 i.types[op] = disp16;
20f0a1fc
NC		 5150 }
5151 else
5152 {
5153 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 5154 i.types[op] = disp32;
29b0f896
AM		 5155 }
5156 }
5157 else /* !i.base_reg && i.index_reg */
5158 {
db51cc60
L		 5159 if (i.index_reg->reg_num == RegEiz
5160 || i.index_reg->reg_num == RegRiz)
5161 i.sib.index = NO_INDEX_REGISTER;
5162 else
5163 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5164 i.sib.base = NO_BASE_REGISTER;
5165 i.sib.scale = i.log2_scale_factor;
5166 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 5167 i.types[op].bitfield.disp8 = 0;
5168 i.types[op].bitfield.disp16 = 0;
5169 i.types[op].bitfield.disp64 = 0;
29b0f896 5170 if (flag_code != CODE_64BIT)
40fb9820
L		 5171 {
5172 /* Must be 32 bit */
5173 i.types[op].bitfield.disp32 = 1;
5174 i.types[op].bitfield.disp32s = 0;
5175 }
29b0f896 5176 else
40fb9820
L		 5177 {
5178 i.types[op].bitfield.disp32 = 0;
5179 i.types[op].bitfield.disp32s = 1;
5180 }
29b0f896 5181 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5182 i.rex |= REX_X;
29b0f896
AM		 5183 }
5184 }
5185 /* RIP addressing for 64bit mode. */
9a04903e
JB		 5186 else if (i.base_reg->reg_num == RegRip ||
5187 i.base_reg->reg_num == RegEip)
29b0f896
AM		 5188 {
5189 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 5190 i.types[op].bitfield.disp8 = 0;
5191 i.types[op].bitfield.disp16 = 0;
5192 i.types[op].bitfield.disp32 = 0;
5193 i.types[op].bitfield.disp32s = 1;
5194 i.types[op].bitfield.disp64 = 0;
71903a11 5195 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 5196 if (! i.disp_operands)
5197 fake_zero_displacement = 1;
29b0f896 5198 }
40fb9820 5199 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896
AM		 5200 {
5201 switch (i.base_reg->reg_num)
5202 {
5203 case 3: /* (%bx) */
5204 if (i.index_reg == 0)
5205 i.rm.regmem = 7;
5206 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5207 i.rm.regmem = i.index_reg->reg_num - 6;
5208 break;
5209 case 5: /* (%bp) */
5210 default_seg = &ss;
5211 if (i.index_reg == 0)
5212 {
5213 i.rm.regmem = 6;
40fb9820 5214 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 5215 {
5216 /* fake (%bp) into 0(%bp) */
40fb9820 5217 i.types[op].bitfield.disp8 = 1;
252b5132 5218 fake_zero_displacement = 1;
29b0f896
AM		 5219 }
5220 }
5221 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5222 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
5223 break;
5224 default: /* (%si) -> 4 or (%di) -> 5 */
5225 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
5226 }
5227 i.rm.mode = mode_from_disp_size (i.types[op]);
5228 }
5229 else /* i.base_reg and 32/64 bit mode */
5230 {
5231 if (flag_code == CODE_64BIT
40fb9820
L		 5232 && operand_type_check (i.types[op], disp))
5233 {
5234 i386_operand_type temp;
0dfbf9d7 5235 operand_type_set (&temp, 0);
40fb9820
L		 5236 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
5237 i.types[op] = temp;
5238 if (i.prefix[ADDR_PREFIX] == 0)
5239 i.types[op].bitfield.disp32s = 1;
5240 else
5241 i.types[op].bitfield.disp32 = 1;
5242 }
20f0a1fc 5243
29b0f896
AM		 5244 i.rm.regmem = i.base_reg->reg_num;
5245 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 5246 i.rex |= REX_B;
29b0f896
AM		 5247 i.sib.base = i.base_reg->reg_num;
5248 /* x86-64 ignores REX prefix bit here to avoid decoder
5249 complications. */
5250 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
5251 {
5252 default_seg = &ss;
5253 if (i.disp_operands == 0)
5254 {
5255 fake_zero_displacement = 1;
40fb9820 5256 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 5257 }
5258 }
5259 else if (i.base_reg->reg_num == ESP_REG_NUM)
5260 {
5261 default_seg = &ss;
5262 }
5263 i.sib.scale = i.log2_scale_factor;
5264 if (i.index_reg == 0)
5265 {
5266 /* <disp>(%esp) becomes two byte modrm with no index
5267 register. We've already stored the code for esp
5268 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5269 Any base register besides %esp will not use the
5270 extra modrm byte. */
5271 i.sib.index = NO_INDEX_REGISTER;
29b0f896
AM		 5272 }
5273 else
5274 {
db51cc60
L		 5275 if (i.index_reg->reg_num == RegEiz
5276 || i.index_reg->reg_num == RegRiz)
5277 i.sib.index = NO_INDEX_REGISTER;
5278 else
5279 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5280 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5281 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5282 i.rex |= REX_X;
29b0f896 5283 }
67a4f2b7
AO		 5284
5285 if (i.disp_operands
5286 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
5287 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
5288 i.rm.mode = 0;
5289 else
5290 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 5291 }
252b5132 5292
29b0f896
AM		 5293 if (fake_zero_displacement)
5294 {
5295 /* Fakes a zero displacement assuming that i.types[op]
5296 holds the correct displacement size. */
5297 expressionS *exp;
5298
9c2799c2 5299 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 5300 exp = &disp_expressions[i.disp_operands++];
5301 i.op[op].disps = exp;
5302 exp->X_op = O_constant;
5303 exp->X_add_number = 0;
5304 exp->X_add_symbol = (symbolS *) 0;
5305 exp->X_op_symbol = (symbolS *) 0;
5306 }
c0f3af97
L		 5307
5308 mem = op;
29b0f896 5309 }
c0f3af97
L		 5310 else
5311 mem = ~0;
252b5132 5312
5dd85c99
SP		 5313 if (vex_2_sources)
5314 {
5315 if (operand_type_check (i.types[0], imm))
5316 i.vex.register_specifier = NULL;
5317 else
5318 {
5319 /* VEX.vvvv encodes one of the sources when the first
5320 operand is not an immediate. */
5321 if (i.tm.opcode_modifier.vexw0)
5322 i.vex.register_specifier = i.op[0].regs;
5323 else
5324 i.vex.register_specifier = i.op[1].regs;
5325 }
5326
5327 /* Destination is a XMM register encoded in the ModRM.reg
5328 and VEX.R bit. */
5329 i.rm.reg = i.op[2].regs->reg_num;
5330 if ((i.op[2].regs->reg_flags & RegRex) != 0)
5331 i.rex |= REX_R;
5332
5333 /* ModRM.rm and VEX.B encodes the other source. */
5334 if (!i.mem_operands)
5335 {
5336 i.rm.mode = 3;
5337
5338 if (i.tm.opcode_modifier.vexw0)
5339 i.rm.regmem = i.op[1].regs->reg_num;
5340 else
5341 i.rm.regmem = i.op[0].regs->reg_num;
5342
5343 if ((i.op[1].regs->reg_flags & RegRex) != 0)
5344 i.rex |= REX_B;
5345 }
5346 }
5347 else if (i.tm.opcode_modifier.vexlwp)
f88c9eb0
SP		 5348 {
5349 i.vex.register_specifier = i.op[2].regs;
5350 if (!i.mem_operands)
5351 {
5352 i.rm.mode = 3;
5353 i.rm.regmem = i.op[1].regs->reg_num;
5354 if ((i.op[1].regs->reg_flags & RegRex) != 0)
5355 i.rex |= REX_B;
5356 }
5357 }
29b0f896
AM		 5358 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5359 (if any) based on i.tm.extension_opcode. Again, we must be
5360 careful to make sure that segment/control/debug/test/MMX
5361 registers are coded into the i.rm.reg field. */
f88c9eb0 5362 else if (i.reg_operands)
29b0f896 5363 {
99018f42 5364 unsigned int op;
7ab9ffdd
L		 5365 unsigned int vex_reg = ~0;
5366
5367 for (op = 0; op < i.operands; op++)
5368 if (i.types[op].bitfield.reg8
5369 || i.types[op].bitfield.reg16
5370 || i.types[op].bitfield.reg32
5371 || i.types[op].bitfield.reg64
5372 || i.types[op].bitfield.regmmx
5373 || i.types[op].bitfield.regxmm
5374 || i.types[op].bitfield.regymm
5375 || i.types[op].bitfield.sreg2
5376 || i.types[op].bitfield.sreg3
5377 || i.types[op].bitfield.control
5378 || i.types[op].bitfield.debug
5379 || i.types[op].bitfield.test)
5380 break;
c0209578 5381
7ab9ffdd
L		 5382 if (vex_3_sources)
5383 op = dest;
5384 else if (i.tm.opcode_modifier.vexnds)
5385 {
5386 /* For instructions with VexNDS, the register-only
5387 source operand is encoded in VEX prefix. */
5388 gas_assert (mem != (unsigned int) ~0);
c0f3af97 5389
7ab9ffdd 5390 if (op > mem)
c0f3af97 5391 {
7ab9ffdd
L		 5392 vex_reg = op++;
5393 gas_assert (op < i.operands);
c0f3af97
L		 5394 }
5395 else
c0f3af97 5396 {
7ab9ffdd
L		 5397 vex_reg = op + 1;
5398 gas_assert (vex_reg < i.operands);
c0f3af97 5399 }
7ab9ffdd
L		 5400 }
5401 else if (i.tm.opcode_modifier.vexndd)
5402 {
5403 /* For instructions with VexNDD, there should be
5404 no memory operand and the register destination
5405 is encoded in VEX prefix. */
5406 gas_assert (i.mem_operands == 0
5407 && (op + 2) == i.operands);
5408 vex_reg = op + 1;
5409 }
5410 else
5411 gas_assert (op < i.operands);
99018f42 5412
7ab9ffdd
L		 5413 if (vex_reg != (unsigned int) ~0)
5414 {
5415 gas_assert (i.reg_operands == 2);
5416
5417 if (!operand_type_equal (&i.tm.operand_types[vex_reg],
76ba9986 5418 &regxmm)
7ab9ffdd
L		 5419 && !operand_type_equal (&i.tm.operand_types[vex_reg],
5420 &regymm))
5421 abort ();
f88c9eb0 5422
7ab9ffdd
L		 5423 i.vex.register_specifier = i.op[vex_reg].regs;
5424 }
5425
1b9f0c97
L		 5426 /* Don't set OP operand twice. */
5427 if (vex_reg != op)
7ab9ffdd 5428 {
1b9f0c97
L		 5429 /* If there is an extension opcode to put here, the
5430 register number must be put into the regmem field. */
5431 if (i.tm.extension_opcode != None)
5432 {
5433 i.rm.regmem = i.op[op].regs->reg_num;
5434 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5435 i.rex |= REX_B;
5436 }
5437 else
5438 {
5439 i.rm.reg = i.op[op].regs->reg_num;
5440 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5441 i.rex |= REX_R;
5442 }
7ab9ffdd 5443 }
252b5132 5444
29b0f896
AM		 5445 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5446 must set it to 3 to indicate this is a register operand
5447 in the regmem field. */
5448 if (!i.mem_operands)
5449 i.rm.mode = 3;
5450 }
252b5132 5451
29b0f896 5452 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 5453 if (i.tm.extension_opcode != None)
29b0f896
AM		 5454 i.rm.reg = i.tm.extension_opcode;
5455 }
5456 return default_seg;
5457}
252b5132 5458
29b0f896 5459static void
e3bb37b5 5460output_branch (void)
29b0f896
AM		 5461{
5462 char *p;
5463 int code16;
5464 int prefix;
5465 relax_substateT subtype;
5466 symbolS *sym;
5467 offsetT off;
5468
5469 code16 = 0;
5470 if (flag_code == CODE_16BIT)
5471 code16 = CODE16;
5472
5473 prefix = 0;
5474 if (i.prefix[DATA_PREFIX] != 0)
252b5132 5475 {
29b0f896
AM		 5476 prefix = 1;
5477 i.prefixes -= 1;
5478 code16 ^= CODE16;
252b5132 5479 }
29b0f896
AM		 5480 /* Pentium4 branch hints. */
5481 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5482 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 5483 {
29b0f896
AM		 5484 prefix++;
5485 i.prefixes--;
5486 }
5487 if (i.prefix[REX_PREFIX] != 0)
5488 {
5489 prefix++;
5490 i.prefixes--;
2f66722d
AM		 5491 }
5492
29b0f896
AM		 5493 if (i.prefixes != 0 && !intel_syntax)
5494 as_warn (_("skipping prefixes on this instruction"));
5495
5496 /* It's always a symbol; End frag & setup for relax.
5497 Make sure there is enough room in this frag for the largest
5498 instruction we may generate in md_convert_frag. This is 2
5499 bytes for the opcode and room for the prefix and largest
5500 displacement. */
5501 frag_grow (prefix + 2 + 4);
5502 /* Prefix and 1 opcode byte go in fr_fix. */
5503 p = frag_more (prefix + 1);
5504 if (i.prefix[DATA_PREFIX] != 0)
5505 *p++ = DATA_PREFIX_OPCODE;
5506 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
5507 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
5508 *p++ = i.prefix[SEG_PREFIX];
5509 if (i.prefix[REX_PREFIX] != 0)
5510 *p++ = i.prefix[REX_PREFIX];
5511 *p = i.tm.base_opcode;
5512
5513 if ((unsigned char) *p == JUMP_PC_RELATIVE)
5514 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
40fb9820 5515 else if (cpu_arch_flags.bitfield.cpui386)
29b0f896
AM		 5516 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
5517 else
5518 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
5519 subtype |= code16;
3e73aa7c 5520
29b0f896
AM		 5521 sym = i.op[0].disps->X_add_symbol;
5522 off = i.op[0].disps->X_add_number;
3e73aa7c 5523
29b0f896
AM		 5524 if (i.op[0].disps->X_op != O_constant
5525 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 5526 {
29b0f896
AM		 5527 /* Handle complex expressions. */
5528 sym = make_expr_symbol (i.op[0].disps);
5529 off = 0;
5530 }
3e73aa7c 5531
29b0f896
AM		 5532 /* 1 possible extra opcode + 4 byte displacement go in var part.
5533 Pass reloc in fr_var. */
5534 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
5535}
3e73aa7c 5536
29b0f896 5537static void
e3bb37b5 5538output_jump (void)
29b0f896
AM		 5539{
5540 char *p;
5541 int size;
3e02c1cc 5542 fixS *fixP;
29b0f896 5543
40fb9820 5544 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 5545 {
5546 /* This is a loop or jecxz type instruction. */
5547 size = 1;
5548 if (i.prefix[ADDR_PREFIX] != 0)
5549 {
5550 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
5551 i.prefixes -= 1;
5552 }
5553 /* Pentium4 branch hints. */
5554 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5555 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5556 {
5557 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
5558 i.prefixes--;
3e73aa7c
JH		 5559 }
5560 }
29b0f896
AM		 5561 else
5562 {
5563 int code16;
3e73aa7c 5564
29b0f896
AM		 5565 code16 = 0;
5566 if (flag_code == CODE_16BIT)
5567 code16 = CODE16;
3e73aa7c 5568
29b0f896
AM		 5569 if (i.prefix[DATA_PREFIX] != 0)
5570 {
5571 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
5572 i.prefixes -= 1;
5573 code16 ^= CODE16;
5574 }
252b5132 5575
29b0f896
AM		 5576 size = 4;
5577 if (code16)
5578 size = 2;
5579 }
9fcc94b6 5580
29b0f896
AM		 5581 if (i.prefix[REX_PREFIX] != 0)
5582 {
5583 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
5584 i.prefixes -= 1;
5585 }
252b5132 5586
29b0f896
AM		 5587 if (i.prefixes != 0 && !intel_syntax)
5588 as_warn (_("skipping prefixes on this instruction"));
e0890092 5589
29b0f896
AM		 5590 p = frag_more (1 + size);
5591 *p++ = i.tm.base_opcode;
e0890092 5592
3e02c1cc
AM		 5593 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5594 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
5595
5596 /* All jumps handled here are signed, but don't use a signed limit
5597 check for 32 and 16 bit jumps as we want to allow wrap around at
5598 4G and 64k respectively. */
5599 if (size == 1)
5600 fixP->fx_signed = 1;
29b0f896 5601}
e0890092 5602
29b0f896 5603static void
e3bb37b5 5604output_interseg_jump (void)
29b0f896
AM		 5605{
5606 char *p;
5607 int size;
5608 int prefix;
5609 int code16;
252b5132 5610
29b0f896
AM		 5611 code16 = 0;
5612 if (flag_code == CODE_16BIT)
5613 code16 = CODE16;
a217f122 5614
29b0f896
AM		 5615 prefix = 0;
5616 if (i.prefix[DATA_PREFIX] != 0)
5617 {
5618 prefix = 1;
5619 i.prefixes -= 1;
5620 code16 ^= CODE16;
5621 }
5622 if (i.prefix[REX_PREFIX] != 0)
5623 {
5624 prefix++;
5625 i.prefixes -= 1;
5626 }
252b5132 5627
29b0f896
AM		 5628 size = 4;
5629 if (code16)
5630 size = 2;
252b5132 5631
29b0f896
AM		 5632 if (i.prefixes != 0 && !intel_syntax)
5633 as_warn (_("skipping prefixes on this instruction"));
252b5132 5634
29b0f896
AM		 5635 /* 1 opcode; 2 segment; offset */
5636 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 5637
29b0f896
AM		 5638 if (i.prefix[DATA_PREFIX] != 0)
5639 *p++ = DATA_PREFIX_OPCODE;
252b5132 5640
29b0f896
AM		 5641 if (i.prefix[REX_PREFIX] != 0)
5642 *p++ = i.prefix[REX_PREFIX];
252b5132 5643
29b0f896
AM		 5644 *p++ = i.tm.base_opcode;
5645 if (i.op[1].imms->X_op == O_constant)
5646 {
5647 offsetT n = i.op[1].imms->X_add_number;
252b5132 5648
29b0f896
AM		 5649 if (size == 2
5650 && !fits_in_unsigned_word (n)
5651 && !fits_in_signed_word (n))
5652 {
5653 as_bad (_("16-bit jump out of range"));
5654 return;
5655 }
5656 md_number_to_chars (p, n, size);
5657 }
5658 else
5659 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5660 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
5661 if (i.op[0].imms->X_op != O_constant)
5662 as_bad (_("can't handle non absolute segment in `%s'"),
5663 i.tm.name);
5664 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
5665}
a217f122 5666
29b0f896 5667static void
e3bb37b5 5668output_insn (void)
29b0f896 5669{
2bbd9c25
JJ		 5670 fragS *insn_start_frag;
5671 offsetT insn_start_off;
5672
29b0f896
AM		 5673 /* Tie dwarf2 debug info to the address at the start of the insn.
5674 We can't do this after the insn has been output as the current
5675 frag may have been closed off. eg. by frag_var. */
5676 dwarf2_emit_insn (0);
5677
2bbd9c25
JJ		 5678 insn_start_frag = frag_now;
5679 insn_start_off = frag_now_fix ();
5680
29b0f896 5681 /* Output jumps. */
40fb9820 5682 if (i.tm.opcode_modifier.jump)
29b0f896 5683 output_branch ();
40fb9820
L		 5684 else if (i.tm.opcode_modifier.jumpbyte
5685 || i.tm.opcode_modifier.jumpdword)
29b0f896 5686 output_jump ();
40fb9820 5687 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 5688 output_interseg_jump ();
5689 else
5690 {
5691 /* Output normal instructions here. */
5692 char *p;
5693 unsigned char *q;
47465058 5694 unsigned int j;
331d2d0d 5695 unsigned int prefix;
4dffcebc 5696
c0f3af97
L		 5697 /* Since the VEX prefix contains the implicit prefix, we don't
5698 need the explicit prefix. */
5699 if (!i.tm.opcode_modifier.vex)
bc4bd9ab 5700 {
c0f3af97 5701 switch (i.tm.opcode_length)
bc4bd9ab 5702 {
c0f3af97
L		 5703 case 3:
5704 if (i.tm.base_opcode & 0xff000000)
4dffcebc 5705 {
c0f3af97
L		 5706 prefix = (i.tm.base_opcode >> 24) & 0xff;
5707 goto check_prefix;
5708 }
5709 break;
5710 case 2:
5711 if ((i.tm.base_opcode & 0xff0000) != 0)
5712 {
5713 prefix = (i.tm.base_opcode >> 16) & 0xff;
5714 if (i.tm.cpu_flags.bitfield.cpupadlock)
5715 {
4dffcebc 5716check_prefix:
c0f3af97 5717 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 5718 || (i.prefix[REP_PREFIX]
c0f3af97
L		 5719 != REPE_PREFIX_OPCODE))
5720 add_prefix (prefix);
5721 }
5722 else
4dffcebc
L		 5723 add_prefix (prefix);
5724 }
c0f3af97
L		 5725 break;
5726 case 1:
5727 break;
5728 default:
5729 abort ();
bc4bd9ab 5730 }
c0f3af97
L		 5731
5732 /* The prefix bytes. */
5733 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
5734 if (*q)
5735 FRAG_APPEND_1_CHAR (*q);
0f10071e 5736 }
252b5132 5737
c0f3af97
L		 5738 if (i.tm.opcode_modifier.vex)
5739 {
5740 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
5741 if (*q)
5742 switch (j)
5743 {
5744 case REX_PREFIX:
5745 /* REX byte is encoded in VEX prefix. */
5746 break;
5747 case SEG_PREFIX:
5748 case ADDR_PREFIX:
5749 FRAG_APPEND_1_CHAR (*q);
5750 break;
5751 default:
5752 /* There should be no other prefixes for instructions
5753 with VEX prefix. */
5754 abort ();
5755 }
5756
5757 /* Now the VEX prefix. */
5758 p = frag_more (i.vex.length);
5759 for (j = 0; j < i.vex.length; j++)
5760 p[j] = i.vex.bytes[j];
5761 }
252b5132 5762
29b0f896 5763 /* Now the opcode; be careful about word order here! */
4dffcebc 5764 if (i.tm.opcode_length == 1)
29b0f896
AM		 5765 {
5766 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5767 }
5768 else
5769 {
4dffcebc 5770 switch (i.tm.opcode_length)
331d2d0d 5771 {
4dffcebc 5772 case 3:
331d2d0d
L		 5773 p = frag_more (3);
5774 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 5775 break;
5776 case 2:
5777 p = frag_more (2);
5778 break;
5779 default:
5780 abort ();
5781 break;
331d2d0d 5782 }
0f10071e 5783
29b0f896
AM		 5784 /* Put out high byte first: can't use md_number_to_chars! */
5785 *p++ = (i.tm.base_opcode >> 8) & 0xff;
5786 *p = i.tm.base_opcode & 0xff;
5787 }
3e73aa7c 5788
29b0f896 5789 /* Now the modrm byte and sib byte (if present). */
40fb9820 5790 if (i.tm.opcode_modifier.modrm)
29b0f896 5791 {
4a3523fa
L		 5792 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
5793 | i.rm.reg << 3
5794 | i.rm.mode << 6));
29b0f896
AM		 5795 /* If i.rm.regmem == ESP (4)
5796 && i.rm.mode != (Register mode)
5797 && not 16 bit
5798 ==> need second modrm byte. */
5799 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
5800 && i.rm.mode != 3
40fb9820 5801 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 5802 FRAG_APPEND_1_CHAR ((i.sib.base << 0
5803 | i.sib.index << 3
5804 | i.sib.scale << 6));
29b0f896 5805 }
3e73aa7c 5806
29b0f896 5807 if (i.disp_operands)
2bbd9c25 5808 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 5809
29b0f896 5810 if (i.imm_operands)
2bbd9c25 5811 output_imm (insn_start_frag, insn_start_off);
29b0f896 5812 }
252b5132 5813
29b0f896
AM		 5814#ifdef DEBUG386
5815 if (flag_debug)
5816 {
7b81dfbb 5817 pi ("" /*line*/, &i);
29b0f896
AM		 5818 }
5819#endif /* DEBUG386 */
5820}
252b5132 5821
e205caa7
L		 5822/* Return the size of the displacement operand N. */
5823
5824static int
5825disp_size (unsigned int n)
5826{
5827 int size = 4;
40fb9820
L		 5828 if (i.types[n].bitfield.disp64)
5829 size = 8;
5830 else if (i.types[n].bitfield.disp8)
5831 size = 1;
5832 else if (i.types[n].bitfield.disp16)
5833 size = 2;
e205caa7
L		 5834 return size;
5835}
5836
5837/* Return the size of the immediate operand N. */
5838
5839static int
5840imm_size (unsigned int n)
5841{
5842 int size = 4;
40fb9820
L		 5843 if (i.types[n].bitfield.imm64)
5844 size = 8;
5845 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
5846 size = 1;
5847 else if (i.types[n].bitfield.imm16)
5848 size = 2;
e205caa7
L		 5849 return size;
5850}
5851
29b0f896 5852static void
64e74474 5853output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 5854{
5855 char *p;
5856 unsigned int n;
252b5132 5857
29b0f896
AM		 5858 for (n = 0; n < i.operands; n++)
5859 {
40fb9820 5860 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 5861 {
5862 if (i.op[n].disps->X_op == O_constant)
5863 {
e205caa7 5864 int size = disp_size (n);
29b0f896 5865 offsetT val;
252b5132 5866
29b0f896
AM		 5867 val = offset_in_range (i.op[n].disps->X_add_number,
5868 size);
5869 p = frag_more (size);
5870 md_number_to_chars (p, val, size);
5871 }
5872 else
5873 {
f86103b7 5874 enum bfd_reloc_code_real reloc_type;
e205caa7 5875 int size = disp_size (n);
40fb9820 5876 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 5877 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
5878
e205caa7 5879 /* We can't have 8 bit displacement here. */
9c2799c2 5880 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 5881
29b0f896
AM		 5882 /* The PC relative address is computed relative
5883 to the instruction boundary, so in case immediate
5884 fields follows, we need to adjust the value. */
5885 if (pcrel && i.imm_operands)
5886 {
29b0f896 5887 unsigned int n1;
e205caa7 5888 int sz = 0;
252b5132 5889
29b0f896 5890 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 5891 if (operand_type_check (i.types[n1], imm))
252b5132 5892 {
e205caa7
L		 5893 /* Only one immediate is allowed for PC
5894 relative address. */
9c2799c2 5895 gas_assert (sz == 0);
e205caa7
L		 5896 sz = imm_size (n1);
5897 i.op[n].disps->X_add_number -= sz;
252b5132 5898 }
29b0f896 5899 /* We should find the immediate. */
9c2799c2 5900 gas_assert (sz != 0);
29b0f896 5901 }
520dc8e8 5902
29b0f896 5903 p = frag_more (size);
2bbd9c25 5904 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 5905 if (GOT_symbol
2bbd9c25 5906 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 5907 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 5908 || reloc_type == BFD_RELOC_X86_64_32S
5909 || (reloc_type == BFD_RELOC_64
5910 && object_64bit))
d6ab8113
JB		 5911 && (i.op[n].disps->X_op == O_symbol
5912 || (i.op[n].disps->X_op == O_add
5913 && ((symbol_get_value_expression
5914 (i.op[n].disps->X_op_symbol)->X_op)
5915 == O_subtract))))
5916 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 5917 {
5918 offsetT add;
5919
5920 if (insn_start_frag == frag_now)
5921 add = (p - frag_now->fr_literal) - insn_start_off;
5922 else
5923 {
5924 fragS *fr;
5925
5926 add = insn_start_frag->fr_fix - insn_start_off;
5927 for (fr = insn_start_frag->fr_next;
5928 fr && fr != frag_now; fr = fr->fr_next)
5929 add += fr->fr_fix;
5930 add += p - frag_now->fr_literal;
5931 }
5932
4fa24527 5933 if (!object_64bit)
7b81dfbb
AJ		 5934 {
5935 reloc_type = BFD_RELOC_386_GOTPC;
5936 i.op[n].imms->X_add_number += add;
5937 }
5938 else if (reloc_type == BFD_RELOC_64)
5939 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 5940 else
7b81dfbb
AJ		 5941 /* Don't do the adjustment for x86-64, as there
5942 the pcrel addressing is relative to the _next_
5943 insn, and that is taken care of in other code. */
d6ab8113 5944 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 5945 }
062cd5e7 5946 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 5947 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 5948 }
5949 }
5950 }
5951}
252b5132 5952
29b0f896 5953static void
64e74474 5954output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 5955{
5956 char *p;
5957 unsigned int n;
252b5132 5958
29b0f896
AM		 5959 for (n = 0; n < i.operands; n++)
5960 {
40fb9820 5961 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 5962 {
5963 if (i.op[n].imms->X_op == O_constant)
5964 {
e205caa7 5965 int size = imm_size (n);
29b0f896 5966 offsetT val;
b4cac588 5967
29b0f896
AM		 5968 val = offset_in_range (i.op[n].imms->X_add_number,
5969 size);
5970 p = frag_more (size);
5971 md_number_to_chars (p, val, size);
5972 }
5973 else
5974 {
5975 /* Not absolute_section.
5976 Need a 32-bit fixup (don't support 8bit
5977 non-absolute imms). Try to support other
5978 sizes ... */
f86103b7 5979 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 5980 int size = imm_size (n);
5981 int sign;
29b0f896 5982
40fb9820 5983 if (i.types[n].bitfield.imm32s
a7d61044 5984 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 5985 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 5986 sign = 1;
e205caa7
L		 5987 else
5988 sign = 0;
520dc8e8 5989
29b0f896
AM		 5990 p = frag_more (size);
5991 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 5992
2bbd9c25
JJ		 5993 /* This is tough to explain. We end up with this one if we
5994 * have operands that look like
5995 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
5996 * obtain the absolute address of the GOT, and it is strongly
5997 * preferable from a performance point of view to avoid using
5998 * a runtime relocation for this. The actual sequence of
5999 * instructions often look something like:
6000 *
6001 * call .L66
6002 * .L66:
6003 * popl %ebx
6004 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6005 *
6006 * The call and pop essentially return the absolute address
6007 * of the label .L66 and store it in %ebx. The linker itself
6008 * will ultimately change the first operand of the addl so
6009 * that %ebx points to the GOT, but to keep things simple, the
6010 * .o file must have this operand set so that it generates not
6011 * the absolute address of .L66, but the absolute address of
6012 * itself. This allows the linker itself simply treat a GOTPC
6013 * relocation as asking for a pcrel offset to the GOT to be
6014 * added in, and the addend of the relocation is stored in the
6015 * operand field for the instruction itself.
6016 *
6017 * Our job here is to fix the operand so that it would add
6018 * the correct offset so that %ebx would point to itself. The
6019 * thing that is tricky is that .-.L66 will point to the
6020 * beginning of the instruction, so we need to further modify
6021 * the operand so that it will point to itself. There are
6022 * other cases where you have something like:
6023 *
6024 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6025 *
6026 * and here no correction would be required. Internally in
6027 * the assembler we treat operands of this form as not being
6028 * pcrel since the '.' is explicitly mentioned, and I wonder
6029 * whether it would simplify matters to do it this way. Who
6030 * knows. In earlier versions of the PIC patches, the
6031 * pcrel_adjust field was used to store the correction, but
6032 * since the expression is not pcrel, I felt it would be
6033 * confusing to do it this way. */
6034
d6ab8113 6035 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6036 || reloc_type == BFD_RELOC_X86_64_32S
6037 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 6038 && GOT_symbol
6039 && GOT_symbol == i.op[n].imms->X_add_symbol
6040 && (i.op[n].imms->X_op == O_symbol
6041 || (i.op[n].imms->X_op == O_add
6042 && ((symbol_get_value_expression
6043 (i.op[n].imms->X_op_symbol)->X_op)
6044 == O_subtract))))
6045 {
2bbd9c25
JJ		 6046 offsetT add;
6047
6048 if (insn_start_frag == frag_now)
6049 add = (p - frag_now->fr_literal) - insn_start_off;
6050 else
6051 {
6052 fragS *fr;
6053
6054 add = insn_start_frag->fr_fix - insn_start_off;
6055 for (fr = insn_start_frag->fr_next;
6056 fr && fr != frag_now; fr = fr->fr_next)
6057 add += fr->fr_fix;
6058 add += p - frag_now->fr_literal;
6059 }
6060
4fa24527 6061 if (!object_64bit)
d6ab8113 6062 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 6063 else if (size == 4)
d6ab8113 6064 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 6065 else if (size == 8)
6066 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 6067 i.op[n].imms->X_add_number += add;
29b0f896 6068 }
29b0f896
AM		 6069 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6070 i.op[n].imms, 0, reloc_type);
6071 }
6072 }
6073 }
252b5132
RH		 6074}
6075\f
d182319b
JB		 6076/* x86_cons_fix_new is called via the expression parsing code when a
6077 reloc is needed. We use this hook to get the correct .got reloc. */
6078static enum bfd_reloc_code_real got_reloc = NO_RELOC;
6079static int cons_sign = -1;
6080
6081void
e3bb37b5 6082x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 6083 expressionS *exp)
d182319b
JB		 6084{
6085 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
6086
6087 got_reloc = NO_RELOC;
6088
6089#ifdef TE_PE
6090 if (exp->X_op == O_secrel)
6091 {
6092 exp->X_op = O_symbol;
6093 r = BFD_RELOC_32_SECREL;
6094 }
6095#endif
6096
6097 fix_new_exp (frag, off, len, exp, 0, r);
6098}
6099
718ddfc0
JB		 6100#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6101# define lex_got(reloc, adjust, types) NULL
6102#else
f3c180ae
AM		 6103/* Parse operands of the form
6104 <symbol>@GOTOFF+<nnn>
6105 and similar .plt or .got references.
6106
6107 If we find one, set up the correct relocation in RELOC and copy the
6108 input string, minus the `@GOTOFF' into a malloc'd buffer for
6109 parsing by the calling routine. Return this buffer, and if ADJUST
6110 is non-null set it to the length of the string we removed from the
6111 input line. Otherwise return NULL. */
6112static char *
3956db08 6113lex_got (enum bfd_reloc_code_real *reloc,
64e74474 6114 int *adjust,
40fb9820 6115 i386_operand_type *types)
f3c180ae 6116{
7b81dfbb
AJ		 6117 /* Some of the relocations depend on the size of what field is to
6118 be relocated. But in our callers i386_immediate and i386_displacement
6119 we don't yet know the operand size (this will be set by insn
6120 matching). Hence we record the word32 relocation here,
6121 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 6122 static const struct {
6123 const char *str;
4fa24527 6124 const enum bfd_reloc_code_real rel[2];
40fb9820 6125 const i386_operand_type types64;
f3c180ae 6126 } gotrel[] = {
1e9cc1c2 6127 { "PLTOFF", { _dummy_first_bfd_reloc_code_real,
4eed87de 6128 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 6129 OPERAND_TYPE_IMM64 },
4eed87de
AM		 6130 { "PLT", { BFD_RELOC_386_PLT32,
6131 BFD_RELOC_X86_64_PLT32 },
40fb9820 6132 OPERAND_TYPE_IMM32_32S_DISP32 },
1e9cc1c2 6133 { "GOTPLT", { _dummy_first_bfd_reloc_code_real,
4eed87de 6134 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 6135 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 6136 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
6137 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 6138 OPERAND_TYPE_IMM64_DISP64 },
1e9cc1c2 6139 { "GOTPCREL", { _dummy_first_bfd_reloc_code_real,
4eed87de 6140 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 6141 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6142 { "TLSGD", { BFD_RELOC_386_TLS_GD,
6143 BFD_RELOC_X86_64_TLSGD },
40fb9820 6144 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de 6145 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
1e9cc1c2 6146 _dummy_first_bfd_reloc_code_real },
40fb9820 6147 OPERAND_TYPE_NONE },
1e9cc1c2 6148 { "TLSLD", { _dummy_first_bfd_reloc_code_real,
4eed87de 6149 BFD_RELOC_X86_64_TLSLD },
40fb9820 6150 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6151 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
6152 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 6153 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6154 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
6155 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 6156 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de 6157 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
1e9cc1c2 6158 _dummy_first_bfd_reloc_code_real },
40fb9820 6159 OPERAND_TYPE_NONE },
4eed87de
AM		 6160 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
6161 BFD_RELOC_X86_64_DTPOFF32 },
7ab9ffdd 6162
40fb9820 6163 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de 6164 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
1e9cc1c2 6165 _dummy_first_bfd_reloc_code_real },
40fb9820 6166 OPERAND_TYPE_NONE },
4eed87de 6167 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
1e9cc1c2 6168 _dummy_first_bfd_reloc_code_real },
40fb9820 6169 OPERAND_TYPE_NONE },
4eed87de
AM		 6170 { "GOT", { BFD_RELOC_386_GOT32,
6171 BFD_RELOC_X86_64_GOT32 },
40fb9820 6172 OPERAND_TYPE_IMM32_32S_64_DISP32 },
4eed87de
AM		 6173 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
6174 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 6175 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6176 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
6177 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 6178 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 6179 };
6180 char *cp;
6181 unsigned int j;
6182
718ddfc0
JB		 6183 if (!IS_ELF)
6184 return NULL;
6185
f3c180ae 6186 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 6187 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 6188 return NULL;
6189
47465058 6190 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae
AM		 6191 {
6192 int len;
6193
6194 len = strlen (gotrel[j].str);
28f81592 6195 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 6196 {
4fa24527 6197 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 6198 {
28f81592
AM		 6199 int first, second;
6200 char *tmpbuf, *past_reloc;
f3c180ae 6201
4fa24527 6202 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 6203 if (adjust)
6204 *adjust = len;
f3c180ae 6205
3956db08
JB		 6206 if (types)
6207 {
6208 if (flag_code != CODE_64BIT)
40fb9820
L		 6209 {
6210 types->bitfield.imm32 = 1;
6211 types->bitfield.disp32 = 1;
6212 }
3956db08
JB		 6213 else
6214 *types = gotrel[j].types64;
6215 }
6216
f3c180ae
AM		 6217 if (GOT_symbol == NULL)
6218 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
6219
28f81592 6220 /* The length of the first part of our input line. */
f3c180ae 6221 first = cp - input_line_pointer;
28f81592
AM		 6222
6223 /* The second part goes from after the reloc token until
67c11a9b 6224 (and including) an end_of_line char or comma. */
28f81592 6225 past_reloc = cp + 1 + len;
67c11a9b
AM		 6226 cp = past_reloc;
6227 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
6228 ++cp;
6229 second = cp + 1 - past_reloc;
28f81592
AM		 6230
6231 /* Allocate and copy string. The trailing NUL shouldn't
6232 be necessary, but be safe. */
1e9cc1c2 6233 tmpbuf = (char *) xmalloc (first + second + 2);
f3c180ae 6234 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 6235 if (second != 0 && *past_reloc != ' ')
6236 /* Replace the relocation token with ' ', so that
6237 errors like foo@GOTOFF1 will be detected. */
6238 tmpbuf[first++] = ' ';
6239 memcpy (tmpbuf + first, past_reloc, second);
6240 tmpbuf[first + second] = '\0';
f3c180ae
AM		 6241 return tmpbuf;
6242 }
6243
4fa24527
JB		 6244 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6245 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 6246 return NULL;
6247 }
6248 }
6249
6250 /* Might be a symbol version string. Don't as_bad here. */
6251 return NULL;
6252}
6253
f3c180ae 6254void
e3bb37b5 6255x86_cons (expressionS *exp, int size)
f3c180ae 6256{
ee86248c
JB		 6257 intel_syntax = -intel_syntax;
6258
4fa24527 6259 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 6260 {
6261 /* Handle @GOTOFF and the like in an expression. */
6262 char *save;
6263 char *gotfree_input_line;
6264 int adjust;
6265
6266 save = input_line_pointer;
3956db08 6267 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 6268 if (gotfree_input_line)
6269 input_line_pointer = gotfree_input_line;
6270
6271 expression (exp);
6272
6273 if (gotfree_input_line)
6274 {
6275 /* expression () has merrily parsed up to the end of line,
6276 or a comma - in the wrong buffer. Transfer how far
6277 input_line_pointer has moved to the right buffer. */
6278 input_line_pointer = (save
6279 + (input_line_pointer - gotfree_input_line)
6280 + adjust);
6281 free (gotfree_input_line);
3992d3b7
AM		 6282 if (exp->X_op == O_constant
6283 || exp->X_op == O_absent
6284 || exp->X_op == O_illegal
6285 || exp->X_op == O_register
6286 || exp->X_op == O_big)
6287 {
6288 char c = *input_line_pointer;
6289 *input_line_pointer = 0;
6290 as_bad (_("missing or invalid expression `%s'"), save);
6291 *input_line_pointer = c;
6292 }
f3c180ae
AM		 6293 }
6294 }
6295 else
6296 expression (exp);
ee86248c
JB		 6297
6298 intel_syntax = -intel_syntax;
6299
6300 if (intel_syntax)
6301 i386_intel_simplify (exp);
f3c180ae
AM		 6302}
6303#endif
6304
9f32dd5b
L		 6305static void
6306signed_cons (int size)
6482c264 6307{
d182319b
JB		 6308 if (flag_code == CODE_64BIT)
6309 cons_sign = 1;
6310 cons (size);
6311 cons_sign = -1;
6482c264
NC		 6312}
6313
d182319b 6314#ifdef TE_PE
6482c264
NC		 6315static void
6316pe_directive_secrel (dummy)
6317 int dummy ATTRIBUTE_UNUSED;
6318{
6319 expressionS exp;
6320
6321 do
6322 {
6323 expression (&exp);
6324 if (exp.X_op == O_symbol)
6325 exp.X_op = O_secrel;
6326
6327 emit_expr (&exp, 4);
6328 }
6329 while (*input_line_pointer++ == ',');
6330
6331 input_line_pointer--;
6332 demand_empty_rest_of_line ();
6333}
6482c264
NC		 6334#endif
6335
252b5132 6336static int
70e41ade 6337i386_immediate (char *imm_start)
252b5132
RH		 6338{
6339 char *save_input_line_pointer;
f3c180ae 6340 char *gotfree_input_line;
252b5132 6341 segT exp_seg = 0;
47926f60 6342 expressionS *exp;
40fb9820
L		 6343 i386_operand_type types;
6344
0dfbf9d7 6345 operand_type_set (&types, ~0);
252b5132
RH		 6346
6347 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
6348 {
31b2323c
L		 6349 as_bad (_("at most %d immediate operands are allowed"),
6350 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 6351 return 0;
6352 }
6353
6354 exp = &im_expressions[i.imm_operands++];
520dc8e8 6355 i.op[this_operand].imms = exp;
252b5132
RH		 6356
6357 if (is_space_char (*imm_start))
6358 ++imm_start;
6359
6360 save_input_line_pointer = input_line_pointer;
6361 input_line_pointer = imm_start;
6362
3956db08 6363 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6364 if (gotfree_input_line)
6365 input_line_pointer = gotfree_input_line;
252b5132
RH		 6366
6367 exp_seg = expression (exp);
6368
83183c0c 6369 SKIP_WHITESPACE ();
252b5132 6370 if (*input_line_pointer)
f3c180ae 6371 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 6372
6373 input_line_pointer = save_input_line_pointer;
f3c180ae 6374 if (gotfree_input_line)
ee86248c
JB		 6375 {
6376 free (gotfree_input_line);
6377
6378 if (exp->X_op == O_constant || exp->X_op == O_register)
6379 exp->X_op = O_illegal;
6380 }
6381
6382 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
6383}
252b5132 6384
ee86248c
JB		 6385static int
6386i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6387 i386_operand_type types, const char *imm_start)
6388{
6389 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 6390 {
313c53d1
L		 6391 if (imm_start)
6392 as_bad (_("missing or invalid immediate expression `%s'"),
6393 imm_start);
3992d3b7 6394 return 0;
252b5132 6395 }
3e73aa7c 6396 else if (exp->X_op == O_constant)
252b5132 6397 {
47926f60 6398 /* Size it properly later. */
40fb9820 6399 i.types[this_operand].bitfield.imm64 = 1;
3e73aa7c 6400 /* If BFD64, sign extend val. */
4eed87de
AM		 6401 if (!use_rela_relocations
6402 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
6403 exp->X_add_number
6404 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 6405 }
4c63da97 6406#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 6407 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 6408 && exp_seg != absolute_section
47926f60 6409 && exp_seg != text_section
24eab124
AM		 6410 && exp_seg != data_section
6411 && exp_seg != bss_section
6412 && exp_seg != undefined_section
f86103b7 6413 && !bfd_is_com_section (exp_seg))
252b5132 6414 {
d0b47220 6415 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 6416 return 0;
6417 }
6418#endif
bb8f5920
L		 6419 else if (!intel_syntax && exp->X_op == O_register)
6420 {
313c53d1
L		 6421 if (imm_start)
6422 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 6423 return 0;
6424 }
252b5132
RH		 6425 else
6426 {
6427 /* This is an address. The size of the address will be
24eab124 6428 determined later, depending on destination register,
3e73aa7c 6429 suffix, or the default for the section. */
40fb9820
L		 6430 i.types[this_operand].bitfield.imm8 = 1;
6431 i.types[this_operand].bitfield.imm16 = 1;
6432 i.types[this_operand].bitfield.imm32 = 1;
6433 i.types[this_operand].bitfield.imm32s = 1;
6434 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 6435 i.types[this_operand] = operand_type_and (i.types[this_operand],
6436 types);
252b5132
RH		 6437 }
6438
6439 return 1;
6440}
6441
551c1ca1 6442static char *
e3bb37b5 6443i386_scale (char *scale)
252b5132 6444{
551c1ca1
AM		 6445 offsetT val;
6446 char *save = input_line_pointer;
252b5132 6447
551c1ca1
AM		 6448 input_line_pointer = scale;
6449 val = get_absolute_expression ();
6450
6451 switch (val)
252b5132 6452 {
551c1ca1 6453 case 1:
252b5132
RH		 6454 i.log2_scale_factor = 0;
6455 break;
551c1ca1 6456 case 2:
252b5132
RH		 6457 i.log2_scale_factor = 1;
6458 break;
551c1ca1 6459 case 4:
252b5132
RH		 6460 i.log2_scale_factor = 2;
6461 break;
551c1ca1 6462 case 8:
252b5132
RH		 6463 i.log2_scale_factor = 3;
6464 break;
6465 default:
a724f0f4
JB		 6466 {
6467 char sep = *input_line_pointer;
6468
6469 *input_line_pointer = '\0';
6470 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6471 scale);
6472 *input_line_pointer = sep;
6473 input_line_pointer = save;
6474 return NULL;
6475 }
252b5132 6476 }
29b0f896 6477 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 6478 {
6479 as_warn (_("scale factor of %d without an index register"),
24eab124 6480 1 << i.log2_scale_factor);
252b5132 6481 i.log2_scale_factor = 0;
252b5132 6482 }
551c1ca1
AM		 6483 scale = input_line_pointer;
6484 input_line_pointer = save;
6485 return scale;
252b5132
RH		 6486}
6487
252b5132 6488static int
e3bb37b5 6489i386_displacement (char *disp_start, char *disp_end)
252b5132 6490{
29b0f896 6491 expressionS *exp;
252b5132
RH		 6492 segT exp_seg = 0;
6493 char *save_input_line_pointer;
f3c180ae 6494 char *gotfree_input_line;
40fb9820
L		 6495 int override;
6496 i386_operand_type bigdisp, types = anydisp;
3992d3b7 6497 int ret;
252b5132 6498
31b2323c
L		 6499 if (i.disp_operands == MAX_MEMORY_OPERANDS)
6500 {
6501 as_bad (_("at most %d displacement operands are allowed"),
6502 MAX_MEMORY_OPERANDS);
6503 return 0;
6504 }
6505
0dfbf9d7 6506 operand_type_set (&bigdisp, 0);
40fb9820
L		 6507 if ((i.types[this_operand].bitfield.jumpabsolute)
6508 || (!current_templates->start->opcode_modifier.jump
6509 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 6510 {
40fb9820 6511 bigdisp.bitfield.disp32 = 1;
e05278af 6512 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 6513 if (flag_code == CODE_64BIT)
6514 {
6515 if (!override)
6516 {
6517 bigdisp.bitfield.disp32s = 1;
6518 bigdisp.bitfield.disp64 = 1;
6519 }
6520 }
6521 else if ((flag_code == CODE_16BIT) ^ override)
6522 {
6523 bigdisp.bitfield.disp32 = 0;
6524 bigdisp.bitfield.disp16 = 1;
6525 }
e05278af
JB		 6526 }
6527 else
6528 {
6529 /* For PC-relative branches, the width of the displacement
6530 is dependent upon data size, not address size. */
e05278af 6531 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 6532 if (flag_code == CODE_64BIT)
6533 {
6534 if (override || i.suffix == WORD_MNEM_SUFFIX)
6535 bigdisp.bitfield.disp16 = 1;
6536 else
6537 {
6538 bigdisp.bitfield.disp32 = 1;
6539 bigdisp.bitfield.disp32s = 1;
6540 }
6541 }
6542 else
e05278af
JB		 6543 {
6544 if (!override)
6545 override = (i.suffix == (flag_code != CODE_16BIT
6546 ? WORD_MNEM_SUFFIX
6547 : LONG_MNEM_SUFFIX));
40fb9820
L		 6548 bigdisp.bitfield.disp32 = 1;
6549 if ((flag_code == CODE_16BIT) ^ override)
6550 {
6551 bigdisp.bitfield.disp32 = 0;
6552 bigdisp.bitfield.disp16 = 1;
6553 }
e05278af 6554 }
e05278af 6555 }
c6fb90c8
L		 6556 i.types[this_operand] = operand_type_or (i.types[this_operand],
6557 bigdisp);
252b5132
RH		 6558
6559 exp = &disp_expressions[i.disp_operands];
520dc8e8 6560 i.op[this_operand].disps = exp;
252b5132
RH		 6561 i.disp_operands++;
6562 save_input_line_pointer = input_line_pointer;
6563 input_line_pointer = disp_start;
6564 END_STRING_AND_SAVE (disp_end);
6565
6566#ifndef GCC_ASM_O_HACK
6567#define GCC_ASM_O_HACK 0
6568#endif
6569#if GCC_ASM_O_HACK
6570 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 6571 if (i.types[this_operand].bitfield.baseIndex
24eab124 6572 && displacement_string_end[-1] == '+')
252b5132
RH		 6573 {
6574 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 6575 constraint within gcc asm statements.
6576 For instance:
6577
6578 #define _set_tssldt_desc(n,addr,limit,type) \
6579 __asm__ __volatile__ ( \
6580 "movw %w2,%0\n\t" \
6581 "movw %w1,2+%0\n\t" \
6582 "rorl $16,%1\n\t" \
6583 "movb %b1,4+%0\n\t" \
6584 "movb %4,5+%0\n\t" \
6585 "movb $0,6+%0\n\t" \
6586 "movb %h1,7+%0\n\t" \
6587 "rorl $16,%1" \
6588 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6589
6590 This works great except that the output assembler ends
6591 up looking a bit weird if it turns out that there is
6592 no offset. You end up producing code that looks like:
6593
6594 #APP
6595 movw $235,(%eax)
6596 movw %dx,2+(%eax)
6597 rorl $16,%edx
6598 movb %dl,4+(%eax)
6599 movb $137,5+(%eax)
6600 movb $0,6+(%eax)
6601 movb %dh,7+(%eax)
6602 rorl $16,%edx
6603 #NO_APP
6604
47926f60 6605 So here we provide the missing zero. */
24eab124
AM		 6606
6607 *displacement_string_end = '0';
252b5132
RH		 6608 }
6609#endif
3956db08 6610 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6611 if (gotfree_input_line)
6612 input_line_pointer = gotfree_input_line;
252b5132 6613
24eab124 6614 exp_seg = expression (exp);
252b5132 6615
636c26b0
AM		 6616 SKIP_WHITESPACE ();
6617 if (*input_line_pointer)
6618 as_bad (_("junk `%s' after expression"), input_line_pointer);
6619#if GCC_ASM_O_HACK
6620 RESTORE_END_STRING (disp_end + 1);
6621#endif
636c26b0 6622 input_line_pointer = save_input_line_pointer;
636c26b0 6623 if (gotfree_input_line)
ee86248c
JB		 6624 {
6625 free (gotfree_input_line);
6626
6627 if (exp->X_op == O_constant || exp->X_op == O_register)
6628 exp->X_op = O_illegal;
6629 }
6630
6631 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
6632
6633 RESTORE_END_STRING (disp_end);
6634
6635 return ret;
6636}
6637
6638static int
6639i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6640 i386_operand_type types, const char *disp_start)
6641{
6642 i386_operand_type bigdisp;
6643 int ret = 1;
636c26b0 6644
24eab124
AM		 6645 /* We do this to make sure that the section symbol is in
6646 the symbol table. We will ultimately change the relocation
47926f60 6647 to be relative to the beginning of the section. */
1ae12ab7 6648 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 6649 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
6650 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 6651 {
636c26b0 6652 if (exp->X_op != O_symbol)
3992d3b7 6653 goto inv_disp;
636c26b0 6654
e5cb08ac 6655 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 6656 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
6657 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 6658 exp->X_op = O_subtract;
6659 exp->X_op_symbol = GOT_symbol;
1ae12ab7 6660 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 6661 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 6662 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6663 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 6664 else
29b0f896 6665 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 6666 }
252b5132 6667
3992d3b7
AM		 6668 else if (exp->X_op == O_absent
6669 || exp->X_op == O_illegal
ee86248c 6670 || exp->X_op == O_big)
2daf4fd8 6671 {
3992d3b7
AM		 6672 inv_disp:
6673 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 6674 disp_start);
3992d3b7 6675 ret = 0;
2daf4fd8
AM		 6676 }
6677
0e1147d9
L		 6678 else if (flag_code == CODE_64BIT
6679 && !i.prefix[ADDR_PREFIX]
6680 && exp->X_op == O_constant)
6681 {
6682 /* Since displacement is signed extended to 64bit, don't allow
6683 disp32 and turn off disp32s if they are out of range. */
6684 i.types[this_operand].bitfield.disp32 = 0;
6685 if (!fits_in_signed_long (exp->X_add_number))
6686 {
6687 i.types[this_operand].bitfield.disp32s = 0;
6688 if (i.types[this_operand].bitfield.baseindex)
6689 {
6690 as_bad (_("0x%lx out range of signed 32bit displacement"),
6691 (long) exp->X_add_number);
6692 ret = 0;
6693 }
6694 }
6695 }
6696
4c63da97 6697#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 6698 else if (exp->X_op != O_constant
6699 && OUTPUT_FLAVOR == bfd_target_aout_flavour
6700 && exp_seg != absolute_section
6701 && exp_seg != text_section
6702 && exp_seg != data_section
6703 && exp_seg != bss_section
6704 && exp_seg != undefined_section
6705 && !bfd_is_com_section (exp_seg))
24eab124 6706 {
d0b47220 6707 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 6708 ret = 0;
24eab124 6709 }
252b5132 6710#endif
3956db08 6711
40fb9820
L		 6712 /* Check if this is a displacement only operand. */
6713 bigdisp = i.types[this_operand];
6714 bigdisp.bitfield.disp8 = 0;
6715 bigdisp.bitfield.disp16 = 0;
6716 bigdisp.bitfield.disp32 = 0;
6717 bigdisp.bitfield.disp32s = 0;
6718 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 6719 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 6720 i.types[this_operand] = operand_type_and (i.types[this_operand],
6721 types);
3956db08 6722
3992d3b7 6723 return ret;
252b5132
RH		 6724}
6725
eecb386c 6726/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 6727 Return 1 on success, 0 on a failure. */
6728
252b5132 6729static int
e3bb37b5 6730i386_index_check (const char *operand_string)
252b5132 6731{
3e73aa7c 6732 int ok;
fc0763e6 6733 const char *kind = "base/index";
24eab124 6734#if INFER_ADDR_PREFIX
eecb386c
AM		 6735 int fudged = 0;
6736
24eab124
AM		 6737 tryprefix:
6738#endif
3e73aa7c 6739 ok = 1;
fc0763e6
JB		 6740 if (current_templates->start->opcode_modifier.isstring
6741 && !current_templates->start->opcode_modifier.immext
6742 && (current_templates->end[-1].opcode_modifier.isstring
6743 || i.mem_operands))
6744 {
6745 /* Memory operands of string insns are special in that they only allow
6746 a single register (rDI, rSI, or rBX) as their memory address. */
6747 unsigned int expected;
6748
6749 kind = "string address";
6750
6751 if (current_templates->start->opcode_modifier.w)
6752 {
6753 i386_operand_type type = current_templates->end[-1].operand_types[0];
6754
6755 if (!type.bitfield.baseindex
6756 || ((!i.mem_operands != !intel_syntax)
6757 && current_templates->end[-1].operand_types[1]
6758 .bitfield.baseindex))
6759 type = current_templates->end[-1].operand_types[1];
6760 expected = type.bitfield.esseg ? 7 /* rDI */ : 6 /* rSI */;
6761 }
6762 else
6763 expected = 3 /* rBX */;
6764
6765 if (!i.base_reg || i.index_reg
6766 || operand_type_check (i.types[this_operand], disp))
6767 ok = -1;
6768 else if (!(flag_code == CODE_64BIT
6769 ? i.prefix[ADDR_PREFIX]
6770 ? i.base_reg->reg_type.bitfield.reg32
6771 : i.base_reg->reg_type.bitfield.reg64
6772 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
6773 ? i.base_reg->reg_type.bitfield.reg32
6774 : i.base_reg->reg_type.bitfield.reg16))
6775 ok = 0;
6776 else if (i.base_reg->reg_num != expected)
6777 ok = -1;
6778
6779 if (ok < 0)
6780 {
6781 unsigned int j;
6782
6783 for (j = 0; j < i386_regtab_size; ++j)
6784 if ((flag_code == CODE_64BIT
6785 ? i.prefix[ADDR_PREFIX]
6786 ? i386_regtab[j].reg_type.bitfield.reg32
6787 : i386_regtab[j].reg_type.bitfield.reg64
6788 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
6789 ? i386_regtab[j].reg_type.bitfield.reg32
6790 : i386_regtab[j].reg_type.bitfield.reg16)
6791 && i386_regtab[j].reg_num == expected)
6792 break;
9c2799c2 6793 gas_assert (j < i386_regtab_size);
fc0763e6
JB		 6794 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
6795 operand_string,
6796 intel_syntax ? '[' : '(',
6797 register_prefix,
6798 i386_regtab[j].reg_name,
6799 intel_syntax ? ']' : ')');
6800 ok = 1;
6801 }
6802 }
6803 else if (flag_code == CODE_64BIT)
64e74474 6804 {
64e74474 6805 if ((i.base_reg
40fb9820
L		 6806 && ((i.prefix[ADDR_PREFIX] == 0
6807 && !i.base_reg->reg_type.bitfield.reg64)
6808 || (i.prefix[ADDR_PREFIX]
6809 && !i.base_reg->reg_type.bitfield.reg32))
6810 && (i.index_reg
9a04903e
JB		 6811 || i.base_reg->reg_num !=
6812 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
64e74474 6813 || (i.index_reg
40fb9820
L		 6814 && (!i.index_reg->reg_type.bitfield.baseindex
6815 || (i.prefix[ADDR_PREFIX] == 0
db51cc60
L		 6816 && i.index_reg->reg_num != RegRiz
6817 && !i.index_reg->reg_type.bitfield.reg64
6818 )
40fb9820 6819 || (i.prefix[ADDR_PREFIX]
db51cc60 6820 && i.index_reg->reg_num != RegEiz
40fb9820 6821 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 6822 ok = 0;
3e73aa7c
JH		 6823 }
6824 else
6825 {
6826 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
6827 {
6828 /* 16bit checks. */
6829 if ((i.base_reg
40fb9820
L		 6830 && (!i.base_reg->reg_type.bitfield.reg16
6831 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 6832 || (i.index_reg
40fb9820
L		 6833 && (!i.index_reg->reg_type.bitfield.reg16
6834 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 6835 || !(i.base_reg
6836 && i.base_reg->reg_num < 6
6837 && i.index_reg->reg_num >= 6
6838 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 6839 ok = 0;
6840 }
6841 else
e5cb08ac 6842 {
3e73aa7c
JH		 6843 /* 32bit checks. */
6844 if ((i.base_reg
40fb9820 6845 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 6846 || (i.index_reg
db51cc60
L		 6847 && ((!i.index_reg->reg_type.bitfield.reg32
6848 && i.index_reg->reg_num != RegEiz)
40fb9820 6849 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 6850 ok = 0;
3e73aa7c
JH		 6851 }
6852 }
6853 if (!ok)
24eab124
AM		 6854 {
6855#if INFER_ADDR_PREFIX
fc0763e6 6856 if (!i.mem_operands && !i.prefix[ADDR_PREFIX])
24eab124
AM		 6857 {
6858 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
6859 i.prefixes += 1;
b23bac36
AM		 6860 /* Change the size of any displacement too. At most one of
6861 Disp16 or Disp32 is set.
6862 FIXME. There doesn't seem to be any real need for separate
6863 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 6864 Removing them would probably clean up the code quite a lot. */
4eed87de 6865 if (flag_code != CODE_64BIT
40fb9820
L		 6866 && (i.types[this_operand].bitfield.disp16
6867 || i.types[this_operand].bitfield.disp32))
6868 i.types[this_operand]
c6fb90c8 6869 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 6870 fudged = 1;
24eab124
AM		 6871 goto tryprefix;
6872 }
eecb386c 6873 if (fudged)
fc0763e6
JB		 6874 as_bad (_("`%s' is not a valid %s expression"),
6875 operand_string,
6876 kind);
eecb386c 6877 else
c388dee8 6878#endif
fc0763e6 6879 as_bad (_("`%s' is not a valid %s-bit %s expression"),
eecb386c 6880 operand_string,
fc0763e6
JB		 6881 flag_code_names[i.prefix[ADDR_PREFIX]
6882 ? flag_code == CODE_32BIT
6883 ? CODE_16BIT
6884 : CODE_32BIT
6885 : flag_code],
6886 kind);
24eab124 6887 }
20f0a1fc 6888 return ok;
24eab124 6889}
252b5132 6890
fc0763e6 6891/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 6892 on error. */
252b5132 6893
252b5132 6894static int
a7619375 6895i386_att_operand (char *operand_string)
252b5132 6896{
af6bdddf
AM		 6897 const reg_entry *r;
6898 char *end_op;
24eab124 6899 char *op_string = operand_string;
252b5132 6900
24eab124 6901 if (is_space_char (*op_string))
252b5132
RH		 6902 ++op_string;
6903
24eab124 6904 /* We check for an absolute prefix (differentiating,
47926f60 6905 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 6906 if (*op_string == ABSOLUTE_PREFIX)
6907 {
6908 ++op_string;
6909 if (is_space_char (*op_string))
6910 ++op_string;
40fb9820 6911 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 6912 }
252b5132 6913
47926f60 6914 /* Check if operand is a register. */
4d1bb795 6915 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 6916 {
40fb9820
L		 6917 i386_operand_type temp;
6918
24eab124
AM		 6919 /* Check for a segment override by searching for ':' after a
6920 segment register. */
6921 op_string = end_op;
6922 if (is_space_char (*op_string))
6923 ++op_string;
40fb9820
L		 6924 if (*op_string == ':'
6925 && (r->reg_type.bitfield.sreg2
6926 || r->reg_type.bitfield.sreg3))
24eab124
AM		 6927 {
6928 switch (r->reg_num)
6929 {
6930 case 0:
6931 i.seg[i.mem_operands] = &es;
6932 break;
6933 case 1:
6934 i.seg[i.mem_operands] = &cs;
6935 break;
6936 case 2:
6937 i.seg[i.mem_operands] = &ss;
6938 break;
6939 case 3:
6940 i.seg[i.mem_operands] = &ds;
6941 break;
6942 case 4:
6943 i.seg[i.mem_operands] = &fs;
6944 break;
6945 case 5:
6946 i.seg[i.mem_operands] = &gs;
6947 break;
6948 }
252b5132 6949
24eab124 6950 /* Skip the ':' and whitespace. */
252b5132
RH		 6951 ++op_string;
6952 if (is_space_char (*op_string))
24eab124 6953 ++op_string;
252b5132 6954
24eab124
AM		 6955 if (!is_digit_char (*op_string)
6956 && !is_identifier_char (*op_string)
6957 && *op_string != '('
6958 && *op_string != ABSOLUTE_PREFIX)
6959 {
6960 as_bad (_("bad memory operand `%s'"), op_string);
6961 return 0;
6962 }
47926f60 6963 /* Handle case of %es:*foo. */
24eab124
AM		 6964 if (*op_string == ABSOLUTE_PREFIX)
6965 {
6966 ++op_string;
6967 if (is_space_char (*op_string))
6968 ++op_string;
40fb9820 6969 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 6970 }
6971 goto do_memory_reference;
6972 }
6973 if (*op_string)
6974 {
d0b47220 6975 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 6976 return 0;
6977 }
40fb9820
L		 6978 temp = r->reg_type;
6979 temp.bitfield.baseindex = 0;
c6fb90c8
L		 6980 i.types[this_operand] = operand_type_or (i.types[this_operand],
6981 temp);
7d5e4556 6982 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 6983 i.op[this_operand].regs = r;
24eab124
AM		 6984 i.reg_operands++;
6985 }
af6bdddf
AM		 6986 else if (*op_string == REGISTER_PREFIX)
6987 {
6988 as_bad (_("bad register name `%s'"), op_string);
6989 return 0;
6990 }
24eab124 6991 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 6992 {
24eab124 6993 ++op_string;
40fb9820 6994 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 6995 {
d0b47220 6996 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 6997 return 0;
6998 }
6999 if (!i386_immediate (op_string))
7000 return 0;
7001 }
7002 else if (is_digit_char (*op_string)
7003 || is_identifier_char (*op_string)
e5cb08ac 7004 || *op_string == '(')
24eab124 7005 {
47926f60 7006 /* This is a memory reference of some sort. */
af6bdddf 7007 char *base_string;
252b5132 7008
47926f60 7009 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 7010 char *displacement_string_start;
7011 char *displacement_string_end;
252b5132 7012
24eab124 7013 do_memory_reference:
24eab124 7014 if ((i.mem_operands == 1
40fb9820 7015 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 7016 || i.mem_operands == 2)
7017 {
7018 as_bad (_("too many memory references for `%s'"),
7019 current_templates->start->name);
7020 return 0;
7021 }
252b5132 7022
24eab124
AM		 7023 /* Check for base index form. We detect the base index form by
7024 looking for an ')' at the end of the operand, searching
7025 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7026 after the '('. */
af6bdddf 7027 base_string = op_string + strlen (op_string);
c3332e24 7028
af6bdddf
AM		 7029 --base_string;
7030 if (is_space_char (*base_string))
7031 --base_string;
252b5132 7032
47926f60 7033 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 7034 displacement_string_start = op_string;
7035 displacement_string_end = base_string + 1;
252b5132 7036
24eab124
AM		 7037 if (*base_string == ')')
7038 {
af6bdddf 7039 char *temp_string;
24eab124
AM		 7040 unsigned int parens_balanced = 1;
7041 /* We've already checked that the number of left & right ()'s are
47926f60 7042 equal, so this loop will not be infinite. */
24eab124
AM		 7043 do
7044 {
7045 base_string--;
7046 if (*base_string == ')')
7047 parens_balanced++;
7048 if (*base_string == '(')
7049 parens_balanced--;
7050 }
7051 while (parens_balanced);
c3332e24 7052
af6bdddf 7053 temp_string = base_string;
c3332e24 7054
24eab124 7055 /* Skip past '(' and whitespace. */
252b5132
RH		 7056 ++base_string;
7057 if (is_space_char (*base_string))
24eab124 7058 ++base_string;
252b5132 7059
af6bdddf 7060 if (*base_string == ','
4eed87de
AM		 7061 || ((i.base_reg = parse_register (base_string, &end_op))
7062 != NULL))
252b5132 7063 {
af6bdddf 7064 displacement_string_end = temp_string;
252b5132 7065
40fb9820 7066 i.types[this_operand].bitfield.baseindex = 1;
252b5132 7067
af6bdddf 7068 if (i.base_reg)
24eab124 7069 {
24eab124
AM		 7070 base_string = end_op;
7071 if (is_space_char (*base_string))
7072 ++base_string;
af6bdddf
AM		 7073 }
7074
7075 /* There may be an index reg or scale factor here. */
7076 if (*base_string == ',')
7077 {
7078 ++base_string;
7079 if (is_space_char (*base_string))
7080 ++base_string;
7081
4eed87de
AM		 7082 if ((i.index_reg = parse_register (base_string, &end_op))
7083 != NULL)
24eab124 7084 {
af6bdddf 7085 base_string = end_op;
24eab124
AM		 7086 if (is_space_char (*base_string))
7087 ++base_string;
af6bdddf
AM		 7088 if (*base_string == ',')
7089 {
7090 ++base_string;
7091 if (is_space_char (*base_string))
7092 ++base_string;
7093 }
e5cb08ac 7094 else if (*base_string != ')')
af6bdddf 7095 {
4eed87de
AM		 7096 as_bad (_("expecting `,' or `)' "
7097 "after index register in `%s'"),
af6bdddf
AM		 7098 operand_string);
7099 return 0;
7100 }
24eab124 7101 }
af6bdddf 7102 else if (*base_string == REGISTER_PREFIX)
24eab124 7103 {
af6bdddf 7104 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 7105 return 0;
7106 }
252b5132 7107
47926f60 7108 /* Check for scale factor. */
551c1ca1 7109 if (*base_string != ')')
af6bdddf 7110 {
551c1ca1
AM		 7111 char *end_scale = i386_scale (base_string);
7112
7113 if (!end_scale)
af6bdddf 7114 return 0;
24eab124 7115
551c1ca1 7116 base_string = end_scale;
af6bdddf
AM		 7117 if (is_space_char (*base_string))
7118 ++base_string;
7119 if (*base_string != ')')
7120 {
4eed87de
AM		 7121 as_bad (_("expecting `)' "
7122 "after scale factor in `%s'"),
af6bdddf
AM		 7123 operand_string);
7124 return 0;
7125 }
7126 }
7127 else if (!i.index_reg)
24eab124 7128 {
4eed87de
AM		 7129 as_bad (_("expecting index register or scale factor "
7130 "after `,'; got '%c'"),
af6bdddf 7131 *base_string);
24eab124
AM		 7132 return 0;
7133 }
7134 }
af6bdddf 7135 else if (*base_string != ')')
24eab124 7136 {
4eed87de
AM		 7137 as_bad (_("expecting `,' or `)' "
7138 "after base register in `%s'"),
af6bdddf 7139 operand_string);
24eab124
AM		 7140 return 0;
7141 }
c3332e24 7142 }
af6bdddf 7143 else if (*base_string == REGISTER_PREFIX)
c3332e24 7144 {
af6bdddf 7145 as_bad (_("bad register name `%s'"), base_string);
24eab124 7146 return 0;
c3332e24 7147 }
24eab124
AM		 7148 }
7149
7150 /* If there's an expression beginning the operand, parse it,
7151 assuming displacement_string_start and
7152 displacement_string_end are meaningful. */
7153 if (displacement_string_start != displacement_string_end)
7154 {
7155 if (!i386_displacement (displacement_string_start,
7156 displacement_string_end))
7157 return 0;
7158 }
7159
7160 /* Special case for (%dx) while doing input/output op. */
7161 if (i.base_reg
0dfbf9d7
L		 7162 && operand_type_equal (&i.base_reg->reg_type,
7163 &reg16_inoutportreg)
24eab124
AM		 7164 && i.index_reg == 0
7165 && i.log2_scale_factor == 0
7166 && i.seg[i.mem_operands] == 0
40fb9820 7167 && !operand_type_check (i.types[this_operand], disp))
24eab124 7168 {
65da13b5 7169 i.types[this_operand] = inoutportreg;
24eab124
AM		 7170 return 1;
7171 }
7172
eecb386c
AM		 7173 if (i386_index_check (operand_string) == 0)
7174 return 0;
5c07affc 7175 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 7176 i.mem_operands++;
7177 }
7178 else
ce8a8b2f
AM		 7179 {
7180 /* It's not a memory operand; argh! */
24eab124
AM		 7181 as_bad (_("invalid char %s beginning operand %d `%s'"),
7182 output_invalid (*op_string),
7183 this_operand + 1,
7184 op_string);
7185 return 0;
7186 }
47926f60 7187 return 1; /* Normal return. */
252b5132
RH		 7188}
7189\f
ee7fcc42
AM		 7190/* md_estimate_size_before_relax()
7191
7192 Called just before relax() for rs_machine_dependent frags. The x86
7193 assembler uses these frags to handle variable size jump
7194 instructions.
7195
7196 Any symbol that is now undefined will not become defined.
7197 Return the correct fr_subtype in the frag.
7198 Return the initial "guess for variable size of frag" to caller.
7199 The guess is actually the growth beyond the fixed part. Whatever
7200 we do to grow the fixed or variable part contributes to our
7201 returned value. */
7202
252b5132
RH		 7203int
7204md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 7205 fragS *fragP;
7206 segT segment;
252b5132 7207{
252b5132 7208 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 7209 check for un-relaxable symbols. On an ELF system, we can't relax
7210 an externally visible symbol, because it may be overridden by a
7211 shared library. */
7212 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 7213#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7214 || (IS_ELF
31312f95 7215 && (S_IS_EXTERNAL (fragP->fr_symbol)
915bcca5
L		 7216 || S_IS_WEAK (fragP->fr_symbol)
7217 || ((symbol_get_bfdsym (fragP->fr_symbol)->flags
7218 & BSF_GNU_INDIRECT_FUNCTION))))
fbeb56a4
DK		 7219#endif
7220#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 7221 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 7222 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 7223#endif
7224 )
252b5132 7225 {
b98ef147
AM		 7226 /* Symbol is undefined in this segment, or we need to keep a
7227 reloc so that weak symbols can be overridden. */
7228 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 7229 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 7230 unsigned char *opcode;
7231 int old_fr_fix;
f6af82bd 7232
ee7fcc42 7233 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 7234 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 7235 else if (size == 2)
f6af82bd
AM		 7236 reloc_type = BFD_RELOC_16_PCREL;
7237 else
7238 reloc_type = BFD_RELOC_32_PCREL;
252b5132 7239
ee7fcc42
AM		 7240 old_fr_fix = fragP->fr_fix;
7241 opcode = (unsigned char *) fragP->fr_opcode;
7242
fddf5b5b 7243 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 7244 {
fddf5b5b
AM		 7245 case UNCOND_JUMP:
7246 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 7247 opcode[0] = 0xe9;
252b5132 7248 fragP->fr_fix += size;
062cd5e7
AS		 7249 fix_new (fragP, old_fr_fix, size,
7250 fragP->fr_symbol,
7251 fragP->fr_offset, 1,
7252 reloc_type);
252b5132
RH		 7253 break;
7254
fddf5b5b 7255 case COND_JUMP86:
412167cb
AM		 7256 if (size == 2
7257 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 7258 {
7259 /* Negate the condition, and branch past an
7260 unconditional jump. */
7261 opcode[0] ^= 1;
7262 opcode[1] = 3;
7263 /* Insert an unconditional jump. */
7264 opcode[2] = 0xe9;
7265 /* We added two extra opcode bytes, and have a two byte
7266 offset. */
7267 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 7268 fix_new (fragP, old_fr_fix + 2, 2,
7269 fragP->fr_symbol,
7270 fragP->fr_offset, 1,
7271 reloc_type);
fddf5b5b
AM		 7272 break;
7273 }
7274 /* Fall through. */
7275
7276 case COND_JUMP:
412167cb
AM		 7277 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
7278 {
3e02c1cc
AM		 7279 fixS *fixP;
7280
412167cb 7281 fragP->fr_fix += 1;
3e02c1cc
AM		 7282 fixP = fix_new (fragP, old_fr_fix, 1,
7283 fragP->fr_symbol,
7284 fragP->fr_offset, 1,
7285 BFD_RELOC_8_PCREL);
7286 fixP->fx_signed = 1;
412167cb
AM		 7287 break;
7288 }
93c2a809 7289
24eab124 7290 /* This changes the byte-displacement jump 0x7N
fddf5b5b 7291 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 7292 opcode[1] = opcode[0] + 0x10;
f6af82bd 7293 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 7294 /* We've added an opcode byte. */
7295 fragP->fr_fix += 1 + size;
062cd5e7
AS		 7296 fix_new (fragP, old_fr_fix + 1, size,
7297 fragP->fr_symbol,
7298 fragP->fr_offset, 1,
7299 reloc_type);
252b5132 7300 break;
fddf5b5b
AM		 7301
7302 default:
7303 BAD_CASE (fragP->fr_subtype);
7304 break;
252b5132
RH		 7305 }
7306 frag_wane (fragP);
ee7fcc42 7307 return fragP->fr_fix - old_fr_fix;
252b5132 7308 }
93c2a809 7309
93c2a809
AM		 7310 /* Guess size depending on current relax state. Initially the relax
7311 state will correspond to a short jump and we return 1, because
7312 the variable part of the frag (the branch offset) is one byte
7313 long. However, we can relax a section more than once and in that
7314 case we must either set fr_subtype back to the unrelaxed state,
7315 or return the value for the appropriate branch. */
7316 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 7317}
7318
47926f60
KH		 7319/* Called after relax() is finished.
7320
7321 In: Address of frag.
7322 fr_type == rs_machine_dependent.
7323 fr_subtype is what the address relaxed to.
7324
7325 Out: Any fixSs and constants are set up.
7326 Caller will turn frag into a ".space 0". */
7327
252b5132
RH		 7328void
7329md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 7330 bfd *abfd ATTRIBUTE_UNUSED;
7331 segT sec ATTRIBUTE_UNUSED;
29b0f896 7332 fragS *fragP;
252b5132 7333{
29b0f896 7334 unsigned char *opcode;
252b5132 7335 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 7336 offsetT target_address;
7337 offsetT opcode_address;
252b5132 7338 unsigned int extension = 0;
847f7ad4 7339 offsetT displacement_from_opcode_start;
252b5132
RH		 7340
7341 opcode = (unsigned char *) fragP->fr_opcode;
7342
47926f60 7343 /* Address we want to reach in file space. */
252b5132 7344 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 7345
47926f60 7346 /* Address opcode resides at in file space. */
252b5132
RH		 7347 opcode_address = fragP->fr_address + fragP->fr_fix;
7348
47926f60 7349 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 7350 displacement_from_opcode_start = target_address - opcode_address;
7351
fddf5b5b 7352 if ((fragP->fr_subtype & BIG) == 0)
252b5132 7353 {
47926f60
KH		 7354 /* Don't have to change opcode. */
7355 extension = 1; /* 1 opcode + 1 displacement */
252b5132 7356 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 7357 }
7358 else
7359 {
7360 if (no_cond_jump_promotion
7361 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 7362 as_warn_where (fragP->fr_file, fragP->fr_line,
7363 _("long jump required"));
252b5132 7364
fddf5b5b
AM		 7365 switch (fragP->fr_subtype)
7366 {
7367 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
7368 extension = 4; /* 1 opcode + 4 displacement */
7369 opcode[0] = 0xe9;
7370 where_to_put_displacement = &opcode[1];
7371 break;
252b5132 7372
fddf5b5b
AM		 7373 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
7374 extension = 2; /* 1 opcode + 2 displacement */
7375 opcode[0] = 0xe9;
7376 where_to_put_displacement = &opcode[1];
7377 break;
252b5132 7378
fddf5b5b
AM		 7379 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
7380 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
7381 extension = 5; /* 2 opcode + 4 displacement */
7382 opcode[1] = opcode[0] + 0x10;
7383 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7384 where_to_put_displacement = &opcode[2];
7385 break;
252b5132 7386
fddf5b5b
AM		 7387 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
7388 extension = 3; /* 2 opcode + 2 displacement */
7389 opcode[1] = opcode[0] + 0x10;
7390 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7391 where_to_put_displacement = &opcode[2];
7392 break;
252b5132 7393
fddf5b5b
AM		 7394 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
7395 extension = 4;
7396 opcode[0] ^= 1;
7397 opcode[1] = 3;
7398 opcode[2] = 0xe9;
7399 where_to_put_displacement = &opcode[3];
7400 break;
7401
7402 default:
7403 BAD_CASE (fragP->fr_subtype);
7404 break;
7405 }
252b5132 7406 }
fddf5b5b 7407
7b81dfbb
AJ		 7408 /* If size if less then four we are sure that the operand fits,
7409 but if it's 4, then it could be that the displacement is larger
7410 then -/+ 2GB. */
7411 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
7412 && object_64bit
7413 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 7414 + ((addressT) 1 << 31))
7415 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 7416 {
7417 as_bad_where (fragP->fr_file, fragP->fr_line,
7418 _("jump target out of range"));
7419 /* Make us emit 0. */
7420 displacement_from_opcode_start = extension;
7421 }
47926f60 7422 /* Now put displacement after opcode. */
252b5132
RH		 7423 md_number_to_chars ((char *) where_to_put_displacement,
7424 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 7425 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 7426 fragP->fr_fix += extension;
7427}
7428\f
252b5132
RH		 7429/* Apply a fixup (fixS) to segment data, once it has been determined
7430 by our caller that we have all the info we need to fix it up.
7431
7432 On the 386, immediates, displacements, and data pointers are all in
7433 the same (little-endian) format, so we don't need to care about which
7434 we are handling. */
7435
94f592af 7436void
55cf6793 7437md_apply_fix (fixP, valP, seg)
47926f60
KH		 7438 /* The fix we're to put in. */
7439 fixS *fixP;
47926f60 7440 /* Pointer to the value of the bits. */
c6682705 7441 valueT *valP;
47926f60
KH		 7442 /* Segment fix is from. */
7443 segT seg ATTRIBUTE_UNUSED;
252b5132 7444{
94f592af 7445 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 7446 valueT value = *valP;
252b5132 7447
f86103b7 7448#if !defined (TE_Mach)
93382f6d
AM		 7449 if (fixP->fx_pcrel)
7450 {
7451 switch (fixP->fx_r_type)
7452 {
5865bb77
ILT		 7453 default:
7454 break;
7455
d6ab8113
JB		 7456 case BFD_RELOC_64:
7457 fixP->fx_r_type = BFD_RELOC_64_PCREL;
7458 break;
93382f6d 7459 case BFD_RELOC_32:
ae8887b5 7460 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 7461 fixP->fx_r_type = BFD_RELOC_32_PCREL;
7462 break;
7463 case BFD_RELOC_16:
7464 fixP->fx_r_type = BFD_RELOC_16_PCREL;
7465 break;
7466 case BFD_RELOC_8:
7467 fixP->fx_r_type = BFD_RELOC_8_PCREL;
7468 break;
7469 }
7470 }
252b5132 7471
a161fe53 7472 if (fixP->fx_addsy != NULL
31312f95 7473 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 7474 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 7475 || fixP->fx_r_type == BFD_RELOC_16_PCREL
7476 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
7477 && !use_rela_relocations)
252b5132 7478 {
31312f95
AM		 7479 /* This is a hack. There should be a better way to handle this.
7480 This covers for the fact that bfd_install_relocation will
7481 subtract the current location (for partial_inplace, PC relative
7482 relocations); see more below. */
252b5132 7483#ifndef OBJ_AOUT
718ddfc0 7484 if (IS_ELF
252b5132
RH		 7485#ifdef TE_PE
7486 || OUTPUT_FLAVOR == bfd_target_coff_flavour
7487#endif
7488 )
7489 value += fixP->fx_where + fixP->fx_frag->fr_address;
7490#endif
7491#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7492 if (IS_ELF)
252b5132 7493 {
6539b54b 7494 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 7495
6539b54b 7496 if ((sym_seg == seg
2f66722d 7497 || (symbol_section_p (fixP->fx_addsy)
6539b54b 7498 && sym_seg != absolute_section))
af65af87 7499 && !generic_force_reloc (fixP))
2f66722d
AM		 7500 {
7501 /* Yes, we add the values in twice. This is because
6539b54b
AM		 7502 bfd_install_relocation subtracts them out again. I think
7503 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 7504 it. FIXME. */
7505 value += fixP->fx_where + fixP->fx_frag->fr_address;
7506 }
252b5132
RH		 7507 }
7508#endif
7509#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 7510 /* For some reason, the PE format does not store a
7511 section address offset for a PC relative symbol. */
7512 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 7513 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 7514 value += md_pcrel_from (fixP);
7515#endif
7516 }
fbeb56a4
DK		 7517#if defined (OBJ_COFF) && defined (TE_PE)
7518 if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
7519 {
7520 value -= S_GET_VALUE (fixP->fx_addsy);
7521 }
7522#endif
252b5132
RH		 7523
7524 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 7525 and we must not disappoint it. */
252b5132 7526#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7527 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 7528 switch (fixP->fx_r_type)
7529 {
7530 case BFD_RELOC_386_PLT32:
3e73aa7c 7531 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 7532 /* Make the jump instruction point to the address of the operand. At
7533 runtime we merely add the offset to the actual PLT entry. */
7534 value = -4;
7535 break;
31312f95 7536
13ae64f3
JJ		 7537 case BFD_RELOC_386_TLS_GD:
7538 case BFD_RELOC_386_TLS_LDM:
13ae64f3 7539 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 7540 case BFD_RELOC_386_TLS_IE:
7541 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 7542 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 7543 case BFD_RELOC_X86_64_TLSGD:
7544 case BFD_RELOC_X86_64_TLSLD:
7545 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 7546 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 7547 value = 0; /* Fully resolved at runtime. No addend. */
7548 /* Fallthrough */
7549 case BFD_RELOC_386_TLS_LE:
7550 case BFD_RELOC_386_TLS_LDO_32:
7551 case BFD_RELOC_386_TLS_LE_32:
7552 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 7553 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 7554 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 7555 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 7556 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7557 break;
7558
67a4f2b7
AO		 7559 case BFD_RELOC_386_TLS_DESC_CALL:
7560 case BFD_RELOC_X86_64_TLSDESC_CALL:
7561 value = 0; /* Fully resolved at runtime. No addend. */
7562 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7563 fixP->fx_done = 0;
7564 return;
7565
00f7efb6
JJ		 7566 case BFD_RELOC_386_GOT32:
7567 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 7568 value = 0; /* Fully resolved at runtime. No addend. */
7569 break;
47926f60
KH		 7570
7571 case BFD_RELOC_VTABLE_INHERIT:
7572 case BFD_RELOC_VTABLE_ENTRY:
7573 fixP->fx_done = 0;
94f592af 7574 return;
47926f60
KH		 7575
7576 default:
7577 break;
7578 }
7579#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 7580 *valP = value;
f86103b7 7581#endif /* !defined (TE_Mach) */
3e73aa7c 7582
3e73aa7c 7583 /* Are we finished with this relocation now? */
c6682705 7584 if (fixP->fx_addsy == NULL)
3e73aa7c 7585 fixP->fx_done = 1;
fbeb56a4
DK		 7586#if defined (OBJ_COFF) && defined (TE_PE)
7587 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
7588 {
7589 fixP->fx_done = 0;
7590 /* Remember value for tc_gen_reloc. */
7591 fixP->fx_addnumber = value;
7592 /* Clear out the frag for now. */
7593 value = 0;
7594 }
7595#endif
3e73aa7c
JH		 7596 else if (use_rela_relocations)
7597 {
7598 fixP->fx_no_overflow = 1;
062cd5e7
AS		 7599 /* Remember value for tc_gen_reloc. */
7600 fixP->fx_addnumber = value;
3e73aa7c
JH		 7601 value = 0;
7602 }
f86103b7 7603
94f592af 7604 md_number_to_chars (p, value, fixP->fx_size);
252b5132 7605}
252b5132 7606\f
252b5132 7607char *
499ac353 7608md_atof (int type, char *litP, int *sizeP)
252b5132 7609{
499ac353
NC		 7610 /* This outputs the LITTLENUMs in REVERSE order;
7611 in accord with the bigendian 386. */
7612 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 7613}
7614\f
2d545b82 7615static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 7616
252b5132 7617static char *
e3bb37b5 7618output_invalid (int c)
252b5132 7619{
3882b010 7620 if (ISPRINT (c))
f9f21a03
L		 7621 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
7622 "'%c'", c);
252b5132 7623 else
f9f21a03 7624 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 7625 "(0x%x)", (unsigned char) c);
252b5132
RH		 7626 return output_invalid_buf;
7627}
7628
af6bdddf 7629/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 7630
7631static const reg_entry *
4d1bb795 7632parse_real_register (char *reg_string, char **end_op)
252b5132 7633{
af6bdddf
AM		 7634 char *s = reg_string;
7635 char *p;
252b5132
RH		 7636 char reg_name_given[MAX_REG_NAME_SIZE + 1];
7637 const reg_entry *r;
7638
7639 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7640 if (*s == REGISTER_PREFIX)
7641 ++s;
7642
7643 if (is_space_char (*s))
7644 ++s;
7645
7646 p = reg_name_given;
af6bdddf 7647 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 7648 {
7649 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 7650 return (const reg_entry *) NULL;
7651 s++;
252b5132
RH		 7652 }
7653
6588847e
DN		 7654 /* For naked regs, make sure that we are not dealing with an identifier.
7655 This prevents confusing an identifier like `eax_var' with register
7656 `eax'. */
7657 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
7658 return (const reg_entry *) NULL;
7659
af6bdddf 7660 *end_op = s;
252b5132
RH		 7661
7662 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
7663
5f47d35b 7664 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 7665 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 7666 {
5f47d35b
AM		 7667 if (is_space_char (*s))
7668 ++s;
7669 if (*s == '(')
7670 {
af6bdddf 7671 ++s;
5f47d35b
AM		 7672 if (is_space_char (*s))
7673 ++s;
7674 if (*s >= '0' && *s <= '7')
7675 {
db557034 7676 int fpr = *s - '0';
af6bdddf 7677 ++s;
5f47d35b
AM		 7678 if (is_space_char (*s))
7679 ++s;
7680 if (*s == ')')
7681 {
7682 *end_op = s + 1;
1e9cc1c2 7683 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 7684 know (r);
7685 return r + fpr;
5f47d35b 7686 }
5f47d35b 7687 }
47926f60 7688 /* We have "%st(" then garbage. */
5f47d35b
AM		 7689 return (const reg_entry *) NULL;
7690 }
7691 }
7692
a60de03c
JB		 7693 if (r == NULL || allow_pseudo_reg)
7694 return r;
7695
0dfbf9d7 7696 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 7697 return (const reg_entry *) NULL;
7698
192dc9c6
JB		 7699 if ((r->reg_type.bitfield.reg32
7700 || r->reg_type.bitfield.sreg3
7701 || r->reg_type.bitfield.control
7702 || r->reg_type.bitfield.debug
7703 || r->reg_type.bitfield.test)
7704 && !cpu_arch_flags.bitfield.cpui386)
7705 return (const reg_entry *) NULL;
7706
309d3373
JB		 7707 if (r->reg_type.bitfield.floatreg
7708 && !cpu_arch_flags.bitfield.cpu8087
7709 && !cpu_arch_flags.bitfield.cpu287
7710 && !cpu_arch_flags.bitfield.cpu387)
7711 return (const reg_entry *) NULL;
7712
192dc9c6
JB		 7713 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
7714 return (const reg_entry *) NULL;
7715
7716 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
7717 return (const reg_entry *) NULL;
7718
40f12533
L		 7719 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
7720 return (const reg_entry *) NULL;
7721
db51cc60 7722 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 7723 if (!allow_index_reg
db51cc60
L		 7724 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
7725 return (const reg_entry *) NULL;
7726
a60de03c
JB		 7727 if (((r->reg_flags & (RegRex64 | RegRex))
7728 || r->reg_type.bitfield.reg64)
40fb9820 7729 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 7730 || !operand_type_equal (&r->reg_type, &control))
1ae00879 7731 && flag_code != CODE_64BIT)
20f0a1fc 7732 return (const reg_entry *) NULL;
1ae00879 7733
b7240065
JB		 7734 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
7735 return (const reg_entry *) NULL;
7736
252b5132
RH		 7737 return r;
7738}
4d1bb795
JB		 7739
7740/* REG_STRING starts *before* REGISTER_PREFIX. */
7741
7742static const reg_entry *
7743parse_register (char *reg_string, char **end_op)
7744{
7745 const reg_entry *r;
7746
7747 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
7748 r = parse_real_register (reg_string, end_op);
7749 else
7750 r = NULL;
7751 if (!r)
7752 {
7753 char *save = input_line_pointer;
7754 char c;
7755 symbolS *symbolP;
7756
7757 input_line_pointer = reg_string;
7758 c = get_symbol_end ();
7759 symbolP = symbol_find (reg_string);
7760 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
7761 {
7762 const expressionS *e = symbol_get_value_expression (symbolP);
7763
7764 know (e->X_op == O_register);
4eed87de 7765 know (e->X_add_number >= 0
c3fe08fa 7766 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 7767 r = i386_regtab + e->X_add_number;
7768 *end_op = input_line_pointer;
7769 }
7770 *input_line_pointer = c;
7771 input_line_pointer = save;
7772 }
7773 return r;
7774}
7775
7776int
7777i386_parse_name (char *name, expressionS *e, char *nextcharP)
7778{
7779 const reg_entry *r;
7780 char *end = input_line_pointer;
7781
7782 *end = *nextcharP;
7783 r = parse_register (name, &input_line_pointer);
7784 if (r && end <= input_line_pointer)
7785 {
7786 *nextcharP = *input_line_pointer;
7787 *input_line_pointer = 0;
7788 e->X_op = O_register;
7789 e->X_add_number = r - i386_regtab;
7790 return 1;
7791 }
7792 input_line_pointer = end;
7793 *end = 0;
ee86248c 7794 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 7795}
7796
7797void
7798md_operand (expressionS *e)
7799{
ee86248c
JB		 7800 char *end;
7801 const reg_entry *r;
4d1bb795 7802
ee86248c
JB		 7803 switch (*input_line_pointer)
7804 {
7805 case REGISTER_PREFIX:
7806 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 7807 if (r)
7808 {
7809 e->X_op = O_register;
7810 e->X_add_number = r - i386_regtab;
7811 input_line_pointer = end;
7812 }
ee86248c
JB		 7813 break;
7814
7815 case '[':
9c2799c2 7816 gas_assert (intel_syntax);
ee86248c
JB		 7817 end = input_line_pointer++;
7818 expression (e);
7819 if (*input_line_pointer == ']')
7820 {
7821 ++input_line_pointer;
7822 e->X_op_symbol = make_expr_symbol (e);
7823 e->X_add_symbol = NULL;
7824 e->X_add_number = 0;
7825 e->X_op = O_index;
7826 }
7827 else
7828 {
7829 e->X_op = O_absent;
7830 input_line_pointer = end;
7831 }
7832 break;
4d1bb795
JB		 7833 }
7834}
7835
252b5132 7836\f
4cc782b5 7837#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 7838const char *md_shortopts = "kVQ:sqn";
252b5132 7839#else
12b55ccc 7840const char *md_shortopts = "qn";
252b5132 7841#endif
6e0b89ee 7842
3e73aa7c 7843#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 7844#define OPTION_64 (OPTION_MD_BASE + 1)
7845#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 7846#define OPTION_MARCH (OPTION_MD_BASE + 3)
7847#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 7848#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7849#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7850#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7851#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7852#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 7853#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 7854#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
b3b91714 7855
99ad8390
NC		 7856struct option md_longopts[] =
7857{
3e73aa7c 7858 {"32", no_argument, NULL, OPTION_32},
321098a5
L		 7859#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7860 || defined (TE_PE) || defined (TE_PEP))
3e73aa7c 7861 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 7862#endif
b3b91714 7863 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 7864 {"march", required_argument, NULL, OPTION_MARCH},
7865 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 7866 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
7867 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
7868 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
7869 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
7870 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 7871 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 7872 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
252b5132
RH		 7873 {NULL, no_argument, NULL, 0}
7874};
7875size_t md_longopts_size = sizeof (md_longopts);
7876
7877int
9103f4f4 7878md_parse_option (int c, char *arg)
252b5132 7879{
9103f4f4 7880 unsigned int i;
6305a203 7881 char *arch, *next;
9103f4f4 7882
252b5132
RH		 7883 switch (c)
7884 {
12b55ccc
L		 7885 case 'n':
7886 optimize_align_code = 0;
7887 break;
7888
a38cf1db
AM		 7889 case 'q':
7890 quiet_warnings = 1;
252b5132
RH		 7891 break;
7892
7893#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 7894 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7895 should be emitted or not. FIXME: Not implemented. */
7896 case 'Q':
252b5132
RH		 7897 break;
7898
7899 /* -V: SVR4 argument to print version ID. */
7900 case 'V':
7901 print_version_id ();
7902 break;
7903
a38cf1db
AM		 7904 /* -k: Ignore for FreeBSD compatibility. */
7905 case 'k':
252b5132 7906 break;
4cc782b5
ILT		 7907
7908 case 's':
7909 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 7910 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 7911 break;
99ad8390 7912#endif
321098a5
L		 7913#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7914 || defined (TE_PE) || defined (TE_PEP))
3e73aa7c
JH		 7915 case OPTION_64:
7916 {
7917 const char **list, **l;
7918
3e73aa7c
JH		 7919 list = bfd_target_list ();
7920 for (l = list; *l != NULL; l++)
8620418b 7921 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 7922 || strcmp (*l, "coff-x86-64") == 0
7923 || strcmp (*l, "pe-x86-64") == 0
7924 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 7925 {
7926 default_arch = "x86_64";
7927 break;
7928 }
3e73aa7c 7929 if (*l == NULL)
6e0b89ee 7930 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 7931 free (list);
7932 }
7933 break;
7934#endif
252b5132 7935
6e0b89ee
AM		 7936 case OPTION_32:
7937 default_arch = "i386";
7938 break;
7939
b3b91714
AM		 7940 case OPTION_DIVIDE:
7941#ifdef SVR4_COMMENT_CHARS
7942 {
7943 char *n, *t;
7944 const char *s;
7945
7946 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
7947 t = n;
7948 for (s = i386_comment_chars; *s != '\0'; s++)
7949 if (*s != '/')
7950 *t++ = *s;
7951 *t = '\0';
7952 i386_comment_chars = n;
7953 }
7954#endif
7955 break;
7956
9103f4f4 7957 case OPTION_MARCH:
6305a203
L		 7958 arch = xstrdup (arg);
7959 do
9103f4f4 7960 {
6305a203
L		 7961 if (*arch == '.')
7962 as_fatal (_("Invalid -march= option: `%s'"), arg);
7963 next = strchr (arch, '+');
7964 if (next)
7965 *next++ = '\0';
7966 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
9103f4f4 7967 {
6305a203 7968 if (strcmp (arch, cpu_arch [i].name) == 0)
ccc9c027 7969 {
6305a203
L		 7970 /* Processor. */
7971 cpu_arch_name = cpu_arch[i].name;
7972 cpu_sub_arch_name = NULL;
7973 cpu_arch_flags = cpu_arch[i].flags;
7974 cpu_arch_isa = cpu_arch[i].type;
7975 cpu_arch_isa_flags = cpu_arch[i].flags;
7976 if (!cpu_arch_tune_set)
7977 {
7978 cpu_arch_tune = cpu_arch_isa;
7979 cpu_arch_tune_flags = cpu_arch_isa_flags;
7980 }
7981 break;
7982 }
7983 else if (*cpu_arch [i].name == '.'
7984 && strcmp (arch, cpu_arch [i].name + 1) == 0)
7985 {
7986 /* ISA entension. */
7987 i386_cpu_flags flags;
309d3373
JB		 7988
7989 if (strncmp (arch, "no", 2))
7990 flags = cpu_flags_or (cpu_arch_flags,
7991 cpu_arch[i].flags);
7992 else
7993 flags = cpu_flags_and_not (cpu_arch_flags,
7994 cpu_arch[i].flags);
0dfbf9d7 7995 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 7996 {
7997 if (cpu_sub_arch_name)
7998 {
7999 char *name = cpu_sub_arch_name;
8000 cpu_sub_arch_name = concat (name,
8001 cpu_arch[i].name,
1bf57e9f 8002 (const char *) NULL);
6305a203
L		 8003 free (name);
8004 }
8005 else
8006 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
8007 cpu_arch_flags = flags;
8008 }
8009 break;
ccc9c027 8010 }
9103f4f4 8011 }
6305a203
L		 8012
8013 if (i >= ARRAY_SIZE (cpu_arch))
8014 as_fatal (_("Invalid -march= option: `%s'"), arg);
8015
8016 arch = next;
9103f4f4 8017 }
6305a203 8018 while (next != NULL );
9103f4f4
L		 8019 break;
8020
8021 case OPTION_MTUNE:
8022 if (*arg == '.')
8023 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
8024 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
8025 {
8026 if (strcmp (arg, cpu_arch [i].name) == 0)
8027 {
ccc9c027 8028 cpu_arch_tune_set = 1;
9103f4f4
L		 8029 cpu_arch_tune = cpu_arch [i].type;
8030 cpu_arch_tune_flags = cpu_arch[i].flags;
8031 break;
8032 }
8033 }
8034 if (i >= ARRAY_SIZE (cpu_arch))
8035 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
8036 break;
8037
1efbbeb4
L		 8038 case OPTION_MMNEMONIC:
8039 if (strcasecmp (arg, "att") == 0)
8040 intel_mnemonic = 0;
8041 else if (strcasecmp (arg, "intel") == 0)
8042 intel_mnemonic = 1;
8043 else
8044 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
8045 break;
8046
8047 case OPTION_MSYNTAX:
8048 if (strcasecmp (arg, "att") == 0)
8049 intel_syntax = 0;
8050 else if (strcasecmp (arg, "intel") == 0)
8051 intel_syntax = 1;
8052 else
8053 as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
8054 break;
8055
8056 case OPTION_MINDEX_REG:
8057 allow_index_reg = 1;
8058 break;
8059
8060 case OPTION_MNAKED_REG:
8061 allow_naked_reg = 1;
8062 break;
8063
8064 case OPTION_MOLD_GCC:
8065 old_gcc = 1;
1efbbeb4
L		 8066 break;
8067
c0f3af97
L		 8068 case OPTION_MSSE2AVX:
8069 sse2avx = 1;
8070 break;
8071
daf50ae7
L		 8072 case OPTION_MSSE_CHECK:
8073 if (strcasecmp (arg, "error") == 0)
8074 sse_check = sse_check_error;
8075 else if (strcasecmp (arg, "warning") == 0)
8076 sse_check = sse_check_warning;
8077 else if (strcasecmp (arg, "none") == 0)
8078 sse_check = sse_check_none;
8079 else
8080 as_fatal (_("Invalid -msse-check= option: `%s'"), arg);
8081 break;
8082
252b5132
RH		 8083 default:
8084 return 0;
8085 }
8086 return 1;
8087}
8088
8a2c8fef
L		 8089#define MESSAGE_TEMPLATE \
8090" "
8091
8092static void
8093show_arch (FILE *stream, int ext)
8094{
8095 static char message[] = MESSAGE_TEMPLATE;
8096 char *start = message + 27;
8097 char *p;
8098 int size = sizeof (MESSAGE_TEMPLATE);
8099 int left;
8100 const char *name;
8101 int len;
8102 unsigned int j;
8103
8104 p = start;
8105 left = size - (start - message);
8106 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
8107 {
8108 /* Should it be skipped? */
8109 if (cpu_arch [j].skip)
8110 continue;
8111
8112 name = cpu_arch [j].name;
8113 len = cpu_arch [j].len;
8114 if (*name == '.')
8115 {
8116 /* It is an extension. Skip if we aren't asked to show it. */
8117 if (ext)
8118 {
8119 name++;
8120 len--;
8121 }
8122 else
8123 continue;
8124 }
8125 else if (ext)
8126 {
8127 /* It is an processor. Skip if we show only extension. */
8128 continue;
8129 }
8130
8131 /* Reserve 2 spaces for ", " or ",\0" */
8132 left -= len + 2;
8133
8134 /* Check if there is any room. */
8135 if (left >= 0)
8136 {
8137 if (p != start)
8138 {
8139 *p++ = ',';
8140 *p++ = ' ';
8141 }
8142 p = mempcpy (p, name, len);
8143 }
8144 else
8145 {
8146 /* Output the current message now and start a new one. */
8147 *p++ = ',';
8148 *p = '\0';
8149 fprintf (stream, "%s\n", message);
8150 p = start;
8151 left = size - (start - message) - len - 2;
8152
8153 gas_assert (left >= 0);
8154
8155 p = mempcpy (p, name, len);
8156 }
8157 }
8158
8159 *p = '\0';
8160 fprintf (stream, "%s\n", message);
8161}
8162
252b5132 8163void
8a2c8fef 8164md_show_usage (FILE *stream)
252b5132 8165{
4cc782b5
ILT		 8166#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8167 fprintf (stream, _("\
a38cf1db
AM		 8168 -Q ignored\n\
8169 -V print assembler version number\n\
b3b91714
AM		 8170 -k ignored\n"));
8171#endif
8172 fprintf (stream, _("\
12b55ccc 8173 -n Do not optimize code alignment\n\
b3b91714
AM		 8174 -q quieten some warnings\n"));
8175#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8176 fprintf (stream, _("\
a38cf1db 8177 -s ignored\n"));
b3b91714 8178#endif
321098a5
L		 8179#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8180 || defined (TE_PE) || defined (TE_PEP))
751d281c
L		 8181 fprintf (stream, _("\
8182 --32/--64 generate 32bit/64bit code\n"));
8183#endif
b3b91714
AM		 8184#ifdef SVR4_COMMENT_CHARS
8185 fprintf (stream, _("\
8186 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 8187#else
8188 fprintf (stream, _("\
b3b91714 8189 --divide ignored\n"));
4cc782b5 8190#endif
9103f4f4 8191 fprintf (stream, _("\
6305a203 8192 -march=CPU[,+EXTENSION...]\n\
8a2c8fef
L		 8193 generate code for CPU and EXTENSION, CPU is one of:\n"));
8194 show_arch (stream, 0);
8195 fprintf (stream, _("\
8196 EXTENSION is combination of:\n"));
8197 show_arch (stream, 1);
6305a203 8198 fprintf (stream, _("\
8a2c8fef
L		 8199 -mtune=CPU optimize for CPU, CPU is one of:\n"));
8200 show_arch (stream, 0);
ba104c83 8201 fprintf (stream, _("\
c0f3af97
L		 8202 -msse2avx encode SSE instructions with VEX prefix\n"));
8203 fprintf (stream, _("\
daf50ae7
L		 8204 -msse-check=[none|error|warning]\n\
8205 check SSE instructions\n"));
8206 fprintf (stream, _("\
ba104c83
L		 8207 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8208 fprintf (stream, _("\
8209 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8210 fprintf (stream, _("\
8211 -mindex-reg support pseudo index registers\n"));
8212 fprintf (stream, _("\
8213 -mnaked-reg don't require `%%' prefix for registers\n"));
8214 fprintf (stream, _("\
8215 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
252b5132
RH		 8216}
8217
3e73aa7c 8218#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 8219 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 8220 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 8221
8222/* Pick the target format to use. */
8223
47926f60 8224const char *
e3bb37b5 8225i386_target_format (void)
252b5132 8226{
3e73aa7c 8227 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 8228 {
8229 set_code_flag (CODE_64BIT);
0dfbf9d7 8230 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
40fb9820
L		 8231 {
8232 cpu_arch_isa_flags.bitfield.cpui186 = 1;
8233 cpu_arch_isa_flags.bitfield.cpui286 = 1;
8234 cpu_arch_isa_flags.bitfield.cpui386 = 1;
8235 cpu_arch_isa_flags.bitfield.cpui486 = 1;
8236 cpu_arch_isa_flags.bitfield.cpui586 = 1;
8237 cpu_arch_isa_flags.bitfield.cpui686 = 1;
bd5295b2 8238 cpu_arch_isa_flags.bitfield.cpuclflush = 1;
40fb9820 8239 cpu_arch_isa_flags.bitfield.cpummx= 1;
40fb9820
L		 8240 cpu_arch_isa_flags.bitfield.cpusse = 1;
8241 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
711eedef 8242 cpu_arch_isa_flags.bitfield.cpulm = 1;
40fb9820 8243 }
0dfbf9d7 8244 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
40fb9820
L		 8245 {
8246 cpu_arch_tune_flags.bitfield.cpui186 = 1;
8247 cpu_arch_tune_flags.bitfield.cpui286 = 1;
8248 cpu_arch_tune_flags.bitfield.cpui386 = 1;
8249 cpu_arch_tune_flags.bitfield.cpui486 = 1;
8250 cpu_arch_tune_flags.bitfield.cpui586 = 1;
8251 cpu_arch_tune_flags.bitfield.cpui686 = 1;
bd5295b2 8252 cpu_arch_tune_flags.bitfield.cpuclflush = 1;
40fb9820 8253 cpu_arch_tune_flags.bitfield.cpummx= 1;
40fb9820
L		 8254 cpu_arch_tune_flags.bitfield.cpusse = 1;
8255 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
8256 }
9103f4f4 8257 }
3e73aa7c 8258 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 8259 {
8260 set_code_flag (CODE_32BIT);
0dfbf9d7 8261 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
40fb9820
L		 8262 {
8263 cpu_arch_isa_flags.bitfield.cpui186 = 1;
8264 cpu_arch_isa_flags.bitfield.cpui286 = 1;
8265 cpu_arch_isa_flags.bitfield.cpui386 = 1;
8266 }
0dfbf9d7 8267 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
40fb9820
L		 8268 {
8269 cpu_arch_tune_flags.bitfield.cpui186 = 1;
8270 cpu_arch_tune_flags.bitfield.cpui286 = 1;
8271 cpu_arch_tune_flags.bitfield.cpui386 = 1;
8272 }
9103f4f4 8273 }
3e73aa7c
JH		 8274 else
8275 as_fatal (_("Unknown architecture"));
252b5132
RH		 8276 switch (OUTPUT_FLAVOR)
8277 {
9384f2ff 8278#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 8279 case bfd_target_aout_flavour:
47926f60 8280 return AOUT_TARGET_FORMAT;
4c63da97 8281#endif
9384f2ff
AM		 8282#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
8283# if defined (TE_PE) || defined (TE_PEP)
8284 case bfd_target_coff_flavour:
8285 return flag_code == CODE_64BIT ? "pe-x86-64" : "pe-i386";
8286# elif defined (TE_GO32)
0561d57c
JK		 8287 case bfd_target_coff_flavour:
8288 return "coff-go32";
9384f2ff 8289# else
252b5132
RH		 8290 case bfd_target_coff_flavour:
8291 return "coff-i386";
9384f2ff 8292# endif
4c63da97 8293#endif
3e73aa7c 8294#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 8295 case bfd_target_elf_flavour:
3e73aa7c 8296 {
e5cb08ac 8297 if (flag_code == CODE_64BIT)
4fa24527
JB		 8298 {
8299 object_64bit = 1;
8300 use_rela_relocations = 1;
8301 }
3632d14b 8302 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 8303 {
8304 if (flag_code != CODE_64BIT)
8305 as_fatal (_("Intel L1OM is 64bit only"));
8306 return ELF_TARGET_L1OM_FORMAT;
8307 }
8308 else
8309 return (flag_code == CODE_64BIT
8310 ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT);
3e73aa7c 8311 }
e57f8c65
TG		 8312#endif
8313#if defined (OBJ_MACH_O)
8314 case bfd_target_mach_o_flavour:
8315 return flag_code == CODE_64BIT ? "mach-o-x86-64" : "mach-o-i386";
4c63da97 8316#endif
252b5132
RH		 8317 default:
8318 abort ();
8319 return NULL;
8320 }
8321}
8322
47926f60 8323#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 8324
8325#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 8326void
8327i386_elf_emit_arch_note (void)
a847613f 8328{
718ddfc0 8329 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 8330 {
8331 char *p;
8332 asection *seg = now_seg;
8333 subsegT subseg = now_subseg;
8334 Elf_Internal_Note i_note;
8335 Elf_External_Note e_note;
8336 asection *note_secp;
8337 int len;
8338
8339 /* Create the .note section. */
8340 note_secp = subseg_new (".note", 0);
8341 bfd_set_section_flags (stdoutput,
8342 note_secp,
8343 SEC_HAS_CONTENTS | SEC_READONLY);
8344
8345 /* Process the arch string. */
8346 len = strlen (cpu_arch_name);
8347
8348 i_note.namesz = len + 1;
8349 i_note.descsz = 0;
8350 i_note.type = NT_ARCH;
8351 p = frag_more (sizeof (e_note.namesz));
8352 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
8353 p = frag_more (sizeof (e_note.descsz));
8354 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
8355 p = frag_more (sizeof (e_note.type));
8356 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
8357 p = frag_more (len + 1);
8358 strcpy (p, cpu_arch_name);
8359
8360 frag_align (2, 0, 0);
8361
8362 subseg_set (seg, subseg);
8363 }
8364}
8365#endif
252b5132 8366\f
252b5132
RH		 8367symbolS *
8368md_undefined_symbol (name)
8369 char *name;
8370{
18dc2407
ILT		 8371 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
8372 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
8373 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
8374 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 8375 {
8376 if (!GOT_symbol)
8377 {
8378 if (symbol_find (name))
8379 as_bad (_("GOT already in symbol table"));
8380 GOT_symbol = symbol_new (name, undefined_section,
8381 (valueT) 0, &zero_address_frag);
8382 };
8383 return GOT_symbol;
8384 }
252b5132
RH		 8385 return 0;
8386}
8387
8388/* Round up a section size to the appropriate boundary. */
47926f60 8389
252b5132
RH		 8390valueT
8391md_section_align (segment, size)
ab9da554 8392 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 8393 valueT size;
8394{
4c63da97
AM		 8395#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8396 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
8397 {
8398 /* For a.out, force the section size to be aligned. If we don't do
8399 this, BFD will align it for us, but it will not write out the
8400 final bytes of the section. This may be a bug in BFD, but it is
8401 easier to fix it here since that is how the other a.out targets
8402 work. */
8403 int align;
8404
8405 align = bfd_get_section_alignment (stdoutput, segment);
8406 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
8407 }
252b5132
RH		 8408#endif
8409
8410 return size;
8411}
8412
8413/* On the i386, PC-relative offsets are relative to the start of the
8414 next instruction. That is, the address of the offset, plus its
8415 size, since the offset is always the last part of the insn. */
8416
8417long
e3bb37b5 8418md_pcrel_from (fixS *fixP)
252b5132
RH		 8419{
8420 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
8421}
8422
8423#ifndef I386COFF
8424
8425static void
e3bb37b5 8426s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 8427{
29b0f896 8428 int temp;
252b5132 8429
8a75718c
JB		 8430#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8431 if (IS_ELF)
8432 obj_elf_section_change_hook ();
8433#endif
252b5132
RH		 8434 temp = get_absolute_expression ();
8435 subseg_set (bss_section, (subsegT) temp);
8436 demand_empty_rest_of_line ();
8437}
8438
8439#endif
8440
252b5132 8441void
e3bb37b5 8442i386_validate_fix (fixS *fixp)
252b5132
RH		 8443{
8444 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
8445 {
23df1078
JH		 8446 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
8447 {
4fa24527 8448 if (!object_64bit)
23df1078
JH		 8449 abort ();
8450 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
8451 }
8452 else
8453 {
4fa24527 8454 if (!object_64bit)
d6ab8113
JB		 8455 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
8456 else
8457 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 8458 }
252b5132
RH		 8459 fixp->fx_subsy = 0;
8460 }
8461}
8462
252b5132
RH		 8463arelent *
8464tc_gen_reloc (section, fixp)
ab9da554 8465 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 8466 fixS *fixp;
8467{
8468 arelent *rel;
8469 bfd_reloc_code_real_type code;
8470
8471 switch (fixp->fx_r_type)
8472 {
3e73aa7c
JH		 8473 case BFD_RELOC_X86_64_PLT32:
8474 case BFD_RELOC_X86_64_GOT32:
8475 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 8476 case BFD_RELOC_386_PLT32:
8477 case BFD_RELOC_386_GOT32:
8478 case BFD_RELOC_386_GOTOFF:
8479 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 8480 case BFD_RELOC_386_TLS_GD:
8481 case BFD_RELOC_386_TLS_LDM:
8482 case BFD_RELOC_386_TLS_LDO_32:
8483 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 8484 case BFD_RELOC_386_TLS_IE:
8485 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 8486 case BFD_RELOC_386_TLS_LE_32:
8487 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 8488 case BFD_RELOC_386_TLS_GOTDESC:
8489 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 8490 case BFD_RELOC_X86_64_TLSGD:
8491 case BFD_RELOC_X86_64_TLSLD:
8492 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 8493 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 8494 case BFD_RELOC_X86_64_GOTTPOFF:
8495 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 8496 case BFD_RELOC_X86_64_TPOFF64:
8497 case BFD_RELOC_X86_64_GOTOFF64:
8498 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 8499 case BFD_RELOC_X86_64_GOT64:
8500 case BFD_RELOC_X86_64_GOTPCREL64:
8501 case BFD_RELOC_X86_64_GOTPC64:
8502 case BFD_RELOC_X86_64_GOTPLT64:
8503 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 8504 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8505 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 8506 case BFD_RELOC_RVA:
8507 case BFD_RELOC_VTABLE_ENTRY:
8508 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 8509#ifdef TE_PE
8510 case BFD_RELOC_32_SECREL:
8511#endif
252b5132
RH		 8512 code = fixp->fx_r_type;
8513 break;
dbbaec26
L		 8514 case BFD_RELOC_X86_64_32S:
8515 if (!fixp->fx_pcrel)
8516 {
8517 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8518 code = fixp->fx_r_type;
8519 break;
8520 }
252b5132 8521 default:
93382f6d 8522 if (fixp->fx_pcrel)
252b5132 8523 {
93382f6d
AM		 8524 switch (fixp->fx_size)
8525 {
8526 default:
b091f402
AM		 8527 as_bad_where (fixp->fx_file, fixp->fx_line,
8528 _("can not do %d byte pc-relative relocation"),
8529 fixp->fx_size);
93382f6d
AM		 8530 code = BFD_RELOC_32_PCREL;
8531 break;
8532 case 1: code = BFD_RELOC_8_PCREL; break;
8533 case 2: code = BFD_RELOC_16_PCREL; break;
8534 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 8535#ifdef BFD64
8536 case 8: code = BFD_RELOC_64_PCREL; break;
8537#endif
93382f6d
AM		 8538 }
8539 }
8540 else
8541 {
8542 switch (fixp->fx_size)
8543 {
8544 default:
b091f402
AM		 8545 as_bad_where (fixp->fx_file, fixp->fx_line,
8546 _("can not do %d byte relocation"),
8547 fixp->fx_size);
93382f6d
AM		 8548 code = BFD_RELOC_32;
8549 break;
8550 case 1: code = BFD_RELOC_8; break;
8551 case 2: code = BFD_RELOC_16; break;
8552 case 4: code = BFD_RELOC_32; break;
937149dd 8553#ifdef BFD64
3e73aa7c 8554 case 8: code = BFD_RELOC_64; break;
937149dd 8555#endif
93382f6d 8556 }
252b5132
RH		 8557 }
8558 break;
8559 }
252b5132 8560
d182319b
JB		 8561 if ((code == BFD_RELOC_32
8562 || code == BFD_RELOC_32_PCREL
8563 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 8564 && GOT_symbol
8565 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 8566 {
4fa24527 8567 if (!object_64bit)
d6ab8113
JB		 8568 code = BFD_RELOC_386_GOTPC;
8569 else
8570 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 8571 }
7b81dfbb
AJ		 8572 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
8573 && GOT_symbol
8574 && fixp->fx_addsy == GOT_symbol)
8575 {
8576 code = BFD_RELOC_X86_64_GOTPC64;
8577 }
252b5132
RH		 8578
8579 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 8580 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
8581 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 8582
8583 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 8584
3e73aa7c
JH		 8585 if (!use_rela_relocations)
8586 {
8587 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8588 vtable entry to be used in the relocation's section offset. */
8589 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
8590 rel->address = fixp->fx_offset;
fbeb56a4
DK		 8591#if defined (OBJ_COFF) && defined (TE_PE)
8592 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
8593 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
8594 else
8595#endif
c6682705 8596 rel->addend = 0;
3e73aa7c
JH		 8597 }
8598 /* Use the rela in 64bit mode. */
252b5132 8599 else
3e73aa7c 8600 {
062cd5e7
AS		 8601 if (!fixp->fx_pcrel)
8602 rel->addend = fixp->fx_offset;
8603 else
8604 switch (code)
8605 {
8606 case BFD_RELOC_X86_64_PLT32:
8607 case BFD_RELOC_X86_64_GOT32:
8608 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 8609 case BFD_RELOC_X86_64_TLSGD:
8610 case BFD_RELOC_X86_64_TLSLD:
8611 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 8612 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8613 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 8614 rel->addend = fixp->fx_offset - fixp->fx_size;
8615 break;
8616 default:
8617 rel->addend = (section->vma
8618 - fixp->fx_size
8619 + fixp->fx_addnumber
8620 + md_pcrel_from (fixp));
8621 break;
8622 }
3e73aa7c
JH		 8623 }
8624
252b5132
RH		 8625 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
8626 if (rel->howto == NULL)
8627 {
8628 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 8629 _("cannot represent relocation type %s"),
252b5132
RH		 8630 bfd_get_reloc_code_name (code));
8631 /* Set howto to a garbage value so that we can keep going. */
8632 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 8633 gas_assert (rel->howto != NULL);
252b5132
RH		 8634 }
8635
8636 return rel;
8637}
8638
ee86248c 8639#include "tc-i386-intel.c"
54cfded0 8640
a60de03c
JB		 8641void
8642tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 8643{
a60de03c
JB		 8644 int saved_naked_reg;
8645 char saved_register_dot;
54cfded0 8646
a60de03c
JB		 8647 saved_naked_reg = allow_naked_reg;
8648 allow_naked_reg = 1;
8649 saved_register_dot = register_chars['.'];
8650 register_chars['.'] = '.';
8651 allow_pseudo_reg = 1;
8652 expression_and_evaluate (exp);
8653 allow_pseudo_reg = 0;
8654 register_chars['.'] = saved_register_dot;
8655 allow_naked_reg = saved_naked_reg;
8656
8657 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 8658 {
a60de03c
JB		 8659 if ((addressT) exp->X_add_number < i386_regtab_size)
8660 {
8661 exp->X_op = O_constant;
8662 exp->X_add_number = i386_regtab[exp->X_add_number]
8663 .dw2_regnum[flag_code >> 1];
8664 }
8665 else
8666 exp->X_op = O_illegal;
54cfded0 8667 }
54cfded0
AM		 8668}
8669
8670void
8671tc_x86_frame_initial_instructions (void)
8672{
a60de03c
JB		 8673 static unsigned int sp_regno[2];
8674
8675 if (!sp_regno[flag_code >> 1])
8676 {
8677 char *saved_input = input_line_pointer;
8678 char sp[][4] = {"esp", "rsp"};
8679 expressionS exp;
a4447b93 8680
a60de03c
JB		 8681 input_line_pointer = sp[flag_code >> 1];
8682 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 8683 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 8684 sp_regno[flag_code >> 1] = exp.X_add_number;
8685 input_line_pointer = saved_input;
8686 }
a4447b93 8687
a60de03c 8688 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
a4447b93 8689 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 8690}
d2b2c203
DJ		 8691
8692int
8693i386_elf_section_type (const char *str, size_t len)
8694{
8695 if (flag_code == CODE_64BIT
8696 && len == sizeof ("unwind") - 1
8697 && strncmp (str, "unwind", 6) == 0)
8698 return SHT_X86_64_UNWIND;
8699
8700 return -1;
8701}
bb41ade5 8702
ad5fec3b
EB		 8703#ifdef TE_SOLARIS
8704void
8705i386_solaris_fix_up_eh_frame (segT sec)
8706{
8707 if (flag_code == CODE_64BIT)
8708 elf_section_type (sec) = SHT_X86_64_UNWIND;
8709}
8710#endif
8711
bb41ade5
AM		 8712#ifdef TE_PE
8713void
8714tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
8715{
8716 expressionS expr;
8717
8718 expr.X_op = O_secrel;
8719 expr.X_add_symbol = symbol;
8720 expr.X_add_number = 0;
8721 emit_expr (&expr, size);
8722}
8723#endif
3b22753a
L		 8724
8725#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8726/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8727
01e1a5bc 8728bfd_vma
3b22753a
L		 8729x86_64_section_letter (int letter, char **ptr_msg)
8730{
8731 if (flag_code == CODE_64BIT)
8732 {
8733 if (letter == 'l')
8734 return SHF_X86_64_LARGE;
8735
8736 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 8737 }
3b22753a 8738 else
64e74474 8739 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 8740 return -1;
8741}
8742
01e1a5bc 8743bfd_vma
3b22753a
L		 8744x86_64_section_word (char *str, size_t len)
8745{
8620418b 8746 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 8747 return SHF_X86_64_LARGE;
8748
8749 return -1;
8750}
8751
8752static void
8753handle_large_common (int small ATTRIBUTE_UNUSED)
8754{
8755 if (flag_code != CODE_64BIT)
8756 {
8757 s_comm_internal (0, elf_common_parse);
8758 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
8759 }
8760 else
8761 {
8762 static segT lbss_section;
8763 asection *saved_com_section_ptr = elf_com_section_ptr;
8764 asection *saved_bss_section = bss_section;
8765
8766 if (lbss_section == NULL)
8767 {
8768 flagword applicable;
8769 segT seg = now_seg;
8770 subsegT subseg = now_subseg;
8771
8772 /* The .lbss section is for local .largecomm symbols. */
8773 lbss_section = subseg_new (".lbss", 0);
8774 applicable = bfd_applicable_section_flags (stdoutput);
8775 bfd_set_section_flags (stdoutput, lbss_section,
8776 applicable & SEC_ALLOC);
8777 seg_info (lbss_section)->bss = 1;
8778
8779 subseg_set (seg, subseg);
8780 }
8781
8782 elf_com_section_ptr = &_bfd_elf_large_com_section;
8783 bss_section = lbss_section;
8784
8785 s_comm_internal (0, elf_common_parse);
8786
8787 elf_com_section_ptr = saved_com_section_ptr;
8788 bss_section = saved_bss_section;
8789 }
8790}
8791#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
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