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* as.h (ENABLE_CHECKING): Default define to 0.
[binutils.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4dc85607 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus ([email protected]).
3e73aa7c 25 x86_64 support by Jan Hubicka ([email protected])
0f10071e 26 VIA PadLock support by Michal Ludvig ([email protected])
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
252b5132 36
252b5132
RH		 37#ifndef REGISTER_WARNINGS
38#define REGISTER_WARNINGS 1
39#endif
40
c3332e24 41#ifndef INFER_ADDR_PREFIX
eecb386c 42#define INFER_ADDR_PREFIX 1
c3332e24
AM		 43#endif
44
252b5132
RH		 45#ifndef SCALE1_WHEN_NO_INDEX
46/* Specifying a scale factor besides 1 when there is no index is
47 futile. eg. `mov (%ebx,2),%al' does exactly the same as
48 `mov (%ebx),%al'. To slavishly follow what the programmer
49 specified, set SCALE1_WHEN_NO_INDEX to 0. */
50#define SCALE1_WHEN_NO_INDEX 1
51#endif
52
29b0f896
AM		 53#ifndef DEFAULT_ARCH
54#define DEFAULT_ARCH "i386"
246fcdee 55#endif
252b5132 56
edde18a5
AM		 57#ifndef INLINE
58#if __GNUC__ >= 2
59#define INLINE __inline__
60#else
61#define INLINE
62#endif
63#endif
64
e3bb37b5
L		 65static void set_code_flag (int);
66static void set_16bit_gcc_code_flag (int);
67static void set_intel_syntax (int);
68static void set_cpu_arch (int);
6482c264 69#ifdef TE_PE
e3bb37b5 70static void pe_directive_secrel (int);
6482c264 71#endif
e3bb37b5
L		 72static void signed_cons (int);
73static char *output_invalid (int c);
74static int i386_operand (char *);
75static int i386_intel_operand (char *, int);
76static const reg_entry *parse_register (char *, char **);
77static char *parse_insn (char *, char *);
78static char *parse_operands (char *, const char *);
79static void swap_operands (void);
4d456e3d 80static void swap_2_operands (int, int);
e3bb37b5
L		 81static void optimize_imm (void);
82static void optimize_disp (void);
83static int match_template (void);
84static int check_string (void);
85static int process_suffix (void);
86static int check_byte_reg (void);
87static int check_long_reg (void);
88static int check_qword_reg (void);
89static int check_word_reg (void);
90static int finalize_imm (void);
91static int process_operands (void);
92static const seg_entry *build_modrm_byte (void);
93static void output_insn (void);
94static void output_imm (fragS *, offsetT);
95static void output_disp (fragS *, offsetT);
29b0f896 96#ifndef I386COFF
e3bb37b5 97static void s_bss (int);
252b5132 98#endif
17d4e2a2
L		 99#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
100static void handle_large_common (int small ATTRIBUTE_UNUSED);
101#endif
252b5132 102
a847613f 103static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 104
252b5132 105/* 'md_assemble ()' gathers together information and puts it into a
47926f60 106 i386_insn. */
252b5132 107
520dc8e8
AM		 108union i386_op
109 {
110 expressionS *disps;
111 expressionS *imms;
112 const reg_entry *regs;
113 };
114
252b5132
RH		 115struct _i386_insn
116 {
47926f60 117 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 118 template tm;
119
120 /* SUFFIX holds the instruction mnemonic suffix if given.
121 (e.g. 'l' for 'movl') */
122 char suffix;
123
47926f60 124 /* OPERANDS gives the number of given operands. */
252b5132
RH		 125 unsigned int operands;
126
127 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
128 of given register, displacement, memory operands and immediate
47926f60 129 operands. */
252b5132
RH		 130 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
131
132 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 133 use OP[i] for the corresponding operand. */
252b5132
RH		 134 unsigned int types[MAX_OPERANDS];
135
520dc8e8
AM		 136 /* Displacement expression, immediate expression, or register for each
137 operand. */
138 union i386_op op[MAX_OPERANDS];
252b5132 139
3e73aa7c
JH		 140 /* Flags for operands. */
141 unsigned int flags[MAX_OPERANDS];
142#define Operand_PCrel 1
143
252b5132 144 /* Relocation type for operand */
f86103b7 145 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 146
252b5132
RH		 147 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
148 the base index byte below. */
149 const reg_entry *base_reg;
150 const reg_entry *index_reg;
151 unsigned int log2_scale_factor;
152
153 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 154 explicit segment overrides are given. */
ce8a8b2f 155 const seg_entry *seg[2];
252b5132
RH		 156
157 /* PREFIX holds all the given prefix opcodes (usually null).
158 PREFIXES is the number of prefix opcodes. */
159 unsigned int prefixes;
160 unsigned char prefix[MAX_PREFIXES];
161
162 /* RM and SIB are the modrm byte and the sib byte where the
163 addressing modes of this insn are encoded. */
164
165 modrm_byte rm;
3e73aa7c 166 rex_byte rex;
252b5132
RH		 167 sib_byte sib;
168 };
169
170typedef struct _i386_insn i386_insn;
171
172/* List of chars besides those in app.c:symbol_chars that can start an
173 operand. Used to prevent the scrubber eating vital white-space. */
32137342 174const char extra_symbol_chars[] = "*%-(["
252b5132 175#ifdef LEX_AT
32137342
NC		 176 "@"
177#endif
178#ifdef LEX_QM
179 "?"
252b5132 180#endif
32137342 181 ;
252b5132 182
29b0f896
AM		 183#if (defined (TE_I386AIX) \
184 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 185 && !defined (TE_GNU) \
29b0f896 186 && !defined (TE_LINUX) \
32137342 187 && !defined (TE_NETWARE) \
29b0f896
AM		 188 && !defined (TE_FreeBSD) \
189 && !defined (TE_NetBSD)))
252b5132 190/* This array holds the chars that always start a comment. If the
b3b91714
AM		 191 pre-processor is disabled, these aren't very useful. The option
192 --divide will remove '/' from this list. */
193const char *i386_comment_chars = "#/";
194#define SVR4_COMMENT_CHARS 1
252b5132 195#define PREFIX_SEPARATOR '\\'
252b5132 196
b3b91714
AM		 197#else
198const char *i386_comment_chars = "#";
199#define PREFIX_SEPARATOR '/'
200#endif
201
252b5132
RH		 202/* This array holds the chars that only start a comment at the beginning of
203 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 204 .line and .file directives will appear in the pre-processed output.
205 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 206 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 207 #NO_APP at the beginning of its output.
208 Also note that comments started like this one will always work if
252b5132 209 '/' isn't otherwise defined. */
b3b91714 210const char line_comment_chars[] = "#/";
252b5132 211
63a0b638 212const char line_separator_chars[] = ";";
252b5132 213
ce8a8b2f
AM		 214/* Chars that can be used to separate mant from exp in floating point
215 nums. */
252b5132
RH		 216const char EXP_CHARS[] = "eE";
217
ce8a8b2f
AM		 218/* Chars that mean this number is a floating point constant
219 As in 0f12.456
220 or 0d1.2345e12. */
252b5132
RH		 221const char FLT_CHARS[] = "fFdDxX";
222
ce8a8b2f 223/* Tables for lexical analysis. */
252b5132
RH		 224static char mnemonic_chars[256];
225static char register_chars[256];
226static char operand_chars[256];
227static char identifier_chars[256];
228static char digit_chars[256];
229
ce8a8b2f 230/* Lexical macros. */
252b5132
RH		 231#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
232#define is_operand_char(x) (operand_chars[(unsigned char) x])
233#define is_register_char(x) (register_chars[(unsigned char) x])
234#define is_space_char(x) ((x) == ' ')
235#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
236#define is_digit_char(x) (digit_chars[(unsigned char) x])
237
0234cb7c 238/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 239static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
240
241/* md_assemble() always leaves the strings it's passed unaltered. To
242 effect this we maintain a stack of saved characters that we've smashed
243 with '\0's (indicating end of strings for various sub-fields of the
47926f60 244 assembler instruction). */
252b5132 245static char save_stack[32];
ce8a8b2f 246static char *save_stack_p;
252b5132
RH		 247#define END_STRING_AND_SAVE(s) \
248 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
249#define RESTORE_END_STRING(s) \
250 do { *(s) = *--save_stack_p; } while (0)
251
47926f60 252/* The instruction we're assembling. */
252b5132
RH		 253static i386_insn i;
254
255/* Possible templates for current insn. */
256static const templates *current_templates;
257
31b2323c
L		 258/* Per instruction expressionS buffers: max displacements & immediates. */
259static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
260static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 261
47926f60
KH		 262/* Current operand we are working on. */
263static int this_operand;
252b5132 264
3e73aa7c
JH		 265/* We support four different modes. FLAG_CODE variable is used to distinguish
266 these. */
267
268enum flag_code {
269 CODE_32BIT,
270 CODE_16BIT,
271 CODE_64BIT };
f3c180ae 272#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
3e73aa7c
JH		 273
274static enum flag_code flag_code;
4fa24527 275static unsigned int object_64bit;
3e73aa7c
JH		 276static int use_rela_relocations = 0;
277
278/* The names used to print error messages. */
b77a7acd 279static const char *flag_code_names[] =
3e73aa7c
JH		 280 {
281 "32",
282 "16",
283 "64"
284 };
252b5132 285
47926f60
KH		 286/* 1 for intel syntax,
287 0 if att syntax. */
288static int intel_syntax = 0;
252b5132 289
47926f60
KH		 290/* 1 if register prefix % not required. */
291static int allow_naked_reg = 0;
252b5132 292
2ca3ace5
L		 293/* Register prefix used for error message. */
294static const char *register_prefix = "%";
295
47926f60
KH		 296/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
297 leave, push, and pop instructions so that gcc has the same stack
298 frame as in 32 bit mode. */
299static char stackop_size = '\0';
eecb386c 300
12b55ccc
L		 301/* Non-zero to optimize code alignment. */
302int optimize_align_code = 1;
303
47926f60
KH		 304/* Non-zero to quieten some warnings. */
305static int quiet_warnings = 0;
a38cf1db 306
47926f60
KH		 307/* CPU name. */
308static const char *cpu_arch_name = NULL;
5c6af06e 309static const char *cpu_sub_arch_name = NULL;
a38cf1db 310
47926f60 311/* CPU feature flags. */
29b0f896 312static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
a38cf1db 313
ccc9c027
L		 314/* If we have selected a cpu we are generating instructions for. */
315static int cpu_arch_tune_set = 0;
316
9103f4f4
L		 317/* Cpu we are generating instructions for. */
318static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
319
320/* CPU feature flags of cpu we are generating instructions for. */
321static unsigned int cpu_arch_tune_flags = 0;
322
ccc9c027
L		 323/* CPU instruction set architecture used. */
324static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
325
9103f4f4
L		 326/* CPU feature flags of instruction set architecture used. */
327static unsigned int cpu_arch_isa_flags = 0;
328
fddf5b5b
AM		 329/* If set, conditional jumps are not automatically promoted to handle
330 larger than a byte offset. */
331static unsigned int no_cond_jump_promotion = 0;
332
29b0f896 333/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 334static symbolS *GOT_symbol;
29b0f896 335
a4447b93
RH		 336/* The dwarf2 return column, adjusted for 32 or 64 bit. */
337unsigned int x86_dwarf2_return_column;
338
339/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
340int x86_cie_data_alignment;
341
252b5132 342/* Interface to relax_segment.
fddf5b5b
AM		 343 There are 3 major relax states for 386 jump insns because the
344 different types of jumps add different sizes to frags when we're
345 figuring out what sort of jump to choose to reach a given label. */
252b5132 346
47926f60 347/* Types. */
93c2a809
AM		 348#define UNCOND_JUMP 0
349#define COND_JUMP 1
350#define COND_JUMP86 2
fddf5b5b 351
47926f60 352/* Sizes. */
252b5132
RH		 353#define CODE16 1
354#define SMALL 0
29b0f896 355#define SMALL16 (SMALL | CODE16)
252b5132 356#define BIG 2
29b0f896 357#define BIG16 (BIG | CODE16)
252b5132
RH		 358
359#ifndef INLINE
360#ifdef __GNUC__
361#define INLINE __inline__
362#else
363#define INLINE
364#endif
365#endif
366
fddf5b5b
AM		 367#define ENCODE_RELAX_STATE(type, size) \
368 ((relax_substateT) (((type) << 2) | (size)))
369#define TYPE_FROM_RELAX_STATE(s) \
370 ((s) >> 2)
371#define DISP_SIZE_FROM_RELAX_STATE(s) \
372 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 373
374/* This table is used by relax_frag to promote short jumps to long
375 ones where necessary. SMALL (short) jumps may be promoted to BIG
376 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
377 don't allow a short jump in a 32 bit code segment to be promoted to
378 a 16 bit offset jump because it's slower (requires data size
379 prefix), and doesn't work, unless the destination is in the bottom
380 64k of the code segment (The top 16 bits of eip are zeroed). */
381
382const relax_typeS md_relax_table[] =
383{
24eab124
AM		 384 /* The fields are:
385 1) most positive reach of this state,
386 2) most negative reach of this state,
93c2a809 387 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 388 4) which index into the table to try if we can't fit into this one. */
252b5132 389
fddf5b5b 390 /* UNCOND_JUMP states. */
93c2a809
AM		 391 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
392 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
393 /* dword jmp adds 4 bytes to frag:
394 0 extra opcode bytes, 4 displacement bytes. */
252b5132 395 {0, 0, 4, 0},
93c2a809
AM		 396 /* word jmp adds 2 byte2 to frag:
397 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 398 {0, 0, 2, 0},
399
93c2a809
AM		 400 /* COND_JUMP states. */
401 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
402 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
403 /* dword conditionals adds 5 bytes to frag:
404 1 extra opcode byte, 4 displacement bytes. */
405 {0, 0, 5, 0},
fddf5b5b 406 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 407 1 extra opcode byte, 2 displacement bytes. */
408 {0, 0, 3, 0},
409
410 /* COND_JUMP86 states. */
411 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
412 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
413 /* dword conditionals adds 5 bytes to frag:
414 1 extra opcode byte, 4 displacement bytes. */
415 {0, 0, 5, 0},
416 /* word conditionals add 4 bytes to frag:
417 1 displacement byte and a 3 byte long branch insn. */
418 {0, 0, 4, 0}
252b5132
RH		 419};
420
9103f4f4
L		 421static const arch_entry cpu_arch[] =
422{
423 {"generic32", PROCESSOR_GENERIC32,
d32cad65 424 Cpu186|Cpu286|Cpu386},
9103f4f4 425 {"generic64", PROCESSOR_GENERIC64,
d32cad65 426 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 427 |CpuMMX2|CpuSSE|CpuSSE2},
428 {"i8086", PROCESSOR_UNKNOWN,
d32cad65 429 0},
9103f4f4 430 {"i186", PROCESSOR_UNKNOWN,
d32cad65 431 Cpu186},
9103f4f4 432 {"i286", PROCESSOR_UNKNOWN,
d32cad65 433 Cpu186|Cpu286},
9103f4f4 434 {"i386", PROCESSOR_GENERIC32,
d32cad65 435 Cpu186|Cpu286|Cpu386},
9103f4f4 436 {"i486", PROCESSOR_I486,
d32cad65 437 Cpu186|Cpu286|Cpu386|Cpu486},
9103f4f4 438 {"i586", PROCESSOR_PENTIUM,
d32cad65 439 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
9103f4f4 440 {"i686", PROCESSOR_PENTIUMPRO,
d32cad65 441 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
9103f4f4 442 {"pentium", PROCESSOR_PENTIUM,
d32cad65 443 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
9103f4f4 444 {"pentiumpro",PROCESSOR_PENTIUMPRO,
d32cad65 445 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
9103f4f4 446 {"pentiumii", PROCESSOR_PENTIUMPRO,
d32cad65 447 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX},
9103f4f4 448 {"pentiumiii",PROCESSOR_PENTIUMPRO,
d32cad65 449 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE},
9103f4f4 450 {"pentium4", PROCESSOR_PENTIUM4,
d32cad65 451 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 452 |CpuMMX2|CpuSSE|CpuSSE2},
453 {"prescott", PROCESSOR_NOCONA,
d32cad65 454 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 455 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
456 {"nocona", PROCESSOR_NOCONA,
d32cad65 457 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4 458 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
ef05d495 459 {"yonah", PROCESSOR_CORE,
d32cad65 460 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4 461 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
ef05d495 462 {"core", PROCESSOR_CORE,
d32cad65 463 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
ef05d495
L		 464 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
465 {"merom", PROCESSOR_CORE2,
466 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
467 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
468 {"core2", PROCESSOR_CORE2,
469 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
470 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
9103f4f4 471 {"k6", PROCESSOR_K6,
d32cad65 472 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX},
9103f4f4 473 {"k6_2", PROCESSOR_K6,
d32cad65 474 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow},
9103f4f4 475 {"athlon", PROCESSOR_ATHLON,
d32cad65 476 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 477 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
478 {"sledgehammer", PROCESSOR_K8,
d32cad65 479 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 480 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
481 {"opteron", PROCESSOR_K8,
d32cad65 482 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 483 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
484 {"k8", PROCESSOR_K8,
d32cad65 485 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4 486 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
050dfa73 487 {"amdfam10", PROCESSOR_AMDFAM10,
d32cad65
L		 488 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuSledgehammer
489 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a
490 |CpuABM},
9103f4f4
L		 491 {".mmx", PROCESSOR_UNKNOWN,
492 CpuMMX},
493 {".sse", PROCESSOR_UNKNOWN,
494 CpuMMX|CpuMMX2|CpuSSE},
495 {".sse2", PROCESSOR_UNKNOWN,
496 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2},
497 {".sse3", PROCESSOR_UNKNOWN,
498 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
ef05d495
L		 499 {".ssse3", PROCESSOR_UNKNOWN,
500 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
42903f7f
L		 501 {".sse4.1", PROCESSOR_UNKNOWN,
502 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1},
381d071f
L		 503 {".sse4.2", PROCESSOR_UNKNOWN,
504 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4},
505 {".sse4", PROCESSOR_UNKNOWN,
506 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4},
9103f4f4
L		 507 {".3dnow", PROCESSOR_UNKNOWN,
508 CpuMMX|Cpu3dnow},
509 {".3dnowa", PROCESSOR_UNKNOWN,
510 CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
511 {".padlock", PROCESSOR_UNKNOWN,
512 CpuPadLock},
513 {".pacifica", PROCESSOR_UNKNOWN,
514 CpuSVME},
515 {".svme", PROCESSOR_UNKNOWN,
050dfa73
MM		 516 CpuSVME},
517 {".sse4a", PROCESSOR_UNKNOWN,
518 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a},
519 {".abm", PROCESSOR_UNKNOWN,
520 CpuABM}
e413e4e9
AM		 521};
522
29b0f896
AM		 523const pseudo_typeS md_pseudo_table[] =
524{
525#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
526 {"align", s_align_bytes, 0},
527#else
528 {"align", s_align_ptwo, 0},
529#endif
530 {"arch", set_cpu_arch, 0},
531#ifndef I386COFF
532 {"bss", s_bss, 0},
533#endif
534 {"ffloat", float_cons, 'f'},
535 {"dfloat", float_cons, 'd'},
536 {"tfloat", float_cons, 'x'},
537 {"value", cons, 2},
d182319b 538 {"slong", signed_cons, 4},
29b0f896
AM		 539 {"noopt", s_ignore, 0},
540 {"optim", s_ignore, 0},
541 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
542 {"code16", set_code_flag, CODE_16BIT},
543 {"code32", set_code_flag, CODE_32BIT},
544 {"code64", set_code_flag, CODE_64BIT},
545 {"intel_syntax", set_intel_syntax, 1},
546 {"att_syntax", set_intel_syntax, 0},
3b22753a
L		 547#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
548 {"largecomm", handle_large_common, 0},
07a53e5c 549#else
e3bb37b5 550 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 551 {"loc", dwarf2_directive_loc, 0},
552 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 553#endif
6482c264
NC		 554#ifdef TE_PE
555 {"secrel32", pe_directive_secrel, 0},
556#endif
29b0f896
AM		 557 {0, 0, 0}
558};
559
560/* For interface with expression (). */
561extern char *input_line_pointer;
562
563/* Hash table for instruction mnemonic lookup. */
564static struct hash_control *op_hash;
565
566/* Hash table for register lookup. */
567static struct hash_control *reg_hash;
568\f
252b5132 569void
e3bb37b5 570i386_align_code (fragS *fragP, int count)
252b5132 571{
ce8a8b2f
AM		 572 /* Various efficient no-op patterns for aligning code labels.
573 Note: Don't try to assemble the instructions in the comments.
574 0L and 0w are not legal. */
252b5132
RH		 575 static const char f32_1[] =
576 {0x90}; /* nop */
577 static const char f32_2[] =
ccc9c027 578 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 579 static const char f32_3[] =
580 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
581 static const char f32_4[] =
582 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
583 static const char f32_5[] =
584 {0x90, /* nop */
585 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
586 static const char f32_6[] =
587 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
588 static const char f32_7[] =
589 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
590 static const char f32_8[] =
591 {0x90, /* nop */
592 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
593 static const char f32_9[] =
594 {0x89,0xf6, /* movl %esi,%esi */
595 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
596 static const char f32_10[] =
597 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
598 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
599 static const char f32_11[] =
600 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
601 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
602 static const char f32_12[] =
603 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
604 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
605 static const char f32_13[] =
606 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
607 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
608 static const char f32_14[] =
609 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
610 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
611 static const char f32_15[] =
612 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
613 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
c3332e24
AM		 614 static const char f16_3[] =
615 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 616 static const char f16_4[] =
617 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
618 static const char f16_5[] =
619 {0x90, /* nop */
620 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
621 static const char f16_6[] =
622 {0x89,0xf6, /* mov %si,%si */
623 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
624 static const char f16_7[] =
625 {0x8d,0x74,0x00, /* lea 0(%si),%si */
626 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
627 static const char f16_8[] =
628 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
629 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
630 static const char *const f32_patt[] = {
631 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
632 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
633 };
634 static const char *const f16_patt[] = {
c3332e24 635 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
252b5132
RH		 636 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
637 };
ccc9c027
L		 638 /* nopl (%[re]ax) */
639 static const char alt_3[] =
640 {0x0f,0x1f,0x00};
641 /* nopl 0(%[re]ax) */
642 static const char alt_4[] =
643 {0x0f,0x1f,0x40,0x00};
644 /* nopl 0(%[re]ax,%[re]ax,1) */
645 static const char alt_5[] =
646 {0x0f,0x1f,0x44,0x00,0x00};
647 /* nopw 0(%[re]ax,%[re]ax,1) */
648 static const char alt_6[] =
649 {0x66,0x0f,0x1f,0x44,0x00,0x00};
650 /* nopl 0L(%[re]ax) */
651 static const char alt_7[] =
652 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
653 /* nopl 0L(%[re]ax,%[re]ax,1) */
654 static const char alt_8[] =
655 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
656 /* nopw 0L(%[re]ax,%[re]ax,1) */
657 static const char alt_9[] =
658 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
659 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
660 static const char alt_10[] =
661 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
662 /* data16
663 nopw %cs:0L(%[re]ax,%[re]ax,1) */
664 static const char alt_long_11[] =
665 {0x66,
666 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
667 /* data16
668 data16
669 nopw %cs:0L(%[re]ax,%[re]ax,1) */
670 static const char alt_long_12[] =
671 {0x66,
672 0x66,
673 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
674 /* data16
675 data16
676 data16
677 nopw %cs:0L(%[re]ax,%[re]ax,1) */
678 static const char alt_long_13[] =
679 {0x66,
680 0x66,
681 0x66,
682 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
683 /* data16
684 data16
685 data16
686 data16
687 nopw %cs:0L(%[re]ax,%[re]ax,1) */
688 static const char alt_long_14[] =
689 {0x66,
690 0x66,
691 0x66,
692 0x66,
693 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
694 /* data16
695 data16
696 data16
697 data16
698 data16
699 nopw %cs:0L(%[re]ax,%[re]ax,1) */
700 static const char alt_long_15[] =
701 {0x66,
702 0x66,
703 0x66,
704 0x66,
705 0x66,
706 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
707 /* nopl 0(%[re]ax,%[re]ax,1)
708 nopw 0(%[re]ax,%[re]ax,1) */
709 static const char alt_short_11[] =
710 {0x0f,0x1f,0x44,0x00,0x00,
711 0x66,0x0f,0x1f,0x44,0x00,0x00};
712 /* nopw 0(%[re]ax,%[re]ax,1)
713 nopw 0(%[re]ax,%[re]ax,1) */
714 static const char alt_short_12[] =
715 {0x66,0x0f,0x1f,0x44,0x00,0x00,
716 0x66,0x0f,0x1f,0x44,0x00,0x00};
717 /* nopw 0(%[re]ax,%[re]ax,1)
718 nopl 0L(%[re]ax) */
719 static const char alt_short_13[] =
720 {0x66,0x0f,0x1f,0x44,0x00,0x00,
721 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
722 /* nopl 0L(%[re]ax)
723 nopl 0L(%[re]ax) */
724 static const char alt_short_14[] =
725 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
726 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
727 /* nopl 0L(%[re]ax)
728 nopl 0L(%[re]ax,%[re]ax,1) */
729 static const char alt_short_15[] =
730 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
731 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
732 static const char *const alt_short_patt[] = {
733 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
734 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
735 alt_short_14, alt_short_15
736 };
737 static const char *const alt_long_patt[] = {
738 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
739 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
740 alt_long_14, alt_long_15
741 };
252b5132 742
33fef721
JH		 743 if (count <= 0 || count > 15)
744 return;
3e73aa7c 745
ccc9c027
L		 746 /* We need to decide which NOP sequence to use for 32bit and
747 64bit. When -mtune= is used:
4eed87de 748
ccc9c027
L		 749 1. For PROCESSOR_I486, PROCESSOR_PENTIUM and PROCESSOR_GENERIC32,
750 f32_patt will be used.
4eed87de
AM		 751 2. For PROCESSOR_K8 and PROCESSOR_AMDFAM10 in 64bit, NOPs with
752 0x66 prefix will be used.
ef05d495 753 3. For PROCESSOR_CORE2, alt_long_patt will be used.
ccc9c027 754 4. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
ef05d495 755 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_K6, PROCESSOR_ATHLON
ccc9c027
L		 756 and PROCESSOR_GENERIC64, alt_short_patt will be used.
757
758 When -mtune= isn't used, alt_short_patt will be used if
759 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will be used.
760
761 When -march= or .arch is used, we can't use anything beyond
762 cpu_arch_isa_flags. */
763
764 if (flag_code == CODE_16BIT)
765 {
766 memcpy (fragP->fr_literal + fragP->fr_fix,
767 f16_patt[count - 1], count);
768 if (count > 8)
769 /* Adjust jump offset. */
770 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
771 }
772 else if (flag_code == CODE_64BIT && cpu_arch_tune == PROCESSOR_K8)
252b5132 773 {
33fef721
JH		 774 int i;
775 int nnops = (count + 3) / 4;
776 int len = count / nnops;
777 int remains = count - nnops * len;
778 int pos = 0;
779
ccc9c027 780 /* The recommended way to pad 64bit code is to use NOPs preceded
4eed87de 781 by maximally four 0x66 prefixes. Balance the size of nops. */
33fef721 782 for (i = 0; i < remains; i++)
252b5132 783 {
33fef721
JH		 784 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
785 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
786 pos += len + 1;
787 }
788 for (; i < nnops; i++)
789 {
790 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
791 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
792 pos += len;
252b5132 793 }
252b5132 794 }
33fef721 795 else
ccc9c027
L		 796 {
797 const char *const *patt = NULL;
798
799 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
800 {
801 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
802 switch (cpu_arch_tune)
803 {
804 case PROCESSOR_UNKNOWN:
805 /* We use cpu_arch_isa_flags to check if we SHOULD
806 optimize for Cpu686. */
807 if ((cpu_arch_isa_flags & Cpu686) != 0)
808 patt = alt_short_patt;
809 else
810 patt = f32_patt;
811 break;
ef05d495 812 case PROCESSOR_CORE2:
ccc9c027
L		 813 patt = alt_long_patt;
814 break;
815 case PROCESSOR_PENTIUMPRO:
816 case PROCESSOR_PENTIUM4:
817 case PROCESSOR_NOCONA:
ef05d495 818 case PROCESSOR_CORE:
ccc9c027
L		 819 case PROCESSOR_K6:
820 case PROCESSOR_ATHLON:
821 case PROCESSOR_K8:
822 case PROCESSOR_GENERIC64:
4eed87de 823 case PROCESSOR_AMDFAM10:
ccc9c027
L		 824 patt = alt_short_patt;
825 break;
826 case PROCESSOR_I486:
827 case PROCESSOR_PENTIUM:
828 case PROCESSOR_GENERIC32:
829 patt = f32_patt;
830 break;
4eed87de 831 }
ccc9c027
L		 832 }
833 else
834 {
835 switch (cpu_arch_tune)
836 {
837 case PROCESSOR_UNKNOWN:
838 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
839 PROCESSOR_UNKNOWN. */
840 abort ();
841 break;
842
843 case PROCESSOR_I486:
844 case PROCESSOR_PENTIUM:
845 case PROCESSOR_PENTIUMPRO:
846 case PROCESSOR_PENTIUM4:
847 case PROCESSOR_NOCONA:
ef05d495 848 case PROCESSOR_CORE:
ccc9c027
L		 849 case PROCESSOR_K6:
850 case PROCESSOR_ATHLON:
851 case PROCESSOR_K8:
4eed87de 852 case PROCESSOR_AMDFAM10:
ccc9c027
L		 853 case PROCESSOR_GENERIC32:
854 /* We use cpu_arch_isa_flags to check if we CAN optimize
855 for Cpu686. */
856 if ((cpu_arch_isa_flags & Cpu686) != 0)
857 patt = alt_short_patt;
858 else
859 patt = f32_patt;
860 break;
ef05d495 861 case PROCESSOR_CORE2:
ccc9c027
L		 862 if ((cpu_arch_isa_flags & Cpu686) != 0)
863 patt = alt_long_patt;
864 else
865 patt = f32_patt;
866 break;
867 case PROCESSOR_GENERIC64:
868 patt = alt_short_patt;
869 break;
4eed87de 870 }
ccc9c027
L		 871 }
872
33fef721 873 memcpy (fragP->fr_literal + fragP->fr_fix,
ccc9c027
L		 874 patt[count - 1], count);
875 }
33fef721 876 fragP->fr_var = count;
252b5132
RH		 877}
878
252b5132 879static INLINE unsigned int
e3bb37b5 880mode_from_disp_size (unsigned int t)
252b5132 881{
3e73aa7c 882 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
252b5132
RH		 883}
884
885static INLINE int
e3bb37b5 886fits_in_signed_byte (offsetT num)
252b5132
RH		 887{
888 return (num >= -128) && (num <= 127);
47926f60 889}
252b5132
RH		 890
891static INLINE int
e3bb37b5 892fits_in_unsigned_byte (offsetT num)
252b5132
RH		 893{
894 return (num & 0xff) == num;
47926f60 895}
252b5132
RH		 896
897static INLINE int
e3bb37b5 898fits_in_unsigned_word (offsetT num)
252b5132
RH		 899{
900 return (num & 0xffff) == num;
47926f60 901}
252b5132
RH		 902
903static INLINE int
e3bb37b5 904fits_in_signed_word (offsetT num)
252b5132
RH		 905{
906 return (-32768 <= num) && (num <= 32767);
47926f60 907}
2a962e6d 908
3e73aa7c 909static INLINE int
e3bb37b5 910fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 911{
912#ifndef BFD64
913 return 1;
914#else
915 return (!(((offsetT) -1 << 31) & num)
916 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
917#endif
918} /* fits_in_signed_long() */
2a962e6d 919
3e73aa7c 920static INLINE int
e3bb37b5 921fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 922{
923#ifndef BFD64
924 return 1;
925#else
926 return (num & (((offsetT) 2 << 31) - 1)) == num;
927#endif
928} /* fits_in_unsigned_long() */
252b5132 929
1509aa9a 930static unsigned int
e3bb37b5 931smallest_imm_type (offsetT num)
252b5132 932{
d32cad65 933 if (cpu_arch_flags != (Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
e413e4e9
AM		 934 {
935 /* This code is disabled on the 486 because all the Imm1 forms
936 in the opcode table are slower on the i486. They're the
937 versions with the implicitly specified single-position
938 displacement, which has another syntax if you really want to
939 use that form. */
940 if (num == 1)
3e73aa7c 941 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
e413e4e9 942 }
252b5132 943 return (fits_in_signed_byte (num)
3e73aa7c 944 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 945 : fits_in_unsigned_byte (num)
3e73aa7c 946 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 947 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
3e73aa7c
JH		 948 ? (Imm16 | Imm32 | Imm32S | Imm64)
949 : fits_in_signed_long (num)
950 ? (Imm32 | Imm32S | Imm64)
951 : fits_in_unsigned_long (num)
952 ? (Imm32 | Imm64)
953 : Imm64);
47926f60 954}
252b5132 955
847f7ad4 956static offsetT
e3bb37b5 957offset_in_range (offsetT val, int size)
847f7ad4 958{
508866be 959 addressT mask;
ba2adb93 960
847f7ad4
AM		 961 switch (size)
962 {
508866be
L		 963 case 1: mask = ((addressT) 1 << 8) - 1; break;
964 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 965 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 966#ifdef BFD64
967 case 8: mask = ((addressT) 2 << 63) - 1; break;
968#endif
47926f60 969 default: abort ();
847f7ad4
AM		 970 }
971
ba2adb93 972 /* If BFD64, sign extend val. */
3e73aa7c
JH		 973 if (!use_rela_relocations)
974 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
975 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 976
47926f60 977 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 978 {
979 char buf1[40], buf2[40];
980
981 sprint_value (buf1, val);
982 sprint_value (buf2, val & mask);
983 as_warn (_("%s shortened to %s"), buf1, buf2);
984 }
985 return val & mask;
986}
987
252b5132
RH		 988/* Returns 0 if attempting to add a prefix where one from the same
989 class already exists, 1 if non rep/repne added, 2 if rep/repne
990 added. */
991static int
e3bb37b5 992add_prefix (unsigned int prefix)
252b5132
RH		 993{
994 int ret = 1;
b1905489 995 unsigned int q;
252b5132 996
29b0f896
AM		 997 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
998 && flag_code == CODE_64BIT)
b1905489 999 {
161a04f6
L		 1000 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1001 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1002 && (prefix & (REX_R | REX_X | REX_B))))
b1905489
JB		 1003 ret = 0;
1004 q = REX_PREFIX;
1005 }
3e73aa7c 1006 else
b1905489
JB		 1007 {
1008 switch (prefix)
1009 {
1010 default:
1011 abort ();
1012
1013 case CS_PREFIX_OPCODE:
1014 case DS_PREFIX_OPCODE:
1015 case ES_PREFIX_OPCODE:
1016 case FS_PREFIX_OPCODE:
1017 case GS_PREFIX_OPCODE:
1018 case SS_PREFIX_OPCODE:
1019 q = SEG_PREFIX;
1020 break;
1021
1022 case REPNE_PREFIX_OPCODE:
1023 case REPE_PREFIX_OPCODE:
1024 ret = 2;
1025 /* fall thru */
1026 case LOCK_PREFIX_OPCODE:
1027 q = LOCKREP_PREFIX;
1028 break;
1029
1030 case FWAIT_OPCODE:
1031 q = WAIT_PREFIX;
1032 break;
1033
1034 case ADDR_PREFIX_OPCODE:
1035 q = ADDR_PREFIX;
1036 break;
1037
1038 case DATA_PREFIX_OPCODE:
1039 q = DATA_PREFIX;
1040 break;
1041 }
1042 if (i.prefix[q] != 0)
1043 ret = 0;
1044 }
252b5132 1045
b1905489 1046 if (ret)
252b5132 1047 {
b1905489
JB		 1048 if (!i.prefix[q])
1049 ++i.prefixes;
1050 i.prefix[q] |= prefix;
252b5132 1051 }
b1905489
JB		 1052 else
1053 as_bad (_("same type of prefix used twice"));
252b5132 1054
252b5132
RH		 1055 return ret;
1056}
1057
1058static void
e3bb37b5 1059set_code_flag (int value)
eecb386c 1060{
3e73aa7c
JH		 1061 flag_code = value;
1062 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1063 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
1064 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
1065 {
1066 as_bad (_("64bit mode not supported on this CPU."));
1067 }
1068 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
1069 {
1070 as_bad (_("32bit mode not supported on this CPU."));
1071 }
eecb386c
AM		 1072 stackop_size = '\0';
1073}
1074
1075static void
e3bb37b5 1076set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1077{
3e73aa7c
JH		 1078 flag_code = new_code_flag;
1079 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1080 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
9306ca4a 1081 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1082}
1083
1084static void
e3bb37b5 1085set_intel_syntax (int syntax_flag)
252b5132
RH		 1086{
1087 /* Find out if register prefixing is specified. */
1088 int ask_naked_reg = 0;
1089
1090 SKIP_WHITESPACE ();
29b0f896 1091 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1092 {
1093 char *string = input_line_pointer;
1094 int e = get_symbol_end ();
1095
47926f60 1096 if (strcmp (string, "prefix") == 0)
252b5132 1097 ask_naked_reg = 1;
47926f60 1098 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1099 ask_naked_reg = -1;
1100 else
d0b47220 1101 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1102 *input_line_pointer = e;
1103 }
1104 demand_empty_rest_of_line ();
c3332e24 1105
252b5132
RH		 1106 intel_syntax = syntax_flag;
1107
1108 if (ask_naked_reg == 0)
f86103b7
AM		 1109 allow_naked_reg = (intel_syntax
1110 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1111 else
1112 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 1113
e4a3b5a4 1114 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 1115 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 1116 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 1117}
1118
e413e4e9 1119static void
e3bb37b5 1120set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 1121{
47926f60 1122 SKIP_WHITESPACE ();
e413e4e9 1123
29b0f896 1124 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 1125 {
1126 char *string = input_line_pointer;
1127 int e = get_symbol_end ();
9103f4f4 1128 unsigned int i;
e413e4e9 1129
9103f4f4 1130 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM		 1131 {
1132 if (strcmp (string, cpu_arch[i].name) == 0)
1133 {
5c6af06e
JB		 1134 if (*string != '.')
1135 {
1136 cpu_arch_name = cpu_arch[i].name;
1137 cpu_sub_arch_name = NULL;
1138 cpu_arch_flags = (cpu_arch[i].flags
4eed87de
AM		 1139 | (flag_code == CODE_64BIT
1140 ? Cpu64 : CpuNo64));
ccc9c027 1141 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 1142 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 1143 if (!cpu_arch_tune_set)
1144 {
1145 cpu_arch_tune = cpu_arch_isa;
1146 cpu_arch_tune_flags = cpu_arch_isa_flags;
1147 }
5c6af06e
JB		 1148 break;
1149 }
1150 if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
1151 {
1152 cpu_sub_arch_name = cpu_arch[i].name;
1153 cpu_arch_flags |= cpu_arch[i].flags;
1154 }
1155 *input_line_pointer = e;
1156 demand_empty_rest_of_line ();
1157 return;
e413e4e9
AM		 1158 }
1159 }
9103f4f4 1160 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 1161 as_bad (_("no such architecture: `%s'"), string);
1162
1163 *input_line_pointer = e;
1164 }
1165 else
1166 as_bad (_("missing cpu architecture"));
1167
fddf5b5b
AM		 1168 no_cond_jump_promotion = 0;
1169 if (*input_line_pointer == ','
29b0f896 1170 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 1171 {
1172 char *string = ++input_line_pointer;
1173 int e = get_symbol_end ();
1174
1175 if (strcmp (string, "nojumps") == 0)
1176 no_cond_jump_promotion = 1;
1177 else if (strcmp (string, "jumps") == 0)
1178 ;
1179 else
1180 as_bad (_("no such architecture modifier: `%s'"), string);
1181
1182 *input_line_pointer = e;
1183 }
1184
e413e4e9
AM		 1185 demand_empty_rest_of_line ();
1186}
1187
b9d79e03
JH		 1188unsigned long
1189i386_mach ()
1190{
1191 if (!strcmp (default_arch, "x86_64"))
1192 return bfd_mach_x86_64;
1193 else if (!strcmp (default_arch, "i386"))
1194 return bfd_mach_i386_i386;
1195 else
1196 as_fatal (_("Unknown architecture"));
1197}
b9d79e03 1198\f
252b5132
RH		 1199void
1200md_begin ()
1201{
1202 const char *hash_err;
1203
47926f60 1204 /* Initialize op_hash hash table. */
252b5132
RH		 1205 op_hash = hash_new ();
1206
1207 {
29b0f896
AM		 1208 const template *optab;
1209 templates *core_optab;
252b5132 1210
47926f60
KH		 1211 /* Setup for loop. */
1212 optab = i386_optab;
252b5132
RH		 1213 core_optab = (templates *) xmalloc (sizeof (templates));
1214 core_optab->start = optab;
1215
1216 while (1)
1217 {
1218 ++optab;
1219 if (optab->name == NULL
1220 || strcmp (optab->name, (optab - 1)->name) != 0)
1221 {
1222 /* different name --> ship out current template list;
47926f60 1223 add to hash table; & begin anew. */
252b5132
RH		 1224 core_optab->end = optab;
1225 hash_err = hash_insert (op_hash,
1226 (optab - 1)->name,
1227 (PTR) core_optab);
1228 if (hash_err)
1229 {
252b5132
RH		 1230 as_fatal (_("Internal Error: Can't hash %s: %s"),
1231 (optab - 1)->name,
1232 hash_err);
1233 }
1234 if (optab->name == NULL)
1235 break;
1236 core_optab = (templates *) xmalloc (sizeof (templates));
1237 core_optab->start = optab;
1238 }
1239 }
1240 }
1241
47926f60 1242 /* Initialize reg_hash hash table. */
252b5132
RH		 1243 reg_hash = hash_new ();
1244 {
29b0f896 1245 const reg_entry *regtab;
c3fe08fa 1246 unsigned int regtab_size = i386_regtab_size;
252b5132 1247
c3fe08fa 1248 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132
RH		 1249 {
1250 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1251 if (hash_err)
3e73aa7c
JH		 1252 as_fatal (_("Internal Error: Can't hash %s: %s"),
1253 regtab->reg_name,
1254 hash_err);
252b5132
RH		 1255 }
1256 }
1257
47926f60 1258 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 1259 {
29b0f896
AM		 1260 int c;
1261 char *p;
252b5132
RH		 1262
1263 for (c = 0; c < 256; c++)
1264 {
3882b010 1265 if (ISDIGIT (c))
252b5132
RH		 1266 {
1267 digit_chars[c] = c;
1268 mnemonic_chars[c] = c;
1269 register_chars[c] = c;
1270 operand_chars[c] = c;
1271 }
3882b010 1272 else if (ISLOWER (c))
252b5132
RH		 1273 {
1274 mnemonic_chars[c] = c;
1275 register_chars[c] = c;
1276 operand_chars[c] = c;
1277 }
3882b010 1278 else if (ISUPPER (c))
252b5132 1279 {
3882b010 1280 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 1281 register_chars[c] = mnemonic_chars[c];
1282 operand_chars[c] = c;
1283 }
1284
3882b010 1285 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 1286 identifier_chars[c] = c;
1287 else if (c >= 128)
1288 {
1289 identifier_chars[c] = c;
1290 operand_chars[c] = c;
1291 }
1292 }
1293
1294#ifdef LEX_AT
1295 identifier_chars['@'] = '@';
32137342
NC		 1296#endif
1297#ifdef LEX_QM
1298 identifier_chars['?'] = '?';
1299 operand_chars['?'] = '?';
252b5132 1300#endif
252b5132 1301 digit_chars['-'] = '-';
791fe849 1302 mnemonic_chars['-'] = '-';
0003779b 1303 mnemonic_chars['.'] = '.';
252b5132
RH		 1304 identifier_chars['_'] = '_';
1305 identifier_chars['.'] = '.';
1306
1307 for (p = operand_special_chars; *p != '\0'; p++)
1308 operand_chars[(unsigned char) *p] = *p;
1309 }
1310
1311#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1312 if (IS_ELF)
252b5132
RH		 1313 {
1314 record_alignment (text_section, 2);
1315 record_alignment (data_section, 2);
1316 record_alignment (bss_section, 2);
1317 }
1318#endif
a4447b93
RH		 1319
1320 if (flag_code == CODE_64BIT)
1321 {
1322 x86_dwarf2_return_column = 16;
1323 x86_cie_data_alignment = -8;
1324 }
1325 else
1326 {
1327 x86_dwarf2_return_column = 8;
1328 x86_cie_data_alignment = -4;
1329 }
252b5132
RH		 1330}
1331
1332void
e3bb37b5 1333i386_print_statistics (FILE *file)
252b5132
RH		 1334{
1335 hash_print_statistics (file, "i386 opcode", op_hash);
1336 hash_print_statistics (file, "i386 register", reg_hash);
1337}
1338\f
252b5132
RH		 1339#ifdef DEBUG386
1340
ce8a8b2f 1341/* Debugging routines for md_assemble. */
e3bb37b5
L		 1342static void pte (template *);
1343static void pt (unsigned int);
1344static void pe (expressionS *);
1345static void ps (symbolS *);
252b5132
RH		 1346
1347static void
e3bb37b5 1348pi (char *line, i386_insn *x)
252b5132 1349{
09f131f2 1350 unsigned int i;
252b5132
RH		 1351
1352 fprintf (stdout, "%s: template ", line);
1353 pte (&x->tm);
09f131f2
JH		 1354 fprintf (stdout, " address: base %s index %s scale %x\n",
1355 x->base_reg ? x->base_reg->reg_name : "none",
1356 x->index_reg ? x->index_reg->reg_name : "none",
1357 x->log2_scale_factor);
1358 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1359 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1360 fprintf (stdout, " sib: base %x index %x scale %x\n",
1361 x->sib.base, x->sib.index, x->sib.scale);
1362 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 1363 (x->rex & REX_W) != 0,
1364 (x->rex & REX_R) != 0,
1365 (x->rex & REX_X) != 0,
1366 (x->rex & REX_B) != 0);
252b5132
RH		 1367 for (i = 0; i < x->operands; i++)
1368 {
1369 fprintf (stdout, " #%d: ", i + 1);
1370 pt (x->types[i]);
1371 fprintf (stdout, "\n");
1372 if (x->types[i]
3f4438ab 1373 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
520dc8e8 1374 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
252b5132 1375 if (x->types[i] & Imm)
520dc8e8 1376 pe (x->op[i].imms);
252b5132 1377 if (x->types[i] & Disp)
520dc8e8 1378 pe (x->op[i].disps);
252b5132
RH		 1379 }
1380}
1381
1382static void
e3bb37b5 1383pte (template *t)
252b5132 1384{
09f131f2 1385 unsigned int i;
252b5132 1386 fprintf (stdout, " %d operands ", t->operands);
47926f60 1387 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1388 if (t->extension_opcode != None)
1389 fprintf (stdout, "ext %x ", t->extension_opcode);
1390 if (t->opcode_modifier & D)
1391 fprintf (stdout, "D");
1392 if (t->opcode_modifier & W)
1393 fprintf (stdout, "W");
1394 fprintf (stdout, "\n");
1395 for (i = 0; i < t->operands; i++)
1396 {
1397 fprintf (stdout, " #%d type ", i + 1);
1398 pt (t->operand_types[i]);
1399 fprintf (stdout, "\n");
1400 }
1401}
1402
1403static void
e3bb37b5 1404pe (expressionS *e)
252b5132 1405{
24eab124 1406 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1407 fprintf (stdout, " add_number %ld (%lx)\n",
1408 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1409 if (e->X_add_symbol)
1410 {
1411 fprintf (stdout, " add_symbol ");
1412 ps (e->X_add_symbol);
1413 fprintf (stdout, "\n");
1414 }
1415 if (e->X_op_symbol)
1416 {
1417 fprintf (stdout, " op_symbol ");
1418 ps (e->X_op_symbol);
1419 fprintf (stdout, "\n");
1420 }
1421}
1422
1423static void
e3bb37b5 1424ps (symbolS *s)
252b5132
RH		 1425{
1426 fprintf (stdout, "%s type %s%s",
1427 S_GET_NAME (s),
1428 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1429 segment_name (S_GET_SEGMENT (s)));
1430}
1431
7b81dfbb 1432static struct type_name
252b5132
RH		 1433 {
1434 unsigned int mask;
1435 char *tname;
1436 }
7b81dfbb 1437const type_names[] =
252b5132
RH		 1438{
1439 { Reg8, "r8" },
1440 { Reg16, "r16" },
1441 { Reg32, "r32" },
09f131f2 1442 { Reg64, "r64" },
252b5132
RH		 1443 { Imm8, "i8" },
1444 { Imm8S, "i8s" },
1445 { Imm16, "i16" },
1446 { Imm32, "i32" },
09f131f2
JH		 1447 { Imm32S, "i32s" },
1448 { Imm64, "i64" },
252b5132
RH		 1449 { Imm1, "i1" },
1450 { BaseIndex, "BaseIndex" },
1451 { Disp8, "d8" },
1452 { Disp16, "d16" },
1453 { Disp32, "d32" },
09f131f2
JH		 1454 { Disp32S, "d32s" },
1455 { Disp64, "d64" },
252b5132
RH		 1456 { InOutPortReg, "InOutPortReg" },
1457 { ShiftCount, "ShiftCount" },
1458 { Control, "control reg" },
1459 { Test, "test reg" },
1460 { Debug, "debug reg" },
1461 { FloatReg, "FReg" },
1462 { FloatAcc, "FAcc" },
1463 { SReg2, "SReg2" },
1464 { SReg3, "SReg3" },
1465 { Acc, "Acc" },
1466 { JumpAbsolute, "Jump Absolute" },
1467 { RegMMX, "rMMX" },
3f4438ab 1468 { RegXMM, "rXMM" },
252b5132
RH		 1469 { EsSeg, "es" },
1470 { 0, "" }
1471};
1472
1473static void
1474pt (t)
1475 unsigned int t;
1476{
29b0f896 1477 const struct type_name *ty;
252b5132 1478
09f131f2
JH		 1479 for (ty = type_names; ty->mask; ty++)
1480 if (t & ty->mask)
1481 fprintf (stdout, "%s, ", ty->tname);
252b5132
RH		 1482 fflush (stdout);
1483}
1484
1485#endif /* DEBUG386 */
1486\f
252b5132 1487static bfd_reloc_code_real_type
3956db08 1488reloc (unsigned int size,
64e74474
AM		 1489 int pcrel,
1490 int sign,
1491 bfd_reloc_code_real_type other)
252b5132 1492{
47926f60 1493 if (other != NO_RELOC)
3956db08
JB		 1494 {
1495 reloc_howto_type *reloc;
1496
1497 if (size == 8)
1498 switch (other)
1499 {
64e74474
AM		 1500 case BFD_RELOC_X86_64_GOT32:
1501 return BFD_RELOC_X86_64_GOT64;
1502 break;
1503 case BFD_RELOC_X86_64_PLTOFF64:
1504 return BFD_RELOC_X86_64_PLTOFF64;
1505 break;
1506 case BFD_RELOC_X86_64_GOTPC32:
1507 other = BFD_RELOC_X86_64_GOTPC64;
1508 break;
1509 case BFD_RELOC_X86_64_GOTPCREL:
1510 other = BFD_RELOC_X86_64_GOTPCREL64;
1511 break;
1512 case BFD_RELOC_X86_64_TPOFF32:
1513 other = BFD_RELOC_X86_64_TPOFF64;
1514 break;
1515 case BFD_RELOC_X86_64_DTPOFF32:
1516 other = BFD_RELOC_X86_64_DTPOFF64;
1517 break;
1518 default:
1519 break;
3956db08 1520 }
e05278af
JB		 1521
1522 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1523 if (size == 4 && flag_code != CODE_64BIT)
1524 sign = -1;
1525
3956db08
JB		 1526 reloc = bfd_reloc_type_lookup (stdoutput, other);
1527 if (!reloc)
1528 as_bad (_("unknown relocation (%u)"), other);
1529 else if (size != bfd_get_reloc_size (reloc))
1530 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1531 bfd_get_reloc_size (reloc),
1532 size);
1533 else if (pcrel && !reloc->pc_relative)
1534 as_bad (_("non-pc-relative relocation for pc-relative field"));
1535 else if ((reloc->complain_on_overflow == complain_overflow_signed
1536 && !sign)
1537 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 1538 && sign > 0))
3956db08
JB		 1539 as_bad (_("relocated field and relocation type differ in signedness"));
1540 else
1541 return other;
1542 return NO_RELOC;
1543 }
252b5132
RH		 1544
1545 if (pcrel)
1546 {
3e73aa7c 1547 if (!sign)
3956db08 1548 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 1549 switch (size)
1550 {
1551 case 1: return BFD_RELOC_8_PCREL;
1552 case 2: return BFD_RELOC_16_PCREL;
1553 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 1554 case 8: return BFD_RELOC_64_PCREL;
252b5132 1555 }
3956db08 1556 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 1557 }
1558 else
1559 {
3956db08 1560 if (sign > 0)
e5cb08ac 1561 switch (size)
3e73aa7c
JH		 1562 {
1563 case 4: return BFD_RELOC_X86_64_32S;
1564 }
1565 else
1566 switch (size)
1567 {
1568 case 1: return BFD_RELOC_8;
1569 case 2: return BFD_RELOC_16;
1570 case 4: return BFD_RELOC_32;
1571 case 8: return BFD_RELOC_64;
1572 }
3956db08
JB		 1573 as_bad (_("cannot do %s %u byte relocation"),
1574 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 1575 }
1576
bfb32b52 1577 abort ();
252b5132
RH		 1578 return BFD_RELOC_NONE;
1579}
1580
47926f60
KH		 1581/* Here we decide which fixups can be adjusted to make them relative to
1582 the beginning of the section instead of the symbol. Basically we need
1583 to make sure that the dynamic relocations are done correctly, so in
1584 some cases we force the original symbol to be used. */
1585
252b5132 1586int
e3bb37b5 1587tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 1588{
6d249963 1589#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1590 if (!IS_ELF)
31312f95
AM		 1591 return 1;
1592
a161fe53
AM		 1593 /* Don't adjust pc-relative references to merge sections in 64-bit
1594 mode. */
1595 if (use_rela_relocations
1596 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1597 && fixP->fx_pcrel)
252b5132 1598 return 0;
31312f95 1599
8d01d9a9
AJ		 1600 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1601 and changed later by validate_fix. */
1602 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
1603 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
1604 return 0;
1605
ce8a8b2f 1606 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1607 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1608 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1609 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 1610 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1611 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1612 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1613 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 1614 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1615 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 1616 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1617 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 1618 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
1619 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 1620 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1621 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 1622 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 1623 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1624 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1625 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 1626 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 1627 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1628 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 1629 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
1630 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 1631 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
1632 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 1633 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1634 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1635 return 0;
31312f95 1636#endif
252b5132
RH		 1637 return 1;
1638}
252b5132 1639
b4cac588 1640static int
e3bb37b5 1641intel_float_operand (const char *mnemonic)
252b5132 1642{
9306ca4a
JB		 1643 /* Note that the value returned is meaningful only for opcodes with (memory)
1644 operands, hence the code here is free to improperly handle opcodes that
1645 have no operands (for better performance and smaller code). */
1646
1647 if (mnemonic[0] != 'f')
1648 return 0; /* non-math */
1649
1650 switch (mnemonic[1])
1651 {
1652 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1653 the fs segment override prefix not currently handled because no
1654 call path can make opcodes without operands get here */
1655 case 'i':
1656 return 2 /* integer op */;
1657 case 'l':
1658 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
1659 return 3; /* fldcw/fldenv */
1660 break;
1661 case 'n':
1662 if (mnemonic[2] != 'o' /* fnop */)
1663 return 3; /* non-waiting control op */
1664 break;
1665 case 'r':
1666 if (mnemonic[2] == 's')
1667 return 3; /* frstor/frstpm */
1668 break;
1669 case 's':
1670 if (mnemonic[2] == 'a')
1671 return 3; /* fsave */
1672 if (mnemonic[2] == 't')
1673 {
1674 switch (mnemonic[3])
1675 {
1676 case 'c': /* fstcw */
1677 case 'd': /* fstdw */
1678 case 'e': /* fstenv */
1679 case 's': /* fsts[gw] */
1680 return 3;
1681 }
1682 }
1683 break;
1684 case 'x':
1685 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
1686 return 0; /* fxsave/fxrstor are not really math ops */
1687 break;
1688 }
252b5132 1689
9306ca4a 1690 return 1;
252b5132
RH		 1691}
1692
1693/* This is the guts of the machine-dependent assembler. LINE points to a
1694 machine dependent instruction. This function is supposed to emit
1695 the frags/bytes it assembles to. */
1696
1697void
1698md_assemble (line)
1699 char *line;
1700{
252b5132 1701 int j;
252b5132
RH		 1702 char mnemonic[MAX_MNEM_SIZE];
1703
47926f60 1704 /* Initialize globals. */
252b5132
RH		 1705 memset (&i, '\0', sizeof (i));
1706 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 1707 i.reloc[j] = NO_RELOC;
252b5132
RH		 1708 memset (disp_expressions, '\0', sizeof (disp_expressions));
1709 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 1710 save_stack_p = save_stack;
252b5132
RH		 1711
1712 /* First parse an instruction mnemonic & call i386_operand for the operands.
1713 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 1714 start of a (possibly prefixed) mnemonic. */
252b5132 1715
29b0f896
AM		 1716 line = parse_insn (line, mnemonic);
1717 if (line == NULL)
1718 return;
252b5132 1719
29b0f896
AM		 1720 line = parse_operands (line, mnemonic);
1721 if (line == NULL)
1722 return;
252b5132 1723
4eed87de 1724 /* The order of the immediates should be reversed
050dfa73 1725 for 2 immediates extrq and insertq instructions */
4d456e3d
L		 1726 if ((i.imm_operands == 2)
1727 && ((strcmp (mnemonic, "extrq") == 0)
1728 || (strcmp (mnemonic, "insertq") == 0)))
050dfa73 1729 {
4eed87de
AM		 1730 swap_2_operands (0, 1);
1731 /* "extrq" and insertq" are the only two instructions whose operands
050dfa73
MM		 1732 have to be reversed even though they have two immediate operands.
1733 */
1734 if (intel_syntax)
1735 swap_operands ();
1736 }
1737
29b0f896
AM		 1738 /* Now we've parsed the mnemonic into a set of templates, and have the
1739 operands at hand. */
1740
1741 /* All intel opcodes have reversed operands except for "bound" and
1742 "enter". We also don't reverse intersegment "jmp" and "call"
1743 instructions with 2 immediate operands so that the immediate segment
050dfa73 1744 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 1745 if (intel_syntax
1746 && i.operands > 1
29b0f896 1747 && (strcmp (mnemonic, "bound") != 0)
30123838 1748 && (strcmp (mnemonic, "invlpga") != 0)
29b0f896
AM		 1749 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1750 swap_operands ();
1751
1752 if (i.imm_operands)
1753 optimize_imm ();
1754
b300c311
L		 1755 /* Don't optimize displacement for movabs since it only takes 64bit
1756 displacement. */
1757 if (i.disp_operands
1758 && (flag_code != CODE_64BIT
1759 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 1760 optimize_disp ();
1761
1762 /* Next, we find a template that matches the given insn,
1763 making sure the overlap of the given operands types is consistent
1764 with the template operand types. */
252b5132 1765
29b0f896
AM		 1766 if (!match_template ())
1767 return;
252b5132 1768
cd61ebfe
AM		 1769 if (intel_syntax)
1770 {
1771 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1772 if (SYSV386_COMPAT
1773 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
8a2ed489 1774 i.tm.base_opcode ^= Opcode_FloatR;
cd61ebfe
AM		 1775
1776 /* Zap movzx and movsx suffix. The suffix may have been set from
1777 "word ptr" or "byte ptr" on the source operand, but we'll use
1778 the suffix later to choose the destination register. */
1779 if ((i.tm.base_opcode & ~9) == 0x0fb6)
9306ca4a
JB		 1780 {
1781 if (i.reg_operands < 2
1782 && !i.suffix
1783 && (~i.tm.opcode_modifier
1784 & (No_bSuf
1785 | No_wSuf
1786 | No_lSuf
1787 | No_sSuf
1788 | No_xSuf
1789 | No_qSuf)))
1790 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
1791
1792 i.suffix = 0;
1793 }
cd61ebfe 1794 }
24eab124 1795
29b0f896
AM		 1796 if (i.tm.opcode_modifier & FWait)
1797 if (!add_prefix (FWAIT_OPCODE))
1798 return;
252b5132 1799
29b0f896
AM		 1800 /* Check string instruction segment overrides. */
1801 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1802 {
1803 if (!check_string ())
5dd0794d 1804 return;
29b0f896 1805 }
5dd0794d 1806
29b0f896
AM		 1807 if (!process_suffix ())
1808 return;
e413e4e9 1809
29b0f896
AM		 1810 /* Make still unresolved immediate matches conform to size of immediate
1811 given in i.suffix. */
1812 if (!finalize_imm ())
1813 return;
252b5132 1814
29b0f896
AM		 1815 if (i.types[0] & Imm1)
1816 i.imm_operands = 0; /* kludge for shift insns. */
1817 if (i.types[0] & ImplicitRegister)
1818 i.reg_operands--;
1819 if (i.types[1] & ImplicitRegister)
1820 i.reg_operands--;
1821 if (i.types[2] & ImplicitRegister)
1822 i.reg_operands--;
252b5132 1823
29b0f896
AM		 1824 if (i.tm.opcode_modifier & ImmExt)
1825 {
02fc3089
L		 1826 expressionS *exp;
1827
b7d9ef37 1828 if ((i.tm.cpu_flags & CpuSSE3) && i.operands > 0)
ca164297 1829 {
b7d9ef37 1830 /* Streaming SIMD extensions 3 Instructions have the fixed
ca164297
L		 1831 operands with an opcode suffix which is coded in the same
1832 place as an 8-bit immediate field would be. Here we check
1833 those operands and remove them afterwards. */
1834 unsigned int x;
1835
a4622f40 1836 for (x = 0; x < i.operands; x++)
ca164297
L		 1837 if (i.op[x].regs->reg_num != x)
1838 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
64e74474 1839 i.op[x].regs->reg_name, x + 1, i.tm.name);
ca164297
L		 1840 i.operands = 0;
1841 }
1842
29b0f896
AM		 1843 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1844 opcode suffix which is coded in the same place as an 8-bit
1845 immediate field would be. Here we fake an 8-bit immediate
1846 operand from the opcode suffix stored in tm.extension_opcode. */
252b5132 1847
29b0f896 1848 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
252b5132 1849
29b0f896
AM		 1850 exp = &im_expressions[i.imm_operands++];
1851 i.op[i.operands].imms = exp;
1852 i.types[i.operands++] = Imm8;
1853 exp->X_op = O_constant;
1854 exp->X_add_number = i.tm.extension_opcode;
1855 i.tm.extension_opcode = None;
1856 }
252b5132 1857
29b0f896
AM		 1858 /* For insns with operands there are more diddles to do to the opcode. */
1859 if (i.operands)
1860 {
1861 if (!process_operands ())
1862 return;
1863 }
1864 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1865 {
1866 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1867 as_warn (_("translating to `%sp'"), i.tm.name);
1868 }
252b5132 1869
29b0f896
AM		 1870 /* Handle conversion of 'int $3' --> special int3 insn. */
1871 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1872 {
1873 i.tm.base_opcode = INT3_OPCODE;
1874 i.imm_operands = 0;
1875 }
252b5132 1876
29b0f896
AM		 1877 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1878 && i.op[0].disps->X_op == O_constant)
1879 {
1880 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1881 the absolute address given by the constant. Since ix86 jumps and
1882 calls are pc relative, we need to generate a reloc. */
1883 i.op[0].disps->X_add_symbol = &abs_symbol;
1884 i.op[0].disps->X_op = O_symbol;
1885 }
252b5132 1886
29b0f896 1887 if ((i.tm.opcode_modifier & Rex64) != 0)
161a04f6 1888 i.rex |= REX_W;
252b5132 1889
29b0f896
AM		 1890 /* For 8 bit registers we need an empty rex prefix. Also if the
1891 instruction already has a prefix, we need to convert old
1892 registers to new ones. */
773f551c 1893
29b0f896
AM		 1894 if (((i.types[0] & Reg8) != 0
1895 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1896 || ((i.types[1] & Reg8) != 0
1897 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1898 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1899 && i.rex != 0))
1900 {
1901 int x;
726c5dcd 1902
29b0f896
AM		 1903 i.rex |= REX_OPCODE;
1904 for (x = 0; x < 2; x++)
1905 {
1906 /* Look for 8 bit operand that uses old registers. */
1907 if ((i.types[x] & Reg8) != 0
1908 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 1909 {
29b0f896
AM		 1910 /* In case it is "hi" register, give up. */
1911 if (i.op[x].regs->reg_num > 3)
4eed87de
AM		 1912 as_bad (_("can't encode register '%%%s' in an "
1913 "instruction requiring REX prefix."),
29b0f896 1914 i.op[x].regs->reg_name);
773f551c 1915
29b0f896
AM		 1916 /* Otherwise it is equivalent to the extended register.
1917 Since the encoding doesn't change this is merely
1918 cosmetic cleanup for debug output. */
1919
1920 i.op[x].regs = i.op[x].regs + 8;
773f551c 1921 }
29b0f896
AM		 1922 }
1923 }
773f551c 1924
29b0f896
AM		 1925 if (i.rex != 0)
1926 add_prefix (REX_OPCODE | i.rex);
1927
1928 /* We are ready to output the insn. */
1929 output_insn ();
1930}
1931
1932static char *
e3bb37b5 1933parse_insn (char *line, char *mnemonic)
29b0f896
AM		 1934{
1935 char *l = line;
1936 char *token_start = l;
1937 char *mnem_p;
5c6af06e
JB		 1938 int supported;
1939 const template *t;
29b0f896
AM		 1940
1941 /* Non-zero if we found a prefix only acceptable with string insns. */
1942 const char *expecting_string_instruction = NULL;
45288df1 1943
29b0f896
AM		 1944 while (1)
1945 {
1946 mnem_p = mnemonic;
1947 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1948 {
1949 mnem_p++;
1950 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 1951 {
29b0f896
AM		 1952 as_bad (_("no such instruction: `%s'"), token_start);
1953 return NULL;
1954 }
1955 l++;
1956 }
1957 if (!is_space_char (*l)
1958 && *l != END_OF_INSN
e44823cf
JB		 1959 && (intel_syntax
1960 || (*l != PREFIX_SEPARATOR
1961 && *l != ',')))
29b0f896
AM		 1962 {
1963 as_bad (_("invalid character %s in mnemonic"),
1964 output_invalid (*l));
1965 return NULL;
1966 }
1967 if (token_start == l)
1968 {
e44823cf 1969 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 1970 as_bad (_("expecting prefix; got nothing"));
1971 else
1972 as_bad (_("expecting mnemonic; got nothing"));
1973 return NULL;
1974 }
45288df1 1975
29b0f896
AM		 1976 /* Look up instruction (or prefix) via hash table. */
1977 current_templates = hash_find (op_hash, mnemonic);
47926f60 1978
29b0f896
AM		 1979 if (*l != END_OF_INSN
1980 && (!is_space_char (*l) || l[1] != END_OF_INSN)
1981 && current_templates
1982 && (current_templates->start->opcode_modifier & IsPrefix))
1983 {
2dd88dca
JB		 1984 if (current_templates->start->cpu_flags
1985 & (flag_code != CODE_64BIT ? Cpu64 : CpuNo64))
1986 {
1987 as_bad ((flag_code != CODE_64BIT
1988 ? _("`%s' is only supported in 64-bit mode")
1989 : _("`%s' is not supported in 64-bit mode")),
1990 current_templates->start->name);
1991 return NULL;
1992 }
29b0f896
AM		 1993 /* If we are in 16-bit mode, do not allow addr16 or data16.
1994 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1995 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1996 && flag_code != CODE_64BIT
1997 && (((current_templates->start->opcode_modifier & Size32) != 0)
1998 ^ (flag_code == CODE_16BIT)))
1999 {
2000 as_bad (_("redundant %s prefix"),
2001 current_templates->start->name);
2002 return NULL;
45288df1 2003 }
29b0f896
AM		 2004 /* Add prefix, checking for repeated prefixes. */
2005 switch (add_prefix (current_templates->start->base_opcode))
2006 {
2007 case 0:
2008 return NULL;
2009 case 2:
2010 expecting_string_instruction = current_templates->start->name;
2011 break;
2012 }
2013 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2014 token_start = ++l;
2015 }
2016 else
2017 break;
2018 }
45288df1 2019
29b0f896
AM		 2020 if (!current_templates)
2021 {
2022 /* See if we can get a match by trimming off a suffix. */
2023 switch (mnem_p[-1])
2024 {
2025 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 2026 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2027 i.suffix = SHORT_MNEM_SUFFIX;
2028 else
29b0f896
AM		 2029 case BYTE_MNEM_SUFFIX:
2030 case QWORD_MNEM_SUFFIX:
2031 i.suffix = mnem_p[-1];
2032 mnem_p[-1] = '\0';
2033 current_templates = hash_find (op_hash, mnemonic);
2034 break;
2035 case SHORT_MNEM_SUFFIX:
2036 case LONG_MNEM_SUFFIX:
2037 if (!intel_syntax)
2038 {
2039 i.suffix = mnem_p[-1];
2040 mnem_p[-1] = '\0';
2041 current_templates = hash_find (op_hash, mnemonic);
2042 }
2043 break;
252b5132 2044
29b0f896
AM		 2045 /* Intel Syntax. */
2046 case 'd':
2047 if (intel_syntax)
2048 {
9306ca4a 2049 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 2050 i.suffix = SHORT_MNEM_SUFFIX;
2051 else
2052 i.suffix = LONG_MNEM_SUFFIX;
2053 mnem_p[-1] = '\0';
2054 current_templates = hash_find (op_hash, mnemonic);
2055 }
2056 break;
2057 }
2058 if (!current_templates)
2059 {
2060 as_bad (_("no such instruction: `%s'"), token_start);
2061 return NULL;
2062 }
2063 }
252b5132 2064
29b0f896
AM		 2065 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
2066 {
2067 /* Check for a branch hint. We allow ",pt" and ",pn" for
2068 predict taken and predict not taken respectively.
2069 I'm not sure that branch hints actually do anything on loop
2070 and jcxz insns (JumpByte) for current Pentium4 chips. They
2071 may work in the future and it doesn't hurt to accept them
2072 now. */
2073 if (l[0] == ',' && l[1] == 'p')
2074 {
2075 if (l[2] == 't')
2076 {
2077 if (!add_prefix (DS_PREFIX_OPCODE))
2078 return NULL;
2079 l += 3;
2080 }
2081 else if (l[2] == 'n')
2082 {
2083 if (!add_prefix (CS_PREFIX_OPCODE))
2084 return NULL;
2085 l += 3;
2086 }
2087 }
2088 }
2089 /* Any other comma loses. */
2090 if (*l == ',')
2091 {
2092 as_bad (_("invalid character %s in mnemonic"),
2093 output_invalid (*l));
2094 return NULL;
2095 }
252b5132 2096
29b0f896 2097 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 2098 supported = 0;
2099 for (t = current_templates->start; t < current_templates->end; ++t)
2100 {
2101 if (!((t->cpu_flags & ~(Cpu64 | CpuNo64))
2102 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))))
64e74474 2103 supported |= 1;
5c6af06e 2104 if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64)))
64e74474 2105 supported |= 2;
5c6af06e
JB		 2106 }
2107 if (!(supported & 2))
2108 {
2109 as_bad (flag_code == CODE_64BIT
2110 ? _("`%s' is not supported in 64-bit mode")
2111 : _("`%s' is only supported in 64-bit mode"),
2112 current_templates->start->name);
2113 return NULL;
2114 }
2115 if (!(supported & 1))
29b0f896 2116 {
5c6af06e
JB		 2117 as_warn (_("`%s' is not supported on `%s%s'"),
2118 current_templates->start->name,
2119 cpu_arch_name,
2120 cpu_sub_arch_name ? cpu_sub_arch_name : "");
29b0f896
AM		 2121 }
2122 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
2123 {
2124 as_warn (_("use .code16 to ensure correct addressing mode"));
2125 }
252b5132 2126
29b0f896 2127 /* Check for rep/repne without a string instruction. */
f41bbced 2128 if (expecting_string_instruction)
29b0f896 2129 {
f41bbced
JB		 2130 static templates override;
2131
2132 for (t = current_templates->start; t < current_templates->end; ++t)
2133 if (t->opcode_modifier & IsString)
2134 break;
2135 if (t >= current_templates->end)
2136 {
2137 as_bad (_("expecting string instruction after `%s'"),
64e74474 2138 expecting_string_instruction);
f41bbced
JB		 2139 return NULL;
2140 }
2141 for (override.start = t; t < current_templates->end; ++t)
2142 if (!(t->opcode_modifier & IsString))
2143 break;
2144 override.end = t;
2145 current_templates = &override;
29b0f896 2146 }
252b5132 2147
29b0f896
AM		 2148 return l;
2149}
252b5132 2150
29b0f896 2151static char *
e3bb37b5 2152parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 2153{
2154 char *token_start;
3138f287 2155
29b0f896
AM		 2156 /* 1 if operand is pending after ','. */
2157 unsigned int expecting_operand = 0;
252b5132 2158
29b0f896
AM		 2159 /* Non-zero if operand parens not balanced. */
2160 unsigned int paren_not_balanced;
2161
2162 while (*l != END_OF_INSN)
2163 {
2164 /* Skip optional white space before operand. */
2165 if (is_space_char (*l))
2166 ++l;
2167 if (!is_operand_char (*l) && *l != END_OF_INSN)
2168 {
2169 as_bad (_("invalid character %s before operand %d"),
2170 output_invalid (*l),
2171 i.operands + 1);
2172 return NULL;
2173 }
2174 token_start = l; /* after white space */
2175 paren_not_balanced = 0;
2176 while (paren_not_balanced || *l != ',')
2177 {
2178 if (*l == END_OF_INSN)
2179 {
2180 if (paren_not_balanced)
2181 {
2182 if (!intel_syntax)
2183 as_bad (_("unbalanced parenthesis in operand %d."),
2184 i.operands + 1);
2185 else
2186 as_bad (_("unbalanced brackets in operand %d."),
2187 i.operands + 1);
2188 return NULL;
2189 }
2190 else
2191 break; /* we are done */
2192 }
2193 else if (!is_operand_char (*l) && !is_space_char (*l))
2194 {
2195 as_bad (_("invalid character %s in operand %d"),
2196 output_invalid (*l),
2197 i.operands + 1);
2198 return NULL;
2199 }
2200 if (!intel_syntax)
2201 {
2202 if (*l == '(')
2203 ++paren_not_balanced;
2204 if (*l == ')')
2205 --paren_not_balanced;
2206 }
2207 else
2208 {
2209 if (*l == '[')
2210 ++paren_not_balanced;
2211 if (*l == ']')
2212 --paren_not_balanced;
2213 }
2214 l++;
2215 }
2216 if (l != token_start)
2217 { /* Yes, we've read in another operand. */
2218 unsigned int operand_ok;
2219 this_operand = i.operands++;
2220 if (i.operands > MAX_OPERANDS)
2221 {
2222 as_bad (_("spurious operands; (%d operands/instruction max)"),
2223 MAX_OPERANDS);
2224 return NULL;
2225 }
2226 /* Now parse operand adding info to 'i' as we go along. */
2227 END_STRING_AND_SAVE (l);
2228
2229 if (intel_syntax)
2230 operand_ok =
2231 i386_intel_operand (token_start,
2232 intel_float_operand (mnemonic));
2233 else
2234 operand_ok = i386_operand (token_start);
2235
2236 RESTORE_END_STRING (l);
2237 if (!operand_ok)
2238 return NULL;
2239 }
2240 else
2241 {
2242 if (expecting_operand)
2243 {
2244 expecting_operand_after_comma:
2245 as_bad (_("expecting operand after ','; got nothing"));
2246 return NULL;
2247 }
2248 if (*l == ',')
2249 {
2250 as_bad (_("expecting operand before ','; got nothing"));
2251 return NULL;
2252 }
2253 }
7f3f1ea2 2254
29b0f896
AM		 2255 /* Now *l must be either ',' or END_OF_INSN. */
2256 if (*l == ',')
2257 {
2258 if (*++l == END_OF_INSN)
2259 {
2260 /* Just skip it, if it's \n complain. */
2261 goto expecting_operand_after_comma;
2262 }
2263 expecting_operand = 1;
2264 }
2265 }
2266 return l;
2267}
7f3f1ea2 2268
050dfa73 2269static void
4d456e3d 2270swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 2271{
2272 union i386_op temp_op;
2273 unsigned int temp_type;
2274 enum bfd_reloc_code_real temp_reloc;
4eed87de 2275
050dfa73
MM		 2276 temp_type = i.types[xchg2];
2277 i.types[xchg2] = i.types[xchg1];
2278 i.types[xchg1] = temp_type;
2279 temp_op = i.op[xchg2];
2280 i.op[xchg2] = i.op[xchg1];
2281 i.op[xchg1] = temp_op;
2282 temp_reloc = i.reloc[xchg2];
2283 i.reloc[xchg2] = i.reloc[xchg1];
2284 i.reloc[xchg1] = temp_reloc;
2285}
2286
29b0f896 2287static void
e3bb37b5 2288swap_operands (void)
29b0f896 2289{
b7c61d9a 2290 switch (i.operands)
050dfa73 2291 {
b7c61d9a 2292 case 4:
4d456e3d 2293 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 2294 case 3:
2295 case 2:
4d456e3d 2296 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 2297 break;
2298 default:
2299 abort ();
29b0f896 2300 }
29b0f896
AM		 2301
2302 if (i.mem_operands == 2)
2303 {
2304 const seg_entry *temp_seg;
2305 temp_seg = i.seg[0];
2306 i.seg[0] = i.seg[1];
2307 i.seg[1] = temp_seg;
2308 }
2309}
252b5132 2310
29b0f896
AM		 2311/* Try to ensure constant immediates are represented in the smallest
2312 opcode possible. */
2313static void
e3bb37b5 2314optimize_imm (void)
29b0f896
AM		 2315{
2316 char guess_suffix = 0;
2317 int op;
252b5132 2318
29b0f896
AM		 2319 if (i.suffix)
2320 guess_suffix = i.suffix;
2321 else if (i.reg_operands)
2322 {
2323 /* Figure out a suffix from the last register operand specified.
2324 We can't do this properly yet, ie. excluding InOutPortReg,
2325 but the following works for instructions with immediates.
2326 In any case, we can't set i.suffix yet. */
2327 for (op = i.operands; --op >= 0;)
2328 if (i.types[op] & Reg)
252b5132 2329 {
29b0f896
AM		 2330 if (i.types[op] & Reg8)
2331 guess_suffix = BYTE_MNEM_SUFFIX;
2332 else if (i.types[op] & Reg16)
2333 guess_suffix = WORD_MNEM_SUFFIX;
2334 else if (i.types[op] & Reg32)
2335 guess_suffix = LONG_MNEM_SUFFIX;
2336 else if (i.types[op] & Reg64)
2337 guess_suffix = QWORD_MNEM_SUFFIX;
2338 break;
252b5132 2339 }
29b0f896
AM		 2340 }
2341 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2342 guess_suffix = WORD_MNEM_SUFFIX;
2343
2344 for (op = i.operands; --op >= 0;)
2345 if (i.types[op] & Imm)
2346 {
2347 switch (i.op[op].imms->X_op)
252b5132 2348 {
29b0f896
AM		 2349 case O_constant:
2350 /* If a suffix is given, this operand may be shortened. */
2351 switch (guess_suffix)
252b5132 2352 {
29b0f896
AM		 2353 case LONG_MNEM_SUFFIX:
2354 i.types[op] |= Imm32 | Imm64;
2355 break;
2356 case WORD_MNEM_SUFFIX:
2357 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
2358 break;
2359 case BYTE_MNEM_SUFFIX:
2360 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
2361 break;
252b5132 2362 }
252b5132 2363
29b0f896
AM		 2364 /* If this operand is at most 16 bits, convert it
2365 to a signed 16 bit number before trying to see
2366 whether it will fit in an even smaller size.
2367 This allows a 16-bit operand such as $0xffe0 to
2368 be recognised as within Imm8S range. */
2369 if ((i.types[op] & Imm16)
2370 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 2371 {
29b0f896
AM		 2372 i.op[op].imms->X_add_number =
2373 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2374 }
2375 if ((i.types[op] & Imm32)
2376 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2377 == 0))
2378 {
2379 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2380 ^ ((offsetT) 1 << 31))
2381 - ((offsetT) 1 << 31));
2382 }
2383 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
252b5132 2384
29b0f896
AM		 2385 /* We must avoid matching of Imm32 templates when 64bit
2386 only immediate is available. */
2387 if (guess_suffix == QWORD_MNEM_SUFFIX)
2388 i.types[op] &= ~Imm32;
2389 break;
252b5132 2390
29b0f896
AM		 2391 case O_absent:
2392 case O_register:
2393 abort ();
2394
2395 /* Symbols and expressions. */
2396 default:
9cd96992
JB		 2397 /* Convert symbolic operand to proper sizes for matching, but don't
2398 prevent matching a set of insns that only supports sizes other
2399 than those matching the insn suffix. */
2400 {
2401 unsigned int mask, allowed = 0;
2402 const template *t;
2403
4eed87de
AM		 2404 for (t = current_templates->start;
2405 t < current_templates->end;
2406 ++t)
2407 allowed |= t->operand_types[op];
9cd96992
JB		 2408 switch (guess_suffix)
2409 {
2410 case QWORD_MNEM_SUFFIX:
2411 mask = Imm64 | Imm32S;
2412 break;
2413 case LONG_MNEM_SUFFIX:
2414 mask = Imm32;
2415 break;
2416 case WORD_MNEM_SUFFIX:
2417 mask = Imm16;
2418 break;
2419 case BYTE_MNEM_SUFFIX:
2420 mask = Imm8;
2421 break;
2422 default:
2423 mask = 0;
2424 break;
2425 }
64e74474
AM		 2426 if (mask & allowed)
2427 i.types[op] &= mask;
9cd96992 2428 }
29b0f896 2429 break;
252b5132 2430 }
29b0f896
AM		 2431 }
2432}
47926f60 2433
29b0f896
AM		 2434/* Try to use the smallest displacement type too. */
2435static void
e3bb37b5 2436optimize_disp (void)
29b0f896
AM		 2437{
2438 int op;
3e73aa7c 2439
29b0f896 2440 for (op = i.operands; --op >= 0;)
b300c311 2441 if (i.types[op] & Disp)
252b5132 2442 {
b300c311 2443 if (i.op[op].disps->X_op == O_constant)
252b5132 2444 {
b300c311 2445 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 2446
b300c311
L		 2447 if ((i.types[op] & Disp16)
2448 && (disp & ~(offsetT) 0xffff) == 0)
2449 {
2450 /* If this operand is at most 16 bits, convert
2451 to a signed 16 bit number and don't use 64bit
2452 displacement. */
2453 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
2454 i.types[op] &= ~Disp64;
2455 }
2456 if ((i.types[op] & Disp32)
2457 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2458 {
2459 /* If this operand is at most 32 bits, convert
2460 to a signed 32 bit number and don't use 64bit
2461 displacement. */
2462 disp &= (((offsetT) 2 << 31) - 1);
2463 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
2464 i.types[op] &= ~Disp64;
2465 }
2466 if (!disp && (i.types[op] & BaseIndex))
2467 {
2468 i.types[op] &= ~Disp;
2469 i.op[op].disps = 0;
2470 i.disp_operands--;
2471 }
2472 else if (flag_code == CODE_64BIT)
2473 {
2474 if (fits_in_signed_long (disp))
28a9d8f5
L		 2475 {
2476 i.types[op] &= ~Disp64;
2477 i.types[op] |= Disp32S;
2478 }
b300c311
L		 2479 if (fits_in_unsigned_long (disp))
2480 i.types[op] |= Disp32;
2481 }
2482 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
2483 && fits_in_signed_byte (disp))
2484 i.types[op] |= Disp8;
252b5132 2485 }
67a4f2b7
AO		 2486 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
2487 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
2488 {
2489 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
2490 i.op[op].disps, 0, i.reloc[op]);
2491 i.types[op] &= ~Disp;
2492 }
2493 else
b300c311
L		 2494 /* We only support 64bit displacement on constants. */
2495 i.types[op] &= ~Disp64;
252b5132 2496 }
29b0f896
AM		 2497}
2498
2499static int
e3bb37b5 2500match_template (void)
29b0f896
AM		 2501{
2502 /* Points to template once we've found it. */
2503 const template *t;
f48ff2ae 2504 unsigned int overlap0, overlap1, overlap2, overlap3;
29b0f896
AM		 2505 unsigned int found_reverse_match;
2506 int suffix_check;
f48ff2ae 2507 unsigned int operand_types [MAX_OPERANDS];
539e75ad 2508 int addr_prefix_disp;
a5c311ca 2509 unsigned int j;
29b0f896 2510
f48ff2ae
L		 2511#if MAX_OPERANDS != 4
2512# error "MAX_OPERANDS must be 4."
2513#endif
2514
29b0f896
AM		 2515#define MATCH(overlap, given, template) \
2516 ((overlap & ~JumpAbsolute) \
2517 && (((given) & (BaseIndex | JumpAbsolute)) \
2518 == ((overlap) & (BaseIndex | JumpAbsolute))))
2519
2520 /* If given types r0 and r1 are registers they must be of the same type
2521 unless the expected operand type register overlap is null.
2522 Note that Acc in a template matches every size of reg. */
2523#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2524 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2525 || ((g0) & Reg) == ((g1) & Reg) \
2526 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2527
2528 overlap0 = 0;
2529 overlap1 = 0;
2530 overlap2 = 0;
f48ff2ae 2531 overlap3 = 0;
29b0f896 2532 found_reverse_match = 0;
a5c311ca
L		 2533 for (j = 0; j < MAX_OPERANDS; j++)
2534 operand_types [j] = 0;
539e75ad 2535 addr_prefix_disp = -1;
29b0f896
AM		 2536 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
2537 ? No_bSuf
2538 : (i.suffix == WORD_MNEM_SUFFIX
2539 ? No_wSuf
2540 : (i.suffix == SHORT_MNEM_SUFFIX
2541 ? No_sSuf
2542 : (i.suffix == LONG_MNEM_SUFFIX
2543 ? No_lSuf
2544 : (i.suffix == QWORD_MNEM_SUFFIX
2545 ? No_qSuf
2546 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
2547 ? No_xSuf : 0))))));
2548
45aa61fe 2549 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 2550 {
539e75ad
L		 2551 addr_prefix_disp = -1;
2552
29b0f896
AM		 2553 /* Must have right number of operands. */
2554 if (i.operands != t->operands)
2555 continue;
2556
2557 /* Check the suffix, except for some instructions in intel mode. */
2558 if ((t->opcode_modifier & suffix_check)
2559 && !(intel_syntax
9306ca4a 2560 && (t->opcode_modifier & IgnoreSize)))
29b0f896
AM		 2561 continue;
2562
a5c311ca
L		 2563 for (j = 0; j < MAX_OPERANDS; j++)
2564 operand_types [j] = t->operand_types [j];
539e75ad 2565
45aa61fe
AM		 2566 /* In general, don't allow 64-bit operands in 32-bit mode. */
2567 if (i.suffix == QWORD_MNEM_SUFFIX
2568 && flag_code != CODE_64BIT
2569 && (intel_syntax
2570 ? (!(t->opcode_modifier & IgnoreSize)
2571 && !intel_float_operand (t->name))
2572 : intel_float_operand (t->name) != 2)
539e75ad
L		 2573 && (!(operand_types[0] & (RegMMX | RegXMM))
2574 || !(operand_types[t->operands > 1] & (RegMMX | RegXMM)))
45aa61fe
AM		 2575 && (t->base_opcode != 0x0fc7
2576 || t->extension_opcode != 1 /* cmpxchg8b */))
2577 continue;
2578
29b0f896
AM		 2579 /* Do not verify operands when there are none. */
2580 else if (!t->operands)
2581 {
2582 if (t->cpu_flags & ~cpu_arch_flags)
2583 continue;
2584 /* We've found a match; break out of loop. */
2585 break;
2586 }
252b5132 2587
539e75ad
L		 2588 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
2589 into Disp32/Disp16/Disp32 operand. */
2590 if (i.prefix[ADDR_PREFIX] != 0)
2591 {
a5c311ca 2592 unsigned int DispOn = 0, DispOff = 0;
539e75ad
L		 2593
2594 switch (flag_code)
2595 {
2596 case CODE_16BIT:
2597 DispOn = Disp32;
2598 DispOff = Disp16;
2599 break;
2600 case CODE_32BIT:
2601 DispOn = Disp16;
2602 DispOff = Disp32;
2603 break;
2604 case CODE_64BIT:
2605 DispOn = Disp32;
2606 DispOff = Disp64;
2607 break;
2608 }
2609
f48ff2ae 2610 for (j = 0; j < MAX_OPERANDS; j++)
539e75ad
L		 2611 {
2612 /* There should be only one Disp operand. */
2613 if ((operand_types[j] & DispOff))
2614 {
2615 addr_prefix_disp = j;
2616 operand_types[j] |= DispOn;
2617 operand_types[j] &= ~DispOff;
2618 break;
2619 }
2620 }
2621 }
2622
2623 overlap0 = i.types[0] & operand_types[0];
29b0f896
AM		 2624 switch (t->operands)
2625 {
2626 case 1:
539e75ad 2627 if (!MATCH (overlap0, i.types[0], operand_types[0]))
29b0f896
AM		 2628 continue;
2629 break;
2630 case 2:
8b38ad71
L		 2631 /* xchg %eax, %eax is a special case. It is an aliase for nop
2632 only in 32bit mode and we can use opcode 0x90. In 64bit
2633 mode, we can't use 0x90 for xchg %eax, %eax since it should
2634 zero-extend %eax to %rax. */
2635 if (flag_code == CODE_64BIT
2636 && t->base_opcode == 0x90
2637 && i.types [0] == (Acc | Reg32)
2638 && i.types [1] == (Acc | Reg32))
2639 continue;
29b0f896 2640 case 3:
f48ff2ae 2641 case 4:
539e75ad
L		 2642 overlap1 = i.types[1] & operand_types[1];
2643 if (!MATCH (overlap0, i.types[0], operand_types[0])
2644 || !MATCH (overlap1, i.types[1], operand_types[1])
cb712a9e 2645 /* monitor in SSE3 is a very special case. The first
708587a4 2646 register and the second register may have different
381d071f 2647 sizes. The same applies to crc32 in SSE4.2. */
cb712a9e
L		 2648 || !((t->base_opcode == 0x0f01
2649 && t->extension_opcode == 0xc8)
381d071f 2650 || t->base_opcode == 0xf20f38f1
cb712a9e 2651 || CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
539e75ad 2652 operand_types[0],
cb712a9e 2653 overlap1, i.types[1],
539e75ad 2654 operand_types[1])))
29b0f896
AM		 2655 {
2656 /* Check if other direction is valid ... */
2657 if ((t->opcode_modifier & (D | FloatD)) == 0)
2658 continue;
2659
2660 /* Try reversing direction of operands. */
539e75ad
L		 2661 overlap0 = i.types[0] & operand_types[1];
2662 overlap1 = i.types[1] & operand_types[0];
2663 if (!MATCH (overlap0, i.types[0], operand_types[1])
2664 || !MATCH (overlap1, i.types[1], operand_types[0])
29b0f896 2665 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
539e75ad 2666 operand_types[1],
29b0f896 2667 overlap1, i.types[1],
539e75ad 2668 operand_types[0]))
29b0f896
AM		 2669 {
2670 /* Does not match either direction. */
2671 continue;
2672 }
2673 /* found_reverse_match holds which of D or FloatDR
2674 we've found. */
8a2ed489
L		 2675 if ((t->opcode_modifier & D))
2676 found_reverse_match = Opcode_D;
2677 else if ((t->opcode_modifier & FloatD))
2678 found_reverse_match = Opcode_FloatD;
2679 else
2680 found_reverse_match = 0;
2681 if ((t->opcode_modifier & FloatR))
2682 found_reverse_match |= Opcode_FloatR;
29b0f896 2683 }
f48ff2ae 2684 else
29b0f896 2685 {
f48ff2ae 2686 /* Found a forward 2 operand match here. */
d1cbb4db
L		 2687 switch (t->operands)
2688 {
2689 case 4:
2690 overlap3 = i.types[3] & operand_types[3];
2691 case 3:
2692 overlap2 = i.types[2] & operand_types[2];
2693 break;
2694 }
29b0f896 2695
f48ff2ae
L		 2696 switch (t->operands)
2697 {
2698 case 4:
2699 if (!MATCH (overlap3, i.types[3], operand_types[3])
2700 || !CONSISTENT_REGISTER_MATCH (overlap2,
2701 i.types[2],
2702 operand_types[2],
2703 overlap3,
2704 i.types[3],
2705 operand_types[3]))
2706 continue;
2707 case 3:
2708 /* Here we make use of the fact that there are no
2709 reverse match 3 operand instructions, and all 3
2710 operand instructions only need to be checked for
2711 register consistency between operands 2 and 3. */
2712 if (!MATCH (overlap2, i.types[2], operand_types[2])
2713 || !CONSISTENT_REGISTER_MATCH (overlap1,
2714 i.types[1],
2715 operand_types[1],
2716 overlap2,
2717 i.types[2],
2718 operand_types[2]))
2719 continue;
2720 break;
2721 }
29b0f896 2722 }
f48ff2ae 2723 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 2724 slip through to break. */
2725 }
2726 if (t->cpu_flags & ~cpu_arch_flags)
2727 {
2728 found_reverse_match = 0;
2729 continue;
2730 }
2731 /* We've found a match; break out of loop. */
2732 break;
2733 }
2734
2735 if (t == current_templates->end)
2736 {
2737 /* We found no match. */
2738 as_bad (_("suffix or operands invalid for `%s'"),
2739 current_templates->start->name);
2740 return 0;
2741 }
252b5132 2742
29b0f896
AM		 2743 if (!quiet_warnings)
2744 {
2745 if (!intel_syntax
2746 && ((i.types[0] & JumpAbsolute)
539e75ad 2747 != (operand_types[0] & JumpAbsolute)))
29b0f896
AM		 2748 {
2749 as_warn (_("indirect %s without `*'"), t->name);
2750 }
2751
2752 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2753 == (IsPrefix | IgnoreSize))
2754 {
2755 /* Warn them that a data or address size prefix doesn't
2756 affect assembly of the next line of code. */
2757 as_warn (_("stand-alone `%s' prefix"), t->name);
2758 }
2759 }
2760
2761 /* Copy the template we found. */
2762 i.tm = *t;
539e75ad
L		 2763
2764 if (addr_prefix_disp != -1)
2765 i.tm.operand_types[addr_prefix_disp]
2766 = operand_types[addr_prefix_disp];
2767
29b0f896
AM		 2768 if (found_reverse_match)
2769 {
2770 /* If we found a reverse match we must alter the opcode
2771 direction bit. found_reverse_match holds bits to change
2772 (different for int & float insns). */
2773
2774 i.tm.base_opcode ^= found_reverse_match;
2775
539e75ad
L		 2776 i.tm.operand_types[0] = operand_types[1];
2777 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 2778 }
2779
2780 return 1;
2781}
2782
2783static int
e3bb37b5 2784check_string (void)
29b0f896
AM		 2785{
2786 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2787 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2788 {
2789 if (i.seg[0] != NULL && i.seg[0] != &es)
2790 {
2791 as_bad (_("`%s' operand %d must use `%%es' segment"),
2792 i.tm.name,
2793 mem_op + 1);
2794 return 0;
2795 }
2796 /* There's only ever one segment override allowed per instruction.
2797 This instruction possibly has a legal segment override on the
2798 second operand, so copy the segment to where non-string
2799 instructions store it, allowing common code. */
2800 i.seg[0] = i.seg[1];
2801 }
2802 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2803 {
2804 if (i.seg[1] != NULL && i.seg[1] != &es)
2805 {
2806 as_bad (_("`%s' operand %d must use `%%es' segment"),
2807 i.tm.name,
2808 mem_op + 2);
2809 return 0;
2810 }
2811 }
2812 return 1;
2813}
2814
2815static int
543613e9 2816process_suffix (void)
29b0f896
AM		 2817{
2818 /* If matched instruction specifies an explicit instruction mnemonic
2819 suffix, use it. */
2820 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2821 {
2822 if (i.tm.opcode_modifier & Size16)
2823 i.suffix = WORD_MNEM_SUFFIX;
2824 else if (i.tm.opcode_modifier & Size64)
2825 i.suffix = QWORD_MNEM_SUFFIX;
2826 else
2827 i.suffix = LONG_MNEM_SUFFIX;
2828 }
2829 else if (i.reg_operands)
2830 {
2831 /* If there's no instruction mnemonic suffix we try to invent one
2832 based on register operands. */
2833 if (!i.suffix)
2834 {
2835 /* We take i.suffix from the last register operand specified,
2836 Destination register type is more significant than source
381d071f
L		 2837 register type. crc32 in SSE4.2 prefers source register
2838 type. */
2839 if (i.tm.base_opcode == 0xf20f38f1)
2840 {
2841 if ((i.types[0] & Reg))
2842 i.suffix = ((i.types[0] & Reg16) ? WORD_MNEM_SUFFIX :
29b0f896 2843 LONG_MNEM_SUFFIX);
381d071f
L		 2844 }
2845
2846 if (!i.suffix)
2847 {
2848 int op;
2849
2850 for (op = i.operands; --op >= 0;)
2851 if ((i.types[op] & Reg)
2852 && !(i.tm.operand_types[op] & InOutPortReg))
2853 {
2854 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2855 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2856 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2857 LONG_MNEM_SUFFIX);
2858 break;
2859 }
2860 }
29b0f896
AM		 2861 }
2862 else if (i.suffix == BYTE_MNEM_SUFFIX)
2863 {
2864 if (!check_byte_reg ())
2865 return 0;
2866 }
2867 else if (i.suffix == LONG_MNEM_SUFFIX)
2868 {
2869 if (!check_long_reg ())
2870 return 0;
2871 }
2872 else if (i.suffix == QWORD_MNEM_SUFFIX)
2873 {
2874 if (!check_qword_reg ())
2875 return 0;
2876 }
2877 else if (i.suffix == WORD_MNEM_SUFFIX)
2878 {
2879 if (!check_word_reg ())
2880 return 0;
2881 }
2882 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2883 /* Do nothing if the instruction is going to ignore the prefix. */
2884 ;
2885 else
2886 abort ();
2887 }
9306ca4a
JB		 2888 else if ((i.tm.opcode_modifier & DefaultSize)
2889 && !i.suffix
2890 /* exclude fldenv/frstor/fsave/fstenv */
2891 && (i.tm.opcode_modifier & No_sSuf))
29b0f896
AM		 2892 {
2893 i.suffix = stackop_size;
2894 }
9306ca4a
JB		 2895 else if (intel_syntax
2896 && !i.suffix
2897 && ((i.tm.operand_types[0] & JumpAbsolute)
64e74474
AM		 2898 || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
2899 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
2900 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 2901 {
2902 switch (flag_code)
2903 {
2904 case CODE_64BIT:
2905 if (!(i.tm.opcode_modifier & No_qSuf))
2906 {
2907 i.suffix = QWORD_MNEM_SUFFIX;
2908 break;
2909 }
2910 case CODE_32BIT:
2911 if (!(i.tm.opcode_modifier & No_lSuf))
2912 i.suffix = LONG_MNEM_SUFFIX;
2913 break;
2914 case CODE_16BIT:
2915 if (!(i.tm.opcode_modifier & No_wSuf))
2916 i.suffix = WORD_MNEM_SUFFIX;
2917 break;
2918 }
2919 }
252b5132 2920
9306ca4a 2921 if (!i.suffix)
29b0f896 2922 {
9306ca4a
JB		 2923 if (!intel_syntax)
2924 {
2925 if (i.tm.opcode_modifier & W)
2926 {
4eed87de
AM		 2927 as_bad (_("no instruction mnemonic suffix given and "
2928 "no register operands; can't size instruction"));
9306ca4a
JB		 2929 return 0;
2930 }
2931 }
2932 else
2933 {
64e74474
AM		 2934 unsigned int suffixes = (~i.tm.opcode_modifier
2935 & (No_bSuf
2936 | No_wSuf
2937 | No_lSuf
2938 | No_sSuf
2939 | No_xSuf
2940 | No_qSuf));
9306ca4a
JB		 2941
2942 if ((i.tm.opcode_modifier & W)
2943 || ((suffixes & (suffixes - 1))
2944 && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize))))
2945 {
2946 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2947 return 0;
2948 }
2949 }
29b0f896 2950 }
252b5132 2951
9306ca4a
JB		 2952 /* Change the opcode based on the operand size given by i.suffix;
2953 We don't need to change things for byte insns. */
2954
29b0f896
AM		 2955 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2956 {
2957 /* It's not a byte, select word/dword operation. */
2958 if (i.tm.opcode_modifier & W)
2959 {
2960 if (i.tm.opcode_modifier & ShortForm)
2961 i.tm.base_opcode |= 8;
2962 else
2963 i.tm.base_opcode |= 1;
2964 }
0f3f3d8b 2965
29b0f896
AM		 2966 /* Now select between word & dword operations via the operand
2967 size prefix, except for instructions that will ignore this
2968 prefix anyway. */
cb712a9e
L		 2969 if (i.tm.base_opcode == 0x0f01 && i.tm.extension_opcode == 0xc8)
2970 {
2971 /* monitor in SSE3 is a very special case. The default size
2972 of AX is the size of mode. The address size override
2973 prefix will change the size of AX. */
2974 if (i.op->regs[0].reg_type &
2975 (flag_code == CODE_32BIT ? Reg16 : Reg32))
2976 if (!add_prefix (ADDR_PREFIX_OPCODE))
2977 return 0;
2978 }
2979 else if (i.suffix != QWORD_MNEM_SUFFIX
2980 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
2981 && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF))
2982 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2983 || (flag_code == CODE_64BIT
2984 && (i.tm.opcode_modifier & JumpByte))))
24eab124
AM		 2985 {
2986 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 2987
29b0f896
AM		 2988 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2989 prefix = ADDR_PREFIX_OPCODE;
252b5132 2990
29b0f896
AM		 2991 if (!add_prefix (prefix))
2992 return 0;
24eab124 2993 }
252b5132 2994
29b0f896
AM		 2995 /* Set mode64 for an operand. */
2996 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 2997 && flag_code == CODE_64BIT
29b0f896 2998 && (i.tm.opcode_modifier & NoRex64) == 0)
46e883c5
L		 2999 {
3000 /* Special case for xchg %rax,%rax. It is NOP and doesn't
3001 need rex64. */
3002 if (i.operands != 2
3003 || i.types [0] != (Acc | Reg64)
3004 || i.types [1] != (Acc | Reg64)
13a1e313 3005 || i.tm.base_opcode != 0x90)
f6bee062 3006 i.rex |= REX_W;
46e883c5 3007 }
3e73aa7c 3008
29b0f896
AM		 3009 /* Size floating point instruction. */
3010 if (i.suffix == LONG_MNEM_SUFFIX)
543613e9
NC		 3011 if (i.tm.opcode_modifier & FloatMF)
3012 i.tm.base_opcode ^= 4;
29b0f896 3013 }
7ecd2f8b 3014
29b0f896
AM		 3015 return 1;
3016}
3e73aa7c 3017
29b0f896 3018static int
543613e9 3019check_byte_reg (void)
29b0f896
AM		 3020{
3021 int op;
543613e9 3022
29b0f896
AM		 3023 for (op = i.operands; --op >= 0;)
3024 {
3025 /* If this is an eight bit register, it's OK. If it's the 16 or
3026 32 bit version of an eight bit register, we will just use the
3027 low portion, and that's OK too. */
3028 if (i.types[op] & Reg8)
3029 continue;
3030
3031 /* movzx and movsx should not generate this warning. */
3032 if (intel_syntax
3033 && (i.tm.base_opcode == 0xfb7
3034 || i.tm.base_opcode == 0xfb6
3035 || i.tm.base_opcode == 0x63
3036 || i.tm.base_opcode == 0xfbe
3037 || i.tm.base_opcode == 0xfbf))
3038 continue;
3039
65ec77d2 3040 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
29b0f896
AM		 3041 {
3042 /* Prohibit these changes in the 64bit mode, since the
3043 lowering is more complicated. */
3044 if (flag_code == CODE_64BIT
3045 && (i.tm.operand_types[op] & InOutPortReg) == 0)
3046 {
2ca3ace5
L		 3047 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3048 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3049 i.suffix);
3050 return 0;
3051 }
3052#if REGISTER_WARNINGS
3053 if (!quiet_warnings
3054 && (i.tm.operand_types[op] & InOutPortReg) == 0)
3055 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3056 (i.op[op].regs + (i.types[op] & Reg16
3057 ? REGNAM_AL - REGNAM_AX
3058 : REGNAM_AL - REGNAM_EAX))->reg_name,
3059 i.op[op].regs->reg_name,
3060 i.suffix);
3061#endif
3062 continue;
3063 }
3064 /* Any other register is bad. */
3065 if (i.types[op] & (Reg | RegMMX | RegXMM
3066 | SReg2 | SReg3
3067 | Control | Debug | Test
3068 | FloatReg | FloatAcc))
3069 {
3070 as_bad (_("`%%%s' not allowed with `%s%c'"),
3071 i.op[op].regs->reg_name,
3072 i.tm.name,
3073 i.suffix);
3074 return 0;
3075 }
3076 }
3077 return 1;
3078}
3079
3080static int
e3bb37b5 3081check_long_reg (void)
29b0f896
AM		 3082{
3083 int op;
3084
3085 for (op = i.operands; --op >= 0;)
3086 /* Reject eight bit registers, except where the template requires
3087 them. (eg. movzb) */
3088 if ((i.types[op] & Reg8) != 0
3089 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3090 {
3091 as_bad (_("`%%%s' not allowed with `%s%c'"),
3092 i.op[op].regs->reg_name,
3093 i.tm.name,
3094 i.suffix);
3095 return 0;
3096 }
3097 /* Warn if the e prefix on a general reg is missing. */
3098 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3099 && (i.types[op] & Reg16) != 0
3100 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3101 {
3102 /* Prohibit these changes in the 64bit mode, since the
3103 lowering is more complicated. */
3104 if (flag_code == CODE_64BIT)
252b5132 3105 {
2ca3ace5
L		 3106 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3107 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3108 i.suffix);
3109 return 0;
252b5132 3110 }
29b0f896
AM		 3111#if REGISTER_WARNINGS
3112 else
3113 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3114 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
3115 i.op[op].regs->reg_name,
3116 i.suffix);
3117#endif
252b5132 3118 }
29b0f896
AM		 3119 /* Warn if the r prefix on a general reg is missing. */
3120 else if ((i.types[op] & Reg64) != 0
3121 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
252b5132 3122 {
2ca3ace5
L		 3123 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3124 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3125 i.suffix);
3126 return 0;
3127 }
3128 return 1;
3129}
252b5132 3130
29b0f896 3131static int
e3bb37b5 3132check_qword_reg (void)
29b0f896
AM		 3133{
3134 int op;
252b5132 3135
29b0f896
AM		 3136 for (op = i.operands; --op >= 0; )
3137 /* Reject eight bit registers, except where the template requires
3138 them. (eg. movzb) */
3139 if ((i.types[op] & Reg8) != 0
3140 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3141 {
3142 as_bad (_("`%%%s' not allowed with `%s%c'"),
3143 i.op[op].regs->reg_name,
3144 i.tm.name,
3145 i.suffix);
3146 return 0;
3147 }
3148 /* Warn if the e prefix on a general reg is missing. */
3149 else if (((i.types[op] & Reg16) != 0
3150 || (i.types[op] & Reg32) != 0)
3151 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3152 {
3153 /* Prohibit these changes in the 64bit mode, since the
3154 lowering is more complicated. */
2ca3ace5
L		 3155 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3156 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3157 i.suffix);
3158 return 0;
252b5132 3159 }
29b0f896
AM		 3160 return 1;
3161}
252b5132 3162
29b0f896 3163static int
e3bb37b5 3164check_word_reg (void)
29b0f896
AM		 3165{
3166 int op;
3167 for (op = i.operands; --op >= 0;)
3168 /* Reject eight bit registers, except where the template requires
3169 them. (eg. movzb) */
3170 if ((i.types[op] & Reg8) != 0
3171 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3172 {
3173 as_bad (_("`%%%s' not allowed with `%s%c'"),
3174 i.op[op].regs->reg_name,
3175 i.tm.name,
3176 i.suffix);
3177 return 0;
3178 }
3179 /* Warn if the e prefix on a general reg is present. */
3180 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3181 && (i.types[op] & Reg32) != 0
3182 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
252b5132 3183 {
29b0f896
AM		 3184 /* Prohibit these changes in the 64bit mode, since the
3185 lowering is more complicated. */
3186 if (flag_code == CODE_64BIT)
252b5132 3187 {
2ca3ace5
L		 3188 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3189 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3190 i.suffix);
3191 return 0;
252b5132 3192 }
29b0f896
AM		 3193 else
3194#if REGISTER_WARNINGS
3195 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3196 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
3197 i.op[op].regs->reg_name,
3198 i.suffix);
3199#endif
3200 }
3201 return 1;
3202}
252b5132 3203
29b0f896 3204static int
e3bb37b5 3205finalize_imm (void)
29b0f896
AM		 3206{
3207 unsigned int overlap0, overlap1, overlap2;
3208
3209 overlap0 = i.types[0] & i.tm.operand_types[0];
20f0a1fc 3210 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64))
29b0f896
AM		 3211 && overlap0 != Imm8 && overlap0 != Imm8S
3212 && overlap0 != Imm16 && overlap0 != Imm32S
3213 && overlap0 != Imm32 && overlap0 != Imm64)
3214 {
3215 if (i.suffix)
3216 {
3217 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
3218 ? Imm8 | Imm8S
3219 : (i.suffix == WORD_MNEM_SUFFIX
3220 ? Imm16
3221 : (i.suffix == QWORD_MNEM_SUFFIX
3222 ? Imm64 | Imm32S
3223 : Imm32)));
3224 }
3225 else if (overlap0 == (Imm16 | Imm32S | Imm32)
3226 || overlap0 == (Imm16 | Imm32)
3227 || overlap0 == (Imm16 | Imm32S))
3228 {
3229 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3230 ? Imm16 : Imm32S);
3231 }
3232 if (overlap0 != Imm8 && overlap0 != Imm8S
3233 && overlap0 != Imm16 && overlap0 != Imm32S
3234 && overlap0 != Imm32 && overlap0 != Imm64)
3235 {
4eed87de
AM		 3236 as_bad (_("no instruction mnemonic suffix given; "
3237 "can't determine immediate size"));
29b0f896
AM		 3238 return 0;
3239 }
3240 }
3241 i.types[0] = overlap0;
3242
3243 overlap1 = i.types[1] & i.tm.operand_types[1];
37edbb65 3244 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64))
29b0f896
AM		 3245 && overlap1 != Imm8 && overlap1 != Imm8S
3246 && overlap1 != Imm16 && overlap1 != Imm32S
3247 && overlap1 != Imm32 && overlap1 != Imm64)
3248 {
3249 if (i.suffix)
3250 {
3251 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
3252 ? Imm8 | Imm8S
3253 : (i.suffix == WORD_MNEM_SUFFIX
3254 ? Imm16
3255 : (i.suffix == QWORD_MNEM_SUFFIX
3256 ? Imm64 | Imm32S
3257 : Imm32)));
3258 }
3259 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
3260 || overlap1 == (Imm16 | Imm32)
3261 || overlap1 == (Imm16 | Imm32S))
3262 {
3263 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3264 ? Imm16 : Imm32S);
3265 }
3266 if (overlap1 != Imm8 && overlap1 != Imm8S
3267 && overlap1 != Imm16 && overlap1 != Imm32S
3268 && overlap1 != Imm32 && overlap1 != Imm64)
3269 {
4eed87de
AM		 3270 as_bad (_("no instruction mnemonic suffix given; "
3271 "can't determine immediate size %x %c"),
3272 overlap1, i.suffix);
29b0f896
AM		 3273 return 0;
3274 }
3275 }
3276 i.types[1] = overlap1;
3277
3278 overlap2 = i.types[2] & i.tm.operand_types[2];
3279 assert ((overlap2 & Imm) == 0);
3280 i.types[2] = overlap2;
3281
3282 return 1;
3283}
3284
3285static int
e3bb37b5 3286process_operands (void)
29b0f896
AM		 3287{
3288 /* Default segment register this instruction will use for memory
3289 accesses. 0 means unknown. This is only for optimizing out
3290 unnecessary segment overrides. */
3291 const seg_entry *default_seg = 0;
3292
3293 /* The imul $imm, %reg instruction is converted into
3294 imul $imm, %reg, %reg, and the clr %reg instruction
3295 is converted into xor %reg, %reg. */
3296 if (i.tm.opcode_modifier & regKludge)
3297 {
42903f7f
L		 3298 if ((i.tm.cpu_flags & CpuSSE4_1))
3299 {
3300 /* The first operand in instruction blendvpd, blendvps and
3301 pblendvb in SSE4.1 is implicit and must be xmm0. */
3302 assert (i.operands == 3
3303 && i.reg_operands >= 2
3304 && i.types[0] == RegXMM);
3305 if (i.op[0].regs->reg_num != 0)
3306 {
3307 if (intel_syntax)
3308 as_bad (_("the last operand of `%s' must be `%sxmm0'"),
3309 i.tm.name, register_prefix);
3310 else
3311 as_bad (_("the first operand of `%s' must be `%sxmm0'"),
3312 i.tm.name, register_prefix);
3313 return 0;
3314 }
3315 i.op[0] = i.op[1];
3316 i.op[1] = i.op[2];
3317 i.types[0] = i.types[1];
3318 i.types[1] = i.types[2];
3319 i.operands--;
3320 i.reg_operands--;
3321
3322 /* We need to adjust fields in i.tm since they are used by
3323 build_modrm_byte. */
3324 i.tm.operand_types [0] = i.tm.operand_types [1];
3325 i.tm.operand_types [1] = i.tm.operand_types [2];
3326 i.tm.operands--;
3327 }
3328 else
3329 {
3330 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
3331 /* Pretend we saw the extra register operand. */
3332 assert (i.reg_operands == 1
3333 && i.op[first_reg_op + 1].regs == 0);
3334 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
3335 i.types[first_reg_op + 1] = i.types[first_reg_op];
3336 i.operands++;
3337 i.reg_operands++;
3338 }
29b0f896
AM		 3339 }
3340
3341 if (i.tm.opcode_modifier & ShortForm)
3342 {
4eed87de 3343 if (i.types[0] & (SReg2 | SReg3))
29b0f896 3344 {
4eed87de
AM		 3345 if (i.tm.base_opcode == POP_SEG_SHORT
3346 && i.op[0].regs->reg_num == 1)
29b0f896 3347 {
4eed87de
AM		 3348 as_bad (_("you can't `pop %%cs'"));
3349 return 0;
29b0f896 3350 }
4eed87de
AM		 3351 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
3352 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 3353 i.rex |= REX_B;
4eed87de
AM		 3354 }
3355 else
3356 {
3357 /* The register or float register operand is in operand 0 or 1. */
3358 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
3359 /* Register goes in low 3 bits of opcode. */
3360 i.tm.base_opcode |= i.op[op].regs->reg_num;
3361 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 3362 i.rex |= REX_B;
4eed87de 3363 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
29b0f896 3364 {
4eed87de
AM		 3365 /* Warn about some common errors, but press on regardless.
3366 The first case can be generated by gcc (<= 2.8.1). */
3367 if (i.operands == 2)
3368 {
3369 /* Reversed arguments on faddp, fsubp, etc. */
3370 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
3371 i.op[1].regs->reg_name,
3372 i.op[0].regs->reg_name);
3373 }
3374 else
3375 {
3376 /* Extraneous `l' suffix on fp insn. */
3377 as_warn (_("translating to `%s %%%s'"), i.tm.name,
3378 i.op[0].regs->reg_name);
3379 }
29b0f896
AM		 3380 }
3381 }
3382 }
3383 else if (i.tm.opcode_modifier & Modrm)
3384 {
3385 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 3386 must be put into the modrm byte). Now, we make the modrm and
3387 index base bytes based on all the info we've collected. */
29b0f896
AM		 3388
3389 default_seg = build_modrm_byte ();
3390 }
8a2ed489 3391 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 3392 {
3393 default_seg = &ds;
3394 }
3395 else if ((i.tm.opcode_modifier & IsString) != 0)
3396 {
3397 /* For the string instructions that allow a segment override
3398 on one of their operands, the default segment is ds. */
3399 default_seg = &ds;
3400 }
3401
30123838
JB		 3402 if ((i.tm.base_opcode == 0x8d /* lea */
3403 || (i.tm.cpu_flags & CpuSVME))
3404 && i.seg[0] && !quiet_warnings)
3405 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 3406
3407 /* If a segment was explicitly specified, and the specified segment
3408 is not the default, use an opcode prefix to select it. If we
3409 never figured out what the default segment is, then default_seg
3410 will be zero at this point, and the specified segment prefix will
3411 always be used. */
29b0f896
AM		 3412 if ((i.seg[0]) && (i.seg[0] != default_seg))
3413 {
3414 if (!add_prefix (i.seg[0]->seg_prefix))
3415 return 0;
3416 }
3417 return 1;
3418}
3419
3420static const seg_entry *
e3bb37b5 3421build_modrm_byte (void)
29b0f896
AM		 3422{
3423 const seg_entry *default_seg = 0;
3424
3425 /* i.reg_operands MUST be the number of real register operands;
3426 implicit registers do not count. */
3427 if (i.reg_operands == 2)
3428 {
3429 unsigned int source, dest;
cab737b9
L		 3430
3431 switch (i.operands)
3432 {
3433 case 2:
3434 source = 0;
3435 break;
3436 case 3:
c81128dc
L		 3437 /* When there are 3 operands, one of them may be immediate,
3438 which may be the first or the last operand. Otherwise,
3439 the first operand must be shift count register (cl). */
3440 assert (i.imm_operands == 1
3441 || (i.imm_operands == 0
3442 && (i.types[0] & ShiftCount)));
3443 source = (i.types[0] & (Imm | ShiftCount)) ? 1 : 0;
cab737b9
L		 3444 break;
3445 case 4:
3446 /* When there are 4 operands, the first two must be immediate
3447 operands. The source operand will be the 3rd one. */
3448 assert (i.imm_operands == 2
3449 && (i.types[0] & Imm)
3450 && (i.types[1] & Imm));
3451 source = 2;
3452 break;
3453 default:
3454 abort ();
3455 }
3456
29b0f896
AM		 3457 dest = source + 1;
3458
3459 i.rm.mode = 3;
3460 /* One of the register operands will be encoded in the i.tm.reg
3461 field, the other in the combined i.tm.mode and i.tm.regmem
3462 fields. If no form of this instruction supports a memory
3463 destination operand, then we assume the source operand may
3464 sometimes be a memory operand and so we need to store the
3465 destination in the i.rm.reg field. */
e72cf3ec 3466 if ((i.tm.operand_types[dest] & (AnyMem | RegMem)) == 0)
29b0f896
AM		 3467 {
3468 i.rm.reg = i.op[dest].regs->reg_num;
3469 i.rm.regmem = i.op[source].regs->reg_num;
3470 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 3471 i.rex |= REX_R;
29b0f896 3472 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 3473 i.rex |= REX_B;
29b0f896
AM		 3474 }
3475 else
3476 {
3477 i.rm.reg = i.op[source].regs->reg_num;
3478 i.rm.regmem = i.op[dest].regs->reg_num;
3479 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 3480 i.rex |= REX_B;
29b0f896 3481 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 3482 i.rex |= REX_R;
29b0f896 3483 }
161a04f6 3484 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5
JB		 3485 {
3486 if (!((i.types[0] | i.types[1]) & Control))
3487 abort ();
161a04f6 3488 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 3489 add_prefix (LOCK_PREFIX_OPCODE);
3490 }
29b0f896
AM		 3491 }
3492 else
3493 { /* If it's not 2 reg operands... */
3494 if (i.mem_operands)
3495 {
3496 unsigned int fake_zero_displacement = 0;
99018f42 3497 unsigned int op;
4eed87de 3498
99018f42
L		 3499 for (op = 0; op < i.operands; op++)
3500 if ((i.types[op] & AnyMem))
3501 break;
3502 assert (op < i.operands);
29b0f896
AM		 3503
3504 default_seg = &ds;
3505
3506 if (i.base_reg == 0)
3507 {
3508 i.rm.mode = 0;
3509 if (!i.disp_operands)
3510 fake_zero_displacement = 1;
3511 if (i.index_reg == 0)
3512 {
3513 /* Operand is just <disp> */
20f0a1fc 3514 if (flag_code == CODE_64BIT)
29b0f896
AM		 3515 {
3516 /* 64bit mode overwrites the 32bit absolute
3517 addressing by RIP relative addressing and
3518 absolute addressing is encoded by one of the
3519 redundant SIB forms. */
3520 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3521 i.sib.base = NO_BASE_REGISTER;
3522 i.sib.index = NO_INDEX_REGISTER;
fc225355
L		 3523 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
3524 ? Disp32S : Disp32);
20f0a1fc 3525 }
fc225355
L		 3526 else if ((flag_code == CODE_16BIT)
3527 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 3528 {
3529 i.rm.regmem = NO_BASE_REGISTER_16;
3530 i.types[op] = Disp16;
3531 }
3532 else
3533 {
3534 i.rm.regmem = NO_BASE_REGISTER;
3535 i.types[op] = Disp32;
29b0f896
AM		 3536 }
3537 }
3538 else /* !i.base_reg && i.index_reg */
3539 {
3540 i.sib.index = i.index_reg->reg_num;
3541 i.sib.base = NO_BASE_REGISTER;
3542 i.sib.scale = i.log2_scale_factor;
3543 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3544 i.types[op] &= ~Disp;
3545 if (flag_code != CODE_64BIT)
3546 i.types[op] |= Disp32; /* Must be 32 bit */
3547 else
3548 i.types[op] |= Disp32S;
3549 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 3550 i.rex |= REX_X;
29b0f896
AM		 3551 }
3552 }
3553 /* RIP addressing for 64bit mode. */
3554 else if (i.base_reg->reg_type == BaseIndex)
3555 {
3556 i.rm.regmem = NO_BASE_REGISTER;
20f0a1fc 3557 i.types[op] &= ~ Disp;
29b0f896 3558 i.types[op] |= Disp32S;
71903a11 3559 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 3560 if (! i.disp_operands)
3561 fake_zero_displacement = 1;
29b0f896
AM		 3562 }
3563 else if (i.base_reg->reg_type & Reg16)
3564 {
3565 switch (i.base_reg->reg_num)
3566 {
3567 case 3: /* (%bx) */
3568 if (i.index_reg == 0)
3569 i.rm.regmem = 7;
3570 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3571 i.rm.regmem = i.index_reg->reg_num - 6;
3572 break;
3573 case 5: /* (%bp) */
3574 default_seg = &ss;
3575 if (i.index_reg == 0)
3576 {
3577 i.rm.regmem = 6;
3578 if ((i.types[op] & Disp) == 0)
3579 {
3580 /* fake (%bp) into 0(%bp) */
3581 i.types[op] |= Disp8;
252b5132 3582 fake_zero_displacement = 1;
29b0f896
AM		 3583 }
3584 }
3585 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3586 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
3587 break;
3588 default: /* (%si) -> 4 or (%di) -> 5 */
3589 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
3590 }
3591 i.rm.mode = mode_from_disp_size (i.types[op]);
3592 }
3593 else /* i.base_reg and 32/64 bit mode */
3594 {
3595 if (flag_code == CODE_64BIT
3596 && (i.types[op] & Disp))
fc225355
L		 3597 i.types[op] = ((i.types[op] & Disp8)
3598 | (i.prefix[ADDR_PREFIX] == 0
3599 ? Disp32S : Disp32));
20f0a1fc 3600
29b0f896
AM		 3601 i.rm.regmem = i.base_reg->reg_num;
3602 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 3603 i.rex |= REX_B;
29b0f896
AM		 3604 i.sib.base = i.base_reg->reg_num;
3605 /* x86-64 ignores REX prefix bit here to avoid decoder
3606 complications. */
3607 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
3608 {
3609 default_seg = &ss;
3610 if (i.disp_operands == 0)
3611 {
3612 fake_zero_displacement = 1;
3613 i.types[op] |= Disp8;
3614 }
3615 }
3616 else if (i.base_reg->reg_num == ESP_REG_NUM)
3617 {
3618 default_seg = &ss;
3619 }
3620 i.sib.scale = i.log2_scale_factor;
3621 if (i.index_reg == 0)
3622 {
3623 /* <disp>(%esp) becomes two byte modrm with no index
3624 register. We've already stored the code for esp
3625 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3626 Any base register besides %esp will not use the
3627 extra modrm byte. */
3628 i.sib.index = NO_INDEX_REGISTER;
3629#if !SCALE1_WHEN_NO_INDEX
3630 /* Another case where we force the second modrm byte. */
3631 if (i.log2_scale_factor)
3632 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
252b5132 3633#endif
29b0f896
AM		 3634 }
3635 else
3636 {
3637 i.sib.index = i.index_reg->reg_num;
3638 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3639 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 3640 i.rex |= REX_X;
29b0f896 3641 }
67a4f2b7
AO		 3642
3643 if (i.disp_operands
3644 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3645 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
3646 i.rm.mode = 0;
3647 else
3648 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 3649 }
252b5132 3650
29b0f896
AM		 3651 if (fake_zero_displacement)
3652 {
3653 /* Fakes a zero displacement assuming that i.types[op]
3654 holds the correct displacement size. */
3655 expressionS *exp;
3656
3657 assert (i.op[op].disps == 0);
3658 exp = &disp_expressions[i.disp_operands++];
3659 i.op[op].disps = exp;
3660 exp->X_op = O_constant;
3661 exp->X_add_number = 0;
3662 exp->X_add_symbol = (symbolS *) 0;
3663 exp->X_op_symbol = (symbolS *) 0;
3664 }
3665 }
252b5132 3666
29b0f896
AM		 3667 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3668 (if any) based on i.tm.extension_opcode. Again, we must be
3669 careful to make sure that segment/control/debug/test/MMX
3670 registers are coded into the i.rm.reg field. */
3671 if (i.reg_operands)
3672 {
99018f42
L		 3673 unsigned int op;
3674
3675 for (op = 0; op < i.operands; op++)
3676 if ((i.types[op] & (Reg | RegMMX | RegXMM
3677 | SReg2 | SReg3
3678 | Control | Debug | Test)))
3679 break;
3680 assert (op < i.operands);
3681
29b0f896
AM		 3682 /* If there is an extension opcode to put here, the register
3683 number must be put into the regmem field. */
3684 if (i.tm.extension_opcode != None)
3685 {
3686 i.rm.regmem = i.op[op].regs->reg_num;
3687 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 3688 i.rex |= REX_B;
29b0f896
AM		 3689 }
3690 else
3691 {
3692 i.rm.reg = i.op[op].regs->reg_num;
3693 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 3694 i.rex |= REX_R;
29b0f896 3695 }
252b5132 3696
29b0f896
AM		 3697 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3698 must set it to 3 to indicate this is a register operand
3699 in the regmem field. */
3700 if (!i.mem_operands)
3701 i.rm.mode = 3;
3702 }
252b5132 3703
29b0f896
AM		 3704 /* Fill in i.rm.reg field with extension opcode (if any). */
3705 if (i.tm.extension_opcode != None)
3706 i.rm.reg = i.tm.extension_opcode;
3707 }
3708 return default_seg;
3709}
252b5132 3710
29b0f896 3711static void
e3bb37b5 3712output_branch (void)
29b0f896
AM		 3713{
3714 char *p;
3715 int code16;
3716 int prefix;
3717 relax_substateT subtype;
3718 symbolS *sym;
3719 offsetT off;
3720
3721 code16 = 0;
3722 if (flag_code == CODE_16BIT)
3723 code16 = CODE16;
3724
3725 prefix = 0;
3726 if (i.prefix[DATA_PREFIX] != 0)
252b5132 3727 {
29b0f896
AM		 3728 prefix = 1;
3729 i.prefixes -= 1;
3730 code16 ^= CODE16;
252b5132 3731 }
29b0f896
AM		 3732 /* Pentium4 branch hints. */
3733 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3734 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 3735 {
29b0f896
AM		 3736 prefix++;
3737 i.prefixes--;
3738 }
3739 if (i.prefix[REX_PREFIX] != 0)
3740 {
3741 prefix++;
3742 i.prefixes--;
2f66722d
AM		 3743 }
3744
29b0f896
AM		 3745 if (i.prefixes != 0 && !intel_syntax)
3746 as_warn (_("skipping prefixes on this instruction"));
3747
3748 /* It's always a symbol; End frag & setup for relax.
3749 Make sure there is enough room in this frag for the largest
3750 instruction we may generate in md_convert_frag. This is 2
3751 bytes for the opcode and room for the prefix and largest
3752 displacement. */
3753 frag_grow (prefix + 2 + 4);
3754 /* Prefix and 1 opcode byte go in fr_fix. */
3755 p = frag_more (prefix + 1);
3756 if (i.prefix[DATA_PREFIX] != 0)
3757 *p++ = DATA_PREFIX_OPCODE;
3758 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
3759 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
3760 *p++ = i.prefix[SEG_PREFIX];
3761 if (i.prefix[REX_PREFIX] != 0)
3762 *p++ = i.prefix[REX_PREFIX];
3763 *p = i.tm.base_opcode;
3764
3765 if ((unsigned char) *p == JUMP_PC_RELATIVE)
3766 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
3767 else if ((cpu_arch_flags & Cpu386) != 0)
3768 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
3769 else
3770 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
3771 subtype |= code16;
3e73aa7c 3772
29b0f896
AM		 3773 sym = i.op[0].disps->X_add_symbol;
3774 off = i.op[0].disps->X_add_number;
3e73aa7c 3775
29b0f896
AM		 3776 if (i.op[0].disps->X_op != O_constant
3777 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 3778 {
29b0f896
AM		 3779 /* Handle complex expressions. */
3780 sym = make_expr_symbol (i.op[0].disps);
3781 off = 0;
3782 }
3e73aa7c 3783
29b0f896
AM		 3784 /* 1 possible extra opcode + 4 byte displacement go in var part.
3785 Pass reloc in fr_var. */
3786 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
3787}
3e73aa7c 3788
29b0f896 3789static void
e3bb37b5 3790output_jump (void)
29b0f896
AM		 3791{
3792 char *p;
3793 int size;
3e02c1cc 3794 fixS *fixP;
29b0f896
AM		 3795
3796 if (i.tm.opcode_modifier & JumpByte)
3797 {
3798 /* This is a loop or jecxz type instruction. */
3799 size = 1;
3800 if (i.prefix[ADDR_PREFIX] != 0)
3801 {
3802 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3803 i.prefixes -= 1;
3804 }
3805 /* Pentium4 branch hints. */
3806 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3807 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3808 {
3809 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3810 i.prefixes--;
3e73aa7c
JH		 3811 }
3812 }
29b0f896
AM		 3813 else
3814 {
3815 int code16;
3e73aa7c 3816
29b0f896
AM		 3817 code16 = 0;
3818 if (flag_code == CODE_16BIT)
3819 code16 = CODE16;
3e73aa7c 3820
29b0f896
AM		 3821 if (i.prefix[DATA_PREFIX] != 0)
3822 {
3823 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3824 i.prefixes -= 1;
3825 code16 ^= CODE16;
3826 }
252b5132 3827
29b0f896
AM		 3828 size = 4;
3829 if (code16)
3830 size = 2;
3831 }
9fcc94b6 3832
29b0f896
AM		 3833 if (i.prefix[REX_PREFIX] != 0)
3834 {
3835 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3836 i.prefixes -= 1;
3837 }
252b5132 3838
29b0f896
AM		 3839 if (i.prefixes != 0 && !intel_syntax)
3840 as_warn (_("skipping prefixes on this instruction"));
e0890092 3841
29b0f896
AM		 3842 p = frag_more (1 + size);
3843 *p++ = i.tm.base_opcode;
e0890092 3844
3e02c1cc
AM		 3845 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3846 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3847
3848 /* All jumps handled here are signed, but don't use a signed limit
3849 check for 32 and 16 bit jumps as we want to allow wrap around at
3850 4G and 64k respectively. */
3851 if (size == 1)
3852 fixP->fx_signed = 1;
29b0f896 3853}
e0890092 3854
29b0f896 3855static void
e3bb37b5 3856output_interseg_jump (void)
29b0f896
AM		 3857{
3858 char *p;
3859 int size;
3860 int prefix;
3861 int code16;
252b5132 3862
29b0f896
AM		 3863 code16 = 0;
3864 if (flag_code == CODE_16BIT)
3865 code16 = CODE16;
a217f122 3866
29b0f896
AM		 3867 prefix = 0;
3868 if (i.prefix[DATA_PREFIX] != 0)
3869 {
3870 prefix = 1;
3871 i.prefixes -= 1;
3872 code16 ^= CODE16;
3873 }
3874 if (i.prefix[REX_PREFIX] != 0)
3875 {
3876 prefix++;
3877 i.prefixes -= 1;
3878 }
252b5132 3879
29b0f896
AM		 3880 size = 4;
3881 if (code16)
3882 size = 2;
252b5132 3883
29b0f896
AM		 3884 if (i.prefixes != 0 && !intel_syntax)
3885 as_warn (_("skipping prefixes on this instruction"));
252b5132 3886
29b0f896
AM		 3887 /* 1 opcode; 2 segment; offset */
3888 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 3889
29b0f896
AM		 3890 if (i.prefix[DATA_PREFIX] != 0)
3891 *p++ = DATA_PREFIX_OPCODE;
252b5132 3892
29b0f896
AM		 3893 if (i.prefix[REX_PREFIX] != 0)
3894 *p++ = i.prefix[REX_PREFIX];
252b5132 3895
29b0f896
AM		 3896 *p++ = i.tm.base_opcode;
3897 if (i.op[1].imms->X_op == O_constant)
3898 {
3899 offsetT n = i.op[1].imms->X_add_number;
252b5132 3900
29b0f896
AM		 3901 if (size == 2
3902 && !fits_in_unsigned_word (n)
3903 && !fits_in_signed_word (n))
3904 {
3905 as_bad (_("16-bit jump out of range"));
3906 return;
3907 }
3908 md_number_to_chars (p, n, size);
3909 }
3910 else
3911 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3912 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3913 if (i.op[0].imms->X_op != O_constant)
3914 as_bad (_("can't handle non absolute segment in `%s'"),
3915 i.tm.name);
3916 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3917}
a217f122 3918
29b0f896 3919static void
e3bb37b5 3920output_insn (void)
29b0f896 3921{
2bbd9c25
JJ		 3922 fragS *insn_start_frag;
3923 offsetT insn_start_off;
3924
29b0f896
AM		 3925 /* Tie dwarf2 debug info to the address at the start of the insn.
3926 We can't do this after the insn has been output as the current
3927 frag may have been closed off. eg. by frag_var. */
3928 dwarf2_emit_insn (0);
3929
2bbd9c25
JJ		 3930 insn_start_frag = frag_now;
3931 insn_start_off = frag_now_fix ();
3932
29b0f896
AM		 3933 /* Output jumps. */
3934 if (i.tm.opcode_modifier & Jump)
3935 output_branch ();
3936 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3937 output_jump ();
3938 else if (i.tm.opcode_modifier & JumpInterSegment)
3939 output_interseg_jump ();
3940 else
3941 {
3942 /* Output normal instructions here. */
3943 char *p;
3944 unsigned char *q;
331d2d0d 3945 unsigned int prefix;
252b5132 3946
42903f7f 3947 /* All opcodes on i386 have either 1 or 2 bytes. SSSE3 and
381d071f
L		 3948 SSE4 instructions have 3 bytes. We may use one more higher
3949 byte to specify a prefix the instruction requires. Exclude
3950 instructions which are in both SSE4 and ABM. */
3951 if ((i.tm.cpu_flags & (CpuSSSE3 | CpuSSE4)) != 0
3952 && (i.tm.cpu_flags & CpuABM) == 0)
bc4bd9ab 3953 {
331d2d0d
L		 3954 if (i.tm.base_opcode & 0xff000000)
3955 {
3956 prefix = (i.tm.base_opcode >> 24) & 0xff;
3957 goto check_prefix;
3958 }
3959 }
3960 else if ((i.tm.base_opcode & 0xff0000) != 0)
3961 {
3962 prefix = (i.tm.base_opcode >> 16) & 0xff;
bc4bd9ab
MK		 3963 if ((i.tm.cpu_flags & CpuPadLock) != 0)
3964 {
64e74474 3965 check_prefix:
bc4bd9ab
MK		 3966 if (prefix != REPE_PREFIX_OPCODE
3967 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
3968 add_prefix (prefix);
3969 }
3970 else
331d2d0d 3971 add_prefix (prefix);
0f10071e 3972 }
252b5132 3973
29b0f896
AM		 3974 /* The prefix bytes. */
3975 for (q = i.prefix;
3976 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3977 q++)
3978 {
3979 if (*q)
3980 {
3981 p = frag_more (1);
3982 md_number_to_chars (p, (valueT) *q, 1);
3983 }
3984 }
252b5132 3985
29b0f896
AM		 3986 /* Now the opcode; be careful about word order here! */
3987 if (fits_in_unsigned_byte (i.tm.base_opcode))
3988 {
3989 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3990 }
3991 else
3992 {
381d071f
L		 3993 if ((i.tm.cpu_flags & (CpuSSSE3 | CpuSSE4)) != 0
3994 && (i.tm.cpu_flags & CpuABM) == 0)
331d2d0d
L		 3995 {
3996 p = frag_more (3);
3997 *p++ = (i.tm.base_opcode >> 16) & 0xff;
3998 }
3999 else
4000 p = frag_more (2);
0f10071e 4001
29b0f896
AM		 4002 /* Put out high byte first: can't use md_number_to_chars! */
4003 *p++ = (i.tm.base_opcode >> 8) & 0xff;
4004 *p = i.tm.base_opcode & 0xff;
4005 }
3e73aa7c 4006
29b0f896
AM		 4007 /* Now the modrm byte and sib byte (if present). */
4008 if (i.tm.opcode_modifier & Modrm)
4009 {
4010 p = frag_more (1);
4011 md_number_to_chars (p,
4012 (valueT) (i.rm.regmem << 0
4013 | i.rm.reg << 3
4014 | i.rm.mode << 6),
4015 1);
4016 /* If i.rm.regmem == ESP (4)
4017 && i.rm.mode != (Register mode)
4018 && not 16 bit
4019 ==> need second modrm byte. */
4020 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
4021 && i.rm.mode != 3
4022 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
4023 {
4024 p = frag_more (1);
4025 md_number_to_chars (p,
4026 (valueT) (i.sib.base << 0
4027 | i.sib.index << 3
4028 | i.sib.scale << 6),
4029 1);
4030 }
4031 }
3e73aa7c 4032
29b0f896 4033 if (i.disp_operands)
2bbd9c25 4034 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 4035
29b0f896 4036 if (i.imm_operands)
2bbd9c25 4037 output_imm (insn_start_frag, insn_start_off);
29b0f896 4038 }
252b5132 4039
29b0f896
AM		 4040#ifdef DEBUG386
4041 if (flag_debug)
4042 {
7b81dfbb 4043 pi ("" /*line*/, &i);
29b0f896
AM		 4044 }
4045#endif /* DEBUG386 */
4046}
252b5132 4047
29b0f896 4048static void
64e74474 4049output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 4050{
4051 char *p;
4052 unsigned int n;
252b5132 4053
29b0f896
AM		 4054 for (n = 0; n < i.operands; n++)
4055 {
4056 if (i.types[n] & Disp)
4057 {
4058 if (i.op[n].disps->X_op == O_constant)
4059 {
4060 int size;
4061 offsetT val;
252b5132 4062
29b0f896
AM		 4063 size = 4;
4064 if (i.types[n] & (Disp8 | Disp16 | Disp64))
4065 {
4066 size = 2;
4067 if (i.types[n] & Disp8)
4068 size = 1;
4069 if (i.types[n] & Disp64)
4070 size = 8;
4071 }
4072 val = offset_in_range (i.op[n].disps->X_add_number,
4073 size);
4074 p = frag_more (size);
4075 md_number_to_chars (p, val, size);
4076 }
4077 else
4078 {
f86103b7 4079 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 4080 int size = 4;
4081 int sign = 0;
4082 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
4083
4084 /* The PC relative address is computed relative
4085 to the instruction boundary, so in case immediate
4086 fields follows, we need to adjust the value. */
4087 if (pcrel && i.imm_operands)
4088 {
4089 int imm_size = 4;
4090 unsigned int n1;
252b5132 4091
29b0f896
AM		 4092 for (n1 = 0; n1 < i.operands; n1++)
4093 if (i.types[n1] & Imm)
252b5132 4094 {
29b0f896 4095 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
252b5132 4096 {
29b0f896
AM		 4097 imm_size = 2;
4098 if (i.types[n1] & (Imm8 | Imm8S))
4099 imm_size = 1;
4100 if (i.types[n1] & Imm64)
4101 imm_size = 8;
252b5132 4102 }
29b0f896 4103 break;
252b5132 4104 }
29b0f896
AM		 4105 /* We should find the immediate. */
4106 if (n1 == i.operands)
4107 abort ();
4108 i.op[n].disps->X_add_number -= imm_size;
4109 }
520dc8e8 4110
29b0f896
AM		 4111 if (i.types[n] & Disp32S)
4112 sign = 1;
3e73aa7c 4113
29b0f896
AM		 4114 if (i.types[n] & (Disp16 | Disp64))
4115 {
4116 size = 2;
4117 if (i.types[n] & Disp64)
4118 size = 8;
4119 }
520dc8e8 4120
29b0f896 4121 p = frag_more (size);
2bbd9c25 4122 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 4123 if (GOT_symbol
2bbd9c25 4124 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 4125 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 4126 || reloc_type == BFD_RELOC_X86_64_32S
4127 || (reloc_type == BFD_RELOC_64
4128 && object_64bit))
d6ab8113
JB		 4129 && (i.op[n].disps->X_op == O_symbol
4130 || (i.op[n].disps->X_op == O_add
4131 && ((symbol_get_value_expression
4132 (i.op[n].disps->X_op_symbol)->X_op)
4133 == O_subtract))))
4134 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 4135 {
4136 offsetT add;
4137
4138 if (insn_start_frag == frag_now)
4139 add = (p - frag_now->fr_literal) - insn_start_off;
4140 else
4141 {
4142 fragS *fr;
4143
4144 add = insn_start_frag->fr_fix - insn_start_off;
4145 for (fr = insn_start_frag->fr_next;
4146 fr && fr != frag_now; fr = fr->fr_next)
4147 add += fr->fr_fix;
4148 add += p - frag_now->fr_literal;
4149 }
4150
4fa24527 4151 if (!object_64bit)
7b81dfbb
AJ		 4152 {
4153 reloc_type = BFD_RELOC_386_GOTPC;
4154 i.op[n].imms->X_add_number += add;
4155 }
4156 else if (reloc_type == BFD_RELOC_64)
4157 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 4158 else
7b81dfbb
AJ		 4159 /* Don't do the adjustment for x86-64, as there
4160 the pcrel addressing is relative to the _next_
4161 insn, and that is taken care of in other code. */
d6ab8113 4162 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 4163 }
062cd5e7 4164 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 4165 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 4166 }
4167 }
4168 }
4169}
252b5132 4170
29b0f896 4171static void
64e74474 4172output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 4173{
4174 char *p;
4175 unsigned int n;
252b5132 4176
29b0f896
AM		 4177 for (n = 0; n < i.operands; n++)
4178 {
4179 if (i.types[n] & Imm)
4180 {
4181 if (i.op[n].imms->X_op == O_constant)
4182 {
4183 int size;
4184 offsetT val;
b4cac588 4185
29b0f896
AM		 4186 size = 4;
4187 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4188 {
4189 size = 2;
4190 if (i.types[n] & (Imm8 | Imm8S))
4191 size = 1;
4192 else if (i.types[n] & Imm64)
4193 size = 8;
4194 }
4195 val = offset_in_range (i.op[n].imms->X_add_number,
4196 size);
4197 p = frag_more (size);
4198 md_number_to_chars (p, val, size);
4199 }
4200 else
4201 {
4202 /* Not absolute_section.
4203 Need a 32-bit fixup (don't support 8bit
4204 non-absolute imms). Try to support other
4205 sizes ... */
f86103b7 4206 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 4207 int size = 4;
4208 int sign = 0;
4209
4210 if ((i.types[n] & (Imm32S))
a7d61044
JB		 4211 && (i.suffix == QWORD_MNEM_SUFFIX
4212 || (!i.suffix && (i.tm.opcode_modifier & No_lSuf))))
29b0f896
AM		 4213 sign = 1;
4214 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4215 {
4216 size = 2;
4217 if (i.types[n] & (Imm8 | Imm8S))
4218 size = 1;
4219 if (i.types[n] & Imm64)
4220 size = 8;
4221 }
520dc8e8 4222
29b0f896
AM		 4223 p = frag_more (size);
4224 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 4225
2bbd9c25
JJ		 4226 /* This is tough to explain. We end up with this one if we
4227 * have operands that look like
4228 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
4229 * obtain the absolute address of the GOT, and it is strongly
4230 * preferable from a performance point of view to avoid using
4231 * a runtime relocation for this. The actual sequence of
4232 * instructions often look something like:
4233 *
4234 * call .L66
4235 * .L66:
4236 * popl %ebx
4237 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4238 *
4239 * The call and pop essentially return the absolute address
4240 * of the label .L66 and store it in %ebx. The linker itself
4241 * will ultimately change the first operand of the addl so
4242 * that %ebx points to the GOT, but to keep things simple, the
4243 * .o file must have this operand set so that it generates not
4244 * the absolute address of .L66, but the absolute address of
4245 * itself. This allows the linker itself simply treat a GOTPC
4246 * relocation as asking for a pcrel offset to the GOT to be
4247 * added in, and the addend of the relocation is stored in the
4248 * operand field for the instruction itself.
4249 *
4250 * Our job here is to fix the operand so that it would add
4251 * the correct offset so that %ebx would point to itself. The
4252 * thing that is tricky is that .-.L66 will point to the
4253 * beginning of the instruction, so we need to further modify
4254 * the operand so that it will point to itself. There are
4255 * other cases where you have something like:
4256 *
4257 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4258 *
4259 * and here no correction would be required. Internally in
4260 * the assembler we treat operands of this form as not being
4261 * pcrel since the '.' is explicitly mentioned, and I wonder
4262 * whether it would simplify matters to do it this way. Who
4263 * knows. In earlier versions of the PIC patches, the
4264 * pcrel_adjust field was used to store the correction, but
4265 * since the expression is not pcrel, I felt it would be
4266 * confusing to do it this way. */
4267
d6ab8113 4268 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 4269 || reloc_type == BFD_RELOC_X86_64_32S
4270 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 4271 && GOT_symbol
4272 && GOT_symbol == i.op[n].imms->X_add_symbol
4273 && (i.op[n].imms->X_op == O_symbol
4274 || (i.op[n].imms->X_op == O_add
4275 && ((symbol_get_value_expression
4276 (i.op[n].imms->X_op_symbol)->X_op)
4277 == O_subtract))))
4278 {
2bbd9c25
JJ		 4279 offsetT add;
4280
4281 if (insn_start_frag == frag_now)
4282 add = (p - frag_now->fr_literal) - insn_start_off;
4283 else
4284 {
4285 fragS *fr;
4286
4287 add = insn_start_frag->fr_fix - insn_start_off;
4288 for (fr = insn_start_frag->fr_next;
4289 fr && fr != frag_now; fr = fr->fr_next)
4290 add += fr->fr_fix;
4291 add += p - frag_now->fr_literal;
4292 }
4293
4fa24527 4294 if (!object_64bit)
d6ab8113 4295 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 4296 else if (size == 4)
d6ab8113 4297 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 4298 else if (size == 8)
4299 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 4300 i.op[n].imms->X_add_number += add;
29b0f896 4301 }
29b0f896
AM		 4302 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4303 i.op[n].imms, 0, reloc_type);
4304 }
4305 }
4306 }
252b5132
RH		 4307}
4308\f
d182319b
JB		 4309/* x86_cons_fix_new is called via the expression parsing code when a
4310 reloc is needed. We use this hook to get the correct .got reloc. */
4311static enum bfd_reloc_code_real got_reloc = NO_RELOC;
4312static int cons_sign = -1;
4313
4314void
e3bb37b5 4315x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 4316 expressionS *exp)
d182319b
JB		 4317{
4318 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
4319
4320 got_reloc = NO_RELOC;
4321
4322#ifdef TE_PE
4323 if (exp->X_op == O_secrel)
4324 {
4325 exp->X_op = O_symbol;
4326 r = BFD_RELOC_32_SECREL;
4327 }
4328#endif
4329
4330 fix_new_exp (frag, off, len, exp, 0, r);
4331}
4332
718ddfc0
JB		 4333#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
4334# define lex_got(reloc, adjust, types) NULL
4335#else
f3c180ae
AM		 4336/* Parse operands of the form
4337 <symbol>@GOTOFF+<nnn>
4338 and similar .plt or .got references.
4339
4340 If we find one, set up the correct relocation in RELOC and copy the
4341 input string, minus the `@GOTOFF' into a malloc'd buffer for
4342 parsing by the calling routine. Return this buffer, and if ADJUST
4343 is non-null set it to the length of the string we removed from the
4344 input line. Otherwise return NULL. */
4345static char *
3956db08 4346lex_got (enum bfd_reloc_code_real *reloc,
64e74474
AM		 4347 int *adjust,
4348 unsigned int *types)
f3c180ae 4349{
7b81dfbb
AJ		 4350 /* Some of the relocations depend on the size of what field is to
4351 be relocated. But in our callers i386_immediate and i386_displacement
4352 we don't yet know the operand size (this will be set by insn
4353 matching). Hence we record the word32 relocation here,
4354 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 4355 static const struct {
4356 const char *str;
4fa24527 4357 const enum bfd_reloc_code_real rel[2];
3956db08 4358 const unsigned int types64;
f3c180ae 4359 } gotrel[] = {
4eed87de
AM		 4360 { "PLTOFF", { 0,
4361 BFD_RELOC_X86_64_PLTOFF64 },
4362 Imm64 },
4363 { "PLT", { BFD_RELOC_386_PLT32,
4364 BFD_RELOC_X86_64_PLT32 },
4365 Imm32 | Imm32S | Disp32 },
4366 { "GOTPLT", { 0,
4367 BFD_RELOC_X86_64_GOTPLT64 },
4368 Imm64 | Disp64 },
4369 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
4370 BFD_RELOC_X86_64_GOTOFF64 },
4371 Imm64 | Disp64 },
4372 { "GOTPCREL", { 0,
4373 BFD_RELOC_X86_64_GOTPCREL },
4374 Imm32 | Imm32S | Disp32 },
4375 { "TLSGD", { BFD_RELOC_386_TLS_GD,
4376 BFD_RELOC_X86_64_TLSGD },
4377 Imm32 | Imm32S | Disp32 },
4378 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
4379 0 },
4380 0 },
4381 { "TLSLD", { 0,
4382 BFD_RELOC_X86_64_TLSLD },
4383 Imm32 | Imm32S | Disp32 },
4384 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
4385 BFD_RELOC_X86_64_GOTTPOFF },
4386 Imm32 | Imm32S | Disp32 },
4387 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
4388 BFD_RELOC_X86_64_TPOFF32 },
4389 Imm32 | Imm32S | Imm64 | Disp32 | Disp64 },
4390 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
4391 0 },
4392 0 },
4393 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
4394 BFD_RELOC_X86_64_DTPOFF32 },
4395 Imm32 | Imm32S | Imm64 | Disp32 | Disp64 },
4396 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
4397 0 },
4398 0 },
4399 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
4400 0 },
4401 0 },
4402 { "GOT", { BFD_RELOC_386_GOT32,
4403 BFD_RELOC_X86_64_GOT32 },
4404 Imm32 | Imm32S | Disp32 | Imm64 },
4405 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
4406 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
4407 Imm32 | Imm32S | Disp32 },
4408 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
4409 BFD_RELOC_X86_64_TLSDESC_CALL },
4410 Imm32 | Imm32S | Disp32 }
f3c180ae
AM		 4411 };
4412 char *cp;
4413 unsigned int j;
4414
718ddfc0
JB		 4415 if (!IS_ELF)
4416 return NULL;
4417
f3c180ae
AM		 4418 for (cp = input_line_pointer; *cp != '@'; cp++)
4419 if (is_end_of_line[(unsigned char) *cp])
4420 return NULL;
4421
4422 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
4423 {
4424 int len;
4425
4426 len = strlen (gotrel[j].str);
28f81592 4427 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 4428 {
4fa24527 4429 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 4430 {
28f81592
AM		 4431 int first, second;
4432 char *tmpbuf, *past_reloc;
f3c180ae 4433
4fa24527 4434 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 4435 if (adjust)
4436 *adjust = len;
f3c180ae 4437
3956db08
JB		 4438 if (types)
4439 {
4440 if (flag_code != CODE_64BIT)
4eed87de 4441 *types = Imm32 | Disp32;
3956db08
JB		 4442 else
4443 *types = gotrel[j].types64;
4444 }
4445
f3c180ae
AM		 4446 if (GOT_symbol == NULL)
4447 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
4448
4449 /* Replace the relocation token with ' ', so that
4450 errors like foo@GOTOFF1 will be detected. */
28f81592
AM		 4451
4452 /* The length of the first part of our input line. */
f3c180ae 4453 first = cp - input_line_pointer;
28f81592
AM		 4454
4455 /* The second part goes from after the reloc token until
4456 (and including) an end_of_line char. Don't use strlen
4457 here as the end_of_line char may not be a NUL. */
4458 past_reloc = cp + 1 + len;
4459 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
4460 ;
4461 second = cp - past_reloc;
4462
4463 /* Allocate and copy string. The trailing NUL shouldn't
4464 be necessary, but be safe. */
4465 tmpbuf = xmalloc (first + second + 2);
f3c180ae
AM		 4466 memcpy (tmpbuf, input_line_pointer, first);
4467 tmpbuf[first] = ' ';
28f81592
AM		 4468 memcpy (tmpbuf + first + 1, past_reloc, second);
4469 tmpbuf[first + second + 1] = '\0';
f3c180ae
AM		 4470 return tmpbuf;
4471 }
4472
4fa24527
JB		 4473 as_bad (_("@%s reloc is not supported with %d-bit output format"),
4474 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 4475 return NULL;
4476 }
4477 }
4478
4479 /* Might be a symbol version string. Don't as_bad here. */
4480 return NULL;
4481}
4482
f3c180ae 4483void
e3bb37b5 4484x86_cons (expressionS *exp, int size)
f3c180ae 4485{
4fa24527 4486 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 4487 {
4488 /* Handle @GOTOFF and the like in an expression. */
4489 char *save;
4490 char *gotfree_input_line;
4491 int adjust;
4492
4493 save = input_line_pointer;
3956db08 4494 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 4495 if (gotfree_input_line)
4496 input_line_pointer = gotfree_input_line;
4497
4498 expression (exp);
4499
4500 if (gotfree_input_line)
4501 {
4502 /* expression () has merrily parsed up to the end of line,
4503 or a comma - in the wrong buffer. Transfer how far
4504 input_line_pointer has moved to the right buffer. */
4505 input_line_pointer = (save
4506 + (input_line_pointer - gotfree_input_line)
4507 + adjust);
4508 free (gotfree_input_line);
4509 }
4510 }
4511 else
4512 expression (exp);
4513}
4514#endif
4515
d182319b 4516static void signed_cons (int size)
6482c264 4517{
d182319b
JB		 4518 if (flag_code == CODE_64BIT)
4519 cons_sign = 1;
4520 cons (size);
4521 cons_sign = -1;
6482c264
NC		 4522}
4523
d182319b 4524#ifdef TE_PE
6482c264
NC		 4525static void
4526pe_directive_secrel (dummy)
4527 int dummy ATTRIBUTE_UNUSED;
4528{
4529 expressionS exp;
4530
4531 do
4532 {
4533 expression (&exp);
4534 if (exp.X_op == O_symbol)
4535 exp.X_op = O_secrel;
4536
4537 emit_expr (&exp, 4);
4538 }
4539 while (*input_line_pointer++ == ',');
4540
4541 input_line_pointer--;
4542 demand_empty_rest_of_line ();
4543}
6482c264
NC		 4544#endif
4545
252b5132 4546static int
70e41ade 4547i386_immediate (char *imm_start)
252b5132
RH		 4548{
4549 char *save_input_line_pointer;
f3c180ae 4550 char *gotfree_input_line;
252b5132 4551 segT exp_seg = 0;
47926f60 4552 expressionS *exp;
3956db08 4553 unsigned int types = ~0U;
252b5132
RH		 4554
4555 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
4556 {
31b2323c
L		 4557 as_bad (_("at most %d immediate operands are allowed"),
4558 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 4559 return 0;
4560 }
4561
4562 exp = &im_expressions[i.imm_operands++];
520dc8e8 4563 i.op[this_operand].imms = exp;
252b5132
RH		 4564
4565 if (is_space_char (*imm_start))
4566 ++imm_start;
4567
4568 save_input_line_pointer = input_line_pointer;
4569 input_line_pointer = imm_start;
4570
3956db08 4571 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4572 if (gotfree_input_line)
4573 input_line_pointer = gotfree_input_line;
252b5132
RH		 4574
4575 exp_seg = expression (exp);
4576
83183c0c 4577 SKIP_WHITESPACE ();
252b5132 4578 if (*input_line_pointer)
f3c180ae 4579 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 4580
4581 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 4582 if (gotfree_input_line)
4583 free (gotfree_input_line);
252b5132 4584
2daf4fd8 4585 if (exp->X_op == O_absent || exp->X_op == O_big)
252b5132 4586 {
47926f60 4587 /* Missing or bad expr becomes absolute 0. */
d0b47220 4588 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
24eab124 4589 imm_start);
252b5132
RH		 4590 exp->X_op = O_constant;
4591 exp->X_add_number = 0;
4592 exp->X_add_symbol = (symbolS *) 0;
4593 exp->X_op_symbol = (symbolS *) 0;
252b5132 4594 }
3e73aa7c 4595 else if (exp->X_op == O_constant)
252b5132 4596 {
47926f60 4597 /* Size it properly later. */
3e73aa7c
JH		 4598 i.types[this_operand] |= Imm64;
4599 /* If BFD64, sign extend val. */
4eed87de
AM		 4600 if (!use_rela_relocations
4601 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
4602 exp->X_add_number
4603 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 4604 }
4c63da97 4605#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 4606 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4607 && exp_seg != absolute_section
47926f60 4608 && exp_seg != text_section
24eab124
AM		 4609 && exp_seg != data_section
4610 && exp_seg != bss_section
4611 && exp_seg != undefined_section
f86103b7 4612 && !bfd_is_com_section (exp_seg))
252b5132 4613 {
d0b47220 4614 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 4615 return 0;
4616 }
4617#endif
bb8f5920
L		 4618 else if (!intel_syntax && exp->X_op == O_register)
4619 {
4620 as_bad (_("illegal immediate register operand %s"), imm_start);
4621 return 0;
4622 }
252b5132
RH		 4623 else
4624 {
4625 /* This is an address. The size of the address will be
24eab124 4626 determined later, depending on destination register,
3e73aa7c
JH		 4627 suffix, or the default for the section. */
4628 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
3956db08 4629 i.types[this_operand] &= types;
252b5132
RH		 4630 }
4631
4632 return 1;
4633}
4634
551c1ca1 4635static char *
e3bb37b5 4636i386_scale (char *scale)
252b5132 4637{
551c1ca1
AM		 4638 offsetT val;
4639 char *save = input_line_pointer;
252b5132 4640
551c1ca1
AM		 4641 input_line_pointer = scale;
4642 val = get_absolute_expression ();
4643
4644 switch (val)
252b5132 4645 {
551c1ca1 4646 case 1:
252b5132
RH		 4647 i.log2_scale_factor = 0;
4648 break;
551c1ca1 4649 case 2:
252b5132
RH		 4650 i.log2_scale_factor = 1;
4651 break;
551c1ca1 4652 case 4:
252b5132
RH		 4653 i.log2_scale_factor = 2;
4654 break;
551c1ca1 4655 case 8:
252b5132
RH		 4656 i.log2_scale_factor = 3;
4657 break;
4658 default:
a724f0f4
JB		 4659 {
4660 char sep = *input_line_pointer;
4661
4662 *input_line_pointer = '\0';
4663 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4664 scale);
4665 *input_line_pointer = sep;
4666 input_line_pointer = save;
4667 return NULL;
4668 }
252b5132 4669 }
29b0f896 4670 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 4671 {
4672 as_warn (_("scale factor of %d without an index register"),
24eab124 4673 1 << i.log2_scale_factor);
252b5132
RH		 4674#if SCALE1_WHEN_NO_INDEX
4675 i.log2_scale_factor = 0;
4676#endif
4677 }
551c1ca1
AM		 4678 scale = input_line_pointer;
4679 input_line_pointer = save;
4680 return scale;
252b5132
RH		 4681}
4682
252b5132 4683static int
e3bb37b5 4684i386_displacement (char *disp_start, char *disp_end)
252b5132 4685{
29b0f896 4686 expressionS *exp;
252b5132
RH		 4687 segT exp_seg = 0;
4688 char *save_input_line_pointer;
f3c180ae 4689 char *gotfree_input_line;
e05278af 4690 int bigdisp, override;
3956db08 4691 unsigned int types = Disp;
252b5132 4692
31b2323c
L		 4693 if (i.disp_operands == MAX_MEMORY_OPERANDS)
4694 {
4695 as_bad (_("at most %d displacement operands are allowed"),
4696 MAX_MEMORY_OPERANDS);
4697 return 0;
4698 }
4699
e05278af
JB		 4700 if ((i.types[this_operand] & JumpAbsolute)
4701 || !(current_templates->start->opcode_modifier & (Jump | JumpDword)))
4702 {
4703 bigdisp = Disp32;
4704 override = (i.prefix[ADDR_PREFIX] != 0);
4705 }
4706 else
4707 {
4708 /* For PC-relative branches, the width of the displacement
4709 is dependent upon data size, not address size. */
4710 bigdisp = 0;
4711 override = (i.prefix[DATA_PREFIX] != 0);
4712 }
3e73aa7c 4713 if (flag_code == CODE_64BIT)
7ecd2f8b 4714 {
e05278af 4715 if (!bigdisp)
64e74474
AM		 4716 bigdisp = ((override || i.suffix == WORD_MNEM_SUFFIX)
4717 ? Disp16
4718 : Disp32S | Disp32);
e05278af 4719 else if (!override)
3956db08 4720 bigdisp = Disp64 | Disp32S | Disp32;
7ecd2f8b 4721 }
e05278af
JB		 4722 else
4723 {
4724 if (!bigdisp)
4725 {
4726 if (!override)
4727 override = (i.suffix == (flag_code != CODE_16BIT
4728 ? WORD_MNEM_SUFFIX
4729 : LONG_MNEM_SUFFIX));
4730 bigdisp = Disp32;
4731 }
4732 if ((flag_code == CODE_16BIT) ^ override)
4733 bigdisp = Disp16;
4734 }
252b5132
RH		 4735 i.types[this_operand] |= bigdisp;
4736
4737 exp = &disp_expressions[i.disp_operands];
520dc8e8 4738 i.op[this_operand].disps = exp;
252b5132
RH		 4739 i.disp_operands++;
4740 save_input_line_pointer = input_line_pointer;
4741 input_line_pointer = disp_start;
4742 END_STRING_AND_SAVE (disp_end);
4743
4744#ifndef GCC_ASM_O_HACK
4745#define GCC_ASM_O_HACK 0
4746#endif
4747#if GCC_ASM_O_HACK
4748 END_STRING_AND_SAVE (disp_end + 1);
4749 if ((i.types[this_operand] & BaseIndex) != 0
24eab124 4750 && displacement_string_end[-1] == '+')
252b5132
RH		 4751 {
4752 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 4753 constraint within gcc asm statements.
4754 For instance:
4755
4756 #define _set_tssldt_desc(n,addr,limit,type) \
4757 __asm__ __volatile__ ( \
4758 "movw %w2,%0\n\t" \
4759 "movw %w1,2+%0\n\t" \
4760 "rorl $16,%1\n\t" \
4761 "movb %b1,4+%0\n\t" \
4762 "movb %4,5+%0\n\t" \
4763 "movb $0,6+%0\n\t" \
4764 "movb %h1,7+%0\n\t" \
4765 "rorl $16,%1" \
4766 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4767
4768 This works great except that the output assembler ends
4769 up looking a bit weird if it turns out that there is
4770 no offset. You end up producing code that looks like:
4771
4772 #APP
4773 movw $235,(%eax)
4774 movw %dx,2+(%eax)
4775 rorl $16,%edx
4776 movb %dl,4+(%eax)
4777 movb $137,5+(%eax)
4778 movb $0,6+(%eax)
4779 movb %dh,7+(%eax)
4780 rorl $16,%edx
4781 #NO_APP
4782
47926f60 4783 So here we provide the missing zero. */
24eab124
AM		 4784
4785 *displacement_string_end = '0';
252b5132
RH		 4786 }
4787#endif
3956db08 4788 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4789 if (gotfree_input_line)
4790 input_line_pointer = gotfree_input_line;
252b5132 4791
24eab124 4792 exp_seg = expression (exp);
252b5132 4793
636c26b0
AM		 4794 SKIP_WHITESPACE ();
4795 if (*input_line_pointer)
4796 as_bad (_("junk `%s' after expression"), input_line_pointer);
4797#if GCC_ASM_O_HACK
4798 RESTORE_END_STRING (disp_end + 1);
4799#endif
4800 RESTORE_END_STRING (disp_end);
4801 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 4802 if (gotfree_input_line)
4803 free (gotfree_input_line);
636c26b0 4804
24eab124
AM		 4805 /* We do this to make sure that the section symbol is in
4806 the symbol table. We will ultimately change the relocation
47926f60 4807 to be relative to the beginning of the section. */
1ae12ab7 4808 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 4809 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4810 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 4811 {
636c26b0
AM		 4812 if (exp->X_op != O_symbol)
4813 {
4814 as_bad (_("bad expression used with @%s"),
4815 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4816 ? "GOTPCREL"
4817 : "GOTOFF"));
4818 return 0;
4819 }
4820
e5cb08ac 4821 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 4822 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
4823 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 4824 exp->X_op = O_subtract;
4825 exp->X_op_symbol = GOT_symbol;
1ae12ab7 4826 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 4827 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 4828 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4829 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 4830 else
29b0f896 4831 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 4832 }
252b5132 4833
2daf4fd8
AM		 4834 if (exp->X_op == O_absent || exp->X_op == O_big)
4835 {
47926f60 4836 /* Missing or bad expr becomes absolute 0. */
d0b47220 4837 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
2daf4fd8
AM		 4838 disp_start);
4839 exp->X_op = O_constant;
4840 exp->X_add_number = 0;
4841 exp->X_add_symbol = (symbolS *) 0;
4842 exp->X_op_symbol = (symbolS *) 0;
4843 }
4844
4c63da97 4845#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
45288df1 4846 if (exp->X_op != O_constant
45288df1 4847 && OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4848 && exp_seg != absolute_section
45288df1
AM		 4849 && exp_seg != text_section
4850 && exp_seg != data_section
4851 && exp_seg != bss_section
31312f95 4852 && exp_seg != undefined_section
f86103b7 4853 && !bfd_is_com_section (exp_seg))
24eab124 4854 {
d0b47220 4855 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
24eab124
AM		 4856 return 0;
4857 }
252b5132 4858#endif
3956db08
JB		 4859
4860 if (!(i.types[this_operand] & ~Disp))
4861 i.types[this_operand] &= types;
4862
252b5132
RH		 4863 return 1;
4864}
4865
eecb386c 4866/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 4867 Return 1 on success, 0 on a failure. */
4868
252b5132 4869static int
e3bb37b5 4870i386_index_check (const char *operand_string)
252b5132 4871{
3e73aa7c 4872 int ok;
24eab124 4873#if INFER_ADDR_PREFIX
eecb386c
AM		 4874 int fudged = 0;
4875
24eab124
AM		 4876 tryprefix:
4877#endif
3e73aa7c 4878 ok = 1;
30123838
JB		 4879 if ((current_templates->start->cpu_flags & CpuSVME)
4880 && current_templates->end[-1].operand_types[0] == AnyMem)
4881 {
4882 /* Memory operands of SVME insns are special in that they only allow
4883 rAX as their memory address and ignore any segment override. */
4884 unsigned RegXX;
4885
4886 /* SKINIT is even more restrictive: it always requires EAX. */
4887 if (strcmp (current_templates->start->name, "skinit") == 0)
4888 RegXX = Reg32;
4889 else if (flag_code == CODE_64BIT)
4890 RegXX = i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32;
4891 else
64e74474
AM		 4892 RegXX = ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
4893 ? Reg16
4894 : Reg32);
30123838
JB		 4895 if (!i.base_reg
4896 || !(i.base_reg->reg_type & Acc)
4897 || !(i.base_reg->reg_type & RegXX)
4898 || i.index_reg
4899 || (i.types[0] & Disp))
4900 ok = 0;
4901 }
4902 else if (flag_code == CODE_64BIT)
64e74474
AM		 4903 {
4904 unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
4905
4906 if ((i.base_reg
4907 && ((i.base_reg->reg_type & RegXX) == 0)
4908 && (i.base_reg->reg_type != BaseIndex
4909 || i.index_reg))
4910 || (i.index_reg
4911 && ((i.index_reg->reg_type & (RegXX | BaseIndex))
4912 != (RegXX | BaseIndex))))
4913 ok = 0;
3e73aa7c
JH		 4914 }
4915 else
4916 {
4917 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4918 {
4919 /* 16bit checks. */
4920 if ((i.base_reg
29b0f896
AM		 4921 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
4922 != (Reg16 | BaseIndex)))
3e73aa7c 4923 || (i.index_reg
29b0f896
AM		 4924 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
4925 != (Reg16 | BaseIndex))
4926 || !(i.base_reg
4927 && i.base_reg->reg_num < 6
4928 && i.index_reg->reg_num >= 6
4929 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 4930 ok = 0;
4931 }
4932 else
e5cb08ac 4933 {
3e73aa7c
JH		 4934 /* 32bit checks. */
4935 if ((i.base_reg
4936 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
4937 || (i.index_reg
29b0f896
AM		 4938 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
4939 != (Reg32 | BaseIndex))))
e5cb08ac 4940 ok = 0;
3e73aa7c
JH		 4941 }
4942 }
4943 if (!ok)
24eab124
AM		 4944 {
4945#if INFER_ADDR_PREFIX
20f0a1fc 4946 if (i.prefix[ADDR_PREFIX] == 0)
24eab124
AM		 4947 {
4948 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
4949 i.prefixes += 1;
b23bac36
AM		 4950 /* Change the size of any displacement too. At most one of
4951 Disp16 or Disp32 is set.
4952 FIXME. There doesn't seem to be any real need for separate
4953 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 4954 Removing them would probably clean up the code quite a lot. */
4eed87de
AM		 4955 if (flag_code != CODE_64BIT
4956 && (i.types[this_operand] & (Disp16 | Disp32)))
64e74474 4957 i.types[this_operand] ^= (Disp16 | Disp32);
eecb386c 4958 fudged = 1;
24eab124
AM		 4959 goto tryprefix;
4960 }
eecb386c
AM		 4961 if (fudged)
4962 as_bad (_("`%s' is not a valid base/index expression"),
4963 operand_string);
4964 else
c388dee8 4965#endif
eecb386c
AM		 4966 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4967 operand_string,
3e73aa7c 4968 flag_code_names[flag_code]);
24eab124 4969 }
20f0a1fc 4970 return ok;
24eab124 4971}
252b5132 4972
252b5132 4973/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 4974 on error. */
252b5132 4975
252b5132 4976static int
e3bb37b5 4977i386_operand (char *operand_string)
252b5132 4978{
af6bdddf
AM		 4979 const reg_entry *r;
4980 char *end_op;
24eab124 4981 char *op_string = operand_string;
252b5132 4982
24eab124 4983 if (is_space_char (*op_string))
252b5132
RH		 4984 ++op_string;
4985
24eab124 4986 /* We check for an absolute prefix (differentiating,
47926f60 4987 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 4988 if (*op_string == ABSOLUTE_PREFIX)
4989 {
4990 ++op_string;
4991 if (is_space_char (*op_string))
4992 ++op_string;
4993 i.types[this_operand] |= JumpAbsolute;
4994 }
252b5132 4995
47926f60 4996 /* Check if operand is a register. */
4d1bb795 4997 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 4998 {
24eab124
AM		 4999 /* Check for a segment override by searching for ':' after a
5000 segment register. */
5001 op_string = end_op;
5002 if (is_space_char (*op_string))
5003 ++op_string;
5004 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
5005 {
5006 switch (r->reg_num)
5007 {
5008 case 0:
5009 i.seg[i.mem_operands] = &es;
5010 break;
5011 case 1:
5012 i.seg[i.mem_operands] = &cs;
5013 break;
5014 case 2:
5015 i.seg[i.mem_operands] = &ss;
5016 break;
5017 case 3:
5018 i.seg[i.mem_operands] = &ds;
5019 break;
5020 case 4:
5021 i.seg[i.mem_operands] = &fs;
5022 break;
5023 case 5:
5024 i.seg[i.mem_operands] = &gs;
5025 break;
5026 }
252b5132 5027
24eab124 5028 /* Skip the ':' and whitespace. */
252b5132
RH		 5029 ++op_string;
5030 if (is_space_char (*op_string))
24eab124 5031 ++op_string;
252b5132 5032
24eab124
AM		 5033 if (!is_digit_char (*op_string)
5034 && !is_identifier_char (*op_string)
5035 && *op_string != '('
5036 && *op_string != ABSOLUTE_PREFIX)
5037 {
5038 as_bad (_("bad memory operand `%s'"), op_string);
5039 return 0;
5040 }
47926f60 5041 /* Handle case of %es:*foo. */
24eab124
AM		 5042 if (*op_string == ABSOLUTE_PREFIX)
5043 {
5044 ++op_string;
5045 if (is_space_char (*op_string))
5046 ++op_string;
5047 i.types[this_operand] |= JumpAbsolute;
5048 }
5049 goto do_memory_reference;
5050 }
5051 if (*op_string)
5052 {
d0b47220 5053 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 5054 return 0;
5055 }
5056 i.types[this_operand] |= r->reg_type & ~BaseIndex;
520dc8e8 5057 i.op[this_operand].regs = r;
24eab124
AM		 5058 i.reg_operands++;
5059 }
af6bdddf
AM		 5060 else if (*op_string == REGISTER_PREFIX)
5061 {
5062 as_bad (_("bad register name `%s'"), op_string);
5063 return 0;
5064 }
24eab124 5065 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 5066 {
24eab124
AM		 5067 ++op_string;
5068 if (i.types[this_operand] & JumpAbsolute)
5069 {
d0b47220 5070 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 5071 return 0;
5072 }
5073 if (!i386_immediate (op_string))
5074 return 0;
5075 }
5076 else if (is_digit_char (*op_string)
5077 || is_identifier_char (*op_string)
e5cb08ac 5078 || *op_string == '(')
24eab124 5079 {
47926f60 5080 /* This is a memory reference of some sort. */
af6bdddf 5081 char *base_string;
252b5132 5082
47926f60 5083 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 5084 char *displacement_string_start;
5085 char *displacement_string_end;
252b5132 5086
24eab124 5087 do_memory_reference:
24eab124
AM		 5088 if ((i.mem_operands == 1
5089 && (current_templates->start->opcode_modifier & IsString) == 0)
5090 || i.mem_operands == 2)
5091 {
5092 as_bad (_("too many memory references for `%s'"),
5093 current_templates->start->name);
5094 return 0;
5095 }
252b5132 5096
24eab124
AM		 5097 /* Check for base index form. We detect the base index form by
5098 looking for an ')' at the end of the operand, searching
5099 for the '(' matching it, and finding a REGISTER_PREFIX or ','
5100 after the '('. */
af6bdddf 5101 base_string = op_string + strlen (op_string);
c3332e24 5102
af6bdddf
AM		 5103 --base_string;
5104 if (is_space_char (*base_string))
5105 --base_string;
252b5132 5106
47926f60 5107 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 5108 displacement_string_start = op_string;
5109 displacement_string_end = base_string + 1;
252b5132 5110
24eab124
AM		 5111 if (*base_string == ')')
5112 {
af6bdddf 5113 char *temp_string;
24eab124
AM		 5114 unsigned int parens_balanced = 1;
5115 /* We've already checked that the number of left & right ()'s are
47926f60 5116 equal, so this loop will not be infinite. */
24eab124
AM		 5117 do
5118 {
5119 base_string--;
5120 if (*base_string == ')')
5121 parens_balanced++;
5122 if (*base_string == '(')
5123 parens_balanced--;
5124 }
5125 while (parens_balanced);
c3332e24 5126
af6bdddf 5127 temp_string = base_string;
c3332e24 5128
24eab124 5129 /* Skip past '(' and whitespace. */
252b5132
RH		 5130 ++base_string;
5131 if (is_space_char (*base_string))
24eab124 5132 ++base_string;
252b5132 5133
af6bdddf 5134 if (*base_string == ','
4eed87de
AM		 5135 || ((i.base_reg = parse_register (base_string, &end_op))
5136 != NULL))
252b5132 5137 {
af6bdddf 5138 displacement_string_end = temp_string;
252b5132 5139
af6bdddf 5140 i.types[this_operand] |= BaseIndex;
252b5132 5141
af6bdddf 5142 if (i.base_reg)
24eab124 5143 {
24eab124
AM		 5144 base_string = end_op;
5145 if (is_space_char (*base_string))
5146 ++base_string;
af6bdddf
AM		 5147 }
5148
5149 /* There may be an index reg or scale factor here. */
5150 if (*base_string == ',')
5151 {
5152 ++base_string;
5153 if (is_space_char (*base_string))
5154 ++base_string;
5155
4eed87de
AM		 5156 if ((i.index_reg = parse_register (base_string, &end_op))
5157 != NULL)
24eab124 5158 {
af6bdddf 5159 base_string = end_op;
24eab124
AM		 5160 if (is_space_char (*base_string))
5161 ++base_string;
af6bdddf
AM		 5162 if (*base_string == ',')
5163 {
5164 ++base_string;
5165 if (is_space_char (*base_string))
5166 ++base_string;
5167 }
e5cb08ac 5168 else if (*base_string != ')')
af6bdddf 5169 {
4eed87de
AM		 5170 as_bad (_("expecting `,' or `)' "
5171 "after index register in `%s'"),
af6bdddf
AM		 5172 operand_string);
5173 return 0;
5174 }
24eab124 5175 }
af6bdddf 5176 else if (*base_string == REGISTER_PREFIX)
24eab124 5177 {
af6bdddf 5178 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 5179 return 0;
5180 }
252b5132 5181
47926f60 5182 /* Check for scale factor. */
551c1ca1 5183 if (*base_string != ')')
af6bdddf 5184 {
551c1ca1
AM		 5185 char *end_scale = i386_scale (base_string);
5186
5187 if (!end_scale)
af6bdddf 5188 return 0;
24eab124 5189
551c1ca1 5190 base_string = end_scale;
af6bdddf
AM		 5191 if (is_space_char (*base_string))
5192 ++base_string;
5193 if (*base_string != ')')
5194 {
4eed87de
AM		 5195 as_bad (_("expecting `)' "
5196 "after scale factor in `%s'"),
af6bdddf
AM		 5197 operand_string);
5198 return 0;
5199 }
5200 }
5201 else if (!i.index_reg)
24eab124 5202 {
4eed87de
AM		 5203 as_bad (_("expecting index register or scale factor "
5204 "after `,'; got '%c'"),
af6bdddf 5205 *base_string);
24eab124
AM		 5206 return 0;
5207 }
5208 }
af6bdddf 5209 else if (*base_string != ')')
24eab124 5210 {
4eed87de
AM		 5211 as_bad (_("expecting `,' or `)' "
5212 "after base register in `%s'"),
af6bdddf 5213 operand_string);
24eab124
AM		 5214 return 0;
5215 }
c3332e24 5216 }
af6bdddf 5217 else if (*base_string == REGISTER_PREFIX)
c3332e24 5218 {
af6bdddf 5219 as_bad (_("bad register name `%s'"), base_string);
24eab124 5220 return 0;
c3332e24 5221 }
24eab124
AM		 5222 }
5223
5224 /* If there's an expression beginning the operand, parse it,
5225 assuming displacement_string_start and
5226 displacement_string_end are meaningful. */
5227 if (displacement_string_start != displacement_string_end)
5228 {
5229 if (!i386_displacement (displacement_string_start,
5230 displacement_string_end))
5231 return 0;
5232 }
5233
5234 /* Special case for (%dx) while doing input/output op. */
5235 if (i.base_reg
5236 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
5237 && i.index_reg == 0
5238 && i.log2_scale_factor == 0
5239 && i.seg[i.mem_operands] == 0
5240 && (i.types[this_operand] & Disp) == 0)
5241 {
5242 i.types[this_operand] = InOutPortReg;
5243 return 1;
5244 }
5245
eecb386c
AM		 5246 if (i386_index_check (operand_string) == 0)
5247 return 0;
24eab124
AM		 5248 i.mem_operands++;
5249 }
5250 else
ce8a8b2f
AM		 5251 {
5252 /* It's not a memory operand; argh! */
24eab124
AM		 5253 as_bad (_("invalid char %s beginning operand %d `%s'"),
5254 output_invalid (*op_string),
5255 this_operand + 1,
5256 op_string);
5257 return 0;
5258 }
47926f60 5259 return 1; /* Normal return. */
252b5132
RH		 5260}
5261\f
ee7fcc42
AM		 5262/* md_estimate_size_before_relax()
5263
5264 Called just before relax() for rs_machine_dependent frags. The x86
5265 assembler uses these frags to handle variable size jump
5266 instructions.
5267
5268 Any symbol that is now undefined will not become defined.
5269 Return the correct fr_subtype in the frag.
5270 Return the initial "guess for variable size of frag" to caller.
5271 The guess is actually the growth beyond the fixed part. Whatever
5272 we do to grow the fixed or variable part contributes to our
5273 returned value. */
5274
252b5132
RH		 5275int
5276md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 5277 fragS *fragP;
5278 segT segment;
252b5132 5279{
252b5132 5280 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 5281 check for un-relaxable symbols. On an ELF system, we can't relax
5282 an externally visible symbol, because it may be overridden by a
5283 shared library. */
5284 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 5285#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5286 || (IS_ELF
31312f95
AM		 5287 && (S_IS_EXTERNAL (fragP->fr_symbol)
5288 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 5289#endif
5290 )
252b5132 5291 {
b98ef147
AM		 5292 /* Symbol is undefined in this segment, or we need to keep a
5293 reloc so that weak symbols can be overridden. */
5294 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 5295 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 5296 unsigned char *opcode;
5297 int old_fr_fix;
f6af82bd 5298
ee7fcc42
AM		 5299 if (fragP->fr_var != NO_RELOC)
5300 reloc_type = fragP->fr_var;
b98ef147 5301 else if (size == 2)
f6af82bd
AM		 5302 reloc_type = BFD_RELOC_16_PCREL;
5303 else
5304 reloc_type = BFD_RELOC_32_PCREL;
252b5132 5305
ee7fcc42
AM		 5306 old_fr_fix = fragP->fr_fix;
5307 opcode = (unsigned char *) fragP->fr_opcode;
5308
fddf5b5b 5309 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 5310 {
fddf5b5b
AM		 5311 case UNCOND_JUMP:
5312 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 5313 opcode[0] = 0xe9;
252b5132 5314 fragP->fr_fix += size;
062cd5e7
AS		 5315 fix_new (fragP, old_fr_fix, size,
5316 fragP->fr_symbol,
5317 fragP->fr_offset, 1,
5318 reloc_type);
252b5132
RH		 5319 break;
5320
fddf5b5b 5321 case COND_JUMP86:
412167cb
AM		 5322 if (size == 2
5323 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 5324 {
5325 /* Negate the condition, and branch past an
5326 unconditional jump. */
5327 opcode[0] ^= 1;
5328 opcode[1] = 3;
5329 /* Insert an unconditional jump. */
5330 opcode[2] = 0xe9;
5331 /* We added two extra opcode bytes, and have a two byte
5332 offset. */
5333 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 5334 fix_new (fragP, old_fr_fix + 2, 2,
5335 fragP->fr_symbol,
5336 fragP->fr_offset, 1,
5337 reloc_type);
fddf5b5b
AM		 5338 break;
5339 }
5340 /* Fall through. */
5341
5342 case COND_JUMP:
412167cb
AM		 5343 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
5344 {
3e02c1cc
AM		 5345 fixS *fixP;
5346
412167cb 5347 fragP->fr_fix += 1;
3e02c1cc
AM		 5348 fixP = fix_new (fragP, old_fr_fix, 1,
5349 fragP->fr_symbol,
5350 fragP->fr_offset, 1,
5351 BFD_RELOC_8_PCREL);
5352 fixP->fx_signed = 1;
412167cb
AM		 5353 break;
5354 }
93c2a809 5355
24eab124 5356 /* This changes the byte-displacement jump 0x7N
fddf5b5b 5357 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 5358 opcode[1] = opcode[0] + 0x10;
f6af82bd 5359 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 5360 /* We've added an opcode byte. */
5361 fragP->fr_fix += 1 + size;
062cd5e7
AS		 5362 fix_new (fragP, old_fr_fix + 1, size,
5363 fragP->fr_symbol,
5364 fragP->fr_offset, 1,
5365 reloc_type);
252b5132 5366 break;
fddf5b5b
AM		 5367
5368 default:
5369 BAD_CASE (fragP->fr_subtype);
5370 break;
252b5132
RH		 5371 }
5372 frag_wane (fragP);
ee7fcc42 5373 return fragP->fr_fix - old_fr_fix;
252b5132 5374 }
93c2a809 5375
93c2a809
AM		 5376 /* Guess size depending on current relax state. Initially the relax
5377 state will correspond to a short jump and we return 1, because
5378 the variable part of the frag (the branch offset) is one byte
5379 long. However, we can relax a section more than once and in that
5380 case we must either set fr_subtype back to the unrelaxed state,
5381 or return the value for the appropriate branch. */
5382 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 5383}
5384
47926f60
KH		 5385/* Called after relax() is finished.
5386
5387 In: Address of frag.
5388 fr_type == rs_machine_dependent.
5389 fr_subtype is what the address relaxed to.
5390
5391 Out: Any fixSs and constants are set up.
5392 Caller will turn frag into a ".space 0". */
5393
252b5132
RH		 5394void
5395md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 5396 bfd *abfd ATTRIBUTE_UNUSED;
5397 segT sec ATTRIBUTE_UNUSED;
29b0f896 5398 fragS *fragP;
252b5132 5399{
29b0f896 5400 unsigned char *opcode;
252b5132 5401 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 5402 offsetT target_address;
5403 offsetT opcode_address;
252b5132 5404 unsigned int extension = 0;
847f7ad4 5405 offsetT displacement_from_opcode_start;
252b5132
RH		 5406
5407 opcode = (unsigned char *) fragP->fr_opcode;
5408
47926f60 5409 /* Address we want to reach in file space. */
252b5132 5410 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 5411
47926f60 5412 /* Address opcode resides at in file space. */
252b5132
RH		 5413 opcode_address = fragP->fr_address + fragP->fr_fix;
5414
47926f60 5415 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 5416 displacement_from_opcode_start = target_address - opcode_address;
5417
fddf5b5b 5418 if ((fragP->fr_subtype & BIG) == 0)
252b5132 5419 {
47926f60
KH		 5420 /* Don't have to change opcode. */
5421 extension = 1; /* 1 opcode + 1 displacement */
252b5132 5422 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 5423 }
5424 else
5425 {
5426 if (no_cond_jump_promotion
5427 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 5428 as_warn_where (fragP->fr_file, fragP->fr_line,
5429 _("long jump required"));
252b5132 5430
fddf5b5b
AM		 5431 switch (fragP->fr_subtype)
5432 {
5433 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
5434 extension = 4; /* 1 opcode + 4 displacement */
5435 opcode[0] = 0xe9;
5436 where_to_put_displacement = &opcode[1];
5437 break;
252b5132 5438
fddf5b5b
AM		 5439 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
5440 extension = 2; /* 1 opcode + 2 displacement */
5441 opcode[0] = 0xe9;
5442 where_to_put_displacement = &opcode[1];
5443 break;
252b5132 5444
fddf5b5b
AM		 5445 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
5446 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
5447 extension = 5; /* 2 opcode + 4 displacement */
5448 opcode[1] = opcode[0] + 0x10;
5449 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5450 where_to_put_displacement = &opcode[2];
5451 break;
252b5132 5452
fddf5b5b
AM		 5453 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
5454 extension = 3; /* 2 opcode + 2 displacement */
5455 opcode[1] = opcode[0] + 0x10;
5456 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5457 where_to_put_displacement = &opcode[2];
5458 break;
252b5132 5459
fddf5b5b
AM		 5460 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
5461 extension = 4;
5462 opcode[0] ^= 1;
5463 opcode[1] = 3;
5464 opcode[2] = 0xe9;
5465 where_to_put_displacement = &opcode[3];
5466 break;
5467
5468 default:
5469 BAD_CASE (fragP->fr_subtype);
5470 break;
5471 }
252b5132 5472 }
fddf5b5b 5473
7b81dfbb
AJ		 5474 /* If size if less then four we are sure that the operand fits,
5475 but if it's 4, then it could be that the displacement is larger
5476 then -/+ 2GB. */
5477 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
5478 && object_64bit
5479 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 5480 + ((addressT) 1 << 31))
5481 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 5482 {
5483 as_bad_where (fragP->fr_file, fragP->fr_line,
5484 _("jump target out of range"));
5485 /* Make us emit 0. */
5486 displacement_from_opcode_start = extension;
5487 }
47926f60 5488 /* Now put displacement after opcode. */
252b5132
RH		 5489 md_number_to_chars ((char *) where_to_put_displacement,
5490 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 5491 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 5492 fragP->fr_fix += extension;
5493}
5494\f
47926f60
KH		 5495/* Size of byte displacement jmp. */
5496int md_short_jump_size = 2;
5497
5498/* Size of dword displacement jmp. */
5499int md_long_jump_size = 5;
252b5132 5500
252b5132
RH		 5501void
5502md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
5503 char *ptr;
5504 addressT from_addr, to_addr;
ab9da554
ILT		 5505 fragS *frag ATTRIBUTE_UNUSED;
5506 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 5507{
847f7ad4 5508 offsetT offset;
252b5132
RH		 5509
5510 offset = to_addr - (from_addr + 2);
47926f60
KH		 5511 /* Opcode for byte-disp jump. */
5512 md_number_to_chars (ptr, (valueT) 0xeb, 1);
252b5132
RH		 5513 md_number_to_chars (ptr + 1, (valueT) offset, 1);
5514}
5515
5516void
5517md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
5518 char *ptr;
5519 addressT from_addr, to_addr;
a38cf1db
AM		 5520 fragS *frag ATTRIBUTE_UNUSED;
5521 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 5522{
847f7ad4 5523 offsetT offset;
252b5132 5524
a38cf1db
AM		 5525 offset = to_addr - (from_addr + 5);
5526 md_number_to_chars (ptr, (valueT) 0xe9, 1);
5527 md_number_to_chars (ptr + 1, (valueT) offset, 4);
252b5132
RH		 5528}
5529\f
5530/* Apply a fixup (fixS) to segment data, once it has been determined
5531 by our caller that we have all the info we need to fix it up.
5532
5533 On the 386, immediates, displacements, and data pointers are all in
5534 the same (little-endian) format, so we don't need to care about which
5535 we are handling. */
5536
94f592af 5537void
55cf6793 5538md_apply_fix (fixP, valP, seg)
47926f60
KH		 5539 /* The fix we're to put in. */
5540 fixS *fixP;
47926f60 5541 /* Pointer to the value of the bits. */
c6682705 5542 valueT *valP;
47926f60
KH		 5543 /* Segment fix is from. */
5544 segT seg ATTRIBUTE_UNUSED;
252b5132 5545{
94f592af 5546 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 5547 valueT value = *valP;
252b5132 5548
f86103b7 5549#if !defined (TE_Mach)
93382f6d
AM		 5550 if (fixP->fx_pcrel)
5551 {
5552 switch (fixP->fx_r_type)
5553 {
5865bb77
ILT		 5554 default:
5555 break;
5556
d6ab8113
JB		 5557 case BFD_RELOC_64:
5558 fixP->fx_r_type = BFD_RELOC_64_PCREL;
5559 break;
93382f6d 5560 case BFD_RELOC_32:
ae8887b5 5561 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 5562 fixP->fx_r_type = BFD_RELOC_32_PCREL;
5563 break;
5564 case BFD_RELOC_16:
5565 fixP->fx_r_type = BFD_RELOC_16_PCREL;
5566 break;
5567 case BFD_RELOC_8:
5568 fixP->fx_r_type = BFD_RELOC_8_PCREL;
5569 break;
5570 }
5571 }
252b5132 5572
a161fe53 5573 if (fixP->fx_addsy != NULL
31312f95 5574 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 5575 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 5576 || fixP->fx_r_type == BFD_RELOC_16_PCREL
5577 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
5578 && !use_rela_relocations)
252b5132 5579 {
31312f95
AM		 5580 /* This is a hack. There should be a better way to handle this.
5581 This covers for the fact that bfd_install_relocation will
5582 subtract the current location (for partial_inplace, PC relative
5583 relocations); see more below. */
252b5132 5584#ifndef OBJ_AOUT
718ddfc0 5585 if (IS_ELF
252b5132
RH		 5586#ifdef TE_PE
5587 || OUTPUT_FLAVOR == bfd_target_coff_flavour
5588#endif
5589 )
5590 value += fixP->fx_where + fixP->fx_frag->fr_address;
5591#endif
5592#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5593 if (IS_ELF)
252b5132 5594 {
6539b54b 5595 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 5596
6539b54b 5597 if ((sym_seg == seg
2f66722d 5598 || (symbol_section_p (fixP->fx_addsy)
6539b54b 5599 && sym_seg != absolute_section))
ae6063d4 5600 && !generic_force_reloc (fixP))
2f66722d
AM		 5601 {
5602 /* Yes, we add the values in twice. This is because
6539b54b
AM		 5603 bfd_install_relocation subtracts them out again. I think
5604 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 5605 it. FIXME. */
5606 value += fixP->fx_where + fixP->fx_frag->fr_address;
5607 }
252b5132
RH		 5608 }
5609#endif
5610#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 5611 /* For some reason, the PE format does not store a
5612 section address offset for a PC relative symbol. */
5613 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 5614 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 5615 value += md_pcrel_from (fixP);
5616#endif
5617 }
5618
5619 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 5620 and we must not disappoint it. */
252b5132 5621#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5622 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 5623 switch (fixP->fx_r_type)
5624 {
5625 case BFD_RELOC_386_PLT32:
3e73aa7c 5626 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 5627 /* Make the jump instruction point to the address of the operand. At
5628 runtime we merely add the offset to the actual PLT entry. */
5629 value = -4;
5630 break;
31312f95 5631
13ae64f3
JJ		 5632 case BFD_RELOC_386_TLS_GD:
5633 case BFD_RELOC_386_TLS_LDM:
13ae64f3 5634 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 5635 case BFD_RELOC_386_TLS_IE:
5636 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 5637 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 5638 case BFD_RELOC_X86_64_TLSGD:
5639 case BFD_RELOC_X86_64_TLSLD:
5640 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 5641 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 5642 value = 0; /* Fully resolved at runtime. No addend. */
5643 /* Fallthrough */
5644 case BFD_RELOC_386_TLS_LE:
5645 case BFD_RELOC_386_TLS_LDO_32:
5646 case BFD_RELOC_386_TLS_LE_32:
5647 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 5648 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 5649 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 5650 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 5651 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5652 break;
5653
67a4f2b7
AO		 5654 case BFD_RELOC_386_TLS_DESC_CALL:
5655 case BFD_RELOC_X86_64_TLSDESC_CALL:
5656 value = 0; /* Fully resolved at runtime. No addend. */
5657 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5658 fixP->fx_done = 0;
5659 return;
5660
00f7efb6
JJ		 5661 case BFD_RELOC_386_GOT32:
5662 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 5663 value = 0; /* Fully resolved at runtime. No addend. */
5664 break;
47926f60
KH		 5665
5666 case BFD_RELOC_VTABLE_INHERIT:
5667 case BFD_RELOC_VTABLE_ENTRY:
5668 fixP->fx_done = 0;
94f592af 5669 return;
47926f60
KH		 5670
5671 default:
5672 break;
5673 }
5674#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 5675 *valP = value;
f86103b7 5676#endif /* !defined (TE_Mach) */
3e73aa7c 5677
3e73aa7c 5678 /* Are we finished with this relocation now? */
c6682705 5679 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 5680 fixP->fx_done = 1;
5681 else if (use_rela_relocations)
5682 {
5683 fixP->fx_no_overflow = 1;
062cd5e7
AS		 5684 /* Remember value for tc_gen_reloc. */
5685 fixP->fx_addnumber = value;
3e73aa7c
JH		 5686 value = 0;
5687 }
f86103b7 5688
94f592af 5689 md_number_to_chars (p, value, fixP->fx_size);
252b5132 5690}
252b5132 5691\f
252b5132
RH		 5692#define MAX_LITTLENUMS 6
5693
47926f60
KH		 5694/* Turn the string pointed to by litP into a floating point constant
5695 of type TYPE, and emit the appropriate bytes. The number of
5696 LITTLENUMS emitted is stored in *SIZEP. An error message is
5697 returned, or NULL on OK. */
5698
252b5132
RH		 5699char *
5700md_atof (type, litP, sizeP)
2ab9b79e 5701 int type;
252b5132
RH		 5702 char *litP;
5703 int *sizeP;
5704{
5705 int prec;
5706 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5707 LITTLENUM_TYPE *wordP;
5708 char *t;
5709
5710 switch (type)
5711 {
5712 case 'f':
5713 case 'F':
5714 prec = 2;
5715 break;
5716
5717 case 'd':
5718 case 'D':
5719 prec = 4;
5720 break;
5721
5722 case 'x':
5723 case 'X':
5724 prec = 5;
5725 break;
5726
5727 default:
5728 *sizeP = 0;
5729 return _("Bad call to md_atof ()");
5730 }
5731 t = atof_ieee (input_line_pointer, type, words);
5732 if (t)
5733 input_line_pointer = t;
5734
5735 *sizeP = prec * sizeof (LITTLENUM_TYPE);
5736 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5737 the bigendian 386. */
5738 for (wordP = words + prec - 1; prec--;)
5739 {
5740 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
5741 litP += sizeof (LITTLENUM_TYPE);
5742 }
5743 return 0;
5744}
5745\f
2d545b82 5746static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 5747
252b5132 5748static char *
e3bb37b5 5749output_invalid (int c)
252b5132 5750{
3882b010 5751 if (ISPRINT (c))
f9f21a03
L		 5752 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
5753 "'%c'", c);
252b5132 5754 else
f9f21a03 5755 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 5756 "(0x%x)", (unsigned char) c);
252b5132
RH		 5757 return output_invalid_buf;
5758}
5759
af6bdddf 5760/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 5761
5762static const reg_entry *
4d1bb795 5763parse_real_register (char *reg_string, char **end_op)
252b5132 5764{
af6bdddf
AM		 5765 char *s = reg_string;
5766 char *p;
252b5132
RH		 5767 char reg_name_given[MAX_REG_NAME_SIZE + 1];
5768 const reg_entry *r;
5769
5770 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5771 if (*s == REGISTER_PREFIX)
5772 ++s;
5773
5774 if (is_space_char (*s))
5775 ++s;
5776
5777 p = reg_name_given;
af6bdddf 5778 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 5779 {
5780 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 5781 return (const reg_entry *) NULL;
5782 s++;
252b5132
RH		 5783 }
5784
6588847e
DN		 5785 /* For naked regs, make sure that we are not dealing with an identifier.
5786 This prevents confusing an identifier like `eax_var' with register
5787 `eax'. */
5788 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
5789 return (const reg_entry *) NULL;
5790
af6bdddf 5791 *end_op = s;
252b5132
RH		 5792
5793 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
5794
5f47d35b 5795 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 5796 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 5797 {
5f47d35b
AM		 5798 if (is_space_char (*s))
5799 ++s;
5800 if (*s == '(')
5801 {
af6bdddf 5802 ++s;
5f47d35b
AM		 5803 if (is_space_char (*s))
5804 ++s;
5805 if (*s >= '0' && *s <= '7')
5806 {
5807 r = &i386_float_regtab[*s - '0'];
af6bdddf 5808 ++s;
5f47d35b
AM		 5809 if (is_space_char (*s))
5810 ++s;
5811 if (*s == ')')
5812 {
5813 *end_op = s + 1;
5814 return r;
5815 }
5f47d35b 5816 }
47926f60 5817 /* We have "%st(" then garbage. */
5f47d35b
AM		 5818 return (const reg_entry *) NULL;
5819 }
5820 }
5821
1ae00879 5822 if (r != NULL
20f0a1fc 5823 && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0
c4a530c5 5824 && (r->reg_type != Control || !(cpu_arch_flags & CpuSledgehammer))
1ae00879 5825 && flag_code != CODE_64BIT)
20f0a1fc 5826 return (const reg_entry *) NULL;
1ae00879 5827
252b5132
RH		 5828 return r;
5829}
4d1bb795
JB		 5830
5831/* REG_STRING starts *before* REGISTER_PREFIX. */
5832
5833static const reg_entry *
5834parse_register (char *reg_string, char **end_op)
5835{
5836 const reg_entry *r;
5837
5838 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
5839 r = parse_real_register (reg_string, end_op);
5840 else
5841 r = NULL;
5842 if (!r)
5843 {
5844 char *save = input_line_pointer;
5845 char c;
5846 symbolS *symbolP;
5847
5848 input_line_pointer = reg_string;
5849 c = get_symbol_end ();
5850 symbolP = symbol_find (reg_string);
5851 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
5852 {
5853 const expressionS *e = symbol_get_value_expression (symbolP);
5854
5855 know (e->X_op == O_register);
4eed87de 5856 know (e->X_add_number >= 0
c3fe08fa 5857 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 5858 r = i386_regtab + e->X_add_number;
5859 *end_op = input_line_pointer;
5860 }
5861 *input_line_pointer = c;
5862 input_line_pointer = save;
5863 }
5864 return r;
5865}
5866
5867int
5868i386_parse_name (char *name, expressionS *e, char *nextcharP)
5869{
5870 const reg_entry *r;
5871 char *end = input_line_pointer;
5872
5873 *end = *nextcharP;
5874 r = parse_register (name, &input_line_pointer);
5875 if (r && end <= input_line_pointer)
5876 {
5877 *nextcharP = *input_line_pointer;
5878 *input_line_pointer = 0;
5879 e->X_op = O_register;
5880 e->X_add_number = r - i386_regtab;
5881 return 1;
5882 }
5883 input_line_pointer = end;
5884 *end = 0;
5885 return 0;
5886}
5887
5888void
5889md_operand (expressionS *e)
5890{
5891 if (*input_line_pointer == REGISTER_PREFIX)
5892 {
5893 char *end;
5894 const reg_entry *r = parse_real_register (input_line_pointer, &end);
5895
5896 if (r)
5897 {
5898 e->X_op = O_register;
5899 e->X_add_number = r - i386_regtab;
5900 input_line_pointer = end;
5901 }
5902 }
5903}
5904
252b5132 5905\f
4cc782b5 5906#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 5907const char *md_shortopts = "kVQ:sqn";
252b5132 5908#else
12b55ccc 5909const char *md_shortopts = "qn";
252b5132 5910#endif
6e0b89ee 5911
3e73aa7c 5912#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 5913#define OPTION_64 (OPTION_MD_BASE + 1)
5914#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 5915#define OPTION_MARCH (OPTION_MD_BASE + 3)
5916#define OPTION_MTUNE (OPTION_MD_BASE + 4)
b3b91714 5917
99ad8390
NC		 5918struct option md_longopts[] =
5919{
3e73aa7c 5920 {"32", no_argument, NULL, OPTION_32},
99ad8390 5921#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c 5922 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 5923#endif
b3b91714 5924 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 5925 {"march", required_argument, NULL, OPTION_MARCH},
5926 {"mtune", required_argument, NULL, OPTION_MTUNE},
252b5132
RH		 5927 {NULL, no_argument, NULL, 0}
5928};
5929size_t md_longopts_size = sizeof (md_longopts);
5930
5931int
9103f4f4 5932md_parse_option (int c, char *arg)
252b5132 5933{
9103f4f4
L		 5934 unsigned int i;
5935
252b5132
RH		 5936 switch (c)
5937 {
12b55ccc
L		 5938 case 'n':
5939 optimize_align_code = 0;
5940 break;
5941
a38cf1db
AM		 5942 case 'q':
5943 quiet_warnings = 1;
252b5132
RH		 5944 break;
5945
5946#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 5947 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5948 should be emitted or not. FIXME: Not implemented. */
5949 case 'Q':
252b5132
RH		 5950 break;
5951
5952 /* -V: SVR4 argument to print version ID. */
5953 case 'V':
5954 print_version_id ();
5955 break;
5956
a38cf1db
AM		 5957 /* -k: Ignore for FreeBSD compatibility. */
5958 case 'k':
252b5132 5959 break;
4cc782b5
ILT		 5960
5961 case 's':
5962 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 5963 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 5964 break;
99ad8390
NC		 5965#endif
5966#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c
JH		 5967 case OPTION_64:
5968 {
5969 const char **list, **l;
5970
3e73aa7c
JH		 5971 list = bfd_target_list ();
5972 for (l = list; *l != NULL; l++)
8620418b 5973 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 5974 || strcmp (*l, "coff-x86-64") == 0
5975 || strcmp (*l, "pe-x86-64") == 0
5976 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 5977 {
5978 default_arch = "x86_64";
5979 break;
5980 }
3e73aa7c 5981 if (*l == NULL)
6e0b89ee 5982 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 5983 free (list);
5984 }
5985 break;
5986#endif
252b5132 5987
6e0b89ee
AM		 5988 case OPTION_32:
5989 default_arch = "i386";
5990 break;
5991
b3b91714
AM		 5992 case OPTION_DIVIDE:
5993#ifdef SVR4_COMMENT_CHARS
5994 {
5995 char *n, *t;
5996 const char *s;
5997
5998 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
5999 t = n;
6000 for (s = i386_comment_chars; *s != '\0'; s++)
6001 if (*s != '/')
6002 *t++ = *s;
6003 *t = '\0';
6004 i386_comment_chars = n;
6005 }
6006#endif
6007 break;
6008
9103f4f4
L		 6009 case OPTION_MARCH:
6010 if (*arg == '.')
6011 as_fatal (_("Invalid -march= option: `%s'"), arg);
6012 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
6013 {
6014 if (strcmp (arg, cpu_arch [i].name) == 0)
6015 {
ccc9c027 6016 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 6017 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 6018 if (!cpu_arch_tune_set)
6019 {
6020 cpu_arch_tune = cpu_arch_isa;
6021 cpu_arch_tune_flags = cpu_arch_isa_flags;
6022 }
9103f4f4
L		 6023 break;
6024 }
6025 }
6026 if (i >= ARRAY_SIZE (cpu_arch))
6027 as_fatal (_("Invalid -march= option: `%s'"), arg);
6028 break;
6029
6030 case OPTION_MTUNE:
6031 if (*arg == '.')
6032 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
6033 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
6034 {
6035 if (strcmp (arg, cpu_arch [i].name) == 0)
6036 {
ccc9c027 6037 cpu_arch_tune_set = 1;
9103f4f4
L		 6038 cpu_arch_tune = cpu_arch [i].type;
6039 cpu_arch_tune_flags = cpu_arch[i].flags;
6040 break;
6041 }
6042 }
6043 if (i >= ARRAY_SIZE (cpu_arch))
6044 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
6045 break;
6046
252b5132
RH		 6047 default:
6048 return 0;
6049 }
6050 return 1;
6051}
6052
6053void
6054md_show_usage (stream)
6055 FILE *stream;
6056{
4cc782b5
ILT		 6057#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6058 fprintf (stream, _("\
a38cf1db
AM		 6059 -Q ignored\n\
6060 -V print assembler version number\n\
b3b91714
AM		 6061 -k ignored\n"));
6062#endif
6063 fprintf (stream, _("\
12b55ccc 6064 -n Do not optimize code alignment\n\
b3b91714
AM		 6065 -q quieten some warnings\n"));
6066#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6067 fprintf (stream, _("\
a38cf1db 6068 -s ignored\n"));
b3b91714 6069#endif
751d281c
L		 6070#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
6071 fprintf (stream, _("\
6072 --32/--64 generate 32bit/64bit code\n"));
6073#endif
b3b91714
AM		 6074#ifdef SVR4_COMMENT_CHARS
6075 fprintf (stream, _("\
6076 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 6077#else
6078 fprintf (stream, _("\
b3b91714 6079 --divide ignored\n"));
4cc782b5 6080#endif
9103f4f4
L		 6081 fprintf (stream, _("\
6082 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
6083 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
4eed87de 6084 core, core2, k6, athlon, k8, generic32, generic64\n"));
9103f4f4 6085
252b5132
RH		 6086}
6087
99ad8390
NC		 6088#if defined(TE_PEP)
6089const char *
6090x86_64_target_format (void)
6091{
6092 if (strcmp (default_arch, "x86_64") == 0)
6093 {
6094 set_code_flag (CODE_64BIT);
6095 return COFF_TARGET_FORMAT;
6096 }
6097 else if (strcmp (default_arch, "i386") == 0)
6098 {
6099 set_code_flag (CODE_32BIT);
6100 return "coff-i386";
6101 }
6102
6103 as_fatal (_("Unknown architecture"));
6104 return NULL;
6105}
6106#endif
6107
3e73aa7c
JH		 6108#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
6109 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
252b5132
RH		 6110
6111/* Pick the target format to use. */
6112
47926f60 6113const char *
e3bb37b5 6114i386_target_format (void)
252b5132 6115{
3e73aa7c 6116 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 6117 {
6118 set_code_flag (CODE_64BIT);
6119 if (cpu_arch_isa_flags == 0)
d32cad65 6120 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386|Cpu486
9103f4f4
L		 6121 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
6122 |CpuSSE|CpuSSE2;
ccc9c027 6123 if (cpu_arch_tune_flags == 0)
d32cad65 6124 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386|Cpu486
ccc9c027
L		 6125 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
6126 |CpuSSE|CpuSSE2;
9103f4f4 6127 }
3e73aa7c 6128 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 6129 {
6130 set_code_flag (CODE_32BIT);
6131 if (cpu_arch_isa_flags == 0)
d32cad65 6132 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386;
ccc9c027 6133 if (cpu_arch_tune_flags == 0)
d32cad65 6134 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386;
9103f4f4 6135 }
3e73aa7c
JH		 6136 else
6137 as_fatal (_("Unknown architecture"));
252b5132
RH		 6138 switch (OUTPUT_FLAVOR)
6139 {
4c63da97
AM		 6140#ifdef OBJ_MAYBE_AOUT
6141 case bfd_target_aout_flavour:
47926f60 6142 return AOUT_TARGET_FORMAT;
4c63da97
AM		 6143#endif
6144#ifdef OBJ_MAYBE_COFF
252b5132
RH		 6145 case bfd_target_coff_flavour:
6146 return "coff-i386";
4c63da97 6147#endif
3e73aa7c 6148#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 6149 case bfd_target_elf_flavour:
3e73aa7c 6150 {
e5cb08ac 6151 if (flag_code == CODE_64BIT)
4fa24527
JB		 6152 {
6153 object_64bit = 1;
6154 use_rela_relocations = 1;
6155 }
9d7cbccd 6156 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
3e73aa7c 6157 }
4c63da97 6158#endif
252b5132
RH		 6159 default:
6160 abort ();
6161 return NULL;
6162 }
6163}
6164
47926f60 6165#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 6166
6167#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 6168void
6169i386_elf_emit_arch_note (void)
a847613f 6170{
718ddfc0 6171 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 6172 {
6173 char *p;
6174 asection *seg = now_seg;
6175 subsegT subseg = now_subseg;
6176 Elf_Internal_Note i_note;
6177 Elf_External_Note e_note;
6178 asection *note_secp;
6179 int len;
6180
6181 /* Create the .note section. */
6182 note_secp = subseg_new (".note", 0);
6183 bfd_set_section_flags (stdoutput,
6184 note_secp,
6185 SEC_HAS_CONTENTS | SEC_READONLY);
6186
6187 /* Process the arch string. */
6188 len = strlen (cpu_arch_name);
6189
6190 i_note.namesz = len + 1;
6191 i_note.descsz = 0;
6192 i_note.type = NT_ARCH;
6193 p = frag_more (sizeof (e_note.namesz));
6194 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
6195 p = frag_more (sizeof (e_note.descsz));
6196 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
6197 p = frag_more (sizeof (e_note.type));
6198 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
6199 p = frag_more (len + 1);
6200 strcpy (p, cpu_arch_name);
6201
6202 frag_align (2, 0, 0);
6203
6204 subseg_set (seg, subseg);
6205 }
6206}
6207#endif
252b5132 6208\f
252b5132
RH		 6209symbolS *
6210md_undefined_symbol (name)
6211 char *name;
6212{
18dc2407
ILT		 6213 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
6214 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
6215 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
6216 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 6217 {
6218 if (!GOT_symbol)
6219 {
6220 if (symbol_find (name))
6221 as_bad (_("GOT already in symbol table"));
6222 GOT_symbol = symbol_new (name, undefined_section,
6223 (valueT) 0, &zero_address_frag);
6224 };
6225 return GOT_symbol;
6226 }
252b5132
RH		 6227 return 0;
6228}
6229
6230/* Round up a section size to the appropriate boundary. */
47926f60 6231
252b5132
RH		 6232valueT
6233md_section_align (segment, size)
ab9da554 6234 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 6235 valueT size;
6236{
4c63da97
AM		 6237#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6238 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
6239 {
6240 /* For a.out, force the section size to be aligned. If we don't do
6241 this, BFD will align it for us, but it will not write out the
6242 final bytes of the section. This may be a bug in BFD, but it is
6243 easier to fix it here since that is how the other a.out targets
6244 work. */
6245 int align;
6246
6247 align = bfd_get_section_alignment (stdoutput, segment);
6248 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
6249 }
252b5132
RH		 6250#endif
6251
6252 return size;
6253}
6254
6255/* On the i386, PC-relative offsets are relative to the start of the
6256 next instruction. That is, the address of the offset, plus its
6257 size, since the offset is always the last part of the insn. */
6258
6259long
e3bb37b5 6260md_pcrel_from (fixS *fixP)
252b5132
RH		 6261{
6262 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
6263}
6264
6265#ifndef I386COFF
6266
6267static void
e3bb37b5 6268s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 6269{
29b0f896 6270 int temp;
252b5132 6271
8a75718c
JB		 6272#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6273 if (IS_ELF)
6274 obj_elf_section_change_hook ();
6275#endif
252b5132
RH		 6276 temp = get_absolute_expression ();
6277 subseg_set (bss_section, (subsegT) temp);
6278 demand_empty_rest_of_line ();
6279}
6280
6281#endif
6282
252b5132 6283void
e3bb37b5 6284i386_validate_fix (fixS *fixp)
252b5132
RH		 6285{
6286 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
6287 {
23df1078
JH		 6288 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
6289 {
4fa24527 6290 if (!object_64bit)
23df1078
JH		 6291 abort ();
6292 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
6293 }
6294 else
6295 {
4fa24527 6296 if (!object_64bit)
d6ab8113
JB		 6297 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
6298 else
6299 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 6300 }
252b5132
RH		 6301 fixp->fx_subsy = 0;
6302 }
6303}
6304
252b5132
RH		 6305arelent *
6306tc_gen_reloc (section, fixp)
ab9da554 6307 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 6308 fixS *fixp;
6309{
6310 arelent *rel;
6311 bfd_reloc_code_real_type code;
6312
6313 switch (fixp->fx_r_type)
6314 {
3e73aa7c
JH		 6315 case BFD_RELOC_X86_64_PLT32:
6316 case BFD_RELOC_X86_64_GOT32:
6317 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 6318 case BFD_RELOC_386_PLT32:
6319 case BFD_RELOC_386_GOT32:
6320 case BFD_RELOC_386_GOTOFF:
6321 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 6322 case BFD_RELOC_386_TLS_GD:
6323 case BFD_RELOC_386_TLS_LDM:
6324 case BFD_RELOC_386_TLS_LDO_32:
6325 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 6326 case BFD_RELOC_386_TLS_IE:
6327 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 6328 case BFD_RELOC_386_TLS_LE_32:
6329 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 6330 case BFD_RELOC_386_TLS_GOTDESC:
6331 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 6332 case BFD_RELOC_X86_64_TLSGD:
6333 case BFD_RELOC_X86_64_TLSLD:
6334 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 6335 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 6336 case BFD_RELOC_X86_64_GOTTPOFF:
6337 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 6338 case BFD_RELOC_X86_64_TPOFF64:
6339 case BFD_RELOC_X86_64_GOTOFF64:
6340 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 6341 case BFD_RELOC_X86_64_GOT64:
6342 case BFD_RELOC_X86_64_GOTPCREL64:
6343 case BFD_RELOC_X86_64_GOTPC64:
6344 case BFD_RELOC_X86_64_GOTPLT64:
6345 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 6346 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6347 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 6348 case BFD_RELOC_RVA:
6349 case BFD_RELOC_VTABLE_ENTRY:
6350 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 6351#ifdef TE_PE
6352 case BFD_RELOC_32_SECREL:
6353#endif
252b5132
RH		 6354 code = fixp->fx_r_type;
6355 break;
dbbaec26
L		 6356 case BFD_RELOC_X86_64_32S:
6357 if (!fixp->fx_pcrel)
6358 {
6359 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
6360 code = fixp->fx_r_type;
6361 break;
6362 }
252b5132 6363 default:
93382f6d 6364 if (fixp->fx_pcrel)
252b5132 6365 {
93382f6d
AM		 6366 switch (fixp->fx_size)
6367 {
6368 default:
b091f402
AM		 6369 as_bad_where (fixp->fx_file, fixp->fx_line,
6370 _("can not do %d byte pc-relative relocation"),
6371 fixp->fx_size);
93382f6d
AM		 6372 code = BFD_RELOC_32_PCREL;
6373 break;
6374 case 1: code = BFD_RELOC_8_PCREL; break;
6375 case 2: code = BFD_RELOC_16_PCREL; break;
6376 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 6377#ifdef BFD64
6378 case 8: code = BFD_RELOC_64_PCREL; break;
6379#endif
93382f6d
AM		 6380 }
6381 }
6382 else
6383 {
6384 switch (fixp->fx_size)
6385 {
6386 default:
b091f402
AM		 6387 as_bad_where (fixp->fx_file, fixp->fx_line,
6388 _("can not do %d byte relocation"),
6389 fixp->fx_size);
93382f6d
AM		 6390 code = BFD_RELOC_32;
6391 break;
6392 case 1: code = BFD_RELOC_8; break;
6393 case 2: code = BFD_RELOC_16; break;
6394 case 4: code = BFD_RELOC_32; break;
937149dd 6395#ifdef BFD64
3e73aa7c 6396 case 8: code = BFD_RELOC_64; break;
937149dd 6397#endif
93382f6d 6398 }
252b5132
RH		 6399 }
6400 break;
6401 }
252b5132 6402
d182319b
JB		 6403 if ((code == BFD_RELOC_32
6404 || code == BFD_RELOC_32_PCREL
6405 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 6406 && GOT_symbol
6407 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 6408 {
4fa24527 6409 if (!object_64bit)
d6ab8113
JB		 6410 code = BFD_RELOC_386_GOTPC;
6411 else
6412 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 6413 }
7b81dfbb
AJ		 6414 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
6415 && GOT_symbol
6416 && fixp->fx_addsy == GOT_symbol)
6417 {
6418 code = BFD_RELOC_X86_64_GOTPC64;
6419 }
252b5132
RH		 6420
6421 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 6422 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
6423 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 6424
6425 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 6426
3e73aa7c
JH		 6427 if (!use_rela_relocations)
6428 {
6429 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
6430 vtable entry to be used in the relocation's section offset. */
6431 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
6432 rel->address = fixp->fx_offset;
252b5132 6433
c6682705 6434 rel->addend = 0;
3e73aa7c
JH		 6435 }
6436 /* Use the rela in 64bit mode. */
252b5132 6437 else
3e73aa7c 6438 {
062cd5e7
AS		 6439 if (!fixp->fx_pcrel)
6440 rel->addend = fixp->fx_offset;
6441 else
6442 switch (code)
6443 {
6444 case BFD_RELOC_X86_64_PLT32:
6445 case BFD_RELOC_X86_64_GOT32:
6446 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 6447 case BFD_RELOC_X86_64_TLSGD:
6448 case BFD_RELOC_X86_64_TLSLD:
6449 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 6450 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6451 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 6452 rel->addend = fixp->fx_offset - fixp->fx_size;
6453 break;
6454 default:
6455 rel->addend = (section->vma
6456 - fixp->fx_size
6457 + fixp->fx_addnumber
6458 + md_pcrel_from (fixp));
6459 break;
6460 }
3e73aa7c
JH		 6461 }
6462
252b5132
RH		 6463 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
6464 if (rel->howto == NULL)
6465 {
6466 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 6467 _("cannot represent relocation type %s"),
252b5132
RH		 6468 bfd_get_reloc_code_name (code));
6469 /* Set howto to a garbage value so that we can keep going. */
6470 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
6471 assert (rel->howto != NULL);
6472 }
6473
6474 return rel;
6475}
6476
64a0c779
DN		 6477\f
6478/* Parse operands using Intel syntax. This implements a recursive descent
6479 parser based on the BNF grammar published in Appendix B of the MASM 6.1
6480 Programmer's Guide.
6481
6482 FIXME: We do not recognize the full operand grammar defined in the MASM
6483 documentation. In particular, all the structure/union and
6484 high-level macro operands are missing.
6485
6486 Uppercase words are terminals, lower case words are non-terminals.
6487 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
6488 bars '|' denote choices. Most grammar productions are implemented in
6489 functions called 'intel_<production>'.
6490
6491 Initial production is 'expr'.
6492
9306ca4a 6493 addOp + | -
64a0c779
DN		 6494
6495 alpha [a-zA-Z]
6496
9306ca4a
JB		 6497 binOp & | AND | \| | OR | ^ | XOR
6498
64a0c779
DN		 6499 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
6500
6501 constant digits [[ radixOverride ]]
6502
9306ca4a 6503 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
64a0c779
DN		 6504
6505 digits decdigit
b77a7acd
AJ		 6506 | digits decdigit
6507 | digits hexdigit
64a0c779
DN		 6508
6509 decdigit [0-9]
6510
9306ca4a
JB		 6511 e04 e04 addOp e05
6512 | e05
6513
6514 e05 e05 binOp e06
b77a7acd 6515 | e06
64a0c779
DN		 6516
6517 e06 e06 mulOp e09
b77a7acd 6518 | e09
64a0c779
DN		 6519
6520 e09 OFFSET e10
a724f0f4
JB		 6521 | SHORT e10
6522 | + e10
6523 | - e10
9306ca4a
JB		 6524 | ~ e10
6525 | NOT e10
64a0c779
DN		 6526 | e09 PTR e10
6527 | e09 : e10
6528 | e10
6529
6530 e10 e10 [ expr ]
b77a7acd 6531 | e11
64a0c779
DN		 6532
6533 e11 ( expr )
b77a7acd 6534 | [ expr ]
64a0c779
DN		 6535 | constant
6536 | dataType
6537 | id
6538 | $
6539 | register
6540
a724f0f4 6541 => expr expr cmpOp e04
9306ca4a 6542 | e04
64a0c779
DN		 6543
6544 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 6545 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 6546
6547 hexdigit a | b | c | d | e | f
b77a7acd 6548 | A | B | C | D | E | F
64a0c779
DN		 6549
6550 id alpha
b77a7acd 6551 | id alpha
64a0c779
DN		 6552 | id decdigit
6553
9306ca4a 6554 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 6555
6556 quote " | '
6557
6558 register specialRegister
b77a7acd 6559 | gpRegister
64a0c779
DN		 6560 | byteRegister
6561
6562 segmentRegister CS | DS | ES | FS | GS | SS
6563
9306ca4a 6564 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 6565 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 6566 | TR3 | TR4 | TR5 | TR6 | TR7
6567
64a0c779
DN		 6568 We simplify the grammar in obvious places (e.g., register parsing is
6569 done by calling parse_register) and eliminate immediate left recursion
6570 to implement a recursive-descent parser.
6571
a724f0f4
JB		 6572 expr e04 expr'
6573
6574 expr' cmpOp e04 expr'
6575 | Empty
9306ca4a
JB		 6576
6577 e04 e05 e04'
6578
6579 e04' addOp e05 e04'
6580 | Empty
64a0c779
DN		 6581
6582 e05 e06 e05'
6583
9306ca4a 6584 e05' binOp e06 e05'
b77a7acd 6585 | Empty
64a0c779
DN		 6586
6587 e06 e09 e06'
6588
6589 e06' mulOp e09 e06'
b77a7acd 6590 | Empty
64a0c779
DN		 6591
6592 e09 OFFSET e10 e09'
a724f0f4
JB		 6593 | SHORT e10'
6594 | + e10'
6595 | - e10'
6596 | ~ e10'
6597 | NOT e10'
b77a7acd 6598 | e10 e09'
64a0c779
DN		 6599
6600 e09' PTR e10 e09'
b77a7acd 6601 | : e10 e09'
64a0c779
DN		 6602 | Empty
6603
6604 e10 e11 e10'
6605
6606 e10' [ expr ] e10'
b77a7acd 6607 | Empty
64a0c779
DN		 6608
6609 e11 ( expr )
b77a7acd 6610 | [ expr ]
64a0c779
DN		 6611 | BYTE
6612 | WORD
6613 | DWORD
9306ca4a 6614 | FWORD
64a0c779 6615 | QWORD
9306ca4a
JB		 6616 | TBYTE
6617 | OWORD
6618 | XMMWORD
64a0c779
DN		 6619 | .
6620 | $
6621 | register
6622 | id
6623 | constant */
6624
6625/* Parsing structure for the intel syntax parser. Used to implement the
6626 semantic actions for the operand grammar. */
6627struct intel_parser_s
6628 {
6629 char *op_string; /* The string being parsed. */
6630 int got_a_float; /* Whether the operand is a float. */
4a1805b1 6631 int op_modifier; /* Operand modifier. */
64a0c779 6632 int is_mem; /* 1 if operand is memory reference. */
4eed87de
AM		 6633 int in_offset; /* >=1 if parsing operand of offset. */
6634 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 6635 const reg_entry *reg; /* Last register reference found. */
6636 char *disp; /* Displacement string being built. */
a724f0f4 6637 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 6638 };
6639
6640static struct intel_parser_s intel_parser;
6641
6642/* Token structure for parsing intel syntax. */
6643struct intel_token
6644 {
6645 int code; /* Token code. */
6646 const reg_entry *reg; /* Register entry for register tokens. */
6647 char *str; /* String representation. */
6648 };
6649
6650static struct intel_token cur_token, prev_token;
6651
50705ef4
AM		 6652/* Token codes for the intel parser. Since T_SHORT is already used
6653 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 6654#define T_NIL -1
6655#define T_CONST 1
6656#define T_REG 2
6657#define T_BYTE 3
6658#define T_WORD 4
9306ca4a
JB		 6659#define T_DWORD 5
6660#define T_FWORD 6
6661#define T_QWORD 7
6662#define T_TBYTE 8
6663#define T_XMMWORD 9
50705ef4 6664#undef T_SHORT
9306ca4a
JB		 6665#define T_SHORT 10
6666#define T_OFFSET 11
6667#define T_PTR 12
6668#define T_ID 13
6669#define T_SHL 14
6670#define T_SHR 15
64a0c779
DN		 6671
6672/* Prototypes for intel parser functions. */
e3bb37b5
L		 6673static int intel_match_token (int);
6674static void intel_putback_token (void);
6675static void intel_get_token (void);
6676static int intel_expr (void);
6677static int intel_e04 (void);
6678static int intel_e05 (void);
6679static int intel_e06 (void);
6680static int intel_e09 (void);
6681static int intel_e10 (void);
6682static int intel_e11 (void);
64a0c779 6683
64a0c779 6684static int
e3bb37b5 6685i386_intel_operand (char *operand_string, int got_a_float)
64a0c779
DN		 6686{
6687 int ret;
6688 char *p;
6689
a724f0f4
JB		 6690 p = intel_parser.op_string = xstrdup (operand_string);
6691 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
6692
6693 for (;;)
64a0c779 6694 {
a724f0f4
JB		 6695 /* Initialize token holders. */
6696 cur_token.code = prev_token.code = T_NIL;
6697 cur_token.reg = prev_token.reg = NULL;
6698 cur_token.str = prev_token.str = NULL;
6699
6700 /* Initialize parser structure. */
6701 intel_parser.got_a_float = got_a_float;
6702 intel_parser.op_modifier = 0;
6703 intel_parser.is_mem = 0;
6704 intel_parser.in_offset = 0;
6705 intel_parser.in_bracket = 0;
6706 intel_parser.reg = NULL;
6707 intel_parser.disp[0] = '\0';
6708 intel_parser.next_operand = NULL;
6709
6710 /* Read the first token and start the parser. */
6711 intel_get_token ();
6712 ret = intel_expr ();
6713
6714 if (!ret)
6715 break;
6716
9306ca4a
JB		 6717 if (cur_token.code != T_NIL)
6718 {
6719 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
6720 current_templates->start->name, cur_token.str);
6721 ret = 0;
6722 }
64a0c779
DN		 6723 /* If we found a memory reference, hand it over to i386_displacement
6724 to fill in the rest of the operand fields. */
9306ca4a 6725 else if (intel_parser.is_mem)
64a0c779
DN		 6726 {
6727 if ((i.mem_operands == 1
6728 && (current_templates->start->opcode_modifier & IsString) == 0)
6729 || i.mem_operands == 2)
6730 {
6731 as_bad (_("too many memory references for '%s'"),
6732 current_templates->start->name);
6733 ret = 0;
6734 }
6735 else
6736 {
6737 char *s = intel_parser.disp;
6738 i.mem_operands++;
6739
a724f0f4
JB		 6740 if (!quiet_warnings && intel_parser.is_mem < 0)
6741 /* See the comments in intel_bracket_expr. */
6742 as_warn (_("Treating `%s' as memory reference"), operand_string);
6743
64a0c779
DN		 6744 /* Add the displacement expression. */
6745 if (*s != '\0')
a4622f40
AM		 6746 ret = i386_displacement (s, s + strlen (s));
6747 if (ret)
a724f0f4
JB		 6748 {
6749 /* Swap base and index in 16-bit memory operands like
6750 [si+bx]. Since i386_index_check is also used in AT&T
6751 mode we have to do that here. */
6752 if (i.base_reg
6753 && i.index_reg
6754 && (i.base_reg->reg_type & Reg16)
6755 && (i.index_reg->reg_type & Reg16)
6756 && i.base_reg->reg_num >= 6
6757 && i.index_reg->reg_num < 6)
6758 {
6759 const reg_entry *base = i.index_reg;
6760
6761 i.index_reg = i.base_reg;
6762 i.base_reg = base;
6763 }
6764 ret = i386_index_check (operand_string);
6765 }
64a0c779
DN		 6766 }
6767 }
6768
6769 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 6770 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779
DN		 6771 || intel_parser.reg == NULL)
6772 ret = i386_immediate (intel_parser.disp);
a724f0f4
JB		 6773
6774 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
4eed87de 6775 ret = 0;
a724f0f4
JB		 6776 if (!ret || !intel_parser.next_operand)
6777 break;
6778 intel_parser.op_string = intel_parser.next_operand;
6779 this_operand = i.operands++;
64a0c779
DN		 6780 }
6781
6782 free (p);
6783 free (intel_parser.disp);
6784
6785 return ret;
6786}
6787
a724f0f4
JB		 6788#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
6789
6790/* expr e04 expr'
6791
6792 expr' cmpOp e04 expr'
6793 | Empty */
64a0c779 6794static int
e3bb37b5 6795intel_expr (void)
64a0c779 6796{
a724f0f4
JB		 6797 /* XXX Implement the comparison operators. */
6798 return intel_e04 ();
9306ca4a
JB		 6799}
6800
a724f0f4 6801/* e04 e05 e04'
9306ca4a 6802
a724f0f4 6803 e04' addOp e05 e04'
9306ca4a
JB		 6804 | Empty */
6805static int
e3bb37b5 6806intel_e04 (void)
9306ca4a 6807{
a724f0f4 6808 int nregs = -1;
9306ca4a 6809
a724f0f4 6810 for (;;)
9306ca4a 6811 {
a724f0f4
JB		 6812 if (!intel_e05())
6813 return 0;
9306ca4a 6814
a724f0f4
JB		 6815 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6816 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 6817
a724f0f4
JB		 6818 if (cur_token.code == '+')
6819 nregs = -1;
6820 else if (cur_token.code == '-')
6821 nregs = NUM_ADDRESS_REGS;
6822 else
6823 return 1;
64a0c779 6824
a724f0f4
JB		 6825 strcat (intel_parser.disp, cur_token.str);
6826 intel_match_token (cur_token.code);
6827 }
64a0c779
DN		 6828}
6829
64a0c779
DN		 6830/* e05 e06 e05'
6831
9306ca4a 6832 e05' binOp e06 e05'
64a0c779
DN		 6833 | Empty */
6834static int
e3bb37b5 6835intel_e05 (void)
64a0c779 6836{
a724f0f4 6837 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6838
a724f0f4 6839 for (;;)
64a0c779 6840 {
a724f0f4
JB		 6841 if (!intel_e06())
6842 return 0;
6843
4eed87de
AM		 6844 if (cur_token.code == '&'
6845 || cur_token.code == '|'
6846 || cur_token.code == '^')
a724f0f4
JB		 6847 {
6848 char str[2];
6849
6850 str[0] = cur_token.code;
6851 str[1] = 0;
6852 strcat (intel_parser.disp, str);
6853 }
6854 else
6855 break;
9306ca4a 6856
64a0c779
DN		 6857 intel_match_token (cur_token.code);
6858
a724f0f4
JB		 6859 if (nregs < 0)
6860 nregs = ~nregs;
64a0c779 6861 }
a724f0f4
JB		 6862 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6863 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
6864 return 1;
4a1805b1 6865}
64a0c779
DN		 6866
6867/* e06 e09 e06'
6868
6869 e06' mulOp e09 e06'
b77a7acd 6870 | Empty */
64a0c779 6871static int
e3bb37b5 6872intel_e06 (void)
64a0c779 6873{
a724f0f4 6874 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6875
a724f0f4 6876 for (;;)
64a0c779 6877 {
a724f0f4
JB		 6878 if (!intel_e09())
6879 return 0;
9306ca4a 6880
4eed87de
AM		 6881 if (cur_token.code == '*'
6882 || cur_token.code == '/'
6883 || cur_token.code == '%')
a724f0f4
JB		 6884 {
6885 char str[2];
9306ca4a 6886
a724f0f4
JB		 6887 str[0] = cur_token.code;
6888 str[1] = 0;
6889 strcat (intel_parser.disp, str);
6890 }
6891 else if (cur_token.code == T_SHL)
6892 strcat (intel_parser.disp, "<<");
6893 else if (cur_token.code == T_SHR)
6894 strcat (intel_parser.disp, ">>");
6895 else
6896 break;
9306ca4a 6897
64e74474 6898 intel_match_token (cur_token.code);
64a0c779 6899
a724f0f4
JB		 6900 if (nregs < 0)
6901 nregs = ~nregs;
64a0c779 6902 }
a724f0f4
JB		 6903 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6904 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
6905 return 1;
64a0c779
DN		 6906}
6907
a724f0f4
JB		 6908/* e09 OFFSET e09
6909 | SHORT e09
6910 | + e09
6911 | - e09
6912 | ~ e09
6913 | NOT e09
9306ca4a
JB		 6914 | e10 e09'
6915
64a0c779 6916 e09' PTR e10 e09'
b77a7acd 6917 | : e10 e09'
64a0c779
DN		 6918 | Empty */
6919static int
e3bb37b5 6920intel_e09 (void)
64a0c779 6921{
a724f0f4
JB		 6922 int nregs = ~NUM_ADDRESS_REGS;
6923 int in_offset = 0;
6924
6925 for (;;)
64a0c779 6926 {
a724f0f4
JB		 6927 /* Don't consume constants here. */
6928 if (cur_token.code == '+' || cur_token.code == '-')
6929 {
6930 /* Need to look one token ahead - if the next token
6931 is a constant, the current token is its sign. */
6932 int next_code;
6933
6934 intel_match_token (cur_token.code);
6935 next_code = cur_token.code;
6936 intel_putback_token ();
6937 if (next_code == T_CONST)
6938 break;
6939 }
6940
6941 /* e09 OFFSET e09 */
6942 if (cur_token.code == T_OFFSET)
6943 {
6944 if (!in_offset++)
6945 ++intel_parser.in_offset;
6946 }
6947
6948 /* e09 SHORT e09 */
6949 else if (cur_token.code == T_SHORT)
6950 intel_parser.op_modifier |= 1 << T_SHORT;
6951
6952 /* e09 + e09 */
6953 else if (cur_token.code == '+')
6954 strcat (intel_parser.disp, "+");
6955
6956 /* e09 - e09
6957 | ~ e09
6958 | NOT e09 */
6959 else if (cur_token.code == '-' || cur_token.code == '~')
6960 {
6961 char str[2];
64a0c779 6962
a724f0f4
JB		 6963 if (nregs < 0)
6964 nregs = ~nregs;
6965 str[0] = cur_token.code;
6966 str[1] = 0;
6967 strcat (intel_parser.disp, str);
6968 }
6969
6970 /* e09 e10 e09' */
6971 else
6972 break;
6973
6974 intel_match_token (cur_token.code);
64a0c779
DN		 6975 }
6976
a724f0f4 6977 for (;;)
9306ca4a 6978 {
a724f0f4
JB		 6979 if (!intel_e10 ())
6980 return 0;
9306ca4a 6981
a724f0f4
JB		 6982 /* e09' PTR e10 e09' */
6983 if (cur_token.code == T_PTR)
6984 {
6985 char suffix;
9306ca4a 6986
a724f0f4
JB		 6987 if (prev_token.code == T_BYTE)
6988 suffix = BYTE_MNEM_SUFFIX;
9306ca4a 6989
a724f0f4
JB		 6990 else if (prev_token.code == T_WORD)
6991 {
6992 if (current_templates->start->name[0] == 'l'
6993 && current_templates->start->name[2] == 's'
6994 && current_templates->start->name[3] == 0)
6995 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6996 else if (intel_parser.got_a_float == 2) /* "fi..." */
6997 suffix = SHORT_MNEM_SUFFIX;
6998 else
6999 suffix = WORD_MNEM_SUFFIX;
7000 }
64a0c779 7001
a724f0f4
JB		 7002 else if (prev_token.code == T_DWORD)
7003 {
7004 if (current_templates->start->name[0] == 'l'
7005 && current_templates->start->name[2] == 's'
7006 && current_templates->start->name[3] == 0)
7007 suffix = WORD_MNEM_SUFFIX;
7008 else if (flag_code == CODE_16BIT
7009 && (current_templates->start->opcode_modifier
435acd52 7010 & (Jump | JumpDword)))
a724f0f4
JB		 7011 suffix = LONG_DOUBLE_MNEM_SUFFIX;
7012 else if (intel_parser.got_a_float == 1) /* "f..." */
7013 suffix = SHORT_MNEM_SUFFIX;
7014 else
7015 suffix = LONG_MNEM_SUFFIX;
7016 }
9306ca4a 7017
a724f0f4
JB		 7018 else if (prev_token.code == T_FWORD)
7019 {
7020 if (current_templates->start->name[0] == 'l'
7021 && current_templates->start->name[2] == 's'
7022 && current_templates->start->name[3] == 0)
7023 suffix = LONG_MNEM_SUFFIX;
7024 else if (!intel_parser.got_a_float)
7025 {
7026 if (flag_code == CODE_16BIT)
7027 add_prefix (DATA_PREFIX_OPCODE);
7028 suffix = LONG_DOUBLE_MNEM_SUFFIX;
7029 }
7030 else
7031 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
7032 }
64a0c779 7033
a724f0f4
JB		 7034 else if (prev_token.code == T_QWORD)
7035 {
7036 if (intel_parser.got_a_float == 1) /* "f..." */
7037 suffix = LONG_MNEM_SUFFIX;
7038 else
7039 suffix = QWORD_MNEM_SUFFIX;
7040 }
64a0c779 7041
a724f0f4
JB		 7042 else if (prev_token.code == T_TBYTE)
7043 {
7044 if (intel_parser.got_a_float == 1)
7045 suffix = LONG_DOUBLE_MNEM_SUFFIX;
7046 else
7047 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
7048 }
9306ca4a 7049
a724f0f4 7050 else if (prev_token.code == T_XMMWORD)
9306ca4a 7051 {
a724f0f4
JB		 7052 /* XXX ignored for now, but accepted since gcc uses it */
7053 suffix = 0;
9306ca4a 7054 }
64a0c779 7055
f16b83df 7056 else
a724f0f4
JB		 7057 {
7058 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
7059 return 0;
7060 }
7061
435acd52
JB		 7062 /* Operands for jump/call using 'ptr' notation denote absolute
7063 addresses. */
7064 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
7065 i.types[this_operand] |= JumpAbsolute;
7066
a724f0f4
JB		 7067 if (current_templates->start->base_opcode == 0x8d /* lea */)
7068 ;
7069 else if (!i.suffix)
7070 i.suffix = suffix;
7071 else if (i.suffix != suffix)
7072 {
7073 as_bad (_("Conflicting operand modifiers"));
7074 return 0;
7075 }
64a0c779 7076
9306ca4a
JB		 7077 }
7078
a724f0f4
JB		 7079 /* e09' : e10 e09' */
7080 else if (cur_token.code == ':')
9306ca4a 7081 {
a724f0f4
JB		 7082 if (prev_token.code != T_REG)
7083 {
7084 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
7085 segment/group identifier (which we don't have), using comma
7086 as the operand separator there is even less consistent, since
7087 there all branches only have a single operand. */
7088 if (this_operand != 0
7089 || intel_parser.in_offset
7090 || intel_parser.in_bracket
7091 || (!(current_templates->start->opcode_modifier
7092 & (Jump|JumpDword|JumpInterSegment))
7093 && !(current_templates->start->operand_types[0]
7094 & JumpAbsolute)))
7095 return intel_match_token (T_NIL);
7096 /* Remember the start of the 2nd operand and terminate 1st
7097 operand here.
7098 XXX This isn't right, yet (when SSSS:OOOO is right operand of
7099 another expression), but it gets at least the simplest case
7100 (a plain number or symbol on the left side) right. */
7101 intel_parser.next_operand = intel_parser.op_string;
7102 *--intel_parser.op_string = '\0';
7103 return intel_match_token (':');
7104 }
9306ca4a 7105 }
64a0c779 7106
a724f0f4 7107 /* e09' Empty */
64a0c779 7108 else
a724f0f4 7109 break;
64a0c779 7110
a724f0f4
JB		 7111 intel_match_token (cur_token.code);
7112
7113 }
7114
7115 if (in_offset)
7116 {
7117 --intel_parser.in_offset;
7118 if (nregs < 0)
7119 nregs = ~nregs;
7120 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 7121 {
a724f0f4 7122 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 7123 return 0;
7124 }
a724f0f4
JB		 7125 intel_parser.op_modifier |= 1 << T_OFFSET;
7126 }
9306ca4a 7127
a724f0f4
JB		 7128 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7129 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
7130 return 1;
7131}
64a0c779 7132
a724f0f4 7133static int
e3bb37b5 7134intel_bracket_expr (void)
a724f0f4
JB		 7135{
7136 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
7137 const char *start = intel_parser.op_string;
7138 int len;
7139
7140 if (i.op[this_operand].regs)
7141 return intel_match_token (T_NIL);
7142
7143 intel_match_token ('[');
7144
7145 /* Mark as a memory operand only if it's not already known to be an
7146 offset expression. If it's an offset expression, we need to keep
7147 the brace in. */
7148 if (!intel_parser.in_offset)
7149 {
7150 ++intel_parser.in_bracket;
435acd52
JB		 7151
7152 /* Operands for jump/call inside brackets denote absolute addresses. */
7153 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
7154 i.types[this_operand] |= JumpAbsolute;
7155
a724f0f4
JB		 7156 /* Unfortunately gas always diverged from MASM in a respect that can't
7157 be easily fixed without risking to break code sequences likely to be
7158 encountered (the testsuite even check for this): MASM doesn't consider
7159 an expression inside brackets unconditionally as a memory reference.
7160 When that is e.g. a constant, an offset expression, or the sum of the
7161 two, this is still taken as a constant load. gas, however, always
7162 treated these as memory references. As a compromise, we'll try to make
7163 offset expressions inside brackets work the MASM way (since that's
7164 less likely to be found in real world code), but make constants alone
7165 continue to work the traditional gas way. In either case, issue a
7166 warning. */
7167 intel_parser.op_modifier &= ~was_offset;
64a0c779 7168 }
a724f0f4 7169 else
64e74474 7170 strcat (intel_parser.disp, "[");
a724f0f4
JB		 7171
7172 /* Add a '+' to the displacement string if necessary. */
7173 if (*intel_parser.disp != '\0'
7174 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
7175 strcat (intel_parser.disp, "+");
64a0c779 7176
a724f0f4
JB		 7177 if (intel_expr ()
7178 && (len = intel_parser.op_string - start - 1,
7179 intel_match_token (']')))
64a0c779 7180 {
a724f0f4
JB		 7181 /* Preserve brackets when the operand is an offset expression. */
7182 if (intel_parser.in_offset)
7183 strcat (intel_parser.disp, "]");
7184 else
7185 {
7186 --intel_parser.in_bracket;
7187 if (i.base_reg || i.index_reg)
7188 intel_parser.is_mem = 1;
7189 if (!intel_parser.is_mem)
7190 {
7191 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
7192 /* Defer the warning until all of the operand was parsed. */
7193 intel_parser.is_mem = -1;
7194 else if (!quiet_warnings)
4eed87de
AM		 7195 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
7196 len, start, len, start);
a724f0f4
JB		 7197 }
7198 }
7199 intel_parser.op_modifier |= was_offset;
64a0c779 7200
a724f0f4 7201 return 1;
64a0c779 7202 }
a724f0f4 7203 return 0;
64a0c779
DN		 7204}
7205
7206/* e10 e11 e10'
7207
7208 e10' [ expr ] e10'
b77a7acd 7209 | Empty */
64a0c779 7210static int
e3bb37b5 7211intel_e10 (void)
64a0c779 7212{
a724f0f4
JB		 7213 if (!intel_e11 ())
7214 return 0;
64a0c779 7215
a724f0f4 7216 while (cur_token.code == '[')
64a0c779 7217 {
a724f0f4 7218 if (!intel_bracket_expr ())
21d6c4af 7219 return 0;
64a0c779
DN		 7220 }
7221
a724f0f4 7222 return 1;
64a0c779
DN		 7223}
7224
64a0c779 7225/* e11 ( expr )
b77a7acd 7226 | [ expr ]
64a0c779
DN		 7227 | BYTE
7228 | WORD
7229 | DWORD
9306ca4a 7230 | FWORD
64a0c779 7231 | QWORD
9306ca4a
JB		 7232 | TBYTE
7233 | OWORD
7234 | XMMWORD
4a1805b1 7235 | $
64a0c779
DN		 7236 | .
7237 | register
7238 | id
7239 | constant */
7240static int
e3bb37b5 7241intel_e11 (void)
64a0c779 7242{
a724f0f4 7243 switch (cur_token.code)
64a0c779 7244 {
a724f0f4
JB		 7245 /* e11 ( expr ) */
7246 case '(':
64a0c779
DN		 7247 intel_match_token ('(');
7248 strcat (intel_parser.disp, "(");
7249
7250 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 7251 {
7252 strcat (intel_parser.disp, ")");
7253 return 1;
7254 }
a724f0f4 7255 return 0;
4a1805b1 7256
a724f0f4
JB		 7257 /* e11 [ expr ] */
7258 case '[':
a724f0f4 7259 return intel_bracket_expr ();
64a0c779 7260
a724f0f4
JB		 7261 /* e11 $
7262 | . */
7263 case '.':
64a0c779
DN		 7264 strcat (intel_parser.disp, cur_token.str);
7265 intel_match_token (cur_token.code);
21d6c4af
DN		 7266
7267 /* Mark as a memory operand only if it's not already known to be an
7268 offset expression. */
a724f0f4 7269 if (!intel_parser.in_offset)
21d6c4af 7270 intel_parser.is_mem = 1;
64a0c779
DN		 7271
7272 return 1;
64a0c779 7273
a724f0f4
JB		 7274 /* e11 register */
7275 case T_REG:
7276 {
7277 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 7278
a724f0f4 7279 intel_match_token (T_REG);
64a0c779 7280
a724f0f4
JB		 7281 /* Check for segment change. */
7282 if (cur_token.code == ':')
7283 {
7284 if (!(reg->reg_type & (SReg2 | SReg3)))
7285 {
4eed87de
AM		 7286 as_bad (_("`%s' is not a valid segment register"),
7287 reg->reg_name);
a724f0f4
JB		 7288 return 0;
7289 }
7290 else if (i.seg[i.mem_operands])
7291 as_warn (_("Extra segment override ignored"));
7292 else
7293 {
7294 if (!intel_parser.in_offset)
7295 intel_parser.is_mem = 1;
7296 switch (reg->reg_num)
7297 {
7298 case 0:
7299 i.seg[i.mem_operands] = &es;
7300 break;
7301 case 1:
7302 i.seg[i.mem_operands] = &cs;
7303 break;
7304 case 2:
7305 i.seg[i.mem_operands] = &ss;
7306 break;
7307 case 3:
7308 i.seg[i.mem_operands] = &ds;
7309 break;
7310 case 4:
7311 i.seg[i.mem_operands] = &fs;
7312 break;
7313 case 5:
7314 i.seg[i.mem_operands] = &gs;
7315 break;
7316 }
7317 }
7318 }
64a0c779 7319
a724f0f4
JB		 7320 /* Not a segment register. Check for register scaling. */
7321 else if (cur_token.code == '*')
7322 {
7323 if (!intel_parser.in_bracket)
7324 {
7325 as_bad (_("Register scaling only allowed in memory operands"));
7326 return 0;
7327 }
64a0c779 7328
a724f0f4
JB		 7329 if (reg->reg_type & Reg16) /* Disallow things like [si*1]. */
7330 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
7331 else if (i.index_reg)
7332 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 7333
a724f0f4
JB		 7334 /* What follows must be a valid scale. */
7335 intel_match_token ('*');
7336 i.index_reg = reg;
7337 i.types[this_operand] |= BaseIndex;
64a0c779 7338
a724f0f4
JB		 7339 /* Set the scale after setting the register (otherwise,
7340 i386_scale will complain) */
7341 if (cur_token.code == '+' || cur_token.code == '-')
7342 {
7343 char *str, sign = cur_token.code;
7344 intel_match_token (cur_token.code);
7345 if (cur_token.code != T_CONST)
7346 {
7347 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7348 cur_token.str);
7349 return 0;
7350 }
7351 str = (char *) xmalloc (strlen (cur_token.str) + 2);
7352 strcpy (str + 1, cur_token.str);
7353 *str = sign;
7354 if (!i386_scale (str))
7355 return 0;
7356 free (str);
7357 }
7358 else if (!i386_scale (cur_token.str))
64a0c779 7359 return 0;
a724f0f4
JB		 7360 intel_match_token (cur_token.code);
7361 }
64a0c779 7362
a724f0f4
JB		 7363 /* No scaling. If this is a memory operand, the register is either a
7364 base register (first occurrence) or an index register (second
7365 occurrence). */
7b0441f6 7366 else if (intel_parser.in_bracket)
a724f0f4 7367 {
64a0c779 7368
a724f0f4
JB		 7369 if (!i.base_reg)
7370 i.base_reg = reg;
7371 else if (!i.index_reg)
7372 i.index_reg = reg;
7373 else
7374 {
7375 as_bad (_("Too many register references in memory operand"));
7376 return 0;
7377 }
64a0c779 7378
a724f0f4
JB		 7379 i.types[this_operand] |= BaseIndex;
7380 }
4a1805b1 7381
4d1bb795
JB		 7382 /* It's neither base nor index. */
7383 else if (!intel_parser.in_offset && !intel_parser.is_mem)
a724f0f4
JB		 7384 {
7385 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
7386 i.op[this_operand].regs = reg;
7387 i.reg_operands++;
7388 }
7389 else
7390 {
7391 as_bad (_("Invalid use of register"));
7392 return 0;
7393 }
64a0c779 7394
a724f0f4
JB		 7395 /* Since registers are not part of the displacement string (except
7396 when we're parsing offset operands), we may need to remove any
7397 preceding '+' from the displacement string. */
7398 if (*intel_parser.disp != '\0'
7399 && !intel_parser.in_offset)
7400 {
7401 char *s = intel_parser.disp;
7402 s += strlen (s) - 1;
7403 if (*s == '+')
7404 *s = '\0';
7405 }
4a1805b1 7406
a724f0f4
JB		 7407 return 1;
7408 }
7409
7410 /* e11 BYTE
7411 | WORD
7412 | DWORD
7413 | FWORD
7414 | QWORD
7415 | TBYTE
7416 | OWORD
7417 | XMMWORD */
7418 case T_BYTE:
7419 case T_WORD:
7420 case T_DWORD:
7421 case T_FWORD:
7422 case T_QWORD:
7423 case T_TBYTE:
7424 case T_XMMWORD:
7425 intel_match_token (cur_token.code);
64a0c779 7426
a724f0f4
JB		 7427 if (cur_token.code == T_PTR)
7428 return 1;
7429
7430 /* It must have been an identifier. */
7431 intel_putback_token ();
7432 cur_token.code = T_ID;
7433 /* FALLTHRU */
7434
7435 /* e11 id
7436 | constant */
7437 case T_ID:
7438 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 7439 {
7440 symbolS *symbolP;
7441
a724f0f4
JB		 7442 /* The identifier represents a memory reference only if it's not
7443 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 7444 symbolP = symbol_find(cur_token.str);
7445 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
7446 intel_parser.is_mem = 1;
7447 }
a724f0f4 7448 /* FALLTHRU */
64a0c779 7449
a724f0f4
JB		 7450 case T_CONST:
7451 case '-':
7452 case '+':
7453 {
7454 char *save_str, sign = 0;
64a0c779 7455
a724f0f4
JB		 7456 /* Allow constants that start with `+' or `-'. */
7457 if (cur_token.code == '-' || cur_token.code == '+')
7458 {
7459 sign = cur_token.code;
7460 intel_match_token (cur_token.code);
7461 if (cur_token.code != T_CONST)
7462 {
7463 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7464 cur_token.str);
7465 return 0;
7466 }
7467 }
64a0c779 7468
a724f0f4
JB		 7469 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
7470 strcpy (save_str + !!sign, cur_token.str);
7471 if (sign)
7472 *save_str = sign;
64a0c779 7473
a724f0f4
JB		 7474 /* Get the next token to check for register scaling. */
7475 intel_match_token (cur_token.code);
64a0c779 7476
4eed87de
AM		 7477 /* Check if this constant is a scaling factor for an
7478 index register. */
a724f0f4
JB		 7479 if (cur_token.code == '*')
7480 {
7481 if (intel_match_token ('*') && cur_token.code == T_REG)
7482 {
7483 const reg_entry *reg = cur_token.reg;
7484
7485 if (!intel_parser.in_bracket)
7486 {
4eed87de
AM		 7487 as_bad (_("Register scaling only allowed "
7488 "in memory operands"));
a724f0f4
JB		 7489 return 0;
7490 }
7491
4eed87de
AM		 7492 /* Disallow things like [1*si].
7493 sp and esp are invalid as index. */
7494 if (reg->reg_type & Reg16)
7495 reg = i386_regtab + REGNAM_AX + 4;
a724f0f4 7496 else if (i.index_reg)
4eed87de 7497 reg = i386_regtab + REGNAM_EAX + 4;
a724f0f4
JB		 7498
7499 /* The constant is followed by `* reg', so it must be
7500 a valid scale. */
7501 i.index_reg = reg;
7502 i.types[this_operand] |= BaseIndex;
7503
7504 /* Set the scale after setting the register (otherwise,
7505 i386_scale will complain) */
7506 if (!i386_scale (save_str))
64a0c779 7507 return 0;
a724f0f4
JB		 7508 intel_match_token (T_REG);
7509
7510 /* Since registers are not part of the displacement
7511 string, we may need to remove any preceding '+' from
7512 the displacement string. */
7513 if (*intel_parser.disp != '\0')
7514 {
7515 char *s = intel_parser.disp;
7516 s += strlen (s) - 1;
7517 if (*s == '+')
7518 *s = '\0';
7519 }
7520
7521 free (save_str);
7522
7523 return 1;
7524 }
64a0c779 7525
a724f0f4
JB		 7526 /* The constant was not used for register scaling. Since we have
7527 already consumed the token following `*' we now need to put it
7528 back in the stream. */
64a0c779 7529 intel_putback_token ();
a724f0f4 7530 }
64a0c779 7531
a724f0f4
JB		 7532 /* Add the constant to the displacement string. */
7533 strcat (intel_parser.disp, save_str);
7534 free (save_str);
64a0c779 7535
a724f0f4
JB		 7536 return 1;
7537 }
64a0c779
DN		 7538 }
7539
64a0c779
DN		 7540 as_bad (_("Unrecognized token '%s'"), cur_token.str);
7541 return 0;
7542}
7543
64a0c779
DN		 7544/* Match the given token against cur_token. If they match, read the next
7545 token from the operand string. */
7546static int
e3bb37b5 7547intel_match_token (int code)
64a0c779
DN		 7548{
7549 if (cur_token.code == code)
7550 {
7551 intel_get_token ();
7552 return 1;
7553 }
7554 else
7555 {
0477af35 7556 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 7557 return 0;
7558 }
7559}
7560
64a0c779
DN		 7561/* Read a new token from intel_parser.op_string and store it in cur_token. */
7562static void
e3bb37b5 7563intel_get_token (void)
64a0c779
DN		 7564{
7565 char *end_op;
7566 const reg_entry *reg;
7567 struct intel_token new_token;
7568
7569 new_token.code = T_NIL;
7570 new_token.reg = NULL;
7571 new_token.str = NULL;
7572
4a1805b1 7573 /* Free the memory allocated to the previous token and move
64a0c779
DN		 7574 cur_token to prev_token. */
7575 if (prev_token.str)
7576 free (prev_token.str);
7577
7578 prev_token = cur_token;
7579
7580 /* Skip whitespace. */
7581 while (is_space_char (*intel_parser.op_string))
7582 intel_parser.op_string++;
7583
7584 /* Return an empty token if we find nothing else on the line. */
7585 if (*intel_parser.op_string == '\0')
7586 {
7587 cur_token = new_token;
7588 return;
7589 }
7590
7591 /* The new token cannot be larger than the remainder of the operand
7592 string. */
a724f0f4 7593 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 7594 new_token.str[0] = '\0';
7595
7596 if (strchr ("0123456789", *intel_parser.op_string))
7597 {
7598 char *p = new_token.str;
7599 char *q = intel_parser.op_string;
7600 new_token.code = T_CONST;
7601
7602 /* Allow any kind of identifier char to encompass floating point and
7603 hexadecimal numbers. */
7604 while (is_identifier_char (*q))
7605 *p++ = *q++;
7606 *p = '\0';
7607
7608 /* Recognize special symbol names [0-9][bf]. */
7609 if (strlen (intel_parser.op_string) == 2
4a1805b1 7610 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 7611 || intel_parser.op_string[1] == 'f'))
7612 new_token.code = T_ID;
7613 }
7614
4d1bb795 7615 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
64a0c779 7616 {
4d1bb795
JB		 7617 size_t len = end_op - intel_parser.op_string;
7618
64a0c779
DN		 7619 new_token.code = T_REG;
7620 new_token.reg = reg;
7621
4d1bb795
JB		 7622 memcpy (new_token.str, intel_parser.op_string, len);
7623 new_token.str[len] = '\0';
64a0c779
DN		 7624 }
7625
7626 else if (is_identifier_char (*intel_parser.op_string))
7627 {
7628 char *p = new_token.str;
7629 char *q = intel_parser.op_string;
7630
7631 /* A '.' or '$' followed by an identifier char is an identifier.
7632 Otherwise, it's operator '.' followed by an expression. */
7633 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
7634 {
9306ca4a
JB		 7635 new_token.code = '.';
7636 new_token.str[0] = '.';
64a0c779
DN		 7637 new_token.str[1] = '\0';
7638 }
7639 else
7640 {
7641 while (is_identifier_char (*q) || *q == '@')
7642 *p++ = *q++;
7643 *p = '\0';
7644
9306ca4a
JB		 7645 if (strcasecmp (new_token.str, "NOT") == 0)
7646 new_token.code = '~';
7647
7648 else if (strcasecmp (new_token.str, "MOD") == 0)
7649 new_token.code = '%';
7650
7651 else if (strcasecmp (new_token.str, "AND") == 0)
7652 new_token.code = '&';
7653
7654 else if (strcasecmp (new_token.str, "OR") == 0)
7655 new_token.code = '|';
7656
7657 else if (strcasecmp (new_token.str, "XOR") == 0)
7658 new_token.code = '^';
7659
7660 else if (strcasecmp (new_token.str, "SHL") == 0)
7661 new_token.code = T_SHL;
7662
7663 else if (strcasecmp (new_token.str, "SHR") == 0)
7664 new_token.code = T_SHR;
7665
7666 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 7667 new_token.code = T_BYTE;
7668
7669 else if (strcasecmp (new_token.str, "WORD") == 0)
7670 new_token.code = T_WORD;
7671
7672 else if (strcasecmp (new_token.str, "DWORD") == 0)
7673 new_token.code = T_DWORD;
7674
9306ca4a
JB		 7675 else if (strcasecmp (new_token.str, "FWORD") == 0)
7676 new_token.code = T_FWORD;
7677
64a0c779
DN		 7678 else if (strcasecmp (new_token.str, "QWORD") == 0)
7679 new_token.code = T_QWORD;
7680
9306ca4a
JB		 7681 else if (strcasecmp (new_token.str, "TBYTE") == 0
7682 /* XXX remove (gcc still uses it) */
7683 || strcasecmp (new_token.str, "XWORD") == 0)
7684 new_token.code = T_TBYTE;
7685
7686 else if (strcasecmp (new_token.str, "XMMWORD") == 0
7687 || strcasecmp (new_token.str, "OWORD") == 0)
7688 new_token.code = T_XMMWORD;
64a0c779
DN		 7689
7690 else if (strcasecmp (new_token.str, "PTR") == 0)
7691 new_token.code = T_PTR;
7692
7693 else if (strcasecmp (new_token.str, "SHORT") == 0)
7694 new_token.code = T_SHORT;
7695
7696 else if (strcasecmp (new_token.str, "OFFSET") == 0)
7697 {
7698 new_token.code = T_OFFSET;
7699
7700 /* ??? This is not mentioned in the MASM grammar but gcc
7701 makes use of it with -mintel-syntax. OFFSET may be
7702 followed by FLAT: */
7703 if (strncasecmp (q, " FLAT:", 6) == 0)
7704 strcat (new_token.str, " FLAT:");
7705 }
7706
7707 /* ??? This is not mentioned in the MASM grammar. */
7708 else if (strcasecmp (new_token.str, "FLAT") == 0)
a724f0f4
JB		 7709 {
7710 new_token.code = T_OFFSET;
7711 if (*q == ':')
7712 strcat (new_token.str, ":");
7713 else
7714 as_bad (_("`:' expected"));
7715 }
64a0c779
DN		 7716
7717 else
7718 new_token.code = T_ID;
7719 }
7720 }
7721
9306ca4a
JB		 7722 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
7723 {
7724 new_token.code = *intel_parser.op_string;
7725 new_token.str[0] = *intel_parser.op_string;
7726 new_token.str[1] = '\0';
7727 }
7728
7729 else if (strchr ("<>", *intel_parser.op_string)
7730 && *intel_parser.op_string == *(intel_parser.op_string + 1))
7731 {
7732 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
7733 new_token.str[0] = *intel_parser.op_string;
7734 new_token.str[1] = *intel_parser.op_string;
7735 new_token.str[2] = '\0';
7736 }
7737
64a0c779 7738 else
0477af35 7739 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 7740
7741 intel_parser.op_string += strlen (new_token.str);
7742 cur_token = new_token;
7743}
7744
64a0c779
DN		 7745/* Put cur_token back into the token stream and make cur_token point to
7746 prev_token. */
7747static void
e3bb37b5 7748intel_putback_token (void)
64a0c779 7749{
a724f0f4
JB		 7750 if (cur_token.code != T_NIL)
7751 {
7752 intel_parser.op_string -= strlen (cur_token.str);
7753 free (cur_token.str);
7754 }
64a0c779 7755 cur_token = prev_token;
4a1805b1 7756
64a0c779
DN		 7757 /* Forget prev_token. */
7758 prev_token.code = T_NIL;
7759 prev_token.reg = NULL;
7760 prev_token.str = NULL;
7761}
54cfded0 7762
a4447b93 7763int
1df69f4f 7764tc_x86_regname_to_dw2regnum (char *regname)
54cfded0
AM		 7765{
7766 unsigned int regnum;
7767 unsigned int regnames_count;
089dfecd 7768 static const char *const regnames_32[] =
54cfded0 7769 {
a4447b93
RH		 7770 "eax", "ecx", "edx", "ebx",
7771 "esp", "ebp", "esi", "edi",
089dfecd
JB		 7772 "eip", "eflags", NULL,
7773 "st0", "st1", "st2", "st3",
7774 "st4", "st5", "st6", "st7",
7775 NULL, NULL,
7776 "xmm0", "xmm1", "xmm2", "xmm3",
7777 "xmm4", "xmm5", "xmm6", "xmm7",
7778 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 7779 "mm4", "mm5", "mm6", "mm7",
7780 "fcw", "fsw", "mxcsr",
7781 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7782 "tr", "ldtr"
54cfded0 7783 };
089dfecd 7784 static const char *const regnames_64[] =
54cfded0 7785 {
089dfecd
JB		 7786 "rax", "rdx", "rcx", "rbx",
7787 "rsi", "rdi", "rbp", "rsp",
7788 "r8", "r9", "r10", "r11",
54cfded0 7789 "r12", "r13", "r14", "r15",
089dfecd
JB		 7790 "rip",
7791 "xmm0", "xmm1", "xmm2", "xmm3",
7792 "xmm4", "xmm5", "xmm6", "xmm7",
7793 "xmm8", "xmm9", "xmm10", "xmm11",
7794 "xmm12", "xmm13", "xmm14", "xmm15",
7795 "st0", "st1", "st2", "st3",
7796 "st4", "st5", "st6", "st7",
7797 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 7798 "mm4", "mm5", "mm6", "mm7",
7799 "rflags",
7800 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7801 "fs.base", "gs.base", NULL, NULL,
7802 "tr", "ldtr",
7803 "mxcsr", "fcw", "fsw"
54cfded0 7804 };
089dfecd 7805 const char *const *regnames;
54cfded0
AM		 7806
7807 if (flag_code == CODE_64BIT)
7808 {
7809 regnames = regnames_64;
0cea6190 7810 regnames_count = ARRAY_SIZE (regnames_64);
54cfded0
AM		 7811 }
7812 else
7813 {
7814 regnames = regnames_32;
0cea6190 7815 regnames_count = ARRAY_SIZE (regnames_32);
54cfded0
AM		 7816 }
7817
7818 for (regnum = 0; regnum < regnames_count; regnum++)
089dfecd
JB		 7819 if (regnames[regnum] != NULL
7820 && strcmp (regname, regnames[regnum]) == 0)
54cfded0
AM		 7821 return regnum;
7822
54cfded0
AM		 7823 return -1;
7824}
7825
7826void
7827tc_x86_frame_initial_instructions (void)
7828{
a4447b93
RH		 7829 static unsigned int sp_regno;
7830
7831 if (!sp_regno)
7832 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
7833 ? "rsp" : "esp");
7834
7835 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
7836 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 7837}
d2b2c203
DJ		 7838
7839int
7840i386_elf_section_type (const char *str, size_t len)
7841{
7842 if (flag_code == CODE_64BIT
7843 && len == sizeof ("unwind") - 1
7844 && strncmp (str, "unwind", 6) == 0)
7845 return SHT_X86_64_UNWIND;
7846
7847 return -1;
7848}
bb41ade5
AM		 7849
7850#ifdef TE_PE
7851void
7852tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
7853{
7854 expressionS expr;
7855
7856 expr.X_op = O_secrel;
7857 expr.X_add_symbol = symbol;
7858 expr.X_add_number = 0;
7859 emit_expr (&expr, size);
7860}
7861#endif
3b22753a
L		 7862
7863#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7864/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7865
7866int
7867x86_64_section_letter (int letter, char **ptr_msg)
7868{
7869 if (flag_code == CODE_64BIT)
7870 {
7871 if (letter == 'l')
7872 return SHF_X86_64_LARGE;
7873
7874 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 7875 }
3b22753a 7876 else
64e74474 7877 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 7878 return -1;
7879}
7880
7881int
7882x86_64_section_word (char *str, size_t len)
7883{
8620418b 7884 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 7885 return SHF_X86_64_LARGE;
7886
7887 return -1;
7888}
7889
7890static void
7891handle_large_common (int small ATTRIBUTE_UNUSED)
7892{
7893 if (flag_code != CODE_64BIT)
7894 {
7895 s_comm_internal (0, elf_common_parse);
7896 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7897 }
7898 else
7899 {
7900 static segT lbss_section;
7901 asection *saved_com_section_ptr = elf_com_section_ptr;
7902 asection *saved_bss_section = bss_section;
7903
7904 if (lbss_section == NULL)
7905 {
7906 flagword applicable;
7907 segT seg = now_seg;
7908 subsegT subseg = now_subseg;
7909
7910 /* The .lbss section is for local .largecomm symbols. */
7911 lbss_section = subseg_new (".lbss", 0);
7912 applicable = bfd_applicable_section_flags (stdoutput);
7913 bfd_set_section_flags (stdoutput, lbss_section,
7914 applicable & SEC_ALLOC);
7915 seg_info (lbss_section)->bss = 1;
7916
7917 subseg_set (seg, subseg);
7918 }
7919
7920 elf_com_section_ptr = &_bfd_elf_large_com_section;
7921 bss_section = lbss_section;
7922
7923 s_comm_internal (0, elf_common_parse);
7924
7925 elf_com_section_ptr = saved_com_section_ptr;
7926 bss_section = saved_bss_section;
7927 }
7928}
7929#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
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