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b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4dc85607 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus ([email protected]).
3e73aa7c 25 x86_64 support by Jan Hubicka ([email protected])
0f10071e 26 VIA PadLock support by Michal Ludvig ([email protected])
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
252b5132 36
252b5132
RH		 37#ifndef REGISTER_WARNINGS
38#define REGISTER_WARNINGS 1
39#endif
40
c3332e24 41#ifndef INFER_ADDR_PREFIX
eecb386c 42#define INFER_ADDR_PREFIX 1
c3332e24
AM		 43#endif
44
252b5132
RH		 45#ifndef SCALE1_WHEN_NO_INDEX
46/* Specifying a scale factor besides 1 when there is no index is
47 futile. eg. `mov (%ebx,2),%al' does exactly the same as
48 `mov (%ebx),%al'. To slavishly follow what the programmer
49 specified, set SCALE1_WHEN_NO_INDEX to 0. */
50#define SCALE1_WHEN_NO_INDEX 1
51#endif
52
29b0f896
AM		 53#ifndef DEFAULT_ARCH
54#define DEFAULT_ARCH "i386"
246fcdee 55#endif
252b5132 56
edde18a5
AM		 57#ifndef INLINE
58#if __GNUC__ >= 2
59#define INLINE __inline__
60#else
61#define INLINE
62#endif
63#endif
64
e3bb37b5
L		 65static void set_code_flag (int);
66static void set_16bit_gcc_code_flag (int);
67static void set_intel_syntax (int);
68static void set_cpu_arch (int);
6482c264 69#ifdef TE_PE
e3bb37b5 70static void pe_directive_secrel (int);
6482c264 71#endif
e3bb37b5
L		 72static void signed_cons (int);
73static char *output_invalid (int c);
74static int i386_operand (char *);
75static int i386_intel_operand (char *, int);
76static const reg_entry *parse_register (char *, char **);
77static char *parse_insn (char *, char *);
78static char *parse_operands (char *, const char *);
79static void swap_operands (void);
4d456e3d 80static void swap_2_operands (int, int);
e3bb37b5
L		 81static void optimize_imm (void);
82static void optimize_disp (void);
83static int match_template (void);
84static int check_string (void);
85static int process_suffix (void);
86static int check_byte_reg (void);
87static int check_long_reg (void);
88static int check_qword_reg (void);
89static int check_word_reg (void);
90static int finalize_imm (void);
91static int process_operands (void);
92static const seg_entry *build_modrm_byte (void);
93static void output_insn (void);
94static void output_imm (fragS *, offsetT);
95static void output_disp (fragS *, offsetT);
29b0f896 96#ifndef I386COFF
e3bb37b5 97static void s_bss (int);
252b5132 98#endif
17d4e2a2
L		 99#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
100static void handle_large_common (int small ATTRIBUTE_UNUSED);
101#endif
252b5132 102
a847613f 103static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 104
252b5132 105/* 'md_assemble ()' gathers together information and puts it into a
47926f60 106 i386_insn. */
252b5132 107
520dc8e8
AM		 108union i386_op
109 {
110 expressionS *disps;
111 expressionS *imms;
112 const reg_entry *regs;
113 };
114
252b5132
RH		 115struct _i386_insn
116 {
47926f60 117 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 118 template tm;
119
120 /* SUFFIX holds the instruction mnemonic suffix if given.
121 (e.g. 'l' for 'movl') */
122 char suffix;
123
47926f60 124 /* OPERANDS gives the number of given operands. */
252b5132
RH		 125 unsigned int operands;
126
127 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
128 of given register, displacement, memory operands and immediate
47926f60 129 operands. */
252b5132
RH		 130 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
131
132 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 133 use OP[i] for the corresponding operand. */
252b5132
RH		 134 unsigned int types[MAX_OPERANDS];
135
520dc8e8
AM		 136 /* Displacement expression, immediate expression, or register for each
137 operand. */
138 union i386_op op[MAX_OPERANDS];
252b5132 139
3e73aa7c
JH		 140 /* Flags for operands. */
141 unsigned int flags[MAX_OPERANDS];
142#define Operand_PCrel 1
143
252b5132 144 /* Relocation type for operand */
f86103b7 145 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 146
252b5132
RH		 147 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
148 the base index byte below. */
149 const reg_entry *base_reg;
150 const reg_entry *index_reg;
151 unsigned int log2_scale_factor;
152
153 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 154 explicit segment overrides are given. */
ce8a8b2f 155 const seg_entry *seg[2];
252b5132
RH		 156
157 /* PREFIX holds all the given prefix opcodes (usually null).
158 PREFIXES is the number of prefix opcodes. */
159 unsigned int prefixes;
160 unsigned char prefix[MAX_PREFIXES];
161
162 /* RM and SIB are the modrm byte and the sib byte where the
163 addressing modes of this insn are encoded. */
164
165 modrm_byte rm;
3e73aa7c 166 rex_byte rex;
252b5132
RH		 167 sib_byte sib;
168 };
169
170typedef struct _i386_insn i386_insn;
171
172/* List of chars besides those in app.c:symbol_chars that can start an
173 operand. Used to prevent the scrubber eating vital white-space. */
32137342 174const char extra_symbol_chars[] = "*%-(["
252b5132 175#ifdef LEX_AT
32137342
NC		 176 "@"
177#endif
178#ifdef LEX_QM
179 "?"
252b5132 180#endif
32137342 181 ;
252b5132 182
29b0f896
AM		 183#if (defined (TE_I386AIX) \
184 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 185 && !defined (TE_GNU) \
29b0f896 186 && !defined (TE_LINUX) \
32137342 187 && !defined (TE_NETWARE) \
29b0f896
AM		 188 && !defined (TE_FreeBSD) \
189 && !defined (TE_NetBSD)))
252b5132 190/* This array holds the chars that always start a comment. If the
b3b91714
AM		 191 pre-processor is disabled, these aren't very useful. The option
192 --divide will remove '/' from this list. */
193const char *i386_comment_chars = "#/";
194#define SVR4_COMMENT_CHARS 1
252b5132 195#define PREFIX_SEPARATOR '\\'
252b5132 196
b3b91714
AM		 197#else
198const char *i386_comment_chars = "#";
199#define PREFIX_SEPARATOR '/'
200#endif
201
252b5132
RH		 202/* This array holds the chars that only start a comment at the beginning of
203 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 204 .line and .file directives will appear in the pre-processed output.
205 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 206 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 207 #NO_APP at the beginning of its output.
208 Also note that comments started like this one will always work if
252b5132 209 '/' isn't otherwise defined. */
b3b91714 210const char line_comment_chars[] = "#/";
252b5132 211
63a0b638 212const char line_separator_chars[] = ";";
252b5132 213
ce8a8b2f
AM		 214/* Chars that can be used to separate mant from exp in floating point
215 nums. */
252b5132
RH		 216const char EXP_CHARS[] = "eE";
217
ce8a8b2f
AM		 218/* Chars that mean this number is a floating point constant
219 As in 0f12.456
220 or 0d1.2345e12. */
252b5132
RH		 221const char FLT_CHARS[] = "fFdDxX";
222
ce8a8b2f 223/* Tables for lexical analysis. */
252b5132
RH		 224static char mnemonic_chars[256];
225static char register_chars[256];
226static char operand_chars[256];
227static char identifier_chars[256];
228static char digit_chars[256];
229
ce8a8b2f 230/* Lexical macros. */
252b5132
RH		 231#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
232#define is_operand_char(x) (operand_chars[(unsigned char) x])
233#define is_register_char(x) (register_chars[(unsigned char) x])
234#define is_space_char(x) ((x) == ' ')
235#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
236#define is_digit_char(x) (digit_chars[(unsigned char) x])
237
0234cb7c 238/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 239static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
240
241/* md_assemble() always leaves the strings it's passed unaltered. To
242 effect this we maintain a stack of saved characters that we've smashed
243 with '\0's (indicating end of strings for various sub-fields of the
47926f60 244 assembler instruction). */
252b5132 245static char save_stack[32];
ce8a8b2f 246static char *save_stack_p;
252b5132
RH		 247#define END_STRING_AND_SAVE(s) \
248 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
249#define RESTORE_END_STRING(s) \
250 do { *(s) = *--save_stack_p; } while (0)
251
47926f60 252/* The instruction we're assembling. */
252b5132
RH		 253static i386_insn i;
254
255/* Possible templates for current insn. */
256static const templates *current_templates;
257
31b2323c
L		 258/* Per instruction expressionS buffers: max displacements & immediates. */
259static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
260static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 261
47926f60
KH		 262/* Current operand we are working on. */
263static int this_operand;
252b5132 264
3e73aa7c
JH		 265/* We support four different modes. FLAG_CODE variable is used to distinguish
266 these. */
267
268enum flag_code {
269 CODE_32BIT,
270 CODE_16BIT,
271 CODE_64BIT };
f3c180ae 272#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
3e73aa7c
JH		 273
274static enum flag_code flag_code;
4fa24527 275static unsigned int object_64bit;
3e73aa7c
JH		 276static int use_rela_relocations = 0;
277
278/* The names used to print error messages. */
b77a7acd 279static const char *flag_code_names[] =
3e73aa7c
JH		 280 {
281 "32",
282 "16",
283 "64"
284 };
252b5132 285
47926f60
KH		 286/* 1 for intel syntax,
287 0 if att syntax. */
288static int intel_syntax = 0;
252b5132 289
47926f60
KH		 290/* 1 if register prefix % not required. */
291static int allow_naked_reg = 0;
252b5132 292
2ca3ace5
L		 293/* Register prefix used for error message. */
294static const char *register_prefix = "%";
295
47926f60
KH		 296/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
297 leave, push, and pop instructions so that gcc has the same stack
298 frame as in 32 bit mode. */
299static char stackop_size = '\0';
eecb386c 300
12b55ccc
L		 301/* Non-zero to optimize code alignment. */
302int optimize_align_code = 1;
303
47926f60
KH		 304/* Non-zero to quieten some warnings. */
305static int quiet_warnings = 0;
a38cf1db 306
47926f60
KH		 307/* CPU name. */
308static const char *cpu_arch_name = NULL;
5c6af06e 309static const char *cpu_sub_arch_name = NULL;
a38cf1db 310
47926f60 311/* CPU feature flags. */
29b0f896 312static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
a38cf1db 313
ccc9c027
L		 314/* If we have selected a cpu we are generating instructions for. */
315static int cpu_arch_tune_set = 0;
316
9103f4f4
L		 317/* Cpu we are generating instructions for. */
318static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
319
320/* CPU feature flags of cpu we are generating instructions for. */
321static unsigned int cpu_arch_tune_flags = 0;
322
ccc9c027
L		 323/* CPU instruction set architecture used. */
324static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
325
9103f4f4
L		 326/* CPU feature flags of instruction set architecture used. */
327static unsigned int cpu_arch_isa_flags = 0;
328
fddf5b5b
AM		 329/* If set, conditional jumps are not automatically promoted to handle
330 larger than a byte offset. */
331static unsigned int no_cond_jump_promotion = 0;
332
29b0f896 333/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 334static symbolS *GOT_symbol;
29b0f896 335
a4447b93
RH		 336/* The dwarf2 return column, adjusted for 32 or 64 bit. */
337unsigned int x86_dwarf2_return_column;
338
339/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
340int x86_cie_data_alignment;
341
252b5132 342/* Interface to relax_segment.
fddf5b5b
AM		 343 There are 3 major relax states for 386 jump insns because the
344 different types of jumps add different sizes to frags when we're
345 figuring out what sort of jump to choose to reach a given label. */
252b5132 346
47926f60 347/* Types. */
93c2a809
AM		 348#define UNCOND_JUMP 0
349#define COND_JUMP 1
350#define COND_JUMP86 2
fddf5b5b 351
47926f60 352/* Sizes. */
252b5132
RH		 353#define CODE16 1
354#define SMALL 0
29b0f896 355#define SMALL16 (SMALL | CODE16)
252b5132 356#define BIG 2
29b0f896 357#define BIG16 (BIG | CODE16)
252b5132
RH		 358
359#ifndef INLINE
360#ifdef __GNUC__
361#define INLINE __inline__
362#else
363#define INLINE
364#endif
365#endif
366
fddf5b5b
AM		 367#define ENCODE_RELAX_STATE(type, size) \
368 ((relax_substateT) (((type) << 2) | (size)))
369#define TYPE_FROM_RELAX_STATE(s) \
370 ((s) >> 2)
371#define DISP_SIZE_FROM_RELAX_STATE(s) \
372 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 373
374/* This table is used by relax_frag to promote short jumps to long
375 ones where necessary. SMALL (short) jumps may be promoted to BIG
376 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
377 don't allow a short jump in a 32 bit code segment to be promoted to
378 a 16 bit offset jump because it's slower (requires data size
379 prefix), and doesn't work, unless the destination is in the bottom
380 64k of the code segment (The top 16 bits of eip are zeroed). */
381
382const relax_typeS md_relax_table[] =
383{
24eab124
AM		 384 /* The fields are:
385 1) most positive reach of this state,
386 2) most negative reach of this state,
93c2a809 387 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 388 4) which index into the table to try if we can't fit into this one. */
252b5132 389
fddf5b5b 390 /* UNCOND_JUMP states. */
93c2a809
AM		 391 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
392 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
393 /* dword jmp adds 4 bytes to frag:
394 0 extra opcode bytes, 4 displacement bytes. */
252b5132 395 {0, 0, 4, 0},
93c2a809
AM		 396 /* word jmp adds 2 byte2 to frag:
397 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 398 {0, 0, 2, 0},
399
93c2a809
AM		 400 /* COND_JUMP states. */
401 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
402 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
403 /* dword conditionals adds 5 bytes to frag:
404 1 extra opcode byte, 4 displacement bytes. */
405 {0, 0, 5, 0},
fddf5b5b 406 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 407 1 extra opcode byte, 2 displacement bytes. */
408 {0, 0, 3, 0},
409
410 /* COND_JUMP86 states. */
411 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
412 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
413 /* dword conditionals adds 5 bytes to frag:
414 1 extra opcode byte, 4 displacement bytes. */
415 {0, 0, 5, 0},
416 /* word conditionals add 4 bytes to frag:
417 1 displacement byte and a 3 byte long branch insn. */
418 {0, 0, 4, 0}
252b5132
RH		 419};
420
9103f4f4
L		 421static const arch_entry cpu_arch[] =
422{
423 {"generic32", PROCESSOR_GENERIC32,
d32cad65 424 Cpu186|Cpu286|Cpu386},
9103f4f4 425 {"generic64", PROCESSOR_GENERIC64,
d32cad65 426 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 427 |CpuMMX2|CpuSSE|CpuSSE2},
428 {"i8086", PROCESSOR_UNKNOWN,
d32cad65 429 0},
9103f4f4 430 {"i186", PROCESSOR_UNKNOWN,
d32cad65 431 Cpu186},
9103f4f4 432 {"i286", PROCESSOR_UNKNOWN,
d32cad65 433 Cpu186|Cpu286},
76bc74dc 434 {"i386", PROCESSOR_I386,
d32cad65 435 Cpu186|Cpu286|Cpu386},
9103f4f4 436 {"i486", PROCESSOR_I486,
d32cad65 437 Cpu186|Cpu286|Cpu386|Cpu486},
9103f4f4 438 {"i586", PROCESSOR_PENTIUM,
d32cad65 439 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
9103f4f4 440 {"i686", PROCESSOR_PENTIUMPRO,
d32cad65 441 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
9103f4f4 442 {"pentium", PROCESSOR_PENTIUM,
d32cad65 443 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
9103f4f4 444 {"pentiumpro",PROCESSOR_PENTIUMPRO,
d32cad65 445 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
9103f4f4 446 {"pentiumii", PROCESSOR_PENTIUMPRO,
d32cad65 447 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX},
9103f4f4 448 {"pentiumiii",PROCESSOR_PENTIUMPRO,
d32cad65 449 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE},
9103f4f4 450 {"pentium4", PROCESSOR_PENTIUM4,
d32cad65 451 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 452 |CpuMMX2|CpuSSE|CpuSSE2},
453 {"prescott", PROCESSOR_NOCONA,
d32cad65 454 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 455 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
456 {"nocona", PROCESSOR_NOCONA,
d32cad65 457 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4 458 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
ef05d495 459 {"yonah", PROCESSOR_CORE,
d32cad65 460 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4 461 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
ef05d495 462 {"core", PROCESSOR_CORE,
d32cad65 463 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
ef05d495
L		 464 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
465 {"merom", PROCESSOR_CORE2,
466 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
467 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
468 {"core2", PROCESSOR_CORE2,
469 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
470 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
9103f4f4 471 {"k6", PROCESSOR_K6,
d32cad65 472 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX},
9103f4f4 473 {"k6_2", PROCESSOR_K6,
d32cad65 474 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow},
9103f4f4 475 {"athlon", PROCESSOR_ATHLON,
d32cad65 476 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 477 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
478 {"sledgehammer", PROCESSOR_K8,
d32cad65 479 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 480 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
481 {"opteron", PROCESSOR_K8,
d32cad65 482 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 483 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
484 {"k8", PROCESSOR_K8,
d32cad65 485 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4 486 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
050dfa73 487 {"amdfam10", PROCESSOR_AMDFAM10,
d32cad65
L		 488 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuSledgehammer
489 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a
490 |CpuABM},
9103f4f4
L		 491 {".mmx", PROCESSOR_UNKNOWN,
492 CpuMMX},
493 {".sse", PROCESSOR_UNKNOWN,
494 CpuMMX|CpuMMX2|CpuSSE},
495 {".sse2", PROCESSOR_UNKNOWN,
496 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2},
497 {".sse3", PROCESSOR_UNKNOWN,
498 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
ef05d495
L		 499 {".ssse3", PROCESSOR_UNKNOWN,
500 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
42903f7f
L		 501 {".sse4.1", PROCESSOR_UNKNOWN,
502 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1},
381d071f
L		 503 {".sse4.2", PROCESSOR_UNKNOWN,
504 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4},
505 {".sse4", PROCESSOR_UNKNOWN,
506 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4},
9103f4f4
L		 507 {".3dnow", PROCESSOR_UNKNOWN,
508 CpuMMX|Cpu3dnow},
509 {".3dnowa", PROCESSOR_UNKNOWN,
510 CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
511 {".padlock", PROCESSOR_UNKNOWN,
512 CpuPadLock},
513 {".pacifica", PROCESSOR_UNKNOWN,
514 CpuSVME},
515 {".svme", PROCESSOR_UNKNOWN,
050dfa73
MM		 516 CpuSVME},
517 {".sse4a", PROCESSOR_UNKNOWN,
518 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a},
519 {".abm", PROCESSOR_UNKNOWN,
520 CpuABM}
e413e4e9
AM		 521};
522
29b0f896
AM		 523const pseudo_typeS md_pseudo_table[] =
524{
525#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
526 {"align", s_align_bytes, 0},
527#else
528 {"align", s_align_ptwo, 0},
529#endif
530 {"arch", set_cpu_arch, 0},
531#ifndef I386COFF
532 {"bss", s_bss, 0},
533#endif
534 {"ffloat", float_cons, 'f'},
535 {"dfloat", float_cons, 'd'},
536 {"tfloat", float_cons, 'x'},
537 {"value", cons, 2},
d182319b 538 {"slong", signed_cons, 4},
29b0f896
AM		 539 {"noopt", s_ignore, 0},
540 {"optim", s_ignore, 0},
541 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
542 {"code16", set_code_flag, CODE_16BIT},
543 {"code32", set_code_flag, CODE_32BIT},
544 {"code64", set_code_flag, CODE_64BIT},
545 {"intel_syntax", set_intel_syntax, 1},
546 {"att_syntax", set_intel_syntax, 0},
3b22753a
L		 547#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
548 {"largecomm", handle_large_common, 0},
07a53e5c 549#else
e3bb37b5 550 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 551 {"loc", dwarf2_directive_loc, 0},
552 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 553#endif
6482c264
NC		 554#ifdef TE_PE
555 {"secrel32", pe_directive_secrel, 0},
556#endif
29b0f896
AM		 557 {0, 0, 0}
558};
559
560/* For interface with expression (). */
561extern char *input_line_pointer;
562
563/* Hash table for instruction mnemonic lookup. */
564static struct hash_control *op_hash;
565
566/* Hash table for register lookup. */
567static struct hash_control *reg_hash;
568\f
252b5132 569void
e3bb37b5 570i386_align_code (fragS *fragP, int count)
252b5132 571{
ce8a8b2f
AM		 572 /* Various efficient no-op patterns for aligning code labels.
573 Note: Don't try to assemble the instructions in the comments.
574 0L and 0w are not legal. */
252b5132
RH		 575 static const char f32_1[] =
576 {0x90}; /* nop */
577 static const char f32_2[] =
ccc9c027 578 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 579 static const char f32_3[] =
580 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
581 static const char f32_4[] =
582 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
583 static const char f32_5[] =
584 {0x90, /* nop */
585 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
586 static const char f32_6[] =
587 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
588 static const char f32_7[] =
589 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
590 static const char f32_8[] =
591 {0x90, /* nop */
592 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
593 static const char f32_9[] =
594 {0x89,0xf6, /* movl %esi,%esi */
595 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
596 static const char f32_10[] =
597 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
598 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
599 static const char f32_11[] =
600 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
601 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
602 static const char f32_12[] =
603 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
604 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
605 static const char f32_13[] =
606 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
607 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
608 static const char f32_14[] =
609 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
610 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 611 static const char f16_3[] =
612 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 613 static const char f16_4[] =
614 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
615 static const char f16_5[] =
616 {0x90, /* nop */
617 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
618 static const char f16_6[] =
619 {0x89,0xf6, /* mov %si,%si */
620 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
621 static const char f16_7[] =
622 {0x8d,0x74,0x00, /* lea 0(%si),%si */
623 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
624 static const char f16_8[] =
625 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
626 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 627 static const char jump_31[] =
628 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
629 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
630 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
631 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 632 static const char *const f32_patt[] = {
633 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 634 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 635 };
636 static const char *const f16_patt[] = {
76bc74dc 637 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 638 };
ccc9c027
L		 639 /* nopl (%[re]ax) */
640 static const char alt_3[] =
641 {0x0f,0x1f,0x00};
642 /* nopl 0(%[re]ax) */
643 static const char alt_4[] =
644 {0x0f,0x1f,0x40,0x00};
645 /* nopl 0(%[re]ax,%[re]ax,1) */
646 static const char alt_5[] =
647 {0x0f,0x1f,0x44,0x00,0x00};
648 /* nopw 0(%[re]ax,%[re]ax,1) */
649 static const char alt_6[] =
650 {0x66,0x0f,0x1f,0x44,0x00,0x00};
651 /* nopl 0L(%[re]ax) */
652 static const char alt_7[] =
653 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
654 /* nopl 0L(%[re]ax,%[re]ax,1) */
655 static const char alt_8[] =
656 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
657 /* nopw 0L(%[re]ax,%[re]ax,1) */
658 static const char alt_9[] =
659 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
660 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
661 static const char alt_10[] =
662 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
663 /* data16
664 nopw %cs:0L(%[re]ax,%[re]ax,1) */
665 static const char alt_long_11[] =
666 {0x66,
667 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
668 /* data16
669 data16
670 nopw %cs:0L(%[re]ax,%[re]ax,1) */
671 static const char alt_long_12[] =
672 {0x66,
673 0x66,
674 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
675 /* data16
676 data16
677 data16
678 nopw %cs:0L(%[re]ax,%[re]ax,1) */
679 static const char alt_long_13[] =
680 {0x66,
681 0x66,
682 0x66,
683 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
684 /* data16
685 data16
686 data16
687 data16
688 nopw %cs:0L(%[re]ax,%[re]ax,1) */
689 static const char alt_long_14[] =
690 {0x66,
691 0x66,
692 0x66,
693 0x66,
694 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
695 /* data16
696 data16
697 data16
698 data16
699 data16
700 nopw %cs:0L(%[re]ax,%[re]ax,1) */
701 static const char alt_long_15[] =
702 {0x66,
703 0x66,
704 0x66,
705 0x66,
706 0x66,
707 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
708 /* nopl 0(%[re]ax,%[re]ax,1)
709 nopw 0(%[re]ax,%[re]ax,1) */
710 static const char alt_short_11[] =
711 {0x0f,0x1f,0x44,0x00,0x00,
712 0x66,0x0f,0x1f,0x44,0x00,0x00};
713 /* nopw 0(%[re]ax,%[re]ax,1)
714 nopw 0(%[re]ax,%[re]ax,1) */
715 static const char alt_short_12[] =
716 {0x66,0x0f,0x1f,0x44,0x00,0x00,
717 0x66,0x0f,0x1f,0x44,0x00,0x00};
718 /* nopw 0(%[re]ax,%[re]ax,1)
719 nopl 0L(%[re]ax) */
720 static const char alt_short_13[] =
721 {0x66,0x0f,0x1f,0x44,0x00,0x00,
722 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
723 /* nopl 0L(%[re]ax)
724 nopl 0L(%[re]ax) */
725 static const char alt_short_14[] =
726 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
727 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
728 /* nopl 0L(%[re]ax)
729 nopl 0L(%[re]ax,%[re]ax,1) */
730 static const char alt_short_15[] =
731 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
732 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
733 static const char *const alt_short_patt[] = {
734 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
735 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
736 alt_short_14, alt_short_15
737 };
738 static const char *const alt_long_patt[] = {
739 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
740 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
741 alt_long_14, alt_long_15
742 };
252b5132 743
76bc74dc
L		 744 /* Only align for at least a positive non-zero boundary. */
745 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 746 return;
3e73aa7c 747
ccc9c027
L		 748 /* We need to decide which NOP sequence to use for 32bit and
749 64bit. When -mtune= is used:
4eed87de 750
76bc74dc
L		 751 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
752 PROCESSOR_GENERIC32, f32_patt will be used.
753 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
754 PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
755 alt_long_patt will be used.
756 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
757 PROCESSOR_AMDFAM10, alt_short_patt will be used.
ccc9c027 758
76bc74dc
L		 759 When -mtune= isn't used, alt_long_patt will be used if
760 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
761 be used.
ccc9c027
L		 762
763 When -march= or .arch is used, we can't use anything beyond
764 cpu_arch_isa_flags. */
765
766 if (flag_code == CODE_16BIT)
767 {
ccc9c027 768 if (count > 8)
33fef721 769 {
76bc74dc
L		 770 memcpy (fragP->fr_literal + fragP->fr_fix,
771 jump_31, count);
772 /* Adjust jump offset. */
773 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 774 }
76bc74dc
L		 775 else
776 memcpy (fragP->fr_literal + fragP->fr_fix,
777 f16_patt[count - 1], count);
252b5132 778 }
33fef721 779 else
ccc9c027
L		 780 {
781 const char *const *patt = NULL;
782
783 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
784 {
785 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
786 switch (cpu_arch_tune)
787 {
788 case PROCESSOR_UNKNOWN:
789 /* We use cpu_arch_isa_flags to check if we SHOULD
790 optimize for Cpu686. */
791 if ((cpu_arch_isa_flags & Cpu686) != 0)
76bc74dc 792 patt = alt_long_patt;
ccc9c027
L		 793 else
794 patt = f32_patt;
795 break;
ccc9c027
L		 796 case PROCESSOR_PENTIUMPRO:
797 case PROCESSOR_PENTIUM4:
798 case PROCESSOR_NOCONA:
ef05d495 799 case PROCESSOR_CORE:
76bc74dc
L		 800 case PROCESSOR_CORE2:
801 case PROCESSOR_GENERIC64:
802 patt = alt_long_patt;
803 break;
ccc9c027
L		 804 case PROCESSOR_K6:
805 case PROCESSOR_ATHLON:
806 case PROCESSOR_K8:
4eed87de 807 case PROCESSOR_AMDFAM10:
ccc9c027
L		 808 patt = alt_short_patt;
809 break;
76bc74dc 810 case PROCESSOR_I386:
ccc9c027
L		 811 case PROCESSOR_I486:
812 case PROCESSOR_PENTIUM:
813 case PROCESSOR_GENERIC32:
814 patt = f32_patt;
815 break;
4eed87de 816 }
ccc9c027
L		 817 }
818 else
819 {
820 switch (cpu_arch_tune)
821 {
822 case PROCESSOR_UNKNOWN:
823 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
824 PROCESSOR_UNKNOWN. */
825 abort ();
826 break;
827
76bc74dc 828 case PROCESSOR_I386:
ccc9c027
L		 829 case PROCESSOR_I486:
830 case PROCESSOR_PENTIUM:
ccc9c027
L		 831 case PROCESSOR_K6:
832 case PROCESSOR_ATHLON:
833 case PROCESSOR_K8:
4eed87de 834 case PROCESSOR_AMDFAM10:
ccc9c027
L		 835 case PROCESSOR_GENERIC32:
836 /* We use cpu_arch_isa_flags to check if we CAN optimize
837 for Cpu686. */
838 if ((cpu_arch_isa_flags & Cpu686) != 0)
839 patt = alt_short_patt;
840 else
841 patt = f32_patt;
842 break;
76bc74dc
L		 843 case PROCESSOR_PENTIUMPRO:
844 case PROCESSOR_PENTIUM4:
845 case PROCESSOR_NOCONA:
846 case PROCESSOR_CORE:
ef05d495 847 case PROCESSOR_CORE2:
ccc9c027
L		 848 if ((cpu_arch_isa_flags & Cpu686) != 0)
849 patt = alt_long_patt;
850 else
851 patt = f32_patt;
852 break;
853 case PROCESSOR_GENERIC64:
76bc74dc 854 patt = alt_long_patt;
ccc9c027 855 break;
4eed87de 856 }
ccc9c027
L		 857 }
858
76bc74dc
L		 859 if (patt == f32_patt)
860 {
861 /* If the padding is less than 15 bytes, we use the normal
862 ones. Otherwise, we use a jump instruction and adjust
863 its offset. */
864 if (count < 15)
865 memcpy (fragP->fr_literal + fragP->fr_fix,
866 patt[count - 1], count);
867 else
868 {
869 memcpy (fragP->fr_literal + fragP->fr_fix,
870 jump_31, count);
871 /* Adjust jump offset. */
872 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
873 }
874 }
875 else
876 {
877 /* Maximum length of an instruction is 15 byte. If the
878 padding is greater than 15 bytes and we don't use jump,
879 we have to break it into smaller pieces. */
880 int padding = count;
881 while (padding > 15)
882 {
883 padding -= 15;
884 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
885 patt [14], 15);
886 }
887
888 if (padding)
889 memcpy (fragP->fr_literal + fragP->fr_fix,
890 patt [padding - 1], padding);
891 }
ccc9c027 892 }
33fef721 893 fragP->fr_var = count;
252b5132
RH		 894}
895
252b5132 896static INLINE unsigned int
e3bb37b5 897mode_from_disp_size (unsigned int t)
252b5132 898{
3e73aa7c 899 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
252b5132
RH		 900}
901
902static INLINE int
e3bb37b5 903fits_in_signed_byte (offsetT num)
252b5132
RH		 904{
905 return (num >= -128) && (num <= 127);
47926f60 906}
252b5132
RH		 907
908static INLINE int
e3bb37b5 909fits_in_unsigned_byte (offsetT num)
252b5132
RH		 910{
911 return (num & 0xff) == num;
47926f60 912}
252b5132
RH		 913
914static INLINE int
e3bb37b5 915fits_in_unsigned_word (offsetT num)
252b5132
RH		 916{
917 return (num & 0xffff) == num;
47926f60 918}
252b5132
RH		 919
920static INLINE int
e3bb37b5 921fits_in_signed_word (offsetT num)
252b5132
RH		 922{
923 return (-32768 <= num) && (num <= 32767);
47926f60 924}
2a962e6d 925
3e73aa7c 926static INLINE int
e3bb37b5 927fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 928{
929#ifndef BFD64
930 return 1;
931#else
932 return (!(((offsetT) -1 << 31) & num)
933 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
934#endif
935} /* fits_in_signed_long() */
2a962e6d 936
3e73aa7c 937static INLINE int
e3bb37b5 938fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 939{
940#ifndef BFD64
941 return 1;
942#else
943 return (num & (((offsetT) 2 << 31) - 1)) == num;
944#endif
945} /* fits_in_unsigned_long() */
252b5132 946
1509aa9a 947static unsigned int
e3bb37b5 948smallest_imm_type (offsetT num)
252b5132 949{
d32cad65 950 if (cpu_arch_flags != (Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
e413e4e9
AM		 951 {
952 /* This code is disabled on the 486 because all the Imm1 forms
953 in the opcode table are slower on the i486. They're the
954 versions with the implicitly specified single-position
955 displacement, which has another syntax if you really want to
956 use that form. */
957 if (num == 1)
3e73aa7c 958 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
e413e4e9 959 }
252b5132 960 return (fits_in_signed_byte (num)
3e73aa7c 961 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 962 : fits_in_unsigned_byte (num)
3e73aa7c 963 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 964 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
3e73aa7c
JH		 965 ? (Imm16 | Imm32 | Imm32S | Imm64)
966 : fits_in_signed_long (num)
967 ? (Imm32 | Imm32S | Imm64)
968 : fits_in_unsigned_long (num)
969 ? (Imm32 | Imm64)
970 : Imm64);
47926f60 971}
252b5132 972
847f7ad4 973static offsetT
e3bb37b5 974offset_in_range (offsetT val, int size)
847f7ad4 975{
508866be 976 addressT mask;
ba2adb93 977
847f7ad4
AM		 978 switch (size)
979 {
508866be
L		 980 case 1: mask = ((addressT) 1 << 8) - 1; break;
981 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 982 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 983#ifdef BFD64
984 case 8: mask = ((addressT) 2 << 63) - 1; break;
985#endif
47926f60 986 default: abort ();
847f7ad4
AM		 987 }
988
ba2adb93 989 /* If BFD64, sign extend val. */
3e73aa7c
JH		 990 if (!use_rela_relocations)
991 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
992 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 993
47926f60 994 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 995 {
996 char buf1[40], buf2[40];
997
998 sprint_value (buf1, val);
999 sprint_value (buf2, val & mask);
1000 as_warn (_("%s shortened to %s"), buf1, buf2);
1001 }
1002 return val & mask;
1003}
1004
252b5132
RH		 1005/* Returns 0 if attempting to add a prefix where one from the same
1006 class already exists, 1 if non rep/repne added, 2 if rep/repne
1007 added. */
1008static int
e3bb37b5 1009add_prefix (unsigned int prefix)
252b5132
RH		 1010{
1011 int ret = 1;
b1905489 1012 unsigned int q;
252b5132 1013
29b0f896
AM		 1014 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1015 && flag_code == CODE_64BIT)
b1905489 1016 {
161a04f6
L		 1017 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1018 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1019 && (prefix & (REX_R | REX_X | REX_B))))
b1905489
JB		 1020 ret = 0;
1021 q = REX_PREFIX;
1022 }
3e73aa7c 1023 else
b1905489
JB		 1024 {
1025 switch (prefix)
1026 {
1027 default:
1028 abort ();
1029
1030 case CS_PREFIX_OPCODE:
1031 case DS_PREFIX_OPCODE:
1032 case ES_PREFIX_OPCODE:
1033 case FS_PREFIX_OPCODE:
1034 case GS_PREFIX_OPCODE:
1035 case SS_PREFIX_OPCODE:
1036 q = SEG_PREFIX;
1037 break;
1038
1039 case REPNE_PREFIX_OPCODE:
1040 case REPE_PREFIX_OPCODE:
1041 ret = 2;
1042 /* fall thru */
1043 case LOCK_PREFIX_OPCODE:
1044 q = LOCKREP_PREFIX;
1045 break;
1046
1047 case FWAIT_OPCODE:
1048 q = WAIT_PREFIX;
1049 break;
1050
1051 case ADDR_PREFIX_OPCODE:
1052 q = ADDR_PREFIX;
1053 break;
1054
1055 case DATA_PREFIX_OPCODE:
1056 q = DATA_PREFIX;
1057 break;
1058 }
1059 if (i.prefix[q] != 0)
1060 ret = 0;
1061 }
252b5132 1062
b1905489 1063 if (ret)
252b5132 1064 {
b1905489
JB		 1065 if (!i.prefix[q])
1066 ++i.prefixes;
1067 i.prefix[q] |= prefix;
252b5132 1068 }
b1905489
JB		 1069 else
1070 as_bad (_("same type of prefix used twice"));
252b5132 1071
252b5132
RH		 1072 return ret;
1073}
1074
1075static void
e3bb37b5 1076set_code_flag (int value)
eecb386c 1077{
3e73aa7c
JH		 1078 flag_code = value;
1079 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1080 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
1081 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
1082 {
1083 as_bad (_("64bit mode not supported on this CPU."));
1084 }
1085 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
1086 {
1087 as_bad (_("32bit mode not supported on this CPU."));
1088 }
eecb386c
AM		 1089 stackop_size = '\0';
1090}
1091
1092static void
e3bb37b5 1093set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1094{
3e73aa7c
JH		 1095 flag_code = new_code_flag;
1096 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1097 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
9306ca4a 1098 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1099}
1100
1101static void
e3bb37b5 1102set_intel_syntax (int syntax_flag)
252b5132
RH		 1103{
1104 /* Find out if register prefixing is specified. */
1105 int ask_naked_reg = 0;
1106
1107 SKIP_WHITESPACE ();
29b0f896 1108 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1109 {
1110 char *string = input_line_pointer;
1111 int e = get_symbol_end ();
1112
47926f60 1113 if (strcmp (string, "prefix") == 0)
252b5132 1114 ask_naked_reg = 1;
47926f60 1115 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1116 ask_naked_reg = -1;
1117 else
d0b47220 1118 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1119 *input_line_pointer = e;
1120 }
1121 demand_empty_rest_of_line ();
c3332e24 1122
252b5132
RH		 1123 intel_syntax = syntax_flag;
1124
1125 if (ask_naked_reg == 0)
f86103b7
AM		 1126 allow_naked_reg = (intel_syntax
1127 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1128 else
1129 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 1130
e4a3b5a4 1131 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 1132 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 1133 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 1134}
1135
e413e4e9 1136static void
e3bb37b5 1137set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 1138{
47926f60 1139 SKIP_WHITESPACE ();
e413e4e9 1140
29b0f896 1141 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 1142 {
1143 char *string = input_line_pointer;
1144 int e = get_symbol_end ();
9103f4f4 1145 unsigned int i;
e413e4e9 1146
9103f4f4 1147 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM		 1148 {
1149 if (strcmp (string, cpu_arch[i].name) == 0)
1150 {
5c6af06e
JB		 1151 if (*string != '.')
1152 {
1153 cpu_arch_name = cpu_arch[i].name;
1154 cpu_sub_arch_name = NULL;
1155 cpu_arch_flags = (cpu_arch[i].flags
4eed87de
AM		 1156 | (flag_code == CODE_64BIT
1157 ? Cpu64 : CpuNo64));
ccc9c027 1158 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 1159 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 1160 if (!cpu_arch_tune_set)
1161 {
1162 cpu_arch_tune = cpu_arch_isa;
1163 cpu_arch_tune_flags = cpu_arch_isa_flags;
1164 }
5c6af06e
JB		 1165 break;
1166 }
1167 if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
1168 {
1169 cpu_sub_arch_name = cpu_arch[i].name;
1170 cpu_arch_flags |= cpu_arch[i].flags;
1171 }
1172 *input_line_pointer = e;
1173 demand_empty_rest_of_line ();
1174 return;
e413e4e9
AM		 1175 }
1176 }
9103f4f4 1177 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 1178 as_bad (_("no such architecture: `%s'"), string);
1179
1180 *input_line_pointer = e;
1181 }
1182 else
1183 as_bad (_("missing cpu architecture"));
1184
fddf5b5b
AM		 1185 no_cond_jump_promotion = 0;
1186 if (*input_line_pointer == ','
29b0f896 1187 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 1188 {
1189 char *string = ++input_line_pointer;
1190 int e = get_symbol_end ();
1191
1192 if (strcmp (string, "nojumps") == 0)
1193 no_cond_jump_promotion = 1;
1194 else if (strcmp (string, "jumps") == 0)
1195 ;
1196 else
1197 as_bad (_("no such architecture modifier: `%s'"), string);
1198
1199 *input_line_pointer = e;
1200 }
1201
e413e4e9
AM		 1202 demand_empty_rest_of_line ();
1203}
1204
b9d79e03
JH		 1205unsigned long
1206i386_mach ()
1207{
1208 if (!strcmp (default_arch, "x86_64"))
1209 return bfd_mach_x86_64;
1210 else if (!strcmp (default_arch, "i386"))
1211 return bfd_mach_i386_i386;
1212 else
1213 as_fatal (_("Unknown architecture"));
1214}
b9d79e03 1215\f
252b5132
RH		 1216void
1217md_begin ()
1218{
1219 const char *hash_err;
1220
47926f60 1221 /* Initialize op_hash hash table. */
252b5132
RH		 1222 op_hash = hash_new ();
1223
1224 {
29b0f896
AM		 1225 const template *optab;
1226 templates *core_optab;
252b5132 1227
47926f60
KH		 1228 /* Setup for loop. */
1229 optab = i386_optab;
252b5132
RH		 1230 core_optab = (templates *) xmalloc (sizeof (templates));
1231 core_optab->start = optab;
1232
1233 while (1)
1234 {
1235 ++optab;
1236 if (optab->name == NULL
1237 || strcmp (optab->name, (optab - 1)->name) != 0)
1238 {
1239 /* different name --> ship out current template list;
47926f60 1240 add to hash table; & begin anew. */
252b5132
RH		 1241 core_optab->end = optab;
1242 hash_err = hash_insert (op_hash,
1243 (optab - 1)->name,
1244 (PTR) core_optab);
1245 if (hash_err)
1246 {
252b5132
RH		 1247 as_fatal (_("Internal Error: Can't hash %s: %s"),
1248 (optab - 1)->name,
1249 hash_err);
1250 }
1251 if (optab->name == NULL)
1252 break;
1253 core_optab = (templates *) xmalloc (sizeof (templates));
1254 core_optab->start = optab;
1255 }
1256 }
1257 }
1258
47926f60 1259 /* Initialize reg_hash hash table. */
252b5132
RH		 1260 reg_hash = hash_new ();
1261 {
29b0f896 1262 const reg_entry *regtab;
c3fe08fa 1263 unsigned int regtab_size = i386_regtab_size;
252b5132 1264
c3fe08fa 1265 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132
RH		 1266 {
1267 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1268 if (hash_err)
3e73aa7c
JH		 1269 as_fatal (_("Internal Error: Can't hash %s: %s"),
1270 regtab->reg_name,
1271 hash_err);
252b5132
RH		 1272 }
1273 }
1274
47926f60 1275 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 1276 {
29b0f896
AM		 1277 int c;
1278 char *p;
252b5132
RH		 1279
1280 for (c = 0; c < 256; c++)
1281 {
3882b010 1282 if (ISDIGIT (c))
252b5132
RH		 1283 {
1284 digit_chars[c] = c;
1285 mnemonic_chars[c] = c;
1286 register_chars[c] = c;
1287 operand_chars[c] = c;
1288 }
3882b010 1289 else if (ISLOWER (c))
252b5132
RH		 1290 {
1291 mnemonic_chars[c] = c;
1292 register_chars[c] = c;
1293 operand_chars[c] = c;
1294 }
3882b010 1295 else if (ISUPPER (c))
252b5132 1296 {
3882b010 1297 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 1298 register_chars[c] = mnemonic_chars[c];
1299 operand_chars[c] = c;
1300 }
1301
3882b010 1302 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 1303 identifier_chars[c] = c;
1304 else if (c >= 128)
1305 {
1306 identifier_chars[c] = c;
1307 operand_chars[c] = c;
1308 }
1309 }
1310
1311#ifdef LEX_AT
1312 identifier_chars['@'] = '@';
32137342
NC		 1313#endif
1314#ifdef LEX_QM
1315 identifier_chars['?'] = '?';
1316 operand_chars['?'] = '?';
252b5132 1317#endif
252b5132 1318 digit_chars['-'] = '-';
791fe849 1319 mnemonic_chars['-'] = '-';
0003779b 1320 mnemonic_chars['.'] = '.';
252b5132
RH		 1321 identifier_chars['_'] = '_';
1322 identifier_chars['.'] = '.';
1323
1324 for (p = operand_special_chars; *p != '\0'; p++)
1325 operand_chars[(unsigned char) *p] = *p;
1326 }
1327
1328#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1329 if (IS_ELF)
252b5132
RH		 1330 {
1331 record_alignment (text_section, 2);
1332 record_alignment (data_section, 2);
1333 record_alignment (bss_section, 2);
1334 }
1335#endif
a4447b93
RH		 1336
1337 if (flag_code == CODE_64BIT)
1338 {
1339 x86_dwarf2_return_column = 16;
1340 x86_cie_data_alignment = -8;
1341 }
1342 else
1343 {
1344 x86_dwarf2_return_column = 8;
1345 x86_cie_data_alignment = -4;
1346 }
252b5132
RH		 1347}
1348
1349void
e3bb37b5 1350i386_print_statistics (FILE *file)
252b5132
RH		 1351{
1352 hash_print_statistics (file, "i386 opcode", op_hash);
1353 hash_print_statistics (file, "i386 register", reg_hash);
1354}
1355\f
252b5132
RH		 1356#ifdef DEBUG386
1357
ce8a8b2f 1358/* Debugging routines for md_assemble. */
e3bb37b5
L		 1359static void pte (template *);
1360static void pt (unsigned int);
1361static void pe (expressionS *);
1362static void ps (symbolS *);
252b5132
RH		 1363
1364static void
e3bb37b5 1365pi (char *line, i386_insn *x)
252b5132 1366{
09f131f2 1367 unsigned int i;
252b5132
RH		 1368
1369 fprintf (stdout, "%s: template ", line);
1370 pte (&x->tm);
09f131f2
JH		 1371 fprintf (stdout, " address: base %s index %s scale %x\n",
1372 x->base_reg ? x->base_reg->reg_name : "none",
1373 x->index_reg ? x->index_reg->reg_name : "none",
1374 x->log2_scale_factor);
1375 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1376 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1377 fprintf (stdout, " sib: base %x index %x scale %x\n",
1378 x->sib.base, x->sib.index, x->sib.scale);
1379 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 1380 (x->rex & REX_W) != 0,
1381 (x->rex & REX_R) != 0,
1382 (x->rex & REX_X) != 0,
1383 (x->rex & REX_B) != 0);
252b5132
RH		 1384 for (i = 0; i < x->operands; i++)
1385 {
1386 fprintf (stdout, " #%d: ", i + 1);
1387 pt (x->types[i]);
1388 fprintf (stdout, "\n");
1389 if (x->types[i]
3f4438ab 1390 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
520dc8e8 1391 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
252b5132 1392 if (x->types[i] & Imm)
520dc8e8 1393 pe (x->op[i].imms);
252b5132 1394 if (x->types[i] & Disp)
520dc8e8 1395 pe (x->op[i].disps);
252b5132
RH		 1396 }
1397}
1398
1399static void
e3bb37b5 1400pte (template *t)
252b5132 1401{
09f131f2 1402 unsigned int i;
252b5132 1403 fprintf (stdout, " %d operands ", t->operands);
47926f60 1404 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1405 if (t->extension_opcode != None)
1406 fprintf (stdout, "ext %x ", t->extension_opcode);
1407 if (t->opcode_modifier & D)
1408 fprintf (stdout, "D");
1409 if (t->opcode_modifier & W)
1410 fprintf (stdout, "W");
1411 fprintf (stdout, "\n");
1412 for (i = 0; i < t->operands; i++)
1413 {
1414 fprintf (stdout, " #%d type ", i + 1);
1415 pt (t->operand_types[i]);
1416 fprintf (stdout, "\n");
1417 }
1418}
1419
1420static void
e3bb37b5 1421pe (expressionS *e)
252b5132 1422{
24eab124 1423 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1424 fprintf (stdout, " add_number %ld (%lx)\n",
1425 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1426 if (e->X_add_symbol)
1427 {
1428 fprintf (stdout, " add_symbol ");
1429 ps (e->X_add_symbol);
1430 fprintf (stdout, "\n");
1431 }
1432 if (e->X_op_symbol)
1433 {
1434 fprintf (stdout, " op_symbol ");
1435 ps (e->X_op_symbol);
1436 fprintf (stdout, "\n");
1437 }
1438}
1439
1440static void
e3bb37b5 1441ps (symbolS *s)
252b5132
RH		 1442{
1443 fprintf (stdout, "%s type %s%s",
1444 S_GET_NAME (s),
1445 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1446 segment_name (S_GET_SEGMENT (s)));
1447}
1448
7b81dfbb 1449static struct type_name
252b5132
RH		 1450 {
1451 unsigned int mask;
1452 char *tname;
1453 }
7b81dfbb 1454const type_names[] =
252b5132
RH		 1455{
1456 { Reg8, "r8" },
1457 { Reg16, "r16" },
1458 { Reg32, "r32" },
09f131f2 1459 { Reg64, "r64" },
252b5132
RH		 1460 { Imm8, "i8" },
1461 { Imm8S, "i8s" },
1462 { Imm16, "i16" },
1463 { Imm32, "i32" },
09f131f2
JH		 1464 { Imm32S, "i32s" },
1465 { Imm64, "i64" },
252b5132
RH		 1466 { Imm1, "i1" },
1467 { BaseIndex, "BaseIndex" },
1468 { Disp8, "d8" },
1469 { Disp16, "d16" },
1470 { Disp32, "d32" },
09f131f2
JH		 1471 { Disp32S, "d32s" },
1472 { Disp64, "d64" },
252b5132
RH		 1473 { InOutPortReg, "InOutPortReg" },
1474 { ShiftCount, "ShiftCount" },
1475 { Control, "control reg" },
1476 { Test, "test reg" },
1477 { Debug, "debug reg" },
1478 { FloatReg, "FReg" },
1479 { FloatAcc, "FAcc" },
1480 { SReg2, "SReg2" },
1481 { SReg3, "SReg3" },
1482 { Acc, "Acc" },
1483 { JumpAbsolute, "Jump Absolute" },
1484 { RegMMX, "rMMX" },
3f4438ab 1485 { RegXMM, "rXMM" },
252b5132
RH		 1486 { EsSeg, "es" },
1487 { 0, "" }
1488};
1489
1490static void
1491pt (t)
1492 unsigned int t;
1493{
29b0f896 1494 const struct type_name *ty;
252b5132 1495
09f131f2
JH		 1496 for (ty = type_names; ty->mask; ty++)
1497 if (t & ty->mask)
1498 fprintf (stdout, "%s, ", ty->tname);
252b5132
RH		 1499 fflush (stdout);
1500}
1501
1502#endif /* DEBUG386 */
1503\f
252b5132 1504static bfd_reloc_code_real_type
3956db08 1505reloc (unsigned int size,
64e74474
AM		 1506 int pcrel,
1507 int sign,
1508 bfd_reloc_code_real_type other)
252b5132 1509{
47926f60 1510 if (other != NO_RELOC)
3956db08
JB		 1511 {
1512 reloc_howto_type *reloc;
1513
1514 if (size == 8)
1515 switch (other)
1516 {
64e74474
AM		 1517 case BFD_RELOC_X86_64_GOT32:
1518 return BFD_RELOC_X86_64_GOT64;
1519 break;
1520 case BFD_RELOC_X86_64_PLTOFF64:
1521 return BFD_RELOC_X86_64_PLTOFF64;
1522 break;
1523 case BFD_RELOC_X86_64_GOTPC32:
1524 other = BFD_RELOC_X86_64_GOTPC64;
1525 break;
1526 case BFD_RELOC_X86_64_GOTPCREL:
1527 other = BFD_RELOC_X86_64_GOTPCREL64;
1528 break;
1529 case BFD_RELOC_X86_64_TPOFF32:
1530 other = BFD_RELOC_X86_64_TPOFF64;
1531 break;
1532 case BFD_RELOC_X86_64_DTPOFF32:
1533 other = BFD_RELOC_X86_64_DTPOFF64;
1534 break;
1535 default:
1536 break;
3956db08 1537 }
e05278af
JB		 1538
1539 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1540 if (size == 4 && flag_code != CODE_64BIT)
1541 sign = -1;
1542
3956db08
JB		 1543 reloc = bfd_reloc_type_lookup (stdoutput, other);
1544 if (!reloc)
1545 as_bad (_("unknown relocation (%u)"), other);
1546 else if (size != bfd_get_reloc_size (reloc))
1547 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1548 bfd_get_reloc_size (reloc),
1549 size);
1550 else if (pcrel && !reloc->pc_relative)
1551 as_bad (_("non-pc-relative relocation for pc-relative field"));
1552 else if ((reloc->complain_on_overflow == complain_overflow_signed
1553 && !sign)
1554 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 1555 && sign > 0))
3956db08
JB		 1556 as_bad (_("relocated field and relocation type differ in signedness"));
1557 else
1558 return other;
1559 return NO_RELOC;
1560 }
252b5132
RH		 1561
1562 if (pcrel)
1563 {
3e73aa7c 1564 if (!sign)
3956db08 1565 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 1566 switch (size)
1567 {
1568 case 1: return BFD_RELOC_8_PCREL;
1569 case 2: return BFD_RELOC_16_PCREL;
1570 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 1571 case 8: return BFD_RELOC_64_PCREL;
252b5132 1572 }
3956db08 1573 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 1574 }
1575 else
1576 {
3956db08 1577 if (sign > 0)
e5cb08ac 1578 switch (size)
3e73aa7c
JH		 1579 {
1580 case 4: return BFD_RELOC_X86_64_32S;
1581 }
1582 else
1583 switch (size)
1584 {
1585 case 1: return BFD_RELOC_8;
1586 case 2: return BFD_RELOC_16;
1587 case 4: return BFD_RELOC_32;
1588 case 8: return BFD_RELOC_64;
1589 }
3956db08
JB		 1590 as_bad (_("cannot do %s %u byte relocation"),
1591 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 1592 }
1593
bfb32b52 1594 abort ();
252b5132
RH		 1595 return BFD_RELOC_NONE;
1596}
1597
47926f60
KH		 1598/* Here we decide which fixups can be adjusted to make them relative to
1599 the beginning of the section instead of the symbol. Basically we need
1600 to make sure that the dynamic relocations are done correctly, so in
1601 some cases we force the original symbol to be used. */
1602
252b5132 1603int
e3bb37b5 1604tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 1605{
6d249963 1606#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1607 if (!IS_ELF)
31312f95
AM		 1608 return 1;
1609
a161fe53
AM		 1610 /* Don't adjust pc-relative references to merge sections in 64-bit
1611 mode. */
1612 if (use_rela_relocations
1613 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1614 && fixP->fx_pcrel)
252b5132 1615 return 0;
31312f95 1616
8d01d9a9
AJ		 1617 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1618 and changed later by validate_fix. */
1619 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
1620 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
1621 return 0;
1622
ce8a8b2f 1623 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1624 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1625 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1626 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 1627 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1628 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1629 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1630 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 1631 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1632 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 1633 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1634 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 1635 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
1636 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 1637 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1638 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 1639 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 1640 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1641 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1642 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 1643 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 1644 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1645 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 1646 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
1647 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 1648 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
1649 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 1650 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1651 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1652 return 0;
31312f95 1653#endif
252b5132
RH		 1654 return 1;
1655}
252b5132 1656
b4cac588 1657static int
e3bb37b5 1658intel_float_operand (const char *mnemonic)
252b5132 1659{
9306ca4a
JB		 1660 /* Note that the value returned is meaningful only for opcodes with (memory)
1661 operands, hence the code here is free to improperly handle opcodes that
1662 have no operands (for better performance and smaller code). */
1663
1664 if (mnemonic[0] != 'f')
1665 return 0; /* non-math */
1666
1667 switch (mnemonic[1])
1668 {
1669 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1670 the fs segment override prefix not currently handled because no
1671 call path can make opcodes without operands get here */
1672 case 'i':
1673 return 2 /* integer op */;
1674 case 'l':
1675 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
1676 return 3; /* fldcw/fldenv */
1677 break;
1678 case 'n':
1679 if (mnemonic[2] != 'o' /* fnop */)
1680 return 3; /* non-waiting control op */
1681 break;
1682 case 'r':
1683 if (mnemonic[2] == 's')
1684 return 3; /* frstor/frstpm */
1685 break;
1686 case 's':
1687 if (mnemonic[2] == 'a')
1688 return 3; /* fsave */
1689 if (mnemonic[2] == 't')
1690 {
1691 switch (mnemonic[3])
1692 {
1693 case 'c': /* fstcw */
1694 case 'd': /* fstdw */
1695 case 'e': /* fstenv */
1696 case 's': /* fsts[gw] */
1697 return 3;
1698 }
1699 }
1700 break;
1701 case 'x':
1702 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
1703 return 0; /* fxsave/fxrstor are not really math ops */
1704 break;
1705 }
252b5132 1706
9306ca4a 1707 return 1;
252b5132
RH		 1708}
1709
1710/* This is the guts of the machine-dependent assembler. LINE points to a
1711 machine dependent instruction. This function is supposed to emit
1712 the frags/bytes it assembles to. */
1713
1714void
1715md_assemble (line)
1716 char *line;
1717{
252b5132 1718 int j;
252b5132
RH		 1719 char mnemonic[MAX_MNEM_SIZE];
1720
47926f60 1721 /* Initialize globals. */
252b5132
RH		 1722 memset (&i, '\0', sizeof (i));
1723 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 1724 i.reloc[j] = NO_RELOC;
252b5132
RH		 1725 memset (disp_expressions, '\0', sizeof (disp_expressions));
1726 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 1727 save_stack_p = save_stack;
252b5132
RH		 1728
1729 /* First parse an instruction mnemonic & call i386_operand for the operands.
1730 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 1731 start of a (possibly prefixed) mnemonic. */
252b5132 1732
29b0f896
AM		 1733 line = parse_insn (line, mnemonic);
1734 if (line == NULL)
1735 return;
252b5132 1736
29b0f896
AM		 1737 line = parse_operands (line, mnemonic);
1738 if (line == NULL)
1739 return;
252b5132 1740
4eed87de 1741 /* The order of the immediates should be reversed
050dfa73 1742 for 2 immediates extrq and insertq instructions */
4d456e3d
L		 1743 if ((i.imm_operands == 2)
1744 && ((strcmp (mnemonic, "extrq") == 0)
1745 || (strcmp (mnemonic, "insertq") == 0)))
050dfa73 1746 {
4eed87de
AM		 1747 swap_2_operands (0, 1);
1748 /* "extrq" and insertq" are the only two instructions whose operands
050dfa73
MM		 1749 have to be reversed even though they have two immediate operands.
1750 */
1751 if (intel_syntax)
1752 swap_operands ();
1753 }
1754
29b0f896
AM		 1755 /* Now we've parsed the mnemonic into a set of templates, and have the
1756 operands at hand. */
1757
1758 /* All intel opcodes have reversed operands except for "bound" and
1759 "enter". We also don't reverse intersegment "jmp" and "call"
1760 instructions with 2 immediate operands so that the immediate segment
050dfa73 1761 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 1762 if (intel_syntax
1763 && i.operands > 1
29b0f896 1764 && (strcmp (mnemonic, "bound") != 0)
30123838 1765 && (strcmp (mnemonic, "invlpga") != 0)
29b0f896
AM		 1766 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1767 swap_operands ();
1768
1769 if (i.imm_operands)
1770 optimize_imm ();
1771
b300c311
L		 1772 /* Don't optimize displacement for movabs since it only takes 64bit
1773 displacement. */
1774 if (i.disp_operands
1775 && (flag_code != CODE_64BIT
1776 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 1777 optimize_disp ();
1778
1779 /* Next, we find a template that matches the given insn,
1780 making sure the overlap of the given operands types is consistent
1781 with the template operand types. */
252b5132 1782
29b0f896
AM		 1783 if (!match_template ())
1784 return;
252b5132 1785
cd61ebfe
AM		 1786 if (intel_syntax)
1787 {
1788 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1789 if (SYSV386_COMPAT
1790 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
8a2ed489 1791 i.tm.base_opcode ^= Opcode_FloatR;
cd61ebfe
AM		 1792
1793 /* Zap movzx and movsx suffix. The suffix may have been set from
1794 "word ptr" or "byte ptr" on the source operand, but we'll use
1795 the suffix later to choose the destination register. */
1796 if ((i.tm.base_opcode & ~9) == 0x0fb6)
9306ca4a
JB		 1797 {
1798 if (i.reg_operands < 2
1799 && !i.suffix
1800 && (~i.tm.opcode_modifier
1801 & (No_bSuf
1802 | No_wSuf
1803 | No_lSuf
1804 | No_sSuf
1805 | No_xSuf
1806 | No_qSuf)))
1807 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
1808
1809 i.suffix = 0;
1810 }
cd61ebfe 1811 }
24eab124 1812
29b0f896
AM		 1813 if (i.tm.opcode_modifier & FWait)
1814 if (!add_prefix (FWAIT_OPCODE))
1815 return;
252b5132 1816
29b0f896
AM		 1817 /* Check string instruction segment overrides. */
1818 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1819 {
1820 if (!check_string ())
5dd0794d 1821 return;
29b0f896 1822 }
5dd0794d 1823
29b0f896
AM		 1824 if (!process_suffix ())
1825 return;
e413e4e9 1826
29b0f896
AM		 1827 /* Make still unresolved immediate matches conform to size of immediate
1828 given in i.suffix. */
1829 if (!finalize_imm ())
1830 return;
252b5132 1831
29b0f896
AM		 1832 if (i.types[0] & Imm1)
1833 i.imm_operands = 0; /* kludge for shift insns. */
1834 if (i.types[0] & ImplicitRegister)
1835 i.reg_operands--;
1836 if (i.types[1] & ImplicitRegister)
1837 i.reg_operands--;
1838 if (i.types[2] & ImplicitRegister)
1839 i.reg_operands--;
252b5132 1840
29b0f896
AM		 1841 if (i.tm.opcode_modifier & ImmExt)
1842 {
02fc3089
L		 1843 expressionS *exp;
1844
b7d9ef37 1845 if ((i.tm.cpu_flags & CpuSSE3) && i.operands > 0)
ca164297 1846 {
b7d9ef37 1847 /* Streaming SIMD extensions 3 Instructions have the fixed
ca164297
L		 1848 operands with an opcode suffix which is coded in the same
1849 place as an 8-bit immediate field would be. Here we check
1850 those operands and remove them afterwards. */
1851 unsigned int x;
1852
a4622f40 1853 for (x = 0; x < i.operands; x++)
ca164297 1854 if (i.op[x].regs->reg_num != x)
a540244d
L		 1855 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1856 register_prefix,
1857 i.op[x].regs->reg_name,
1858 x + 1,
1859 i.tm.name);
ca164297
L		 1860 i.operands = 0;
1861 }
1862
29b0f896
AM		 1863 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1864 opcode suffix which is coded in the same place as an 8-bit
1865 immediate field would be. Here we fake an 8-bit immediate
1866 operand from the opcode suffix stored in tm.extension_opcode. */
252b5132 1867
29b0f896 1868 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
252b5132 1869
29b0f896
AM		 1870 exp = &im_expressions[i.imm_operands++];
1871 i.op[i.operands].imms = exp;
1872 i.types[i.operands++] = Imm8;
1873 exp->X_op = O_constant;
1874 exp->X_add_number = i.tm.extension_opcode;
1875 i.tm.extension_opcode = None;
1876 }
252b5132 1877
29b0f896
AM		 1878 /* For insns with operands there are more diddles to do to the opcode. */
1879 if (i.operands)
1880 {
1881 if (!process_operands ())
1882 return;
1883 }
1884 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1885 {
1886 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1887 as_warn (_("translating to `%sp'"), i.tm.name);
1888 }
252b5132 1889
29b0f896
AM		 1890 /* Handle conversion of 'int $3' --> special int3 insn. */
1891 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1892 {
1893 i.tm.base_opcode = INT3_OPCODE;
1894 i.imm_operands = 0;
1895 }
252b5132 1896
29b0f896
AM		 1897 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1898 && i.op[0].disps->X_op == O_constant)
1899 {
1900 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1901 the absolute address given by the constant. Since ix86 jumps and
1902 calls are pc relative, we need to generate a reloc. */
1903 i.op[0].disps->X_add_symbol = &abs_symbol;
1904 i.op[0].disps->X_op = O_symbol;
1905 }
252b5132 1906
29b0f896 1907 if ((i.tm.opcode_modifier & Rex64) != 0)
161a04f6 1908 i.rex |= REX_W;
252b5132 1909
29b0f896
AM		 1910 /* For 8 bit registers we need an empty rex prefix. Also if the
1911 instruction already has a prefix, we need to convert old
1912 registers to new ones. */
773f551c 1913
29b0f896
AM		 1914 if (((i.types[0] & Reg8) != 0
1915 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1916 || ((i.types[1] & Reg8) != 0
1917 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1918 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1919 && i.rex != 0))
1920 {
1921 int x;
726c5dcd 1922
29b0f896
AM		 1923 i.rex |= REX_OPCODE;
1924 for (x = 0; x < 2; x++)
1925 {
1926 /* Look for 8 bit operand that uses old registers. */
1927 if ((i.types[x] & Reg8) != 0
1928 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 1929 {
29b0f896
AM		 1930 /* In case it is "hi" register, give up. */
1931 if (i.op[x].regs->reg_num > 3)
a540244d 1932 as_bad (_("can't encode register '%s%s' in an "
4eed87de 1933 "instruction requiring REX prefix."),
a540244d 1934 register_prefix, i.op[x].regs->reg_name);
773f551c 1935
29b0f896
AM		 1936 /* Otherwise it is equivalent to the extended register.
1937 Since the encoding doesn't change this is merely
1938 cosmetic cleanup for debug output. */
1939
1940 i.op[x].regs = i.op[x].regs + 8;
773f551c 1941 }
29b0f896
AM		 1942 }
1943 }
773f551c 1944
29b0f896
AM		 1945 if (i.rex != 0)
1946 add_prefix (REX_OPCODE | i.rex);
1947
1948 /* We are ready to output the insn. */
1949 output_insn ();
1950}
1951
1952static char *
e3bb37b5 1953parse_insn (char *line, char *mnemonic)
29b0f896
AM		 1954{
1955 char *l = line;
1956 char *token_start = l;
1957 char *mnem_p;
5c6af06e
JB		 1958 int supported;
1959 const template *t;
29b0f896
AM		 1960
1961 /* Non-zero if we found a prefix only acceptable with string insns. */
1962 const char *expecting_string_instruction = NULL;
45288df1 1963
29b0f896
AM		 1964 while (1)
1965 {
1966 mnem_p = mnemonic;
1967 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1968 {
1969 mnem_p++;
1970 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 1971 {
29b0f896
AM		 1972 as_bad (_("no such instruction: `%s'"), token_start);
1973 return NULL;
1974 }
1975 l++;
1976 }
1977 if (!is_space_char (*l)
1978 && *l != END_OF_INSN
e44823cf
JB		 1979 && (intel_syntax
1980 || (*l != PREFIX_SEPARATOR
1981 && *l != ',')))
29b0f896
AM		 1982 {
1983 as_bad (_("invalid character %s in mnemonic"),
1984 output_invalid (*l));
1985 return NULL;
1986 }
1987 if (token_start == l)
1988 {
e44823cf 1989 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 1990 as_bad (_("expecting prefix; got nothing"));
1991 else
1992 as_bad (_("expecting mnemonic; got nothing"));
1993 return NULL;
1994 }
45288df1 1995
29b0f896
AM		 1996 /* Look up instruction (or prefix) via hash table. */
1997 current_templates = hash_find (op_hash, mnemonic);
47926f60 1998
29b0f896
AM		 1999 if (*l != END_OF_INSN
2000 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2001 && current_templates
2002 && (current_templates->start->opcode_modifier & IsPrefix))
2003 {
2dd88dca
JB		 2004 if (current_templates->start->cpu_flags
2005 & (flag_code != CODE_64BIT ? Cpu64 : CpuNo64))
2006 {
2007 as_bad ((flag_code != CODE_64BIT
2008 ? _("`%s' is only supported in 64-bit mode")
2009 : _("`%s' is not supported in 64-bit mode")),
2010 current_templates->start->name);
2011 return NULL;
2012 }
29b0f896
AM		 2013 /* If we are in 16-bit mode, do not allow addr16 or data16.
2014 Similarly, in 32-bit mode, do not allow addr32 or data32. */
2015 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
2016 && flag_code != CODE_64BIT
2017 && (((current_templates->start->opcode_modifier & Size32) != 0)
2018 ^ (flag_code == CODE_16BIT)))
2019 {
2020 as_bad (_("redundant %s prefix"),
2021 current_templates->start->name);
2022 return NULL;
45288df1 2023 }
29b0f896
AM		 2024 /* Add prefix, checking for repeated prefixes. */
2025 switch (add_prefix (current_templates->start->base_opcode))
2026 {
2027 case 0:
2028 return NULL;
2029 case 2:
2030 expecting_string_instruction = current_templates->start->name;
2031 break;
2032 }
2033 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2034 token_start = ++l;
2035 }
2036 else
2037 break;
2038 }
45288df1 2039
29b0f896
AM		 2040 if (!current_templates)
2041 {
2042 /* See if we can get a match by trimming off a suffix. */
2043 switch (mnem_p[-1])
2044 {
2045 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 2046 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2047 i.suffix = SHORT_MNEM_SUFFIX;
2048 else
29b0f896
AM		 2049 case BYTE_MNEM_SUFFIX:
2050 case QWORD_MNEM_SUFFIX:
2051 i.suffix = mnem_p[-1];
2052 mnem_p[-1] = '\0';
2053 current_templates = hash_find (op_hash, mnemonic);
2054 break;
2055 case SHORT_MNEM_SUFFIX:
2056 case LONG_MNEM_SUFFIX:
2057 if (!intel_syntax)
2058 {
2059 i.suffix = mnem_p[-1];
2060 mnem_p[-1] = '\0';
2061 current_templates = hash_find (op_hash, mnemonic);
2062 }
2063 break;
252b5132 2064
29b0f896
AM		 2065 /* Intel Syntax. */
2066 case 'd':
2067 if (intel_syntax)
2068 {
9306ca4a 2069 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 2070 i.suffix = SHORT_MNEM_SUFFIX;
2071 else
2072 i.suffix = LONG_MNEM_SUFFIX;
2073 mnem_p[-1] = '\0';
2074 current_templates = hash_find (op_hash, mnemonic);
2075 }
2076 break;
2077 }
2078 if (!current_templates)
2079 {
2080 as_bad (_("no such instruction: `%s'"), token_start);
2081 return NULL;
2082 }
2083 }
252b5132 2084
29b0f896
AM		 2085 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
2086 {
2087 /* Check for a branch hint. We allow ",pt" and ",pn" for
2088 predict taken and predict not taken respectively.
2089 I'm not sure that branch hints actually do anything on loop
2090 and jcxz insns (JumpByte) for current Pentium4 chips. They
2091 may work in the future and it doesn't hurt to accept them
2092 now. */
2093 if (l[0] == ',' && l[1] == 'p')
2094 {
2095 if (l[2] == 't')
2096 {
2097 if (!add_prefix (DS_PREFIX_OPCODE))
2098 return NULL;
2099 l += 3;
2100 }
2101 else if (l[2] == 'n')
2102 {
2103 if (!add_prefix (CS_PREFIX_OPCODE))
2104 return NULL;
2105 l += 3;
2106 }
2107 }
2108 }
2109 /* Any other comma loses. */
2110 if (*l == ',')
2111 {
2112 as_bad (_("invalid character %s in mnemonic"),
2113 output_invalid (*l));
2114 return NULL;
2115 }
252b5132 2116
29b0f896 2117 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 2118 supported = 0;
2119 for (t = current_templates->start; t < current_templates->end; ++t)
2120 {
2121 if (!((t->cpu_flags & ~(Cpu64 | CpuNo64))
2122 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))))
64e74474 2123 supported |= 1;
5c6af06e 2124 if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64)))
64e74474 2125 supported |= 2;
5c6af06e
JB		 2126 }
2127 if (!(supported & 2))
2128 {
2129 as_bad (flag_code == CODE_64BIT
2130 ? _("`%s' is not supported in 64-bit mode")
2131 : _("`%s' is only supported in 64-bit mode"),
2132 current_templates->start->name);
2133 return NULL;
2134 }
2135 if (!(supported & 1))
29b0f896 2136 {
5c6af06e
JB		 2137 as_warn (_("`%s' is not supported on `%s%s'"),
2138 current_templates->start->name,
2139 cpu_arch_name,
2140 cpu_sub_arch_name ? cpu_sub_arch_name : "");
29b0f896
AM		 2141 }
2142 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
2143 {
2144 as_warn (_("use .code16 to ensure correct addressing mode"));
2145 }
252b5132 2146
29b0f896 2147 /* Check for rep/repne without a string instruction. */
f41bbced 2148 if (expecting_string_instruction)
29b0f896 2149 {
f41bbced
JB		 2150 static templates override;
2151
2152 for (t = current_templates->start; t < current_templates->end; ++t)
2153 if (t->opcode_modifier & IsString)
2154 break;
2155 if (t >= current_templates->end)
2156 {
2157 as_bad (_("expecting string instruction after `%s'"),
64e74474 2158 expecting_string_instruction);
f41bbced
JB		 2159 return NULL;
2160 }
2161 for (override.start = t; t < current_templates->end; ++t)
2162 if (!(t->opcode_modifier & IsString))
2163 break;
2164 override.end = t;
2165 current_templates = &override;
29b0f896 2166 }
252b5132 2167
29b0f896
AM		 2168 return l;
2169}
252b5132 2170
29b0f896 2171static char *
e3bb37b5 2172parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 2173{
2174 char *token_start;
3138f287 2175
29b0f896
AM		 2176 /* 1 if operand is pending after ','. */
2177 unsigned int expecting_operand = 0;
252b5132 2178
29b0f896
AM		 2179 /* Non-zero if operand parens not balanced. */
2180 unsigned int paren_not_balanced;
2181
2182 while (*l != END_OF_INSN)
2183 {
2184 /* Skip optional white space before operand. */
2185 if (is_space_char (*l))
2186 ++l;
2187 if (!is_operand_char (*l) && *l != END_OF_INSN)
2188 {
2189 as_bad (_("invalid character %s before operand %d"),
2190 output_invalid (*l),
2191 i.operands + 1);
2192 return NULL;
2193 }
2194 token_start = l; /* after white space */
2195 paren_not_balanced = 0;
2196 while (paren_not_balanced || *l != ',')
2197 {
2198 if (*l == END_OF_INSN)
2199 {
2200 if (paren_not_balanced)
2201 {
2202 if (!intel_syntax)
2203 as_bad (_("unbalanced parenthesis in operand %d."),
2204 i.operands + 1);
2205 else
2206 as_bad (_("unbalanced brackets in operand %d."),
2207 i.operands + 1);
2208 return NULL;
2209 }
2210 else
2211 break; /* we are done */
2212 }
2213 else if (!is_operand_char (*l) && !is_space_char (*l))
2214 {
2215 as_bad (_("invalid character %s in operand %d"),
2216 output_invalid (*l),
2217 i.operands + 1);
2218 return NULL;
2219 }
2220 if (!intel_syntax)
2221 {
2222 if (*l == '(')
2223 ++paren_not_balanced;
2224 if (*l == ')')
2225 --paren_not_balanced;
2226 }
2227 else
2228 {
2229 if (*l == '[')
2230 ++paren_not_balanced;
2231 if (*l == ']')
2232 --paren_not_balanced;
2233 }
2234 l++;
2235 }
2236 if (l != token_start)
2237 { /* Yes, we've read in another operand. */
2238 unsigned int operand_ok;
2239 this_operand = i.operands++;
2240 if (i.operands > MAX_OPERANDS)
2241 {
2242 as_bad (_("spurious operands; (%d operands/instruction max)"),
2243 MAX_OPERANDS);
2244 return NULL;
2245 }
2246 /* Now parse operand adding info to 'i' as we go along. */
2247 END_STRING_AND_SAVE (l);
2248
2249 if (intel_syntax)
2250 operand_ok =
2251 i386_intel_operand (token_start,
2252 intel_float_operand (mnemonic));
2253 else
2254 operand_ok = i386_operand (token_start);
2255
2256 RESTORE_END_STRING (l);
2257 if (!operand_ok)
2258 return NULL;
2259 }
2260 else
2261 {
2262 if (expecting_operand)
2263 {
2264 expecting_operand_after_comma:
2265 as_bad (_("expecting operand after ','; got nothing"));
2266 return NULL;
2267 }
2268 if (*l == ',')
2269 {
2270 as_bad (_("expecting operand before ','; got nothing"));
2271 return NULL;
2272 }
2273 }
7f3f1ea2 2274
29b0f896
AM		 2275 /* Now *l must be either ',' or END_OF_INSN. */
2276 if (*l == ',')
2277 {
2278 if (*++l == END_OF_INSN)
2279 {
2280 /* Just skip it, if it's \n complain. */
2281 goto expecting_operand_after_comma;
2282 }
2283 expecting_operand = 1;
2284 }
2285 }
2286 return l;
2287}
7f3f1ea2 2288
050dfa73 2289static void
4d456e3d 2290swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 2291{
2292 union i386_op temp_op;
2293 unsigned int temp_type;
2294 enum bfd_reloc_code_real temp_reloc;
4eed87de 2295
050dfa73
MM		 2296 temp_type = i.types[xchg2];
2297 i.types[xchg2] = i.types[xchg1];
2298 i.types[xchg1] = temp_type;
2299 temp_op = i.op[xchg2];
2300 i.op[xchg2] = i.op[xchg1];
2301 i.op[xchg1] = temp_op;
2302 temp_reloc = i.reloc[xchg2];
2303 i.reloc[xchg2] = i.reloc[xchg1];
2304 i.reloc[xchg1] = temp_reloc;
2305}
2306
29b0f896 2307static void
e3bb37b5 2308swap_operands (void)
29b0f896 2309{
b7c61d9a 2310 switch (i.operands)
050dfa73 2311 {
b7c61d9a 2312 case 4:
4d456e3d 2313 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 2314 case 3:
2315 case 2:
4d456e3d 2316 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 2317 break;
2318 default:
2319 abort ();
29b0f896 2320 }
29b0f896
AM		 2321
2322 if (i.mem_operands == 2)
2323 {
2324 const seg_entry *temp_seg;
2325 temp_seg = i.seg[0];
2326 i.seg[0] = i.seg[1];
2327 i.seg[1] = temp_seg;
2328 }
2329}
252b5132 2330
29b0f896
AM		 2331/* Try to ensure constant immediates are represented in the smallest
2332 opcode possible. */
2333static void
e3bb37b5 2334optimize_imm (void)
29b0f896
AM		 2335{
2336 char guess_suffix = 0;
2337 int op;
252b5132 2338
29b0f896
AM		 2339 if (i.suffix)
2340 guess_suffix = i.suffix;
2341 else if (i.reg_operands)
2342 {
2343 /* Figure out a suffix from the last register operand specified.
2344 We can't do this properly yet, ie. excluding InOutPortReg,
2345 but the following works for instructions with immediates.
2346 In any case, we can't set i.suffix yet. */
2347 for (op = i.operands; --op >= 0;)
2348 if (i.types[op] & Reg)
252b5132 2349 {
29b0f896
AM		 2350 if (i.types[op] & Reg8)
2351 guess_suffix = BYTE_MNEM_SUFFIX;
2352 else if (i.types[op] & Reg16)
2353 guess_suffix = WORD_MNEM_SUFFIX;
2354 else if (i.types[op] & Reg32)
2355 guess_suffix = LONG_MNEM_SUFFIX;
2356 else if (i.types[op] & Reg64)
2357 guess_suffix = QWORD_MNEM_SUFFIX;
2358 break;
252b5132 2359 }
29b0f896
AM		 2360 }
2361 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2362 guess_suffix = WORD_MNEM_SUFFIX;
2363
2364 for (op = i.operands; --op >= 0;)
2365 if (i.types[op] & Imm)
2366 {
2367 switch (i.op[op].imms->X_op)
252b5132 2368 {
29b0f896
AM		 2369 case O_constant:
2370 /* If a suffix is given, this operand may be shortened. */
2371 switch (guess_suffix)
252b5132 2372 {
29b0f896
AM		 2373 case LONG_MNEM_SUFFIX:
2374 i.types[op] |= Imm32 | Imm64;
2375 break;
2376 case WORD_MNEM_SUFFIX:
2377 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
2378 break;
2379 case BYTE_MNEM_SUFFIX:
2380 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
2381 break;
252b5132 2382 }
252b5132 2383
29b0f896
AM		 2384 /* If this operand is at most 16 bits, convert it
2385 to a signed 16 bit number before trying to see
2386 whether it will fit in an even smaller size.
2387 This allows a 16-bit operand such as $0xffe0 to
2388 be recognised as within Imm8S range. */
2389 if ((i.types[op] & Imm16)
2390 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 2391 {
29b0f896
AM		 2392 i.op[op].imms->X_add_number =
2393 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2394 }
2395 if ((i.types[op] & Imm32)
2396 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2397 == 0))
2398 {
2399 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2400 ^ ((offsetT) 1 << 31))
2401 - ((offsetT) 1 << 31));
2402 }
2403 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
252b5132 2404
29b0f896
AM		 2405 /* We must avoid matching of Imm32 templates when 64bit
2406 only immediate is available. */
2407 if (guess_suffix == QWORD_MNEM_SUFFIX)
2408 i.types[op] &= ~Imm32;
2409 break;
252b5132 2410
29b0f896
AM		 2411 case O_absent:
2412 case O_register:
2413 abort ();
2414
2415 /* Symbols and expressions. */
2416 default:
9cd96992
JB		 2417 /* Convert symbolic operand to proper sizes for matching, but don't
2418 prevent matching a set of insns that only supports sizes other
2419 than those matching the insn suffix. */
2420 {
2421 unsigned int mask, allowed = 0;
2422 const template *t;
2423
4eed87de
AM		 2424 for (t = current_templates->start;
2425 t < current_templates->end;
2426 ++t)
2427 allowed |= t->operand_types[op];
9cd96992
JB		 2428 switch (guess_suffix)
2429 {
2430 case QWORD_MNEM_SUFFIX:
2431 mask = Imm64 | Imm32S;
2432 break;
2433 case LONG_MNEM_SUFFIX:
2434 mask = Imm32;
2435 break;
2436 case WORD_MNEM_SUFFIX:
2437 mask = Imm16;
2438 break;
2439 case BYTE_MNEM_SUFFIX:
2440 mask = Imm8;
2441 break;
2442 default:
2443 mask = 0;
2444 break;
2445 }
64e74474
AM		 2446 if (mask & allowed)
2447 i.types[op] &= mask;
9cd96992 2448 }
29b0f896 2449 break;
252b5132 2450 }
29b0f896
AM		 2451 }
2452}
47926f60 2453
29b0f896
AM		 2454/* Try to use the smallest displacement type too. */
2455static void
e3bb37b5 2456optimize_disp (void)
29b0f896
AM		 2457{
2458 int op;
3e73aa7c 2459
29b0f896 2460 for (op = i.operands; --op >= 0;)
b300c311 2461 if (i.types[op] & Disp)
252b5132 2462 {
b300c311 2463 if (i.op[op].disps->X_op == O_constant)
252b5132 2464 {
b300c311 2465 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 2466
b300c311
L		 2467 if ((i.types[op] & Disp16)
2468 && (disp & ~(offsetT) 0xffff) == 0)
2469 {
2470 /* If this operand is at most 16 bits, convert
2471 to a signed 16 bit number and don't use 64bit
2472 displacement. */
2473 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
2474 i.types[op] &= ~Disp64;
2475 }
2476 if ((i.types[op] & Disp32)
2477 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2478 {
2479 /* If this operand is at most 32 bits, convert
2480 to a signed 32 bit number and don't use 64bit
2481 displacement. */
2482 disp &= (((offsetT) 2 << 31) - 1);
2483 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
2484 i.types[op] &= ~Disp64;
2485 }
2486 if (!disp && (i.types[op] & BaseIndex))
2487 {
2488 i.types[op] &= ~Disp;
2489 i.op[op].disps = 0;
2490 i.disp_operands--;
2491 }
2492 else if (flag_code == CODE_64BIT)
2493 {
2494 if (fits_in_signed_long (disp))
28a9d8f5
L		 2495 {
2496 i.types[op] &= ~Disp64;
2497 i.types[op] |= Disp32S;
2498 }
b300c311
L		 2499 if (fits_in_unsigned_long (disp))
2500 i.types[op] |= Disp32;
2501 }
2502 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
2503 && fits_in_signed_byte (disp))
2504 i.types[op] |= Disp8;
252b5132 2505 }
67a4f2b7
AO		 2506 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
2507 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
2508 {
2509 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
2510 i.op[op].disps, 0, i.reloc[op]);
2511 i.types[op] &= ~Disp;
2512 }
2513 else
b300c311
L		 2514 /* We only support 64bit displacement on constants. */
2515 i.types[op] &= ~Disp64;
252b5132 2516 }
29b0f896
AM		 2517}
2518
2519static int
e3bb37b5 2520match_template (void)
29b0f896
AM		 2521{
2522 /* Points to template once we've found it. */
2523 const template *t;
f48ff2ae 2524 unsigned int overlap0, overlap1, overlap2, overlap3;
29b0f896
AM		 2525 unsigned int found_reverse_match;
2526 int suffix_check;
f48ff2ae 2527 unsigned int operand_types [MAX_OPERANDS];
539e75ad 2528 int addr_prefix_disp;
a5c311ca 2529 unsigned int j;
29b0f896 2530
f48ff2ae
L		 2531#if MAX_OPERANDS != 4
2532# error "MAX_OPERANDS must be 4."
2533#endif
2534
29b0f896
AM		 2535#define MATCH(overlap, given, template) \
2536 ((overlap & ~JumpAbsolute) \
2537 && (((given) & (BaseIndex | JumpAbsolute)) \
2538 == ((overlap) & (BaseIndex | JumpAbsolute))))
2539
2540 /* If given types r0 and r1 are registers they must be of the same type
2541 unless the expected operand type register overlap is null.
2542 Note that Acc in a template matches every size of reg. */
2543#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2544 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2545 || ((g0) & Reg) == ((g1) & Reg) \
2546 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2547
2548 overlap0 = 0;
2549 overlap1 = 0;
2550 overlap2 = 0;
f48ff2ae 2551 overlap3 = 0;
29b0f896 2552 found_reverse_match = 0;
a5c311ca
L		 2553 for (j = 0; j < MAX_OPERANDS; j++)
2554 operand_types [j] = 0;
539e75ad 2555 addr_prefix_disp = -1;
29b0f896
AM		 2556 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
2557 ? No_bSuf
2558 : (i.suffix == WORD_MNEM_SUFFIX
2559 ? No_wSuf
2560 : (i.suffix == SHORT_MNEM_SUFFIX
2561 ? No_sSuf
2562 : (i.suffix == LONG_MNEM_SUFFIX
2563 ? No_lSuf
2564 : (i.suffix == QWORD_MNEM_SUFFIX
2565 ? No_qSuf
2566 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
2567 ? No_xSuf : 0))))));
2568
45aa61fe 2569 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 2570 {
539e75ad
L		 2571 addr_prefix_disp = -1;
2572
29b0f896
AM		 2573 /* Must have right number of operands. */
2574 if (i.operands != t->operands)
2575 continue;
2576
20592a94 2577 /* Check the suffix, except for some instructions in intel mode. */
29b0f896
AM		 2578 if ((t->opcode_modifier & suffix_check)
2579 && !(intel_syntax
9306ca4a 2580 && (t->opcode_modifier & IgnoreSize)))
29b0f896
AM		 2581 continue;
2582
a5c311ca
L		 2583 for (j = 0; j < MAX_OPERANDS; j++)
2584 operand_types [j] = t->operand_types [j];
539e75ad 2585
45aa61fe
AM		 2586 /* In general, don't allow 64-bit operands in 32-bit mode. */
2587 if (i.suffix == QWORD_MNEM_SUFFIX
2588 && flag_code != CODE_64BIT
2589 && (intel_syntax
2590 ? (!(t->opcode_modifier & IgnoreSize)
2591 && !intel_float_operand (t->name))
2592 : intel_float_operand (t->name) != 2)
539e75ad
L		 2593 && (!(operand_types[0] & (RegMMX | RegXMM))
2594 || !(operand_types[t->operands > 1] & (RegMMX | RegXMM)))
45aa61fe
AM		 2595 && (t->base_opcode != 0x0fc7
2596 || t->extension_opcode != 1 /* cmpxchg8b */))
2597 continue;
2598
29b0f896
AM		 2599 /* Do not verify operands when there are none. */
2600 else if (!t->operands)
2601 {
2602 if (t->cpu_flags & ~cpu_arch_flags)
2603 continue;
2604 /* We've found a match; break out of loop. */
2605 break;
2606 }
252b5132 2607
539e75ad
L		 2608 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
2609 into Disp32/Disp16/Disp32 operand. */
2610 if (i.prefix[ADDR_PREFIX] != 0)
2611 {
a5c311ca 2612 unsigned int DispOn = 0, DispOff = 0;
539e75ad
L		 2613
2614 switch (flag_code)
2615 {
2616 case CODE_16BIT:
2617 DispOn = Disp32;
2618 DispOff = Disp16;
2619 break;
2620 case CODE_32BIT:
2621 DispOn = Disp16;
2622 DispOff = Disp32;
2623 break;
2624 case CODE_64BIT:
2625 DispOn = Disp32;
2626 DispOff = Disp64;
2627 break;
2628 }
2629
f48ff2ae 2630 for (j = 0; j < MAX_OPERANDS; j++)
539e75ad
L		 2631 {
2632 /* There should be only one Disp operand. */
2633 if ((operand_types[j] & DispOff))
2634 {
2635 addr_prefix_disp = j;
2636 operand_types[j] |= DispOn;
2637 operand_types[j] &= ~DispOff;
2638 break;
2639 }
2640 }
2641 }
2642
2643 overlap0 = i.types[0] & operand_types[0];
29b0f896
AM		 2644 switch (t->operands)
2645 {
2646 case 1:
539e75ad 2647 if (!MATCH (overlap0, i.types[0], operand_types[0]))
29b0f896
AM		 2648 continue;
2649 break;
2650 case 2:
8b38ad71
L		 2651 /* xchg %eax, %eax is a special case. It is an aliase for nop
2652 only in 32bit mode and we can use opcode 0x90. In 64bit
2653 mode, we can't use 0x90 for xchg %eax, %eax since it should
2654 zero-extend %eax to %rax. */
2655 if (flag_code == CODE_64BIT
2656 && t->base_opcode == 0x90
2657 && i.types [0] == (Acc | Reg32)
2658 && i.types [1] == (Acc | Reg32))
2659 continue;
29b0f896 2660 case 3:
f48ff2ae 2661 case 4:
539e75ad
L		 2662 overlap1 = i.types[1] & operand_types[1];
2663 if (!MATCH (overlap0, i.types[0], operand_types[0])
2664 || !MATCH (overlap1, i.types[1], operand_types[1])
cb712a9e 2665 /* monitor in SSE3 is a very special case. The first
708587a4 2666 register and the second register may have different
381d071f 2667 sizes. The same applies to crc32 in SSE4.2. */
cb712a9e
L		 2668 || !((t->base_opcode == 0x0f01
2669 && t->extension_opcode == 0xc8)
381d071f 2670 || t->base_opcode == 0xf20f38f1
cb712a9e 2671 || CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
539e75ad 2672 operand_types[0],
cb712a9e 2673 overlap1, i.types[1],
539e75ad 2674 operand_types[1])))
29b0f896
AM		 2675 {
2676 /* Check if other direction is valid ... */
2677 if ((t->opcode_modifier & (D | FloatD)) == 0)
2678 continue;
2679
2680 /* Try reversing direction of operands. */
539e75ad
L		 2681 overlap0 = i.types[0] & operand_types[1];
2682 overlap1 = i.types[1] & operand_types[0];
2683 if (!MATCH (overlap0, i.types[0], operand_types[1])
2684 || !MATCH (overlap1, i.types[1], operand_types[0])
29b0f896 2685 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
539e75ad 2686 operand_types[1],
29b0f896 2687 overlap1, i.types[1],
539e75ad 2688 operand_types[0]))
29b0f896
AM		 2689 {
2690 /* Does not match either direction. */
2691 continue;
2692 }
2693 /* found_reverse_match holds which of D or FloatDR
2694 we've found. */
8a2ed489
L		 2695 if ((t->opcode_modifier & D))
2696 found_reverse_match = Opcode_D;
2697 else if ((t->opcode_modifier & FloatD))
2698 found_reverse_match = Opcode_FloatD;
2699 else
2700 found_reverse_match = 0;
2701 if ((t->opcode_modifier & FloatR))
2702 found_reverse_match |= Opcode_FloatR;
29b0f896 2703 }
f48ff2ae 2704 else
29b0f896 2705 {
f48ff2ae 2706 /* Found a forward 2 operand match here. */
d1cbb4db
L		 2707 switch (t->operands)
2708 {
2709 case 4:
2710 overlap3 = i.types[3] & operand_types[3];
2711 case 3:
2712 overlap2 = i.types[2] & operand_types[2];
2713 break;
2714 }
29b0f896 2715
f48ff2ae
L		 2716 switch (t->operands)
2717 {
2718 case 4:
2719 if (!MATCH (overlap3, i.types[3], operand_types[3])
2720 || !CONSISTENT_REGISTER_MATCH (overlap2,
2721 i.types[2],
2722 operand_types[2],
2723 overlap3,
2724 i.types[3],
2725 operand_types[3]))
2726 continue;
2727 case 3:
2728 /* Here we make use of the fact that there are no
2729 reverse match 3 operand instructions, and all 3
2730 operand instructions only need to be checked for
2731 register consistency between operands 2 and 3. */
2732 if (!MATCH (overlap2, i.types[2], operand_types[2])
2733 || !CONSISTENT_REGISTER_MATCH (overlap1,
2734 i.types[1],
2735 operand_types[1],
2736 overlap2,
2737 i.types[2],
2738 operand_types[2]))
2739 continue;
2740 break;
2741 }
29b0f896 2742 }
f48ff2ae 2743 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 2744 slip through to break. */
2745 }
2746 if (t->cpu_flags & ~cpu_arch_flags)
2747 {
2748 found_reverse_match = 0;
2749 continue;
2750 }
2751 /* We've found a match; break out of loop. */
2752 break;
2753 }
2754
2755 if (t == current_templates->end)
2756 {
2757 /* We found no match. */
2758 as_bad (_("suffix or operands invalid for `%s'"),
2759 current_templates->start->name);
2760 return 0;
2761 }
252b5132 2762
29b0f896
AM		 2763 if (!quiet_warnings)
2764 {
2765 if (!intel_syntax
2766 && ((i.types[0] & JumpAbsolute)
539e75ad 2767 != (operand_types[0] & JumpAbsolute)))
29b0f896
AM		 2768 {
2769 as_warn (_("indirect %s without `*'"), t->name);
2770 }
2771
2772 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2773 == (IsPrefix | IgnoreSize))
2774 {
2775 /* Warn them that a data or address size prefix doesn't
2776 affect assembly of the next line of code. */
2777 as_warn (_("stand-alone `%s' prefix"), t->name);
2778 }
2779 }
2780
2781 /* Copy the template we found. */
2782 i.tm = *t;
539e75ad
L		 2783
2784 if (addr_prefix_disp != -1)
2785 i.tm.operand_types[addr_prefix_disp]
2786 = operand_types[addr_prefix_disp];
2787
29b0f896
AM		 2788 if (found_reverse_match)
2789 {
2790 /* If we found a reverse match we must alter the opcode
2791 direction bit. found_reverse_match holds bits to change
2792 (different for int & float insns). */
2793
2794 i.tm.base_opcode ^= found_reverse_match;
2795
539e75ad
L		 2796 i.tm.operand_types[0] = operand_types[1];
2797 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 2798 }
2799
2800 return 1;
2801}
2802
2803static int
e3bb37b5 2804check_string (void)
29b0f896
AM		 2805{
2806 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2807 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2808 {
2809 if (i.seg[0] != NULL && i.seg[0] != &es)
2810 {
2811 as_bad (_("`%s' operand %d must use `%%es' segment"),
2812 i.tm.name,
2813 mem_op + 1);
2814 return 0;
2815 }
2816 /* There's only ever one segment override allowed per instruction.
2817 This instruction possibly has a legal segment override on the
2818 second operand, so copy the segment to where non-string
2819 instructions store it, allowing common code. */
2820 i.seg[0] = i.seg[1];
2821 }
2822 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2823 {
2824 if (i.seg[1] != NULL && i.seg[1] != &es)
2825 {
2826 as_bad (_("`%s' operand %d must use `%%es' segment"),
2827 i.tm.name,
2828 mem_op + 2);
2829 return 0;
2830 }
2831 }
2832 return 1;
2833}
2834
2835static int
543613e9 2836process_suffix (void)
29b0f896
AM		 2837{
2838 /* If matched instruction specifies an explicit instruction mnemonic
2839 suffix, use it. */
2840 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2841 {
2842 if (i.tm.opcode_modifier & Size16)
2843 i.suffix = WORD_MNEM_SUFFIX;
2844 else if (i.tm.opcode_modifier & Size64)
2845 i.suffix = QWORD_MNEM_SUFFIX;
2846 else
2847 i.suffix = LONG_MNEM_SUFFIX;
2848 }
2849 else if (i.reg_operands)
2850 {
2851 /* If there's no instruction mnemonic suffix we try to invent one
2852 based on register operands. */
2853 if (!i.suffix)
2854 {
2855 /* We take i.suffix from the last register operand specified,
2856 Destination register type is more significant than source
381d071f
L		 2857 register type. crc32 in SSE4.2 prefers source register
2858 type. */
2859 if (i.tm.base_opcode == 0xf20f38f1)
2860 {
2861 if ((i.types[0] & Reg))
2862 i.suffix = ((i.types[0] & Reg16) ? WORD_MNEM_SUFFIX :
29b0f896 2863 LONG_MNEM_SUFFIX);
381d071f 2864 }
9344ff29 2865 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94
L		 2866 {
2867 if ((i.types[0] & Reg8))
2868 i.suffix = BYTE_MNEM_SUFFIX;
2869 }
381d071f
L		 2870
2871 if (!i.suffix)
2872 {
2873 int op;
2874
20592a94
L		 2875 if (i.tm.base_opcode == 0xf20f38f1
2876 || i.tm.base_opcode == 0xf20f38f0)
2877 {
2878 /* We have to know the operand size for crc32. */
2879 as_bad (_("ambiguous memory operand size for `%s`"),
2880 i.tm.name);
2881 return 0;
2882 }
2883
381d071f
L		 2884 for (op = i.operands; --op >= 0;)
2885 if ((i.types[op] & Reg)
2886 && !(i.tm.operand_types[op] & InOutPortReg))
2887 {
2888 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2889 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2890 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2891 LONG_MNEM_SUFFIX);
2892 break;
2893 }
2894 }
29b0f896
AM		 2895 }
2896 else if (i.suffix == BYTE_MNEM_SUFFIX)
2897 {
2898 if (!check_byte_reg ())
2899 return 0;
2900 }
2901 else if (i.suffix == LONG_MNEM_SUFFIX)
2902 {
2903 if (!check_long_reg ())
2904 return 0;
2905 }
2906 else if (i.suffix == QWORD_MNEM_SUFFIX)
2907 {
2908 if (!check_qword_reg ())
2909 return 0;
2910 }
2911 else if (i.suffix == WORD_MNEM_SUFFIX)
2912 {
2913 if (!check_word_reg ())
2914 return 0;
2915 }
2916 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2917 /* Do nothing if the instruction is going to ignore the prefix. */
2918 ;
2919 else
2920 abort ();
2921 }
9306ca4a
JB		 2922 else if ((i.tm.opcode_modifier & DefaultSize)
2923 && !i.suffix
2924 /* exclude fldenv/frstor/fsave/fstenv */
2925 && (i.tm.opcode_modifier & No_sSuf))
29b0f896
AM		 2926 {
2927 i.suffix = stackop_size;
2928 }
9306ca4a
JB		 2929 else if (intel_syntax
2930 && !i.suffix
2931 && ((i.tm.operand_types[0] & JumpAbsolute)
64e74474
AM		 2932 || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
2933 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
2934 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 2935 {
2936 switch (flag_code)
2937 {
2938 case CODE_64BIT:
2939 if (!(i.tm.opcode_modifier & No_qSuf))
2940 {
2941 i.suffix = QWORD_MNEM_SUFFIX;
2942 break;
2943 }
2944 case CODE_32BIT:
2945 if (!(i.tm.opcode_modifier & No_lSuf))
2946 i.suffix = LONG_MNEM_SUFFIX;
2947 break;
2948 case CODE_16BIT:
2949 if (!(i.tm.opcode_modifier & No_wSuf))
2950 i.suffix = WORD_MNEM_SUFFIX;
2951 break;
2952 }
2953 }
252b5132 2954
9306ca4a 2955 if (!i.suffix)
29b0f896 2956 {
9306ca4a
JB		 2957 if (!intel_syntax)
2958 {
2959 if (i.tm.opcode_modifier & W)
2960 {
4eed87de
AM		 2961 as_bad (_("no instruction mnemonic suffix given and "
2962 "no register operands; can't size instruction"));
9306ca4a
JB		 2963 return 0;
2964 }
2965 }
2966 else
2967 {
64e74474
AM		 2968 unsigned int suffixes = (~i.tm.opcode_modifier
2969 & (No_bSuf
2970 | No_wSuf
2971 | No_lSuf
2972 | No_sSuf
2973 | No_xSuf
2974 | No_qSuf));
9306ca4a
JB		 2975
2976 if ((i.tm.opcode_modifier & W)
2977 || ((suffixes & (suffixes - 1))
2978 && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize))))
2979 {
2980 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2981 return 0;
2982 }
2983 }
29b0f896 2984 }
252b5132 2985
9306ca4a
JB		 2986 /* Change the opcode based on the operand size given by i.suffix;
2987 We don't need to change things for byte insns. */
2988
29b0f896
AM		 2989 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2990 {
2991 /* It's not a byte, select word/dword operation. */
2992 if (i.tm.opcode_modifier & W)
2993 {
2994 if (i.tm.opcode_modifier & ShortForm)
2995 i.tm.base_opcode |= 8;
2996 else
2997 i.tm.base_opcode |= 1;
2998 }
0f3f3d8b 2999
29b0f896
AM		 3000 /* Now select between word & dword operations via the operand
3001 size prefix, except for instructions that will ignore this
3002 prefix anyway. */
cb712a9e
L		 3003 if (i.tm.base_opcode == 0x0f01 && i.tm.extension_opcode == 0xc8)
3004 {
3005 /* monitor in SSE3 is a very special case. The default size
3006 of AX is the size of mode. The address size override
3007 prefix will change the size of AX. */
3008 if (i.op->regs[0].reg_type &
3009 (flag_code == CODE_32BIT ? Reg16 : Reg32))
3010 if (!add_prefix (ADDR_PREFIX_OPCODE))
3011 return 0;
3012 }
3013 else if (i.suffix != QWORD_MNEM_SUFFIX
3014 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
3015 && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF))
3016 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
3017 || (flag_code == CODE_64BIT
3018 && (i.tm.opcode_modifier & JumpByte))))
24eab124
AM		 3019 {
3020 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 3021
29b0f896
AM		 3022 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
3023 prefix = ADDR_PREFIX_OPCODE;
252b5132 3024
29b0f896
AM		 3025 if (!add_prefix (prefix))
3026 return 0;
24eab124 3027 }
252b5132 3028
29b0f896
AM		 3029 /* Set mode64 for an operand. */
3030 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 3031 && flag_code == CODE_64BIT
29b0f896 3032 && (i.tm.opcode_modifier & NoRex64) == 0)
46e883c5
L		 3033 {
3034 /* Special case for xchg %rax,%rax. It is NOP and doesn't
3035 need rex64. */
3036 if (i.operands != 2
3037 || i.types [0] != (Acc | Reg64)
3038 || i.types [1] != (Acc | Reg64)
13a1e313 3039 || i.tm.base_opcode != 0x90)
f6bee062 3040 i.rex |= REX_W;
46e883c5 3041 }
3e73aa7c 3042
29b0f896
AM		 3043 /* Size floating point instruction. */
3044 if (i.suffix == LONG_MNEM_SUFFIX)
543613e9
NC		 3045 if (i.tm.opcode_modifier & FloatMF)
3046 i.tm.base_opcode ^= 4;
29b0f896 3047 }
7ecd2f8b 3048
29b0f896
AM		 3049 return 1;
3050}
3e73aa7c 3051
29b0f896 3052static int
543613e9 3053check_byte_reg (void)
29b0f896
AM		 3054{
3055 int op;
543613e9 3056
29b0f896
AM		 3057 for (op = i.operands; --op >= 0;)
3058 {
3059 /* If this is an eight bit register, it's OK. If it's the 16 or
3060 32 bit version of an eight bit register, we will just use the
3061 low portion, and that's OK too. */
3062 if (i.types[op] & Reg8)
3063 continue;
3064
3065 /* movzx and movsx should not generate this warning. */
3066 if (intel_syntax
3067 && (i.tm.base_opcode == 0xfb7
3068 || i.tm.base_opcode == 0xfb6
3069 || i.tm.base_opcode == 0x63
3070 || i.tm.base_opcode == 0xfbe
3071 || i.tm.base_opcode == 0xfbf))
3072 continue;
3073
9344ff29
L		 3074 /* crc32 doesn't generate this warning. */
3075 if (i.tm.base_opcode == 0xf20f38f0)
3076 continue;
3077
65ec77d2 3078 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
29b0f896
AM		 3079 {
3080 /* Prohibit these changes in the 64bit mode, since the
3081 lowering is more complicated. */
3082 if (flag_code == CODE_64BIT
3083 && (i.tm.operand_types[op] & InOutPortReg) == 0)
3084 {
2ca3ace5
L		 3085 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3086 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3087 i.suffix);
3088 return 0;
3089 }
3090#if REGISTER_WARNINGS
3091 if (!quiet_warnings
3092 && (i.tm.operand_types[op] & InOutPortReg) == 0)
a540244d
L		 3093 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3094 register_prefix,
29b0f896
AM		 3095 (i.op[op].regs + (i.types[op] & Reg16
3096 ? REGNAM_AL - REGNAM_AX
3097 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 3098 register_prefix,
29b0f896
AM		 3099 i.op[op].regs->reg_name,
3100 i.suffix);
3101#endif
3102 continue;
3103 }
3104 /* Any other register is bad. */
3105 if (i.types[op] & (Reg | RegMMX | RegXMM
3106 | SReg2 | SReg3
3107 | Control | Debug | Test
3108 | FloatReg | FloatAcc))
3109 {
a540244d
L		 3110 as_bad (_("`%s%s' not allowed with `%s%c'"),
3111 register_prefix,
29b0f896
AM		 3112 i.op[op].regs->reg_name,
3113 i.tm.name,
3114 i.suffix);
3115 return 0;
3116 }
3117 }
3118 return 1;
3119}
3120
3121static int
e3bb37b5 3122check_long_reg (void)
29b0f896
AM		 3123{
3124 int op;
3125
3126 for (op = i.operands; --op >= 0;)
3127 /* Reject eight bit registers, except where the template requires
3128 them. (eg. movzb) */
3129 if ((i.types[op] & Reg8) != 0
3130 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3131 {
a540244d
L		 3132 as_bad (_("`%s%s' not allowed with `%s%c'"),
3133 register_prefix,
29b0f896
AM		 3134 i.op[op].regs->reg_name,
3135 i.tm.name,
3136 i.suffix);
3137 return 0;
3138 }
3139 /* Warn if the e prefix on a general reg is missing. */
3140 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3141 && (i.types[op] & Reg16) != 0
3142 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3143 {
3144 /* Prohibit these changes in the 64bit mode, since the
3145 lowering is more complicated. */
3146 if (flag_code == CODE_64BIT)
252b5132 3147 {
2ca3ace5
L		 3148 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3149 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3150 i.suffix);
3151 return 0;
252b5132 3152 }
29b0f896
AM		 3153#if REGISTER_WARNINGS
3154 else
a540244d
L		 3155 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3156 register_prefix,
29b0f896 3157 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 3158 register_prefix,
29b0f896
AM		 3159 i.op[op].regs->reg_name,
3160 i.suffix);
3161#endif
252b5132 3162 }
29b0f896
AM		 3163 /* Warn if the r prefix on a general reg is missing. */
3164 else if ((i.types[op] & Reg64) != 0
3165 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
252b5132 3166 {
2ca3ace5
L		 3167 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3168 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3169 i.suffix);
3170 return 0;
3171 }
3172 return 1;
3173}
252b5132 3174
29b0f896 3175static int
e3bb37b5 3176check_qword_reg (void)
29b0f896
AM		 3177{
3178 int op;
252b5132 3179
29b0f896
AM		 3180 for (op = i.operands; --op >= 0; )
3181 /* Reject eight bit registers, except where the template requires
3182 them. (eg. movzb) */
3183 if ((i.types[op] & Reg8) != 0
3184 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3185 {
a540244d
L		 3186 as_bad (_("`%s%s' not allowed with `%s%c'"),
3187 register_prefix,
29b0f896
AM		 3188 i.op[op].regs->reg_name,
3189 i.tm.name,
3190 i.suffix);
3191 return 0;
3192 }
3193 /* Warn if the e prefix on a general reg is missing. */
3194 else if (((i.types[op] & Reg16) != 0
3195 || (i.types[op] & Reg32) != 0)
3196 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3197 {
3198 /* Prohibit these changes in the 64bit mode, since the
3199 lowering is more complicated. */
2ca3ace5
L		 3200 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3201 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3202 i.suffix);
3203 return 0;
252b5132 3204 }
29b0f896
AM		 3205 return 1;
3206}
252b5132 3207
29b0f896 3208static int
e3bb37b5 3209check_word_reg (void)
29b0f896
AM		 3210{
3211 int op;
3212 for (op = i.operands; --op >= 0;)
3213 /* Reject eight bit registers, except where the template requires
3214 them. (eg. movzb) */
3215 if ((i.types[op] & Reg8) != 0
3216 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3217 {
a540244d
L		 3218 as_bad (_("`%s%s' not allowed with `%s%c'"),
3219 register_prefix,
29b0f896
AM		 3220 i.op[op].regs->reg_name,
3221 i.tm.name,
3222 i.suffix);
3223 return 0;
3224 }
3225 /* Warn if the e prefix on a general reg is present. */
3226 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3227 && (i.types[op] & Reg32) != 0
3228 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
252b5132 3229 {
29b0f896
AM		 3230 /* Prohibit these changes in the 64bit mode, since the
3231 lowering is more complicated. */
3232 if (flag_code == CODE_64BIT)
252b5132 3233 {
2ca3ace5
L		 3234 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3235 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3236 i.suffix);
3237 return 0;
252b5132 3238 }
29b0f896
AM		 3239 else
3240#if REGISTER_WARNINGS
a540244d
L		 3241 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3242 register_prefix,
29b0f896 3243 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 3244 register_prefix,
29b0f896
AM		 3245 i.op[op].regs->reg_name,
3246 i.suffix);
3247#endif
3248 }
3249 return 1;
3250}
252b5132 3251
29b0f896 3252static int
e3bb37b5 3253finalize_imm (void)
29b0f896
AM		 3254{
3255 unsigned int overlap0, overlap1, overlap2;
3256
3257 overlap0 = i.types[0] & i.tm.operand_types[0];
20f0a1fc 3258 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64))
29b0f896
AM		 3259 && overlap0 != Imm8 && overlap0 != Imm8S
3260 && overlap0 != Imm16 && overlap0 != Imm32S
3261 && overlap0 != Imm32 && overlap0 != Imm64)
3262 {
3263 if (i.suffix)
3264 {
3265 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
3266 ? Imm8 | Imm8S
3267 : (i.suffix == WORD_MNEM_SUFFIX
3268 ? Imm16
3269 : (i.suffix == QWORD_MNEM_SUFFIX
3270 ? Imm64 | Imm32S
3271 : Imm32)));
3272 }
3273 else if (overlap0 == (Imm16 | Imm32S | Imm32)
3274 || overlap0 == (Imm16 | Imm32)
3275 || overlap0 == (Imm16 | Imm32S))
3276 {
3277 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3278 ? Imm16 : Imm32S);
3279 }
3280 if (overlap0 != Imm8 && overlap0 != Imm8S
3281 && overlap0 != Imm16 && overlap0 != Imm32S
3282 && overlap0 != Imm32 && overlap0 != Imm64)
3283 {
4eed87de
AM		 3284 as_bad (_("no instruction mnemonic suffix given; "
3285 "can't determine immediate size"));
29b0f896
AM		 3286 return 0;
3287 }
3288 }
3289 i.types[0] = overlap0;
3290
3291 overlap1 = i.types[1] & i.tm.operand_types[1];
37edbb65 3292 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64))
29b0f896
AM		 3293 && overlap1 != Imm8 && overlap1 != Imm8S
3294 && overlap1 != Imm16 && overlap1 != Imm32S
3295 && overlap1 != Imm32 && overlap1 != Imm64)
3296 {
3297 if (i.suffix)
3298 {
3299 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
3300 ? Imm8 | Imm8S
3301 : (i.suffix == WORD_MNEM_SUFFIX
3302 ? Imm16
3303 : (i.suffix == QWORD_MNEM_SUFFIX
3304 ? Imm64 | Imm32S
3305 : Imm32)));
3306 }
3307 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
3308 || overlap1 == (Imm16 | Imm32)
3309 || overlap1 == (Imm16 | Imm32S))
3310 {
3311 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3312 ? Imm16 : Imm32S);
3313 }
3314 if (overlap1 != Imm8 && overlap1 != Imm8S
3315 && overlap1 != Imm16 && overlap1 != Imm32S
3316 && overlap1 != Imm32 && overlap1 != Imm64)
3317 {
4eed87de
AM		 3318 as_bad (_("no instruction mnemonic suffix given; "
3319 "can't determine immediate size %x %c"),
3320 overlap1, i.suffix);
29b0f896
AM		 3321 return 0;
3322 }
3323 }
3324 i.types[1] = overlap1;
3325
3326 overlap2 = i.types[2] & i.tm.operand_types[2];
3327 assert ((overlap2 & Imm) == 0);
3328 i.types[2] = overlap2;
3329
3330 return 1;
3331}
3332
3333static int
e3bb37b5 3334process_operands (void)
29b0f896
AM		 3335{
3336 /* Default segment register this instruction will use for memory
3337 accesses. 0 means unknown. This is only for optimizing out
3338 unnecessary segment overrides. */
3339 const seg_entry *default_seg = 0;
3340
3341 /* The imul $imm, %reg instruction is converted into
3342 imul $imm, %reg, %reg, and the clr %reg instruction
3343 is converted into xor %reg, %reg. */
5f15756d 3344 if (i.tm.opcode_modifier & RegKludge)
29b0f896 3345 {
42903f7f
L		 3346 if ((i.tm.cpu_flags & CpuSSE4_1))
3347 {
3348 /* The first operand in instruction blendvpd, blendvps and
3349 pblendvb in SSE4.1 is implicit and must be xmm0. */
3350 assert (i.operands == 3
3351 && i.reg_operands >= 2
3352 && i.types[0] == RegXMM);
3353 if (i.op[0].regs->reg_num != 0)
3354 {
3355 if (intel_syntax)
3356 as_bad (_("the last operand of `%s' must be `%sxmm0'"),
3357 i.tm.name, register_prefix);
3358 else
3359 as_bad (_("the first operand of `%s' must be `%sxmm0'"),
3360 i.tm.name, register_prefix);
3361 return 0;
3362 }
3363 i.op[0] = i.op[1];
3364 i.op[1] = i.op[2];
3365 i.types[0] = i.types[1];
3366 i.types[1] = i.types[2];
3367 i.operands--;
3368 i.reg_operands--;
3369
3370 /* We need to adjust fields in i.tm since they are used by
3371 build_modrm_byte. */
3372 i.tm.operand_types [0] = i.tm.operand_types [1];
3373 i.tm.operand_types [1] = i.tm.operand_types [2];
3374 i.tm.operands--;
3375 }
3376 else
3377 {
3378 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
3379 /* Pretend we saw the extra register operand. */
3380 assert (i.reg_operands == 1
3381 && i.op[first_reg_op + 1].regs == 0);
3382 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
3383 i.types[first_reg_op + 1] = i.types[first_reg_op];
3384 i.operands++;
3385 i.reg_operands++;
3386 }
29b0f896
AM		 3387 }
3388
3389 if (i.tm.opcode_modifier & ShortForm)
3390 {
4eed87de 3391 if (i.types[0] & (SReg2 | SReg3))
29b0f896 3392 {
4eed87de
AM		 3393 if (i.tm.base_opcode == POP_SEG_SHORT
3394 && i.op[0].regs->reg_num == 1)
29b0f896 3395 {
4eed87de
AM		 3396 as_bad (_("you can't `pop %%cs'"));
3397 return 0;
29b0f896 3398 }
4eed87de
AM		 3399 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
3400 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 3401 i.rex |= REX_B;
4eed87de
AM		 3402 }
3403 else
3404 {
3405 /* The register or float register operand is in operand 0 or 1. */
3406 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
3407 /* Register goes in low 3 bits of opcode. */
3408 i.tm.base_opcode |= i.op[op].regs->reg_num;
3409 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 3410 i.rex |= REX_B;
4eed87de 3411 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
29b0f896 3412 {
4eed87de
AM		 3413 /* Warn about some common errors, but press on regardless.
3414 The first case can be generated by gcc (<= 2.8.1). */
3415 if (i.operands == 2)
3416 {
3417 /* Reversed arguments on faddp, fsubp, etc. */
a540244d
L		 3418 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
3419 register_prefix, i.op[1].regs->reg_name,
3420 register_prefix, i.op[0].regs->reg_name);
4eed87de
AM		 3421 }
3422 else
3423 {
3424 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 3425 as_warn (_("translating to `%s %s%s'"), i.tm.name,
3426 register_prefix, i.op[0].regs->reg_name);
4eed87de 3427 }
29b0f896
AM		 3428 }
3429 }
3430 }
3431 else if (i.tm.opcode_modifier & Modrm)
3432 {
3433 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 3434 must be put into the modrm byte). Now, we make the modrm and
3435 index base bytes based on all the info we've collected. */
29b0f896
AM		 3436
3437 default_seg = build_modrm_byte ();
3438 }
8a2ed489 3439 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 3440 {
3441 default_seg = &ds;
3442 }
3443 else if ((i.tm.opcode_modifier & IsString) != 0)
3444 {
3445 /* For the string instructions that allow a segment override
3446 on one of their operands, the default segment is ds. */
3447 default_seg = &ds;
3448 }
3449
30123838
JB		 3450 if ((i.tm.base_opcode == 0x8d /* lea */
3451 || (i.tm.cpu_flags & CpuSVME))
3452 && i.seg[0] && !quiet_warnings)
3453 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 3454
3455 /* If a segment was explicitly specified, and the specified segment
3456 is not the default, use an opcode prefix to select it. If we
3457 never figured out what the default segment is, then default_seg
3458 will be zero at this point, and the specified segment prefix will
3459 always be used. */
29b0f896
AM		 3460 if ((i.seg[0]) && (i.seg[0] != default_seg))
3461 {
3462 if (!add_prefix (i.seg[0]->seg_prefix))
3463 return 0;
3464 }
3465 return 1;
3466}
3467
3468static const seg_entry *
e3bb37b5 3469build_modrm_byte (void)
29b0f896
AM		 3470{
3471 const seg_entry *default_seg = 0;
3472
3473 /* i.reg_operands MUST be the number of real register operands;
3474 implicit registers do not count. */
3475 if (i.reg_operands == 2)
3476 {
3477 unsigned int source, dest;
cab737b9
L		 3478
3479 switch (i.operands)
3480 {
3481 case 2:
3482 source = 0;
3483 break;
3484 case 3:
c81128dc
L		 3485 /* When there are 3 operands, one of them may be immediate,
3486 which may be the first or the last operand. Otherwise,
3487 the first operand must be shift count register (cl). */
3488 assert (i.imm_operands == 1
3489 || (i.imm_operands == 0
3490 && (i.types[0] & ShiftCount)));
3491 source = (i.types[0] & (Imm | ShiftCount)) ? 1 : 0;
cab737b9
L		 3492 break;
3493 case 4:
3494 /* When there are 4 operands, the first two must be immediate
3495 operands. The source operand will be the 3rd one. */
3496 assert (i.imm_operands == 2
3497 && (i.types[0] & Imm)
3498 && (i.types[1] & Imm));
3499 source = 2;
3500 break;
3501 default:
3502 abort ();
3503 }
3504
29b0f896
AM		 3505 dest = source + 1;
3506
3507 i.rm.mode = 3;
3508 /* One of the register operands will be encoded in the i.tm.reg
3509 field, the other in the combined i.tm.mode and i.tm.regmem
3510 fields. If no form of this instruction supports a memory
3511 destination operand, then we assume the source operand may
3512 sometimes be a memory operand and so we need to store the
3513 destination in the i.rm.reg field. */
e72cf3ec 3514 if ((i.tm.operand_types[dest] & (AnyMem | RegMem)) == 0)
29b0f896
AM		 3515 {
3516 i.rm.reg = i.op[dest].regs->reg_num;
3517 i.rm.regmem = i.op[source].regs->reg_num;
3518 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 3519 i.rex |= REX_R;
29b0f896 3520 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 3521 i.rex |= REX_B;
29b0f896
AM		 3522 }
3523 else
3524 {
3525 i.rm.reg = i.op[source].regs->reg_num;
3526 i.rm.regmem = i.op[dest].regs->reg_num;
3527 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 3528 i.rex |= REX_B;
29b0f896 3529 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 3530 i.rex |= REX_R;
29b0f896 3531 }
161a04f6 3532 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5
JB		 3533 {
3534 if (!((i.types[0] | i.types[1]) & Control))
3535 abort ();
161a04f6 3536 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 3537 add_prefix (LOCK_PREFIX_OPCODE);
3538 }
29b0f896
AM		 3539 }
3540 else
3541 { /* If it's not 2 reg operands... */
3542 if (i.mem_operands)
3543 {
3544 unsigned int fake_zero_displacement = 0;
99018f42 3545 unsigned int op;
4eed87de 3546
99018f42
L		 3547 for (op = 0; op < i.operands; op++)
3548 if ((i.types[op] & AnyMem))
3549 break;
3550 assert (op < i.operands);
29b0f896
AM		 3551
3552 default_seg = &ds;
3553
3554 if (i.base_reg == 0)
3555 {
3556 i.rm.mode = 0;
3557 if (!i.disp_operands)
3558 fake_zero_displacement = 1;
3559 if (i.index_reg == 0)
3560 {
3561 /* Operand is just <disp> */
20f0a1fc 3562 if (flag_code == CODE_64BIT)
29b0f896
AM		 3563 {
3564 /* 64bit mode overwrites the 32bit absolute
3565 addressing by RIP relative addressing and
3566 absolute addressing is encoded by one of the
3567 redundant SIB forms. */
3568 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3569 i.sib.base = NO_BASE_REGISTER;
3570 i.sib.index = NO_INDEX_REGISTER;
fc225355
L		 3571 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
3572 ? Disp32S : Disp32);
20f0a1fc 3573 }
fc225355
L		 3574 else if ((flag_code == CODE_16BIT)
3575 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 3576 {
3577 i.rm.regmem = NO_BASE_REGISTER_16;
3578 i.types[op] = Disp16;
3579 }
3580 else
3581 {
3582 i.rm.regmem = NO_BASE_REGISTER;
3583 i.types[op] = Disp32;
29b0f896
AM		 3584 }
3585 }
3586 else /* !i.base_reg && i.index_reg */
3587 {
3588 i.sib.index = i.index_reg->reg_num;
3589 i.sib.base = NO_BASE_REGISTER;
3590 i.sib.scale = i.log2_scale_factor;
3591 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3592 i.types[op] &= ~Disp;
3593 if (flag_code != CODE_64BIT)
3594 i.types[op] |= Disp32; /* Must be 32 bit */
3595 else
3596 i.types[op] |= Disp32S;
3597 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 3598 i.rex |= REX_X;
29b0f896
AM		 3599 }
3600 }
3601 /* RIP addressing for 64bit mode. */
3602 else if (i.base_reg->reg_type == BaseIndex)
3603 {
3604 i.rm.regmem = NO_BASE_REGISTER;
20f0a1fc 3605 i.types[op] &= ~ Disp;
29b0f896 3606 i.types[op] |= Disp32S;
71903a11 3607 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 3608 if (! i.disp_operands)
3609 fake_zero_displacement = 1;
29b0f896
AM		 3610 }
3611 else if (i.base_reg->reg_type & Reg16)
3612 {
3613 switch (i.base_reg->reg_num)
3614 {
3615 case 3: /* (%bx) */
3616 if (i.index_reg == 0)
3617 i.rm.regmem = 7;
3618 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3619 i.rm.regmem = i.index_reg->reg_num - 6;
3620 break;
3621 case 5: /* (%bp) */
3622 default_seg = &ss;
3623 if (i.index_reg == 0)
3624 {
3625 i.rm.regmem = 6;
3626 if ((i.types[op] & Disp) == 0)
3627 {
3628 /* fake (%bp) into 0(%bp) */
3629 i.types[op] |= Disp8;
252b5132 3630 fake_zero_displacement = 1;
29b0f896
AM		 3631 }
3632 }
3633 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3634 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
3635 break;
3636 default: /* (%si) -> 4 or (%di) -> 5 */
3637 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
3638 }
3639 i.rm.mode = mode_from_disp_size (i.types[op]);
3640 }
3641 else /* i.base_reg and 32/64 bit mode */
3642 {
3643 if (flag_code == CODE_64BIT
3644 && (i.types[op] & Disp))
fc225355
L		 3645 i.types[op] = ((i.types[op] & Disp8)
3646 | (i.prefix[ADDR_PREFIX] == 0
3647 ? Disp32S : Disp32));
20f0a1fc 3648
29b0f896
AM		 3649 i.rm.regmem = i.base_reg->reg_num;
3650 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 3651 i.rex |= REX_B;
29b0f896
AM		 3652 i.sib.base = i.base_reg->reg_num;
3653 /* x86-64 ignores REX prefix bit here to avoid decoder
3654 complications. */
3655 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
3656 {
3657 default_seg = &ss;
3658 if (i.disp_operands == 0)
3659 {
3660 fake_zero_displacement = 1;
3661 i.types[op] |= Disp8;
3662 }
3663 }
3664 else if (i.base_reg->reg_num == ESP_REG_NUM)
3665 {
3666 default_seg = &ss;
3667 }
3668 i.sib.scale = i.log2_scale_factor;
3669 if (i.index_reg == 0)
3670 {
3671 /* <disp>(%esp) becomes two byte modrm with no index
3672 register. We've already stored the code for esp
3673 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3674 Any base register besides %esp will not use the
3675 extra modrm byte. */
3676 i.sib.index = NO_INDEX_REGISTER;
3677#if !SCALE1_WHEN_NO_INDEX
3678 /* Another case where we force the second modrm byte. */
3679 if (i.log2_scale_factor)
3680 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
252b5132 3681#endif
29b0f896
AM		 3682 }
3683 else
3684 {
3685 i.sib.index = i.index_reg->reg_num;
3686 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3687 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 3688 i.rex |= REX_X;
29b0f896 3689 }
67a4f2b7
AO		 3690
3691 if (i.disp_operands
3692 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3693 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
3694 i.rm.mode = 0;
3695 else
3696 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 3697 }
252b5132 3698
29b0f896
AM		 3699 if (fake_zero_displacement)
3700 {
3701 /* Fakes a zero displacement assuming that i.types[op]
3702 holds the correct displacement size. */
3703 expressionS *exp;
3704
3705 assert (i.op[op].disps == 0);
3706 exp = &disp_expressions[i.disp_operands++];
3707 i.op[op].disps = exp;
3708 exp->X_op = O_constant;
3709 exp->X_add_number = 0;
3710 exp->X_add_symbol = (symbolS *) 0;
3711 exp->X_op_symbol = (symbolS *) 0;
3712 }
3713 }
252b5132 3714
29b0f896
AM		 3715 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3716 (if any) based on i.tm.extension_opcode. Again, we must be
3717 careful to make sure that segment/control/debug/test/MMX
3718 registers are coded into the i.rm.reg field. */
3719 if (i.reg_operands)
3720 {
99018f42
L		 3721 unsigned int op;
3722
3723 for (op = 0; op < i.operands; op++)
3724 if ((i.types[op] & (Reg | RegMMX | RegXMM
3725 | SReg2 | SReg3
3726 | Control | Debug | Test)))
3727 break;
3728 assert (op < i.operands);
3729
29b0f896
AM		 3730 /* If there is an extension opcode to put here, the register
3731 number must be put into the regmem field. */
3732 if (i.tm.extension_opcode != None)
3733 {
3734 i.rm.regmem = i.op[op].regs->reg_num;
3735 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 3736 i.rex |= REX_B;
29b0f896
AM		 3737 }
3738 else
3739 {
3740 i.rm.reg = i.op[op].regs->reg_num;
3741 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 3742 i.rex |= REX_R;
29b0f896 3743 }
252b5132 3744
29b0f896
AM		 3745 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3746 must set it to 3 to indicate this is a register operand
3747 in the regmem field. */
3748 if (!i.mem_operands)
3749 i.rm.mode = 3;
3750 }
252b5132 3751
29b0f896
AM		 3752 /* Fill in i.rm.reg field with extension opcode (if any). */
3753 if (i.tm.extension_opcode != None)
3754 i.rm.reg = i.tm.extension_opcode;
3755 }
3756 return default_seg;
3757}
252b5132 3758
29b0f896 3759static void
e3bb37b5 3760output_branch (void)
29b0f896
AM		 3761{
3762 char *p;
3763 int code16;
3764 int prefix;
3765 relax_substateT subtype;
3766 symbolS *sym;
3767 offsetT off;
3768
3769 code16 = 0;
3770 if (flag_code == CODE_16BIT)
3771 code16 = CODE16;
3772
3773 prefix = 0;
3774 if (i.prefix[DATA_PREFIX] != 0)
252b5132 3775 {
29b0f896
AM		 3776 prefix = 1;
3777 i.prefixes -= 1;
3778 code16 ^= CODE16;
252b5132 3779 }
29b0f896
AM		 3780 /* Pentium4 branch hints. */
3781 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3782 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 3783 {
29b0f896
AM		 3784 prefix++;
3785 i.prefixes--;
3786 }
3787 if (i.prefix[REX_PREFIX] != 0)
3788 {
3789 prefix++;
3790 i.prefixes--;
2f66722d
AM		 3791 }
3792
29b0f896
AM		 3793 if (i.prefixes != 0 && !intel_syntax)
3794 as_warn (_("skipping prefixes on this instruction"));
3795
3796 /* It's always a symbol; End frag & setup for relax.
3797 Make sure there is enough room in this frag for the largest
3798 instruction we may generate in md_convert_frag. This is 2
3799 bytes for the opcode and room for the prefix and largest
3800 displacement. */
3801 frag_grow (prefix + 2 + 4);
3802 /* Prefix and 1 opcode byte go in fr_fix. */
3803 p = frag_more (prefix + 1);
3804 if (i.prefix[DATA_PREFIX] != 0)
3805 *p++ = DATA_PREFIX_OPCODE;
3806 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
3807 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
3808 *p++ = i.prefix[SEG_PREFIX];
3809 if (i.prefix[REX_PREFIX] != 0)
3810 *p++ = i.prefix[REX_PREFIX];
3811 *p = i.tm.base_opcode;
3812
3813 if ((unsigned char) *p == JUMP_PC_RELATIVE)
3814 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
3815 else if ((cpu_arch_flags & Cpu386) != 0)
3816 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
3817 else
3818 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
3819 subtype |= code16;
3e73aa7c 3820
29b0f896
AM		 3821 sym = i.op[0].disps->X_add_symbol;
3822 off = i.op[0].disps->X_add_number;
3e73aa7c 3823
29b0f896
AM		 3824 if (i.op[0].disps->X_op != O_constant
3825 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 3826 {
29b0f896
AM		 3827 /* Handle complex expressions. */
3828 sym = make_expr_symbol (i.op[0].disps);
3829 off = 0;
3830 }
3e73aa7c 3831
29b0f896
AM		 3832 /* 1 possible extra opcode + 4 byte displacement go in var part.
3833 Pass reloc in fr_var. */
3834 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
3835}
3e73aa7c 3836
29b0f896 3837static void
e3bb37b5 3838output_jump (void)
29b0f896
AM		 3839{
3840 char *p;
3841 int size;
3e02c1cc 3842 fixS *fixP;
29b0f896
AM		 3843
3844 if (i.tm.opcode_modifier & JumpByte)
3845 {
3846 /* This is a loop or jecxz type instruction. */
3847 size = 1;
3848 if (i.prefix[ADDR_PREFIX] != 0)
3849 {
3850 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3851 i.prefixes -= 1;
3852 }
3853 /* Pentium4 branch hints. */
3854 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3855 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3856 {
3857 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3858 i.prefixes--;
3e73aa7c
JH		 3859 }
3860 }
29b0f896
AM		 3861 else
3862 {
3863 int code16;
3e73aa7c 3864
29b0f896
AM		 3865 code16 = 0;
3866 if (flag_code == CODE_16BIT)
3867 code16 = CODE16;
3e73aa7c 3868
29b0f896
AM		 3869 if (i.prefix[DATA_PREFIX] != 0)
3870 {
3871 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3872 i.prefixes -= 1;
3873 code16 ^= CODE16;
3874 }
252b5132 3875
29b0f896
AM		 3876 size = 4;
3877 if (code16)
3878 size = 2;
3879 }
9fcc94b6 3880
29b0f896
AM		 3881 if (i.prefix[REX_PREFIX] != 0)
3882 {
3883 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3884 i.prefixes -= 1;
3885 }
252b5132 3886
29b0f896
AM		 3887 if (i.prefixes != 0 && !intel_syntax)
3888 as_warn (_("skipping prefixes on this instruction"));
e0890092 3889
29b0f896
AM		 3890 p = frag_more (1 + size);
3891 *p++ = i.tm.base_opcode;
e0890092 3892
3e02c1cc
AM		 3893 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3894 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3895
3896 /* All jumps handled here are signed, but don't use a signed limit
3897 check for 32 and 16 bit jumps as we want to allow wrap around at
3898 4G and 64k respectively. */
3899 if (size == 1)
3900 fixP->fx_signed = 1;
29b0f896 3901}
e0890092 3902
29b0f896 3903static void
e3bb37b5 3904output_interseg_jump (void)
29b0f896
AM		 3905{
3906 char *p;
3907 int size;
3908 int prefix;
3909 int code16;
252b5132 3910
29b0f896
AM		 3911 code16 = 0;
3912 if (flag_code == CODE_16BIT)
3913 code16 = CODE16;
a217f122 3914
29b0f896
AM		 3915 prefix = 0;
3916 if (i.prefix[DATA_PREFIX] != 0)
3917 {
3918 prefix = 1;
3919 i.prefixes -= 1;
3920 code16 ^= CODE16;
3921 }
3922 if (i.prefix[REX_PREFIX] != 0)
3923 {
3924 prefix++;
3925 i.prefixes -= 1;
3926 }
252b5132 3927
29b0f896
AM		 3928 size = 4;
3929 if (code16)
3930 size = 2;
252b5132 3931
29b0f896
AM		 3932 if (i.prefixes != 0 && !intel_syntax)
3933 as_warn (_("skipping prefixes on this instruction"));
252b5132 3934
29b0f896
AM		 3935 /* 1 opcode; 2 segment; offset */
3936 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 3937
29b0f896
AM		 3938 if (i.prefix[DATA_PREFIX] != 0)
3939 *p++ = DATA_PREFIX_OPCODE;
252b5132 3940
29b0f896
AM		 3941 if (i.prefix[REX_PREFIX] != 0)
3942 *p++ = i.prefix[REX_PREFIX];
252b5132 3943
29b0f896
AM		 3944 *p++ = i.tm.base_opcode;
3945 if (i.op[1].imms->X_op == O_constant)
3946 {
3947 offsetT n = i.op[1].imms->X_add_number;
252b5132 3948
29b0f896
AM		 3949 if (size == 2
3950 && !fits_in_unsigned_word (n)
3951 && !fits_in_signed_word (n))
3952 {
3953 as_bad (_("16-bit jump out of range"));
3954 return;
3955 }
3956 md_number_to_chars (p, n, size);
3957 }
3958 else
3959 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3960 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3961 if (i.op[0].imms->X_op != O_constant)
3962 as_bad (_("can't handle non absolute segment in `%s'"),
3963 i.tm.name);
3964 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3965}
a217f122 3966
29b0f896 3967static void
e3bb37b5 3968output_insn (void)
29b0f896 3969{
2bbd9c25
JJ		 3970 fragS *insn_start_frag;
3971 offsetT insn_start_off;
3972
29b0f896
AM		 3973 /* Tie dwarf2 debug info to the address at the start of the insn.
3974 We can't do this after the insn has been output as the current
3975 frag may have been closed off. eg. by frag_var. */
3976 dwarf2_emit_insn (0);
3977
2bbd9c25
JJ		 3978 insn_start_frag = frag_now;
3979 insn_start_off = frag_now_fix ();
3980
29b0f896
AM		 3981 /* Output jumps. */
3982 if (i.tm.opcode_modifier & Jump)
3983 output_branch ();
3984 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3985 output_jump ();
3986 else if (i.tm.opcode_modifier & JumpInterSegment)
3987 output_interseg_jump ();
3988 else
3989 {
3990 /* Output normal instructions here. */
3991 char *p;
3992 unsigned char *q;
331d2d0d 3993 unsigned int prefix;
252b5132 3994
42903f7f 3995 /* All opcodes on i386 have either 1 or 2 bytes. SSSE3 and
381d071f
L		 3996 SSE4 instructions have 3 bytes. We may use one more higher
3997 byte to specify a prefix the instruction requires. Exclude
3998 instructions which are in both SSE4 and ABM. */
3999 if ((i.tm.cpu_flags & (CpuSSSE3 | CpuSSE4)) != 0
4000 && (i.tm.cpu_flags & CpuABM) == 0)
bc4bd9ab 4001 {
331d2d0d
L		 4002 if (i.tm.base_opcode & 0xff000000)
4003 {
4004 prefix = (i.tm.base_opcode >> 24) & 0xff;
4005 goto check_prefix;
4006 }
4007 }
4008 else if ((i.tm.base_opcode & 0xff0000) != 0)
4009 {
4010 prefix = (i.tm.base_opcode >> 16) & 0xff;
bc4bd9ab
MK		 4011 if ((i.tm.cpu_flags & CpuPadLock) != 0)
4012 {
64e74474 4013 check_prefix:
bc4bd9ab
MK		 4014 if (prefix != REPE_PREFIX_OPCODE
4015 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
4016 add_prefix (prefix);
4017 }
4018 else
331d2d0d 4019 add_prefix (prefix);
0f10071e 4020 }
252b5132 4021
29b0f896
AM		 4022 /* The prefix bytes. */
4023 for (q = i.prefix;
4024 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
4025 q++)
4026 {
4027 if (*q)
4028 {
4029 p = frag_more (1);
4030 md_number_to_chars (p, (valueT) *q, 1);
4031 }
4032 }
252b5132 4033
29b0f896
AM		 4034 /* Now the opcode; be careful about word order here! */
4035 if (fits_in_unsigned_byte (i.tm.base_opcode))
4036 {
4037 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
4038 }
4039 else
4040 {
381d071f
L		 4041 if ((i.tm.cpu_flags & (CpuSSSE3 | CpuSSE4)) != 0
4042 && (i.tm.cpu_flags & CpuABM) == 0)
331d2d0d
L		 4043 {
4044 p = frag_more (3);
4045 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4046 }
4047 else
4048 p = frag_more (2);
0f10071e 4049
29b0f896
AM		 4050 /* Put out high byte first: can't use md_number_to_chars! */
4051 *p++ = (i.tm.base_opcode >> 8) & 0xff;
4052 *p = i.tm.base_opcode & 0xff;
4053 }
3e73aa7c 4054
29b0f896
AM		 4055 /* Now the modrm byte and sib byte (if present). */
4056 if (i.tm.opcode_modifier & Modrm)
4057 {
4058 p = frag_more (1);
4059 md_number_to_chars (p,
4060 (valueT) (i.rm.regmem << 0
4061 | i.rm.reg << 3
4062 | i.rm.mode << 6),
4063 1);
4064 /* If i.rm.regmem == ESP (4)
4065 && i.rm.mode != (Register mode)
4066 && not 16 bit
4067 ==> need second modrm byte. */
4068 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
4069 && i.rm.mode != 3
4070 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
4071 {
4072 p = frag_more (1);
4073 md_number_to_chars (p,
4074 (valueT) (i.sib.base << 0
4075 | i.sib.index << 3
4076 | i.sib.scale << 6),
4077 1);
4078 }
4079 }
3e73aa7c 4080
29b0f896 4081 if (i.disp_operands)
2bbd9c25 4082 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 4083
29b0f896 4084 if (i.imm_operands)
2bbd9c25 4085 output_imm (insn_start_frag, insn_start_off);
29b0f896 4086 }
252b5132 4087
29b0f896
AM		 4088#ifdef DEBUG386
4089 if (flag_debug)
4090 {
7b81dfbb 4091 pi ("" /*line*/, &i);
29b0f896
AM		 4092 }
4093#endif /* DEBUG386 */
4094}
252b5132 4095
e205caa7
L		 4096/* Return the size of the displacement operand N. */
4097
4098static int
4099disp_size (unsigned int n)
4100{
4101 int size = 4;
4102 if (i.types[n] & (Disp8 | Disp16 | Disp64))
4103 {
4104 size = 2;
4105 if (i.types[n] & Disp8)
4106 size = 1;
4107 if (i.types[n] & Disp64)
4108 size = 8;
4109 }
4110 return size;
4111}
4112
4113/* Return the size of the immediate operand N. */
4114
4115static int
4116imm_size (unsigned int n)
4117{
4118 int size = 4;
4119 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4120 {
4121 size = 2;
4122 if (i.types[n] & (Imm8 | Imm8S))
4123 size = 1;
4124 if (i.types[n] & Imm64)
4125 size = 8;
4126 }
4127 return size;
4128}
4129
29b0f896 4130static void
64e74474 4131output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 4132{
4133 char *p;
4134 unsigned int n;
252b5132 4135
29b0f896
AM		 4136 for (n = 0; n < i.operands; n++)
4137 {
4138 if (i.types[n] & Disp)
4139 {
4140 if (i.op[n].disps->X_op == O_constant)
4141 {
e205caa7 4142 int size = disp_size (n);
29b0f896 4143 offsetT val;
252b5132 4144
29b0f896
AM		 4145 val = offset_in_range (i.op[n].disps->X_add_number,
4146 size);
4147 p = frag_more (size);
4148 md_number_to_chars (p, val, size);
4149 }
4150 else
4151 {
f86103b7 4152 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 4153 int size = disp_size (n);
4154 int sign = (i.types[n] & Disp32S) != 0;
29b0f896
AM		 4155 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
4156
e205caa7
L		 4157 /* We can't have 8 bit displacement here. */
4158 assert ((i.types[n] & Disp8) == 0);
4159
29b0f896
AM		 4160 /* The PC relative address is computed relative
4161 to the instruction boundary, so in case immediate
4162 fields follows, we need to adjust the value. */
4163 if (pcrel && i.imm_operands)
4164 {
29b0f896 4165 unsigned int n1;
e205caa7 4166 int sz = 0;
252b5132 4167
29b0f896
AM		 4168 for (n1 = 0; n1 < i.operands; n1++)
4169 if (i.types[n1] & Imm)
252b5132 4170 {
e205caa7
L		 4171 /* Only one immediate is allowed for PC
4172 relative address. */
4173 assert (sz == 0);
4174 sz = imm_size (n1);
4175 i.op[n].disps->X_add_number -= sz;
252b5132 4176 }
29b0f896 4177 /* We should find the immediate. */
e205caa7 4178 assert (sz != 0);
29b0f896 4179 }
520dc8e8 4180
29b0f896 4181 p = frag_more (size);
2bbd9c25 4182 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 4183 if (GOT_symbol
2bbd9c25 4184 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 4185 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 4186 || reloc_type == BFD_RELOC_X86_64_32S
4187 || (reloc_type == BFD_RELOC_64
4188 && object_64bit))
d6ab8113
JB		 4189 && (i.op[n].disps->X_op == O_symbol
4190 || (i.op[n].disps->X_op == O_add
4191 && ((symbol_get_value_expression
4192 (i.op[n].disps->X_op_symbol)->X_op)
4193 == O_subtract))))
4194 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 4195 {
4196 offsetT add;
4197
4198 if (insn_start_frag == frag_now)
4199 add = (p - frag_now->fr_literal) - insn_start_off;
4200 else
4201 {
4202 fragS *fr;
4203
4204 add = insn_start_frag->fr_fix - insn_start_off;
4205 for (fr = insn_start_frag->fr_next;
4206 fr && fr != frag_now; fr = fr->fr_next)
4207 add += fr->fr_fix;
4208 add += p - frag_now->fr_literal;
4209 }
4210
4fa24527 4211 if (!object_64bit)
7b81dfbb
AJ		 4212 {
4213 reloc_type = BFD_RELOC_386_GOTPC;
4214 i.op[n].imms->X_add_number += add;
4215 }
4216 else if (reloc_type == BFD_RELOC_64)
4217 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 4218 else
7b81dfbb
AJ		 4219 /* Don't do the adjustment for x86-64, as there
4220 the pcrel addressing is relative to the _next_
4221 insn, and that is taken care of in other code. */
d6ab8113 4222 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 4223 }
062cd5e7 4224 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 4225 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 4226 }
4227 }
4228 }
4229}
252b5132 4230
29b0f896 4231static void
64e74474 4232output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 4233{
4234 char *p;
4235 unsigned int n;
252b5132 4236
29b0f896
AM		 4237 for (n = 0; n < i.operands; n++)
4238 {
4239 if (i.types[n] & Imm)
4240 {
4241 if (i.op[n].imms->X_op == O_constant)
4242 {
e205caa7 4243 int size = imm_size (n);
29b0f896 4244 offsetT val;
b4cac588 4245
29b0f896
AM		 4246 val = offset_in_range (i.op[n].imms->X_add_number,
4247 size);
4248 p = frag_more (size);
4249 md_number_to_chars (p, val, size);
4250 }
4251 else
4252 {
4253 /* Not absolute_section.
4254 Need a 32-bit fixup (don't support 8bit
4255 non-absolute imms). Try to support other
4256 sizes ... */
f86103b7 4257 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 4258 int size = imm_size (n);
4259 int sign;
29b0f896
AM		 4260
4261 if ((i.types[n] & (Imm32S))
a7d61044
JB		 4262 && (i.suffix == QWORD_MNEM_SUFFIX
4263 || (!i.suffix && (i.tm.opcode_modifier & No_lSuf))))
29b0f896 4264 sign = 1;
e205caa7
L		 4265 else
4266 sign = 0;
520dc8e8 4267
29b0f896
AM		 4268 p = frag_more (size);
4269 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 4270
2bbd9c25
JJ		 4271 /* This is tough to explain. We end up with this one if we
4272 * have operands that look like
4273 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
4274 * obtain the absolute address of the GOT, and it is strongly
4275 * preferable from a performance point of view to avoid using
4276 * a runtime relocation for this. The actual sequence of
4277 * instructions often look something like:
4278 *
4279 * call .L66
4280 * .L66:
4281 * popl %ebx
4282 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4283 *
4284 * The call and pop essentially return the absolute address
4285 * of the label .L66 and store it in %ebx. The linker itself
4286 * will ultimately change the first operand of the addl so
4287 * that %ebx points to the GOT, but to keep things simple, the
4288 * .o file must have this operand set so that it generates not
4289 * the absolute address of .L66, but the absolute address of
4290 * itself. This allows the linker itself simply treat a GOTPC
4291 * relocation as asking for a pcrel offset to the GOT to be
4292 * added in, and the addend of the relocation is stored in the
4293 * operand field for the instruction itself.
4294 *
4295 * Our job here is to fix the operand so that it would add
4296 * the correct offset so that %ebx would point to itself. The
4297 * thing that is tricky is that .-.L66 will point to the
4298 * beginning of the instruction, so we need to further modify
4299 * the operand so that it will point to itself. There are
4300 * other cases where you have something like:
4301 *
4302 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4303 *
4304 * and here no correction would be required. Internally in
4305 * the assembler we treat operands of this form as not being
4306 * pcrel since the '.' is explicitly mentioned, and I wonder
4307 * whether it would simplify matters to do it this way. Who
4308 * knows. In earlier versions of the PIC patches, the
4309 * pcrel_adjust field was used to store the correction, but
4310 * since the expression is not pcrel, I felt it would be
4311 * confusing to do it this way. */
4312
d6ab8113 4313 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 4314 || reloc_type == BFD_RELOC_X86_64_32S
4315 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 4316 && GOT_symbol
4317 && GOT_symbol == i.op[n].imms->X_add_symbol
4318 && (i.op[n].imms->X_op == O_symbol
4319 || (i.op[n].imms->X_op == O_add
4320 && ((symbol_get_value_expression
4321 (i.op[n].imms->X_op_symbol)->X_op)
4322 == O_subtract))))
4323 {
2bbd9c25
JJ		 4324 offsetT add;
4325
4326 if (insn_start_frag == frag_now)
4327 add = (p - frag_now->fr_literal) - insn_start_off;
4328 else
4329 {
4330 fragS *fr;
4331
4332 add = insn_start_frag->fr_fix - insn_start_off;
4333 for (fr = insn_start_frag->fr_next;
4334 fr && fr != frag_now; fr = fr->fr_next)
4335 add += fr->fr_fix;
4336 add += p - frag_now->fr_literal;
4337 }
4338
4fa24527 4339 if (!object_64bit)
d6ab8113 4340 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 4341 else if (size == 4)
d6ab8113 4342 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 4343 else if (size == 8)
4344 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 4345 i.op[n].imms->X_add_number += add;
29b0f896 4346 }
29b0f896
AM		 4347 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4348 i.op[n].imms, 0, reloc_type);
4349 }
4350 }
4351 }
252b5132
RH		 4352}
4353\f
d182319b
JB		 4354/* x86_cons_fix_new is called via the expression parsing code when a
4355 reloc is needed. We use this hook to get the correct .got reloc. */
4356static enum bfd_reloc_code_real got_reloc = NO_RELOC;
4357static int cons_sign = -1;
4358
4359void
e3bb37b5 4360x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 4361 expressionS *exp)
d182319b
JB		 4362{
4363 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
4364
4365 got_reloc = NO_RELOC;
4366
4367#ifdef TE_PE
4368 if (exp->X_op == O_secrel)
4369 {
4370 exp->X_op = O_symbol;
4371 r = BFD_RELOC_32_SECREL;
4372 }
4373#endif
4374
4375 fix_new_exp (frag, off, len, exp, 0, r);
4376}
4377
718ddfc0
JB		 4378#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
4379# define lex_got(reloc, adjust, types) NULL
4380#else
f3c180ae
AM		 4381/* Parse operands of the form
4382 <symbol>@GOTOFF+<nnn>
4383 and similar .plt or .got references.
4384
4385 If we find one, set up the correct relocation in RELOC and copy the
4386 input string, minus the `@GOTOFF' into a malloc'd buffer for
4387 parsing by the calling routine. Return this buffer, and if ADJUST
4388 is non-null set it to the length of the string we removed from the
4389 input line. Otherwise return NULL. */
4390static char *
3956db08 4391lex_got (enum bfd_reloc_code_real *reloc,
64e74474
AM		 4392 int *adjust,
4393 unsigned int *types)
f3c180ae 4394{
7b81dfbb
AJ		 4395 /* Some of the relocations depend on the size of what field is to
4396 be relocated. But in our callers i386_immediate and i386_displacement
4397 we don't yet know the operand size (this will be set by insn
4398 matching). Hence we record the word32 relocation here,
4399 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 4400 static const struct {
4401 const char *str;
4fa24527 4402 const enum bfd_reloc_code_real rel[2];
3956db08 4403 const unsigned int types64;
f3c180ae 4404 } gotrel[] = {
4eed87de
AM		 4405 { "PLTOFF", { 0,
4406 BFD_RELOC_X86_64_PLTOFF64 },
4407 Imm64 },
4408 { "PLT", { BFD_RELOC_386_PLT32,
4409 BFD_RELOC_X86_64_PLT32 },
4410 Imm32 | Imm32S | Disp32 },
4411 { "GOTPLT", { 0,
4412 BFD_RELOC_X86_64_GOTPLT64 },
4413 Imm64 | Disp64 },
4414 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
4415 BFD_RELOC_X86_64_GOTOFF64 },
4416 Imm64 | Disp64 },
4417 { "GOTPCREL", { 0,
4418 BFD_RELOC_X86_64_GOTPCREL },
4419 Imm32 | Imm32S | Disp32 },
4420 { "TLSGD", { BFD_RELOC_386_TLS_GD,
4421 BFD_RELOC_X86_64_TLSGD },
4422 Imm32 | Imm32S | Disp32 },
4423 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
4424 0 },
4425 0 },
4426 { "TLSLD", { 0,
4427 BFD_RELOC_X86_64_TLSLD },
4428 Imm32 | Imm32S | Disp32 },
4429 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
4430 BFD_RELOC_X86_64_GOTTPOFF },
4431 Imm32 | Imm32S | Disp32 },
4432 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
4433 BFD_RELOC_X86_64_TPOFF32 },
4434 Imm32 | Imm32S | Imm64 | Disp32 | Disp64 },
4435 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
4436 0 },
4437 0 },
4438 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
4439 BFD_RELOC_X86_64_DTPOFF32 },
4440 Imm32 | Imm32S | Imm64 | Disp32 | Disp64 },
4441 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
4442 0 },
4443 0 },
4444 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
4445 0 },
4446 0 },
4447 { "GOT", { BFD_RELOC_386_GOT32,
4448 BFD_RELOC_X86_64_GOT32 },
4449 Imm32 | Imm32S | Disp32 | Imm64 },
4450 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
4451 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
4452 Imm32 | Imm32S | Disp32 },
4453 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
4454 BFD_RELOC_X86_64_TLSDESC_CALL },
4455 Imm32 | Imm32S | Disp32 }
f3c180ae
AM		 4456 };
4457 char *cp;
4458 unsigned int j;
4459
718ddfc0
JB		 4460 if (!IS_ELF)
4461 return NULL;
4462
f3c180ae
AM		 4463 for (cp = input_line_pointer; *cp != '@'; cp++)
4464 if (is_end_of_line[(unsigned char) *cp])
4465 return NULL;
4466
4467 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
4468 {
4469 int len;
4470
4471 len = strlen (gotrel[j].str);
28f81592 4472 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 4473 {
4fa24527 4474 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 4475 {
28f81592
AM		 4476 int first, second;
4477 char *tmpbuf, *past_reloc;
f3c180ae 4478
4fa24527 4479 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 4480 if (adjust)
4481 *adjust = len;
f3c180ae 4482
3956db08
JB		 4483 if (types)
4484 {
4485 if (flag_code != CODE_64BIT)
4eed87de 4486 *types = Imm32 | Disp32;
3956db08
JB		 4487 else
4488 *types = gotrel[j].types64;
4489 }
4490
f3c180ae
AM		 4491 if (GOT_symbol == NULL)
4492 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
4493
28f81592 4494 /* The length of the first part of our input line. */
f3c180ae 4495 first = cp - input_line_pointer;
28f81592
AM		 4496
4497 /* The second part goes from after the reloc token until
4498 (and including) an end_of_line char. Don't use strlen
4499 here as the end_of_line char may not be a NUL. */
4500 past_reloc = cp + 1 + len;
4501 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
4502 ;
4503 second = cp - past_reloc;
4504
4505 /* Allocate and copy string. The trailing NUL shouldn't
4506 be necessary, but be safe. */
4507 tmpbuf = xmalloc (first + second + 2);
f3c180ae 4508 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 4509 if (second != 0 && *past_reloc != ' ')
4510 /* Replace the relocation token with ' ', so that
4511 errors like foo@GOTOFF1 will be detected. */
4512 tmpbuf[first++] = ' ';
4513 memcpy (tmpbuf + first, past_reloc, second);
4514 tmpbuf[first + second] = '\0';
f3c180ae
AM		 4515 return tmpbuf;
4516 }
4517
4fa24527
JB		 4518 as_bad (_("@%s reloc is not supported with %d-bit output format"),
4519 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 4520 return NULL;
4521 }
4522 }
4523
4524 /* Might be a symbol version string. Don't as_bad here. */
4525 return NULL;
4526}
4527
f3c180ae 4528void
e3bb37b5 4529x86_cons (expressionS *exp, int size)
f3c180ae 4530{
4fa24527 4531 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 4532 {
4533 /* Handle @GOTOFF and the like in an expression. */
4534 char *save;
4535 char *gotfree_input_line;
4536 int adjust;
4537
4538 save = input_line_pointer;
3956db08 4539 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 4540 if (gotfree_input_line)
4541 input_line_pointer = gotfree_input_line;
4542
4543 expression (exp);
4544
4545 if (gotfree_input_line)
4546 {
4547 /* expression () has merrily parsed up to the end of line,
4548 or a comma - in the wrong buffer. Transfer how far
4549 input_line_pointer has moved to the right buffer. */
4550 input_line_pointer = (save
4551 + (input_line_pointer - gotfree_input_line)
4552 + adjust);
4553 free (gotfree_input_line);
4554 }
4555 }
4556 else
4557 expression (exp);
4558}
4559#endif
4560
d182319b 4561static void signed_cons (int size)
6482c264 4562{
d182319b
JB		 4563 if (flag_code == CODE_64BIT)
4564 cons_sign = 1;
4565 cons (size);
4566 cons_sign = -1;
6482c264
NC		 4567}
4568
d182319b 4569#ifdef TE_PE
6482c264
NC		 4570static void
4571pe_directive_secrel (dummy)
4572 int dummy ATTRIBUTE_UNUSED;
4573{
4574 expressionS exp;
4575
4576 do
4577 {
4578 expression (&exp);
4579 if (exp.X_op == O_symbol)
4580 exp.X_op = O_secrel;
4581
4582 emit_expr (&exp, 4);
4583 }
4584 while (*input_line_pointer++ == ',');
4585
4586 input_line_pointer--;
4587 demand_empty_rest_of_line ();
4588}
6482c264
NC		 4589#endif
4590
252b5132 4591static int
70e41ade 4592i386_immediate (char *imm_start)
252b5132
RH		 4593{
4594 char *save_input_line_pointer;
f3c180ae 4595 char *gotfree_input_line;
252b5132 4596 segT exp_seg = 0;
47926f60 4597 expressionS *exp;
3956db08 4598 unsigned int types = ~0U;
252b5132
RH		 4599
4600 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
4601 {
31b2323c
L		 4602 as_bad (_("at most %d immediate operands are allowed"),
4603 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 4604 return 0;
4605 }
4606
4607 exp = &im_expressions[i.imm_operands++];
520dc8e8 4608 i.op[this_operand].imms = exp;
252b5132
RH		 4609
4610 if (is_space_char (*imm_start))
4611 ++imm_start;
4612
4613 save_input_line_pointer = input_line_pointer;
4614 input_line_pointer = imm_start;
4615
3956db08 4616 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4617 if (gotfree_input_line)
4618 input_line_pointer = gotfree_input_line;
252b5132
RH		 4619
4620 exp_seg = expression (exp);
4621
83183c0c 4622 SKIP_WHITESPACE ();
252b5132 4623 if (*input_line_pointer)
f3c180ae 4624 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 4625
4626 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 4627 if (gotfree_input_line)
4628 free (gotfree_input_line);
252b5132 4629
2daf4fd8 4630 if (exp->X_op == O_absent || exp->X_op == O_big)
252b5132 4631 {
47926f60 4632 /* Missing or bad expr becomes absolute 0. */
d0b47220 4633 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
24eab124 4634 imm_start);
252b5132
RH		 4635 exp->X_op = O_constant;
4636 exp->X_add_number = 0;
4637 exp->X_add_symbol = (symbolS *) 0;
4638 exp->X_op_symbol = (symbolS *) 0;
252b5132 4639 }
3e73aa7c 4640 else if (exp->X_op == O_constant)
252b5132 4641 {
47926f60 4642 /* Size it properly later. */
3e73aa7c
JH		 4643 i.types[this_operand] |= Imm64;
4644 /* If BFD64, sign extend val. */
4eed87de
AM		 4645 if (!use_rela_relocations
4646 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
4647 exp->X_add_number
4648 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 4649 }
4c63da97 4650#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 4651 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4652 && exp_seg != absolute_section
47926f60 4653 && exp_seg != text_section
24eab124
AM		 4654 && exp_seg != data_section
4655 && exp_seg != bss_section
4656 && exp_seg != undefined_section
f86103b7 4657 && !bfd_is_com_section (exp_seg))
252b5132 4658 {
d0b47220 4659 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 4660 return 0;
4661 }
4662#endif
bb8f5920
L		 4663 else if (!intel_syntax && exp->X_op == O_register)
4664 {
4665 as_bad (_("illegal immediate register operand %s"), imm_start);
4666 return 0;
4667 }
252b5132
RH		 4668 else
4669 {
4670 /* This is an address. The size of the address will be
24eab124 4671 determined later, depending on destination register,
3e73aa7c
JH		 4672 suffix, or the default for the section. */
4673 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
3956db08 4674 i.types[this_operand] &= types;
252b5132
RH		 4675 }
4676
4677 return 1;
4678}
4679
551c1ca1 4680static char *
e3bb37b5 4681i386_scale (char *scale)
252b5132 4682{
551c1ca1
AM		 4683 offsetT val;
4684 char *save = input_line_pointer;
252b5132 4685
551c1ca1
AM		 4686 input_line_pointer = scale;
4687 val = get_absolute_expression ();
4688
4689 switch (val)
252b5132 4690 {
551c1ca1 4691 case 1:
252b5132
RH		 4692 i.log2_scale_factor = 0;
4693 break;
551c1ca1 4694 case 2:
252b5132
RH		 4695 i.log2_scale_factor = 1;
4696 break;
551c1ca1 4697 case 4:
252b5132
RH		 4698 i.log2_scale_factor = 2;
4699 break;
551c1ca1 4700 case 8:
252b5132
RH		 4701 i.log2_scale_factor = 3;
4702 break;
4703 default:
a724f0f4
JB		 4704 {
4705 char sep = *input_line_pointer;
4706
4707 *input_line_pointer = '\0';
4708 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4709 scale);
4710 *input_line_pointer = sep;
4711 input_line_pointer = save;
4712 return NULL;
4713 }
252b5132 4714 }
29b0f896 4715 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 4716 {
4717 as_warn (_("scale factor of %d without an index register"),
24eab124 4718 1 << i.log2_scale_factor);
252b5132
RH		 4719#if SCALE1_WHEN_NO_INDEX
4720 i.log2_scale_factor = 0;
4721#endif
4722 }
551c1ca1
AM		 4723 scale = input_line_pointer;
4724 input_line_pointer = save;
4725 return scale;
252b5132
RH		 4726}
4727
252b5132 4728static int
e3bb37b5 4729i386_displacement (char *disp_start, char *disp_end)
252b5132 4730{
29b0f896 4731 expressionS *exp;
252b5132
RH		 4732 segT exp_seg = 0;
4733 char *save_input_line_pointer;
f3c180ae 4734 char *gotfree_input_line;
e05278af 4735 int bigdisp, override;
3956db08 4736 unsigned int types = Disp;
252b5132 4737
31b2323c
L		 4738 if (i.disp_operands == MAX_MEMORY_OPERANDS)
4739 {
4740 as_bad (_("at most %d displacement operands are allowed"),
4741 MAX_MEMORY_OPERANDS);
4742 return 0;
4743 }
4744
e05278af
JB		 4745 if ((i.types[this_operand] & JumpAbsolute)
4746 || !(current_templates->start->opcode_modifier & (Jump | JumpDword)))
4747 {
4748 bigdisp = Disp32;
4749 override = (i.prefix[ADDR_PREFIX] != 0);
4750 }
4751 else
4752 {
4753 /* For PC-relative branches, the width of the displacement
4754 is dependent upon data size, not address size. */
4755 bigdisp = 0;
4756 override = (i.prefix[DATA_PREFIX] != 0);
4757 }
3e73aa7c 4758 if (flag_code == CODE_64BIT)
7ecd2f8b 4759 {
e05278af 4760 if (!bigdisp)
64e74474
AM		 4761 bigdisp = ((override || i.suffix == WORD_MNEM_SUFFIX)
4762 ? Disp16
4763 : Disp32S | Disp32);
e05278af 4764 else if (!override)
3956db08 4765 bigdisp = Disp64 | Disp32S | Disp32;
7ecd2f8b 4766 }
e05278af
JB		 4767 else
4768 {
4769 if (!bigdisp)
4770 {
4771 if (!override)
4772 override = (i.suffix == (flag_code != CODE_16BIT
4773 ? WORD_MNEM_SUFFIX
4774 : LONG_MNEM_SUFFIX));
4775 bigdisp = Disp32;
4776 }
4777 if ((flag_code == CODE_16BIT) ^ override)
4778 bigdisp = Disp16;
4779 }
252b5132
RH		 4780 i.types[this_operand] |= bigdisp;
4781
4782 exp = &disp_expressions[i.disp_operands];
520dc8e8 4783 i.op[this_operand].disps = exp;
252b5132
RH		 4784 i.disp_operands++;
4785 save_input_line_pointer = input_line_pointer;
4786 input_line_pointer = disp_start;
4787 END_STRING_AND_SAVE (disp_end);
4788
4789#ifndef GCC_ASM_O_HACK
4790#define GCC_ASM_O_HACK 0
4791#endif
4792#if GCC_ASM_O_HACK
4793 END_STRING_AND_SAVE (disp_end + 1);
4794 if ((i.types[this_operand] & BaseIndex) != 0
24eab124 4795 && displacement_string_end[-1] == '+')
252b5132
RH		 4796 {
4797 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 4798 constraint within gcc asm statements.
4799 For instance:
4800
4801 #define _set_tssldt_desc(n,addr,limit,type) \
4802 __asm__ __volatile__ ( \
4803 "movw %w2,%0\n\t" \
4804 "movw %w1,2+%0\n\t" \
4805 "rorl $16,%1\n\t" \
4806 "movb %b1,4+%0\n\t" \
4807 "movb %4,5+%0\n\t" \
4808 "movb $0,6+%0\n\t" \
4809 "movb %h1,7+%0\n\t" \
4810 "rorl $16,%1" \
4811 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4812
4813 This works great except that the output assembler ends
4814 up looking a bit weird if it turns out that there is
4815 no offset. You end up producing code that looks like:
4816
4817 #APP
4818 movw $235,(%eax)
4819 movw %dx,2+(%eax)
4820 rorl $16,%edx
4821 movb %dl,4+(%eax)
4822 movb $137,5+(%eax)
4823 movb $0,6+(%eax)
4824 movb %dh,7+(%eax)
4825 rorl $16,%edx
4826 #NO_APP
4827
47926f60 4828 So here we provide the missing zero. */
24eab124
AM		 4829
4830 *displacement_string_end = '0';
252b5132
RH		 4831 }
4832#endif
3956db08 4833 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4834 if (gotfree_input_line)
4835 input_line_pointer = gotfree_input_line;
252b5132 4836
24eab124 4837 exp_seg = expression (exp);
252b5132 4838
636c26b0
AM		 4839 SKIP_WHITESPACE ();
4840 if (*input_line_pointer)
4841 as_bad (_("junk `%s' after expression"), input_line_pointer);
4842#if GCC_ASM_O_HACK
4843 RESTORE_END_STRING (disp_end + 1);
4844#endif
4845 RESTORE_END_STRING (disp_end);
4846 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 4847 if (gotfree_input_line)
4848 free (gotfree_input_line);
636c26b0 4849
24eab124
AM		 4850 /* We do this to make sure that the section symbol is in
4851 the symbol table. We will ultimately change the relocation
47926f60 4852 to be relative to the beginning of the section. */
1ae12ab7 4853 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 4854 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4855 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 4856 {
636c26b0
AM		 4857 if (exp->X_op != O_symbol)
4858 {
4859 as_bad (_("bad expression used with @%s"),
4860 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4861 ? "GOTPCREL"
4862 : "GOTOFF"));
4863 return 0;
4864 }
4865
e5cb08ac 4866 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 4867 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
4868 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 4869 exp->X_op = O_subtract;
4870 exp->X_op_symbol = GOT_symbol;
1ae12ab7 4871 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 4872 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 4873 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4874 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 4875 else
29b0f896 4876 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 4877 }
252b5132 4878
2daf4fd8
AM		 4879 if (exp->X_op == O_absent || exp->X_op == O_big)
4880 {
47926f60 4881 /* Missing or bad expr becomes absolute 0. */
d0b47220 4882 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
2daf4fd8
AM		 4883 disp_start);
4884 exp->X_op = O_constant;
4885 exp->X_add_number = 0;
4886 exp->X_add_symbol = (symbolS *) 0;
4887 exp->X_op_symbol = (symbolS *) 0;
4888 }
4889
4c63da97 4890#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
45288df1 4891 if (exp->X_op != O_constant
45288df1 4892 && OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4893 && exp_seg != absolute_section
45288df1
AM		 4894 && exp_seg != text_section
4895 && exp_seg != data_section
4896 && exp_seg != bss_section
31312f95 4897 && exp_seg != undefined_section
f86103b7 4898 && !bfd_is_com_section (exp_seg))
24eab124 4899 {
d0b47220 4900 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
24eab124
AM		 4901 return 0;
4902 }
252b5132 4903#endif
3956db08
JB		 4904
4905 if (!(i.types[this_operand] & ~Disp))
4906 i.types[this_operand] &= types;
4907
252b5132
RH		 4908 return 1;
4909}
4910
eecb386c 4911/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 4912 Return 1 on success, 0 on a failure. */
4913
252b5132 4914static int
e3bb37b5 4915i386_index_check (const char *operand_string)
252b5132 4916{
3e73aa7c 4917 int ok;
24eab124 4918#if INFER_ADDR_PREFIX
eecb386c
AM		 4919 int fudged = 0;
4920
24eab124
AM		 4921 tryprefix:
4922#endif
3e73aa7c 4923 ok = 1;
30123838
JB		 4924 if ((current_templates->start->cpu_flags & CpuSVME)
4925 && current_templates->end[-1].operand_types[0] == AnyMem)
4926 {
4927 /* Memory operands of SVME insns are special in that they only allow
4928 rAX as their memory address and ignore any segment override. */
4929 unsigned RegXX;
4930
4931 /* SKINIT is even more restrictive: it always requires EAX. */
4932 if (strcmp (current_templates->start->name, "skinit") == 0)
4933 RegXX = Reg32;
4934 else if (flag_code == CODE_64BIT)
4935 RegXX = i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32;
4936 else
64e74474
AM		 4937 RegXX = ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
4938 ? Reg16
4939 : Reg32);
30123838
JB		 4940 if (!i.base_reg
4941 || !(i.base_reg->reg_type & Acc)
4942 || !(i.base_reg->reg_type & RegXX)
4943 || i.index_reg
4944 || (i.types[0] & Disp))
4945 ok = 0;
4946 }
4947 else if (flag_code == CODE_64BIT)
64e74474
AM		 4948 {
4949 unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
4950
4951 if ((i.base_reg
4952 && ((i.base_reg->reg_type & RegXX) == 0)
4953 && (i.base_reg->reg_type != BaseIndex
4954 || i.index_reg))
4955 || (i.index_reg
4956 && ((i.index_reg->reg_type & (RegXX | BaseIndex))
4957 != (RegXX | BaseIndex))))
4958 ok = 0;
3e73aa7c
JH		 4959 }
4960 else
4961 {
4962 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4963 {
4964 /* 16bit checks. */
4965 if ((i.base_reg
29b0f896
AM		 4966 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
4967 != (Reg16 | BaseIndex)))
3e73aa7c 4968 || (i.index_reg
29b0f896
AM		 4969 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
4970 != (Reg16 | BaseIndex))
4971 || !(i.base_reg
4972 && i.base_reg->reg_num < 6
4973 && i.index_reg->reg_num >= 6
4974 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 4975 ok = 0;
4976 }
4977 else
e5cb08ac 4978 {
3e73aa7c
JH		 4979 /* 32bit checks. */
4980 if ((i.base_reg
4981 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
4982 || (i.index_reg
29b0f896
AM		 4983 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
4984 != (Reg32 | BaseIndex))))
e5cb08ac 4985 ok = 0;
3e73aa7c
JH		 4986 }
4987 }
4988 if (!ok)
24eab124
AM		 4989 {
4990#if INFER_ADDR_PREFIX
20f0a1fc 4991 if (i.prefix[ADDR_PREFIX] == 0)
24eab124
AM		 4992 {
4993 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
4994 i.prefixes += 1;
b23bac36
AM		 4995 /* Change the size of any displacement too. At most one of
4996 Disp16 or Disp32 is set.
4997 FIXME. There doesn't seem to be any real need for separate
4998 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 4999 Removing them would probably clean up the code quite a lot. */
4eed87de
AM		 5000 if (flag_code != CODE_64BIT
5001 && (i.types[this_operand] & (Disp16 | Disp32)))
64e74474 5002 i.types[this_operand] ^= (Disp16 | Disp32);
eecb386c 5003 fudged = 1;
24eab124
AM		 5004 goto tryprefix;
5005 }
eecb386c
AM		 5006 if (fudged)
5007 as_bad (_("`%s' is not a valid base/index expression"),
5008 operand_string);
5009 else
c388dee8 5010#endif
eecb386c
AM		 5011 as_bad (_("`%s' is not a valid %s bit base/index expression"),
5012 operand_string,
3e73aa7c 5013 flag_code_names[flag_code]);
24eab124 5014 }
20f0a1fc 5015 return ok;
24eab124 5016}
252b5132 5017
252b5132 5018/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 5019 on error. */
252b5132 5020
252b5132 5021static int
e3bb37b5 5022i386_operand (char *operand_string)
252b5132 5023{
af6bdddf
AM		 5024 const reg_entry *r;
5025 char *end_op;
24eab124 5026 char *op_string = operand_string;
252b5132 5027
24eab124 5028 if (is_space_char (*op_string))
252b5132
RH		 5029 ++op_string;
5030
24eab124 5031 /* We check for an absolute prefix (differentiating,
47926f60 5032 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 5033 if (*op_string == ABSOLUTE_PREFIX)
5034 {
5035 ++op_string;
5036 if (is_space_char (*op_string))
5037 ++op_string;
5038 i.types[this_operand] |= JumpAbsolute;
5039 }
252b5132 5040
47926f60 5041 /* Check if operand is a register. */
4d1bb795 5042 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 5043 {
24eab124
AM		 5044 /* Check for a segment override by searching for ':' after a
5045 segment register. */
5046 op_string = end_op;
5047 if (is_space_char (*op_string))
5048 ++op_string;
5049 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
5050 {
5051 switch (r->reg_num)
5052 {
5053 case 0:
5054 i.seg[i.mem_operands] = &es;
5055 break;
5056 case 1:
5057 i.seg[i.mem_operands] = &cs;
5058 break;
5059 case 2:
5060 i.seg[i.mem_operands] = &ss;
5061 break;
5062 case 3:
5063 i.seg[i.mem_operands] = &ds;
5064 break;
5065 case 4:
5066 i.seg[i.mem_operands] = &fs;
5067 break;
5068 case 5:
5069 i.seg[i.mem_operands] = &gs;
5070 break;
5071 }
252b5132 5072
24eab124 5073 /* Skip the ':' and whitespace. */
252b5132
RH		 5074 ++op_string;
5075 if (is_space_char (*op_string))
24eab124 5076 ++op_string;
252b5132 5077
24eab124
AM		 5078 if (!is_digit_char (*op_string)
5079 && !is_identifier_char (*op_string)
5080 && *op_string != '('
5081 && *op_string != ABSOLUTE_PREFIX)
5082 {
5083 as_bad (_("bad memory operand `%s'"), op_string);
5084 return 0;
5085 }
47926f60 5086 /* Handle case of %es:*foo. */
24eab124
AM		 5087 if (*op_string == ABSOLUTE_PREFIX)
5088 {
5089 ++op_string;
5090 if (is_space_char (*op_string))
5091 ++op_string;
5092 i.types[this_operand] |= JumpAbsolute;
5093 }
5094 goto do_memory_reference;
5095 }
5096 if (*op_string)
5097 {
d0b47220 5098 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 5099 return 0;
5100 }
5101 i.types[this_operand] |= r->reg_type & ~BaseIndex;
520dc8e8 5102 i.op[this_operand].regs = r;
24eab124
AM		 5103 i.reg_operands++;
5104 }
af6bdddf
AM		 5105 else if (*op_string == REGISTER_PREFIX)
5106 {
5107 as_bad (_("bad register name `%s'"), op_string);
5108 return 0;
5109 }
24eab124 5110 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 5111 {
24eab124
AM		 5112 ++op_string;
5113 if (i.types[this_operand] & JumpAbsolute)
5114 {
d0b47220 5115 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 5116 return 0;
5117 }
5118 if (!i386_immediate (op_string))
5119 return 0;
5120 }
5121 else if (is_digit_char (*op_string)
5122 || is_identifier_char (*op_string)
e5cb08ac 5123 || *op_string == '(')
24eab124 5124 {
47926f60 5125 /* This is a memory reference of some sort. */
af6bdddf 5126 char *base_string;
252b5132 5127
47926f60 5128 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 5129 char *displacement_string_start;
5130 char *displacement_string_end;
252b5132 5131
24eab124 5132 do_memory_reference:
24eab124
AM		 5133 if ((i.mem_operands == 1
5134 && (current_templates->start->opcode_modifier & IsString) == 0)
5135 || i.mem_operands == 2)
5136 {
5137 as_bad (_("too many memory references for `%s'"),
5138 current_templates->start->name);
5139 return 0;
5140 }
252b5132 5141
24eab124
AM		 5142 /* Check for base index form. We detect the base index form by
5143 looking for an ')' at the end of the operand, searching
5144 for the '(' matching it, and finding a REGISTER_PREFIX or ','
5145 after the '('. */
af6bdddf 5146 base_string = op_string + strlen (op_string);
c3332e24 5147
af6bdddf
AM		 5148 --base_string;
5149 if (is_space_char (*base_string))
5150 --base_string;
252b5132 5151
47926f60 5152 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 5153 displacement_string_start = op_string;
5154 displacement_string_end = base_string + 1;
252b5132 5155
24eab124
AM		 5156 if (*base_string == ')')
5157 {
af6bdddf 5158 char *temp_string;
24eab124
AM		 5159 unsigned int parens_balanced = 1;
5160 /* We've already checked that the number of left & right ()'s are
47926f60 5161 equal, so this loop will not be infinite. */
24eab124
AM		 5162 do
5163 {
5164 base_string--;
5165 if (*base_string == ')')
5166 parens_balanced++;
5167 if (*base_string == '(')
5168 parens_balanced--;
5169 }
5170 while (parens_balanced);
c3332e24 5171
af6bdddf 5172 temp_string = base_string;
c3332e24 5173
24eab124 5174 /* Skip past '(' and whitespace. */
252b5132
RH		 5175 ++base_string;
5176 if (is_space_char (*base_string))
24eab124 5177 ++base_string;
252b5132 5178
af6bdddf 5179 if (*base_string == ','
4eed87de
AM		 5180 || ((i.base_reg = parse_register (base_string, &end_op))
5181 != NULL))
252b5132 5182 {
af6bdddf 5183 displacement_string_end = temp_string;
252b5132 5184
af6bdddf 5185 i.types[this_operand] |= BaseIndex;
252b5132 5186
af6bdddf 5187 if (i.base_reg)
24eab124 5188 {
24eab124
AM		 5189 base_string = end_op;
5190 if (is_space_char (*base_string))
5191 ++base_string;
af6bdddf
AM		 5192 }
5193
5194 /* There may be an index reg or scale factor here. */
5195 if (*base_string == ',')
5196 {
5197 ++base_string;
5198 if (is_space_char (*base_string))
5199 ++base_string;
5200
4eed87de
AM		 5201 if ((i.index_reg = parse_register (base_string, &end_op))
5202 != NULL)
24eab124 5203 {
af6bdddf 5204 base_string = end_op;
24eab124
AM		 5205 if (is_space_char (*base_string))
5206 ++base_string;
af6bdddf
AM		 5207 if (*base_string == ',')
5208 {
5209 ++base_string;
5210 if (is_space_char (*base_string))
5211 ++base_string;
5212 }
e5cb08ac 5213 else if (*base_string != ')')
af6bdddf 5214 {
4eed87de
AM		 5215 as_bad (_("expecting `,' or `)' "
5216 "after index register in `%s'"),
af6bdddf
AM		 5217 operand_string);
5218 return 0;
5219 }
24eab124 5220 }
af6bdddf 5221 else if (*base_string == REGISTER_PREFIX)
24eab124 5222 {
af6bdddf 5223 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 5224 return 0;
5225 }
252b5132 5226
47926f60 5227 /* Check for scale factor. */
551c1ca1 5228 if (*base_string != ')')
af6bdddf 5229 {
551c1ca1
AM		 5230 char *end_scale = i386_scale (base_string);
5231
5232 if (!end_scale)
af6bdddf 5233 return 0;
24eab124 5234
551c1ca1 5235 base_string = end_scale;
af6bdddf
AM		 5236 if (is_space_char (*base_string))
5237 ++base_string;
5238 if (*base_string != ')')
5239 {
4eed87de
AM		 5240 as_bad (_("expecting `)' "
5241 "after scale factor in `%s'"),
af6bdddf
AM		 5242 operand_string);
5243 return 0;
5244 }
5245 }
5246 else if (!i.index_reg)
24eab124 5247 {
4eed87de
AM		 5248 as_bad (_("expecting index register or scale factor "
5249 "after `,'; got '%c'"),
af6bdddf 5250 *base_string);
24eab124
AM		 5251 return 0;
5252 }
5253 }
af6bdddf 5254 else if (*base_string != ')')
24eab124 5255 {
4eed87de
AM		 5256 as_bad (_("expecting `,' or `)' "
5257 "after base register in `%s'"),
af6bdddf 5258 operand_string);
24eab124
AM		 5259 return 0;
5260 }
c3332e24 5261 }
af6bdddf 5262 else if (*base_string == REGISTER_PREFIX)
c3332e24 5263 {
af6bdddf 5264 as_bad (_("bad register name `%s'"), base_string);
24eab124 5265 return 0;
c3332e24 5266 }
24eab124
AM		 5267 }
5268
5269 /* If there's an expression beginning the operand, parse it,
5270 assuming displacement_string_start and
5271 displacement_string_end are meaningful. */
5272 if (displacement_string_start != displacement_string_end)
5273 {
5274 if (!i386_displacement (displacement_string_start,
5275 displacement_string_end))
5276 return 0;
5277 }
5278
5279 /* Special case for (%dx) while doing input/output op. */
5280 if (i.base_reg
5281 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
5282 && i.index_reg == 0
5283 && i.log2_scale_factor == 0
5284 && i.seg[i.mem_operands] == 0
5285 && (i.types[this_operand] & Disp) == 0)
5286 {
5287 i.types[this_operand] = InOutPortReg;
5288 return 1;
5289 }
5290
eecb386c
AM		 5291 if (i386_index_check (operand_string) == 0)
5292 return 0;
24eab124
AM		 5293 i.mem_operands++;
5294 }
5295 else
ce8a8b2f
AM		 5296 {
5297 /* It's not a memory operand; argh! */
24eab124
AM		 5298 as_bad (_("invalid char %s beginning operand %d `%s'"),
5299 output_invalid (*op_string),
5300 this_operand + 1,
5301 op_string);
5302 return 0;
5303 }
47926f60 5304 return 1; /* Normal return. */
252b5132
RH		 5305}
5306\f
ee7fcc42
AM		 5307/* md_estimate_size_before_relax()
5308
5309 Called just before relax() for rs_machine_dependent frags. The x86
5310 assembler uses these frags to handle variable size jump
5311 instructions.
5312
5313 Any symbol that is now undefined will not become defined.
5314 Return the correct fr_subtype in the frag.
5315 Return the initial "guess for variable size of frag" to caller.
5316 The guess is actually the growth beyond the fixed part. Whatever
5317 we do to grow the fixed or variable part contributes to our
5318 returned value. */
5319
252b5132
RH		 5320int
5321md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 5322 fragS *fragP;
5323 segT segment;
252b5132 5324{
252b5132 5325 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 5326 check for un-relaxable symbols. On an ELF system, we can't relax
5327 an externally visible symbol, because it may be overridden by a
5328 shared library. */
5329 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 5330#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5331 || (IS_ELF
31312f95
AM		 5332 && (S_IS_EXTERNAL (fragP->fr_symbol)
5333 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 5334#endif
5335 )
252b5132 5336 {
b98ef147
AM		 5337 /* Symbol is undefined in this segment, or we need to keep a
5338 reloc so that weak symbols can be overridden. */
5339 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 5340 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 5341 unsigned char *opcode;
5342 int old_fr_fix;
f6af82bd 5343
ee7fcc42
AM		 5344 if (fragP->fr_var != NO_RELOC)
5345 reloc_type = fragP->fr_var;
b98ef147 5346 else if (size == 2)
f6af82bd
AM		 5347 reloc_type = BFD_RELOC_16_PCREL;
5348 else
5349 reloc_type = BFD_RELOC_32_PCREL;
252b5132 5350
ee7fcc42
AM		 5351 old_fr_fix = fragP->fr_fix;
5352 opcode = (unsigned char *) fragP->fr_opcode;
5353
fddf5b5b 5354 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 5355 {
fddf5b5b
AM		 5356 case UNCOND_JUMP:
5357 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 5358 opcode[0] = 0xe9;
252b5132 5359 fragP->fr_fix += size;
062cd5e7
AS		 5360 fix_new (fragP, old_fr_fix, size,
5361 fragP->fr_symbol,
5362 fragP->fr_offset, 1,
5363 reloc_type);
252b5132
RH		 5364 break;
5365
fddf5b5b 5366 case COND_JUMP86:
412167cb
AM		 5367 if (size == 2
5368 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 5369 {
5370 /* Negate the condition, and branch past an
5371 unconditional jump. */
5372 opcode[0] ^= 1;
5373 opcode[1] = 3;
5374 /* Insert an unconditional jump. */
5375 opcode[2] = 0xe9;
5376 /* We added two extra opcode bytes, and have a two byte
5377 offset. */
5378 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 5379 fix_new (fragP, old_fr_fix + 2, 2,
5380 fragP->fr_symbol,
5381 fragP->fr_offset, 1,
5382 reloc_type);
fddf5b5b
AM		 5383 break;
5384 }
5385 /* Fall through. */
5386
5387 case COND_JUMP:
412167cb
AM		 5388 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
5389 {
3e02c1cc
AM		 5390 fixS *fixP;
5391
412167cb 5392 fragP->fr_fix += 1;
3e02c1cc
AM		 5393 fixP = fix_new (fragP, old_fr_fix, 1,
5394 fragP->fr_symbol,
5395 fragP->fr_offset, 1,
5396 BFD_RELOC_8_PCREL);
5397 fixP->fx_signed = 1;
412167cb
AM		 5398 break;
5399 }
93c2a809 5400
24eab124 5401 /* This changes the byte-displacement jump 0x7N
fddf5b5b 5402 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 5403 opcode[1] = opcode[0] + 0x10;
f6af82bd 5404 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 5405 /* We've added an opcode byte. */
5406 fragP->fr_fix += 1 + size;
062cd5e7
AS		 5407 fix_new (fragP, old_fr_fix + 1, size,
5408 fragP->fr_symbol,
5409 fragP->fr_offset, 1,
5410 reloc_type);
252b5132 5411 break;
fddf5b5b
AM		 5412
5413 default:
5414 BAD_CASE (fragP->fr_subtype);
5415 break;
252b5132
RH		 5416 }
5417 frag_wane (fragP);
ee7fcc42 5418 return fragP->fr_fix - old_fr_fix;
252b5132 5419 }
93c2a809 5420
93c2a809
AM		 5421 /* Guess size depending on current relax state. Initially the relax
5422 state will correspond to a short jump and we return 1, because
5423 the variable part of the frag (the branch offset) is one byte
5424 long. However, we can relax a section more than once and in that
5425 case we must either set fr_subtype back to the unrelaxed state,
5426 or return the value for the appropriate branch. */
5427 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 5428}
5429
47926f60
KH		 5430/* Called after relax() is finished.
5431
5432 In: Address of frag.
5433 fr_type == rs_machine_dependent.
5434 fr_subtype is what the address relaxed to.
5435
5436 Out: Any fixSs and constants are set up.
5437 Caller will turn frag into a ".space 0". */
5438
252b5132
RH		 5439void
5440md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 5441 bfd *abfd ATTRIBUTE_UNUSED;
5442 segT sec ATTRIBUTE_UNUSED;
29b0f896 5443 fragS *fragP;
252b5132 5444{
29b0f896 5445 unsigned char *opcode;
252b5132 5446 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 5447 offsetT target_address;
5448 offsetT opcode_address;
252b5132 5449 unsigned int extension = 0;
847f7ad4 5450 offsetT displacement_from_opcode_start;
252b5132
RH		 5451
5452 opcode = (unsigned char *) fragP->fr_opcode;
5453
47926f60 5454 /* Address we want to reach in file space. */
252b5132 5455 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 5456
47926f60 5457 /* Address opcode resides at in file space. */
252b5132
RH		 5458 opcode_address = fragP->fr_address + fragP->fr_fix;
5459
47926f60 5460 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 5461 displacement_from_opcode_start = target_address - opcode_address;
5462
fddf5b5b 5463 if ((fragP->fr_subtype & BIG) == 0)
252b5132 5464 {
47926f60
KH		 5465 /* Don't have to change opcode. */
5466 extension = 1; /* 1 opcode + 1 displacement */
252b5132 5467 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 5468 }
5469 else
5470 {
5471 if (no_cond_jump_promotion
5472 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 5473 as_warn_where (fragP->fr_file, fragP->fr_line,
5474 _("long jump required"));
252b5132 5475
fddf5b5b
AM		 5476 switch (fragP->fr_subtype)
5477 {
5478 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
5479 extension = 4; /* 1 opcode + 4 displacement */
5480 opcode[0] = 0xe9;
5481 where_to_put_displacement = &opcode[1];
5482 break;
252b5132 5483
fddf5b5b
AM		 5484 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
5485 extension = 2; /* 1 opcode + 2 displacement */
5486 opcode[0] = 0xe9;
5487 where_to_put_displacement = &opcode[1];
5488 break;
252b5132 5489
fddf5b5b
AM		 5490 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
5491 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
5492 extension = 5; /* 2 opcode + 4 displacement */
5493 opcode[1] = opcode[0] + 0x10;
5494 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5495 where_to_put_displacement = &opcode[2];
5496 break;
252b5132 5497
fddf5b5b
AM		 5498 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
5499 extension = 3; /* 2 opcode + 2 displacement */
5500 opcode[1] = opcode[0] + 0x10;
5501 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5502 where_to_put_displacement = &opcode[2];
5503 break;
252b5132 5504
fddf5b5b
AM		 5505 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
5506 extension = 4;
5507 opcode[0] ^= 1;
5508 opcode[1] = 3;
5509 opcode[2] = 0xe9;
5510 where_to_put_displacement = &opcode[3];
5511 break;
5512
5513 default:
5514 BAD_CASE (fragP->fr_subtype);
5515 break;
5516 }
252b5132 5517 }
fddf5b5b 5518
7b81dfbb
AJ		 5519 /* If size if less then four we are sure that the operand fits,
5520 but if it's 4, then it could be that the displacement is larger
5521 then -/+ 2GB. */
5522 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
5523 && object_64bit
5524 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 5525 + ((addressT) 1 << 31))
5526 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 5527 {
5528 as_bad_where (fragP->fr_file, fragP->fr_line,
5529 _("jump target out of range"));
5530 /* Make us emit 0. */
5531 displacement_from_opcode_start = extension;
5532 }
47926f60 5533 /* Now put displacement after opcode. */
252b5132
RH		 5534 md_number_to_chars ((char *) where_to_put_displacement,
5535 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 5536 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 5537 fragP->fr_fix += extension;
5538}
5539\f
47926f60
KH		 5540/* Size of byte displacement jmp. */
5541int md_short_jump_size = 2;
5542
5543/* Size of dword displacement jmp. */
5544int md_long_jump_size = 5;
252b5132 5545
252b5132
RH		 5546void
5547md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
5548 char *ptr;
5549 addressT from_addr, to_addr;
ab9da554
ILT		 5550 fragS *frag ATTRIBUTE_UNUSED;
5551 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 5552{
847f7ad4 5553 offsetT offset;
252b5132
RH		 5554
5555 offset = to_addr - (from_addr + 2);
47926f60
KH		 5556 /* Opcode for byte-disp jump. */
5557 md_number_to_chars (ptr, (valueT) 0xeb, 1);
252b5132
RH		 5558 md_number_to_chars (ptr + 1, (valueT) offset, 1);
5559}
5560
5561void
5562md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
5563 char *ptr;
5564 addressT from_addr, to_addr;
a38cf1db
AM		 5565 fragS *frag ATTRIBUTE_UNUSED;
5566 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 5567{
847f7ad4 5568 offsetT offset;
252b5132 5569
a38cf1db
AM		 5570 offset = to_addr - (from_addr + 5);
5571 md_number_to_chars (ptr, (valueT) 0xe9, 1);
5572 md_number_to_chars (ptr + 1, (valueT) offset, 4);
252b5132
RH		 5573}
5574\f
5575/* Apply a fixup (fixS) to segment data, once it has been determined
5576 by our caller that we have all the info we need to fix it up.
5577
5578 On the 386, immediates, displacements, and data pointers are all in
5579 the same (little-endian) format, so we don't need to care about which
5580 we are handling. */
5581
94f592af 5582void
55cf6793 5583md_apply_fix (fixP, valP, seg)
47926f60
KH		 5584 /* The fix we're to put in. */
5585 fixS *fixP;
47926f60 5586 /* Pointer to the value of the bits. */
c6682705 5587 valueT *valP;
47926f60
KH		 5588 /* Segment fix is from. */
5589 segT seg ATTRIBUTE_UNUSED;
252b5132 5590{
94f592af 5591 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 5592 valueT value = *valP;
252b5132 5593
f86103b7 5594#if !defined (TE_Mach)
93382f6d
AM		 5595 if (fixP->fx_pcrel)
5596 {
5597 switch (fixP->fx_r_type)
5598 {
5865bb77
ILT		 5599 default:
5600 break;
5601
d6ab8113
JB		 5602 case BFD_RELOC_64:
5603 fixP->fx_r_type = BFD_RELOC_64_PCREL;
5604 break;
93382f6d 5605 case BFD_RELOC_32:
ae8887b5 5606 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 5607 fixP->fx_r_type = BFD_RELOC_32_PCREL;
5608 break;
5609 case BFD_RELOC_16:
5610 fixP->fx_r_type = BFD_RELOC_16_PCREL;
5611 break;
5612 case BFD_RELOC_8:
5613 fixP->fx_r_type = BFD_RELOC_8_PCREL;
5614 break;
5615 }
5616 }
252b5132 5617
a161fe53 5618 if (fixP->fx_addsy != NULL
31312f95 5619 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 5620 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 5621 || fixP->fx_r_type == BFD_RELOC_16_PCREL
5622 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
5623 && !use_rela_relocations)
252b5132 5624 {
31312f95
AM		 5625 /* This is a hack. There should be a better way to handle this.
5626 This covers for the fact that bfd_install_relocation will
5627 subtract the current location (for partial_inplace, PC relative
5628 relocations); see more below. */
252b5132 5629#ifndef OBJ_AOUT
718ddfc0 5630 if (IS_ELF
252b5132
RH		 5631#ifdef TE_PE
5632 || OUTPUT_FLAVOR == bfd_target_coff_flavour
5633#endif
5634 )
5635 value += fixP->fx_where + fixP->fx_frag->fr_address;
5636#endif
5637#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5638 if (IS_ELF)
252b5132 5639 {
6539b54b 5640 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 5641
6539b54b 5642 if ((sym_seg == seg
2f66722d 5643 || (symbol_section_p (fixP->fx_addsy)
6539b54b 5644 && sym_seg != absolute_section))
ae6063d4 5645 && !generic_force_reloc (fixP))
2f66722d
AM		 5646 {
5647 /* Yes, we add the values in twice. This is because
6539b54b
AM		 5648 bfd_install_relocation subtracts them out again. I think
5649 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 5650 it. FIXME. */
5651 value += fixP->fx_where + fixP->fx_frag->fr_address;
5652 }
252b5132
RH		 5653 }
5654#endif
5655#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 5656 /* For some reason, the PE format does not store a
5657 section address offset for a PC relative symbol. */
5658 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 5659 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 5660 value += md_pcrel_from (fixP);
5661#endif
5662 }
5663
5664 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 5665 and we must not disappoint it. */
252b5132 5666#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5667 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 5668 switch (fixP->fx_r_type)
5669 {
5670 case BFD_RELOC_386_PLT32:
3e73aa7c 5671 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 5672 /* Make the jump instruction point to the address of the operand. At
5673 runtime we merely add the offset to the actual PLT entry. */
5674 value = -4;
5675 break;
31312f95 5676
13ae64f3
JJ		 5677 case BFD_RELOC_386_TLS_GD:
5678 case BFD_RELOC_386_TLS_LDM:
13ae64f3 5679 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 5680 case BFD_RELOC_386_TLS_IE:
5681 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 5682 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 5683 case BFD_RELOC_X86_64_TLSGD:
5684 case BFD_RELOC_X86_64_TLSLD:
5685 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 5686 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 5687 value = 0; /* Fully resolved at runtime. No addend. */
5688 /* Fallthrough */
5689 case BFD_RELOC_386_TLS_LE:
5690 case BFD_RELOC_386_TLS_LDO_32:
5691 case BFD_RELOC_386_TLS_LE_32:
5692 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 5693 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 5694 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 5695 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 5696 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5697 break;
5698
67a4f2b7
AO		 5699 case BFD_RELOC_386_TLS_DESC_CALL:
5700 case BFD_RELOC_X86_64_TLSDESC_CALL:
5701 value = 0; /* Fully resolved at runtime. No addend. */
5702 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5703 fixP->fx_done = 0;
5704 return;
5705
00f7efb6
JJ		 5706 case BFD_RELOC_386_GOT32:
5707 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 5708 value = 0; /* Fully resolved at runtime. No addend. */
5709 break;
47926f60
KH		 5710
5711 case BFD_RELOC_VTABLE_INHERIT:
5712 case BFD_RELOC_VTABLE_ENTRY:
5713 fixP->fx_done = 0;
94f592af 5714 return;
47926f60
KH		 5715
5716 default:
5717 break;
5718 }
5719#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 5720 *valP = value;
f86103b7 5721#endif /* !defined (TE_Mach) */
3e73aa7c 5722
3e73aa7c 5723 /* Are we finished with this relocation now? */
c6682705 5724 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 5725 fixP->fx_done = 1;
5726 else if (use_rela_relocations)
5727 {
5728 fixP->fx_no_overflow = 1;
062cd5e7
AS		 5729 /* Remember value for tc_gen_reloc. */
5730 fixP->fx_addnumber = value;
3e73aa7c
JH		 5731 value = 0;
5732 }
f86103b7 5733
94f592af 5734 md_number_to_chars (p, value, fixP->fx_size);
252b5132 5735}
252b5132 5736\f
252b5132
RH		 5737#define MAX_LITTLENUMS 6
5738
47926f60
KH		 5739/* Turn the string pointed to by litP into a floating point constant
5740 of type TYPE, and emit the appropriate bytes. The number of
5741 LITTLENUMS emitted is stored in *SIZEP. An error message is
5742 returned, or NULL on OK. */
5743
252b5132
RH		 5744char *
5745md_atof (type, litP, sizeP)
2ab9b79e 5746 int type;
252b5132
RH		 5747 char *litP;
5748 int *sizeP;
5749{
5750 int prec;
5751 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5752 LITTLENUM_TYPE *wordP;
5753 char *t;
5754
5755 switch (type)
5756 {
5757 case 'f':
5758 case 'F':
5759 prec = 2;
5760 break;
5761
5762 case 'd':
5763 case 'D':
5764 prec = 4;
5765 break;
5766
5767 case 'x':
5768 case 'X':
5769 prec = 5;
5770 break;
5771
5772 default:
5773 *sizeP = 0;
5774 return _("Bad call to md_atof ()");
5775 }
5776 t = atof_ieee (input_line_pointer, type, words);
5777 if (t)
5778 input_line_pointer = t;
5779
5780 *sizeP = prec * sizeof (LITTLENUM_TYPE);
5781 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5782 the bigendian 386. */
5783 for (wordP = words + prec - 1; prec--;)
5784 {
5785 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
5786 litP += sizeof (LITTLENUM_TYPE);
5787 }
5788 return 0;
5789}
5790\f
2d545b82 5791static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 5792
252b5132 5793static char *
e3bb37b5 5794output_invalid (int c)
252b5132 5795{
3882b010 5796 if (ISPRINT (c))
f9f21a03
L		 5797 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
5798 "'%c'", c);
252b5132 5799 else
f9f21a03 5800 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 5801 "(0x%x)", (unsigned char) c);
252b5132
RH		 5802 return output_invalid_buf;
5803}
5804
af6bdddf 5805/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 5806
5807static const reg_entry *
4d1bb795 5808parse_real_register (char *reg_string, char **end_op)
252b5132 5809{
af6bdddf
AM		 5810 char *s = reg_string;
5811 char *p;
252b5132
RH		 5812 char reg_name_given[MAX_REG_NAME_SIZE + 1];
5813 const reg_entry *r;
5814
5815 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5816 if (*s == REGISTER_PREFIX)
5817 ++s;
5818
5819 if (is_space_char (*s))
5820 ++s;
5821
5822 p = reg_name_given;
af6bdddf 5823 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 5824 {
5825 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 5826 return (const reg_entry *) NULL;
5827 s++;
252b5132
RH		 5828 }
5829
6588847e
DN		 5830 /* For naked regs, make sure that we are not dealing with an identifier.
5831 This prevents confusing an identifier like `eax_var' with register
5832 `eax'. */
5833 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
5834 return (const reg_entry *) NULL;
5835
af6bdddf 5836 *end_op = s;
252b5132
RH		 5837
5838 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
5839
5f47d35b 5840 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 5841 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 5842 {
5f47d35b
AM		 5843 if (is_space_char (*s))
5844 ++s;
5845 if (*s == '(')
5846 {
af6bdddf 5847 ++s;
5f47d35b
AM		 5848 if (is_space_char (*s))
5849 ++s;
5850 if (*s >= '0' && *s <= '7')
5851 {
db557034 5852 int fpr = *s - '0';
af6bdddf 5853 ++s;
5f47d35b
AM		 5854 if (is_space_char (*s))
5855 ++s;
5856 if (*s == ')')
5857 {
5858 *end_op = s + 1;
db557034
AM		 5859 r = hash_find (reg_hash, "st(0)");
5860 know (r);
5861 return r + fpr;
5f47d35b 5862 }
5f47d35b 5863 }
47926f60 5864 /* We have "%st(" then garbage. */
5f47d35b
AM		 5865 return (const reg_entry *) NULL;
5866 }
5867 }
5868
1ae00879 5869 if (r != NULL
20f0a1fc 5870 && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0
c4a530c5 5871 && (r->reg_type != Control || !(cpu_arch_flags & CpuSledgehammer))
1ae00879 5872 && flag_code != CODE_64BIT)
20f0a1fc 5873 return (const reg_entry *) NULL;
1ae00879 5874
252b5132
RH		 5875 return r;
5876}
4d1bb795
JB		 5877
5878/* REG_STRING starts *before* REGISTER_PREFIX. */
5879
5880static const reg_entry *
5881parse_register (char *reg_string, char **end_op)
5882{
5883 const reg_entry *r;
5884
5885 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
5886 r = parse_real_register (reg_string, end_op);
5887 else
5888 r = NULL;
5889 if (!r)
5890 {
5891 char *save = input_line_pointer;
5892 char c;
5893 symbolS *symbolP;
5894
5895 input_line_pointer = reg_string;
5896 c = get_symbol_end ();
5897 symbolP = symbol_find (reg_string);
5898 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
5899 {
5900 const expressionS *e = symbol_get_value_expression (symbolP);
5901
5902 know (e->X_op == O_register);
4eed87de 5903 know (e->X_add_number >= 0
c3fe08fa 5904 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 5905 r = i386_regtab + e->X_add_number;
5906 *end_op = input_line_pointer;
5907 }
5908 *input_line_pointer = c;
5909 input_line_pointer = save;
5910 }
5911 return r;
5912}
5913
5914int
5915i386_parse_name (char *name, expressionS *e, char *nextcharP)
5916{
5917 const reg_entry *r;
5918 char *end = input_line_pointer;
5919
5920 *end = *nextcharP;
5921 r = parse_register (name, &input_line_pointer);
5922 if (r && end <= input_line_pointer)
5923 {
5924 *nextcharP = *input_line_pointer;
5925 *input_line_pointer = 0;
5926 e->X_op = O_register;
5927 e->X_add_number = r - i386_regtab;
5928 return 1;
5929 }
5930 input_line_pointer = end;
5931 *end = 0;
5932 return 0;
5933}
5934
5935void
5936md_operand (expressionS *e)
5937{
5938 if (*input_line_pointer == REGISTER_PREFIX)
5939 {
5940 char *end;
5941 const reg_entry *r = parse_real_register (input_line_pointer, &end);
5942
5943 if (r)
5944 {
5945 e->X_op = O_register;
5946 e->X_add_number = r - i386_regtab;
5947 input_line_pointer = end;
5948 }
5949 }
5950}
5951
252b5132 5952\f
4cc782b5 5953#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 5954const char *md_shortopts = "kVQ:sqn";
252b5132 5955#else
12b55ccc 5956const char *md_shortopts = "qn";
252b5132 5957#endif
6e0b89ee 5958
3e73aa7c 5959#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 5960#define OPTION_64 (OPTION_MD_BASE + 1)
5961#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 5962#define OPTION_MARCH (OPTION_MD_BASE + 3)
5963#define OPTION_MTUNE (OPTION_MD_BASE + 4)
b3b91714 5964
99ad8390
NC		 5965struct option md_longopts[] =
5966{
3e73aa7c 5967 {"32", no_argument, NULL, OPTION_32},
99ad8390 5968#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c 5969 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 5970#endif
b3b91714 5971 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 5972 {"march", required_argument, NULL, OPTION_MARCH},
5973 {"mtune", required_argument, NULL, OPTION_MTUNE},
252b5132
RH		 5974 {NULL, no_argument, NULL, 0}
5975};
5976size_t md_longopts_size = sizeof (md_longopts);
5977
5978int
9103f4f4 5979md_parse_option (int c, char *arg)
252b5132 5980{
9103f4f4
L		 5981 unsigned int i;
5982
252b5132
RH		 5983 switch (c)
5984 {
12b55ccc
L		 5985 case 'n':
5986 optimize_align_code = 0;
5987 break;
5988
a38cf1db
AM		 5989 case 'q':
5990 quiet_warnings = 1;
252b5132
RH		 5991 break;
5992
5993#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 5994 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5995 should be emitted or not. FIXME: Not implemented. */
5996 case 'Q':
252b5132
RH		 5997 break;
5998
5999 /* -V: SVR4 argument to print version ID. */
6000 case 'V':
6001 print_version_id ();
6002 break;
6003
a38cf1db
AM		 6004 /* -k: Ignore for FreeBSD compatibility. */
6005 case 'k':
252b5132 6006 break;
4cc782b5
ILT		 6007
6008 case 's':
6009 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 6010 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 6011 break;
99ad8390
NC		 6012#endif
6013#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c
JH		 6014 case OPTION_64:
6015 {
6016 const char **list, **l;
6017
3e73aa7c
JH		 6018 list = bfd_target_list ();
6019 for (l = list; *l != NULL; l++)
8620418b 6020 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 6021 || strcmp (*l, "coff-x86-64") == 0
6022 || strcmp (*l, "pe-x86-64") == 0
6023 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 6024 {
6025 default_arch = "x86_64";
6026 break;
6027 }
3e73aa7c 6028 if (*l == NULL)
6e0b89ee 6029 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 6030 free (list);
6031 }
6032 break;
6033#endif
252b5132 6034
6e0b89ee
AM		 6035 case OPTION_32:
6036 default_arch = "i386";
6037 break;
6038
b3b91714
AM		 6039 case OPTION_DIVIDE:
6040#ifdef SVR4_COMMENT_CHARS
6041 {
6042 char *n, *t;
6043 const char *s;
6044
6045 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
6046 t = n;
6047 for (s = i386_comment_chars; *s != '\0'; s++)
6048 if (*s != '/')
6049 *t++ = *s;
6050 *t = '\0';
6051 i386_comment_chars = n;
6052 }
6053#endif
6054 break;
6055
9103f4f4
L		 6056 case OPTION_MARCH:
6057 if (*arg == '.')
6058 as_fatal (_("Invalid -march= option: `%s'"), arg);
6059 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
6060 {
6061 if (strcmp (arg, cpu_arch [i].name) == 0)
6062 {
ccc9c027 6063 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 6064 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 6065 if (!cpu_arch_tune_set)
6066 {
6067 cpu_arch_tune = cpu_arch_isa;
6068 cpu_arch_tune_flags = cpu_arch_isa_flags;
6069 }
9103f4f4
L		 6070 break;
6071 }
6072 }
6073 if (i >= ARRAY_SIZE (cpu_arch))
6074 as_fatal (_("Invalid -march= option: `%s'"), arg);
6075 break;
6076
6077 case OPTION_MTUNE:
6078 if (*arg == '.')
6079 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
6080 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
6081 {
6082 if (strcmp (arg, cpu_arch [i].name) == 0)
6083 {
ccc9c027 6084 cpu_arch_tune_set = 1;
9103f4f4
L		 6085 cpu_arch_tune = cpu_arch [i].type;
6086 cpu_arch_tune_flags = cpu_arch[i].flags;
6087 break;
6088 }
6089 }
6090 if (i >= ARRAY_SIZE (cpu_arch))
6091 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
6092 break;
6093
252b5132
RH		 6094 default:
6095 return 0;
6096 }
6097 return 1;
6098}
6099
6100void
6101md_show_usage (stream)
6102 FILE *stream;
6103{
4cc782b5
ILT		 6104#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6105 fprintf (stream, _("\
a38cf1db
AM		 6106 -Q ignored\n\
6107 -V print assembler version number\n\
b3b91714
AM		 6108 -k ignored\n"));
6109#endif
6110 fprintf (stream, _("\
12b55ccc 6111 -n Do not optimize code alignment\n\
b3b91714
AM		 6112 -q quieten some warnings\n"));
6113#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6114 fprintf (stream, _("\
a38cf1db 6115 -s ignored\n"));
b3b91714 6116#endif
751d281c
L		 6117#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
6118 fprintf (stream, _("\
6119 --32/--64 generate 32bit/64bit code\n"));
6120#endif
b3b91714
AM		 6121#ifdef SVR4_COMMENT_CHARS
6122 fprintf (stream, _("\
6123 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 6124#else
6125 fprintf (stream, _("\
b3b91714 6126 --divide ignored\n"));
4cc782b5 6127#endif
9103f4f4
L		 6128 fprintf (stream, _("\
6129 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
6130 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
4eed87de 6131 core, core2, k6, athlon, k8, generic32, generic64\n"));
9103f4f4 6132
252b5132
RH		 6133}
6134
3e73aa7c 6135#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
872ce6ff 6136 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
252b5132
RH		 6137
6138/* Pick the target format to use. */
6139
47926f60 6140const char *
e3bb37b5 6141i386_target_format (void)
252b5132 6142{
3e73aa7c 6143 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 6144 {
6145 set_code_flag (CODE_64BIT);
6146 if (cpu_arch_isa_flags == 0)
d32cad65 6147 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386|Cpu486
9103f4f4
L		 6148 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
6149 |CpuSSE|CpuSSE2;
ccc9c027 6150 if (cpu_arch_tune_flags == 0)
d32cad65 6151 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386|Cpu486
ccc9c027
L		 6152 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
6153 |CpuSSE|CpuSSE2;
9103f4f4 6154 }
3e73aa7c 6155 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 6156 {
6157 set_code_flag (CODE_32BIT);
6158 if (cpu_arch_isa_flags == 0)
d32cad65 6159 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386;
ccc9c027 6160 if (cpu_arch_tune_flags == 0)
d32cad65 6161 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386;
9103f4f4 6162 }
3e73aa7c
JH		 6163 else
6164 as_fatal (_("Unknown architecture"));
252b5132
RH		 6165 switch (OUTPUT_FLAVOR)
6166 {
872ce6ff
L		 6167#ifdef TE_PEP
6168 case bfd_target_coff_flavour:
6169 return flag_code == CODE_64BIT ? COFF_TARGET_FORMAT : "coff-i386";
6170 break;
6171#endif
4c63da97
AM		 6172#ifdef OBJ_MAYBE_AOUT
6173 case bfd_target_aout_flavour:
47926f60 6174 return AOUT_TARGET_FORMAT;
4c63da97
AM		 6175#endif
6176#ifdef OBJ_MAYBE_COFF
252b5132
RH		 6177 case bfd_target_coff_flavour:
6178 return "coff-i386";
4c63da97 6179#endif
3e73aa7c 6180#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 6181 case bfd_target_elf_flavour:
3e73aa7c 6182 {
e5cb08ac 6183 if (flag_code == CODE_64BIT)
4fa24527
JB		 6184 {
6185 object_64bit = 1;
6186 use_rela_relocations = 1;
6187 }
9d7cbccd 6188 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
3e73aa7c 6189 }
4c63da97 6190#endif
252b5132
RH		 6191 default:
6192 abort ();
6193 return NULL;
6194 }
6195}
6196
47926f60 6197#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 6198
6199#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 6200void
6201i386_elf_emit_arch_note (void)
a847613f 6202{
718ddfc0 6203 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 6204 {
6205 char *p;
6206 asection *seg = now_seg;
6207 subsegT subseg = now_subseg;
6208 Elf_Internal_Note i_note;
6209 Elf_External_Note e_note;
6210 asection *note_secp;
6211 int len;
6212
6213 /* Create the .note section. */
6214 note_secp = subseg_new (".note", 0);
6215 bfd_set_section_flags (stdoutput,
6216 note_secp,
6217 SEC_HAS_CONTENTS | SEC_READONLY);
6218
6219 /* Process the arch string. */
6220 len = strlen (cpu_arch_name);
6221
6222 i_note.namesz = len + 1;
6223 i_note.descsz = 0;
6224 i_note.type = NT_ARCH;
6225 p = frag_more (sizeof (e_note.namesz));
6226 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
6227 p = frag_more (sizeof (e_note.descsz));
6228 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
6229 p = frag_more (sizeof (e_note.type));
6230 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
6231 p = frag_more (len + 1);
6232 strcpy (p, cpu_arch_name);
6233
6234 frag_align (2, 0, 0);
6235
6236 subseg_set (seg, subseg);
6237 }
6238}
6239#endif
252b5132 6240\f
252b5132
RH		 6241symbolS *
6242md_undefined_symbol (name)
6243 char *name;
6244{
18dc2407
ILT		 6245 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
6246 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
6247 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
6248 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 6249 {
6250 if (!GOT_symbol)
6251 {
6252 if (symbol_find (name))
6253 as_bad (_("GOT already in symbol table"));
6254 GOT_symbol = symbol_new (name, undefined_section,
6255 (valueT) 0, &zero_address_frag);
6256 };
6257 return GOT_symbol;
6258 }
252b5132
RH		 6259 return 0;
6260}
6261
6262/* Round up a section size to the appropriate boundary. */
47926f60 6263
252b5132
RH		 6264valueT
6265md_section_align (segment, size)
ab9da554 6266 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 6267 valueT size;
6268{
4c63da97
AM		 6269#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6270 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
6271 {
6272 /* For a.out, force the section size to be aligned. If we don't do
6273 this, BFD will align it for us, but it will not write out the
6274 final bytes of the section. This may be a bug in BFD, but it is
6275 easier to fix it here since that is how the other a.out targets
6276 work. */
6277 int align;
6278
6279 align = bfd_get_section_alignment (stdoutput, segment);
6280 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
6281 }
252b5132
RH		 6282#endif
6283
6284 return size;
6285}
6286
6287/* On the i386, PC-relative offsets are relative to the start of the
6288 next instruction. That is, the address of the offset, plus its
6289 size, since the offset is always the last part of the insn. */
6290
6291long
e3bb37b5 6292md_pcrel_from (fixS *fixP)
252b5132
RH		 6293{
6294 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
6295}
6296
6297#ifndef I386COFF
6298
6299static void
e3bb37b5 6300s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 6301{
29b0f896 6302 int temp;
252b5132 6303
8a75718c
JB		 6304#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6305 if (IS_ELF)
6306 obj_elf_section_change_hook ();
6307#endif
252b5132
RH		 6308 temp = get_absolute_expression ();
6309 subseg_set (bss_section, (subsegT) temp);
6310 demand_empty_rest_of_line ();
6311}
6312
6313#endif
6314
252b5132 6315void
e3bb37b5 6316i386_validate_fix (fixS *fixp)
252b5132
RH		 6317{
6318 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
6319 {
23df1078
JH		 6320 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
6321 {
4fa24527 6322 if (!object_64bit)
23df1078
JH		 6323 abort ();
6324 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
6325 }
6326 else
6327 {
4fa24527 6328 if (!object_64bit)
d6ab8113
JB		 6329 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
6330 else
6331 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 6332 }
252b5132
RH		 6333 fixp->fx_subsy = 0;
6334 }
6335}
6336
252b5132
RH		 6337arelent *
6338tc_gen_reloc (section, fixp)
ab9da554 6339 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 6340 fixS *fixp;
6341{
6342 arelent *rel;
6343 bfd_reloc_code_real_type code;
6344
6345 switch (fixp->fx_r_type)
6346 {
3e73aa7c
JH		 6347 case BFD_RELOC_X86_64_PLT32:
6348 case BFD_RELOC_X86_64_GOT32:
6349 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 6350 case BFD_RELOC_386_PLT32:
6351 case BFD_RELOC_386_GOT32:
6352 case BFD_RELOC_386_GOTOFF:
6353 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 6354 case BFD_RELOC_386_TLS_GD:
6355 case BFD_RELOC_386_TLS_LDM:
6356 case BFD_RELOC_386_TLS_LDO_32:
6357 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 6358 case BFD_RELOC_386_TLS_IE:
6359 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 6360 case BFD_RELOC_386_TLS_LE_32:
6361 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 6362 case BFD_RELOC_386_TLS_GOTDESC:
6363 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 6364 case BFD_RELOC_X86_64_TLSGD:
6365 case BFD_RELOC_X86_64_TLSLD:
6366 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 6367 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 6368 case BFD_RELOC_X86_64_GOTTPOFF:
6369 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 6370 case BFD_RELOC_X86_64_TPOFF64:
6371 case BFD_RELOC_X86_64_GOTOFF64:
6372 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 6373 case BFD_RELOC_X86_64_GOT64:
6374 case BFD_RELOC_X86_64_GOTPCREL64:
6375 case BFD_RELOC_X86_64_GOTPC64:
6376 case BFD_RELOC_X86_64_GOTPLT64:
6377 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 6378 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6379 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 6380 case BFD_RELOC_RVA:
6381 case BFD_RELOC_VTABLE_ENTRY:
6382 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 6383#ifdef TE_PE
6384 case BFD_RELOC_32_SECREL:
6385#endif
252b5132
RH		 6386 code = fixp->fx_r_type;
6387 break;
dbbaec26
L		 6388 case BFD_RELOC_X86_64_32S:
6389 if (!fixp->fx_pcrel)
6390 {
6391 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
6392 code = fixp->fx_r_type;
6393 break;
6394 }
252b5132 6395 default:
93382f6d 6396 if (fixp->fx_pcrel)
252b5132 6397 {
93382f6d
AM		 6398 switch (fixp->fx_size)
6399 {
6400 default:
b091f402
AM		 6401 as_bad_where (fixp->fx_file, fixp->fx_line,
6402 _("can not do %d byte pc-relative relocation"),
6403 fixp->fx_size);
93382f6d
AM		 6404 code = BFD_RELOC_32_PCREL;
6405 break;
6406 case 1: code = BFD_RELOC_8_PCREL; break;
6407 case 2: code = BFD_RELOC_16_PCREL; break;
6408 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 6409#ifdef BFD64
6410 case 8: code = BFD_RELOC_64_PCREL; break;
6411#endif
93382f6d
AM		 6412 }
6413 }
6414 else
6415 {
6416 switch (fixp->fx_size)
6417 {
6418 default:
b091f402
AM		 6419 as_bad_where (fixp->fx_file, fixp->fx_line,
6420 _("can not do %d byte relocation"),
6421 fixp->fx_size);
93382f6d
AM		 6422 code = BFD_RELOC_32;
6423 break;
6424 case 1: code = BFD_RELOC_8; break;
6425 case 2: code = BFD_RELOC_16; break;
6426 case 4: code = BFD_RELOC_32; break;
937149dd 6427#ifdef BFD64
3e73aa7c 6428 case 8: code = BFD_RELOC_64; break;
937149dd 6429#endif
93382f6d 6430 }
252b5132
RH		 6431 }
6432 break;
6433 }
252b5132 6434
d182319b
JB		 6435 if ((code == BFD_RELOC_32
6436 || code == BFD_RELOC_32_PCREL
6437 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 6438 && GOT_symbol
6439 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 6440 {
4fa24527 6441 if (!object_64bit)
d6ab8113
JB		 6442 code = BFD_RELOC_386_GOTPC;
6443 else
6444 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 6445 }
7b81dfbb
AJ		 6446 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
6447 && GOT_symbol
6448 && fixp->fx_addsy == GOT_symbol)
6449 {
6450 code = BFD_RELOC_X86_64_GOTPC64;
6451 }
252b5132
RH		 6452
6453 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 6454 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
6455 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 6456
6457 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 6458
3e73aa7c
JH		 6459 if (!use_rela_relocations)
6460 {
6461 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
6462 vtable entry to be used in the relocation's section offset. */
6463 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
6464 rel->address = fixp->fx_offset;
252b5132 6465
c6682705 6466 rel->addend = 0;
3e73aa7c
JH		 6467 }
6468 /* Use the rela in 64bit mode. */
252b5132 6469 else
3e73aa7c 6470 {
062cd5e7
AS		 6471 if (!fixp->fx_pcrel)
6472 rel->addend = fixp->fx_offset;
6473 else
6474 switch (code)
6475 {
6476 case BFD_RELOC_X86_64_PLT32:
6477 case BFD_RELOC_X86_64_GOT32:
6478 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 6479 case BFD_RELOC_X86_64_TLSGD:
6480 case BFD_RELOC_X86_64_TLSLD:
6481 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 6482 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6483 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 6484 rel->addend = fixp->fx_offset - fixp->fx_size;
6485 break;
6486 default:
6487 rel->addend = (section->vma
6488 - fixp->fx_size
6489 + fixp->fx_addnumber
6490 + md_pcrel_from (fixp));
6491 break;
6492 }
3e73aa7c
JH		 6493 }
6494
252b5132
RH		 6495 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
6496 if (rel->howto == NULL)
6497 {
6498 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 6499 _("cannot represent relocation type %s"),
252b5132
RH		 6500 bfd_get_reloc_code_name (code));
6501 /* Set howto to a garbage value so that we can keep going. */
6502 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
6503 assert (rel->howto != NULL);
6504 }
6505
6506 return rel;
6507}
6508
64a0c779
DN		 6509\f
6510/* Parse operands using Intel syntax. This implements a recursive descent
6511 parser based on the BNF grammar published in Appendix B of the MASM 6.1
6512 Programmer's Guide.
6513
6514 FIXME: We do not recognize the full operand grammar defined in the MASM
6515 documentation. In particular, all the structure/union and
6516 high-level macro operands are missing.
6517
6518 Uppercase words are terminals, lower case words are non-terminals.
6519 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
6520 bars '|' denote choices. Most grammar productions are implemented in
6521 functions called 'intel_<production>'.
6522
6523 Initial production is 'expr'.
6524
9306ca4a 6525 addOp + | -
64a0c779
DN		 6526
6527 alpha [a-zA-Z]
6528
9306ca4a
JB		 6529 binOp & | AND | \| | OR | ^ | XOR
6530
64a0c779
DN		 6531 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
6532
6533 constant digits [[ radixOverride ]]
6534
9306ca4a 6535 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
64a0c779
DN		 6536
6537 digits decdigit
b77a7acd
AJ		 6538 | digits decdigit
6539 | digits hexdigit
64a0c779
DN		 6540
6541 decdigit [0-9]
6542
9306ca4a
JB		 6543 e04 e04 addOp e05
6544 | e05
6545
6546 e05 e05 binOp e06
b77a7acd 6547 | e06
64a0c779
DN		 6548
6549 e06 e06 mulOp e09
b77a7acd 6550 | e09
64a0c779
DN		 6551
6552 e09 OFFSET e10
a724f0f4
JB		 6553 | SHORT e10
6554 | + e10
6555 | - e10
9306ca4a
JB		 6556 | ~ e10
6557 | NOT e10
64a0c779
DN		 6558 | e09 PTR e10
6559 | e09 : e10
6560 | e10
6561
6562 e10 e10 [ expr ]
b77a7acd 6563 | e11
64a0c779
DN		 6564
6565 e11 ( expr )
b77a7acd 6566 | [ expr ]
64a0c779
DN		 6567 | constant
6568 | dataType
6569 | id
6570 | $
6571 | register
6572
a724f0f4 6573 => expr expr cmpOp e04
9306ca4a 6574 | e04
64a0c779
DN		 6575
6576 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 6577 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 6578
6579 hexdigit a | b | c | d | e | f
b77a7acd 6580 | A | B | C | D | E | F
64a0c779
DN		 6581
6582 id alpha
b77a7acd 6583 | id alpha
64a0c779
DN		 6584 | id decdigit
6585
9306ca4a 6586 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 6587
6588 quote " | '
6589
6590 register specialRegister
b77a7acd 6591 | gpRegister
64a0c779
DN		 6592 | byteRegister
6593
6594 segmentRegister CS | DS | ES | FS | GS | SS
6595
9306ca4a 6596 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 6597 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 6598 | TR3 | TR4 | TR5 | TR6 | TR7
6599
64a0c779
DN		 6600 We simplify the grammar in obvious places (e.g., register parsing is
6601 done by calling parse_register) and eliminate immediate left recursion
6602 to implement a recursive-descent parser.
6603
a724f0f4
JB		 6604 expr e04 expr'
6605
6606 expr' cmpOp e04 expr'
6607 | Empty
9306ca4a
JB		 6608
6609 e04 e05 e04'
6610
6611 e04' addOp e05 e04'
6612 | Empty
64a0c779
DN		 6613
6614 e05 e06 e05'
6615
9306ca4a 6616 e05' binOp e06 e05'
b77a7acd 6617 | Empty
64a0c779
DN		 6618
6619 e06 e09 e06'
6620
6621 e06' mulOp e09 e06'
b77a7acd 6622 | Empty
64a0c779
DN		 6623
6624 e09 OFFSET e10 e09'
a724f0f4
JB		 6625 | SHORT e10'
6626 | + e10'
6627 | - e10'
6628 | ~ e10'
6629 | NOT e10'
b77a7acd 6630 | e10 e09'
64a0c779
DN		 6631
6632 e09' PTR e10 e09'
b77a7acd 6633 | : e10 e09'
64a0c779
DN		 6634 | Empty
6635
6636 e10 e11 e10'
6637
6638 e10' [ expr ] e10'
b77a7acd 6639 | Empty
64a0c779
DN		 6640
6641 e11 ( expr )
b77a7acd 6642 | [ expr ]
64a0c779
DN		 6643 | BYTE
6644 | WORD
6645 | DWORD
9306ca4a 6646 | FWORD
64a0c779 6647 | QWORD
9306ca4a
JB		 6648 | TBYTE
6649 | OWORD
6650 | XMMWORD
64a0c779
DN		 6651 | .
6652 | $
6653 | register
6654 | id
6655 | constant */
6656
6657/* Parsing structure for the intel syntax parser. Used to implement the
6658 semantic actions for the operand grammar. */
6659struct intel_parser_s
6660 {
6661 char *op_string; /* The string being parsed. */
6662 int got_a_float; /* Whether the operand is a float. */
4a1805b1 6663 int op_modifier; /* Operand modifier. */
64a0c779 6664 int is_mem; /* 1 if operand is memory reference. */
4eed87de
AM		 6665 int in_offset; /* >=1 if parsing operand of offset. */
6666 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 6667 const reg_entry *reg; /* Last register reference found. */
6668 char *disp; /* Displacement string being built. */
a724f0f4 6669 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 6670 };
6671
6672static struct intel_parser_s intel_parser;
6673
6674/* Token structure for parsing intel syntax. */
6675struct intel_token
6676 {
6677 int code; /* Token code. */
6678 const reg_entry *reg; /* Register entry for register tokens. */
6679 char *str; /* String representation. */
6680 };
6681
6682static struct intel_token cur_token, prev_token;
6683
50705ef4
AM		 6684/* Token codes for the intel parser. Since T_SHORT is already used
6685 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 6686#define T_NIL -1
6687#define T_CONST 1
6688#define T_REG 2
6689#define T_BYTE 3
6690#define T_WORD 4
9306ca4a
JB		 6691#define T_DWORD 5
6692#define T_FWORD 6
6693#define T_QWORD 7
6694#define T_TBYTE 8
6695#define T_XMMWORD 9
50705ef4 6696#undef T_SHORT
9306ca4a
JB		 6697#define T_SHORT 10
6698#define T_OFFSET 11
6699#define T_PTR 12
6700#define T_ID 13
6701#define T_SHL 14
6702#define T_SHR 15
64a0c779
DN		 6703
6704/* Prototypes for intel parser functions. */
e3bb37b5
L		 6705static int intel_match_token (int);
6706static void intel_putback_token (void);
6707static void intel_get_token (void);
6708static int intel_expr (void);
6709static int intel_e04 (void);
6710static int intel_e05 (void);
6711static int intel_e06 (void);
6712static int intel_e09 (void);
6713static int intel_e10 (void);
6714static int intel_e11 (void);
64a0c779 6715
64a0c779 6716static int
e3bb37b5 6717i386_intel_operand (char *operand_string, int got_a_float)
64a0c779
DN		 6718{
6719 int ret;
6720 char *p;
6721
a724f0f4
JB		 6722 p = intel_parser.op_string = xstrdup (operand_string);
6723 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
6724
6725 for (;;)
64a0c779 6726 {
a724f0f4
JB		 6727 /* Initialize token holders. */
6728 cur_token.code = prev_token.code = T_NIL;
6729 cur_token.reg = prev_token.reg = NULL;
6730 cur_token.str = prev_token.str = NULL;
6731
6732 /* Initialize parser structure. */
6733 intel_parser.got_a_float = got_a_float;
6734 intel_parser.op_modifier = 0;
6735 intel_parser.is_mem = 0;
6736 intel_parser.in_offset = 0;
6737 intel_parser.in_bracket = 0;
6738 intel_parser.reg = NULL;
6739 intel_parser.disp[0] = '\0';
6740 intel_parser.next_operand = NULL;
6741
6742 /* Read the first token and start the parser. */
6743 intel_get_token ();
6744 ret = intel_expr ();
6745
6746 if (!ret)
6747 break;
6748
9306ca4a
JB		 6749 if (cur_token.code != T_NIL)
6750 {
6751 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
6752 current_templates->start->name, cur_token.str);
6753 ret = 0;
6754 }
64a0c779
DN		 6755 /* If we found a memory reference, hand it over to i386_displacement
6756 to fill in the rest of the operand fields. */
9306ca4a 6757 else if (intel_parser.is_mem)
64a0c779
DN		 6758 {
6759 if ((i.mem_operands == 1
6760 && (current_templates->start->opcode_modifier & IsString) == 0)
6761 || i.mem_operands == 2)
6762 {
6763 as_bad (_("too many memory references for '%s'"),
6764 current_templates->start->name);
6765 ret = 0;
6766 }
6767 else
6768 {
6769 char *s = intel_parser.disp;
6770 i.mem_operands++;
6771
a724f0f4
JB		 6772 if (!quiet_warnings && intel_parser.is_mem < 0)
6773 /* See the comments in intel_bracket_expr. */
6774 as_warn (_("Treating `%s' as memory reference"), operand_string);
6775
64a0c779
DN		 6776 /* Add the displacement expression. */
6777 if (*s != '\0')
a4622f40
AM		 6778 ret = i386_displacement (s, s + strlen (s));
6779 if (ret)
a724f0f4
JB		 6780 {
6781 /* Swap base and index in 16-bit memory operands like
6782 [si+bx]. Since i386_index_check is also used in AT&T
6783 mode we have to do that here. */
6784 if (i.base_reg
6785 && i.index_reg
6786 && (i.base_reg->reg_type & Reg16)
6787 && (i.index_reg->reg_type & Reg16)
6788 && i.base_reg->reg_num >= 6
6789 && i.index_reg->reg_num < 6)
6790 {
6791 const reg_entry *base = i.index_reg;
6792
6793 i.index_reg = i.base_reg;
6794 i.base_reg = base;
6795 }
6796 ret = i386_index_check (operand_string);
6797 }
64a0c779
DN		 6798 }
6799 }
6800
6801 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 6802 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779
DN		 6803 || intel_parser.reg == NULL)
6804 ret = i386_immediate (intel_parser.disp);
a724f0f4
JB		 6805
6806 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
4eed87de 6807 ret = 0;
a724f0f4
JB		 6808 if (!ret || !intel_parser.next_operand)
6809 break;
6810 intel_parser.op_string = intel_parser.next_operand;
6811 this_operand = i.operands++;
64a0c779
DN		 6812 }
6813
6814 free (p);
6815 free (intel_parser.disp);
6816
6817 return ret;
6818}
6819
a724f0f4
JB		 6820#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
6821
6822/* expr e04 expr'
6823
6824 expr' cmpOp e04 expr'
6825 | Empty */
64a0c779 6826static int
e3bb37b5 6827intel_expr (void)
64a0c779 6828{
a724f0f4
JB		 6829 /* XXX Implement the comparison operators. */
6830 return intel_e04 ();
9306ca4a
JB		 6831}
6832
a724f0f4 6833/* e04 e05 e04'
9306ca4a 6834
a724f0f4 6835 e04' addOp e05 e04'
9306ca4a
JB		 6836 | Empty */
6837static int
e3bb37b5 6838intel_e04 (void)
9306ca4a 6839{
a724f0f4 6840 int nregs = -1;
9306ca4a 6841
a724f0f4 6842 for (;;)
9306ca4a 6843 {
a724f0f4
JB		 6844 if (!intel_e05())
6845 return 0;
9306ca4a 6846
a724f0f4
JB		 6847 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6848 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 6849
a724f0f4
JB		 6850 if (cur_token.code == '+')
6851 nregs = -1;
6852 else if (cur_token.code == '-')
6853 nregs = NUM_ADDRESS_REGS;
6854 else
6855 return 1;
64a0c779 6856
a724f0f4
JB		 6857 strcat (intel_parser.disp, cur_token.str);
6858 intel_match_token (cur_token.code);
6859 }
64a0c779
DN		 6860}
6861
64a0c779
DN		 6862/* e05 e06 e05'
6863
9306ca4a 6864 e05' binOp e06 e05'
64a0c779
DN		 6865 | Empty */
6866static int
e3bb37b5 6867intel_e05 (void)
64a0c779 6868{
a724f0f4 6869 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6870
a724f0f4 6871 for (;;)
64a0c779 6872 {
a724f0f4
JB		 6873 if (!intel_e06())
6874 return 0;
6875
4eed87de
AM		 6876 if (cur_token.code == '&'
6877 || cur_token.code == '|'
6878 || cur_token.code == '^')
a724f0f4
JB		 6879 {
6880 char str[2];
6881
6882 str[0] = cur_token.code;
6883 str[1] = 0;
6884 strcat (intel_parser.disp, str);
6885 }
6886 else
6887 break;
9306ca4a 6888
64a0c779
DN		 6889 intel_match_token (cur_token.code);
6890
a724f0f4
JB		 6891 if (nregs < 0)
6892 nregs = ~nregs;
64a0c779 6893 }
a724f0f4
JB		 6894 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6895 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
6896 return 1;
4a1805b1 6897}
64a0c779
DN		 6898
6899/* e06 e09 e06'
6900
6901 e06' mulOp e09 e06'
b77a7acd 6902 | Empty */
64a0c779 6903static int
e3bb37b5 6904intel_e06 (void)
64a0c779 6905{
a724f0f4 6906 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6907
a724f0f4 6908 for (;;)
64a0c779 6909 {
a724f0f4
JB		 6910 if (!intel_e09())
6911 return 0;
9306ca4a 6912
4eed87de
AM		 6913 if (cur_token.code == '*'
6914 || cur_token.code == '/'
6915 || cur_token.code == '%')
a724f0f4
JB		 6916 {
6917 char str[2];
9306ca4a 6918
a724f0f4
JB		 6919 str[0] = cur_token.code;
6920 str[1] = 0;
6921 strcat (intel_parser.disp, str);
6922 }
6923 else if (cur_token.code == T_SHL)
6924 strcat (intel_parser.disp, "<<");
6925 else if (cur_token.code == T_SHR)
6926 strcat (intel_parser.disp, ">>");
6927 else
6928 break;
9306ca4a 6929
64e74474 6930 intel_match_token (cur_token.code);
64a0c779 6931
a724f0f4
JB		 6932 if (nregs < 0)
6933 nregs = ~nregs;
64a0c779 6934 }
a724f0f4
JB		 6935 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6936 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
6937 return 1;
64a0c779
DN		 6938}
6939
a724f0f4
JB		 6940/* e09 OFFSET e09
6941 | SHORT e09
6942 | + e09
6943 | - e09
6944 | ~ e09
6945 | NOT e09
9306ca4a
JB		 6946 | e10 e09'
6947
64a0c779 6948 e09' PTR e10 e09'
b77a7acd 6949 | : e10 e09'
64a0c779
DN		 6950 | Empty */
6951static int
e3bb37b5 6952intel_e09 (void)
64a0c779 6953{
a724f0f4
JB		 6954 int nregs = ~NUM_ADDRESS_REGS;
6955 int in_offset = 0;
6956
6957 for (;;)
64a0c779 6958 {
a724f0f4
JB		 6959 /* Don't consume constants here. */
6960 if (cur_token.code == '+' || cur_token.code == '-')
6961 {
6962 /* Need to look one token ahead - if the next token
6963 is a constant, the current token is its sign. */
6964 int next_code;
6965
6966 intel_match_token (cur_token.code);
6967 next_code = cur_token.code;
6968 intel_putback_token ();
6969 if (next_code == T_CONST)
6970 break;
6971 }
6972
6973 /* e09 OFFSET e09 */
6974 if (cur_token.code == T_OFFSET)
6975 {
6976 if (!in_offset++)
6977 ++intel_parser.in_offset;
6978 }
6979
6980 /* e09 SHORT e09 */
6981 else if (cur_token.code == T_SHORT)
6982 intel_parser.op_modifier |= 1 << T_SHORT;
6983
6984 /* e09 + e09 */
6985 else if (cur_token.code == '+')
6986 strcat (intel_parser.disp, "+");
6987
6988 /* e09 - e09
6989 | ~ e09
6990 | NOT e09 */
6991 else if (cur_token.code == '-' || cur_token.code == '~')
6992 {
6993 char str[2];
64a0c779 6994
a724f0f4
JB		 6995 if (nregs < 0)
6996 nregs = ~nregs;
6997 str[0] = cur_token.code;
6998 str[1] = 0;
6999 strcat (intel_parser.disp, str);
7000 }
7001
7002 /* e09 e10 e09' */
7003 else
7004 break;
7005
7006 intel_match_token (cur_token.code);
64a0c779
DN		 7007 }
7008
a724f0f4 7009 for (;;)
9306ca4a 7010 {
a724f0f4
JB		 7011 if (!intel_e10 ())
7012 return 0;
9306ca4a 7013
a724f0f4
JB		 7014 /* e09' PTR e10 e09' */
7015 if (cur_token.code == T_PTR)
7016 {
7017 char suffix;
9306ca4a 7018
a724f0f4
JB		 7019 if (prev_token.code == T_BYTE)
7020 suffix = BYTE_MNEM_SUFFIX;
9306ca4a 7021
a724f0f4
JB		 7022 else if (prev_token.code == T_WORD)
7023 {
7024 if (current_templates->start->name[0] == 'l'
7025 && current_templates->start->name[2] == 's'
7026 && current_templates->start->name[3] == 0)
7027 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
7028 else if (intel_parser.got_a_float == 2) /* "fi..." */
7029 suffix = SHORT_MNEM_SUFFIX;
7030 else
7031 suffix = WORD_MNEM_SUFFIX;
7032 }
64a0c779 7033
a724f0f4
JB		 7034 else if (prev_token.code == T_DWORD)
7035 {
7036 if (current_templates->start->name[0] == 'l'
7037 && current_templates->start->name[2] == 's'
7038 && current_templates->start->name[3] == 0)
7039 suffix = WORD_MNEM_SUFFIX;
7040 else if (flag_code == CODE_16BIT
7041 && (current_templates->start->opcode_modifier
435acd52 7042 & (Jump | JumpDword)))
a724f0f4
JB		 7043 suffix = LONG_DOUBLE_MNEM_SUFFIX;
7044 else if (intel_parser.got_a_float == 1) /* "f..." */
7045 suffix = SHORT_MNEM_SUFFIX;
7046 else
7047 suffix = LONG_MNEM_SUFFIX;
7048 }
9306ca4a 7049
a724f0f4
JB		 7050 else if (prev_token.code == T_FWORD)
7051 {
7052 if (current_templates->start->name[0] == 'l'
7053 && current_templates->start->name[2] == 's'
7054 && current_templates->start->name[3] == 0)
7055 suffix = LONG_MNEM_SUFFIX;
7056 else if (!intel_parser.got_a_float)
7057 {
7058 if (flag_code == CODE_16BIT)
7059 add_prefix (DATA_PREFIX_OPCODE);
7060 suffix = LONG_DOUBLE_MNEM_SUFFIX;
7061 }
7062 else
7063 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
7064 }
64a0c779 7065
a724f0f4
JB		 7066 else if (prev_token.code == T_QWORD)
7067 {
7068 if (intel_parser.got_a_float == 1) /* "f..." */
7069 suffix = LONG_MNEM_SUFFIX;
7070 else
7071 suffix = QWORD_MNEM_SUFFIX;
7072 }
64a0c779 7073
a724f0f4
JB		 7074 else if (prev_token.code == T_TBYTE)
7075 {
7076 if (intel_parser.got_a_float == 1)
7077 suffix = LONG_DOUBLE_MNEM_SUFFIX;
7078 else
7079 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
7080 }
9306ca4a 7081
a724f0f4 7082 else if (prev_token.code == T_XMMWORD)
9306ca4a 7083 {
a724f0f4
JB		 7084 /* XXX ignored for now, but accepted since gcc uses it */
7085 suffix = 0;
9306ca4a 7086 }
64a0c779 7087
f16b83df 7088 else
a724f0f4
JB		 7089 {
7090 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
7091 return 0;
7092 }
7093
435acd52
JB		 7094 /* Operands for jump/call using 'ptr' notation denote absolute
7095 addresses. */
7096 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
7097 i.types[this_operand] |= JumpAbsolute;
7098
a724f0f4
JB		 7099 if (current_templates->start->base_opcode == 0x8d /* lea */)
7100 ;
7101 else if (!i.suffix)
7102 i.suffix = suffix;
7103 else if (i.suffix != suffix)
7104 {
7105 as_bad (_("Conflicting operand modifiers"));
7106 return 0;
7107 }
64a0c779 7108
9306ca4a
JB		 7109 }
7110
a724f0f4
JB		 7111 /* e09' : e10 e09' */
7112 else if (cur_token.code == ':')
9306ca4a 7113 {
a724f0f4
JB		 7114 if (prev_token.code != T_REG)
7115 {
7116 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
7117 segment/group identifier (which we don't have), using comma
7118 as the operand separator there is even less consistent, since
7119 there all branches only have a single operand. */
7120 if (this_operand != 0
7121 || intel_parser.in_offset
7122 || intel_parser.in_bracket
7123 || (!(current_templates->start->opcode_modifier
7124 & (Jump|JumpDword|JumpInterSegment))
7125 && !(current_templates->start->operand_types[0]
7126 & JumpAbsolute)))
7127 return intel_match_token (T_NIL);
7128 /* Remember the start of the 2nd operand and terminate 1st
7129 operand here.
7130 XXX This isn't right, yet (when SSSS:OOOO is right operand of
7131 another expression), but it gets at least the simplest case
7132 (a plain number or symbol on the left side) right. */
7133 intel_parser.next_operand = intel_parser.op_string;
7134 *--intel_parser.op_string = '\0';
7135 return intel_match_token (':');
7136 }
9306ca4a 7137 }
64a0c779 7138
a724f0f4 7139 /* e09' Empty */
64a0c779 7140 else
a724f0f4 7141 break;
64a0c779 7142
a724f0f4
JB		 7143 intel_match_token (cur_token.code);
7144
7145 }
7146
7147 if (in_offset)
7148 {
7149 --intel_parser.in_offset;
7150 if (nregs < 0)
7151 nregs = ~nregs;
7152 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 7153 {
a724f0f4 7154 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 7155 return 0;
7156 }
a724f0f4
JB		 7157 intel_parser.op_modifier |= 1 << T_OFFSET;
7158 }
9306ca4a 7159
a724f0f4
JB		 7160 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7161 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
7162 return 1;
7163}
64a0c779 7164
a724f0f4 7165static int
e3bb37b5 7166intel_bracket_expr (void)
a724f0f4
JB		 7167{
7168 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
7169 const char *start = intel_parser.op_string;
7170 int len;
7171
7172 if (i.op[this_operand].regs)
7173 return intel_match_token (T_NIL);
7174
7175 intel_match_token ('[');
7176
7177 /* Mark as a memory operand only if it's not already known to be an
7178 offset expression. If it's an offset expression, we need to keep
7179 the brace in. */
7180 if (!intel_parser.in_offset)
7181 {
7182 ++intel_parser.in_bracket;
435acd52
JB		 7183
7184 /* Operands for jump/call inside brackets denote absolute addresses. */
7185 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
7186 i.types[this_operand] |= JumpAbsolute;
7187
a724f0f4
JB		 7188 /* Unfortunately gas always diverged from MASM in a respect that can't
7189 be easily fixed without risking to break code sequences likely to be
7190 encountered (the testsuite even check for this): MASM doesn't consider
7191 an expression inside brackets unconditionally as a memory reference.
7192 When that is e.g. a constant, an offset expression, or the sum of the
7193 two, this is still taken as a constant load. gas, however, always
7194 treated these as memory references. As a compromise, we'll try to make
7195 offset expressions inside brackets work the MASM way (since that's
7196 less likely to be found in real world code), but make constants alone
7197 continue to work the traditional gas way. In either case, issue a
7198 warning. */
7199 intel_parser.op_modifier &= ~was_offset;
64a0c779 7200 }
a724f0f4 7201 else
64e74474 7202 strcat (intel_parser.disp, "[");
a724f0f4
JB		 7203
7204 /* Add a '+' to the displacement string if necessary. */
7205 if (*intel_parser.disp != '\0'
7206 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
7207 strcat (intel_parser.disp, "+");
64a0c779 7208
a724f0f4
JB		 7209 if (intel_expr ()
7210 && (len = intel_parser.op_string - start - 1,
7211 intel_match_token (']')))
64a0c779 7212 {
a724f0f4
JB		 7213 /* Preserve brackets when the operand is an offset expression. */
7214 if (intel_parser.in_offset)
7215 strcat (intel_parser.disp, "]");
7216 else
7217 {
7218 --intel_parser.in_bracket;
7219 if (i.base_reg || i.index_reg)
7220 intel_parser.is_mem = 1;
7221 if (!intel_parser.is_mem)
7222 {
7223 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
7224 /* Defer the warning until all of the operand was parsed. */
7225 intel_parser.is_mem = -1;
7226 else if (!quiet_warnings)
4eed87de
AM		 7227 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
7228 len, start, len, start);
a724f0f4
JB		 7229 }
7230 }
7231 intel_parser.op_modifier |= was_offset;
64a0c779 7232
a724f0f4 7233 return 1;
64a0c779 7234 }
a724f0f4 7235 return 0;
64a0c779
DN		 7236}
7237
7238/* e10 e11 e10'
7239
7240 e10' [ expr ] e10'
b77a7acd 7241 | Empty */
64a0c779 7242static int
e3bb37b5 7243intel_e10 (void)
64a0c779 7244{
a724f0f4
JB		 7245 if (!intel_e11 ())
7246 return 0;
64a0c779 7247
a724f0f4 7248 while (cur_token.code == '[')
64a0c779 7249 {
a724f0f4 7250 if (!intel_bracket_expr ())
21d6c4af 7251 return 0;
64a0c779
DN		 7252 }
7253
a724f0f4 7254 return 1;
64a0c779
DN		 7255}
7256
64a0c779 7257/* e11 ( expr )
b77a7acd 7258 | [ expr ]
64a0c779
DN		 7259 | BYTE
7260 | WORD
7261 | DWORD
9306ca4a 7262 | FWORD
64a0c779 7263 | QWORD
9306ca4a
JB		 7264 | TBYTE
7265 | OWORD
7266 | XMMWORD
4a1805b1 7267 | $
64a0c779
DN		 7268 | .
7269 | register
7270 | id
7271 | constant */
7272static int
e3bb37b5 7273intel_e11 (void)
64a0c779 7274{
a724f0f4 7275 switch (cur_token.code)
64a0c779 7276 {
a724f0f4
JB		 7277 /* e11 ( expr ) */
7278 case '(':
64a0c779
DN		 7279 intel_match_token ('(');
7280 strcat (intel_parser.disp, "(");
7281
7282 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 7283 {
7284 strcat (intel_parser.disp, ")");
7285 return 1;
7286 }
a724f0f4 7287 return 0;
4a1805b1 7288
a724f0f4
JB		 7289 /* e11 [ expr ] */
7290 case '[':
a724f0f4 7291 return intel_bracket_expr ();
64a0c779 7292
a724f0f4
JB		 7293 /* e11 $
7294 | . */
7295 case '.':
64a0c779
DN		 7296 strcat (intel_parser.disp, cur_token.str);
7297 intel_match_token (cur_token.code);
21d6c4af
DN		 7298
7299 /* Mark as a memory operand only if it's not already known to be an
7300 offset expression. */
a724f0f4 7301 if (!intel_parser.in_offset)
21d6c4af 7302 intel_parser.is_mem = 1;
64a0c779
DN		 7303
7304 return 1;
64a0c779 7305
a724f0f4
JB		 7306 /* e11 register */
7307 case T_REG:
7308 {
7309 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 7310
a724f0f4 7311 intel_match_token (T_REG);
64a0c779 7312
a724f0f4
JB		 7313 /* Check for segment change. */
7314 if (cur_token.code == ':')
7315 {
7316 if (!(reg->reg_type & (SReg2 | SReg3)))
7317 {
4eed87de
AM		 7318 as_bad (_("`%s' is not a valid segment register"),
7319 reg->reg_name);
a724f0f4
JB		 7320 return 0;
7321 }
7322 else if (i.seg[i.mem_operands])
7323 as_warn (_("Extra segment override ignored"));
7324 else
7325 {
7326 if (!intel_parser.in_offset)
7327 intel_parser.is_mem = 1;
7328 switch (reg->reg_num)
7329 {
7330 case 0:
7331 i.seg[i.mem_operands] = &es;
7332 break;
7333 case 1:
7334 i.seg[i.mem_operands] = &cs;
7335 break;
7336 case 2:
7337 i.seg[i.mem_operands] = &ss;
7338 break;
7339 case 3:
7340 i.seg[i.mem_operands] = &ds;
7341 break;
7342 case 4:
7343 i.seg[i.mem_operands] = &fs;
7344 break;
7345 case 5:
7346 i.seg[i.mem_operands] = &gs;
7347 break;
7348 }
7349 }
7350 }
64a0c779 7351
a724f0f4
JB		 7352 /* Not a segment register. Check for register scaling. */
7353 else if (cur_token.code == '*')
7354 {
7355 if (!intel_parser.in_bracket)
7356 {
7357 as_bad (_("Register scaling only allowed in memory operands"));
7358 return 0;
7359 }
64a0c779 7360
a724f0f4
JB		 7361 if (reg->reg_type & Reg16) /* Disallow things like [si*1]. */
7362 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
7363 else if (i.index_reg)
7364 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 7365
a724f0f4
JB		 7366 /* What follows must be a valid scale. */
7367 intel_match_token ('*');
7368 i.index_reg = reg;
7369 i.types[this_operand] |= BaseIndex;
64a0c779 7370
a724f0f4
JB		 7371 /* Set the scale after setting the register (otherwise,
7372 i386_scale will complain) */
7373 if (cur_token.code == '+' || cur_token.code == '-')
7374 {
7375 char *str, sign = cur_token.code;
7376 intel_match_token (cur_token.code);
7377 if (cur_token.code != T_CONST)
7378 {
7379 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7380 cur_token.str);
7381 return 0;
7382 }
7383 str = (char *) xmalloc (strlen (cur_token.str) + 2);
7384 strcpy (str + 1, cur_token.str);
7385 *str = sign;
7386 if (!i386_scale (str))
7387 return 0;
7388 free (str);
7389 }
7390 else if (!i386_scale (cur_token.str))
64a0c779 7391 return 0;
a724f0f4
JB		 7392 intel_match_token (cur_token.code);
7393 }
64a0c779 7394
a724f0f4
JB		 7395 /* No scaling. If this is a memory operand, the register is either a
7396 base register (first occurrence) or an index register (second
7397 occurrence). */
7b0441f6 7398 else if (intel_parser.in_bracket)
a724f0f4 7399 {
64a0c779 7400
a724f0f4
JB		 7401 if (!i.base_reg)
7402 i.base_reg = reg;
7403 else if (!i.index_reg)
7404 i.index_reg = reg;
7405 else
7406 {
7407 as_bad (_("Too many register references in memory operand"));
7408 return 0;
7409 }
64a0c779 7410
a724f0f4
JB		 7411 i.types[this_operand] |= BaseIndex;
7412 }
4a1805b1 7413
4d1bb795
JB		 7414 /* It's neither base nor index. */
7415 else if (!intel_parser.in_offset && !intel_parser.is_mem)
a724f0f4
JB		 7416 {
7417 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
7418 i.op[this_operand].regs = reg;
7419 i.reg_operands++;
7420 }
7421 else
7422 {
7423 as_bad (_("Invalid use of register"));
7424 return 0;
7425 }
64a0c779 7426
a724f0f4
JB		 7427 /* Since registers are not part of the displacement string (except
7428 when we're parsing offset operands), we may need to remove any
7429 preceding '+' from the displacement string. */
7430 if (*intel_parser.disp != '\0'
7431 && !intel_parser.in_offset)
7432 {
7433 char *s = intel_parser.disp;
7434 s += strlen (s) - 1;
7435 if (*s == '+')
7436 *s = '\0';
7437 }
4a1805b1 7438
a724f0f4
JB		 7439 return 1;
7440 }
7441
7442 /* e11 BYTE
7443 | WORD
7444 | DWORD
7445 | FWORD
7446 | QWORD
7447 | TBYTE
7448 | OWORD
7449 | XMMWORD */
7450 case T_BYTE:
7451 case T_WORD:
7452 case T_DWORD:
7453 case T_FWORD:
7454 case T_QWORD:
7455 case T_TBYTE:
7456 case T_XMMWORD:
7457 intel_match_token (cur_token.code);
64a0c779 7458
a724f0f4
JB		 7459 if (cur_token.code == T_PTR)
7460 return 1;
7461
7462 /* It must have been an identifier. */
7463 intel_putback_token ();
7464 cur_token.code = T_ID;
7465 /* FALLTHRU */
7466
7467 /* e11 id
7468 | constant */
7469 case T_ID:
7470 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 7471 {
7472 symbolS *symbolP;
7473
a724f0f4
JB		 7474 /* The identifier represents a memory reference only if it's not
7475 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 7476 symbolP = symbol_find(cur_token.str);
7477 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
7478 intel_parser.is_mem = 1;
7479 }
a724f0f4 7480 /* FALLTHRU */
64a0c779 7481
a724f0f4
JB		 7482 case T_CONST:
7483 case '-':
7484 case '+':
7485 {
7486 char *save_str, sign = 0;
64a0c779 7487
a724f0f4
JB		 7488 /* Allow constants that start with `+' or `-'. */
7489 if (cur_token.code == '-' || cur_token.code == '+')
7490 {
7491 sign = cur_token.code;
7492 intel_match_token (cur_token.code);
7493 if (cur_token.code != T_CONST)
7494 {
7495 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7496 cur_token.str);
7497 return 0;
7498 }
7499 }
64a0c779 7500
a724f0f4
JB		 7501 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
7502 strcpy (save_str + !!sign, cur_token.str);
7503 if (sign)
7504 *save_str = sign;
64a0c779 7505
a724f0f4
JB		 7506 /* Get the next token to check for register scaling. */
7507 intel_match_token (cur_token.code);
64a0c779 7508
4eed87de
AM		 7509 /* Check if this constant is a scaling factor for an
7510 index register. */
a724f0f4
JB		 7511 if (cur_token.code == '*')
7512 {
7513 if (intel_match_token ('*') && cur_token.code == T_REG)
7514 {
7515 const reg_entry *reg = cur_token.reg;
7516
7517 if (!intel_parser.in_bracket)
7518 {
4eed87de
AM		 7519 as_bad (_("Register scaling only allowed "
7520 "in memory operands"));
a724f0f4
JB		 7521 return 0;
7522 }
7523
4eed87de
AM		 7524 /* Disallow things like [1*si].
7525 sp and esp are invalid as index. */
7526 if (reg->reg_type & Reg16)
7527 reg = i386_regtab + REGNAM_AX + 4;
a724f0f4 7528 else if (i.index_reg)
4eed87de 7529 reg = i386_regtab + REGNAM_EAX + 4;
a724f0f4
JB		 7530
7531 /* The constant is followed by `* reg', so it must be
7532 a valid scale. */
7533 i.index_reg = reg;
7534 i.types[this_operand] |= BaseIndex;
7535
7536 /* Set the scale after setting the register (otherwise,
7537 i386_scale will complain) */
7538 if (!i386_scale (save_str))
64a0c779 7539 return 0;
a724f0f4
JB		 7540 intel_match_token (T_REG);
7541
7542 /* Since registers are not part of the displacement
7543 string, we may need to remove any preceding '+' from
7544 the displacement string. */
7545 if (*intel_parser.disp != '\0')
7546 {
7547 char *s = intel_parser.disp;
7548 s += strlen (s) - 1;
7549 if (*s == '+')
7550 *s = '\0';
7551 }
7552
7553 free (save_str);
7554
7555 return 1;
7556 }
64a0c779 7557
a724f0f4
JB		 7558 /* The constant was not used for register scaling. Since we have
7559 already consumed the token following `*' we now need to put it
7560 back in the stream. */
64a0c779 7561 intel_putback_token ();
a724f0f4 7562 }
64a0c779 7563
a724f0f4
JB		 7564 /* Add the constant to the displacement string. */
7565 strcat (intel_parser.disp, save_str);
7566 free (save_str);
64a0c779 7567
a724f0f4
JB		 7568 return 1;
7569 }
64a0c779
DN		 7570 }
7571
64a0c779
DN		 7572 as_bad (_("Unrecognized token '%s'"), cur_token.str);
7573 return 0;
7574}
7575
64a0c779
DN		 7576/* Match the given token against cur_token. If they match, read the next
7577 token from the operand string. */
7578static int
e3bb37b5 7579intel_match_token (int code)
64a0c779
DN		 7580{
7581 if (cur_token.code == code)
7582 {
7583 intel_get_token ();
7584 return 1;
7585 }
7586 else
7587 {
0477af35 7588 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 7589 return 0;
7590 }
7591}
7592
64a0c779
DN		 7593/* Read a new token from intel_parser.op_string and store it in cur_token. */
7594static void
e3bb37b5 7595intel_get_token (void)
64a0c779
DN		 7596{
7597 char *end_op;
7598 const reg_entry *reg;
7599 struct intel_token new_token;
7600
7601 new_token.code = T_NIL;
7602 new_token.reg = NULL;
7603 new_token.str = NULL;
7604
4a1805b1 7605 /* Free the memory allocated to the previous token and move
64a0c779
DN		 7606 cur_token to prev_token. */
7607 if (prev_token.str)
7608 free (prev_token.str);
7609
7610 prev_token = cur_token;
7611
7612 /* Skip whitespace. */
7613 while (is_space_char (*intel_parser.op_string))
7614 intel_parser.op_string++;
7615
7616 /* Return an empty token if we find nothing else on the line. */
7617 if (*intel_parser.op_string == '\0')
7618 {
7619 cur_token = new_token;
7620 return;
7621 }
7622
7623 /* The new token cannot be larger than the remainder of the operand
7624 string. */
a724f0f4 7625 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 7626 new_token.str[0] = '\0';
7627
7628 if (strchr ("0123456789", *intel_parser.op_string))
7629 {
7630 char *p = new_token.str;
7631 char *q = intel_parser.op_string;
7632 new_token.code = T_CONST;
7633
7634 /* Allow any kind of identifier char to encompass floating point and
7635 hexadecimal numbers. */
7636 while (is_identifier_char (*q))
7637 *p++ = *q++;
7638 *p = '\0';
7639
7640 /* Recognize special symbol names [0-9][bf]. */
7641 if (strlen (intel_parser.op_string) == 2
4a1805b1 7642 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 7643 || intel_parser.op_string[1] == 'f'))
7644 new_token.code = T_ID;
7645 }
7646
4d1bb795 7647 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
64a0c779 7648 {
4d1bb795
JB		 7649 size_t len = end_op - intel_parser.op_string;
7650
64a0c779
DN		 7651 new_token.code = T_REG;
7652 new_token.reg = reg;
7653
4d1bb795
JB		 7654 memcpy (new_token.str, intel_parser.op_string, len);
7655 new_token.str[len] = '\0';
64a0c779
DN		 7656 }
7657
7658 else if (is_identifier_char (*intel_parser.op_string))
7659 {
7660 char *p = new_token.str;
7661 char *q = intel_parser.op_string;
7662
7663 /* A '.' or '$' followed by an identifier char is an identifier.
7664 Otherwise, it's operator '.' followed by an expression. */
7665 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
7666 {
9306ca4a
JB		 7667 new_token.code = '.';
7668 new_token.str[0] = '.';
64a0c779
DN		 7669 new_token.str[1] = '\0';
7670 }
7671 else
7672 {
7673 while (is_identifier_char (*q) || *q == '@')
7674 *p++ = *q++;
7675 *p = '\0';
7676
9306ca4a
JB		 7677 if (strcasecmp (new_token.str, "NOT") == 0)
7678 new_token.code = '~';
7679
7680 else if (strcasecmp (new_token.str, "MOD") == 0)
7681 new_token.code = '%';
7682
7683 else if (strcasecmp (new_token.str, "AND") == 0)
7684 new_token.code = '&';
7685
7686 else if (strcasecmp (new_token.str, "OR") == 0)
7687 new_token.code = '|';
7688
7689 else if (strcasecmp (new_token.str, "XOR") == 0)
7690 new_token.code = '^';
7691
7692 else if (strcasecmp (new_token.str, "SHL") == 0)
7693 new_token.code = T_SHL;
7694
7695 else if (strcasecmp (new_token.str, "SHR") == 0)
7696 new_token.code = T_SHR;
7697
7698 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 7699 new_token.code = T_BYTE;
7700
7701 else if (strcasecmp (new_token.str, "WORD") == 0)
7702 new_token.code = T_WORD;
7703
7704 else if (strcasecmp (new_token.str, "DWORD") == 0)
7705 new_token.code = T_DWORD;
7706
9306ca4a
JB		 7707 else if (strcasecmp (new_token.str, "FWORD") == 0)
7708 new_token.code = T_FWORD;
7709
64a0c779
DN		 7710 else if (strcasecmp (new_token.str, "QWORD") == 0)
7711 new_token.code = T_QWORD;
7712
9306ca4a
JB		 7713 else if (strcasecmp (new_token.str, "TBYTE") == 0
7714 /* XXX remove (gcc still uses it) */
7715 || strcasecmp (new_token.str, "XWORD") == 0)
7716 new_token.code = T_TBYTE;
7717
7718 else if (strcasecmp (new_token.str, "XMMWORD") == 0
7719 || strcasecmp (new_token.str, "OWORD") == 0)
7720 new_token.code = T_XMMWORD;
64a0c779
DN		 7721
7722 else if (strcasecmp (new_token.str, "PTR") == 0)
7723 new_token.code = T_PTR;
7724
7725 else if (strcasecmp (new_token.str, "SHORT") == 0)
7726 new_token.code = T_SHORT;
7727
7728 else if (strcasecmp (new_token.str, "OFFSET") == 0)
7729 {
7730 new_token.code = T_OFFSET;
7731
7732 /* ??? This is not mentioned in the MASM grammar but gcc
7733 makes use of it with -mintel-syntax. OFFSET may be
7734 followed by FLAT: */
7735 if (strncasecmp (q, " FLAT:", 6) == 0)
7736 strcat (new_token.str, " FLAT:");
7737 }
7738
7739 /* ??? This is not mentioned in the MASM grammar. */
7740 else if (strcasecmp (new_token.str, "FLAT") == 0)
a724f0f4
JB		 7741 {
7742 new_token.code = T_OFFSET;
7743 if (*q == ':')
7744 strcat (new_token.str, ":");
7745 else
7746 as_bad (_("`:' expected"));
7747 }
64a0c779
DN		 7748
7749 else
7750 new_token.code = T_ID;
7751 }
7752 }
7753
9306ca4a
JB		 7754 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
7755 {
7756 new_token.code = *intel_parser.op_string;
7757 new_token.str[0] = *intel_parser.op_string;
7758 new_token.str[1] = '\0';
7759 }
7760
7761 else if (strchr ("<>", *intel_parser.op_string)
7762 && *intel_parser.op_string == *(intel_parser.op_string + 1))
7763 {
7764 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
7765 new_token.str[0] = *intel_parser.op_string;
7766 new_token.str[1] = *intel_parser.op_string;
7767 new_token.str[2] = '\0';
7768 }
7769
64a0c779 7770 else
0477af35 7771 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 7772
7773 intel_parser.op_string += strlen (new_token.str);
7774 cur_token = new_token;
7775}
7776
64a0c779
DN		 7777/* Put cur_token back into the token stream and make cur_token point to
7778 prev_token. */
7779static void
e3bb37b5 7780intel_putback_token (void)
64a0c779 7781{
a724f0f4
JB		 7782 if (cur_token.code != T_NIL)
7783 {
7784 intel_parser.op_string -= strlen (cur_token.str);
7785 free (cur_token.str);
7786 }
64a0c779 7787 cur_token = prev_token;
4a1805b1 7788
64a0c779
DN		 7789 /* Forget prev_token. */
7790 prev_token.code = T_NIL;
7791 prev_token.reg = NULL;
7792 prev_token.str = NULL;
7793}
54cfded0 7794
a4447b93 7795int
1df69f4f 7796tc_x86_regname_to_dw2regnum (char *regname)
54cfded0
AM		 7797{
7798 unsigned int regnum;
7799 unsigned int regnames_count;
089dfecd 7800 static const char *const regnames_32[] =
54cfded0 7801 {
a4447b93
RH		 7802 "eax", "ecx", "edx", "ebx",
7803 "esp", "ebp", "esi", "edi",
089dfecd
JB		 7804 "eip", "eflags", NULL,
7805 "st0", "st1", "st2", "st3",
7806 "st4", "st5", "st6", "st7",
7807 NULL, NULL,
7808 "xmm0", "xmm1", "xmm2", "xmm3",
7809 "xmm4", "xmm5", "xmm6", "xmm7",
7810 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 7811 "mm4", "mm5", "mm6", "mm7",
7812 "fcw", "fsw", "mxcsr",
7813 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7814 "tr", "ldtr"
54cfded0 7815 };
089dfecd 7816 static const char *const regnames_64[] =
54cfded0 7817 {
089dfecd
JB		 7818 "rax", "rdx", "rcx", "rbx",
7819 "rsi", "rdi", "rbp", "rsp",
7820 "r8", "r9", "r10", "r11",
54cfded0 7821 "r12", "r13", "r14", "r15",
089dfecd
JB		 7822 "rip",
7823 "xmm0", "xmm1", "xmm2", "xmm3",
7824 "xmm4", "xmm5", "xmm6", "xmm7",
7825 "xmm8", "xmm9", "xmm10", "xmm11",
7826 "xmm12", "xmm13", "xmm14", "xmm15",
7827 "st0", "st1", "st2", "st3",
7828 "st4", "st5", "st6", "st7",
7829 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 7830 "mm4", "mm5", "mm6", "mm7",
7831 "rflags",
7832 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7833 "fs.base", "gs.base", NULL, NULL,
7834 "tr", "ldtr",
7835 "mxcsr", "fcw", "fsw"
54cfded0 7836 };
089dfecd 7837 const char *const *regnames;
54cfded0
AM		 7838
7839 if (flag_code == CODE_64BIT)
7840 {
7841 regnames = regnames_64;
0cea6190 7842 regnames_count = ARRAY_SIZE (regnames_64);
54cfded0
AM		 7843 }
7844 else
7845 {
7846 regnames = regnames_32;
0cea6190 7847 regnames_count = ARRAY_SIZE (regnames_32);
54cfded0
AM		 7848 }
7849
7850 for (regnum = 0; regnum < regnames_count; regnum++)
089dfecd
JB		 7851 if (regnames[regnum] != NULL
7852 && strcmp (regname, regnames[regnum]) == 0)
54cfded0
AM		 7853 return regnum;
7854
54cfded0
AM		 7855 return -1;
7856}
7857
7858void
7859tc_x86_frame_initial_instructions (void)
7860{
a4447b93
RH		 7861 static unsigned int sp_regno;
7862
7863 if (!sp_regno)
7864 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
7865 ? "rsp" : "esp");
7866
7867 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
7868 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 7869}
d2b2c203
DJ		 7870
7871int
7872i386_elf_section_type (const char *str, size_t len)
7873{
7874 if (flag_code == CODE_64BIT
7875 && len == sizeof ("unwind") - 1
7876 && strncmp (str, "unwind", 6) == 0)
7877 return SHT_X86_64_UNWIND;
7878
7879 return -1;
7880}
bb41ade5
AM		 7881
7882#ifdef TE_PE
7883void
7884tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
7885{
7886 expressionS expr;
7887
7888 expr.X_op = O_secrel;
7889 expr.X_add_symbol = symbol;
7890 expr.X_add_number = 0;
7891 emit_expr (&expr, size);
7892}
7893#endif
3b22753a
L		 7894
7895#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7896/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7897
7898int
7899x86_64_section_letter (int letter, char **ptr_msg)
7900{
7901 if (flag_code == CODE_64BIT)
7902 {
7903 if (letter == 'l')
7904 return SHF_X86_64_LARGE;
7905
7906 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 7907 }
3b22753a 7908 else
64e74474 7909 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 7910 return -1;
7911}
7912
7913int
7914x86_64_section_word (char *str, size_t len)
7915{
8620418b 7916 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 7917 return SHF_X86_64_LARGE;
7918
7919 return -1;
7920}
7921
7922static void
7923handle_large_common (int small ATTRIBUTE_UNUSED)
7924{
7925 if (flag_code != CODE_64BIT)
7926 {
7927 s_comm_internal (0, elf_common_parse);
7928 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7929 }
7930 else
7931 {
7932 static segT lbss_section;
7933 asection *saved_com_section_ptr = elf_com_section_ptr;
7934 asection *saved_bss_section = bss_section;
7935
7936 if (lbss_section == NULL)
7937 {
7938 flagword applicable;
7939 segT seg = now_seg;
7940 subsegT subseg = now_subseg;
7941
7942 /* The .lbss section is for local .largecomm symbols. */
7943 lbss_section = subseg_new (".lbss", 0);
7944 applicable = bfd_applicable_section_flags (stdoutput);
7945 bfd_set_section_flags (stdoutput, lbss_section,
7946 applicable & SEC_ALLOC);
7947 seg_info (lbss_section)->bss = 1;
7948
7949 subseg_set (seg, subseg);
7950 }
7951
7952 elf_com_section_ptr = &_bfd_elf_large_com_section;
7953 bss_section = lbss_section;
7954
7955 s_comm_internal (0, elf_common_parse);
7956
7957 elf_com_section_ptr = saved_com_section_ptr;
7958 bss_section = saved_bss_section;
7959 }
7960}
7961#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
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