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b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
c75ef631 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus ([email protected]).
3e73aa7c 25 x86_64 support by Jan Hubicka ([email protected])
0f10071e 26 VIA PadLock support by Michal Ludvig ([email protected])
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
40fb9820 36#include "opcodes/i386-init.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
29b0f896
AM		 46#ifndef DEFAULT_ARCH
47#define DEFAULT_ARCH "i386"
246fcdee 48#endif
252b5132 49
edde18a5
AM		 50#ifndef INLINE
51#if __GNUC__ >= 2
52#define INLINE __inline__
53#else
54#define INLINE
55#endif
56#endif
57
6305a203
L		 58/* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
c32fa91d 62 REP_PREFIX, LOCK_PREFIX. */
6305a203
L		 63#define WAIT_PREFIX 0
64#define SEG_PREFIX 1
65#define ADDR_PREFIX 2
66#define DATA_PREFIX 3
c32fa91d
L		 67#define REP_PREFIX 4
68#define LOCK_PREFIX 5
69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
84#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 85#define YMMWORD_MNEM_SUFFIX 'y'
6305a203
L		 86/* Intel Syntax. Use a non-ascii letter since since it never appears
87 in instructions. */
88#define LONG_DOUBLE_MNEM_SUFFIX '\1'
89
90#define END_OF_INSN '\0'
91
92/*
93 'templates' is for grouping together 'template' structures for opcodes
94 of the same name. This is only used for storing the insns in the grand
95 ole hash table of insns.
96 The templates themselves start at START and range up to (but not including)
97 END.
98 */
99typedef struct
100{
d3ce72d0
NC		 101 const insn_template *start;
102 const insn_template *end;
6305a203
L		 103}
104templates;
105
106/* 386 operand encoding bytes: see 386 book for details of this. */
107typedef struct
108{
109 unsigned int regmem; /* codes register or memory operand */
110 unsigned int reg; /* codes register operand (or extended opcode) */
111 unsigned int mode; /* how to interpret regmem & reg */
112}
113modrm_byte;
114
115/* x86-64 extension prefix. */
116typedef int rex_byte;
117
6305a203
L		 118/* 386 opcode byte to code indirect addressing. */
119typedef struct
120{
121 unsigned base;
122 unsigned index;
123 unsigned scale;
124}
125sib_byte;
126
6305a203
L		 127/* x86 arch names, types and features */
128typedef struct
129{
130 const char *name; /* arch name */
8a2c8fef 131 unsigned int len; /* arch string length */
6305a203
L		 132 enum processor_type type; /* arch type */
133 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 134 unsigned int skip; /* show_arch should skip this. */
6305a203
L		 135}
136arch_entry;
137
78f12dd3 138static void update_code_flag (int, int);
e3bb37b5
L		 139static void set_code_flag (int);
140static void set_16bit_gcc_code_flag (int);
141static void set_intel_syntax (int);
1efbbeb4 142static void set_intel_mnemonic (int);
db51cc60 143static void set_allow_index_reg (int);
cb19c032 144static void set_sse_check (int);
e3bb37b5 145static void set_cpu_arch (int);
6482c264 146#ifdef TE_PE
e3bb37b5 147static void pe_directive_secrel (int);
6482c264 148#endif
e3bb37b5
L		 149static void signed_cons (int);
150static char *output_invalid (int c);
ee86248c
JB		 151static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
152 const char *);
153static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
154 const char *);
a7619375 155static int i386_att_operand (char *);
e3bb37b5 156static int i386_intel_operand (char *, int);
ee86248c
JB		 157static int i386_intel_simplify (expressionS *);
158static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 159static const reg_entry *parse_register (char *, char **);
160static char *parse_insn (char *, char *);
161static char *parse_operands (char *, const char *);
162static void swap_operands (void);
4d456e3d 163static void swap_2_operands (int, int);
e3bb37b5
L		 164static void optimize_imm (void);
165static void optimize_disp (void);
d3ce72d0 166static const insn_template *match_template (void);
e3bb37b5
L		 167static int check_string (void);
168static int process_suffix (void);
169static int check_byte_reg (void);
170static int check_long_reg (void);
171static int check_qword_reg (void);
172static int check_word_reg (void);
173static int finalize_imm (void);
174static int process_operands (void);
175static const seg_entry *build_modrm_byte (void);
176static void output_insn (void);
177static void output_imm (fragS *, offsetT);
178static void output_disp (fragS *, offsetT);
29b0f896 179#ifndef I386COFF
e3bb37b5 180static void s_bss (int);
252b5132 181#endif
17d4e2a2
L		 182#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
183static void handle_large_common (int small ATTRIBUTE_UNUSED);
184#endif
252b5132 185
a847613f 186static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 187
c0f3af97
L		 188/* VEX prefix. */
189typedef struct
190{
191 /* VEX prefix is either 2 byte or 3 byte. */
192 unsigned char bytes[3];
193 unsigned int length;
194 /* Destination or source register specifier. */
195 const reg_entry *register_specifier;
196} vex_prefix;
197
252b5132 198/* 'md_assemble ()' gathers together information and puts it into a
47926f60 199 i386_insn. */
252b5132 200
520dc8e8
AM		 201union i386_op
202 {
203 expressionS *disps;
204 expressionS *imms;
205 const reg_entry *regs;
206 };
207
a65babc9
L		 208enum i386_error
209 {
86e026a4 210 operand_size_mismatch,
a65babc9
L		 211 operand_type_mismatch,
212 register_type_mismatch,
213 number_of_operands_mismatch,
214 invalid_instruction_suffix,
215 bad_imm4,
216 old_gcc_only,
217 unsupported_with_intel_mnemonic,
218 unsupported_syntax,
219 unsupported
220 };
221
252b5132
RH		 222struct _i386_insn
223 {
47926f60 224 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 225 insn_template tm;
252b5132 226
7d5e4556
L		 227 /* SUFFIX holds the instruction size suffix for byte, word, dword
228 or qword, if given. */
252b5132
RH		 229 char suffix;
230
47926f60 231 /* OPERANDS gives the number of given operands. */
252b5132
RH		 232 unsigned int operands;
233
234 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
235 of given register, displacement, memory operands and immediate
47926f60 236 operands. */
252b5132
RH		 237 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
238
239 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 240 use OP[i] for the corresponding operand. */
40fb9820 241 i386_operand_type types[MAX_OPERANDS];
252b5132 242
520dc8e8
AM		 243 /* Displacement expression, immediate expression, or register for each
244 operand. */
245 union i386_op op[MAX_OPERANDS];
252b5132 246
3e73aa7c
JH		 247 /* Flags for operands. */
248 unsigned int flags[MAX_OPERANDS];
249#define Operand_PCrel 1
250
252b5132 251 /* Relocation type for operand */
f86103b7 252 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 253
252b5132
RH		 254 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
255 the base index byte below. */
256 const reg_entry *base_reg;
257 const reg_entry *index_reg;
258 unsigned int log2_scale_factor;
259
260 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 261 explicit segment overrides are given. */
ce8a8b2f 262 const seg_entry *seg[2];
252b5132
RH		 263
264 /* PREFIX holds all the given prefix opcodes (usually null).
265 PREFIXES is the number of prefix opcodes. */
266 unsigned int prefixes;
267 unsigned char prefix[MAX_PREFIXES];
268
269 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 270 addressing modes of this insn are encoded. */
252b5132 271 modrm_byte rm;
3e73aa7c 272 rex_byte rex;
252b5132 273 sib_byte sib;
c0f3af97 274 vex_prefix vex;
b6169b20
L		 275
276 /* Swap operand in encoding. */
4473e004 277 unsigned int swap_operand;
891edac4
L		 278
279 /* Error message. */
a65babc9 280 enum i386_error error;
252b5132
RH		 281 };
282
283typedef struct _i386_insn i386_insn;
284
285/* List of chars besides those in app.c:symbol_chars that can start an
286 operand. Used to prevent the scrubber eating vital white-space. */
32137342 287const char extra_symbol_chars[] = "*%-(["
252b5132 288#ifdef LEX_AT
32137342
NC		 289 "@"
290#endif
291#ifdef LEX_QM
292 "?"
252b5132 293#endif
32137342 294 ;
252b5132 295
29b0f896
AM		 296#if (defined (TE_I386AIX) \
297 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 298 && !defined (TE_GNU) \
29b0f896 299 && !defined (TE_LINUX) \
32137342 300 && !defined (TE_NETWARE) \
29b0f896
AM		 301 && !defined (TE_FreeBSD) \
302 && !defined (TE_NetBSD)))
252b5132 303/* This array holds the chars that always start a comment. If the
b3b91714
AM		 304 pre-processor is disabled, these aren't very useful. The option
305 --divide will remove '/' from this list. */
306const char *i386_comment_chars = "#/";
307#define SVR4_COMMENT_CHARS 1
252b5132 308#define PREFIX_SEPARATOR '\\'
252b5132 309
b3b91714
AM		 310#else
311const char *i386_comment_chars = "#";
312#define PREFIX_SEPARATOR '/'
313#endif
314
252b5132
RH		 315/* This array holds the chars that only start a comment at the beginning of
316 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 317 .line and .file directives will appear in the pre-processed output.
318 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 319 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 320 #NO_APP at the beginning of its output.
321 Also note that comments started like this one will always work if
252b5132 322 '/' isn't otherwise defined. */
b3b91714 323const char line_comment_chars[] = "#/";
252b5132 324
63a0b638 325const char line_separator_chars[] = ";";
252b5132 326
ce8a8b2f
AM		 327/* Chars that can be used to separate mant from exp in floating point
328 nums. */
252b5132
RH		 329const char EXP_CHARS[] = "eE";
330
ce8a8b2f
AM		 331/* Chars that mean this number is a floating point constant
332 As in 0f12.456
333 or 0d1.2345e12. */
252b5132
RH		 334const char FLT_CHARS[] = "fFdDxX";
335
ce8a8b2f 336/* Tables for lexical analysis. */
252b5132
RH		 337static char mnemonic_chars[256];
338static char register_chars[256];
339static char operand_chars[256];
340static char identifier_chars[256];
341static char digit_chars[256];
342
ce8a8b2f 343/* Lexical macros. */
252b5132
RH		 344#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
345#define is_operand_char(x) (operand_chars[(unsigned char) x])
346#define is_register_char(x) (register_chars[(unsigned char) x])
347#define is_space_char(x) ((x) == ' ')
348#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
349#define is_digit_char(x) (digit_chars[(unsigned char) x])
350
0234cb7c 351/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 352static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
353
354/* md_assemble() always leaves the strings it's passed unaltered. To
355 effect this we maintain a stack of saved characters that we've smashed
356 with '\0's (indicating end of strings for various sub-fields of the
47926f60 357 assembler instruction). */
252b5132 358static char save_stack[32];
ce8a8b2f 359static char *save_stack_p;
252b5132
RH		 360#define END_STRING_AND_SAVE(s) \
361 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
362#define RESTORE_END_STRING(s) \
363 do { *(s) = *--save_stack_p; } while (0)
364
47926f60 365/* The instruction we're assembling. */
252b5132
RH		 366static i386_insn i;
367
368/* Possible templates for current insn. */
369static const templates *current_templates;
370
31b2323c
L		 371/* Per instruction expressionS buffers: max displacements & immediates. */
372static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
373static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 374
47926f60 375/* Current operand we are working on. */
ee86248c 376static int this_operand = -1;
252b5132 377
3e73aa7c
JH		 378/* We support four different modes. FLAG_CODE variable is used to distinguish
379 these. */
380
381enum flag_code {
382 CODE_32BIT,
383 CODE_16BIT,
384 CODE_64BIT };
385
386static enum flag_code flag_code;
4fa24527 387static unsigned int object_64bit;
3e73aa7c
JH		 388static int use_rela_relocations = 0;
389
390/* The names used to print error messages. */
b77a7acd 391static const char *flag_code_names[] =
3e73aa7c
JH		 392 {
393 "32",
394 "16",
395 "64"
396 };
252b5132 397
47926f60
KH		 398/* 1 for intel syntax,
399 0 if att syntax. */
400static int intel_syntax = 0;
252b5132 401
1efbbeb4
L		 402/* 1 for intel mnemonic,
403 0 if att mnemonic. */
404static int intel_mnemonic = !SYSV386_COMPAT;
405
5209009a 406/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 407static int old_gcc = OLDGCC_COMPAT;
408
a60de03c
JB		 409/* 1 if pseudo registers are permitted. */
410static int allow_pseudo_reg = 0;
411
47926f60
KH		 412/* 1 if register prefix % not required. */
413static int allow_naked_reg = 0;
252b5132 414
ba104c83 415/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 416static int allow_index_reg = 0;
417
daf50ae7
L		 418static enum
419 {
420 sse_check_none = 0,
421 sse_check_warning,
422 sse_check_error
423 }
424sse_check;
425
2ca3ace5
L		 426/* Register prefix used for error message. */
427static const char *register_prefix = "%";
428
47926f60
KH		 429/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
430 leave, push, and pop instructions so that gcc has the same stack
431 frame as in 32 bit mode. */
432static char stackop_size = '\0';
eecb386c 433
12b55ccc
L		 434/* Non-zero to optimize code alignment. */
435int optimize_align_code = 1;
436
47926f60
KH		 437/* Non-zero to quieten some warnings. */
438static int quiet_warnings = 0;
a38cf1db 439
47926f60
KH		 440/* CPU name. */
441static const char *cpu_arch_name = NULL;
6305a203 442static char *cpu_sub_arch_name = NULL;
a38cf1db 443
47926f60 444/* CPU feature flags. */
40fb9820
L		 445static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
446
ccc9c027
L		 447/* If we have selected a cpu we are generating instructions for. */
448static int cpu_arch_tune_set = 0;
449
9103f4f4 450/* Cpu we are generating instructions for. */
fbf3f584 451enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 452
453/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 454static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 455
ccc9c027 456/* CPU instruction set architecture used. */
fbf3f584 457enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 458
9103f4f4 459/* CPU feature flags of instruction set architecture used. */
fbf3f584 460i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 461
fddf5b5b
AM		 462/* If set, conditional jumps are not automatically promoted to handle
463 larger than a byte offset. */
464static unsigned int no_cond_jump_promotion = 0;
465
c0f3af97
L		 466/* Encode SSE instructions with VEX prefix. */
467static unsigned int sse2avx;
468
539f890d
L		 469/* Encode scalar AVX instructions with specific vector length. */
470static enum
471 {
472 vex128 = 0,
473 vex256
474 } avxscalar;
475
29b0f896 476/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 477static symbolS *GOT_symbol;
29b0f896 478
a4447b93
RH		 479/* The dwarf2 return column, adjusted for 32 or 64 bit. */
480unsigned int x86_dwarf2_return_column;
481
482/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
483int x86_cie_data_alignment;
484
252b5132 485/* Interface to relax_segment.
fddf5b5b
AM		 486 There are 3 major relax states for 386 jump insns because the
487 different types of jumps add different sizes to frags when we're
488 figuring out what sort of jump to choose to reach a given label. */
252b5132 489
47926f60 490/* Types. */
93c2a809
AM		 491#define UNCOND_JUMP 0
492#define COND_JUMP 1
493#define COND_JUMP86 2
fddf5b5b 494
47926f60 495/* Sizes. */
252b5132
RH		 496#define CODE16 1
497#define SMALL 0
29b0f896 498#define SMALL16 (SMALL | CODE16)
252b5132 499#define BIG 2
29b0f896 500#define BIG16 (BIG | CODE16)
252b5132
RH		 501
502#ifndef INLINE
503#ifdef __GNUC__
504#define INLINE __inline__
505#else
506#define INLINE
507#endif
508#endif
509
fddf5b5b
AM		 510#define ENCODE_RELAX_STATE(type, size) \
511 ((relax_substateT) (((type) << 2) | (size)))
512#define TYPE_FROM_RELAX_STATE(s) \
513 ((s) >> 2)
514#define DISP_SIZE_FROM_RELAX_STATE(s) \
515 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 516
517/* This table is used by relax_frag to promote short jumps to long
518 ones where necessary. SMALL (short) jumps may be promoted to BIG
519 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
520 don't allow a short jump in a 32 bit code segment to be promoted to
521 a 16 bit offset jump because it's slower (requires data size
522 prefix), and doesn't work, unless the destination is in the bottom
523 64k of the code segment (The top 16 bits of eip are zeroed). */
524
525const relax_typeS md_relax_table[] =
526{
24eab124
AM		 527 /* The fields are:
528 1) most positive reach of this state,
529 2) most negative reach of this state,
93c2a809 530 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 531 4) which index into the table to try if we can't fit into this one. */
252b5132 532
fddf5b5b 533 /* UNCOND_JUMP states. */
93c2a809
AM		 534 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
535 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
536 /* dword jmp adds 4 bytes to frag:
537 0 extra opcode bytes, 4 displacement bytes. */
252b5132 538 {0, 0, 4, 0},
93c2a809
AM		 539 /* word jmp adds 2 byte2 to frag:
540 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 541 {0, 0, 2, 0},
542
93c2a809
AM		 543 /* COND_JUMP states. */
544 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
545 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
546 /* dword conditionals adds 5 bytes to frag:
547 1 extra opcode byte, 4 displacement bytes. */
548 {0, 0, 5, 0},
fddf5b5b 549 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 550 1 extra opcode byte, 2 displacement bytes. */
551 {0, 0, 3, 0},
552
553 /* COND_JUMP86 states. */
554 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
555 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
556 /* dword conditionals adds 5 bytes to frag:
557 1 extra opcode byte, 4 displacement bytes. */
558 {0, 0, 5, 0},
559 /* word conditionals add 4 bytes to frag:
560 1 displacement byte and a 3 byte long branch insn. */
561 {0, 0, 4, 0}
252b5132
RH		 562};
563
9103f4f4
L		 564static const arch_entry cpu_arch[] =
565{
89507696
JB		 566 /* Do not replace the first two entries - i386_target_format()
567 relies on them being there in this order. */
8a2c8fef
L		 568 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
569 CPU_GENERIC32_FLAGS, 0 },
570 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
571 CPU_GENERIC64_FLAGS, 0 },
572 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
573 CPU_NONE_FLAGS, 0 },
574 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
575 CPU_I186_FLAGS, 0 },
576 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
577 CPU_I286_FLAGS, 0 },
578 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
579 CPU_I386_FLAGS, 0 },
580 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
581 CPU_I486_FLAGS, 0 },
582 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
583 CPU_I586_FLAGS, 0 },
584 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
585 CPU_I686_FLAGS, 0 },
586 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
587 CPU_I586_FLAGS, 0 },
588 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
589 CPU_I686_FLAGS, 0 },
590 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
591 CPU_P2_FLAGS, 0 },
592 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
593 CPU_P3_FLAGS, 0 },
594 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
595 CPU_P4_FLAGS, 0 },
596 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
597 CPU_CORE_FLAGS, 0 },
598 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
599 CPU_NOCONA_FLAGS, 0 },
600 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
601 CPU_CORE_FLAGS, 1 },
602 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
603 CPU_CORE_FLAGS, 0 },
604 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
605 CPU_CORE2_FLAGS, 1 },
606 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
607 CPU_CORE2_FLAGS, 0 },
608 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
609 CPU_COREI7_FLAGS, 0 },
610 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
611 CPU_L1OM_FLAGS, 0 },
612 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
613 CPU_K6_FLAGS, 0 },
614 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
615 CPU_K6_2_FLAGS, 0 },
616 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
617 CPU_ATHLON_FLAGS, 0 },
618 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
619 CPU_K8_FLAGS, 1 },
620 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
621 CPU_K8_FLAGS, 0 },
622 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
623 CPU_K8_FLAGS, 0 },
624 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
625 CPU_AMDFAM10_FLAGS, 0 },
68339fdf
SP		 626 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BDVER1,
627 CPU_BDVER1_FLAGS, 0 },
8a2c8fef
L		 628 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
629 CPU_8087_FLAGS, 0 },
630 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
631 CPU_287_FLAGS, 0 },
632 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
633 CPU_387_FLAGS, 0 },
634 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
635 CPU_ANY87_FLAGS, 0 },
636 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
637 CPU_MMX_FLAGS, 0 },
638 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
639 CPU_3DNOWA_FLAGS, 0 },
640 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
641 CPU_SSE_FLAGS, 0 },
642 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
643 CPU_SSE2_FLAGS, 0 },
644 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
645 CPU_SSE3_FLAGS, 0 },
646 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
647 CPU_SSSE3_FLAGS, 0 },
648 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
649 CPU_SSE4_1_FLAGS, 0 },
650 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
651 CPU_SSE4_2_FLAGS, 0 },
652 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
653 CPU_SSE4_2_FLAGS, 0 },
654 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
655 CPU_ANY_SSE_FLAGS, 0 },
656 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
657 CPU_AVX_FLAGS, 0 },
658 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
659 CPU_ANY_AVX_FLAGS, 0 },
660 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
661 CPU_VMX_FLAGS, 0 },
662 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
663 CPU_SMX_FLAGS, 0 },
664 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
665 CPU_XSAVE_FLAGS, 0 },
666 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
667 CPU_AES_FLAGS, 0 },
668 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
669 CPU_PCLMUL_FLAGS, 0 },
670 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
671 CPU_PCLMUL_FLAGS, 1 },
672 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
673 CPU_FMA_FLAGS, 0 },
674 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
675 CPU_FMA4_FLAGS, 0 },
676 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
677 CPU_XOP_FLAGS, 0 },
678 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
679 CPU_LWP_FLAGS, 0 },
680 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
681 CPU_MOVBE_FLAGS, 0 },
682 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
683 CPU_EPT_FLAGS, 0 },
684 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
685 CPU_CLFLUSH_FLAGS, 0 },
686 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
687 CPU_SYSCALL_FLAGS, 0 },
688 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
689 CPU_RDTSCP_FLAGS, 0 },
690 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
691 CPU_3DNOW_FLAGS, 0 },
692 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
693 CPU_3DNOWA_FLAGS, 0 },
694 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
695 CPU_PADLOCK_FLAGS, 0 },
696 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
697 CPU_SVME_FLAGS, 1 },
698 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
699 CPU_SVME_FLAGS, 0 },
700 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
701 CPU_SSE4A_FLAGS, 0 },
702 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
703 CPU_ABM_FLAGS, 0 },
e413e4e9
AM		 704};
705
704209c0 706#ifdef I386COFF
a6c24e68
NC		 707/* Like s_lcomm_internal in gas/read.c but the alignment string
708 is allowed to be optional. */
709
710static symbolS *
711pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
712{
713 addressT align = 0;
714
715 SKIP_WHITESPACE ();
716
7ab9ffdd 717 if (needs_align
a6c24e68
NC		 718 && *input_line_pointer == ',')
719 {
720 align = parse_align (needs_align - 1);
7ab9ffdd 721
a6c24e68
NC		 722 if (align == (addressT) -1)
723 return NULL;
724 }
725 else
726 {
727 if (size >= 8)
728 align = 3;
729 else if (size >= 4)
730 align = 2;
731 else if (size >= 2)
732 align = 1;
733 else
734 align = 0;
735 }
736
737 bss_alloc (symbolP, size, align);
738 return symbolP;
739}
740
704209c0 741static void
a6c24e68
NC		 742pe_lcomm (int needs_align)
743{
744 s_comm_internal (needs_align * 2, pe_lcomm_internal);
745}
704209c0 746#endif
a6c24e68 747
29b0f896
AM		 748const pseudo_typeS md_pseudo_table[] =
749{
750#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
751 {"align", s_align_bytes, 0},
752#else
753 {"align", s_align_ptwo, 0},
754#endif
755 {"arch", set_cpu_arch, 0},
756#ifndef I386COFF
757 {"bss", s_bss, 0},
a6c24e68
NC		 758#else
759 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 760#endif
761 {"ffloat", float_cons, 'f'},
762 {"dfloat", float_cons, 'd'},
763 {"tfloat", float_cons, 'x'},
764 {"value", cons, 2},
d182319b 765 {"slong", signed_cons, 4},
29b0f896
AM		 766 {"noopt", s_ignore, 0},
767 {"optim", s_ignore, 0},
768 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
769 {"code16", set_code_flag, CODE_16BIT},
770 {"code32", set_code_flag, CODE_32BIT},
771 {"code64", set_code_flag, CODE_64BIT},
772 {"intel_syntax", set_intel_syntax, 1},
773 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 774 {"intel_mnemonic", set_intel_mnemonic, 1},
775 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 776 {"allow_index_reg", set_allow_index_reg, 1},
777 {"disallow_index_reg", set_allow_index_reg, 0},
cb19c032 778 {"sse_check", set_sse_check, 0},
3b22753a
L		 779#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
780 {"largecomm", handle_large_common, 0},
07a53e5c 781#else
e3bb37b5 782 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 783 {"loc", dwarf2_directive_loc, 0},
784 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 785#endif
6482c264
NC		 786#ifdef TE_PE
787 {"secrel32", pe_directive_secrel, 0},
788#endif
29b0f896
AM		 789 {0, 0, 0}
790};
791
792/* For interface with expression (). */
793extern char *input_line_pointer;
794
795/* Hash table for instruction mnemonic lookup. */
796static struct hash_control *op_hash;
797
798/* Hash table for register lookup. */
799static struct hash_control *reg_hash;
800\f
252b5132 801void
e3bb37b5 802i386_align_code (fragS *fragP, int count)
252b5132 803{
ce8a8b2f
AM		 804 /* Various efficient no-op patterns for aligning code labels.
805 Note: Don't try to assemble the instructions in the comments.
806 0L and 0w are not legal. */
252b5132
RH		 807 static const char f32_1[] =
808 {0x90}; /* nop */
809 static const char f32_2[] =
ccc9c027 810 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 811 static const char f32_3[] =
812 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
813 static const char f32_4[] =
814 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
815 static const char f32_5[] =
816 {0x90, /* nop */
817 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
818 static const char f32_6[] =
819 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
820 static const char f32_7[] =
821 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
822 static const char f32_8[] =
823 {0x90, /* nop */
824 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
825 static const char f32_9[] =
826 {0x89,0xf6, /* movl %esi,%esi */
827 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
828 static const char f32_10[] =
829 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
830 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
831 static const char f32_11[] =
832 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
833 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
834 static const char f32_12[] =
835 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
836 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
837 static const char f32_13[] =
838 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
839 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
840 static const char f32_14[] =
841 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
842 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 843 static const char f16_3[] =
844 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 845 static const char f16_4[] =
846 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
847 static const char f16_5[] =
848 {0x90, /* nop */
849 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
850 static const char f16_6[] =
851 {0x89,0xf6, /* mov %si,%si */
852 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
853 static const char f16_7[] =
854 {0x8d,0x74,0x00, /* lea 0(%si),%si */
855 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
856 static const char f16_8[] =
857 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
858 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 859 static const char jump_31[] =
860 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
861 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
862 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
863 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 864 static const char *const f32_patt[] = {
865 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 866 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 867 };
868 static const char *const f16_patt[] = {
76bc74dc 869 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 870 };
ccc9c027
L		 871 /* nopl (%[re]ax) */
872 static const char alt_3[] =
873 {0x0f,0x1f,0x00};
874 /* nopl 0(%[re]ax) */
875 static const char alt_4[] =
876 {0x0f,0x1f,0x40,0x00};
877 /* nopl 0(%[re]ax,%[re]ax,1) */
878 static const char alt_5[] =
879 {0x0f,0x1f,0x44,0x00,0x00};
880 /* nopw 0(%[re]ax,%[re]ax,1) */
881 static const char alt_6[] =
882 {0x66,0x0f,0x1f,0x44,0x00,0x00};
883 /* nopl 0L(%[re]ax) */
884 static const char alt_7[] =
885 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
886 /* nopl 0L(%[re]ax,%[re]ax,1) */
887 static const char alt_8[] =
888 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
889 /* nopw 0L(%[re]ax,%[re]ax,1) */
890 static const char alt_9[] =
891 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
892 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
893 static const char alt_10[] =
894 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
895 /* data16
896 nopw %cs:0L(%[re]ax,%[re]ax,1) */
897 static const char alt_long_11[] =
898 {0x66,
899 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
900 /* data16
901 data16
902 nopw %cs:0L(%[re]ax,%[re]ax,1) */
903 static const char alt_long_12[] =
904 {0x66,
905 0x66,
906 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
907 /* data16
908 data16
909 data16
910 nopw %cs:0L(%[re]ax,%[re]ax,1) */
911 static const char alt_long_13[] =
912 {0x66,
913 0x66,
914 0x66,
915 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
916 /* data16
917 data16
918 data16
919 data16
920 nopw %cs:0L(%[re]ax,%[re]ax,1) */
921 static const char alt_long_14[] =
922 {0x66,
923 0x66,
924 0x66,
925 0x66,
926 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
927 /* data16
928 data16
929 data16
930 data16
931 data16
932 nopw %cs:0L(%[re]ax,%[re]ax,1) */
933 static const char alt_long_15[] =
934 {0x66,
935 0x66,
936 0x66,
937 0x66,
938 0x66,
939 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
940 /* nopl 0(%[re]ax,%[re]ax,1)
941 nopw 0(%[re]ax,%[re]ax,1) */
942 static const char alt_short_11[] =
943 {0x0f,0x1f,0x44,0x00,0x00,
944 0x66,0x0f,0x1f,0x44,0x00,0x00};
945 /* nopw 0(%[re]ax,%[re]ax,1)
946 nopw 0(%[re]ax,%[re]ax,1) */
947 static const char alt_short_12[] =
948 {0x66,0x0f,0x1f,0x44,0x00,0x00,
949 0x66,0x0f,0x1f,0x44,0x00,0x00};
950 /* nopw 0(%[re]ax,%[re]ax,1)
951 nopl 0L(%[re]ax) */
952 static const char alt_short_13[] =
953 {0x66,0x0f,0x1f,0x44,0x00,0x00,
954 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
955 /* nopl 0L(%[re]ax)
956 nopl 0L(%[re]ax) */
957 static const char alt_short_14[] =
958 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
959 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
960 /* nopl 0L(%[re]ax)
961 nopl 0L(%[re]ax,%[re]ax,1) */
962 static const char alt_short_15[] =
963 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
964 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
965 static const char *const alt_short_patt[] = {
966 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
967 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
968 alt_short_14, alt_short_15
969 };
970 static const char *const alt_long_patt[] = {
971 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
972 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
973 alt_long_14, alt_long_15
974 };
252b5132 975
76bc74dc
L		 976 /* Only align for at least a positive non-zero boundary. */
977 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 978 return;
3e73aa7c 979
ccc9c027
L		 980 /* We need to decide which NOP sequence to use for 32bit and
981 64bit. When -mtune= is used:
4eed87de 982
76bc74dc
L		 983 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
984 PROCESSOR_GENERIC32, f32_patt will be used.
985 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
bd5295b2
L		 986 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
987 PROCESSOR_GENERIC64, alt_long_patt will be used.
76bc74dc 988 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
68339fdf 989 PROCESSOR_AMDFAM10, and PROCESSOR_BDVER1, alt_short_patt
69dd9865 990 will be used.
ccc9c027 991
76bc74dc
L		 992 When -mtune= isn't used, alt_long_patt will be used if
993 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
994 be used.
ccc9c027
L		 995
996 When -march= or .arch is used, we can't use anything beyond
997 cpu_arch_isa_flags. */
998
999 if (flag_code == CODE_16BIT)
1000 {
ccc9c027 1001 if (count > 8)
33fef721 1002 {
76bc74dc
L		 1003 memcpy (fragP->fr_literal + fragP->fr_fix,
1004 jump_31, count);
1005 /* Adjust jump offset. */
1006 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1007 }
76bc74dc
L		 1008 else
1009 memcpy (fragP->fr_literal + fragP->fr_fix,
1010 f16_patt[count - 1], count);
252b5132 1011 }
33fef721 1012 else
ccc9c027
L		 1013 {
1014 const char *const *patt = NULL;
1015
fbf3f584 1016 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1017 {
1018 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1019 switch (cpu_arch_tune)
1020 {
1021 case PROCESSOR_UNKNOWN:
1022 /* We use cpu_arch_isa_flags to check if we SHOULD
1023 optimize for Cpu686. */
fbf3f584 1024 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
76bc74dc 1025 patt = alt_long_patt;
ccc9c027
L		 1026 else
1027 patt = f32_patt;
1028 break;
ccc9c027
L		 1029 case PROCESSOR_PENTIUMPRO:
1030 case PROCESSOR_PENTIUM4:
1031 case PROCESSOR_NOCONA:
ef05d495 1032 case PROCESSOR_CORE:
76bc74dc 1033 case PROCESSOR_CORE2:
bd5295b2 1034 case PROCESSOR_COREI7:
3632d14b 1035 case PROCESSOR_L1OM:
76bc74dc
L		 1036 case PROCESSOR_GENERIC64:
1037 patt = alt_long_patt;
1038 break;
ccc9c027
L		 1039 case PROCESSOR_K6:
1040 case PROCESSOR_ATHLON:
1041 case PROCESSOR_K8:
4eed87de 1042 case PROCESSOR_AMDFAM10:
68339fdf 1043 case PROCESSOR_BDVER1:
ccc9c027
L		 1044 patt = alt_short_patt;
1045 break;
76bc74dc 1046 case PROCESSOR_I386:
ccc9c027
L		 1047 case PROCESSOR_I486:
1048 case PROCESSOR_PENTIUM:
1049 case PROCESSOR_GENERIC32:
1050 patt = f32_patt;
1051 break;
4eed87de 1052 }
ccc9c027
L		 1053 }
1054 else
1055 {
fbf3f584 1056 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1057 {
1058 case PROCESSOR_UNKNOWN:
e6a14101 1059 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1060 PROCESSOR_UNKNOWN. */
1061 abort ();
1062 break;
1063
76bc74dc 1064 case PROCESSOR_I386:
ccc9c027
L		 1065 case PROCESSOR_I486:
1066 case PROCESSOR_PENTIUM:
ccc9c027
L		 1067 case PROCESSOR_K6:
1068 case PROCESSOR_ATHLON:
1069 case PROCESSOR_K8:
4eed87de 1070 case PROCESSOR_AMDFAM10:
68339fdf 1071 case PROCESSOR_BDVER1:
ccc9c027
L		 1072 case PROCESSOR_GENERIC32:
1073 /* We use cpu_arch_isa_flags to check if we CAN optimize
1074 for Cpu686. */
fbf3f584 1075 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
ccc9c027
L		 1076 patt = alt_short_patt;
1077 else
1078 patt = f32_patt;
1079 break;
76bc74dc
L		 1080 case PROCESSOR_PENTIUMPRO:
1081 case PROCESSOR_PENTIUM4:
1082 case PROCESSOR_NOCONA:
1083 case PROCESSOR_CORE:
ef05d495 1084 case PROCESSOR_CORE2:
bd5295b2 1085 case PROCESSOR_COREI7:
3632d14b 1086 case PROCESSOR_L1OM:
fbf3f584 1087 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
ccc9c027
L		 1088 patt = alt_long_patt;
1089 else
1090 patt = f32_patt;
1091 break;
1092 case PROCESSOR_GENERIC64:
76bc74dc 1093 patt = alt_long_patt;
ccc9c027 1094 break;
4eed87de 1095 }
ccc9c027
L		 1096 }
1097
76bc74dc
L		 1098 if (patt == f32_patt)
1099 {
1100 /* If the padding is less than 15 bytes, we use the normal
1101 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1102 its offset. */
1103 int limit;
76ba9986 1104
711eedef
L		 1105 /* For 64bit, the limit is 3 bytes. */
1106 if (flag_code == CODE_64BIT
1107 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1108 limit = 3;
1109 else
1110 limit = 15;
1111 if (count < limit)
76bc74dc
L		 1112 memcpy (fragP->fr_literal + fragP->fr_fix,
1113 patt[count - 1], count);
1114 else
1115 {
1116 memcpy (fragP->fr_literal + fragP->fr_fix,
1117 jump_31, count);
1118 /* Adjust jump offset. */
1119 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1120 }
1121 }
1122 else
1123 {
1124 /* Maximum length of an instruction is 15 byte. If the
1125 padding is greater than 15 bytes and we don't use jump,
1126 we have to break it into smaller pieces. */
1127 int padding = count;
1128 while (padding > 15)
1129 {
1130 padding -= 15;
1131 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1132 patt [14], 15);
1133 }
1134
1135 if (padding)
1136 memcpy (fragP->fr_literal + fragP->fr_fix,
1137 patt [padding - 1], padding);
1138 }
ccc9c027 1139 }
33fef721 1140 fragP->fr_var = count;
252b5132
RH		 1141}
1142
c6fb90c8 1143static INLINE int
0dfbf9d7 1144operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1145{
0dfbf9d7 1146 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1147 {
1148 case 3:
0dfbf9d7 1149 if (x->array[2])
c6fb90c8
L		 1150 return 0;
1151 case 2:
0dfbf9d7 1152 if (x->array[1])
c6fb90c8
L		 1153 return 0;
1154 case 1:
0dfbf9d7 1155 return !x->array[0];
c6fb90c8
L		 1156 default:
1157 abort ();
1158 }
40fb9820
L		 1159}
1160
c6fb90c8 1161static INLINE void
0dfbf9d7 1162operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1163{
0dfbf9d7 1164 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1165 {
1166 case 3:
0dfbf9d7 1167 x->array[2] = v;
c6fb90c8 1168 case 2:
0dfbf9d7 1169 x->array[1] = v;
c6fb90c8 1170 case 1:
0dfbf9d7 1171 x->array[0] = v;
c6fb90c8
L		 1172 break;
1173 default:
1174 abort ();
1175 }
1176}
40fb9820 1177
c6fb90c8 1178static INLINE int
0dfbf9d7
L		 1179operand_type_equal (const union i386_operand_type *x,
1180 const union i386_operand_type *y)
c6fb90c8 1181{
0dfbf9d7 1182 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1183 {
1184 case 3:
0dfbf9d7 1185 if (x->array[2] != y->array[2])
c6fb90c8
L		 1186 return 0;
1187 case 2:
0dfbf9d7 1188 if (x->array[1] != y->array[1])
c6fb90c8
L		 1189 return 0;
1190 case 1:
0dfbf9d7 1191 return x->array[0] == y->array[0];
c6fb90c8
L		 1192 break;
1193 default:
1194 abort ();
1195 }
1196}
40fb9820 1197
0dfbf9d7
L		 1198static INLINE int
1199cpu_flags_all_zero (const union i386_cpu_flags *x)
1200{
1201 switch (ARRAY_SIZE(x->array))
1202 {
1203 case 3:
1204 if (x->array[2])
1205 return 0;
1206 case 2:
1207 if (x->array[1])
1208 return 0;
1209 case 1:
1210 return !x->array[0];
1211 default:
1212 abort ();
1213 }
1214}
1215
1216static INLINE void
1217cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1218{
1219 switch (ARRAY_SIZE(x->array))
1220 {
1221 case 3:
1222 x->array[2] = v;
1223 case 2:
1224 x->array[1] = v;
1225 case 1:
1226 x->array[0] = v;
1227 break;
1228 default:
1229 abort ();
1230 }
1231}
1232
1233static INLINE int
1234cpu_flags_equal (const union i386_cpu_flags *x,
1235 const union i386_cpu_flags *y)
1236{
1237 switch (ARRAY_SIZE(x->array))
1238 {
1239 case 3:
1240 if (x->array[2] != y->array[2])
1241 return 0;
1242 case 2:
1243 if (x->array[1] != y->array[1])
1244 return 0;
1245 case 1:
1246 return x->array[0] == y->array[0];
1247 break;
1248 default:
1249 abort ();
1250 }
1251}
c6fb90c8
L		 1252
1253static INLINE int
1254cpu_flags_check_cpu64 (i386_cpu_flags f)
1255{
1256 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1257 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1258}
1259
c6fb90c8
L		 1260static INLINE i386_cpu_flags
1261cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1262{
c6fb90c8
L		 1263 switch (ARRAY_SIZE (x.array))
1264 {
1265 case 3:
1266 x.array [2] &= y.array [2];
1267 case 2:
1268 x.array [1] &= y.array [1];
1269 case 1:
1270 x.array [0] &= y.array [0];
1271 break;
1272 default:
1273 abort ();
1274 }
1275 return x;
1276}
40fb9820 1277
c6fb90c8
L		 1278static INLINE i386_cpu_flags
1279cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1280{
c6fb90c8 1281 switch (ARRAY_SIZE (x.array))
40fb9820 1282 {
c6fb90c8
L		 1283 case 3:
1284 x.array [2] |= y.array [2];
1285 case 2:
1286 x.array [1] |= y.array [1];
1287 case 1:
1288 x.array [0] |= y.array [0];
40fb9820
L		 1289 break;
1290 default:
1291 abort ();
1292 }
40fb9820
L		 1293 return x;
1294}
1295
309d3373
JB		 1296static INLINE i386_cpu_flags
1297cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1298{
1299 switch (ARRAY_SIZE (x.array))
1300 {
1301 case 3:
1302 x.array [2] &= ~y.array [2];
1303 case 2:
1304 x.array [1] &= ~y.array [1];
1305 case 1:
1306 x.array [0] &= ~y.array [0];
1307 break;
1308 default:
1309 abort ();
1310 }
1311 return x;
1312}
1313
c0f3af97
L		 1314#define CPU_FLAGS_ARCH_MATCH 0x1
1315#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1316#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1317#define CPU_FLAGS_PCLMUL_MATCH 0x8
1318#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1319
a5ff0eb2 1320#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1321 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1322 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1323#define CPU_FLAGS_PERFECT_MATCH \
1324 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1325
1326/* Return CPU flags match bits. */
3629bb00 1327
40fb9820 1328static int
d3ce72d0 1329cpu_flags_match (const insn_template *t)
40fb9820 1330{
c0f3af97
L		 1331 i386_cpu_flags x = t->cpu_flags;
1332 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1333
1334 x.bitfield.cpu64 = 0;
1335 x.bitfield.cpuno64 = 0;
1336
0dfbf9d7 1337 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1338 {
1339 /* This instruction is available on all archs. */
1340 match |= CPU_FLAGS_32BIT_MATCH;
1341 }
3629bb00
L		 1342 else
1343 {
c0f3af97 1344 /* This instruction is available only on some archs. */
3629bb00
L		 1345 i386_cpu_flags cpu = cpu_arch_flags;
1346
1347 cpu.bitfield.cpu64 = 0;
1348 cpu.bitfield.cpuno64 = 0;
1349 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1350 if (!cpu_flags_all_zero (&cpu))
1351 {
a5ff0eb2
L		 1352 if (x.bitfield.cpuavx)
1353 {
ce2f5b3c 1354 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1355 if (cpu.bitfield.cpuavx)
1356 {
1357 /* Check SSE2AVX. */
1358 if (!t->opcode_modifier.sse2avx|| sse2avx)
1359 {
1360 match |= (CPU_FLAGS_ARCH_MATCH
1361 | CPU_FLAGS_AVX_MATCH);
1362 /* Check AES. */
1363 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1364 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1365 /* Check PCLMUL. */
1366 if (!x.bitfield.cpupclmul
1367 || cpu.bitfield.cpupclmul)
1368 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1369 }
1370 }
1371 else
1372 match |= CPU_FLAGS_ARCH_MATCH;
1373 }
1374 else
c0f3af97
L		 1375 match |= CPU_FLAGS_32BIT_MATCH;
1376 }
3629bb00 1377 }
c0f3af97 1378 return match;
40fb9820
L		 1379}
1380
c6fb90c8
L		 1381static INLINE i386_operand_type
1382operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1383{
c6fb90c8
L		 1384 switch (ARRAY_SIZE (x.array))
1385 {
1386 case 3:
1387 x.array [2] &= y.array [2];
1388 case 2:
1389 x.array [1] &= y.array [1];
1390 case 1:
1391 x.array [0] &= y.array [0];
1392 break;
1393 default:
1394 abort ();
1395 }
1396 return x;
40fb9820
L		 1397}
1398
c6fb90c8
L		 1399static INLINE i386_operand_type
1400operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1401{
c6fb90c8 1402 switch (ARRAY_SIZE (x.array))
40fb9820 1403 {
c6fb90c8
L		 1404 case 3:
1405 x.array [2] |= y.array [2];
1406 case 2:
1407 x.array [1] |= y.array [1];
1408 case 1:
1409 x.array [0] |= y.array [0];
40fb9820
L		 1410 break;
1411 default:
1412 abort ();
1413 }
c6fb90c8
L		 1414 return x;
1415}
40fb9820 1416
c6fb90c8
L		 1417static INLINE i386_operand_type
1418operand_type_xor (i386_operand_type x, i386_operand_type y)
1419{
1420 switch (ARRAY_SIZE (x.array))
1421 {
1422 case 3:
1423 x.array [2] ^= y.array [2];
1424 case 2:
1425 x.array [1] ^= y.array [1];
1426 case 1:
1427 x.array [0] ^= y.array [0];
1428 break;
1429 default:
1430 abort ();
1431 }
40fb9820
L		 1432 return x;
1433}
1434
1435static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1436static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1437static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1438static const i386_operand_type inoutportreg
1439 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1440static const i386_operand_type reg16_inoutportreg
1441 = OPERAND_TYPE_REG16_INOUTPORTREG;
1442static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1443static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1444static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1445static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1446static const i386_operand_type anydisp
1447 = OPERAND_TYPE_ANYDISP;
40fb9820 1448static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1449static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
40fb9820
L		 1450static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1451static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1452static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1453static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1454static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1455static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1456static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1457static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1458static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1459static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1460
1461enum operand_type
1462{
1463 reg,
40fb9820
L		 1464 imm,
1465 disp,
1466 anymem
1467};
1468
c6fb90c8 1469static INLINE int
40fb9820
L		 1470operand_type_check (i386_operand_type t, enum operand_type c)
1471{
1472 switch (c)
1473 {
1474 case reg:
1475 return (t.bitfield.reg8
1476 || t.bitfield.reg16
1477 || t.bitfield.reg32
1478 || t.bitfield.reg64);
1479
40fb9820
L		 1480 case imm:
1481 return (t.bitfield.imm8
1482 || t.bitfield.imm8s
1483 || t.bitfield.imm16
1484 || t.bitfield.imm32
1485 || t.bitfield.imm32s
1486 || t.bitfield.imm64);
1487
1488 case disp:
1489 return (t.bitfield.disp8
1490 || t.bitfield.disp16
1491 || t.bitfield.disp32
1492 || t.bitfield.disp32s
1493 || t.bitfield.disp64);
1494
1495 case anymem:
1496 return (t.bitfield.disp8
1497 || t.bitfield.disp16
1498 || t.bitfield.disp32
1499 || t.bitfield.disp32s
1500 || t.bitfield.disp64
1501 || t.bitfield.baseindex);
1502
1503 default:
1504 abort ();
1505 }
2cfe26b6
AM		 1506
1507 return 0;
40fb9820
L		 1508}
1509
5c07affc
L		 1510/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1511 operand J for instruction template T. */
1512
1513static INLINE int
d3ce72d0 1514match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1515{
1516 return !((i.types[j].bitfield.byte
1517 && !t->operand_types[j].bitfield.byte)
1518 || (i.types[j].bitfield.word
1519 && !t->operand_types[j].bitfield.word)
1520 || (i.types[j].bitfield.dword
1521 && !t->operand_types[j].bitfield.dword)
1522 || (i.types[j].bitfield.qword
1523 && !t->operand_types[j].bitfield.qword));
1524}
1525
1526/* Return 1 if there is no conflict in any size on operand J for
1527 instruction template T. */
1528
1529static INLINE int
d3ce72d0 1530match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1531{
1532 return (match_reg_size (t, j)
1533 && !((i.types[j].bitfield.unspecified
1534 && !t->operand_types[j].bitfield.unspecified)
1535 || (i.types[j].bitfield.fword
1536 && !t->operand_types[j].bitfield.fword)
1537 || (i.types[j].bitfield.tbyte
1538 && !t->operand_types[j].bitfield.tbyte)
1539 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1540 && !t->operand_types[j].bitfield.xmmword)
1541 || (i.types[j].bitfield.ymmword
1542 && !t->operand_types[j].bitfield.ymmword)));
5c07affc
L		 1543}
1544
1545/* Return 1 if there is no size conflict on any operands for
1546 instruction template T. */
1547
1548static INLINE int
d3ce72d0 1549operand_size_match (const insn_template *t)
5c07affc
L		 1550{
1551 unsigned int j;
1552 int match = 1;
1553
1554 /* Don't check jump instructions. */
1555 if (t->opcode_modifier.jump
1556 || t->opcode_modifier.jumpbyte
1557 || t->opcode_modifier.jumpdword
1558 || t->opcode_modifier.jumpintersegment)
1559 return match;
1560
1561 /* Check memory and accumulator operand size. */
1562 for (j = 0; j < i.operands; j++)
1563 {
1564 if (t->operand_types[j].bitfield.anysize)
1565 continue;
1566
1567 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1568 {
1569 match = 0;
1570 break;
1571 }
1572
1573 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1574 {
1575 match = 0;
1576 break;
1577 }
1578 }
1579
891edac4 1580 if (match)
5c07affc 1581 return match;
891edac4
L		 1582 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1583 {
1584mismatch:
86e026a4 1585 i.error = operand_size_mismatch;
891edac4
L		 1586 return 0;
1587 }
5c07affc
L		 1588
1589 /* Check reverse. */
9c2799c2 1590 gas_assert (i.operands == 2);
5c07affc
L		 1591
1592 match = 1;
1593 for (j = 0; j < 2; j++)
1594 {
1595 if (t->operand_types[j].bitfield.acc
1596 && !match_reg_size (t, j ? 0 : 1))
891edac4 1597 goto mismatch;
5c07affc
L		 1598
1599 if (i.types[j].bitfield.mem
1600 && !match_mem_size (t, j ? 0 : 1))
891edac4 1601 goto mismatch;
5c07affc
L		 1602 }
1603
1604 return match;
1605}
1606
c6fb90c8 1607static INLINE int
40fb9820
L		 1608operand_type_match (i386_operand_type overlap,
1609 i386_operand_type given)
1610{
1611 i386_operand_type temp = overlap;
1612
1613 temp.bitfield.jumpabsolute = 0;
7d5e4556 1614 temp.bitfield.unspecified = 0;
5c07affc
L		 1615 temp.bitfield.byte = 0;
1616 temp.bitfield.word = 0;
1617 temp.bitfield.dword = 0;
1618 temp.bitfield.fword = 0;
1619 temp.bitfield.qword = 0;
1620 temp.bitfield.tbyte = 0;
1621 temp.bitfield.xmmword = 0;
c0f3af97 1622 temp.bitfield.ymmword = 0;
0dfbf9d7 1623 if (operand_type_all_zero (&temp))
891edac4 1624 goto mismatch;
40fb9820 1625
891edac4
L		 1626 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1627 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1628 return 1;
1629
1630mismatch:
a65babc9 1631 i.error = operand_type_mismatch;
891edac4 1632 return 0;
40fb9820
L		 1633}
1634
7d5e4556 1635/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1636 unless the expected operand type register overlap is null.
1637 Note that Acc in a template matches every size of reg. */
1638
c6fb90c8 1639static INLINE int
40fb9820
L		 1640operand_type_register_match (i386_operand_type m0,
1641 i386_operand_type g0,
1642 i386_operand_type t0,
1643 i386_operand_type m1,
1644 i386_operand_type g1,
1645 i386_operand_type t1)
1646{
1647 if (!operand_type_check (g0, reg))
1648 return 1;
1649
1650 if (!operand_type_check (g1, reg))
1651 return 1;
1652
1653 if (g0.bitfield.reg8 == g1.bitfield.reg8
1654 && g0.bitfield.reg16 == g1.bitfield.reg16
1655 && g0.bitfield.reg32 == g1.bitfield.reg32
1656 && g0.bitfield.reg64 == g1.bitfield.reg64)
1657 return 1;
1658
1659 if (m0.bitfield.acc)
1660 {
1661 t0.bitfield.reg8 = 1;
1662 t0.bitfield.reg16 = 1;
1663 t0.bitfield.reg32 = 1;
1664 t0.bitfield.reg64 = 1;
1665 }
1666
1667 if (m1.bitfield.acc)
1668 {
1669 t1.bitfield.reg8 = 1;
1670 t1.bitfield.reg16 = 1;
1671 t1.bitfield.reg32 = 1;
1672 t1.bitfield.reg64 = 1;
1673 }
1674
891edac4
L		 1675 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1676 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1677 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1678 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1679 return 1;
1680
a65babc9 1681 i.error = register_type_mismatch;
891edac4
L		 1682
1683 return 0;
40fb9820
L		 1684}
1685
252b5132 1686static INLINE unsigned int
40fb9820 1687mode_from_disp_size (i386_operand_type t)
252b5132 1688{
40fb9820
L		 1689 if (t.bitfield.disp8)
1690 return 1;
1691 else if (t.bitfield.disp16
1692 || t.bitfield.disp32
1693 || t.bitfield.disp32s)
1694 return 2;
1695 else
1696 return 0;
252b5132
RH		 1697}
1698
1699static INLINE int
e3bb37b5 1700fits_in_signed_byte (offsetT num)
252b5132
RH		 1701{
1702 return (num >= -128) && (num <= 127);
47926f60 1703}
252b5132
RH		 1704
1705static INLINE int
e3bb37b5 1706fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1707{
1708 return (num & 0xff) == num;
47926f60 1709}
252b5132
RH		 1710
1711static INLINE int
e3bb37b5 1712fits_in_unsigned_word (offsetT num)
252b5132
RH		 1713{
1714 return (num & 0xffff) == num;
47926f60 1715}
252b5132
RH		 1716
1717static INLINE int
e3bb37b5 1718fits_in_signed_word (offsetT num)
252b5132
RH		 1719{
1720 return (-32768 <= num) && (num <= 32767);
47926f60 1721}
2a962e6d 1722
3e73aa7c 1723static INLINE int
e3bb37b5 1724fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1725{
1726#ifndef BFD64
1727 return 1;
1728#else
1729 return (!(((offsetT) -1 << 31) & num)
1730 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1731#endif
1732} /* fits_in_signed_long() */
2a962e6d 1733
3e73aa7c 1734static INLINE int
e3bb37b5 1735fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1736{
1737#ifndef BFD64
1738 return 1;
1739#else
1740 return (num & (((offsetT) 2 << 31) - 1)) == num;
1741#endif
1742} /* fits_in_unsigned_long() */
252b5132 1743
a683cc34
SP		 1744static INLINE int
1745fits_in_imm4 (offsetT num)
1746{
1747 return (num & 0xf) == num;
1748}
1749
40fb9820 1750static i386_operand_type
e3bb37b5 1751smallest_imm_type (offsetT num)
252b5132 1752{
40fb9820 1753 i386_operand_type t;
7ab9ffdd 1754
0dfbf9d7 1755 operand_type_set (&t, 0);
40fb9820
L		 1756 t.bitfield.imm64 = 1;
1757
1758 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1759 {
1760 /* This code is disabled on the 486 because all the Imm1 forms
1761 in the opcode table are slower on the i486. They're the
1762 versions with the implicitly specified single-position
1763 displacement, which has another syntax if you really want to
1764 use that form. */
40fb9820
L		 1765 t.bitfield.imm1 = 1;
1766 t.bitfield.imm8 = 1;
1767 t.bitfield.imm8s = 1;
1768 t.bitfield.imm16 = 1;
1769 t.bitfield.imm32 = 1;
1770 t.bitfield.imm32s = 1;
1771 }
1772 else if (fits_in_signed_byte (num))
1773 {
1774 t.bitfield.imm8 = 1;
1775 t.bitfield.imm8s = 1;
1776 t.bitfield.imm16 = 1;
1777 t.bitfield.imm32 = 1;
1778 t.bitfield.imm32s = 1;
1779 }
1780 else if (fits_in_unsigned_byte (num))
1781 {
1782 t.bitfield.imm8 = 1;
1783 t.bitfield.imm16 = 1;
1784 t.bitfield.imm32 = 1;
1785 t.bitfield.imm32s = 1;
1786 }
1787 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1788 {
1789 t.bitfield.imm16 = 1;
1790 t.bitfield.imm32 = 1;
1791 t.bitfield.imm32s = 1;
1792 }
1793 else if (fits_in_signed_long (num))
1794 {
1795 t.bitfield.imm32 = 1;
1796 t.bitfield.imm32s = 1;
1797 }
1798 else if (fits_in_unsigned_long (num))
1799 t.bitfield.imm32 = 1;
1800
1801 return t;
47926f60 1802}
252b5132 1803
847f7ad4 1804static offsetT
e3bb37b5 1805offset_in_range (offsetT val, int size)
847f7ad4 1806{
508866be 1807 addressT mask;
ba2adb93 1808
847f7ad4
AM		 1809 switch (size)
1810 {
508866be
L		 1811 case 1: mask = ((addressT) 1 << 8) - 1; break;
1812 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1813 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1814#ifdef BFD64
1815 case 8: mask = ((addressT) 2 << 63) - 1; break;
1816#endif
47926f60 1817 default: abort ();
847f7ad4
AM		 1818 }
1819
9de868bf
L		 1820#ifdef BFD64
1821 /* If BFD64, sign extend val for 32bit address mode. */
1822 if (flag_code != CODE_64BIT
1823 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 1824 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1825 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 1826#endif
ba2adb93 1827
47926f60 1828 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1829 {
1830 char buf1[40], buf2[40];
1831
1832 sprint_value (buf1, val);
1833 sprint_value (buf2, val & mask);
1834 as_warn (_("%s shortened to %s"), buf1, buf2);
1835 }
1836 return val & mask;
1837}
1838
c32fa91d
L		 1839enum PREFIX_GROUP
1840{
1841 PREFIX_EXIST = 0,
1842 PREFIX_LOCK,
1843 PREFIX_REP,
1844 PREFIX_OTHER
1845};
1846
1847/* Returns
1848 a. PREFIX_EXIST if attempting to add a prefix where one from the
1849 same class already exists.
1850 b. PREFIX_LOCK if lock prefix is added.
1851 c. PREFIX_REP if rep/repne prefix is added.
1852 d. PREFIX_OTHER if other prefix is added.
1853 */
1854
1855static enum PREFIX_GROUP
e3bb37b5 1856add_prefix (unsigned int prefix)
252b5132 1857{
c32fa91d 1858 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 1859 unsigned int q;
252b5132 1860
29b0f896
AM		 1861 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1862 && flag_code == CODE_64BIT)
b1905489 1863 {
161a04f6
L		 1864 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1865 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1866 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 1867 ret = PREFIX_EXIST;
b1905489
JB		 1868 q = REX_PREFIX;
1869 }
3e73aa7c 1870 else
b1905489
JB		 1871 {
1872 switch (prefix)
1873 {
1874 default:
1875 abort ();
1876
1877 case CS_PREFIX_OPCODE:
1878 case DS_PREFIX_OPCODE:
1879 case ES_PREFIX_OPCODE:
1880 case FS_PREFIX_OPCODE:
1881 case GS_PREFIX_OPCODE:
1882 case SS_PREFIX_OPCODE:
1883 q = SEG_PREFIX;
1884 break;
1885
1886 case REPNE_PREFIX_OPCODE:
1887 case REPE_PREFIX_OPCODE:
c32fa91d
L		 1888 q = REP_PREFIX;
1889 ret = PREFIX_REP;
1890 break;
1891
b1905489 1892 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 1893 q = LOCK_PREFIX;
1894 ret = PREFIX_LOCK;
b1905489
JB		 1895 break;
1896
1897 case FWAIT_OPCODE:
1898 q = WAIT_PREFIX;
1899 break;
1900
1901 case ADDR_PREFIX_OPCODE:
1902 q = ADDR_PREFIX;
1903 break;
1904
1905 case DATA_PREFIX_OPCODE:
1906 q = DATA_PREFIX;
1907 break;
1908 }
1909 if (i.prefix[q] != 0)
c32fa91d 1910 ret = PREFIX_EXIST;
b1905489 1911 }
252b5132 1912
b1905489 1913 if (ret)
252b5132 1914 {
b1905489
JB		 1915 if (!i.prefix[q])
1916 ++i.prefixes;
1917 i.prefix[q] |= prefix;
252b5132 1918 }
b1905489
JB		 1919 else
1920 as_bad (_("same type of prefix used twice"));
252b5132 1921
252b5132
RH		 1922 return ret;
1923}
1924
1925static void
78f12dd3 1926update_code_flag (int value, int check)
eecb386c 1927{
78f12dd3
L		 1928 PRINTF_LIKE ((*as_error));
1929
1e9cc1c2 1930 flag_code = (enum flag_code) value;
40fb9820
L		 1931 if (flag_code == CODE_64BIT)
1932 {
1933 cpu_arch_flags.bitfield.cpu64 = 1;
1934 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 1935 }
1936 else
1937 {
1938 cpu_arch_flags.bitfield.cpu64 = 0;
1939 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 1940 }
1941 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 1942 {
78f12dd3
L		 1943 if (check)
1944 as_error = as_fatal;
1945 else
1946 as_error = as_bad;
1947 (*as_error) (_("64bit mode not supported on `%s'."),
1948 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 1949 }
40fb9820 1950 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 1951 {
78f12dd3
L		 1952 if (check)
1953 as_error = as_fatal;
1954 else
1955 as_error = as_bad;
1956 (*as_error) (_("32bit mode not supported on `%s'."),
1957 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 1958 }
eecb386c
AM		 1959 stackop_size = '\0';
1960}
1961
78f12dd3
L		 1962static void
1963set_code_flag (int value)
1964{
1965 update_code_flag (value, 0);
1966}
1967
eecb386c 1968static void
e3bb37b5 1969set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1970{
1e9cc1c2 1971 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 1972 if (flag_code != CODE_16BIT)
1973 abort ();
1974 cpu_arch_flags.bitfield.cpu64 = 0;
1975 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 1976 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1977}
1978
1979static void
e3bb37b5 1980set_intel_syntax (int syntax_flag)
252b5132
RH		 1981{
1982 /* Find out if register prefixing is specified. */
1983 int ask_naked_reg = 0;
1984
1985 SKIP_WHITESPACE ();
29b0f896 1986 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1987 {
1988 char *string = input_line_pointer;
1989 int e = get_symbol_end ();
1990
47926f60 1991 if (strcmp (string, "prefix") == 0)
252b5132 1992 ask_naked_reg = 1;
47926f60 1993 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1994 ask_naked_reg = -1;
1995 else
d0b47220 1996 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1997 *input_line_pointer = e;
1998 }
1999 demand_empty_rest_of_line ();
c3332e24 2000
252b5132
RH		 2001 intel_syntax = syntax_flag;
2002
2003 if (ask_naked_reg == 0)
f86103b7
AM		 2004 allow_naked_reg = (intel_syntax
2005 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2006 else
2007 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2008
ee86248c 2009 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2010
e4a3b5a4 2011 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2012 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2013 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2014}
2015
1efbbeb4
L		 2016static void
2017set_intel_mnemonic (int mnemonic_flag)
2018{
e1d4d893 2019 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2020}
2021
db51cc60
L		 2022static void
2023set_allow_index_reg (int flag)
2024{
2025 allow_index_reg = flag;
2026}
2027
cb19c032
L		 2028static void
2029set_sse_check (int dummy ATTRIBUTE_UNUSED)
2030{
2031 SKIP_WHITESPACE ();
2032
2033 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2034 {
2035 char *string = input_line_pointer;
2036 int e = get_symbol_end ();
2037
2038 if (strcmp (string, "none") == 0)
2039 sse_check = sse_check_none;
2040 else if (strcmp (string, "warning") == 0)
2041 sse_check = sse_check_warning;
2042 else if (strcmp (string, "error") == 0)
2043 sse_check = sse_check_error;
2044 else
2045 as_bad (_("bad argument to sse_check directive."));
2046 *input_line_pointer = e;
2047 }
2048 else
2049 as_bad (_("missing argument for sse_check directive"));
2050
2051 demand_empty_rest_of_line ();
2052}
2053
8a9036a4
L		 2054static void
2055check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2056 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2057{
2058#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2059 static const char *arch;
2060
2061 /* Intel LIOM is only supported on ELF. */
2062 if (!IS_ELF)
2063 return;
2064
2065 if (!arch)
2066 {
2067 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2068 use default_arch. */
2069 arch = cpu_arch_name;
2070 if (!arch)
2071 arch = default_arch;
2072 }
2073
3632d14b 2074 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2075 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2076 || new_flag.bitfield.cpul1om)
8a9036a4 2077 return;
76ba9986 2078
8a9036a4
L		 2079 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2080#endif
2081}
2082
e413e4e9 2083static void
e3bb37b5 2084set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2085{
47926f60 2086 SKIP_WHITESPACE ();
e413e4e9 2087
29b0f896 2088 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 2089 {
2090 char *string = input_line_pointer;
2091 int e = get_symbol_end ();
91d6fa6a 2092 unsigned int j;
40fb9820 2093 i386_cpu_flags flags;
e413e4e9 2094
91d6fa6a 2095 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2096 {
91d6fa6a 2097 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2098 {
91d6fa6a 2099 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2100
5c6af06e
JB		 2101 if (*string != '.')
2102 {
91d6fa6a 2103 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2104 cpu_sub_arch_name = NULL;
91d6fa6a 2105 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2106 if (flag_code == CODE_64BIT)
2107 {
2108 cpu_arch_flags.bitfield.cpu64 = 1;
2109 cpu_arch_flags.bitfield.cpuno64 = 0;
2110 }
2111 else
2112 {
2113 cpu_arch_flags.bitfield.cpu64 = 0;
2114 cpu_arch_flags.bitfield.cpuno64 = 1;
2115 }
91d6fa6a
NC		 2116 cpu_arch_isa = cpu_arch[j].type;
2117 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2118 if (!cpu_arch_tune_set)
2119 {
2120 cpu_arch_tune = cpu_arch_isa;
2121 cpu_arch_tune_flags = cpu_arch_isa_flags;
2122 }
5c6af06e
JB		 2123 break;
2124 }
40fb9820 2125
309d3373
JB		 2126 if (strncmp (string + 1, "no", 2))
2127 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 2128 cpu_arch[j].flags);
309d3373
JB		 2129 else
2130 flags = cpu_flags_and_not (cpu_arch_flags,
91d6fa6a 2131 cpu_arch[j].flags);
0dfbf9d7 2132 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2133 {
6305a203
L		 2134 if (cpu_sub_arch_name)
2135 {
2136 char *name = cpu_sub_arch_name;
2137 cpu_sub_arch_name = concat (name,
91d6fa6a 2138 cpu_arch[j].name,
1bf57e9f 2139 (const char *) NULL);
6305a203
L		 2140 free (name);
2141 }
2142 else
91d6fa6a 2143 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2144 cpu_arch_flags = flags;
5c6af06e
JB		 2145 }
2146 *input_line_pointer = e;
2147 demand_empty_rest_of_line ();
2148 return;
e413e4e9
AM		 2149 }
2150 }
91d6fa6a 2151 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2152 as_bad (_("no such architecture: `%s'"), string);
2153
2154 *input_line_pointer = e;
2155 }
2156 else
2157 as_bad (_("missing cpu architecture"));
2158
fddf5b5b
AM		 2159 no_cond_jump_promotion = 0;
2160 if (*input_line_pointer == ','
29b0f896 2161 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 2162 {
2163 char *string = ++input_line_pointer;
2164 int e = get_symbol_end ();
2165
2166 if (strcmp (string, "nojumps") == 0)
2167 no_cond_jump_promotion = 1;
2168 else if (strcmp (string, "jumps") == 0)
2169 ;
2170 else
2171 as_bad (_("no such architecture modifier: `%s'"), string);
2172
2173 *input_line_pointer = e;
2174 }
2175
e413e4e9
AM		 2176 demand_empty_rest_of_line ();
2177}
2178
8a9036a4
L		 2179enum bfd_architecture
2180i386_arch (void)
2181{
3632d14b 2182 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2183 {
2184 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2185 || flag_code != CODE_64BIT)
2186 as_fatal (_("Intel L1OM is 64bit ELF only"));
2187 return bfd_arch_l1om;
2188 }
2189 else
2190 return bfd_arch_i386;
2191}
2192
b9d79e03
JH		 2193unsigned long
2194i386_mach ()
2195{
2196 if (!strcmp (default_arch, "x86_64"))
8a9036a4 2197 {
3632d14b 2198 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2199 {
2200 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2201 as_fatal (_("Intel L1OM is 64bit ELF only"));
2202 return bfd_mach_l1om;
2203 }
2204 else
2205 return bfd_mach_x86_64;
2206 }
b9d79e03
JH		 2207 else if (!strcmp (default_arch, "i386"))
2208 return bfd_mach_i386_i386;
2209 else
2210 as_fatal (_("Unknown architecture"));
2211}
b9d79e03 2212\f
252b5132
RH		 2213void
2214md_begin ()
2215{
2216 const char *hash_err;
2217
47926f60 2218 /* Initialize op_hash hash table. */
252b5132
RH		 2219 op_hash = hash_new ();
2220
2221 {
d3ce72d0 2222 const insn_template *optab;
29b0f896 2223 templates *core_optab;
252b5132 2224
47926f60
KH		 2225 /* Setup for loop. */
2226 optab = i386_optab;
252b5132
RH		 2227 core_optab = (templates *) xmalloc (sizeof (templates));
2228 core_optab->start = optab;
2229
2230 while (1)
2231 {
2232 ++optab;
2233 if (optab->name == NULL
2234 || strcmp (optab->name, (optab - 1)->name) != 0)
2235 {
2236 /* different name --> ship out current template list;
47926f60 2237 add to hash table; & begin anew. */
252b5132
RH		 2238 core_optab->end = optab;
2239 hash_err = hash_insert (op_hash,
2240 (optab - 1)->name,
5a49b8ac 2241 (void *) core_optab);
252b5132
RH		 2242 if (hash_err)
2243 {
252b5132
RH		 2244 as_fatal (_("Internal Error: Can't hash %s: %s"),
2245 (optab - 1)->name,
2246 hash_err);
2247 }
2248 if (optab->name == NULL)
2249 break;
2250 core_optab = (templates *) xmalloc (sizeof (templates));
2251 core_optab->start = optab;
2252 }
2253 }
2254 }
2255
47926f60 2256 /* Initialize reg_hash hash table. */
252b5132
RH		 2257 reg_hash = hash_new ();
2258 {
29b0f896 2259 const reg_entry *regtab;
c3fe08fa 2260 unsigned int regtab_size = i386_regtab_size;
252b5132 2261
c3fe08fa 2262 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2263 {
5a49b8ac 2264 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2265 if (hash_err)
3e73aa7c
JH		 2266 as_fatal (_("Internal Error: Can't hash %s: %s"),
2267 regtab->reg_name,
2268 hash_err);
252b5132
RH		 2269 }
2270 }
2271
47926f60 2272 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2273 {
29b0f896
AM		 2274 int c;
2275 char *p;
252b5132
RH		 2276
2277 for (c = 0; c < 256; c++)
2278 {
3882b010 2279 if (ISDIGIT (c))
252b5132
RH		 2280 {
2281 digit_chars[c] = c;
2282 mnemonic_chars[c] = c;
2283 register_chars[c] = c;
2284 operand_chars[c] = c;
2285 }
3882b010 2286 else if (ISLOWER (c))
252b5132
RH		 2287 {
2288 mnemonic_chars[c] = c;
2289 register_chars[c] = c;
2290 operand_chars[c] = c;
2291 }
3882b010 2292 else if (ISUPPER (c))
252b5132 2293 {
3882b010 2294 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2295 register_chars[c] = mnemonic_chars[c];
2296 operand_chars[c] = c;
2297 }
2298
3882b010 2299 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2300 identifier_chars[c] = c;
2301 else if (c >= 128)
2302 {
2303 identifier_chars[c] = c;
2304 operand_chars[c] = c;
2305 }
2306 }
2307
2308#ifdef LEX_AT
2309 identifier_chars['@'] = '@';
32137342
NC		 2310#endif
2311#ifdef LEX_QM
2312 identifier_chars['?'] = '?';
2313 operand_chars['?'] = '?';
252b5132 2314#endif
252b5132 2315 digit_chars['-'] = '-';
c0f3af97 2316 mnemonic_chars['_'] = '_';
791fe849 2317 mnemonic_chars['-'] = '-';
0003779b 2318 mnemonic_chars['.'] = '.';
252b5132
RH		 2319 identifier_chars['_'] = '_';
2320 identifier_chars['.'] = '.';
2321
2322 for (p = operand_special_chars; *p != '\0'; p++)
2323 operand_chars[(unsigned char) *p] = *p;
2324 }
2325
2326#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2327 if (IS_ELF)
252b5132
RH		 2328 {
2329 record_alignment (text_section, 2);
2330 record_alignment (data_section, 2);
2331 record_alignment (bss_section, 2);
2332 }
2333#endif
a4447b93
RH		 2334
2335 if (flag_code == CODE_64BIT)
2336 {
2337 x86_dwarf2_return_column = 16;
2338 x86_cie_data_alignment = -8;
2339 }
2340 else
2341 {
2342 x86_dwarf2_return_column = 8;
2343 x86_cie_data_alignment = -4;
2344 }
252b5132
RH		 2345}
2346
2347void
e3bb37b5 2348i386_print_statistics (FILE *file)
252b5132
RH		 2349{
2350 hash_print_statistics (file, "i386 opcode", op_hash);
2351 hash_print_statistics (file, "i386 register", reg_hash);
2352}
2353\f
252b5132
RH		 2354#ifdef DEBUG386
2355
ce8a8b2f 2356/* Debugging routines for md_assemble. */
d3ce72d0 2357static void pte (insn_template *);
40fb9820 2358static void pt (i386_operand_type);
e3bb37b5
L		 2359static void pe (expressionS *);
2360static void ps (symbolS *);
252b5132
RH		 2361
2362static void
e3bb37b5 2363pi (char *line, i386_insn *x)
252b5132 2364{
09137c09 2365 unsigned int j;
252b5132
RH		 2366
2367 fprintf (stdout, "%s: template ", line);
2368 pte (&x->tm);
09f131f2
JH		 2369 fprintf (stdout, " address: base %s index %s scale %x\n",
2370 x->base_reg ? x->base_reg->reg_name : "none",
2371 x->index_reg ? x->index_reg->reg_name : "none",
2372 x->log2_scale_factor);
2373 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2374 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2375 fprintf (stdout, " sib: base %x index %x scale %x\n",
2376 x->sib.base, x->sib.index, x->sib.scale);
2377 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2378 (x->rex & REX_W) != 0,
2379 (x->rex & REX_R) != 0,
2380 (x->rex & REX_X) != 0,
2381 (x->rex & REX_B) != 0);
09137c09 2382 for (j = 0; j < x->operands; j++)
252b5132 2383 {
09137c09
SP		 2384 fprintf (stdout, " #%d: ", j + 1);
2385 pt (x->types[j]);
252b5132 2386 fprintf (stdout, "\n");
09137c09
SP		 2387 if (x->types[j].bitfield.reg8
2388 || x->types[j].bitfield.reg16
2389 || x->types[j].bitfield.reg32
2390 || x->types[j].bitfield.reg64
2391 || x->types[j].bitfield.regmmx
2392 || x->types[j].bitfield.regxmm
2393 || x->types[j].bitfield.regymm
2394 || x->types[j].bitfield.sreg2
2395 || x->types[j].bitfield.sreg3
2396 || x->types[j].bitfield.control
2397 || x->types[j].bitfield.debug
2398 || x->types[j].bitfield.test)
2399 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2400 if (operand_type_check (x->types[j], imm))
2401 pe (x->op[j].imms);
2402 if (operand_type_check (x->types[j], disp))
2403 pe (x->op[j].disps);
252b5132
RH		 2404 }
2405}
2406
2407static void
d3ce72d0 2408pte (insn_template *t)
252b5132 2409{
09137c09 2410 unsigned int j;
252b5132 2411 fprintf (stdout, " %d operands ", t->operands);
47926f60 2412 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2413 if (t->extension_opcode != None)
2414 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2415 if (t->opcode_modifier.d)
252b5132 2416 fprintf (stdout, "D");
40fb9820 2417 if (t->opcode_modifier.w)
252b5132
RH		 2418 fprintf (stdout, "W");
2419 fprintf (stdout, "\n");
09137c09 2420 for (j = 0; j < t->operands; j++)
252b5132 2421 {
09137c09
SP		 2422 fprintf (stdout, " #%d type ", j + 1);
2423 pt (t->operand_types[j]);
252b5132
RH		 2424 fprintf (stdout, "\n");
2425 }
2426}
2427
2428static void
e3bb37b5 2429pe (expressionS *e)
252b5132 2430{
24eab124 2431 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2432 fprintf (stdout, " add_number %ld (%lx)\n",
2433 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2434 if (e->X_add_symbol)
2435 {
2436 fprintf (stdout, " add_symbol ");
2437 ps (e->X_add_symbol);
2438 fprintf (stdout, "\n");
2439 }
2440 if (e->X_op_symbol)
2441 {
2442 fprintf (stdout, " op_symbol ");
2443 ps (e->X_op_symbol);
2444 fprintf (stdout, "\n");
2445 }
2446}
2447
2448static void
e3bb37b5 2449ps (symbolS *s)
252b5132
RH		 2450{
2451 fprintf (stdout, "%s type %s%s",
2452 S_GET_NAME (s),
2453 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2454 segment_name (S_GET_SEGMENT (s)));
2455}
2456
7b81dfbb 2457static struct type_name
252b5132 2458 {
40fb9820
L		 2459 i386_operand_type mask;
2460 const char *name;
252b5132 2461 }
7b81dfbb 2462const type_names[] =
252b5132 2463{
40fb9820
L		 2464 { OPERAND_TYPE_REG8, "r8" },
2465 { OPERAND_TYPE_REG16, "r16" },
2466 { OPERAND_TYPE_REG32, "r32" },
2467 { OPERAND_TYPE_REG64, "r64" },
2468 { OPERAND_TYPE_IMM8, "i8" },
2469 { OPERAND_TYPE_IMM8, "i8s" },
2470 { OPERAND_TYPE_IMM16, "i16" },
2471 { OPERAND_TYPE_IMM32, "i32" },
2472 { OPERAND_TYPE_IMM32S, "i32s" },
2473 { OPERAND_TYPE_IMM64, "i64" },
2474 { OPERAND_TYPE_IMM1, "i1" },
2475 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2476 { OPERAND_TYPE_DISP8, "d8" },
2477 { OPERAND_TYPE_DISP16, "d16" },
2478 { OPERAND_TYPE_DISP32, "d32" },
2479 { OPERAND_TYPE_DISP32S, "d32s" },
2480 { OPERAND_TYPE_DISP64, "d64" },
2481 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2482 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2483 { OPERAND_TYPE_CONTROL, "control reg" },
2484 { OPERAND_TYPE_TEST, "test reg" },
2485 { OPERAND_TYPE_DEBUG, "debug reg" },
2486 { OPERAND_TYPE_FLOATREG, "FReg" },
2487 { OPERAND_TYPE_FLOATACC, "FAcc" },
2488 { OPERAND_TYPE_SREG2, "SReg2" },
2489 { OPERAND_TYPE_SREG3, "SReg3" },
2490 { OPERAND_TYPE_ACC, "Acc" },
2491 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2492 { OPERAND_TYPE_REGMMX, "rMMX" },
2493 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2494 { OPERAND_TYPE_REGYMM, "rYMM" },
40fb9820 2495 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2496};
2497
2498static void
40fb9820 2499pt (i386_operand_type t)
252b5132 2500{
40fb9820 2501 unsigned int j;
c6fb90c8 2502 i386_operand_type a;
252b5132 2503
40fb9820 2504 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2505 {
2506 a = operand_type_and (t, type_names[j].mask);
0349dc08 2507 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2508 fprintf (stdout, "%s, ", type_names[j].name);
2509 }
252b5132
RH		 2510 fflush (stdout);
2511}
2512
2513#endif /* DEBUG386 */
2514\f
252b5132 2515static bfd_reloc_code_real_type
3956db08 2516reloc (unsigned int size,
64e74474
AM		 2517 int pcrel,
2518 int sign,
2519 bfd_reloc_code_real_type other)
252b5132 2520{
47926f60 2521 if (other != NO_RELOC)
3956db08 2522 {
91d6fa6a 2523 reloc_howto_type *rel;
3956db08
JB		 2524
2525 if (size == 8)
2526 switch (other)
2527 {
64e74474
AM		 2528 case BFD_RELOC_X86_64_GOT32:
2529 return BFD_RELOC_X86_64_GOT64;
2530 break;
2531 case BFD_RELOC_X86_64_PLTOFF64:
2532 return BFD_RELOC_X86_64_PLTOFF64;
2533 break;
2534 case BFD_RELOC_X86_64_GOTPC32:
2535 other = BFD_RELOC_X86_64_GOTPC64;
2536 break;
2537 case BFD_RELOC_X86_64_GOTPCREL:
2538 other = BFD_RELOC_X86_64_GOTPCREL64;
2539 break;
2540 case BFD_RELOC_X86_64_TPOFF32:
2541 other = BFD_RELOC_X86_64_TPOFF64;
2542 break;
2543 case BFD_RELOC_X86_64_DTPOFF32:
2544 other = BFD_RELOC_X86_64_DTPOFF64;
2545 break;
2546 default:
2547 break;
3956db08 2548 }
e05278af
JB		 2549
2550 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2551 if (size == 4 && flag_code != CODE_64BIT)
2552 sign = -1;
2553
91d6fa6a
NC		 2554 rel = bfd_reloc_type_lookup (stdoutput, other);
2555 if (!rel)
3956db08 2556 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2557 else if (size != bfd_get_reloc_size (rel))
3956db08 2558 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2559 bfd_get_reloc_size (rel),
3956db08 2560 size);
91d6fa6a 2561 else if (pcrel && !rel->pc_relative)
3956db08 2562 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2563 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2564 && !sign)
91d6fa6a 2565 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2566 && sign > 0))
3956db08
JB		 2567 as_bad (_("relocated field and relocation type differ in signedness"));
2568 else
2569 return other;
2570 return NO_RELOC;
2571 }
252b5132
RH		 2572
2573 if (pcrel)
2574 {
3e73aa7c 2575 if (!sign)
3956db08 2576 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2577 switch (size)
2578 {
2579 case 1: return BFD_RELOC_8_PCREL;
2580 case 2: return BFD_RELOC_16_PCREL;
2581 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2582 case 8: return BFD_RELOC_64_PCREL;
252b5132 2583 }
3956db08 2584 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2585 }
2586 else
2587 {
3956db08 2588 if (sign > 0)
e5cb08ac 2589 switch (size)
3e73aa7c
JH		 2590 {
2591 case 4: return BFD_RELOC_X86_64_32S;
2592 }
2593 else
2594 switch (size)
2595 {
2596 case 1: return BFD_RELOC_8;
2597 case 2: return BFD_RELOC_16;
2598 case 4: return BFD_RELOC_32;
2599 case 8: return BFD_RELOC_64;
2600 }
3956db08
JB		 2601 as_bad (_("cannot do %s %u byte relocation"),
2602 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2603 }
2604
0cc9e1d3 2605 return NO_RELOC;
252b5132
RH		 2606}
2607
47926f60
KH		 2608/* Here we decide which fixups can be adjusted to make them relative to
2609 the beginning of the section instead of the symbol. Basically we need
2610 to make sure that the dynamic relocations are done correctly, so in
2611 some cases we force the original symbol to be used. */
2612
252b5132 2613int
e3bb37b5 2614tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2615{
6d249963 2616#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2617 if (!IS_ELF)
31312f95
AM		 2618 return 1;
2619
a161fe53
AM		 2620 /* Don't adjust pc-relative references to merge sections in 64-bit
2621 mode. */
2622 if (use_rela_relocations
2623 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2624 && fixP->fx_pcrel)
252b5132 2625 return 0;
31312f95 2626
8d01d9a9
AJ		 2627 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2628 and changed later by validate_fix. */
2629 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2630 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2631 return 0;
2632
ce8a8b2f 2633 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 2634 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2635 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2636 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2637 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2638 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2639 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2640 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2641 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2642 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2643 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2644 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2645 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2646 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2647 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2648 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2649 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2650 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2651 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2652 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2653 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2654 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2655 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2656 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2657 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2658 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2659 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2660 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2661 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2662 return 0;
31312f95 2663#endif
252b5132
RH		 2664 return 1;
2665}
252b5132 2666
b4cac588 2667static int
e3bb37b5 2668intel_float_operand (const char *mnemonic)
252b5132 2669{
9306ca4a
JB		 2670 /* Note that the value returned is meaningful only for opcodes with (memory)
2671 operands, hence the code here is free to improperly handle opcodes that
2672 have no operands (for better performance and smaller code). */
2673
2674 if (mnemonic[0] != 'f')
2675 return 0; /* non-math */
2676
2677 switch (mnemonic[1])
2678 {
2679 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2680 the fs segment override prefix not currently handled because no
2681 call path can make opcodes without operands get here */
2682 case 'i':
2683 return 2 /* integer op */;
2684 case 'l':
2685 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2686 return 3; /* fldcw/fldenv */
2687 break;
2688 case 'n':
2689 if (mnemonic[2] != 'o' /* fnop */)
2690 return 3; /* non-waiting control op */
2691 break;
2692 case 'r':
2693 if (mnemonic[2] == 's')
2694 return 3; /* frstor/frstpm */
2695 break;
2696 case 's':
2697 if (mnemonic[2] == 'a')
2698 return 3; /* fsave */
2699 if (mnemonic[2] == 't')
2700 {
2701 switch (mnemonic[3])
2702 {
2703 case 'c': /* fstcw */
2704 case 'd': /* fstdw */
2705 case 'e': /* fstenv */
2706 case 's': /* fsts[gw] */
2707 return 3;
2708 }
2709 }
2710 break;
2711 case 'x':
2712 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2713 return 0; /* fxsave/fxrstor are not really math ops */
2714 break;
2715 }
252b5132 2716
9306ca4a 2717 return 1;
252b5132
RH		 2718}
2719
c0f3af97
L		 2720/* Build the VEX prefix. */
2721
2722static void
d3ce72d0 2723build_vex_prefix (const insn_template *t)
c0f3af97
L		 2724{
2725 unsigned int register_specifier;
2726 unsigned int implied_prefix;
2727 unsigned int vector_length;
2728
2729 /* Check register specifier. */
2730 if (i.vex.register_specifier)
2731 {
2732 register_specifier = i.vex.register_specifier->reg_num;
2733 if ((i.vex.register_specifier->reg_flags & RegRex))
2734 register_specifier += 8;
2735 register_specifier = ~register_specifier & 0xf;
2736 }
2737 else
2738 register_specifier = 0xf;
2739
fa99fab2
L		 2740 /* Use 2-byte VEX prefix by swappping destination and source
2741 operand. */
2742 if (!i.swap_operand
2743 && i.operands == i.reg_operands
7f399153 2744 && i.tm.opcode_modifier.vexopcode == VEX0F
fa99fab2
L		 2745 && i.tm.opcode_modifier.s
2746 && i.rex == REX_B)
2747 {
2748 unsigned int xchg = i.operands - 1;
2749 union i386_op temp_op;
2750 i386_operand_type temp_type;
2751
2752 temp_type = i.types[xchg];
2753 i.types[xchg] = i.types[0];
2754 i.types[0] = temp_type;
2755 temp_op = i.op[xchg];
2756 i.op[xchg] = i.op[0];
2757 i.op[0] = temp_op;
2758
9c2799c2 2759 gas_assert (i.rm.mode == 3);
fa99fab2
L		 2760
2761 i.rex = REX_R;
2762 xchg = i.rm.regmem;
2763 i.rm.regmem = i.rm.reg;
2764 i.rm.reg = xchg;
2765
2766 /* Use the next insn. */
2767 i.tm = t[1];
2768 }
2769
539f890d
L		 2770 if (i.tm.opcode_modifier.vex == VEXScalar)
2771 vector_length = avxscalar;
2772 else
2773 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 2774
2775 switch ((i.tm.base_opcode >> 8) & 0xff)
2776 {
2777 case 0:
2778 implied_prefix = 0;
2779 break;
2780 case DATA_PREFIX_OPCODE:
2781 implied_prefix = 1;
2782 break;
2783 case REPE_PREFIX_OPCODE:
2784 implied_prefix = 2;
2785 break;
2786 case REPNE_PREFIX_OPCODE:
2787 implied_prefix = 3;
2788 break;
2789 default:
2790 abort ();
2791 }
2792
2793 /* Use 2-byte VEX prefix if possible. */
7f399153 2794 if (i.tm.opcode_modifier.vexopcode == VEX0F
c0f3af97
L		 2795 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
2796 {
2797 /* 2-byte VEX prefix. */
2798 unsigned int r;
2799
2800 i.vex.length = 2;
2801 i.vex.bytes[0] = 0xc5;
2802
2803 /* Check the REX.R bit. */
2804 r = (i.rex & REX_R) ? 0 : 1;
2805 i.vex.bytes[1] = (r << 7
2806 | register_specifier << 3
2807 | vector_length << 2
2808 | implied_prefix);
2809 }
2810 else
2811 {
2812 /* 3-byte VEX prefix. */
2813 unsigned int m, w;
2814
f88c9eb0 2815 i.vex.length = 3;
f88c9eb0 2816
7f399153 2817 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 2818 {
7f399153
L		 2819 case VEX0F:
2820 m = 0x1;
80de6e00 2821 i.vex.bytes[0] = 0xc4;
7f399153
L		 2822 break;
2823 case VEX0F38:
2824 m = 0x2;
80de6e00 2825 i.vex.bytes[0] = 0xc4;
7f399153
L		 2826 break;
2827 case VEX0F3A:
2828 m = 0x3;
80de6e00 2829 i.vex.bytes[0] = 0xc4;
7f399153
L		 2830 break;
2831 case XOP08:
5dd85c99
SP		 2832 m = 0x8;
2833 i.vex.bytes[0] = 0x8f;
7f399153
L		 2834 break;
2835 case XOP09:
f88c9eb0
SP		 2836 m = 0x9;
2837 i.vex.bytes[0] = 0x8f;
7f399153
L		 2838 break;
2839 case XOP0A:
f88c9eb0
SP		 2840 m = 0xa;
2841 i.vex.bytes[0] = 0x8f;
7f399153
L		 2842 break;
2843 default:
2844 abort ();
f88c9eb0 2845 }
c0f3af97 2846
c0f3af97
L		 2847 /* The high 3 bits of the second VEX byte are 1's compliment
2848 of RXB bits from REX. */
2849 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
2850
2851 /* Check the REX.W bit. */
2852 w = (i.rex & REX_W) ? 1 : 0;
1ef99a7b 2853 if (i.tm.opcode_modifier.vexw)
c0f3af97
L		 2854 {
2855 if (w)
2856 abort ();
2857
1ef99a7b 2858 if (i.tm.opcode_modifier.vexw == VEXW1)
c0f3af97
L		 2859 w = 1;
2860 }
2861
2862 i.vex.bytes[2] = (w << 7
2863 | register_specifier << 3
2864 | vector_length << 2
2865 | implied_prefix);
2866 }
2867}
2868
65da13b5
L		 2869static void
2870process_immext (void)
2871{
2872 expressionS *exp;
2873
2874 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2875 {
1fed0ba1
L		 2876 /* SSE3 Instructions have the fixed operands with an opcode
2877 suffix which is coded in the same place as an 8-bit immediate
2878 field would be. Here we check those operands and remove them
2879 afterwards. */
65da13b5
L		 2880 unsigned int x;
2881
2882 for (x = 0; x < i.operands; x++)
2883 if (i.op[x].regs->reg_num != x)
2884 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 2885 register_prefix, i.op[x].regs->reg_name, x + 1,
2886 i.tm.name);
2887
2888 i.operands = 0;
65da13b5
L		 2889 }
2890
c0f3af97 2891 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 2892 which is coded in the same place as an 8-bit immediate field
2893 would be. Here we fake an 8-bit immediate operand from the
2894 opcode suffix stored in tm.extension_opcode.
2895
c1e679ec 2896 AVX instructions also use this encoding, for some of
c0f3af97 2897 3 argument instructions. */
65da13b5 2898
9c2799c2 2899 gas_assert (i.imm_operands == 0
7ab9ffdd
L		 2900 && (i.operands <= 2
2901 || (i.tm.opcode_modifier.vex
2902 && i.operands <= 4)));
65da13b5
L		 2903
2904 exp = &im_expressions[i.imm_operands++];
2905 i.op[i.operands].imms = exp;
2906 i.types[i.operands] = imm8;
2907 i.operands++;
2908 exp->X_op = O_constant;
2909 exp->X_add_number = i.tm.extension_opcode;
2910 i.tm.extension_opcode = None;
2911}
2912
252b5132
RH		 2913/* This is the guts of the machine-dependent assembler. LINE points to a
2914 machine dependent instruction. This function is supposed to emit
2915 the frags/bytes it assembles to. */
2916
2917void
65da13b5 2918md_assemble (char *line)
252b5132 2919{
40fb9820 2920 unsigned int j;
252b5132 2921 char mnemonic[MAX_MNEM_SIZE];
d3ce72d0 2922 const insn_template *t;
252b5132 2923
47926f60 2924 /* Initialize globals. */
252b5132
RH		 2925 memset (&i, '\0', sizeof (i));
2926 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 2927 i.reloc[j] = NO_RELOC;
252b5132
RH		 2928 memset (disp_expressions, '\0', sizeof (disp_expressions));
2929 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 2930 save_stack_p = save_stack;
252b5132
RH		 2931
2932 /* First parse an instruction mnemonic & call i386_operand for the operands.
2933 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 2934 start of a (possibly prefixed) mnemonic. */
252b5132 2935
29b0f896
AM		 2936 line = parse_insn (line, mnemonic);
2937 if (line == NULL)
2938 return;
252b5132 2939
29b0f896 2940 line = parse_operands (line, mnemonic);
ee86248c 2941 this_operand = -1;
29b0f896
AM		 2942 if (line == NULL)
2943 return;
252b5132 2944
29b0f896
AM		 2945 /* Now we've parsed the mnemonic into a set of templates, and have the
2946 operands at hand. */
2947
2948 /* All intel opcodes have reversed operands except for "bound" and
2949 "enter". We also don't reverse intersegment "jmp" and "call"
2950 instructions with 2 immediate operands so that the immediate segment
050dfa73 2951 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 2952 if (intel_syntax
2953 && i.operands > 1
29b0f896 2954 && (strcmp (mnemonic, "bound") != 0)
30123838 2955 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 2956 && !(operand_type_check (i.types[0], imm)
2957 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 2958 swap_operands ();
2959
ec56d5c0
JB		 2960 /* The order of the immediates should be reversed
2961 for 2 immediates extrq and insertq instructions */
2962 if (i.imm_operands == 2
2963 && (strcmp (mnemonic, "extrq") == 0
2964 || strcmp (mnemonic, "insertq") == 0))
2965 swap_2_operands (0, 1);
2966
29b0f896
AM		 2967 if (i.imm_operands)
2968 optimize_imm ();
2969
b300c311
L		 2970 /* Don't optimize displacement for movabs since it only takes 64bit
2971 displacement. */
2972 if (i.disp_operands
2973 && (flag_code != CODE_64BIT
2974 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 2975 optimize_disp ();
2976
2977 /* Next, we find a template that matches the given insn,
2978 making sure the overlap of the given operands types is consistent
2979 with the template operand types. */
252b5132 2980
fa99fab2 2981 if (!(t = match_template ()))
29b0f896 2982 return;
252b5132 2983
daf50ae7 2984 if (sse_check != sse_check_none
81f8a913 2985 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 2986 && (i.tm.cpu_flags.bitfield.cpusse
2987 || i.tm.cpu_flags.bitfield.cpusse2
2988 || i.tm.cpu_flags.bitfield.cpusse3
2989 || i.tm.cpu_flags.bitfield.cpussse3
2990 || i.tm.cpu_flags.bitfield.cpusse4_1
2991 || i.tm.cpu_flags.bitfield.cpusse4_2))
2992 {
2993 (sse_check == sse_check_warning
2994 ? as_warn
2995 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
2996 }
2997
321fd21e
L		 2998 /* Zap movzx and movsx suffix. The suffix has been set from
2999 "word ptr" or "byte ptr" on the source operand in Intel syntax
3000 or extracted from mnemonic in AT&T syntax. But we'll use
3001 the destination register to choose the suffix for encoding. */
3002 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3003 {
321fd21e
L		 3004 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3005 there is no suffix, the default will be byte extension. */
3006 if (i.reg_operands != 2
3007 && !i.suffix
7ab9ffdd 3008 && intel_syntax)
321fd21e
L		 3009 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3010
3011 i.suffix = 0;
cd61ebfe 3012 }
24eab124 3013
40fb9820 3014 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3015 if (!add_prefix (FWAIT_OPCODE))
3016 return;
252b5132 3017
c1ba0266
L		 3018 /* Check for lock without a lockable instruction. Destination operand
3019 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3020 if (i.prefix[LOCK_PREFIX]
3021 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3022 || i.mem_operands == 0
3023 || (i.tm.base_opcode != 0x86
3024 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3025 {
3026 as_bad (_("expecting lockable instruction after `lock'"));
3027 return;
3028 }
3029
29b0f896 3030 /* Check string instruction segment overrides. */
40fb9820 3031 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3032 {
3033 if (!check_string ())
5dd0794d 3034 return;
fc0763e6 3035 i.disp_operands = 0;
29b0f896 3036 }
5dd0794d 3037
29b0f896
AM		 3038 if (!process_suffix ())
3039 return;
e413e4e9 3040
bc0844ae
L		 3041 /* Update operand types. */
3042 for (j = 0; j < i.operands; j++)
3043 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3044
29b0f896
AM		 3045 /* Make still unresolved immediate matches conform to size of immediate
3046 given in i.suffix. */
3047 if (!finalize_imm ())
3048 return;
252b5132 3049
40fb9820 3050 if (i.types[0].bitfield.imm1)
29b0f896 3051 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3052
9afe6eb8
L		 3053 /* We only need to check those implicit registers for instructions
3054 with 3 operands or less. */
3055 if (i.operands <= 3)
3056 for (j = 0; j < i.operands; j++)
3057 if (i.types[j].bitfield.inoutportreg
3058 || i.types[j].bitfield.shiftcount
3059 || i.types[j].bitfield.acc
3060 || i.types[j].bitfield.floatacc)
3061 i.reg_operands--;
40fb9820 3062
c0f3af97
L		 3063 /* ImmExt should be processed after SSE2AVX. */
3064 if (!i.tm.opcode_modifier.sse2avx
3065 && i.tm.opcode_modifier.immext)
65da13b5 3066 process_immext ();
252b5132 3067
29b0f896
AM		 3068 /* For insns with operands there are more diddles to do to the opcode. */
3069 if (i.operands)
3070 {
3071 if (!process_operands ())
3072 return;
3073 }
40fb9820 3074 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3075 {
3076 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3077 as_warn (_("translating to `%sp'"), i.tm.name);
3078 }
252b5132 3079
c0f3af97 3080 if (i.tm.opcode_modifier.vex)
fa99fab2 3081 build_vex_prefix (t);
c0f3af97 3082
5dd85c99
SP		 3083 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3084 instructions may define INT_OPCODE as well, so avoid this corner
3085 case for those instructions that use MODRM. */
3086 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3087 && !i.tm.opcode_modifier.modrm
3088 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3089 {
3090 i.tm.base_opcode = INT3_OPCODE;
3091 i.imm_operands = 0;
3092 }
252b5132 3093
40fb9820
L		 3094 if ((i.tm.opcode_modifier.jump
3095 || i.tm.opcode_modifier.jumpbyte
3096 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3097 && i.op[0].disps->X_op == O_constant)
3098 {
3099 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3100 the absolute address given by the constant. Since ix86 jumps and
3101 calls are pc relative, we need to generate a reloc. */
3102 i.op[0].disps->X_add_symbol = &abs_symbol;
3103 i.op[0].disps->X_op = O_symbol;
3104 }
252b5132 3105
40fb9820 3106 if (i.tm.opcode_modifier.rex64)
161a04f6 3107 i.rex |= REX_W;
252b5132 3108
29b0f896
AM		 3109 /* For 8 bit registers we need an empty rex prefix. Also if the
3110 instruction already has a prefix, we need to convert old
3111 registers to new ones. */
773f551c 3112
40fb9820 3113 if ((i.types[0].bitfield.reg8
29b0f896 3114 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3115 || (i.types[1].bitfield.reg8
29b0f896 3116 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3117 || ((i.types[0].bitfield.reg8
3118 || i.types[1].bitfield.reg8)
29b0f896
AM		 3119 && i.rex != 0))
3120 {
3121 int x;
726c5dcd 3122
29b0f896
AM		 3123 i.rex |= REX_OPCODE;
3124 for (x = 0; x < 2; x++)
3125 {
3126 /* Look for 8 bit operand that uses old registers. */
40fb9820 3127 if (i.types[x].bitfield.reg8
29b0f896 3128 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3129 {
29b0f896
AM		 3130 /* In case it is "hi" register, give up. */
3131 if (i.op[x].regs->reg_num > 3)
a540244d 3132 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3133 "instruction requiring REX prefix."),
a540244d 3134 register_prefix, i.op[x].regs->reg_name);
773f551c 3135
29b0f896
AM		 3136 /* Otherwise it is equivalent to the extended register.
3137 Since the encoding doesn't change this is merely
3138 cosmetic cleanup for debug output. */
3139
3140 i.op[x].regs = i.op[x].regs + 8;
773f551c 3141 }
29b0f896
AM		 3142 }
3143 }
773f551c 3144
7ab9ffdd 3145 if (i.rex != 0)
29b0f896
AM		 3146 add_prefix (REX_OPCODE | i.rex);
3147
3148 /* We are ready to output the insn. */
3149 output_insn ();
3150}
3151
3152static char *
e3bb37b5 3153parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3154{
3155 char *l = line;
3156 char *token_start = l;
3157 char *mnem_p;
5c6af06e 3158 int supported;
d3ce72d0 3159 const insn_template *t;
b6169b20 3160 char *dot_p = NULL;
29b0f896
AM		 3161
3162 /* Non-zero if we found a prefix only acceptable with string insns. */
3163 const char *expecting_string_instruction = NULL;
45288df1 3164
29b0f896
AM		 3165 while (1)
3166 {
3167 mnem_p = mnemonic;
3168 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3169 {
b6169b20
L		 3170 if (*mnem_p == '.')
3171 dot_p = mnem_p;
29b0f896
AM		 3172 mnem_p++;
3173 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3174 {
29b0f896
AM		 3175 as_bad (_("no such instruction: `%s'"), token_start);
3176 return NULL;
3177 }
3178 l++;
3179 }
3180 if (!is_space_char (*l)
3181 && *l != END_OF_INSN
e44823cf
JB		 3182 && (intel_syntax
3183 || (*l != PREFIX_SEPARATOR
3184 && *l != ',')))
29b0f896
AM		 3185 {
3186 as_bad (_("invalid character %s in mnemonic"),
3187 output_invalid (*l));
3188 return NULL;
3189 }
3190 if (token_start == l)
3191 {
e44823cf 3192 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3193 as_bad (_("expecting prefix; got nothing"));
3194 else
3195 as_bad (_("expecting mnemonic; got nothing"));
3196 return NULL;
3197 }
45288df1 3198
29b0f896 3199 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3200 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3201
29b0f896
AM		 3202 if (*l != END_OF_INSN
3203 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3204 && current_templates
40fb9820 3205 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3206 {
c6fb90c8 3207 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3208 {
3209 as_bad ((flag_code != CODE_64BIT
3210 ? _("`%s' is only supported in 64-bit mode")
3211 : _("`%s' is not supported in 64-bit mode")),
3212 current_templates->start->name);
3213 return NULL;
3214 }
29b0f896
AM		 3215 /* If we are in 16-bit mode, do not allow addr16 or data16.
3216 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3217 if ((current_templates->start->opcode_modifier.size16
3218 || current_templates->start->opcode_modifier.size32)
29b0f896 3219 && flag_code != CODE_64BIT
40fb9820 3220 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3221 ^ (flag_code == CODE_16BIT)))
3222 {
3223 as_bad (_("redundant %s prefix"),
3224 current_templates->start->name);
3225 return NULL;
45288df1 3226 }
29b0f896
AM		 3227 /* Add prefix, checking for repeated prefixes. */
3228 switch (add_prefix (current_templates->start->base_opcode))
3229 {
c32fa91d 3230 case PREFIX_EXIST:
29b0f896 3231 return NULL;
c32fa91d 3232 case PREFIX_REP:
29b0f896
AM		 3233 expecting_string_instruction = current_templates->start->name;
3234 break;
c32fa91d
L		 3235 default:
3236 break;
29b0f896
AM		 3237 }
3238 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3239 token_start = ++l;
3240 }
3241 else
3242 break;
3243 }
45288df1 3244
30a55f88 3245 if (!current_templates)
b6169b20 3246 {
30a55f88
L		 3247 /* Check if we should swap operand in encoding. */
3248 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3249 i.swap_operand = 1;
3250 else
3251 goto check_suffix;
3252 mnem_p = dot_p;
3253 *dot_p = '\0';
d3ce72d0 3254 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3255 }
3256
29b0f896
AM		 3257 if (!current_templates)
3258 {
b6169b20 3259check_suffix:
29b0f896
AM		 3260 /* See if we can get a match by trimming off a suffix. */
3261 switch (mnem_p[-1])
3262 {
3263 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3264 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3265 i.suffix = SHORT_MNEM_SUFFIX;
3266 else
29b0f896
AM		 3267 case BYTE_MNEM_SUFFIX:
3268 case QWORD_MNEM_SUFFIX:
3269 i.suffix = mnem_p[-1];
3270 mnem_p[-1] = '\0';
d3ce72d0
NC		 3271 current_templates = (const templates *) hash_find (op_hash,
3272 mnemonic);
29b0f896
AM		 3273 break;
3274 case SHORT_MNEM_SUFFIX:
3275 case LONG_MNEM_SUFFIX:
3276 if (!intel_syntax)
3277 {
3278 i.suffix = mnem_p[-1];
3279 mnem_p[-1] = '\0';
d3ce72d0
NC		 3280 current_templates = (const templates *) hash_find (op_hash,
3281 mnemonic);
29b0f896
AM		 3282 }
3283 break;
252b5132 3284
29b0f896
AM		 3285 /* Intel Syntax. */
3286 case 'd':
3287 if (intel_syntax)
3288 {
9306ca4a 3289 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3290 i.suffix = SHORT_MNEM_SUFFIX;
3291 else
3292 i.suffix = LONG_MNEM_SUFFIX;
3293 mnem_p[-1] = '\0';
d3ce72d0
NC		 3294 current_templates = (const templates *) hash_find (op_hash,
3295 mnemonic);
29b0f896
AM		 3296 }
3297 break;
3298 }
3299 if (!current_templates)
3300 {
3301 as_bad (_("no such instruction: `%s'"), token_start);
3302 return NULL;
3303 }
3304 }
252b5132 3305
40fb9820
L		 3306 if (current_templates->start->opcode_modifier.jump
3307 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3308 {
3309 /* Check for a branch hint. We allow ",pt" and ",pn" for
3310 predict taken and predict not taken respectively.
3311 I'm not sure that branch hints actually do anything on loop
3312 and jcxz insns (JumpByte) for current Pentium4 chips. They
3313 may work in the future and it doesn't hurt to accept them
3314 now. */
3315 if (l[0] == ',' && l[1] == 'p')
3316 {
3317 if (l[2] == 't')
3318 {
3319 if (!add_prefix (DS_PREFIX_OPCODE))
3320 return NULL;
3321 l += 3;
3322 }
3323 else if (l[2] == 'n')
3324 {
3325 if (!add_prefix (CS_PREFIX_OPCODE))
3326 return NULL;
3327 l += 3;
3328 }
3329 }
3330 }
3331 /* Any other comma loses. */
3332 if (*l == ',')
3333 {
3334 as_bad (_("invalid character %s in mnemonic"),
3335 output_invalid (*l));
3336 return NULL;
3337 }
252b5132 3338
29b0f896 3339 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3340 supported = 0;
3341 for (t = current_templates->start; t < current_templates->end; ++t)
3342 {
c0f3af97
L		 3343 supported |= cpu_flags_match (t);
3344 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3345 goto skip;
5c6af06e 3346 }
3629bb00 3347
c0f3af97 3348 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3349 {
3350 as_bad (flag_code == CODE_64BIT
3351 ? _("`%s' is not supported in 64-bit mode")
3352 : _("`%s' is only supported in 64-bit mode"),
3353 current_templates->start->name);
3354 return NULL;
3355 }
c0f3af97 3356 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3357 {
3629bb00 3358 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 3359 current_templates->start->name,
41aacd83 3360 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3361 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3362 return NULL;
29b0f896 3363 }
3629bb00
L		 3364
3365skip:
3366 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3367 && (flag_code != CODE_16BIT))
29b0f896
AM		 3368 {
3369 as_warn (_("use .code16 to ensure correct addressing mode"));
3370 }
252b5132 3371
29b0f896 3372 /* Check for rep/repne without a string instruction. */
f41bbced 3373 if (expecting_string_instruction)
29b0f896 3374 {
f41bbced
JB		 3375 static templates override;
3376
3377 for (t = current_templates->start; t < current_templates->end; ++t)
40fb9820 3378 if (t->opcode_modifier.isstring)
f41bbced
JB		 3379 break;
3380 if (t >= current_templates->end)
3381 {
3382 as_bad (_("expecting string instruction after `%s'"),
64e74474 3383 expecting_string_instruction);
f41bbced
JB		 3384 return NULL;
3385 }
3386 for (override.start = t; t < current_templates->end; ++t)
40fb9820 3387 if (!t->opcode_modifier.isstring)
f41bbced
JB		 3388 break;
3389 override.end = t;
3390 current_templates = &override;
29b0f896 3391 }
252b5132 3392
29b0f896
AM		 3393 return l;
3394}
252b5132 3395
29b0f896 3396static char *
e3bb37b5 3397parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3398{
3399 char *token_start;
3138f287 3400
29b0f896
AM		 3401 /* 1 if operand is pending after ','. */
3402 unsigned int expecting_operand = 0;
252b5132 3403
29b0f896
AM		 3404 /* Non-zero if operand parens not balanced. */
3405 unsigned int paren_not_balanced;
3406
3407 while (*l != END_OF_INSN)
3408 {
3409 /* Skip optional white space before operand. */
3410 if (is_space_char (*l))
3411 ++l;
3412 if (!is_operand_char (*l) && *l != END_OF_INSN)
3413 {
3414 as_bad (_("invalid character %s before operand %d"),
3415 output_invalid (*l),
3416 i.operands + 1);
3417 return NULL;
3418 }
3419 token_start = l; /* after white space */
3420 paren_not_balanced = 0;
3421 while (paren_not_balanced || *l != ',')
3422 {
3423 if (*l == END_OF_INSN)
3424 {
3425 if (paren_not_balanced)
3426 {
3427 if (!intel_syntax)
3428 as_bad (_("unbalanced parenthesis in operand %d."),
3429 i.operands + 1);
3430 else
3431 as_bad (_("unbalanced brackets in operand %d."),
3432 i.operands + 1);
3433 return NULL;
3434 }
3435 else
3436 break; /* we are done */
3437 }
3438 else if (!is_operand_char (*l) && !is_space_char (*l))
3439 {
3440 as_bad (_("invalid character %s in operand %d"),
3441 output_invalid (*l),
3442 i.operands + 1);
3443 return NULL;
3444 }
3445 if (!intel_syntax)
3446 {
3447 if (*l == '(')
3448 ++paren_not_balanced;
3449 if (*l == ')')
3450 --paren_not_balanced;
3451 }
3452 else
3453 {
3454 if (*l == '[')
3455 ++paren_not_balanced;
3456 if (*l == ']')
3457 --paren_not_balanced;
3458 }
3459 l++;
3460 }
3461 if (l != token_start)
3462 { /* Yes, we've read in another operand. */
3463 unsigned int operand_ok;
3464 this_operand = i.operands++;
7d5e4556 3465 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 3466 if (i.operands > MAX_OPERANDS)
3467 {
3468 as_bad (_("spurious operands; (%d operands/instruction max)"),
3469 MAX_OPERANDS);
3470 return NULL;
3471 }
3472 /* Now parse operand adding info to 'i' as we go along. */
3473 END_STRING_AND_SAVE (l);
3474
3475 if (intel_syntax)
3476 operand_ok =
3477 i386_intel_operand (token_start,
3478 intel_float_operand (mnemonic));
3479 else
a7619375 3480 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 3481
3482 RESTORE_END_STRING (l);
3483 if (!operand_ok)
3484 return NULL;
3485 }
3486 else
3487 {
3488 if (expecting_operand)
3489 {
3490 expecting_operand_after_comma:
3491 as_bad (_("expecting operand after ','; got nothing"));
3492 return NULL;
3493 }
3494 if (*l == ',')
3495 {
3496 as_bad (_("expecting operand before ','; got nothing"));
3497 return NULL;
3498 }
3499 }
7f3f1ea2 3500
29b0f896
AM		 3501 /* Now *l must be either ',' or END_OF_INSN. */
3502 if (*l == ',')
3503 {
3504 if (*++l == END_OF_INSN)
3505 {
3506 /* Just skip it, if it's \n complain. */
3507 goto expecting_operand_after_comma;
3508 }
3509 expecting_operand = 1;
3510 }
3511 }
3512 return l;
3513}
7f3f1ea2 3514
050dfa73 3515static void
4d456e3d 3516swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 3517{
3518 union i386_op temp_op;
40fb9820 3519 i386_operand_type temp_type;
050dfa73 3520 enum bfd_reloc_code_real temp_reloc;
4eed87de 3521
050dfa73
MM		 3522 temp_type = i.types[xchg2];
3523 i.types[xchg2] = i.types[xchg1];
3524 i.types[xchg1] = temp_type;
3525 temp_op = i.op[xchg2];
3526 i.op[xchg2] = i.op[xchg1];
3527 i.op[xchg1] = temp_op;
3528 temp_reloc = i.reloc[xchg2];
3529 i.reloc[xchg2] = i.reloc[xchg1];
3530 i.reloc[xchg1] = temp_reloc;
3531}
3532
29b0f896 3533static void
e3bb37b5 3534swap_operands (void)
29b0f896 3535{
b7c61d9a 3536 switch (i.operands)
050dfa73 3537 {
c0f3af97 3538 case 5:
b7c61d9a 3539 case 4:
4d456e3d 3540 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 3541 case 3:
3542 case 2:
4d456e3d 3543 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 3544 break;
3545 default:
3546 abort ();
29b0f896 3547 }
29b0f896
AM		 3548
3549 if (i.mem_operands == 2)
3550 {
3551 const seg_entry *temp_seg;
3552 temp_seg = i.seg[0];
3553 i.seg[0] = i.seg[1];
3554 i.seg[1] = temp_seg;
3555 }
3556}
252b5132 3557
29b0f896
AM		 3558/* Try to ensure constant immediates are represented in the smallest
3559 opcode possible. */
3560static void
e3bb37b5 3561optimize_imm (void)
29b0f896
AM		 3562{
3563 char guess_suffix = 0;
3564 int op;
252b5132 3565
29b0f896
AM		 3566 if (i.suffix)
3567 guess_suffix = i.suffix;
3568 else if (i.reg_operands)
3569 {
3570 /* Figure out a suffix from the last register operand specified.
3571 We can't do this properly yet, ie. excluding InOutPortReg,
3572 but the following works for instructions with immediates.
3573 In any case, we can't set i.suffix yet. */
3574 for (op = i.operands; --op >= 0;)
40fb9820 3575 if (i.types[op].bitfield.reg8)
7ab9ffdd 3576 {
40fb9820
L		 3577 guess_suffix = BYTE_MNEM_SUFFIX;
3578 break;
3579 }
3580 else if (i.types[op].bitfield.reg16)
252b5132 3581 {
40fb9820
L		 3582 guess_suffix = WORD_MNEM_SUFFIX;
3583 break;
3584 }
3585 else if (i.types[op].bitfield.reg32)
3586 {
3587 guess_suffix = LONG_MNEM_SUFFIX;
3588 break;
3589 }
3590 else if (i.types[op].bitfield.reg64)
3591 {
3592 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 3593 break;
252b5132 3594 }
29b0f896
AM		 3595 }
3596 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3597 guess_suffix = WORD_MNEM_SUFFIX;
3598
3599 for (op = i.operands; --op >= 0;)
40fb9820 3600 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 3601 {
3602 switch (i.op[op].imms->X_op)
252b5132 3603 {
29b0f896
AM		 3604 case O_constant:
3605 /* If a suffix is given, this operand may be shortened. */
3606 switch (guess_suffix)
252b5132 3607 {
29b0f896 3608 case LONG_MNEM_SUFFIX:
40fb9820
L		 3609 i.types[op].bitfield.imm32 = 1;
3610 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3611 break;
3612 case WORD_MNEM_SUFFIX:
40fb9820
L		 3613 i.types[op].bitfield.imm16 = 1;
3614 i.types[op].bitfield.imm32 = 1;
3615 i.types[op].bitfield.imm32s = 1;
3616 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3617 break;
3618 case BYTE_MNEM_SUFFIX:
40fb9820
L		 3619 i.types[op].bitfield.imm8 = 1;
3620 i.types[op].bitfield.imm8s = 1;
3621 i.types[op].bitfield.imm16 = 1;
3622 i.types[op].bitfield.imm32 = 1;
3623 i.types[op].bitfield.imm32s = 1;
3624 i.types[op].bitfield.imm64 = 1;
29b0f896 3625 break;
252b5132 3626 }
252b5132 3627
29b0f896
AM		 3628 /* If this operand is at most 16 bits, convert it
3629 to a signed 16 bit number before trying to see
3630 whether it will fit in an even smaller size.
3631 This allows a 16-bit operand such as $0xffe0 to
3632 be recognised as within Imm8S range. */
40fb9820 3633 if ((i.types[op].bitfield.imm16)
29b0f896 3634 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 3635 {
29b0f896
AM		 3636 i.op[op].imms->X_add_number =
3637 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3638 }
40fb9820 3639 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 3640 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3641 == 0))
3642 {
3643 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3644 ^ ((offsetT) 1 << 31))
3645 - ((offsetT) 1 << 31));
3646 }
40fb9820 3647 i.types[op]
c6fb90c8
L		 3648 = operand_type_or (i.types[op],
3649 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 3650
29b0f896
AM		 3651 /* We must avoid matching of Imm32 templates when 64bit
3652 only immediate is available. */
3653 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 3654 i.types[op].bitfield.imm32 = 0;
29b0f896 3655 break;
252b5132 3656
29b0f896
AM		 3657 case O_absent:
3658 case O_register:
3659 abort ();
3660
3661 /* Symbols and expressions. */
3662 default:
9cd96992
JB		 3663 /* Convert symbolic operand to proper sizes for matching, but don't
3664 prevent matching a set of insns that only supports sizes other
3665 than those matching the insn suffix. */
3666 {
40fb9820 3667 i386_operand_type mask, allowed;
d3ce72d0 3668 const insn_template *t;
9cd96992 3669
0dfbf9d7
L		 3670 operand_type_set (&mask, 0);
3671 operand_type_set (&allowed, 0);
40fb9820 3672
4eed87de
AM		 3673 for (t = current_templates->start;
3674 t < current_templates->end;
3675 ++t)
c6fb90c8
L		 3676 allowed = operand_type_or (allowed,
3677 t->operand_types[op]);
9cd96992
JB		 3678 switch (guess_suffix)
3679 {
3680 case QWORD_MNEM_SUFFIX:
40fb9820
L		 3681 mask.bitfield.imm64 = 1;
3682 mask.bitfield.imm32s = 1;
9cd96992
JB		 3683 break;
3684 case LONG_MNEM_SUFFIX:
40fb9820 3685 mask.bitfield.imm32 = 1;
9cd96992
JB		 3686 break;
3687 case WORD_MNEM_SUFFIX:
40fb9820 3688 mask.bitfield.imm16 = 1;
9cd96992
JB		 3689 break;
3690 case BYTE_MNEM_SUFFIX:
40fb9820 3691 mask.bitfield.imm8 = 1;
9cd96992
JB		 3692 break;
3693 default:
9cd96992
JB		 3694 break;
3695 }
c6fb90c8 3696 allowed = operand_type_and (mask, allowed);
0dfbf9d7 3697 if (!operand_type_all_zero (&allowed))
c6fb90c8 3698 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 3699 }
29b0f896 3700 break;
252b5132 3701 }
29b0f896
AM		 3702 }
3703}
47926f60 3704
29b0f896
AM		 3705/* Try to use the smallest displacement type too. */
3706static void
e3bb37b5 3707optimize_disp (void)
29b0f896
AM		 3708{
3709 int op;
3e73aa7c 3710
29b0f896 3711 for (op = i.operands; --op >= 0;)
40fb9820 3712 if (operand_type_check (i.types[op], disp))
252b5132 3713 {
b300c311 3714 if (i.op[op].disps->X_op == O_constant)
252b5132 3715 {
91d6fa6a 3716 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 3717
40fb9820 3718 if (i.types[op].bitfield.disp16
91d6fa6a 3719 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 3720 {
3721 /* If this operand is at most 16 bits, convert
3722 to a signed 16 bit number and don't use 64bit
3723 displacement. */
91d6fa6a 3724 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 3725 i.types[op].bitfield.disp64 = 0;
b300c311 3726 }
40fb9820 3727 if (i.types[op].bitfield.disp32
91d6fa6a 3728 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 3729 {
3730 /* If this operand is at most 32 bits, convert
3731 to a signed 32 bit number and don't use 64bit
3732 displacement. */
91d6fa6a
NC		 3733 op_disp &= (((offsetT) 2 << 31) - 1);
3734 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 3735 i.types[op].bitfield.disp64 = 0;
b300c311 3736 }
91d6fa6a 3737 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 3738 {
40fb9820
L		 3739 i.types[op].bitfield.disp8 = 0;
3740 i.types[op].bitfield.disp16 = 0;
3741 i.types[op].bitfield.disp32 = 0;
3742 i.types[op].bitfield.disp32s = 0;
3743 i.types[op].bitfield.disp64 = 0;
b300c311
L		 3744 i.op[op].disps = 0;
3745 i.disp_operands--;
3746 }
3747 else if (flag_code == CODE_64BIT)
3748 {
91d6fa6a 3749 if (fits_in_signed_long (op_disp))
28a9d8f5 3750 {
40fb9820
L		 3751 i.types[op].bitfield.disp64 = 0;
3752 i.types[op].bitfield.disp32s = 1;
28a9d8f5 3753 }
0e1147d9 3754 if (i.prefix[ADDR_PREFIX]
91d6fa6a 3755 && fits_in_unsigned_long (op_disp))
40fb9820 3756 i.types[op].bitfield.disp32 = 1;
b300c311 3757 }
40fb9820
L		 3758 if ((i.types[op].bitfield.disp32
3759 || i.types[op].bitfield.disp32s
3760 || i.types[op].bitfield.disp16)
91d6fa6a 3761 && fits_in_signed_byte (op_disp))
40fb9820 3762 i.types[op].bitfield.disp8 = 1;
252b5132 3763 }
67a4f2b7
AO		 3764 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3765 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3766 {
3767 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3768 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 3769 i.types[op].bitfield.disp8 = 0;
3770 i.types[op].bitfield.disp16 = 0;
3771 i.types[op].bitfield.disp32 = 0;
3772 i.types[op].bitfield.disp32s = 0;
3773 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 3774 }
3775 else
b300c311 3776 /* We only support 64bit displacement on constants. */
40fb9820 3777 i.types[op].bitfield.disp64 = 0;
252b5132 3778 }
29b0f896
AM		 3779}
3780
a683cc34
SP		 3781/* Check if operands are valid for the instrucrtion. Update VEX
3782 operand types. */
3783
3784static int
3785VEX_check_operands (const insn_template *t)
3786{
3787 if (!t->opcode_modifier.vex)
3788 return 0;
3789
3790 /* Only check VEX_Imm4, which must be the first operand. */
3791 if (t->operand_types[0].bitfield.vec_imm4)
3792 {
3793 if (i.op[0].imms->X_op != O_constant
3794 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 3795 {
a65babc9 3796 i.error = bad_imm4;
891edac4
L		 3797 return 1;
3798 }
a683cc34
SP		 3799
3800 /* Turn off Imm8 so that update_imm won't complain. */
3801 i.types[0] = vec_imm4;
3802 }
3803
3804 return 0;
3805}
3806
d3ce72d0 3807static const insn_template *
e3bb37b5 3808match_template (void)
29b0f896
AM		 3809{
3810 /* Points to template once we've found it. */
d3ce72d0 3811 const insn_template *t;
40fb9820 3812 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 3813 i386_operand_type overlap4;
29b0f896 3814 unsigned int found_reverse_match;
40fb9820
L		 3815 i386_opcode_modifier suffix_check;
3816 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 3817 int addr_prefix_disp;
a5c311ca 3818 unsigned int j;
3629bb00 3819 unsigned int found_cpu_match;
45664ddb 3820 unsigned int check_register;
29b0f896 3821
c0f3af97
L		 3822#if MAX_OPERANDS != 5
3823# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 3824#endif
3825
29b0f896 3826 found_reverse_match = 0;
539e75ad 3827 addr_prefix_disp = -1;
40fb9820
L		 3828
3829 memset (&suffix_check, 0, sizeof (suffix_check));
3830 if (i.suffix == BYTE_MNEM_SUFFIX)
3831 suffix_check.no_bsuf = 1;
3832 else if (i.suffix == WORD_MNEM_SUFFIX)
3833 suffix_check.no_wsuf = 1;
3834 else if (i.suffix == SHORT_MNEM_SUFFIX)
3835 suffix_check.no_ssuf = 1;
3836 else if (i.suffix == LONG_MNEM_SUFFIX)
3837 suffix_check.no_lsuf = 1;
3838 else if (i.suffix == QWORD_MNEM_SUFFIX)
3839 suffix_check.no_qsuf = 1;
3840 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 3841 suffix_check.no_ldsuf = 1;
29b0f896 3842
45aa61fe 3843 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 3844 {
539e75ad
L		 3845 addr_prefix_disp = -1;
3846
29b0f896 3847 /* Must have right number of operands. */
a65babc9 3848 i.error = number_of_operands_mismatch;
29b0f896
AM		 3849 if (i.operands != t->operands)
3850 continue;
3851
50aecf8c 3852 /* Check processor support. */
a65babc9 3853 i.error = unsupported;
c0f3af97
L		 3854 found_cpu_match = (cpu_flags_match (t)
3855 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 3856 if (!found_cpu_match)
3857 continue;
3858
e1d4d893 3859 /* Check old gcc support. */
a65babc9 3860 i.error = old_gcc_only;
e1d4d893
L		 3861 if (!old_gcc && t->opcode_modifier.oldgcc)
3862 continue;
3863
3864 /* Check AT&T mnemonic. */
a65babc9 3865 i.error = unsupported_with_intel_mnemonic;
e1d4d893 3866 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 3867 continue;
3868
891edac4 3869 /* Check AT&T/Intel syntax. */
a65babc9 3870 i.error = unsupported_syntax;
5c07affc
L		 3871 if ((intel_syntax && t->opcode_modifier.attsyntax)
3872 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 3873 continue;
3874
20592a94 3875 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 3876 i.error = invalid_instruction_suffix;
567e4e96
L		 3877 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3878 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3879 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3880 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3881 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3882 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3883 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 3884 continue;
3885
5c07affc 3886 if (!operand_size_match (t))
7d5e4556 3887 continue;
539e75ad 3888
5c07affc
L		 3889 for (j = 0; j < MAX_OPERANDS; j++)
3890 operand_types[j] = t->operand_types[j];
3891
45aa61fe
AM		 3892 /* In general, don't allow 64-bit operands in 32-bit mode. */
3893 if (i.suffix == QWORD_MNEM_SUFFIX
3894 && flag_code != CODE_64BIT
3895 && (intel_syntax
40fb9820 3896 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 3897 && !intel_float_operand (t->name))
3898 : intel_float_operand (t->name) != 2)
40fb9820 3899 && ((!operand_types[0].bitfield.regmmx
c0f3af97
L		 3900 && !operand_types[0].bitfield.regxmm
3901 && !operand_types[0].bitfield.regymm)
40fb9820 3902 || (!operand_types[t->operands > 1].bitfield.regmmx
c0f3af97
L		 3903 && !!operand_types[t->operands > 1].bitfield.regxmm
3904 && !!operand_types[t->operands > 1].bitfield.regymm))
45aa61fe
AM		 3905 && (t->base_opcode != 0x0fc7
3906 || t->extension_opcode != 1 /* cmpxchg8b */))
3907 continue;
3908
192dc9c6
JB		 3909 /* In general, don't allow 32-bit operands on pre-386. */
3910 else if (i.suffix == LONG_MNEM_SUFFIX
3911 && !cpu_arch_flags.bitfield.cpui386
3912 && (intel_syntax
3913 ? (!t->opcode_modifier.ignoresize
3914 && !intel_float_operand (t->name))
3915 : intel_float_operand (t->name) != 2)
3916 && ((!operand_types[0].bitfield.regmmx
3917 && !operand_types[0].bitfield.regxmm)
3918 || (!operand_types[t->operands > 1].bitfield.regmmx
3919 && !!operand_types[t->operands > 1].bitfield.regxmm)))
3920 continue;
3921
29b0f896 3922 /* Do not verify operands when there are none. */
50aecf8c 3923 else
29b0f896 3924 {
c6fb90c8 3925 if (!t->operands)
2dbab7d5
L		 3926 /* We've found a match; break out of loop. */
3927 break;
29b0f896 3928 }
252b5132 3929
539e75ad
L		 3930 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3931 into Disp32/Disp16/Disp32 operand. */
3932 if (i.prefix[ADDR_PREFIX] != 0)
3933 {
40fb9820 3934 /* There should be only one Disp operand. */
539e75ad
L		 3935 switch (flag_code)
3936 {
3937 case CODE_16BIT:
40fb9820
L		 3938 for (j = 0; j < MAX_OPERANDS; j++)
3939 {
3940 if (operand_types[j].bitfield.disp16)
3941 {
3942 addr_prefix_disp = j;
3943 operand_types[j].bitfield.disp32 = 1;
3944 operand_types[j].bitfield.disp16 = 0;
3945 break;
3946 }
3947 }
539e75ad
L		 3948 break;
3949 case CODE_32BIT:
40fb9820
L		 3950 for (j = 0; j < MAX_OPERANDS; j++)
3951 {
3952 if (operand_types[j].bitfield.disp32)
3953 {
3954 addr_prefix_disp = j;
3955 operand_types[j].bitfield.disp32 = 0;
3956 operand_types[j].bitfield.disp16 = 1;
3957 break;
3958 }
3959 }
539e75ad
L		 3960 break;
3961 case CODE_64BIT:
40fb9820
L		 3962 for (j = 0; j < MAX_OPERANDS; j++)
3963 {
3964 if (operand_types[j].bitfield.disp64)
3965 {
3966 addr_prefix_disp = j;
3967 operand_types[j].bitfield.disp64 = 0;
3968 operand_types[j].bitfield.disp32 = 1;
3969 break;
3970 }
3971 }
539e75ad
L		 3972 break;
3973 }
539e75ad
L		 3974 }
3975
45664ddb
L		 3976 /* We check register size only if size of operands can be
3977 encoded the canonical way. */
3978 check_register = t->opcode_modifier.w;
c6fb90c8 3979 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 3980 switch (t->operands)
3981 {
3982 case 1:
40fb9820 3983 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 3984 continue;
3985 break;
3986 case 2:
8b38ad71
L		 3987 /* xchg %eax, %eax is a special case. It is an aliase for nop
3988 only in 32bit mode and we can use opcode 0x90. In 64bit
3989 mode, we can't use 0x90 for xchg %eax, %eax since it should
3990 zero-extend %eax to %rax. */
3991 if (flag_code == CODE_64BIT
3992 && t->base_opcode == 0x90
0dfbf9d7
L		 3993 && operand_type_equal (&i.types [0], &acc32)
3994 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 3995 continue;
b6169b20
L		 3996 if (i.swap_operand)
3997 {
3998 /* If we swap operand in encoding, we either match
3999 the next one or reverse direction of operands. */
4000 if (t->opcode_modifier.s)
4001 continue;
4002 else if (t->opcode_modifier.d)
4003 goto check_reverse;
4004 }
4005
29b0f896 4006 case 3:
fa99fab2
L		 4007 /* If we swap operand in encoding, we match the next one. */
4008 if (i.swap_operand && t->opcode_modifier.s)
4009 continue;
f48ff2ae 4010 case 4:
c0f3af97 4011 case 5:
c6fb90c8 4012 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 4013 if (!operand_type_match (overlap0, i.types[0])
4014 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4015 || (check_register
4016 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 4017 operand_types[0],
4018 overlap1, i.types[1],
4019 operand_types[1])))
29b0f896
AM		 4020 {
4021 /* Check if other direction is valid ... */
40fb9820 4022 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 4023 continue;
4024
b6169b20 4025check_reverse:
29b0f896 4026 /* Try reversing direction of operands. */
c6fb90c8
L		 4027 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4028 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 4029 if (!operand_type_match (overlap0, i.types[0])
4030 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4031 || (check_register
4032 && !operand_type_register_match (overlap0,
4033 i.types[0],
4034 operand_types[1],
4035 overlap1,
4036 i.types[1],
4037 operand_types[0])))
29b0f896
AM		 4038 {
4039 /* Does not match either direction. */
4040 continue;
4041 }
4042 /* found_reverse_match holds which of D or FloatDR
4043 we've found. */
40fb9820 4044 if (t->opcode_modifier.d)
8a2ed489 4045 found_reverse_match = Opcode_D;
40fb9820 4046 else if (t->opcode_modifier.floatd)
8a2ed489
L		 4047 found_reverse_match = Opcode_FloatD;
4048 else
4049 found_reverse_match = 0;
40fb9820 4050 if (t->opcode_modifier.floatr)
8a2ed489 4051 found_reverse_match |= Opcode_FloatR;
29b0f896 4052 }
f48ff2ae 4053 else
29b0f896 4054 {
f48ff2ae 4055 /* Found a forward 2 operand match here. */
d1cbb4db
L		 4056 switch (t->operands)
4057 {
c0f3af97
L		 4058 case 5:
4059 overlap4 = operand_type_and (i.types[4],
4060 operand_types[4]);
d1cbb4db 4061 case 4:
c6fb90c8
L		 4062 overlap3 = operand_type_and (i.types[3],
4063 operand_types[3]);
d1cbb4db 4064 case 3:
c6fb90c8
L		 4065 overlap2 = operand_type_and (i.types[2],
4066 operand_types[2]);
d1cbb4db
L		 4067 break;
4068 }
29b0f896 4069
f48ff2ae
L		 4070 switch (t->operands)
4071 {
c0f3af97
L		 4072 case 5:
4073 if (!operand_type_match (overlap4, i.types[4])
4074 || !operand_type_register_match (overlap3,
4075 i.types[3],
4076 operand_types[3],
4077 overlap4,
4078 i.types[4],
4079 operand_types[4]))
4080 continue;
f48ff2ae 4081 case 4:
40fb9820 4082 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 4083 || (check_register
4084 && !operand_type_register_match (overlap2,
4085 i.types[2],
4086 operand_types[2],
4087 overlap3,
4088 i.types[3],
4089 operand_types[3])))
f48ff2ae
L		 4090 continue;
4091 case 3:
4092 /* Here we make use of the fact that there are no
4093 reverse match 3 operand instructions, and all 3
4094 operand instructions only need to be checked for
4095 register consistency between operands 2 and 3. */
40fb9820 4096 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 4097 || (check_register
4098 && !operand_type_register_match (overlap1,
4099 i.types[1],
4100 operand_types[1],
4101 overlap2,
4102 i.types[2],
4103 operand_types[2])))
f48ff2ae
L		 4104 continue;
4105 break;
4106 }
29b0f896 4107 }
f48ff2ae 4108 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 4109 slip through to break. */
4110 }
3629bb00 4111 if (!found_cpu_match)
29b0f896
AM		 4112 {
4113 found_reverse_match = 0;
4114 continue;
4115 }
c0f3af97 4116
a683cc34
SP		 4117 /* Check if VEX operands are valid. */
4118 if (VEX_check_operands (t))
4119 continue;
4120
29b0f896
AM		 4121 /* We've found a match; break out of loop. */
4122 break;
4123 }
4124
4125 if (t == current_templates->end)
4126 {
4127 /* We found no match. */
a65babc9
L		 4128 const char *err_msg;
4129 switch (i.error)
4130 {
4131 default:
4132 abort ();
86e026a4 4133 case operand_size_mismatch:
a65babc9
L		 4134 err_msg = _("operand size mismatch");
4135 break;
4136 case operand_type_mismatch:
4137 err_msg = _("operand type mismatch");
4138 break;
4139 case register_type_mismatch:
4140 err_msg = _("register type mismatch");
4141 break;
4142 case number_of_operands_mismatch:
4143 err_msg = _("number of operands mismatch");
4144 break;
4145 case invalid_instruction_suffix:
4146 err_msg = _("invalid instruction suffix");
4147 break;
4148 case bad_imm4:
4149 err_msg = _("Imm4 isn't the first operand");
4150 break;
4151 case old_gcc_only:
4152 err_msg = _("only supported with old gcc");
4153 break;
4154 case unsupported_with_intel_mnemonic:
4155 err_msg = _("unsupported with Intel mnemonic");
4156 break;
4157 case unsupported_syntax:
4158 err_msg = _("unsupported syntax");
4159 break;
4160 case unsupported:
4161 err_msg = _("unsupported");
4162 break;
4163 }
4164 as_bad (_("%s for `%s'"), err_msg,
891edac4 4165 current_templates->start->name);
fa99fab2 4166 return NULL;
29b0f896 4167 }
252b5132 4168
29b0f896
AM		 4169 if (!quiet_warnings)
4170 {
4171 if (!intel_syntax
40fb9820
L		 4172 && (i.types[0].bitfield.jumpabsolute
4173 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 4174 {
4175 as_warn (_("indirect %s without `*'"), t->name);
4176 }
4177
40fb9820
L		 4178 if (t->opcode_modifier.isprefix
4179 && t->opcode_modifier.ignoresize)
29b0f896
AM		 4180 {
4181 /* Warn them that a data or address size prefix doesn't
4182 affect assembly of the next line of code. */
4183 as_warn (_("stand-alone `%s' prefix"), t->name);
4184 }
4185 }
4186
4187 /* Copy the template we found. */
4188 i.tm = *t;
539e75ad
L		 4189
4190 if (addr_prefix_disp != -1)
4191 i.tm.operand_types[addr_prefix_disp]
4192 = operand_types[addr_prefix_disp];
4193
29b0f896
AM		 4194 if (found_reverse_match)
4195 {
4196 /* If we found a reverse match we must alter the opcode
4197 direction bit. found_reverse_match holds bits to change
4198 (different for int & float insns). */
4199
4200 i.tm.base_opcode ^= found_reverse_match;
4201
539e75ad
L		 4202 i.tm.operand_types[0] = operand_types[1];
4203 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 4204 }
4205
fa99fab2 4206 return t;
29b0f896
AM		 4207}
4208
4209static int
e3bb37b5 4210check_string (void)
29b0f896 4211{
40fb9820
L		 4212 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
4213 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 4214 {
4215 if (i.seg[0] != NULL && i.seg[0] != &es)
4216 {
a87af027 4217 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 4218 i.tm.name,
a87af027
JB		 4219 mem_op + 1,
4220 register_prefix);
29b0f896
AM		 4221 return 0;
4222 }
4223 /* There's only ever one segment override allowed per instruction.
4224 This instruction possibly has a legal segment override on the
4225 second operand, so copy the segment to where non-string
4226 instructions store it, allowing common code. */
4227 i.seg[0] = i.seg[1];
4228 }
40fb9820 4229 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 4230 {
4231 if (i.seg[1] != NULL && i.seg[1] != &es)
4232 {
a87af027 4233 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 4234 i.tm.name,
a87af027
JB		 4235 mem_op + 2,
4236 register_prefix);
29b0f896
AM		 4237 return 0;
4238 }
4239 }
4240 return 1;
4241}
4242
4243static int
543613e9 4244process_suffix (void)
29b0f896
AM		 4245{
4246 /* If matched instruction specifies an explicit instruction mnemonic
4247 suffix, use it. */
40fb9820
L		 4248 if (i.tm.opcode_modifier.size16)
4249 i.suffix = WORD_MNEM_SUFFIX;
4250 else if (i.tm.opcode_modifier.size32)
4251 i.suffix = LONG_MNEM_SUFFIX;
4252 else if (i.tm.opcode_modifier.size64)
4253 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 4254 else if (i.reg_operands)
4255 {
4256 /* If there's no instruction mnemonic suffix we try to invent one
4257 based on register operands. */
4258 if (!i.suffix)
4259 {
4260 /* We take i.suffix from the last register operand specified,
4261 Destination register type is more significant than source
381d071f
L		 4262 register type. crc32 in SSE4.2 prefers source register
4263 type. */
4264 if (i.tm.base_opcode == 0xf20f38f1)
4265 {
40fb9820
L		 4266 if (i.types[0].bitfield.reg16)
4267 i.suffix = WORD_MNEM_SUFFIX;
4268 else if (i.types[0].bitfield.reg32)
4269 i.suffix = LONG_MNEM_SUFFIX;
4270 else if (i.types[0].bitfield.reg64)
4271 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 4272 }
9344ff29 4273 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 4274 {
40fb9820 4275 if (i.types[0].bitfield.reg8)
20592a94
L		 4276 i.suffix = BYTE_MNEM_SUFFIX;
4277 }
381d071f
L		 4278
4279 if (!i.suffix)
4280 {
4281 int op;
4282
20592a94
L		 4283 if (i.tm.base_opcode == 0xf20f38f1
4284 || i.tm.base_opcode == 0xf20f38f0)
4285 {
4286 /* We have to know the operand size for crc32. */
4287 as_bad (_("ambiguous memory operand size for `%s`"),
4288 i.tm.name);
4289 return 0;
4290 }
4291
381d071f 4292 for (op = i.operands; --op >= 0;)
40fb9820 4293 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 4294 {
40fb9820
L		 4295 if (i.types[op].bitfield.reg8)
4296 {
4297 i.suffix = BYTE_MNEM_SUFFIX;
4298 break;
4299 }
4300 else if (i.types[op].bitfield.reg16)
4301 {
4302 i.suffix = WORD_MNEM_SUFFIX;
4303 break;
4304 }
4305 else if (i.types[op].bitfield.reg32)
4306 {
4307 i.suffix = LONG_MNEM_SUFFIX;
4308 break;
4309 }
4310 else if (i.types[op].bitfield.reg64)
4311 {
4312 i.suffix = QWORD_MNEM_SUFFIX;
4313 break;
4314 }
381d071f
L		 4315 }
4316 }
29b0f896
AM		 4317 }
4318 else if (i.suffix == BYTE_MNEM_SUFFIX)
4319 {
2eb952a4
L		 4320 if (intel_syntax
4321 && i.tm.opcode_modifier.ignoresize
4322 && i.tm.opcode_modifier.no_bsuf)
4323 i.suffix = 0;
4324 else if (!check_byte_reg ())
29b0f896
AM		 4325 return 0;
4326 }
4327 else if (i.suffix == LONG_MNEM_SUFFIX)
4328 {
2eb952a4
L		 4329 if (intel_syntax
4330 && i.tm.opcode_modifier.ignoresize
4331 && i.tm.opcode_modifier.no_lsuf)
4332 i.suffix = 0;
4333 else if (!check_long_reg ())
29b0f896
AM		 4334 return 0;
4335 }
4336 else if (i.suffix == QWORD_MNEM_SUFFIX)
4337 {
955e1e6a
L		 4338 if (intel_syntax
4339 && i.tm.opcode_modifier.ignoresize
4340 && i.tm.opcode_modifier.no_qsuf)
4341 i.suffix = 0;
4342 else if (!check_qword_reg ())
29b0f896
AM		 4343 return 0;
4344 }
4345 else if (i.suffix == WORD_MNEM_SUFFIX)
4346 {
2eb952a4
L		 4347 if (intel_syntax
4348 && i.tm.opcode_modifier.ignoresize
4349 && i.tm.opcode_modifier.no_wsuf)
4350 i.suffix = 0;
4351 else if (!check_word_reg ())
29b0f896
AM		 4352 return 0;
4353 }
c0f3af97
L		 4354 else if (i.suffix == XMMWORD_MNEM_SUFFIX
4355 || i.suffix == YMMWORD_MNEM_SUFFIX)
582d5edd 4356 {
c0f3af97 4357 /* Skip if the instruction has x/y suffix. match_template
582d5edd
L		 4358 should check if it is a valid suffix. */
4359 }
40fb9820 4360 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 4361 /* Do nothing if the instruction is going to ignore the prefix. */
4362 ;
4363 else
4364 abort ();
4365 }
40fb9820 4366 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 4367 && !i.suffix
4368 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 4369 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 4370 {
4371 i.suffix = stackop_size;
4372 }
9306ca4a
JB		 4373 else if (intel_syntax
4374 && !i.suffix
40fb9820
L		 4375 && (i.tm.operand_types[0].bitfield.jumpabsolute
4376 || i.tm.opcode_modifier.jumpbyte
4377 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 4378 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
4379 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 4380 {
4381 switch (flag_code)
4382 {
4383 case CODE_64BIT:
40fb9820 4384 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 4385 {
4386 i.suffix = QWORD_MNEM_SUFFIX;
4387 break;
4388 }
4389 case CODE_32BIT:
40fb9820 4390 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 4391 i.suffix = LONG_MNEM_SUFFIX;
4392 break;
4393 case CODE_16BIT:
40fb9820 4394 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 4395 i.suffix = WORD_MNEM_SUFFIX;
4396 break;
4397 }
4398 }
252b5132 4399
9306ca4a 4400 if (!i.suffix)
29b0f896 4401 {
9306ca4a
JB		 4402 if (!intel_syntax)
4403 {
40fb9820 4404 if (i.tm.opcode_modifier.w)
9306ca4a 4405 {
4eed87de
AM		 4406 as_bad (_("no instruction mnemonic suffix given and "
4407 "no register operands; can't size instruction"));
9306ca4a
JB		 4408 return 0;
4409 }
4410 }
4411 else
4412 {
40fb9820 4413 unsigned int suffixes;
7ab9ffdd 4414
40fb9820
L		 4415 suffixes = !i.tm.opcode_modifier.no_bsuf;
4416 if (!i.tm.opcode_modifier.no_wsuf)
4417 suffixes |= 1 << 1;
4418 if (!i.tm.opcode_modifier.no_lsuf)
4419 suffixes |= 1 << 2;
fc4adea1 4420 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 4421 suffixes |= 1 << 3;
4422 if (!i.tm.opcode_modifier.no_ssuf)
4423 suffixes |= 1 << 4;
4424 if (!i.tm.opcode_modifier.no_qsuf)
4425 suffixes |= 1 << 5;
4426
4427 /* There are more than suffix matches. */
4428 if (i.tm.opcode_modifier.w
9306ca4a 4429 || ((suffixes & (suffixes - 1))
40fb9820
L		 4430 && !i.tm.opcode_modifier.defaultsize
4431 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 4432 {
4433 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4434 return 0;
4435 }
4436 }
29b0f896 4437 }
252b5132 4438
9306ca4a
JB		 4439 /* Change the opcode based on the operand size given by i.suffix;
4440 We don't need to change things for byte insns. */
4441
582d5edd
L		 4442 if (i.suffix
4443 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97
L		 4444 && i.suffix != XMMWORD_MNEM_SUFFIX
4445 && i.suffix != YMMWORD_MNEM_SUFFIX)
29b0f896
AM		 4446 {
4447 /* It's not a byte, select word/dword operation. */
40fb9820 4448 if (i.tm.opcode_modifier.w)
29b0f896 4449 {
40fb9820 4450 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 4451 i.tm.base_opcode |= 8;
4452 else
4453 i.tm.base_opcode |= 1;
4454 }
0f3f3d8b 4455
29b0f896
AM		 4456 /* Now select between word & dword operations via the operand
4457 size prefix, except for instructions that will ignore this
4458 prefix anyway. */
ca61edf2 4459 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 4460 {
ca61edf2
L		 4461 /* The address size override prefix changes the size of the
4462 first operand. */
40fb9820
L		 4463 if ((flag_code == CODE_32BIT
4464 && i.op->regs[0].reg_type.bitfield.reg16)
4465 || (flag_code != CODE_32BIT
4466 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 4467 if (!add_prefix (ADDR_PREFIX_OPCODE))
4468 return 0;
4469 }
4470 else if (i.suffix != QWORD_MNEM_SUFFIX
4471 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 4472 && !i.tm.opcode_modifier.ignoresize
4473 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 4474 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
4475 || (flag_code == CODE_64BIT
40fb9820 4476 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 4477 {
4478 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 4479
40fb9820 4480 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 4481 prefix = ADDR_PREFIX_OPCODE;
252b5132 4482
29b0f896
AM		 4483 if (!add_prefix (prefix))
4484 return 0;
24eab124 4485 }
252b5132 4486
29b0f896
AM		 4487 /* Set mode64 for an operand. */
4488 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 4489 && flag_code == CODE_64BIT
40fb9820 4490 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 4491 {
4492 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 4493 need rex64. cmpxchg8b is also a special case. */
4494 if (! (i.operands == 2
4495 && i.tm.base_opcode == 0x90
4496 && i.tm.extension_opcode == None
0dfbf9d7
L		 4497 && operand_type_equal (&i.types [0], &acc64)
4498 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 4499 && ! (i.operands == 1
4500 && i.tm.base_opcode == 0xfc7
4501 && i.tm.extension_opcode == 1
40fb9820
L		 4502 && !operand_type_check (i.types [0], reg)
4503 && operand_type_check (i.types [0], anymem)))
f6bee062 4504 i.rex |= REX_W;
46e883c5 4505 }
3e73aa7c 4506
29b0f896
AM		 4507 /* Size floating point instruction. */
4508 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 4509 if (i.tm.opcode_modifier.floatmf)
543613e9 4510 i.tm.base_opcode ^= 4;
29b0f896 4511 }
7ecd2f8b 4512
29b0f896
AM		 4513 return 1;
4514}
3e73aa7c 4515
29b0f896 4516static int
543613e9 4517check_byte_reg (void)
29b0f896
AM		 4518{
4519 int op;
543613e9 4520
29b0f896
AM		 4521 for (op = i.operands; --op >= 0;)
4522 {
4523 /* If this is an eight bit register, it's OK. If it's the 16 or
4524 32 bit version of an eight bit register, we will just use the
4525 low portion, and that's OK too. */
40fb9820 4526 if (i.types[op].bitfield.reg8)
29b0f896
AM		 4527 continue;
4528
9344ff29
L		 4529 /* crc32 doesn't generate this warning. */
4530 if (i.tm.base_opcode == 0xf20f38f0)
4531 continue;
4532
40fb9820
L		 4533 if ((i.types[op].bitfield.reg16
4534 || i.types[op].bitfield.reg32
4535 || i.types[op].bitfield.reg64)
4536 && i.op[op].regs->reg_num < 4)
29b0f896
AM		 4537 {
4538 /* Prohibit these changes in the 64bit mode, since the
4539 lowering is more complicated. */
4540 if (flag_code == CODE_64BIT
40fb9820 4541 && !i.tm.operand_types[op].bitfield.inoutportreg)
29b0f896 4542 {
2ca3ace5
L		 4543 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4544 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4545 i.suffix);
4546 return 0;
4547 }
4548#if REGISTER_WARNINGS
4549 if (!quiet_warnings
40fb9820 4550 && !i.tm.operand_types[op].bitfield.inoutportreg)
a540244d
L		 4551 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4552 register_prefix,
40fb9820 4553 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 4554 ? REGNAM_AL - REGNAM_AX
4555 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 4556 register_prefix,
29b0f896
AM		 4557 i.op[op].regs->reg_name,
4558 i.suffix);
4559#endif
4560 continue;
4561 }
4562 /* Any other register is bad. */
40fb9820
L		 4563 if (i.types[op].bitfield.reg16
4564 || i.types[op].bitfield.reg32
4565 || i.types[op].bitfield.reg64
4566 || i.types[op].bitfield.regmmx
4567 || i.types[op].bitfield.regxmm
c0f3af97 4568 || i.types[op].bitfield.regymm
40fb9820
L		 4569 || i.types[op].bitfield.sreg2
4570 || i.types[op].bitfield.sreg3
4571 || i.types[op].bitfield.control
4572 || i.types[op].bitfield.debug
4573 || i.types[op].bitfield.test
4574 || i.types[op].bitfield.floatreg
4575 || i.types[op].bitfield.floatacc)
29b0f896 4576 {
a540244d
L		 4577 as_bad (_("`%s%s' not allowed with `%s%c'"),
4578 register_prefix,
29b0f896
AM		 4579 i.op[op].regs->reg_name,
4580 i.tm.name,
4581 i.suffix);
4582 return 0;
4583 }
4584 }
4585 return 1;
4586}
4587
4588static int
e3bb37b5 4589check_long_reg (void)
29b0f896
AM		 4590{
4591 int op;
4592
4593 for (op = i.operands; --op >= 0;)
4594 /* Reject eight bit registers, except where the template requires
4595 them. (eg. movzb) */
40fb9820
L		 4596 if (i.types[op].bitfield.reg8
4597 && (i.tm.operand_types[op].bitfield.reg16
4598 || i.tm.operand_types[op].bitfield.reg32
4599 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4600 {
a540244d
L		 4601 as_bad (_("`%s%s' not allowed with `%s%c'"),
4602 register_prefix,
29b0f896
AM		 4603 i.op[op].regs->reg_name,
4604 i.tm.name,
4605 i.suffix);
4606 return 0;
4607 }
4608 /* Warn if the e prefix on a general reg is missing. */
4609 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4610 && i.types[op].bitfield.reg16
4611 && (i.tm.operand_types[op].bitfield.reg32
4612 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4613 {
4614 /* Prohibit these changes in the 64bit mode, since the
4615 lowering is more complicated. */
4616 if (flag_code == CODE_64BIT)
252b5132 4617 {
2ca3ace5
L		 4618 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4619 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4620 i.suffix);
4621 return 0;
252b5132 4622 }
29b0f896
AM		 4623#if REGISTER_WARNINGS
4624 else
a540244d
L		 4625 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4626 register_prefix,
29b0f896 4627 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 4628 register_prefix,
29b0f896
AM		 4629 i.op[op].regs->reg_name,
4630 i.suffix);
4631#endif
252b5132 4632 }
29b0f896 4633 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 4634 else if (i.types[op].bitfield.reg64
4635 && (i.tm.operand_types[op].bitfield.reg32
4636 || i.tm.operand_types[op].bitfield.acc))
252b5132 4637 {
34828aad 4638 if (intel_syntax
ca61edf2 4639 && i.tm.opcode_modifier.toqword
40fb9820 4640 && !i.types[0].bitfield.regxmm)
34828aad 4641 {
ca61edf2 4642 /* Convert to QWORD. We want REX byte. */
34828aad
L		 4643 i.suffix = QWORD_MNEM_SUFFIX;
4644 }
4645 else
4646 {
4647 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4648 register_prefix, i.op[op].regs->reg_name,
4649 i.suffix);
4650 return 0;
4651 }
29b0f896
AM		 4652 }
4653 return 1;
4654}
252b5132 4655
29b0f896 4656static int
e3bb37b5 4657check_qword_reg (void)
29b0f896
AM		 4658{
4659 int op;
252b5132 4660
29b0f896
AM		 4661 for (op = i.operands; --op >= 0; )
4662 /* Reject eight bit registers, except where the template requires
4663 them. (eg. movzb) */
40fb9820
L		 4664 if (i.types[op].bitfield.reg8
4665 && (i.tm.operand_types[op].bitfield.reg16
4666 || i.tm.operand_types[op].bitfield.reg32
4667 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4668 {
a540244d
L		 4669 as_bad (_("`%s%s' not allowed with `%s%c'"),
4670 register_prefix,
29b0f896
AM		 4671 i.op[op].regs->reg_name,
4672 i.tm.name,
4673 i.suffix);
4674 return 0;
4675 }
4676 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 4677 else if ((i.types[op].bitfield.reg16
4678 || i.types[op].bitfield.reg32)
4679 && (i.tm.operand_types[op].bitfield.reg32
4680 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4681 {
4682 /* Prohibit these changes in the 64bit mode, since the
4683 lowering is more complicated. */
34828aad 4684 if (intel_syntax
ca61edf2 4685 && i.tm.opcode_modifier.todword
40fb9820 4686 && !i.types[0].bitfield.regxmm)
34828aad 4687 {
ca61edf2 4688 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 4689 i.suffix = LONG_MNEM_SUFFIX;
4690 }
4691 else
4692 {
4693 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4694 register_prefix, i.op[op].regs->reg_name,
4695 i.suffix);
4696 return 0;
4697 }
252b5132 4698 }
29b0f896
AM		 4699 return 1;
4700}
252b5132 4701
29b0f896 4702static int
e3bb37b5 4703check_word_reg (void)
29b0f896
AM		 4704{
4705 int op;
4706 for (op = i.operands; --op >= 0;)
4707 /* Reject eight bit registers, except where the template requires
4708 them. (eg. movzb) */
40fb9820
L		 4709 if (i.types[op].bitfield.reg8
4710 && (i.tm.operand_types[op].bitfield.reg16
4711 || i.tm.operand_types[op].bitfield.reg32
4712 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4713 {
a540244d
L		 4714 as_bad (_("`%s%s' not allowed with `%s%c'"),
4715 register_prefix,
29b0f896
AM		 4716 i.op[op].regs->reg_name,
4717 i.tm.name,
4718 i.suffix);
4719 return 0;
4720 }
4721 /* Warn if the e prefix on a general reg is present. */
4722 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4723 && i.types[op].bitfield.reg32
4724 && (i.tm.operand_types[op].bitfield.reg16
4725 || i.tm.operand_types[op].bitfield.acc))
252b5132 4726 {
29b0f896
AM		 4727 /* Prohibit these changes in the 64bit mode, since the
4728 lowering is more complicated. */
4729 if (flag_code == CODE_64BIT)
252b5132 4730 {
2ca3ace5
L		 4731 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4732 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4733 i.suffix);
4734 return 0;
252b5132 4735 }
29b0f896
AM		 4736 else
4737#if REGISTER_WARNINGS
a540244d
L		 4738 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4739 register_prefix,
29b0f896 4740 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 4741 register_prefix,
29b0f896
AM		 4742 i.op[op].regs->reg_name,
4743 i.suffix);
4744#endif
4745 }
4746 return 1;
4747}
252b5132 4748
29b0f896 4749static int
40fb9820 4750update_imm (unsigned int j)
29b0f896 4751{
bc0844ae 4752 i386_operand_type overlap = i.types[j];
40fb9820
L		 4753 if ((overlap.bitfield.imm8
4754 || overlap.bitfield.imm8s
4755 || overlap.bitfield.imm16
4756 || overlap.bitfield.imm32
4757 || overlap.bitfield.imm32s
4758 || overlap.bitfield.imm64)
0dfbf9d7
L		 4759 && !operand_type_equal (&overlap, &imm8)
4760 && !operand_type_equal (&overlap, &imm8s)
4761 && !operand_type_equal (&overlap, &imm16)
4762 && !operand_type_equal (&overlap, &imm32)
4763 && !operand_type_equal (&overlap, &imm32s)
4764 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 4765 {
4766 if (i.suffix)
4767 {
40fb9820
L		 4768 i386_operand_type temp;
4769
0dfbf9d7 4770 operand_type_set (&temp, 0);
7ab9ffdd 4771 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 4772 {
4773 temp.bitfield.imm8 = overlap.bitfield.imm8;
4774 temp.bitfield.imm8s = overlap.bitfield.imm8s;
4775 }
4776 else if (i.suffix == WORD_MNEM_SUFFIX)
4777 temp.bitfield.imm16 = overlap.bitfield.imm16;
4778 else if (i.suffix == QWORD_MNEM_SUFFIX)
4779 {
4780 temp.bitfield.imm64 = overlap.bitfield.imm64;
4781 temp.bitfield.imm32s = overlap.bitfield.imm32s;
4782 }
4783 else
4784 temp.bitfield.imm32 = overlap.bitfield.imm32;
4785 overlap = temp;
29b0f896 4786 }
0dfbf9d7
L		 4787 else if (operand_type_equal (&overlap, &imm16_32_32s)
4788 || operand_type_equal (&overlap, &imm16_32)
4789 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 4790 {
40fb9820 4791 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 4792 overlap = imm16;
40fb9820 4793 else
65da13b5 4794 overlap = imm32s;
29b0f896 4795 }
0dfbf9d7
L		 4796 if (!operand_type_equal (&overlap, &imm8)
4797 && !operand_type_equal (&overlap, &imm8s)
4798 && !operand_type_equal (&overlap, &imm16)
4799 && !operand_type_equal (&overlap, &imm32)
4800 && !operand_type_equal (&overlap, &imm32s)
4801 && !operand_type_equal (&overlap, &imm64))
29b0f896 4802 {
4eed87de
AM		 4803 as_bad (_("no instruction mnemonic suffix given; "
4804 "can't determine immediate size"));
29b0f896
AM		 4805 return 0;
4806 }
4807 }
40fb9820 4808 i.types[j] = overlap;
29b0f896 4809
40fb9820
L		 4810 return 1;
4811}
4812
4813static int
4814finalize_imm (void)
4815{
bc0844ae 4816 unsigned int j, n;
29b0f896 4817
bc0844ae
L		 4818 /* Update the first 2 immediate operands. */
4819 n = i.operands > 2 ? 2 : i.operands;
4820 if (n)
4821 {
4822 for (j = 0; j < n; j++)
4823 if (update_imm (j) == 0)
4824 return 0;
40fb9820 4825
bc0844ae
L		 4826 /* The 3rd operand can't be immediate operand. */
4827 gas_assert (operand_type_check (i.types[2], imm) == 0);
4828 }
29b0f896
AM		 4829
4830 return 1;
4831}
4832
c0f3af97
L		 4833static int
4834bad_implicit_operand (int xmm)
4835{
91d6fa6a
NC		 4836 const char *ireg = xmm ? "xmm0" : "ymm0";
4837
c0f3af97
L		 4838 if (intel_syntax)
4839 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 4840 i.tm.name, register_prefix, ireg);
c0f3af97
L		 4841 else
4842 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 4843 i.tm.name, register_prefix, ireg);
c0f3af97
L		 4844 return 0;
4845}
4846
29b0f896 4847static int
e3bb37b5 4848process_operands (void)
29b0f896
AM		 4849{
4850 /* Default segment register this instruction will use for memory
4851 accesses. 0 means unknown. This is only for optimizing out
4852 unnecessary segment overrides. */
4853 const seg_entry *default_seg = 0;
4854
2426c15f 4855 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 4856 {
91d6fa6a
NC		 4857 unsigned int dupl = i.operands;
4858 unsigned int dest = dupl - 1;
9fcfb3d7
L		 4859 unsigned int j;
4860
c0f3af97 4861 /* The destination must be an xmm register. */
9c2799c2 4862 gas_assert (i.reg_operands
91d6fa6a 4863 && MAX_OPERANDS > dupl
7ab9ffdd 4864 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 4865
4866 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 4867 {
c0f3af97 4868 /* The first operand is implicit and must be xmm0. */
9c2799c2 4869 gas_assert (operand_type_equal (&i.types[0], &regxmm));
c0f3af97
L		 4870 if (i.op[0].regs->reg_num != 0)
4871 return bad_implicit_operand (1);
4872
8cd7925b 4873 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 4874 {
4875 /* Keep xmm0 for instructions with VEX prefix and 3
4876 sources. */
4877 goto duplicate;
4878 }
e2ec9d29 4879 else
c0f3af97
L		 4880 {
4881 /* We remove the first xmm0 and keep the number of
4882 operands unchanged, which in fact duplicates the
4883 destination. */
4884 for (j = 1; j < i.operands; j++)
4885 {
4886 i.op[j - 1] = i.op[j];
4887 i.types[j - 1] = i.types[j];
4888 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
4889 }
4890 }
4891 }
4892 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 4893 {
91d6fa6a 4894 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 4895 && (i.tm.opcode_modifier.vexsources
4896 == VEX3SOURCES));
c0f3af97
L		 4897
4898 /* Add the implicit xmm0 for instructions with VEX prefix
4899 and 3 sources. */
4900 for (j = i.operands; j > 0; j--)
4901 {
4902 i.op[j] = i.op[j - 1];
4903 i.types[j] = i.types[j - 1];
4904 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
4905 }
4906 i.op[0].regs
4907 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 4908 i.types[0] = regxmm;
c0f3af97
L		 4909 i.tm.operand_types[0] = regxmm;
4910
4911 i.operands += 2;
4912 i.reg_operands += 2;
4913 i.tm.operands += 2;
4914
91d6fa6a 4915 dupl++;
c0f3af97 4916 dest++;
91d6fa6a
NC		 4917 i.op[dupl] = i.op[dest];
4918 i.types[dupl] = i.types[dest];
4919 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 4920 }
c0f3af97
L		 4921 else
4922 {
4923duplicate:
4924 i.operands++;
4925 i.reg_operands++;
4926 i.tm.operands++;
4927
91d6fa6a
NC		 4928 i.op[dupl] = i.op[dest];
4929 i.types[dupl] = i.types[dest];
4930 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 4931 }
4932
4933 if (i.tm.opcode_modifier.immext)
4934 process_immext ();
4935 }
4936 else if (i.tm.opcode_modifier.firstxmm0)
4937 {
4938 unsigned int j;
4939
4940 /* The first operand is implicit and must be xmm0/ymm0. */
9c2799c2 4941 gas_assert (i.reg_operands
7ab9ffdd
L		 4942 && (operand_type_equal (&i.types[0], &regxmm)
4943 || operand_type_equal (&i.types[0], &regymm)));
c0f3af97
L		 4944 if (i.op[0].regs->reg_num != 0)
4945 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 4946
4947 for (j = 1; j < i.operands; j++)
4948 {
4949 i.op[j - 1] = i.op[j];
4950 i.types[j - 1] = i.types[j];
4951
4952 /* We need to adjust fields in i.tm since they are used by
4953 build_modrm_byte. */
4954 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
4955 }
4956
e2ec9d29
L		 4957 i.operands--;
4958 i.reg_operands--;
e2ec9d29
L		 4959 i.tm.operands--;
4960 }
4961 else if (i.tm.opcode_modifier.regkludge)
4962 {
4963 /* The imul $imm, %reg instruction is converted into
4964 imul $imm, %reg, %reg, and the clr %reg instruction
4965 is converted into xor %reg, %reg. */
4966
4967 unsigned int first_reg_op;
4968
4969 if (operand_type_check (i.types[0], reg))
4970 first_reg_op = 0;
4971 else
4972 first_reg_op = 1;
4973 /* Pretend we saw the extra register operand. */
9c2799c2 4974 gas_assert (i.reg_operands == 1
7ab9ffdd 4975 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 4976 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
4977 i.types[first_reg_op + 1] = i.types[first_reg_op];
4978 i.operands++;
4979 i.reg_operands++;
29b0f896
AM		 4980 }
4981
40fb9820 4982 if (i.tm.opcode_modifier.shortform)
29b0f896 4983 {
40fb9820
L		 4984 if (i.types[0].bitfield.sreg2
4985 || i.types[0].bitfield.sreg3)
29b0f896 4986 {
4eed87de
AM		 4987 if (i.tm.base_opcode == POP_SEG_SHORT
4988 && i.op[0].regs->reg_num == 1)
29b0f896 4989 {
a87af027 4990 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 4991 return 0;
29b0f896 4992 }
4eed87de
AM		 4993 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
4994 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 4995 i.rex |= REX_B;
4eed87de
AM		 4996 }
4997 else
4998 {
7ab9ffdd 4999 /* The register or float register operand is in operand
85f10a01 5000 0 or 1. */
40fb9820 5001 unsigned int op;
7ab9ffdd
L		 5002
5003 if (i.types[0].bitfield.floatreg
5004 || operand_type_check (i.types[0], reg))
5005 op = 0;
5006 else
5007 op = 1;
4eed87de
AM		 5008 /* Register goes in low 3 bits of opcode. */
5009 i.tm.base_opcode |= i.op[op].regs->reg_num;
5010 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 5011 i.rex |= REX_B;
40fb9820 5012 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 5013 {
4eed87de
AM		 5014 /* Warn about some common errors, but press on regardless.
5015 The first case can be generated by gcc (<= 2.8.1). */
5016 if (i.operands == 2)
5017 {
5018 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 5019 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 5020 register_prefix, i.op[!intel_syntax].regs->reg_name,
5021 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 5022 }
5023 else
5024 {
5025 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 5026 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5027 register_prefix, i.op[0].regs->reg_name);
4eed87de 5028 }
29b0f896
AM		 5029 }
5030 }
5031 }
40fb9820 5032 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5033 {
5034 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 5035 must be put into the modrm byte). Now, we make the modrm and
5036 index base bytes based on all the info we've collected. */
29b0f896
AM		 5037
5038 default_seg = build_modrm_byte ();
5039 }
8a2ed489 5040 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 5041 {
5042 default_seg = &ds;
5043 }
40fb9820 5044 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 5045 {
5046 /* For the string instructions that allow a segment override
5047 on one of their operands, the default segment is ds. */
5048 default_seg = &ds;
5049 }
5050
75178d9d
L		 5051 if (i.tm.base_opcode == 0x8d /* lea */
5052 && i.seg[0]
5053 && !quiet_warnings)
30123838 5054 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 5055
5056 /* If a segment was explicitly specified, and the specified segment
5057 is not the default, use an opcode prefix to select it. If we
5058 never figured out what the default segment is, then default_seg
5059 will be zero at this point, and the specified segment prefix will
5060 always be used. */
29b0f896
AM		 5061 if ((i.seg[0]) && (i.seg[0] != default_seg))
5062 {
5063 if (!add_prefix (i.seg[0]->seg_prefix))
5064 return 0;
5065 }
5066 return 1;
5067}
5068
5069static const seg_entry *
e3bb37b5 5070build_modrm_byte (void)
29b0f896
AM		 5071{
5072 const seg_entry *default_seg = 0;
c0f3af97 5073 unsigned int source, dest;
8cd7925b 5074 int vex_3_sources;
c0f3af97
L		 5075
5076 /* The first operand of instructions with VEX prefix and 3 sources
5077 must be VEX_Imm4. */
8cd7925b 5078 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 5079 if (vex_3_sources)
5080 {
91d6fa6a 5081 unsigned int nds, reg_slot;
4c2c6516 5082 expressionS *exp;
c0f3af97 5083
922d8de8 5084 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 5085 && i.tm.opcode_modifier.immext)
5086 {
5087 dest = i.operands - 2;
5088 gas_assert (dest == 3);
5089 }
922d8de8 5090 else
a683cc34 5091 dest = i.operands - 1;
c0f3af97 5092 nds = dest - 1;
922d8de8 5093
a683cc34
SP		 5094 /* There are 2 kinds of instructions:
5095 1. 5 operands: 4 register operands or 3 register operands
5096 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5097 VexW0 or VexW1. The destination must be either XMM or YMM
5098 register.
5099 2. 4 operands: 4 register operands or 3 register operands
5100 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 5101 gas_assert ((i.reg_operands == 4
a683cc34
SP		 5102 || (i.reg_operands == 3 && i.mem_operands == 1))
5103 && i.tm.opcode_modifier.vexvvvv == VEXXDS
5104 && (i.tm.opcode_modifier.veximmext
5105 || (i.imm_operands == 1
5106 && i.types[0].bitfield.vec_imm4
5107 && (i.tm.opcode_modifier.vexw == VEXW0
5108 || i.tm.opcode_modifier.vexw == VEXW1)
5109 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
5110 || operand_type_equal (&i.tm.operand_types[dest], &regymm)))));
5111
5112 if (i.imm_operands == 0)
5113 {
5114 /* When there is no immediate operand, generate an 8bit
5115 immediate operand to encode the first operand. */
5116 exp = &im_expressions[i.imm_operands++];
5117 i.op[i.operands].imms = exp;
5118 i.types[i.operands] = imm8;
5119 i.operands++;
5120 /* If VexW1 is set, the first operand is the source and
5121 the second operand is encoded in the immediate operand. */
5122 if (i.tm.opcode_modifier.vexw == VEXW1)
5123 {
5124 source = 0;
5125 reg_slot = 1;
5126 }
5127 else
5128 {
5129 source = 1;
5130 reg_slot = 0;
5131 }
5132
5133 /* FMA swaps REG and NDS. */
5134 if (i.tm.cpu_flags.bitfield.cpufma)
5135 {
5136 unsigned int tmp;
5137 tmp = reg_slot;
5138 reg_slot = nds;
5139 nds = tmp;
5140 }
5141
24981e7b
L		 5142 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5143 &regxmm)
a683cc34
SP		 5144 || operand_type_equal (&i.tm.operand_types[reg_slot],
5145 &regymm));
5146 exp->X_op = O_constant;
5147 exp->X_add_number
5148 = ((i.op[reg_slot].regs->reg_num
24981e7b
L		 5149 + ((i.op[reg_slot].regs->reg_flags & RegRex) ? 8 : 0))
5150 << 4);
a683cc34 5151 }
922d8de8 5152 else
a683cc34
SP		 5153 {
5154 unsigned int imm_slot;
5155
5156 if (i.tm.opcode_modifier.vexw == VEXW0)
5157 {
5158 /* If VexW0 is set, the third operand is the source and
5159 the second operand is encoded in the immediate
5160 operand. */
5161 source = 2;
5162 reg_slot = 1;
5163 }
5164 else
5165 {
5166 /* VexW1 is set, the second operand is the source and
5167 the third operand is encoded in the immediate
5168 operand. */
5169 source = 1;
5170 reg_slot = 2;
5171 }
5172
5173 if (i.tm.opcode_modifier.immext)
5174 {
5175 /* When ImmExt is set, the immdiate byte is the last
5176 operand. */
5177 imm_slot = i.operands - 1;
5178 source--;
5179 reg_slot--;
5180 }
5181 else
5182 {
5183 imm_slot = 0;
5184
5185 /* Turn on Imm8 so that output_imm will generate it. */
5186 i.types[imm_slot].bitfield.imm8 = 1;
5187 }
5188
24981e7b
L		 5189 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5190 &regxmm)
5191 || operand_type_equal (&i.tm.operand_types[reg_slot],
5192 &regymm));
a683cc34
SP		 5193 i.op[imm_slot].imms->X_add_number
5194 |= ((i.op[reg_slot].regs->reg_num
24981e7b
L		 5195 + ((i.op[reg_slot].regs->reg_flags & RegRex) ? 8 : 0))
5196 << 4);
a683cc34
SP		 5197 }
5198
5199 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
5200 || operand_type_equal (&i.tm.operand_types[nds],
5201 &regymm));
dae39acc 5202 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 5203 }
5204 else
5205 source = dest = 0;
29b0f896
AM		 5206
5207 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 5208 implicit registers do not count. If there are 3 register
5209 operands, it must be a instruction with VexNDS. For a
5210 instruction with VexNDD, the destination register is encoded
5211 in VEX prefix. If there are 4 register operands, it must be
5212 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 5213 if (i.mem_operands == 0
5214 && ((i.reg_operands == 2
2426c15f 5215 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 5216 || (i.reg_operands == 3
2426c15f 5217 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 5218 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 5219 {
cab737b9
L		 5220 switch (i.operands)
5221 {
5222 case 2:
5223 source = 0;
5224 break;
5225 case 3:
c81128dc
L		 5226 /* When there are 3 operands, one of them may be immediate,
5227 which may be the first or the last operand. Otherwise,
c0f3af97
L		 5228 the first operand must be shift count register (cl) or it
5229 is an instruction with VexNDS. */
9c2799c2 5230 gas_assert (i.imm_operands == 1
7ab9ffdd 5231 || (i.imm_operands == 0
2426c15f 5232 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 5233 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 5234 if (operand_type_check (i.types[0], imm)
5235 || i.types[0].bitfield.shiftcount)
5236 source = 1;
5237 else
5238 source = 0;
cab737b9
L		 5239 break;
5240 case 4:
368d64cc
L		 5241 /* When there are 4 operands, the first two must be 8bit
5242 immediate operands. The source operand will be the 3rd
c0f3af97
L		 5243 one.
5244
5245 For instructions with VexNDS, if the first operand
5246 an imm8, the source operand is the 2nd one. If the last
5247 operand is imm8, the source operand is the first one. */
9c2799c2 5248 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 5249 && i.types[0].bitfield.imm8
5250 && i.types[1].bitfield.imm8)
2426c15f 5251 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 5252 && i.imm_operands == 1
5253 && (i.types[0].bitfield.imm8
5254 || i.types[i.operands - 1].bitfield.imm8)));
2426c15f 5255 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97
L		 5256 {
5257 if (i.types[0].bitfield.imm8)
5258 source = 1;
5259 else
5260 source = 0;
5261 }
5262 else
5263 source = 2;
5264 break;
5265 case 5:
cab737b9
L		 5266 break;
5267 default:
5268 abort ();
5269 }
5270
c0f3af97
L		 5271 if (!vex_3_sources)
5272 {
5273 dest = source + 1;
5274
2426c15f 5275 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97
L		 5276 {
5277 /* For instructions with VexNDS, the register-only
5278 source operand must be XMM or YMM register. It is
fa99fab2
L		 5279 encoded in VEX prefix. We need to clear RegMem bit
5280 before calling operand_type_equal. */
5281 i386_operand_type op = i.tm.operand_types[dest];
5282 op.bitfield.regmem = 0;
c0f3af97 5283 if ((dest + 1) >= i.operands
fa99fab2
L		 5284 || (!operand_type_equal (&op, &regxmm)
5285 && !operand_type_equal (&op, &regymm)))
c0f3af97
L		 5286 abort ();
5287 i.vex.register_specifier = i.op[dest].regs;
5288 dest++;
5289 }
5290 }
29b0f896
AM		 5291
5292 i.rm.mode = 3;
5293 /* One of the register operands will be encoded in the i.tm.reg
5294 field, the other in the combined i.tm.mode and i.tm.regmem
5295 fields. If no form of this instruction supports a memory
5296 destination operand, then we assume the source operand may
5297 sometimes be a memory operand and so we need to store the
5298 destination in the i.rm.reg field. */
40fb9820
L		 5299 if (!i.tm.operand_types[dest].bitfield.regmem
5300 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 5301 {
5302 i.rm.reg = i.op[dest].regs->reg_num;
5303 i.rm.regmem = i.op[source].regs->reg_num;
5304 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5305 i.rex |= REX_R;
29b0f896 5306 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5307 i.rex |= REX_B;
29b0f896
AM		 5308 }
5309 else
5310 {
5311 i.rm.reg = i.op[source].regs->reg_num;
5312 i.rm.regmem = i.op[dest].regs->reg_num;
5313 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5314 i.rex |= REX_B;
29b0f896 5315 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5316 i.rex |= REX_R;
29b0f896 5317 }
161a04f6 5318 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 5319 {
40fb9820
L		 5320 if (!i.types[0].bitfield.control
5321 && !i.types[1].bitfield.control)
c4a530c5 5322 abort ();
161a04f6 5323 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 5324 add_prefix (LOCK_PREFIX_OPCODE);
5325 }
29b0f896
AM		 5326 }
5327 else
5328 { /* If it's not 2 reg operands... */
c0f3af97
L		 5329 unsigned int mem;
5330
29b0f896
AM		 5331 if (i.mem_operands)
5332 {
5333 unsigned int fake_zero_displacement = 0;
99018f42 5334 unsigned int op;
4eed87de 5335
7ab9ffdd
L		 5336 for (op = 0; op < i.operands; op++)
5337 if (operand_type_check (i.types[op], anymem))
5338 break;
7ab9ffdd 5339 gas_assert (op < i.operands);
29b0f896
AM		 5340
5341 default_seg = &ds;
5342
5343 if (i.base_reg == 0)
5344 {
5345 i.rm.mode = 0;
5346 if (!i.disp_operands)
5347 fake_zero_displacement = 1;
5348 if (i.index_reg == 0)
5349 {
5350 /* Operand is just <disp> */
20f0a1fc 5351 if (flag_code == CODE_64BIT)
29b0f896
AM		 5352 {
5353 /* 64bit mode overwrites the 32bit absolute
5354 addressing by RIP relative addressing and
5355 absolute addressing is encoded by one of the
5356 redundant SIB forms. */
5357 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5358 i.sib.base = NO_BASE_REGISTER;
5359 i.sib.index = NO_INDEX_REGISTER;
fc225355 5360 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 5361 ? disp32s : disp32);
20f0a1fc 5362 }
fc225355
L		 5363 else if ((flag_code == CODE_16BIT)
5364 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 5365 {
5366 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 5367 i.types[op] = disp16;
20f0a1fc
NC		 5368 }
5369 else
5370 {
5371 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 5372 i.types[op] = disp32;
29b0f896
AM		 5373 }
5374 }
5375 else /* !i.base_reg && i.index_reg */
5376 {
db51cc60
L		 5377 if (i.index_reg->reg_num == RegEiz
5378 || i.index_reg->reg_num == RegRiz)
5379 i.sib.index = NO_INDEX_REGISTER;
5380 else
5381 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5382 i.sib.base = NO_BASE_REGISTER;
5383 i.sib.scale = i.log2_scale_factor;
5384 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 5385 i.types[op].bitfield.disp8 = 0;
5386 i.types[op].bitfield.disp16 = 0;
5387 i.types[op].bitfield.disp64 = 0;
29b0f896 5388 if (flag_code != CODE_64BIT)
40fb9820
L		 5389 {
5390 /* Must be 32 bit */
5391 i.types[op].bitfield.disp32 = 1;
5392 i.types[op].bitfield.disp32s = 0;
5393 }
29b0f896 5394 else
40fb9820
L		 5395 {
5396 i.types[op].bitfield.disp32 = 0;
5397 i.types[op].bitfield.disp32s = 1;
5398 }
29b0f896 5399 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5400 i.rex |= REX_X;
29b0f896
AM		 5401 }
5402 }
5403 /* RIP addressing for 64bit mode. */
9a04903e
JB		 5404 else if (i.base_reg->reg_num == RegRip ||
5405 i.base_reg->reg_num == RegEip)
29b0f896
AM		 5406 {
5407 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 5408 i.types[op].bitfield.disp8 = 0;
5409 i.types[op].bitfield.disp16 = 0;
5410 i.types[op].bitfield.disp32 = 0;
5411 i.types[op].bitfield.disp32s = 1;
5412 i.types[op].bitfield.disp64 = 0;
71903a11 5413 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 5414 if (! i.disp_operands)
5415 fake_zero_displacement = 1;
29b0f896 5416 }
40fb9820 5417 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896
AM		 5418 {
5419 switch (i.base_reg->reg_num)
5420 {
5421 case 3: /* (%bx) */
5422 if (i.index_reg == 0)
5423 i.rm.regmem = 7;
5424 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5425 i.rm.regmem = i.index_reg->reg_num - 6;
5426 break;
5427 case 5: /* (%bp) */
5428 default_seg = &ss;
5429 if (i.index_reg == 0)
5430 {
5431 i.rm.regmem = 6;
40fb9820 5432 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 5433 {
5434 /* fake (%bp) into 0(%bp) */
40fb9820 5435 i.types[op].bitfield.disp8 = 1;
252b5132 5436 fake_zero_displacement = 1;
29b0f896
AM		 5437 }
5438 }
5439 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5440 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
5441 break;
5442 default: /* (%si) -> 4 or (%di) -> 5 */
5443 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
5444 }
5445 i.rm.mode = mode_from_disp_size (i.types[op]);
5446 }
5447 else /* i.base_reg and 32/64 bit mode */
5448 {
5449 if (flag_code == CODE_64BIT
40fb9820
L		 5450 && operand_type_check (i.types[op], disp))
5451 {
5452 i386_operand_type temp;
0dfbf9d7 5453 operand_type_set (&temp, 0);
40fb9820
L		 5454 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
5455 i.types[op] = temp;
5456 if (i.prefix[ADDR_PREFIX] == 0)
5457 i.types[op].bitfield.disp32s = 1;
5458 else
5459 i.types[op].bitfield.disp32 = 1;
5460 }
20f0a1fc 5461
29b0f896
AM		 5462 i.rm.regmem = i.base_reg->reg_num;
5463 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 5464 i.rex |= REX_B;
29b0f896
AM		 5465 i.sib.base = i.base_reg->reg_num;
5466 /* x86-64 ignores REX prefix bit here to avoid decoder
5467 complications. */
5468 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
5469 {
5470 default_seg = &ss;
5471 if (i.disp_operands == 0)
5472 {
5473 fake_zero_displacement = 1;
40fb9820 5474 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 5475 }
5476 }
5477 else if (i.base_reg->reg_num == ESP_REG_NUM)
5478 {
5479 default_seg = &ss;
5480 }
5481 i.sib.scale = i.log2_scale_factor;
5482 if (i.index_reg == 0)
5483 {
5484 /* <disp>(%esp) becomes two byte modrm with no index
5485 register. We've already stored the code for esp
5486 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5487 Any base register besides %esp will not use the
5488 extra modrm byte. */
5489 i.sib.index = NO_INDEX_REGISTER;
29b0f896
AM		 5490 }
5491 else
5492 {
db51cc60
L		 5493 if (i.index_reg->reg_num == RegEiz
5494 || i.index_reg->reg_num == RegRiz)
5495 i.sib.index = NO_INDEX_REGISTER;
5496 else
5497 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5498 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5499 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5500 i.rex |= REX_X;
29b0f896 5501 }
67a4f2b7
AO		 5502
5503 if (i.disp_operands
5504 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
5505 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
5506 i.rm.mode = 0;
5507 else
5508 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 5509 }
252b5132 5510
29b0f896
AM		 5511 if (fake_zero_displacement)
5512 {
5513 /* Fakes a zero displacement assuming that i.types[op]
5514 holds the correct displacement size. */
5515 expressionS *exp;
5516
9c2799c2 5517 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 5518 exp = &disp_expressions[i.disp_operands++];
5519 i.op[op].disps = exp;
5520 exp->X_op = O_constant;
5521 exp->X_add_number = 0;
5522 exp->X_add_symbol = (symbolS *) 0;
5523 exp->X_op_symbol = (symbolS *) 0;
5524 }
c0f3af97
L		 5525
5526 mem = op;
29b0f896 5527 }
c0f3af97
L		 5528 else
5529 mem = ~0;
252b5132 5530
8c43a48b 5531 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 5532 {
5533 if (operand_type_check (i.types[0], imm))
5534 i.vex.register_specifier = NULL;
5535 else
5536 {
5537 /* VEX.vvvv encodes one of the sources when the first
5538 operand is not an immediate. */
1ef99a7b 5539 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 5540 i.vex.register_specifier = i.op[0].regs;
5541 else
5542 i.vex.register_specifier = i.op[1].regs;
5543 }
5544
5545 /* Destination is a XMM register encoded in the ModRM.reg
5546 and VEX.R bit. */
5547 i.rm.reg = i.op[2].regs->reg_num;
5548 if ((i.op[2].regs->reg_flags & RegRex) != 0)
5549 i.rex |= REX_R;
5550
5551 /* ModRM.rm and VEX.B encodes the other source. */
5552 if (!i.mem_operands)
5553 {
5554 i.rm.mode = 3;
5555
1ef99a7b 5556 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 5557 i.rm.regmem = i.op[1].regs->reg_num;
5558 else
5559 i.rm.regmem = i.op[0].regs->reg_num;
5560
5561 if ((i.op[1].regs->reg_flags & RegRex) != 0)
5562 i.rex |= REX_B;
5563 }
5564 }
2426c15f 5565 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 5566 {
5567 i.vex.register_specifier = i.op[2].regs;
5568 if (!i.mem_operands)
5569 {
5570 i.rm.mode = 3;
5571 i.rm.regmem = i.op[1].regs->reg_num;
5572 if ((i.op[1].regs->reg_flags & RegRex) != 0)
5573 i.rex |= REX_B;
5574 }
5575 }
29b0f896
AM		 5576 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5577 (if any) based on i.tm.extension_opcode. Again, we must be
5578 careful to make sure that segment/control/debug/test/MMX
5579 registers are coded into the i.rm.reg field. */
f88c9eb0 5580 else if (i.reg_operands)
29b0f896 5581 {
99018f42 5582 unsigned int op;
7ab9ffdd
L		 5583 unsigned int vex_reg = ~0;
5584
5585 for (op = 0; op < i.operands; op++)
5586 if (i.types[op].bitfield.reg8
5587 || i.types[op].bitfield.reg16
5588 || i.types[op].bitfield.reg32
5589 || i.types[op].bitfield.reg64
5590 || i.types[op].bitfield.regmmx
5591 || i.types[op].bitfield.regxmm
5592 || i.types[op].bitfield.regymm
5593 || i.types[op].bitfield.sreg2
5594 || i.types[op].bitfield.sreg3
5595 || i.types[op].bitfield.control
5596 || i.types[op].bitfield.debug
5597 || i.types[op].bitfield.test)
5598 break;
c0209578 5599
7ab9ffdd
L		 5600 if (vex_3_sources)
5601 op = dest;
2426c15f 5602 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 5603 {
5604 /* For instructions with VexNDS, the register-only
5605 source operand is encoded in VEX prefix. */
5606 gas_assert (mem != (unsigned int) ~0);
c0f3af97 5607
7ab9ffdd 5608 if (op > mem)
c0f3af97 5609 {
7ab9ffdd
L		 5610 vex_reg = op++;
5611 gas_assert (op < i.operands);
c0f3af97
L		 5612 }
5613 else
c0f3af97 5614 {
7ab9ffdd
L		 5615 vex_reg = op + 1;
5616 gas_assert (vex_reg < i.operands);
c0f3af97 5617 }
7ab9ffdd 5618 }
2426c15f 5619 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd
L		 5620 {
5621 /* For instructions with VexNDD, there should be
5622 no memory operand and the register destination
5623 is encoded in VEX prefix. */
5624 gas_assert (i.mem_operands == 0
5625 && (op + 2) == i.operands);
5626 vex_reg = op + 1;
5627 }
5628 else
5629 gas_assert (op < i.operands);
99018f42 5630
7ab9ffdd
L		 5631 if (vex_reg != (unsigned int) ~0)
5632 {
5633 gas_assert (i.reg_operands == 2);
5634
5635 if (!operand_type_equal (&i.tm.operand_types[vex_reg],
76ba9986 5636 &regxmm)
7ab9ffdd
L		 5637 && !operand_type_equal (&i.tm.operand_types[vex_reg],
5638 &regymm))
5639 abort ();
f88c9eb0 5640
7ab9ffdd
L		 5641 i.vex.register_specifier = i.op[vex_reg].regs;
5642 }
5643
1b9f0c97
L		 5644 /* Don't set OP operand twice. */
5645 if (vex_reg != op)
7ab9ffdd 5646 {
1b9f0c97
L		 5647 /* If there is an extension opcode to put here, the
5648 register number must be put into the regmem field. */
5649 if (i.tm.extension_opcode != None)
5650 {
5651 i.rm.regmem = i.op[op].regs->reg_num;
5652 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5653 i.rex |= REX_B;
5654 }
5655 else
5656 {
5657 i.rm.reg = i.op[op].regs->reg_num;
5658 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5659 i.rex |= REX_R;
5660 }
7ab9ffdd 5661 }
252b5132 5662
29b0f896
AM		 5663 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5664 must set it to 3 to indicate this is a register operand
5665 in the regmem field. */
5666 if (!i.mem_operands)
5667 i.rm.mode = 3;
5668 }
252b5132 5669
29b0f896 5670 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 5671 if (i.tm.extension_opcode != None)
29b0f896
AM		 5672 i.rm.reg = i.tm.extension_opcode;
5673 }
5674 return default_seg;
5675}
252b5132 5676
29b0f896 5677static void
e3bb37b5 5678output_branch (void)
29b0f896
AM		 5679{
5680 char *p;
5681 int code16;
5682 int prefix;
5683 relax_substateT subtype;
5684 symbolS *sym;
5685 offsetT off;
5686
5687 code16 = 0;
5688 if (flag_code == CODE_16BIT)
5689 code16 = CODE16;
5690
5691 prefix = 0;
5692 if (i.prefix[DATA_PREFIX] != 0)
252b5132 5693 {
29b0f896
AM		 5694 prefix = 1;
5695 i.prefixes -= 1;
5696 code16 ^= CODE16;
252b5132 5697 }
29b0f896
AM		 5698 /* Pentium4 branch hints. */
5699 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5700 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 5701 {
29b0f896
AM		 5702 prefix++;
5703 i.prefixes--;
5704 }
5705 if (i.prefix[REX_PREFIX] != 0)
5706 {
5707 prefix++;
5708 i.prefixes--;
2f66722d
AM		 5709 }
5710
29b0f896
AM		 5711 if (i.prefixes != 0 && !intel_syntax)
5712 as_warn (_("skipping prefixes on this instruction"));
5713
5714 /* It's always a symbol; End frag & setup for relax.
5715 Make sure there is enough room in this frag for the largest
5716 instruction we may generate in md_convert_frag. This is 2
5717 bytes for the opcode and room for the prefix and largest
5718 displacement. */
5719 frag_grow (prefix + 2 + 4);
5720 /* Prefix and 1 opcode byte go in fr_fix. */
5721 p = frag_more (prefix + 1);
5722 if (i.prefix[DATA_PREFIX] != 0)
5723 *p++ = DATA_PREFIX_OPCODE;
5724 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
5725 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
5726 *p++ = i.prefix[SEG_PREFIX];
5727 if (i.prefix[REX_PREFIX] != 0)
5728 *p++ = i.prefix[REX_PREFIX];
5729 *p = i.tm.base_opcode;
5730
5731 if ((unsigned char) *p == JUMP_PC_RELATIVE)
5732 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
40fb9820 5733 else if (cpu_arch_flags.bitfield.cpui386)
29b0f896
AM		 5734 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
5735 else
5736 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
5737 subtype |= code16;
3e73aa7c 5738
29b0f896
AM		 5739 sym = i.op[0].disps->X_add_symbol;
5740 off = i.op[0].disps->X_add_number;
3e73aa7c 5741
29b0f896
AM		 5742 if (i.op[0].disps->X_op != O_constant
5743 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 5744 {
29b0f896
AM		 5745 /* Handle complex expressions. */
5746 sym = make_expr_symbol (i.op[0].disps);
5747 off = 0;
5748 }
3e73aa7c 5749
29b0f896
AM		 5750 /* 1 possible extra opcode + 4 byte displacement go in var part.
5751 Pass reloc in fr_var. */
5752 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
5753}
3e73aa7c 5754
29b0f896 5755static void
e3bb37b5 5756output_jump (void)
29b0f896
AM		 5757{
5758 char *p;
5759 int size;
3e02c1cc 5760 fixS *fixP;
29b0f896 5761
40fb9820 5762 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 5763 {
5764 /* This is a loop or jecxz type instruction. */
5765 size = 1;
5766 if (i.prefix[ADDR_PREFIX] != 0)
5767 {
5768 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
5769 i.prefixes -= 1;
5770 }
5771 /* Pentium4 branch hints. */
5772 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5773 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5774 {
5775 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
5776 i.prefixes--;
3e73aa7c
JH		 5777 }
5778 }
29b0f896
AM		 5779 else
5780 {
5781 int code16;
3e73aa7c 5782
29b0f896
AM		 5783 code16 = 0;
5784 if (flag_code == CODE_16BIT)
5785 code16 = CODE16;
3e73aa7c 5786
29b0f896
AM		 5787 if (i.prefix[DATA_PREFIX] != 0)
5788 {
5789 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
5790 i.prefixes -= 1;
5791 code16 ^= CODE16;
5792 }
252b5132 5793
29b0f896
AM		 5794 size = 4;
5795 if (code16)
5796 size = 2;
5797 }
9fcc94b6 5798
29b0f896
AM		 5799 if (i.prefix[REX_PREFIX] != 0)
5800 {
5801 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
5802 i.prefixes -= 1;
5803 }
252b5132 5804
29b0f896
AM		 5805 if (i.prefixes != 0 && !intel_syntax)
5806 as_warn (_("skipping prefixes on this instruction"));
e0890092 5807
29b0f896
AM		 5808 p = frag_more (1 + size);
5809 *p++ = i.tm.base_opcode;
e0890092 5810
3e02c1cc
AM		 5811 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5812 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
5813
5814 /* All jumps handled here are signed, but don't use a signed limit
5815 check for 32 and 16 bit jumps as we want to allow wrap around at
5816 4G and 64k respectively. */
5817 if (size == 1)
5818 fixP->fx_signed = 1;
29b0f896 5819}
e0890092 5820
29b0f896 5821static void
e3bb37b5 5822output_interseg_jump (void)
29b0f896
AM		 5823{
5824 char *p;
5825 int size;
5826 int prefix;
5827 int code16;
252b5132 5828
29b0f896
AM		 5829 code16 = 0;
5830 if (flag_code == CODE_16BIT)
5831 code16 = CODE16;
a217f122 5832
29b0f896
AM		 5833 prefix = 0;
5834 if (i.prefix[DATA_PREFIX] != 0)
5835 {
5836 prefix = 1;
5837 i.prefixes -= 1;
5838 code16 ^= CODE16;
5839 }
5840 if (i.prefix[REX_PREFIX] != 0)
5841 {
5842 prefix++;
5843 i.prefixes -= 1;
5844 }
252b5132 5845
29b0f896
AM		 5846 size = 4;
5847 if (code16)
5848 size = 2;
252b5132 5849
29b0f896
AM		 5850 if (i.prefixes != 0 && !intel_syntax)
5851 as_warn (_("skipping prefixes on this instruction"));
252b5132 5852
29b0f896
AM		 5853 /* 1 opcode; 2 segment; offset */
5854 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 5855
29b0f896
AM		 5856 if (i.prefix[DATA_PREFIX] != 0)
5857 *p++ = DATA_PREFIX_OPCODE;
252b5132 5858
29b0f896
AM		 5859 if (i.prefix[REX_PREFIX] != 0)
5860 *p++ = i.prefix[REX_PREFIX];
252b5132 5861
29b0f896
AM		 5862 *p++ = i.tm.base_opcode;
5863 if (i.op[1].imms->X_op == O_constant)
5864 {
5865 offsetT n = i.op[1].imms->X_add_number;
252b5132 5866
29b0f896
AM		 5867 if (size == 2
5868 && !fits_in_unsigned_word (n)
5869 && !fits_in_signed_word (n))
5870 {
5871 as_bad (_("16-bit jump out of range"));
5872 return;
5873 }
5874 md_number_to_chars (p, n, size);
5875 }
5876 else
5877 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5878 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
5879 if (i.op[0].imms->X_op != O_constant)
5880 as_bad (_("can't handle non absolute segment in `%s'"),
5881 i.tm.name);
5882 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
5883}
a217f122 5884
29b0f896 5885static void
e3bb37b5 5886output_insn (void)
29b0f896 5887{
2bbd9c25
JJ		 5888 fragS *insn_start_frag;
5889 offsetT insn_start_off;
5890
29b0f896
AM		 5891 /* Tie dwarf2 debug info to the address at the start of the insn.
5892 We can't do this after the insn has been output as the current
5893 frag may have been closed off. eg. by frag_var. */
5894 dwarf2_emit_insn (0);
5895
2bbd9c25
JJ		 5896 insn_start_frag = frag_now;
5897 insn_start_off = frag_now_fix ();
5898
29b0f896 5899 /* Output jumps. */
40fb9820 5900 if (i.tm.opcode_modifier.jump)
29b0f896 5901 output_branch ();
40fb9820
L		 5902 else if (i.tm.opcode_modifier.jumpbyte
5903 || i.tm.opcode_modifier.jumpdword)
29b0f896 5904 output_jump ();
40fb9820 5905 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 5906 output_interseg_jump ();
5907 else
5908 {
5909 /* Output normal instructions here. */
5910 char *p;
5911 unsigned char *q;
47465058 5912 unsigned int j;
331d2d0d 5913 unsigned int prefix;
4dffcebc 5914
c0f3af97
L		 5915 /* Since the VEX prefix contains the implicit prefix, we don't
5916 need the explicit prefix. */
5917 if (!i.tm.opcode_modifier.vex)
bc4bd9ab 5918 {
c0f3af97 5919 switch (i.tm.opcode_length)
bc4bd9ab 5920 {
c0f3af97
L		 5921 case 3:
5922 if (i.tm.base_opcode & 0xff000000)
4dffcebc 5923 {
c0f3af97
L		 5924 prefix = (i.tm.base_opcode >> 24) & 0xff;
5925 goto check_prefix;
5926 }
5927 break;
5928 case 2:
5929 if ((i.tm.base_opcode & 0xff0000) != 0)
5930 {
5931 prefix = (i.tm.base_opcode >> 16) & 0xff;
5932 if (i.tm.cpu_flags.bitfield.cpupadlock)
5933 {
4dffcebc 5934check_prefix:
c0f3af97 5935 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 5936 || (i.prefix[REP_PREFIX]
c0f3af97
L		 5937 != REPE_PREFIX_OPCODE))
5938 add_prefix (prefix);
5939 }
5940 else
4dffcebc
L		 5941 add_prefix (prefix);
5942 }
c0f3af97
L		 5943 break;
5944 case 1:
5945 break;
5946 default:
5947 abort ();
bc4bd9ab 5948 }
c0f3af97
L		 5949
5950 /* The prefix bytes. */
5951 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
5952 if (*q)
5953 FRAG_APPEND_1_CHAR (*q);
0f10071e 5954 }
252b5132 5955
c0f3af97
L		 5956 if (i.tm.opcode_modifier.vex)
5957 {
5958 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
5959 if (*q)
5960 switch (j)
5961 {
5962 case REX_PREFIX:
5963 /* REX byte is encoded in VEX prefix. */
5964 break;
5965 case SEG_PREFIX:
5966 case ADDR_PREFIX:
5967 FRAG_APPEND_1_CHAR (*q);
5968 break;
5969 default:
5970 /* There should be no other prefixes for instructions
5971 with VEX prefix. */
5972 abort ();
5973 }
5974
5975 /* Now the VEX prefix. */
5976 p = frag_more (i.vex.length);
5977 for (j = 0; j < i.vex.length; j++)
5978 p[j] = i.vex.bytes[j];
5979 }
252b5132 5980
29b0f896 5981 /* Now the opcode; be careful about word order here! */
4dffcebc 5982 if (i.tm.opcode_length == 1)
29b0f896
AM		 5983 {
5984 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5985 }
5986 else
5987 {
4dffcebc 5988 switch (i.tm.opcode_length)
331d2d0d 5989 {
4dffcebc 5990 case 3:
331d2d0d
L		 5991 p = frag_more (3);
5992 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 5993 break;
5994 case 2:
5995 p = frag_more (2);
5996 break;
5997 default:
5998 abort ();
5999 break;
331d2d0d 6000 }
0f10071e 6001
29b0f896
AM		 6002 /* Put out high byte first: can't use md_number_to_chars! */
6003 *p++ = (i.tm.base_opcode >> 8) & 0xff;
6004 *p = i.tm.base_opcode & 0xff;
6005 }
3e73aa7c 6006
29b0f896 6007 /* Now the modrm byte and sib byte (if present). */
40fb9820 6008 if (i.tm.opcode_modifier.modrm)
29b0f896 6009 {
4a3523fa
L		 6010 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
6011 | i.rm.reg << 3
6012 | i.rm.mode << 6));
29b0f896
AM		 6013 /* If i.rm.regmem == ESP (4)
6014 && i.rm.mode != (Register mode)
6015 && not 16 bit
6016 ==> need second modrm byte. */
6017 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
6018 && i.rm.mode != 3
40fb9820 6019 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 6020 FRAG_APPEND_1_CHAR ((i.sib.base << 0
6021 | i.sib.index << 3
6022 | i.sib.scale << 6));
29b0f896 6023 }
3e73aa7c 6024
29b0f896 6025 if (i.disp_operands)
2bbd9c25 6026 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 6027
29b0f896 6028 if (i.imm_operands)
2bbd9c25 6029 output_imm (insn_start_frag, insn_start_off);
29b0f896 6030 }
252b5132 6031
29b0f896
AM		 6032#ifdef DEBUG386
6033 if (flag_debug)
6034 {
7b81dfbb 6035 pi ("" /*line*/, &i);
29b0f896
AM		 6036 }
6037#endif /* DEBUG386 */
6038}
252b5132 6039
e205caa7
L		 6040/* Return the size of the displacement operand N. */
6041
6042static int
6043disp_size (unsigned int n)
6044{
6045 int size = 4;
40fb9820
L		 6046 if (i.types[n].bitfield.disp64)
6047 size = 8;
6048 else if (i.types[n].bitfield.disp8)
6049 size = 1;
6050 else if (i.types[n].bitfield.disp16)
6051 size = 2;
e205caa7
L		 6052 return size;
6053}
6054
6055/* Return the size of the immediate operand N. */
6056
6057static int
6058imm_size (unsigned int n)
6059{
6060 int size = 4;
40fb9820
L		 6061 if (i.types[n].bitfield.imm64)
6062 size = 8;
6063 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
6064 size = 1;
6065 else if (i.types[n].bitfield.imm16)
6066 size = 2;
e205caa7
L		 6067 return size;
6068}
6069
29b0f896 6070static void
64e74474 6071output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 6072{
6073 char *p;
6074 unsigned int n;
252b5132 6075
29b0f896
AM		 6076 for (n = 0; n < i.operands; n++)
6077 {
40fb9820 6078 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 6079 {
6080 if (i.op[n].disps->X_op == O_constant)
6081 {
e205caa7 6082 int size = disp_size (n);
29b0f896 6083 offsetT val;
252b5132 6084
29b0f896
AM		 6085 val = offset_in_range (i.op[n].disps->X_add_number,
6086 size);
6087 p = frag_more (size);
6088 md_number_to_chars (p, val, size);
6089 }
6090 else
6091 {
f86103b7 6092 enum bfd_reloc_code_real reloc_type;
e205caa7 6093 int size = disp_size (n);
40fb9820 6094 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 6095 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
6096
e205caa7 6097 /* We can't have 8 bit displacement here. */
9c2799c2 6098 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 6099
29b0f896
AM		 6100 /* The PC relative address is computed relative
6101 to the instruction boundary, so in case immediate
6102 fields follows, we need to adjust the value. */
6103 if (pcrel && i.imm_operands)
6104 {
29b0f896 6105 unsigned int n1;
e205caa7 6106 int sz = 0;
252b5132 6107
29b0f896 6108 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 6109 if (operand_type_check (i.types[n1], imm))
252b5132 6110 {
e205caa7
L		 6111 /* Only one immediate is allowed for PC
6112 relative address. */
9c2799c2 6113 gas_assert (sz == 0);
e205caa7
L		 6114 sz = imm_size (n1);
6115 i.op[n].disps->X_add_number -= sz;
252b5132 6116 }
29b0f896 6117 /* We should find the immediate. */
9c2799c2 6118 gas_assert (sz != 0);
29b0f896 6119 }
520dc8e8 6120
29b0f896 6121 p = frag_more (size);
2bbd9c25 6122 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 6123 if (GOT_symbol
2bbd9c25 6124 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 6125 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6126 || reloc_type == BFD_RELOC_X86_64_32S
6127 || (reloc_type == BFD_RELOC_64
6128 && object_64bit))
d6ab8113
JB		 6129 && (i.op[n].disps->X_op == O_symbol
6130 || (i.op[n].disps->X_op == O_add
6131 && ((symbol_get_value_expression
6132 (i.op[n].disps->X_op_symbol)->X_op)
6133 == O_subtract))))
6134 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 6135 {
6136 offsetT add;
6137
6138 if (insn_start_frag == frag_now)
6139 add = (p - frag_now->fr_literal) - insn_start_off;
6140 else
6141 {
6142 fragS *fr;
6143
6144 add = insn_start_frag->fr_fix - insn_start_off;
6145 for (fr = insn_start_frag->fr_next;
6146 fr && fr != frag_now; fr = fr->fr_next)
6147 add += fr->fr_fix;
6148 add += p - frag_now->fr_literal;
6149 }
6150
4fa24527 6151 if (!object_64bit)
7b81dfbb
AJ		 6152 {
6153 reloc_type = BFD_RELOC_386_GOTPC;
6154 i.op[n].imms->X_add_number += add;
6155 }
6156 else if (reloc_type == BFD_RELOC_64)
6157 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 6158 else
7b81dfbb
AJ		 6159 /* Don't do the adjustment for x86-64, as there
6160 the pcrel addressing is relative to the _next_
6161 insn, and that is taken care of in other code. */
d6ab8113 6162 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 6163 }
062cd5e7 6164 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 6165 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 6166 }
6167 }
6168 }
6169}
252b5132 6170
29b0f896 6171static void
64e74474 6172output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 6173{
6174 char *p;
6175 unsigned int n;
252b5132 6176
29b0f896
AM		 6177 for (n = 0; n < i.operands; n++)
6178 {
40fb9820 6179 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 6180 {
6181 if (i.op[n].imms->X_op == O_constant)
6182 {
e205caa7 6183 int size = imm_size (n);
29b0f896 6184 offsetT val;
b4cac588 6185
29b0f896
AM		 6186 val = offset_in_range (i.op[n].imms->X_add_number,
6187 size);
6188 p = frag_more (size);
6189 md_number_to_chars (p, val, size);
6190 }
6191 else
6192 {
6193 /* Not absolute_section.
6194 Need a 32-bit fixup (don't support 8bit
6195 non-absolute imms). Try to support other
6196 sizes ... */
f86103b7 6197 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 6198 int size = imm_size (n);
6199 int sign;
29b0f896 6200
40fb9820 6201 if (i.types[n].bitfield.imm32s
a7d61044 6202 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 6203 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 6204 sign = 1;
e205caa7
L		 6205 else
6206 sign = 0;
520dc8e8 6207
29b0f896
AM		 6208 p = frag_more (size);
6209 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 6210
2bbd9c25
JJ		 6211 /* This is tough to explain. We end up with this one if we
6212 * have operands that look like
6213 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6214 * obtain the absolute address of the GOT, and it is strongly
6215 * preferable from a performance point of view to avoid using
6216 * a runtime relocation for this. The actual sequence of
6217 * instructions often look something like:
6218 *
6219 * call .L66
6220 * .L66:
6221 * popl %ebx
6222 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6223 *
6224 * The call and pop essentially return the absolute address
6225 * of the label .L66 and store it in %ebx. The linker itself
6226 * will ultimately change the first operand of the addl so
6227 * that %ebx points to the GOT, but to keep things simple, the
6228 * .o file must have this operand set so that it generates not
6229 * the absolute address of .L66, but the absolute address of
6230 * itself. This allows the linker itself simply treat a GOTPC
6231 * relocation as asking for a pcrel offset to the GOT to be
6232 * added in, and the addend of the relocation is stored in the
6233 * operand field for the instruction itself.
6234 *
6235 * Our job here is to fix the operand so that it would add
6236 * the correct offset so that %ebx would point to itself. The
6237 * thing that is tricky is that .-.L66 will point to the
6238 * beginning of the instruction, so we need to further modify
6239 * the operand so that it will point to itself. There are
6240 * other cases where you have something like:
6241 *
6242 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6243 *
6244 * and here no correction would be required. Internally in
6245 * the assembler we treat operands of this form as not being
6246 * pcrel since the '.' is explicitly mentioned, and I wonder
6247 * whether it would simplify matters to do it this way. Who
6248 * knows. In earlier versions of the PIC patches, the
6249 * pcrel_adjust field was used to store the correction, but
6250 * since the expression is not pcrel, I felt it would be
6251 * confusing to do it this way. */
6252
d6ab8113 6253 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6254 || reloc_type == BFD_RELOC_X86_64_32S
6255 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 6256 && GOT_symbol
6257 && GOT_symbol == i.op[n].imms->X_add_symbol
6258 && (i.op[n].imms->X_op == O_symbol
6259 || (i.op[n].imms->X_op == O_add
6260 && ((symbol_get_value_expression
6261 (i.op[n].imms->X_op_symbol)->X_op)
6262 == O_subtract))))
6263 {
2bbd9c25
JJ		 6264 offsetT add;
6265
6266 if (insn_start_frag == frag_now)
6267 add = (p - frag_now->fr_literal) - insn_start_off;
6268 else
6269 {
6270 fragS *fr;
6271
6272 add = insn_start_frag->fr_fix - insn_start_off;
6273 for (fr = insn_start_frag->fr_next;
6274 fr && fr != frag_now; fr = fr->fr_next)
6275 add += fr->fr_fix;
6276 add += p - frag_now->fr_literal;
6277 }
6278
4fa24527 6279 if (!object_64bit)
d6ab8113 6280 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 6281 else if (size == 4)
d6ab8113 6282 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 6283 else if (size == 8)
6284 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 6285 i.op[n].imms->X_add_number += add;
29b0f896 6286 }
29b0f896
AM		 6287 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6288 i.op[n].imms, 0, reloc_type);
6289 }
6290 }
6291 }
252b5132
RH		 6292}
6293\f
d182319b
JB		 6294/* x86_cons_fix_new is called via the expression parsing code when a
6295 reloc is needed. We use this hook to get the correct .got reloc. */
6296static enum bfd_reloc_code_real got_reloc = NO_RELOC;
6297static int cons_sign = -1;
6298
6299void
e3bb37b5 6300x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 6301 expressionS *exp)
d182319b
JB		 6302{
6303 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
6304
6305 got_reloc = NO_RELOC;
6306
6307#ifdef TE_PE
6308 if (exp->X_op == O_secrel)
6309 {
6310 exp->X_op = O_symbol;
6311 r = BFD_RELOC_32_SECREL;
6312 }
6313#endif
6314
6315 fix_new_exp (frag, off, len, exp, 0, r);
6316}
6317
718ddfc0
JB		 6318#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6319# define lex_got(reloc, adjust, types) NULL
6320#else
f3c180ae
AM		 6321/* Parse operands of the form
6322 <symbol>@GOTOFF+<nnn>
6323 and similar .plt or .got references.
6324
6325 If we find one, set up the correct relocation in RELOC and copy the
6326 input string, minus the `@GOTOFF' into a malloc'd buffer for
6327 parsing by the calling routine. Return this buffer, and if ADJUST
6328 is non-null set it to the length of the string we removed from the
6329 input line. Otherwise return NULL. */
6330static char *
91d6fa6a 6331lex_got (enum bfd_reloc_code_real *rel,
64e74474 6332 int *adjust,
40fb9820 6333 i386_operand_type *types)
f3c180ae 6334{
7b81dfbb
AJ		 6335 /* Some of the relocations depend on the size of what field is to
6336 be relocated. But in our callers i386_immediate and i386_displacement
6337 we don't yet know the operand size (this will be set by insn
6338 matching). Hence we record the word32 relocation here,
6339 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 6340 static const struct {
6341 const char *str;
cff8d58a 6342 int len;
4fa24527 6343 const enum bfd_reloc_code_real rel[2];
40fb9820 6344 const i386_operand_type types64;
f3c180ae 6345 } gotrel[] = {
cff8d58a
L		 6346 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
6347 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 6348 OPERAND_TYPE_IMM64 },
cff8d58a
L		 6349 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
6350 BFD_RELOC_X86_64_PLT32 },
40fb9820 6351 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6352 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
6353 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 6354 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 6355 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
6356 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 6357 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 6358 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
6359 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 6360 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6361 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
6362 BFD_RELOC_X86_64_TLSGD },
40fb9820 6363 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6364 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
6365 _dummy_first_bfd_reloc_code_real },
40fb9820 6366 OPERAND_TYPE_NONE },
cff8d58a
L		 6367 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
6368 BFD_RELOC_X86_64_TLSLD },
40fb9820 6369 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6370 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
6371 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 6372 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6373 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
6374 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 6375 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 6376 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
6377 _dummy_first_bfd_reloc_code_real },
40fb9820 6378 OPERAND_TYPE_NONE },
cff8d58a
L		 6379 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
6380 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 6381 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 6382 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
6383 _dummy_first_bfd_reloc_code_real },
40fb9820 6384 OPERAND_TYPE_NONE },
cff8d58a
L		 6385 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
6386 _dummy_first_bfd_reloc_code_real },
40fb9820 6387 OPERAND_TYPE_NONE },
cff8d58a
L		 6388 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
6389 BFD_RELOC_X86_64_GOT32 },
40fb9820 6390 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 6391 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
6392 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 6393 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6394 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
6395 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 6396 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 6397 };
6398 char *cp;
6399 unsigned int j;
6400
718ddfc0
JB		 6401 if (!IS_ELF)
6402 return NULL;
6403
f3c180ae 6404 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 6405 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 6406 return NULL;
6407
47465058 6408 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 6409 {
cff8d58a 6410 int len = gotrel[j].len;
28f81592 6411 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 6412 {
4fa24527 6413 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 6414 {
28f81592
AM		 6415 int first, second;
6416 char *tmpbuf, *past_reloc;
f3c180ae 6417
91d6fa6a 6418 *rel = gotrel[j].rel[object_64bit];
28f81592
AM		 6419 if (adjust)
6420 *adjust = len;
f3c180ae 6421
3956db08
JB		 6422 if (types)
6423 {
6424 if (flag_code != CODE_64BIT)
40fb9820
L		 6425 {
6426 types->bitfield.imm32 = 1;
6427 types->bitfield.disp32 = 1;
6428 }
3956db08
JB		 6429 else
6430 *types = gotrel[j].types64;
6431 }
6432
f3c180ae
AM		 6433 if (GOT_symbol == NULL)
6434 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
6435
28f81592 6436 /* The length of the first part of our input line. */
f3c180ae 6437 first = cp - input_line_pointer;
28f81592
AM		 6438
6439 /* The second part goes from after the reloc token until
67c11a9b 6440 (and including) an end_of_line char or comma. */
28f81592 6441 past_reloc = cp + 1 + len;
67c11a9b
AM		 6442 cp = past_reloc;
6443 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
6444 ++cp;
6445 second = cp + 1 - past_reloc;
28f81592
AM		 6446
6447 /* Allocate and copy string. The trailing NUL shouldn't
6448 be necessary, but be safe. */
1e9cc1c2 6449 tmpbuf = (char *) xmalloc (first + second + 2);
f3c180ae 6450 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 6451 if (second != 0 && *past_reloc != ' ')
6452 /* Replace the relocation token with ' ', so that
6453 errors like foo@GOTOFF1 will be detected. */
6454 tmpbuf[first++] = ' ';
6455 memcpy (tmpbuf + first, past_reloc, second);
6456 tmpbuf[first + second] = '\0';
f3c180ae
AM		 6457 return tmpbuf;
6458 }
6459
4fa24527
JB		 6460 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6461 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 6462 return NULL;
6463 }
6464 }
6465
6466 /* Might be a symbol version string. Don't as_bad here. */
6467 return NULL;
6468}
6469
f3c180ae 6470void
e3bb37b5 6471x86_cons (expressionS *exp, int size)
f3c180ae 6472{
ee86248c
JB		 6473 intel_syntax = -intel_syntax;
6474
3c7b9c2c 6475 exp->X_md = 0;
4fa24527 6476 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 6477 {
6478 /* Handle @GOTOFF and the like in an expression. */
6479 char *save;
6480 char *gotfree_input_line;
6481 int adjust;
6482
6483 save = input_line_pointer;
3956db08 6484 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 6485 if (gotfree_input_line)
6486 input_line_pointer = gotfree_input_line;
6487
6488 expression (exp);
6489
6490 if (gotfree_input_line)
6491 {
6492 /* expression () has merrily parsed up to the end of line,
6493 or a comma - in the wrong buffer. Transfer how far
6494 input_line_pointer has moved to the right buffer. */
6495 input_line_pointer = (save
6496 + (input_line_pointer - gotfree_input_line)
6497 + adjust);
6498 free (gotfree_input_line);
3992d3b7
AM		 6499 if (exp->X_op == O_constant
6500 || exp->X_op == O_absent
6501 || exp->X_op == O_illegal
0398aac5 6502 || exp->X_op == O_register
3992d3b7
AM		 6503 || exp->X_op == O_big)
6504 {
6505 char c = *input_line_pointer;
6506 *input_line_pointer = 0;
6507 as_bad (_("missing or invalid expression `%s'"), save);
6508 *input_line_pointer = c;
6509 }
f3c180ae
AM		 6510 }
6511 }
6512 else
6513 expression (exp);
ee86248c
JB		 6514
6515 intel_syntax = -intel_syntax;
6516
6517 if (intel_syntax)
6518 i386_intel_simplify (exp);
f3c180ae
AM		 6519}
6520#endif
6521
9f32dd5b
L		 6522static void
6523signed_cons (int size)
6482c264 6524{
d182319b
JB		 6525 if (flag_code == CODE_64BIT)
6526 cons_sign = 1;
6527 cons (size);
6528 cons_sign = -1;
6482c264
NC		 6529}
6530
d182319b 6531#ifdef TE_PE
6482c264
NC		 6532static void
6533pe_directive_secrel (dummy)
6534 int dummy ATTRIBUTE_UNUSED;
6535{
6536 expressionS exp;
6537
6538 do
6539 {
6540 expression (&exp);
6541 if (exp.X_op == O_symbol)
6542 exp.X_op = O_secrel;
6543
6544 emit_expr (&exp, 4);
6545 }
6546 while (*input_line_pointer++ == ',');
6547
6548 input_line_pointer--;
6549 demand_empty_rest_of_line ();
6550}
6482c264
NC		 6551#endif
6552
252b5132 6553static int
70e41ade 6554i386_immediate (char *imm_start)
252b5132
RH		 6555{
6556 char *save_input_line_pointer;
f3c180ae 6557 char *gotfree_input_line;
252b5132 6558 segT exp_seg = 0;
47926f60 6559 expressionS *exp;
40fb9820
L		 6560 i386_operand_type types;
6561
0dfbf9d7 6562 operand_type_set (&types, ~0);
252b5132
RH		 6563
6564 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
6565 {
31b2323c
L		 6566 as_bad (_("at most %d immediate operands are allowed"),
6567 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 6568 return 0;
6569 }
6570
6571 exp = &im_expressions[i.imm_operands++];
520dc8e8 6572 i.op[this_operand].imms = exp;
252b5132
RH		 6573
6574 if (is_space_char (*imm_start))
6575 ++imm_start;
6576
6577 save_input_line_pointer = input_line_pointer;
6578 input_line_pointer = imm_start;
6579
3956db08 6580 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6581 if (gotfree_input_line)
6582 input_line_pointer = gotfree_input_line;
252b5132
RH		 6583
6584 exp_seg = expression (exp);
6585
83183c0c 6586 SKIP_WHITESPACE ();
252b5132 6587 if (*input_line_pointer)
f3c180ae 6588 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 6589
6590 input_line_pointer = save_input_line_pointer;
f3c180ae 6591 if (gotfree_input_line)
ee86248c
JB		 6592 {
6593 free (gotfree_input_line);
6594
6595 if (exp->X_op == O_constant || exp->X_op == O_register)
6596 exp->X_op = O_illegal;
6597 }
6598
6599 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
6600}
252b5132 6601
ee86248c
JB		 6602static int
6603i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6604 i386_operand_type types, const char *imm_start)
6605{
6606 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 6607 {
313c53d1
L		 6608 if (imm_start)
6609 as_bad (_("missing or invalid immediate expression `%s'"),
6610 imm_start);
3992d3b7 6611 return 0;
252b5132 6612 }
3e73aa7c 6613 else if (exp->X_op == O_constant)
252b5132 6614 {
47926f60 6615 /* Size it properly later. */
40fb9820 6616 i.types[this_operand].bitfield.imm64 = 1;
3e73aa7c 6617 /* If BFD64, sign extend val. */
4eed87de
AM		 6618 if (!use_rela_relocations
6619 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
6620 exp->X_add_number
6621 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 6622 }
4c63da97 6623#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 6624 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 6625 && exp_seg != absolute_section
47926f60 6626 && exp_seg != text_section
24eab124
AM		 6627 && exp_seg != data_section
6628 && exp_seg != bss_section
6629 && exp_seg != undefined_section
f86103b7 6630 && !bfd_is_com_section (exp_seg))
252b5132 6631 {
d0b47220 6632 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 6633 return 0;
6634 }
6635#endif
bb8f5920
L		 6636 else if (!intel_syntax && exp->X_op == O_register)
6637 {
313c53d1
L		 6638 if (imm_start)
6639 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 6640 return 0;
6641 }
252b5132
RH		 6642 else
6643 {
6644 /* This is an address. The size of the address will be
24eab124 6645 determined later, depending on destination register,
3e73aa7c 6646 suffix, or the default for the section. */
40fb9820
L		 6647 i.types[this_operand].bitfield.imm8 = 1;
6648 i.types[this_operand].bitfield.imm16 = 1;
6649 i.types[this_operand].bitfield.imm32 = 1;
6650 i.types[this_operand].bitfield.imm32s = 1;
6651 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 6652 i.types[this_operand] = operand_type_and (i.types[this_operand],
6653 types);
252b5132
RH		 6654 }
6655
6656 return 1;
6657}
6658
551c1ca1 6659static char *
e3bb37b5 6660i386_scale (char *scale)
252b5132 6661{
551c1ca1
AM		 6662 offsetT val;
6663 char *save = input_line_pointer;
252b5132 6664
551c1ca1
AM		 6665 input_line_pointer = scale;
6666 val = get_absolute_expression ();
6667
6668 switch (val)
252b5132 6669 {
551c1ca1 6670 case 1:
252b5132
RH		 6671 i.log2_scale_factor = 0;
6672 break;
551c1ca1 6673 case 2:
252b5132
RH		 6674 i.log2_scale_factor = 1;
6675 break;
551c1ca1 6676 case 4:
252b5132
RH		 6677 i.log2_scale_factor = 2;
6678 break;
551c1ca1 6679 case 8:
252b5132
RH		 6680 i.log2_scale_factor = 3;
6681 break;
6682 default:
a724f0f4
JB		 6683 {
6684 char sep = *input_line_pointer;
6685
6686 *input_line_pointer = '\0';
6687 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6688 scale);
6689 *input_line_pointer = sep;
6690 input_line_pointer = save;
6691 return NULL;
6692 }
252b5132 6693 }
29b0f896 6694 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 6695 {
6696 as_warn (_("scale factor of %d without an index register"),
24eab124 6697 1 << i.log2_scale_factor);
252b5132 6698 i.log2_scale_factor = 0;
252b5132 6699 }
551c1ca1
AM		 6700 scale = input_line_pointer;
6701 input_line_pointer = save;
6702 return scale;
252b5132
RH		 6703}
6704
252b5132 6705static int
e3bb37b5 6706i386_displacement (char *disp_start, char *disp_end)
252b5132 6707{
29b0f896 6708 expressionS *exp;
252b5132
RH		 6709 segT exp_seg = 0;
6710 char *save_input_line_pointer;
f3c180ae 6711 char *gotfree_input_line;
40fb9820
L		 6712 int override;
6713 i386_operand_type bigdisp, types = anydisp;
3992d3b7 6714 int ret;
252b5132 6715
31b2323c
L		 6716 if (i.disp_operands == MAX_MEMORY_OPERANDS)
6717 {
6718 as_bad (_("at most %d displacement operands are allowed"),
6719 MAX_MEMORY_OPERANDS);
6720 return 0;
6721 }
6722
0dfbf9d7 6723 operand_type_set (&bigdisp, 0);
40fb9820
L		 6724 if ((i.types[this_operand].bitfield.jumpabsolute)
6725 || (!current_templates->start->opcode_modifier.jump
6726 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 6727 {
40fb9820 6728 bigdisp.bitfield.disp32 = 1;
e05278af 6729 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 6730 if (flag_code == CODE_64BIT)
6731 {
6732 if (!override)
6733 {
6734 bigdisp.bitfield.disp32s = 1;
6735 bigdisp.bitfield.disp64 = 1;
6736 }
6737 }
6738 else if ((flag_code == CODE_16BIT) ^ override)
6739 {
6740 bigdisp.bitfield.disp32 = 0;
6741 bigdisp.bitfield.disp16 = 1;
6742 }
e05278af
JB		 6743 }
6744 else
6745 {
6746 /* For PC-relative branches, the width of the displacement
6747 is dependent upon data size, not address size. */
e05278af 6748 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 6749 if (flag_code == CODE_64BIT)
6750 {
6751 if (override || i.suffix == WORD_MNEM_SUFFIX)
6752 bigdisp.bitfield.disp16 = 1;
6753 else
6754 {
6755 bigdisp.bitfield.disp32 = 1;
6756 bigdisp.bitfield.disp32s = 1;
6757 }
6758 }
6759 else
e05278af
JB		 6760 {
6761 if (!override)
6762 override = (i.suffix == (flag_code != CODE_16BIT
6763 ? WORD_MNEM_SUFFIX
6764 : LONG_MNEM_SUFFIX));
40fb9820
L		 6765 bigdisp.bitfield.disp32 = 1;
6766 if ((flag_code == CODE_16BIT) ^ override)
6767 {
6768 bigdisp.bitfield.disp32 = 0;
6769 bigdisp.bitfield.disp16 = 1;
6770 }
e05278af 6771 }
e05278af 6772 }
c6fb90c8
L		 6773 i.types[this_operand] = operand_type_or (i.types[this_operand],
6774 bigdisp);
252b5132
RH		 6775
6776 exp = &disp_expressions[i.disp_operands];
520dc8e8 6777 i.op[this_operand].disps = exp;
252b5132
RH		 6778 i.disp_operands++;
6779 save_input_line_pointer = input_line_pointer;
6780 input_line_pointer = disp_start;
6781 END_STRING_AND_SAVE (disp_end);
6782
6783#ifndef GCC_ASM_O_HACK
6784#define GCC_ASM_O_HACK 0
6785#endif
6786#if GCC_ASM_O_HACK
6787 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 6788 if (i.types[this_operand].bitfield.baseIndex
24eab124 6789 && displacement_string_end[-1] == '+')
252b5132
RH		 6790 {
6791 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 6792 constraint within gcc asm statements.
6793 For instance:
6794
6795 #define _set_tssldt_desc(n,addr,limit,type) \
6796 __asm__ __volatile__ ( \
6797 "movw %w2,%0\n\t" \
6798 "movw %w1,2+%0\n\t" \
6799 "rorl $16,%1\n\t" \
6800 "movb %b1,4+%0\n\t" \
6801 "movb %4,5+%0\n\t" \
6802 "movb $0,6+%0\n\t" \
6803 "movb %h1,7+%0\n\t" \
6804 "rorl $16,%1" \
6805 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6806
6807 This works great except that the output assembler ends
6808 up looking a bit weird if it turns out that there is
6809 no offset. You end up producing code that looks like:
6810
6811 #APP
6812 movw $235,(%eax)
6813 movw %dx,2+(%eax)
6814 rorl $16,%edx
6815 movb %dl,4+(%eax)
6816 movb $137,5+(%eax)
6817 movb $0,6+(%eax)
6818 movb %dh,7+(%eax)
6819 rorl $16,%edx
6820 #NO_APP
6821
47926f60 6822 So here we provide the missing zero. */
24eab124
AM		 6823
6824 *displacement_string_end = '0';
252b5132
RH		 6825 }
6826#endif
3956db08 6827 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6828 if (gotfree_input_line)
6829 input_line_pointer = gotfree_input_line;
252b5132 6830
24eab124 6831 exp_seg = expression (exp);
252b5132 6832
636c26b0
AM		 6833 SKIP_WHITESPACE ();
6834 if (*input_line_pointer)
6835 as_bad (_("junk `%s' after expression"), input_line_pointer);
6836#if GCC_ASM_O_HACK
6837 RESTORE_END_STRING (disp_end + 1);
6838#endif
636c26b0 6839 input_line_pointer = save_input_line_pointer;
636c26b0 6840 if (gotfree_input_line)
ee86248c
JB		 6841 {
6842 free (gotfree_input_line);
6843
6844 if (exp->X_op == O_constant || exp->X_op == O_register)
6845 exp->X_op = O_illegal;
6846 }
6847
6848 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
6849
6850 RESTORE_END_STRING (disp_end);
6851
6852 return ret;
6853}
6854
6855static int
6856i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6857 i386_operand_type types, const char *disp_start)
6858{
6859 i386_operand_type bigdisp;
6860 int ret = 1;
636c26b0 6861
24eab124
AM		 6862 /* We do this to make sure that the section symbol is in
6863 the symbol table. We will ultimately change the relocation
47926f60 6864 to be relative to the beginning of the section. */
1ae12ab7 6865 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 6866 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
6867 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 6868 {
636c26b0 6869 if (exp->X_op != O_symbol)
3992d3b7 6870 goto inv_disp;
636c26b0 6871
e5cb08ac 6872 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 6873 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
6874 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 6875 exp->X_op = O_subtract;
6876 exp->X_op_symbol = GOT_symbol;
1ae12ab7 6877 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 6878 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 6879 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6880 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 6881 else
29b0f896 6882 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 6883 }
252b5132 6884
3992d3b7
AM		 6885 else if (exp->X_op == O_absent
6886 || exp->X_op == O_illegal
ee86248c 6887 || exp->X_op == O_big)
2daf4fd8 6888 {
3992d3b7
AM		 6889 inv_disp:
6890 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 6891 disp_start);
3992d3b7 6892 ret = 0;
2daf4fd8
AM		 6893 }
6894
0e1147d9
L		 6895 else if (flag_code == CODE_64BIT
6896 && !i.prefix[ADDR_PREFIX]
6897 && exp->X_op == O_constant)
6898 {
6899 /* Since displacement is signed extended to 64bit, don't allow
6900 disp32 and turn off disp32s if they are out of range. */
6901 i.types[this_operand].bitfield.disp32 = 0;
6902 if (!fits_in_signed_long (exp->X_add_number))
6903 {
6904 i.types[this_operand].bitfield.disp32s = 0;
6905 if (i.types[this_operand].bitfield.baseindex)
6906 {
6907 as_bad (_("0x%lx out range of signed 32bit displacement"),
6908 (long) exp->X_add_number);
6909 ret = 0;
6910 }
6911 }
6912 }
6913
4c63da97 6914#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 6915 else if (exp->X_op != O_constant
6916 && OUTPUT_FLAVOR == bfd_target_aout_flavour
6917 && exp_seg != absolute_section
6918 && exp_seg != text_section
6919 && exp_seg != data_section
6920 && exp_seg != bss_section
6921 && exp_seg != undefined_section
6922 && !bfd_is_com_section (exp_seg))
24eab124 6923 {
d0b47220 6924 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 6925 ret = 0;
24eab124 6926 }
252b5132 6927#endif
3956db08 6928
40fb9820
L		 6929 /* Check if this is a displacement only operand. */
6930 bigdisp = i.types[this_operand];
6931 bigdisp.bitfield.disp8 = 0;
6932 bigdisp.bitfield.disp16 = 0;
6933 bigdisp.bitfield.disp32 = 0;
6934 bigdisp.bitfield.disp32s = 0;
6935 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 6936 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 6937 i.types[this_operand] = operand_type_and (i.types[this_operand],
6938 types);
3956db08 6939
3992d3b7 6940 return ret;
252b5132
RH		 6941}
6942
eecb386c 6943/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 6944 Return 1 on success, 0 on a failure. */
6945
252b5132 6946static int
e3bb37b5 6947i386_index_check (const char *operand_string)
252b5132 6948{
3e73aa7c 6949 int ok;
fc0763e6 6950 const char *kind = "base/index";
24eab124 6951#if INFER_ADDR_PREFIX
eecb386c
AM		 6952 int fudged = 0;
6953
24eab124
AM		 6954 tryprefix:
6955#endif
3e73aa7c 6956 ok = 1;
fc0763e6
JB		 6957 if (current_templates->start->opcode_modifier.isstring
6958 && !current_templates->start->opcode_modifier.immext
6959 && (current_templates->end[-1].opcode_modifier.isstring
6960 || i.mem_operands))
6961 {
6962 /* Memory operands of string insns are special in that they only allow
6963 a single register (rDI, rSI, or rBX) as their memory address. */
6964 unsigned int expected;
6965
6966 kind = "string address";
6967
6968 if (current_templates->start->opcode_modifier.w)
6969 {
6970 i386_operand_type type = current_templates->end[-1].operand_types[0];
6971
6972 if (!type.bitfield.baseindex
6973 || ((!i.mem_operands != !intel_syntax)
6974 && current_templates->end[-1].operand_types[1]
6975 .bitfield.baseindex))
6976 type = current_templates->end[-1].operand_types[1];
6977 expected = type.bitfield.esseg ? 7 /* rDI */ : 6 /* rSI */;
6978 }
6979 else
6980 expected = 3 /* rBX */;
6981
6982 if (!i.base_reg || i.index_reg
6983 || operand_type_check (i.types[this_operand], disp))
6984 ok = -1;
6985 else if (!(flag_code == CODE_64BIT
6986 ? i.prefix[ADDR_PREFIX]
6987 ? i.base_reg->reg_type.bitfield.reg32
6988 : i.base_reg->reg_type.bitfield.reg64
6989 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
6990 ? i.base_reg->reg_type.bitfield.reg32
6991 : i.base_reg->reg_type.bitfield.reg16))
6992 ok = 0;
6993 else if (i.base_reg->reg_num != expected)
6994 ok = -1;
6995
6996 if (ok < 0)
6997 {
6998 unsigned int j;
6999
7000 for (j = 0; j < i386_regtab_size; ++j)
7001 if ((flag_code == CODE_64BIT
7002 ? i.prefix[ADDR_PREFIX]
7003 ? i386_regtab[j].reg_type.bitfield.reg32
7004 : i386_regtab[j].reg_type.bitfield.reg64
7005 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
7006 ? i386_regtab[j].reg_type.bitfield.reg32
7007 : i386_regtab[j].reg_type.bitfield.reg16)
7008 && i386_regtab[j].reg_num == expected)
7009 break;
9c2799c2 7010 gas_assert (j < i386_regtab_size);
fc0763e6
JB		 7011 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
7012 operand_string,
7013 intel_syntax ? '[' : '(',
7014 register_prefix,
7015 i386_regtab[j].reg_name,
7016 intel_syntax ? ']' : ')');
7017 ok = 1;
7018 }
7019 }
7020 else if (flag_code == CODE_64BIT)
64e74474 7021 {
64e74474 7022 if ((i.base_reg
40fb9820
L		 7023 && ((i.prefix[ADDR_PREFIX] == 0
7024 && !i.base_reg->reg_type.bitfield.reg64)
7025 || (i.prefix[ADDR_PREFIX]
7026 && !i.base_reg->reg_type.bitfield.reg32))
7027 && (i.index_reg
9a04903e
JB		 7028 || i.base_reg->reg_num !=
7029 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
64e74474 7030 || (i.index_reg
40fb9820
L		 7031 && (!i.index_reg->reg_type.bitfield.baseindex
7032 || (i.prefix[ADDR_PREFIX] == 0
db51cc60
L		 7033 && i.index_reg->reg_num != RegRiz
7034 && !i.index_reg->reg_type.bitfield.reg64
7035 )
40fb9820 7036 || (i.prefix[ADDR_PREFIX]
db51cc60 7037 && i.index_reg->reg_num != RegEiz
40fb9820 7038 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 7039 ok = 0;
3e73aa7c
JH		 7040 }
7041 else
7042 {
7043 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
7044 {
7045 /* 16bit checks. */
7046 if ((i.base_reg
40fb9820
L		 7047 && (!i.base_reg->reg_type.bitfield.reg16
7048 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 7049 || (i.index_reg
40fb9820
L		 7050 && (!i.index_reg->reg_type.bitfield.reg16
7051 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 7052 || !(i.base_reg
7053 && i.base_reg->reg_num < 6
7054 && i.index_reg->reg_num >= 6
7055 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 7056 ok = 0;
7057 }
7058 else
e5cb08ac 7059 {
3e73aa7c
JH		 7060 /* 32bit checks. */
7061 if ((i.base_reg
40fb9820 7062 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 7063 || (i.index_reg
db51cc60
L		 7064 && ((!i.index_reg->reg_type.bitfield.reg32
7065 && i.index_reg->reg_num != RegEiz)
40fb9820 7066 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 7067 ok = 0;
3e73aa7c
JH		 7068 }
7069 }
7070 if (!ok)
24eab124
AM		 7071 {
7072#if INFER_ADDR_PREFIX
fc0763e6 7073 if (!i.mem_operands && !i.prefix[ADDR_PREFIX])
24eab124
AM		 7074 {
7075 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
7076 i.prefixes += 1;
b23bac36
AM		 7077 /* Change the size of any displacement too. At most one of
7078 Disp16 or Disp32 is set.
7079 FIXME. There doesn't seem to be any real need for separate
7080 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 7081 Removing them would probably clean up the code quite a lot. */
4eed87de 7082 if (flag_code != CODE_64BIT
40fb9820
L		 7083 && (i.types[this_operand].bitfield.disp16
7084 || i.types[this_operand].bitfield.disp32))
7085 i.types[this_operand]
c6fb90c8 7086 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 7087 fudged = 1;
24eab124
AM		 7088 goto tryprefix;
7089 }
eecb386c 7090 if (fudged)
fc0763e6
JB		 7091 as_bad (_("`%s' is not a valid %s expression"),
7092 operand_string,
7093 kind);
eecb386c 7094 else
c388dee8 7095#endif
fc0763e6 7096 as_bad (_("`%s' is not a valid %s-bit %s expression"),
eecb386c 7097 operand_string,
fc0763e6
JB		 7098 flag_code_names[i.prefix[ADDR_PREFIX]
7099 ? flag_code == CODE_32BIT
7100 ? CODE_16BIT
7101 : CODE_32BIT
7102 : flag_code],
7103 kind);
24eab124 7104 }
20f0a1fc 7105 return ok;
24eab124 7106}
252b5132 7107
fc0763e6 7108/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 7109 on error. */
252b5132 7110
252b5132 7111static int
a7619375 7112i386_att_operand (char *operand_string)
252b5132 7113{
af6bdddf
AM		 7114 const reg_entry *r;
7115 char *end_op;
24eab124 7116 char *op_string = operand_string;
252b5132 7117
24eab124 7118 if (is_space_char (*op_string))
252b5132
RH		 7119 ++op_string;
7120
24eab124 7121 /* We check for an absolute prefix (differentiating,
47926f60 7122 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 7123 if (*op_string == ABSOLUTE_PREFIX)
7124 {
7125 ++op_string;
7126 if (is_space_char (*op_string))
7127 ++op_string;
40fb9820 7128 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 7129 }
252b5132 7130
47926f60 7131 /* Check if operand is a register. */
4d1bb795 7132 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 7133 {
40fb9820
L		 7134 i386_operand_type temp;
7135
24eab124
AM		 7136 /* Check for a segment override by searching for ':' after a
7137 segment register. */
7138 op_string = end_op;
7139 if (is_space_char (*op_string))
7140 ++op_string;
40fb9820
L		 7141 if (*op_string == ':'
7142 && (r->reg_type.bitfield.sreg2
7143 || r->reg_type.bitfield.sreg3))
24eab124
AM		 7144 {
7145 switch (r->reg_num)
7146 {
7147 case 0:
7148 i.seg[i.mem_operands] = &es;
7149 break;
7150 case 1:
7151 i.seg[i.mem_operands] = &cs;
7152 break;
7153 case 2:
7154 i.seg[i.mem_operands] = &ss;
7155 break;
7156 case 3:
7157 i.seg[i.mem_operands] = &ds;
7158 break;
7159 case 4:
7160 i.seg[i.mem_operands] = &fs;
7161 break;
7162 case 5:
7163 i.seg[i.mem_operands] = &gs;
7164 break;
7165 }
252b5132 7166
24eab124 7167 /* Skip the ':' and whitespace. */
252b5132
RH		 7168 ++op_string;
7169 if (is_space_char (*op_string))
24eab124 7170 ++op_string;
252b5132 7171
24eab124
AM		 7172 if (!is_digit_char (*op_string)
7173 && !is_identifier_char (*op_string)
7174 && *op_string != '('
7175 && *op_string != ABSOLUTE_PREFIX)
7176 {
7177 as_bad (_("bad memory operand `%s'"), op_string);
7178 return 0;
7179 }
47926f60 7180 /* Handle case of %es:*foo. */
24eab124
AM		 7181 if (*op_string == ABSOLUTE_PREFIX)
7182 {
7183 ++op_string;
7184 if (is_space_char (*op_string))
7185 ++op_string;
40fb9820 7186 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 7187 }
7188 goto do_memory_reference;
7189 }
7190 if (*op_string)
7191 {
d0b47220 7192 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 7193 return 0;
7194 }
40fb9820
L		 7195 temp = r->reg_type;
7196 temp.bitfield.baseindex = 0;
c6fb90c8
L		 7197 i.types[this_operand] = operand_type_or (i.types[this_operand],
7198 temp);
7d5e4556 7199 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 7200 i.op[this_operand].regs = r;
24eab124
AM		 7201 i.reg_operands++;
7202 }
af6bdddf
AM		 7203 else if (*op_string == REGISTER_PREFIX)
7204 {
7205 as_bad (_("bad register name `%s'"), op_string);
7206 return 0;
7207 }
24eab124 7208 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 7209 {
24eab124 7210 ++op_string;
40fb9820 7211 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 7212 {
d0b47220 7213 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 7214 return 0;
7215 }
7216 if (!i386_immediate (op_string))
7217 return 0;
7218 }
7219 else if (is_digit_char (*op_string)
7220 || is_identifier_char (*op_string)
e5cb08ac 7221 || *op_string == '(')
24eab124 7222 {
47926f60 7223 /* This is a memory reference of some sort. */
af6bdddf 7224 char *base_string;
252b5132 7225
47926f60 7226 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 7227 char *displacement_string_start;
7228 char *displacement_string_end;
252b5132 7229
24eab124 7230 do_memory_reference:
24eab124 7231 if ((i.mem_operands == 1
40fb9820 7232 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 7233 || i.mem_operands == 2)
7234 {
7235 as_bad (_("too many memory references for `%s'"),
7236 current_templates->start->name);
7237 return 0;
7238 }
252b5132 7239
24eab124
AM		 7240 /* Check for base index form. We detect the base index form by
7241 looking for an ')' at the end of the operand, searching
7242 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7243 after the '('. */
af6bdddf 7244 base_string = op_string + strlen (op_string);
c3332e24 7245
af6bdddf
AM		 7246 --base_string;
7247 if (is_space_char (*base_string))
7248 --base_string;
252b5132 7249
47926f60 7250 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 7251 displacement_string_start = op_string;
7252 displacement_string_end = base_string + 1;
252b5132 7253
24eab124
AM		 7254 if (*base_string == ')')
7255 {
af6bdddf 7256 char *temp_string;
24eab124
AM		 7257 unsigned int parens_balanced = 1;
7258 /* We've already checked that the number of left & right ()'s are
47926f60 7259 equal, so this loop will not be infinite. */
24eab124
AM		 7260 do
7261 {
7262 base_string--;
7263 if (*base_string == ')')
7264 parens_balanced++;
7265 if (*base_string == '(')
7266 parens_balanced--;
7267 }
7268 while (parens_balanced);
c3332e24 7269
af6bdddf 7270 temp_string = base_string;
c3332e24 7271
24eab124 7272 /* Skip past '(' and whitespace. */
252b5132
RH		 7273 ++base_string;
7274 if (is_space_char (*base_string))
24eab124 7275 ++base_string;
252b5132 7276
af6bdddf 7277 if (*base_string == ','
4eed87de
AM		 7278 || ((i.base_reg = parse_register (base_string, &end_op))
7279 != NULL))
252b5132 7280 {
af6bdddf 7281 displacement_string_end = temp_string;
252b5132 7282
40fb9820 7283 i.types[this_operand].bitfield.baseindex = 1;
252b5132 7284
af6bdddf 7285 if (i.base_reg)
24eab124 7286 {
24eab124
AM		 7287 base_string = end_op;
7288 if (is_space_char (*base_string))
7289 ++base_string;
af6bdddf
AM		 7290 }
7291
7292 /* There may be an index reg or scale factor here. */
7293 if (*base_string == ',')
7294 {
7295 ++base_string;
7296 if (is_space_char (*base_string))
7297 ++base_string;
7298
4eed87de
AM		 7299 if ((i.index_reg = parse_register (base_string, &end_op))
7300 != NULL)
24eab124 7301 {
af6bdddf 7302 base_string = end_op;
24eab124
AM		 7303 if (is_space_char (*base_string))
7304 ++base_string;
af6bdddf
AM		 7305 if (*base_string == ',')
7306 {
7307 ++base_string;
7308 if (is_space_char (*base_string))
7309 ++base_string;
7310 }
e5cb08ac 7311 else if (*base_string != ')')
af6bdddf 7312 {
4eed87de
AM		 7313 as_bad (_("expecting `,' or `)' "
7314 "after index register in `%s'"),
af6bdddf
AM		 7315 operand_string);
7316 return 0;
7317 }
24eab124 7318 }
af6bdddf 7319 else if (*base_string == REGISTER_PREFIX)
24eab124 7320 {
af6bdddf 7321 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 7322 return 0;
7323 }
252b5132 7324
47926f60 7325 /* Check for scale factor. */
551c1ca1 7326 if (*base_string != ')')
af6bdddf 7327 {
551c1ca1
AM		 7328 char *end_scale = i386_scale (base_string);
7329
7330 if (!end_scale)
af6bdddf 7331 return 0;
24eab124 7332
551c1ca1 7333 base_string = end_scale;
af6bdddf
AM		 7334 if (is_space_char (*base_string))
7335 ++base_string;
7336 if (*base_string != ')')
7337 {
4eed87de
AM		 7338 as_bad (_("expecting `)' "
7339 "after scale factor in `%s'"),
af6bdddf
AM		 7340 operand_string);
7341 return 0;
7342 }
7343 }
7344 else if (!i.index_reg)
24eab124 7345 {
4eed87de
AM		 7346 as_bad (_("expecting index register or scale factor "
7347 "after `,'; got '%c'"),
af6bdddf 7348 *base_string);
24eab124
AM		 7349 return 0;
7350 }
7351 }
af6bdddf 7352 else if (*base_string != ')')
24eab124 7353 {
4eed87de
AM		 7354 as_bad (_("expecting `,' or `)' "
7355 "after base register in `%s'"),
af6bdddf 7356 operand_string);
24eab124
AM		 7357 return 0;
7358 }
c3332e24 7359 }
af6bdddf 7360 else if (*base_string == REGISTER_PREFIX)
c3332e24 7361 {
af6bdddf 7362 as_bad (_("bad register name `%s'"), base_string);
24eab124 7363 return 0;
c3332e24 7364 }
24eab124
AM		 7365 }
7366
7367 /* If there's an expression beginning the operand, parse it,
7368 assuming displacement_string_start and
7369 displacement_string_end are meaningful. */
7370 if (displacement_string_start != displacement_string_end)
7371 {
7372 if (!i386_displacement (displacement_string_start,
7373 displacement_string_end))
7374 return 0;
7375 }
7376
7377 /* Special case for (%dx) while doing input/output op. */
7378 if (i.base_reg
0dfbf9d7
L		 7379 && operand_type_equal (&i.base_reg->reg_type,
7380 &reg16_inoutportreg)
24eab124
AM		 7381 && i.index_reg == 0
7382 && i.log2_scale_factor == 0
7383 && i.seg[i.mem_operands] == 0
40fb9820 7384 && !operand_type_check (i.types[this_operand], disp))
24eab124 7385 {
65da13b5 7386 i.types[this_operand] = inoutportreg;
24eab124
AM		 7387 return 1;
7388 }
7389
eecb386c
AM		 7390 if (i386_index_check (operand_string) == 0)
7391 return 0;
5c07affc 7392 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 7393 i.mem_operands++;
7394 }
7395 else
ce8a8b2f
AM		 7396 {
7397 /* It's not a memory operand; argh! */
24eab124
AM		 7398 as_bad (_("invalid char %s beginning operand %d `%s'"),
7399 output_invalid (*op_string),
7400 this_operand + 1,
7401 op_string);
7402 return 0;
7403 }
47926f60 7404 return 1; /* Normal return. */
252b5132
RH		 7405}
7406\f
ee7fcc42
AM		 7407/* md_estimate_size_before_relax()
7408
7409 Called just before relax() for rs_machine_dependent frags. The x86
7410 assembler uses these frags to handle variable size jump
7411 instructions.
7412
7413 Any symbol that is now undefined will not become defined.
7414 Return the correct fr_subtype in the frag.
7415 Return the initial "guess for variable size of frag" to caller.
7416 The guess is actually the growth beyond the fixed part. Whatever
7417 we do to grow the fixed or variable part contributes to our
7418 returned value. */
7419
252b5132
RH		 7420int
7421md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 7422 fragS *fragP;
7423 segT segment;
252b5132 7424{
252b5132 7425 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 7426 check for un-relaxable symbols. On an ELF system, we can't relax
7427 an externally visible symbol, because it may be overridden by a
7428 shared library. */
7429 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 7430#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7431 || (IS_ELF
31312f95 7432 && (S_IS_EXTERNAL (fragP->fr_symbol)
915bcca5
L		 7433 || S_IS_WEAK (fragP->fr_symbol)
7434 || ((symbol_get_bfdsym (fragP->fr_symbol)->flags
7435 & BSF_GNU_INDIRECT_FUNCTION))))
fbeb56a4
DK		 7436#endif
7437#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 7438 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 7439 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 7440#endif
7441 )
252b5132 7442 {
b98ef147
AM		 7443 /* Symbol is undefined in this segment, or we need to keep a
7444 reloc so that weak symbols can be overridden. */
7445 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 7446 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 7447 unsigned char *opcode;
7448 int old_fr_fix;
f6af82bd 7449
ee7fcc42 7450 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 7451 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 7452 else if (size == 2)
f6af82bd
AM		 7453 reloc_type = BFD_RELOC_16_PCREL;
7454 else
7455 reloc_type = BFD_RELOC_32_PCREL;
252b5132 7456
ee7fcc42
AM		 7457 old_fr_fix = fragP->fr_fix;
7458 opcode = (unsigned char *) fragP->fr_opcode;
7459
fddf5b5b 7460 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 7461 {
fddf5b5b
AM		 7462 case UNCOND_JUMP:
7463 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 7464 opcode[0] = 0xe9;
252b5132 7465 fragP->fr_fix += size;
062cd5e7
AS		 7466 fix_new (fragP, old_fr_fix, size,
7467 fragP->fr_symbol,
7468 fragP->fr_offset, 1,
7469 reloc_type);
252b5132
RH		 7470 break;
7471
fddf5b5b 7472 case COND_JUMP86:
412167cb
AM		 7473 if (size == 2
7474 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 7475 {
7476 /* Negate the condition, and branch past an
7477 unconditional jump. */
7478 opcode[0] ^= 1;
7479 opcode[1] = 3;
7480 /* Insert an unconditional jump. */
7481 opcode[2] = 0xe9;
7482 /* We added two extra opcode bytes, and have a two byte
7483 offset. */
7484 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 7485 fix_new (fragP, old_fr_fix + 2, 2,
7486 fragP->fr_symbol,
7487 fragP->fr_offset, 1,
7488 reloc_type);
fddf5b5b
AM		 7489 break;
7490 }
7491 /* Fall through. */
7492
7493 case COND_JUMP:
412167cb
AM		 7494 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
7495 {
3e02c1cc
AM		 7496 fixS *fixP;
7497
412167cb 7498 fragP->fr_fix += 1;
3e02c1cc
AM		 7499 fixP = fix_new (fragP, old_fr_fix, 1,
7500 fragP->fr_symbol,
7501 fragP->fr_offset, 1,
7502 BFD_RELOC_8_PCREL);
7503 fixP->fx_signed = 1;
412167cb
AM		 7504 break;
7505 }
93c2a809 7506
24eab124 7507 /* This changes the byte-displacement jump 0x7N
fddf5b5b 7508 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 7509 opcode[1] = opcode[0] + 0x10;
f6af82bd 7510 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 7511 /* We've added an opcode byte. */
7512 fragP->fr_fix += 1 + size;
062cd5e7
AS		 7513 fix_new (fragP, old_fr_fix + 1, size,
7514 fragP->fr_symbol,
7515 fragP->fr_offset, 1,
7516 reloc_type);
252b5132 7517 break;
fddf5b5b
AM		 7518
7519 default:
7520 BAD_CASE (fragP->fr_subtype);
7521 break;
252b5132
RH		 7522 }
7523 frag_wane (fragP);
ee7fcc42 7524 return fragP->fr_fix - old_fr_fix;
252b5132 7525 }
93c2a809 7526
93c2a809
AM		 7527 /* Guess size depending on current relax state. Initially the relax
7528 state will correspond to a short jump and we return 1, because
7529 the variable part of the frag (the branch offset) is one byte
7530 long. However, we can relax a section more than once and in that
7531 case we must either set fr_subtype back to the unrelaxed state,
7532 or return the value for the appropriate branch. */
7533 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 7534}
7535
47926f60
KH		 7536/* Called after relax() is finished.
7537
7538 In: Address of frag.
7539 fr_type == rs_machine_dependent.
7540 fr_subtype is what the address relaxed to.
7541
7542 Out: Any fixSs and constants are set up.
7543 Caller will turn frag into a ".space 0". */
7544
252b5132
RH		 7545void
7546md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 7547 bfd *abfd ATTRIBUTE_UNUSED;
7548 segT sec ATTRIBUTE_UNUSED;
29b0f896 7549 fragS *fragP;
252b5132 7550{
29b0f896 7551 unsigned char *opcode;
252b5132 7552 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 7553 offsetT target_address;
7554 offsetT opcode_address;
252b5132 7555 unsigned int extension = 0;
847f7ad4 7556 offsetT displacement_from_opcode_start;
252b5132
RH		 7557
7558 opcode = (unsigned char *) fragP->fr_opcode;
7559
47926f60 7560 /* Address we want to reach in file space. */
252b5132 7561 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 7562
47926f60 7563 /* Address opcode resides at in file space. */
252b5132
RH		 7564 opcode_address = fragP->fr_address + fragP->fr_fix;
7565
47926f60 7566 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 7567 displacement_from_opcode_start = target_address - opcode_address;
7568
fddf5b5b 7569 if ((fragP->fr_subtype & BIG) == 0)
252b5132 7570 {
47926f60
KH		 7571 /* Don't have to change opcode. */
7572 extension = 1; /* 1 opcode + 1 displacement */
252b5132 7573 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 7574 }
7575 else
7576 {
7577 if (no_cond_jump_promotion
7578 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 7579 as_warn_where (fragP->fr_file, fragP->fr_line,
7580 _("long jump required"));
252b5132 7581
fddf5b5b
AM		 7582 switch (fragP->fr_subtype)
7583 {
7584 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
7585 extension = 4; /* 1 opcode + 4 displacement */
7586 opcode[0] = 0xe9;
7587 where_to_put_displacement = &opcode[1];
7588 break;
252b5132 7589
fddf5b5b
AM		 7590 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
7591 extension = 2; /* 1 opcode + 2 displacement */
7592 opcode[0] = 0xe9;
7593 where_to_put_displacement = &opcode[1];
7594 break;
252b5132 7595
fddf5b5b
AM		 7596 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
7597 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
7598 extension = 5; /* 2 opcode + 4 displacement */
7599 opcode[1] = opcode[0] + 0x10;
7600 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7601 where_to_put_displacement = &opcode[2];
7602 break;
252b5132 7603
fddf5b5b
AM		 7604 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
7605 extension = 3; /* 2 opcode + 2 displacement */
7606 opcode[1] = opcode[0] + 0x10;
7607 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7608 where_to_put_displacement = &opcode[2];
7609 break;
252b5132 7610
fddf5b5b
AM		 7611 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
7612 extension = 4;
7613 opcode[0] ^= 1;
7614 opcode[1] = 3;
7615 opcode[2] = 0xe9;
7616 where_to_put_displacement = &opcode[3];
7617 break;
7618
7619 default:
7620 BAD_CASE (fragP->fr_subtype);
7621 break;
7622 }
252b5132 7623 }
fddf5b5b 7624
7b81dfbb
AJ		 7625 /* If size if less then four we are sure that the operand fits,
7626 but if it's 4, then it could be that the displacement is larger
7627 then -/+ 2GB. */
7628 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
7629 && object_64bit
7630 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 7631 + ((addressT) 1 << 31))
7632 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 7633 {
7634 as_bad_where (fragP->fr_file, fragP->fr_line,
7635 _("jump target out of range"));
7636 /* Make us emit 0. */
7637 displacement_from_opcode_start = extension;
7638 }
47926f60 7639 /* Now put displacement after opcode. */
252b5132
RH		 7640 md_number_to_chars ((char *) where_to_put_displacement,
7641 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 7642 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 7643 fragP->fr_fix += extension;
7644}
7645\f
252b5132
RH		 7646/* Apply a fixup (fixS) to segment data, once it has been determined
7647 by our caller that we have all the info we need to fix it up.
7648
7649 On the 386, immediates, displacements, and data pointers are all in
7650 the same (little-endian) format, so we don't need to care about which
7651 we are handling. */
7652
94f592af 7653void
55cf6793 7654md_apply_fix (fixP, valP, seg)
47926f60
KH		 7655 /* The fix we're to put in. */
7656 fixS *fixP;
47926f60 7657 /* Pointer to the value of the bits. */
c6682705 7658 valueT *valP;
47926f60
KH		 7659 /* Segment fix is from. */
7660 segT seg ATTRIBUTE_UNUSED;
252b5132 7661{
94f592af 7662 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 7663 valueT value = *valP;
252b5132 7664
f86103b7 7665#if !defined (TE_Mach)
93382f6d
AM		 7666 if (fixP->fx_pcrel)
7667 {
7668 switch (fixP->fx_r_type)
7669 {
5865bb77
ILT		 7670 default:
7671 break;
7672
d6ab8113
JB		 7673 case BFD_RELOC_64:
7674 fixP->fx_r_type = BFD_RELOC_64_PCREL;
7675 break;
93382f6d 7676 case BFD_RELOC_32:
ae8887b5 7677 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 7678 fixP->fx_r_type = BFD_RELOC_32_PCREL;
7679 break;
7680 case BFD_RELOC_16:
7681 fixP->fx_r_type = BFD_RELOC_16_PCREL;
7682 break;
7683 case BFD_RELOC_8:
7684 fixP->fx_r_type = BFD_RELOC_8_PCREL;
7685 break;
7686 }
7687 }
252b5132 7688
a161fe53 7689 if (fixP->fx_addsy != NULL
31312f95 7690 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 7691 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 7692 || fixP->fx_r_type == BFD_RELOC_16_PCREL
7693 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
7694 && !use_rela_relocations)
252b5132 7695 {
31312f95
AM		 7696 /* This is a hack. There should be a better way to handle this.
7697 This covers for the fact that bfd_install_relocation will
7698 subtract the current location (for partial_inplace, PC relative
7699 relocations); see more below. */
252b5132 7700#ifndef OBJ_AOUT
718ddfc0 7701 if (IS_ELF
252b5132
RH		 7702#ifdef TE_PE
7703 || OUTPUT_FLAVOR == bfd_target_coff_flavour
7704#endif
7705 )
7706 value += fixP->fx_where + fixP->fx_frag->fr_address;
7707#endif
7708#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7709 if (IS_ELF)
252b5132 7710 {
6539b54b 7711 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 7712
6539b54b 7713 if ((sym_seg == seg
2f66722d 7714 || (symbol_section_p (fixP->fx_addsy)
6539b54b 7715 && sym_seg != absolute_section))
af65af87 7716 && !generic_force_reloc (fixP))
2f66722d
AM		 7717 {
7718 /* Yes, we add the values in twice. This is because
6539b54b
AM		 7719 bfd_install_relocation subtracts them out again. I think
7720 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 7721 it. FIXME. */
7722 value += fixP->fx_where + fixP->fx_frag->fr_address;
7723 }
252b5132
RH		 7724 }
7725#endif
7726#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 7727 /* For some reason, the PE format does not store a
7728 section address offset for a PC relative symbol. */
7729 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 7730 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 7731 value += md_pcrel_from (fixP);
7732#endif
7733 }
fbeb56a4
DK		 7734#if defined (OBJ_COFF) && defined (TE_PE)
7735 if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
7736 {
7737 value -= S_GET_VALUE (fixP->fx_addsy);
7738 }
7739#endif
252b5132
RH		 7740
7741 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 7742 and we must not disappoint it. */
252b5132 7743#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7744 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 7745 switch (fixP->fx_r_type)
7746 {
7747 case BFD_RELOC_386_PLT32:
3e73aa7c 7748 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 7749 /* Make the jump instruction point to the address of the operand. At
7750 runtime we merely add the offset to the actual PLT entry. */
7751 value = -4;
7752 break;
31312f95 7753
13ae64f3
JJ		 7754 case BFD_RELOC_386_TLS_GD:
7755 case BFD_RELOC_386_TLS_LDM:
13ae64f3 7756 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 7757 case BFD_RELOC_386_TLS_IE:
7758 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 7759 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 7760 case BFD_RELOC_X86_64_TLSGD:
7761 case BFD_RELOC_X86_64_TLSLD:
7762 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 7763 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 7764 value = 0; /* Fully resolved at runtime. No addend. */
7765 /* Fallthrough */
7766 case BFD_RELOC_386_TLS_LE:
7767 case BFD_RELOC_386_TLS_LDO_32:
7768 case BFD_RELOC_386_TLS_LE_32:
7769 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 7770 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 7771 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 7772 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 7773 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7774 break;
7775
67a4f2b7
AO		 7776 case BFD_RELOC_386_TLS_DESC_CALL:
7777 case BFD_RELOC_X86_64_TLSDESC_CALL:
7778 value = 0; /* Fully resolved at runtime. No addend. */
7779 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7780 fixP->fx_done = 0;
7781 return;
7782
00f7efb6
JJ		 7783 case BFD_RELOC_386_GOT32:
7784 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 7785 value = 0; /* Fully resolved at runtime. No addend. */
7786 break;
47926f60
KH		 7787
7788 case BFD_RELOC_VTABLE_INHERIT:
7789 case BFD_RELOC_VTABLE_ENTRY:
7790 fixP->fx_done = 0;
94f592af 7791 return;
47926f60
KH		 7792
7793 default:
7794 break;
7795 }
7796#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 7797 *valP = value;
f86103b7 7798#endif /* !defined (TE_Mach) */
3e73aa7c 7799
3e73aa7c 7800 /* Are we finished with this relocation now? */
c6682705 7801 if (fixP->fx_addsy == NULL)
3e73aa7c 7802 fixP->fx_done = 1;
fbeb56a4
DK		 7803#if defined (OBJ_COFF) && defined (TE_PE)
7804 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
7805 {
7806 fixP->fx_done = 0;
7807 /* Remember value for tc_gen_reloc. */
7808 fixP->fx_addnumber = value;
7809 /* Clear out the frag for now. */
7810 value = 0;
7811 }
7812#endif
3e73aa7c
JH		 7813 else if (use_rela_relocations)
7814 {
7815 fixP->fx_no_overflow = 1;
062cd5e7
AS		 7816 /* Remember value for tc_gen_reloc. */
7817 fixP->fx_addnumber = value;
3e73aa7c
JH		 7818 value = 0;
7819 }
f86103b7 7820
94f592af 7821 md_number_to_chars (p, value, fixP->fx_size);
252b5132 7822}
252b5132 7823\f
252b5132 7824char *
499ac353 7825md_atof (int type, char *litP, int *sizeP)
252b5132 7826{
499ac353
NC		 7827 /* This outputs the LITTLENUMs in REVERSE order;
7828 in accord with the bigendian 386. */
7829 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 7830}
7831\f
2d545b82 7832static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 7833
252b5132 7834static char *
e3bb37b5 7835output_invalid (int c)
252b5132 7836{
3882b010 7837 if (ISPRINT (c))
f9f21a03
L		 7838 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
7839 "'%c'", c);
252b5132 7840 else
f9f21a03 7841 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 7842 "(0x%x)", (unsigned char) c);
252b5132
RH		 7843 return output_invalid_buf;
7844}
7845
af6bdddf 7846/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 7847
7848static const reg_entry *
4d1bb795 7849parse_real_register (char *reg_string, char **end_op)
252b5132 7850{
af6bdddf
AM		 7851 char *s = reg_string;
7852 char *p;
252b5132
RH		 7853 char reg_name_given[MAX_REG_NAME_SIZE + 1];
7854 const reg_entry *r;
7855
7856 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7857 if (*s == REGISTER_PREFIX)
7858 ++s;
7859
7860 if (is_space_char (*s))
7861 ++s;
7862
7863 p = reg_name_given;
af6bdddf 7864 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 7865 {
7866 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 7867 return (const reg_entry *) NULL;
7868 s++;
252b5132
RH		 7869 }
7870
6588847e
DN		 7871 /* For naked regs, make sure that we are not dealing with an identifier.
7872 This prevents confusing an identifier like `eax_var' with register
7873 `eax'. */
7874 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
7875 return (const reg_entry *) NULL;
7876
af6bdddf 7877 *end_op = s;
252b5132
RH		 7878
7879 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
7880
5f47d35b 7881 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 7882 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 7883 {
5f47d35b
AM		 7884 if (is_space_char (*s))
7885 ++s;
7886 if (*s == '(')
7887 {
af6bdddf 7888 ++s;
5f47d35b
AM		 7889 if (is_space_char (*s))
7890 ++s;
7891 if (*s >= '0' && *s <= '7')
7892 {
db557034 7893 int fpr = *s - '0';
af6bdddf 7894 ++s;
5f47d35b
AM		 7895 if (is_space_char (*s))
7896 ++s;
7897 if (*s == ')')
7898 {
7899 *end_op = s + 1;
1e9cc1c2 7900 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 7901 know (r);
7902 return r + fpr;
5f47d35b 7903 }
5f47d35b 7904 }
47926f60 7905 /* We have "%st(" then garbage. */
5f47d35b
AM		 7906 return (const reg_entry *) NULL;
7907 }
7908 }
7909
a60de03c
JB		 7910 if (r == NULL || allow_pseudo_reg)
7911 return r;
7912
0dfbf9d7 7913 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 7914 return (const reg_entry *) NULL;
7915
192dc9c6
JB		 7916 if ((r->reg_type.bitfield.reg32
7917 || r->reg_type.bitfield.sreg3
7918 || r->reg_type.bitfield.control
7919 || r->reg_type.bitfield.debug
7920 || r->reg_type.bitfield.test)
7921 && !cpu_arch_flags.bitfield.cpui386)
7922 return (const reg_entry *) NULL;
7923
309d3373
JB		 7924 if (r->reg_type.bitfield.floatreg
7925 && !cpu_arch_flags.bitfield.cpu8087
7926 && !cpu_arch_flags.bitfield.cpu287
7927 && !cpu_arch_flags.bitfield.cpu387)
7928 return (const reg_entry *) NULL;
7929
192dc9c6
JB		 7930 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
7931 return (const reg_entry *) NULL;
7932
7933 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
7934 return (const reg_entry *) NULL;
7935
40f12533
L		 7936 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
7937 return (const reg_entry *) NULL;
7938
db51cc60 7939 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 7940 if (!allow_index_reg
db51cc60
L		 7941 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
7942 return (const reg_entry *) NULL;
7943
a60de03c
JB		 7944 if (((r->reg_flags & (RegRex64 | RegRex))
7945 || r->reg_type.bitfield.reg64)
40fb9820 7946 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 7947 || !operand_type_equal (&r->reg_type, &control))
1ae00879 7948 && flag_code != CODE_64BIT)
20f0a1fc 7949 return (const reg_entry *) NULL;
1ae00879 7950
b7240065
JB		 7951 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
7952 return (const reg_entry *) NULL;
7953
252b5132
RH		 7954 return r;
7955}
4d1bb795
JB		 7956
7957/* REG_STRING starts *before* REGISTER_PREFIX. */
7958
7959static const reg_entry *
7960parse_register (char *reg_string, char **end_op)
7961{
7962 const reg_entry *r;
7963
7964 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
7965 r = parse_real_register (reg_string, end_op);
7966 else
7967 r = NULL;
7968 if (!r)
7969 {
7970 char *save = input_line_pointer;
7971 char c;
7972 symbolS *symbolP;
7973
7974 input_line_pointer = reg_string;
7975 c = get_symbol_end ();
7976 symbolP = symbol_find (reg_string);
7977 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
7978 {
7979 const expressionS *e = symbol_get_value_expression (symbolP);
7980
0398aac5 7981 know (e->X_op == O_register);
4eed87de 7982 know (e->X_add_number >= 0
c3fe08fa 7983 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 7984 r = i386_regtab + e->X_add_number;
7985 *end_op = input_line_pointer;
7986 }
7987 *input_line_pointer = c;
7988 input_line_pointer = save;
7989 }
7990 return r;
7991}
7992
7993int
7994i386_parse_name (char *name, expressionS *e, char *nextcharP)
7995{
7996 const reg_entry *r;
7997 char *end = input_line_pointer;
7998
7999 *end = *nextcharP;
8000 r = parse_register (name, &input_line_pointer);
8001 if (r && end <= input_line_pointer)
8002 {
8003 *nextcharP = *input_line_pointer;
8004 *input_line_pointer = 0;
8005 e->X_op = O_register;
8006 e->X_add_number = r - i386_regtab;
8007 return 1;
8008 }
8009 input_line_pointer = end;
8010 *end = 0;
ee86248c 8011 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 8012}
8013
8014void
8015md_operand (expressionS *e)
8016{
ee86248c
JB		 8017 char *end;
8018 const reg_entry *r;
4d1bb795 8019
ee86248c
JB		 8020 switch (*input_line_pointer)
8021 {
8022 case REGISTER_PREFIX:
8023 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 8024 if (r)
8025 {
8026 e->X_op = O_register;
8027 e->X_add_number = r - i386_regtab;
8028 input_line_pointer = end;
8029 }
ee86248c
JB		 8030 break;
8031
8032 case '[':
9c2799c2 8033 gas_assert (intel_syntax);
ee86248c
JB		 8034 end = input_line_pointer++;
8035 expression (e);
8036 if (*input_line_pointer == ']')
8037 {
8038 ++input_line_pointer;
8039 e->X_op_symbol = make_expr_symbol (e);
8040 e->X_add_symbol = NULL;
8041 e->X_add_number = 0;
8042 e->X_op = O_index;
8043 }
8044 else
8045 {
8046 e->X_op = O_absent;
8047 input_line_pointer = end;
8048 }
8049 break;
4d1bb795
JB		 8050 }
8051}
8052
252b5132 8053\f
4cc782b5 8054#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 8055const char *md_shortopts = "kVQ:sqn";
252b5132 8056#else
12b55ccc 8057const char *md_shortopts = "qn";
252b5132 8058#endif
6e0b89ee 8059
3e73aa7c 8060#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 8061#define OPTION_64 (OPTION_MD_BASE + 1)
8062#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 8063#define OPTION_MARCH (OPTION_MD_BASE + 3)
8064#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 8065#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
8066#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
8067#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
8068#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
8069#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 8070#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 8071#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
40a9833c 8072#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 12)
b3b91714 8073
99ad8390
NC		 8074struct option md_longopts[] =
8075{
3e73aa7c 8076 {"32", no_argument, NULL, OPTION_32},
321098a5
L		 8077#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8078 || defined (TE_PE) || defined (TE_PEP))
3e73aa7c 8079 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 8080#endif
b3b91714 8081 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 8082 {"march", required_argument, NULL, OPTION_MARCH},
8083 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 8084 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
8085 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
8086 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
8087 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
8088 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 8089 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 8090 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
539f890d 8091 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
252b5132
RH		 8092 {NULL, no_argument, NULL, 0}
8093};
8094size_t md_longopts_size = sizeof (md_longopts);
8095
8096int
9103f4f4 8097md_parse_option (int c, char *arg)
252b5132 8098{
91d6fa6a 8099 unsigned int j;
6305a203 8100 char *arch, *next;
9103f4f4 8101
252b5132
RH		 8102 switch (c)
8103 {
12b55ccc
L		 8104 case 'n':
8105 optimize_align_code = 0;
8106 break;
8107
a38cf1db
AM		 8108 case 'q':
8109 quiet_warnings = 1;
252b5132
RH		 8110 break;
8111
8112#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 8113 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
8114 should be emitted or not. FIXME: Not implemented. */
8115 case 'Q':
252b5132
RH		 8116 break;
8117
8118 /* -V: SVR4 argument to print version ID. */
8119 case 'V':
8120 print_version_id ();
8121 break;
8122
a38cf1db
AM		 8123 /* -k: Ignore for FreeBSD compatibility. */
8124 case 'k':
252b5132 8125 break;
4cc782b5
ILT		 8126
8127 case 's':
8128 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 8129 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 8130 break;
99ad8390 8131#endif
321098a5
L		 8132#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8133 || defined (TE_PE) || defined (TE_PEP))
3e73aa7c
JH		 8134 case OPTION_64:
8135 {
8136 const char **list, **l;
8137
3e73aa7c
JH		 8138 list = bfd_target_list ();
8139 for (l = list; *l != NULL; l++)
8620418b 8140 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 8141 || strcmp (*l, "coff-x86-64") == 0
8142 || strcmp (*l, "pe-x86-64") == 0
8143 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 8144 {
8145 default_arch = "x86_64";
8146 break;
8147 }
3e73aa7c 8148 if (*l == NULL)
6e0b89ee 8149 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 8150 free (list);
8151 }
8152 break;
8153#endif
252b5132 8154
6e0b89ee
AM		 8155 case OPTION_32:
8156 default_arch = "i386";
8157 break;
8158
b3b91714
AM		 8159 case OPTION_DIVIDE:
8160#ifdef SVR4_COMMENT_CHARS
8161 {
8162 char *n, *t;
8163 const char *s;
8164
8165 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
8166 t = n;
8167 for (s = i386_comment_chars; *s != '\0'; s++)
8168 if (*s != '/')
8169 *t++ = *s;
8170 *t = '\0';
8171 i386_comment_chars = n;
8172 }
8173#endif
8174 break;
8175
9103f4f4 8176 case OPTION_MARCH:
6305a203
L		 8177 arch = xstrdup (arg);
8178 do
9103f4f4 8179 {
6305a203
L		 8180 if (*arch == '.')
8181 as_fatal (_("Invalid -march= option: `%s'"), arg);
8182 next = strchr (arch, '+');
8183 if (next)
8184 *next++ = '\0';
91d6fa6a 8185 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 8186 {
91d6fa6a 8187 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 8188 {
6305a203 8189 /* Processor. */
91d6fa6a 8190 cpu_arch_name = cpu_arch[j].name;
6305a203 8191 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 8192 cpu_arch_flags = cpu_arch[j].flags;
8193 cpu_arch_isa = cpu_arch[j].type;
8194 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 8195 if (!cpu_arch_tune_set)
8196 {
8197 cpu_arch_tune = cpu_arch_isa;
8198 cpu_arch_tune_flags = cpu_arch_isa_flags;
8199 }
8200 break;
8201 }
91d6fa6a
NC		 8202 else if (*cpu_arch [j].name == '.'
8203 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203
L		 8204 {
8205 /* ISA entension. */
8206 i386_cpu_flags flags;
309d3373
JB		 8207
8208 if (strncmp (arch, "no", 2))
8209 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 8210 cpu_arch[j].flags);
309d3373
JB		 8211 else
8212 flags = cpu_flags_and_not (cpu_arch_flags,
91d6fa6a 8213 cpu_arch[j].flags);
0dfbf9d7 8214 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 8215 {
8216 if (cpu_sub_arch_name)
8217 {
8218 char *name = cpu_sub_arch_name;
8219 cpu_sub_arch_name = concat (name,
91d6fa6a 8220 cpu_arch[j].name,
1bf57e9f 8221 (const char *) NULL);
6305a203
L		 8222 free (name);
8223 }
8224 else
91d6fa6a 8225 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203
L		 8226 cpu_arch_flags = flags;
8227 }
8228 break;
ccc9c027 8229 }
9103f4f4 8230 }
6305a203 8231
91d6fa6a 8232 if (j >= ARRAY_SIZE (cpu_arch))
6305a203
L		 8233 as_fatal (_("Invalid -march= option: `%s'"), arg);
8234
8235 arch = next;
9103f4f4 8236 }
6305a203 8237 while (next != NULL );
9103f4f4
L		 8238 break;
8239
8240 case OPTION_MTUNE:
8241 if (*arg == '.')
8242 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
91d6fa6a 8243 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 8244 {
91d6fa6a 8245 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 8246 {
ccc9c027 8247 cpu_arch_tune_set = 1;
91d6fa6a
NC		 8248 cpu_arch_tune = cpu_arch [j].type;
8249 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 8250 break;
8251 }
8252 }
91d6fa6a 8253 if (j >= ARRAY_SIZE (cpu_arch))
9103f4f4
L		 8254 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
8255 break;
8256
1efbbeb4
L		 8257 case OPTION_MMNEMONIC:
8258 if (strcasecmp (arg, "att") == 0)
8259 intel_mnemonic = 0;
8260 else if (strcasecmp (arg, "intel") == 0)
8261 intel_mnemonic = 1;
8262 else
8263 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
8264 break;
8265
8266 case OPTION_MSYNTAX:
8267 if (strcasecmp (arg, "att") == 0)
8268 intel_syntax = 0;
8269 else if (strcasecmp (arg, "intel") == 0)
8270 intel_syntax = 1;
8271 else
8272 as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
8273 break;
8274
8275 case OPTION_MINDEX_REG:
8276 allow_index_reg = 1;
8277 break;
8278
8279 case OPTION_MNAKED_REG:
8280 allow_naked_reg = 1;
8281 break;
8282
8283 case OPTION_MOLD_GCC:
8284 old_gcc = 1;
1efbbeb4
L		 8285 break;
8286
c0f3af97
L		 8287 case OPTION_MSSE2AVX:
8288 sse2avx = 1;
8289 break;
8290
daf50ae7
L		 8291 case OPTION_MSSE_CHECK:
8292 if (strcasecmp (arg, "error") == 0)
8293 sse_check = sse_check_error;
8294 else if (strcasecmp (arg, "warning") == 0)
8295 sse_check = sse_check_warning;
8296 else if (strcasecmp (arg, "none") == 0)
8297 sse_check = sse_check_none;
8298 else
8299 as_fatal (_("Invalid -msse-check= option: `%s'"), arg);
8300 break;
8301
539f890d
L		 8302 case OPTION_MAVXSCALAR:
8303 if (strcasecmp (arg, "128") == 0)
8304 avxscalar = vex128;
8305 else if (strcasecmp (arg, "256") == 0)
8306 avxscalar = vex256;
8307 else
8308 as_fatal (_("Invalid -mavxscalar= option: `%s'"), arg);
8309 break;
8310
252b5132
RH		 8311 default:
8312 return 0;
8313 }
8314 return 1;
8315}
8316
8a2c8fef
L		 8317#define MESSAGE_TEMPLATE \
8318" "
8319
8320static void
8321show_arch (FILE *stream, int ext)
8322{
8323 static char message[] = MESSAGE_TEMPLATE;
8324 char *start = message + 27;
8325 char *p;
8326 int size = sizeof (MESSAGE_TEMPLATE);
8327 int left;
8328 const char *name;
8329 int len;
8330 unsigned int j;
8331
8332 p = start;
8333 left = size - (start - message);
8334 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
8335 {
8336 /* Should it be skipped? */
8337 if (cpu_arch [j].skip)
8338 continue;
8339
8340 name = cpu_arch [j].name;
8341 len = cpu_arch [j].len;
8342 if (*name == '.')
8343 {
8344 /* It is an extension. Skip if we aren't asked to show it. */
8345 if (ext)
8346 {
8347 name++;
8348 len--;
8349 }
8350 else
8351 continue;
8352 }
8353 else if (ext)
8354 {
8355 /* It is an processor. Skip if we show only extension. */
8356 continue;
8357 }
8358
8359 /* Reserve 2 spaces for ", " or ",\0" */
8360 left -= len + 2;
8361
8362 /* Check if there is any room. */
8363 if (left >= 0)
8364 {
8365 if (p != start)
8366 {
8367 *p++ = ',';
8368 *p++ = ' ';
8369 }
8370 p = mempcpy (p, name, len);
8371 }
8372 else
8373 {
8374 /* Output the current message now and start a new one. */
8375 *p++ = ',';
8376 *p = '\0';
8377 fprintf (stream, "%s\n", message);
8378 p = start;
8379 left = size - (start - message) - len - 2;
8380
8381 gas_assert (left >= 0);
8382
8383 p = mempcpy (p, name, len);
8384 }
8385 }
8386
8387 *p = '\0';
8388 fprintf (stream, "%s\n", message);
8389}
8390
252b5132 8391void
8a2c8fef 8392md_show_usage (FILE *stream)
252b5132 8393{
4cc782b5
ILT		 8394#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8395 fprintf (stream, _("\
a38cf1db
AM		 8396 -Q ignored\n\
8397 -V print assembler version number\n\
b3b91714
AM		 8398 -k ignored\n"));
8399#endif
8400 fprintf (stream, _("\
12b55ccc 8401 -n Do not optimize code alignment\n\
b3b91714
AM		 8402 -q quieten some warnings\n"));
8403#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8404 fprintf (stream, _("\
a38cf1db 8405 -s ignored\n"));
b3b91714 8406#endif
321098a5
L		 8407#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8408 || defined (TE_PE) || defined (TE_PEP))
751d281c
L		 8409 fprintf (stream, _("\
8410 --32/--64 generate 32bit/64bit code\n"));
8411#endif
b3b91714
AM		 8412#ifdef SVR4_COMMENT_CHARS
8413 fprintf (stream, _("\
8414 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 8415#else
8416 fprintf (stream, _("\
b3b91714 8417 --divide ignored\n"));
4cc782b5 8418#endif
9103f4f4 8419 fprintf (stream, _("\
6305a203 8420 -march=CPU[,+EXTENSION...]\n\
8a2c8fef
L		 8421 generate code for CPU and EXTENSION, CPU is one of:\n"));
8422 show_arch (stream, 0);
8423 fprintf (stream, _("\
8424 EXTENSION is combination of:\n"));
8425 show_arch (stream, 1);
6305a203 8426 fprintf (stream, _("\
8a2c8fef
L		 8427 -mtune=CPU optimize for CPU, CPU is one of:\n"));
8428 show_arch (stream, 0);
ba104c83 8429 fprintf (stream, _("\
c0f3af97
L		 8430 -msse2avx encode SSE instructions with VEX prefix\n"));
8431 fprintf (stream, _("\
daf50ae7
L		 8432 -msse-check=[none|error|warning]\n\
8433 check SSE instructions\n"));
8434 fprintf (stream, _("\
539f890d
L		 8435 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
8436 length\n"));
8437 fprintf (stream, _("\
ba104c83
L		 8438 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8439 fprintf (stream, _("\
8440 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8441 fprintf (stream, _("\
8442 -mindex-reg support pseudo index registers\n"));
8443 fprintf (stream, _("\
8444 -mnaked-reg don't require `%%' prefix for registers\n"));
8445 fprintf (stream, _("\
8446 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
252b5132
RH		 8447}
8448
3e73aa7c 8449#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 8450 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 8451 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 8452
8453/* Pick the target format to use. */
8454
47926f60 8455const char *
e3bb37b5 8456i386_target_format (void)
252b5132 8457{
3e73aa7c 8458 if (!strcmp (default_arch, "x86_64"))
78f12dd3 8459 update_code_flag (CODE_64BIT, 1);
3e73aa7c 8460 else if (!strcmp (default_arch, "i386"))
78f12dd3 8461 update_code_flag (CODE_32BIT, 1);
3e73aa7c
JH		 8462 else
8463 as_fatal (_("Unknown architecture"));
89507696
JB		 8464
8465 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
8466 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
8467 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
8468 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
8469
252b5132
RH		 8470 switch (OUTPUT_FLAVOR)
8471 {
9384f2ff 8472#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 8473 case bfd_target_aout_flavour:
47926f60 8474 return AOUT_TARGET_FORMAT;
4c63da97 8475#endif
9384f2ff
AM		 8476#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
8477# if defined (TE_PE) || defined (TE_PEP)
8478 case bfd_target_coff_flavour:
8479 return flag_code == CODE_64BIT ? "pe-x86-64" : "pe-i386";
8480# elif defined (TE_GO32)
0561d57c
JK		 8481 case bfd_target_coff_flavour:
8482 return "coff-go32";
9384f2ff 8483# else
252b5132
RH		 8484 case bfd_target_coff_flavour:
8485 return "coff-i386";
9384f2ff 8486# endif
4c63da97 8487#endif
3e73aa7c 8488#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 8489 case bfd_target_elf_flavour:
3e73aa7c 8490 {
e5cb08ac 8491 if (flag_code == CODE_64BIT)
4fa24527
JB		 8492 {
8493 object_64bit = 1;
8494 use_rela_relocations = 1;
8495 }
3632d14b 8496 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 8497 {
8498 if (flag_code != CODE_64BIT)
8499 as_fatal (_("Intel L1OM is 64bit only"));
8500 return ELF_TARGET_L1OM_FORMAT;
8501 }
8502 else
8503 return (flag_code == CODE_64BIT
8504 ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT);
3e73aa7c 8505 }
e57f8c65
TG		 8506#endif
8507#if defined (OBJ_MACH_O)
8508 case bfd_target_mach_o_flavour:
8509 return flag_code == CODE_64BIT ? "mach-o-x86-64" : "mach-o-i386";
4c63da97 8510#endif
252b5132
RH		 8511 default:
8512 abort ();
8513 return NULL;
8514 }
8515}
8516
47926f60 8517#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 8518
8519#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 8520void
8521i386_elf_emit_arch_note (void)
a847613f 8522{
718ddfc0 8523 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 8524 {
8525 char *p;
8526 asection *seg = now_seg;
8527 subsegT subseg = now_subseg;
8528 Elf_Internal_Note i_note;
8529 Elf_External_Note e_note;
8530 asection *note_secp;
8531 int len;
8532
8533 /* Create the .note section. */
8534 note_secp = subseg_new (".note", 0);
8535 bfd_set_section_flags (stdoutput,
8536 note_secp,
8537 SEC_HAS_CONTENTS | SEC_READONLY);
8538
8539 /* Process the arch string. */
8540 len = strlen (cpu_arch_name);
8541
8542 i_note.namesz = len + 1;
8543 i_note.descsz = 0;
8544 i_note.type = NT_ARCH;
8545 p = frag_more (sizeof (e_note.namesz));
8546 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
8547 p = frag_more (sizeof (e_note.descsz));
8548 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
8549 p = frag_more (sizeof (e_note.type));
8550 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
8551 p = frag_more (len + 1);
8552 strcpy (p, cpu_arch_name);
8553
8554 frag_align (2, 0, 0);
8555
8556 subseg_set (seg, subseg);
8557 }
8558}
8559#endif
252b5132 8560\f
252b5132
RH		 8561symbolS *
8562md_undefined_symbol (name)
8563 char *name;
8564{
18dc2407
ILT		 8565 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
8566 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
8567 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
8568 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 8569 {
8570 if (!GOT_symbol)
8571 {
8572 if (symbol_find (name))
8573 as_bad (_("GOT already in symbol table"));
8574 GOT_symbol = symbol_new (name, undefined_section,
8575 (valueT) 0, &zero_address_frag);
8576 };
8577 return GOT_symbol;
8578 }
252b5132
RH		 8579 return 0;
8580}
8581
8582/* Round up a section size to the appropriate boundary. */
47926f60 8583
252b5132
RH		 8584valueT
8585md_section_align (segment, size)
ab9da554 8586 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 8587 valueT size;
8588{
4c63da97
AM		 8589#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8590 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
8591 {
8592 /* For a.out, force the section size to be aligned. If we don't do
8593 this, BFD will align it for us, but it will not write out the
8594 final bytes of the section. This may be a bug in BFD, but it is
8595 easier to fix it here since that is how the other a.out targets
8596 work. */
8597 int align;
8598
8599 align = bfd_get_section_alignment (stdoutput, segment);
8600 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
8601 }
252b5132
RH		 8602#endif
8603
8604 return size;
8605}
8606
8607/* On the i386, PC-relative offsets are relative to the start of the
8608 next instruction. That is, the address of the offset, plus its
8609 size, since the offset is always the last part of the insn. */
8610
8611long
e3bb37b5 8612md_pcrel_from (fixS *fixP)
252b5132
RH		 8613{
8614 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
8615}
8616
8617#ifndef I386COFF
8618
8619static void
e3bb37b5 8620s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 8621{
29b0f896 8622 int temp;
252b5132 8623
8a75718c
JB		 8624#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8625 if (IS_ELF)
8626 obj_elf_section_change_hook ();
8627#endif
252b5132
RH		 8628 temp = get_absolute_expression ();
8629 subseg_set (bss_section, (subsegT) temp);
8630 demand_empty_rest_of_line ();
8631}
8632
8633#endif
8634
252b5132 8635void
e3bb37b5 8636i386_validate_fix (fixS *fixp)
252b5132
RH		 8637{
8638 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
8639 {
23df1078
JH		 8640 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
8641 {
4fa24527 8642 if (!object_64bit)
23df1078
JH		 8643 abort ();
8644 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
8645 }
8646 else
8647 {
4fa24527 8648 if (!object_64bit)
d6ab8113
JB		 8649 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
8650 else
8651 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 8652 }
252b5132
RH		 8653 fixp->fx_subsy = 0;
8654 }
8655}
8656
252b5132
RH		 8657arelent *
8658tc_gen_reloc (section, fixp)
ab9da554 8659 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 8660 fixS *fixp;
8661{
8662 arelent *rel;
8663 bfd_reloc_code_real_type code;
8664
8665 switch (fixp->fx_r_type)
8666 {
3e73aa7c
JH		 8667 case BFD_RELOC_X86_64_PLT32:
8668 case BFD_RELOC_X86_64_GOT32:
8669 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 8670 case BFD_RELOC_386_PLT32:
8671 case BFD_RELOC_386_GOT32:
8672 case BFD_RELOC_386_GOTOFF:
8673 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 8674 case BFD_RELOC_386_TLS_GD:
8675 case BFD_RELOC_386_TLS_LDM:
8676 case BFD_RELOC_386_TLS_LDO_32:
8677 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 8678 case BFD_RELOC_386_TLS_IE:
8679 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 8680 case BFD_RELOC_386_TLS_LE_32:
8681 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 8682 case BFD_RELOC_386_TLS_GOTDESC:
8683 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 8684 case BFD_RELOC_X86_64_TLSGD:
8685 case BFD_RELOC_X86_64_TLSLD:
8686 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 8687 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 8688 case BFD_RELOC_X86_64_GOTTPOFF:
8689 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 8690 case BFD_RELOC_X86_64_TPOFF64:
8691 case BFD_RELOC_X86_64_GOTOFF64:
8692 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 8693 case BFD_RELOC_X86_64_GOT64:
8694 case BFD_RELOC_X86_64_GOTPCREL64:
8695 case BFD_RELOC_X86_64_GOTPC64:
8696 case BFD_RELOC_X86_64_GOTPLT64:
8697 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 8698 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8699 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 8700 case BFD_RELOC_RVA:
8701 case BFD_RELOC_VTABLE_ENTRY:
8702 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 8703#ifdef TE_PE
8704 case BFD_RELOC_32_SECREL:
8705#endif
252b5132
RH		 8706 code = fixp->fx_r_type;
8707 break;
dbbaec26
L		 8708 case BFD_RELOC_X86_64_32S:
8709 if (!fixp->fx_pcrel)
8710 {
8711 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8712 code = fixp->fx_r_type;
8713 break;
8714 }
252b5132 8715 default:
93382f6d 8716 if (fixp->fx_pcrel)
252b5132 8717 {
93382f6d
AM		 8718 switch (fixp->fx_size)
8719 {
8720 default:
b091f402
AM		 8721 as_bad_where (fixp->fx_file, fixp->fx_line,
8722 _("can not do %d byte pc-relative relocation"),
8723 fixp->fx_size);
93382f6d
AM		 8724 code = BFD_RELOC_32_PCREL;
8725 break;
8726 case 1: code = BFD_RELOC_8_PCREL; break;
8727 case 2: code = BFD_RELOC_16_PCREL; break;
8728 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 8729#ifdef BFD64
8730 case 8: code = BFD_RELOC_64_PCREL; break;
8731#endif
93382f6d
AM		 8732 }
8733 }
8734 else
8735 {
8736 switch (fixp->fx_size)
8737 {
8738 default:
b091f402
AM		 8739 as_bad_where (fixp->fx_file, fixp->fx_line,
8740 _("can not do %d byte relocation"),
8741 fixp->fx_size);
93382f6d
AM		 8742 code = BFD_RELOC_32;
8743 break;
8744 case 1: code = BFD_RELOC_8; break;
8745 case 2: code = BFD_RELOC_16; break;
8746 case 4: code = BFD_RELOC_32; break;
937149dd 8747#ifdef BFD64
3e73aa7c 8748 case 8: code = BFD_RELOC_64; break;
937149dd 8749#endif
93382f6d 8750 }
252b5132
RH		 8751 }
8752 break;
8753 }
252b5132 8754
d182319b
JB		 8755 if ((code == BFD_RELOC_32
8756 || code == BFD_RELOC_32_PCREL
8757 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 8758 && GOT_symbol
8759 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 8760 {
4fa24527 8761 if (!object_64bit)
d6ab8113
JB		 8762 code = BFD_RELOC_386_GOTPC;
8763 else
8764 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 8765 }
7b81dfbb
AJ		 8766 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
8767 && GOT_symbol
8768 && fixp->fx_addsy == GOT_symbol)
8769 {
8770 code = BFD_RELOC_X86_64_GOTPC64;
8771 }
252b5132
RH		 8772
8773 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 8774 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
8775 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 8776
8777 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 8778
3e73aa7c
JH		 8779 if (!use_rela_relocations)
8780 {
8781 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8782 vtable entry to be used in the relocation's section offset. */
8783 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
8784 rel->address = fixp->fx_offset;
fbeb56a4
DK		 8785#if defined (OBJ_COFF) && defined (TE_PE)
8786 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
8787 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
8788 else
8789#endif
c6682705 8790 rel->addend = 0;
3e73aa7c
JH		 8791 }
8792 /* Use the rela in 64bit mode. */
252b5132 8793 else
3e73aa7c 8794 {
062cd5e7
AS		 8795 if (!fixp->fx_pcrel)
8796 rel->addend = fixp->fx_offset;
8797 else
8798 switch (code)
8799 {
8800 case BFD_RELOC_X86_64_PLT32:
8801 case BFD_RELOC_X86_64_GOT32:
8802 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 8803 case BFD_RELOC_X86_64_TLSGD:
8804 case BFD_RELOC_X86_64_TLSLD:
8805 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 8806 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8807 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 8808 rel->addend = fixp->fx_offset - fixp->fx_size;
8809 break;
8810 default:
8811 rel->addend = (section->vma
8812 - fixp->fx_size
8813 + fixp->fx_addnumber
8814 + md_pcrel_from (fixp));
8815 break;
8816 }
3e73aa7c
JH		 8817 }
8818
252b5132
RH		 8819 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
8820 if (rel->howto == NULL)
8821 {
8822 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 8823 _("cannot represent relocation type %s"),
252b5132
RH		 8824 bfd_get_reloc_code_name (code));
8825 /* Set howto to a garbage value so that we can keep going. */
8826 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 8827 gas_assert (rel->howto != NULL);
252b5132
RH		 8828 }
8829
8830 return rel;
8831}
8832
ee86248c 8833#include "tc-i386-intel.c"
54cfded0 8834
a60de03c
JB		 8835void
8836tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 8837{
a60de03c
JB		 8838 int saved_naked_reg;
8839 char saved_register_dot;
54cfded0 8840
a60de03c
JB		 8841 saved_naked_reg = allow_naked_reg;
8842 allow_naked_reg = 1;
8843 saved_register_dot = register_chars['.'];
8844 register_chars['.'] = '.';
8845 allow_pseudo_reg = 1;
8846 expression_and_evaluate (exp);
8847 allow_pseudo_reg = 0;
8848 register_chars['.'] = saved_register_dot;
8849 allow_naked_reg = saved_naked_reg;
8850
e96d56a1 8851 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 8852 {
a60de03c
JB		 8853 if ((addressT) exp->X_add_number < i386_regtab_size)
8854 {
8855 exp->X_op = O_constant;
8856 exp->X_add_number = i386_regtab[exp->X_add_number]
8857 .dw2_regnum[flag_code >> 1];
8858 }
8859 else
8860 exp->X_op = O_illegal;
54cfded0 8861 }
54cfded0
AM		 8862}
8863
8864void
8865tc_x86_frame_initial_instructions (void)
8866{
a60de03c
JB		 8867 static unsigned int sp_regno[2];
8868
8869 if (!sp_regno[flag_code >> 1])
8870 {
8871 char *saved_input = input_line_pointer;
8872 char sp[][4] = {"esp", "rsp"};
8873 expressionS exp;
a4447b93 8874
a60de03c
JB		 8875 input_line_pointer = sp[flag_code >> 1];
8876 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 8877 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 8878 sp_regno[flag_code >> 1] = exp.X_add_number;
8879 input_line_pointer = saved_input;
8880 }
a4447b93 8881
a60de03c 8882 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
a4447b93 8883 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 8884}
d2b2c203
DJ		 8885
8886int
8887i386_elf_section_type (const char *str, size_t len)
8888{
8889 if (flag_code == CODE_64BIT
8890 && len == sizeof ("unwind") - 1
8891 && strncmp (str, "unwind", 6) == 0)
8892 return SHT_X86_64_UNWIND;
8893
8894 return -1;
8895}
bb41ade5 8896
ad5fec3b
EB		 8897#ifdef TE_SOLARIS
8898void
8899i386_solaris_fix_up_eh_frame (segT sec)
8900{
8901 if (flag_code == CODE_64BIT)
8902 elf_section_type (sec) = SHT_X86_64_UNWIND;
8903}
8904#endif
8905
bb41ade5
AM		 8906#ifdef TE_PE
8907void
8908tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
8909{
91d6fa6a 8910 expressionS exp;
bb41ade5 8911
91d6fa6a
NC		 8912 exp.X_op = O_secrel;
8913 exp.X_add_symbol = symbol;
8914 exp.X_add_number = 0;
8915 emit_expr (&exp, size);
bb41ade5
AM		 8916}
8917#endif
3b22753a
L		 8918
8919#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8920/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8921
01e1a5bc 8922bfd_vma
3b22753a
L		 8923x86_64_section_letter (int letter, char **ptr_msg)
8924{
8925 if (flag_code == CODE_64BIT)
8926 {
8927 if (letter == 'l')
8928 return SHF_X86_64_LARGE;
8929
8930 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 8931 }
3b22753a 8932 else
64e74474 8933 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 8934 return -1;
8935}
8936
01e1a5bc 8937bfd_vma
3b22753a
L		 8938x86_64_section_word (char *str, size_t len)
8939{
8620418b 8940 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 8941 return SHF_X86_64_LARGE;
8942
8943 return -1;
8944}
8945
8946static void
8947handle_large_common (int small ATTRIBUTE_UNUSED)
8948{
8949 if (flag_code != CODE_64BIT)
8950 {
8951 s_comm_internal (0, elf_common_parse);
8952 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
8953 }
8954 else
8955 {
8956 static segT lbss_section;
8957 asection *saved_com_section_ptr = elf_com_section_ptr;
8958 asection *saved_bss_section = bss_section;
8959
8960 if (lbss_section == NULL)
8961 {
8962 flagword applicable;
8963 segT seg = now_seg;
8964 subsegT subseg = now_subseg;
8965
8966 /* The .lbss section is for local .largecomm symbols. */
8967 lbss_section = subseg_new (".lbss", 0);
8968 applicable = bfd_applicable_section_flags (stdoutput);
8969 bfd_set_section_flags (stdoutput, lbss_section,
8970 applicable & SEC_ALLOC);
8971 seg_info (lbss_section)->bss = 1;
8972
8973 subseg_set (seg, subseg);
8974 }
8975
8976 elf_com_section_ptr = &_bfd_elf_large_com_section;
8977 bss_section = lbss_section;
8978
8979 s_comm_internal (0, elf_common_parse);
8980
8981 elf_com_section_ptr = saved_com_section_ptr;
8982 bss_section = saved_bss_section;
8983 }
8984}
8985#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
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