]> Git Repo - binutils.git/blame - gas/config/tc-i386.c
projects / binutils.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Replace Vex0F, Vex0F38, Vex0F3A, XOP08, XOP09 and XOP0A with VexOpcode.
[binutils.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
0bfee649 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus ([email protected]).
3e73aa7c 25 x86_64 support by Jan Hubicka ([email protected])
0f10071e 26 VIA PadLock support by Michal Ludvig ([email protected])
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
40fb9820 36#include "opcodes/i386-init.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
29b0f896
AM		 46#ifndef DEFAULT_ARCH
47#define DEFAULT_ARCH "i386"
246fcdee 48#endif
252b5132 49
edde18a5
AM		 50#ifndef INLINE
51#if __GNUC__ >= 2
52#define INLINE __inline__
53#else
54#define INLINE
55#endif
56#endif
57
6305a203
L		 58/* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
c32fa91d 62 REP_PREFIX, LOCK_PREFIX. */
6305a203
L		 63#define WAIT_PREFIX 0
64#define SEG_PREFIX 1
65#define ADDR_PREFIX 2
66#define DATA_PREFIX 3
c32fa91d
L		 67#define REP_PREFIX 4
68#define LOCK_PREFIX 5
69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
84#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 85#define YMMWORD_MNEM_SUFFIX 'y'
6305a203
L		 86/* Intel Syntax. Use a non-ascii letter since since it never appears
87 in instructions. */
88#define LONG_DOUBLE_MNEM_SUFFIX '\1'
89
90#define END_OF_INSN '\0'
91
92/*
93 'templates' is for grouping together 'template' structures for opcodes
94 of the same name. This is only used for storing the insns in the grand
95 ole hash table of insns.
96 The templates themselves start at START and range up to (but not including)
97 END.
98 */
99typedef struct
100{
d3ce72d0
NC		 101 const insn_template *start;
102 const insn_template *end;
6305a203
L		 103}
104templates;
105
106/* 386 operand encoding bytes: see 386 book for details of this. */
107typedef struct
108{
109 unsigned int regmem; /* codes register or memory operand */
110 unsigned int reg; /* codes register operand (or extended opcode) */
111 unsigned int mode; /* how to interpret regmem & reg */
112}
113modrm_byte;
114
115/* x86-64 extension prefix. */
116typedef int rex_byte;
117
6305a203
L		 118/* 386 opcode byte to code indirect addressing. */
119typedef struct
120{
121 unsigned base;
122 unsigned index;
123 unsigned scale;
124}
125sib_byte;
126
6305a203
L		 127/* x86 arch names, types and features */
128typedef struct
129{
130 const char *name; /* arch name */
8a2c8fef 131 unsigned int len; /* arch string length */
6305a203
L		 132 enum processor_type type; /* arch type */
133 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 134 unsigned int skip; /* show_arch should skip this. */
6305a203
L		 135}
136arch_entry;
137
e3bb37b5
L		 138static void set_code_flag (int);
139static void set_16bit_gcc_code_flag (int);
140static void set_intel_syntax (int);
1efbbeb4 141static void set_intel_mnemonic (int);
db51cc60 142static void set_allow_index_reg (int);
cb19c032 143static void set_sse_check (int);
e3bb37b5 144static void set_cpu_arch (int);
6482c264 145#ifdef TE_PE
e3bb37b5 146static void pe_directive_secrel (int);
6482c264 147#endif
e3bb37b5
L		 148static void signed_cons (int);
149static char *output_invalid (int c);
ee86248c
JB		 150static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
151 const char *);
152static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
153 const char *);
a7619375 154static int i386_att_operand (char *);
e3bb37b5 155static int i386_intel_operand (char *, int);
ee86248c
JB		 156static int i386_intel_simplify (expressionS *);
157static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 158static const reg_entry *parse_register (char *, char **);
159static char *parse_insn (char *, char *);
160static char *parse_operands (char *, const char *);
161static void swap_operands (void);
4d456e3d 162static void swap_2_operands (int, int);
e3bb37b5
L		 163static void optimize_imm (void);
164static void optimize_disp (void);
d3ce72d0 165static const insn_template *match_template (void);
e3bb37b5
L		 166static int check_string (void);
167static int process_suffix (void);
168static int check_byte_reg (void);
169static int check_long_reg (void);
170static int check_qword_reg (void);
171static int check_word_reg (void);
172static int finalize_imm (void);
173static int process_operands (void);
174static const seg_entry *build_modrm_byte (void);
175static void output_insn (void);
176static void output_imm (fragS *, offsetT);
177static void output_disp (fragS *, offsetT);
29b0f896 178#ifndef I386COFF
e3bb37b5 179static void s_bss (int);
252b5132 180#endif
17d4e2a2
L		 181#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
182static void handle_large_common (int small ATTRIBUTE_UNUSED);
183#endif
252b5132 184
a847613f 185static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 186
c0f3af97
L		 187/* VEX prefix. */
188typedef struct
189{
190 /* VEX prefix is either 2 byte or 3 byte. */
191 unsigned char bytes[3];
192 unsigned int length;
193 /* Destination or source register specifier. */
194 const reg_entry *register_specifier;
195} vex_prefix;
196
252b5132 197/* 'md_assemble ()' gathers together information and puts it into a
47926f60 198 i386_insn. */
252b5132 199
520dc8e8
AM		 200union i386_op
201 {
202 expressionS *disps;
203 expressionS *imms;
204 const reg_entry *regs;
205 };
206
252b5132
RH		 207struct _i386_insn
208 {
47926f60 209 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 210 insn_template tm;
252b5132 211
7d5e4556
L		 212 /* SUFFIX holds the instruction size suffix for byte, word, dword
213 or qword, if given. */
252b5132
RH		 214 char suffix;
215
47926f60 216 /* OPERANDS gives the number of given operands. */
252b5132
RH		 217 unsigned int operands;
218
219 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
220 of given register, displacement, memory operands and immediate
47926f60 221 operands. */
252b5132
RH		 222 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
223
224 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 225 use OP[i] for the corresponding operand. */
40fb9820 226 i386_operand_type types[MAX_OPERANDS];
252b5132 227
520dc8e8
AM		 228 /* Displacement expression, immediate expression, or register for each
229 operand. */
230 union i386_op op[MAX_OPERANDS];
252b5132 231
3e73aa7c
JH		 232 /* Flags for operands. */
233 unsigned int flags[MAX_OPERANDS];
234#define Operand_PCrel 1
235
252b5132 236 /* Relocation type for operand */
f86103b7 237 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 238
252b5132
RH		 239 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
240 the base index byte below. */
241 const reg_entry *base_reg;
242 const reg_entry *index_reg;
243 unsigned int log2_scale_factor;
244
245 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 246 explicit segment overrides are given. */
ce8a8b2f 247 const seg_entry *seg[2];
252b5132
RH		 248
249 /* PREFIX holds all the given prefix opcodes (usually null).
250 PREFIXES is the number of prefix opcodes. */
251 unsigned int prefixes;
252 unsigned char prefix[MAX_PREFIXES];
253
254 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 255 addressing modes of this insn are encoded. */
252b5132 256 modrm_byte rm;
3e73aa7c 257 rex_byte rex;
252b5132 258 sib_byte sib;
c0f3af97 259 vex_prefix vex;
b6169b20
L		 260
261 /* Swap operand in encoding. */
4473e004 262 unsigned int swap_operand;
252b5132
RH		 263 };
264
265typedef struct _i386_insn i386_insn;
266
267/* List of chars besides those in app.c:symbol_chars that can start an
268 operand. Used to prevent the scrubber eating vital white-space. */
32137342 269const char extra_symbol_chars[] = "*%-(["
252b5132 270#ifdef LEX_AT
32137342
NC		 271 "@"
272#endif
273#ifdef LEX_QM
274 "?"
252b5132 275#endif
32137342 276 ;
252b5132 277
29b0f896
AM		 278#if (defined (TE_I386AIX) \
279 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 280 && !defined (TE_GNU) \
29b0f896 281 && !defined (TE_LINUX) \
32137342 282 && !defined (TE_NETWARE) \
29b0f896
AM		 283 && !defined (TE_FreeBSD) \
284 && !defined (TE_NetBSD)))
252b5132 285/* This array holds the chars that always start a comment. If the
b3b91714
AM		 286 pre-processor is disabled, these aren't very useful. The option
287 --divide will remove '/' from this list. */
288const char *i386_comment_chars = "#/";
289#define SVR4_COMMENT_CHARS 1
252b5132 290#define PREFIX_SEPARATOR '\\'
252b5132 291
b3b91714
AM		 292#else
293const char *i386_comment_chars = "#";
294#define PREFIX_SEPARATOR '/'
295#endif
296
252b5132
RH		 297/* This array holds the chars that only start a comment at the beginning of
298 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 299 .line and .file directives will appear in the pre-processed output.
300 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 301 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 302 #NO_APP at the beginning of its output.
303 Also note that comments started like this one will always work if
252b5132 304 '/' isn't otherwise defined. */
b3b91714 305const char line_comment_chars[] = "#/";
252b5132 306
63a0b638 307const char line_separator_chars[] = ";";
252b5132 308
ce8a8b2f
AM		 309/* Chars that can be used to separate mant from exp in floating point
310 nums. */
252b5132
RH		 311const char EXP_CHARS[] = "eE";
312
ce8a8b2f
AM		 313/* Chars that mean this number is a floating point constant
314 As in 0f12.456
315 or 0d1.2345e12. */
252b5132
RH		 316const char FLT_CHARS[] = "fFdDxX";
317
ce8a8b2f 318/* Tables for lexical analysis. */
252b5132
RH		 319static char mnemonic_chars[256];
320static char register_chars[256];
321static char operand_chars[256];
322static char identifier_chars[256];
323static char digit_chars[256];
324
ce8a8b2f 325/* Lexical macros. */
252b5132
RH		 326#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
327#define is_operand_char(x) (operand_chars[(unsigned char) x])
328#define is_register_char(x) (register_chars[(unsigned char) x])
329#define is_space_char(x) ((x) == ' ')
330#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
331#define is_digit_char(x) (digit_chars[(unsigned char) x])
332
0234cb7c 333/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 334static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
335
336/* md_assemble() always leaves the strings it's passed unaltered. To
337 effect this we maintain a stack of saved characters that we've smashed
338 with '\0's (indicating end of strings for various sub-fields of the
47926f60 339 assembler instruction). */
252b5132 340static char save_stack[32];
ce8a8b2f 341static char *save_stack_p;
252b5132
RH		 342#define END_STRING_AND_SAVE(s) \
343 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
344#define RESTORE_END_STRING(s) \
345 do { *(s) = *--save_stack_p; } while (0)
346
47926f60 347/* The instruction we're assembling. */
252b5132
RH		 348static i386_insn i;
349
350/* Possible templates for current insn. */
351static const templates *current_templates;
352
31b2323c
L		 353/* Per instruction expressionS buffers: max displacements & immediates. */
354static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
355static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 356
47926f60 357/* Current operand we are working on. */
ee86248c 358static int this_operand = -1;
252b5132 359
3e73aa7c
JH		 360/* We support four different modes. FLAG_CODE variable is used to distinguish
361 these. */
362
363enum flag_code {
364 CODE_32BIT,
365 CODE_16BIT,
366 CODE_64BIT };
367
368static enum flag_code flag_code;
4fa24527 369static unsigned int object_64bit;
3e73aa7c
JH		 370static int use_rela_relocations = 0;
371
372/* The names used to print error messages. */
b77a7acd 373static const char *flag_code_names[] =
3e73aa7c
JH		 374 {
375 "32",
376 "16",
377 "64"
378 };
252b5132 379
47926f60
KH		 380/* 1 for intel syntax,
381 0 if att syntax. */
382static int intel_syntax = 0;
252b5132 383
1efbbeb4
L		 384/* 1 for intel mnemonic,
385 0 if att mnemonic. */
386static int intel_mnemonic = !SYSV386_COMPAT;
387
5209009a 388/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 389static int old_gcc = OLDGCC_COMPAT;
390
a60de03c
JB		 391/* 1 if pseudo registers are permitted. */
392static int allow_pseudo_reg = 0;
393
47926f60
KH		 394/* 1 if register prefix % not required. */
395static int allow_naked_reg = 0;
252b5132 396
ba104c83 397/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 398static int allow_index_reg = 0;
399
daf50ae7
L		 400static enum
401 {
402 sse_check_none = 0,
403 sse_check_warning,
404 sse_check_error
405 }
406sse_check;
407
2ca3ace5
L		 408/* Register prefix used for error message. */
409static const char *register_prefix = "%";
410
47926f60
KH		 411/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
412 leave, push, and pop instructions so that gcc has the same stack
413 frame as in 32 bit mode. */
414static char stackop_size = '\0';
eecb386c 415
12b55ccc
L		 416/* Non-zero to optimize code alignment. */
417int optimize_align_code = 1;
418
47926f60
KH		 419/* Non-zero to quieten some warnings. */
420static int quiet_warnings = 0;
a38cf1db 421
47926f60
KH		 422/* CPU name. */
423static const char *cpu_arch_name = NULL;
6305a203 424static char *cpu_sub_arch_name = NULL;
a38cf1db 425
47926f60 426/* CPU feature flags. */
40fb9820
L		 427static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
428
ccc9c027
L		 429/* If we have selected a cpu we are generating instructions for. */
430static int cpu_arch_tune_set = 0;
431
9103f4f4 432/* Cpu we are generating instructions for. */
fbf3f584 433enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 434
435/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 436static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 437
ccc9c027 438/* CPU instruction set architecture used. */
fbf3f584 439enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 440
9103f4f4 441/* CPU feature flags of instruction set architecture used. */
fbf3f584 442i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 443
fddf5b5b
AM		 444/* If set, conditional jumps are not automatically promoted to handle
445 larger than a byte offset. */
446static unsigned int no_cond_jump_promotion = 0;
447
c0f3af97
L		 448/* Encode SSE instructions with VEX prefix. */
449static unsigned int sse2avx;
450
29b0f896 451/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 452static symbolS *GOT_symbol;
29b0f896 453
a4447b93
RH		 454/* The dwarf2 return column, adjusted for 32 or 64 bit. */
455unsigned int x86_dwarf2_return_column;
456
457/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
458int x86_cie_data_alignment;
459
252b5132 460/* Interface to relax_segment.
fddf5b5b
AM		 461 There are 3 major relax states for 386 jump insns because the
462 different types of jumps add different sizes to frags when we're
463 figuring out what sort of jump to choose to reach a given label. */
252b5132 464
47926f60 465/* Types. */
93c2a809
AM		 466#define UNCOND_JUMP 0
467#define COND_JUMP 1
468#define COND_JUMP86 2
fddf5b5b 469
47926f60 470/* Sizes. */
252b5132
RH		 471#define CODE16 1
472#define SMALL 0
29b0f896 473#define SMALL16 (SMALL | CODE16)
252b5132 474#define BIG 2
29b0f896 475#define BIG16 (BIG | CODE16)
252b5132
RH		 476
477#ifndef INLINE
478#ifdef __GNUC__
479#define INLINE __inline__
480#else
481#define INLINE
482#endif
483#endif
484
fddf5b5b
AM		 485#define ENCODE_RELAX_STATE(type, size) \
486 ((relax_substateT) (((type) << 2) | (size)))
487#define TYPE_FROM_RELAX_STATE(s) \
488 ((s) >> 2)
489#define DISP_SIZE_FROM_RELAX_STATE(s) \
490 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 491
492/* This table is used by relax_frag to promote short jumps to long
493 ones where necessary. SMALL (short) jumps may be promoted to BIG
494 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
495 don't allow a short jump in a 32 bit code segment to be promoted to
496 a 16 bit offset jump because it's slower (requires data size
497 prefix), and doesn't work, unless the destination is in the bottom
498 64k of the code segment (The top 16 bits of eip are zeroed). */
499
500const relax_typeS md_relax_table[] =
501{
24eab124
AM		 502 /* The fields are:
503 1) most positive reach of this state,
504 2) most negative reach of this state,
93c2a809 505 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 506 4) which index into the table to try if we can't fit into this one. */
252b5132 507
fddf5b5b 508 /* UNCOND_JUMP states. */
93c2a809
AM		 509 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
510 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
511 /* dword jmp adds 4 bytes to frag:
512 0 extra opcode bytes, 4 displacement bytes. */
252b5132 513 {0, 0, 4, 0},
93c2a809
AM		 514 /* word jmp adds 2 byte2 to frag:
515 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 516 {0, 0, 2, 0},
517
93c2a809
AM		 518 /* COND_JUMP states. */
519 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
520 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
521 /* dword conditionals adds 5 bytes to frag:
522 1 extra opcode byte, 4 displacement bytes. */
523 {0, 0, 5, 0},
fddf5b5b 524 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 525 1 extra opcode byte, 2 displacement bytes. */
526 {0, 0, 3, 0},
527
528 /* COND_JUMP86 states. */
529 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
530 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
531 /* dword conditionals adds 5 bytes to frag:
532 1 extra opcode byte, 4 displacement bytes. */
533 {0, 0, 5, 0},
534 /* word conditionals add 4 bytes to frag:
535 1 displacement byte and a 3 byte long branch insn. */
536 {0, 0, 4, 0}
252b5132
RH		 537};
538
9103f4f4
L		 539static const arch_entry cpu_arch[] =
540{
8a2c8fef
L		 541 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
542 CPU_GENERIC32_FLAGS, 0 },
543 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
544 CPU_GENERIC64_FLAGS, 0 },
545 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
546 CPU_NONE_FLAGS, 0 },
547 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
548 CPU_I186_FLAGS, 0 },
549 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
550 CPU_I286_FLAGS, 0 },
551 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
552 CPU_I386_FLAGS, 0 },
553 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
554 CPU_I486_FLAGS, 0 },
555 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
556 CPU_I586_FLAGS, 0 },
557 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
558 CPU_I686_FLAGS, 0 },
559 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
560 CPU_I586_FLAGS, 0 },
561 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
562 CPU_I686_FLAGS, 0 },
563 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
564 CPU_P2_FLAGS, 0 },
565 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
566 CPU_P3_FLAGS, 0 },
567 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
568 CPU_P4_FLAGS, 0 },
569 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
570 CPU_CORE_FLAGS, 0 },
571 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
572 CPU_NOCONA_FLAGS, 0 },
573 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
574 CPU_CORE_FLAGS, 1 },
575 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
576 CPU_CORE_FLAGS, 0 },
577 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
578 CPU_CORE2_FLAGS, 1 },
579 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
580 CPU_CORE2_FLAGS, 0 },
581 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
582 CPU_COREI7_FLAGS, 0 },
583 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
584 CPU_L1OM_FLAGS, 0 },
585 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
586 CPU_K6_FLAGS, 0 },
587 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
588 CPU_K6_2_FLAGS, 0 },
589 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
590 CPU_ATHLON_FLAGS, 0 },
591 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
592 CPU_K8_FLAGS, 1 },
593 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
594 CPU_K8_FLAGS, 0 },
595 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
596 CPU_K8_FLAGS, 0 },
597 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
598 CPU_AMDFAM10_FLAGS, 0 },
599 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
600 CPU_8087_FLAGS, 0 },
601 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
602 CPU_287_FLAGS, 0 },
603 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
604 CPU_387_FLAGS, 0 },
605 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
606 CPU_ANY87_FLAGS, 0 },
607 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
608 CPU_MMX_FLAGS, 0 },
609 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
610 CPU_3DNOWA_FLAGS, 0 },
611 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
612 CPU_SSE_FLAGS, 0 },
613 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
614 CPU_SSE2_FLAGS, 0 },
615 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
616 CPU_SSE3_FLAGS, 0 },
617 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
618 CPU_SSSE3_FLAGS, 0 },
619 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
620 CPU_SSE4_1_FLAGS, 0 },
621 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
622 CPU_SSE4_2_FLAGS, 0 },
623 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
624 CPU_SSE4_2_FLAGS, 0 },
625 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
626 CPU_ANY_SSE_FLAGS, 0 },
627 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
628 CPU_AVX_FLAGS, 0 },
629 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
630 CPU_ANY_AVX_FLAGS, 0 },
631 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
632 CPU_VMX_FLAGS, 0 },
633 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
634 CPU_SMX_FLAGS, 0 },
635 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
636 CPU_XSAVE_FLAGS, 0 },
637 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
638 CPU_AES_FLAGS, 0 },
639 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
640 CPU_PCLMUL_FLAGS, 0 },
641 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
642 CPU_PCLMUL_FLAGS, 1 },
643 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
644 CPU_FMA_FLAGS, 0 },
645 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
646 CPU_FMA4_FLAGS, 0 },
647 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
648 CPU_XOP_FLAGS, 0 },
649 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
650 CPU_LWP_FLAGS, 0 },
651 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
652 CPU_MOVBE_FLAGS, 0 },
653 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
654 CPU_EPT_FLAGS, 0 },
655 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
656 CPU_CLFLUSH_FLAGS, 0 },
657 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
658 CPU_SYSCALL_FLAGS, 0 },
659 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
660 CPU_RDTSCP_FLAGS, 0 },
661 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
662 CPU_3DNOW_FLAGS, 0 },
663 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
664 CPU_3DNOWA_FLAGS, 0 },
665 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
666 CPU_PADLOCK_FLAGS, 0 },
667 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
668 CPU_SVME_FLAGS, 1 },
669 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
670 CPU_SVME_FLAGS, 0 },
671 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
672 CPU_SSE4A_FLAGS, 0 },
673 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
674 CPU_ABM_FLAGS, 0 },
e413e4e9
AM		 675};
676
704209c0 677#ifdef I386COFF
a6c24e68
NC		 678/* Like s_lcomm_internal in gas/read.c but the alignment string
679 is allowed to be optional. */
680
681static symbolS *
682pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
683{
684 addressT align = 0;
685
686 SKIP_WHITESPACE ();
687
7ab9ffdd 688 if (needs_align
a6c24e68
NC		 689 && *input_line_pointer == ',')
690 {
691 align = parse_align (needs_align - 1);
7ab9ffdd 692
a6c24e68
NC		 693 if (align == (addressT) -1)
694 return NULL;
695 }
696 else
697 {
698 if (size >= 8)
699 align = 3;
700 else if (size >= 4)
701 align = 2;
702 else if (size >= 2)
703 align = 1;
704 else
705 align = 0;
706 }
707
708 bss_alloc (symbolP, size, align);
709 return symbolP;
710}
711
704209c0 712static void
a6c24e68
NC		 713pe_lcomm (int needs_align)
714{
715 s_comm_internal (needs_align * 2, pe_lcomm_internal);
716}
704209c0 717#endif
a6c24e68 718
29b0f896
AM		 719const pseudo_typeS md_pseudo_table[] =
720{
721#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
722 {"align", s_align_bytes, 0},
723#else
724 {"align", s_align_ptwo, 0},
725#endif
726 {"arch", set_cpu_arch, 0},
727#ifndef I386COFF
728 {"bss", s_bss, 0},
a6c24e68
NC		 729#else
730 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 731#endif
732 {"ffloat", float_cons, 'f'},
733 {"dfloat", float_cons, 'd'},
734 {"tfloat", float_cons, 'x'},
735 {"value", cons, 2},
d182319b 736 {"slong", signed_cons, 4},
29b0f896
AM		 737 {"noopt", s_ignore, 0},
738 {"optim", s_ignore, 0},
739 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
740 {"code16", set_code_flag, CODE_16BIT},
741 {"code32", set_code_flag, CODE_32BIT},
742 {"code64", set_code_flag, CODE_64BIT},
743 {"intel_syntax", set_intel_syntax, 1},
744 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 745 {"intel_mnemonic", set_intel_mnemonic, 1},
746 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 747 {"allow_index_reg", set_allow_index_reg, 1},
748 {"disallow_index_reg", set_allow_index_reg, 0},
cb19c032 749 {"sse_check", set_sse_check, 0},
3b22753a
L		 750#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
751 {"largecomm", handle_large_common, 0},
07a53e5c 752#else
e3bb37b5 753 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 754 {"loc", dwarf2_directive_loc, 0},
755 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 756#endif
6482c264
NC		 757#ifdef TE_PE
758 {"secrel32", pe_directive_secrel, 0},
759#endif
29b0f896
AM		 760 {0, 0, 0}
761};
762
763/* For interface with expression (). */
764extern char *input_line_pointer;
765
766/* Hash table for instruction mnemonic lookup. */
767static struct hash_control *op_hash;
768
769/* Hash table for register lookup. */
770static struct hash_control *reg_hash;
771\f
252b5132 772void
e3bb37b5 773i386_align_code (fragS *fragP, int count)
252b5132 774{
ce8a8b2f
AM		 775 /* Various efficient no-op patterns for aligning code labels.
776 Note: Don't try to assemble the instructions in the comments.
777 0L and 0w are not legal. */
252b5132
RH		 778 static const char f32_1[] =
779 {0x90}; /* nop */
780 static const char f32_2[] =
ccc9c027 781 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 782 static const char f32_3[] =
783 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
784 static const char f32_4[] =
785 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
786 static const char f32_5[] =
787 {0x90, /* nop */
788 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
789 static const char f32_6[] =
790 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
791 static const char f32_7[] =
792 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
793 static const char f32_8[] =
794 {0x90, /* nop */
795 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
796 static const char f32_9[] =
797 {0x89,0xf6, /* movl %esi,%esi */
798 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
799 static const char f32_10[] =
800 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
801 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
802 static const char f32_11[] =
803 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
804 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
805 static const char f32_12[] =
806 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
807 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
808 static const char f32_13[] =
809 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
810 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
811 static const char f32_14[] =
812 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
813 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 814 static const char f16_3[] =
815 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 816 static const char f16_4[] =
817 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
818 static const char f16_5[] =
819 {0x90, /* nop */
820 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
821 static const char f16_6[] =
822 {0x89,0xf6, /* mov %si,%si */
823 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
824 static const char f16_7[] =
825 {0x8d,0x74,0x00, /* lea 0(%si),%si */
826 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
827 static const char f16_8[] =
828 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
829 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 830 static const char jump_31[] =
831 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
832 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
833 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
834 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 835 static const char *const f32_patt[] = {
836 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 837 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 838 };
839 static const char *const f16_patt[] = {
76bc74dc 840 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 841 };
ccc9c027
L		 842 /* nopl (%[re]ax) */
843 static const char alt_3[] =
844 {0x0f,0x1f,0x00};
845 /* nopl 0(%[re]ax) */
846 static const char alt_4[] =
847 {0x0f,0x1f,0x40,0x00};
848 /* nopl 0(%[re]ax,%[re]ax,1) */
849 static const char alt_5[] =
850 {0x0f,0x1f,0x44,0x00,0x00};
851 /* nopw 0(%[re]ax,%[re]ax,1) */
852 static const char alt_6[] =
853 {0x66,0x0f,0x1f,0x44,0x00,0x00};
854 /* nopl 0L(%[re]ax) */
855 static const char alt_7[] =
856 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
857 /* nopl 0L(%[re]ax,%[re]ax,1) */
858 static const char alt_8[] =
859 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
860 /* nopw 0L(%[re]ax,%[re]ax,1) */
861 static const char alt_9[] =
862 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
863 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
864 static const char alt_10[] =
865 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
866 /* data16
867 nopw %cs:0L(%[re]ax,%[re]ax,1) */
868 static const char alt_long_11[] =
869 {0x66,
870 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
871 /* data16
872 data16
873 nopw %cs:0L(%[re]ax,%[re]ax,1) */
874 static const char alt_long_12[] =
875 {0x66,
876 0x66,
877 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
878 /* data16
879 data16
880 data16
881 nopw %cs:0L(%[re]ax,%[re]ax,1) */
882 static const char alt_long_13[] =
883 {0x66,
884 0x66,
885 0x66,
886 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
887 /* data16
888 data16
889 data16
890 data16
891 nopw %cs:0L(%[re]ax,%[re]ax,1) */
892 static const char alt_long_14[] =
893 {0x66,
894 0x66,
895 0x66,
896 0x66,
897 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
898 /* data16
899 data16
900 data16
901 data16
902 data16
903 nopw %cs:0L(%[re]ax,%[re]ax,1) */
904 static const char alt_long_15[] =
905 {0x66,
906 0x66,
907 0x66,
908 0x66,
909 0x66,
910 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
911 /* nopl 0(%[re]ax,%[re]ax,1)
912 nopw 0(%[re]ax,%[re]ax,1) */
913 static const char alt_short_11[] =
914 {0x0f,0x1f,0x44,0x00,0x00,
915 0x66,0x0f,0x1f,0x44,0x00,0x00};
916 /* nopw 0(%[re]ax,%[re]ax,1)
917 nopw 0(%[re]ax,%[re]ax,1) */
918 static const char alt_short_12[] =
919 {0x66,0x0f,0x1f,0x44,0x00,0x00,
920 0x66,0x0f,0x1f,0x44,0x00,0x00};
921 /* nopw 0(%[re]ax,%[re]ax,1)
922 nopl 0L(%[re]ax) */
923 static const char alt_short_13[] =
924 {0x66,0x0f,0x1f,0x44,0x00,0x00,
925 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
926 /* nopl 0L(%[re]ax)
927 nopl 0L(%[re]ax) */
928 static const char alt_short_14[] =
929 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
930 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
931 /* nopl 0L(%[re]ax)
932 nopl 0L(%[re]ax,%[re]ax,1) */
933 static const char alt_short_15[] =
934 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
935 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
936 static const char *const alt_short_patt[] = {
937 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
938 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
939 alt_short_14, alt_short_15
940 };
941 static const char *const alt_long_patt[] = {
942 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
943 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
944 alt_long_14, alt_long_15
945 };
252b5132 946
76bc74dc
L		 947 /* Only align for at least a positive non-zero boundary. */
948 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 949 return;
3e73aa7c 950
ccc9c027
L		 951 /* We need to decide which NOP sequence to use for 32bit and
952 64bit. When -mtune= is used:
4eed87de 953
76bc74dc
L		 954 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
955 PROCESSOR_GENERIC32, f32_patt will be used.
956 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
bd5295b2
L		 957 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
958 PROCESSOR_GENERIC64, alt_long_patt will be used.
76bc74dc
L		 959 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
960 PROCESSOR_AMDFAM10, alt_short_patt will be used.
ccc9c027 961
76bc74dc
L		 962 When -mtune= isn't used, alt_long_patt will be used if
963 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
964 be used.
ccc9c027
L		 965
966 When -march= or .arch is used, we can't use anything beyond
967 cpu_arch_isa_flags. */
968
969 if (flag_code == CODE_16BIT)
970 {
ccc9c027 971 if (count > 8)
33fef721 972 {
76bc74dc
L		 973 memcpy (fragP->fr_literal + fragP->fr_fix,
974 jump_31, count);
975 /* Adjust jump offset. */
976 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 977 }
76bc74dc
L		 978 else
979 memcpy (fragP->fr_literal + fragP->fr_fix,
980 f16_patt[count - 1], count);
252b5132 981 }
33fef721 982 else
ccc9c027
L		 983 {
984 const char *const *patt = NULL;
985
fbf3f584 986 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 987 {
988 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
989 switch (cpu_arch_tune)
990 {
991 case PROCESSOR_UNKNOWN:
992 /* We use cpu_arch_isa_flags to check if we SHOULD
993 optimize for Cpu686. */
fbf3f584 994 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
76bc74dc 995 patt = alt_long_patt;
ccc9c027
L		 996 else
997 patt = f32_patt;
998 break;
ccc9c027
L		 999 case PROCESSOR_PENTIUMPRO:
1000 case PROCESSOR_PENTIUM4:
1001 case PROCESSOR_NOCONA:
ef05d495 1002 case PROCESSOR_CORE:
76bc74dc 1003 case PROCESSOR_CORE2:
bd5295b2 1004 case PROCESSOR_COREI7:
3632d14b 1005 case PROCESSOR_L1OM:
76bc74dc
L		 1006 case PROCESSOR_GENERIC64:
1007 patt = alt_long_patt;
1008 break;
ccc9c027
L		 1009 case PROCESSOR_K6:
1010 case PROCESSOR_ATHLON:
1011 case PROCESSOR_K8:
4eed87de 1012 case PROCESSOR_AMDFAM10:
ccc9c027
L		 1013 patt = alt_short_patt;
1014 break;
76bc74dc 1015 case PROCESSOR_I386:
ccc9c027
L		 1016 case PROCESSOR_I486:
1017 case PROCESSOR_PENTIUM:
1018 case PROCESSOR_GENERIC32:
1019 patt = f32_patt;
1020 break;
4eed87de 1021 }
ccc9c027
L		 1022 }
1023 else
1024 {
fbf3f584 1025 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1026 {
1027 case PROCESSOR_UNKNOWN:
e6a14101 1028 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1029 PROCESSOR_UNKNOWN. */
1030 abort ();
1031 break;
1032
76bc74dc 1033 case PROCESSOR_I386:
ccc9c027
L		 1034 case PROCESSOR_I486:
1035 case PROCESSOR_PENTIUM:
ccc9c027
L		 1036 case PROCESSOR_K6:
1037 case PROCESSOR_ATHLON:
1038 case PROCESSOR_K8:
4eed87de 1039 case PROCESSOR_AMDFAM10:
ccc9c027
L		 1040 case PROCESSOR_GENERIC32:
1041 /* We use cpu_arch_isa_flags to check if we CAN optimize
1042 for Cpu686. */
fbf3f584 1043 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
ccc9c027
L		 1044 patt = alt_short_patt;
1045 else
1046 patt = f32_patt;
1047 break;
76bc74dc
L		 1048 case PROCESSOR_PENTIUMPRO:
1049 case PROCESSOR_PENTIUM4:
1050 case PROCESSOR_NOCONA:
1051 case PROCESSOR_CORE:
ef05d495 1052 case PROCESSOR_CORE2:
bd5295b2 1053 case PROCESSOR_COREI7:
3632d14b 1054 case PROCESSOR_L1OM:
fbf3f584 1055 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
ccc9c027
L		 1056 patt = alt_long_patt;
1057 else
1058 patt = f32_patt;
1059 break;
1060 case PROCESSOR_GENERIC64:
76bc74dc 1061 patt = alt_long_patt;
ccc9c027 1062 break;
4eed87de 1063 }
ccc9c027
L		 1064 }
1065
76bc74dc
L		 1066 if (patt == f32_patt)
1067 {
1068 /* If the padding is less than 15 bytes, we use the normal
1069 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1070 its offset. */
1071 int limit;
76ba9986 1072
711eedef
L		 1073 /* For 64bit, the limit is 3 bytes. */
1074 if (flag_code == CODE_64BIT
1075 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1076 limit = 3;
1077 else
1078 limit = 15;
1079 if (count < limit)
76bc74dc
L		 1080 memcpy (fragP->fr_literal + fragP->fr_fix,
1081 patt[count - 1], count);
1082 else
1083 {
1084 memcpy (fragP->fr_literal + fragP->fr_fix,
1085 jump_31, count);
1086 /* Adjust jump offset. */
1087 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1088 }
1089 }
1090 else
1091 {
1092 /* Maximum length of an instruction is 15 byte. If the
1093 padding is greater than 15 bytes and we don't use jump,
1094 we have to break it into smaller pieces. */
1095 int padding = count;
1096 while (padding > 15)
1097 {
1098 padding -= 15;
1099 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1100 patt [14], 15);
1101 }
1102
1103 if (padding)
1104 memcpy (fragP->fr_literal + fragP->fr_fix,
1105 patt [padding - 1], padding);
1106 }
ccc9c027 1107 }
33fef721 1108 fragP->fr_var = count;
252b5132
RH		 1109}
1110
c6fb90c8 1111static INLINE int
0dfbf9d7 1112operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1113{
0dfbf9d7 1114 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1115 {
1116 case 3:
0dfbf9d7 1117 if (x->array[2])
c6fb90c8
L		 1118 return 0;
1119 case 2:
0dfbf9d7 1120 if (x->array[1])
c6fb90c8
L		 1121 return 0;
1122 case 1:
0dfbf9d7 1123 return !x->array[0];
c6fb90c8
L		 1124 default:
1125 abort ();
1126 }
40fb9820
L		 1127}
1128
c6fb90c8 1129static INLINE void
0dfbf9d7 1130operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1131{
0dfbf9d7 1132 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1133 {
1134 case 3:
0dfbf9d7 1135 x->array[2] = v;
c6fb90c8 1136 case 2:
0dfbf9d7 1137 x->array[1] = v;
c6fb90c8 1138 case 1:
0dfbf9d7 1139 x->array[0] = v;
c6fb90c8
L		 1140 break;
1141 default:
1142 abort ();
1143 }
1144}
40fb9820 1145
c6fb90c8 1146static INLINE int
0dfbf9d7
L		 1147operand_type_equal (const union i386_operand_type *x,
1148 const union i386_operand_type *y)
c6fb90c8 1149{
0dfbf9d7 1150 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1151 {
1152 case 3:
0dfbf9d7 1153 if (x->array[2] != y->array[2])
c6fb90c8
L		 1154 return 0;
1155 case 2:
0dfbf9d7 1156 if (x->array[1] != y->array[1])
c6fb90c8
L		 1157 return 0;
1158 case 1:
0dfbf9d7 1159 return x->array[0] == y->array[0];
c6fb90c8
L		 1160 break;
1161 default:
1162 abort ();
1163 }
1164}
40fb9820 1165
0dfbf9d7
L		 1166static INLINE int
1167cpu_flags_all_zero (const union i386_cpu_flags *x)
1168{
1169 switch (ARRAY_SIZE(x->array))
1170 {
1171 case 3:
1172 if (x->array[2])
1173 return 0;
1174 case 2:
1175 if (x->array[1])
1176 return 0;
1177 case 1:
1178 return !x->array[0];
1179 default:
1180 abort ();
1181 }
1182}
1183
1184static INLINE void
1185cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1186{
1187 switch (ARRAY_SIZE(x->array))
1188 {
1189 case 3:
1190 x->array[2] = v;
1191 case 2:
1192 x->array[1] = v;
1193 case 1:
1194 x->array[0] = v;
1195 break;
1196 default:
1197 abort ();
1198 }
1199}
1200
1201static INLINE int
1202cpu_flags_equal (const union i386_cpu_flags *x,
1203 const union i386_cpu_flags *y)
1204{
1205 switch (ARRAY_SIZE(x->array))
1206 {
1207 case 3:
1208 if (x->array[2] != y->array[2])
1209 return 0;
1210 case 2:
1211 if (x->array[1] != y->array[1])
1212 return 0;
1213 case 1:
1214 return x->array[0] == y->array[0];
1215 break;
1216 default:
1217 abort ();
1218 }
1219}
c6fb90c8
L		 1220
1221static INLINE int
1222cpu_flags_check_cpu64 (i386_cpu_flags f)
1223{
1224 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1225 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1226}
1227
c6fb90c8
L		 1228static INLINE i386_cpu_flags
1229cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1230{
c6fb90c8
L		 1231 switch (ARRAY_SIZE (x.array))
1232 {
1233 case 3:
1234 x.array [2] &= y.array [2];
1235 case 2:
1236 x.array [1] &= y.array [1];
1237 case 1:
1238 x.array [0] &= y.array [0];
1239 break;
1240 default:
1241 abort ();
1242 }
1243 return x;
1244}
40fb9820 1245
c6fb90c8
L		 1246static INLINE i386_cpu_flags
1247cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1248{
c6fb90c8 1249 switch (ARRAY_SIZE (x.array))
40fb9820 1250 {
c6fb90c8
L		 1251 case 3:
1252 x.array [2] |= y.array [2];
1253 case 2:
1254 x.array [1] |= y.array [1];
1255 case 1:
1256 x.array [0] |= y.array [0];
40fb9820
L		 1257 break;
1258 default:
1259 abort ();
1260 }
40fb9820
L		 1261 return x;
1262}
1263
309d3373
JB		 1264static INLINE i386_cpu_flags
1265cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1266{
1267 switch (ARRAY_SIZE (x.array))
1268 {
1269 case 3:
1270 x.array [2] &= ~y.array [2];
1271 case 2:
1272 x.array [1] &= ~y.array [1];
1273 case 1:
1274 x.array [0] &= ~y.array [0];
1275 break;
1276 default:
1277 abort ();
1278 }
1279 return x;
1280}
1281
c0f3af97
L		 1282#define CPU_FLAGS_ARCH_MATCH 0x1
1283#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1284#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1285#define CPU_FLAGS_PCLMUL_MATCH 0x8
1286#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1287
a5ff0eb2 1288#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1289 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1290 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1291#define CPU_FLAGS_PERFECT_MATCH \
1292 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1293
1294/* Return CPU flags match bits. */
3629bb00 1295
40fb9820 1296static int
d3ce72d0 1297cpu_flags_match (const insn_template *t)
40fb9820 1298{
c0f3af97
L		 1299 i386_cpu_flags x = t->cpu_flags;
1300 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1301
1302 x.bitfield.cpu64 = 0;
1303 x.bitfield.cpuno64 = 0;
1304
0dfbf9d7 1305 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1306 {
1307 /* This instruction is available on all archs. */
1308 match |= CPU_FLAGS_32BIT_MATCH;
1309 }
3629bb00
L		 1310 else
1311 {
c0f3af97 1312 /* This instruction is available only on some archs. */
3629bb00
L		 1313 i386_cpu_flags cpu = cpu_arch_flags;
1314
1315 cpu.bitfield.cpu64 = 0;
1316 cpu.bitfield.cpuno64 = 0;
1317 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1318 if (!cpu_flags_all_zero (&cpu))
1319 {
a5ff0eb2
L		 1320 if (x.bitfield.cpuavx)
1321 {
ce2f5b3c 1322 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1323 if (cpu.bitfield.cpuavx)
1324 {
1325 /* Check SSE2AVX. */
1326 if (!t->opcode_modifier.sse2avx|| sse2avx)
1327 {
1328 match |= (CPU_FLAGS_ARCH_MATCH
1329 | CPU_FLAGS_AVX_MATCH);
1330 /* Check AES. */
1331 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1332 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1333 /* Check PCLMUL. */
1334 if (!x.bitfield.cpupclmul
1335 || cpu.bitfield.cpupclmul)
1336 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1337 }
1338 }
1339 else
1340 match |= CPU_FLAGS_ARCH_MATCH;
1341 }
1342 else
c0f3af97
L		 1343 match |= CPU_FLAGS_32BIT_MATCH;
1344 }
3629bb00 1345 }
c0f3af97 1346 return match;
40fb9820
L		 1347}
1348
c6fb90c8
L		 1349static INLINE i386_operand_type
1350operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1351{
c6fb90c8
L		 1352 switch (ARRAY_SIZE (x.array))
1353 {
1354 case 3:
1355 x.array [2] &= y.array [2];
1356 case 2:
1357 x.array [1] &= y.array [1];
1358 case 1:
1359 x.array [0] &= y.array [0];
1360 break;
1361 default:
1362 abort ();
1363 }
1364 return x;
40fb9820
L		 1365}
1366
c6fb90c8
L		 1367static INLINE i386_operand_type
1368operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1369{
c6fb90c8 1370 switch (ARRAY_SIZE (x.array))
40fb9820 1371 {
c6fb90c8
L		 1372 case 3:
1373 x.array [2] |= y.array [2];
1374 case 2:
1375 x.array [1] |= y.array [1];
1376 case 1:
1377 x.array [0] |= y.array [0];
40fb9820
L		 1378 break;
1379 default:
1380 abort ();
1381 }
c6fb90c8
L		 1382 return x;
1383}
40fb9820 1384
c6fb90c8
L		 1385static INLINE i386_operand_type
1386operand_type_xor (i386_operand_type x, i386_operand_type y)
1387{
1388 switch (ARRAY_SIZE (x.array))
1389 {
1390 case 3:
1391 x.array [2] ^= y.array [2];
1392 case 2:
1393 x.array [1] ^= y.array [1];
1394 case 1:
1395 x.array [0] ^= y.array [0];
1396 break;
1397 default:
1398 abort ();
1399 }
40fb9820
L		 1400 return x;
1401}
1402
1403static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1404static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1405static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1406static const i386_operand_type inoutportreg
1407 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1408static const i386_operand_type reg16_inoutportreg
1409 = OPERAND_TYPE_REG16_INOUTPORTREG;
1410static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1411static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1412static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1413static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1414static const i386_operand_type anydisp
1415 = OPERAND_TYPE_ANYDISP;
40fb9820 1416static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1417static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
40fb9820
L		 1418static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1419static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1420static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1421static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1422static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1423static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1424static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1425static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1426static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1427
1428enum operand_type
1429{
1430 reg,
40fb9820
L		 1431 imm,
1432 disp,
1433 anymem
1434};
1435
c6fb90c8 1436static INLINE int
40fb9820
L		 1437operand_type_check (i386_operand_type t, enum operand_type c)
1438{
1439 switch (c)
1440 {
1441 case reg:
1442 return (t.bitfield.reg8
1443 || t.bitfield.reg16
1444 || t.bitfield.reg32
1445 || t.bitfield.reg64);
1446
40fb9820
L		 1447 case imm:
1448 return (t.bitfield.imm8
1449 || t.bitfield.imm8s
1450 || t.bitfield.imm16
1451 || t.bitfield.imm32
1452 || t.bitfield.imm32s
1453 || t.bitfield.imm64);
1454
1455 case disp:
1456 return (t.bitfield.disp8
1457 || t.bitfield.disp16
1458 || t.bitfield.disp32
1459 || t.bitfield.disp32s
1460 || t.bitfield.disp64);
1461
1462 case anymem:
1463 return (t.bitfield.disp8
1464 || t.bitfield.disp16
1465 || t.bitfield.disp32
1466 || t.bitfield.disp32s
1467 || t.bitfield.disp64
1468 || t.bitfield.baseindex);
1469
1470 default:
1471 abort ();
1472 }
2cfe26b6
AM		 1473
1474 return 0;
40fb9820
L		 1475}
1476
5c07affc
L		 1477/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1478 operand J for instruction template T. */
1479
1480static INLINE int
d3ce72d0 1481match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1482{
1483 return !((i.types[j].bitfield.byte
1484 && !t->operand_types[j].bitfield.byte)
1485 || (i.types[j].bitfield.word
1486 && !t->operand_types[j].bitfield.word)
1487 || (i.types[j].bitfield.dword
1488 && !t->operand_types[j].bitfield.dword)
1489 || (i.types[j].bitfield.qword
1490 && !t->operand_types[j].bitfield.qword));
1491}
1492
1493/* Return 1 if there is no conflict in any size on operand J for
1494 instruction template T. */
1495
1496static INLINE int
d3ce72d0 1497match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1498{
1499 return (match_reg_size (t, j)
1500 && !((i.types[j].bitfield.unspecified
1501 && !t->operand_types[j].bitfield.unspecified)
1502 || (i.types[j].bitfield.fword
1503 && !t->operand_types[j].bitfield.fword)
1504 || (i.types[j].bitfield.tbyte
1505 && !t->operand_types[j].bitfield.tbyte)
1506 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1507 && !t->operand_types[j].bitfield.xmmword)
1508 || (i.types[j].bitfield.ymmword
1509 && !t->operand_types[j].bitfield.ymmword)));
5c07affc
L		 1510}
1511
1512/* Return 1 if there is no size conflict on any operands for
1513 instruction template T. */
1514
1515static INLINE int
d3ce72d0 1516operand_size_match (const insn_template *t)
5c07affc
L		 1517{
1518 unsigned int j;
1519 int match = 1;
1520
1521 /* Don't check jump instructions. */
1522 if (t->opcode_modifier.jump
1523 || t->opcode_modifier.jumpbyte
1524 || t->opcode_modifier.jumpdword
1525 || t->opcode_modifier.jumpintersegment)
1526 return match;
1527
1528 /* Check memory and accumulator operand size. */
1529 for (j = 0; j < i.operands; j++)
1530 {
1531 if (t->operand_types[j].bitfield.anysize)
1532 continue;
1533
1534 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1535 {
1536 match = 0;
1537 break;
1538 }
1539
1540 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1541 {
1542 match = 0;
1543 break;
1544 }
1545 }
1546
1547 if (match
1548 || (!t->opcode_modifier.d && !t->opcode_modifier.floatd))
1549 return match;
1550
1551 /* Check reverse. */
9c2799c2 1552 gas_assert (i.operands == 2);
5c07affc
L		 1553
1554 match = 1;
1555 for (j = 0; j < 2; j++)
1556 {
1557 if (t->operand_types[j].bitfield.acc
1558 && !match_reg_size (t, j ? 0 : 1))
1559 {
1560 match = 0;
1561 break;
1562 }
1563
1564 if (i.types[j].bitfield.mem
1565 && !match_mem_size (t, j ? 0 : 1))
1566 {
1567 match = 0;
1568 break;
1569 }
1570 }
1571
1572 return match;
1573}
1574
c6fb90c8 1575static INLINE int
40fb9820
L		 1576operand_type_match (i386_operand_type overlap,
1577 i386_operand_type given)
1578{
1579 i386_operand_type temp = overlap;
1580
1581 temp.bitfield.jumpabsolute = 0;
7d5e4556 1582 temp.bitfield.unspecified = 0;
5c07affc
L		 1583 temp.bitfield.byte = 0;
1584 temp.bitfield.word = 0;
1585 temp.bitfield.dword = 0;
1586 temp.bitfield.fword = 0;
1587 temp.bitfield.qword = 0;
1588 temp.bitfield.tbyte = 0;
1589 temp.bitfield.xmmword = 0;
c0f3af97 1590 temp.bitfield.ymmword = 0;
0dfbf9d7 1591 if (operand_type_all_zero (&temp))
40fb9820
L		 1592 return 0;
1593
1594 return (given.bitfield.baseindex == overlap.bitfield.baseindex
1595 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1596}
1597
7d5e4556 1598/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1599 unless the expected operand type register overlap is null.
1600 Note that Acc in a template matches every size of reg. */
1601
c6fb90c8 1602static INLINE int
40fb9820
L		 1603operand_type_register_match (i386_operand_type m0,
1604 i386_operand_type g0,
1605 i386_operand_type t0,
1606 i386_operand_type m1,
1607 i386_operand_type g1,
1608 i386_operand_type t1)
1609{
1610 if (!operand_type_check (g0, reg))
1611 return 1;
1612
1613 if (!operand_type_check (g1, reg))
1614 return 1;
1615
1616 if (g0.bitfield.reg8 == g1.bitfield.reg8
1617 && g0.bitfield.reg16 == g1.bitfield.reg16
1618 && g0.bitfield.reg32 == g1.bitfield.reg32
1619 && g0.bitfield.reg64 == g1.bitfield.reg64)
1620 return 1;
1621
1622 if (m0.bitfield.acc)
1623 {
1624 t0.bitfield.reg8 = 1;
1625 t0.bitfield.reg16 = 1;
1626 t0.bitfield.reg32 = 1;
1627 t0.bitfield.reg64 = 1;
1628 }
1629
1630 if (m1.bitfield.acc)
1631 {
1632 t1.bitfield.reg8 = 1;
1633 t1.bitfield.reg16 = 1;
1634 t1.bitfield.reg32 = 1;
1635 t1.bitfield.reg64 = 1;
1636 }
1637
1638 return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1639 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1640 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1641 && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1642}
1643
252b5132 1644static INLINE unsigned int
40fb9820 1645mode_from_disp_size (i386_operand_type t)
252b5132 1646{
40fb9820
L		 1647 if (t.bitfield.disp8)
1648 return 1;
1649 else if (t.bitfield.disp16
1650 || t.bitfield.disp32
1651 || t.bitfield.disp32s)
1652 return 2;
1653 else
1654 return 0;
252b5132
RH		 1655}
1656
1657static INLINE int
e3bb37b5 1658fits_in_signed_byte (offsetT num)
252b5132
RH		 1659{
1660 return (num >= -128) && (num <= 127);
47926f60 1661}
252b5132
RH		 1662
1663static INLINE int
e3bb37b5 1664fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1665{
1666 return (num & 0xff) == num;
47926f60 1667}
252b5132
RH		 1668
1669static INLINE int
e3bb37b5 1670fits_in_unsigned_word (offsetT num)
252b5132
RH		 1671{
1672 return (num & 0xffff) == num;
47926f60 1673}
252b5132
RH		 1674
1675static INLINE int
e3bb37b5 1676fits_in_signed_word (offsetT num)
252b5132
RH		 1677{
1678 return (-32768 <= num) && (num <= 32767);
47926f60 1679}
2a962e6d 1680
3e73aa7c 1681static INLINE int
e3bb37b5 1682fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1683{
1684#ifndef BFD64
1685 return 1;
1686#else
1687 return (!(((offsetT) -1 << 31) & num)
1688 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1689#endif
1690} /* fits_in_signed_long() */
2a962e6d 1691
3e73aa7c 1692static INLINE int
e3bb37b5 1693fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1694{
1695#ifndef BFD64
1696 return 1;
1697#else
1698 return (num & (((offsetT) 2 << 31) - 1)) == num;
1699#endif
1700} /* fits_in_unsigned_long() */
252b5132 1701
40fb9820 1702static i386_operand_type
e3bb37b5 1703smallest_imm_type (offsetT num)
252b5132 1704{
40fb9820 1705 i386_operand_type t;
7ab9ffdd 1706
0dfbf9d7 1707 operand_type_set (&t, 0);
40fb9820
L		 1708 t.bitfield.imm64 = 1;
1709
1710 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1711 {
1712 /* This code is disabled on the 486 because all the Imm1 forms
1713 in the opcode table are slower on the i486. They're the
1714 versions with the implicitly specified single-position
1715 displacement, which has another syntax if you really want to
1716 use that form. */
40fb9820
L		 1717 t.bitfield.imm1 = 1;
1718 t.bitfield.imm8 = 1;
1719 t.bitfield.imm8s = 1;
1720 t.bitfield.imm16 = 1;
1721 t.bitfield.imm32 = 1;
1722 t.bitfield.imm32s = 1;
1723 }
1724 else if (fits_in_signed_byte (num))
1725 {
1726 t.bitfield.imm8 = 1;
1727 t.bitfield.imm8s = 1;
1728 t.bitfield.imm16 = 1;
1729 t.bitfield.imm32 = 1;
1730 t.bitfield.imm32s = 1;
1731 }
1732 else if (fits_in_unsigned_byte (num))
1733 {
1734 t.bitfield.imm8 = 1;
1735 t.bitfield.imm16 = 1;
1736 t.bitfield.imm32 = 1;
1737 t.bitfield.imm32s = 1;
1738 }
1739 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1740 {
1741 t.bitfield.imm16 = 1;
1742 t.bitfield.imm32 = 1;
1743 t.bitfield.imm32s = 1;
1744 }
1745 else if (fits_in_signed_long (num))
1746 {
1747 t.bitfield.imm32 = 1;
1748 t.bitfield.imm32s = 1;
1749 }
1750 else if (fits_in_unsigned_long (num))
1751 t.bitfield.imm32 = 1;
1752
1753 return t;
47926f60 1754}
252b5132 1755
847f7ad4 1756static offsetT
e3bb37b5 1757offset_in_range (offsetT val, int size)
847f7ad4 1758{
508866be 1759 addressT mask;
ba2adb93 1760
847f7ad4
AM		 1761 switch (size)
1762 {
508866be
L		 1763 case 1: mask = ((addressT) 1 << 8) - 1; break;
1764 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1765 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1766#ifdef BFD64
1767 case 8: mask = ((addressT) 2 << 63) - 1; break;
1768#endif
47926f60 1769 default: abort ();
847f7ad4
AM		 1770 }
1771
9de868bf
L		 1772#ifdef BFD64
1773 /* If BFD64, sign extend val for 32bit address mode. */
1774 if (flag_code != CODE_64BIT
1775 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 1776 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1777 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 1778#endif
ba2adb93 1779
47926f60 1780 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1781 {
1782 char buf1[40], buf2[40];
1783
1784 sprint_value (buf1, val);
1785 sprint_value (buf2, val & mask);
1786 as_warn (_("%s shortened to %s"), buf1, buf2);
1787 }
1788 return val & mask;
1789}
1790
c32fa91d
L		 1791enum PREFIX_GROUP
1792{
1793 PREFIX_EXIST = 0,
1794 PREFIX_LOCK,
1795 PREFIX_REP,
1796 PREFIX_OTHER
1797};
1798
1799/* Returns
1800 a. PREFIX_EXIST if attempting to add a prefix where one from the
1801 same class already exists.
1802 b. PREFIX_LOCK if lock prefix is added.
1803 c. PREFIX_REP if rep/repne prefix is added.
1804 d. PREFIX_OTHER if other prefix is added.
1805 */
1806
1807static enum PREFIX_GROUP
e3bb37b5 1808add_prefix (unsigned int prefix)
252b5132 1809{
c32fa91d 1810 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 1811 unsigned int q;
252b5132 1812
29b0f896
AM		 1813 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1814 && flag_code == CODE_64BIT)
b1905489 1815 {
161a04f6
L		 1816 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1817 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1818 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 1819 ret = PREFIX_EXIST;
b1905489
JB		 1820 q = REX_PREFIX;
1821 }
3e73aa7c 1822 else
b1905489
JB		 1823 {
1824 switch (prefix)
1825 {
1826 default:
1827 abort ();
1828
1829 case CS_PREFIX_OPCODE:
1830 case DS_PREFIX_OPCODE:
1831 case ES_PREFIX_OPCODE:
1832 case FS_PREFIX_OPCODE:
1833 case GS_PREFIX_OPCODE:
1834 case SS_PREFIX_OPCODE:
1835 q = SEG_PREFIX;
1836 break;
1837
1838 case REPNE_PREFIX_OPCODE:
1839 case REPE_PREFIX_OPCODE:
c32fa91d
L		 1840 q = REP_PREFIX;
1841 ret = PREFIX_REP;
1842 break;
1843
b1905489 1844 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 1845 q = LOCK_PREFIX;
1846 ret = PREFIX_LOCK;
b1905489
JB		 1847 break;
1848
1849 case FWAIT_OPCODE:
1850 q = WAIT_PREFIX;
1851 break;
1852
1853 case ADDR_PREFIX_OPCODE:
1854 q = ADDR_PREFIX;
1855 break;
1856
1857 case DATA_PREFIX_OPCODE:
1858 q = DATA_PREFIX;
1859 break;
1860 }
1861 if (i.prefix[q] != 0)
c32fa91d 1862 ret = PREFIX_EXIST;
b1905489 1863 }
252b5132 1864
b1905489 1865 if (ret)
252b5132 1866 {
b1905489
JB		 1867 if (!i.prefix[q])
1868 ++i.prefixes;
1869 i.prefix[q] |= prefix;
252b5132 1870 }
b1905489
JB		 1871 else
1872 as_bad (_("same type of prefix used twice"));
252b5132 1873
252b5132
RH		 1874 return ret;
1875}
1876
1877static void
e3bb37b5 1878set_code_flag (int value)
eecb386c 1879{
1e9cc1c2 1880 flag_code = (enum flag_code) value;
40fb9820
L		 1881 if (flag_code == CODE_64BIT)
1882 {
1883 cpu_arch_flags.bitfield.cpu64 = 1;
1884 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 1885 }
1886 else
1887 {
1888 cpu_arch_flags.bitfield.cpu64 = 0;
1889 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 1890 }
1891 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c
JH		 1892 {
1893 as_bad (_("64bit mode not supported on this CPU."));
1894 }
40fb9820 1895 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c
JH		 1896 {
1897 as_bad (_("32bit mode not supported on this CPU."));
1898 }
eecb386c
AM		 1899 stackop_size = '\0';
1900}
1901
1902static void
e3bb37b5 1903set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1904{
1e9cc1c2 1905 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 1906 if (flag_code != CODE_16BIT)
1907 abort ();
1908 cpu_arch_flags.bitfield.cpu64 = 0;
1909 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 1910 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1911}
1912
1913static void
e3bb37b5 1914set_intel_syntax (int syntax_flag)
252b5132
RH		 1915{
1916 /* Find out if register prefixing is specified. */
1917 int ask_naked_reg = 0;
1918
1919 SKIP_WHITESPACE ();
29b0f896 1920 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1921 {
1922 char *string = input_line_pointer;
1923 int e = get_symbol_end ();
1924
47926f60 1925 if (strcmp (string, "prefix") == 0)
252b5132 1926 ask_naked_reg = 1;
47926f60 1927 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1928 ask_naked_reg = -1;
1929 else
d0b47220 1930 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1931 *input_line_pointer = e;
1932 }
1933 demand_empty_rest_of_line ();
c3332e24 1934
252b5132
RH		 1935 intel_syntax = syntax_flag;
1936
1937 if (ask_naked_reg == 0)
f86103b7
AM		 1938 allow_naked_reg = (intel_syntax
1939 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1940 else
1941 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 1942
ee86248c 1943 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 1944
e4a3b5a4 1945 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 1946 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 1947 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 1948}
1949
1efbbeb4
L		 1950static void
1951set_intel_mnemonic (int mnemonic_flag)
1952{
e1d4d893 1953 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 1954}
1955
db51cc60
L		 1956static void
1957set_allow_index_reg (int flag)
1958{
1959 allow_index_reg = flag;
1960}
1961
cb19c032
L		 1962static void
1963set_sse_check (int dummy ATTRIBUTE_UNUSED)
1964{
1965 SKIP_WHITESPACE ();
1966
1967 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1968 {
1969 char *string = input_line_pointer;
1970 int e = get_symbol_end ();
1971
1972 if (strcmp (string, "none") == 0)
1973 sse_check = sse_check_none;
1974 else if (strcmp (string, "warning") == 0)
1975 sse_check = sse_check_warning;
1976 else if (strcmp (string, "error") == 0)
1977 sse_check = sse_check_error;
1978 else
1979 as_bad (_("bad argument to sse_check directive."));
1980 *input_line_pointer = e;
1981 }
1982 else
1983 as_bad (_("missing argument for sse_check directive"));
1984
1985 demand_empty_rest_of_line ();
1986}
1987
8a9036a4
L		 1988static void
1989check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 1990 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 1991{
1992#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1993 static const char *arch;
1994
1995 /* Intel LIOM is only supported on ELF. */
1996 if (!IS_ELF)
1997 return;
1998
1999 if (!arch)
2000 {
2001 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2002 use default_arch. */
2003 arch = cpu_arch_name;
2004 if (!arch)
2005 arch = default_arch;
2006 }
2007
3632d14b 2008 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2009 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2010 || new_flag.bitfield.cpul1om)
8a9036a4 2011 return;
76ba9986 2012
8a9036a4
L		 2013 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2014#endif
2015}
2016
e413e4e9 2017static void
e3bb37b5 2018set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2019{
47926f60 2020 SKIP_WHITESPACE ();
e413e4e9 2021
29b0f896 2022 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 2023 {
2024 char *string = input_line_pointer;
2025 int e = get_symbol_end ();
91d6fa6a 2026 unsigned int j;
40fb9820 2027 i386_cpu_flags flags;
e413e4e9 2028
91d6fa6a 2029 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2030 {
91d6fa6a 2031 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2032 {
91d6fa6a 2033 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2034
5c6af06e
JB		 2035 if (*string != '.')
2036 {
91d6fa6a 2037 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2038 cpu_sub_arch_name = NULL;
91d6fa6a 2039 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2040 if (flag_code == CODE_64BIT)
2041 {
2042 cpu_arch_flags.bitfield.cpu64 = 1;
2043 cpu_arch_flags.bitfield.cpuno64 = 0;
2044 }
2045 else
2046 {
2047 cpu_arch_flags.bitfield.cpu64 = 0;
2048 cpu_arch_flags.bitfield.cpuno64 = 1;
2049 }
91d6fa6a
NC		 2050 cpu_arch_isa = cpu_arch[j].type;
2051 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2052 if (!cpu_arch_tune_set)
2053 {
2054 cpu_arch_tune = cpu_arch_isa;
2055 cpu_arch_tune_flags = cpu_arch_isa_flags;
2056 }
5c6af06e
JB		 2057 break;
2058 }
40fb9820 2059
309d3373
JB		 2060 if (strncmp (string + 1, "no", 2))
2061 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 2062 cpu_arch[j].flags);
309d3373
JB		 2063 else
2064 flags = cpu_flags_and_not (cpu_arch_flags,
91d6fa6a 2065 cpu_arch[j].flags);
0dfbf9d7 2066 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2067 {
6305a203
L		 2068 if (cpu_sub_arch_name)
2069 {
2070 char *name = cpu_sub_arch_name;
2071 cpu_sub_arch_name = concat (name,
91d6fa6a 2072 cpu_arch[j].name,
1bf57e9f 2073 (const char *) NULL);
6305a203
L		 2074 free (name);
2075 }
2076 else
91d6fa6a 2077 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2078 cpu_arch_flags = flags;
5c6af06e
JB		 2079 }
2080 *input_line_pointer = e;
2081 demand_empty_rest_of_line ();
2082 return;
e413e4e9
AM		 2083 }
2084 }
91d6fa6a 2085 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2086 as_bad (_("no such architecture: `%s'"), string);
2087
2088 *input_line_pointer = e;
2089 }
2090 else
2091 as_bad (_("missing cpu architecture"));
2092
fddf5b5b
AM		 2093 no_cond_jump_promotion = 0;
2094 if (*input_line_pointer == ','
29b0f896 2095 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 2096 {
2097 char *string = ++input_line_pointer;
2098 int e = get_symbol_end ();
2099
2100 if (strcmp (string, "nojumps") == 0)
2101 no_cond_jump_promotion = 1;
2102 else if (strcmp (string, "jumps") == 0)
2103 ;
2104 else
2105 as_bad (_("no such architecture modifier: `%s'"), string);
2106
2107 *input_line_pointer = e;
2108 }
2109
e413e4e9
AM		 2110 demand_empty_rest_of_line ();
2111}
2112
8a9036a4
L		 2113enum bfd_architecture
2114i386_arch (void)
2115{
3632d14b 2116 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2117 {
2118 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2119 || flag_code != CODE_64BIT)
2120 as_fatal (_("Intel L1OM is 64bit ELF only"));
2121 return bfd_arch_l1om;
2122 }
2123 else
2124 return bfd_arch_i386;
2125}
2126
b9d79e03
JH		 2127unsigned long
2128i386_mach ()
2129{
2130 if (!strcmp (default_arch, "x86_64"))
8a9036a4 2131 {
3632d14b 2132 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2133 {
2134 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2135 as_fatal (_("Intel L1OM is 64bit ELF only"));
2136 return bfd_mach_l1om;
2137 }
2138 else
2139 return bfd_mach_x86_64;
2140 }
b9d79e03
JH		 2141 else if (!strcmp (default_arch, "i386"))
2142 return bfd_mach_i386_i386;
2143 else
2144 as_fatal (_("Unknown architecture"));
2145}
b9d79e03 2146\f
252b5132
RH		 2147void
2148md_begin ()
2149{
2150 const char *hash_err;
2151
47926f60 2152 /* Initialize op_hash hash table. */
252b5132
RH		 2153 op_hash = hash_new ();
2154
2155 {
d3ce72d0 2156 const insn_template *optab;
29b0f896 2157 templates *core_optab;
252b5132 2158
47926f60
KH		 2159 /* Setup for loop. */
2160 optab = i386_optab;
252b5132
RH		 2161 core_optab = (templates *) xmalloc (sizeof (templates));
2162 core_optab->start = optab;
2163
2164 while (1)
2165 {
2166 ++optab;
2167 if (optab->name == NULL
2168 || strcmp (optab->name, (optab - 1)->name) != 0)
2169 {
2170 /* different name --> ship out current template list;
47926f60 2171 add to hash table; & begin anew. */
252b5132
RH		 2172 core_optab->end = optab;
2173 hash_err = hash_insert (op_hash,
2174 (optab - 1)->name,
5a49b8ac 2175 (void *) core_optab);
252b5132
RH		 2176 if (hash_err)
2177 {
252b5132
RH		 2178 as_fatal (_("Internal Error: Can't hash %s: %s"),
2179 (optab - 1)->name,
2180 hash_err);
2181 }
2182 if (optab->name == NULL)
2183 break;
2184 core_optab = (templates *) xmalloc (sizeof (templates));
2185 core_optab->start = optab;
2186 }
2187 }
2188 }
2189
47926f60 2190 /* Initialize reg_hash hash table. */
252b5132
RH		 2191 reg_hash = hash_new ();
2192 {
29b0f896 2193 const reg_entry *regtab;
c3fe08fa 2194 unsigned int regtab_size = i386_regtab_size;
252b5132 2195
c3fe08fa 2196 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2197 {
5a49b8ac 2198 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2199 if (hash_err)
3e73aa7c
JH		 2200 as_fatal (_("Internal Error: Can't hash %s: %s"),
2201 regtab->reg_name,
2202 hash_err);
252b5132
RH		 2203 }
2204 }
2205
47926f60 2206 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2207 {
29b0f896
AM		 2208 int c;
2209 char *p;
252b5132
RH		 2210
2211 for (c = 0; c < 256; c++)
2212 {
3882b010 2213 if (ISDIGIT (c))
252b5132
RH		 2214 {
2215 digit_chars[c] = c;
2216 mnemonic_chars[c] = c;
2217 register_chars[c] = c;
2218 operand_chars[c] = c;
2219 }
3882b010 2220 else if (ISLOWER (c))
252b5132
RH		 2221 {
2222 mnemonic_chars[c] = c;
2223 register_chars[c] = c;
2224 operand_chars[c] = c;
2225 }
3882b010 2226 else if (ISUPPER (c))
252b5132 2227 {
3882b010 2228 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2229 register_chars[c] = mnemonic_chars[c];
2230 operand_chars[c] = c;
2231 }
2232
3882b010 2233 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2234 identifier_chars[c] = c;
2235 else if (c >= 128)
2236 {
2237 identifier_chars[c] = c;
2238 operand_chars[c] = c;
2239 }
2240 }
2241
2242#ifdef LEX_AT
2243 identifier_chars['@'] = '@';
32137342
NC		 2244#endif
2245#ifdef LEX_QM
2246 identifier_chars['?'] = '?';
2247 operand_chars['?'] = '?';
252b5132 2248#endif
252b5132 2249 digit_chars['-'] = '-';
c0f3af97 2250 mnemonic_chars['_'] = '_';
791fe849 2251 mnemonic_chars['-'] = '-';
0003779b 2252 mnemonic_chars['.'] = '.';
252b5132
RH		 2253 identifier_chars['_'] = '_';
2254 identifier_chars['.'] = '.';
2255
2256 for (p = operand_special_chars; *p != '\0'; p++)
2257 operand_chars[(unsigned char) *p] = *p;
2258 }
2259
2260#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2261 if (IS_ELF)
252b5132
RH		 2262 {
2263 record_alignment (text_section, 2);
2264 record_alignment (data_section, 2);
2265 record_alignment (bss_section, 2);
2266 }
2267#endif
a4447b93
RH		 2268
2269 if (flag_code == CODE_64BIT)
2270 {
2271 x86_dwarf2_return_column = 16;
2272 x86_cie_data_alignment = -8;
2273 }
2274 else
2275 {
2276 x86_dwarf2_return_column = 8;
2277 x86_cie_data_alignment = -4;
2278 }
252b5132
RH		 2279}
2280
2281void
e3bb37b5 2282i386_print_statistics (FILE *file)
252b5132
RH		 2283{
2284 hash_print_statistics (file, "i386 opcode", op_hash);
2285 hash_print_statistics (file, "i386 register", reg_hash);
2286}
2287\f
252b5132
RH		 2288#ifdef DEBUG386
2289
ce8a8b2f 2290/* Debugging routines for md_assemble. */
d3ce72d0 2291static void pte (insn_template *);
40fb9820 2292static void pt (i386_operand_type);
e3bb37b5
L		 2293static void pe (expressionS *);
2294static void ps (symbolS *);
252b5132
RH		 2295
2296static void
e3bb37b5 2297pi (char *line, i386_insn *x)
252b5132 2298{
09f131f2 2299 unsigned int i;
252b5132
RH		 2300
2301 fprintf (stdout, "%s: template ", line);
2302 pte (&x->tm);
09f131f2
JH		 2303 fprintf (stdout, " address: base %s index %s scale %x\n",
2304 x->base_reg ? x->base_reg->reg_name : "none",
2305 x->index_reg ? x->index_reg->reg_name : "none",
2306 x->log2_scale_factor);
2307 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2308 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2309 fprintf (stdout, " sib: base %x index %x scale %x\n",
2310 x->sib.base, x->sib.index, x->sib.scale);
2311 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2312 (x->rex & REX_W) != 0,
2313 (x->rex & REX_R) != 0,
2314 (x->rex & REX_X) != 0,
2315 (x->rex & REX_B) != 0);
252b5132
RH		 2316 for (i = 0; i < x->operands; i++)
2317 {
2318 fprintf (stdout, " #%d: ", i + 1);
2319 pt (x->types[i]);
2320 fprintf (stdout, "\n");
40fb9820
L		 2321 if (x->types[i].bitfield.reg8
2322 || x->types[i].bitfield.reg16
2323 || x->types[i].bitfield.reg32
2324 || x->types[i].bitfield.reg64
2325 || x->types[i].bitfield.regmmx
2326 || x->types[i].bitfield.regxmm
c0f3af97 2327 || x->types[i].bitfield.regymm
40fb9820
L		 2328 || x->types[i].bitfield.sreg2
2329 || x->types[i].bitfield.sreg3
2330 || x->types[i].bitfield.control
2331 || x->types[i].bitfield.debug
2332 || x->types[i].bitfield.test)
520dc8e8 2333 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
40fb9820 2334 if (operand_type_check (x->types[i], imm))
520dc8e8 2335 pe (x->op[i].imms);
40fb9820 2336 if (operand_type_check (x->types[i], disp))
520dc8e8 2337 pe (x->op[i].disps);
252b5132
RH		 2338 }
2339}
2340
2341static void
d3ce72d0 2342pte (insn_template *t)
252b5132 2343{
09f131f2 2344 unsigned int i;
252b5132 2345 fprintf (stdout, " %d operands ", t->operands);
47926f60 2346 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2347 if (t->extension_opcode != None)
2348 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2349 if (t->opcode_modifier.d)
252b5132 2350 fprintf (stdout, "D");
40fb9820 2351 if (t->opcode_modifier.w)
252b5132
RH		 2352 fprintf (stdout, "W");
2353 fprintf (stdout, "\n");
2354 for (i = 0; i < t->operands; i++)
2355 {
2356 fprintf (stdout, " #%d type ", i + 1);
2357 pt (t->operand_types[i]);
2358 fprintf (stdout, "\n");
2359 }
2360}
2361
2362static void
e3bb37b5 2363pe (expressionS *e)
252b5132 2364{
24eab124 2365 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2366 fprintf (stdout, " add_number %ld (%lx)\n",
2367 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2368 if (e->X_add_symbol)
2369 {
2370 fprintf (stdout, " add_symbol ");
2371 ps (e->X_add_symbol);
2372 fprintf (stdout, "\n");
2373 }
2374 if (e->X_op_symbol)
2375 {
2376 fprintf (stdout, " op_symbol ");
2377 ps (e->X_op_symbol);
2378 fprintf (stdout, "\n");
2379 }
2380}
2381
2382static void
e3bb37b5 2383ps (symbolS *s)
252b5132
RH		 2384{
2385 fprintf (stdout, "%s type %s%s",
2386 S_GET_NAME (s),
2387 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2388 segment_name (S_GET_SEGMENT (s)));
2389}
2390
7b81dfbb 2391static struct type_name
252b5132 2392 {
40fb9820
L		 2393 i386_operand_type mask;
2394 const char *name;
252b5132 2395 }
7b81dfbb 2396const type_names[] =
252b5132 2397{
40fb9820
L		 2398 { OPERAND_TYPE_REG8, "r8" },
2399 { OPERAND_TYPE_REG16, "r16" },
2400 { OPERAND_TYPE_REG32, "r32" },
2401 { OPERAND_TYPE_REG64, "r64" },
2402 { OPERAND_TYPE_IMM8, "i8" },
2403 { OPERAND_TYPE_IMM8, "i8s" },
2404 { OPERAND_TYPE_IMM16, "i16" },
2405 { OPERAND_TYPE_IMM32, "i32" },
2406 { OPERAND_TYPE_IMM32S, "i32s" },
2407 { OPERAND_TYPE_IMM64, "i64" },
2408 { OPERAND_TYPE_IMM1, "i1" },
2409 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2410 { OPERAND_TYPE_DISP8, "d8" },
2411 { OPERAND_TYPE_DISP16, "d16" },
2412 { OPERAND_TYPE_DISP32, "d32" },
2413 { OPERAND_TYPE_DISP32S, "d32s" },
2414 { OPERAND_TYPE_DISP64, "d64" },
2415 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2416 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2417 { OPERAND_TYPE_CONTROL, "control reg" },
2418 { OPERAND_TYPE_TEST, "test reg" },
2419 { OPERAND_TYPE_DEBUG, "debug reg" },
2420 { OPERAND_TYPE_FLOATREG, "FReg" },
2421 { OPERAND_TYPE_FLOATACC, "FAcc" },
2422 { OPERAND_TYPE_SREG2, "SReg2" },
2423 { OPERAND_TYPE_SREG3, "SReg3" },
2424 { OPERAND_TYPE_ACC, "Acc" },
2425 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2426 { OPERAND_TYPE_REGMMX, "rMMX" },
2427 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2428 { OPERAND_TYPE_REGYMM, "rYMM" },
40fb9820 2429 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2430};
2431
2432static void
40fb9820 2433pt (i386_operand_type t)
252b5132 2434{
40fb9820 2435 unsigned int j;
c6fb90c8 2436 i386_operand_type a;
252b5132 2437
40fb9820 2438 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2439 {
2440 a = operand_type_and (t, type_names[j].mask);
0349dc08 2441 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2442 fprintf (stdout, "%s, ", type_names[j].name);
2443 }
252b5132
RH		 2444 fflush (stdout);
2445}
2446
2447#endif /* DEBUG386 */
2448\f
252b5132 2449static bfd_reloc_code_real_type
3956db08 2450reloc (unsigned int size,
64e74474
AM		 2451 int pcrel,
2452 int sign,
2453 bfd_reloc_code_real_type other)
252b5132 2454{
47926f60 2455 if (other != NO_RELOC)
3956db08 2456 {
91d6fa6a 2457 reloc_howto_type *rel;
3956db08
JB		 2458
2459 if (size == 8)
2460 switch (other)
2461 {
64e74474
AM		 2462 case BFD_RELOC_X86_64_GOT32:
2463 return BFD_RELOC_X86_64_GOT64;
2464 break;
2465 case BFD_RELOC_X86_64_PLTOFF64:
2466 return BFD_RELOC_X86_64_PLTOFF64;
2467 break;
2468 case BFD_RELOC_X86_64_GOTPC32:
2469 other = BFD_RELOC_X86_64_GOTPC64;
2470 break;
2471 case BFD_RELOC_X86_64_GOTPCREL:
2472 other = BFD_RELOC_X86_64_GOTPCREL64;
2473 break;
2474 case BFD_RELOC_X86_64_TPOFF32:
2475 other = BFD_RELOC_X86_64_TPOFF64;
2476 break;
2477 case BFD_RELOC_X86_64_DTPOFF32:
2478 other = BFD_RELOC_X86_64_DTPOFF64;
2479 break;
2480 default:
2481 break;
3956db08 2482 }
e05278af
JB		 2483
2484 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2485 if (size == 4 && flag_code != CODE_64BIT)
2486 sign = -1;
2487
91d6fa6a
NC		 2488 rel = bfd_reloc_type_lookup (stdoutput, other);
2489 if (!rel)
3956db08 2490 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2491 else if (size != bfd_get_reloc_size (rel))
3956db08 2492 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2493 bfd_get_reloc_size (rel),
3956db08 2494 size);
91d6fa6a 2495 else if (pcrel && !rel->pc_relative)
3956db08 2496 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2497 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2498 && !sign)
91d6fa6a 2499 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2500 && sign > 0))
3956db08
JB		 2501 as_bad (_("relocated field and relocation type differ in signedness"));
2502 else
2503 return other;
2504 return NO_RELOC;
2505 }
252b5132
RH		 2506
2507 if (pcrel)
2508 {
3e73aa7c 2509 if (!sign)
3956db08 2510 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2511 switch (size)
2512 {
2513 case 1: return BFD_RELOC_8_PCREL;
2514 case 2: return BFD_RELOC_16_PCREL;
2515 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2516 case 8: return BFD_RELOC_64_PCREL;
252b5132 2517 }
3956db08 2518 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2519 }
2520 else
2521 {
3956db08 2522 if (sign > 0)
e5cb08ac 2523 switch (size)
3e73aa7c
JH		 2524 {
2525 case 4: return BFD_RELOC_X86_64_32S;
2526 }
2527 else
2528 switch (size)
2529 {
2530 case 1: return BFD_RELOC_8;
2531 case 2: return BFD_RELOC_16;
2532 case 4: return BFD_RELOC_32;
2533 case 8: return BFD_RELOC_64;
2534 }
3956db08
JB		 2535 as_bad (_("cannot do %s %u byte relocation"),
2536 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2537 }
2538
0cc9e1d3 2539 return NO_RELOC;
252b5132
RH		 2540}
2541
47926f60
KH		 2542/* Here we decide which fixups can be adjusted to make them relative to
2543 the beginning of the section instead of the symbol. Basically we need
2544 to make sure that the dynamic relocations are done correctly, so in
2545 some cases we force the original symbol to be used. */
2546
252b5132 2547int
e3bb37b5 2548tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2549{
6d249963 2550#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2551 if (!IS_ELF)
31312f95
AM		 2552 return 1;
2553
a161fe53
AM		 2554 /* Don't adjust pc-relative references to merge sections in 64-bit
2555 mode. */
2556 if (use_rela_relocations
2557 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2558 && fixP->fx_pcrel)
252b5132 2559 return 0;
31312f95 2560
8d01d9a9
AJ		 2561 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2562 and changed later by validate_fix. */
2563 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2564 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2565 return 0;
2566
ce8a8b2f 2567 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 2568 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2569 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2570 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2571 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2572 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2573 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2574 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2575 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2576 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2577 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2578 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2579 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2580 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2581 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2582 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2583 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2584 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2585 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2586 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2587 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2588 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2589 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2590 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2591 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2592 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2593 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2594 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2595 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2596 return 0;
31312f95 2597#endif
252b5132
RH		 2598 return 1;
2599}
252b5132 2600
b4cac588 2601static int
e3bb37b5 2602intel_float_operand (const char *mnemonic)
252b5132 2603{
9306ca4a
JB		 2604 /* Note that the value returned is meaningful only for opcodes with (memory)
2605 operands, hence the code here is free to improperly handle opcodes that
2606 have no operands (for better performance and smaller code). */
2607
2608 if (mnemonic[0] != 'f')
2609 return 0; /* non-math */
2610
2611 switch (mnemonic[1])
2612 {
2613 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2614 the fs segment override prefix not currently handled because no
2615 call path can make opcodes without operands get here */
2616 case 'i':
2617 return 2 /* integer op */;
2618 case 'l':
2619 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2620 return 3; /* fldcw/fldenv */
2621 break;
2622 case 'n':
2623 if (mnemonic[2] != 'o' /* fnop */)
2624 return 3; /* non-waiting control op */
2625 break;
2626 case 'r':
2627 if (mnemonic[2] == 's')
2628 return 3; /* frstor/frstpm */
2629 break;
2630 case 's':
2631 if (mnemonic[2] == 'a')
2632 return 3; /* fsave */
2633 if (mnemonic[2] == 't')
2634 {
2635 switch (mnemonic[3])
2636 {
2637 case 'c': /* fstcw */
2638 case 'd': /* fstdw */
2639 case 'e': /* fstenv */
2640 case 's': /* fsts[gw] */
2641 return 3;
2642 }
2643 }
2644 break;
2645 case 'x':
2646 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2647 return 0; /* fxsave/fxrstor are not really math ops */
2648 break;
2649 }
252b5132 2650
9306ca4a 2651 return 1;
252b5132
RH		 2652}
2653
c0f3af97
L		 2654/* Build the VEX prefix. */
2655
2656static void
d3ce72d0 2657build_vex_prefix (const insn_template *t)
c0f3af97
L		 2658{
2659 unsigned int register_specifier;
2660 unsigned int implied_prefix;
2661 unsigned int vector_length;
2662
2663 /* Check register specifier. */
2664 if (i.vex.register_specifier)
2665 {
2666 register_specifier = i.vex.register_specifier->reg_num;
2667 if ((i.vex.register_specifier->reg_flags & RegRex))
2668 register_specifier += 8;
2669 register_specifier = ~register_specifier & 0xf;
2670 }
2671 else
2672 register_specifier = 0xf;
2673
fa99fab2
L		 2674 /* Use 2-byte VEX prefix by swappping destination and source
2675 operand. */
2676 if (!i.swap_operand
2677 && i.operands == i.reg_operands
7f399153 2678 && i.tm.opcode_modifier.vexopcode == VEX0F
fa99fab2
L		 2679 && i.tm.opcode_modifier.s
2680 && i.rex == REX_B)
2681 {
2682 unsigned int xchg = i.operands - 1;
2683 union i386_op temp_op;
2684 i386_operand_type temp_type;
2685
2686 temp_type = i.types[xchg];
2687 i.types[xchg] = i.types[0];
2688 i.types[0] = temp_type;
2689 temp_op = i.op[xchg];
2690 i.op[xchg] = i.op[0];
2691 i.op[0] = temp_op;
2692
9c2799c2 2693 gas_assert (i.rm.mode == 3);
fa99fab2
L		 2694
2695 i.rex = REX_R;
2696 xchg = i.rm.regmem;
2697 i.rm.regmem = i.rm.reg;
2698 i.rm.reg = xchg;
2699
2700 /* Use the next insn. */
2701 i.tm = t[1];
2702 }
2703
e3c58833 2704 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 2705
2706 switch ((i.tm.base_opcode >> 8) & 0xff)
2707 {
2708 case 0:
2709 implied_prefix = 0;
2710 break;
2711 case DATA_PREFIX_OPCODE:
2712 implied_prefix = 1;
2713 break;
2714 case REPE_PREFIX_OPCODE:
2715 implied_prefix = 2;
2716 break;
2717 case REPNE_PREFIX_OPCODE:
2718 implied_prefix = 3;
2719 break;
2720 default:
2721 abort ();
2722 }
2723
2724 /* Use 2-byte VEX prefix if possible. */
7f399153 2725 if (i.tm.opcode_modifier.vexopcode == VEX0F
c0f3af97
L		 2726 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
2727 {
2728 /* 2-byte VEX prefix. */
2729 unsigned int r;
2730
2731 i.vex.length = 2;
2732 i.vex.bytes[0] = 0xc5;
2733
2734 /* Check the REX.R bit. */
2735 r = (i.rex & REX_R) ? 0 : 1;
2736 i.vex.bytes[1] = (r << 7
2737 | register_specifier << 3
2738 | vector_length << 2
2739 | implied_prefix);
2740 }
2741 else
2742 {
2743 /* 3-byte VEX prefix. */
2744 unsigned int m, w;
2745
f88c9eb0
SP		 2746 i.vex.length = 3;
2747 i.vex.bytes[0] = 0xc4;
2748
7f399153 2749 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 2750 {
7f399153
L		 2751 case VEX0F:
2752 m = 0x1;
2753 break;
2754 case VEX0F38:
2755 m = 0x2;
2756 break;
2757 case VEX0F3A:
2758 m = 0x3;
2759 break;
2760 case XOP08:
5dd85c99
SP		 2761 m = 0x8;
2762 i.vex.bytes[0] = 0x8f;
7f399153
L		 2763 break;
2764 case XOP09:
f88c9eb0
SP		 2765 m = 0x9;
2766 i.vex.bytes[0] = 0x8f;
7f399153
L		 2767 break;
2768 case XOP0A:
f88c9eb0
SP		 2769 m = 0xa;
2770 i.vex.bytes[0] = 0x8f;
7f399153
L		 2771 break;
2772 default:
2773 abort ();
f88c9eb0 2774 }
c0f3af97 2775
c0f3af97
L		 2776 /* The high 3 bits of the second VEX byte are 1's compliment
2777 of RXB bits from REX. */
2778 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
2779
2780 /* Check the REX.W bit. */
2781 w = (i.rex & REX_W) ? 1 : 0;
1ef99a7b 2782 if (i.tm.opcode_modifier.vexw)
c0f3af97
L		 2783 {
2784 if (w)
2785 abort ();
2786
1ef99a7b 2787 if (i.tm.opcode_modifier.vexw == VEXW1)
c0f3af97
L		 2788 w = 1;
2789 }
2790
2791 i.vex.bytes[2] = (w << 7
2792 | register_specifier << 3
2793 | vector_length << 2
2794 | implied_prefix);
2795 }
2796}
2797
65da13b5
L		 2798static void
2799process_immext (void)
2800{
2801 expressionS *exp;
2802
2803 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2804 {
1fed0ba1
L		 2805 /* SSE3 Instructions have the fixed operands with an opcode
2806 suffix which is coded in the same place as an 8-bit immediate
2807 field would be. Here we check those operands and remove them
2808 afterwards. */
65da13b5
L		 2809 unsigned int x;
2810
2811 for (x = 0; x < i.operands; x++)
2812 if (i.op[x].regs->reg_num != x)
2813 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 2814 register_prefix, i.op[x].regs->reg_name, x + 1,
2815 i.tm.name);
2816
2817 i.operands = 0;
65da13b5
L		 2818 }
2819
c0f3af97 2820 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 2821 which is coded in the same place as an 8-bit immediate field
2822 would be. Here we fake an 8-bit immediate operand from the
2823 opcode suffix stored in tm.extension_opcode.
2824
c1e679ec 2825 AVX instructions also use this encoding, for some of
c0f3af97 2826 3 argument instructions. */
65da13b5 2827
9c2799c2 2828 gas_assert (i.imm_operands == 0
7ab9ffdd
L		 2829 && (i.operands <= 2
2830 || (i.tm.opcode_modifier.vex
2831 && i.operands <= 4)));
65da13b5
L		 2832
2833 exp = &im_expressions[i.imm_operands++];
2834 i.op[i.operands].imms = exp;
2835 i.types[i.operands] = imm8;
2836 i.operands++;
2837 exp->X_op = O_constant;
2838 exp->X_add_number = i.tm.extension_opcode;
2839 i.tm.extension_opcode = None;
2840}
2841
252b5132
RH		 2842/* This is the guts of the machine-dependent assembler. LINE points to a
2843 machine dependent instruction. This function is supposed to emit
2844 the frags/bytes it assembles to. */
2845
2846void
65da13b5 2847md_assemble (char *line)
252b5132 2848{
40fb9820 2849 unsigned int j;
252b5132 2850 char mnemonic[MAX_MNEM_SIZE];
d3ce72d0 2851 const insn_template *t;
252b5132 2852
47926f60 2853 /* Initialize globals. */
252b5132
RH		 2854 memset (&i, '\0', sizeof (i));
2855 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 2856 i.reloc[j] = NO_RELOC;
252b5132
RH		 2857 memset (disp_expressions, '\0', sizeof (disp_expressions));
2858 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 2859 save_stack_p = save_stack;
252b5132
RH		 2860
2861 /* First parse an instruction mnemonic & call i386_operand for the operands.
2862 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 2863 start of a (possibly prefixed) mnemonic. */
252b5132 2864
29b0f896
AM		 2865 line = parse_insn (line, mnemonic);
2866 if (line == NULL)
2867 return;
252b5132 2868
29b0f896 2869 line = parse_operands (line, mnemonic);
ee86248c 2870 this_operand = -1;
29b0f896
AM		 2871 if (line == NULL)
2872 return;
252b5132 2873
29b0f896
AM		 2874 /* Now we've parsed the mnemonic into a set of templates, and have the
2875 operands at hand. */
2876
2877 /* All intel opcodes have reversed operands except for "bound" and
2878 "enter". We also don't reverse intersegment "jmp" and "call"
2879 instructions with 2 immediate operands so that the immediate segment
050dfa73 2880 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 2881 if (intel_syntax
2882 && i.operands > 1
29b0f896 2883 && (strcmp (mnemonic, "bound") != 0)
30123838 2884 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 2885 && !(operand_type_check (i.types[0], imm)
2886 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 2887 swap_operands ();
2888
ec56d5c0
JB		 2889 /* The order of the immediates should be reversed
2890 for 2 immediates extrq and insertq instructions */
2891 if (i.imm_operands == 2
2892 && (strcmp (mnemonic, "extrq") == 0
2893 || strcmp (mnemonic, "insertq") == 0))
2894 swap_2_operands (0, 1);
2895
29b0f896
AM		 2896 if (i.imm_operands)
2897 optimize_imm ();
2898
b300c311
L		 2899 /* Don't optimize displacement for movabs since it only takes 64bit
2900 displacement. */
2901 if (i.disp_operands
2902 && (flag_code != CODE_64BIT
2903 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 2904 optimize_disp ();
2905
2906 /* Next, we find a template that matches the given insn,
2907 making sure the overlap of the given operands types is consistent
2908 with the template operand types. */
252b5132 2909
fa99fab2 2910 if (!(t = match_template ()))
29b0f896 2911 return;
252b5132 2912
daf50ae7 2913 if (sse_check != sse_check_none
81f8a913 2914 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 2915 && (i.tm.cpu_flags.bitfield.cpusse
2916 || i.tm.cpu_flags.bitfield.cpusse2
2917 || i.tm.cpu_flags.bitfield.cpusse3
2918 || i.tm.cpu_flags.bitfield.cpussse3
2919 || i.tm.cpu_flags.bitfield.cpusse4_1
2920 || i.tm.cpu_flags.bitfield.cpusse4_2))
2921 {
2922 (sse_check == sse_check_warning
2923 ? as_warn
2924 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
2925 }
2926
321fd21e
L		 2927 /* Zap movzx and movsx suffix. The suffix has been set from
2928 "word ptr" or "byte ptr" on the source operand in Intel syntax
2929 or extracted from mnemonic in AT&T syntax. But we'll use
2930 the destination register to choose the suffix for encoding. */
2931 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 2932 {
321fd21e
L		 2933 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2934 there is no suffix, the default will be byte extension. */
2935 if (i.reg_operands != 2
2936 && !i.suffix
7ab9ffdd 2937 && intel_syntax)
321fd21e
L		 2938 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2939
2940 i.suffix = 0;
cd61ebfe 2941 }
24eab124 2942
40fb9820 2943 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 2944 if (!add_prefix (FWAIT_OPCODE))
2945 return;
252b5132 2946
c1ba0266
L		 2947 /* Check for lock without a lockable instruction. Destination operand
2948 must be memory unless it is xchg (0x86). */
c32fa91d
L		 2949 if (i.prefix[LOCK_PREFIX]
2950 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 2951 || i.mem_operands == 0
2952 || (i.tm.base_opcode != 0x86
2953 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 2954 {
2955 as_bad (_("expecting lockable instruction after `lock'"));
2956 return;
2957 }
2958
29b0f896 2959 /* Check string instruction segment overrides. */
40fb9820 2960 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 2961 {
2962 if (!check_string ())
5dd0794d 2963 return;
fc0763e6 2964 i.disp_operands = 0;
29b0f896 2965 }
5dd0794d 2966
29b0f896
AM		 2967 if (!process_suffix ())
2968 return;
e413e4e9 2969
bc0844ae
L		 2970 /* Update operand types. */
2971 for (j = 0; j < i.operands; j++)
2972 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
2973
29b0f896
AM		 2974 /* Make still unresolved immediate matches conform to size of immediate
2975 given in i.suffix. */
2976 if (!finalize_imm ())
2977 return;
252b5132 2978
40fb9820 2979 if (i.types[0].bitfield.imm1)
29b0f896 2980 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 2981
9afe6eb8
L		 2982 /* We only need to check those implicit registers for instructions
2983 with 3 operands or less. */
2984 if (i.operands <= 3)
2985 for (j = 0; j < i.operands; j++)
2986 if (i.types[j].bitfield.inoutportreg
2987 || i.types[j].bitfield.shiftcount
2988 || i.types[j].bitfield.acc
2989 || i.types[j].bitfield.floatacc)
2990 i.reg_operands--;
40fb9820 2991
c0f3af97
L		 2992 /* ImmExt should be processed after SSE2AVX. */
2993 if (!i.tm.opcode_modifier.sse2avx
2994 && i.tm.opcode_modifier.immext)
65da13b5 2995 process_immext ();
252b5132 2996
29b0f896
AM		 2997 /* For insns with operands there are more diddles to do to the opcode. */
2998 if (i.operands)
2999 {
3000 if (!process_operands ())
3001 return;
3002 }
40fb9820 3003 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3004 {
3005 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3006 as_warn (_("translating to `%sp'"), i.tm.name);
3007 }
252b5132 3008
c0f3af97 3009 if (i.tm.opcode_modifier.vex)
fa99fab2 3010 build_vex_prefix (t);
c0f3af97 3011
5dd85c99
SP		 3012 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3013 instructions may define INT_OPCODE as well, so avoid this corner
3014 case for those instructions that use MODRM. */
3015 if (i.tm.base_opcode == INT_OPCODE
3016 && i.op[0].imms->X_add_number == 3
3017 && !i.tm.opcode_modifier.modrm)
29b0f896
AM		 3018 {
3019 i.tm.base_opcode = INT3_OPCODE;
3020 i.imm_operands = 0;
3021 }
252b5132 3022
40fb9820
L		 3023 if ((i.tm.opcode_modifier.jump
3024 || i.tm.opcode_modifier.jumpbyte
3025 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3026 && i.op[0].disps->X_op == O_constant)
3027 {
3028 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3029 the absolute address given by the constant. Since ix86 jumps and
3030 calls are pc relative, we need to generate a reloc. */
3031 i.op[0].disps->X_add_symbol = &abs_symbol;
3032 i.op[0].disps->X_op = O_symbol;
3033 }
252b5132 3034
40fb9820 3035 if (i.tm.opcode_modifier.rex64)
161a04f6 3036 i.rex |= REX_W;
252b5132 3037
29b0f896
AM		 3038 /* For 8 bit registers we need an empty rex prefix. Also if the
3039 instruction already has a prefix, we need to convert old
3040 registers to new ones. */
773f551c 3041
40fb9820 3042 if ((i.types[0].bitfield.reg8
29b0f896 3043 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3044 || (i.types[1].bitfield.reg8
29b0f896 3045 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3046 || ((i.types[0].bitfield.reg8
3047 || i.types[1].bitfield.reg8)
29b0f896
AM		 3048 && i.rex != 0))
3049 {
3050 int x;
726c5dcd 3051
29b0f896
AM		 3052 i.rex |= REX_OPCODE;
3053 for (x = 0; x < 2; x++)
3054 {
3055 /* Look for 8 bit operand that uses old registers. */
40fb9820 3056 if (i.types[x].bitfield.reg8
29b0f896 3057 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3058 {
29b0f896
AM		 3059 /* In case it is "hi" register, give up. */
3060 if (i.op[x].regs->reg_num > 3)
a540244d 3061 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3062 "instruction requiring REX prefix."),
a540244d 3063 register_prefix, i.op[x].regs->reg_name);
773f551c 3064
29b0f896
AM		 3065 /* Otherwise it is equivalent to the extended register.
3066 Since the encoding doesn't change this is merely
3067 cosmetic cleanup for debug output. */
3068
3069 i.op[x].regs = i.op[x].regs + 8;
773f551c 3070 }
29b0f896
AM		 3071 }
3072 }
773f551c 3073
7ab9ffdd 3074 if (i.rex != 0)
29b0f896
AM		 3075 add_prefix (REX_OPCODE | i.rex);
3076
3077 /* We are ready to output the insn. */
3078 output_insn ();
3079}
3080
3081static char *
e3bb37b5 3082parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3083{
3084 char *l = line;
3085 char *token_start = l;
3086 char *mnem_p;
5c6af06e 3087 int supported;
d3ce72d0 3088 const insn_template *t;
b6169b20 3089 char *dot_p = NULL;
29b0f896
AM		 3090
3091 /* Non-zero if we found a prefix only acceptable with string insns. */
3092 const char *expecting_string_instruction = NULL;
45288df1 3093
29b0f896
AM		 3094 while (1)
3095 {
3096 mnem_p = mnemonic;
3097 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3098 {
b6169b20
L		 3099 if (*mnem_p == '.')
3100 dot_p = mnem_p;
29b0f896
AM		 3101 mnem_p++;
3102 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3103 {
29b0f896
AM		 3104 as_bad (_("no such instruction: `%s'"), token_start);
3105 return NULL;
3106 }
3107 l++;
3108 }
3109 if (!is_space_char (*l)
3110 && *l != END_OF_INSN
e44823cf
JB		 3111 && (intel_syntax
3112 || (*l != PREFIX_SEPARATOR
3113 && *l != ',')))
29b0f896
AM		 3114 {
3115 as_bad (_("invalid character %s in mnemonic"),
3116 output_invalid (*l));
3117 return NULL;
3118 }
3119 if (token_start == l)
3120 {
e44823cf 3121 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3122 as_bad (_("expecting prefix; got nothing"));
3123 else
3124 as_bad (_("expecting mnemonic; got nothing"));
3125 return NULL;
3126 }
45288df1 3127
29b0f896 3128 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3129 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3130
29b0f896
AM		 3131 if (*l != END_OF_INSN
3132 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3133 && current_templates
40fb9820 3134 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3135 {
c6fb90c8 3136 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3137 {
3138 as_bad ((flag_code != CODE_64BIT
3139 ? _("`%s' is only supported in 64-bit mode")
3140 : _("`%s' is not supported in 64-bit mode")),
3141 current_templates->start->name);
3142 return NULL;
3143 }
29b0f896
AM		 3144 /* If we are in 16-bit mode, do not allow addr16 or data16.
3145 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3146 if ((current_templates->start->opcode_modifier.size16
3147 || current_templates->start->opcode_modifier.size32)
29b0f896 3148 && flag_code != CODE_64BIT
40fb9820 3149 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3150 ^ (flag_code == CODE_16BIT)))
3151 {
3152 as_bad (_("redundant %s prefix"),
3153 current_templates->start->name);
3154 return NULL;
45288df1 3155 }
29b0f896
AM		 3156 /* Add prefix, checking for repeated prefixes. */
3157 switch (add_prefix (current_templates->start->base_opcode))
3158 {
c32fa91d 3159 case PREFIX_EXIST:
29b0f896 3160 return NULL;
c32fa91d 3161 case PREFIX_REP:
29b0f896
AM		 3162 expecting_string_instruction = current_templates->start->name;
3163 break;
c32fa91d
L		 3164 default:
3165 break;
29b0f896
AM		 3166 }
3167 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3168 token_start = ++l;
3169 }
3170 else
3171 break;
3172 }
45288df1 3173
30a55f88 3174 if (!current_templates)
b6169b20 3175 {
30a55f88
L		 3176 /* Check if we should swap operand in encoding. */
3177 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3178 i.swap_operand = 1;
3179 else
3180 goto check_suffix;
3181 mnem_p = dot_p;
3182 *dot_p = '\0';
d3ce72d0 3183 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3184 }
3185
29b0f896
AM		 3186 if (!current_templates)
3187 {
b6169b20 3188check_suffix:
29b0f896
AM		 3189 /* See if we can get a match by trimming off a suffix. */
3190 switch (mnem_p[-1])
3191 {
3192 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3193 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3194 i.suffix = SHORT_MNEM_SUFFIX;
3195 else
29b0f896
AM		 3196 case BYTE_MNEM_SUFFIX:
3197 case QWORD_MNEM_SUFFIX:
3198 i.suffix = mnem_p[-1];
3199 mnem_p[-1] = '\0';
d3ce72d0
NC		 3200 current_templates = (const templates *) hash_find (op_hash,
3201 mnemonic);
29b0f896
AM		 3202 break;
3203 case SHORT_MNEM_SUFFIX:
3204 case LONG_MNEM_SUFFIX:
3205 if (!intel_syntax)
3206 {
3207 i.suffix = mnem_p[-1];
3208 mnem_p[-1] = '\0';
d3ce72d0
NC		 3209 current_templates = (const templates *) hash_find (op_hash,
3210 mnemonic);
29b0f896
AM		 3211 }
3212 break;
252b5132 3213
29b0f896
AM		 3214 /* Intel Syntax. */
3215 case 'd':
3216 if (intel_syntax)
3217 {
9306ca4a 3218 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3219 i.suffix = SHORT_MNEM_SUFFIX;
3220 else
3221 i.suffix = LONG_MNEM_SUFFIX;
3222 mnem_p[-1] = '\0';
d3ce72d0
NC		 3223 current_templates = (const templates *) hash_find (op_hash,
3224 mnemonic);
29b0f896
AM		 3225 }
3226 break;
3227 }
3228 if (!current_templates)
3229 {
3230 as_bad (_("no such instruction: `%s'"), token_start);
3231 return NULL;
3232 }
3233 }
252b5132 3234
40fb9820
L		 3235 if (current_templates->start->opcode_modifier.jump
3236 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3237 {
3238 /* Check for a branch hint. We allow ",pt" and ",pn" for
3239 predict taken and predict not taken respectively.
3240 I'm not sure that branch hints actually do anything on loop
3241 and jcxz insns (JumpByte) for current Pentium4 chips. They
3242 may work in the future and it doesn't hurt to accept them
3243 now. */
3244 if (l[0] == ',' && l[1] == 'p')
3245 {
3246 if (l[2] == 't')
3247 {
3248 if (!add_prefix (DS_PREFIX_OPCODE))
3249 return NULL;
3250 l += 3;
3251 }
3252 else if (l[2] == 'n')
3253 {
3254 if (!add_prefix (CS_PREFIX_OPCODE))
3255 return NULL;
3256 l += 3;
3257 }
3258 }
3259 }
3260 /* Any other comma loses. */
3261 if (*l == ',')
3262 {
3263 as_bad (_("invalid character %s in mnemonic"),
3264 output_invalid (*l));
3265 return NULL;
3266 }
252b5132 3267
29b0f896 3268 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3269 supported = 0;
3270 for (t = current_templates->start; t < current_templates->end; ++t)
3271 {
c0f3af97
L		 3272 supported |= cpu_flags_match (t);
3273 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3274 goto skip;
5c6af06e 3275 }
3629bb00 3276
c0f3af97 3277 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3278 {
3279 as_bad (flag_code == CODE_64BIT
3280 ? _("`%s' is not supported in 64-bit mode")
3281 : _("`%s' is only supported in 64-bit mode"),
3282 current_templates->start->name);
3283 return NULL;
3284 }
c0f3af97 3285 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3286 {
3629bb00 3287 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 3288 current_templates->start->name,
41aacd83 3289 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3290 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3291 return NULL;
29b0f896 3292 }
3629bb00
L		 3293
3294skip:
3295 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3296 && (flag_code != CODE_16BIT))
29b0f896
AM		 3297 {
3298 as_warn (_("use .code16 to ensure correct addressing mode"));
3299 }
252b5132 3300
29b0f896 3301 /* Check for rep/repne without a string instruction. */
f41bbced 3302 if (expecting_string_instruction)
29b0f896 3303 {
f41bbced
JB		 3304 static templates override;
3305
3306 for (t = current_templates->start; t < current_templates->end; ++t)
40fb9820 3307 if (t->opcode_modifier.isstring)
f41bbced
JB		 3308 break;
3309 if (t >= current_templates->end)
3310 {
3311 as_bad (_("expecting string instruction after `%s'"),
64e74474 3312 expecting_string_instruction);
f41bbced
JB		 3313 return NULL;
3314 }
3315 for (override.start = t; t < current_templates->end; ++t)
40fb9820 3316 if (!t->opcode_modifier.isstring)
f41bbced
JB		 3317 break;
3318 override.end = t;
3319 current_templates = &override;
29b0f896 3320 }
252b5132 3321
29b0f896
AM		 3322 return l;
3323}
252b5132 3324
29b0f896 3325static char *
e3bb37b5 3326parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3327{
3328 char *token_start;
3138f287 3329
29b0f896
AM		 3330 /* 1 if operand is pending after ','. */
3331 unsigned int expecting_operand = 0;
252b5132 3332
29b0f896
AM		 3333 /* Non-zero if operand parens not balanced. */
3334 unsigned int paren_not_balanced;
3335
3336 while (*l != END_OF_INSN)
3337 {
3338 /* Skip optional white space before operand. */
3339 if (is_space_char (*l))
3340 ++l;
3341 if (!is_operand_char (*l) && *l != END_OF_INSN)
3342 {
3343 as_bad (_("invalid character %s before operand %d"),
3344 output_invalid (*l),
3345 i.operands + 1);
3346 return NULL;
3347 }
3348 token_start = l; /* after white space */
3349 paren_not_balanced = 0;
3350 while (paren_not_balanced || *l != ',')
3351 {
3352 if (*l == END_OF_INSN)
3353 {
3354 if (paren_not_balanced)
3355 {
3356 if (!intel_syntax)
3357 as_bad (_("unbalanced parenthesis in operand %d."),
3358 i.operands + 1);
3359 else
3360 as_bad (_("unbalanced brackets in operand %d."),
3361 i.operands + 1);
3362 return NULL;
3363 }
3364 else
3365 break; /* we are done */
3366 }
3367 else if (!is_operand_char (*l) && !is_space_char (*l))
3368 {
3369 as_bad (_("invalid character %s in operand %d"),
3370 output_invalid (*l),
3371 i.operands + 1);
3372 return NULL;
3373 }
3374 if (!intel_syntax)
3375 {
3376 if (*l == '(')
3377 ++paren_not_balanced;
3378 if (*l == ')')
3379 --paren_not_balanced;
3380 }
3381 else
3382 {
3383 if (*l == '[')
3384 ++paren_not_balanced;
3385 if (*l == ']')
3386 --paren_not_balanced;
3387 }
3388 l++;
3389 }
3390 if (l != token_start)
3391 { /* Yes, we've read in another operand. */
3392 unsigned int operand_ok;
3393 this_operand = i.operands++;
7d5e4556 3394 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 3395 if (i.operands > MAX_OPERANDS)
3396 {
3397 as_bad (_("spurious operands; (%d operands/instruction max)"),
3398 MAX_OPERANDS);
3399 return NULL;
3400 }
3401 /* Now parse operand adding info to 'i' as we go along. */
3402 END_STRING_AND_SAVE (l);
3403
3404 if (intel_syntax)
3405 operand_ok =
3406 i386_intel_operand (token_start,
3407 intel_float_operand (mnemonic));
3408 else
a7619375 3409 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 3410
3411 RESTORE_END_STRING (l);
3412 if (!operand_ok)
3413 return NULL;
3414 }
3415 else
3416 {
3417 if (expecting_operand)
3418 {
3419 expecting_operand_after_comma:
3420 as_bad (_("expecting operand after ','; got nothing"));
3421 return NULL;
3422 }
3423 if (*l == ',')
3424 {
3425 as_bad (_("expecting operand before ','; got nothing"));
3426 return NULL;
3427 }
3428 }
7f3f1ea2 3429
29b0f896
AM		 3430 /* Now *l must be either ',' or END_OF_INSN. */
3431 if (*l == ',')
3432 {
3433 if (*++l == END_OF_INSN)
3434 {
3435 /* Just skip it, if it's \n complain. */
3436 goto expecting_operand_after_comma;
3437 }
3438 expecting_operand = 1;
3439 }
3440 }
3441 return l;
3442}
7f3f1ea2 3443
050dfa73 3444static void
4d456e3d 3445swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 3446{
3447 union i386_op temp_op;
40fb9820 3448 i386_operand_type temp_type;
050dfa73 3449 enum bfd_reloc_code_real temp_reloc;
4eed87de 3450
050dfa73
MM		 3451 temp_type = i.types[xchg2];
3452 i.types[xchg2] = i.types[xchg1];
3453 i.types[xchg1] = temp_type;
3454 temp_op = i.op[xchg2];
3455 i.op[xchg2] = i.op[xchg1];
3456 i.op[xchg1] = temp_op;
3457 temp_reloc = i.reloc[xchg2];
3458 i.reloc[xchg2] = i.reloc[xchg1];
3459 i.reloc[xchg1] = temp_reloc;
3460}
3461
29b0f896 3462static void
e3bb37b5 3463swap_operands (void)
29b0f896 3464{
b7c61d9a 3465 switch (i.operands)
050dfa73 3466 {
c0f3af97 3467 case 5:
b7c61d9a 3468 case 4:
4d456e3d 3469 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 3470 case 3:
3471 case 2:
4d456e3d 3472 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 3473 break;
3474 default:
3475 abort ();
29b0f896 3476 }
29b0f896
AM		 3477
3478 if (i.mem_operands == 2)
3479 {
3480 const seg_entry *temp_seg;
3481 temp_seg = i.seg[0];
3482 i.seg[0] = i.seg[1];
3483 i.seg[1] = temp_seg;
3484 }
3485}
252b5132 3486
29b0f896
AM		 3487/* Try to ensure constant immediates are represented in the smallest
3488 opcode possible. */
3489static void
e3bb37b5 3490optimize_imm (void)
29b0f896
AM		 3491{
3492 char guess_suffix = 0;
3493 int op;
252b5132 3494
29b0f896
AM		 3495 if (i.suffix)
3496 guess_suffix = i.suffix;
3497 else if (i.reg_operands)
3498 {
3499 /* Figure out a suffix from the last register operand specified.
3500 We can't do this properly yet, ie. excluding InOutPortReg,
3501 but the following works for instructions with immediates.
3502 In any case, we can't set i.suffix yet. */
3503 for (op = i.operands; --op >= 0;)
40fb9820 3504 if (i.types[op].bitfield.reg8)
7ab9ffdd 3505 {
40fb9820
L		 3506 guess_suffix = BYTE_MNEM_SUFFIX;
3507 break;
3508 }
3509 else if (i.types[op].bitfield.reg16)
252b5132 3510 {
40fb9820
L		 3511 guess_suffix = WORD_MNEM_SUFFIX;
3512 break;
3513 }
3514 else if (i.types[op].bitfield.reg32)
3515 {
3516 guess_suffix = LONG_MNEM_SUFFIX;
3517 break;
3518 }
3519 else if (i.types[op].bitfield.reg64)
3520 {
3521 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 3522 break;
252b5132 3523 }
29b0f896
AM		 3524 }
3525 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3526 guess_suffix = WORD_MNEM_SUFFIX;
3527
3528 for (op = i.operands; --op >= 0;)
40fb9820 3529 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 3530 {
3531 switch (i.op[op].imms->X_op)
252b5132 3532 {
29b0f896
AM		 3533 case O_constant:
3534 /* If a suffix is given, this operand may be shortened. */
3535 switch (guess_suffix)
252b5132 3536 {
29b0f896 3537 case LONG_MNEM_SUFFIX:
40fb9820
L		 3538 i.types[op].bitfield.imm32 = 1;
3539 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3540 break;
3541 case WORD_MNEM_SUFFIX:
40fb9820
L		 3542 i.types[op].bitfield.imm16 = 1;
3543 i.types[op].bitfield.imm32 = 1;
3544 i.types[op].bitfield.imm32s = 1;
3545 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3546 break;
3547 case BYTE_MNEM_SUFFIX:
40fb9820
L		 3548 i.types[op].bitfield.imm8 = 1;
3549 i.types[op].bitfield.imm8s = 1;
3550 i.types[op].bitfield.imm16 = 1;
3551 i.types[op].bitfield.imm32 = 1;
3552 i.types[op].bitfield.imm32s = 1;
3553 i.types[op].bitfield.imm64 = 1;
29b0f896 3554 break;
252b5132 3555 }
252b5132 3556
29b0f896
AM		 3557 /* If this operand is at most 16 bits, convert it
3558 to a signed 16 bit number before trying to see
3559 whether it will fit in an even smaller size.
3560 This allows a 16-bit operand such as $0xffe0 to
3561 be recognised as within Imm8S range. */
40fb9820 3562 if ((i.types[op].bitfield.imm16)
29b0f896 3563 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 3564 {
29b0f896
AM		 3565 i.op[op].imms->X_add_number =
3566 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3567 }
40fb9820 3568 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 3569 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3570 == 0))
3571 {
3572 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3573 ^ ((offsetT) 1 << 31))
3574 - ((offsetT) 1 << 31));
3575 }
40fb9820 3576 i.types[op]
c6fb90c8
L		 3577 = operand_type_or (i.types[op],
3578 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 3579
29b0f896
AM		 3580 /* We must avoid matching of Imm32 templates when 64bit
3581 only immediate is available. */
3582 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 3583 i.types[op].bitfield.imm32 = 0;
29b0f896 3584 break;
252b5132 3585
29b0f896
AM		 3586 case O_absent:
3587 case O_register:
3588 abort ();
3589
3590 /* Symbols and expressions. */
3591 default:
9cd96992
JB		 3592 /* Convert symbolic operand to proper sizes for matching, but don't
3593 prevent matching a set of insns that only supports sizes other
3594 than those matching the insn suffix. */
3595 {
40fb9820 3596 i386_operand_type mask, allowed;
d3ce72d0 3597 const insn_template *t;
9cd96992 3598
0dfbf9d7
L		 3599 operand_type_set (&mask, 0);
3600 operand_type_set (&allowed, 0);
40fb9820 3601
4eed87de
AM		 3602 for (t = current_templates->start;
3603 t < current_templates->end;
3604 ++t)
c6fb90c8
L		 3605 allowed = operand_type_or (allowed,
3606 t->operand_types[op]);
9cd96992
JB		 3607 switch (guess_suffix)
3608 {
3609 case QWORD_MNEM_SUFFIX:
40fb9820
L		 3610 mask.bitfield.imm64 = 1;
3611 mask.bitfield.imm32s = 1;
9cd96992
JB		 3612 break;
3613 case LONG_MNEM_SUFFIX:
40fb9820 3614 mask.bitfield.imm32 = 1;
9cd96992
JB		 3615 break;
3616 case WORD_MNEM_SUFFIX:
40fb9820 3617 mask.bitfield.imm16 = 1;
9cd96992
JB		 3618 break;
3619 case BYTE_MNEM_SUFFIX:
40fb9820 3620 mask.bitfield.imm8 = 1;
9cd96992
JB		 3621 break;
3622 default:
9cd96992
JB		 3623 break;
3624 }
c6fb90c8 3625 allowed = operand_type_and (mask, allowed);
0dfbf9d7 3626 if (!operand_type_all_zero (&allowed))
c6fb90c8 3627 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 3628 }
29b0f896 3629 break;
252b5132 3630 }
29b0f896
AM		 3631 }
3632}
47926f60 3633
29b0f896
AM		 3634/* Try to use the smallest displacement type too. */
3635static void
e3bb37b5 3636optimize_disp (void)
29b0f896
AM		 3637{
3638 int op;
3e73aa7c 3639
29b0f896 3640 for (op = i.operands; --op >= 0;)
40fb9820 3641 if (operand_type_check (i.types[op], disp))
252b5132 3642 {
b300c311 3643 if (i.op[op].disps->X_op == O_constant)
252b5132 3644 {
91d6fa6a 3645 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 3646
40fb9820 3647 if (i.types[op].bitfield.disp16
91d6fa6a 3648 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 3649 {
3650 /* If this operand is at most 16 bits, convert
3651 to a signed 16 bit number and don't use 64bit
3652 displacement. */
91d6fa6a 3653 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 3654 i.types[op].bitfield.disp64 = 0;
b300c311 3655 }
40fb9820 3656 if (i.types[op].bitfield.disp32
91d6fa6a 3657 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 3658 {
3659 /* If this operand is at most 32 bits, convert
3660 to a signed 32 bit number and don't use 64bit
3661 displacement. */
91d6fa6a
NC		 3662 op_disp &= (((offsetT) 2 << 31) - 1);
3663 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 3664 i.types[op].bitfield.disp64 = 0;
b300c311 3665 }
91d6fa6a 3666 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 3667 {
40fb9820
L		 3668 i.types[op].bitfield.disp8 = 0;
3669 i.types[op].bitfield.disp16 = 0;
3670 i.types[op].bitfield.disp32 = 0;
3671 i.types[op].bitfield.disp32s = 0;
3672 i.types[op].bitfield.disp64 = 0;
b300c311
L		 3673 i.op[op].disps = 0;
3674 i.disp_operands--;
3675 }
3676 else if (flag_code == CODE_64BIT)
3677 {
91d6fa6a 3678 if (fits_in_signed_long (op_disp))
28a9d8f5 3679 {
40fb9820
L		 3680 i.types[op].bitfield.disp64 = 0;
3681 i.types[op].bitfield.disp32s = 1;
28a9d8f5 3682 }
0e1147d9 3683 if (i.prefix[ADDR_PREFIX]
91d6fa6a 3684 && fits_in_unsigned_long (op_disp))
40fb9820 3685 i.types[op].bitfield.disp32 = 1;
b300c311 3686 }
40fb9820
L		 3687 if ((i.types[op].bitfield.disp32
3688 || i.types[op].bitfield.disp32s
3689 || i.types[op].bitfield.disp16)
91d6fa6a 3690 && fits_in_signed_byte (op_disp))
40fb9820 3691 i.types[op].bitfield.disp8 = 1;
252b5132 3692 }
67a4f2b7
AO		 3693 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3694 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3695 {
3696 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3697 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 3698 i.types[op].bitfield.disp8 = 0;
3699 i.types[op].bitfield.disp16 = 0;
3700 i.types[op].bitfield.disp32 = 0;
3701 i.types[op].bitfield.disp32s = 0;
3702 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 3703 }
3704 else
b300c311 3705 /* We only support 64bit displacement on constants. */
40fb9820 3706 i.types[op].bitfield.disp64 = 0;
252b5132 3707 }
29b0f896
AM		 3708}
3709
d3ce72d0 3710static const insn_template *
e3bb37b5 3711match_template (void)
29b0f896
AM		 3712{
3713 /* Points to template once we've found it. */
d3ce72d0 3714 const insn_template *t;
40fb9820 3715 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 3716 i386_operand_type overlap4;
29b0f896 3717 unsigned int found_reverse_match;
40fb9820
L		 3718 i386_opcode_modifier suffix_check;
3719 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 3720 int addr_prefix_disp;
a5c311ca 3721 unsigned int j;
3629bb00 3722 unsigned int found_cpu_match;
45664ddb 3723 unsigned int check_register;
29b0f896 3724
c0f3af97
L		 3725#if MAX_OPERANDS != 5
3726# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 3727#endif
3728
29b0f896 3729 found_reverse_match = 0;
539e75ad 3730 addr_prefix_disp = -1;
40fb9820
L		 3731
3732 memset (&suffix_check, 0, sizeof (suffix_check));
3733 if (i.suffix == BYTE_MNEM_SUFFIX)
3734 suffix_check.no_bsuf = 1;
3735 else if (i.suffix == WORD_MNEM_SUFFIX)
3736 suffix_check.no_wsuf = 1;
3737 else if (i.suffix == SHORT_MNEM_SUFFIX)
3738 suffix_check.no_ssuf = 1;
3739 else if (i.suffix == LONG_MNEM_SUFFIX)
3740 suffix_check.no_lsuf = 1;
3741 else if (i.suffix == QWORD_MNEM_SUFFIX)
3742 suffix_check.no_qsuf = 1;
3743 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 3744 suffix_check.no_ldsuf = 1;
29b0f896 3745
45aa61fe 3746 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 3747 {
539e75ad
L		 3748 addr_prefix_disp = -1;
3749
29b0f896
AM		 3750 /* Must have right number of operands. */
3751 if (i.operands != t->operands)
3752 continue;
3753
50aecf8c 3754 /* Check processor support. */
c0f3af97
L		 3755 found_cpu_match = (cpu_flags_match (t)
3756 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 3757 if (!found_cpu_match)
3758 continue;
3759
e1d4d893
L		 3760 /* Check old gcc support. */
3761 if (!old_gcc && t->opcode_modifier.oldgcc)
3762 continue;
3763
3764 /* Check AT&T mnemonic. */
3765 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 3766 continue;
3767
5c07affc
L		 3768 /* Check AT&T syntax Intel syntax. */
3769 if ((intel_syntax && t->opcode_modifier.attsyntax)
3770 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 3771 continue;
3772
20592a94 3773 /* Check the suffix, except for some instructions in intel mode. */
567e4e96
L		 3774 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3775 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3776 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3777 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3778 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3779 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3780 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 3781 continue;
3782
5c07affc 3783 if (!operand_size_match (t))
7d5e4556 3784 continue;
539e75ad 3785
5c07affc
L		 3786 for (j = 0; j < MAX_OPERANDS; j++)
3787 operand_types[j] = t->operand_types[j];
3788
45aa61fe
AM		 3789 /* In general, don't allow 64-bit operands in 32-bit mode. */
3790 if (i.suffix == QWORD_MNEM_SUFFIX
3791 && flag_code != CODE_64BIT
3792 && (intel_syntax
40fb9820 3793 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 3794 && !intel_float_operand (t->name))
3795 : intel_float_operand (t->name) != 2)
40fb9820 3796 && ((!operand_types[0].bitfield.regmmx
c0f3af97
L		 3797 && !operand_types[0].bitfield.regxmm
3798 && !operand_types[0].bitfield.regymm)
40fb9820 3799 || (!operand_types[t->operands > 1].bitfield.regmmx
c0f3af97
L		 3800 && !!operand_types[t->operands > 1].bitfield.regxmm
3801 && !!operand_types[t->operands > 1].bitfield.regymm))
45aa61fe
AM		 3802 && (t->base_opcode != 0x0fc7
3803 || t->extension_opcode != 1 /* cmpxchg8b */))
3804 continue;
3805
192dc9c6
JB		 3806 /* In general, don't allow 32-bit operands on pre-386. */
3807 else if (i.suffix == LONG_MNEM_SUFFIX
3808 && !cpu_arch_flags.bitfield.cpui386
3809 && (intel_syntax
3810 ? (!t->opcode_modifier.ignoresize
3811 && !intel_float_operand (t->name))
3812 : intel_float_operand (t->name) != 2)
3813 && ((!operand_types[0].bitfield.regmmx
3814 && !operand_types[0].bitfield.regxmm)
3815 || (!operand_types[t->operands > 1].bitfield.regmmx
3816 && !!operand_types[t->operands > 1].bitfield.regxmm)))
3817 continue;
3818
29b0f896 3819 /* Do not verify operands when there are none. */
50aecf8c 3820 else
29b0f896 3821 {
c6fb90c8 3822 if (!t->operands)
2dbab7d5
L		 3823 /* We've found a match; break out of loop. */
3824 break;
29b0f896 3825 }
252b5132 3826
539e75ad
L		 3827 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3828 into Disp32/Disp16/Disp32 operand. */
3829 if (i.prefix[ADDR_PREFIX] != 0)
3830 {
40fb9820 3831 /* There should be only one Disp operand. */
539e75ad
L		 3832 switch (flag_code)
3833 {
3834 case CODE_16BIT:
40fb9820
L		 3835 for (j = 0; j < MAX_OPERANDS; j++)
3836 {
3837 if (operand_types[j].bitfield.disp16)
3838 {
3839 addr_prefix_disp = j;
3840 operand_types[j].bitfield.disp32 = 1;
3841 operand_types[j].bitfield.disp16 = 0;
3842 break;
3843 }
3844 }
539e75ad
L		 3845 break;
3846 case CODE_32BIT:
40fb9820
L		 3847 for (j = 0; j < MAX_OPERANDS; j++)
3848 {
3849 if (operand_types[j].bitfield.disp32)
3850 {
3851 addr_prefix_disp = j;
3852 operand_types[j].bitfield.disp32 = 0;
3853 operand_types[j].bitfield.disp16 = 1;
3854 break;
3855 }
3856 }
539e75ad
L		 3857 break;
3858 case CODE_64BIT:
40fb9820
L		 3859 for (j = 0; j < MAX_OPERANDS; j++)
3860 {
3861 if (operand_types[j].bitfield.disp64)
3862 {
3863 addr_prefix_disp = j;
3864 operand_types[j].bitfield.disp64 = 0;
3865 operand_types[j].bitfield.disp32 = 1;
3866 break;
3867 }
3868 }
539e75ad
L		 3869 break;
3870 }
539e75ad
L		 3871 }
3872
45664ddb
L		 3873 /* We check register size only if size of operands can be
3874 encoded the canonical way. */
3875 check_register = t->opcode_modifier.w;
c6fb90c8 3876 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 3877 switch (t->operands)
3878 {
3879 case 1:
40fb9820 3880 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 3881 continue;
3882 break;
3883 case 2:
8b38ad71
L		 3884 /* xchg %eax, %eax is a special case. It is an aliase for nop
3885 only in 32bit mode and we can use opcode 0x90. In 64bit
3886 mode, we can't use 0x90 for xchg %eax, %eax since it should
3887 zero-extend %eax to %rax. */
3888 if (flag_code == CODE_64BIT
3889 && t->base_opcode == 0x90
0dfbf9d7
L		 3890 && operand_type_equal (&i.types [0], &acc32)
3891 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 3892 continue;
b6169b20
L		 3893 if (i.swap_operand)
3894 {
3895 /* If we swap operand in encoding, we either match
3896 the next one or reverse direction of operands. */
3897 if (t->opcode_modifier.s)
3898 continue;
3899 else if (t->opcode_modifier.d)
3900 goto check_reverse;
3901 }
3902
29b0f896 3903 case 3:
fa99fab2
L		 3904 /* If we swap operand in encoding, we match the next one. */
3905 if (i.swap_operand && t->opcode_modifier.s)
3906 continue;
f48ff2ae 3907 case 4:
c0f3af97 3908 case 5:
c6fb90c8 3909 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 3910 if (!operand_type_match (overlap0, i.types[0])
3911 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3912 || (check_register
3913 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 3914 operand_types[0],
3915 overlap1, i.types[1],
3916 operand_types[1])))
29b0f896
AM		 3917 {
3918 /* Check if other direction is valid ... */
40fb9820 3919 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 3920 continue;
3921
b6169b20 3922check_reverse:
29b0f896 3923 /* Try reversing direction of operands. */
c6fb90c8
L		 3924 overlap0 = operand_type_and (i.types[0], operand_types[1]);
3925 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 3926 if (!operand_type_match (overlap0, i.types[0])
3927 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3928 || (check_register
3929 && !operand_type_register_match (overlap0,
3930 i.types[0],
3931 operand_types[1],
3932 overlap1,
3933 i.types[1],
3934 operand_types[0])))
29b0f896
AM		 3935 {
3936 /* Does not match either direction. */
3937 continue;
3938 }
3939 /* found_reverse_match holds which of D or FloatDR
3940 we've found. */
40fb9820 3941 if (t->opcode_modifier.d)
8a2ed489 3942 found_reverse_match = Opcode_D;
40fb9820 3943 else if (t->opcode_modifier.floatd)
8a2ed489
L		 3944 found_reverse_match = Opcode_FloatD;
3945 else
3946 found_reverse_match = 0;
40fb9820 3947 if (t->opcode_modifier.floatr)
8a2ed489 3948 found_reverse_match |= Opcode_FloatR;
29b0f896 3949 }
f48ff2ae 3950 else
29b0f896 3951 {
f48ff2ae 3952 /* Found a forward 2 operand match here. */
d1cbb4db
L		 3953 switch (t->operands)
3954 {
c0f3af97
L		 3955 case 5:
3956 overlap4 = operand_type_and (i.types[4],
3957 operand_types[4]);
d1cbb4db 3958 case 4:
c6fb90c8
L		 3959 overlap3 = operand_type_and (i.types[3],
3960 operand_types[3]);
d1cbb4db 3961 case 3:
c6fb90c8
L		 3962 overlap2 = operand_type_and (i.types[2],
3963 operand_types[2]);
d1cbb4db
L		 3964 break;
3965 }
29b0f896 3966
f48ff2ae
L		 3967 switch (t->operands)
3968 {
c0f3af97
L		 3969 case 5:
3970 if (!operand_type_match (overlap4, i.types[4])
3971 || !operand_type_register_match (overlap3,
3972 i.types[3],
3973 operand_types[3],
3974 overlap4,
3975 i.types[4],
3976 operand_types[4]))
3977 continue;
f48ff2ae 3978 case 4:
40fb9820 3979 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 3980 || (check_register
3981 && !operand_type_register_match (overlap2,
3982 i.types[2],
3983 operand_types[2],
3984 overlap3,
3985 i.types[3],
3986 operand_types[3])))
f48ff2ae
L		 3987 continue;
3988 case 3:
3989 /* Here we make use of the fact that there are no
3990 reverse match 3 operand instructions, and all 3
3991 operand instructions only need to be checked for
3992 register consistency between operands 2 and 3. */
40fb9820 3993 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 3994 || (check_register
3995 && !operand_type_register_match (overlap1,
3996 i.types[1],
3997 operand_types[1],
3998 overlap2,
3999 i.types[2],
4000 operand_types[2])))
f48ff2ae
L		 4001 continue;
4002 break;
4003 }
29b0f896 4004 }
f48ff2ae 4005 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 4006 slip through to break. */
4007 }
3629bb00 4008 if (!found_cpu_match)
29b0f896
AM		 4009 {
4010 found_reverse_match = 0;
4011 continue;
4012 }
c0f3af97 4013
29b0f896
AM		 4014 /* We've found a match; break out of loop. */
4015 break;
4016 }
4017
4018 if (t == current_templates->end)
4019 {
4020 /* We found no match. */
95f283e8
L		 4021 if (intel_syntax)
4022 as_bad (_("ambiguous operand size or operands invalid for `%s'"),
4023 current_templates->start->name);
4024 else
4025 as_bad (_("suffix or operands invalid for `%s'"),
4026 current_templates->start->name);
fa99fab2 4027 return NULL;
29b0f896 4028 }
252b5132 4029
29b0f896
AM		 4030 if (!quiet_warnings)
4031 {
4032 if (!intel_syntax
40fb9820
L		 4033 && (i.types[0].bitfield.jumpabsolute
4034 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 4035 {
4036 as_warn (_("indirect %s without `*'"), t->name);
4037 }
4038
40fb9820
L		 4039 if (t->opcode_modifier.isprefix
4040 && t->opcode_modifier.ignoresize)
29b0f896
AM		 4041 {
4042 /* Warn them that a data or address size prefix doesn't
4043 affect assembly of the next line of code. */
4044 as_warn (_("stand-alone `%s' prefix"), t->name);
4045 }
4046 }
4047
4048 /* Copy the template we found. */
4049 i.tm = *t;
539e75ad
L		 4050
4051 if (addr_prefix_disp != -1)
4052 i.tm.operand_types[addr_prefix_disp]
4053 = operand_types[addr_prefix_disp];
4054
29b0f896
AM		 4055 if (found_reverse_match)
4056 {
4057 /* If we found a reverse match we must alter the opcode
4058 direction bit. found_reverse_match holds bits to change
4059 (different for int & float insns). */
4060
4061 i.tm.base_opcode ^= found_reverse_match;
4062
539e75ad
L		 4063 i.tm.operand_types[0] = operand_types[1];
4064 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 4065 }
4066
fa99fab2 4067 return t;
29b0f896
AM		 4068}
4069
4070static int
e3bb37b5 4071check_string (void)
29b0f896 4072{
40fb9820
L		 4073 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
4074 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 4075 {
4076 if (i.seg[0] != NULL && i.seg[0] != &es)
4077 {
a87af027 4078 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 4079 i.tm.name,
a87af027
JB		 4080 mem_op + 1,
4081 register_prefix);
29b0f896
AM		 4082 return 0;
4083 }
4084 /* There's only ever one segment override allowed per instruction.
4085 This instruction possibly has a legal segment override on the
4086 second operand, so copy the segment to where non-string
4087 instructions store it, allowing common code. */
4088 i.seg[0] = i.seg[1];
4089 }
40fb9820 4090 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 4091 {
4092 if (i.seg[1] != NULL && i.seg[1] != &es)
4093 {
a87af027 4094 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 4095 i.tm.name,
a87af027
JB		 4096 mem_op + 2,
4097 register_prefix);
29b0f896
AM		 4098 return 0;
4099 }
4100 }
4101 return 1;
4102}
4103
4104static int
543613e9 4105process_suffix (void)
29b0f896
AM		 4106{
4107 /* If matched instruction specifies an explicit instruction mnemonic
4108 suffix, use it. */
40fb9820
L		 4109 if (i.tm.opcode_modifier.size16)
4110 i.suffix = WORD_MNEM_SUFFIX;
4111 else if (i.tm.opcode_modifier.size32)
4112 i.suffix = LONG_MNEM_SUFFIX;
4113 else if (i.tm.opcode_modifier.size64)
4114 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 4115 else if (i.reg_operands)
4116 {
4117 /* If there's no instruction mnemonic suffix we try to invent one
4118 based on register operands. */
4119 if (!i.suffix)
4120 {
4121 /* We take i.suffix from the last register operand specified,
4122 Destination register type is more significant than source
381d071f
L		 4123 register type. crc32 in SSE4.2 prefers source register
4124 type. */
4125 if (i.tm.base_opcode == 0xf20f38f1)
4126 {
40fb9820
L		 4127 if (i.types[0].bitfield.reg16)
4128 i.suffix = WORD_MNEM_SUFFIX;
4129 else if (i.types[0].bitfield.reg32)
4130 i.suffix = LONG_MNEM_SUFFIX;
4131 else if (i.types[0].bitfield.reg64)
4132 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 4133 }
9344ff29 4134 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 4135 {
40fb9820 4136 if (i.types[0].bitfield.reg8)
20592a94
L		 4137 i.suffix = BYTE_MNEM_SUFFIX;
4138 }
381d071f
L		 4139
4140 if (!i.suffix)
4141 {
4142 int op;
4143
20592a94
L		 4144 if (i.tm.base_opcode == 0xf20f38f1
4145 || i.tm.base_opcode == 0xf20f38f0)
4146 {
4147 /* We have to know the operand size for crc32. */
4148 as_bad (_("ambiguous memory operand size for `%s`"),
4149 i.tm.name);
4150 return 0;
4151 }
4152
381d071f 4153 for (op = i.operands; --op >= 0;)
40fb9820 4154 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 4155 {
40fb9820
L		 4156 if (i.types[op].bitfield.reg8)
4157 {
4158 i.suffix = BYTE_MNEM_SUFFIX;
4159 break;
4160 }
4161 else if (i.types[op].bitfield.reg16)
4162 {
4163 i.suffix = WORD_MNEM_SUFFIX;
4164 break;
4165 }
4166 else if (i.types[op].bitfield.reg32)
4167 {
4168 i.suffix = LONG_MNEM_SUFFIX;
4169 break;
4170 }
4171 else if (i.types[op].bitfield.reg64)
4172 {
4173 i.suffix = QWORD_MNEM_SUFFIX;
4174 break;
4175 }
381d071f
L		 4176 }
4177 }
29b0f896
AM		 4178 }
4179 else if (i.suffix == BYTE_MNEM_SUFFIX)
4180 {
4181 if (!check_byte_reg ())
4182 return 0;
4183 }
4184 else if (i.suffix == LONG_MNEM_SUFFIX)
4185 {
4186 if (!check_long_reg ())
4187 return 0;
4188 }
4189 else if (i.suffix == QWORD_MNEM_SUFFIX)
4190 {
955e1e6a
L		 4191 if (intel_syntax
4192 && i.tm.opcode_modifier.ignoresize
4193 && i.tm.opcode_modifier.no_qsuf)
4194 i.suffix = 0;
4195 else if (!check_qword_reg ())
29b0f896
AM		 4196 return 0;
4197 }
4198 else if (i.suffix == WORD_MNEM_SUFFIX)
4199 {
4200 if (!check_word_reg ())
4201 return 0;
4202 }
c0f3af97
L		 4203 else if (i.suffix == XMMWORD_MNEM_SUFFIX
4204 || i.suffix == YMMWORD_MNEM_SUFFIX)
582d5edd 4205 {
c0f3af97 4206 /* Skip if the instruction has x/y suffix. match_template
582d5edd
L		 4207 should check if it is a valid suffix. */
4208 }
40fb9820 4209 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 4210 /* Do nothing if the instruction is going to ignore the prefix. */
4211 ;
4212 else
4213 abort ();
4214 }
40fb9820 4215 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 4216 && !i.suffix
4217 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 4218 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 4219 {
4220 i.suffix = stackop_size;
4221 }
9306ca4a
JB		 4222 else if (intel_syntax
4223 && !i.suffix
40fb9820
L		 4224 && (i.tm.operand_types[0].bitfield.jumpabsolute
4225 || i.tm.opcode_modifier.jumpbyte
4226 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 4227 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
4228 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 4229 {
4230 switch (flag_code)
4231 {
4232 case CODE_64BIT:
40fb9820 4233 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 4234 {
4235 i.suffix = QWORD_MNEM_SUFFIX;
4236 break;
4237 }
4238 case CODE_32BIT:
40fb9820 4239 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 4240 i.suffix = LONG_MNEM_SUFFIX;
4241 break;
4242 case CODE_16BIT:
40fb9820 4243 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 4244 i.suffix = WORD_MNEM_SUFFIX;
4245 break;
4246 }
4247 }
252b5132 4248
9306ca4a 4249 if (!i.suffix)
29b0f896 4250 {
9306ca4a
JB		 4251 if (!intel_syntax)
4252 {
40fb9820 4253 if (i.tm.opcode_modifier.w)
9306ca4a 4254 {
4eed87de
AM		 4255 as_bad (_("no instruction mnemonic suffix given and "
4256 "no register operands; can't size instruction"));
9306ca4a
JB		 4257 return 0;
4258 }
4259 }
4260 else
4261 {
40fb9820 4262 unsigned int suffixes;
7ab9ffdd 4263
40fb9820
L		 4264 suffixes = !i.tm.opcode_modifier.no_bsuf;
4265 if (!i.tm.opcode_modifier.no_wsuf)
4266 suffixes |= 1 << 1;
4267 if (!i.tm.opcode_modifier.no_lsuf)
4268 suffixes |= 1 << 2;
fc4adea1 4269 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 4270 suffixes |= 1 << 3;
4271 if (!i.tm.opcode_modifier.no_ssuf)
4272 suffixes |= 1 << 4;
4273 if (!i.tm.opcode_modifier.no_qsuf)
4274 suffixes |= 1 << 5;
4275
4276 /* There are more than suffix matches. */
4277 if (i.tm.opcode_modifier.w
9306ca4a 4278 || ((suffixes & (suffixes - 1))
40fb9820
L		 4279 && !i.tm.opcode_modifier.defaultsize
4280 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 4281 {
4282 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4283 return 0;
4284 }
4285 }
29b0f896 4286 }
252b5132 4287
9306ca4a
JB		 4288 /* Change the opcode based on the operand size given by i.suffix;
4289 We don't need to change things for byte insns. */
4290
582d5edd
L		 4291 if (i.suffix
4292 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97
L		 4293 && i.suffix != XMMWORD_MNEM_SUFFIX
4294 && i.suffix != YMMWORD_MNEM_SUFFIX)
29b0f896
AM		 4295 {
4296 /* It's not a byte, select word/dword operation. */
40fb9820 4297 if (i.tm.opcode_modifier.w)
29b0f896 4298 {
40fb9820 4299 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 4300 i.tm.base_opcode |= 8;
4301 else
4302 i.tm.base_opcode |= 1;
4303 }
0f3f3d8b 4304
29b0f896
AM		 4305 /* Now select between word & dword operations via the operand
4306 size prefix, except for instructions that will ignore this
4307 prefix anyway. */
ca61edf2 4308 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 4309 {
ca61edf2
L		 4310 /* The address size override prefix changes the size of the
4311 first operand. */
40fb9820
L		 4312 if ((flag_code == CODE_32BIT
4313 && i.op->regs[0].reg_type.bitfield.reg16)
4314 || (flag_code != CODE_32BIT
4315 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 4316 if (!add_prefix (ADDR_PREFIX_OPCODE))
4317 return 0;
4318 }
4319 else if (i.suffix != QWORD_MNEM_SUFFIX
4320 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 4321 && !i.tm.opcode_modifier.ignoresize
4322 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 4323 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
4324 || (flag_code == CODE_64BIT
40fb9820 4325 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 4326 {
4327 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 4328
40fb9820 4329 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 4330 prefix = ADDR_PREFIX_OPCODE;
252b5132 4331
29b0f896
AM		 4332 if (!add_prefix (prefix))
4333 return 0;
24eab124 4334 }
252b5132 4335
29b0f896
AM		 4336 /* Set mode64 for an operand. */
4337 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 4338 && flag_code == CODE_64BIT
40fb9820 4339 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 4340 {
4341 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 4342 need rex64. cmpxchg8b is also a special case. */
4343 if (! (i.operands == 2
4344 && i.tm.base_opcode == 0x90
4345 && i.tm.extension_opcode == None
0dfbf9d7
L		 4346 && operand_type_equal (&i.types [0], &acc64)
4347 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 4348 && ! (i.operands == 1
4349 && i.tm.base_opcode == 0xfc7
4350 && i.tm.extension_opcode == 1
40fb9820
L		 4351 && !operand_type_check (i.types [0], reg)
4352 && operand_type_check (i.types [0], anymem)))
f6bee062 4353 i.rex |= REX_W;
46e883c5 4354 }
3e73aa7c 4355
29b0f896
AM		 4356 /* Size floating point instruction. */
4357 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 4358 if (i.tm.opcode_modifier.floatmf)
543613e9 4359 i.tm.base_opcode ^= 4;
29b0f896 4360 }
7ecd2f8b 4361
29b0f896
AM		 4362 return 1;
4363}
3e73aa7c 4364
29b0f896 4365static int
543613e9 4366check_byte_reg (void)
29b0f896
AM		 4367{
4368 int op;
543613e9 4369
29b0f896
AM		 4370 for (op = i.operands; --op >= 0;)
4371 {
4372 /* If this is an eight bit register, it's OK. If it's the 16 or
4373 32 bit version of an eight bit register, we will just use the
4374 low portion, and that's OK too. */
40fb9820 4375 if (i.types[op].bitfield.reg8)
29b0f896
AM		 4376 continue;
4377
ca61edf2
L		 4378 /* Don't generate this warning if not needed. */
4379 if (intel_syntax && i.tm.opcode_modifier.byteokintel)
29b0f896
AM		 4380 continue;
4381
9344ff29
L		 4382 /* crc32 doesn't generate this warning. */
4383 if (i.tm.base_opcode == 0xf20f38f0)
4384 continue;
4385
40fb9820
L		 4386 if ((i.types[op].bitfield.reg16
4387 || i.types[op].bitfield.reg32
4388 || i.types[op].bitfield.reg64)
4389 && i.op[op].regs->reg_num < 4)
29b0f896
AM		 4390 {
4391 /* Prohibit these changes in the 64bit mode, since the
4392 lowering is more complicated. */
4393 if (flag_code == CODE_64BIT
40fb9820 4394 && !i.tm.operand_types[op].bitfield.inoutportreg)
29b0f896 4395 {
2ca3ace5
L		 4396 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4397 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4398 i.suffix);
4399 return 0;
4400 }
4401#if REGISTER_WARNINGS
4402 if (!quiet_warnings
40fb9820 4403 && !i.tm.operand_types[op].bitfield.inoutportreg)
a540244d
L		 4404 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4405 register_prefix,
40fb9820 4406 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 4407 ? REGNAM_AL - REGNAM_AX
4408 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 4409 register_prefix,
29b0f896
AM		 4410 i.op[op].regs->reg_name,
4411 i.suffix);
4412#endif
4413 continue;
4414 }
4415 /* Any other register is bad. */
40fb9820
L		 4416 if (i.types[op].bitfield.reg16
4417 || i.types[op].bitfield.reg32
4418 || i.types[op].bitfield.reg64
4419 || i.types[op].bitfield.regmmx
4420 || i.types[op].bitfield.regxmm
c0f3af97 4421 || i.types[op].bitfield.regymm
40fb9820
L		 4422 || i.types[op].bitfield.sreg2
4423 || i.types[op].bitfield.sreg3
4424 || i.types[op].bitfield.control
4425 || i.types[op].bitfield.debug
4426 || i.types[op].bitfield.test
4427 || i.types[op].bitfield.floatreg
4428 || i.types[op].bitfield.floatacc)
29b0f896 4429 {
a540244d
L		 4430 as_bad (_("`%s%s' not allowed with `%s%c'"),
4431 register_prefix,
29b0f896
AM		 4432 i.op[op].regs->reg_name,
4433 i.tm.name,
4434 i.suffix);
4435 return 0;
4436 }
4437 }
4438 return 1;
4439}
4440
4441static int
e3bb37b5 4442check_long_reg (void)
29b0f896
AM		 4443{
4444 int op;
4445
4446 for (op = i.operands; --op >= 0;)
4447 /* Reject eight bit registers, except where the template requires
4448 them. (eg. movzb) */
40fb9820
L		 4449 if (i.types[op].bitfield.reg8
4450 && (i.tm.operand_types[op].bitfield.reg16
4451 || i.tm.operand_types[op].bitfield.reg32
4452 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4453 {
a540244d
L		 4454 as_bad (_("`%s%s' not allowed with `%s%c'"),
4455 register_prefix,
29b0f896
AM		 4456 i.op[op].regs->reg_name,
4457 i.tm.name,
4458 i.suffix);
4459 return 0;
4460 }
4461 /* Warn if the e prefix on a general reg is missing. */
4462 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4463 && i.types[op].bitfield.reg16
4464 && (i.tm.operand_types[op].bitfield.reg32
4465 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4466 {
4467 /* Prohibit these changes in the 64bit mode, since the
4468 lowering is more complicated. */
4469 if (flag_code == CODE_64BIT)
252b5132 4470 {
2ca3ace5
L		 4471 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4472 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4473 i.suffix);
4474 return 0;
252b5132 4475 }
29b0f896
AM		 4476#if REGISTER_WARNINGS
4477 else
a540244d
L		 4478 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4479 register_prefix,
29b0f896 4480 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 4481 register_prefix,
29b0f896
AM		 4482 i.op[op].regs->reg_name,
4483 i.suffix);
4484#endif
252b5132 4485 }
29b0f896 4486 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 4487 else if (i.types[op].bitfield.reg64
4488 && (i.tm.operand_types[op].bitfield.reg32
4489 || i.tm.operand_types[op].bitfield.acc))
252b5132 4490 {
34828aad 4491 if (intel_syntax
ca61edf2 4492 && i.tm.opcode_modifier.toqword
40fb9820 4493 && !i.types[0].bitfield.regxmm)
34828aad 4494 {
ca61edf2 4495 /* Convert to QWORD. We want REX byte. */
34828aad
L		 4496 i.suffix = QWORD_MNEM_SUFFIX;
4497 }
4498 else
4499 {
4500 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4501 register_prefix, i.op[op].regs->reg_name,
4502 i.suffix);
4503 return 0;
4504 }
29b0f896
AM		 4505 }
4506 return 1;
4507}
252b5132 4508
29b0f896 4509static int
e3bb37b5 4510check_qword_reg (void)
29b0f896
AM		 4511{
4512 int op;
252b5132 4513
29b0f896
AM		 4514 for (op = i.operands; --op >= 0; )
4515 /* Reject eight bit registers, except where the template requires
4516 them. (eg. movzb) */
40fb9820
L		 4517 if (i.types[op].bitfield.reg8
4518 && (i.tm.operand_types[op].bitfield.reg16
4519 || i.tm.operand_types[op].bitfield.reg32
4520 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4521 {
a540244d
L		 4522 as_bad (_("`%s%s' not allowed with `%s%c'"),
4523 register_prefix,
29b0f896
AM		 4524 i.op[op].regs->reg_name,
4525 i.tm.name,
4526 i.suffix);
4527 return 0;
4528 }
4529 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 4530 else if ((i.types[op].bitfield.reg16
4531 || i.types[op].bitfield.reg32)
4532 && (i.tm.operand_types[op].bitfield.reg32
4533 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4534 {
4535 /* Prohibit these changes in the 64bit mode, since the
4536 lowering is more complicated. */
34828aad 4537 if (intel_syntax
ca61edf2 4538 && i.tm.opcode_modifier.todword
40fb9820 4539 && !i.types[0].bitfield.regxmm)
34828aad 4540 {
ca61edf2 4541 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 4542 i.suffix = LONG_MNEM_SUFFIX;
4543 }
4544 else
4545 {
4546 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4547 register_prefix, i.op[op].regs->reg_name,
4548 i.suffix);
4549 return 0;
4550 }
252b5132 4551 }
29b0f896
AM		 4552 return 1;
4553}
252b5132 4554
29b0f896 4555static int
e3bb37b5 4556check_word_reg (void)
29b0f896
AM		 4557{
4558 int op;
4559 for (op = i.operands; --op >= 0;)
4560 /* Reject eight bit registers, except where the template requires
4561 them. (eg. movzb) */
40fb9820
L		 4562 if (i.types[op].bitfield.reg8
4563 && (i.tm.operand_types[op].bitfield.reg16
4564 || i.tm.operand_types[op].bitfield.reg32
4565 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4566 {
a540244d
L		 4567 as_bad (_("`%s%s' not allowed with `%s%c'"),
4568 register_prefix,
29b0f896
AM		 4569 i.op[op].regs->reg_name,
4570 i.tm.name,
4571 i.suffix);
4572 return 0;
4573 }
4574 /* Warn if the e prefix on a general reg is present. */
4575 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4576 && i.types[op].bitfield.reg32
4577 && (i.tm.operand_types[op].bitfield.reg16
4578 || i.tm.operand_types[op].bitfield.acc))
252b5132 4579 {
29b0f896
AM		 4580 /* Prohibit these changes in the 64bit mode, since the
4581 lowering is more complicated. */
4582 if (flag_code == CODE_64BIT)
252b5132 4583 {
2ca3ace5
L		 4584 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4585 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4586 i.suffix);
4587 return 0;
252b5132 4588 }
29b0f896
AM		 4589 else
4590#if REGISTER_WARNINGS
a540244d
L		 4591 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4592 register_prefix,
29b0f896 4593 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 4594 register_prefix,
29b0f896
AM		 4595 i.op[op].regs->reg_name,
4596 i.suffix);
4597#endif
4598 }
4599 return 1;
4600}
252b5132 4601
29b0f896 4602static int
40fb9820 4603update_imm (unsigned int j)
29b0f896 4604{
bc0844ae 4605 i386_operand_type overlap = i.types[j];
40fb9820
L		 4606 if ((overlap.bitfield.imm8
4607 || overlap.bitfield.imm8s
4608 || overlap.bitfield.imm16
4609 || overlap.bitfield.imm32
4610 || overlap.bitfield.imm32s
4611 || overlap.bitfield.imm64)
0dfbf9d7
L		 4612 && !operand_type_equal (&overlap, &imm8)
4613 && !operand_type_equal (&overlap, &imm8s)
4614 && !operand_type_equal (&overlap, &imm16)
4615 && !operand_type_equal (&overlap, &imm32)
4616 && !operand_type_equal (&overlap, &imm32s)
4617 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 4618 {
4619 if (i.suffix)
4620 {
40fb9820
L		 4621 i386_operand_type temp;
4622
0dfbf9d7 4623 operand_type_set (&temp, 0);
7ab9ffdd 4624 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 4625 {
4626 temp.bitfield.imm8 = overlap.bitfield.imm8;
4627 temp.bitfield.imm8s = overlap.bitfield.imm8s;
4628 }
4629 else if (i.suffix == WORD_MNEM_SUFFIX)
4630 temp.bitfield.imm16 = overlap.bitfield.imm16;
4631 else if (i.suffix == QWORD_MNEM_SUFFIX)
4632 {
4633 temp.bitfield.imm64 = overlap.bitfield.imm64;
4634 temp.bitfield.imm32s = overlap.bitfield.imm32s;
4635 }
4636 else
4637 temp.bitfield.imm32 = overlap.bitfield.imm32;
4638 overlap = temp;
29b0f896 4639 }
0dfbf9d7
L		 4640 else if (operand_type_equal (&overlap, &imm16_32_32s)
4641 || operand_type_equal (&overlap, &imm16_32)
4642 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 4643 {
40fb9820 4644 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 4645 overlap = imm16;
40fb9820 4646 else
65da13b5 4647 overlap = imm32s;
29b0f896 4648 }
0dfbf9d7
L		 4649 if (!operand_type_equal (&overlap, &imm8)
4650 && !operand_type_equal (&overlap, &imm8s)
4651 && !operand_type_equal (&overlap, &imm16)
4652 && !operand_type_equal (&overlap, &imm32)
4653 && !operand_type_equal (&overlap, &imm32s)
4654 && !operand_type_equal (&overlap, &imm64))
29b0f896 4655 {
4eed87de
AM		 4656 as_bad (_("no instruction mnemonic suffix given; "
4657 "can't determine immediate size"));
29b0f896
AM		 4658 return 0;
4659 }
4660 }
40fb9820 4661 i.types[j] = overlap;
29b0f896 4662
40fb9820
L		 4663 return 1;
4664}
4665
4666static int
4667finalize_imm (void)
4668{
bc0844ae 4669 unsigned int j, n;
29b0f896 4670
bc0844ae
L		 4671 /* Update the first 2 immediate operands. */
4672 n = i.operands > 2 ? 2 : i.operands;
4673 if (n)
4674 {
4675 for (j = 0; j < n; j++)
4676 if (update_imm (j) == 0)
4677 return 0;
40fb9820 4678
bc0844ae
L		 4679 /* The 3rd operand can't be immediate operand. */
4680 gas_assert (operand_type_check (i.types[2], imm) == 0);
4681 }
29b0f896
AM		 4682
4683 return 1;
4684}
4685
c0f3af97
L		 4686static int
4687bad_implicit_operand (int xmm)
4688{
91d6fa6a
NC		 4689 const char *ireg = xmm ? "xmm0" : "ymm0";
4690
c0f3af97
L		 4691 if (intel_syntax)
4692 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 4693 i.tm.name, register_prefix, ireg);
c0f3af97
L		 4694 else
4695 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 4696 i.tm.name, register_prefix, ireg);
c0f3af97
L		 4697 return 0;
4698}
4699
29b0f896 4700static int
e3bb37b5 4701process_operands (void)
29b0f896
AM		 4702{
4703 /* Default segment register this instruction will use for memory
4704 accesses. 0 means unknown. This is only for optimizing out
4705 unnecessary segment overrides. */
4706 const seg_entry *default_seg = 0;
4707
c0f3af97
L		 4708 if (i.tm.opcode_modifier.sse2avx
4709 && (i.tm.opcode_modifier.vexnds
4710 || i.tm.opcode_modifier.vexndd))
29b0f896 4711 {
91d6fa6a
NC		 4712 unsigned int dupl = i.operands;
4713 unsigned int dest = dupl - 1;
9fcfb3d7
L		 4714 unsigned int j;
4715
c0f3af97 4716 /* The destination must be an xmm register. */
9c2799c2 4717 gas_assert (i.reg_operands
91d6fa6a 4718 && MAX_OPERANDS > dupl
7ab9ffdd 4719 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 4720
4721 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 4722 {
c0f3af97 4723 /* The first operand is implicit and must be xmm0. */
9c2799c2 4724 gas_assert (operand_type_equal (&i.types[0], &regxmm));
c0f3af97
L		 4725 if (i.op[0].regs->reg_num != 0)
4726 return bad_implicit_operand (1);
4727
8cd7925b 4728 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 4729 {
4730 /* Keep xmm0 for instructions with VEX prefix and 3
4731 sources. */
4732 goto duplicate;
4733 }
e2ec9d29 4734 else
c0f3af97
L		 4735 {
4736 /* We remove the first xmm0 and keep the number of
4737 operands unchanged, which in fact duplicates the
4738 destination. */
4739 for (j = 1; j < i.operands; j++)
4740 {
4741 i.op[j - 1] = i.op[j];
4742 i.types[j - 1] = i.types[j];
4743 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
4744 }
4745 }
4746 }
4747 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 4748 {
91d6fa6a 4749 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 4750 && (i.tm.opcode_modifier.vexsources
4751 == VEX3SOURCES));
c0f3af97
L		 4752
4753 /* Add the implicit xmm0 for instructions with VEX prefix
4754 and 3 sources. */
4755 for (j = i.operands; j > 0; j--)
4756 {
4757 i.op[j] = i.op[j - 1];
4758 i.types[j] = i.types[j - 1];
4759 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
4760 }
4761 i.op[0].regs
4762 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 4763 i.types[0] = regxmm;
c0f3af97
L		 4764 i.tm.operand_types[0] = regxmm;
4765
4766 i.operands += 2;
4767 i.reg_operands += 2;
4768 i.tm.operands += 2;
4769
91d6fa6a 4770 dupl++;
c0f3af97 4771 dest++;
91d6fa6a
NC		 4772 i.op[dupl] = i.op[dest];
4773 i.types[dupl] = i.types[dest];
4774 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 4775 }
c0f3af97
L		 4776 else
4777 {
4778duplicate:
4779 i.operands++;
4780 i.reg_operands++;
4781 i.tm.operands++;
4782
91d6fa6a
NC		 4783 i.op[dupl] = i.op[dest];
4784 i.types[dupl] = i.types[dest];
4785 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 4786 }
4787
4788 if (i.tm.opcode_modifier.immext)
4789 process_immext ();
4790 }
4791 else if (i.tm.opcode_modifier.firstxmm0)
4792 {
4793 unsigned int j;
4794
4795 /* The first operand is implicit and must be xmm0/ymm0. */
9c2799c2 4796 gas_assert (i.reg_operands
7ab9ffdd
L		 4797 && (operand_type_equal (&i.types[0], &regxmm)
4798 || operand_type_equal (&i.types[0], &regymm)));
c0f3af97
L		 4799 if (i.op[0].regs->reg_num != 0)
4800 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 4801
4802 for (j = 1; j < i.operands; j++)
4803 {
4804 i.op[j - 1] = i.op[j];
4805 i.types[j - 1] = i.types[j];
4806
4807 /* We need to adjust fields in i.tm since they are used by
4808 build_modrm_byte. */
4809 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
4810 }
4811
e2ec9d29
L		 4812 i.operands--;
4813 i.reg_operands--;
e2ec9d29
L		 4814 i.tm.operands--;
4815 }
4816 else if (i.tm.opcode_modifier.regkludge)
4817 {
4818 /* The imul $imm, %reg instruction is converted into
4819 imul $imm, %reg, %reg, and the clr %reg instruction
4820 is converted into xor %reg, %reg. */
4821
4822 unsigned int first_reg_op;
4823
4824 if (operand_type_check (i.types[0], reg))
4825 first_reg_op = 0;
4826 else
4827 first_reg_op = 1;
4828 /* Pretend we saw the extra register operand. */
9c2799c2 4829 gas_assert (i.reg_operands == 1
7ab9ffdd 4830 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 4831 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
4832 i.types[first_reg_op + 1] = i.types[first_reg_op];
4833 i.operands++;
4834 i.reg_operands++;
29b0f896
AM		 4835 }
4836
40fb9820 4837 if (i.tm.opcode_modifier.shortform)
29b0f896 4838 {
40fb9820
L		 4839 if (i.types[0].bitfield.sreg2
4840 || i.types[0].bitfield.sreg3)
29b0f896 4841 {
4eed87de
AM		 4842 if (i.tm.base_opcode == POP_SEG_SHORT
4843 && i.op[0].regs->reg_num == 1)
29b0f896 4844 {
a87af027 4845 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 4846 return 0;
29b0f896 4847 }
4eed87de
AM		 4848 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
4849 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 4850 i.rex |= REX_B;
4eed87de
AM		 4851 }
4852 else
4853 {
7ab9ffdd 4854 /* The register or float register operand is in operand
85f10a01 4855 0 or 1. */
40fb9820 4856 unsigned int op;
7ab9ffdd
L		 4857
4858 if (i.types[0].bitfield.floatreg
4859 || operand_type_check (i.types[0], reg))
4860 op = 0;
4861 else
4862 op = 1;
4eed87de
AM		 4863 /* Register goes in low 3 bits of opcode. */
4864 i.tm.base_opcode |= i.op[op].regs->reg_num;
4865 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 4866 i.rex |= REX_B;
40fb9820 4867 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 4868 {
4eed87de
AM		 4869 /* Warn about some common errors, but press on regardless.
4870 The first case can be generated by gcc (<= 2.8.1). */
4871 if (i.operands == 2)
4872 {
4873 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 4874 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 4875 register_prefix, i.op[!intel_syntax].regs->reg_name,
4876 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 4877 }
4878 else
4879 {
4880 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 4881 as_warn (_("translating to `%s %s%s'"), i.tm.name,
4882 register_prefix, i.op[0].regs->reg_name);
4eed87de 4883 }
29b0f896
AM		 4884 }
4885 }
4886 }
40fb9820 4887 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 4888 {
4889 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 4890 must be put into the modrm byte). Now, we make the modrm and
4891 index base bytes based on all the info we've collected. */
29b0f896
AM		 4892
4893 default_seg = build_modrm_byte ();
4894 }
8a2ed489 4895 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 4896 {
4897 default_seg = &ds;
4898 }
40fb9820 4899 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 4900 {
4901 /* For the string instructions that allow a segment override
4902 on one of their operands, the default segment is ds. */
4903 default_seg = &ds;
4904 }
4905
75178d9d
L		 4906 if (i.tm.base_opcode == 0x8d /* lea */
4907 && i.seg[0]
4908 && !quiet_warnings)
30123838 4909 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 4910
4911 /* If a segment was explicitly specified, and the specified segment
4912 is not the default, use an opcode prefix to select it. If we
4913 never figured out what the default segment is, then default_seg
4914 will be zero at this point, and the specified segment prefix will
4915 always be used. */
29b0f896
AM		 4916 if ((i.seg[0]) && (i.seg[0] != default_seg))
4917 {
4918 if (!add_prefix (i.seg[0]->seg_prefix))
4919 return 0;
4920 }
4921 return 1;
4922}
4923
4924static const seg_entry *
e3bb37b5 4925build_modrm_byte (void)
29b0f896
AM		 4926{
4927 const seg_entry *default_seg = 0;
c0f3af97 4928 unsigned int source, dest;
8cd7925b 4929 int vex_3_sources;
c0f3af97
L		 4930
4931 /* The first operand of instructions with VEX prefix and 3 sources
4932 must be VEX_Imm4. */
8cd7925b 4933 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 4934 if (vex_3_sources)
4935 {
91d6fa6a 4936 unsigned int nds, reg_slot;
4c2c6516 4937 expressionS *exp;
c0f3af97 4938
922d8de8
DR		 4939 if (i.tm.opcode_modifier.veximmext
4940 && i.tm.opcode_modifier.immext)
4941 {
4942 dest = i.operands - 2;
4943 gas_assert (dest == 3);
4944 }
4945 else
91d6fa6a 4946 dest = i.operands - 1;
c0f3af97 4947 nds = dest - 1;
922d8de8 4948
76ba9986
L		 4949 /* This instruction must have 4 register operands
4950 or 3 register operands plus 1 memory operand.
922d8de8
DR		 4951 It must have VexNDS and VexImmExt. */
4952 gas_assert ((i.reg_operands == 4
7ab9ffdd
L		 4953 || (i.reg_operands == 3 && i.mem_operands == 1))
4954 && i.tm.opcode_modifier.vexnds
4955 && i.tm.opcode_modifier.veximmext
922d8de8
DR		 4956 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
4957 || operand_type_equal (&i.tm.operand_types[dest], &regymm)));
c0f3af97 4958
0bfee649
L		 4959 /* Generate an 8bit immediate operand to encode the register
4960 operand. */
4c2c6516 4961 exp = &im_expressions[i.imm_operands++];
0bfee649
L		 4962 i.op[i.operands].imms = exp;
4963 i.types[i.operands] = imm8;
4964 i.operands++;
922d8de8
DR		 4965 /* If VexW1 is set, the first operand is the source and
4966 the second operand is encoded in the immediate operand. */
1ef99a7b 4967 if (i.tm.opcode_modifier.vexw == VEXW1)
922d8de8
DR		 4968 {
4969 source = 0;
91d6fa6a 4970 reg_slot = 1;
922d8de8
DR		 4971 }
4972 else
4973 {
4974 source = 1;
91d6fa6a 4975 reg_slot = 0;
76ba9986 4976 }
91d6fa6a
NC		 4977 gas_assert ((operand_type_equal (&i.tm.operand_types[reg_slot], &regxmm)
4978 || operand_type_equal (&i.tm.operand_types[reg_slot],
76ba9986 4979 &regymm))
922d8de8 4980 && (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
76ba9986 4981 || operand_type_equal (&i.tm.operand_types[nds],
922d8de8 4982 &regymm)));
0bfee649
L		 4983 exp->X_op = O_constant;
4984 exp->X_add_number
91d6fa6a
NC		 4985 = ((i.op[reg_slot].regs->reg_num
4986 + ((i.op[reg_slot].regs->reg_flags & RegRex) ? 8 : 0)) << 4);
dae39acc 4987 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 4988 }
4989 else
4990 source = dest = 0;
29b0f896
AM		 4991
4992 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 4993 implicit registers do not count. If there are 3 register
4994 operands, it must be a instruction with VexNDS. For a
4995 instruction with VexNDD, the destination register is encoded
4996 in VEX prefix. If there are 4 register operands, it must be
4997 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 4998 if (i.mem_operands == 0
4999 && ((i.reg_operands == 2
f88c9eb0
SP		 5000 && !i.tm.opcode_modifier.vexndd
5001 && !i.tm.opcode_modifier.vexlwp)
7ab9ffdd
L		 5002 || (i.reg_operands == 3
5003 && i.tm.opcode_modifier.vexnds)
5004 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 5005 {
cab737b9
L		 5006 switch (i.operands)
5007 {
5008 case 2:
5009 source = 0;
5010 break;
5011 case 3:
c81128dc
L		 5012 /* When there are 3 operands, one of them may be immediate,
5013 which may be the first or the last operand. Otherwise,
c0f3af97
L		 5014 the first operand must be shift count register (cl) or it
5015 is an instruction with VexNDS. */
9c2799c2 5016 gas_assert (i.imm_operands == 1
7ab9ffdd
L		 5017 || (i.imm_operands == 0
5018 && (i.tm.opcode_modifier.vexnds
5019 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 5020 if (operand_type_check (i.types[0], imm)
5021 || i.types[0].bitfield.shiftcount)
5022 source = 1;
5023 else
5024 source = 0;
cab737b9
L		 5025 break;
5026 case 4:
368d64cc
L		 5027 /* When there are 4 operands, the first two must be 8bit
5028 immediate operands. The source operand will be the 3rd
c0f3af97
L		 5029 one.
5030
5031 For instructions with VexNDS, if the first operand
5032 an imm8, the source operand is the 2nd one. If the last
5033 operand is imm8, the source operand is the first one. */
9c2799c2 5034 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 5035 && i.types[0].bitfield.imm8
5036 && i.types[1].bitfield.imm8)
5037 || (i.tm.opcode_modifier.vexnds
5038 && i.imm_operands == 1
5039 && (i.types[0].bitfield.imm8
5040 || i.types[i.operands - 1].bitfield.imm8)));
c0f3af97
L		 5041 if (i.tm.opcode_modifier.vexnds)
5042 {
5043 if (i.types[0].bitfield.imm8)
5044 source = 1;
5045 else
5046 source = 0;
5047 }
5048 else
5049 source = 2;
5050 break;
5051 case 5:
cab737b9
L		 5052 break;
5053 default:
5054 abort ();
5055 }
5056
c0f3af97
L		 5057 if (!vex_3_sources)
5058 {
5059 dest = source + 1;
5060
5061 if (i.tm.opcode_modifier.vexnds)
5062 {
5063 /* For instructions with VexNDS, the register-only
5064 source operand must be XMM or YMM register. It is
fa99fab2
L		 5065 encoded in VEX prefix. We need to clear RegMem bit
5066 before calling operand_type_equal. */
5067 i386_operand_type op = i.tm.operand_types[dest];
5068 op.bitfield.regmem = 0;
c0f3af97 5069 if ((dest + 1) >= i.operands
fa99fab2
L		 5070 || (!operand_type_equal (&op, &regxmm)
5071 && !operand_type_equal (&op, &regymm)))
c0f3af97
L		 5072 abort ();
5073 i.vex.register_specifier = i.op[dest].regs;
5074 dest++;
5075 }
5076 }
29b0f896
AM		 5077
5078 i.rm.mode = 3;
5079 /* One of the register operands will be encoded in the i.tm.reg
5080 field, the other in the combined i.tm.mode and i.tm.regmem
5081 fields. If no form of this instruction supports a memory
5082 destination operand, then we assume the source operand may
5083 sometimes be a memory operand and so we need to store the
5084 destination in the i.rm.reg field. */
40fb9820
L		 5085 if (!i.tm.operand_types[dest].bitfield.regmem
5086 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 5087 {
5088 i.rm.reg = i.op[dest].regs->reg_num;
5089 i.rm.regmem = i.op[source].regs->reg_num;
5090 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5091 i.rex |= REX_R;
29b0f896 5092 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5093 i.rex |= REX_B;
29b0f896
AM		 5094 }
5095 else
5096 {
5097 i.rm.reg = i.op[source].regs->reg_num;
5098 i.rm.regmem = i.op[dest].regs->reg_num;
5099 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5100 i.rex |= REX_B;
29b0f896 5101 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5102 i.rex |= REX_R;
29b0f896 5103 }
161a04f6 5104 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 5105 {
40fb9820
L		 5106 if (!i.types[0].bitfield.control
5107 && !i.types[1].bitfield.control)
c4a530c5 5108 abort ();
161a04f6 5109 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 5110 add_prefix (LOCK_PREFIX_OPCODE);
5111 }
29b0f896
AM		 5112 }
5113 else
5114 { /* If it's not 2 reg operands... */
c0f3af97
L		 5115 unsigned int mem;
5116
29b0f896
AM		 5117 if (i.mem_operands)
5118 {
5119 unsigned int fake_zero_displacement = 0;
99018f42 5120 unsigned int op;
4eed87de 5121
7ab9ffdd
L		 5122 for (op = 0; op < i.operands; op++)
5123 if (operand_type_check (i.types[op], anymem))
5124 break;
7ab9ffdd 5125 gas_assert (op < i.operands);
29b0f896
AM		 5126
5127 default_seg = &ds;
5128
5129 if (i.base_reg == 0)
5130 {
5131 i.rm.mode = 0;
5132 if (!i.disp_operands)
5133 fake_zero_displacement = 1;
5134 if (i.index_reg == 0)
5135 {
5136 /* Operand is just <disp> */
20f0a1fc 5137 if (flag_code == CODE_64BIT)
29b0f896
AM		 5138 {
5139 /* 64bit mode overwrites the 32bit absolute
5140 addressing by RIP relative addressing and
5141 absolute addressing is encoded by one of the
5142 redundant SIB forms. */
5143 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5144 i.sib.base = NO_BASE_REGISTER;
5145 i.sib.index = NO_INDEX_REGISTER;
fc225355 5146 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 5147 ? disp32s : disp32);
20f0a1fc 5148 }
fc225355
L		 5149 else if ((flag_code == CODE_16BIT)
5150 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 5151 {
5152 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 5153 i.types[op] = disp16;
20f0a1fc
NC		 5154 }
5155 else
5156 {
5157 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 5158 i.types[op] = disp32;
29b0f896
AM		 5159 }
5160 }
5161 else /* !i.base_reg && i.index_reg */
5162 {
db51cc60
L		 5163 if (i.index_reg->reg_num == RegEiz
5164 || i.index_reg->reg_num == RegRiz)
5165 i.sib.index = NO_INDEX_REGISTER;
5166 else
5167 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5168 i.sib.base = NO_BASE_REGISTER;
5169 i.sib.scale = i.log2_scale_factor;
5170 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 5171 i.types[op].bitfield.disp8 = 0;
5172 i.types[op].bitfield.disp16 = 0;
5173 i.types[op].bitfield.disp64 = 0;
29b0f896 5174 if (flag_code != CODE_64BIT)
40fb9820
L		 5175 {
5176 /* Must be 32 bit */
5177 i.types[op].bitfield.disp32 = 1;
5178 i.types[op].bitfield.disp32s = 0;
5179 }
29b0f896 5180 else
40fb9820
L		 5181 {
5182 i.types[op].bitfield.disp32 = 0;
5183 i.types[op].bitfield.disp32s = 1;
5184 }
29b0f896 5185 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5186 i.rex |= REX_X;
29b0f896
AM		 5187 }
5188 }
5189 /* RIP addressing for 64bit mode. */
9a04903e
JB		 5190 else if (i.base_reg->reg_num == RegRip ||
5191 i.base_reg->reg_num == RegEip)
29b0f896
AM		 5192 {
5193 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 5194 i.types[op].bitfield.disp8 = 0;
5195 i.types[op].bitfield.disp16 = 0;
5196 i.types[op].bitfield.disp32 = 0;
5197 i.types[op].bitfield.disp32s = 1;
5198 i.types[op].bitfield.disp64 = 0;
71903a11 5199 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 5200 if (! i.disp_operands)
5201 fake_zero_displacement = 1;
29b0f896 5202 }
40fb9820 5203 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896
AM		 5204 {
5205 switch (i.base_reg->reg_num)
5206 {
5207 case 3: /* (%bx) */
5208 if (i.index_reg == 0)
5209 i.rm.regmem = 7;
5210 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5211 i.rm.regmem = i.index_reg->reg_num - 6;
5212 break;
5213 case 5: /* (%bp) */
5214 default_seg = &ss;
5215 if (i.index_reg == 0)
5216 {
5217 i.rm.regmem = 6;
40fb9820 5218 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 5219 {
5220 /* fake (%bp) into 0(%bp) */
40fb9820 5221 i.types[op].bitfield.disp8 = 1;
252b5132 5222 fake_zero_displacement = 1;
29b0f896
AM		 5223 }
5224 }
5225 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5226 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
5227 break;
5228 default: /* (%si) -> 4 or (%di) -> 5 */
5229 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
5230 }
5231 i.rm.mode = mode_from_disp_size (i.types[op]);
5232 }
5233 else /* i.base_reg and 32/64 bit mode */
5234 {
5235 if (flag_code == CODE_64BIT
40fb9820
L		 5236 && operand_type_check (i.types[op], disp))
5237 {
5238 i386_operand_type temp;
0dfbf9d7 5239 operand_type_set (&temp, 0);
40fb9820
L		 5240 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
5241 i.types[op] = temp;
5242 if (i.prefix[ADDR_PREFIX] == 0)
5243 i.types[op].bitfield.disp32s = 1;
5244 else
5245 i.types[op].bitfield.disp32 = 1;
5246 }
20f0a1fc 5247
29b0f896
AM		 5248 i.rm.regmem = i.base_reg->reg_num;
5249 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 5250 i.rex |= REX_B;
29b0f896
AM		 5251 i.sib.base = i.base_reg->reg_num;
5252 /* x86-64 ignores REX prefix bit here to avoid decoder
5253 complications. */
5254 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
5255 {
5256 default_seg = &ss;
5257 if (i.disp_operands == 0)
5258 {
5259 fake_zero_displacement = 1;
40fb9820 5260 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 5261 }
5262 }
5263 else if (i.base_reg->reg_num == ESP_REG_NUM)
5264 {
5265 default_seg = &ss;
5266 }
5267 i.sib.scale = i.log2_scale_factor;
5268 if (i.index_reg == 0)
5269 {
5270 /* <disp>(%esp) becomes two byte modrm with no index
5271 register. We've already stored the code for esp
5272 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5273 Any base register besides %esp will not use the
5274 extra modrm byte. */
5275 i.sib.index = NO_INDEX_REGISTER;
29b0f896
AM		 5276 }
5277 else
5278 {
db51cc60
L		 5279 if (i.index_reg->reg_num == RegEiz
5280 || i.index_reg->reg_num == RegRiz)
5281 i.sib.index = NO_INDEX_REGISTER;
5282 else
5283 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5284 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5285 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5286 i.rex |= REX_X;
29b0f896 5287 }
67a4f2b7
AO		 5288
5289 if (i.disp_operands
5290 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
5291 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
5292 i.rm.mode = 0;
5293 else
5294 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 5295 }
252b5132 5296
29b0f896
AM		 5297 if (fake_zero_displacement)
5298 {
5299 /* Fakes a zero displacement assuming that i.types[op]
5300 holds the correct displacement size. */
5301 expressionS *exp;
5302
9c2799c2 5303 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 5304 exp = &disp_expressions[i.disp_operands++];
5305 i.op[op].disps = exp;
5306 exp->X_op = O_constant;
5307 exp->X_add_number = 0;
5308 exp->X_add_symbol = (symbolS *) 0;
5309 exp->X_op_symbol = (symbolS *) 0;
5310 }
c0f3af97
L		 5311
5312 mem = op;
29b0f896 5313 }
c0f3af97
L		 5314 else
5315 mem = ~0;
252b5132 5316
8c43a48b 5317 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 5318 {
5319 if (operand_type_check (i.types[0], imm))
5320 i.vex.register_specifier = NULL;
5321 else
5322 {
5323 /* VEX.vvvv encodes one of the sources when the first
5324 operand is not an immediate. */
1ef99a7b 5325 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 5326 i.vex.register_specifier = i.op[0].regs;
5327 else
5328 i.vex.register_specifier = i.op[1].regs;
5329 }
5330
5331 /* Destination is a XMM register encoded in the ModRM.reg
5332 and VEX.R bit. */
5333 i.rm.reg = i.op[2].regs->reg_num;
5334 if ((i.op[2].regs->reg_flags & RegRex) != 0)
5335 i.rex |= REX_R;
5336
5337 /* ModRM.rm and VEX.B encodes the other source. */
5338 if (!i.mem_operands)
5339 {
5340 i.rm.mode = 3;
5341
1ef99a7b 5342 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 5343 i.rm.regmem = i.op[1].regs->reg_num;
5344 else
5345 i.rm.regmem = i.op[0].regs->reg_num;
5346
5347 if ((i.op[1].regs->reg_flags & RegRex) != 0)
5348 i.rex |= REX_B;
5349 }
5350 }
5351 else if (i.tm.opcode_modifier.vexlwp)
f88c9eb0
SP		 5352 {
5353 i.vex.register_specifier = i.op[2].regs;
5354 if (!i.mem_operands)
5355 {
5356 i.rm.mode = 3;
5357 i.rm.regmem = i.op[1].regs->reg_num;
5358 if ((i.op[1].regs->reg_flags & RegRex) != 0)
5359 i.rex |= REX_B;
5360 }
5361 }
29b0f896
AM		 5362 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5363 (if any) based on i.tm.extension_opcode. Again, we must be
5364 careful to make sure that segment/control/debug/test/MMX
5365 registers are coded into the i.rm.reg field. */
f88c9eb0 5366 else if (i.reg_operands)
29b0f896 5367 {
99018f42 5368 unsigned int op;
7ab9ffdd
L		 5369 unsigned int vex_reg = ~0;
5370
5371 for (op = 0; op < i.operands; op++)
5372 if (i.types[op].bitfield.reg8
5373 || i.types[op].bitfield.reg16
5374 || i.types[op].bitfield.reg32
5375 || i.types[op].bitfield.reg64
5376 || i.types[op].bitfield.regmmx
5377 || i.types[op].bitfield.regxmm
5378 || i.types[op].bitfield.regymm
5379 || i.types[op].bitfield.sreg2
5380 || i.types[op].bitfield.sreg3
5381 || i.types[op].bitfield.control
5382 || i.types[op].bitfield.debug
5383 || i.types[op].bitfield.test)
5384 break;
c0209578 5385
7ab9ffdd
L		 5386 if (vex_3_sources)
5387 op = dest;
5388 else if (i.tm.opcode_modifier.vexnds)
5389 {
5390 /* For instructions with VexNDS, the register-only
5391 source operand is encoded in VEX prefix. */
5392 gas_assert (mem != (unsigned int) ~0);
c0f3af97 5393
7ab9ffdd 5394 if (op > mem)
c0f3af97 5395 {
7ab9ffdd
L		 5396 vex_reg = op++;
5397 gas_assert (op < i.operands);
c0f3af97
L		 5398 }
5399 else
c0f3af97 5400 {
7ab9ffdd
L		 5401 vex_reg = op + 1;
5402 gas_assert (vex_reg < i.operands);
c0f3af97 5403 }
7ab9ffdd
L		 5404 }
5405 else if (i.tm.opcode_modifier.vexndd)
5406 {
5407 /* For instructions with VexNDD, there should be
5408 no memory operand and the register destination
5409 is encoded in VEX prefix. */
5410 gas_assert (i.mem_operands == 0
5411 && (op + 2) == i.operands);
5412 vex_reg = op + 1;
5413 }
5414 else
5415 gas_assert (op < i.operands);
99018f42 5416
7ab9ffdd
L		 5417 if (vex_reg != (unsigned int) ~0)
5418 {
5419 gas_assert (i.reg_operands == 2);
5420
5421 if (!operand_type_equal (&i.tm.operand_types[vex_reg],
76ba9986 5422 &regxmm)
7ab9ffdd
L		 5423 && !operand_type_equal (&i.tm.operand_types[vex_reg],
5424 &regymm))
5425 abort ();
f88c9eb0 5426
7ab9ffdd
L		 5427 i.vex.register_specifier = i.op[vex_reg].regs;
5428 }
5429
1b9f0c97
L		 5430 /* Don't set OP operand twice. */
5431 if (vex_reg != op)
7ab9ffdd 5432 {
1b9f0c97
L		 5433 /* If there is an extension opcode to put here, the
5434 register number must be put into the regmem field. */
5435 if (i.tm.extension_opcode != None)
5436 {
5437 i.rm.regmem = i.op[op].regs->reg_num;
5438 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5439 i.rex |= REX_B;
5440 }
5441 else
5442 {
5443 i.rm.reg = i.op[op].regs->reg_num;
5444 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5445 i.rex |= REX_R;
5446 }
7ab9ffdd 5447 }
252b5132 5448
29b0f896
AM		 5449 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5450 must set it to 3 to indicate this is a register operand
5451 in the regmem field. */
5452 if (!i.mem_operands)
5453 i.rm.mode = 3;
5454 }
252b5132 5455
29b0f896 5456 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 5457 if (i.tm.extension_opcode != None)
29b0f896
AM		 5458 i.rm.reg = i.tm.extension_opcode;
5459 }
5460 return default_seg;
5461}
252b5132 5462
29b0f896 5463static void
e3bb37b5 5464output_branch (void)
29b0f896
AM		 5465{
5466 char *p;
5467 int code16;
5468 int prefix;
5469 relax_substateT subtype;
5470 symbolS *sym;
5471 offsetT off;
5472
5473 code16 = 0;
5474 if (flag_code == CODE_16BIT)
5475 code16 = CODE16;
5476
5477 prefix = 0;
5478 if (i.prefix[DATA_PREFIX] != 0)
252b5132 5479 {
29b0f896
AM		 5480 prefix = 1;
5481 i.prefixes -= 1;
5482 code16 ^= CODE16;
252b5132 5483 }
29b0f896
AM		 5484 /* Pentium4 branch hints. */
5485 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5486 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 5487 {
29b0f896
AM		 5488 prefix++;
5489 i.prefixes--;
5490 }
5491 if (i.prefix[REX_PREFIX] != 0)
5492 {
5493 prefix++;
5494 i.prefixes--;
2f66722d
AM		 5495 }
5496
29b0f896
AM		 5497 if (i.prefixes != 0 && !intel_syntax)
5498 as_warn (_("skipping prefixes on this instruction"));
5499
5500 /* It's always a symbol; End frag & setup for relax.
5501 Make sure there is enough room in this frag for the largest
5502 instruction we may generate in md_convert_frag. This is 2
5503 bytes for the opcode and room for the prefix and largest
5504 displacement. */
5505 frag_grow (prefix + 2 + 4);
5506 /* Prefix and 1 opcode byte go in fr_fix. */
5507 p = frag_more (prefix + 1);
5508 if (i.prefix[DATA_PREFIX] != 0)
5509 *p++ = DATA_PREFIX_OPCODE;
5510 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
5511 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
5512 *p++ = i.prefix[SEG_PREFIX];
5513 if (i.prefix[REX_PREFIX] != 0)
5514 *p++ = i.prefix[REX_PREFIX];
5515 *p = i.tm.base_opcode;
5516
5517 if ((unsigned char) *p == JUMP_PC_RELATIVE)
5518 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
40fb9820 5519 else if (cpu_arch_flags.bitfield.cpui386)
29b0f896
AM		 5520 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
5521 else
5522 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
5523 subtype |= code16;
3e73aa7c 5524
29b0f896
AM		 5525 sym = i.op[0].disps->X_add_symbol;
5526 off = i.op[0].disps->X_add_number;
3e73aa7c 5527
29b0f896
AM		 5528 if (i.op[0].disps->X_op != O_constant
5529 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 5530 {
29b0f896
AM		 5531 /* Handle complex expressions. */
5532 sym = make_expr_symbol (i.op[0].disps);
5533 off = 0;
5534 }
3e73aa7c 5535
29b0f896
AM		 5536 /* 1 possible extra opcode + 4 byte displacement go in var part.
5537 Pass reloc in fr_var. */
5538 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
5539}
3e73aa7c 5540
29b0f896 5541static void
e3bb37b5 5542output_jump (void)
29b0f896
AM		 5543{
5544 char *p;
5545 int size;
3e02c1cc 5546 fixS *fixP;
29b0f896 5547
40fb9820 5548 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 5549 {
5550 /* This is a loop or jecxz type instruction. */
5551 size = 1;
5552 if (i.prefix[ADDR_PREFIX] != 0)
5553 {
5554 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
5555 i.prefixes -= 1;
5556 }
5557 /* Pentium4 branch hints. */
5558 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5559 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5560 {
5561 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
5562 i.prefixes--;
3e73aa7c
JH		 5563 }
5564 }
29b0f896
AM		 5565 else
5566 {
5567 int code16;
3e73aa7c 5568
29b0f896
AM		 5569 code16 = 0;
5570 if (flag_code == CODE_16BIT)
5571 code16 = CODE16;
3e73aa7c 5572
29b0f896
AM		 5573 if (i.prefix[DATA_PREFIX] != 0)
5574 {
5575 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
5576 i.prefixes -= 1;
5577 code16 ^= CODE16;
5578 }
252b5132 5579
29b0f896
AM		 5580 size = 4;
5581 if (code16)
5582 size = 2;
5583 }
9fcc94b6 5584
29b0f896
AM		 5585 if (i.prefix[REX_PREFIX] != 0)
5586 {
5587 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
5588 i.prefixes -= 1;
5589 }
252b5132 5590
29b0f896
AM		 5591 if (i.prefixes != 0 && !intel_syntax)
5592 as_warn (_("skipping prefixes on this instruction"));
e0890092 5593
29b0f896
AM		 5594 p = frag_more (1 + size);
5595 *p++ = i.tm.base_opcode;
e0890092 5596
3e02c1cc
AM		 5597 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5598 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
5599
5600 /* All jumps handled here are signed, but don't use a signed limit
5601 check for 32 and 16 bit jumps as we want to allow wrap around at
5602 4G and 64k respectively. */
5603 if (size == 1)
5604 fixP->fx_signed = 1;
29b0f896 5605}
e0890092 5606
29b0f896 5607static void
e3bb37b5 5608output_interseg_jump (void)
29b0f896
AM		 5609{
5610 char *p;
5611 int size;
5612 int prefix;
5613 int code16;
252b5132 5614
29b0f896
AM		 5615 code16 = 0;
5616 if (flag_code == CODE_16BIT)
5617 code16 = CODE16;
a217f122 5618
29b0f896
AM		 5619 prefix = 0;
5620 if (i.prefix[DATA_PREFIX] != 0)
5621 {
5622 prefix = 1;
5623 i.prefixes -= 1;
5624 code16 ^= CODE16;
5625 }
5626 if (i.prefix[REX_PREFIX] != 0)
5627 {
5628 prefix++;
5629 i.prefixes -= 1;
5630 }
252b5132 5631
29b0f896
AM		 5632 size = 4;
5633 if (code16)
5634 size = 2;
252b5132 5635
29b0f896
AM		 5636 if (i.prefixes != 0 && !intel_syntax)
5637 as_warn (_("skipping prefixes on this instruction"));
252b5132 5638
29b0f896
AM		 5639 /* 1 opcode; 2 segment; offset */
5640 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 5641
29b0f896
AM		 5642 if (i.prefix[DATA_PREFIX] != 0)
5643 *p++ = DATA_PREFIX_OPCODE;
252b5132 5644
29b0f896
AM		 5645 if (i.prefix[REX_PREFIX] != 0)
5646 *p++ = i.prefix[REX_PREFIX];
252b5132 5647
29b0f896
AM		 5648 *p++ = i.tm.base_opcode;
5649 if (i.op[1].imms->X_op == O_constant)
5650 {
5651 offsetT n = i.op[1].imms->X_add_number;
252b5132 5652
29b0f896
AM		 5653 if (size == 2
5654 && !fits_in_unsigned_word (n)
5655 && !fits_in_signed_word (n))
5656 {
5657 as_bad (_("16-bit jump out of range"));
5658 return;
5659 }
5660 md_number_to_chars (p, n, size);
5661 }
5662 else
5663 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5664 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
5665 if (i.op[0].imms->X_op != O_constant)
5666 as_bad (_("can't handle non absolute segment in `%s'"),
5667 i.tm.name);
5668 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
5669}
a217f122 5670
29b0f896 5671static void
e3bb37b5 5672output_insn (void)
29b0f896 5673{
2bbd9c25
JJ		 5674 fragS *insn_start_frag;
5675 offsetT insn_start_off;
5676
29b0f896
AM		 5677 /* Tie dwarf2 debug info to the address at the start of the insn.
5678 We can't do this after the insn has been output as the current
5679 frag may have been closed off. eg. by frag_var. */
5680 dwarf2_emit_insn (0);
5681
2bbd9c25
JJ		 5682 insn_start_frag = frag_now;
5683 insn_start_off = frag_now_fix ();
5684
29b0f896 5685 /* Output jumps. */
40fb9820 5686 if (i.tm.opcode_modifier.jump)
29b0f896 5687 output_branch ();
40fb9820
L		 5688 else if (i.tm.opcode_modifier.jumpbyte
5689 || i.tm.opcode_modifier.jumpdword)
29b0f896 5690 output_jump ();
40fb9820 5691 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 5692 output_interseg_jump ();
5693 else
5694 {
5695 /* Output normal instructions here. */
5696 char *p;
5697 unsigned char *q;
47465058 5698 unsigned int j;
331d2d0d 5699 unsigned int prefix;
4dffcebc 5700
c0f3af97
L		 5701 /* Since the VEX prefix contains the implicit prefix, we don't
5702 need the explicit prefix. */
5703 if (!i.tm.opcode_modifier.vex)
bc4bd9ab 5704 {
c0f3af97 5705 switch (i.tm.opcode_length)
bc4bd9ab 5706 {
c0f3af97
L		 5707 case 3:
5708 if (i.tm.base_opcode & 0xff000000)
4dffcebc 5709 {
c0f3af97
L		 5710 prefix = (i.tm.base_opcode >> 24) & 0xff;
5711 goto check_prefix;
5712 }
5713 break;
5714 case 2:
5715 if ((i.tm.base_opcode & 0xff0000) != 0)
5716 {
5717 prefix = (i.tm.base_opcode >> 16) & 0xff;
5718 if (i.tm.cpu_flags.bitfield.cpupadlock)
5719 {
4dffcebc 5720check_prefix:
c0f3af97 5721 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 5722 || (i.prefix[REP_PREFIX]
c0f3af97
L		 5723 != REPE_PREFIX_OPCODE))
5724 add_prefix (prefix);
5725 }
5726 else
4dffcebc
L		 5727 add_prefix (prefix);
5728 }
c0f3af97
L		 5729 break;
5730 case 1:
5731 break;
5732 default:
5733 abort ();
bc4bd9ab 5734 }
c0f3af97
L		 5735
5736 /* The prefix bytes. */
5737 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
5738 if (*q)
5739 FRAG_APPEND_1_CHAR (*q);
0f10071e 5740 }
252b5132 5741
c0f3af97
L		 5742 if (i.tm.opcode_modifier.vex)
5743 {
5744 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
5745 if (*q)
5746 switch (j)
5747 {
5748 case REX_PREFIX:
5749 /* REX byte is encoded in VEX prefix. */
5750 break;
5751 case SEG_PREFIX:
5752 case ADDR_PREFIX:
5753 FRAG_APPEND_1_CHAR (*q);
5754 break;
5755 default:
5756 /* There should be no other prefixes for instructions
5757 with VEX prefix. */
5758 abort ();
5759 }
5760
5761 /* Now the VEX prefix. */
5762 p = frag_more (i.vex.length);
5763 for (j = 0; j < i.vex.length; j++)
5764 p[j] = i.vex.bytes[j];
5765 }
252b5132 5766
29b0f896 5767 /* Now the opcode; be careful about word order here! */
4dffcebc 5768 if (i.tm.opcode_length == 1)
29b0f896
AM		 5769 {
5770 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5771 }
5772 else
5773 {
4dffcebc 5774 switch (i.tm.opcode_length)
331d2d0d 5775 {
4dffcebc 5776 case 3:
331d2d0d
L		 5777 p = frag_more (3);
5778 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 5779 break;
5780 case 2:
5781 p = frag_more (2);
5782 break;
5783 default:
5784 abort ();
5785 break;
331d2d0d 5786 }
0f10071e 5787
29b0f896
AM		 5788 /* Put out high byte first: can't use md_number_to_chars! */
5789 *p++ = (i.tm.base_opcode >> 8) & 0xff;
5790 *p = i.tm.base_opcode & 0xff;
5791 }
3e73aa7c 5792
29b0f896 5793 /* Now the modrm byte and sib byte (if present). */
40fb9820 5794 if (i.tm.opcode_modifier.modrm)
29b0f896 5795 {
4a3523fa
L		 5796 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
5797 | i.rm.reg << 3
5798 | i.rm.mode << 6));
29b0f896
AM		 5799 /* If i.rm.regmem == ESP (4)
5800 && i.rm.mode != (Register mode)
5801 && not 16 bit
5802 ==> need second modrm byte. */
5803 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
5804 && i.rm.mode != 3
40fb9820 5805 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 5806 FRAG_APPEND_1_CHAR ((i.sib.base << 0
5807 | i.sib.index << 3
5808 | i.sib.scale << 6));
29b0f896 5809 }
3e73aa7c 5810
29b0f896 5811 if (i.disp_operands)
2bbd9c25 5812 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 5813
29b0f896 5814 if (i.imm_operands)
2bbd9c25 5815 output_imm (insn_start_frag, insn_start_off);
29b0f896 5816 }
252b5132 5817
29b0f896
AM		 5818#ifdef DEBUG386
5819 if (flag_debug)
5820 {
7b81dfbb 5821 pi ("" /*line*/, &i);
29b0f896
AM		 5822 }
5823#endif /* DEBUG386 */
5824}
252b5132 5825
e205caa7
L		 5826/* Return the size of the displacement operand N. */
5827
5828static int
5829disp_size (unsigned int n)
5830{
5831 int size = 4;
40fb9820
L		 5832 if (i.types[n].bitfield.disp64)
5833 size = 8;
5834 else if (i.types[n].bitfield.disp8)
5835 size = 1;
5836 else if (i.types[n].bitfield.disp16)
5837 size = 2;
e205caa7
L		 5838 return size;
5839}
5840
5841/* Return the size of the immediate operand N. */
5842
5843static int
5844imm_size (unsigned int n)
5845{
5846 int size = 4;
40fb9820
L		 5847 if (i.types[n].bitfield.imm64)
5848 size = 8;
5849 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
5850 size = 1;
5851 else if (i.types[n].bitfield.imm16)
5852 size = 2;
e205caa7
L		 5853 return size;
5854}
5855
29b0f896 5856static void
64e74474 5857output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 5858{
5859 char *p;
5860 unsigned int n;
252b5132 5861
29b0f896
AM		 5862 for (n = 0; n < i.operands; n++)
5863 {
40fb9820 5864 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 5865 {
5866 if (i.op[n].disps->X_op == O_constant)
5867 {
e205caa7 5868 int size = disp_size (n);
29b0f896 5869 offsetT val;
252b5132 5870
29b0f896
AM		 5871 val = offset_in_range (i.op[n].disps->X_add_number,
5872 size);
5873 p = frag_more (size);
5874 md_number_to_chars (p, val, size);
5875 }
5876 else
5877 {
f86103b7 5878 enum bfd_reloc_code_real reloc_type;
e205caa7 5879 int size = disp_size (n);
40fb9820 5880 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 5881 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
5882
e205caa7 5883 /* We can't have 8 bit displacement here. */
9c2799c2 5884 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 5885
29b0f896
AM		 5886 /* The PC relative address is computed relative
5887 to the instruction boundary, so in case immediate
5888 fields follows, we need to adjust the value. */
5889 if (pcrel && i.imm_operands)
5890 {
29b0f896 5891 unsigned int n1;
e205caa7 5892 int sz = 0;
252b5132 5893
29b0f896 5894 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 5895 if (operand_type_check (i.types[n1], imm))
252b5132 5896 {
e205caa7
L		 5897 /* Only one immediate is allowed for PC
5898 relative address. */
9c2799c2 5899 gas_assert (sz == 0);
e205caa7
L		 5900 sz = imm_size (n1);
5901 i.op[n].disps->X_add_number -= sz;
252b5132 5902 }
29b0f896 5903 /* We should find the immediate. */
9c2799c2 5904 gas_assert (sz != 0);
29b0f896 5905 }
520dc8e8 5906
29b0f896 5907 p = frag_more (size);
2bbd9c25 5908 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 5909 if (GOT_symbol
2bbd9c25 5910 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 5911 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 5912 || reloc_type == BFD_RELOC_X86_64_32S
5913 || (reloc_type == BFD_RELOC_64
5914 && object_64bit))
d6ab8113
JB		 5915 && (i.op[n].disps->X_op == O_symbol
5916 || (i.op[n].disps->X_op == O_add
5917 && ((symbol_get_value_expression
5918 (i.op[n].disps->X_op_symbol)->X_op)
5919 == O_subtract))))
5920 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 5921 {
5922 offsetT add;
5923
5924 if (insn_start_frag == frag_now)
5925 add = (p - frag_now->fr_literal) - insn_start_off;
5926 else
5927 {
5928 fragS *fr;
5929
5930 add = insn_start_frag->fr_fix - insn_start_off;
5931 for (fr = insn_start_frag->fr_next;
5932 fr && fr != frag_now; fr = fr->fr_next)
5933 add += fr->fr_fix;
5934 add += p - frag_now->fr_literal;
5935 }
5936
4fa24527 5937 if (!object_64bit)
7b81dfbb
AJ		 5938 {
5939 reloc_type = BFD_RELOC_386_GOTPC;
5940 i.op[n].imms->X_add_number += add;
5941 }
5942 else if (reloc_type == BFD_RELOC_64)
5943 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 5944 else
7b81dfbb
AJ		 5945 /* Don't do the adjustment for x86-64, as there
5946 the pcrel addressing is relative to the _next_
5947 insn, and that is taken care of in other code. */
d6ab8113 5948 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 5949 }
062cd5e7 5950 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 5951 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 5952 }
5953 }
5954 }
5955}
252b5132 5956
29b0f896 5957static void
64e74474 5958output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 5959{
5960 char *p;
5961 unsigned int n;
252b5132 5962
29b0f896
AM		 5963 for (n = 0; n < i.operands; n++)
5964 {
40fb9820 5965 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 5966 {
5967 if (i.op[n].imms->X_op == O_constant)
5968 {
e205caa7 5969 int size = imm_size (n);
29b0f896 5970 offsetT val;
b4cac588 5971
29b0f896
AM		 5972 val = offset_in_range (i.op[n].imms->X_add_number,
5973 size);
5974 p = frag_more (size);
5975 md_number_to_chars (p, val, size);
5976 }
5977 else
5978 {
5979 /* Not absolute_section.
5980 Need a 32-bit fixup (don't support 8bit
5981 non-absolute imms). Try to support other
5982 sizes ... */
f86103b7 5983 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 5984 int size = imm_size (n);
5985 int sign;
29b0f896 5986
40fb9820 5987 if (i.types[n].bitfield.imm32s
a7d61044 5988 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 5989 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 5990 sign = 1;
e205caa7
L		 5991 else
5992 sign = 0;
520dc8e8 5993
29b0f896
AM		 5994 p = frag_more (size);
5995 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 5996
2bbd9c25
JJ		 5997 /* This is tough to explain. We end up with this one if we
5998 * have operands that look like
5999 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6000 * obtain the absolute address of the GOT, and it is strongly
6001 * preferable from a performance point of view to avoid using
6002 * a runtime relocation for this. The actual sequence of
6003 * instructions often look something like:
6004 *
6005 * call .L66
6006 * .L66:
6007 * popl %ebx
6008 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6009 *
6010 * The call and pop essentially return the absolute address
6011 * of the label .L66 and store it in %ebx. The linker itself
6012 * will ultimately change the first operand of the addl so
6013 * that %ebx points to the GOT, but to keep things simple, the
6014 * .o file must have this operand set so that it generates not
6015 * the absolute address of .L66, but the absolute address of
6016 * itself. This allows the linker itself simply treat a GOTPC
6017 * relocation as asking for a pcrel offset to the GOT to be
6018 * added in, and the addend of the relocation is stored in the
6019 * operand field for the instruction itself.
6020 *
6021 * Our job here is to fix the operand so that it would add
6022 * the correct offset so that %ebx would point to itself. The
6023 * thing that is tricky is that .-.L66 will point to the
6024 * beginning of the instruction, so we need to further modify
6025 * the operand so that it will point to itself. There are
6026 * other cases where you have something like:
6027 *
6028 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6029 *
6030 * and here no correction would be required. Internally in
6031 * the assembler we treat operands of this form as not being
6032 * pcrel since the '.' is explicitly mentioned, and I wonder
6033 * whether it would simplify matters to do it this way. Who
6034 * knows. In earlier versions of the PIC patches, the
6035 * pcrel_adjust field was used to store the correction, but
6036 * since the expression is not pcrel, I felt it would be
6037 * confusing to do it this way. */
6038
d6ab8113 6039 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6040 || reloc_type == BFD_RELOC_X86_64_32S
6041 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 6042 && GOT_symbol
6043 && GOT_symbol == i.op[n].imms->X_add_symbol
6044 && (i.op[n].imms->X_op == O_symbol
6045 || (i.op[n].imms->X_op == O_add
6046 && ((symbol_get_value_expression
6047 (i.op[n].imms->X_op_symbol)->X_op)
6048 == O_subtract))))
6049 {
2bbd9c25
JJ		 6050 offsetT add;
6051
6052 if (insn_start_frag == frag_now)
6053 add = (p - frag_now->fr_literal) - insn_start_off;
6054 else
6055 {
6056 fragS *fr;
6057
6058 add = insn_start_frag->fr_fix - insn_start_off;
6059 for (fr = insn_start_frag->fr_next;
6060 fr && fr != frag_now; fr = fr->fr_next)
6061 add += fr->fr_fix;
6062 add += p - frag_now->fr_literal;
6063 }
6064
4fa24527 6065 if (!object_64bit)
d6ab8113 6066 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 6067 else if (size == 4)
d6ab8113 6068 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 6069 else if (size == 8)
6070 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 6071 i.op[n].imms->X_add_number += add;
29b0f896 6072 }
29b0f896
AM		 6073 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6074 i.op[n].imms, 0, reloc_type);
6075 }
6076 }
6077 }
252b5132
RH		 6078}
6079\f
d182319b
JB		 6080/* x86_cons_fix_new is called via the expression parsing code when a
6081 reloc is needed. We use this hook to get the correct .got reloc. */
6082static enum bfd_reloc_code_real got_reloc = NO_RELOC;
6083static int cons_sign = -1;
6084
6085void
e3bb37b5 6086x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 6087 expressionS *exp)
d182319b
JB		 6088{
6089 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
6090
6091 got_reloc = NO_RELOC;
6092
6093#ifdef TE_PE
6094 if (exp->X_op == O_secrel)
6095 {
6096 exp->X_op = O_symbol;
6097 r = BFD_RELOC_32_SECREL;
6098 }
6099#endif
6100
6101 fix_new_exp (frag, off, len, exp, 0, r);
6102}
6103
718ddfc0
JB		 6104#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6105# define lex_got(reloc, adjust, types) NULL
6106#else
f3c180ae
AM		 6107/* Parse operands of the form
6108 <symbol>@GOTOFF+<nnn>
6109 and similar .plt or .got references.
6110
6111 If we find one, set up the correct relocation in RELOC and copy the
6112 input string, minus the `@GOTOFF' into a malloc'd buffer for
6113 parsing by the calling routine. Return this buffer, and if ADJUST
6114 is non-null set it to the length of the string we removed from the
6115 input line. Otherwise return NULL. */
6116static char *
91d6fa6a 6117lex_got (enum bfd_reloc_code_real *rel,
64e74474 6118 int *adjust,
40fb9820 6119 i386_operand_type *types)
f3c180ae 6120{
7b81dfbb
AJ		 6121 /* Some of the relocations depend on the size of what field is to
6122 be relocated. But in our callers i386_immediate and i386_displacement
6123 we don't yet know the operand size (this will be set by insn
6124 matching). Hence we record the word32 relocation here,
6125 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 6126 static const struct {
6127 const char *str;
4fa24527 6128 const enum bfd_reloc_code_real rel[2];
40fb9820 6129 const i386_operand_type types64;
f3c180ae 6130 } gotrel[] = {
1e9cc1c2 6131 { "PLTOFF", { _dummy_first_bfd_reloc_code_real,
4eed87de 6132 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 6133 OPERAND_TYPE_IMM64 },
4eed87de
AM		 6134 { "PLT", { BFD_RELOC_386_PLT32,
6135 BFD_RELOC_X86_64_PLT32 },
40fb9820 6136 OPERAND_TYPE_IMM32_32S_DISP32 },
1e9cc1c2 6137 { "GOTPLT", { _dummy_first_bfd_reloc_code_real,
4eed87de 6138 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 6139 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 6140 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
6141 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 6142 OPERAND_TYPE_IMM64_DISP64 },
1e9cc1c2 6143 { "GOTPCREL", { _dummy_first_bfd_reloc_code_real,
4eed87de 6144 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 6145 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6146 { "TLSGD", { BFD_RELOC_386_TLS_GD,
6147 BFD_RELOC_X86_64_TLSGD },
40fb9820 6148 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de 6149 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
1e9cc1c2 6150 _dummy_first_bfd_reloc_code_real },
40fb9820 6151 OPERAND_TYPE_NONE },
1e9cc1c2 6152 { "TLSLD", { _dummy_first_bfd_reloc_code_real,
4eed87de 6153 BFD_RELOC_X86_64_TLSLD },
40fb9820 6154 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6155 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
6156 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 6157 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6158 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
6159 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 6160 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de 6161 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
1e9cc1c2 6162 _dummy_first_bfd_reloc_code_real },
40fb9820 6163 OPERAND_TYPE_NONE },
4eed87de
AM		 6164 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
6165 BFD_RELOC_X86_64_DTPOFF32 },
7ab9ffdd 6166
40fb9820 6167 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de 6168 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
1e9cc1c2 6169 _dummy_first_bfd_reloc_code_real },
40fb9820 6170 OPERAND_TYPE_NONE },
4eed87de 6171 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
1e9cc1c2 6172 _dummy_first_bfd_reloc_code_real },
40fb9820 6173 OPERAND_TYPE_NONE },
4eed87de
AM		 6174 { "GOT", { BFD_RELOC_386_GOT32,
6175 BFD_RELOC_X86_64_GOT32 },
40fb9820 6176 OPERAND_TYPE_IMM32_32S_64_DISP32 },
4eed87de
AM		 6177 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
6178 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 6179 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6180 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
6181 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 6182 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 6183 };
6184 char *cp;
6185 unsigned int j;
6186
718ddfc0
JB		 6187 if (!IS_ELF)
6188 return NULL;
6189
f3c180ae 6190 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 6191 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 6192 return NULL;
6193
47465058 6194 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae
AM		 6195 {
6196 int len;
6197
6198 len = strlen (gotrel[j].str);
28f81592 6199 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 6200 {
4fa24527 6201 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 6202 {
28f81592
AM		 6203 int first, second;
6204 char *tmpbuf, *past_reloc;
f3c180ae 6205
91d6fa6a 6206 *rel = gotrel[j].rel[object_64bit];
28f81592
AM		 6207 if (adjust)
6208 *adjust = len;
f3c180ae 6209
3956db08
JB		 6210 if (types)
6211 {
6212 if (flag_code != CODE_64BIT)
40fb9820
L		 6213 {
6214 types->bitfield.imm32 = 1;
6215 types->bitfield.disp32 = 1;
6216 }
3956db08
JB		 6217 else
6218 *types = gotrel[j].types64;
6219 }
6220
f3c180ae
AM		 6221 if (GOT_symbol == NULL)
6222 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
6223
28f81592 6224 /* The length of the first part of our input line. */
f3c180ae 6225 first = cp - input_line_pointer;
28f81592
AM		 6226
6227 /* The second part goes from after the reloc token until
67c11a9b 6228 (and including) an end_of_line char or comma. */
28f81592 6229 past_reloc = cp + 1 + len;
67c11a9b
AM		 6230 cp = past_reloc;
6231 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
6232 ++cp;
6233 second = cp + 1 - past_reloc;
28f81592
AM		 6234
6235 /* Allocate and copy string. The trailing NUL shouldn't
6236 be necessary, but be safe. */
1e9cc1c2 6237 tmpbuf = (char *) xmalloc (first + second + 2);
f3c180ae 6238 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 6239 if (second != 0 && *past_reloc != ' ')
6240 /* Replace the relocation token with ' ', so that
6241 errors like foo@GOTOFF1 will be detected. */
6242 tmpbuf[first++] = ' ';
6243 memcpy (tmpbuf + first, past_reloc, second);
6244 tmpbuf[first + second] = '\0';
f3c180ae
AM		 6245 return tmpbuf;
6246 }
6247
4fa24527
JB		 6248 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6249 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 6250 return NULL;
6251 }
6252 }
6253
6254 /* Might be a symbol version string. Don't as_bad here. */
6255 return NULL;
6256}
6257
f3c180ae 6258void
e3bb37b5 6259x86_cons (expressionS *exp, int size)
f3c180ae 6260{
ee86248c
JB		 6261 intel_syntax = -intel_syntax;
6262
4fa24527 6263 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 6264 {
6265 /* Handle @GOTOFF and the like in an expression. */
6266 char *save;
6267 char *gotfree_input_line;
6268 int adjust;
6269
6270 save = input_line_pointer;
3956db08 6271 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 6272 if (gotfree_input_line)
6273 input_line_pointer = gotfree_input_line;
6274
6275 expression (exp);
6276
6277 if (gotfree_input_line)
6278 {
6279 /* expression () has merrily parsed up to the end of line,
6280 or a comma - in the wrong buffer. Transfer how far
6281 input_line_pointer has moved to the right buffer. */
6282 input_line_pointer = (save
6283 + (input_line_pointer - gotfree_input_line)
6284 + adjust);
6285 free (gotfree_input_line);
3992d3b7
AM		 6286 if (exp->X_op == O_constant
6287 || exp->X_op == O_absent
6288 || exp->X_op == O_illegal
6289 || exp->X_op == O_register
6290 || exp->X_op == O_big)
6291 {
6292 char c = *input_line_pointer;
6293 *input_line_pointer = 0;
6294 as_bad (_("missing or invalid expression `%s'"), save);
6295 *input_line_pointer = c;
6296 }
f3c180ae
AM		 6297 }
6298 }
6299 else
6300 expression (exp);
ee86248c
JB		 6301
6302 intel_syntax = -intel_syntax;
6303
6304 if (intel_syntax)
6305 i386_intel_simplify (exp);
f3c180ae
AM		 6306}
6307#endif
6308
9f32dd5b
L		 6309static void
6310signed_cons (int size)
6482c264 6311{
d182319b
JB		 6312 if (flag_code == CODE_64BIT)
6313 cons_sign = 1;
6314 cons (size);
6315 cons_sign = -1;
6482c264
NC		 6316}
6317
d182319b 6318#ifdef TE_PE
6482c264
NC		 6319static void
6320pe_directive_secrel (dummy)
6321 int dummy ATTRIBUTE_UNUSED;
6322{
6323 expressionS exp;
6324
6325 do
6326 {
6327 expression (&exp);
6328 if (exp.X_op == O_symbol)
6329 exp.X_op = O_secrel;
6330
6331 emit_expr (&exp, 4);
6332 }
6333 while (*input_line_pointer++ == ',');
6334
6335 input_line_pointer--;
6336 demand_empty_rest_of_line ();
6337}
6482c264
NC		 6338#endif
6339
252b5132 6340static int
70e41ade 6341i386_immediate (char *imm_start)
252b5132
RH		 6342{
6343 char *save_input_line_pointer;
f3c180ae 6344 char *gotfree_input_line;
252b5132 6345 segT exp_seg = 0;
47926f60 6346 expressionS *exp;
40fb9820
L		 6347 i386_operand_type types;
6348
0dfbf9d7 6349 operand_type_set (&types, ~0);
252b5132
RH		 6350
6351 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
6352 {
31b2323c
L		 6353 as_bad (_("at most %d immediate operands are allowed"),
6354 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 6355 return 0;
6356 }
6357
6358 exp = &im_expressions[i.imm_operands++];
520dc8e8 6359 i.op[this_operand].imms = exp;
252b5132
RH		 6360
6361 if (is_space_char (*imm_start))
6362 ++imm_start;
6363
6364 save_input_line_pointer = input_line_pointer;
6365 input_line_pointer = imm_start;
6366
3956db08 6367 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6368 if (gotfree_input_line)
6369 input_line_pointer = gotfree_input_line;
252b5132
RH		 6370
6371 exp_seg = expression (exp);
6372
83183c0c 6373 SKIP_WHITESPACE ();
252b5132 6374 if (*input_line_pointer)
f3c180ae 6375 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 6376
6377 input_line_pointer = save_input_line_pointer;
f3c180ae 6378 if (gotfree_input_line)
ee86248c
JB		 6379 {
6380 free (gotfree_input_line);
6381
6382 if (exp->X_op == O_constant || exp->X_op == O_register)
6383 exp->X_op = O_illegal;
6384 }
6385
6386 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
6387}
252b5132 6388
ee86248c
JB		 6389static int
6390i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6391 i386_operand_type types, const char *imm_start)
6392{
6393 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 6394 {
313c53d1
L		 6395 if (imm_start)
6396 as_bad (_("missing or invalid immediate expression `%s'"),
6397 imm_start);
3992d3b7 6398 return 0;
252b5132 6399 }
3e73aa7c 6400 else if (exp->X_op == O_constant)
252b5132 6401 {
47926f60 6402 /* Size it properly later. */
40fb9820 6403 i.types[this_operand].bitfield.imm64 = 1;
3e73aa7c 6404 /* If BFD64, sign extend val. */
4eed87de
AM		 6405 if (!use_rela_relocations
6406 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
6407 exp->X_add_number
6408 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 6409 }
4c63da97 6410#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 6411 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 6412 && exp_seg != absolute_section
47926f60 6413 && exp_seg != text_section
24eab124
AM		 6414 && exp_seg != data_section
6415 && exp_seg != bss_section
6416 && exp_seg != undefined_section
f86103b7 6417 && !bfd_is_com_section (exp_seg))
252b5132 6418 {
d0b47220 6419 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 6420 return 0;
6421 }
6422#endif
bb8f5920
L		 6423 else if (!intel_syntax && exp->X_op == O_register)
6424 {
313c53d1
L		 6425 if (imm_start)
6426 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 6427 return 0;
6428 }
252b5132
RH		 6429 else
6430 {
6431 /* This is an address. The size of the address will be
24eab124 6432 determined later, depending on destination register,
3e73aa7c 6433 suffix, or the default for the section. */
40fb9820
L		 6434 i.types[this_operand].bitfield.imm8 = 1;
6435 i.types[this_operand].bitfield.imm16 = 1;
6436 i.types[this_operand].bitfield.imm32 = 1;
6437 i.types[this_operand].bitfield.imm32s = 1;
6438 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 6439 i.types[this_operand] = operand_type_and (i.types[this_operand],
6440 types);
252b5132
RH		 6441 }
6442
6443 return 1;
6444}
6445
551c1ca1 6446static char *
e3bb37b5 6447i386_scale (char *scale)
252b5132 6448{
551c1ca1
AM		 6449 offsetT val;
6450 char *save = input_line_pointer;
252b5132 6451
551c1ca1
AM		 6452 input_line_pointer = scale;
6453 val = get_absolute_expression ();
6454
6455 switch (val)
252b5132 6456 {
551c1ca1 6457 case 1:
252b5132
RH		 6458 i.log2_scale_factor = 0;
6459 break;
551c1ca1 6460 case 2:
252b5132
RH		 6461 i.log2_scale_factor = 1;
6462 break;
551c1ca1 6463 case 4:
252b5132
RH		 6464 i.log2_scale_factor = 2;
6465 break;
551c1ca1 6466 case 8:
252b5132
RH		 6467 i.log2_scale_factor = 3;
6468 break;
6469 default:
a724f0f4
JB		 6470 {
6471 char sep = *input_line_pointer;
6472
6473 *input_line_pointer = '\0';
6474 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6475 scale);
6476 *input_line_pointer = sep;
6477 input_line_pointer = save;
6478 return NULL;
6479 }
252b5132 6480 }
29b0f896 6481 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 6482 {
6483 as_warn (_("scale factor of %d without an index register"),
24eab124 6484 1 << i.log2_scale_factor);
252b5132 6485 i.log2_scale_factor = 0;
252b5132 6486 }
551c1ca1
AM		 6487 scale = input_line_pointer;
6488 input_line_pointer = save;
6489 return scale;
252b5132
RH		 6490}
6491
252b5132 6492static int
e3bb37b5 6493i386_displacement (char *disp_start, char *disp_end)
252b5132 6494{
29b0f896 6495 expressionS *exp;
252b5132
RH		 6496 segT exp_seg = 0;
6497 char *save_input_line_pointer;
f3c180ae 6498 char *gotfree_input_line;
40fb9820
L		 6499 int override;
6500 i386_operand_type bigdisp, types = anydisp;
3992d3b7 6501 int ret;
252b5132 6502
31b2323c
L		 6503 if (i.disp_operands == MAX_MEMORY_OPERANDS)
6504 {
6505 as_bad (_("at most %d displacement operands are allowed"),
6506 MAX_MEMORY_OPERANDS);
6507 return 0;
6508 }
6509
0dfbf9d7 6510 operand_type_set (&bigdisp, 0);
40fb9820
L		 6511 if ((i.types[this_operand].bitfield.jumpabsolute)
6512 || (!current_templates->start->opcode_modifier.jump
6513 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 6514 {
40fb9820 6515 bigdisp.bitfield.disp32 = 1;
e05278af 6516 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 6517 if (flag_code == CODE_64BIT)
6518 {
6519 if (!override)
6520 {
6521 bigdisp.bitfield.disp32s = 1;
6522 bigdisp.bitfield.disp64 = 1;
6523 }
6524 }
6525 else if ((flag_code == CODE_16BIT) ^ override)
6526 {
6527 bigdisp.bitfield.disp32 = 0;
6528 bigdisp.bitfield.disp16 = 1;
6529 }
e05278af
JB		 6530 }
6531 else
6532 {
6533 /* For PC-relative branches, the width of the displacement
6534 is dependent upon data size, not address size. */
e05278af 6535 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 6536 if (flag_code == CODE_64BIT)
6537 {
6538 if (override || i.suffix == WORD_MNEM_SUFFIX)
6539 bigdisp.bitfield.disp16 = 1;
6540 else
6541 {
6542 bigdisp.bitfield.disp32 = 1;
6543 bigdisp.bitfield.disp32s = 1;
6544 }
6545 }
6546 else
e05278af
JB		 6547 {
6548 if (!override)
6549 override = (i.suffix == (flag_code != CODE_16BIT
6550 ? WORD_MNEM_SUFFIX
6551 : LONG_MNEM_SUFFIX));
40fb9820
L		 6552 bigdisp.bitfield.disp32 = 1;
6553 if ((flag_code == CODE_16BIT) ^ override)
6554 {
6555 bigdisp.bitfield.disp32 = 0;
6556 bigdisp.bitfield.disp16 = 1;
6557 }
e05278af 6558 }
e05278af 6559 }
c6fb90c8
L		 6560 i.types[this_operand] = operand_type_or (i.types[this_operand],
6561 bigdisp);
252b5132
RH		 6562
6563 exp = &disp_expressions[i.disp_operands];
520dc8e8 6564 i.op[this_operand].disps = exp;
252b5132
RH		 6565 i.disp_operands++;
6566 save_input_line_pointer = input_line_pointer;
6567 input_line_pointer = disp_start;
6568 END_STRING_AND_SAVE (disp_end);
6569
6570#ifndef GCC_ASM_O_HACK
6571#define GCC_ASM_O_HACK 0
6572#endif
6573#if GCC_ASM_O_HACK
6574 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 6575 if (i.types[this_operand].bitfield.baseIndex
24eab124 6576 && displacement_string_end[-1] == '+')
252b5132
RH		 6577 {
6578 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 6579 constraint within gcc asm statements.
6580 For instance:
6581
6582 #define _set_tssldt_desc(n,addr,limit,type) \
6583 __asm__ __volatile__ ( \
6584 "movw %w2,%0\n\t" \
6585 "movw %w1,2+%0\n\t" \
6586 "rorl $16,%1\n\t" \
6587 "movb %b1,4+%0\n\t" \
6588 "movb %4,5+%0\n\t" \
6589 "movb $0,6+%0\n\t" \
6590 "movb %h1,7+%0\n\t" \
6591 "rorl $16,%1" \
6592 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6593
6594 This works great except that the output assembler ends
6595 up looking a bit weird if it turns out that there is
6596 no offset. You end up producing code that looks like:
6597
6598 #APP
6599 movw $235,(%eax)
6600 movw %dx,2+(%eax)
6601 rorl $16,%edx
6602 movb %dl,4+(%eax)
6603 movb $137,5+(%eax)
6604 movb $0,6+(%eax)
6605 movb %dh,7+(%eax)
6606 rorl $16,%edx
6607 #NO_APP
6608
47926f60 6609 So here we provide the missing zero. */
24eab124
AM		 6610
6611 *displacement_string_end = '0';
252b5132
RH		 6612 }
6613#endif
3956db08 6614 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6615 if (gotfree_input_line)
6616 input_line_pointer = gotfree_input_line;
252b5132 6617
24eab124 6618 exp_seg = expression (exp);
252b5132 6619
636c26b0
AM		 6620 SKIP_WHITESPACE ();
6621 if (*input_line_pointer)
6622 as_bad (_("junk `%s' after expression"), input_line_pointer);
6623#if GCC_ASM_O_HACK
6624 RESTORE_END_STRING (disp_end + 1);
6625#endif
636c26b0 6626 input_line_pointer = save_input_line_pointer;
636c26b0 6627 if (gotfree_input_line)
ee86248c
JB		 6628 {
6629 free (gotfree_input_line);
6630
6631 if (exp->X_op == O_constant || exp->X_op == O_register)
6632 exp->X_op = O_illegal;
6633 }
6634
6635 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
6636
6637 RESTORE_END_STRING (disp_end);
6638
6639 return ret;
6640}
6641
6642static int
6643i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6644 i386_operand_type types, const char *disp_start)
6645{
6646 i386_operand_type bigdisp;
6647 int ret = 1;
636c26b0 6648
24eab124
AM		 6649 /* We do this to make sure that the section symbol is in
6650 the symbol table. We will ultimately change the relocation
47926f60 6651 to be relative to the beginning of the section. */
1ae12ab7 6652 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 6653 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
6654 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 6655 {
636c26b0 6656 if (exp->X_op != O_symbol)
3992d3b7 6657 goto inv_disp;
636c26b0 6658
e5cb08ac 6659 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 6660 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
6661 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 6662 exp->X_op = O_subtract;
6663 exp->X_op_symbol = GOT_symbol;
1ae12ab7 6664 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 6665 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 6666 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6667 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 6668 else
29b0f896 6669 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 6670 }
252b5132 6671
3992d3b7
AM		 6672 else if (exp->X_op == O_absent
6673 || exp->X_op == O_illegal
ee86248c 6674 || exp->X_op == O_big)
2daf4fd8 6675 {
3992d3b7
AM		 6676 inv_disp:
6677 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 6678 disp_start);
3992d3b7 6679 ret = 0;
2daf4fd8
AM		 6680 }
6681
0e1147d9
L		 6682 else if (flag_code == CODE_64BIT
6683 && !i.prefix[ADDR_PREFIX]
6684 && exp->X_op == O_constant)
6685 {
6686 /* Since displacement is signed extended to 64bit, don't allow
6687 disp32 and turn off disp32s if they are out of range. */
6688 i.types[this_operand].bitfield.disp32 = 0;
6689 if (!fits_in_signed_long (exp->X_add_number))
6690 {
6691 i.types[this_operand].bitfield.disp32s = 0;
6692 if (i.types[this_operand].bitfield.baseindex)
6693 {
6694 as_bad (_("0x%lx out range of signed 32bit displacement"),
6695 (long) exp->X_add_number);
6696 ret = 0;
6697 }
6698 }
6699 }
6700
4c63da97 6701#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 6702 else if (exp->X_op != O_constant
6703 && OUTPUT_FLAVOR == bfd_target_aout_flavour
6704 && exp_seg != absolute_section
6705 && exp_seg != text_section
6706 && exp_seg != data_section
6707 && exp_seg != bss_section
6708 && exp_seg != undefined_section
6709 && !bfd_is_com_section (exp_seg))
24eab124 6710 {
d0b47220 6711 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 6712 ret = 0;
24eab124 6713 }
252b5132 6714#endif
3956db08 6715
40fb9820
L		 6716 /* Check if this is a displacement only operand. */
6717 bigdisp = i.types[this_operand];
6718 bigdisp.bitfield.disp8 = 0;
6719 bigdisp.bitfield.disp16 = 0;
6720 bigdisp.bitfield.disp32 = 0;
6721 bigdisp.bitfield.disp32s = 0;
6722 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 6723 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 6724 i.types[this_operand] = operand_type_and (i.types[this_operand],
6725 types);
3956db08 6726
3992d3b7 6727 return ret;
252b5132
RH		 6728}
6729
eecb386c 6730/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 6731 Return 1 on success, 0 on a failure. */
6732
252b5132 6733static int
e3bb37b5 6734i386_index_check (const char *operand_string)
252b5132 6735{
3e73aa7c 6736 int ok;
fc0763e6 6737 const char *kind = "base/index";
24eab124 6738#if INFER_ADDR_PREFIX
eecb386c
AM		 6739 int fudged = 0;
6740
24eab124
AM		 6741 tryprefix:
6742#endif
3e73aa7c 6743 ok = 1;
fc0763e6
JB		 6744 if (current_templates->start->opcode_modifier.isstring
6745 && !current_templates->start->opcode_modifier.immext
6746 && (current_templates->end[-1].opcode_modifier.isstring
6747 || i.mem_operands))
6748 {
6749 /* Memory operands of string insns are special in that they only allow
6750 a single register (rDI, rSI, or rBX) as their memory address. */
6751 unsigned int expected;
6752
6753 kind = "string address";
6754
6755 if (current_templates->start->opcode_modifier.w)
6756 {
6757 i386_operand_type type = current_templates->end[-1].operand_types[0];
6758
6759 if (!type.bitfield.baseindex
6760 || ((!i.mem_operands != !intel_syntax)
6761 && current_templates->end[-1].operand_types[1]
6762 .bitfield.baseindex))
6763 type = current_templates->end[-1].operand_types[1];
6764 expected = type.bitfield.esseg ? 7 /* rDI */ : 6 /* rSI */;
6765 }
6766 else
6767 expected = 3 /* rBX */;
6768
6769 if (!i.base_reg || i.index_reg
6770 || operand_type_check (i.types[this_operand], disp))
6771 ok = -1;
6772 else if (!(flag_code == CODE_64BIT
6773 ? i.prefix[ADDR_PREFIX]
6774 ? i.base_reg->reg_type.bitfield.reg32
6775 : i.base_reg->reg_type.bitfield.reg64
6776 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
6777 ? i.base_reg->reg_type.bitfield.reg32
6778 : i.base_reg->reg_type.bitfield.reg16))
6779 ok = 0;
6780 else if (i.base_reg->reg_num != expected)
6781 ok = -1;
6782
6783 if (ok < 0)
6784 {
6785 unsigned int j;
6786
6787 for (j = 0; j < i386_regtab_size; ++j)
6788 if ((flag_code == CODE_64BIT
6789 ? i.prefix[ADDR_PREFIX]
6790 ? i386_regtab[j].reg_type.bitfield.reg32
6791 : i386_regtab[j].reg_type.bitfield.reg64
6792 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
6793 ? i386_regtab[j].reg_type.bitfield.reg32
6794 : i386_regtab[j].reg_type.bitfield.reg16)
6795 && i386_regtab[j].reg_num == expected)
6796 break;
9c2799c2 6797 gas_assert (j < i386_regtab_size);
fc0763e6
JB		 6798 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
6799 operand_string,
6800 intel_syntax ? '[' : '(',
6801 register_prefix,
6802 i386_regtab[j].reg_name,
6803 intel_syntax ? ']' : ')');
6804 ok = 1;
6805 }
6806 }
6807 else if (flag_code == CODE_64BIT)
64e74474 6808 {
64e74474 6809 if ((i.base_reg
40fb9820
L		 6810 && ((i.prefix[ADDR_PREFIX] == 0
6811 && !i.base_reg->reg_type.bitfield.reg64)
6812 || (i.prefix[ADDR_PREFIX]
6813 && !i.base_reg->reg_type.bitfield.reg32))
6814 && (i.index_reg
9a04903e
JB		 6815 || i.base_reg->reg_num !=
6816 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
64e74474 6817 || (i.index_reg
40fb9820
L		 6818 && (!i.index_reg->reg_type.bitfield.baseindex
6819 || (i.prefix[ADDR_PREFIX] == 0
db51cc60
L		 6820 && i.index_reg->reg_num != RegRiz
6821 && !i.index_reg->reg_type.bitfield.reg64
6822 )
40fb9820 6823 || (i.prefix[ADDR_PREFIX]
db51cc60 6824 && i.index_reg->reg_num != RegEiz
40fb9820 6825 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 6826 ok = 0;
3e73aa7c
JH		 6827 }
6828 else
6829 {
6830 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
6831 {
6832 /* 16bit checks. */
6833 if ((i.base_reg
40fb9820
L		 6834 && (!i.base_reg->reg_type.bitfield.reg16
6835 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 6836 || (i.index_reg
40fb9820
L		 6837 && (!i.index_reg->reg_type.bitfield.reg16
6838 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 6839 || !(i.base_reg
6840 && i.base_reg->reg_num < 6
6841 && i.index_reg->reg_num >= 6
6842 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 6843 ok = 0;
6844 }
6845 else
e5cb08ac 6846 {
3e73aa7c
JH		 6847 /* 32bit checks. */
6848 if ((i.base_reg
40fb9820 6849 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 6850 || (i.index_reg
db51cc60
L		 6851 && ((!i.index_reg->reg_type.bitfield.reg32
6852 && i.index_reg->reg_num != RegEiz)
40fb9820 6853 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 6854 ok = 0;
3e73aa7c
JH		 6855 }
6856 }
6857 if (!ok)
24eab124
AM		 6858 {
6859#if INFER_ADDR_PREFIX
fc0763e6 6860 if (!i.mem_operands && !i.prefix[ADDR_PREFIX])
24eab124
AM		 6861 {
6862 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
6863 i.prefixes += 1;
b23bac36
AM		 6864 /* Change the size of any displacement too. At most one of
6865 Disp16 or Disp32 is set.
6866 FIXME. There doesn't seem to be any real need for separate
6867 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 6868 Removing them would probably clean up the code quite a lot. */
4eed87de 6869 if (flag_code != CODE_64BIT
40fb9820
L		 6870 && (i.types[this_operand].bitfield.disp16
6871 || i.types[this_operand].bitfield.disp32))
6872 i.types[this_operand]
c6fb90c8 6873 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 6874 fudged = 1;
24eab124
AM		 6875 goto tryprefix;
6876 }
eecb386c 6877 if (fudged)
fc0763e6
JB		 6878 as_bad (_("`%s' is not a valid %s expression"),
6879 operand_string,
6880 kind);
eecb386c 6881 else
c388dee8 6882#endif
fc0763e6 6883 as_bad (_("`%s' is not a valid %s-bit %s expression"),
eecb386c 6884 operand_string,
fc0763e6
JB		 6885 flag_code_names[i.prefix[ADDR_PREFIX]
6886 ? flag_code == CODE_32BIT
6887 ? CODE_16BIT
6888 : CODE_32BIT
6889 : flag_code],
6890 kind);
24eab124 6891 }
20f0a1fc 6892 return ok;
24eab124 6893}
252b5132 6894
fc0763e6 6895/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 6896 on error. */
252b5132 6897
252b5132 6898static int
a7619375 6899i386_att_operand (char *operand_string)
252b5132 6900{
af6bdddf
AM		 6901 const reg_entry *r;
6902 char *end_op;
24eab124 6903 char *op_string = operand_string;
252b5132 6904
24eab124 6905 if (is_space_char (*op_string))
252b5132
RH		 6906 ++op_string;
6907
24eab124 6908 /* We check for an absolute prefix (differentiating,
47926f60 6909 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 6910 if (*op_string == ABSOLUTE_PREFIX)
6911 {
6912 ++op_string;
6913 if (is_space_char (*op_string))
6914 ++op_string;
40fb9820 6915 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 6916 }
252b5132 6917
47926f60 6918 /* Check if operand is a register. */
4d1bb795 6919 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 6920 {
40fb9820
L		 6921 i386_operand_type temp;
6922
24eab124
AM		 6923 /* Check for a segment override by searching for ':' after a
6924 segment register. */
6925 op_string = end_op;
6926 if (is_space_char (*op_string))
6927 ++op_string;
40fb9820
L		 6928 if (*op_string == ':'
6929 && (r->reg_type.bitfield.sreg2
6930 || r->reg_type.bitfield.sreg3))
24eab124
AM		 6931 {
6932 switch (r->reg_num)
6933 {
6934 case 0:
6935 i.seg[i.mem_operands] = &es;
6936 break;
6937 case 1:
6938 i.seg[i.mem_operands] = &cs;
6939 break;
6940 case 2:
6941 i.seg[i.mem_operands] = &ss;
6942 break;
6943 case 3:
6944 i.seg[i.mem_operands] = &ds;
6945 break;
6946 case 4:
6947 i.seg[i.mem_operands] = &fs;
6948 break;
6949 case 5:
6950 i.seg[i.mem_operands] = &gs;
6951 break;
6952 }
252b5132 6953
24eab124 6954 /* Skip the ':' and whitespace. */
252b5132
RH		 6955 ++op_string;
6956 if (is_space_char (*op_string))
24eab124 6957 ++op_string;
252b5132 6958
24eab124
AM		 6959 if (!is_digit_char (*op_string)
6960 && !is_identifier_char (*op_string)
6961 && *op_string != '('
6962 && *op_string != ABSOLUTE_PREFIX)
6963 {
6964 as_bad (_("bad memory operand `%s'"), op_string);
6965 return 0;
6966 }
47926f60 6967 /* Handle case of %es:*foo. */
24eab124
AM		 6968 if (*op_string == ABSOLUTE_PREFIX)
6969 {
6970 ++op_string;
6971 if (is_space_char (*op_string))
6972 ++op_string;
40fb9820 6973 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 6974 }
6975 goto do_memory_reference;
6976 }
6977 if (*op_string)
6978 {
d0b47220 6979 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 6980 return 0;
6981 }
40fb9820
L		 6982 temp = r->reg_type;
6983 temp.bitfield.baseindex = 0;
c6fb90c8
L		 6984 i.types[this_operand] = operand_type_or (i.types[this_operand],
6985 temp);
7d5e4556 6986 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 6987 i.op[this_operand].regs = r;
24eab124
AM		 6988 i.reg_operands++;
6989 }
af6bdddf
AM		 6990 else if (*op_string == REGISTER_PREFIX)
6991 {
6992 as_bad (_("bad register name `%s'"), op_string);
6993 return 0;
6994 }
24eab124 6995 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 6996 {
24eab124 6997 ++op_string;
40fb9820 6998 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 6999 {
d0b47220 7000 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 7001 return 0;
7002 }
7003 if (!i386_immediate (op_string))
7004 return 0;
7005 }
7006 else if (is_digit_char (*op_string)
7007 || is_identifier_char (*op_string)
e5cb08ac 7008 || *op_string == '(')
24eab124 7009 {
47926f60 7010 /* This is a memory reference of some sort. */
af6bdddf 7011 char *base_string;
252b5132 7012
47926f60 7013 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 7014 char *displacement_string_start;
7015 char *displacement_string_end;
252b5132 7016
24eab124 7017 do_memory_reference:
24eab124 7018 if ((i.mem_operands == 1
40fb9820 7019 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 7020 || i.mem_operands == 2)
7021 {
7022 as_bad (_("too many memory references for `%s'"),
7023 current_templates->start->name);
7024 return 0;
7025 }
252b5132 7026
24eab124
AM		 7027 /* Check for base index form. We detect the base index form by
7028 looking for an ')' at the end of the operand, searching
7029 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7030 after the '('. */
af6bdddf 7031 base_string = op_string + strlen (op_string);
c3332e24 7032
af6bdddf
AM		 7033 --base_string;
7034 if (is_space_char (*base_string))
7035 --base_string;
252b5132 7036
47926f60 7037 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 7038 displacement_string_start = op_string;
7039 displacement_string_end = base_string + 1;
252b5132 7040
24eab124
AM		 7041 if (*base_string == ')')
7042 {
af6bdddf 7043 char *temp_string;
24eab124
AM		 7044 unsigned int parens_balanced = 1;
7045 /* We've already checked that the number of left & right ()'s are
47926f60 7046 equal, so this loop will not be infinite. */
24eab124
AM		 7047 do
7048 {
7049 base_string--;
7050 if (*base_string == ')')
7051 parens_balanced++;
7052 if (*base_string == '(')
7053 parens_balanced--;
7054 }
7055 while (parens_balanced);
c3332e24 7056
af6bdddf 7057 temp_string = base_string;
c3332e24 7058
24eab124 7059 /* Skip past '(' and whitespace. */
252b5132
RH		 7060 ++base_string;
7061 if (is_space_char (*base_string))
24eab124 7062 ++base_string;
252b5132 7063
af6bdddf 7064 if (*base_string == ','
4eed87de
AM		 7065 || ((i.base_reg = parse_register (base_string, &end_op))
7066 != NULL))
252b5132 7067 {
af6bdddf 7068 displacement_string_end = temp_string;
252b5132 7069
40fb9820 7070 i.types[this_operand].bitfield.baseindex = 1;
252b5132 7071
af6bdddf 7072 if (i.base_reg)
24eab124 7073 {
24eab124
AM		 7074 base_string = end_op;
7075 if (is_space_char (*base_string))
7076 ++base_string;
af6bdddf
AM		 7077 }
7078
7079 /* There may be an index reg or scale factor here. */
7080 if (*base_string == ',')
7081 {
7082 ++base_string;
7083 if (is_space_char (*base_string))
7084 ++base_string;
7085
4eed87de
AM		 7086 if ((i.index_reg = parse_register (base_string, &end_op))
7087 != NULL)
24eab124 7088 {
af6bdddf 7089 base_string = end_op;
24eab124
AM		 7090 if (is_space_char (*base_string))
7091 ++base_string;
af6bdddf
AM		 7092 if (*base_string == ',')
7093 {
7094 ++base_string;
7095 if (is_space_char (*base_string))
7096 ++base_string;
7097 }
e5cb08ac 7098 else if (*base_string != ')')
af6bdddf 7099 {
4eed87de
AM		 7100 as_bad (_("expecting `,' or `)' "
7101 "after index register in `%s'"),
af6bdddf
AM		 7102 operand_string);
7103 return 0;
7104 }
24eab124 7105 }
af6bdddf 7106 else if (*base_string == REGISTER_PREFIX)
24eab124 7107 {
af6bdddf 7108 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 7109 return 0;
7110 }
252b5132 7111
47926f60 7112 /* Check for scale factor. */
551c1ca1 7113 if (*base_string != ')')
af6bdddf 7114 {
551c1ca1
AM		 7115 char *end_scale = i386_scale (base_string);
7116
7117 if (!end_scale)
af6bdddf 7118 return 0;
24eab124 7119
551c1ca1 7120 base_string = end_scale;
af6bdddf
AM		 7121 if (is_space_char (*base_string))
7122 ++base_string;
7123 if (*base_string != ')')
7124 {
4eed87de
AM		 7125 as_bad (_("expecting `)' "
7126 "after scale factor in `%s'"),
af6bdddf
AM		 7127 operand_string);
7128 return 0;
7129 }
7130 }
7131 else if (!i.index_reg)
24eab124 7132 {
4eed87de
AM		 7133 as_bad (_("expecting index register or scale factor "
7134 "after `,'; got '%c'"),
af6bdddf 7135 *base_string);
24eab124
AM		 7136 return 0;
7137 }
7138 }
af6bdddf 7139 else if (*base_string != ')')
24eab124 7140 {
4eed87de
AM		 7141 as_bad (_("expecting `,' or `)' "
7142 "after base register in `%s'"),
af6bdddf 7143 operand_string);
24eab124
AM		 7144 return 0;
7145 }
c3332e24 7146 }
af6bdddf 7147 else if (*base_string == REGISTER_PREFIX)
c3332e24 7148 {
af6bdddf 7149 as_bad (_("bad register name `%s'"), base_string);
24eab124 7150 return 0;
c3332e24 7151 }
24eab124
AM		 7152 }
7153
7154 /* If there's an expression beginning the operand, parse it,
7155 assuming displacement_string_start and
7156 displacement_string_end are meaningful. */
7157 if (displacement_string_start != displacement_string_end)
7158 {
7159 if (!i386_displacement (displacement_string_start,
7160 displacement_string_end))
7161 return 0;
7162 }
7163
7164 /* Special case for (%dx) while doing input/output op. */
7165 if (i.base_reg
0dfbf9d7
L		 7166 && operand_type_equal (&i.base_reg->reg_type,
7167 &reg16_inoutportreg)
24eab124
AM		 7168 && i.index_reg == 0
7169 && i.log2_scale_factor == 0
7170 && i.seg[i.mem_operands] == 0
40fb9820 7171 && !operand_type_check (i.types[this_operand], disp))
24eab124 7172 {
65da13b5 7173 i.types[this_operand] = inoutportreg;
24eab124
AM		 7174 return 1;
7175 }
7176
eecb386c
AM		 7177 if (i386_index_check (operand_string) == 0)
7178 return 0;
5c07affc 7179 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 7180 i.mem_operands++;
7181 }
7182 else
ce8a8b2f
AM		 7183 {
7184 /* It's not a memory operand; argh! */
24eab124
AM		 7185 as_bad (_("invalid char %s beginning operand %d `%s'"),
7186 output_invalid (*op_string),
7187 this_operand + 1,
7188 op_string);
7189 return 0;
7190 }
47926f60 7191 return 1; /* Normal return. */
252b5132
RH		 7192}
7193\f
ee7fcc42
AM		 7194/* md_estimate_size_before_relax()
7195
7196 Called just before relax() for rs_machine_dependent frags. The x86
7197 assembler uses these frags to handle variable size jump
7198 instructions.
7199
7200 Any symbol that is now undefined will not become defined.
7201 Return the correct fr_subtype in the frag.
7202 Return the initial "guess for variable size of frag" to caller.
7203 The guess is actually the growth beyond the fixed part. Whatever
7204 we do to grow the fixed or variable part contributes to our
7205 returned value. */
7206
252b5132
RH		 7207int
7208md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 7209 fragS *fragP;
7210 segT segment;
252b5132 7211{
252b5132 7212 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 7213 check for un-relaxable symbols. On an ELF system, we can't relax
7214 an externally visible symbol, because it may be overridden by a
7215 shared library. */
7216 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 7217#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7218 || (IS_ELF
31312f95 7219 && (S_IS_EXTERNAL (fragP->fr_symbol)
915bcca5
L		 7220 || S_IS_WEAK (fragP->fr_symbol)
7221 || ((symbol_get_bfdsym (fragP->fr_symbol)->flags
7222 & BSF_GNU_INDIRECT_FUNCTION))))
fbeb56a4
DK		 7223#endif
7224#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 7225 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 7226 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 7227#endif
7228 )
252b5132 7229 {
b98ef147
AM		 7230 /* Symbol is undefined in this segment, or we need to keep a
7231 reloc so that weak symbols can be overridden. */
7232 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 7233 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 7234 unsigned char *opcode;
7235 int old_fr_fix;
f6af82bd 7236
ee7fcc42 7237 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 7238 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 7239 else if (size == 2)
f6af82bd
AM		 7240 reloc_type = BFD_RELOC_16_PCREL;
7241 else
7242 reloc_type = BFD_RELOC_32_PCREL;
252b5132 7243
ee7fcc42
AM		 7244 old_fr_fix = fragP->fr_fix;
7245 opcode = (unsigned char *) fragP->fr_opcode;
7246
fddf5b5b 7247 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 7248 {
fddf5b5b
AM		 7249 case UNCOND_JUMP:
7250 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 7251 opcode[0] = 0xe9;
252b5132 7252 fragP->fr_fix += size;
062cd5e7
AS		 7253 fix_new (fragP, old_fr_fix, size,
7254 fragP->fr_symbol,
7255 fragP->fr_offset, 1,
7256 reloc_type);
252b5132
RH		 7257 break;
7258
fddf5b5b 7259 case COND_JUMP86:
412167cb
AM		 7260 if (size == 2
7261 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 7262 {
7263 /* Negate the condition, and branch past an
7264 unconditional jump. */
7265 opcode[0] ^= 1;
7266 opcode[1] = 3;
7267 /* Insert an unconditional jump. */
7268 opcode[2] = 0xe9;
7269 /* We added two extra opcode bytes, and have a two byte
7270 offset. */
7271 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 7272 fix_new (fragP, old_fr_fix + 2, 2,
7273 fragP->fr_symbol,
7274 fragP->fr_offset, 1,
7275 reloc_type);
fddf5b5b
AM		 7276 break;
7277 }
7278 /* Fall through. */
7279
7280 case COND_JUMP:
412167cb
AM		 7281 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
7282 {
3e02c1cc
AM		 7283 fixS *fixP;
7284
412167cb 7285 fragP->fr_fix += 1;
3e02c1cc
AM		 7286 fixP = fix_new (fragP, old_fr_fix, 1,
7287 fragP->fr_symbol,
7288 fragP->fr_offset, 1,
7289 BFD_RELOC_8_PCREL);
7290 fixP->fx_signed = 1;
412167cb
AM		 7291 break;
7292 }
93c2a809 7293
24eab124 7294 /* This changes the byte-displacement jump 0x7N
fddf5b5b 7295 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 7296 opcode[1] = opcode[0] + 0x10;
f6af82bd 7297 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 7298 /* We've added an opcode byte. */
7299 fragP->fr_fix += 1 + size;
062cd5e7
AS		 7300 fix_new (fragP, old_fr_fix + 1, size,
7301 fragP->fr_symbol,
7302 fragP->fr_offset, 1,
7303 reloc_type);
252b5132 7304 break;
fddf5b5b
AM		 7305
7306 default:
7307 BAD_CASE (fragP->fr_subtype);
7308 break;
252b5132
RH		 7309 }
7310 frag_wane (fragP);
ee7fcc42 7311 return fragP->fr_fix - old_fr_fix;
252b5132 7312 }
93c2a809 7313
93c2a809
AM		 7314 /* Guess size depending on current relax state. Initially the relax
7315 state will correspond to a short jump and we return 1, because
7316 the variable part of the frag (the branch offset) is one byte
7317 long. However, we can relax a section more than once and in that
7318 case we must either set fr_subtype back to the unrelaxed state,
7319 or return the value for the appropriate branch. */
7320 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 7321}
7322
47926f60
KH		 7323/* Called after relax() is finished.
7324
7325 In: Address of frag.
7326 fr_type == rs_machine_dependent.
7327 fr_subtype is what the address relaxed to.
7328
7329 Out: Any fixSs and constants are set up.
7330 Caller will turn frag into a ".space 0". */
7331
252b5132
RH		 7332void
7333md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 7334 bfd *abfd ATTRIBUTE_UNUSED;
7335 segT sec ATTRIBUTE_UNUSED;
29b0f896 7336 fragS *fragP;
252b5132 7337{
29b0f896 7338 unsigned char *opcode;
252b5132 7339 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 7340 offsetT target_address;
7341 offsetT opcode_address;
252b5132 7342 unsigned int extension = 0;
847f7ad4 7343 offsetT displacement_from_opcode_start;
252b5132
RH		 7344
7345 opcode = (unsigned char *) fragP->fr_opcode;
7346
47926f60 7347 /* Address we want to reach in file space. */
252b5132 7348 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 7349
47926f60 7350 /* Address opcode resides at in file space. */
252b5132
RH		 7351 opcode_address = fragP->fr_address + fragP->fr_fix;
7352
47926f60 7353 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 7354 displacement_from_opcode_start = target_address - opcode_address;
7355
fddf5b5b 7356 if ((fragP->fr_subtype & BIG) == 0)
252b5132 7357 {
47926f60
KH		 7358 /* Don't have to change opcode. */
7359 extension = 1; /* 1 opcode + 1 displacement */
252b5132 7360 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 7361 }
7362 else
7363 {
7364 if (no_cond_jump_promotion
7365 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 7366 as_warn_where (fragP->fr_file, fragP->fr_line,
7367 _("long jump required"));
252b5132 7368
fddf5b5b
AM		 7369 switch (fragP->fr_subtype)
7370 {
7371 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
7372 extension = 4; /* 1 opcode + 4 displacement */
7373 opcode[0] = 0xe9;
7374 where_to_put_displacement = &opcode[1];
7375 break;
252b5132 7376
fddf5b5b
AM		 7377 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
7378 extension = 2; /* 1 opcode + 2 displacement */
7379 opcode[0] = 0xe9;
7380 where_to_put_displacement = &opcode[1];
7381 break;
252b5132 7382
fddf5b5b
AM		 7383 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
7384 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
7385 extension = 5; /* 2 opcode + 4 displacement */
7386 opcode[1] = opcode[0] + 0x10;
7387 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7388 where_to_put_displacement = &opcode[2];
7389 break;
252b5132 7390
fddf5b5b
AM		 7391 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
7392 extension = 3; /* 2 opcode + 2 displacement */
7393 opcode[1] = opcode[0] + 0x10;
7394 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7395 where_to_put_displacement = &opcode[2];
7396 break;
252b5132 7397
fddf5b5b
AM		 7398 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
7399 extension = 4;
7400 opcode[0] ^= 1;
7401 opcode[1] = 3;
7402 opcode[2] = 0xe9;
7403 where_to_put_displacement = &opcode[3];
7404 break;
7405
7406 default:
7407 BAD_CASE (fragP->fr_subtype);
7408 break;
7409 }
252b5132 7410 }
fddf5b5b 7411
7b81dfbb
AJ		 7412 /* If size if less then four we are sure that the operand fits,
7413 but if it's 4, then it could be that the displacement is larger
7414 then -/+ 2GB. */
7415 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
7416 && object_64bit
7417 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 7418 + ((addressT) 1 << 31))
7419 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 7420 {
7421 as_bad_where (fragP->fr_file, fragP->fr_line,
7422 _("jump target out of range"));
7423 /* Make us emit 0. */
7424 displacement_from_opcode_start = extension;
7425 }
47926f60 7426 /* Now put displacement after opcode. */
252b5132
RH		 7427 md_number_to_chars ((char *) where_to_put_displacement,
7428 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 7429 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 7430 fragP->fr_fix += extension;
7431}
7432\f
252b5132
RH		 7433/* Apply a fixup (fixS) to segment data, once it has been determined
7434 by our caller that we have all the info we need to fix it up.
7435
7436 On the 386, immediates, displacements, and data pointers are all in
7437 the same (little-endian) format, so we don't need to care about which
7438 we are handling. */
7439
94f592af 7440void
55cf6793 7441md_apply_fix (fixP, valP, seg)
47926f60
KH		 7442 /* The fix we're to put in. */
7443 fixS *fixP;
47926f60 7444 /* Pointer to the value of the bits. */
c6682705 7445 valueT *valP;
47926f60
KH		 7446 /* Segment fix is from. */
7447 segT seg ATTRIBUTE_UNUSED;
252b5132 7448{
94f592af 7449 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 7450 valueT value = *valP;
252b5132 7451
f86103b7 7452#if !defined (TE_Mach)
93382f6d
AM		 7453 if (fixP->fx_pcrel)
7454 {
7455 switch (fixP->fx_r_type)
7456 {
5865bb77
ILT		 7457 default:
7458 break;
7459
d6ab8113
JB		 7460 case BFD_RELOC_64:
7461 fixP->fx_r_type = BFD_RELOC_64_PCREL;
7462 break;
93382f6d 7463 case BFD_RELOC_32:
ae8887b5 7464 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 7465 fixP->fx_r_type = BFD_RELOC_32_PCREL;
7466 break;
7467 case BFD_RELOC_16:
7468 fixP->fx_r_type = BFD_RELOC_16_PCREL;
7469 break;
7470 case BFD_RELOC_8:
7471 fixP->fx_r_type = BFD_RELOC_8_PCREL;
7472 break;
7473 }
7474 }
252b5132 7475
a161fe53 7476 if (fixP->fx_addsy != NULL
31312f95 7477 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 7478 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 7479 || fixP->fx_r_type == BFD_RELOC_16_PCREL
7480 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
7481 && !use_rela_relocations)
252b5132 7482 {
31312f95
AM		 7483 /* This is a hack. There should be a better way to handle this.
7484 This covers for the fact that bfd_install_relocation will
7485 subtract the current location (for partial_inplace, PC relative
7486 relocations); see more below. */
252b5132 7487#ifndef OBJ_AOUT
718ddfc0 7488 if (IS_ELF
252b5132
RH		 7489#ifdef TE_PE
7490 || OUTPUT_FLAVOR == bfd_target_coff_flavour
7491#endif
7492 )
7493 value += fixP->fx_where + fixP->fx_frag->fr_address;
7494#endif
7495#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7496 if (IS_ELF)
252b5132 7497 {
6539b54b 7498 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 7499
6539b54b 7500 if ((sym_seg == seg
2f66722d 7501 || (symbol_section_p (fixP->fx_addsy)
6539b54b 7502 && sym_seg != absolute_section))
af65af87 7503 && !generic_force_reloc (fixP))
2f66722d
AM		 7504 {
7505 /* Yes, we add the values in twice. This is because
6539b54b
AM		 7506 bfd_install_relocation subtracts them out again. I think
7507 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 7508 it. FIXME. */
7509 value += fixP->fx_where + fixP->fx_frag->fr_address;
7510 }
252b5132
RH		 7511 }
7512#endif
7513#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 7514 /* For some reason, the PE format does not store a
7515 section address offset for a PC relative symbol. */
7516 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 7517 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 7518 value += md_pcrel_from (fixP);
7519#endif
7520 }
fbeb56a4
DK		 7521#if defined (OBJ_COFF) && defined (TE_PE)
7522 if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
7523 {
7524 value -= S_GET_VALUE (fixP->fx_addsy);
7525 }
7526#endif
252b5132
RH		 7527
7528 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 7529 and we must not disappoint it. */
252b5132 7530#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7531 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 7532 switch (fixP->fx_r_type)
7533 {
7534 case BFD_RELOC_386_PLT32:
3e73aa7c 7535 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 7536 /* Make the jump instruction point to the address of the operand. At
7537 runtime we merely add the offset to the actual PLT entry. */
7538 value = -4;
7539 break;
31312f95 7540
13ae64f3
JJ		 7541 case BFD_RELOC_386_TLS_GD:
7542 case BFD_RELOC_386_TLS_LDM:
13ae64f3 7543 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 7544 case BFD_RELOC_386_TLS_IE:
7545 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 7546 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 7547 case BFD_RELOC_X86_64_TLSGD:
7548 case BFD_RELOC_X86_64_TLSLD:
7549 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 7550 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 7551 value = 0; /* Fully resolved at runtime. No addend. */
7552 /* Fallthrough */
7553 case BFD_RELOC_386_TLS_LE:
7554 case BFD_RELOC_386_TLS_LDO_32:
7555 case BFD_RELOC_386_TLS_LE_32:
7556 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 7557 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 7558 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 7559 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 7560 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7561 break;
7562
67a4f2b7
AO		 7563 case BFD_RELOC_386_TLS_DESC_CALL:
7564 case BFD_RELOC_X86_64_TLSDESC_CALL:
7565 value = 0; /* Fully resolved at runtime. No addend. */
7566 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7567 fixP->fx_done = 0;
7568 return;
7569
00f7efb6
JJ		 7570 case BFD_RELOC_386_GOT32:
7571 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 7572 value = 0; /* Fully resolved at runtime. No addend. */
7573 break;
47926f60
KH		 7574
7575 case BFD_RELOC_VTABLE_INHERIT:
7576 case BFD_RELOC_VTABLE_ENTRY:
7577 fixP->fx_done = 0;
94f592af 7578 return;
47926f60
KH		 7579
7580 default:
7581 break;
7582 }
7583#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 7584 *valP = value;
f86103b7 7585#endif /* !defined (TE_Mach) */
3e73aa7c 7586
3e73aa7c 7587 /* Are we finished with this relocation now? */
c6682705 7588 if (fixP->fx_addsy == NULL)
3e73aa7c 7589 fixP->fx_done = 1;
fbeb56a4
DK		 7590#if defined (OBJ_COFF) && defined (TE_PE)
7591 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
7592 {
7593 fixP->fx_done = 0;
7594 /* Remember value for tc_gen_reloc. */
7595 fixP->fx_addnumber = value;
7596 /* Clear out the frag for now. */
7597 value = 0;
7598 }
7599#endif
3e73aa7c
JH		 7600 else if (use_rela_relocations)
7601 {
7602 fixP->fx_no_overflow = 1;
062cd5e7
AS		 7603 /* Remember value for tc_gen_reloc. */
7604 fixP->fx_addnumber = value;
3e73aa7c
JH		 7605 value = 0;
7606 }
f86103b7 7607
94f592af 7608 md_number_to_chars (p, value, fixP->fx_size);
252b5132 7609}
252b5132 7610\f
252b5132 7611char *
499ac353 7612md_atof (int type, char *litP, int *sizeP)
252b5132 7613{
499ac353
NC		 7614 /* This outputs the LITTLENUMs in REVERSE order;
7615 in accord with the bigendian 386. */
7616 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 7617}
7618\f
2d545b82 7619static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 7620
252b5132 7621static char *
e3bb37b5 7622output_invalid (int c)
252b5132 7623{
3882b010 7624 if (ISPRINT (c))
f9f21a03
L		 7625 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
7626 "'%c'", c);
252b5132 7627 else
f9f21a03 7628 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 7629 "(0x%x)", (unsigned char) c);
252b5132
RH		 7630 return output_invalid_buf;
7631}
7632
af6bdddf 7633/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 7634
7635static const reg_entry *
4d1bb795 7636parse_real_register (char *reg_string, char **end_op)
252b5132 7637{
af6bdddf
AM		 7638 char *s = reg_string;
7639 char *p;
252b5132
RH		 7640 char reg_name_given[MAX_REG_NAME_SIZE + 1];
7641 const reg_entry *r;
7642
7643 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7644 if (*s == REGISTER_PREFIX)
7645 ++s;
7646
7647 if (is_space_char (*s))
7648 ++s;
7649
7650 p = reg_name_given;
af6bdddf 7651 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 7652 {
7653 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 7654 return (const reg_entry *) NULL;
7655 s++;
252b5132
RH		 7656 }
7657
6588847e
DN		 7658 /* For naked regs, make sure that we are not dealing with an identifier.
7659 This prevents confusing an identifier like `eax_var' with register
7660 `eax'. */
7661 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
7662 return (const reg_entry *) NULL;
7663
af6bdddf 7664 *end_op = s;
252b5132
RH		 7665
7666 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
7667
5f47d35b 7668 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 7669 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 7670 {
5f47d35b
AM		 7671 if (is_space_char (*s))
7672 ++s;
7673 if (*s == '(')
7674 {
af6bdddf 7675 ++s;
5f47d35b
AM		 7676 if (is_space_char (*s))
7677 ++s;
7678 if (*s >= '0' && *s <= '7')
7679 {
db557034 7680 int fpr = *s - '0';
af6bdddf 7681 ++s;
5f47d35b
AM		 7682 if (is_space_char (*s))
7683 ++s;
7684 if (*s == ')')
7685 {
7686 *end_op = s + 1;
1e9cc1c2 7687 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 7688 know (r);
7689 return r + fpr;
5f47d35b 7690 }
5f47d35b 7691 }
47926f60 7692 /* We have "%st(" then garbage. */
5f47d35b
AM		 7693 return (const reg_entry *) NULL;
7694 }
7695 }
7696
a60de03c
JB		 7697 if (r == NULL || allow_pseudo_reg)
7698 return r;
7699
0dfbf9d7 7700 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 7701 return (const reg_entry *) NULL;
7702
192dc9c6
JB		 7703 if ((r->reg_type.bitfield.reg32
7704 || r->reg_type.bitfield.sreg3
7705 || r->reg_type.bitfield.control
7706 || r->reg_type.bitfield.debug
7707 || r->reg_type.bitfield.test)
7708 && !cpu_arch_flags.bitfield.cpui386)
7709 return (const reg_entry *) NULL;
7710
309d3373
JB		 7711 if (r->reg_type.bitfield.floatreg
7712 && !cpu_arch_flags.bitfield.cpu8087
7713 && !cpu_arch_flags.bitfield.cpu287
7714 && !cpu_arch_flags.bitfield.cpu387)
7715 return (const reg_entry *) NULL;
7716
192dc9c6
JB		 7717 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
7718 return (const reg_entry *) NULL;
7719
7720 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
7721 return (const reg_entry *) NULL;
7722
40f12533
L		 7723 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
7724 return (const reg_entry *) NULL;
7725
db51cc60 7726 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 7727 if (!allow_index_reg
db51cc60
L		 7728 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
7729 return (const reg_entry *) NULL;
7730
a60de03c
JB		 7731 if (((r->reg_flags & (RegRex64 | RegRex))
7732 || r->reg_type.bitfield.reg64)
40fb9820 7733 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 7734 || !operand_type_equal (&r->reg_type, &control))
1ae00879 7735 && flag_code != CODE_64BIT)
20f0a1fc 7736 return (const reg_entry *) NULL;
1ae00879 7737
b7240065
JB		 7738 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
7739 return (const reg_entry *) NULL;
7740
252b5132
RH		 7741 return r;
7742}
4d1bb795
JB		 7743
7744/* REG_STRING starts *before* REGISTER_PREFIX. */
7745
7746static const reg_entry *
7747parse_register (char *reg_string, char **end_op)
7748{
7749 const reg_entry *r;
7750
7751 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
7752 r = parse_real_register (reg_string, end_op);
7753 else
7754 r = NULL;
7755 if (!r)
7756 {
7757 char *save = input_line_pointer;
7758 char c;
7759 symbolS *symbolP;
7760
7761 input_line_pointer = reg_string;
7762 c = get_symbol_end ();
7763 symbolP = symbol_find (reg_string);
7764 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
7765 {
7766 const expressionS *e = symbol_get_value_expression (symbolP);
7767
7768 know (e->X_op == O_register);
4eed87de 7769 know (e->X_add_number >= 0
c3fe08fa 7770 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 7771 r = i386_regtab + e->X_add_number;
7772 *end_op = input_line_pointer;
7773 }
7774 *input_line_pointer = c;
7775 input_line_pointer = save;
7776 }
7777 return r;
7778}
7779
7780int
7781i386_parse_name (char *name, expressionS *e, char *nextcharP)
7782{
7783 const reg_entry *r;
7784 char *end = input_line_pointer;
7785
7786 *end = *nextcharP;
7787 r = parse_register (name, &input_line_pointer);
7788 if (r && end <= input_line_pointer)
7789 {
7790 *nextcharP = *input_line_pointer;
7791 *input_line_pointer = 0;
7792 e->X_op = O_register;
7793 e->X_add_number = r - i386_regtab;
7794 return 1;
7795 }
7796 input_line_pointer = end;
7797 *end = 0;
ee86248c 7798 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 7799}
7800
7801void
7802md_operand (expressionS *e)
7803{
ee86248c
JB		 7804 char *end;
7805 const reg_entry *r;
4d1bb795 7806
ee86248c
JB		 7807 switch (*input_line_pointer)
7808 {
7809 case REGISTER_PREFIX:
7810 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 7811 if (r)
7812 {
7813 e->X_op = O_register;
7814 e->X_add_number = r - i386_regtab;
7815 input_line_pointer = end;
7816 }
ee86248c
JB		 7817 break;
7818
7819 case '[':
9c2799c2 7820 gas_assert (intel_syntax);
ee86248c
JB		 7821 end = input_line_pointer++;
7822 expression (e);
7823 if (*input_line_pointer == ']')
7824 {
7825 ++input_line_pointer;
7826 e->X_op_symbol = make_expr_symbol (e);
7827 e->X_add_symbol = NULL;
7828 e->X_add_number = 0;
7829 e->X_op = O_index;
7830 }
7831 else
7832 {
7833 e->X_op = O_absent;
7834 input_line_pointer = end;
7835 }
7836 break;
4d1bb795
JB		 7837 }
7838}
7839
252b5132 7840\f
4cc782b5 7841#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 7842const char *md_shortopts = "kVQ:sqn";
252b5132 7843#else
12b55ccc 7844const char *md_shortopts = "qn";
252b5132 7845#endif
6e0b89ee 7846
3e73aa7c 7847#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 7848#define OPTION_64 (OPTION_MD_BASE + 1)
7849#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 7850#define OPTION_MARCH (OPTION_MD_BASE + 3)
7851#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 7852#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7853#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7854#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7855#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7856#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 7857#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 7858#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
b3b91714 7859
99ad8390
NC		 7860struct option md_longopts[] =
7861{
3e73aa7c 7862 {"32", no_argument, NULL, OPTION_32},
321098a5
L		 7863#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7864 || defined (TE_PE) || defined (TE_PEP))
3e73aa7c 7865 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 7866#endif
b3b91714 7867 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 7868 {"march", required_argument, NULL, OPTION_MARCH},
7869 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 7870 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
7871 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
7872 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
7873 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
7874 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 7875 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 7876 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
252b5132
RH		 7877 {NULL, no_argument, NULL, 0}
7878};
7879size_t md_longopts_size = sizeof (md_longopts);
7880
7881int
9103f4f4 7882md_parse_option (int c, char *arg)
252b5132 7883{
91d6fa6a 7884 unsigned int j;
6305a203 7885 char *arch, *next;
9103f4f4 7886
252b5132
RH		 7887 switch (c)
7888 {
12b55ccc
L		 7889 case 'n':
7890 optimize_align_code = 0;
7891 break;
7892
a38cf1db
AM		 7893 case 'q':
7894 quiet_warnings = 1;
252b5132
RH		 7895 break;
7896
7897#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 7898 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7899 should be emitted or not. FIXME: Not implemented. */
7900 case 'Q':
252b5132
RH		 7901 break;
7902
7903 /* -V: SVR4 argument to print version ID. */
7904 case 'V':
7905 print_version_id ();
7906 break;
7907
a38cf1db
AM		 7908 /* -k: Ignore for FreeBSD compatibility. */
7909 case 'k':
252b5132 7910 break;
4cc782b5
ILT		 7911
7912 case 's':
7913 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 7914 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 7915 break;
99ad8390 7916#endif
321098a5
L		 7917#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7918 || defined (TE_PE) || defined (TE_PEP))
3e73aa7c
JH		 7919 case OPTION_64:
7920 {
7921 const char **list, **l;
7922
3e73aa7c
JH		 7923 list = bfd_target_list ();
7924 for (l = list; *l != NULL; l++)
8620418b 7925 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 7926 || strcmp (*l, "coff-x86-64") == 0
7927 || strcmp (*l, "pe-x86-64") == 0
7928 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 7929 {
7930 default_arch = "x86_64";
7931 break;
7932 }
3e73aa7c 7933 if (*l == NULL)
6e0b89ee 7934 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 7935 free (list);
7936 }
7937 break;
7938#endif
252b5132 7939
6e0b89ee
AM		 7940 case OPTION_32:
7941 default_arch = "i386";
7942 break;
7943
b3b91714
AM		 7944 case OPTION_DIVIDE:
7945#ifdef SVR4_COMMENT_CHARS
7946 {
7947 char *n, *t;
7948 const char *s;
7949
7950 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
7951 t = n;
7952 for (s = i386_comment_chars; *s != '\0'; s++)
7953 if (*s != '/')
7954 *t++ = *s;
7955 *t = '\0';
7956 i386_comment_chars = n;
7957 }
7958#endif
7959 break;
7960
9103f4f4 7961 case OPTION_MARCH:
6305a203
L		 7962 arch = xstrdup (arg);
7963 do
9103f4f4 7964 {
6305a203
L		 7965 if (*arch == '.')
7966 as_fatal (_("Invalid -march= option: `%s'"), arg);
7967 next = strchr (arch, '+');
7968 if (next)
7969 *next++ = '\0';
91d6fa6a 7970 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 7971 {
91d6fa6a 7972 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 7973 {
6305a203 7974 /* Processor. */
91d6fa6a 7975 cpu_arch_name = cpu_arch[j].name;
6305a203 7976 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 7977 cpu_arch_flags = cpu_arch[j].flags;
7978 cpu_arch_isa = cpu_arch[j].type;
7979 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 7980 if (!cpu_arch_tune_set)
7981 {
7982 cpu_arch_tune = cpu_arch_isa;
7983 cpu_arch_tune_flags = cpu_arch_isa_flags;
7984 }
7985 break;
7986 }
91d6fa6a
NC		 7987 else if (*cpu_arch [j].name == '.'
7988 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203
L		 7989 {
7990 /* ISA entension. */
7991 i386_cpu_flags flags;
309d3373
JB		 7992
7993 if (strncmp (arch, "no", 2))
7994 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 7995 cpu_arch[j].flags);
309d3373
JB		 7996 else
7997 flags = cpu_flags_and_not (cpu_arch_flags,
91d6fa6a 7998 cpu_arch[j].flags);
0dfbf9d7 7999 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 8000 {
8001 if (cpu_sub_arch_name)
8002 {
8003 char *name = cpu_sub_arch_name;
8004 cpu_sub_arch_name = concat (name,
91d6fa6a 8005 cpu_arch[j].name,
1bf57e9f 8006 (const char *) NULL);
6305a203
L		 8007 free (name);
8008 }
8009 else
91d6fa6a 8010 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203
L		 8011 cpu_arch_flags = flags;
8012 }
8013 break;
ccc9c027 8014 }
9103f4f4 8015 }
6305a203 8016
91d6fa6a 8017 if (j >= ARRAY_SIZE (cpu_arch))
6305a203
L		 8018 as_fatal (_("Invalid -march= option: `%s'"), arg);
8019
8020 arch = next;
9103f4f4 8021 }
6305a203 8022 while (next != NULL );
9103f4f4
L		 8023 break;
8024
8025 case OPTION_MTUNE:
8026 if (*arg == '.')
8027 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
91d6fa6a 8028 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 8029 {
91d6fa6a 8030 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 8031 {
ccc9c027 8032 cpu_arch_tune_set = 1;
91d6fa6a
NC		 8033 cpu_arch_tune = cpu_arch [j].type;
8034 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 8035 break;
8036 }
8037 }
91d6fa6a 8038 if (j >= ARRAY_SIZE (cpu_arch))
9103f4f4
L		 8039 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
8040 break;
8041
1efbbeb4
L		 8042 case OPTION_MMNEMONIC:
8043 if (strcasecmp (arg, "att") == 0)
8044 intel_mnemonic = 0;
8045 else if (strcasecmp (arg, "intel") == 0)
8046 intel_mnemonic = 1;
8047 else
8048 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
8049 break;
8050
8051 case OPTION_MSYNTAX:
8052 if (strcasecmp (arg, "att") == 0)
8053 intel_syntax = 0;
8054 else if (strcasecmp (arg, "intel") == 0)
8055 intel_syntax = 1;
8056 else
8057 as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
8058 break;
8059
8060 case OPTION_MINDEX_REG:
8061 allow_index_reg = 1;
8062 break;
8063
8064 case OPTION_MNAKED_REG:
8065 allow_naked_reg = 1;
8066 break;
8067
8068 case OPTION_MOLD_GCC:
8069 old_gcc = 1;
1efbbeb4
L		 8070 break;
8071
c0f3af97
L		 8072 case OPTION_MSSE2AVX:
8073 sse2avx = 1;
8074 break;
8075
daf50ae7
L		 8076 case OPTION_MSSE_CHECK:
8077 if (strcasecmp (arg, "error") == 0)
8078 sse_check = sse_check_error;
8079 else if (strcasecmp (arg, "warning") == 0)
8080 sse_check = sse_check_warning;
8081 else if (strcasecmp (arg, "none") == 0)
8082 sse_check = sse_check_none;
8083 else
8084 as_fatal (_("Invalid -msse-check= option: `%s'"), arg);
8085 break;
8086
252b5132
RH		 8087 default:
8088 return 0;
8089 }
8090 return 1;
8091}
8092
8a2c8fef
L		 8093#define MESSAGE_TEMPLATE \
8094" "
8095
8096static void
8097show_arch (FILE *stream, int ext)
8098{
8099 static char message[] = MESSAGE_TEMPLATE;
8100 char *start = message + 27;
8101 char *p;
8102 int size = sizeof (MESSAGE_TEMPLATE);
8103 int left;
8104 const char *name;
8105 int len;
8106 unsigned int j;
8107
8108 p = start;
8109 left = size - (start - message);
8110 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
8111 {
8112 /* Should it be skipped? */
8113 if (cpu_arch [j].skip)
8114 continue;
8115
8116 name = cpu_arch [j].name;
8117 len = cpu_arch [j].len;
8118 if (*name == '.')
8119 {
8120 /* It is an extension. Skip if we aren't asked to show it. */
8121 if (ext)
8122 {
8123 name++;
8124 len--;
8125 }
8126 else
8127 continue;
8128 }
8129 else if (ext)
8130 {
8131 /* It is an processor. Skip if we show only extension. */
8132 continue;
8133 }
8134
8135 /* Reserve 2 spaces for ", " or ",\0" */
8136 left -= len + 2;
8137
8138 /* Check if there is any room. */
8139 if (left >= 0)
8140 {
8141 if (p != start)
8142 {
8143 *p++ = ',';
8144 *p++ = ' ';
8145 }
8146 p = mempcpy (p, name, len);
8147 }
8148 else
8149 {
8150 /* Output the current message now and start a new one. */
8151 *p++ = ',';
8152 *p = '\0';
8153 fprintf (stream, "%s\n", message);
8154 p = start;
8155 left = size - (start - message) - len - 2;
8156
8157 gas_assert (left >= 0);
8158
8159 p = mempcpy (p, name, len);
8160 }
8161 }
8162
8163 *p = '\0';
8164 fprintf (stream, "%s\n", message);
8165}
8166
252b5132 8167void
8a2c8fef 8168md_show_usage (FILE *stream)
252b5132 8169{
4cc782b5
ILT		 8170#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8171 fprintf (stream, _("\
a38cf1db
AM		 8172 -Q ignored\n\
8173 -V print assembler version number\n\
b3b91714
AM		 8174 -k ignored\n"));
8175#endif
8176 fprintf (stream, _("\
12b55ccc 8177 -n Do not optimize code alignment\n\
b3b91714
AM		 8178 -q quieten some warnings\n"));
8179#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8180 fprintf (stream, _("\
a38cf1db 8181 -s ignored\n"));
b3b91714 8182#endif
321098a5
L		 8183#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8184 || defined (TE_PE) || defined (TE_PEP))
751d281c
L		 8185 fprintf (stream, _("\
8186 --32/--64 generate 32bit/64bit code\n"));
8187#endif
b3b91714
AM		 8188#ifdef SVR4_COMMENT_CHARS
8189 fprintf (stream, _("\
8190 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 8191#else
8192 fprintf (stream, _("\
b3b91714 8193 --divide ignored\n"));
4cc782b5 8194#endif
9103f4f4 8195 fprintf (stream, _("\
6305a203 8196 -march=CPU[,+EXTENSION...]\n\
8a2c8fef
L		 8197 generate code for CPU and EXTENSION, CPU is one of:\n"));
8198 show_arch (stream, 0);
8199 fprintf (stream, _("\
8200 EXTENSION is combination of:\n"));
8201 show_arch (stream, 1);
6305a203 8202 fprintf (stream, _("\
8a2c8fef
L		 8203 -mtune=CPU optimize for CPU, CPU is one of:\n"));
8204 show_arch (stream, 0);
ba104c83 8205 fprintf (stream, _("\
c0f3af97
L		 8206 -msse2avx encode SSE instructions with VEX prefix\n"));
8207 fprintf (stream, _("\
daf50ae7
L		 8208 -msse-check=[none|error|warning]\n\
8209 check SSE instructions\n"));
8210 fprintf (stream, _("\
ba104c83
L		 8211 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8212 fprintf (stream, _("\
8213 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8214 fprintf (stream, _("\
8215 -mindex-reg support pseudo index registers\n"));
8216 fprintf (stream, _("\
8217 -mnaked-reg don't require `%%' prefix for registers\n"));
8218 fprintf (stream, _("\
8219 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
252b5132
RH		 8220}
8221
3e73aa7c 8222#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 8223 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 8224 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 8225
8226/* Pick the target format to use. */
8227
47926f60 8228const char *
e3bb37b5 8229i386_target_format (void)
252b5132 8230{
3e73aa7c 8231 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 8232 {
8233 set_code_flag (CODE_64BIT);
0dfbf9d7 8234 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
40fb9820
L		 8235 {
8236 cpu_arch_isa_flags.bitfield.cpui186 = 1;
8237 cpu_arch_isa_flags.bitfield.cpui286 = 1;
8238 cpu_arch_isa_flags.bitfield.cpui386 = 1;
8239 cpu_arch_isa_flags.bitfield.cpui486 = 1;
8240 cpu_arch_isa_flags.bitfield.cpui586 = 1;
8241 cpu_arch_isa_flags.bitfield.cpui686 = 1;
bd5295b2 8242 cpu_arch_isa_flags.bitfield.cpuclflush = 1;
40fb9820 8243 cpu_arch_isa_flags.bitfield.cpummx= 1;
40fb9820
L		 8244 cpu_arch_isa_flags.bitfield.cpusse = 1;
8245 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
711eedef 8246 cpu_arch_isa_flags.bitfield.cpulm = 1;
40fb9820 8247 }
0dfbf9d7 8248 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
40fb9820
L		 8249 {
8250 cpu_arch_tune_flags.bitfield.cpui186 = 1;
8251 cpu_arch_tune_flags.bitfield.cpui286 = 1;
8252 cpu_arch_tune_flags.bitfield.cpui386 = 1;
8253 cpu_arch_tune_flags.bitfield.cpui486 = 1;
8254 cpu_arch_tune_flags.bitfield.cpui586 = 1;
8255 cpu_arch_tune_flags.bitfield.cpui686 = 1;
bd5295b2 8256 cpu_arch_tune_flags.bitfield.cpuclflush = 1;
40fb9820 8257 cpu_arch_tune_flags.bitfield.cpummx= 1;
40fb9820
L		 8258 cpu_arch_tune_flags.bitfield.cpusse = 1;
8259 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
8260 }
9103f4f4 8261 }
3e73aa7c 8262 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 8263 {
8264 set_code_flag (CODE_32BIT);
0dfbf9d7 8265 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
40fb9820
L		 8266 {
8267 cpu_arch_isa_flags.bitfield.cpui186 = 1;
8268 cpu_arch_isa_flags.bitfield.cpui286 = 1;
8269 cpu_arch_isa_flags.bitfield.cpui386 = 1;
8270 }
0dfbf9d7 8271 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
40fb9820
L		 8272 {
8273 cpu_arch_tune_flags.bitfield.cpui186 = 1;
8274 cpu_arch_tune_flags.bitfield.cpui286 = 1;
8275 cpu_arch_tune_flags.bitfield.cpui386 = 1;
8276 }
9103f4f4 8277 }
3e73aa7c
JH		 8278 else
8279 as_fatal (_("Unknown architecture"));
252b5132
RH		 8280 switch (OUTPUT_FLAVOR)
8281 {
9384f2ff 8282#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 8283 case bfd_target_aout_flavour:
47926f60 8284 return AOUT_TARGET_FORMAT;
4c63da97 8285#endif
9384f2ff
AM		 8286#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
8287# if defined (TE_PE) || defined (TE_PEP)
8288 case bfd_target_coff_flavour:
8289 return flag_code == CODE_64BIT ? "pe-x86-64" : "pe-i386";
8290# elif defined (TE_GO32)
0561d57c
JK		 8291 case bfd_target_coff_flavour:
8292 return "coff-go32";
9384f2ff 8293# else
252b5132
RH		 8294 case bfd_target_coff_flavour:
8295 return "coff-i386";
9384f2ff 8296# endif
4c63da97 8297#endif
3e73aa7c 8298#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 8299 case bfd_target_elf_flavour:
3e73aa7c 8300 {
e5cb08ac 8301 if (flag_code == CODE_64BIT)
4fa24527
JB		 8302 {
8303 object_64bit = 1;
8304 use_rela_relocations = 1;
8305 }
3632d14b 8306 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 8307 {
8308 if (flag_code != CODE_64BIT)
8309 as_fatal (_("Intel L1OM is 64bit only"));
8310 return ELF_TARGET_L1OM_FORMAT;
8311 }
8312 else
8313 return (flag_code == CODE_64BIT
8314 ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT);
3e73aa7c 8315 }
e57f8c65
TG		 8316#endif
8317#if defined (OBJ_MACH_O)
8318 case bfd_target_mach_o_flavour:
8319 return flag_code == CODE_64BIT ? "mach-o-x86-64" : "mach-o-i386";
4c63da97 8320#endif
252b5132
RH		 8321 default:
8322 abort ();
8323 return NULL;
8324 }
8325}
8326
47926f60 8327#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 8328
8329#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 8330void
8331i386_elf_emit_arch_note (void)
a847613f 8332{
718ddfc0 8333 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 8334 {
8335 char *p;
8336 asection *seg = now_seg;
8337 subsegT subseg = now_subseg;
8338 Elf_Internal_Note i_note;
8339 Elf_External_Note e_note;
8340 asection *note_secp;
8341 int len;
8342
8343 /* Create the .note section. */
8344 note_secp = subseg_new (".note", 0);
8345 bfd_set_section_flags (stdoutput,
8346 note_secp,
8347 SEC_HAS_CONTENTS | SEC_READONLY);
8348
8349 /* Process the arch string. */
8350 len = strlen (cpu_arch_name);
8351
8352 i_note.namesz = len + 1;
8353 i_note.descsz = 0;
8354 i_note.type = NT_ARCH;
8355 p = frag_more (sizeof (e_note.namesz));
8356 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
8357 p = frag_more (sizeof (e_note.descsz));
8358 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
8359 p = frag_more (sizeof (e_note.type));
8360 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
8361 p = frag_more (len + 1);
8362 strcpy (p, cpu_arch_name);
8363
8364 frag_align (2, 0, 0);
8365
8366 subseg_set (seg, subseg);
8367 }
8368}
8369#endif
252b5132 8370\f
252b5132
RH		 8371symbolS *
8372md_undefined_symbol (name)
8373 char *name;
8374{
18dc2407
ILT		 8375 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
8376 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
8377 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
8378 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 8379 {
8380 if (!GOT_symbol)
8381 {
8382 if (symbol_find (name))
8383 as_bad (_("GOT already in symbol table"));
8384 GOT_symbol = symbol_new (name, undefined_section,
8385 (valueT) 0, &zero_address_frag);
8386 };
8387 return GOT_symbol;
8388 }
252b5132
RH		 8389 return 0;
8390}
8391
8392/* Round up a section size to the appropriate boundary. */
47926f60 8393
252b5132
RH		 8394valueT
8395md_section_align (segment, size)
ab9da554 8396 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 8397 valueT size;
8398{
4c63da97
AM		 8399#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8400 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
8401 {
8402 /* For a.out, force the section size to be aligned. If we don't do
8403 this, BFD will align it for us, but it will not write out the
8404 final bytes of the section. This may be a bug in BFD, but it is
8405 easier to fix it here since that is how the other a.out targets
8406 work. */
8407 int align;
8408
8409 align = bfd_get_section_alignment (stdoutput, segment);
8410 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
8411 }
252b5132
RH		 8412#endif
8413
8414 return size;
8415}
8416
8417/* On the i386, PC-relative offsets are relative to the start of the
8418 next instruction. That is, the address of the offset, plus its
8419 size, since the offset is always the last part of the insn. */
8420
8421long
e3bb37b5 8422md_pcrel_from (fixS *fixP)
252b5132
RH		 8423{
8424 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
8425}
8426
8427#ifndef I386COFF
8428
8429static void
e3bb37b5 8430s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 8431{
29b0f896 8432 int temp;
252b5132 8433
8a75718c
JB		 8434#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8435 if (IS_ELF)
8436 obj_elf_section_change_hook ();
8437#endif
252b5132
RH		 8438 temp = get_absolute_expression ();
8439 subseg_set (bss_section, (subsegT) temp);
8440 demand_empty_rest_of_line ();
8441}
8442
8443#endif
8444
252b5132 8445void
e3bb37b5 8446i386_validate_fix (fixS *fixp)
252b5132
RH		 8447{
8448 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
8449 {
23df1078
JH		 8450 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
8451 {
4fa24527 8452 if (!object_64bit)
23df1078
JH		 8453 abort ();
8454 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
8455 }
8456 else
8457 {
4fa24527 8458 if (!object_64bit)
d6ab8113
JB		 8459 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
8460 else
8461 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 8462 }
252b5132
RH		 8463 fixp->fx_subsy = 0;
8464 }
8465}
8466
252b5132
RH		 8467arelent *
8468tc_gen_reloc (section, fixp)
ab9da554 8469 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 8470 fixS *fixp;
8471{
8472 arelent *rel;
8473 bfd_reloc_code_real_type code;
8474
8475 switch (fixp->fx_r_type)
8476 {
3e73aa7c
JH		 8477 case BFD_RELOC_X86_64_PLT32:
8478 case BFD_RELOC_X86_64_GOT32:
8479 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 8480 case BFD_RELOC_386_PLT32:
8481 case BFD_RELOC_386_GOT32:
8482 case BFD_RELOC_386_GOTOFF:
8483 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 8484 case BFD_RELOC_386_TLS_GD:
8485 case BFD_RELOC_386_TLS_LDM:
8486 case BFD_RELOC_386_TLS_LDO_32:
8487 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 8488 case BFD_RELOC_386_TLS_IE:
8489 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 8490 case BFD_RELOC_386_TLS_LE_32:
8491 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 8492 case BFD_RELOC_386_TLS_GOTDESC:
8493 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 8494 case BFD_RELOC_X86_64_TLSGD:
8495 case BFD_RELOC_X86_64_TLSLD:
8496 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 8497 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 8498 case BFD_RELOC_X86_64_GOTTPOFF:
8499 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 8500 case BFD_RELOC_X86_64_TPOFF64:
8501 case BFD_RELOC_X86_64_GOTOFF64:
8502 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 8503 case BFD_RELOC_X86_64_GOT64:
8504 case BFD_RELOC_X86_64_GOTPCREL64:
8505 case BFD_RELOC_X86_64_GOTPC64:
8506 case BFD_RELOC_X86_64_GOTPLT64:
8507 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 8508 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8509 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 8510 case BFD_RELOC_RVA:
8511 case BFD_RELOC_VTABLE_ENTRY:
8512 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 8513#ifdef TE_PE
8514 case BFD_RELOC_32_SECREL:
8515#endif
252b5132
RH		 8516 code = fixp->fx_r_type;
8517 break;
dbbaec26
L		 8518 case BFD_RELOC_X86_64_32S:
8519 if (!fixp->fx_pcrel)
8520 {
8521 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8522 code = fixp->fx_r_type;
8523 break;
8524 }
252b5132 8525 default:
93382f6d 8526 if (fixp->fx_pcrel)
252b5132 8527 {
93382f6d
AM		 8528 switch (fixp->fx_size)
8529 {
8530 default:
b091f402
AM		 8531 as_bad_where (fixp->fx_file, fixp->fx_line,
8532 _("can not do %d byte pc-relative relocation"),
8533 fixp->fx_size);
93382f6d
AM		 8534 code = BFD_RELOC_32_PCREL;
8535 break;
8536 case 1: code = BFD_RELOC_8_PCREL; break;
8537 case 2: code = BFD_RELOC_16_PCREL; break;
8538 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 8539#ifdef BFD64
8540 case 8: code = BFD_RELOC_64_PCREL; break;
8541#endif
93382f6d
AM		 8542 }
8543 }
8544 else
8545 {
8546 switch (fixp->fx_size)
8547 {
8548 default:
b091f402
AM		 8549 as_bad_where (fixp->fx_file, fixp->fx_line,
8550 _("can not do %d byte relocation"),
8551 fixp->fx_size);
93382f6d
AM		 8552 code = BFD_RELOC_32;
8553 break;
8554 case 1: code = BFD_RELOC_8; break;
8555 case 2: code = BFD_RELOC_16; break;
8556 case 4: code = BFD_RELOC_32; break;
937149dd 8557#ifdef BFD64
3e73aa7c 8558 case 8: code = BFD_RELOC_64; break;
937149dd 8559#endif
93382f6d 8560 }
252b5132
RH		 8561 }
8562 break;
8563 }
252b5132 8564
d182319b
JB		 8565 if ((code == BFD_RELOC_32
8566 || code == BFD_RELOC_32_PCREL
8567 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 8568 && GOT_symbol
8569 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 8570 {
4fa24527 8571 if (!object_64bit)
d6ab8113
JB		 8572 code = BFD_RELOC_386_GOTPC;
8573 else
8574 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 8575 }
7b81dfbb
AJ		 8576 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
8577 && GOT_symbol
8578 && fixp->fx_addsy == GOT_symbol)
8579 {
8580 code = BFD_RELOC_X86_64_GOTPC64;
8581 }
252b5132
RH		 8582
8583 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 8584 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
8585 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 8586
8587 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 8588
3e73aa7c
JH		 8589 if (!use_rela_relocations)
8590 {
8591 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8592 vtable entry to be used in the relocation's section offset. */
8593 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
8594 rel->address = fixp->fx_offset;
fbeb56a4
DK		 8595#if defined (OBJ_COFF) && defined (TE_PE)
8596 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
8597 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
8598 else
8599#endif
c6682705 8600 rel->addend = 0;
3e73aa7c
JH		 8601 }
8602 /* Use the rela in 64bit mode. */
252b5132 8603 else
3e73aa7c 8604 {
062cd5e7
AS		 8605 if (!fixp->fx_pcrel)
8606 rel->addend = fixp->fx_offset;
8607 else
8608 switch (code)
8609 {
8610 case BFD_RELOC_X86_64_PLT32:
8611 case BFD_RELOC_X86_64_GOT32:
8612 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 8613 case BFD_RELOC_X86_64_TLSGD:
8614 case BFD_RELOC_X86_64_TLSLD:
8615 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 8616 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8617 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 8618 rel->addend = fixp->fx_offset - fixp->fx_size;
8619 break;
8620 default:
8621 rel->addend = (section->vma
8622 - fixp->fx_size
8623 + fixp->fx_addnumber
8624 + md_pcrel_from (fixp));
8625 break;
8626 }
3e73aa7c
JH		 8627 }
8628
252b5132
RH		 8629 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
8630 if (rel->howto == NULL)
8631 {
8632 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 8633 _("cannot represent relocation type %s"),
252b5132
RH		 8634 bfd_get_reloc_code_name (code));
8635 /* Set howto to a garbage value so that we can keep going. */
8636 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 8637 gas_assert (rel->howto != NULL);
252b5132
RH		 8638 }
8639
8640 return rel;
8641}
8642
ee86248c 8643#include "tc-i386-intel.c"
54cfded0 8644
a60de03c
JB		 8645void
8646tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 8647{
a60de03c
JB		 8648 int saved_naked_reg;
8649 char saved_register_dot;
54cfded0 8650
a60de03c
JB		 8651 saved_naked_reg = allow_naked_reg;
8652 allow_naked_reg = 1;
8653 saved_register_dot = register_chars['.'];
8654 register_chars['.'] = '.';
8655 allow_pseudo_reg = 1;
8656 expression_and_evaluate (exp);
8657 allow_pseudo_reg = 0;
8658 register_chars['.'] = saved_register_dot;
8659 allow_naked_reg = saved_naked_reg;
8660
8661 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 8662 {
a60de03c
JB		 8663 if ((addressT) exp->X_add_number < i386_regtab_size)
8664 {
8665 exp->X_op = O_constant;
8666 exp->X_add_number = i386_regtab[exp->X_add_number]
8667 .dw2_regnum[flag_code >> 1];
8668 }
8669 else
8670 exp->X_op = O_illegal;
54cfded0 8671 }
54cfded0
AM		 8672}
8673
8674void
8675tc_x86_frame_initial_instructions (void)
8676{
a60de03c
JB		 8677 static unsigned int sp_regno[2];
8678
8679 if (!sp_regno[flag_code >> 1])
8680 {
8681 char *saved_input = input_line_pointer;
8682 char sp[][4] = {"esp", "rsp"};
8683 expressionS exp;
a4447b93 8684
a60de03c
JB		 8685 input_line_pointer = sp[flag_code >> 1];
8686 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 8687 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 8688 sp_regno[flag_code >> 1] = exp.X_add_number;
8689 input_line_pointer = saved_input;
8690 }
a4447b93 8691
a60de03c 8692 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
a4447b93 8693 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 8694}
d2b2c203
DJ		 8695
8696int
8697i386_elf_section_type (const char *str, size_t len)
8698{
8699 if (flag_code == CODE_64BIT
8700 && len == sizeof ("unwind") - 1
8701 && strncmp (str, "unwind", 6) == 0)
8702 return SHT_X86_64_UNWIND;
8703
8704 return -1;
8705}
bb41ade5 8706
ad5fec3b
EB		 8707#ifdef TE_SOLARIS
8708void
8709i386_solaris_fix_up_eh_frame (segT sec)
8710{
8711 if (flag_code == CODE_64BIT)
8712 elf_section_type (sec) = SHT_X86_64_UNWIND;
8713}
8714#endif
8715
bb41ade5
AM		 8716#ifdef TE_PE
8717void
8718tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
8719{
91d6fa6a 8720 expressionS exp;
bb41ade5 8721
91d6fa6a
NC		 8722 exp.X_op = O_secrel;
8723 exp.X_add_symbol = symbol;
8724 exp.X_add_number = 0;
8725 emit_expr (&exp, size);
bb41ade5
AM		 8726}
8727#endif
3b22753a
L		 8728
8729#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8730/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8731
01e1a5bc 8732bfd_vma
3b22753a
L		 8733x86_64_section_letter (int letter, char **ptr_msg)
8734{
8735 if (flag_code == CODE_64BIT)
8736 {
8737 if (letter == 'l')
8738 return SHF_X86_64_LARGE;
8739
8740 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 8741 }
3b22753a 8742 else
64e74474 8743 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 8744 return -1;
8745}
8746
01e1a5bc 8747bfd_vma
3b22753a
L		 8748x86_64_section_word (char *str, size_t len)
8749{
8620418b 8750 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 8751 return SHF_X86_64_LARGE;
8752
8753 return -1;
8754}
8755
8756static void
8757handle_large_common (int small ATTRIBUTE_UNUSED)
8758{
8759 if (flag_code != CODE_64BIT)
8760 {
8761 s_comm_internal (0, elf_common_parse);
8762 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
8763 }
8764 else
8765 {
8766 static segT lbss_section;
8767 asection *saved_com_section_ptr = elf_com_section_ptr;
8768 asection *saved_bss_section = bss_section;
8769
8770 if (lbss_section == NULL)
8771 {
8772 flagword applicable;
8773 segT seg = now_seg;
8774 subsegT subseg = now_subseg;
8775
8776 /* The .lbss section is for local .largecomm symbols. */
8777 lbss_section = subseg_new (".lbss", 0);
8778 applicable = bfd_applicable_section_flags (stdoutput);
8779 bfd_set_section_flags (stdoutput, lbss_section,
8780 applicable & SEC_ALLOC);
8781 seg_info (lbss_section)->bss = 1;
8782
8783 subseg_set (seg, subseg);
8784 }
8785
8786 elf_com_section_ptr = &_bfd_elf_large_com_section;
8787 bss_section = lbss_section;
8788
8789 s_comm_internal (0, elf_common_parse);
8790
8791 elf_com_section_ptr = saved_com_section_ptr;
8792 bss_section = saved_bss_section;
8793 }
8794}
8795#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
Empty description
This page took 2.588137 seconds and 4 git commands to generate.