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b534c6d3 | 1 | /* tc-i386.c -- Assemble code for the Intel 80386 |
219d1afa | 2 | Copyright (C) 1989-2018 Free Software Foundation, Inc. |
252b5132 RH |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 8 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
9 | any later version. |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
18 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
19 | 02110-1301, USA. */ | |
252b5132 | 20 | |
47926f60 KH |
21 | /* Intel 80386 machine specific gas. |
22 | Written by Eliot Dresselhaus ([email protected]). | |
3e73aa7c | 23 | x86_64 support by Jan Hubicka ([email protected]) |
0f10071e | 24 | VIA PadLock support by Michal Ludvig ([email protected]) |
47926f60 KH |
25 | Bugs & suggestions are completely welcome. This is free software. |
26 | Please help us make it better. */ | |
252b5132 | 27 | |
252b5132 | 28 | #include "as.h" |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 | 30 | #include "subsegs.h" |
316e2c05 | 31 | #include "dwarf2dbg.h" |
54cfded0 | 32 | #include "dw2gencfi.h" |
d2b2c203 | 33 | #include "elf/x86-64.h" |
40fb9820 | 34 | #include "opcodes/i386-init.h" |
252b5132 | 35 | |
252b5132 RH |
36 | #ifndef REGISTER_WARNINGS |
37 | #define REGISTER_WARNINGS 1 | |
38 | #endif | |
39 | ||
c3332e24 | 40 | #ifndef INFER_ADDR_PREFIX |
eecb386c | 41 | #define INFER_ADDR_PREFIX 1 |
c3332e24 AM |
42 | #endif |
43 | ||
29b0f896 AM |
44 | #ifndef DEFAULT_ARCH |
45 | #define DEFAULT_ARCH "i386" | |
246fcdee | 46 | #endif |
252b5132 | 47 | |
edde18a5 AM |
48 | #ifndef INLINE |
49 | #if __GNUC__ >= 2 | |
50 | #define INLINE __inline__ | |
51 | #else | |
52 | #define INLINE | |
53 | #endif | |
54 | #endif | |
55 | ||
6305a203 L |
56 | /* Prefixes will be emitted in the order defined below. |
57 | WAIT_PREFIX must be the first prefix since FWAIT is really is an | |
58 | instruction, and so must come before any prefixes. | |
59 | The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX, | |
42164a71 | 60 | REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */ |
6305a203 L |
61 | #define WAIT_PREFIX 0 |
62 | #define SEG_PREFIX 1 | |
63 | #define ADDR_PREFIX 2 | |
64 | #define DATA_PREFIX 3 | |
c32fa91d | 65 | #define REP_PREFIX 4 |
42164a71 | 66 | #define HLE_PREFIX REP_PREFIX |
7e8b059b | 67 | #define BND_PREFIX REP_PREFIX |
c32fa91d | 68 | #define LOCK_PREFIX 5 |
4e9ac44a L |
69 | #define REX_PREFIX 6 /* must come last. */ |
70 | #define MAX_PREFIXES 7 /* max prefixes per opcode */ | |
6305a203 L |
71 | |
72 | /* we define the syntax here (modulo base,index,scale syntax) */ | |
73 | #define REGISTER_PREFIX '%' | |
74 | #define IMMEDIATE_PREFIX '$' | |
75 | #define ABSOLUTE_PREFIX '*' | |
76 | ||
77 | /* these are the instruction mnemonic suffixes in AT&T syntax or | |
78 | memory operand size in Intel syntax. */ | |
79 | #define WORD_MNEM_SUFFIX 'w' | |
80 | #define BYTE_MNEM_SUFFIX 'b' | |
81 | #define SHORT_MNEM_SUFFIX 's' | |
82 | #define LONG_MNEM_SUFFIX 'l' | |
83 | #define QWORD_MNEM_SUFFIX 'q' | |
6305a203 L |
84 | /* Intel Syntax. Use a non-ascii letter since since it never appears |
85 | in instructions. */ | |
86 | #define LONG_DOUBLE_MNEM_SUFFIX '\1' | |
87 | ||
88 | #define END_OF_INSN '\0' | |
89 | ||
90 | /* | |
91 | 'templates' is for grouping together 'template' structures for opcodes | |
92 | of the same name. This is only used for storing the insns in the grand | |
93 | ole hash table of insns. | |
94 | The templates themselves start at START and range up to (but not including) | |
95 | END. | |
96 | */ | |
97 | typedef struct | |
98 | { | |
d3ce72d0 NC |
99 | const insn_template *start; |
100 | const insn_template *end; | |
6305a203 L |
101 | } |
102 | templates; | |
103 | ||
104 | /* 386 operand encoding bytes: see 386 book for details of this. */ | |
105 | typedef struct | |
106 | { | |
107 | unsigned int regmem; /* codes register or memory operand */ | |
108 | unsigned int reg; /* codes register operand (or extended opcode) */ | |
109 | unsigned int mode; /* how to interpret regmem & reg */ | |
110 | } | |
111 | modrm_byte; | |
112 | ||
113 | /* x86-64 extension prefix. */ | |
114 | typedef int rex_byte; | |
115 | ||
6305a203 L |
116 | /* 386 opcode byte to code indirect addressing. */ |
117 | typedef struct | |
118 | { | |
119 | unsigned base; | |
120 | unsigned index; | |
121 | unsigned scale; | |
122 | } | |
123 | sib_byte; | |
124 | ||
6305a203 L |
125 | /* x86 arch names, types and features */ |
126 | typedef struct | |
127 | { | |
128 | const char *name; /* arch name */ | |
8a2c8fef | 129 | unsigned int len; /* arch string length */ |
6305a203 L |
130 | enum processor_type type; /* arch type */ |
131 | i386_cpu_flags flags; /* cpu feature flags */ | |
8a2c8fef | 132 | unsigned int skip; /* show_arch should skip this. */ |
6305a203 L |
133 | } |
134 | arch_entry; | |
135 | ||
293f5f65 L |
136 | /* Used to turn off indicated flags. */ |
137 | typedef struct | |
138 | { | |
139 | const char *name; /* arch name */ | |
140 | unsigned int len; /* arch string length */ | |
141 | i386_cpu_flags flags; /* cpu feature flags */ | |
142 | } | |
143 | noarch_entry; | |
144 | ||
78f12dd3 | 145 | static void update_code_flag (int, int); |
e3bb37b5 L |
146 | static void set_code_flag (int); |
147 | static void set_16bit_gcc_code_flag (int); | |
148 | static void set_intel_syntax (int); | |
1efbbeb4 | 149 | static void set_intel_mnemonic (int); |
db51cc60 | 150 | static void set_allow_index_reg (int); |
7bab8ab5 | 151 | static void set_check (int); |
e3bb37b5 | 152 | static void set_cpu_arch (int); |
6482c264 | 153 | #ifdef TE_PE |
e3bb37b5 | 154 | static void pe_directive_secrel (int); |
6482c264 | 155 | #endif |
e3bb37b5 L |
156 | static void signed_cons (int); |
157 | static char *output_invalid (int c); | |
ee86248c JB |
158 | static int i386_finalize_immediate (segT, expressionS *, i386_operand_type, |
159 | const char *); | |
160 | static int i386_finalize_displacement (segT, expressionS *, i386_operand_type, | |
161 | const char *); | |
a7619375 | 162 | static int i386_att_operand (char *); |
e3bb37b5 | 163 | static int i386_intel_operand (char *, int); |
ee86248c JB |
164 | static int i386_intel_simplify (expressionS *); |
165 | static int i386_intel_parse_name (const char *, expressionS *); | |
e3bb37b5 L |
166 | static const reg_entry *parse_register (char *, char **); |
167 | static char *parse_insn (char *, char *); | |
168 | static char *parse_operands (char *, const char *); | |
169 | static void swap_operands (void); | |
4d456e3d | 170 | static void swap_2_operands (int, int); |
e3bb37b5 L |
171 | static void optimize_imm (void); |
172 | static void optimize_disp (void); | |
83b16ac6 | 173 | static const insn_template *match_template (char); |
e3bb37b5 L |
174 | static int check_string (void); |
175 | static int process_suffix (void); | |
176 | static int check_byte_reg (void); | |
177 | static int check_long_reg (void); | |
178 | static int check_qword_reg (void); | |
179 | static int check_word_reg (void); | |
180 | static int finalize_imm (void); | |
181 | static int process_operands (void); | |
182 | static const seg_entry *build_modrm_byte (void); | |
183 | static void output_insn (void); | |
184 | static void output_imm (fragS *, offsetT); | |
185 | static void output_disp (fragS *, offsetT); | |
29b0f896 | 186 | #ifndef I386COFF |
e3bb37b5 | 187 | static void s_bss (int); |
252b5132 | 188 | #endif |
17d4e2a2 L |
189 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
190 | static void handle_large_common (int small ATTRIBUTE_UNUSED); | |
b4a3a7b4 L |
191 | |
192 | /* GNU_PROPERTY_X86_ISA_1_USED. */ | |
193 | static unsigned int x86_isa_1_used; | |
194 | /* GNU_PROPERTY_X86_FEATURE_2_USED. */ | |
195 | static unsigned int x86_feature_2_used; | |
196 | /* Generate x86 used ISA and feature properties. */ | |
197 | static unsigned int x86_used_note = DEFAULT_X86_USED_NOTE; | |
17d4e2a2 | 198 | #endif |
252b5132 | 199 | |
a847613f | 200 | static const char *default_arch = DEFAULT_ARCH; |
3e73aa7c | 201 | |
43234a1e L |
202 | /* This struct describes rounding control and SAE in the instruction. */ |
203 | struct RC_Operation | |
204 | { | |
205 | enum rc_type | |
206 | { | |
207 | rne = 0, | |
208 | rd, | |
209 | ru, | |
210 | rz, | |
211 | saeonly | |
212 | } type; | |
213 | int operand; | |
214 | }; | |
215 | ||
216 | static struct RC_Operation rc_op; | |
217 | ||
218 | /* The struct describes masking, applied to OPERAND in the instruction. | |
219 | MASK is a pointer to the corresponding mask register. ZEROING tells | |
220 | whether merging or zeroing mask is used. */ | |
221 | struct Mask_Operation | |
222 | { | |
223 | const reg_entry *mask; | |
224 | unsigned int zeroing; | |
225 | /* The operand where this operation is associated. */ | |
226 | int operand; | |
227 | }; | |
228 | ||
229 | static struct Mask_Operation mask_op; | |
230 | ||
231 | /* The struct describes broadcasting, applied to OPERAND. FACTOR is | |
232 | broadcast factor. */ | |
233 | struct Broadcast_Operation | |
234 | { | |
8e6e0792 | 235 | /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */ |
43234a1e L |
236 | int type; |
237 | ||
238 | /* Index of broadcasted operand. */ | |
239 | int operand; | |
4a1b91ea L |
240 | |
241 | /* Number of bytes to broadcast. */ | |
242 | int bytes; | |
43234a1e L |
243 | }; |
244 | ||
245 | static struct Broadcast_Operation broadcast_op; | |
246 | ||
c0f3af97 L |
247 | /* VEX prefix. */ |
248 | typedef struct | |
249 | { | |
43234a1e L |
250 | /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */ |
251 | unsigned char bytes[4]; | |
c0f3af97 L |
252 | unsigned int length; |
253 | /* Destination or source register specifier. */ | |
254 | const reg_entry *register_specifier; | |
255 | } vex_prefix; | |
256 | ||
252b5132 | 257 | /* 'md_assemble ()' gathers together information and puts it into a |
47926f60 | 258 | i386_insn. */ |
252b5132 | 259 | |
520dc8e8 AM |
260 | union i386_op |
261 | { | |
262 | expressionS *disps; | |
263 | expressionS *imms; | |
264 | const reg_entry *regs; | |
265 | }; | |
266 | ||
a65babc9 L |
267 | enum i386_error |
268 | { | |
86e026a4 | 269 | operand_size_mismatch, |
a65babc9 L |
270 | operand_type_mismatch, |
271 | register_type_mismatch, | |
272 | number_of_operands_mismatch, | |
273 | invalid_instruction_suffix, | |
274 | bad_imm4, | |
a65babc9 L |
275 | unsupported_with_intel_mnemonic, |
276 | unsupported_syntax, | |
6c30d220 L |
277 | unsupported, |
278 | invalid_vsib_address, | |
7bab8ab5 | 279 | invalid_vector_register_set, |
43234a1e L |
280 | unsupported_vector_index_register, |
281 | unsupported_broadcast, | |
43234a1e L |
282 | broadcast_needed, |
283 | unsupported_masking, | |
284 | mask_not_on_destination, | |
285 | no_default_mask, | |
286 | unsupported_rc_sae, | |
287 | rc_sae_operand_not_last_imm, | |
288 | invalid_register_operand, | |
a65babc9 L |
289 | }; |
290 | ||
252b5132 RH |
291 | struct _i386_insn |
292 | { | |
47926f60 | 293 | /* TM holds the template for the insn were currently assembling. */ |
d3ce72d0 | 294 | insn_template tm; |
252b5132 | 295 | |
7d5e4556 L |
296 | /* SUFFIX holds the instruction size suffix for byte, word, dword |
297 | or qword, if given. */ | |
252b5132 RH |
298 | char suffix; |
299 | ||
47926f60 | 300 | /* OPERANDS gives the number of given operands. */ |
252b5132 RH |
301 | unsigned int operands; |
302 | ||
303 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number | |
304 | of given register, displacement, memory operands and immediate | |
47926f60 | 305 | operands. */ |
252b5132 RH |
306 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; |
307 | ||
308 | /* TYPES [i] is the type (see above #defines) which tells us how to | |
520dc8e8 | 309 | use OP[i] for the corresponding operand. */ |
40fb9820 | 310 | i386_operand_type types[MAX_OPERANDS]; |
252b5132 | 311 | |
520dc8e8 AM |
312 | /* Displacement expression, immediate expression, or register for each |
313 | operand. */ | |
314 | union i386_op op[MAX_OPERANDS]; | |
252b5132 | 315 | |
3e73aa7c JH |
316 | /* Flags for operands. */ |
317 | unsigned int flags[MAX_OPERANDS]; | |
318 | #define Operand_PCrel 1 | |
c48dadc9 | 319 | #define Operand_Mem 2 |
3e73aa7c | 320 | |
252b5132 | 321 | /* Relocation type for operand */ |
f86103b7 | 322 | enum bfd_reloc_code_real reloc[MAX_OPERANDS]; |
252b5132 | 323 | |
252b5132 RH |
324 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode |
325 | the base index byte below. */ | |
326 | const reg_entry *base_reg; | |
327 | const reg_entry *index_reg; | |
328 | unsigned int log2_scale_factor; | |
329 | ||
330 | /* SEG gives the seg_entries of this insn. They are zero unless | |
47926f60 | 331 | explicit segment overrides are given. */ |
ce8a8b2f | 332 | const seg_entry *seg[2]; |
252b5132 | 333 | |
8325cc63 JB |
334 | /* Copied first memory operand string, for re-checking. */ |
335 | char *memop1_string; | |
336 | ||
252b5132 RH |
337 | /* PREFIX holds all the given prefix opcodes (usually null). |
338 | PREFIXES is the number of prefix opcodes. */ | |
339 | unsigned int prefixes; | |
340 | unsigned char prefix[MAX_PREFIXES]; | |
341 | ||
b4a3a7b4 L |
342 | /* Has MMX register operands. */ |
343 | bfd_boolean has_regmmx; | |
344 | ||
345 | /* Has XMM register operands. */ | |
346 | bfd_boolean has_regxmm; | |
347 | ||
348 | /* Has YMM register operands. */ | |
349 | bfd_boolean has_regymm; | |
350 | ||
351 | /* Has ZMM register operands. */ | |
352 | bfd_boolean has_regzmm; | |
353 | ||
252b5132 | 354 | /* RM and SIB are the modrm byte and the sib byte where the |
c1e679ec | 355 | addressing modes of this insn are encoded. */ |
252b5132 | 356 | modrm_byte rm; |
3e73aa7c | 357 | rex_byte rex; |
43234a1e | 358 | rex_byte vrex; |
252b5132 | 359 | sib_byte sib; |
c0f3af97 | 360 | vex_prefix vex; |
b6169b20 | 361 | |
43234a1e L |
362 | /* Masking attributes. */ |
363 | struct Mask_Operation *mask; | |
364 | ||
365 | /* Rounding control and SAE attributes. */ | |
366 | struct RC_Operation *rounding; | |
367 | ||
368 | /* Broadcasting attributes. */ | |
369 | struct Broadcast_Operation *broadcast; | |
370 | ||
371 | /* Compressed disp8*N attribute. */ | |
372 | unsigned int memshift; | |
373 | ||
86fa6981 L |
374 | /* Prefer load or store in encoding. */ |
375 | enum | |
376 | { | |
377 | dir_encoding_default = 0, | |
378 | dir_encoding_load, | |
64c49ab3 JB |
379 | dir_encoding_store, |
380 | dir_encoding_swap | |
86fa6981 | 381 | } dir_encoding; |
891edac4 | 382 | |
a501d77e L |
383 | /* Prefer 8bit or 32bit displacement in encoding. */ |
384 | enum | |
385 | { | |
386 | disp_encoding_default = 0, | |
387 | disp_encoding_8bit, | |
388 | disp_encoding_32bit | |
389 | } disp_encoding; | |
f8a5c266 | 390 | |
6b6b6807 L |
391 | /* Prefer the REX byte in encoding. */ |
392 | bfd_boolean rex_encoding; | |
393 | ||
b6f8c7c4 L |
394 | /* Disable instruction size optimization. */ |
395 | bfd_boolean no_optimize; | |
396 | ||
86fa6981 L |
397 | /* How to encode vector instructions. */ |
398 | enum | |
399 | { | |
400 | vex_encoding_default = 0, | |
401 | vex_encoding_vex2, | |
402 | vex_encoding_vex3, | |
403 | vex_encoding_evex | |
404 | } vec_encoding; | |
405 | ||
d5de92cf L |
406 | /* REP prefix. */ |
407 | const char *rep_prefix; | |
408 | ||
165de32a L |
409 | /* HLE prefix. */ |
410 | const char *hle_prefix; | |
42164a71 | 411 | |
7e8b059b L |
412 | /* Have BND prefix. */ |
413 | const char *bnd_prefix; | |
414 | ||
04ef582a L |
415 | /* Have NOTRACK prefix. */ |
416 | const char *notrack_prefix; | |
417 | ||
891edac4 | 418 | /* Error message. */ |
a65babc9 | 419 | enum i386_error error; |
252b5132 RH |
420 | }; |
421 | ||
422 | typedef struct _i386_insn i386_insn; | |
423 | ||
43234a1e L |
424 | /* Link RC type with corresponding string, that'll be looked for in |
425 | asm. */ | |
426 | struct RC_name | |
427 | { | |
428 | enum rc_type type; | |
429 | const char *name; | |
430 | unsigned int len; | |
431 | }; | |
432 | ||
433 | static const struct RC_name RC_NamesTable[] = | |
434 | { | |
435 | { rne, STRING_COMMA_LEN ("rn-sae") }, | |
436 | { rd, STRING_COMMA_LEN ("rd-sae") }, | |
437 | { ru, STRING_COMMA_LEN ("ru-sae") }, | |
438 | { rz, STRING_COMMA_LEN ("rz-sae") }, | |
439 | { saeonly, STRING_COMMA_LEN ("sae") }, | |
440 | }; | |
441 | ||
252b5132 RH |
442 | /* List of chars besides those in app.c:symbol_chars that can start an |
443 | operand. Used to prevent the scrubber eating vital white-space. */ | |
86fa6981 | 444 | const char extra_symbol_chars[] = "*%-([{}" |
252b5132 | 445 | #ifdef LEX_AT |
32137342 NC |
446 | "@" |
447 | #endif | |
448 | #ifdef LEX_QM | |
449 | "?" | |
252b5132 | 450 | #endif |
32137342 | 451 | ; |
252b5132 | 452 | |
29b0f896 AM |
453 | #if (defined (TE_I386AIX) \ |
454 | || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \ | |
3896cfd5 | 455 | && !defined (TE_GNU) \ |
29b0f896 | 456 | && !defined (TE_LINUX) \ |
8d63c93e | 457 | && !defined (TE_NACL) \ |
29b0f896 | 458 | && !defined (TE_FreeBSD) \ |
5b806d27 | 459 | && !defined (TE_DragonFly) \ |
29b0f896 | 460 | && !defined (TE_NetBSD))) |
252b5132 | 461 | /* This array holds the chars that always start a comment. If the |
b3b91714 AM |
462 | pre-processor is disabled, these aren't very useful. The option |
463 | --divide will remove '/' from this list. */ | |
464 | const char *i386_comment_chars = "#/"; | |
465 | #define SVR4_COMMENT_CHARS 1 | |
252b5132 | 466 | #define PREFIX_SEPARATOR '\\' |
252b5132 | 467 | |
b3b91714 AM |
468 | #else |
469 | const char *i386_comment_chars = "#"; | |
470 | #define PREFIX_SEPARATOR '/' | |
471 | #endif | |
472 | ||
252b5132 RH |
473 | /* This array holds the chars that only start a comment at the beginning of |
474 | a line. If the line seems to have the form '# 123 filename' | |
ce8a8b2f AM |
475 | .line and .file directives will appear in the pre-processed output. |
476 | Note that input_file.c hand checks for '#' at the beginning of the | |
252b5132 | 477 | first line of the input file. This is because the compiler outputs |
ce8a8b2f AM |
478 | #NO_APP at the beginning of its output. |
479 | Also note that comments started like this one will always work if | |
252b5132 | 480 | '/' isn't otherwise defined. */ |
b3b91714 | 481 | const char line_comment_chars[] = "#/"; |
252b5132 | 482 | |
63a0b638 | 483 | const char line_separator_chars[] = ";"; |
252b5132 | 484 | |
ce8a8b2f AM |
485 | /* Chars that can be used to separate mant from exp in floating point |
486 | nums. */ | |
252b5132 RH |
487 | const char EXP_CHARS[] = "eE"; |
488 | ||
ce8a8b2f AM |
489 | /* Chars that mean this number is a floating point constant |
490 | As in 0f12.456 | |
491 | or 0d1.2345e12. */ | |
252b5132 RH |
492 | const char FLT_CHARS[] = "fFdDxX"; |
493 | ||
ce8a8b2f | 494 | /* Tables for lexical analysis. */ |
252b5132 RH |
495 | static char mnemonic_chars[256]; |
496 | static char register_chars[256]; | |
497 | static char operand_chars[256]; | |
498 | static char identifier_chars[256]; | |
499 | static char digit_chars[256]; | |
500 | ||
ce8a8b2f | 501 | /* Lexical macros. */ |
252b5132 RH |
502 | #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x]) |
503 | #define is_operand_char(x) (operand_chars[(unsigned char) x]) | |
504 | #define is_register_char(x) (register_chars[(unsigned char) x]) | |
505 | #define is_space_char(x) ((x) == ' ') | |
506 | #define is_identifier_char(x) (identifier_chars[(unsigned char) x]) | |
507 | #define is_digit_char(x) (digit_chars[(unsigned char) x]) | |
508 | ||
0234cb7c | 509 | /* All non-digit non-letter characters that may occur in an operand. */ |
252b5132 RH |
510 | static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; |
511 | ||
512 | /* md_assemble() always leaves the strings it's passed unaltered. To | |
513 | effect this we maintain a stack of saved characters that we've smashed | |
514 | with '\0's (indicating end of strings for various sub-fields of the | |
47926f60 | 515 | assembler instruction). */ |
252b5132 | 516 | static char save_stack[32]; |
ce8a8b2f | 517 | static char *save_stack_p; |
252b5132 RH |
518 | #define END_STRING_AND_SAVE(s) \ |
519 | do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) | |
520 | #define RESTORE_END_STRING(s) \ | |
521 | do { *(s) = *--save_stack_p; } while (0) | |
522 | ||
47926f60 | 523 | /* The instruction we're assembling. */ |
252b5132 RH |
524 | static i386_insn i; |
525 | ||
526 | /* Possible templates for current insn. */ | |
527 | static const templates *current_templates; | |
528 | ||
31b2323c L |
529 | /* Per instruction expressionS buffers: max displacements & immediates. */ |
530 | static expressionS disp_expressions[MAX_MEMORY_OPERANDS]; | |
531 | static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS]; | |
252b5132 | 532 | |
47926f60 | 533 | /* Current operand we are working on. */ |
ee86248c | 534 | static int this_operand = -1; |
252b5132 | 535 | |
3e73aa7c JH |
536 | /* We support four different modes. FLAG_CODE variable is used to distinguish |
537 | these. */ | |
538 | ||
539 | enum flag_code { | |
540 | CODE_32BIT, | |
541 | CODE_16BIT, | |
542 | CODE_64BIT }; | |
543 | ||
544 | static enum flag_code flag_code; | |
4fa24527 | 545 | static unsigned int object_64bit; |
862be3fb | 546 | static unsigned int disallow_64bit_reloc; |
3e73aa7c JH |
547 | static int use_rela_relocations = 0; |
548 | ||
7af8ed2d NC |
549 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
550 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ | |
551 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) | |
552 | ||
351f65ca L |
553 | /* The ELF ABI to use. */ |
554 | enum x86_elf_abi | |
555 | { | |
556 | I386_ABI, | |
7f56bc95 L |
557 | X86_64_ABI, |
558 | X86_64_X32_ABI | |
351f65ca L |
559 | }; |
560 | ||
561 | static enum x86_elf_abi x86_elf_abi = I386_ABI; | |
7af8ed2d | 562 | #endif |
351f65ca | 563 | |
167ad85b TG |
564 | #if defined (TE_PE) || defined (TE_PEP) |
565 | /* Use big object file format. */ | |
566 | static int use_big_obj = 0; | |
567 | #endif | |
568 | ||
8dcea932 L |
569 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
570 | /* 1 if generating code for a shared library. */ | |
571 | static int shared = 0; | |
572 | #endif | |
573 | ||
47926f60 KH |
574 | /* 1 for intel syntax, |
575 | 0 if att syntax. */ | |
576 | static int intel_syntax = 0; | |
252b5132 | 577 | |
e89c5eaa L |
578 | /* 1 for Intel64 ISA, |
579 | 0 if AMD64 ISA. */ | |
580 | static int intel64; | |
581 | ||
1efbbeb4 L |
582 | /* 1 for intel mnemonic, |
583 | 0 if att mnemonic. */ | |
584 | static int intel_mnemonic = !SYSV386_COMPAT; | |
585 | ||
a60de03c JB |
586 | /* 1 if pseudo registers are permitted. */ |
587 | static int allow_pseudo_reg = 0; | |
588 | ||
47926f60 KH |
589 | /* 1 if register prefix % not required. */ |
590 | static int allow_naked_reg = 0; | |
252b5132 | 591 | |
33eaf5de | 592 | /* 1 if the assembler should add BND prefix for all control-transferring |
7e8b059b L |
593 | instructions supporting it, even if this prefix wasn't specified |
594 | explicitly. */ | |
595 | static int add_bnd_prefix = 0; | |
596 | ||
ba104c83 | 597 | /* 1 if pseudo index register, eiz/riz, is allowed . */ |
db51cc60 L |
598 | static int allow_index_reg = 0; |
599 | ||
d022bddd IT |
600 | /* 1 if the assembler should ignore LOCK prefix, even if it was |
601 | specified explicitly. */ | |
602 | static int omit_lock_prefix = 0; | |
603 | ||
e4e00185 AS |
604 | /* 1 if the assembler should encode lfence, mfence, and sfence as |
605 | "lock addl $0, (%{re}sp)". */ | |
606 | static int avoid_fence = 0; | |
607 | ||
0cb4071e L |
608 | /* 1 if the assembler should generate relax relocations. */ |
609 | ||
610 | static int generate_relax_relocations | |
611 | = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS; | |
612 | ||
7bab8ab5 | 613 | static enum check_kind |
daf50ae7 | 614 | { |
7bab8ab5 JB |
615 | check_none = 0, |
616 | check_warning, | |
617 | check_error | |
daf50ae7 | 618 | } |
7bab8ab5 | 619 | sse_check, operand_check = check_warning; |
daf50ae7 | 620 | |
b6f8c7c4 L |
621 | /* Optimization: |
622 | 1. Clear the REX_W bit with register operand if possible. | |
623 | 2. Above plus use 128bit vector instruction to clear the full vector | |
624 | register. | |
625 | */ | |
626 | static int optimize = 0; | |
627 | ||
628 | /* Optimization: | |
629 | 1. Clear the REX_W bit with register operand if possible. | |
630 | 2. Above plus use 128bit vector instruction to clear the full vector | |
631 | register. | |
632 | 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to | |
633 | "testb $imm7,%r8". | |
634 | */ | |
635 | static int optimize_for_space = 0; | |
636 | ||
2ca3ace5 L |
637 | /* Register prefix used for error message. */ |
638 | static const char *register_prefix = "%"; | |
639 | ||
47926f60 KH |
640 | /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter, |
641 | leave, push, and pop instructions so that gcc has the same stack | |
642 | frame as in 32 bit mode. */ | |
643 | static char stackop_size = '\0'; | |
eecb386c | 644 | |
12b55ccc L |
645 | /* Non-zero to optimize code alignment. */ |
646 | int optimize_align_code = 1; | |
647 | ||
47926f60 KH |
648 | /* Non-zero to quieten some warnings. */ |
649 | static int quiet_warnings = 0; | |
a38cf1db | 650 | |
47926f60 KH |
651 | /* CPU name. */ |
652 | static const char *cpu_arch_name = NULL; | |
6305a203 | 653 | static char *cpu_sub_arch_name = NULL; |
a38cf1db | 654 | |
47926f60 | 655 | /* CPU feature flags. */ |
40fb9820 L |
656 | static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS; |
657 | ||
ccc9c027 L |
658 | /* If we have selected a cpu we are generating instructions for. */ |
659 | static int cpu_arch_tune_set = 0; | |
660 | ||
9103f4f4 | 661 | /* Cpu we are generating instructions for. */ |
fbf3f584 | 662 | enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN; |
9103f4f4 L |
663 | |
664 | /* CPU feature flags of cpu we are generating instructions for. */ | |
40fb9820 | 665 | static i386_cpu_flags cpu_arch_tune_flags; |
9103f4f4 | 666 | |
ccc9c027 | 667 | /* CPU instruction set architecture used. */ |
fbf3f584 | 668 | enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN; |
ccc9c027 | 669 | |
9103f4f4 | 670 | /* CPU feature flags of instruction set architecture used. */ |
fbf3f584 | 671 | i386_cpu_flags cpu_arch_isa_flags; |
9103f4f4 | 672 | |
fddf5b5b AM |
673 | /* If set, conditional jumps are not automatically promoted to handle |
674 | larger than a byte offset. */ | |
675 | static unsigned int no_cond_jump_promotion = 0; | |
676 | ||
c0f3af97 L |
677 | /* Encode SSE instructions with VEX prefix. */ |
678 | static unsigned int sse2avx; | |
679 | ||
539f890d L |
680 | /* Encode scalar AVX instructions with specific vector length. */ |
681 | static enum | |
682 | { | |
683 | vex128 = 0, | |
684 | vex256 | |
685 | } avxscalar; | |
686 | ||
43234a1e L |
687 | /* Encode scalar EVEX LIG instructions with specific vector length. */ |
688 | static enum | |
689 | { | |
690 | evexl128 = 0, | |
691 | evexl256, | |
692 | evexl512 | |
693 | } evexlig; | |
694 | ||
695 | /* Encode EVEX WIG instructions with specific evex.w. */ | |
696 | static enum | |
697 | { | |
698 | evexw0 = 0, | |
699 | evexw1 | |
700 | } evexwig; | |
701 | ||
d3d3c6db IT |
702 | /* Value to encode in EVEX RC bits, for SAE-only instructions. */ |
703 | static enum rc_type evexrcig = rne; | |
704 | ||
29b0f896 | 705 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ |
87c245cc | 706 | static symbolS *GOT_symbol; |
29b0f896 | 707 | |
a4447b93 RH |
708 | /* The dwarf2 return column, adjusted for 32 or 64 bit. */ |
709 | unsigned int x86_dwarf2_return_column; | |
710 | ||
711 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ | |
712 | int x86_cie_data_alignment; | |
713 | ||
252b5132 | 714 | /* Interface to relax_segment. |
fddf5b5b AM |
715 | There are 3 major relax states for 386 jump insns because the |
716 | different types of jumps add different sizes to frags when we're | |
717 | figuring out what sort of jump to choose to reach a given label. */ | |
252b5132 | 718 | |
47926f60 | 719 | /* Types. */ |
93c2a809 AM |
720 | #define UNCOND_JUMP 0 |
721 | #define COND_JUMP 1 | |
722 | #define COND_JUMP86 2 | |
fddf5b5b | 723 | |
47926f60 | 724 | /* Sizes. */ |
252b5132 RH |
725 | #define CODE16 1 |
726 | #define SMALL 0 | |
29b0f896 | 727 | #define SMALL16 (SMALL | CODE16) |
252b5132 | 728 | #define BIG 2 |
29b0f896 | 729 | #define BIG16 (BIG | CODE16) |
252b5132 RH |
730 | |
731 | #ifndef INLINE | |
732 | #ifdef __GNUC__ | |
733 | #define INLINE __inline__ | |
734 | #else | |
735 | #define INLINE | |
736 | #endif | |
737 | #endif | |
738 | ||
fddf5b5b AM |
739 | #define ENCODE_RELAX_STATE(type, size) \ |
740 | ((relax_substateT) (((type) << 2) | (size))) | |
741 | #define TYPE_FROM_RELAX_STATE(s) \ | |
742 | ((s) >> 2) | |
743 | #define DISP_SIZE_FROM_RELAX_STATE(s) \ | |
744 | ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1))) | |
252b5132 RH |
745 | |
746 | /* This table is used by relax_frag to promote short jumps to long | |
747 | ones where necessary. SMALL (short) jumps may be promoted to BIG | |
748 | (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We | |
749 | don't allow a short jump in a 32 bit code segment to be promoted to | |
750 | a 16 bit offset jump because it's slower (requires data size | |
751 | prefix), and doesn't work, unless the destination is in the bottom | |
752 | 64k of the code segment (The top 16 bits of eip are zeroed). */ | |
753 | ||
754 | const relax_typeS md_relax_table[] = | |
755 | { | |
24eab124 AM |
756 | /* The fields are: |
757 | 1) most positive reach of this state, | |
758 | 2) most negative reach of this state, | |
93c2a809 | 759 | 3) how many bytes this mode will have in the variable part of the frag |
ce8a8b2f | 760 | 4) which index into the table to try if we can't fit into this one. */ |
252b5132 | 761 | |
fddf5b5b | 762 | /* UNCOND_JUMP states. */ |
93c2a809 AM |
763 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, |
764 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, | |
765 | /* dword jmp adds 4 bytes to frag: | |
766 | 0 extra opcode bytes, 4 displacement bytes. */ | |
252b5132 | 767 | {0, 0, 4, 0}, |
93c2a809 AM |
768 | /* word jmp adds 2 byte2 to frag: |
769 | 0 extra opcode bytes, 2 displacement bytes. */ | |
252b5132 RH |
770 | {0, 0, 2, 0}, |
771 | ||
93c2a809 AM |
772 | /* COND_JUMP states. */ |
773 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, | |
774 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, | |
775 | /* dword conditionals adds 5 bytes to frag: | |
776 | 1 extra opcode byte, 4 displacement bytes. */ | |
777 | {0, 0, 5, 0}, | |
fddf5b5b | 778 | /* word conditionals add 3 bytes to frag: |
93c2a809 AM |
779 | 1 extra opcode byte, 2 displacement bytes. */ |
780 | {0, 0, 3, 0}, | |
781 | ||
782 | /* COND_JUMP86 states. */ | |
783 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)}, | |
784 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)}, | |
785 | /* dword conditionals adds 5 bytes to frag: | |
786 | 1 extra opcode byte, 4 displacement bytes. */ | |
787 | {0, 0, 5, 0}, | |
788 | /* word conditionals add 4 bytes to frag: | |
789 | 1 displacement byte and a 3 byte long branch insn. */ | |
790 | {0, 0, 4, 0} | |
252b5132 RH |
791 | }; |
792 | ||
9103f4f4 L |
793 | static const arch_entry cpu_arch[] = |
794 | { | |
89507696 JB |
795 | /* Do not replace the first two entries - i386_target_format() |
796 | relies on them being there in this order. */ | |
8a2c8fef | 797 | { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32, |
293f5f65 | 798 | CPU_GENERIC32_FLAGS, 0 }, |
8a2c8fef | 799 | { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64, |
293f5f65 | 800 | CPU_GENERIC64_FLAGS, 0 }, |
8a2c8fef | 801 | { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN, |
293f5f65 | 802 | CPU_NONE_FLAGS, 0 }, |
8a2c8fef | 803 | { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN, |
293f5f65 | 804 | CPU_I186_FLAGS, 0 }, |
8a2c8fef | 805 | { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN, |
293f5f65 | 806 | CPU_I286_FLAGS, 0 }, |
8a2c8fef | 807 | { STRING_COMMA_LEN ("i386"), PROCESSOR_I386, |
293f5f65 | 808 | CPU_I386_FLAGS, 0 }, |
8a2c8fef | 809 | { STRING_COMMA_LEN ("i486"), PROCESSOR_I486, |
293f5f65 | 810 | CPU_I486_FLAGS, 0 }, |
8a2c8fef | 811 | { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM, |
293f5f65 | 812 | CPU_I586_FLAGS, 0 }, |
8a2c8fef | 813 | { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 814 | CPU_I686_FLAGS, 0 }, |
8a2c8fef | 815 | { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM, |
293f5f65 | 816 | CPU_I586_FLAGS, 0 }, |
8a2c8fef | 817 | { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 818 | CPU_PENTIUMPRO_FLAGS, 0 }, |
8a2c8fef | 819 | { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 820 | CPU_P2_FLAGS, 0 }, |
8a2c8fef | 821 | { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO, |
293f5f65 | 822 | CPU_P3_FLAGS, 0 }, |
8a2c8fef | 823 | { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4, |
293f5f65 | 824 | CPU_P4_FLAGS, 0 }, |
8a2c8fef | 825 | { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA, |
293f5f65 | 826 | CPU_CORE_FLAGS, 0 }, |
8a2c8fef | 827 | { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA, |
293f5f65 | 828 | CPU_NOCONA_FLAGS, 0 }, |
8a2c8fef | 829 | { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE, |
293f5f65 | 830 | CPU_CORE_FLAGS, 1 }, |
8a2c8fef | 831 | { STRING_COMMA_LEN ("core"), PROCESSOR_CORE, |
293f5f65 | 832 | CPU_CORE_FLAGS, 0 }, |
8a2c8fef | 833 | { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2, |
293f5f65 | 834 | CPU_CORE2_FLAGS, 1 }, |
8a2c8fef | 835 | { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2, |
293f5f65 | 836 | CPU_CORE2_FLAGS, 0 }, |
8a2c8fef | 837 | { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7, |
293f5f65 | 838 | CPU_COREI7_FLAGS, 0 }, |
8a2c8fef | 839 | { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM, |
293f5f65 | 840 | CPU_L1OM_FLAGS, 0 }, |
7a9068fe | 841 | { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM, |
293f5f65 | 842 | CPU_K1OM_FLAGS, 0 }, |
81486035 | 843 | { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU, |
293f5f65 | 844 | CPU_IAMCU_FLAGS, 0 }, |
8a2c8fef | 845 | { STRING_COMMA_LEN ("k6"), PROCESSOR_K6, |
293f5f65 | 846 | CPU_K6_FLAGS, 0 }, |
8a2c8fef | 847 | { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6, |
293f5f65 | 848 | CPU_K6_2_FLAGS, 0 }, |
8a2c8fef | 849 | { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON, |
293f5f65 | 850 | CPU_ATHLON_FLAGS, 0 }, |
8a2c8fef | 851 | { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8, |
293f5f65 | 852 | CPU_K8_FLAGS, 1 }, |
8a2c8fef | 853 | { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8, |
293f5f65 | 854 | CPU_K8_FLAGS, 0 }, |
8a2c8fef | 855 | { STRING_COMMA_LEN ("k8"), PROCESSOR_K8, |
293f5f65 | 856 | CPU_K8_FLAGS, 0 }, |
8a2c8fef | 857 | { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10, |
293f5f65 | 858 | CPU_AMDFAM10_FLAGS, 0 }, |
8aedb9fe | 859 | { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD, |
293f5f65 | 860 | CPU_BDVER1_FLAGS, 0 }, |
8aedb9fe | 861 | { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD, |
293f5f65 | 862 | CPU_BDVER2_FLAGS, 0 }, |
5e5c50d3 | 863 | { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD, |
293f5f65 | 864 | CPU_BDVER3_FLAGS, 0 }, |
c7b0bd56 | 865 | { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD, |
293f5f65 | 866 | CPU_BDVER4_FLAGS, 0 }, |
029f3522 | 867 | { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER, |
293f5f65 | 868 | CPU_ZNVER1_FLAGS, 0 }, |
a9660a6f AP |
869 | { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER, |
870 | CPU_ZNVER2_FLAGS, 0 }, | |
7b458c12 | 871 | { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT, |
293f5f65 | 872 | CPU_BTVER1_FLAGS, 0 }, |
7b458c12 | 873 | { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT, |
293f5f65 | 874 | CPU_BTVER2_FLAGS, 0 }, |
8a2c8fef | 875 | { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN, |
293f5f65 | 876 | CPU_8087_FLAGS, 0 }, |
8a2c8fef | 877 | { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN, |
293f5f65 | 878 | CPU_287_FLAGS, 0 }, |
8a2c8fef | 879 | { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN, |
293f5f65 | 880 | CPU_387_FLAGS, 0 }, |
1848e567 L |
881 | { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN, |
882 | CPU_687_FLAGS, 0 }, | |
d871f3f4 L |
883 | { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN, |
884 | CPU_CMOV_FLAGS, 0 }, | |
885 | { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN, | |
886 | CPU_FXSR_FLAGS, 0 }, | |
8a2c8fef | 887 | { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN, |
293f5f65 | 888 | CPU_MMX_FLAGS, 0 }, |
8a2c8fef | 889 | { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN, |
293f5f65 | 890 | CPU_SSE_FLAGS, 0 }, |
8a2c8fef | 891 | { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN, |
293f5f65 | 892 | CPU_SSE2_FLAGS, 0 }, |
8a2c8fef | 893 | { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN, |
293f5f65 | 894 | CPU_SSE3_FLAGS, 0 }, |
8a2c8fef | 895 | { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN, |
293f5f65 | 896 | CPU_SSSE3_FLAGS, 0 }, |
8a2c8fef | 897 | { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN, |
293f5f65 | 898 | CPU_SSE4_1_FLAGS, 0 }, |
8a2c8fef | 899 | { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN, |
293f5f65 | 900 | CPU_SSE4_2_FLAGS, 0 }, |
8a2c8fef | 901 | { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN, |
293f5f65 | 902 | CPU_SSE4_2_FLAGS, 0 }, |
8a2c8fef | 903 | { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN, |
293f5f65 | 904 | CPU_AVX_FLAGS, 0 }, |
6c30d220 | 905 | { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN, |
293f5f65 | 906 | CPU_AVX2_FLAGS, 0 }, |
43234a1e | 907 | { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN, |
293f5f65 | 908 | CPU_AVX512F_FLAGS, 0 }, |
43234a1e | 909 | { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN, |
293f5f65 | 910 | CPU_AVX512CD_FLAGS, 0 }, |
43234a1e | 911 | { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN, |
293f5f65 | 912 | CPU_AVX512ER_FLAGS, 0 }, |
43234a1e | 913 | { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN, |
293f5f65 | 914 | CPU_AVX512PF_FLAGS, 0 }, |
1dfc6506 | 915 | { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN, |
293f5f65 | 916 | CPU_AVX512DQ_FLAGS, 0 }, |
1dfc6506 | 917 | { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN, |
293f5f65 | 918 | CPU_AVX512BW_FLAGS, 0 }, |
1dfc6506 | 919 | { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN, |
293f5f65 | 920 | CPU_AVX512VL_FLAGS, 0 }, |
8a2c8fef | 921 | { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN, |
293f5f65 | 922 | CPU_VMX_FLAGS, 0 }, |
8729a6f6 | 923 | { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN, |
293f5f65 | 924 | CPU_VMFUNC_FLAGS, 0 }, |
8a2c8fef | 925 | { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN, |
293f5f65 | 926 | CPU_SMX_FLAGS, 0 }, |
8a2c8fef | 927 | { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN, |
293f5f65 | 928 | CPU_XSAVE_FLAGS, 0 }, |
c7b8aa3a | 929 | { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN, |
293f5f65 | 930 | CPU_XSAVEOPT_FLAGS, 0 }, |
1dfc6506 | 931 | { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN, |
293f5f65 | 932 | CPU_XSAVEC_FLAGS, 0 }, |
1dfc6506 | 933 | { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN, |
293f5f65 | 934 | CPU_XSAVES_FLAGS, 0 }, |
8a2c8fef | 935 | { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN, |
293f5f65 | 936 | CPU_AES_FLAGS, 0 }, |
8a2c8fef | 937 | { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN, |
293f5f65 | 938 | CPU_PCLMUL_FLAGS, 0 }, |
8a2c8fef | 939 | { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN, |
293f5f65 | 940 | CPU_PCLMUL_FLAGS, 1 }, |
c7b8aa3a | 941 | { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN, |
293f5f65 | 942 | CPU_FSGSBASE_FLAGS, 0 }, |
c7b8aa3a | 943 | { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN, |
293f5f65 | 944 | CPU_RDRND_FLAGS, 0 }, |
c7b8aa3a | 945 | { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN, |
293f5f65 | 946 | CPU_F16C_FLAGS, 0 }, |
6c30d220 | 947 | { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN, |
293f5f65 | 948 | CPU_BMI2_FLAGS, 0 }, |
8a2c8fef | 949 | { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN, |
293f5f65 | 950 | CPU_FMA_FLAGS, 0 }, |
8a2c8fef | 951 | { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN, |
293f5f65 | 952 | CPU_FMA4_FLAGS, 0 }, |
8a2c8fef | 953 | { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN, |
293f5f65 | 954 | CPU_XOP_FLAGS, 0 }, |
8a2c8fef | 955 | { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN, |
293f5f65 | 956 | CPU_LWP_FLAGS, 0 }, |
8a2c8fef | 957 | { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN, |
293f5f65 | 958 | CPU_MOVBE_FLAGS, 0 }, |
60aa667e | 959 | { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN, |
293f5f65 | 960 | CPU_CX16_FLAGS, 0 }, |
8a2c8fef | 961 | { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN, |
293f5f65 | 962 | CPU_EPT_FLAGS, 0 }, |
6c30d220 | 963 | { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN, |
293f5f65 | 964 | CPU_LZCNT_FLAGS, 0 }, |
42164a71 | 965 | { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN, |
293f5f65 | 966 | CPU_HLE_FLAGS, 0 }, |
42164a71 | 967 | { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN, |
293f5f65 | 968 | CPU_RTM_FLAGS, 0 }, |
6c30d220 | 969 | { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN, |
293f5f65 | 970 | CPU_INVPCID_FLAGS, 0 }, |
8a2c8fef | 971 | { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN, |
293f5f65 | 972 | CPU_CLFLUSH_FLAGS, 0 }, |
22109423 | 973 | { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN, |
293f5f65 | 974 | CPU_NOP_FLAGS, 0 }, |
8a2c8fef | 975 | { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN, |
293f5f65 | 976 | CPU_SYSCALL_FLAGS, 0 }, |
8a2c8fef | 977 | { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN, |
293f5f65 | 978 | CPU_RDTSCP_FLAGS, 0 }, |
8a2c8fef | 979 | { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN, |
293f5f65 | 980 | CPU_3DNOW_FLAGS, 0 }, |
8a2c8fef | 981 | { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN, |
293f5f65 | 982 | CPU_3DNOWA_FLAGS, 0 }, |
8a2c8fef | 983 | { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN, |
293f5f65 | 984 | CPU_PADLOCK_FLAGS, 0 }, |
8a2c8fef | 985 | { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN, |
293f5f65 | 986 | CPU_SVME_FLAGS, 1 }, |
8a2c8fef | 987 | { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN, |
293f5f65 | 988 | CPU_SVME_FLAGS, 0 }, |
8a2c8fef | 989 | { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN, |
293f5f65 | 990 | CPU_SSE4A_FLAGS, 0 }, |
8a2c8fef | 991 | { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN, |
293f5f65 | 992 | CPU_ABM_FLAGS, 0 }, |
87973e9f | 993 | { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN, |
293f5f65 | 994 | CPU_BMI_FLAGS, 0 }, |
2a2a0f38 | 995 | { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN, |
293f5f65 | 996 | CPU_TBM_FLAGS, 0 }, |
e2e1fcde | 997 | { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN, |
293f5f65 | 998 | CPU_ADX_FLAGS, 0 }, |
e2e1fcde | 999 | { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN, |
293f5f65 | 1000 | CPU_RDSEED_FLAGS, 0 }, |
e2e1fcde | 1001 | { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN, |
293f5f65 | 1002 | CPU_PRFCHW_FLAGS, 0 }, |
5c111e37 | 1003 | { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN, |
293f5f65 | 1004 | CPU_SMAP_FLAGS, 0 }, |
7e8b059b | 1005 | { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1006 | CPU_MPX_FLAGS, 0 }, |
a0046408 | 1007 | { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN, |
293f5f65 | 1008 | CPU_SHA_FLAGS, 0 }, |
963f3586 | 1009 | { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN, |
293f5f65 | 1010 | CPU_CLFLUSHOPT_FLAGS, 0 }, |
dcf893b5 | 1011 | { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN, |
293f5f65 | 1012 | CPU_PREFETCHWT1_FLAGS, 0 }, |
2cf200a4 | 1013 | { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN, |
293f5f65 | 1014 | CPU_SE1_FLAGS, 0 }, |
c5e7287a | 1015 | { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN, |
293f5f65 | 1016 | CPU_CLWB_FLAGS, 0 }, |
2cc1b5aa | 1017 | { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN, |
293f5f65 | 1018 | CPU_AVX512IFMA_FLAGS, 0 }, |
14f195c9 | 1019 | { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN, |
293f5f65 | 1020 | CPU_AVX512VBMI_FLAGS, 0 }, |
920d2ddc IT |
1021 | { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN, |
1022 | CPU_AVX512_4FMAPS_FLAGS, 0 }, | |
47acf0bd IT |
1023 | { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN, |
1024 | CPU_AVX512_4VNNIW_FLAGS, 0 }, | |
620214f7 IT |
1025 | { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN, |
1026 | CPU_AVX512_VPOPCNTDQ_FLAGS, 0 }, | |
53467f57 IT |
1027 | { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN, |
1028 | CPU_AVX512_VBMI2_FLAGS, 0 }, | |
8cfcb765 IT |
1029 | { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN, |
1030 | CPU_AVX512_VNNI_FLAGS, 0 }, | |
ee6872be IT |
1031 | { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN, |
1032 | CPU_AVX512_BITALG_FLAGS, 0 }, | |
029f3522 | 1033 | { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN, |
293f5f65 | 1034 | CPU_CLZERO_FLAGS, 0 }, |
9916071f | 1035 | { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1036 | CPU_MWAITX_FLAGS, 0 }, |
8eab4136 | 1037 | { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN, |
293f5f65 | 1038 | CPU_OSPKE_FLAGS, 0 }, |
8bc52696 | 1039 | { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN, |
293f5f65 | 1040 | CPU_RDPID_FLAGS, 0 }, |
6b40c462 L |
1041 | { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN, |
1042 | CPU_PTWRITE_FLAGS, 0 }, | |
d777820b IT |
1043 | { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN, |
1044 | CPU_IBT_FLAGS, 0 }, | |
1045 | { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN, | |
1046 | CPU_SHSTK_FLAGS, 0 }, | |
48521003 IT |
1047 | { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN, |
1048 | CPU_GFNI_FLAGS, 0 }, | |
8dcf1fad IT |
1049 | { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN, |
1050 | CPU_VAES_FLAGS, 0 }, | |
ff1982d5 IT |
1051 | { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN, |
1052 | CPU_VPCLMULQDQ_FLAGS, 0 }, | |
3233d7d0 IT |
1053 | { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN, |
1054 | CPU_WBNOINVD_FLAGS, 0 }, | |
be3a8dca IT |
1055 | { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN, |
1056 | CPU_PCONFIG_FLAGS, 0 }, | |
de89d0a3 IT |
1057 | { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN, |
1058 | CPU_WAITPKG_FLAGS, 0 }, | |
c48935d7 IT |
1059 | { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN, |
1060 | CPU_CLDEMOTE_FLAGS, 0 }, | |
c0a30a9f L |
1061 | { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN, |
1062 | CPU_MOVDIRI_FLAGS, 0 }, | |
1063 | { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN, | |
1064 | CPU_MOVDIR64B_FLAGS, 0 }, | |
293f5f65 L |
1065 | }; |
1066 | ||
1067 | static const noarch_entry cpu_noarch[] = | |
1068 | { | |
1069 | { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS }, | |
1848e567 L |
1070 | { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS }, |
1071 | { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS }, | |
1072 | { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS }, | |
d871f3f4 L |
1073 | { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS }, |
1074 | { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS }, | |
293f5f65 L |
1075 | { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS }, |
1076 | { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS }, | |
1848e567 L |
1077 | { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS }, |
1078 | { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS }, | |
1079 | { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS }, | |
1080 | { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS }, | |
1081 | { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS }, | |
1082 | { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS }, | |
293f5f65 | 1083 | { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS }, |
1848e567 | 1084 | { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS }, |
144b71e2 L |
1085 | { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS }, |
1086 | { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS }, | |
1087 | { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS }, | |
1088 | { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS }, | |
1089 | { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS }, | |
1090 | { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS }, | |
1091 | { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS }, | |
1092 | { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS }, | |
1093 | { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS }, | |
920d2ddc | 1094 | { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS }, |
47acf0bd | 1095 | { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS }, |
620214f7 | 1096 | { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS }, |
53467f57 | 1097 | { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS }, |
8cfcb765 | 1098 | { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS }, |
ee6872be | 1099 | { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS }, |
d777820b IT |
1100 | { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS }, |
1101 | { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS }, | |
c0a30a9f L |
1102 | { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS }, |
1103 | { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS }, | |
e413e4e9 AM |
1104 | }; |
1105 | ||
704209c0 | 1106 | #ifdef I386COFF |
a6c24e68 NC |
1107 | /* Like s_lcomm_internal in gas/read.c but the alignment string |
1108 | is allowed to be optional. */ | |
1109 | ||
1110 | static symbolS * | |
1111 | pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size) | |
1112 | { | |
1113 | addressT align = 0; | |
1114 | ||
1115 | SKIP_WHITESPACE (); | |
1116 | ||
7ab9ffdd | 1117 | if (needs_align |
a6c24e68 NC |
1118 | && *input_line_pointer == ',') |
1119 | { | |
1120 | align = parse_align (needs_align - 1); | |
7ab9ffdd | 1121 | |
a6c24e68 NC |
1122 | if (align == (addressT) -1) |
1123 | return NULL; | |
1124 | } | |
1125 | else | |
1126 | { | |
1127 | if (size >= 8) | |
1128 | align = 3; | |
1129 | else if (size >= 4) | |
1130 | align = 2; | |
1131 | else if (size >= 2) | |
1132 | align = 1; | |
1133 | else | |
1134 | align = 0; | |
1135 | } | |
1136 | ||
1137 | bss_alloc (symbolP, size, align); | |
1138 | return symbolP; | |
1139 | } | |
1140 | ||
704209c0 | 1141 | static void |
a6c24e68 NC |
1142 | pe_lcomm (int needs_align) |
1143 | { | |
1144 | s_comm_internal (needs_align * 2, pe_lcomm_internal); | |
1145 | } | |
704209c0 | 1146 | #endif |
a6c24e68 | 1147 | |
29b0f896 AM |
1148 | const pseudo_typeS md_pseudo_table[] = |
1149 | { | |
1150 | #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) | |
1151 | {"align", s_align_bytes, 0}, | |
1152 | #else | |
1153 | {"align", s_align_ptwo, 0}, | |
1154 | #endif | |
1155 | {"arch", set_cpu_arch, 0}, | |
1156 | #ifndef I386COFF | |
1157 | {"bss", s_bss, 0}, | |
a6c24e68 NC |
1158 | #else |
1159 | {"lcomm", pe_lcomm, 1}, | |
29b0f896 AM |
1160 | #endif |
1161 | {"ffloat", float_cons, 'f'}, | |
1162 | {"dfloat", float_cons, 'd'}, | |
1163 | {"tfloat", float_cons, 'x'}, | |
1164 | {"value", cons, 2}, | |
d182319b | 1165 | {"slong", signed_cons, 4}, |
29b0f896 AM |
1166 | {"noopt", s_ignore, 0}, |
1167 | {"optim", s_ignore, 0}, | |
1168 | {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT}, | |
1169 | {"code16", set_code_flag, CODE_16BIT}, | |
1170 | {"code32", set_code_flag, CODE_32BIT}, | |
da5f19a2 | 1171 | #ifdef BFD64 |
29b0f896 | 1172 | {"code64", set_code_flag, CODE_64BIT}, |
da5f19a2 | 1173 | #endif |
29b0f896 AM |
1174 | {"intel_syntax", set_intel_syntax, 1}, |
1175 | {"att_syntax", set_intel_syntax, 0}, | |
1efbbeb4 L |
1176 | {"intel_mnemonic", set_intel_mnemonic, 1}, |
1177 | {"att_mnemonic", set_intel_mnemonic, 0}, | |
db51cc60 L |
1178 | {"allow_index_reg", set_allow_index_reg, 1}, |
1179 | {"disallow_index_reg", set_allow_index_reg, 0}, | |
7bab8ab5 JB |
1180 | {"sse_check", set_check, 0}, |
1181 | {"operand_check", set_check, 1}, | |
3b22753a L |
1182 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
1183 | {"largecomm", handle_large_common, 0}, | |
07a53e5c | 1184 | #else |
68d20676 | 1185 | {"file", dwarf2_directive_file, 0}, |
07a53e5c RH |
1186 | {"loc", dwarf2_directive_loc, 0}, |
1187 | {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0}, | |
3b22753a | 1188 | #endif |
6482c264 NC |
1189 | #ifdef TE_PE |
1190 | {"secrel32", pe_directive_secrel, 0}, | |
1191 | #endif | |
29b0f896 AM |
1192 | {0, 0, 0} |
1193 | }; | |
1194 | ||
1195 | /* For interface with expression (). */ | |
1196 | extern char *input_line_pointer; | |
1197 | ||
1198 | /* Hash table for instruction mnemonic lookup. */ | |
1199 | static struct hash_control *op_hash; | |
1200 | ||
1201 | /* Hash table for register lookup. */ | |
1202 | static struct hash_control *reg_hash; | |
1203 | \f | |
ce8a8b2f AM |
1204 | /* Various efficient no-op patterns for aligning code labels. |
1205 | Note: Don't try to assemble the instructions in the comments. | |
1206 | 0L and 0w are not legal. */ | |
62a02d25 L |
1207 | static const unsigned char f32_1[] = |
1208 | {0x90}; /* nop */ | |
1209 | static const unsigned char f32_2[] = | |
1210 | {0x66,0x90}; /* xchg %ax,%ax */ | |
1211 | static const unsigned char f32_3[] = | |
1212 | {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ | |
1213 | static const unsigned char f32_4[] = | |
1214 | {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
62a02d25 L |
1215 | static const unsigned char f32_6[] = |
1216 | {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ | |
1217 | static const unsigned char f32_7[] = | |
1218 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
62a02d25 | 1219 | static const unsigned char f16_3[] = |
3ae729d5 | 1220 | {0x8d,0x74,0x00}; /* lea 0(%si),%si */ |
62a02d25 | 1221 | static const unsigned char f16_4[] = |
3ae729d5 L |
1222 | {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */ |
1223 | static const unsigned char jump_disp8[] = | |
1224 | {0xeb}; /* jmp disp8 */ | |
1225 | static const unsigned char jump32_disp32[] = | |
1226 | {0xe9}; /* jmp disp32 */ | |
1227 | static const unsigned char jump16_disp32[] = | |
1228 | {0x66,0xe9}; /* jmp disp32 */ | |
62a02d25 L |
1229 | /* 32-bit NOPs patterns. */ |
1230 | static const unsigned char *const f32_patt[] = { | |
3ae729d5 | 1231 | f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7 |
62a02d25 L |
1232 | }; |
1233 | /* 16-bit NOPs patterns. */ | |
1234 | static const unsigned char *const f16_patt[] = { | |
3ae729d5 | 1235 | f32_1, f32_2, f16_3, f16_4 |
62a02d25 L |
1236 | }; |
1237 | /* nopl (%[re]ax) */ | |
1238 | static const unsigned char alt_3[] = | |
1239 | {0x0f,0x1f,0x00}; | |
1240 | /* nopl 0(%[re]ax) */ | |
1241 | static const unsigned char alt_4[] = | |
1242 | {0x0f,0x1f,0x40,0x00}; | |
1243 | /* nopl 0(%[re]ax,%[re]ax,1) */ | |
1244 | static const unsigned char alt_5[] = | |
1245 | {0x0f,0x1f,0x44,0x00,0x00}; | |
1246 | /* nopw 0(%[re]ax,%[re]ax,1) */ | |
1247 | static const unsigned char alt_6[] = | |
1248 | {0x66,0x0f,0x1f,0x44,0x00,0x00}; | |
1249 | /* nopl 0L(%[re]ax) */ | |
1250 | static const unsigned char alt_7[] = | |
1251 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; | |
1252 | /* nopl 0L(%[re]ax,%[re]ax,1) */ | |
1253 | static const unsigned char alt_8[] = | |
1254 | {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
1255 | /* nopw 0L(%[re]ax,%[re]ax,1) */ | |
1256 | static const unsigned char alt_9[] = | |
1257 | {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
1258 | /* nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
1259 | static const unsigned char alt_10[] = | |
1260 | {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
3ae729d5 L |
1261 | /* data16 nopw %cs:0L(%eax,%eax,1) */ |
1262 | static const unsigned char alt_11[] = | |
1263 | {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
62a02d25 L |
1264 | /* 32-bit and 64-bit NOPs patterns. */ |
1265 | static const unsigned char *const alt_patt[] = { | |
1266 | f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, | |
3ae729d5 | 1267 | alt_9, alt_10, alt_11 |
62a02d25 L |
1268 | }; |
1269 | ||
1270 | /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum | |
1271 | size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */ | |
1272 | ||
1273 | static void | |
1274 | i386_output_nops (char *where, const unsigned char *const *patt, | |
1275 | int count, int max_single_nop_size) | |
1276 | ||
1277 | { | |
3ae729d5 L |
1278 | /* Place the longer NOP first. */ |
1279 | int last; | |
1280 | int offset; | |
1281 | const unsigned char *nops = patt[max_single_nop_size - 1]; | |
1282 | ||
1283 | /* Use the smaller one if the requsted one isn't available. */ | |
1284 | if (nops == NULL) | |
62a02d25 | 1285 | { |
3ae729d5 L |
1286 | max_single_nop_size--; |
1287 | nops = patt[max_single_nop_size - 1]; | |
62a02d25 L |
1288 | } |
1289 | ||
3ae729d5 L |
1290 | last = count % max_single_nop_size; |
1291 | ||
1292 | count -= last; | |
1293 | for (offset = 0; offset < count; offset += max_single_nop_size) | |
1294 | memcpy (where + offset, nops, max_single_nop_size); | |
1295 | ||
1296 | if (last) | |
1297 | { | |
1298 | nops = patt[last - 1]; | |
1299 | if (nops == NULL) | |
1300 | { | |
1301 | /* Use the smaller one plus one-byte NOP if the needed one | |
1302 | isn't available. */ | |
1303 | last--; | |
1304 | nops = patt[last - 1]; | |
1305 | memcpy (where + offset, nops, last); | |
1306 | where[offset + last] = *patt[0]; | |
1307 | } | |
1308 | else | |
1309 | memcpy (where + offset, nops, last); | |
1310 | } | |
62a02d25 L |
1311 | } |
1312 | ||
3ae729d5 L |
1313 | static INLINE int |
1314 | fits_in_imm7 (offsetT num) | |
1315 | { | |
1316 | return (num & 0x7f) == num; | |
1317 | } | |
1318 | ||
1319 | static INLINE int | |
1320 | fits_in_imm31 (offsetT num) | |
1321 | { | |
1322 | return (num & 0x7fffffff) == num; | |
1323 | } | |
62a02d25 L |
1324 | |
1325 | /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a | |
1326 | single NOP instruction LIMIT. */ | |
1327 | ||
1328 | void | |
3ae729d5 | 1329 | i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit) |
62a02d25 | 1330 | { |
3ae729d5 | 1331 | const unsigned char *const *patt = NULL; |
62a02d25 | 1332 | int max_single_nop_size; |
3ae729d5 L |
1333 | /* Maximum number of NOPs before switching to jump over NOPs. */ |
1334 | int max_number_of_nops; | |
62a02d25 | 1335 | |
3ae729d5 | 1336 | switch (fragP->fr_type) |
62a02d25 | 1337 | { |
3ae729d5 L |
1338 | case rs_fill_nop: |
1339 | case rs_align_code: | |
1340 | break; | |
1341 | default: | |
62a02d25 L |
1342 | return; |
1343 | } | |
1344 | ||
ccc9c027 L |
1345 | /* We need to decide which NOP sequence to use for 32bit and |
1346 | 64bit. When -mtune= is used: | |
4eed87de | 1347 | |
76bc74dc L |
1348 | 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and |
1349 | PROCESSOR_GENERIC32, f32_patt will be used. | |
80b8656c L |
1350 | 2. For the rest, alt_patt will be used. |
1351 | ||
1352 | When -mtune= isn't used, alt_patt will be used if | |
22109423 | 1353 | cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will |
76bc74dc | 1354 | be used. |
ccc9c027 L |
1355 | |
1356 | When -march= or .arch is used, we can't use anything beyond | |
1357 | cpu_arch_isa_flags. */ | |
1358 | ||
1359 | if (flag_code == CODE_16BIT) | |
1360 | { | |
3ae729d5 L |
1361 | patt = f16_patt; |
1362 | max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]); | |
1363 | /* Limit number of NOPs to 2 in 16-bit mode. */ | |
1364 | max_number_of_nops = 2; | |
252b5132 | 1365 | } |
33fef721 | 1366 | else |
ccc9c027 | 1367 | { |
fbf3f584 | 1368 | if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN) |
ccc9c027 L |
1369 | { |
1370 | /* PROCESSOR_UNKNOWN means that all ISAs may be used. */ | |
1371 | switch (cpu_arch_tune) | |
1372 | { | |
1373 | case PROCESSOR_UNKNOWN: | |
1374 | /* We use cpu_arch_isa_flags to check if we SHOULD | |
22109423 L |
1375 | optimize with nops. */ |
1376 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) | |
80b8656c | 1377 | patt = alt_patt; |
ccc9c027 L |
1378 | else |
1379 | patt = f32_patt; | |
1380 | break; | |
ccc9c027 L |
1381 | case PROCESSOR_PENTIUM4: |
1382 | case PROCESSOR_NOCONA: | |
ef05d495 | 1383 | case PROCESSOR_CORE: |
76bc74dc | 1384 | case PROCESSOR_CORE2: |
bd5295b2 | 1385 | case PROCESSOR_COREI7: |
3632d14b | 1386 | case PROCESSOR_L1OM: |
7a9068fe | 1387 | case PROCESSOR_K1OM: |
76bc74dc | 1388 | case PROCESSOR_GENERIC64: |
ccc9c027 L |
1389 | case PROCESSOR_K6: |
1390 | case PROCESSOR_ATHLON: | |
1391 | case PROCESSOR_K8: | |
4eed87de | 1392 | case PROCESSOR_AMDFAM10: |
8aedb9fe | 1393 | case PROCESSOR_BD: |
029f3522 | 1394 | case PROCESSOR_ZNVER: |
7b458c12 | 1395 | case PROCESSOR_BT: |
80b8656c | 1396 | patt = alt_patt; |
ccc9c027 | 1397 | break; |
76bc74dc | 1398 | case PROCESSOR_I386: |
ccc9c027 L |
1399 | case PROCESSOR_I486: |
1400 | case PROCESSOR_PENTIUM: | |
2dde1948 | 1401 | case PROCESSOR_PENTIUMPRO: |
81486035 | 1402 | case PROCESSOR_IAMCU: |
ccc9c027 L |
1403 | case PROCESSOR_GENERIC32: |
1404 | patt = f32_patt; | |
1405 | break; | |
4eed87de | 1406 | } |
ccc9c027 L |
1407 | } |
1408 | else | |
1409 | { | |
fbf3f584 | 1410 | switch (fragP->tc_frag_data.tune) |
ccc9c027 L |
1411 | { |
1412 | case PROCESSOR_UNKNOWN: | |
e6a14101 | 1413 | /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be |
ccc9c027 L |
1414 | PROCESSOR_UNKNOWN. */ |
1415 | abort (); | |
1416 | break; | |
1417 | ||
76bc74dc | 1418 | case PROCESSOR_I386: |
ccc9c027 L |
1419 | case PROCESSOR_I486: |
1420 | case PROCESSOR_PENTIUM: | |
81486035 | 1421 | case PROCESSOR_IAMCU: |
ccc9c027 L |
1422 | case PROCESSOR_K6: |
1423 | case PROCESSOR_ATHLON: | |
1424 | case PROCESSOR_K8: | |
4eed87de | 1425 | case PROCESSOR_AMDFAM10: |
8aedb9fe | 1426 | case PROCESSOR_BD: |
029f3522 | 1427 | case PROCESSOR_ZNVER: |
7b458c12 | 1428 | case PROCESSOR_BT: |
ccc9c027 L |
1429 | case PROCESSOR_GENERIC32: |
1430 | /* We use cpu_arch_isa_flags to check if we CAN optimize | |
22109423 L |
1431 | with nops. */ |
1432 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) | |
80b8656c | 1433 | patt = alt_patt; |
ccc9c027 L |
1434 | else |
1435 | patt = f32_patt; | |
1436 | break; | |
76bc74dc L |
1437 | case PROCESSOR_PENTIUMPRO: |
1438 | case PROCESSOR_PENTIUM4: | |
1439 | case PROCESSOR_NOCONA: | |
1440 | case PROCESSOR_CORE: | |
ef05d495 | 1441 | case PROCESSOR_CORE2: |
bd5295b2 | 1442 | case PROCESSOR_COREI7: |
3632d14b | 1443 | case PROCESSOR_L1OM: |
7a9068fe | 1444 | case PROCESSOR_K1OM: |
22109423 | 1445 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) |
80b8656c | 1446 | patt = alt_patt; |
ccc9c027 L |
1447 | else |
1448 | patt = f32_patt; | |
1449 | break; | |
1450 | case PROCESSOR_GENERIC64: | |
80b8656c | 1451 | patt = alt_patt; |
ccc9c027 | 1452 | break; |
4eed87de | 1453 | } |
ccc9c027 L |
1454 | } |
1455 | ||
76bc74dc L |
1456 | if (patt == f32_patt) |
1457 | { | |
3ae729d5 L |
1458 | max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]); |
1459 | /* Limit number of NOPs to 2 for older processors. */ | |
1460 | max_number_of_nops = 2; | |
76bc74dc L |
1461 | } |
1462 | else | |
1463 | { | |
3ae729d5 L |
1464 | max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]); |
1465 | /* Limit number of NOPs to 7 for newer processors. */ | |
1466 | max_number_of_nops = 7; | |
1467 | } | |
1468 | } | |
1469 | ||
1470 | if (limit == 0) | |
1471 | limit = max_single_nop_size; | |
1472 | ||
1473 | if (fragP->fr_type == rs_fill_nop) | |
1474 | { | |
1475 | /* Output NOPs for .nop directive. */ | |
1476 | if (limit > max_single_nop_size) | |
1477 | { | |
1478 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
1479 | _("invalid single nop size: %d " | |
1480 | "(expect within [0, %d])"), | |
1481 | limit, max_single_nop_size); | |
1482 | return; | |
1483 | } | |
1484 | } | |
1485 | else | |
1486 | fragP->fr_var = count; | |
1487 | ||
1488 | if ((count / max_single_nop_size) > max_number_of_nops) | |
1489 | { | |
1490 | /* Generate jump over NOPs. */ | |
1491 | offsetT disp = count - 2; | |
1492 | if (fits_in_imm7 (disp)) | |
1493 | { | |
1494 | /* Use "jmp disp8" if possible. */ | |
1495 | count = disp; | |
1496 | where[0] = jump_disp8[0]; | |
1497 | where[1] = count; | |
1498 | where += 2; | |
1499 | } | |
1500 | else | |
1501 | { | |
1502 | unsigned int size_of_jump; | |
1503 | ||
1504 | if (flag_code == CODE_16BIT) | |
1505 | { | |
1506 | where[0] = jump16_disp32[0]; | |
1507 | where[1] = jump16_disp32[1]; | |
1508 | size_of_jump = 2; | |
1509 | } | |
1510 | else | |
1511 | { | |
1512 | where[0] = jump32_disp32[0]; | |
1513 | size_of_jump = 1; | |
1514 | } | |
1515 | ||
1516 | count -= size_of_jump + 4; | |
1517 | if (!fits_in_imm31 (count)) | |
1518 | { | |
1519 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
1520 | _("jump over nop padding out of range")); | |
1521 | return; | |
1522 | } | |
1523 | ||
1524 | md_number_to_chars (where + size_of_jump, count, 4); | |
1525 | where += size_of_jump + 4; | |
76bc74dc | 1526 | } |
ccc9c027 | 1527 | } |
3ae729d5 L |
1528 | |
1529 | /* Generate multiple NOPs. */ | |
1530 | i386_output_nops (where, patt, count, limit); | |
252b5132 RH |
1531 | } |
1532 | ||
c6fb90c8 | 1533 | static INLINE int |
0dfbf9d7 | 1534 | operand_type_all_zero (const union i386_operand_type *x) |
40fb9820 | 1535 | { |
0dfbf9d7 | 1536 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1537 | { |
1538 | case 3: | |
0dfbf9d7 | 1539 | if (x->array[2]) |
c6fb90c8 | 1540 | return 0; |
1a0670f3 | 1541 | /* Fall through. */ |
c6fb90c8 | 1542 | case 2: |
0dfbf9d7 | 1543 | if (x->array[1]) |
c6fb90c8 | 1544 | return 0; |
1a0670f3 | 1545 | /* Fall through. */ |
c6fb90c8 | 1546 | case 1: |
0dfbf9d7 | 1547 | return !x->array[0]; |
c6fb90c8 L |
1548 | default: |
1549 | abort (); | |
1550 | } | |
40fb9820 L |
1551 | } |
1552 | ||
c6fb90c8 | 1553 | static INLINE void |
0dfbf9d7 | 1554 | operand_type_set (union i386_operand_type *x, unsigned int v) |
40fb9820 | 1555 | { |
0dfbf9d7 | 1556 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1557 | { |
1558 | case 3: | |
0dfbf9d7 | 1559 | x->array[2] = v; |
1a0670f3 | 1560 | /* Fall through. */ |
c6fb90c8 | 1561 | case 2: |
0dfbf9d7 | 1562 | x->array[1] = v; |
1a0670f3 | 1563 | /* Fall through. */ |
c6fb90c8 | 1564 | case 1: |
0dfbf9d7 | 1565 | x->array[0] = v; |
1a0670f3 | 1566 | /* Fall through. */ |
c6fb90c8 L |
1567 | break; |
1568 | default: | |
1569 | abort (); | |
1570 | } | |
1571 | } | |
40fb9820 | 1572 | |
c6fb90c8 | 1573 | static INLINE int |
0dfbf9d7 L |
1574 | operand_type_equal (const union i386_operand_type *x, |
1575 | const union i386_operand_type *y) | |
c6fb90c8 | 1576 | { |
0dfbf9d7 | 1577 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1578 | { |
1579 | case 3: | |
0dfbf9d7 | 1580 | if (x->array[2] != y->array[2]) |
c6fb90c8 | 1581 | return 0; |
1a0670f3 | 1582 | /* Fall through. */ |
c6fb90c8 | 1583 | case 2: |
0dfbf9d7 | 1584 | if (x->array[1] != y->array[1]) |
c6fb90c8 | 1585 | return 0; |
1a0670f3 | 1586 | /* Fall through. */ |
c6fb90c8 | 1587 | case 1: |
0dfbf9d7 | 1588 | return x->array[0] == y->array[0]; |
c6fb90c8 L |
1589 | break; |
1590 | default: | |
1591 | abort (); | |
1592 | } | |
1593 | } | |
40fb9820 | 1594 | |
0dfbf9d7 L |
1595 | static INLINE int |
1596 | cpu_flags_all_zero (const union i386_cpu_flags *x) | |
1597 | { | |
1598 | switch (ARRAY_SIZE(x->array)) | |
1599 | { | |
53467f57 IT |
1600 | case 4: |
1601 | if (x->array[3]) | |
1602 | return 0; | |
1603 | /* Fall through. */ | |
0dfbf9d7 L |
1604 | case 3: |
1605 | if (x->array[2]) | |
1606 | return 0; | |
1a0670f3 | 1607 | /* Fall through. */ |
0dfbf9d7 L |
1608 | case 2: |
1609 | if (x->array[1]) | |
1610 | return 0; | |
1a0670f3 | 1611 | /* Fall through. */ |
0dfbf9d7 L |
1612 | case 1: |
1613 | return !x->array[0]; | |
1614 | default: | |
1615 | abort (); | |
1616 | } | |
1617 | } | |
1618 | ||
0dfbf9d7 L |
1619 | static INLINE int |
1620 | cpu_flags_equal (const union i386_cpu_flags *x, | |
1621 | const union i386_cpu_flags *y) | |
1622 | { | |
1623 | switch (ARRAY_SIZE(x->array)) | |
1624 | { | |
53467f57 IT |
1625 | case 4: |
1626 | if (x->array[3] != y->array[3]) | |
1627 | return 0; | |
1628 | /* Fall through. */ | |
0dfbf9d7 L |
1629 | case 3: |
1630 | if (x->array[2] != y->array[2]) | |
1631 | return 0; | |
1a0670f3 | 1632 | /* Fall through. */ |
0dfbf9d7 L |
1633 | case 2: |
1634 | if (x->array[1] != y->array[1]) | |
1635 | return 0; | |
1a0670f3 | 1636 | /* Fall through. */ |
0dfbf9d7 L |
1637 | case 1: |
1638 | return x->array[0] == y->array[0]; | |
1639 | break; | |
1640 | default: | |
1641 | abort (); | |
1642 | } | |
1643 | } | |
c6fb90c8 L |
1644 | |
1645 | static INLINE int | |
1646 | cpu_flags_check_cpu64 (i386_cpu_flags f) | |
1647 | { | |
1648 | return !((flag_code == CODE_64BIT && f.bitfield.cpuno64) | |
1649 | || (flag_code != CODE_64BIT && f.bitfield.cpu64)); | |
40fb9820 L |
1650 | } |
1651 | ||
c6fb90c8 L |
1652 | static INLINE i386_cpu_flags |
1653 | cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1654 | { |
c6fb90c8 L |
1655 | switch (ARRAY_SIZE (x.array)) |
1656 | { | |
53467f57 IT |
1657 | case 4: |
1658 | x.array [3] &= y.array [3]; | |
1659 | /* Fall through. */ | |
c6fb90c8 L |
1660 | case 3: |
1661 | x.array [2] &= y.array [2]; | |
1a0670f3 | 1662 | /* Fall through. */ |
c6fb90c8 L |
1663 | case 2: |
1664 | x.array [1] &= y.array [1]; | |
1a0670f3 | 1665 | /* Fall through. */ |
c6fb90c8 L |
1666 | case 1: |
1667 | x.array [0] &= y.array [0]; | |
1668 | break; | |
1669 | default: | |
1670 | abort (); | |
1671 | } | |
1672 | return x; | |
1673 | } | |
40fb9820 | 1674 | |
c6fb90c8 L |
1675 | static INLINE i386_cpu_flags |
1676 | cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1677 | { |
c6fb90c8 | 1678 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1679 | { |
53467f57 IT |
1680 | case 4: |
1681 | x.array [3] |= y.array [3]; | |
1682 | /* Fall through. */ | |
c6fb90c8 L |
1683 | case 3: |
1684 | x.array [2] |= y.array [2]; | |
1a0670f3 | 1685 | /* Fall through. */ |
c6fb90c8 L |
1686 | case 2: |
1687 | x.array [1] |= y.array [1]; | |
1a0670f3 | 1688 | /* Fall through. */ |
c6fb90c8 L |
1689 | case 1: |
1690 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1691 | break; |
1692 | default: | |
1693 | abort (); | |
1694 | } | |
40fb9820 L |
1695 | return x; |
1696 | } | |
1697 | ||
309d3373 JB |
1698 | static INLINE i386_cpu_flags |
1699 | cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y) | |
1700 | { | |
1701 | switch (ARRAY_SIZE (x.array)) | |
1702 | { | |
53467f57 IT |
1703 | case 4: |
1704 | x.array [3] &= ~y.array [3]; | |
1705 | /* Fall through. */ | |
309d3373 JB |
1706 | case 3: |
1707 | x.array [2] &= ~y.array [2]; | |
1a0670f3 | 1708 | /* Fall through. */ |
309d3373 JB |
1709 | case 2: |
1710 | x.array [1] &= ~y.array [1]; | |
1a0670f3 | 1711 | /* Fall through. */ |
309d3373 JB |
1712 | case 1: |
1713 | x.array [0] &= ~y.array [0]; | |
1714 | break; | |
1715 | default: | |
1716 | abort (); | |
1717 | } | |
1718 | return x; | |
1719 | } | |
1720 | ||
c0f3af97 L |
1721 | #define CPU_FLAGS_ARCH_MATCH 0x1 |
1722 | #define CPU_FLAGS_64BIT_MATCH 0x2 | |
1723 | ||
c0f3af97 | 1724 | #define CPU_FLAGS_PERFECT_MATCH \ |
db12e14e | 1725 | (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH) |
c0f3af97 L |
1726 | |
1727 | /* Return CPU flags match bits. */ | |
3629bb00 | 1728 | |
40fb9820 | 1729 | static int |
d3ce72d0 | 1730 | cpu_flags_match (const insn_template *t) |
40fb9820 | 1731 | { |
c0f3af97 L |
1732 | i386_cpu_flags x = t->cpu_flags; |
1733 | int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0; | |
40fb9820 L |
1734 | |
1735 | x.bitfield.cpu64 = 0; | |
1736 | x.bitfield.cpuno64 = 0; | |
1737 | ||
0dfbf9d7 | 1738 | if (cpu_flags_all_zero (&x)) |
c0f3af97 L |
1739 | { |
1740 | /* This instruction is available on all archs. */ | |
db12e14e | 1741 | match |= CPU_FLAGS_ARCH_MATCH; |
c0f3af97 | 1742 | } |
3629bb00 L |
1743 | else |
1744 | { | |
c0f3af97 | 1745 | /* This instruction is available only on some archs. */ |
3629bb00 L |
1746 | i386_cpu_flags cpu = cpu_arch_flags; |
1747 | ||
ab592e75 JB |
1748 | /* AVX512VL is no standalone feature - match it and then strip it. */ |
1749 | if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl) | |
1750 | return match; | |
1751 | x.bitfield.cpuavx512vl = 0; | |
1752 | ||
3629bb00 | 1753 | cpu = cpu_flags_and (x, cpu); |
c0f3af97 L |
1754 | if (!cpu_flags_all_zero (&cpu)) |
1755 | { | |
a5ff0eb2 L |
1756 | if (x.bitfield.cpuavx) |
1757 | { | |
929f69fa | 1758 | /* We need to check a few extra flags with AVX. */ |
b9d49817 JB |
1759 | if (cpu.bitfield.cpuavx |
1760 | && (!t->opcode_modifier.sse2avx || sse2avx) | |
1761 | && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes) | |
929f69fa | 1762 | && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni) |
b9d49817 JB |
1763 | && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul)) |
1764 | match |= CPU_FLAGS_ARCH_MATCH; | |
a5ff0eb2 | 1765 | } |
929f69fa JB |
1766 | else if (x.bitfield.cpuavx512f) |
1767 | { | |
1768 | /* We need to check a few extra flags with AVX512F. */ | |
1769 | if (cpu.bitfield.cpuavx512f | |
1770 | && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni) | |
1771 | && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes) | |
1772 | && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq)) | |
1773 | match |= CPU_FLAGS_ARCH_MATCH; | |
1774 | } | |
a5ff0eb2 | 1775 | else |
db12e14e | 1776 | match |= CPU_FLAGS_ARCH_MATCH; |
c0f3af97 | 1777 | } |
3629bb00 | 1778 | } |
c0f3af97 | 1779 | return match; |
40fb9820 L |
1780 | } |
1781 | ||
c6fb90c8 L |
1782 | static INLINE i386_operand_type |
1783 | operand_type_and (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1784 | { |
c6fb90c8 L |
1785 | switch (ARRAY_SIZE (x.array)) |
1786 | { | |
1787 | case 3: | |
1788 | x.array [2] &= y.array [2]; | |
1a0670f3 | 1789 | /* Fall through. */ |
c6fb90c8 L |
1790 | case 2: |
1791 | x.array [1] &= y.array [1]; | |
1a0670f3 | 1792 | /* Fall through. */ |
c6fb90c8 L |
1793 | case 1: |
1794 | x.array [0] &= y.array [0]; | |
1795 | break; | |
1796 | default: | |
1797 | abort (); | |
1798 | } | |
1799 | return x; | |
40fb9820 L |
1800 | } |
1801 | ||
73053c1f JB |
1802 | static INLINE i386_operand_type |
1803 | operand_type_and_not (i386_operand_type x, i386_operand_type y) | |
1804 | { | |
1805 | switch (ARRAY_SIZE (x.array)) | |
1806 | { | |
1807 | case 3: | |
1808 | x.array [2] &= ~y.array [2]; | |
1809 | /* Fall through. */ | |
1810 | case 2: | |
1811 | x.array [1] &= ~y.array [1]; | |
1812 | /* Fall through. */ | |
1813 | case 1: | |
1814 | x.array [0] &= ~y.array [0]; | |
1815 | break; | |
1816 | default: | |
1817 | abort (); | |
1818 | } | |
1819 | return x; | |
1820 | } | |
1821 | ||
c6fb90c8 L |
1822 | static INLINE i386_operand_type |
1823 | operand_type_or (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1824 | { |
c6fb90c8 | 1825 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1826 | { |
c6fb90c8 L |
1827 | case 3: |
1828 | x.array [2] |= y.array [2]; | |
1a0670f3 | 1829 | /* Fall through. */ |
c6fb90c8 L |
1830 | case 2: |
1831 | x.array [1] |= y.array [1]; | |
1a0670f3 | 1832 | /* Fall through. */ |
c6fb90c8 L |
1833 | case 1: |
1834 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1835 | break; |
1836 | default: | |
1837 | abort (); | |
1838 | } | |
c6fb90c8 L |
1839 | return x; |
1840 | } | |
40fb9820 | 1841 | |
c6fb90c8 L |
1842 | static INLINE i386_operand_type |
1843 | operand_type_xor (i386_operand_type x, i386_operand_type y) | |
1844 | { | |
1845 | switch (ARRAY_SIZE (x.array)) | |
1846 | { | |
1847 | case 3: | |
1848 | x.array [2] ^= y.array [2]; | |
1a0670f3 | 1849 | /* Fall through. */ |
c6fb90c8 L |
1850 | case 2: |
1851 | x.array [1] ^= y.array [1]; | |
1a0670f3 | 1852 | /* Fall through. */ |
c6fb90c8 L |
1853 | case 1: |
1854 | x.array [0] ^= y.array [0]; | |
1855 | break; | |
1856 | default: | |
1857 | abort (); | |
1858 | } | |
40fb9820 L |
1859 | return x; |
1860 | } | |
1861 | ||
1862 | static const i386_operand_type acc32 = OPERAND_TYPE_ACC32; | |
1863 | static const i386_operand_type acc64 = OPERAND_TYPE_ACC64; | |
40fb9820 L |
1864 | static const i386_operand_type disp16 = OPERAND_TYPE_DISP16; |
1865 | static const i386_operand_type disp32 = OPERAND_TYPE_DISP32; | |
1866 | static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S; | |
1867 | static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32; | |
1868 | static const i386_operand_type anydisp | |
1869 | = OPERAND_TYPE_ANYDISP; | |
40fb9820 | 1870 | static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM; |
43234a1e | 1871 | static const i386_operand_type regmask = OPERAND_TYPE_REGMASK; |
40fb9820 L |
1872 | static const i386_operand_type imm8 = OPERAND_TYPE_IMM8; |
1873 | static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S; | |
1874 | static const i386_operand_type imm16 = OPERAND_TYPE_IMM16; | |
1875 | static const i386_operand_type imm32 = OPERAND_TYPE_IMM32; | |
1876 | static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S; | |
1877 | static const i386_operand_type imm64 = OPERAND_TYPE_IMM64; | |
1878 | static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32; | |
1879 | static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S; | |
1880 | static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S; | |
a683cc34 | 1881 | static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4; |
40fb9820 L |
1882 | |
1883 | enum operand_type | |
1884 | { | |
1885 | reg, | |
40fb9820 L |
1886 | imm, |
1887 | disp, | |
1888 | anymem | |
1889 | }; | |
1890 | ||
c6fb90c8 | 1891 | static INLINE int |
40fb9820 L |
1892 | operand_type_check (i386_operand_type t, enum operand_type c) |
1893 | { | |
1894 | switch (c) | |
1895 | { | |
1896 | case reg: | |
dc821c5f | 1897 | return t.bitfield.reg; |
40fb9820 | 1898 | |
40fb9820 L |
1899 | case imm: |
1900 | return (t.bitfield.imm8 | |
1901 | || t.bitfield.imm8s | |
1902 | || t.bitfield.imm16 | |
1903 | || t.bitfield.imm32 | |
1904 | || t.bitfield.imm32s | |
1905 | || t.bitfield.imm64); | |
1906 | ||
1907 | case disp: | |
1908 | return (t.bitfield.disp8 | |
1909 | || t.bitfield.disp16 | |
1910 | || t.bitfield.disp32 | |
1911 | || t.bitfield.disp32s | |
1912 | || t.bitfield.disp64); | |
1913 | ||
1914 | case anymem: | |
1915 | return (t.bitfield.disp8 | |
1916 | || t.bitfield.disp16 | |
1917 | || t.bitfield.disp32 | |
1918 | || t.bitfield.disp32s | |
1919 | || t.bitfield.disp64 | |
1920 | || t.bitfield.baseindex); | |
1921 | ||
1922 | default: | |
1923 | abort (); | |
1924 | } | |
2cfe26b6 AM |
1925 | |
1926 | return 0; | |
40fb9820 L |
1927 | } |
1928 | ||
7a54636a L |
1929 | /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size |
1930 | between operand GIVEN and opeand WANTED for instruction template T. */ | |
5c07affc L |
1931 | |
1932 | static INLINE int | |
7a54636a L |
1933 | match_operand_size (const insn_template *t, unsigned int wanted, |
1934 | unsigned int given) | |
5c07affc | 1935 | { |
3ac21baa JB |
1936 | return !((i.types[given].bitfield.byte |
1937 | && !t->operand_types[wanted].bitfield.byte) | |
1938 | || (i.types[given].bitfield.word | |
1939 | && !t->operand_types[wanted].bitfield.word) | |
1940 | || (i.types[given].bitfield.dword | |
1941 | && !t->operand_types[wanted].bitfield.dword) | |
1942 | || (i.types[given].bitfield.qword | |
1943 | && !t->operand_types[wanted].bitfield.qword) | |
1944 | || (i.types[given].bitfield.tbyte | |
1945 | && !t->operand_types[wanted].bitfield.tbyte)); | |
5c07affc L |
1946 | } |
1947 | ||
dd40ce22 L |
1948 | /* Return 1 if there is no conflict in SIMD register between operand |
1949 | GIVEN and opeand WANTED for instruction template T. */ | |
1b54b8d7 JB |
1950 | |
1951 | static INLINE int | |
dd40ce22 L |
1952 | match_simd_size (const insn_template *t, unsigned int wanted, |
1953 | unsigned int given) | |
1b54b8d7 | 1954 | { |
3ac21baa JB |
1955 | return !((i.types[given].bitfield.xmmword |
1956 | && !t->operand_types[wanted].bitfield.xmmword) | |
1957 | || (i.types[given].bitfield.ymmword | |
1958 | && !t->operand_types[wanted].bitfield.ymmword) | |
1959 | || (i.types[given].bitfield.zmmword | |
1960 | && !t->operand_types[wanted].bitfield.zmmword)); | |
1b54b8d7 JB |
1961 | } |
1962 | ||
7a54636a L |
1963 | /* Return 1 if there is no conflict in any size between operand GIVEN |
1964 | and opeand WANTED for instruction template T. */ | |
5c07affc L |
1965 | |
1966 | static INLINE int | |
dd40ce22 L |
1967 | match_mem_size (const insn_template *t, unsigned int wanted, |
1968 | unsigned int given) | |
5c07affc | 1969 | { |
7a54636a | 1970 | return (match_operand_size (t, wanted, given) |
3ac21baa | 1971 | && !((i.types[given].bitfield.unspecified |
af508cb9 | 1972 | && !i.broadcast |
3ac21baa JB |
1973 | && !t->operand_types[wanted].bitfield.unspecified) |
1974 | || (i.types[given].bitfield.fword | |
1975 | && !t->operand_types[wanted].bitfield.fword) | |
1b54b8d7 JB |
1976 | /* For scalar opcode templates to allow register and memory |
1977 | operands at the same time, some special casing is needed | |
d6793fa1 JB |
1978 | here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and |
1979 | down-conversion vpmov*. */ | |
3ac21baa | 1980 | || ((t->operand_types[wanted].bitfield.regsimd |
1b54b8d7 | 1981 | && !t->opcode_modifier.broadcast |
3ac21baa JB |
1982 | && (t->operand_types[wanted].bitfield.byte |
1983 | || t->operand_types[wanted].bitfield.word | |
1984 | || t->operand_types[wanted].bitfield.dword | |
1985 | || t->operand_types[wanted].bitfield.qword)) | |
1986 | ? (i.types[given].bitfield.xmmword | |
1987 | || i.types[given].bitfield.ymmword | |
1988 | || i.types[given].bitfield.zmmword) | |
1989 | : !match_simd_size(t, wanted, given)))); | |
5c07affc L |
1990 | } |
1991 | ||
3ac21baa JB |
1992 | /* Return value has MATCH_STRAIGHT set if there is no size conflict on any |
1993 | operands for instruction template T, and it has MATCH_REVERSE set if there | |
1994 | is no size conflict on any operands for the template with operands reversed | |
1995 | (and the template allows for reversing in the first place). */ | |
5c07affc | 1996 | |
3ac21baa JB |
1997 | #define MATCH_STRAIGHT 1 |
1998 | #define MATCH_REVERSE 2 | |
1999 | ||
2000 | static INLINE unsigned int | |
d3ce72d0 | 2001 | operand_size_match (const insn_template *t) |
5c07affc | 2002 | { |
3ac21baa | 2003 | unsigned int j, match = MATCH_STRAIGHT; |
5c07affc L |
2004 | |
2005 | /* Don't check jump instructions. */ | |
2006 | if (t->opcode_modifier.jump | |
2007 | || t->opcode_modifier.jumpbyte | |
2008 | || t->opcode_modifier.jumpdword | |
2009 | || t->opcode_modifier.jumpintersegment) | |
2010 | return match; | |
2011 | ||
2012 | /* Check memory and accumulator operand size. */ | |
2013 | for (j = 0; j < i.operands; j++) | |
2014 | { | |
1b54b8d7 JB |
2015 | if (!i.types[j].bitfield.reg && !i.types[j].bitfield.regsimd |
2016 | && t->operand_types[j].bitfield.anysize) | |
5c07affc L |
2017 | continue; |
2018 | ||
1b54b8d7 | 2019 | if (t->operand_types[j].bitfield.reg |
7a54636a | 2020 | && !match_operand_size (t, j, j)) |
5c07affc L |
2021 | { |
2022 | match = 0; | |
2023 | break; | |
2024 | } | |
2025 | ||
1b54b8d7 | 2026 | if (t->operand_types[j].bitfield.regsimd |
3ac21baa | 2027 | && !match_simd_size (t, j, j)) |
1b54b8d7 JB |
2028 | { |
2029 | match = 0; | |
2030 | break; | |
2031 | } | |
2032 | ||
2033 | if (t->operand_types[j].bitfield.acc | |
7a54636a | 2034 | && (!match_operand_size (t, j, j) || !match_simd_size (t, j, j))) |
1b54b8d7 JB |
2035 | { |
2036 | match = 0; | |
2037 | break; | |
2038 | } | |
2039 | ||
c48dadc9 | 2040 | if ((i.flags[j] & Operand_Mem) && !match_mem_size (t, j, j)) |
5c07affc L |
2041 | { |
2042 | match = 0; | |
2043 | break; | |
2044 | } | |
2045 | } | |
2046 | ||
3ac21baa | 2047 | if (!t->opcode_modifier.d) |
891edac4 L |
2048 | { |
2049 | mismatch: | |
3ac21baa JB |
2050 | if (!match) |
2051 | i.error = operand_size_mismatch; | |
2052 | return match; | |
891edac4 | 2053 | } |
5c07affc L |
2054 | |
2055 | /* Check reverse. */ | |
9c2799c2 | 2056 | gas_assert (i.operands == 2); |
5c07affc | 2057 | |
5c07affc L |
2058 | for (j = 0; j < 2; j++) |
2059 | { | |
dbbc8b7e | 2060 | if (t->operand_types[j].bitfield.reg |
7a54636a | 2061 | && !match_operand_size (t, j, !j)) |
891edac4 | 2062 | goto mismatch; |
5c07affc | 2063 | |
dbbc8b7e JB |
2064 | if (t->operand_types[j].bitfield.regsimd |
2065 | && !match_simd_size (t, j, !j)) | |
2066 | goto mismatch; | |
2067 | ||
2068 | if (t->operand_types[j].bitfield.acc | |
2069 | && (!match_operand_size (t, j, !j) || !match_simd_size (t, j, !j))) | |
2070 | goto mismatch; | |
2071 | ||
c48dadc9 | 2072 | if ((i.flags[!j] & Operand_Mem) && !match_mem_size (t, j, !j)) |
891edac4 | 2073 | goto mismatch; |
5c07affc L |
2074 | } |
2075 | ||
3ac21baa | 2076 | return match | MATCH_REVERSE; |
5c07affc L |
2077 | } |
2078 | ||
c6fb90c8 | 2079 | static INLINE int |
40fb9820 L |
2080 | operand_type_match (i386_operand_type overlap, |
2081 | i386_operand_type given) | |
2082 | { | |
2083 | i386_operand_type temp = overlap; | |
2084 | ||
2085 | temp.bitfield.jumpabsolute = 0; | |
7d5e4556 | 2086 | temp.bitfield.unspecified = 0; |
5c07affc L |
2087 | temp.bitfield.byte = 0; |
2088 | temp.bitfield.word = 0; | |
2089 | temp.bitfield.dword = 0; | |
2090 | temp.bitfield.fword = 0; | |
2091 | temp.bitfield.qword = 0; | |
2092 | temp.bitfield.tbyte = 0; | |
2093 | temp.bitfield.xmmword = 0; | |
c0f3af97 | 2094 | temp.bitfield.ymmword = 0; |
43234a1e | 2095 | temp.bitfield.zmmword = 0; |
0dfbf9d7 | 2096 | if (operand_type_all_zero (&temp)) |
891edac4 | 2097 | goto mismatch; |
40fb9820 | 2098 | |
891edac4 L |
2099 | if (given.bitfield.baseindex == overlap.bitfield.baseindex |
2100 | && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute) | |
2101 | return 1; | |
2102 | ||
2103 | mismatch: | |
a65babc9 | 2104 | i.error = operand_type_mismatch; |
891edac4 | 2105 | return 0; |
40fb9820 L |
2106 | } |
2107 | ||
7d5e4556 | 2108 | /* If given types g0 and g1 are registers they must be of the same type |
10c17abd JB |
2109 | unless the expected operand type register overlap is null. |
2110 | Memory operand size of certain SIMD instructions is also being checked | |
2111 | here. */ | |
40fb9820 | 2112 | |
c6fb90c8 | 2113 | static INLINE int |
dc821c5f | 2114 | operand_type_register_match (i386_operand_type g0, |
40fb9820 | 2115 | i386_operand_type t0, |
40fb9820 L |
2116 | i386_operand_type g1, |
2117 | i386_operand_type t1) | |
2118 | { | |
10c17abd JB |
2119 | if (!g0.bitfield.reg |
2120 | && !g0.bitfield.regsimd | |
2121 | && (!operand_type_check (g0, anymem) | |
2122 | || g0.bitfield.unspecified | |
2123 | || !t0.bitfield.regsimd)) | |
40fb9820 L |
2124 | return 1; |
2125 | ||
10c17abd JB |
2126 | if (!g1.bitfield.reg |
2127 | && !g1.bitfield.regsimd | |
2128 | && (!operand_type_check (g1, anymem) | |
2129 | || g1.bitfield.unspecified | |
2130 | || !t1.bitfield.regsimd)) | |
40fb9820 L |
2131 | return 1; |
2132 | ||
dc821c5f JB |
2133 | if (g0.bitfield.byte == g1.bitfield.byte |
2134 | && g0.bitfield.word == g1.bitfield.word | |
2135 | && g0.bitfield.dword == g1.bitfield.dword | |
10c17abd JB |
2136 | && g0.bitfield.qword == g1.bitfield.qword |
2137 | && g0.bitfield.xmmword == g1.bitfield.xmmword | |
2138 | && g0.bitfield.ymmword == g1.bitfield.ymmword | |
2139 | && g0.bitfield.zmmword == g1.bitfield.zmmword) | |
40fb9820 L |
2140 | return 1; |
2141 | ||
dc821c5f JB |
2142 | if (!(t0.bitfield.byte & t1.bitfield.byte) |
2143 | && !(t0.bitfield.word & t1.bitfield.word) | |
2144 | && !(t0.bitfield.dword & t1.bitfield.dword) | |
10c17abd JB |
2145 | && !(t0.bitfield.qword & t1.bitfield.qword) |
2146 | && !(t0.bitfield.xmmword & t1.bitfield.xmmword) | |
2147 | && !(t0.bitfield.ymmword & t1.bitfield.ymmword) | |
2148 | && !(t0.bitfield.zmmword & t1.bitfield.zmmword)) | |
891edac4 L |
2149 | return 1; |
2150 | ||
a65babc9 | 2151 | i.error = register_type_mismatch; |
891edac4 L |
2152 | |
2153 | return 0; | |
40fb9820 L |
2154 | } |
2155 | ||
4c692bc7 JB |
2156 | static INLINE unsigned int |
2157 | register_number (const reg_entry *r) | |
2158 | { | |
2159 | unsigned int nr = r->reg_num; | |
2160 | ||
2161 | if (r->reg_flags & RegRex) | |
2162 | nr += 8; | |
2163 | ||
200cbe0f L |
2164 | if (r->reg_flags & RegVRex) |
2165 | nr += 16; | |
2166 | ||
4c692bc7 JB |
2167 | return nr; |
2168 | } | |
2169 | ||
252b5132 | 2170 | static INLINE unsigned int |
40fb9820 | 2171 | mode_from_disp_size (i386_operand_type t) |
252b5132 | 2172 | { |
b5014f7a | 2173 | if (t.bitfield.disp8) |
40fb9820 L |
2174 | return 1; |
2175 | else if (t.bitfield.disp16 | |
2176 | || t.bitfield.disp32 | |
2177 | || t.bitfield.disp32s) | |
2178 | return 2; | |
2179 | else | |
2180 | return 0; | |
252b5132 RH |
2181 | } |
2182 | ||
2183 | static INLINE int | |
65879393 | 2184 | fits_in_signed_byte (addressT num) |
252b5132 | 2185 | { |
65879393 | 2186 | return num + 0x80 <= 0xff; |
47926f60 | 2187 | } |
252b5132 RH |
2188 | |
2189 | static INLINE int | |
65879393 | 2190 | fits_in_unsigned_byte (addressT num) |
252b5132 | 2191 | { |
65879393 | 2192 | return num <= 0xff; |
47926f60 | 2193 | } |
252b5132 RH |
2194 | |
2195 | static INLINE int | |
65879393 | 2196 | fits_in_unsigned_word (addressT num) |
252b5132 | 2197 | { |
65879393 | 2198 | return num <= 0xffff; |
47926f60 | 2199 | } |
252b5132 RH |
2200 | |
2201 | static INLINE int | |
65879393 | 2202 | fits_in_signed_word (addressT num) |
252b5132 | 2203 | { |
65879393 | 2204 | return num + 0x8000 <= 0xffff; |
47926f60 | 2205 | } |
2a962e6d | 2206 | |
3e73aa7c | 2207 | static INLINE int |
65879393 | 2208 | fits_in_signed_long (addressT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
2209 | { |
2210 | #ifndef BFD64 | |
2211 | return 1; | |
2212 | #else | |
65879393 | 2213 | return num + 0x80000000 <= 0xffffffff; |
3e73aa7c JH |
2214 | #endif |
2215 | } /* fits_in_signed_long() */ | |
2a962e6d | 2216 | |
3e73aa7c | 2217 | static INLINE int |
65879393 | 2218 | fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
2219 | { |
2220 | #ifndef BFD64 | |
2221 | return 1; | |
2222 | #else | |
65879393 | 2223 | return num <= 0xffffffff; |
3e73aa7c JH |
2224 | #endif |
2225 | } /* fits_in_unsigned_long() */ | |
252b5132 | 2226 | |
43234a1e | 2227 | static INLINE int |
b5014f7a | 2228 | fits_in_disp8 (offsetT num) |
43234a1e L |
2229 | { |
2230 | int shift = i.memshift; | |
2231 | unsigned int mask; | |
2232 | ||
2233 | if (shift == -1) | |
2234 | abort (); | |
2235 | ||
2236 | mask = (1 << shift) - 1; | |
2237 | ||
2238 | /* Return 0 if NUM isn't properly aligned. */ | |
2239 | if ((num & mask)) | |
2240 | return 0; | |
2241 | ||
2242 | /* Check if NUM will fit in 8bit after shift. */ | |
2243 | return fits_in_signed_byte (num >> shift); | |
2244 | } | |
2245 | ||
a683cc34 SP |
2246 | static INLINE int |
2247 | fits_in_imm4 (offsetT num) | |
2248 | { | |
2249 | return (num & 0xf) == num; | |
2250 | } | |
2251 | ||
40fb9820 | 2252 | static i386_operand_type |
e3bb37b5 | 2253 | smallest_imm_type (offsetT num) |
252b5132 | 2254 | { |
40fb9820 | 2255 | i386_operand_type t; |
7ab9ffdd | 2256 | |
0dfbf9d7 | 2257 | operand_type_set (&t, 0); |
40fb9820 L |
2258 | t.bitfield.imm64 = 1; |
2259 | ||
2260 | if (cpu_arch_tune != PROCESSOR_I486 && num == 1) | |
e413e4e9 AM |
2261 | { |
2262 | /* This code is disabled on the 486 because all the Imm1 forms | |
2263 | in the opcode table are slower on the i486. They're the | |
2264 | versions with the implicitly specified single-position | |
2265 | displacement, which has another syntax if you really want to | |
2266 | use that form. */ | |
40fb9820 L |
2267 | t.bitfield.imm1 = 1; |
2268 | t.bitfield.imm8 = 1; | |
2269 | t.bitfield.imm8s = 1; | |
2270 | t.bitfield.imm16 = 1; | |
2271 | t.bitfield.imm32 = 1; | |
2272 | t.bitfield.imm32s = 1; | |
2273 | } | |
2274 | else if (fits_in_signed_byte (num)) | |
2275 | { | |
2276 | t.bitfield.imm8 = 1; | |
2277 | t.bitfield.imm8s = 1; | |
2278 | t.bitfield.imm16 = 1; | |
2279 | t.bitfield.imm32 = 1; | |
2280 | t.bitfield.imm32s = 1; | |
2281 | } | |
2282 | else if (fits_in_unsigned_byte (num)) | |
2283 | { | |
2284 | t.bitfield.imm8 = 1; | |
2285 | t.bitfield.imm16 = 1; | |
2286 | t.bitfield.imm32 = 1; | |
2287 | t.bitfield.imm32s = 1; | |
2288 | } | |
2289 | else if (fits_in_signed_word (num) || fits_in_unsigned_word (num)) | |
2290 | { | |
2291 | t.bitfield.imm16 = 1; | |
2292 | t.bitfield.imm32 = 1; | |
2293 | t.bitfield.imm32s = 1; | |
2294 | } | |
2295 | else if (fits_in_signed_long (num)) | |
2296 | { | |
2297 | t.bitfield.imm32 = 1; | |
2298 | t.bitfield.imm32s = 1; | |
2299 | } | |
2300 | else if (fits_in_unsigned_long (num)) | |
2301 | t.bitfield.imm32 = 1; | |
2302 | ||
2303 | return t; | |
47926f60 | 2304 | } |
252b5132 | 2305 | |
847f7ad4 | 2306 | static offsetT |
e3bb37b5 | 2307 | offset_in_range (offsetT val, int size) |
847f7ad4 | 2308 | { |
508866be | 2309 | addressT mask; |
ba2adb93 | 2310 | |
847f7ad4 AM |
2311 | switch (size) |
2312 | { | |
508866be L |
2313 | case 1: mask = ((addressT) 1 << 8) - 1; break; |
2314 | case 2: mask = ((addressT) 1 << 16) - 1; break; | |
3b0ec529 | 2315 | case 4: mask = ((addressT) 2 << 31) - 1; break; |
3e73aa7c JH |
2316 | #ifdef BFD64 |
2317 | case 8: mask = ((addressT) 2 << 63) - 1; break; | |
2318 | #endif | |
47926f60 | 2319 | default: abort (); |
847f7ad4 AM |
2320 | } |
2321 | ||
9de868bf L |
2322 | #ifdef BFD64 |
2323 | /* If BFD64, sign extend val for 32bit address mode. */ | |
2324 | if (flag_code != CODE_64BIT | |
2325 | || i.prefix[ADDR_PREFIX]) | |
3e73aa7c JH |
2326 | if ((val & ~(((addressT) 2 << 31) - 1)) == 0) |
2327 | val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
fa289fb8 | 2328 | #endif |
ba2adb93 | 2329 | |
47926f60 | 2330 | if ((val & ~mask) != 0 && (val & ~mask) != ~mask) |
847f7ad4 AM |
2331 | { |
2332 | char buf1[40], buf2[40]; | |
2333 | ||
2334 | sprint_value (buf1, val); | |
2335 | sprint_value (buf2, val & mask); | |
2336 | as_warn (_("%s shortened to %s"), buf1, buf2); | |
2337 | } | |
2338 | return val & mask; | |
2339 | } | |
2340 | ||
c32fa91d L |
2341 | enum PREFIX_GROUP |
2342 | { | |
2343 | PREFIX_EXIST = 0, | |
2344 | PREFIX_LOCK, | |
2345 | PREFIX_REP, | |
04ef582a | 2346 | PREFIX_DS, |
c32fa91d L |
2347 | PREFIX_OTHER |
2348 | }; | |
2349 | ||
2350 | /* Returns | |
2351 | a. PREFIX_EXIST if attempting to add a prefix where one from the | |
2352 | same class already exists. | |
2353 | b. PREFIX_LOCK if lock prefix is added. | |
2354 | c. PREFIX_REP if rep/repne prefix is added. | |
04ef582a L |
2355 | d. PREFIX_DS if ds prefix is added. |
2356 | e. PREFIX_OTHER if other prefix is added. | |
c32fa91d L |
2357 | */ |
2358 | ||
2359 | static enum PREFIX_GROUP | |
e3bb37b5 | 2360 | add_prefix (unsigned int prefix) |
252b5132 | 2361 | { |
c32fa91d | 2362 | enum PREFIX_GROUP ret = PREFIX_OTHER; |
b1905489 | 2363 | unsigned int q; |
252b5132 | 2364 | |
29b0f896 AM |
2365 | if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16 |
2366 | && flag_code == CODE_64BIT) | |
b1905489 | 2367 | { |
161a04f6 | 2368 | if ((i.prefix[REX_PREFIX] & prefix & REX_W) |
44846f29 JB |
2369 | || (i.prefix[REX_PREFIX] & prefix & REX_R) |
2370 | || (i.prefix[REX_PREFIX] & prefix & REX_X) | |
2371 | || (i.prefix[REX_PREFIX] & prefix & REX_B)) | |
c32fa91d | 2372 | ret = PREFIX_EXIST; |
b1905489 JB |
2373 | q = REX_PREFIX; |
2374 | } | |
3e73aa7c | 2375 | else |
b1905489 JB |
2376 | { |
2377 | switch (prefix) | |
2378 | { | |
2379 | default: | |
2380 | abort (); | |
2381 | ||
b1905489 | 2382 | case DS_PREFIX_OPCODE: |
04ef582a L |
2383 | ret = PREFIX_DS; |
2384 | /* Fall through. */ | |
2385 | case CS_PREFIX_OPCODE: | |
b1905489 JB |
2386 | case ES_PREFIX_OPCODE: |
2387 | case FS_PREFIX_OPCODE: | |
2388 | case GS_PREFIX_OPCODE: | |
2389 | case SS_PREFIX_OPCODE: | |
2390 | q = SEG_PREFIX; | |
2391 | break; | |
2392 | ||
2393 | case REPNE_PREFIX_OPCODE: | |
2394 | case REPE_PREFIX_OPCODE: | |
c32fa91d L |
2395 | q = REP_PREFIX; |
2396 | ret = PREFIX_REP; | |
2397 | break; | |
2398 | ||
b1905489 | 2399 | case LOCK_PREFIX_OPCODE: |
c32fa91d L |
2400 | q = LOCK_PREFIX; |
2401 | ret = PREFIX_LOCK; | |
b1905489 JB |
2402 | break; |
2403 | ||
2404 | case FWAIT_OPCODE: | |
2405 | q = WAIT_PREFIX; | |
2406 | break; | |
2407 | ||
2408 | case ADDR_PREFIX_OPCODE: | |
2409 | q = ADDR_PREFIX; | |
2410 | break; | |
2411 | ||
2412 | case DATA_PREFIX_OPCODE: | |
2413 | q = DATA_PREFIX; | |
2414 | break; | |
2415 | } | |
2416 | if (i.prefix[q] != 0) | |
c32fa91d | 2417 | ret = PREFIX_EXIST; |
b1905489 | 2418 | } |
252b5132 | 2419 | |
b1905489 | 2420 | if (ret) |
252b5132 | 2421 | { |
b1905489 JB |
2422 | if (!i.prefix[q]) |
2423 | ++i.prefixes; | |
2424 | i.prefix[q] |= prefix; | |
252b5132 | 2425 | } |
b1905489 JB |
2426 | else |
2427 | as_bad (_("same type of prefix used twice")); | |
252b5132 | 2428 | |
252b5132 RH |
2429 | return ret; |
2430 | } | |
2431 | ||
2432 | static void | |
78f12dd3 | 2433 | update_code_flag (int value, int check) |
eecb386c | 2434 | { |
78f12dd3 L |
2435 | PRINTF_LIKE ((*as_error)); |
2436 | ||
1e9cc1c2 | 2437 | flag_code = (enum flag_code) value; |
40fb9820 L |
2438 | if (flag_code == CODE_64BIT) |
2439 | { | |
2440 | cpu_arch_flags.bitfield.cpu64 = 1; | |
2441 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
40fb9820 L |
2442 | } |
2443 | else | |
2444 | { | |
2445 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2446 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
40fb9820 L |
2447 | } |
2448 | if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm ) | |
3e73aa7c | 2449 | { |
78f12dd3 L |
2450 | if (check) |
2451 | as_error = as_fatal; | |
2452 | else | |
2453 | as_error = as_bad; | |
2454 | (*as_error) (_("64bit mode not supported on `%s'."), | |
2455 | cpu_arch_name ? cpu_arch_name : default_arch); | |
3e73aa7c | 2456 | } |
40fb9820 | 2457 | if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386) |
3e73aa7c | 2458 | { |
78f12dd3 L |
2459 | if (check) |
2460 | as_error = as_fatal; | |
2461 | else | |
2462 | as_error = as_bad; | |
2463 | (*as_error) (_("32bit mode not supported on `%s'."), | |
2464 | cpu_arch_name ? cpu_arch_name : default_arch); | |
3e73aa7c | 2465 | } |
eecb386c AM |
2466 | stackop_size = '\0'; |
2467 | } | |
2468 | ||
78f12dd3 L |
2469 | static void |
2470 | set_code_flag (int value) | |
2471 | { | |
2472 | update_code_flag (value, 0); | |
2473 | } | |
2474 | ||
eecb386c | 2475 | static void |
e3bb37b5 | 2476 | set_16bit_gcc_code_flag (int new_code_flag) |
252b5132 | 2477 | { |
1e9cc1c2 | 2478 | flag_code = (enum flag_code) new_code_flag; |
40fb9820 L |
2479 | if (flag_code != CODE_16BIT) |
2480 | abort (); | |
2481 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2482 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
9306ca4a | 2483 | stackop_size = LONG_MNEM_SUFFIX; |
252b5132 RH |
2484 | } |
2485 | ||
2486 | static void | |
e3bb37b5 | 2487 | set_intel_syntax (int syntax_flag) |
252b5132 RH |
2488 | { |
2489 | /* Find out if register prefixing is specified. */ | |
2490 | int ask_naked_reg = 0; | |
2491 | ||
2492 | SKIP_WHITESPACE (); | |
29b0f896 | 2493 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
252b5132 | 2494 | { |
d02603dc NC |
2495 | char *string; |
2496 | int e = get_symbol_name (&string); | |
252b5132 | 2497 | |
47926f60 | 2498 | if (strcmp (string, "prefix") == 0) |
252b5132 | 2499 | ask_naked_reg = 1; |
47926f60 | 2500 | else if (strcmp (string, "noprefix") == 0) |
252b5132 RH |
2501 | ask_naked_reg = -1; |
2502 | else | |
d0b47220 | 2503 | as_bad (_("bad argument to syntax directive.")); |
d02603dc | 2504 | (void) restore_line_pointer (e); |
252b5132 RH |
2505 | } |
2506 | demand_empty_rest_of_line (); | |
c3332e24 | 2507 | |
252b5132 RH |
2508 | intel_syntax = syntax_flag; |
2509 | ||
2510 | if (ask_naked_reg == 0) | |
f86103b7 AM |
2511 | allow_naked_reg = (intel_syntax |
2512 | && (bfd_get_symbol_leading_char (stdoutput) != '\0')); | |
252b5132 RH |
2513 | else |
2514 | allow_naked_reg = (ask_naked_reg < 0); | |
9306ca4a | 2515 | |
ee86248c | 2516 | expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0); |
7ab9ffdd | 2517 | |
e4a3b5a4 | 2518 | identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0; |
9306ca4a | 2519 | identifier_chars['$'] = intel_syntax ? '$' : 0; |
e4a3b5a4 | 2520 | register_prefix = allow_naked_reg ? "" : "%"; |
252b5132 RH |
2521 | } |
2522 | ||
1efbbeb4 L |
2523 | static void |
2524 | set_intel_mnemonic (int mnemonic_flag) | |
2525 | { | |
e1d4d893 | 2526 | intel_mnemonic = mnemonic_flag; |
1efbbeb4 L |
2527 | } |
2528 | ||
db51cc60 L |
2529 | static void |
2530 | set_allow_index_reg (int flag) | |
2531 | { | |
2532 | allow_index_reg = flag; | |
2533 | } | |
2534 | ||
cb19c032 | 2535 | static void |
7bab8ab5 | 2536 | set_check (int what) |
cb19c032 | 2537 | { |
7bab8ab5 JB |
2538 | enum check_kind *kind; |
2539 | const char *str; | |
2540 | ||
2541 | if (what) | |
2542 | { | |
2543 | kind = &operand_check; | |
2544 | str = "operand"; | |
2545 | } | |
2546 | else | |
2547 | { | |
2548 | kind = &sse_check; | |
2549 | str = "sse"; | |
2550 | } | |
2551 | ||
cb19c032 L |
2552 | SKIP_WHITESPACE (); |
2553 | ||
2554 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
2555 | { | |
d02603dc NC |
2556 | char *string; |
2557 | int e = get_symbol_name (&string); | |
cb19c032 L |
2558 | |
2559 | if (strcmp (string, "none") == 0) | |
7bab8ab5 | 2560 | *kind = check_none; |
cb19c032 | 2561 | else if (strcmp (string, "warning") == 0) |
7bab8ab5 | 2562 | *kind = check_warning; |
cb19c032 | 2563 | else if (strcmp (string, "error") == 0) |
7bab8ab5 | 2564 | *kind = check_error; |
cb19c032 | 2565 | else |
7bab8ab5 | 2566 | as_bad (_("bad argument to %s_check directive."), str); |
d02603dc | 2567 | (void) restore_line_pointer (e); |
cb19c032 L |
2568 | } |
2569 | else | |
7bab8ab5 | 2570 | as_bad (_("missing argument for %s_check directive"), str); |
cb19c032 L |
2571 | |
2572 | demand_empty_rest_of_line (); | |
2573 | } | |
2574 | ||
8a9036a4 L |
2575 | static void |
2576 | check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED, | |
1e9cc1c2 | 2577 | i386_cpu_flags new_flag ATTRIBUTE_UNUSED) |
8a9036a4 L |
2578 | { |
2579 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
2580 | static const char *arch; | |
2581 | ||
2582 | /* Intel LIOM is only supported on ELF. */ | |
2583 | if (!IS_ELF) | |
2584 | return; | |
2585 | ||
2586 | if (!arch) | |
2587 | { | |
2588 | /* Use cpu_arch_name if it is set in md_parse_option. Otherwise | |
2589 | use default_arch. */ | |
2590 | arch = cpu_arch_name; | |
2591 | if (!arch) | |
2592 | arch = default_arch; | |
2593 | } | |
2594 | ||
81486035 L |
2595 | /* If we are targeting Intel MCU, we must enable it. */ |
2596 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU | |
2597 | || new_flag.bitfield.cpuiamcu) | |
2598 | return; | |
2599 | ||
3632d14b | 2600 | /* If we are targeting Intel L1OM, we must enable it. */ |
8a9036a4 | 2601 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM |
1e9cc1c2 | 2602 | || new_flag.bitfield.cpul1om) |
8a9036a4 | 2603 | return; |
76ba9986 | 2604 | |
7a9068fe L |
2605 | /* If we are targeting Intel K1OM, we must enable it. */ |
2606 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM | |
2607 | || new_flag.bitfield.cpuk1om) | |
2608 | return; | |
2609 | ||
8a9036a4 L |
2610 | as_bad (_("`%s' is not supported on `%s'"), name, arch); |
2611 | #endif | |
2612 | } | |
2613 | ||
e413e4e9 | 2614 | static void |
e3bb37b5 | 2615 | set_cpu_arch (int dummy ATTRIBUTE_UNUSED) |
e413e4e9 | 2616 | { |
47926f60 | 2617 | SKIP_WHITESPACE (); |
e413e4e9 | 2618 | |
29b0f896 | 2619 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
e413e4e9 | 2620 | { |
d02603dc NC |
2621 | char *string; |
2622 | int e = get_symbol_name (&string); | |
91d6fa6a | 2623 | unsigned int j; |
40fb9820 | 2624 | i386_cpu_flags flags; |
e413e4e9 | 2625 | |
91d6fa6a | 2626 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
e413e4e9 | 2627 | { |
91d6fa6a | 2628 | if (strcmp (string, cpu_arch[j].name) == 0) |
e413e4e9 | 2629 | { |
91d6fa6a | 2630 | check_cpu_arch_compatible (string, cpu_arch[j].flags); |
8a9036a4 | 2631 | |
5c6af06e JB |
2632 | if (*string != '.') |
2633 | { | |
91d6fa6a | 2634 | cpu_arch_name = cpu_arch[j].name; |
5c6af06e | 2635 | cpu_sub_arch_name = NULL; |
91d6fa6a | 2636 | cpu_arch_flags = cpu_arch[j].flags; |
40fb9820 L |
2637 | if (flag_code == CODE_64BIT) |
2638 | { | |
2639 | cpu_arch_flags.bitfield.cpu64 = 1; | |
2640 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
2641 | } | |
2642 | else | |
2643 | { | |
2644 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2645 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
2646 | } | |
91d6fa6a NC |
2647 | cpu_arch_isa = cpu_arch[j].type; |
2648 | cpu_arch_isa_flags = cpu_arch[j].flags; | |
ccc9c027 L |
2649 | if (!cpu_arch_tune_set) |
2650 | { | |
2651 | cpu_arch_tune = cpu_arch_isa; | |
2652 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
2653 | } | |
5c6af06e JB |
2654 | break; |
2655 | } | |
40fb9820 | 2656 | |
293f5f65 L |
2657 | flags = cpu_flags_or (cpu_arch_flags, |
2658 | cpu_arch[j].flags); | |
81486035 | 2659 | |
5b64d091 | 2660 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
5c6af06e | 2661 | { |
6305a203 L |
2662 | if (cpu_sub_arch_name) |
2663 | { | |
2664 | char *name = cpu_sub_arch_name; | |
2665 | cpu_sub_arch_name = concat (name, | |
91d6fa6a | 2666 | cpu_arch[j].name, |
1bf57e9f | 2667 | (const char *) NULL); |
6305a203 L |
2668 | free (name); |
2669 | } | |
2670 | else | |
91d6fa6a | 2671 | cpu_sub_arch_name = xstrdup (cpu_arch[j].name); |
40fb9820 | 2672 | cpu_arch_flags = flags; |
a586129e | 2673 | cpu_arch_isa_flags = flags; |
5c6af06e | 2674 | } |
0089dace L |
2675 | else |
2676 | cpu_arch_isa_flags | |
2677 | = cpu_flags_or (cpu_arch_isa_flags, | |
2678 | cpu_arch[j].flags); | |
d02603dc | 2679 | (void) restore_line_pointer (e); |
5c6af06e JB |
2680 | demand_empty_rest_of_line (); |
2681 | return; | |
e413e4e9 AM |
2682 | } |
2683 | } | |
293f5f65 L |
2684 | |
2685 | if (*string == '.' && j >= ARRAY_SIZE (cpu_arch)) | |
2686 | { | |
33eaf5de | 2687 | /* Disable an ISA extension. */ |
293f5f65 L |
2688 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) |
2689 | if (strcmp (string + 1, cpu_noarch [j].name) == 0) | |
2690 | { | |
2691 | flags = cpu_flags_and_not (cpu_arch_flags, | |
2692 | cpu_noarch[j].flags); | |
2693 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) | |
2694 | { | |
2695 | if (cpu_sub_arch_name) | |
2696 | { | |
2697 | char *name = cpu_sub_arch_name; | |
2698 | cpu_sub_arch_name = concat (name, string, | |
2699 | (const char *) NULL); | |
2700 | free (name); | |
2701 | } | |
2702 | else | |
2703 | cpu_sub_arch_name = xstrdup (string); | |
2704 | cpu_arch_flags = flags; | |
2705 | cpu_arch_isa_flags = flags; | |
2706 | } | |
2707 | (void) restore_line_pointer (e); | |
2708 | demand_empty_rest_of_line (); | |
2709 | return; | |
2710 | } | |
2711 | ||
2712 | j = ARRAY_SIZE (cpu_arch); | |
2713 | } | |
2714 | ||
91d6fa6a | 2715 | if (j >= ARRAY_SIZE (cpu_arch)) |
e413e4e9 AM |
2716 | as_bad (_("no such architecture: `%s'"), string); |
2717 | ||
2718 | *input_line_pointer = e; | |
2719 | } | |
2720 | else | |
2721 | as_bad (_("missing cpu architecture")); | |
2722 | ||
fddf5b5b AM |
2723 | no_cond_jump_promotion = 0; |
2724 | if (*input_line_pointer == ',' | |
29b0f896 | 2725 | && !is_end_of_line[(unsigned char) input_line_pointer[1]]) |
fddf5b5b | 2726 | { |
d02603dc NC |
2727 | char *string; |
2728 | char e; | |
2729 | ||
2730 | ++input_line_pointer; | |
2731 | e = get_symbol_name (&string); | |
fddf5b5b AM |
2732 | |
2733 | if (strcmp (string, "nojumps") == 0) | |
2734 | no_cond_jump_promotion = 1; | |
2735 | else if (strcmp (string, "jumps") == 0) | |
2736 | ; | |
2737 | else | |
2738 | as_bad (_("no such architecture modifier: `%s'"), string); | |
2739 | ||
d02603dc | 2740 | (void) restore_line_pointer (e); |
fddf5b5b AM |
2741 | } |
2742 | ||
e413e4e9 AM |
2743 | demand_empty_rest_of_line (); |
2744 | } | |
2745 | ||
8a9036a4 L |
2746 | enum bfd_architecture |
2747 | i386_arch (void) | |
2748 | { | |
3632d14b | 2749 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 L |
2750 | { |
2751 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2752 | || flag_code != CODE_64BIT) | |
2753 | as_fatal (_("Intel L1OM is 64bit ELF only")); | |
2754 | return bfd_arch_l1om; | |
2755 | } | |
7a9068fe L |
2756 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
2757 | { | |
2758 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2759 | || flag_code != CODE_64BIT) | |
2760 | as_fatal (_("Intel K1OM is 64bit ELF only")); | |
2761 | return bfd_arch_k1om; | |
2762 | } | |
81486035 L |
2763 | else if (cpu_arch_isa == PROCESSOR_IAMCU) |
2764 | { | |
2765 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2766 | || flag_code == CODE_64BIT) | |
2767 | as_fatal (_("Intel MCU is 32bit ELF only")); | |
2768 | return bfd_arch_iamcu; | |
2769 | } | |
8a9036a4 L |
2770 | else |
2771 | return bfd_arch_i386; | |
2772 | } | |
2773 | ||
b9d79e03 | 2774 | unsigned long |
7016a5d5 | 2775 | i386_mach (void) |
b9d79e03 | 2776 | { |
351f65ca | 2777 | if (!strncmp (default_arch, "x86_64", 6)) |
8a9036a4 | 2778 | { |
3632d14b | 2779 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 | 2780 | { |
351f65ca L |
2781 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour |
2782 | || default_arch[6] != '\0') | |
8a9036a4 L |
2783 | as_fatal (_("Intel L1OM is 64bit ELF only")); |
2784 | return bfd_mach_l1om; | |
2785 | } | |
7a9068fe L |
2786 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
2787 | { | |
2788 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2789 | || default_arch[6] != '\0') | |
2790 | as_fatal (_("Intel K1OM is 64bit ELF only")); | |
2791 | return bfd_mach_k1om; | |
2792 | } | |
351f65ca | 2793 | else if (default_arch[6] == '\0') |
8a9036a4 | 2794 | return bfd_mach_x86_64; |
351f65ca L |
2795 | else |
2796 | return bfd_mach_x64_32; | |
8a9036a4 | 2797 | } |
5197d474 L |
2798 | else if (!strcmp (default_arch, "i386") |
2799 | || !strcmp (default_arch, "iamcu")) | |
81486035 L |
2800 | { |
2801 | if (cpu_arch_isa == PROCESSOR_IAMCU) | |
2802 | { | |
2803 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
2804 | as_fatal (_("Intel MCU is 32bit ELF only")); | |
2805 | return bfd_mach_i386_iamcu; | |
2806 | } | |
2807 | else | |
2808 | return bfd_mach_i386_i386; | |
2809 | } | |
b9d79e03 | 2810 | else |
2b5d6a91 | 2811 | as_fatal (_("unknown architecture")); |
b9d79e03 | 2812 | } |
b9d79e03 | 2813 | \f |
252b5132 | 2814 | void |
7016a5d5 | 2815 | md_begin (void) |
252b5132 RH |
2816 | { |
2817 | const char *hash_err; | |
2818 | ||
86fa6981 L |
2819 | /* Support pseudo prefixes like {disp32}. */ |
2820 | lex_type ['{'] = LEX_BEGIN_NAME; | |
2821 | ||
47926f60 | 2822 | /* Initialize op_hash hash table. */ |
252b5132 RH |
2823 | op_hash = hash_new (); |
2824 | ||
2825 | { | |
d3ce72d0 | 2826 | const insn_template *optab; |
29b0f896 | 2827 | templates *core_optab; |
252b5132 | 2828 | |
47926f60 KH |
2829 | /* Setup for loop. */ |
2830 | optab = i386_optab; | |
add39d23 | 2831 | core_optab = XNEW (templates); |
252b5132 RH |
2832 | core_optab->start = optab; |
2833 | ||
2834 | while (1) | |
2835 | { | |
2836 | ++optab; | |
2837 | if (optab->name == NULL | |
2838 | || strcmp (optab->name, (optab - 1)->name) != 0) | |
2839 | { | |
2840 | /* different name --> ship out current template list; | |
47926f60 | 2841 | add to hash table; & begin anew. */ |
252b5132 RH |
2842 | core_optab->end = optab; |
2843 | hash_err = hash_insert (op_hash, | |
2844 | (optab - 1)->name, | |
5a49b8ac | 2845 | (void *) core_optab); |
252b5132 RH |
2846 | if (hash_err) |
2847 | { | |
b37df7c4 | 2848 | as_fatal (_("can't hash %s: %s"), |
252b5132 RH |
2849 | (optab - 1)->name, |
2850 | hash_err); | |
2851 | } | |
2852 | if (optab->name == NULL) | |
2853 | break; | |
add39d23 | 2854 | core_optab = XNEW (templates); |
252b5132 RH |
2855 | core_optab->start = optab; |
2856 | } | |
2857 | } | |
2858 | } | |
2859 | ||
47926f60 | 2860 | /* Initialize reg_hash hash table. */ |
252b5132 RH |
2861 | reg_hash = hash_new (); |
2862 | { | |
29b0f896 | 2863 | const reg_entry *regtab; |
c3fe08fa | 2864 | unsigned int regtab_size = i386_regtab_size; |
252b5132 | 2865 | |
c3fe08fa | 2866 | for (regtab = i386_regtab; regtab_size--; regtab++) |
252b5132 | 2867 | { |
5a49b8ac | 2868 | hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab); |
252b5132 | 2869 | if (hash_err) |
b37df7c4 | 2870 | as_fatal (_("can't hash %s: %s"), |
3e73aa7c JH |
2871 | regtab->reg_name, |
2872 | hash_err); | |
252b5132 RH |
2873 | } |
2874 | } | |
2875 | ||
47926f60 | 2876 | /* Fill in lexical tables: mnemonic_chars, operand_chars. */ |
252b5132 | 2877 | { |
29b0f896 AM |
2878 | int c; |
2879 | char *p; | |
252b5132 RH |
2880 | |
2881 | for (c = 0; c < 256; c++) | |
2882 | { | |
3882b010 | 2883 | if (ISDIGIT (c)) |
252b5132 RH |
2884 | { |
2885 | digit_chars[c] = c; | |
2886 | mnemonic_chars[c] = c; | |
2887 | register_chars[c] = c; | |
2888 | operand_chars[c] = c; | |
2889 | } | |
3882b010 | 2890 | else if (ISLOWER (c)) |
252b5132 RH |
2891 | { |
2892 | mnemonic_chars[c] = c; | |
2893 | register_chars[c] = c; | |
2894 | operand_chars[c] = c; | |
2895 | } | |
3882b010 | 2896 | else if (ISUPPER (c)) |
252b5132 | 2897 | { |
3882b010 | 2898 | mnemonic_chars[c] = TOLOWER (c); |
252b5132 RH |
2899 | register_chars[c] = mnemonic_chars[c]; |
2900 | operand_chars[c] = c; | |
2901 | } | |
43234a1e | 2902 | else if (c == '{' || c == '}') |
86fa6981 L |
2903 | { |
2904 | mnemonic_chars[c] = c; | |
2905 | operand_chars[c] = c; | |
2906 | } | |
252b5132 | 2907 | |
3882b010 | 2908 | if (ISALPHA (c) || ISDIGIT (c)) |
252b5132 RH |
2909 | identifier_chars[c] = c; |
2910 | else if (c >= 128) | |
2911 | { | |
2912 | identifier_chars[c] = c; | |
2913 | operand_chars[c] = c; | |
2914 | } | |
2915 | } | |
2916 | ||
2917 | #ifdef LEX_AT | |
2918 | identifier_chars['@'] = '@'; | |
32137342 NC |
2919 | #endif |
2920 | #ifdef LEX_QM | |
2921 | identifier_chars['?'] = '?'; | |
2922 | operand_chars['?'] = '?'; | |
252b5132 | 2923 | #endif |
252b5132 | 2924 | digit_chars['-'] = '-'; |
c0f3af97 | 2925 | mnemonic_chars['_'] = '_'; |
791fe849 | 2926 | mnemonic_chars['-'] = '-'; |
0003779b | 2927 | mnemonic_chars['.'] = '.'; |
252b5132 RH |
2928 | identifier_chars['_'] = '_'; |
2929 | identifier_chars['.'] = '.'; | |
2930 | ||
2931 | for (p = operand_special_chars; *p != '\0'; p++) | |
2932 | operand_chars[(unsigned char) *p] = *p; | |
2933 | } | |
2934 | ||
a4447b93 RH |
2935 | if (flag_code == CODE_64BIT) |
2936 | { | |
ca19b261 KT |
2937 | #if defined (OBJ_COFF) && defined (TE_PE) |
2938 | x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour | |
2939 | ? 32 : 16); | |
2940 | #else | |
a4447b93 | 2941 | x86_dwarf2_return_column = 16; |
ca19b261 | 2942 | #endif |
61ff971f | 2943 | x86_cie_data_alignment = -8; |
a4447b93 RH |
2944 | } |
2945 | else | |
2946 | { | |
2947 | x86_dwarf2_return_column = 8; | |
2948 | x86_cie_data_alignment = -4; | |
2949 | } | |
252b5132 RH |
2950 | } |
2951 | ||
2952 | void | |
e3bb37b5 | 2953 | i386_print_statistics (FILE *file) |
252b5132 RH |
2954 | { |
2955 | hash_print_statistics (file, "i386 opcode", op_hash); | |
2956 | hash_print_statistics (file, "i386 register", reg_hash); | |
2957 | } | |
2958 | \f | |
252b5132 RH |
2959 | #ifdef DEBUG386 |
2960 | ||
ce8a8b2f | 2961 | /* Debugging routines for md_assemble. */ |
d3ce72d0 | 2962 | static void pte (insn_template *); |
40fb9820 | 2963 | static void pt (i386_operand_type); |
e3bb37b5 L |
2964 | static void pe (expressionS *); |
2965 | static void ps (symbolS *); | |
252b5132 RH |
2966 | |
2967 | static void | |
e3bb37b5 | 2968 | pi (char *line, i386_insn *x) |
252b5132 | 2969 | { |
09137c09 | 2970 | unsigned int j; |
252b5132 RH |
2971 | |
2972 | fprintf (stdout, "%s: template ", line); | |
2973 | pte (&x->tm); | |
09f131f2 JH |
2974 | fprintf (stdout, " address: base %s index %s scale %x\n", |
2975 | x->base_reg ? x->base_reg->reg_name : "none", | |
2976 | x->index_reg ? x->index_reg->reg_name : "none", | |
2977 | x->log2_scale_factor); | |
2978 | fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n", | |
252b5132 | 2979 | x->rm.mode, x->rm.reg, x->rm.regmem); |
09f131f2 JH |
2980 | fprintf (stdout, " sib: base %x index %x scale %x\n", |
2981 | x->sib.base, x->sib.index, x->sib.scale); | |
2982 | fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n", | |
161a04f6 L |
2983 | (x->rex & REX_W) != 0, |
2984 | (x->rex & REX_R) != 0, | |
2985 | (x->rex & REX_X) != 0, | |
2986 | (x->rex & REX_B) != 0); | |
09137c09 | 2987 | for (j = 0; j < x->operands; j++) |
252b5132 | 2988 | { |
09137c09 SP |
2989 | fprintf (stdout, " #%d: ", j + 1); |
2990 | pt (x->types[j]); | |
252b5132 | 2991 | fprintf (stdout, "\n"); |
dc821c5f | 2992 | if (x->types[j].bitfield.reg |
09137c09 | 2993 | || x->types[j].bitfield.regmmx |
1b54b8d7 | 2994 | || x->types[j].bitfield.regsimd |
09137c09 SP |
2995 | || x->types[j].bitfield.sreg2 |
2996 | || x->types[j].bitfield.sreg3 | |
2997 | || x->types[j].bitfield.control | |
2998 | || x->types[j].bitfield.debug | |
2999 | || x->types[j].bitfield.test) | |
3000 | fprintf (stdout, "%s\n", x->op[j].regs->reg_name); | |
3001 | if (operand_type_check (x->types[j], imm)) | |
3002 | pe (x->op[j].imms); | |
3003 | if (operand_type_check (x->types[j], disp)) | |
3004 | pe (x->op[j].disps); | |
252b5132 RH |
3005 | } |
3006 | } | |
3007 | ||
3008 | static void | |
d3ce72d0 | 3009 | pte (insn_template *t) |
252b5132 | 3010 | { |
09137c09 | 3011 | unsigned int j; |
252b5132 | 3012 | fprintf (stdout, " %d operands ", t->operands); |
47926f60 | 3013 | fprintf (stdout, "opcode %x ", t->base_opcode); |
252b5132 RH |
3014 | if (t->extension_opcode != None) |
3015 | fprintf (stdout, "ext %x ", t->extension_opcode); | |
40fb9820 | 3016 | if (t->opcode_modifier.d) |
252b5132 | 3017 | fprintf (stdout, "D"); |
40fb9820 | 3018 | if (t->opcode_modifier.w) |
252b5132 RH |
3019 | fprintf (stdout, "W"); |
3020 | fprintf (stdout, "\n"); | |
09137c09 | 3021 | for (j = 0; j < t->operands; j++) |
252b5132 | 3022 | { |
09137c09 SP |
3023 | fprintf (stdout, " #%d type ", j + 1); |
3024 | pt (t->operand_types[j]); | |
252b5132 RH |
3025 | fprintf (stdout, "\n"); |
3026 | } | |
3027 | } | |
3028 | ||
3029 | static void | |
e3bb37b5 | 3030 | pe (expressionS *e) |
252b5132 | 3031 | { |
24eab124 | 3032 | fprintf (stdout, " operation %d\n", e->X_op); |
b77ad1d4 AM |
3033 | fprintf (stdout, " add_number %ld (%lx)\n", |
3034 | (long) e->X_add_number, (long) e->X_add_number); | |
252b5132 RH |
3035 | if (e->X_add_symbol) |
3036 | { | |
3037 | fprintf (stdout, " add_symbol "); | |
3038 | ps (e->X_add_symbol); | |
3039 | fprintf (stdout, "\n"); | |
3040 | } | |
3041 | if (e->X_op_symbol) | |
3042 | { | |
3043 | fprintf (stdout, " op_symbol "); | |
3044 | ps (e->X_op_symbol); | |
3045 | fprintf (stdout, "\n"); | |
3046 | } | |
3047 | } | |
3048 | ||
3049 | static void | |
e3bb37b5 | 3050 | ps (symbolS *s) |
252b5132 RH |
3051 | { |
3052 | fprintf (stdout, "%s type %s%s", | |
3053 | S_GET_NAME (s), | |
3054 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", | |
3055 | segment_name (S_GET_SEGMENT (s))); | |
3056 | } | |
3057 | ||
7b81dfbb | 3058 | static struct type_name |
252b5132 | 3059 | { |
40fb9820 L |
3060 | i386_operand_type mask; |
3061 | const char *name; | |
252b5132 | 3062 | } |
7b81dfbb | 3063 | const type_names[] = |
252b5132 | 3064 | { |
40fb9820 L |
3065 | { OPERAND_TYPE_REG8, "r8" }, |
3066 | { OPERAND_TYPE_REG16, "r16" }, | |
3067 | { OPERAND_TYPE_REG32, "r32" }, | |
3068 | { OPERAND_TYPE_REG64, "r64" }, | |
3069 | { OPERAND_TYPE_IMM8, "i8" }, | |
3070 | { OPERAND_TYPE_IMM8, "i8s" }, | |
3071 | { OPERAND_TYPE_IMM16, "i16" }, | |
3072 | { OPERAND_TYPE_IMM32, "i32" }, | |
3073 | { OPERAND_TYPE_IMM32S, "i32s" }, | |
3074 | { OPERAND_TYPE_IMM64, "i64" }, | |
3075 | { OPERAND_TYPE_IMM1, "i1" }, | |
3076 | { OPERAND_TYPE_BASEINDEX, "BaseIndex" }, | |
3077 | { OPERAND_TYPE_DISP8, "d8" }, | |
3078 | { OPERAND_TYPE_DISP16, "d16" }, | |
3079 | { OPERAND_TYPE_DISP32, "d32" }, | |
3080 | { OPERAND_TYPE_DISP32S, "d32s" }, | |
3081 | { OPERAND_TYPE_DISP64, "d64" }, | |
3082 | { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" }, | |
3083 | { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" }, | |
3084 | { OPERAND_TYPE_CONTROL, "control reg" }, | |
3085 | { OPERAND_TYPE_TEST, "test reg" }, | |
3086 | { OPERAND_TYPE_DEBUG, "debug reg" }, | |
3087 | { OPERAND_TYPE_FLOATREG, "FReg" }, | |
3088 | { OPERAND_TYPE_FLOATACC, "FAcc" }, | |
3089 | { OPERAND_TYPE_SREG2, "SReg2" }, | |
3090 | { OPERAND_TYPE_SREG3, "SReg3" }, | |
3091 | { OPERAND_TYPE_ACC, "Acc" }, | |
3092 | { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" }, | |
3093 | { OPERAND_TYPE_REGMMX, "rMMX" }, | |
3094 | { OPERAND_TYPE_REGXMM, "rXMM" }, | |
0349dc08 | 3095 | { OPERAND_TYPE_REGYMM, "rYMM" }, |
43234a1e L |
3096 | { OPERAND_TYPE_REGZMM, "rZMM" }, |
3097 | { OPERAND_TYPE_REGMASK, "Mask reg" }, | |
40fb9820 | 3098 | { OPERAND_TYPE_ESSEG, "es" }, |
252b5132 RH |
3099 | }; |
3100 | ||
3101 | static void | |
40fb9820 | 3102 | pt (i386_operand_type t) |
252b5132 | 3103 | { |
40fb9820 | 3104 | unsigned int j; |
c6fb90c8 | 3105 | i386_operand_type a; |
252b5132 | 3106 | |
40fb9820 | 3107 | for (j = 0; j < ARRAY_SIZE (type_names); j++) |
c6fb90c8 L |
3108 | { |
3109 | a = operand_type_and (t, type_names[j].mask); | |
0349dc08 | 3110 | if (!operand_type_all_zero (&a)) |
c6fb90c8 L |
3111 | fprintf (stdout, "%s, ", type_names[j].name); |
3112 | } | |
252b5132 RH |
3113 | fflush (stdout); |
3114 | } | |
3115 | ||
3116 | #endif /* DEBUG386 */ | |
3117 | \f | |
252b5132 | 3118 | static bfd_reloc_code_real_type |
3956db08 | 3119 | reloc (unsigned int size, |
64e74474 AM |
3120 | int pcrel, |
3121 | int sign, | |
3122 | bfd_reloc_code_real_type other) | |
252b5132 | 3123 | { |
47926f60 | 3124 | if (other != NO_RELOC) |
3956db08 | 3125 | { |
91d6fa6a | 3126 | reloc_howto_type *rel; |
3956db08 JB |
3127 | |
3128 | if (size == 8) | |
3129 | switch (other) | |
3130 | { | |
64e74474 AM |
3131 | case BFD_RELOC_X86_64_GOT32: |
3132 | return BFD_RELOC_X86_64_GOT64; | |
3133 | break; | |
553d1284 L |
3134 | case BFD_RELOC_X86_64_GOTPLT64: |
3135 | return BFD_RELOC_X86_64_GOTPLT64; | |
3136 | break; | |
64e74474 AM |
3137 | case BFD_RELOC_X86_64_PLTOFF64: |
3138 | return BFD_RELOC_X86_64_PLTOFF64; | |
3139 | break; | |
3140 | case BFD_RELOC_X86_64_GOTPC32: | |
3141 | other = BFD_RELOC_X86_64_GOTPC64; | |
3142 | break; | |
3143 | case BFD_RELOC_X86_64_GOTPCREL: | |
3144 | other = BFD_RELOC_X86_64_GOTPCREL64; | |
3145 | break; | |
3146 | case BFD_RELOC_X86_64_TPOFF32: | |
3147 | other = BFD_RELOC_X86_64_TPOFF64; | |
3148 | break; | |
3149 | case BFD_RELOC_X86_64_DTPOFF32: | |
3150 | other = BFD_RELOC_X86_64_DTPOFF64; | |
3151 | break; | |
3152 | default: | |
3153 | break; | |
3956db08 | 3154 | } |
e05278af | 3155 | |
8ce3d284 | 3156 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
3157 | if (other == BFD_RELOC_SIZE32) |
3158 | { | |
3159 | if (size == 8) | |
1ab668bf | 3160 | other = BFD_RELOC_SIZE64; |
8fd4256d | 3161 | if (pcrel) |
1ab668bf AM |
3162 | { |
3163 | as_bad (_("there are no pc-relative size relocations")); | |
3164 | return NO_RELOC; | |
3165 | } | |
8fd4256d | 3166 | } |
8ce3d284 | 3167 | #endif |
8fd4256d | 3168 | |
e05278af | 3169 | /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */ |
f2d8a97c | 3170 | if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc)) |
e05278af JB |
3171 | sign = -1; |
3172 | ||
91d6fa6a NC |
3173 | rel = bfd_reloc_type_lookup (stdoutput, other); |
3174 | if (!rel) | |
3956db08 | 3175 | as_bad (_("unknown relocation (%u)"), other); |
91d6fa6a | 3176 | else if (size != bfd_get_reloc_size (rel)) |
3956db08 | 3177 | as_bad (_("%u-byte relocation cannot be applied to %u-byte field"), |
91d6fa6a | 3178 | bfd_get_reloc_size (rel), |
3956db08 | 3179 | size); |
91d6fa6a | 3180 | else if (pcrel && !rel->pc_relative) |
3956db08 | 3181 | as_bad (_("non-pc-relative relocation for pc-relative field")); |
91d6fa6a | 3182 | else if ((rel->complain_on_overflow == complain_overflow_signed |
3956db08 | 3183 | && !sign) |
91d6fa6a | 3184 | || (rel->complain_on_overflow == complain_overflow_unsigned |
64e74474 | 3185 | && sign > 0)) |
3956db08 JB |
3186 | as_bad (_("relocated field and relocation type differ in signedness")); |
3187 | else | |
3188 | return other; | |
3189 | return NO_RELOC; | |
3190 | } | |
252b5132 RH |
3191 | |
3192 | if (pcrel) | |
3193 | { | |
3e73aa7c | 3194 | if (!sign) |
3956db08 | 3195 | as_bad (_("there are no unsigned pc-relative relocations")); |
252b5132 RH |
3196 | switch (size) |
3197 | { | |
3198 | case 1: return BFD_RELOC_8_PCREL; | |
3199 | case 2: return BFD_RELOC_16_PCREL; | |
d258b828 | 3200 | case 4: return BFD_RELOC_32_PCREL; |
d6ab8113 | 3201 | case 8: return BFD_RELOC_64_PCREL; |
252b5132 | 3202 | } |
3956db08 | 3203 | as_bad (_("cannot do %u byte pc-relative relocation"), size); |
252b5132 RH |
3204 | } |
3205 | else | |
3206 | { | |
3956db08 | 3207 | if (sign > 0) |
e5cb08ac | 3208 | switch (size) |
3e73aa7c JH |
3209 | { |
3210 | case 4: return BFD_RELOC_X86_64_32S; | |
3211 | } | |
3212 | else | |
3213 | switch (size) | |
3214 | { | |
3215 | case 1: return BFD_RELOC_8; | |
3216 | case 2: return BFD_RELOC_16; | |
3217 | case 4: return BFD_RELOC_32; | |
3218 | case 8: return BFD_RELOC_64; | |
3219 | } | |
3956db08 JB |
3220 | as_bad (_("cannot do %s %u byte relocation"), |
3221 | sign > 0 ? "signed" : "unsigned", size); | |
252b5132 RH |
3222 | } |
3223 | ||
0cc9e1d3 | 3224 | return NO_RELOC; |
252b5132 RH |
3225 | } |
3226 | ||
47926f60 KH |
3227 | /* Here we decide which fixups can be adjusted to make them relative to |
3228 | the beginning of the section instead of the symbol. Basically we need | |
3229 | to make sure that the dynamic relocations are done correctly, so in | |
3230 | some cases we force the original symbol to be used. */ | |
3231 | ||
252b5132 | 3232 | int |
e3bb37b5 | 3233 | tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED) |
252b5132 | 3234 | { |
6d249963 | 3235 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 3236 | if (!IS_ELF) |
31312f95 AM |
3237 | return 1; |
3238 | ||
a161fe53 AM |
3239 | /* Don't adjust pc-relative references to merge sections in 64-bit |
3240 | mode. */ | |
3241 | if (use_rela_relocations | |
3242 | && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0 | |
3243 | && fixP->fx_pcrel) | |
252b5132 | 3244 | return 0; |
31312f95 | 3245 | |
8d01d9a9 AJ |
3246 | /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations |
3247 | and changed later by validate_fix. */ | |
3248 | if (GOT_symbol && fixP->fx_subsy == GOT_symbol | |
3249 | && fixP->fx_r_type == BFD_RELOC_32_PCREL) | |
3250 | return 0; | |
3251 | ||
8fd4256d L |
3252 | /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol |
3253 | for size relocations. */ | |
3254 | if (fixP->fx_r_type == BFD_RELOC_SIZE32 | |
3255 | || fixP->fx_r_type == BFD_RELOC_SIZE64 | |
3256 | || fixP->fx_r_type == BFD_RELOC_386_GOTOFF | |
252b5132 RH |
3257 | || fixP->fx_r_type == BFD_RELOC_386_PLT32 |
3258 | || fixP->fx_r_type == BFD_RELOC_386_GOT32 | |
02a86693 | 3259 | || fixP->fx_r_type == BFD_RELOC_386_GOT32X |
13ae64f3 JJ |
3260 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GD |
3261 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM | |
3262 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32 | |
3263 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32 | |
37e55690 JJ |
3264 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE |
3265 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE | |
13ae64f3 JJ |
3266 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32 |
3267 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE | |
67a4f2b7 AO |
3268 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC |
3269 | || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL | |
3e73aa7c JH |
3270 | || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32 |
3271 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32 | |
80b3ee89 | 3272 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL |
56ceb5b5 L |
3273 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX |
3274 | || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX | |
bffbf940 JJ |
3275 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD |
3276 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD | |
3277 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32 | |
d6ab8113 | 3278 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64 |
bffbf940 JJ |
3279 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF |
3280 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32 | |
d6ab8113 JB |
3281 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64 |
3282 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64 | |
67a4f2b7 AO |
3283 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC |
3284 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL | |
252b5132 RH |
3285 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
3286 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
3287 | return 0; | |
31312f95 | 3288 | #endif |
252b5132 RH |
3289 | return 1; |
3290 | } | |
252b5132 | 3291 | |
b4cac588 | 3292 | static int |
e3bb37b5 | 3293 | intel_float_operand (const char *mnemonic) |
252b5132 | 3294 | { |
9306ca4a JB |
3295 | /* Note that the value returned is meaningful only for opcodes with (memory) |
3296 | operands, hence the code here is free to improperly handle opcodes that | |
3297 | have no operands (for better performance and smaller code). */ | |
3298 | ||
3299 | if (mnemonic[0] != 'f') | |
3300 | return 0; /* non-math */ | |
3301 | ||
3302 | switch (mnemonic[1]) | |
3303 | { | |
3304 | /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and | |
3305 | the fs segment override prefix not currently handled because no | |
3306 | call path can make opcodes without operands get here */ | |
3307 | case 'i': | |
3308 | return 2 /* integer op */; | |
3309 | case 'l': | |
3310 | if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e')) | |
3311 | return 3; /* fldcw/fldenv */ | |
3312 | break; | |
3313 | case 'n': | |
3314 | if (mnemonic[2] != 'o' /* fnop */) | |
3315 | return 3; /* non-waiting control op */ | |
3316 | break; | |
3317 | case 'r': | |
3318 | if (mnemonic[2] == 's') | |
3319 | return 3; /* frstor/frstpm */ | |
3320 | break; | |
3321 | case 's': | |
3322 | if (mnemonic[2] == 'a') | |
3323 | return 3; /* fsave */ | |
3324 | if (mnemonic[2] == 't') | |
3325 | { | |
3326 | switch (mnemonic[3]) | |
3327 | { | |
3328 | case 'c': /* fstcw */ | |
3329 | case 'd': /* fstdw */ | |
3330 | case 'e': /* fstenv */ | |
3331 | case 's': /* fsts[gw] */ | |
3332 | return 3; | |
3333 | } | |
3334 | } | |
3335 | break; | |
3336 | case 'x': | |
3337 | if (mnemonic[2] == 'r' || mnemonic[2] == 's') | |
3338 | return 0; /* fxsave/fxrstor are not really math ops */ | |
3339 | break; | |
3340 | } | |
252b5132 | 3341 | |
9306ca4a | 3342 | return 1; |
252b5132 RH |
3343 | } |
3344 | ||
c0f3af97 L |
3345 | /* Build the VEX prefix. */ |
3346 | ||
3347 | static void | |
d3ce72d0 | 3348 | build_vex_prefix (const insn_template *t) |
c0f3af97 L |
3349 | { |
3350 | unsigned int register_specifier; | |
3351 | unsigned int implied_prefix; | |
3352 | unsigned int vector_length; | |
3353 | ||
3354 | /* Check register specifier. */ | |
3355 | if (i.vex.register_specifier) | |
43234a1e L |
3356 | { |
3357 | register_specifier = | |
3358 | ~register_number (i.vex.register_specifier) & 0xf; | |
3359 | gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0); | |
3360 | } | |
c0f3af97 L |
3361 | else |
3362 | register_specifier = 0xf; | |
3363 | ||
33eaf5de | 3364 | /* Use 2-byte VEX prefix by swapping destination and source |
fa99fab2 | 3365 | operand. */ |
86fa6981 L |
3366 | if (i.vec_encoding != vex_encoding_vex3 |
3367 | && i.dir_encoding == dir_encoding_default | |
fa99fab2 | 3368 | && i.operands == i.reg_operands |
dbbc8b7e | 3369 | && operand_type_equal (&i.types[0], &i.types[i.operands - 1]) |
7f399153 | 3370 | && i.tm.opcode_modifier.vexopcode == VEX0F |
dbbc8b7e | 3371 | && (i.tm.opcode_modifier.load || i.tm.opcode_modifier.d) |
fa99fab2 L |
3372 | && i.rex == REX_B) |
3373 | { | |
3374 | unsigned int xchg = i.operands - 1; | |
3375 | union i386_op temp_op; | |
3376 | i386_operand_type temp_type; | |
3377 | ||
3378 | temp_type = i.types[xchg]; | |
3379 | i.types[xchg] = i.types[0]; | |
3380 | i.types[0] = temp_type; | |
3381 | temp_op = i.op[xchg]; | |
3382 | i.op[xchg] = i.op[0]; | |
3383 | i.op[0] = temp_op; | |
3384 | ||
9c2799c2 | 3385 | gas_assert (i.rm.mode == 3); |
fa99fab2 L |
3386 | |
3387 | i.rex = REX_R; | |
3388 | xchg = i.rm.regmem; | |
3389 | i.rm.regmem = i.rm.reg; | |
3390 | i.rm.reg = xchg; | |
3391 | ||
dbbc8b7e JB |
3392 | if (i.tm.opcode_modifier.d) |
3393 | i.tm.base_opcode ^= (i.tm.base_opcode & 0xee) != 0x6e | |
3394 | ? Opcode_SIMD_FloatD : Opcode_SIMD_IntD; | |
3395 | else /* Use the next insn. */ | |
3396 | i.tm = t[1]; | |
fa99fab2 L |
3397 | } |
3398 | ||
539f890d L |
3399 | if (i.tm.opcode_modifier.vex == VEXScalar) |
3400 | vector_length = avxscalar; | |
10c17abd JB |
3401 | else if (i.tm.opcode_modifier.vex == VEX256) |
3402 | vector_length = 1; | |
539f890d | 3403 | else |
10c17abd | 3404 | { |
56522fc5 | 3405 | unsigned int op; |
10c17abd | 3406 | |
c7213af9 L |
3407 | /* Determine vector length from the last multi-length vector |
3408 | operand. */ | |
10c17abd | 3409 | vector_length = 0; |
56522fc5 | 3410 | for (op = t->operands; op--;) |
10c17abd JB |
3411 | if (t->operand_types[op].bitfield.xmmword |
3412 | && t->operand_types[op].bitfield.ymmword | |
3413 | && i.types[op].bitfield.ymmword) | |
3414 | { | |
3415 | vector_length = 1; | |
3416 | break; | |
3417 | } | |
3418 | } | |
c0f3af97 L |
3419 | |
3420 | switch ((i.tm.base_opcode >> 8) & 0xff) | |
3421 | { | |
3422 | case 0: | |
3423 | implied_prefix = 0; | |
3424 | break; | |
3425 | case DATA_PREFIX_OPCODE: | |
3426 | implied_prefix = 1; | |
3427 | break; | |
3428 | case REPE_PREFIX_OPCODE: | |
3429 | implied_prefix = 2; | |
3430 | break; | |
3431 | case REPNE_PREFIX_OPCODE: | |
3432 | implied_prefix = 3; | |
3433 | break; | |
3434 | default: | |
3435 | abort (); | |
3436 | } | |
3437 | ||
3438 | /* Use 2-byte VEX prefix if possible. */ | |
86fa6981 L |
3439 | if (i.vec_encoding != vex_encoding_vex3 |
3440 | && i.tm.opcode_modifier.vexopcode == VEX0F | |
04251de0 | 3441 | && i.tm.opcode_modifier.vexw != VEXW1 |
c0f3af97 L |
3442 | && (i.rex & (REX_W | REX_X | REX_B)) == 0) |
3443 | { | |
3444 | /* 2-byte VEX prefix. */ | |
3445 | unsigned int r; | |
3446 | ||
3447 | i.vex.length = 2; | |
3448 | i.vex.bytes[0] = 0xc5; | |
3449 | ||
3450 | /* Check the REX.R bit. */ | |
3451 | r = (i.rex & REX_R) ? 0 : 1; | |
3452 | i.vex.bytes[1] = (r << 7 | |
3453 | | register_specifier << 3 | |
3454 | | vector_length << 2 | |
3455 | | implied_prefix); | |
3456 | } | |
3457 | else | |
3458 | { | |
3459 | /* 3-byte VEX prefix. */ | |
3460 | unsigned int m, w; | |
3461 | ||
f88c9eb0 | 3462 | i.vex.length = 3; |
f88c9eb0 | 3463 | |
7f399153 | 3464 | switch (i.tm.opcode_modifier.vexopcode) |
5dd85c99 | 3465 | { |
7f399153 L |
3466 | case VEX0F: |
3467 | m = 0x1; | |
80de6e00 | 3468 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3469 | break; |
3470 | case VEX0F38: | |
3471 | m = 0x2; | |
80de6e00 | 3472 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3473 | break; |
3474 | case VEX0F3A: | |
3475 | m = 0x3; | |
80de6e00 | 3476 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3477 | break; |
3478 | case XOP08: | |
5dd85c99 SP |
3479 | m = 0x8; |
3480 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3481 | break; |
3482 | case XOP09: | |
f88c9eb0 SP |
3483 | m = 0x9; |
3484 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3485 | break; |
3486 | case XOP0A: | |
f88c9eb0 SP |
3487 | m = 0xa; |
3488 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3489 | break; |
3490 | default: | |
3491 | abort (); | |
f88c9eb0 | 3492 | } |
c0f3af97 | 3493 | |
c0f3af97 L |
3494 | /* The high 3 bits of the second VEX byte are 1's compliment |
3495 | of RXB bits from REX. */ | |
3496 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; | |
3497 | ||
3498 | /* Check the REX.W bit. */ | |
3499 | w = (i.rex & REX_W) ? 1 : 0; | |
b28d1bda IT |
3500 | if (i.tm.opcode_modifier.vexw == VEXW1) |
3501 | w = 1; | |
c0f3af97 L |
3502 | |
3503 | i.vex.bytes[2] = (w << 7 | |
3504 | | register_specifier << 3 | |
3505 | | vector_length << 2 | |
3506 | | implied_prefix); | |
3507 | } | |
3508 | } | |
3509 | ||
e771e7c9 JB |
3510 | static INLINE bfd_boolean |
3511 | is_evex_encoding (const insn_template *t) | |
3512 | { | |
7091c612 | 3513 | return t->opcode_modifier.evex || t->opcode_modifier.disp8memshift |
e771e7c9 JB |
3514 | || t->opcode_modifier.broadcast || t->opcode_modifier.masking |
3515 | || t->opcode_modifier.staticrounding || t->opcode_modifier.sae; | |
3516 | } | |
3517 | ||
7a8655d2 JB |
3518 | static INLINE bfd_boolean |
3519 | is_any_vex_encoding (const insn_template *t) | |
3520 | { | |
3521 | return t->opcode_modifier.vex || t->opcode_modifier.vexopcode | |
3522 | || is_evex_encoding (t); | |
3523 | } | |
3524 | ||
43234a1e L |
3525 | /* Build the EVEX prefix. */ |
3526 | ||
3527 | static void | |
3528 | build_evex_prefix (void) | |
3529 | { | |
3530 | unsigned int register_specifier; | |
3531 | unsigned int implied_prefix; | |
3532 | unsigned int m, w; | |
3533 | rex_byte vrex_used = 0; | |
3534 | ||
3535 | /* Check register specifier. */ | |
3536 | if (i.vex.register_specifier) | |
3537 | { | |
3538 | gas_assert ((i.vrex & REX_X) == 0); | |
3539 | ||
3540 | register_specifier = i.vex.register_specifier->reg_num; | |
3541 | if ((i.vex.register_specifier->reg_flags & RegRex)) | |
3542 | register_specifier += 8; | |
3543 | /* The upper 16 registers are encoded in the fourth byte of the | |
3544 | EVEX prefix. */ | |
3545 | if (!(i.vex.register_specifier->reg_flags & RegVRex)) | |
3546 | i.vex.bytes[3] = 0x8; | |
3547 | register_specifier = ~register_specifier & 0xf; | |
3548 | } | |
3549 | else | |
3550 | { | |
3551 | register_specifier = 0xf; | |
3552 | ||
3553 | /* Encode upper 16 vector index register in the fourth byte of | |
3554 | the EVEX prefix. */ | |
3555 | if (!(i.vrex & REX_X)) | |
3556 | i.vex.bytes[3] = 0x8; | |
3557 | else | |
3558 | vrex_used |= REX_X; | |
3559 | } | |
3560 | ||
3561 | switch ((i.tm.base_opcode >> 8) & 0xff) | |
3562 | { | |
3563 | case 0: | |
3564 | implied_prefix = 0; | |
3565 | break; | |
3566 | case DATA_PREFIX_OPCODE: | |
3567 | implied_prefix = 1; | |
3568 | break; | |
3569 | case REPE_PREFIX_OPCODE: | |
3570 | implied_prefix = 2; | |
3571 | break; | |
3572 | case REPNE_PREFIX_OPCODE: | |
3573 | implied_prefix = 3; | |
3574 | break; | |
3575 | default: | |
3576 | abort (); | |
3577 | } | |
3578 | ||
3579 | /* 4 byte EVEX prefix. */ | |
3580 | i.vex.length = 4; | |
3581 | i.vex.bytes[0] = 0x62; | |
3582 | ||
3583 | /* mmmm bits. */ | |
3584 | switch (i.tm.opcode_modifier.vexopcode) | |
3585 | { | |
3586 | case VEX0F: | |
3587 | m = 1; | |
3588 | break; | |
3589 | case VEX0F38: | |
3590 | m = 2; | |
3591 | break; | |
3592 | case VEX0F3A: | |
3593 | m = 3; | |
3594 | break; | |
3595 | default: | |
3596 | abort (); | |
3597 | break; | |
3598 | } | |
3599 | ||
3600 | /* The high 3 bits of the second EVEX byte are 1's compliment of RXB | |
3601 | bits from REX. */ | |
3602 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; | |
3603 | ||
3604 | /* The fifth bit of the second EVEX byte is 1's compliment of the | |
3605 | REX_R bit in VREX. */ | |
3606 | if (!(i.vrex & REX_R)) | |
3607 | i.vex.bytes[1] |= 0x10; | |
3608 | else | |
3609 | vrex_used |= REX_R; | |
3610 | ||
3611 | if ((i.reg_operands + i.imm_operands) == i.operands) | |
3612 | { | |
3613 | /* When all operands are registers, the REX_X bit in REX is not | |
3614 | used. We reuse it to encode the upper 16 registers, which is | |
3615 | indicated by the REX_B bit in VREX. The REX_X bit is encoded | |
3616 | as 1's compliment. */ | |
3617 | if ((i.vrex & REX_B)) | |
3618 | { | |
3619 | vrex_used |= REX_B; | |
3620 | i.vex.bytes[1] &= ~0x40; | |
3621 | } | |
3622 | } | |
3623 | ||
3624 | /* EVEX instructions shouldn't need the REX prefix. */ | |
3625 | i.vrex &= ~vrex_used; | |
3626 | gas_assert (i.vrex == 0); | |
3627 | ||
3628 | /* Check the REX.W bit. */ | |
3629 | w = (i.rex & REX_W) ? 1 : 0; | |
3630 | if (i.tm.opcode_modifier.vexw) | |
3631 | { | |
3632 | if (i.tm.opcode_modifier.vexw == VEXW1) | |
3633 | w = 1; | |
3634 | } | |
3635 | /* If w is not set it means we are dealing with WIG instruction. */ | |
3636 | else if (!w) | |
3637 | { | |
3638 | if (evexwig == evexw1) | |
3639 | w = 1; | |
3640 | } | |
3641 | ||
3642 | /* Encode the U bit. */ | |
3643 | implied_prefix |= 0x4; | |
3644 | ||
3645 | /* The third byte of the EVEX prefix. */ | |
3646 | i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix); | |
3647 | ||
3648 | /* The fourth byte of the EVEX prefix. */ | |
3649 | /* The zeroing-masking bit. */ | |
3650 | if (i.mask && i.mask->zeroing) | |
3651 | i.vex.bytes[3] |= 0x80; | |
3652 | ||
3653 | /* Don't always set the broadcast bit if there is no RC. */ | |
3654 | if (!i.rounding) | |
3655 | { | |
3656 | /* Encode the vector length. */ | |
3657 | unsigned int vec_length; | |
3658 | ||
e771e7c9 JB |
3659 | if (!i.tm.opcode_modifier.evex |
3660 | || i.tm.opcode_modifier.evex == EVEXDYN) | |
3661 | { | |
56522fc5 | 3662 | unsigned int op; |
e771e7c9 | 3663 | |
c7213af9 L |
3664 | /* Determine vector length from the last multi-length vector |
3665 | operand. */ | |
e771e7c9 | 3666 | vec_length = 0; |
56522fc5 | 3667 | for (op = i.operands; op--;) |
e771e7c9 JB |
3668 | if (i.tm.operand_types[op].bitfield.xmmword |
3669 | + i.tm.operand_types[op].bitfield.ymmword | |
3670 | + i.tm.operand_types[op].bitfield.zmmword > 1) | |
3671 | { | |
3672 | if (i.types[op].bitfield.zmmword) | |
c7213af9 L |
3673 | { |
3674 | i.tm.opcode_modifier.evex = EVEX512; | |
3675 | break; | |
3676 | } | |
e771e7c9 | 3677 | else if (i.types[op].bitfield.ymmword) |
c7213af9 L |
3678 | { |
3679 | i.tm.opcode_modifier.evex = EVEX256; | |
3680 | break; | |
3681 | } | |
e771e7c9 | 3682 | else if (i.types[op].bitfield.xmmword) |
c7213af9 L |
3683 | { |
3684 | i.tm.opcode_modifier.evex = EVEX128; | |
3685 | break; | |
3686 | } | |
625cbd7a JB |
3687 | else if (i.broadcast && (int) op == i.broadcast->operand) |
3688 | { | |
4a1b91ea | 3689 | switch (i.broadcast->bytes) |
625cbd7a JB |
3690 | { |
3691 | case 64: | |
3692 | i.tm.opcode_modifier.evex = EVEX512; | |
3693 | break; | |
3694 | case 32: | |
3695 | i.tm.opcode_modifier.evex = EVEX256; | |
3696 | break; | |
3697 | case 16: | |
3698 | i.tm.opcode_modifier.evex = EVEX128; | |
3699 | break; | |
3700 | default: | |
c7213af9 | 3701 | abort (); |
625cbd7a | 3702 | } |
c7213af9 | 3703 | break; |
625cbd7a | 3704 | } |
e771e7c9 | 3705 | } |
c7213af9 | 3706 | |
56522fc5 | 3707 | if (op >= MAX_OPERANDS) |
c7213af9 | 3708 | abort (); |
e771e7c9 JB |
3709 | } |
3710 | ||
43234a1e L |
3711 | switch (i.tm.opcode_modifier.evex) |
3712 | { | |
3713 | case EVEXLIG: /* LL' is ignored */ | |
3714 | vec_length = evexlig << 5; | |
3715 | break; | |
3716 | case EVEX128: | |
3717 | vec_length = 0 << 5; | |
3718 | break; | |
3719 | case EVEX256: | |
3720 | vec_length = 1 << 5; | |
3721 | break; | |
3722 | case EVEX512: | |
3723 | vec_length = 2 << 5; | |
3724 | break; | |
3725 | default: | |
3726 | abort (); | |
3727 | break; | |
3728 | } | |
3729 | i.vex.bytes[3] |= vec_length; | |
3730 | /* Encode the broadcast bit. */ | |
3731 | if (i.broadcast) | |
3732 | i.vex.bytes[3] |= 0x10; | |
3733 | } | |
3734 | else | |
3735 | { | |
3736 | if (i.rounding->type != saeonly) | |
3737 | i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5); | |
3738 | else | |
d3d3c6db | 3739 | i.vex.bytes[3] |= 0x10 | (evexrcig << 5); |
43234a1e L |
3740 | } |
3741 | ||
3742 | if (i.mask && i.mask->mask) | |
3743 | i.vex.bytes[3] |= i.mask->mask->reg_num; | |
3744 | } | |
3745 | ||
65da13b5 L |
3746 | static void |
3747 | process_immext (void) | |
3748 | { | |
3749 | expressionS *exp; | |
3750 | ||
4c692bc7 JB |
3751 | if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme) |
3752 | && i.operands > 0) | |
65da13b5 | 3753 | { |
4c692bc7 JB |
3754 | /* MONITOR/MWAIT as well as SVME instructions have fixed operands |
3755 | with an opcode suffix which is coded in the same place as an | |
3756 | 8-bit immediate field would be. | |
3757 | Here we check those operands and remove them afterwards. */ | |
65da13b5 L |
3758 | unsigned int x; |
3759 | ||
3760 | for (x = 0; x < i.operands; x++) | |
4c692bc7 | 3761 | if (register_number (i.op[x].regs) != x) |
65da13b5 | 3762 | as_bad (_("can't use register '%s%s' as operand %d in '%s'."), |
1fed0ba1 L |
3763 | register_prefix, i.op[x].regs->reg_name, x + 1, |
3764 | i.tm.name); | |
3765 | ||
3766 | i.operands = 0; | |
65da13b5 L |
3767 | } |
3768 | ||
9916071f AP |
3769 | if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0) |
3770 | { | |
3771 | /* MONITORX/MWAITX instructions have fixed operands with an opcode | |
3772 | suffix which is coded in the same place as an 8-bit immediate | |
3773 | field would be. | |
3774 | Here we check those operands and remove them afterwards. */ | |
3775 | unsigned int x; | |
3776 | ||
3777 | if (i.operands != 3) | |
3778 | abort(); | |
3779 | ||
3780 | for (x = 0; x < 2; x++) | |
3781 | if (register_number (i.op[x].regs) != x) | |
3782 | goto bad_register_operand; | |
3783 | ||
3784 | /* Check for third operand for mwaitx/monitorx insn. */ | |
3785 | if (register_number (i.op[x].regs) | |
3786 | != (x + (i.tm.extension_opcode == 0xfb))) | |
3787 | { | |
3788 | bad_register_operand: | |
3789 | as_bad (_("can't use register '%s%s' as operand %d in '%s'."), | |
3790 | register_prefix, i.op[x].regs->reg_name, x+1, | |
3791 | i.tm.name); | |
3792 | } | |
3793 | ||
3794 | i.operands = 0; | |
3795 | } | |
3796 | ||
c0f3af97 | 3797 | /* These AMD 3DNow! and SSE2 instructions have an opcode suffix |
65da13b5 L |
3798 | which is coded in the same place as an 8-bit immediate field |
3799 | would be. Here we fake an 8-bit immediate operand from the | |
3800 | opcode suffix stored in tm.extension_opcode. | |
3801 | ||
c1e679ec | 3802 | AVX instructions also use this encoding, for some of |
c0f3af97 | 3803 | 3 argument instructions. */ |
65da13b5 | 3804 | |
43234a1e | 3805 | gas_assert (i.imm_operands <= 1 |
7ab9ffdd | 3806 | && (i.operands <= 2 |
7a8655d2 | 3807 | || (is_any_vex_encoding (&i.tm) |
7ab9ffdd | 3808 | && i.operands <= 4))); |
65da13b5 L |
3809 | |
3810 | exp = &im_expressions[i.imm_operands++]; | |
3811 | i.op[i.operands].imms = exp; | |
3812 | i.types[i.operands] = imm8; | |
3813 | i.operands++; | |
3814 | exp->X_op = O_constant; | |
3815 | exp->X_add_number = i.tm.extension_opcode; | |
3816 | i.tm.extension_opcode = None; | |
3817 | } | |
3818 | ||
42164a71 L |
3819 | |
3820 | static int | |
3821 | check_hle (void) | |
3822 | { | |
3823 | switch (i.tm.opcode_modifier.hleprefixok) | |
3824 | { | |
3825 | default: | |
3826 | abort (); | |
82c2def5 | 3827 | case HLEPrefixNone: |
165de32a L |
3828 | as_bad (_("invalid instruction `%s' after `%s'"), |
3829 | i.tm.name, i.hle_prefix); | |
42164a71 | 3830 | return 0; |
82c2def5 | 3831 | case HLEPrefixLock: |
42164a71 L |
3832 | if (i.prefix[LOCK_PREFIX]) |
3833 | return 1; | |
165de32a | 3834 | as_bad (_("missing `lock' with `%s'"), i.hle_prefix); |
42164a71 | 3835 | return 0; |
82c2def5 | 3836 | case HLEPrefixAny: |
42164a71 | 3837 | return 1; |
82c2def5 | 3838 | case HLEPrefixRelease: |
42164a71 L |
3839 | if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE) |
3840 | { | |
3841 | as_bad (_("instruction `%s' after `xacquire' not allowed"), | |
3842 | i.tm.name); | |
3843 | return 0; | |
3844 | } | |
3845 | if (i.mem_operands == 0 | |
3846 | || !operand_type_check (i.types[i.operands - 1], anymem)) | |
3847 | { | |
3848 | as_bad (_("memory destination needed for instruction `%s'" | |
3849 | " after `xrelease'"), i.tm.name); | |
3850 | return 0; | |
3851 | } | |
3852 | return 1; | |
3853 | } | |
3854 | } | |
3855 | ||
b6f8c7c4 L |
3856 | /* Try the shortest encoding by shortening operand size. */ |
3857 | ||
3858 | static void | |
3859 | optimize_encoding (void) | |
3860 | { | |
3861 | int j; | |
3862 | ||
3863 | if (optimize_for_space | |
3864 | && i.reg_operands == 1 | |
3865 | && i.imm_operands == 1 | |
3866 | && !i.types[1].bitfield.byte | |
3867 | && i.op[0].imms->X_op == O_constant | |
3868 | && fits_in_imm7 (i.op[0].imms->X_add_number) | |
3869 | && ((i.tm.base_opcode == 0xa8 | |
3870 | && i.tm.extension_opcode == None) | |
3871 | || (i.tm.base_opcode == 0xf6 | |
3872 | && i.tm.extension_opcode == 0x0))) | |
3873 | { | |
3874 | /* Optimize: -Os: | |
3875 | test $imm7, %r64/%r32/%r16 -> test $imm7, %r8 | |
3876 | */ | |
3877 | unsigned int base_regnum = i.op[1].regs->reg_num; | |
3878 | if (flag_code == CODE_64BIT || base_regnum < 4) | |
3879 | { | |
3880 | i.types[1].bitfield.byte = 1; | |
3881 | /* Ignore the suffix. */ | |
3882 | i.suffix = 0; | |
3883 | if (base_regnum >= 4 | |
3884 | && !(i.op[1].regs->reg_flags & RegRex)) | |
3885 | { | |
3886 | /* Handle SP, BP, SI and DI registers. */ | |
3887 | if (i.types[1].bitfield.word) | |
3888 | j = 16; | |
3889 | else if (i.types[1].bitfield.dword) | |
3890 | j = 32; | |
3891 | else | |
3892 | j = 48; | |
3893 | i.op[1].regs -= j; | |
3894 | } | |
3895 | } | |
3896 | } | |
3897 | else if (flag_code == CODE_64BIT | |
d3d50934 L |
3898 | && ((i.types[1].bitfield.qword |
3899 | && i.reg_operands == 1 | |
b6f8c7c4 L |
3900 | && i.imm_operands == 1 |
3901 | && i.op[0].imms->X_op == O_constant | |
3902 | && ((i.tm.base_opcode == 0xb0 | |
3903 | && i.tm.extension_opcode == None | |
3904 | && fits_in_unsigned_long (i.op[0].imms->X_add_number)) | |
3905 | || (fits_in_imm31 (i.op[0].imms->X_add_number) | |
3906 | && (((i.tm.base_opcode == 0x24 | |
3907 | || i.tm.base_opcode == 0xa8) | |
3908 | && i.tm.extension_opcode == None) | |
3909 | || (i.tm.base_opcode == 0x80 | |
3910 | && i.tm.extension_opcode == 0x4) | |
3911 | || ((i.tm.base_opcode == 0xf6 | |
3912 | || i.tm.base_opcode == 0xc6) | |
3913 | && i.tm.extension_opcode == 0x0))))) | |
d3d50934 L |
3914 | || (i.types[0].bitfield.qword |
3915 | && ((i.reg_operands == 2 | |
3916 | && i.op[0].regs == i.op[1].regs | |
3917 | && ((i.tm.base_opcode == 0x30 | |
3918 | || i.tm.base_opcode == 0x28) | |
3919 | && i.tm.extension_opcode == None)) | |
3920 | || (i.reg_operands == 1 | |
3921 | && i.operands == 1 | |
3922 | && i.tm.base_opcode == 0x30 | |
3923 | && i.tm.extension_opcode == None))))) | |
b6f8c7c4 L |
3924 | { |
3925 | /* Optimize: -O: | |
3926 | andq $imm31, %r64 -> andl $imm31, %r32 | |
3927 | testq $imm31, %r64 -> testl $imm31, %r32 | |
3928 | xorq %r64, %r64 -> xorl %r32, %r32 | |
3929 | subq %r64, %r64 -> subl %r32, %r32 | |
3930 | movq $imm31, %r64 -> movl $imm31, %r32 | |
3931 | movq $imm32, %r64 -> movl $imm32, %r32 | |
3932 | */ | |
3933 | i.tm.opcode_modifier.norex64 = 1; | |
3934 | if (i.tm.base_opcode == 0xb0 || i.tm.base_opcode == 0xc6) | |
3935 | { | |
3936 | /* Handle | |
3937 | movq $imm31, %r64 -> movl $imm31, %r32 | |
3938 | movq $imm32, %r64 -> movl $imm32, %r32 | |
3939 | */ | |
3940 | i.tm.operand_types[0].bitfield.imm32 = 1; | |
3941 | i.tm.operand_types[0].bitfield.imm32s = 0; | |
3942 | i.tm.operand_types[0].bitfield.imm64 = 0; | |
3943 | i.types[0].bitfield.imm32 = 1; | |
3944 | i.types[0].bitfield.imm32s = 0; | |
3945 | i.types[0].bitfield.imm64 = 0; | |
3946 | i.types[1].bitfield.dword = 1; | |
3947 | i.types[1].bitfield.qword = 0; | |
3948 | if (i.tm.base_opcode == 0xc6) | |
3949 | { | |
3950 | /* Handle | |
3951 | movq $imm31, %r64 -> movl $imm31, %r32 | |
3952 | */ | |
3953 | i.tm.base_opcode = 0xb0; | |
3954 | i.tm.extension_opcode = None; | |
3955 | i.tm.opcode_modifier.shortform = 1; | |
3956 | i.tm.opcode_modifier.modrm = 0; | |
3957 | } | |
3958 | } | |
3959 | } | |
3960 | else if (optimize > 1 | |
3961 | && i.reg_operands == 3 | |
3962 | && i.op[0].regs == i.op[1].regs | |
3963 | && !i.types[2].bitfield.xmmword | |
3964 | && (i.tm.opcode_modifier.vex | |
7a69eac3 | 3965 | || ((!i.mask || i.mask->zeroing) |
b6f8c7c4 | 3966 | && !i.rounding |
e771e7c9 | 3967 | && is_evex_encoding (&i.tm) |
80c34c38 L |
3968 | && (i.vec_encoding != vex_encoding_evex |
3969 | || i.tm.cpu_flags.bitfield.cpuavx512vl | |
7091c612 JB |
3970 | || (i.tm.operand_types[2].bitfield.zmmword |
3971 | && i.types[2].bitfield.ymmword) | |
0089dace | 3972 | || cpu_arch_isa_flags.bitfield.cpuavx512vl))) |
b6f8c7c4 L |
3973 | && ((i.tm.base_opcode == 0x55 |
3974 | || i.tm.base_opcode == 0x6655 | |
3975 | || i.tm.base_opcode == 0x66df | |
3976 | || i.tm.base_opcode == 0x57 | |
3977 | || i.tm.base_opcode == 0x6657 | |
8305403a L |
3978 | || i.tm.base_opcode == 0x66ef |
3979 | || i.tm.base_opcode == 0x66f8 | |
3980 | || i.tm.base_opcode == 0x66f9 | |
3981 | || i.tm.base_opcode == 0x66fa | |
1424ad86 JB |
3982 | || i.tm.base_opcode == 0x66fb |
3983 | || i.tm.base_opcode == 0x42 | |
3984 | || i.tm.base_opcode == 0x6642 | |
3985 | || i.tm.base_opcode == 0x47 | |
3986 | || i.tm.base_opcode == 0x6647) | |
b6f8c7c4 L |
3987 | && i.tm.extension_opcode == None)) |
3988 | { | |
3989 | /* Optimize: -O2: | |
8305403a L |
3990 | VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd, |
3991 | vpsubq and vpsubw: | |
b6f8c7c4 L |
3992 | EVEX VOP %zmmM, %zmmM, %zmmN |
3993 | -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16) | |
3994 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) | |
3995 | EVEX VOP %ymmM, %ymmM, %ymmN | |
3996 | -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16) | |
3997 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) | |
3998 | VEX VOP %ymmM, %ymmM, %ymmN | |
3999 | -> VEX VOP %xmmM, %xmmM, %xmmN | |
4000 | VOP, one of vpandn and vpxor: | |
4001 | VEX VOP %ymmM, %ymmM, %ymmN | |
4002 | -> VEX VOP %xmmM, %xmmM, %xmmN | |
4003 | VOP, one of vpandnd and vpandnq: | |
4004 | EVEX VOP %zmmM, %zmmM, %zmmN | |
4005 | -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16) | |
4006 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) | |
4007 | EVEX VOP %ymmM, %ymmM, %ymmN | |
4008 | -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16) | |
4009 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) | |
4010 | VOP, one of vpxord and vpxorq: | |
4011 | EVEX VOP %zmmM, %zmmM, %zmmN | |
4012 | -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16) | |
4013 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) | |
4014 | EVEX VOP %ymmM, %ymmM, %ymmN | |
4015 | -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16) | |
4016 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) | |
1424ad86 JB |
4017 | VOP, one of kxord and kxorq: |
4018 | VEX VOP %kM, %kM, %kN | |
4019 | -> VEX kxorw %kM, %kM, %kN | |
4020 | VOP, one of kandnd and kandnq: | |
4021 | VEX VOP %kM, %kM, %kN | |
4022 | -> VEX kandnw %kM, %kM, %kN | |
b6f8c7c4 | 4023 | */ |
e771e7c9 | 4024 | if (is_evex_encoding (&i.tm)) |
b6f8c7c4 | 4025 | { |
0089dace | 4026 | if (i.vec_encoding == vex_encoding_evex) |
b6f8c7c4 L |
4027 | i.tm.opcode_modifier.evex = EVEX128; |
4028 | else | |
4029 | { | |
4030 | i.tm.opcode_modifier.vex = VEX128; | |
4031 | i.tm.opcode_modifier.vexw = VEXW0; | |
4032 | i.tm.opcode_modifier.evex = 0; | |
4033 | } | |
4034 | } | |
1424ad86 JB |
4035 | else if (i.tm.operand_types[0].bitfield.regmask) |
4036 | { | |
4037 | i.tm.base_opcode &= 0xff; | |
4038 | i.tm.opcode_modifier.vexw = VEXW0; | |
4039 | } | |
b6f8c7c4 L |
4040 | else |
4041 | i.tm.opcode_modifier.vex = VEX128; | |
4042 | ||
4043 | if (i.tm.opcode_modifier.vex) | |
4044 | for (j = 0; j < 3; j++) | |
4045 | { | |
4046 | i.types[j].bitfield.xmmword = 1; | |
4047 | i.types[j].bitfield.ymmword = 0; | |
4048 | } | |
4049 | } | |
4050 | } | |
4051 | ||
252b5132 RH |
4052 | /* This is the guts of the machine-dependent assembler. LINE points to a |
4053 | machine dependent instruction. This function is supposed to emit | |
4054 | the frags/bytes it assembles to. */ | |
4055 | ||
4056 | void | |
65da13b5 | 4057 | md_assemble (char *line) |
252b5132 | 4058 | { |
40fb9820 | 4059 | unsigned int j; |
83b16ac6 | 4060 | char mnemonic[MAX_MNEM_SIZE], mnem_suffix; |
d3ce72d0 | 4061 | const insn_template *t; |
252b5132 | 4062 | |
47926f60 | 4063 | /* Initialize globals. */ |
252b5132 RH |
4064 | memset (&i, '\0', sizeof (i)); |
4065 | for (j = 0; j < MAX_OPERANDS; j++) | |
1ae12ab7 | 4066 | i.reloc[j] = NO_RELOC; |
252b5132 RH |
4067 | memset (disp_expressions, '\0', sizeof (disp_expressions)); |
4068 | memset (im_expressions, '\0', sizeof (im_expressions)); | |
ce8a8b2f | 4069 | save_stack_p = save_stack; |
252b5132 RH |
4070 | |
4071 | /* First parse an instruction mnemonic & call i386_operand for the operands. | |
4072 | We assume that the scrubber has arranged it so that line[0] is the valid | |
47926f60 | 4073 | start of a (possibly prefixed) mnemonic. */ |
252b5132 | 4074 | |
29b0f896 AM |
4075 | line = parse_insn (line, mnemonic); |
4076 | if (line == NULL) | |
4077 | return; | |
83b16ac6 | 4078 | mnem_suffix = i.suffix; |
252b5132 | 4079 | |
29b0f896 | 4080 | line = parse_operands (line, mnemonic); |
ee86248c | 4081 | this_operand = -1; |
8325cc63 JB |
4082 | xfree (i.memop1_string); |
4083 | i.memop1_string = NULL; | |
29b0f896 AM |
4084 | if (line == NULL) |
4085 | return; | |
252b5132 | 4086 | |
29b0f896 AM |
4087 | /* Now we've parsed the mnemonic into a set of templates, and have the |
4088 | operands at hand. */ | |
4089 | ||
4090 | /* All intel opcodes have reversed operands except for "bound" and | |
4091 | "enter". We also don't reverse intersegment "jmp" and "call" | |
4092 | instructions with 2 immediate operands so that the immediate segment | |
050dfa73 | 4093 | precedes the offset, as it does when in AT&T mode. */ |
4d456e3d L |
4094 | if (intel_syntax |
4095 | && i.operands > 1 | |
29b0f896 | 4096 | && (strcmp (mnemonic, "bound") != 0) |
30123838 | 4097 | && (strcmp (mnemonic, "invlpga") != 0) |
40fb9820 L |
4098 | && !(operand_type_check (i.types[0], imm) |
4099 | && operand_type_check (i.types[1], imm))) | |
29b0f896 AM |
4100 | swap_operands (); |
4101 | ||
ec56d5c0 JB |
4102 | /* The order of the immediates should be reversed |
4103 | for 2 immediates extrq and insertq instructions */ | |
4104 | if (i.imm_operands == 2 | |
4105 | && (strcmp (mnemonic, "extrq") == 0 | |
4106 | || strcmp (mnemonic, "insertq") == 0)) | |
4107 | swap_2_operands (0, 1); | |
4108 | ||
29b0f896 AM |
4109 | if (i.imm_operands) |
4110 | optimize_imm (); | |
4111 | ||
b300c311 L |
4112 | /* Don't optimize displacement for movabs since it only takes 64bit |
4113 | displacement. */ | |
4114 | if (i.disp_operands | |
a501d77e | 4115 | && i.disp_encoding != disp_encoding_32bit |
862be3fb L |
4116 | && (flag_code != CODE_64BIT |
4117 | || strcmp (mnemonic, "movabs") != 0)) | |
4118 | optimize_disp (); | |
29b0f896 AM |
4119 | |
4120 | /* Next, we find a template that matches the given insn, | |
4121 | making sure the overlap of the given operands types is consistent | |
4122 | with the template operand types. */ | |
252b5132 | 4123 | |
83b16ac6 | 4124 | if (!(t = match_template (mnem_suffix))) |
29b0f896 | 4125 | return; |
252b5132 | 4126 | |
7bab8ab5 | 4127 | if (sse_check != check_none |
81f8a913 | 4128 | && !i.tm.opcode_modifier.noavx |
6e3e5c9e | 4129 | && !i.tm.cpu_flags.bitfield.cpuavx |
daf50ae7 L |
4130 | && (i.tm.cpu_flags.bitfield.cpusse |
4131 | || i.tm.cpu_flags.bitfield.cpusse2 | |
4132 | || i.tm.cpu_flags.bitfield.cpusse3 | |
4133 | || i.tm.cpu_flags.bitfield.cpussse3 | |
4134 | || i.tm.cpu_flags.bitfield.cpusse4_1 | |
6e3e5c9e JB |
4135 | || i.tm.cpu_flags.bitfield.cpusse4_2 |
4136 | || i.tm.cpu_flags.bitfield.cpupclmul | |
4137 | || i.tm.cpu_flags.bitfield.cpuaes | |
4138 | || i.tm.cpu_flags.bitfield.cpugfni)) | |
daf50ae7 | 4139 | { |
7bab8ab5 | 4140 | (sse_check == check_warning |
daf50ae7 L |
4141 | ? as_warn |
4142 | : as_bad) (_("SSE instruction `%s' is used"), i.tm.name); | |
4143 | } | |
4144 | ||
321fd21e L |
4145 | /* Zap movzx and movsx suffix. The suffix has been set from |
4146 | "word ptr" or "byte ptr" on the source operand in Intel syntax | |
4147 | or extracted from mnemonic in AT&T syntax. But we'll use | |
4148 | the destination register to choose the suffix for encoding. */ | |
4149 | if ((i.tm.base_opcode & ~9) == 0x0fb6) | |
cd61ebfe | 4150 | { |
321fd21e L |
4151 | /* In Intel syntax, there must be a suffix. In AT&T syntax, if |
4152 | there is no suffix, the default will be byte extension. */ | |
4153 | if (i.reg_operands != 2 | |
4154 | && !i.suffix | |
7ab9ffdd | 4155 | && intel_syntax) |
321fd21e L |
4156 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); |
4157 | ||
4158 | i.suffix = 0; | |
cd61ebfe | 4159 | } |
24eab124 | 4160 | |
40fb9820 | 4161 | if (i.tm.opcode_modifier.fwait) |
29b0f896 AM |
4162 | if (!add_prefix (FWAIT_OPCODE)) |
4163 | return; | |
252b5132 | 4164 | |
d5de92cf L |
4165 | /* Check if REP prefix is OK. */ |
4166 | if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok) | |
4167 | { | |
4168 | as_bad (_("invalid instruction `%s' after `%s'"), | |
4169 | i.tm.name, i.rep_prefix); | |
4170 | return; | |
4171 | } | |
4172 | ||
c1ba0266 L |
4173 | /* Check for lock without a lockable instruction. Destination operand |
4174 | must be memory unless it is xchg (0x86). */ | |
c32fa91d L |
4175 | if (i.prefix[LOCK_PREFIX] |
4176 | && (!i.tm.opcode_modifier.islockable | |
c1ba0266 L |
4177 | || i.mem_operands == 0 |
4178 | || (i.tm.base_opcode != 0x86 | |
4179 | && !operand_type_check (i.types[i.operands - 1], anymem)))) | |
c32fa91d L |
4180 | { |
4181 | as_bad (_("expecting lockable instruction after `lock'")); | |
4182 | return; | |
4183 | } | |
4184 | ||
7a8655d2 JB |
4185 | /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */ |
4186 | if (i.prefix[DATA_PREFIX] && is_any_vex_encoding (&i.tm)) | |
4187 | { | |
4188 | as_bad (_("data size prefix invalid with `%s'"), i.tm.name); | |
4189 | return; | |
4190 | } | |
4191 | ||
42164a71 | 4192 | /* Check if HLE prefix is OK. */ |
165de32a | 4193 | if (i.hle_prefix && !check_hle ()) |
42164a71 L |
4194 | return; |
4195 | ||
7e8b059b L |
4196 | /* Check BND prefix. */ |
4197 | if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok) | |
4198 | as_bad (_("expecting valid branch instruction after `bnd'")); | |
4199 | ||
04ef582a | 4200 | /* Check NOTRACK prefix. */ |
9fef80d6 L |
4201 | if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok) |
4202 | as_bad (_("expecting indirect branch instruction after `notrack'")); | |
04ef582a | 4203 | |
327e8c42 JB |
4204 | if (i.tm.cpu_flags.bitfield.cpumpx) |
4205 | { | |
4206 | if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX]) | |
4207 | as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions.")); | |
4208 | else if (flag_code != CODE_16BIT | |
4209 | ? i.prefix[ADDR_PREFIX] | |
4210 | : i.mem_operands && !i.prefix[ADDR_PREFIX]) | |
4211 | as_bad (_("16-bit address isn't allowed in MPX instructions")); | |
4212 | } | |
7e8b059b L |
4213 | |
4214 | /* Insert BND prefix. */ | |
76d3a78a JB |
4215 | if (add_bnd_prefix && i.tm.opcode_modifier.bndprefixok) |
4216 | { | |
4217 | if (!i.prefix[BND_PREFIX]) | |
4218 | add_prefix (BND_PREFIX_OPCODE); | |
4219 | else if (i.prefix[BND_PREFIX] != BND_PREFIX_OPCODE) | |
4220 | { | |
4221 | as_warn (_("replacing `rep'/`repe' prefix by `bnd'")); | |
4222 | i.prefix[BND_PREFIX] = BND_PREFIX_OPCODE; | |
4223 | } | |
4224 | } | |
7e8b059b | 4225 | |
29b0f896 | 4226 | /* Check string instruction segment overrides. */ |
40fb9820 | 4227 | if (i.tm.opcode_modifier.isstring && i.mem_operands != 0) |
29b0f896 AM |
4228 | { |
4229 | if (!check_string ()) | |
5dd0794d | 4230 | return; |
fc0763e6 | 4231 | i.disp_operands = 0; |
29b0f896 | 4232 | } |
5dd0794d | 4233 | |
b6f8c7c4 L |
4234 | if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize) |
4235 | optimize_encoding (); | |
4236 | ||
29b0f896 AM |
4237 | if (!process_suffix ()) |
4238 | return; | |
e413e4e9 | 4239 | |
bc0844ae L |
4240 | /* Update operand types. */ |
4241 | for (j = 0; j < i.operands; j++) | |
4242 | i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]); | |
4243 | ||
29b0f896 AM |
4244 | /* Make still unresolved immediate matches conform to size of immediate |
4245 | given in i.suffix. */ | |
4246 | if (!finalize_imm ()) | |
4247 | return; | |
252b5132 | 4248 | |
40fb9820 | 4249 | if (i.types[0].bitfield.imm1) |
29b0f896 | 4250 | i.imm_operands = 0; /* kludge for shift insns. */ |
252b5132 | 4251 | |
9afe6eb8 L |
4252 | /* We only need to check those implicit registers for instructions |
4253 | with 3 operands or less. */ | |
4254 | if (i.operands <= 3) | |
4255 | for (j = 0; j < i.operands; j++) | |
4256 | if (i.types[j].bitfield.inoutportreg | |
4257 | || i.types[j].bitfield.shiftcount | |
1b54b8d7 | 4258 | || (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword)) |
9afe6eb8 | 4259 | i.reg_operands--; |
40fb9820 | 4260 | |
c0f3af97 L |
4261 | /* ImmExt should be processed after SSE2AVX. */ |
4262 | if (!i.tm.opcode_modifier.sse2avx | |
4263 | && i.tm.opcode_modifier.immext) | |
65da13b5 | 4264 | process_immext (); |
252b5132 | 4265 | |
29b0f896 AM |
4266 | /* For insns with operands there are more diddles to do to the opcode. */ |
4267 | if (i.operands) | |
4268 | { | |
4269 | if (!process_operands ()) | |
4270 | return; | |
4271 | } | |
40fb9820 | 4272 | else if (!quiet_warnings && i.tm.opcode_modifier.ugh) |
29b0f896 AM |
4273 | { |
4274 | /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ | |
4275 | as_warn (_("translating to `%sp'"), i.tm.name); | |
4276 | } | |
252b5132 | 4277 | |
7a8655d2 | 4278 | if (is_any_vex_encoding (&i.tm)) |
9e5e5283 L |
4279 | { |
4280 | if (flag_code == CODE_16BIT) | |
4281 | { | |
4282 | as_bad (_("instruction `%s' isn't supported in 16-bit mode."), | |
4283 | i.tm.name); | |
4284 | return; | |
4285 | } | |
c0f3af97 | 4286 | |
9e5e5283 L |
4287 | if (i.tm.opcode_modifier.vex) |
4288 | build_vex_prefix (t); | |
4289 | else | |
4290 | build_evex_prefix (); | |
4291 | } | |
43234a1e | 4292 | |
5dd85c99 SP |
4293 | /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4 |
4294 | instructions may define INT_OPCODE as well, so avoid this corner | |
4295 | case for those instructions that use MODRM. */ | |
4296 | if (i.tm.base_opcode == INT_OPCODE | |
a6461c02 SP |
4297 | && !i.tm.opcode_modifier.modrm |
4298 | && i.op[0].imms->X_add_number == 3) | |
29b0f896 AM |
4299 | { |
4300 | i.tm.base_opcode = INT3_OPCODE; | |
4301 | i.imm_operands = 0; | |
4302 | } | |
252b5132 | 4303 | |
40fb9820 L |
4304 | if ((i.tm.opcode_modifier.jump |
4305 | || i.tm.opcode_modifier.jumpbyte | |
4306 | || i.tm.opcode_modifier.jumpdword) | |
29b0f896 AM |
4307 | && i.op[0].disps->X_op == O_constant) |
4308 | { | |
4309 | /* Convert "jmp constant" (and "call constant") to a jump (call) to | |
4310 | the absolute address given by the constant. Since ix86 jumps and | |
4311 | calls are pc relative, we need to generate a reloc. */ | |
4312 | i.op[0].disps->X_add_symbol = &abs_symbol; | |
4313 | i.op[0].disps->X_op = O_symbol; | |
4314 | } | |
252b5132 | 4315 | |
40fb9820 | 4316 | if (i.tm.opcode_modifier.rex64) |
161a04f6 | 4317 | i.rex |= REX_W; |
252b5132 | 4318 | |
29b0f896 AM |
4319 | /* For 8 bit registers we need an empty rex prefix. Also if the |
4320 | instruction already has a prefix, we need to convert old | |
4321 | registers to new ones. */ | |
773f551c | 4322 | |
dc821c5f | 4323 | if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte |
29b0f896 | 4324 | && (i.op[0].regs->reg_flags & RegRex64) != 0) |
dc821c5f | 4325 | || (i.types[1].bitfield.reg && i.types[1].bitfield.byte |
29b0f896 | 4326 | && (i.op[1].regs->reg_flags & RegRex64) != 0) |
dc821c5f JB |
4327 | || (((i.types[0].bitfield.reg && i.types[0].bitfield.byte) |
4328 | || (i.types[1].bitfield.reg && i.types[1].bitfield.byte)) | |
29b0f896 AM |
4329 | && i.rex != 0)) |
4330 | { | |
4331 | int x; | |
726c5dcd | 4332 | |
29b0f896 AM |
4333 | i.rex |= REX_OPCODE; |
4334 | for (x = 0; x < 2; x++) | |
4335 | { | |
4336 | /* Look for 8 bit operand that uses old registers. */ | |
dc821c5f | 4337 | if (i.types[x].bitfield.reg && i.types[x].bitfield.byte |
29b0f896 | 4338 | && (i.op[x].regs->reg_flags & RegRex64) == 0) |
773f551c | 4339 | { |
29b0f896 AM |
4340 | /* In case it is "hi" register, give up. */ |
4341 | if (i.op[x].regs->reg_num > 3) | |
a540244d | 4342 | as_bad (_("can't encode register '%s%s' in an " |
4eed87de | 4343 | "instruction requiring REX prefix."), |
a540244d | 4344 | register_prefix, i.op[x].regs->reg_name); |
773f551c | 4345 | |
29b0f896 AM |
4346 | /* Otherwise it is equivalent to the extended register. |
4347 | Since the encoding doesn't change this is merely | |
4348 | cosmetic cleanup for debug output. */ | |
4349 | ||
4350 | i.op[x].regs = i.op[x].regs + 8; | |
773f551c | 4351 | } |
29b0f896 AM |
4352 | } |
4353 | } | |
773f551c | 4354 | |
6b6b6807 L |
4355 | if (i.rex == 0 && i.rex_encoding) |
4356 | { | |
4357 | /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand | |
4358 | that uses legacy register. If it is "hi" register, don't add | |
4359 | the REX_OPCODE byte. */ | |
4360 | int x; | |
4361 | for (x = 0; x < 2; x++) | |
4362 | if (i.types[x].bitfield.reg | |
4363 | && i.types[x].bitfield.byte | |
4364 | && (i.op[x].regs->reg_flags & RegRex64) == 0 | |
4365 | && i.op[x].regs->reg_num > 3) | |
4366 | { | |
4367 | i.rex_encoding = FALSE; | |
4368 | break; | |
4369 | } | |
4370 | ||
4371 | if (i.rex_encoding) | |
4372 | i.rex = REX_OPCODE; | |
4373 | } | |
4374 | ||
7ab9ffdd | 4375 | if (i.rex != 0) |
29b0f896 AM |
4376 | add_prefix (REX_OPCODE | i.rex); |
4377 | ||
4378 | /* We are ready to output the insn. */ | |
4379 | output_insn (); | |
4380 | } | |
4381 | ||
4382 | static char * | |
e3bb37b5 | 4383 | parse_insn (char *line, char *mnemonic) |
29b0f896 AM |
4384 | { |
4385 | char *l = line; | |
4386 | char *token_start = l; | |
4387 | char *mnem_p; | |
5c6af06e | 4388 | int supported; |
d3ce72d0 | 4389 | const insn_template *t; |
b6169b20 | 4390 | char *dot_p = NULL; |
29b0f896 | 4391 | |
29b0f896 AM |
4392 | while (1) |
4393 | { | |
4394 | mnem_p = mnemonic; | |
4395 | while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) | |
4396 | { | |
b6169b20 L |
4397 | if (*mnem_p == '.') |
4398 | dot_p = mnem_p; | |
29b0f896 AM |
4399 | mnem_p++; |
4400 | if (mnem_p >= mnemonic + MAX_MNEM_SIZE) | |
45288df1 | 4401 | { |
29b0f896 AM |
4402 | as_bad (_("no such instruction: `%s'"), token_start); |
4403 | return NULL; | |
4404 | } | |
4405 | l++; | |
4406 | } | |
4407 | if (!is_space_char (*l) | |
4408 | && *l != END_OF_INSN | |
e44823cf JB |
4409 | && (intel_syntax |
4410 | || (*l != PREFIX_SEPARATOR | |
4411 | && *l != ','))) | |
29b0f896 AM |
4412 | { |
4413 | as_bad (_("invalid character %s in mnemonic"), | |
4414 | output_invalid (*l)); | |
4415 | return NULL; | |
4416 | } | |
4417 | if (token_start == l) | |
4418 | { | |
e44823cf | 4419 | if (!intel_syntax && *l == PREFIX_SEPARATOR) |
29b0f896 AM |
4420 | as_bad (_("expecting prefix; got nothing")); |
4421 | else | |
4422 | as_bad (_("expecting mnemonic; got nothing")); | |
4423 | return NULL; | |
4424 | } | |
45288df1 | 4425 | |
29b0f896 | 4426 | /* Look up instruction (or prefix) via hash table. */ |
d3ce72d0 | 4427 | current_templates = (const templates *) hash_find (op_hash, mnemonic); |
47926f60 | 4428 | |
29b0f896 AM |
4429 | if (*l != END_OF_INSN |
4430 | && (!is_space_char (*l) || l[1] != END_OF_INSN) | |
4431 | && current_templates | |
40fb9820 | 4432 | && current_templates->start->opcode_modifier.isprefix) |
29b0f896 | 4433 | { |
c6fb90c8 | 4434 | if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags)) |
2dd88dca JB |
4435 | { |
4436 | as_bad ((flag_code != CODE_64BIT | |
4437 | ? _("`%s' is only supported in 64-bit mode") | |
4438 | : _("`%s' is not supported in 64-bit mode")), | |
4439 | current_templates->start->name); | |
4440 | return NULL; | |
4441 | } | |
29b0f896 AM |
4442 | /* If we are in 16-bit mode, do not allow addr16 or data16. |
4443 | Similarly, in 32-bit mode, do not allow addr32 or data32. */ | |
40fb9820 L |
4444 | if ((current_templates->start->opcode_modifier.size16 |
4445 | || current_templates->start->opcode_modifier.size32) | |
29b0f896 | 4446 | && flag_code != CODE_64BIT |
40fb9820 | 4447 | && (current_templates->start->opcode_modifier.size32 |
29b0f896 AM |
4448 | ^ (flag_code == CODE_16BIT))) |
4449 | { | |
4450 | as_bad (_("redundant %s prefix"), | |
4451 | current_templates->start->name); | |
4452 | return NULL; | |
45288df1 | 4453 | } |
86fa6981 | 4454 | if (current_templates->start->opcode_length == 0) |
29b0f896 | 4455 | { |
86fa6981 L |
4456 | /* Handle pseudo prefixes. */ |
4457 | switch (current_templates->start->base_opcode) | |
4458 | { | |
4459 | case 0x0: | |
4460 | /* {disp8} */ | |
4461 | i.disp_encoding = disp_encoding_8bit; | |
4462 | break; | |
4463 | case 0x1: | |
4464 | /* {disp32} */ | |
4465 | i.disp_encoding = disp_encoding_32bit; | |
4466 | break; | |
4467 | case 0x2: | |
4468 | /* {load} */ | |
4469 | i.dir_encoding = dir_encoding_load; | |
4470 | break; | |
4471 | case 0x3: | |
4472 | /* {store} */ | |
4473 | i.dir_encoding = dir_encoding_store; | |
4474 | break; | |
4475 | case 0x4: | |
4476 | /* {vex2} */ | |
4477 | i.vec_encoding = vex_encoding_vex2; | |
4478 | break; | |
4479 | case 0x5: | |
4480 | /* {vex3} */ | |
4481 | i.vec_encoding = vex_encoding_vex3; | |
4482 | break; | |
4483 | case 0x6: | |
4484 | /* {evex} */ | |
4485 | i.vec_encoding = vex_encoding_evex; | |
4486 | break; | |
6b6b6807 L |
4487 | case 0x7: |
4488 | /* {rex} */ | |
4489 | i.rex_encoding = TRUE; | |
4490 | break; | |
b6f8c7c4 L |
4491 | case 0x8: |
4492 | /* {nooptimize} */ | |
4493 | i.no_optimize = TRUE; | |
4494 | break; | |
86fa6981 L |
4495 | default: |
4496 | abort (); | |
4497 | } | |
4498 | } | |
4499 | else | |
4500 | { | |
4501 | /* Add prefix, checking for repeated prefixes. */ | |
4e9ac44a | 4502 | switch (add_prefix (current_templates->start->base_opcode)) |
86fa6981 | 4503 | { |
4e9ac44a L |
4504 | case PREFIX_EXIST: |
4505 | return NULL; | |
4506 | case PREFIX_DS: | |
d777820b | 4507 | if (current_templates->start->cpu_flags.bitfield.cpuibt) |
4e9ac44a L |
4508 | i.notrack_prefix = current_templates->start->name; |
4509 | break; | |
4510 | case PREFIX_REP: | |
4511 | if (current_templates->start->cpu_flags.bitfield.cpuhle) | |
4512 | i.hle_prefix = current_templates->start->name; | |
4513 | else if (current_templates->start->cpu_flags.bitfield.cpumpx) | |
4514 | i.bnd_prefix = current_templates->start->name; | |
4515 | else | |
4516 | i.rep_prefix = current_templates->start->name; | |
4517 | break; | |
4518 | default: | |
4519 | break; | |
86fa6981 | 4520 | } |
29b0f896 AM |
4521 | } |
4522 | /* Skip past PREFIX_SEPARATOR and reset token_start. */ | |
4523 | token_start = ++l; | |
4524 | } | |
4525 | else | |
4526 | break; | |
4527 | } | |
45288df1 | 4528 | |
30a55f88 | 4529 | if (!current_templates) |
b6169b20 | 4530 | { |
07d5e953 JB |
4531 | /* Deprecated functionality (new code should use pseudo-prefixes instead): |
4532 | Check if we should swap operand or force 32bit displacement in | |
f8a5c266 | 4533 | encoding. */ |
30a55f88 | 4534 | if (mnem_p - 2 == dot_p && dot_p[1] == 's') |
64c49ab3 | 4535 | i.dir_encoding = dir_encoding_swap; |
8d63c93e | 4536 | else if (mnem_p - 3 == dot_p |
a501d77e L |
4537 | && dot_p[1] == 'd' |
4538 | && dot_p[2] == '8') | |
4539 | i.disp_encoding = disp_encoding_8bit; | |
8d63c93e | 4540 | else if (mnem_p - 4 == dot_p |
f8a5c266 L |
4541 | && dot_p[1] == 'd' |
4542 | && dot_p[2] == '3' | |
4543 | && dot_p[3] == '2') | |
a501d77e | 4544 | i.disp_encoding = disp_encoding_32bit; |
30a55f88 L |
4545 | else |
4546 | goto check_suffix; | |
4547 | mnem_p = dot_p; | |
4548 | *dot_p = '\0'; | |
d3ce72d0 | 4549 | current_templates = (const templates *) hash_find (op_hash, mnemonic); |
b6169b20 L |
4550 | } |
4551 | ||
29b0f896 AM |
4552 | if (!current_templates) |
4553 | { | |
b6169b20 | 4554 | check_suffix: |
29b0f896 AM |
4555 | /* See if we can get a match by trimming off a suffix. */ |
4556 | switch (mnem_p[-1]) | |
4557 | { | |
4558 | case WORD_MNEM_SUFFIX: | |
9306ca4a JB |
4559 | if (intel_syntax && (intel_float_operand (mnemonic) & 2)) |
4560 | i.suffix = SHORT_MNEM_SUFFIX; | |
4561 | else | |
1a0670f3 | 4562 | /* Fall through. */ |
29b0f896 AM |
4563 | case BYTE_MNEM_SUFFIX: |
4564 | case QWORD_MNEM_SUFFIX: | |
4565 | i.suffix = mnem_p[-1]; | |
4566 | mnem_p[-1] = '\0'; | |
d3ce72d0 NC |
4567 | current_templates = (const templates *) hash_find (op_hash, |
4568 | mnemonic); | |
29b0f896 AM |
4569 | break; |
4570 | case SHORT_MNEM_SUFFIX: | |
4571 | case LONG_MNEM_SUFFIX: | |
4572 | if (!intel_syntax) | |
4573 | { | |
4574 | i.suffix = mnem_p[-1]; | |
4575 | mnem_p[-1] = '\0'; | |
d3ce72d0 NC |
4576 | current_templates = (const templates *) hash_find (op_hash, |
4577 | mnemonic); | |
29b0f896 AM |
4578 | } |
4579 | break; | |
252b5132 | 4580 | |
29b0f896 AM |
4581 | /* Intel Syntax. */ |
4582 | case 'd': | |
4583 | if (intel_syntax) | |
4584 | { | |
9306ca4a | 4585 | if (intel_float_operand (mnemonic) == 1) |
29b0f896 AM |
4586 | i.suffix = SHORT_MNEM_SUFFIX; |
4587 | else | |
4588 | i.suffix = LONG_MNEM_SUFFIX; | |
4589 | mnem_p[-1] = '\0'; | |
d3ce72d0 NC |
4590 | current_templates = (const templates *) hash_find (op_hash, |
4591 | mnemonic); | |
29b0f896 AM |
4592 | } |
4593 | break; | |
4594 | } | |
4595 | if (!current_templates) | |
4596 | { | |
4597 | as_bad (_("no such instruction: `%s'"), token_start); | |
4598 | return NULL; | |
4599 | } | |
4600 | } | |
252b5132 | 4601 | |
40fb9820 L |
4602 | if (current_templates->start->opcode_modifier.jump |
4603 | || current_templates->start->opcode_modifier.jumpbyte) | |
29b0f896 AM |
4604 | { |
4605 | /* Check for a branch hint. We allow ",pt" and ",pn" for | |
4606 | predict taken and predict not taken respectively. | |
4607 | I'm not sure that branch hints actually do anything on loop | |
4608 | and jcxz insns (JumpByte) for current Pentium4 chips. They | |
4609 | may work in the future and it doesn't hurt to accept them | |
4610 | now. */ | |
4611 | if (l[0] == ',' && l[1] == 'p') | |
4612 | { | |
4613 | if (l[2] == 't') | |
4614 | { | |
4615 | if (!add_prefix (DS_PREFIX_OPCODE)) | |
4616 | return NULL; | |
4617 | l += 3; | |
4618 | } | |
4619 | else if (l[2] == 'n') | |
4620 | { | |
4621 | if (!add_prefix (CS_PREFIX_OPCODE)) | |
4622 | return NULL; | |
4623 | l += 3; | |
4624 | } | |
4625 | } | |
4626 | } | |
4627 | /* Any other comma loses. */ | |
4628 | if (*l == ',') | |
4629 | { | |
4630 | as_bad (_("invalid character %s in mnemonic"), | |
4631 | output_invalid (*l)); | |
4632 | return NULL; | |
4633 | } | |
252b5132 | 4634 | |
29b0f896 | 4635 | /* Check if instruction is supported on specified architecture. */ |
5c6af06e JB |
4636 | supported = 0; |
4637 | for (t = current_templates->start; t < current_templates->end; ++t) | |
4638 | { | |
c0f3af97 L |
4639 | supported |= cpu_flags_match (t); |
4640 | if (supported == CPU_FLAGS_PERFECT_MATCH) | |
548d0ee6 JB |
4641 | { |
4642 | if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT)) | |
4643 | as_warn (_("use .code16 to ensure correct addressing mode")); | |
3629bb00 | 4644 | |
548d0ee6 JB |
4645 | return l; |
4646 | } | |
29b0f896 | 4647 | } |
3629bb00 | 4648 | |
548d0ee6 JB |
4649 | if (!(supported & CPU_FLAGS_64BIT_MATCH)) |
4650 | as_bad (flag_code == CODE_64BIT | |
4651 | ? _("`%s' is not supported in 64-bit mode") | |
4652 | : _("`%s' is only supported in 64-bit mode"), | |
4653 | current_templates->start->name); | |
4654 | else | |
4655 | as_bad (_("`%s' is not supported on `%s%s'"), | |
4656 | current_templates->start->name, | |
4657 | cpu_arch_name ? cpu_arch_name : default_arch, | |
4658 | cpu_sub_arch_name ? cpu_sub_arch_name : ""); | |
252b5132 | 4659 | |
548d0ee6 | 4660 | return NULL; |
29b0f896 | 4661 | } |
252b5132 | 4662 | |
29b0f896 | 4663 | static char * |
e3bb37b5 | 4664 | parse_operands (char *l, const char *mnemonic) |
29b0f896 AM |
4665 | { |
4666 | char *token_start; | |
3138f287 | 4667 | |
29b0f896 AM |
4668 | /* 1 if operand is pending after ','. */ |
4669 | unsigned int expecting_operand = 0; | |
252b5132 | 4670 | |
29b0f896 AM |
4671 | /* Non-zero if operand parens not balanced. */ |
4672 | unsigned int paren_not_balanced; | |
4673 | ||
4674 | while (*l != END_OF_INSN) | |
4675 | { | |
4676 | /* Skip optional white space before operand. */ | |
4677 | if (is_space_char (*l)) | |
4678 | ++l; | |
d02603dc | 4679 | if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"') |
29b0f896 AM |
4680 | { |
4681 | as_bad (_("invalid character %s before operand %d"), | |
4682 | output_invalid (*l), | |
4683 | i.operands + 1); | |
4684 | return NULL; | |
4685 | } | |
d02603dc | 4686 | token_start = l; /* After white space. */ |
29b0f896 AM |
4687 | paren_not_balanced = 0; |
4688 | while (paren_not_balanced || *l != ',') | |
4689 | { | |
4690 | if (*l == END_OF_INSN) | |
4691 | { | |
4692 | if (paren_not_balanced) | |
4693 | { | |
4694 | if (!intel_syntax) | |
4695 | as_bad (_("unbalanced parenthesis in operand %d."), | |
4696 | i.operands + 1); | |
4697 | else | |
4698 | as_bad (_("unbalanced brackets in operand %d."), | |
4699 | i.operands + 1); | |
4700 | return NULL; | |
4701 | } | |
4702 | else | |
4703 | break; /* we are done */ | |
4704 | } | |
d02603dc | 4705 | else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"') |
29b0f896 AM |
4706 | { |
4707 | as_bad (_("invalid character %s in operand %d"), | |
4708 | output_invalid (*l), | |
4709 | i.operands + 1); | |
4710 | return NULL; | |
4711 | } | |
4712 | if (!intel_syntax) | |
4713 | { | |
4714 | if (*l == '(') | |
4715 | ++paren_not_balanced; | |
4716 | if (*l == ')') | |
4717 | --paren_not_balanced; | |
4718 | } | |
4719 | else | |
4720 | { | |
4721 | if (*l == '[') | |
4722 | ++paren_not_balanced; | |
4723 | if (*l == ']') | |
4724 | --paren_not_balanced; | |
4725 | } | |
4726 | l++; | |
4727 | } | |
4728 | if (l != token_start) | |
4729 | { /* Yes, we've read in another operand. */ | |
4730 | unsigned int operand_ok; | |
4731 | this_operand = i.operands++; | |
4732 | if (i.operands > MAX_OPERANDS) | |
4733 | { | |
4734 | as_bad (_("spurious operands; (%d operands/instruction max)"), | |
4735 | MAX_OPERANDS); | |
4736 | return NULL; | |
4737 | } | |
9d46ce34 | 4738 | i.types[this_operand].bitfield.unspecified = 1; |
29b0f896 AM |
4739 | /* Now parse operand adding info to 'i' as we go along. */ |
4740 | END_STRING_AND_SAVE (l); | |
4741 | ||
1286ab78 L |
4742 | if (i.mem_operands > 1) |
4743 | { | |
4744 | as_bad (_("too many memory references for `%s'"), | |
4745 | mnemonic); | |
4746 | return 0; | |
4747 | } | |
4748 | ||
29b0f896 AM |
4749 | if (intel_syntax) |
4750 | operand_ok = | |
4751 | i386_intel_operand (token_start, | |
4752 | intel_float_operand (mnemonic)); | |
4753 | else | |
a7619375 | 4754 | operand_ok = i386_att_operand (token_start); |
29b0f896 AM |
4755 | |
4756 | RESTORE_END_STRING (l); | |
4757 | if (!operand_ok) | |
4758 | return NULL; | |
4759 | } | |
4760 | else | |
4761 | { | |
4762 | if (expecting_operand) | |
4763 | { | |
4764 | expecting_operand_after_comma: | |
4765 | as_bad (_("expecting operand after ','; got nothing")); | |
4766 | return NULL; | |
4767 | } | |
4768 | if (*l == ',') | |
4769 | { | |
4770 | as_bad (_("expecting operand before ','; got nothing")); | |
4771 | return NULL; | |
4772 | } | |
4773 | } | |
7f3f1ea2 | 4774 | |
29b0f896 AM |
4775 | /* Now *l must be either ',' or END_OF_INSN. */ |
4776 | if (*l == ',') | |
4777 | { | |
4778 | if (*++l == END_OF_INSN) | |
4779 | { | |
4780 | /* Just skip it, if it's \n complain. */ | |
4781 | goto expecting_operand_after_comma; | |
4782 | } | |
4783 | expecting_operand = 1; | |
4784 | } | |
4785 | } | |
4786 | return l; | |
4787 | } | |
7f3f1ea2 | 4788 | |
050dfa73 | 4789 | static void |
4d456e3d | 4790 | swap_2_operands (int xchg1, int xchg2) |
050dfa73 MM |
4791 | { |
4792 | union i386_op temp_op; | |
40fb9820 | 4793 | i386_operand_type temp_type; |
c48dadc9 | 4794 | unsigned int temp_flags; |
050dfa73 | 4795 | enum bfd_reloc_code_real temp_reloc; |
4eed87de | 4796 | |
050dfa73 MM |
4797 | temp_type = i.types[xchg2]; |
4798 | i.types[xchg2] = i.types[xchg1]; | |
4799 | i.types[xchg1] = temp_type; | |
c48dadc9 JB |
4800 | |
4801 | temp_flags = i.flags[xchg2]; | |
4802 | i.flags[xchg2] = i.flags[xchg1]; | |
4803 | i.flags[xchg1] = temp_flags; | |
4804 | ||
050dfa73 MM |
4805 | temp_op = i.op[xchg2]; |
4806 | i.op[xchg2] = i.op[xchg1]; | |
4807 | i.op[xchg1] = temp_op; | |
c48dadc9 | 4808 | |
050dfa73 MM |
4809 | temp_reloc = i.reloc[xchg2]; |
4810 | i.reloc[xchg2] = i.reloc[xchg1]; | |
4811 | i.reloc[xchg1] = temp_reloc; | |
43234a1e L |
4812 | |
4813 | if (i.mask) | |
4814 | { | |
4815 | if (i.mask->operand == xchg1) | |
4816 | i.mask->operand = xchg2; | |
4817 | else if (i.mask->operand == xchg2) | |
4818 | i.mask->operand = xchg1; | |
4819 | } | |
4820 | if (i.broadcast) | |
4821 | { | |
4822 | if (i.broadcast->operand == xchg1) | |
4823 | i.broadcast->operand = xchg2; | |
4824 | else if (i.broadcast->operand == xchg2) | |
4825 | i.broadcast->operand = xchg1; | |
4826 | } | |
4827 | if (i.rounding) | |
4828 | { | |
4829 | if (i.rounding->operand == xchg1) | |
4830 | i.rounding->operand = xchg2; | |
4831 | else if (i.rounding->operand == xchg2) | |
4832 | i.rounding->operand = xchg1; | |
4833 | } | |
050dfa73 MM |
4834 | } |
4835 | ||
29b0f896 | 4836 | static void |
e3bb37b5 | 4837 | swap_operands (void) |
29b0f896 | 4838 | { |
b7c61d9a | 4839 | switch (i.operands) |
050dfa73 | 4840 | { |
c0f3af97 | 4841 | case 5: |
b7c61d9a | 4842 | case 4: |
4d456e3d | 4843 | swap_2_operands (1, i.operands - 2); |
1a0670f3 | 4844 | /* Fall through. */ |
b7c61d9a L |
4845 | case 3: |
4846 | case 2: | |
4d456e3d | 4847 | swap_2_operands (0, i.operands - 1); |
b7c61d9a L |
4848 | break; |
4849 | default: | |
4850 | abort (); | |
29b0f896 | 4851 | } |
29b0f896 AM |
4852 | |
4853 | if (i.mem_operands == 2) | |
4854 | { | |
4855 | const seg_entry *temp_seg; | |
4856 | temp_seg = i.seg[0]; | |
4857 | i.seg[0] = i.seg[1]; | |
4858 | i.seg[1] = temp_seg; | |
4859 | } | |
4860 | } | |
252b5132 | 4861 | |
29b0f896 AM |
4862 | /* Try to ensure constant immediates are represented in the smallest |
4863 | opcode possible. */ | |
4864 | static void | |
e3bb37b5 | 4865 | optimize_imm (void) |
29b0f896 AM |
4866 | { |
4867 | char guess_suffix = 0; | |
4868 | int op; | |
252b5132 | 4869 | |
29b0f896 AM |
4870 | if (i.suffix) |
4871 | guess_suffix = i.suffix; | |
4872 | else if (i.reg_operands) | |
4873 | { | |
4874 | /* Figure out a suffix from the last register operand specified. | |
4875 | We can't do this properly yet, ie. excluding InOutPortReg, | |
4876 | but the following works for instructions with immediates. | |
4877 | In any case, we can't set i.suffix yet. */ | |
4878 | for (op = i.operands; --op >= 0;) | |
dc821c5f | 4879 | if (i.types[op].bitfield.reg && i.types[op].bitfield.byte) |
7ab9ffdd | 4880 | { |
40fb9820 L |
4881 | guess_suffix = BYTE_MNEM_SUFFIX; |
4882 | break; | |
4883 | } | |
dc821c5f | 4884 | else if (i.types[op].bitfield.reg && i.types[op].bitfield.word) |
252b5132 | 4885 | { |
40fb9820 L |
4886 | guess_suffix = WORD_MNEM_SUFFIX; |
4887 | break; | |
4888 | } | |
dc821c5f | 4889 | else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword) |
40fb9820 L |
4890 | { |
4891 | guess_suffix = LONG_MNEM_SUFFIX; | |
4892 | break; | |
4893 | } | |
dc821c5f | 4894 | else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword) |
40fb9820 L |
4895 | { |
4896 | guess_suffix = QWORD_MNEM_SUFFIX; | |
29b0f896 | 4897 | break; |
252b5132 | 4898 | } |
29b0f896 AM |
4899 | } |
4900 | else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) | |
4901 | guess_suffix = WORD_MNEM_SUFFIX; | |
4902 | ||
4903 | for (op = i.operands; --op >= 0;) | |
40fb9820 | 4904 | if (operand_type_check (i.types[op], imm)) |
29b0f896 AM |
4905 | { |
4906 | switch (i.op[op].imms->X_op) | |
252b5132 | 4907 | { |
29b0f896 AM |
4908 | case O_constant: |
4909 | /* If a suffix is given, this operand may be shortened. */ | |
4910 | switch (guess_suffix) | |
252b5132 | 4911 | { |
29b0f896 | 4912 | case LONG_MNEM_SUFFIX: |
40fb9820 L |
4913 | i.types[op].bitfield.imm32 = 1; |
4914 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
4915 | break; |
4916 | case WORD_MNEM_SUFFIX: | |
40fb9820 L |
4917 | i.types[op].bitfield.imm16 = 1; |
4918 | i.types[op].bitfield.imm32 = 1; | |
4919 | i.types[op].bitfield.imm32s = 1; | |
4920 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
4921 | break; |
4922 | case BYTE_MNEM_SUFFIX: | |
40fb9820 L |
4923 | i.types[op].bitfield.imm8 = 1; |
4924 | i.types[op].bitfield.imm8s = 1; | |
4925 | i.types[op].bitfield.imm16 = 1; | |
4926 | i.types[op].bitfield.imm32 = 1; | |
4927 | i.types[op].bitfield.imm32s = 1; | |
4928 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 | 4929 | break; |
252b5132 | 4930 | } |
252b5132 | 4931 | |
29b0f896 AM |
4932 | /* If this operand is at most 16 bits, convert it |
4933 | to a signed 16 bit number before trying to see | |
4934 | whether it will fit in an even smaller size. | |
4935 | This allows a 16-bit operand such as $0xffe0 to | |
4936 | be recognised as within Imm8S range. */ | |
40fb9820 | 4937 | if ((i.types[op].bitfield.imm16) |
29b0f896 | 4938 | && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0) |
252b5132 | 4939 | { |
29b0f896 AM |
4940 | i.op[op].imms->X_add_number = |
4941 | (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000); | |
4942 | } | |
a28def75 L |
4943 | #ifdef BFD64 |
4944 | /* Store 32-bit immediate in 64-bit for 64-bit BFD. */ | |
40fb9820 | 4945 | if ((i.types[op].bitfield.imm32) |
29b0f896 AM |
4946 | && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1)) |
4947 | == 0)) | |
4948 | { | |
4949 | i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number | |
4950 | ^ ((offsetT) 1 << 31)) | |
4951 | - ((offsetT) 1 << 31)); | |
4952 | } | |
a28def75 | 4953 | #endif |
40fb9820 | 4954 | i.types[op] |
c6fb90c8 L |
4955 | = operand_type_or (i.types[op], |
4956 | smallest_imm_type (i.op[op].imms->X_add_number)); | |
252b5132 | 4957 | |
29b0f896 AM |
4958 | /* We must avoid matching of Imm32 templates when 64bit |
4959 | only immediate is available. */ | |
4960 | if (guess_suffix == QWORD_MNEM_SUFFIX) | |
40fb9820 | 4961 | i.types[op].bitfield.imm32 = 0; |
29b0f896 | 4962 | break; |
252b5132 | 4963 | |
29b0f896 AM |
4964 | case O_absent: |
4965 | case O_register: | |
4966 | abort (); | |
4967 | ||
4968 | /* Symbols and expressions. */ | |
4969 | default: | |
9cd96992 JB |
4970 | /* Convert symbolic operand to proper sizes for matching, but don't |
4971 | prevent matching a set of insns that only supports sizes other | |
4972 | than those matching the insn suffix. */ | |
4973 | { | |
40fb9820 | 4974 | i386_operand_type mask, allowed; |
d3ce72d0 | 4975 | const insn_template *t; |
9cd96992 | 4976 | |
0dfbf9d7 L |
4977 | operand_type_set (&mask, 0); |
4978 | operand_type_set (&allowed, 0); | |
40fb9820 | 4979 | |
4eed87de AM |
4980 | for (t = current_templates->start; |
4981 | t < current_templates->end; | |
4982 | ++t) | |
c6fb90c8 L |
4983 | allowed = operand_type_or (allowed, |
4984 | t->operand_types[op]); | |
9cd96992 JB |
4985 | switch (guess_suffix) |
4986 | { | |
4987 | case QWORD_MNEM_SUFFIX: | |
40fb9820 L |
4988 | mask.bitfield.imm64 = 1; |
4989 | mask.bitfield.imm32s = 1; | |
9cd96992 JB |
4990 | break; |
4991 | case LONG_MNEM_SUFFIX: | |
40fb9820 | 4992 | mask.bitfield.imm32 = 1; |
9cd96992 JB |
4993 | break; |
4994 | case WORD_MNEM_SUFFIX: | |
40fb9820 | 4995 | mask.bitfield.imm16 = 1; |
9cd96992 JB |
4996 | break; |
4997 | case BYTE_MNEM_SUFFIX: | |
40fb9820 | 4998 | mask.bitfield.imm8 = 1; |
9cd96992 JB |
4999 | break; |
5000 | default: | |
9cd96992 JB |
5001 | break; |
5002 | } | |
c6fb90c8 | 5003 | allowed = operand_type_and (mask, allowed); |
0dfbf9d7 | 5004 | if (!operand_type_all_zero (&allowed)) |
c6fb90c8 | 5005 | i.types[op] = operand_type_and (i.types[op], mask); |
9cd96992 | 5006 | } |
29b0f896 | 5007 | break; |
252b5132 | 5008 | } |
29b0f896 AM |
5009 | } |
5010 | } | |
47926f60 | 5011 | |
29b0f896 AM |
5012 | /* Try to use the smallest displacement type too. */ |
5013 | static void | |
e3bb37b5 | 5014 | optimize_disp (void) |
29b0f896 AM |
5015 | { |
5016 | int op; | |
3e73aa7c | 5017 | |
29b0f896 | 5018 | for (op = i.operands; --op >= 0;) |
40fb9820 | 5019 | if (operand_type_check (i.types[op], disp)) |
252b5132 | 5020 | { |
b300c311 | 5021 | if (i.op[op].disps->X_op == O_constant) |
252b5132 | 5022 | { |
91d6fa6a | 5023 | offsetT op_disp = i.op[op].disps->X_add_number; |
29b0f896 | 5024 | |
40fb9820 | 5025 | if (i.types[op].bitfield.disp16 |
91d6fa6a | 5026 | && (op_disp & ~(offsetT) 0xffff) == 0) |
b300c311 L |
5027 | { |
5028 | /* If this operand is at most 16 bits, convert | |
5029 | to a signed 16 bit number and don't use 64bit | |
5030 | displacement. */ | |
91d6fa6a | 5031 | op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000); |
40fb9820 | 5032 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 5033 | } |
a28def75 L |
5034 | #ifdef BFD64 |
5035 | /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */ | |
40fb9820 | 5036 | if (i.types[op].bitfield.disp32 |
91d6fa6a | 5037 | && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0) |
b300c311 L |
5038 | { |
5039 | /* If this operand is at most 32 bits, convert | |
5040 | to a signed 32 bit number and don't use 64bit | |
5041 | displacement. */ | |
91d6fa6a NC |
5042 | op_disp &= (((offsetT) 2 << 31) - 1); |
5043 | op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); | |
40fb9820 | 5044 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 5045 | } |
a28def75 | 5046 | #endif |
91d6fa6a | 5047 | if (!op_disp && i.types[op].bitfield.baseindex) |
b300c311 | 5048 | { |
40fb9820 L |
5049 | i.types[op].bitfield.disp8 = 0; |
5050 | i.types[op].bitfield.disp16 = 0; | |
5051 | i.types[op].bitfield.disp32 = 0; | |
5052 | i.types[op].bitfield.disp32s = 0; | |
5053 | i.types[op].bitfield.disp64 = 0; | |
b300c311 L |
5054 | i.op[op].disps = 0; |
5055 | i.disp_operands--; | |
5056 | } | |
5057 | else if (flag_code == CODE_64BIT) | |
5058 | { | |
91d6fa6a | 5059 | if (fits_in_signed_long (op_disp)) |
28a9d8f5 | 5060 | { |
40fb9820 L |
5061 | i.types[op].bitfield.disp64 = 0; |
5062 | i.types[op].bitfield.disp32s = 1; | |
28a9d8f5 | 5063 | } |
0e1147d9 | 5064 | if (i.prefix[ADDR_PREFIX] |
91d6fa6a | 5065 | && fits_in_unsigned_long (op_disp)) |
40fb9820 | 5066 | i.types[op].bitfield.disp32 = 1; |
b300c311 | 5067 | } |
40fb9820 L |
5068 | if ((i.types[op].bitfield.disp32 |
5069 | || i.types[op].bitfield.disp32s | |
5070 | || i.types[op].bitfield.disp16) | |
b5014f7a | 5071 | && fits_in_disp8 (op_disp)) |
40fb9820 | 5072 | i.types[op].bitfield.disp8 = 1; |
252b5132 | 5073 | } |
67a4f2b7 AO |
5074 | else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL |
5075 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL) | |
5076 | { | |
5077 | fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0, | |
5078 | i.op[op].disps, 0, i.reloc[op]); | |
40fb9820 L |
5079 | i.types[op].bitfield.disp8 = 0; |
5080 | i.types[op].bitfield.disp16 = 0; | |
5081 | i.types[op].bitfield.disp32 = 0; | |
5082 | i.types[op].bitfield.disp32s = 0; | |
5083 | i.types[op].bitfield.disp64 = 0; | |
67a4f2b7 AO |
5084 | } |
5085 | else | |
b300c311 | 5086 | /* We only support 64bit displacement on constants. */ |
40fb9820 | 5087 | i.types[op].bitfield.disp64 = 0; |
252b5132 | 5088 | } |
29b0f896 AM |
5089 | } |
5090 | ||
4a1b91ea L |
5091 | /* Return 1 if there is a match in broadcast bytes between operand |
5092 | GIVEN and instruction template T. */ | |
5093 | ||
5094 | static INLINE int | |
5095 | match_broadcast_size (const insn_template *t, unsigned int given) | |
5096 | { | |
5097 | return ((t->opcode_modifier.broadcast == BYTE_BROADCAST | |
5098 | && i.types[given].bitfield.byte) | |
5099 | || (t->opcode_modifier.broadcast == WORD_BROADCAST | |
5100 | && i.types[given].bitfield.word) | |
5101 | || (t->opcode_modifier.broadcast == DWORD_BROADCAST | |
5102 | && i.types[given].bitfield.dword) | |
5103 | || (t->opcode_modifier.broadcast == QWORD_BROADCAST | |
5104 | && i.types[given].bitfield.qword)); | |
5105 | } | |
5106 | ||
6c30d220 L |
5107 | /* Check if operands are valid for the instruction. */ |
5108 | ||
5109 | static int | |
5110 | check_VecOperands (const insn_template *t) | |
5111 | { | |
43234a1e | 5112 | unsigned int op; |
e2195274 JB |
5113 | i386_cpu_flags cpu; |
5114 | static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS; | |
5115 | ||
5116 | /* Templates allowing for ZMMword as well as YMMword and/or XMMword for | |
5117 | any one operand are implicity requiring AVX512VL support if the actual | |
5118 | operand size is YMMword or XMMword. Since this function runs after | |
5119 | template matching, there's no need to check for YMMword/XMMword in | |
5120 | the template. */ | |
5121 | cpu = cpu_flags_and (t->cpu_flags, avx512); | |
5122 | if (!cpu_flags_all_zero (&cpu) | |
5123 | && !t->cpu_flags.bitfield.cpuavx512vl | |
5124 | && !cpu_arch_flags.bitfield.cpuavx512vl) | |
5125 | { | |
5126 | for (op = 0; op < t->operands; ++op) | |
5127 | { | |
5128 | if (t->operand_types[op].bitfield.zmmword | |
5129 | && (i.types[op].bitfield.ymmword | |
5130 | || i.types[op].bitfield.xmmword)) | |
5131 | { | |
5132 | i.error = unsupported; | |
5133 | return 1; | |
5134 | } | |
5135 | } | |
5136 | } | |
43234a1e | 5137 | |
6c30d220 L |
5138 | /* Without VSIB byte, we can't have a vector register for index. */ |
5139 | if (!t->opcode_modifier.vecsib | |
5140 | && i.index_reg | |
1b54b8d7 JB |
5141 | && (i.index_reg->reg_type.bitfield.xmmword |
5142 | || i.index_reg->reg_type.bitfield.ymmword | |
5143 | || i.index_reg->reg_type.bitfield.zmmword)) | |
6c30d220 L |
5144 | { |
5145 | i.error = unsupported_vector_index_register; | |
5146 | return 1; | |
5147 | } | |
5148 | ||
ad8ecc81 MZ |
5149 | /* Check if default mask is allowed. */ |
5150 | if (t->opcode_modifier.nodefmask | |
5151 | && (!i.mask || i.mask->mask->reg_num == 0)) | |
5152 | { | |
5153 | i.error = no_default_mask; | |
5154 | return 1; | |
5155 | } | |
5156 | ||
7bab8ab5 JB |
5157 | /* For VSIB byte, we need a vector register for index, and all vector |
5158 | registers must be distinct. */ | |
5159 | if (t->opcode_modifier.vecsib) | |
5160 | { | |
5161 | if (!i.index_reg | |
6c30d220 | 5162 | || !((t->opcode_modifier.vecsib == VecSIB128 |
1b54b8d7 | 5163 | && i.index_reg->reg_type.bitfield.xmmword) |
6c30d220 | 5164 | || (t->opcode_modifier.vecsib == VecSIB256 |
1b54b8d7 | 5165 | && i.index_reg->reg_type.bitfield.ymmword) |
43234a1e | 5166 | || (t->opcode_modifier.vecsib == VecSIB512 |
1b54b8d7 | 5167 | && i.index_reg->reg_type.bitfield.zmmword))) |
7bab8ab5 JB |
5168 | { |
5169 | i.error = invalid_vsib_address; | |
5170 | return 1; | |
5171 | } | |
5172 | ||
43234a1e L |
5173 | gas_assert (i.reg_operands == 2 || i.mask); |
5174 | if (i.reg_operands == 2 && !i.mask) | |
5175 | { | |
1b54b8d7 JB |
5176 | gas_assert (i.types[0].bitfield.regsimd); |
5177 | gas_assert (i.types[0].bitfield.xmmword | |
5178 | || i.types[0].bitfield.ymmword); | |
5179 | gas_assert (i.types[2].bitfield.regsimd); | |
5180 | gas_assert (i.types[2].bitfield.xmmword | |
5181 | || i.types[2].bitfield.ymmword); | |
43234a1e L |
5182 | if (operand_check == check_none) |
5183 | return 0; | |
5184 | if (register_number (i.op[0].regs) | |
5185 | != register_number (i.index_reg) | |
5186 | && register_number (i.op[2].regs) | |
5187 | != register_number (i.index_reg) | |
5188 | && register_number (i.op[0].regs) | |
5189 | != register_number (i.op[2].regs)) | |
5190 | return 0; | |
5191 | if (operand_check == check_error) | |
5192 | { | |
5193 | i.error = invalid_vector_register_set; | |
5194 | return 1; | |
5195 | } | |
5196 | as_warn (_("mask, index, and destination registers should be distinct")); | |
5197 | } | |
8444f82a MZ |
5198 | else if (i.reg_operands == 1 && i.mask) |
5199 | { | |
1b54b8d7 JB |
5200 | if (i.types[1].bitfield.regsimd |
5201 | && (i.types[1].bitfield.xmmword | |
5202 | || i.types[1].bitfield.ymmword | |
5203 | || i.types[1].bitfield.zmmword) | |
8444f82a MZ |
5204 | && (register_number (i.op[1].regs) |
5205 | == register_number (i.index_reg))) | |
5206 | { | |
5207 | if (operand_check == check_error) | |
5208 | { | |
5209 | i.error = invalid_vector_register_set; | |
5210 | return 1; | |
5211 | } | |
5212 | if (operand_check != check_none) | |
5213 | as_warn (_("index and destination registers should be distinct")); | |
5214 | } | |
5215 | } | |
43234a1e | 5216 | } |
7bab8ab5 | 5217 | |
43234a1e L |
5218 | /* Check if broadcast is supported by the instruction and is applied |
5219 | to the memory operand. */ | |
5220 | if (i.broadcast) | |
5221 | { | |
8e6e0792 | 5222 | i386_operand_type type, overlap; |
43234a1e L |
5223 | |
5224 | /* Check if specified broadcast is supported in this instruction, | |
4a1b91ea | 5225 | and its broadcast bytes match the memory operand. */ |
32546502 | 5226 | op = i.broadcast->operand; |
8e6e0792 | 5227 | if (!t->opcode_modifier.broadcast |
c48dadc9 | 5228 | || !(i.flags[op] & Operand_Mem) |
c39e5b26 | 5229 | || (!i.types[op].bitfield.unspecified |
4a1b91ea | 5230 | && !match_broadcast_size (t, op))) |
43234a1e L |
5231 | { |
5232 | bad_broadcast: | |
5233 | i.error = unsupported_broadcast; | |
5234 | return 1; | |
5235 | } | |
8e6e0792 | 5236 | |
4a1b91ea L |
5237 | i.broadcast->bytes = ((1 << (t->opcode_modifier.broadcast - 1)) |
5238 | * i.broadcast->type); | |
8e6e0792 | 5239 | operand_type_set (&type, 0); |
4a1b91ea | 5240 | switch (i.broadcast->bytes) |
8e6e0792 | 5241 | { |
4a1b91ea L |
5242 | case 2: |
5243 | type.bitfield.word = 1; | |
5244 | break; | |
5245 | case 4: | |
5246 | type.bitfield.dword = 1; | |
5247 | break; | |
8e6e0792 JB |
5248 | case 8: |
5249 | type.bitfield.qword = 1; | |
5250 | break; | |
5251 | case 16: | |
5252 | type.bitfield.xmmword = 1; | |
5253 | break; | |
5254 | case 32: | |
5255 | type.bitfield.ymmword = 1; | |
5256 | break; | |
5257 | case 64: | |
5258 | type.bitfield.zmmword = 1; | |
5259 | break; | |
5260 | default: | |
5261 | goto bad_broadcast; | |
5262 | } | |
5263 | ||
5264 | overlap = operand_type_and (type, t->operand_types[op]); | |
5265 | if (operand_type_all_zero (&overlap)) | |
5266 | goto bad_broadcast; | |
5267 | ||
5268 | if (t->opcode_modifier.checkregsize) | |
5269 | { | |
5270 | unsigned int j; | |
5271 | ||
e2195274 | 5272 | type.bitfield.baseindex = 1; |
8e6e0792 JB |
5273 | for (j = 0; j < i.operands; ++j) |
5274 | { | |
5275 | if (j != op | |
5276 | && !operand_type_register_match(i.types[j], | |
5277 | t->operand_types[j], | |
5278 | type, | |
5279 | t->operand_types[op])) | |
5280 | goto bad_broadcast; | |
5281 | } | |
5282 | } | |
43234a1e L |
5283 | } |
5284 | /* If broadcast is supported in this instruction, we need to check if | |
5285 | operand of one-element size isn't specified without broadcast. */ | |
5286 | else if (t->opcode_modifier.broadcast && i.mem_operands) | |
5287 | { | |
5288 | /* Find memory operand. */ | |
5289 | for (op = 0; op < i.operands; op++) | |
5290 | if (operand_type_check (i.types[op], anymem)) | |
5291 | break; | |
5292 | gas_assert (op < i.operands); | |
5293 | /* Check size of the memory operand. */ | |
4a1b91ea | 5294 | if (match_broadcast_size (t, op)) |
43234a1e L |
5295 | { |
5296 | i.error = broadcast_needed; | |
5297 | return 1; | |
5298 | } | |
5299 | } | |
c39e5b26 JB |
5300 | else |
5301 | op = MAX_OPERANDS - 1; /* Avoid uninitialized variable warning. */ | |
43234a1e L |
5302 | |
5303 | /* Check if requested masking is supported. */ | |
ae2387fe | 5304 | if (i.mask) |
43234a1e | 5305 | { |
ae2387fe JB |
5306 | switch (t->opcode_modifier.masking) |
5307 | { | |
5308 | case BOTH_MASKING: | |
5309 | break; | |
5310 | case MERGING_MASKING: | |
5311 | if (i.mask->zeroing) | |
5312 | { | |
5313 | case 0: | |
5314 | i.error = unsupported_masking; | |
5315 | return 1; | |
5316 | } | |
5317 | break; | |
5318 | case DYNAMIC_MASKING: | |
5319 | /* Memory destinations allow only merging masking. */ | |
5320 | if (i.mask->zeroing && i.mem_operands) | |
5321 | { | |
5322 | /* Find memory operand. */ | |
5323 | for (op = 0; op < i.operands; op++) | |
c48dadc9 | 5324 | if (i.flags[op] & Operand_Mem) |
ae2387fe JB |
5325 | break; |
5326 | gas_assert (op < i.operands); | |
5327 | if (op == i.operands - 1) | |
5328 | { | |
5329 | i.error = unsupported_masking; | |
5330 | return 1; | |
5331 | } | |
5332 | } | |
5333 | break; | |
5334 | default: | |
5335 | abort (); | |
5336 | } | |
43234a1e L |
5337 | } |
5338 | ||
5339 | /* Check if masking is applied to dest operand. */ | |
5340 | if (i.mask && (i.mask->operand != (int) (i.operands - 1))) | |
5341 | { | |
5342 | i.error = mask_not_on_destination; | |
5343 | return 1; | |
5344 | } | |
5345 | ||
43234a1e L |
5346 | /* Check RC/SAE. */ |
5347 | if (i.rounding) | |
5348 | { | |
5349 | if ((i.rounding->type != saeonly | |
5350 | && !t->opcode_modifier.staticrounding) | |
5351 | || (i.rounding->type == saeonly | |
5352 | && (t->opcode_modifier.staticrounding | |
5353 | || !t->opcode_modifier.sae))) | |
5354 | { | |
5355 | i.error = unsupported_rc_sae; | |
5356 | return 1; | |
5357 | } | |
5358 | /* If the instruction has several immediate operands and one of | |
5359 | them is rounding, the rounding operand should be the last | |
5360 | immediate operand. */ | |
5361 | if (i.imm_operands > 1 | |
5362 | && i.rounding->operand != (int) (i.imm_operands - 1)) | |
7bab8ab5 | 5363 | { |
43234a1e | 5364 | i.error = rc_sae_operand_not_last_imm; |
7bab8ab5 JB |
5365 | return 1; |
5366 | } | |
6c30d220 L |
5367 | } |
5368 | ||
43234a1e | 5369 | /* Check vector Disp8 operand. */ |
b5014f7a JB |
5370 | if (t->opcode_modifier.disp8memshift |
5371 | && i.disp_encoding != disp_encoding_32bit) | |
43234a1e L |
5372 | { |
5373 | if (i.broadcast) | |
4a1b91ea | 5374 | i.memshift = t->opcode_modifier.broadcast - 1; |
7091c612 | 5375 | else if (t->opcode_modifier.disp8memshift != DISP8_SHIFT_VL) |
43234a1e | 5376 | i.memshift = t->opcode_modifier.disp8memshift; |
7091c612 JB |
5377 | else |
5378 | { | |
5379 | const i386_operand_type *type = NULL; | |
5380 | ||
5381 | i.memshift = 0; | |
5382 | for (op = 0; op < i.operands; op++) | |
5383 | if (operand_type_check (i.types[op], anymem)) | |
5384 | { | |
4174bfff JB |
5385 | if (t->opcode_modifier.evex == EVEXLIG) |
5386 | i.memshift = 2 + (i.suffix == QWORD_MNEM_SUFFIX); | |
5387 | else if (t->operand_types[op].bitfield.xmmword | |
5388 | + t->operand_types[op].bitfield.ymmword | |
5389 | + t->operand_types[op].bitfield.zmmword <= 1) | |
7091c612 JB |
5390 | type = &t->operand_types[op]; |
5391 | else if (!i.types[op].bitfield.unspecified) | |
5392 | type = &i.types[op]; | |
5393 | } | |
4174bfff JB |
5394 | else if (i.types[op].bitfield.regsimd |
5395 | && t->opcode_modifier.evex != EVEXLIG) | |
7091c612 JB |
5396 | { |
5397 | if (i.types[op].bitfield.zmmword) | |
5398 | i.memshift = 6; | |
5399 | else if (i.types[op].bitfield.ymmword && i.memshift < 5) | |
5400 | i.memshift = 5; | |
5401 | else if (i.types[op].bitfield.xmmword && i.memshift < 4) | |
5402 | i.memshift = 4; | |
5403 | } | |
5404 | ||
5405 | if (type) | |
5406 | { | |
5407 | if (type->bitfield.zmmword) | |
5408 | i.memshift = 6; | |
5409 | else if (type->bitfield.ymmword) | |
5410 | i.memshift = 5; | |
5411 | else if (type->bitfield.xmmword) | |
5412 | i.memshift = 4; | |
5413 | } | |
5414 | ||
5415 | /* For the check in fits_in_disp8(). */ | |
5416 | if (i.memshift == 0) | |
5417 | i.memshift = -1; | |
5418 | } | |
43234a1e L |
5419 | |
5420 | for (op = 0; op < i.operands; op++) | |
5421 | if (operand_type_check (i.types[op], disp) | |
5422 | && i.op[op].disps->X_op == O_constant) | |
5423 | { | |
b5014f7a | 5424 | if (fits_in_disp8 (i.op[op].disps->X_add_number)) |
43234a1e | 5425 | { |
b5014f7a JB |
5426 | i.types[op].bitfield.disp8 = 1; |
5427 | return 0; | |
43234a1e | 5428 | } |
b5014f7a | 5429 | i.types[op].bitfield.disp8 = 0; |
43234a1e L |
5430 | } |
5431 | } | |
b5014f7a JB |
5432 | |
5433 | i.memshift = 0; | |
43234a1e | 5434 | |
6c30d220 L |
5435 | return 0; |
5436 | } | |
5437 | ||
43f3e2ee | 5438 | /* Check if operands are valid for the instruction. Update VEX |
a683cc34 SP |
5439 | operand types. */ |
5440 | ||
5441 | static int | |
5442 | VEX_check_operands (const insn_template *t) | |
5443 | { | |
86fa6981 | 5444 | if (i.vec_encoding == vex_encoding_evex) |
43234a1e | 5445 | { |
86fa6981 | 5446 | /* This instruction must be encoded with EVEX prefix. */ |
e771e7c9 | 5447 | if (!is_evex_encoding (t)) |
86fa6981 L |
5448 | { |
5449 | i.error = unsupported; | |
5450 | return 1; | |
5451 | } | |
5452 | return 0; | |
43234a1e L |
5453 | } |
5454 | ||
a683cc34 | 5455 | if (!t->opcode_modifier.vex) |
86fa6981 L |
5456 | { |
5457 | /* This instruction template doesn't have VEX prefix. */ | |
5458 | if (i.vec_encoding != vex_encoding_default) | |
5459 | { | |
5460 | i.error = unsupported; | |
5461 | return 1; | |
5462 | } | |
5463 | return 0; | |
5464 | } | |
a683cc34 SP |
5465 | |
5466 | /* Only check VEX_Imm4, which must be the first operand. */ | |
5467 | if (t->operand_types[0].bitfield.vec_imm4) | |
5468 | { | |
5469 | if (i.op[0].imms->X_op != O_constant | |
5470 | || !fits_in_imm4 (i.op[0].imms->X_add_number)) | |
891edac4 | 5471 | { |
a65babc9 | 5472 | i.error = bad_imm4; |
891edac4 L |
5473 | return 1; |
5474 | } | |
a683cc34 SP |
5475 | |
5476 | /* Turn off Imm8 so that update_imm won't complain. */ | |
5477 | i.types[0] = vec_imm4; | |
5478 | } | |
5479 | ||
5480 | return 0; | |
5481 | } | |
5482 | ||
d3ce72d0 | 5483 | static const insn_template * |
83b16ac6 | 5484 | match_template (char mnem_suffix) |
29b0f896 AM |
5485 | { |
5486 | /* Points to template once we've found it. */ | |
d3ce72d0 | 5487 | const insn_template *t; |
40fb9820 | 5488 | i386_operand_type overlap0, overlap1, overlap2, overlap3; |
c0f3af97 | 5489 | i386_operand_type overlap4; |
29b0f896 | 5490 | unsigned int found_reverse_match; |
83b16ac6 | 5491 | i386_opcode_modifier suffix_check, mnemsuf_check; |
40fb9820 | 5492 | i386_operand_type operand_types [MAX_OPERANDS]; |
539e75ad | 5493 | int addr_prefix_disp; |
a5c311ca | 5494 | unsigned int j; |
3ac21baa | 5495 | unsigned int found_cpu_match, size_match; |
45664ddb | 5496 | unsigned int check_register; |
5614d22c | 5497 | enum i386_error specific_error = 0; |
29b0f896 | 5498 | |
c0f3af97 L |
5499 | #if MAX_OPERANDS != 5 |
5500 | # error "MAX_OPERANDS must be 5." | |
f48ff2ae L |
5501 | #endif |
5502 | ||
29b0f896 | 5503 | found_reverse_match = 0; |
539e75ad | 5504 | addr_prefix_disp = -1; |
40fb9820 L |
5505 | |
5506 | memset (&suffix_check, 0, sizeof (suffix_check)); | |
e2195274 JB |
5507 | if (intel_syntax && i.broadcast) |
5508 | /* nothing */; | |
5509 | else if (i.suffix == BYTE_MNEM_SUFFIX) | |
40fb9820 L |
5510 | suffix_check.no_bsuf = 1; |
5511 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
5512 | suffix_check.no_wsuf = 1; | |
5513 | else if (i.suffix == SHORT_MNEM_SUFFIX) | |
5514 | suffix_check.no_ssuf = 1; | |
5515 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
5516 | suffix_check.no_lsuf = 1; | |
5517 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
5518 | suffix_check.no_qsuf = 1; | |
5519 | else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX) | |
7ce189b3 | 5520 | suffix_check.no_ldsuf = 1; |
29b0f896 | 5521 | |
83b16ac6 JB |
5522 | memset (&mnemsuf_check, 0, sizeof (mnemsuf_check)); |
5523 | if (intel_syntax) | |
5524 | { | |
5525 | switch (mnem_suffix) | |
5526 | { | |
5527 | case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break; | |
5528 | case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break; | |
5529 | case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break; | |
5530 | case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break; | |
5531 | case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break; | |
5532 | } | |
5533 | } | |
5534 | ||
01559ecc L |
5535 | /* Must have right number of operands. */ |
5536 | i.error = number_of_operands_mismatch; | |
5537 | ||
45aa61fe | 5538 | for (t = current_templates->start; t < current_templates->end; t++) |
29b0f896 | 5539 | { |
539e75ad | 5540 | addr_prefix_disp = -1; |
dbbc8b7e | 5541 | found_reverse_match = 0; |
539e75ad | 5542 | |
29b0f896 AM |
5543 | if (i.operands != t->operands) |
5544 | continue; | |
5545 | ||
50aecf8c | 5546 | /* Check processor support. */ |
a65babc9 | 5547 | i.error = unsupported; |
c0f3af97 L |
5548 | found_cpu_match = (cpu_flags_match (t) |
5549 | == CPU_FLAGS_PERFECT_MATCH); | |
50aecf8c L |
5550 | if (!found_cpu_match) |
5551 | continue; | |
5552 | ||
e1d4d893 | 5553 | /* Check AT&T mnemonic. */ |
a65babc9 | 5554 | i.error = unsupported_with_intel_mnemonic; |
e1d4d893 | 5555 | if (intel_mnemonic && t->opcode_modifier.attmnemonic) |
1efbbeb4 L |
5556 | continue; |
5557 | ||
e92bae62 | 5558 | /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */ |
a65babc9 | 5559 | i.error = unsupported_syntax; |
5c07affc | 5560 | if ((intel_syntax && t->opcode_modifier.attsyntax) |
e92bae62 L |
5561 | || (!intel_syntax && t->opcode_modifier.intelsyntax) |
5562 | || (intel64 && t->opcode_modifier.amd64) | |
5563 | || (!intel64 && t->opcode_modifier.intel64)) | |
1efbbeb4 L |
5564 | continue; |
5565 | ||
20592a94 | 5566 | /* Check the suffix, except for some instructions in intel mode. */ |
a65babc9 | 5567 | i.error = invalid_instruction_suffix; |
567e4e96 L |
5568 | if ((!intel_syntax || !t->opcode_modifier.ignoresize) |
5569 | && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf) | |
5570 | || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf) | |
5571 | || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf) | |
5572 | || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf) | |
5573 | || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf) | |
5574 | || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf))) | |
29b0f896 | 5575 | continue; |
83b16ac6 JB |
5576 | /* In Intel mode all mnemonic suffixes must be explicitly allowed. */ |
5577 | if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf) | |
5578 | || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf) | |
5579 | || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf) | |
5580 | || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf) | |
5581 | || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf) | |
5582 | || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf)) | |
5583 | continue; | |
29b0f896 | 5584 | |
3ac21baa JB |
5585 | size_match = operand_size_match (t); |
5586 | if (!size_match) | |
7d5e4556 | 5587 | continue; |
539e75ad | 5588 | |
5c07affc L |
5589 | for (j = 0; j < MAX_OPERANDS; j++) |
5590 | operand_types[j] = t->operand_types[j]; | |
5591 | ||
45aa61fe AM |
5592 | /* In general, don't allow 64-bit operands in 32-bit mode. */ |
5593 | if (i.suffix == QWORD_MNEM_SUFFIX | |
5594 | && flag_code != CODE_64BIT | |
5595 | && (intel_syntax | |
40fb9820 | 5596 | ? (!t->opcode_modifier.ignoresize |
625cbd7a | 5597 | && !t->opcode_modifier.broadcast |
45aa61fe AM |
5598 | && !intel_float_operand (t->name)) |
5599 | : intel_float_operand (t->name) != 2) | |
40fb9820 | 5600 | && ((!operand_types[0].bitfield.regmmx |
1b54b8d7 | 5601 | && !operand_types[0].bitfield.regsimd) |
40fb9820 | 5602 | || (!operand_types[t->operands > 1].bitfield.regmmx |
1b54b8d7 | 5603 | && !operand_types[t->operands > 1].bitfield.regsimd)) |
45aa61fe AM |
5604 | && (t->base_opcode != 0x0fc7 |
5605 | || t->extension_opcode != 1 /* cmpxchg8b */)) | |
5606 | continue; | |
5607 | ||
192dc9c6 JB |
5608 | /* In general, don't allow 32-bit operands on pre-386. */ |
5609 | else if (i.suffix == LONG_MNEM_SUFFIX | |
5610 | && !cpu_arch_flags.bitfield.cpui386 | |
5611 | && (intel_syntax | |
5612 | ? (!t->opcode_modifier.ignoresize | |
5613 | && !intel_float_operand (t->name)) | |
5614 | : intel_float_operand (t->name) != 2) | |
5615 | && ((!operand_types[0].bitfield.regmmx | |
1b54b8d7 | 5616 | && !operand_types[0].bitfield.regsimd) |
192dc9c6 | 5617 | || (!operand_types[t->operands > 1].bitfield.regmmx |
1b54b8d7 | 5618 | && !operand_types[t->operands > 1].bitfield.regsimd))) |
192dc9c6 JB |
5619 | continue; |
5620 | ||
29b0f896 | 5621 | /* Do not verify operands when there are none. */ |
50aecf8c | 5622 | else |
29b0f896 | 5623 | { |
c6fb90c8 | 5624 | if (!t->operands) |
2dbab7d5 L |
5625 | /* We've found a match; break out of loop. */ |
5626 | break; | |
29b0f896 | 5627 | } |
252b5132 | 5628 | |
539e75ad L |
5629 | /* Address size prefix will turn Disp64/Disp32/Disp16 operand |
5630 | into Disp32/Disp16/Disp32 operand. */ | |
5631 | if (i.prefix[ADDR_PREFIX] != 0) | |
5632 | { | |
40fb9820 | 5633 | /* There should be only one Disp operand. */ |
539e75ad L |
5634 | switch (flag_code) |
5635 | { | |
5636 | case CODE_16BIT: | |
40fb9820 L |
5637 | for (j = 0; j < MAX_OPERANDS; j++) |
5638 | { | |
5639 | if (operand_types[j].bitfield.disp16) | |
5640 | { | |
5641 | addr_prefix_disp = j; | |
5642 | operand_types[j].bitfield.disp32 = 1; | |
5643 | operand_types[j].bitfield.disp16 = 0; | |
5644 | break; | |
5645 | } | |
5646 | } | |
539e75ad L |
5647 | break; |
5648 | case CODE_32BIT: | |
40fb9820 L |
5649 | for (j = 0; j < MAX_OPERANDS; j++) |
5650 | { | |
5651 | if (operand_types[j].bitfield.disp32) | |
5652 | { | |
5653 | addr_prefix_disp = j; | |
5654 | operand_types[j].bitfield.disp32 = 0; | |
5655 | operand_types[j].bitfield.disp16 = 1; | |
5656 | break; | |
5657 | } | |
5658 | } | |
539e75ad L |
5659 | break; |
5660 | case CODE_64BIT: | |
40fb9820 L |
5661 | for (j = 0; j < MAX_OPERANDS; j++) |
5662 | { | |
5663 | if (operand_types[j].bitfield.disp64) | |
5664 | { | |
5665 | addr_prefix_disp = j; | |
5666 | operand_types[j].bitfield.disp64 = 0; | |
5667 | operand_types[j].bitfield.disp32 = 1; | |
5668 | break; | |
5669 | } | |
5670 | } | |
539e75ad L |
5671 | break; |
5672 | } | |
539e75ad L |
5673 | } |
5674 | ||
02a86693 L |
5675 | /* Force 0x8b encoding for "mov foo@GOT, %eax". */ |
5676 | if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0) | |
5677 | continue; | |
5678 | ||
56ffb741 | 5679 | /* We check register size if needed. */ |
e2195274 JB |
5680 | if (t->opcode_modifier.checkregsize) |
5681 | { | |
5682 | check_register = (1 << t->operands) - 1; | |
5683 | if (i.broadcast) | |
5684 | check_register &= ~(1 << i.broadcast->operand); | |
5685 | } | |
5686 | else | |
5687 | check_register = 0; | |
5688 | ||
c6fb90c8 | 5689 | overlap0 = operand_type_and (i.types[0], operand_types[0]); |
29b0f896 AM |
5690 | switch (t->operands) |
5691 | { | |
5692 | case 1: | |
40fb9820 | 5693 | if (!operand_type_match (overlap0, i.types[0])) |
29b0f896 AM |
5694 | continue; |
5695 | break; | |
5696 | case 2: | |
33eaf5de | 5697 | /* xchg %eax, %eax is a special case. It is an alias for nop |
8b38ad71 L |
5698 | only in 32bit mode and we can use opcode 0x90. In 64bit |
5699 | mode, we can't use 0x90 for xchg %eax, %eax since it should | |
5700 | zero-extend %eax to %rax. */ | |
5701 | if (flag_code == CODE_64BIT | |
5702 | && t->base_opcode == 0x90 | |
0dfbf9d7 L |
5703 | && operand_type_equal (&i.types [0], &acc32) |
5704 | && operand_type_equal (&i.types [1], &acc32)) | |
8b38ad71 | 5705 | continue; |
1212781b JB |
5706 | /* xrelease mov %eax, <disp> is another special case. It must not |
5707 | match the accumulator-only encoding of mov. */ | |
5708 | if (flag_code != CODE_64BIT | |
5709 | && i.hle_prefix | |
5710 | && t->base_opcode == 0xa0 | |
5711 | && i.types[0].bitfield.acc | |
5712 | && operand_type_check (i.types[1], anymem)) | |
5713 | continue; | |
3ac21baa JB |
5714 | if (!(size_match & MATCH_STRAIGHT)) |
5715 | goto check_reverse; | |
64c49ab3 JB |
5716 | /* Reverse direction of operands if swapping is possible in the first |
5717 | place (operands need to be symmetric) and | |
5718 | - the load form is requested, and the template is a store form, | |
5719 | - the store form is requested, and the template is a load form, | |
5720 | - the non-default (swapped) form is requested. */ | |
5721 | overlap1 = operand_type_and (operand_types[0], operand_types[1]); | |
5722 | if (t->opcode_modifier.d && i.reg_operands == 2 | |
5723 | && !operand_type_all_zero (&overlap1)) | |
5724 | switch (i.dir_encoding) | |
5725 | { | |
5726 | case dir_encoding_load: | |
5727 | if (operand_type_check (operand_types[i.operands - 1], anymem) | |
5728 | || operand_types[i.operands - 1].bitfield.regmem) | |
5729 | goto check_reverse; | |
5730 | break; | |
5731 | ||
5732 | case dir_encoding_store: | |
5733 | if (!operand_type_check (operand_types[i.operands - 1], anymem) | |
5734 | && !operand_types[i.operands - 1].bitfield.regmem) | |
5735 | goto check_reverse; | |
5736 | break; | |
5737 | ||
5738 | case dir_encoding_swap: | |
5739 | goto check_reverse; | |
5740 | ||
5741 | case dir_encoding_default: | |
5742 | break; | |
5743 | } | |
1a0670f3 | 5744 | /* Fall through. */ |
b6169b20 | 5745 | |
29b0f896 | 5746 | case 3: |
86fa6981 | 5747 | /* If we want store form, we skip the current load. */ |
64c49ab3 JB |
5748 | if ((i.dir_encoding == dir_encoding_store |
5749 | || i.dir_encoding == dir_encoding_swap) | |
86fa6981 L |
5750 | && i.mem_operands == 0 |
5751 | && t->opcode_modifier.load) | |
fa99fab2 | 5752 | continue; |
1a0670f3 | 5753 | /* Fall through. */ |
f48ff2ae | 5754 | case 4: |
c0f3af97 | 5755 | case 5: |
c6fb90c8 | 5756 | overlap1 = operand_type_and (i.types[1], operand_types[1]); |
40fb9820 L |
5757 | if (!operand_type_match (overlap0, i.types[0]) |
5758 | || !operand_type_match (overlap1, i.types[1]) | |
e2195274 | 5759 | || ((check_register & 3) == 3 |
dc821c5f | 5760 | && !operand_type_register_match (i.types[0], |
40fb9820 | 5761 | operand_types[0], |
dc821c5f | 5762 | i.types[1], |
40fb9820 | 5763 | operand_types[1]))) |
29b0f896 AM |
5764 | { |
5765 | /* Check if other direction is valid ... */ | |
38e314eb | 5766 | if (!t->opcode_modifier.d) |
29b0f896 AM |
5767 | continue; |
5768 | ||
b6169b20 | 5769 | check_reverse: |
3ac21baa JB |
5770 | if (!(size_match & MATCH_REVERSE)) |
5771 | continue; | |
29b0f896 | 5772 | /* Try reversing direction of operands. */ |
c6fb90c8 L |
5773 | overlap0 = operand_type_and (i.types[0], operand_types[1]); |
5774 | overlap1 = operand_type_and (i.types[1], operand_types[0]); | |
40fb9820 L |
5775 | if (!operand_type_match (overlap0, i.types[0]) |
5776 | || !operand_type_match (overlap1, i.types[1]) | |
45664ddb | 5777 | || (check_register |
dc821c5f | 5778 | && !operand_type_register_match (i.types[0], |
45664ddb | 5779 | operand_types[1], |
45664ddb L |
5780 | i.types[1], |
5781 | operand_types[0]))) | |
29b0f896 AM |
5782 | { |
5783 | /* Does not match either direction. */ | |
5784 | continue; | |
5785 | } | |
38e314eb | 5786 | /* found_reverse_match holds which of D or FloatR |
29b0f896 | 5787 | we've found. */ |
38e314eb JB |
5788 | if (!t->opcode_modifier.d) |
5789 | found_reverse_match = 0; | |
5790 | else if (operand_types[0].bitfield.tbyte) | |
8a2ed489 | 5791 | found_reverse_match = Opcode_FloatD; |
dbbc8b7e JB |
5792 | else if (operand_types[0].bitfield.xmmword |
5793 | || operand_types[1].bitfield.xmmword | |
5794 | || operand_types[0].bitfield.regmmx | |
5795 | || operand_types[1].bitfield.regmmx | |
5796 | || is_any_vex_encoding(t)) | |
5797 | found_reverse_match = (t->base_opcode & 0xee) != 0x6e | |
5798 | ? Opcode_SIMD_FloatD : Opcode_SIMD_IntD; | |
8a2ed489 | 5799 | else |
38e314eb | 5800 | found_reverse_match = Opcode_D; |
40fb9820 | 5801 | if (t->opcode_modifier.floatr) |
8a2ed489 | 5802 | found_reverse_match |= Opcode_FloatR; |
29b0f896 | 5803 | } |
f48ff2ae | 5804 | else |
29b0f896 | 5805 | { |
f48ff2ae | 5806 | /* Found a forward 2 operand match here. */ |
d1cbb4db L |
5807 | switch (t->operands) |
5808 | { | |
c0f3af97 L |
5809 | case 5: |
5810 | overlap4 = operand_type_and (i.types[4], | |
5811 | operand_types[4]); | |
1a0670f3 | 5812 | /* Fall through. */ |
d1cbb4db | 5813 | case 4: |
c6fb90c8 L |
5814 | overlap3 = operand_type_and (i.types[3], |
5815 | operand_types[3]); | |
1a0670f3 | 5816 | /* Fall through. */ |
d1cbb4db | 5817 | case 3: |
c6fb90c8 L |
5818 | overlap2 = operand_type_and (i.types[2], |
5819 | operand_types[2]); | |
d1cbb4db L |
5820 | break; |
5821 | } | |
29b0f896 | 5822 | |
f48ff2ae L |
5823 | switch (t->operands) |
5824 | { | |
c0f3af97 L |
5825 | case 5: |
5826 | if (!operand_type_match (overlap4, i.types[4]) | |
dc821c5f | 5827 | || !operand_type_register_match (i.types[3], |
c0f3af97 | 5828 | operand_types[3], |
c0f3af97 L |
5829 | i.types[4], |
5830 | operand_types[4])) | |
5831 | continue; | |
1a0670f3 | 5832 | /* Fall through. */ |
f48ff2ae | 5833 | case 4: |
40fb9820 | 5834 | if (!operand_type_match (overlap3, i.types[3]) |
e2195274 JB |
5835 | || ((check_register & 0xa) == 0xa |
5836 | && !operand_type_register_match (i.types[1], | |
f7768225 JB |
5837 | operand_types[1], |
5838 | i.types[3], | |
e2195274 JB |
5839 | operand_types[3])) |
5840 | || ((check_register & 0xc) == 0xc | |
5841 | && !operand_type_register_match (i.types[2], | |
5842 | operand_types[2], | |
5843 | i.types[3], | |
5844 | operand_types[3]))) | |
f48ff2ae | 5845 | continue; |
1a0670f3 | 5846 | /* Fall through. */ |
f48ff2ae L |
5847 | case 3: |
5848 | /* Here we make use of the fact that there are no | |
23e42951 | 5849 | reverse match 3 operand instructions. */ |
40fb9820 | 5850 | if (!operand_type_match (overlap2, i.types[2]) |
e2195274 JB |
5851 | || ((check_register & 5) == 5 |
5852 | && !operand_type_register_match (i.types[0], | |
23e42951 JB |
5853 | operand_types[0], |
5854 | i.types[2], | |
e2195274 JB |
5855 | operand_types[2])) |
5856 | || ((check_register & 6) == 6 | |
5857 | && !operand_type_register_match (i.types[1], | |
5858 | operand_types[1], | |
5859 | i.types[2], | |
5860 | operand_types[2]))) | |
f48ff2ae L |
5861 | continue; |
5862 | break; | |
5863 | } | |
29b0f896 | 5864 | } |
f48ff2ae | 5865 | /* Found either forward/reverse 2, 3 or 4 operand match here: |
29b0f896 AM |
5866 | slip through to break. */ |
5867 | } | |
3629bb00 | 5868 | if (!found_cpu_match) |
dbbc8b7e | 5869 | continue; |
c0f3af97 | 5870 | |
5614d22c JB |
5871 | /* Check if vector and VEX operands are valid. */ |
5872 | if (check_VecOperands (t) || VEX_check_operands (t)) | |
5873 | { | |
5874 | specific_error = i.error; | |
5875 | continue; | |
5876 | } | |
a683cc34 | 5877 | |
29b0f896 AM |
5878 | /* We've found a match; break out of loop. */ |
5879 | break; | |
5880 | } | |
5881 | ||
5882 | if (t == current_templates->end) | |
5883 | { | |
5884 | /* We found no match. */ | |
a65babc9 | 5885 | const char *err_msg; |
5614d22c | 5886 | switch (specific_error ? specific_error : i.error) |
a65babc9 L |
5887 | { |
5888 | default: | |
5889 | abort (); | |
86e026a4 | 5890 | case operand_size_mismatch: |
a65babc9 L |
5891 | err_msg = _("operand size mismatch"); |
5892 | break; | |
5893 | case operand_type_mismatch: | |
5894 | err_msg = _("operand type mismatch"); | |
5895 | break; | |
5896 | case register_type_mismatch: | |
5897 | err_msg = _("register type mismatch"); | |
5898 | break; | |
5899 | case number_of_operands_mismatch: | |
5900 | err_msg = _("number of operands mismatch"); | |
5901 | break; | |
5902 | case invalid_instruction_suffix: | |
5903 | err_msg = _("invalid instruction suffix"); | |
5904 | break; | |
5905 | case bad_imm4: | |
4a2608e3 | 5906 | err_msg = _("constant doesn't fit in 4 bits"); |
a65babc9 | 5907 | break; |
a65babc9 L |
5908 | case unsupported_with_intel_mnemonic: |
5909 | err_msg = _("unsupported with Intel mnemonic"); | |
5910 | break; | |
5911 | case unsupported_syntax: | |
5912 | err_msg = _("unsupported syntax"); | |
5913 | break; | |
5914 | case unsupported: | |
35262a23 | 5915 | as_bad (_("unsupported instruction `%s'"), |
10efe3f6 L |
5916 | current_templates->start->name); |
5917 | return NULL; | |
6c30d220 L |
5918 | case invalid_vsib_address: |
5919 | err_msg = _("invalid VSIB address"); | |
5920 | break; | |
7bab8ab5 JB |
5921 | case invalid_vector_register_set: |
5922 | err_msg = _("mask, index, and destination registers must be distinct"); | |
5923 | break; | |
6c30d220 L |
5924 | case unsupported_vector_index_register: |
5925 | err_msg = _("unsupported vector index register"); | |
5926 | break; | |
43234a1e L |
5927 | case unsupported_broadcast: |
5928 | err_msg = _("unsupported broadcast"); | |
5929 | break; | |
43234a1e L |
5930 | case broadcast_needed: |
5931 | err_msg = _("broadcast is needed for operand of such type"); | |
5932 | break; | |
5933 | case unsupported_masking: | |
5934 | err_msg = _("unsupported masking"); | |
5935 | break; | |
5936 | case mask_not_on_destination: | |
5937 | err_msg = _("mask not on destination operand"); | |
5938 | break; | |
5939 | case no_default_mask: | |
5940 | err_msg = _("default mask isn't allowed"); | |
5941 | break; | |
5942 | case unsupported_rc_sae: | |
5943 | err_msg = _("unsupported static rounding/sae"); | |
5944 | break; | |
5945 | case rc_sae_operand_not_last_imm: | |
5946 | if (intel_syntax) | |
5947 | err_msg = _("RC/SAE operand must precede immediate operands"); | |
5948 | else | |
5949 | err_msg = _("RC/SAE operand must follow immediate operands"); | |
5950 | break; | |
5951 | case invalid_register_operand: | |
5952 | err_msg = _("invalid register operand"); | |
5953 | break; | |
a65babc9 L |
5954 | } |
5955 | as_bad (_("%s for `%s'"), err_msg, | |
891edac4 | 5956 | current_templates->start->name); |
fa99fab2 | 5957 | return NULL; |
29b0f896 | 5958 | } |
252b5132 | 5959 | |
29b0f896 AM |
5960 | if (!quiet_warnings) |
5961 | { | |
5962 | if (!intel_syntax | |
40fb9820 L |
5963 | && (i.types[0].bitfield.jumpabsolute |
5964 | != operand_types[0].bitfield.jumpabsolute)) | |
29b0f896 AM |
5965 | { |
5966 | as_warn (_("indirect %s without `*'"), t->name); | |
5967 | } | |
5968 | ||
40fb9820 L |
5969 | if (t->opcode_modifier.isprefix |
5970 | && t->opcode_modifier.ignoresize) | |
29b0f896 AM |
5971 | { |
5972 | /* Warn them that a data or address size prefix doesn't | |
5973 | affect assembly of the next line of code. */ | |
5974 | as_warn (_("stand-alone `%s' prefix"), t->name); | |
5975 | } | |
5976 | } | |
5977 | ||
5978 | /* Copy the template we found. */ | |
5979 | i.tm = *t; | |
539e75ad L |
5980 | |
5981 | if (addr_prefix_disp != -1) | |
5982 | i.tm.operand_types[addr_prefix_disp] | |
5983 | = operand_types[addr_prefix_disp]; | |
5984 | ||
29b0f896 AM |
5985 | if (found_reverse_match) |
5986 | { | |
5987 | /* If we found a reverse match we must alter the opcode | |
5988 | direction bit. found_reverse_match holds bits to change | |
5989 | (different for int & float insns). */ | |
5990 | ||
5991 | i.tm.base_opcode ^= found_reverse_match; | |
5992 | ||
539e75ad L |
5993 | i.tm.operand_types[0] = operand_types[1]; |
5994 | i.tm.operand_types[1] = operand_types[0]; | |
29b0f896 AM |
5995 | } |
5996 | ||
fa99fab2 | 5997 | return t; |
29b0f896 AM |
5998 | } |
5999 | ||
6000 | static int | |
e3bb37b5 | 6001 | check_string (void) |
29b0f896 | 6002 | { |
40fb9820 L |
6003 | int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1; |
6004 | if (i.tm.operand_types[mem_op].bitfield.esseg) | |
29b0f896 AM |
6005 | { |
6006 | if (i.seg[0] != NULL && i.seg[0] != &es) | |
6007 | { | |
a87af027 | 6008 | as_bad (_("`%s' operand %d must use `%ses' segment"), |
29b0f896 | 6009 | i.tm.name, |
a87af027 JB |
6010 | mem_op + 1, |
6011 | register_prefix); | |
29b0f896 AM |
6012 | return 0; |
6013 | } | |
6014 | /* There's only ever one segment override allowed per instruction. | |
6015 | This instruction possibly has a legal segment override on the | |
6016 | second operand, so copy the segment to where non-string | |
6017 | instructions store it, allowing common code. */ | |
6018 | i.seg[0] = i.seg[1]; | |
6019 | } | |
40fb9820 | 6020 | else if (i.tm.operand_types[mem_op + 1].bitfield.esseg) |
29b0f896 AM |
6021 | { |
6022 | if (i.seg[1] != NULL && i.seg[1] != &es) | |
6023 | { | |
a87af027 | 6024 | as_bad (_("`%s' operand %d must use `%ses' segment"), |
29b0f896 | 6025 | i.tm.name, |
a87af027 JB |
6026 | mem_op + 2, |
6027 | register_prefix); | |
29b0f896 AM |
6028 | return 0; |
6029 | } | |
6030 | } | |
6031 | return 1; | |
6032 | } | |
6033 | ||
6034 | static int | |
543613e9 | 6035 | process_suffix (void) |
29b0f896 AM |
6036 | { |
6037 | /* If matched instruction specifies an explicit instruction mnemonic | |
6038 | suffix, use it. */ | |
40fb9820 L |
6039 | if (i.tm.opcode_modifier.size16) |
6040 | i.suffix = WORD_MNEM_SUFFIX; | |
6041 | else if (i.tm.opcode_modifier.size32) | |
6042 | i.suffix = LONG_MNEM_SUFFIX; | |
6043 | else if (i.tm.opcode_modifier.size64) | |
6044 | i.suffix = QWORD_MNEM_SUFFIX; | |
29b0f896 AM |
6045 | else if (i.reg_operands) |
6046 | { | |
6047 | /* If there's no instruction mnemonic suffix we try to invent one | |
6048 | based on register operands. */ | |
6049 | if (!i.suffix) | |
6050 | { | |
6051 | /* We take i.suffix from the last register operand specified, | |
6052 | Destination register type is more significant than source | |
381d071f L |
6053 | register type. crc32 in SSE4.2 prefers source register |
6054 | type. */ | |
6055 | if (i.tm.base_opcode == 0xf20f38f1) | |
6056 | { | |
dc821c5f | 6057 | if (i.types[0].bitfield.reg && i.types[0].bitfield.word) |
40fb9820 | 6058 | i.suffix = WORD_MNEM_SUFFIX; |
dc821c5f | 6059 | else if (i.types[0].bitfield.reg && i.types[0].bitfield.dword) |
40fb9820 | 6060 | i.suffix = LONG_MNEM_SUFFIX; |
dc821c5f | 6061 | else if (i.types[0].bitfield.reg && i.types[0].bitfield.qword) |
40fb9820 | 6062 | i.suffix = QWORD_MNEM_SUFFIX; |
381d071f | 6063 | } |
9344ff29 | 6064 | else if (i.tm.base_opcode == 0xf20f38f0) |
20592a94 | 6065 | { |
dc821c5f | 6066 | if (i.types[0].bitfield.reg && i.types[0].bitfield.byte) |
20592a94 L |
6067 | i.suffix = BYTE_MNEM_SUFFIX; |
6068 | } | |
381d071f L |
6069 | |
6070 | if (!i.suffix) | |
6071 | { | |
6072 | int op; | |
6073 | ||
20592a94 L |
6074 | if (i.tm.base_opcode == 0xf20f38f1 |
6075 | || i.tm.base_opcode == 0xf20f38f0) | |
6076 | { | |
6077 | /* We have to know the operand size for crc32. */ | |
6078 | as_bad (_("ambiguous memory operand size for `%s`"), | |
6079 | i.tm.name); | |
6080 | return 0; | |
6081 | } | |
6082 | ||
381d071f | 6083 | for (op = i.operands; --op >= 0;) |
b76bc5d5 JB |
6084 | if (!i.tm.operand_types[op].bitfield.inoutportreg |
6085 | && !i.tm.operand_types[op].bitfield.shiftcount) | |
381d071f | 6086 | { |
8819ada6 JB |
6087 | if (!i.types[op].bitfield.reg) |
6088 | continue; | |
6089 | if (i.types[op].bitfield.byte) | |
6090 | i.suffix = BYTE_MNEM_SUFFIX; | |
6091 | else if (i.types[op].bitfield.word) | |
6092 | i.suffix = WORD_MNEM_SUFFIX; | |
6093 | else if (i.types[op].bitfield.dword) | |
6094 | i.suffix = LONG_MNEM_SUFFIX; | |
6095 | else if (i.types[op].bitfield.qword) | |
6096 | i.suffix = QWORD_MNEM_SUFFIX; | |
6097 | else | |
6098 | continue; | |
6099 | break; | |
381d071f L |
6100 | } |
6101 | } | |
29b0f896 AM |
6102 | } |
6103 | else if (i.suffix == BYTE_MNEM_SUFFIX) | |
6104 | { | |
2eb952a4 L |
6105 | if (intel_syntax |
6106 | && i.tm.opcode_modifier.ignoresize | |
6107 | && i.tm.opcode_modifier.no_bsuf) | |
6108 | i.suffix = 0; | |
6109 | else if (!check_byte_reg ()) | |
29b0f896 AM |
6110 | return 0; |
6111 | } | |
6112 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
6113 | { | |
2eb952a4 L |
6114 | if (intel_syntax |
6115 | && i.tm.opcode_modifier.ignoresize | |
9f123b91 JB |
6116 | && i.tm.opcode_modifier.no_lsuf |
6117 | && !i.tm.opcode_modifier.todword | |
6118 | && !i.tm.opcode_modifier.toqword) | |
2eb952a4 L |
6119 | i.suffix = 0; |
6120 | else if (!check_long_reg ()) | |
29b0f896 AM |
6121 | return 0; |
6122 | } | |
6123 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
6124 | { | |
955e1e6a L |
6125 | if (intel_syntax |
6126 | && i.tm.opcode_modifier.ignoresize | |
9f123b91 JB |
6127 | && i.tm.opcode_modifier.no_qsuf |
6128 | && !i.tm.opcode_modifier.todword | |
6129 | && !i.tm.opcode_modifier.toqword) | |
955e1e6a L |
6130 | i.suffix = 0; |
6131 | else if (!check_qword_reg ()) | |
29b0f896 AM |
6132 | return 0; |
6133 | } | |
6134 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
6135 | { | |
2eb952a4 L |
6136 | if (intel_syntax |
6137 | && i.tm.opcode_modifier.ignoresize | |
6138 | && i.tm.opcode_modifier.no_wsuf) | |
6139 | i.suffix = 0; | |
6140 | else if (!check_word_reg ()) | |
29b0f896 AM |
6141 | return 0; |
6142 | } | |
40fb9820 | 6143 | else if (intel_syntax && i.tm.opcode_modifier.ignoresize) |
29b0f896 AM |
6144 | /* Do nothing if the instruction is going to ignore the prefix. */ |
6145 | ; | |
6146 | else | |
6147 | abort (); | |
6148 | } | |
40fb9820 | 6149 | else if (i.tm.opcode_modifier.defaultsize |
9306ca4a JB |
6150 | && !i.suffix |
6151 | /* exclude fldenv/frstor/fsave/fstenv */ | |
40fb9820 | 6152 | && i.tm.opcode_modifier.no_ssuf) |
29b0f896 AM |
6153 | { |
6154 | i.suffix = stackop_size; | |
6155 | } | |
9306ca4a JB |
6156 | else if (intel_syntax |
6157 | && !i.suffix | |
40fb9820 L |
6158 | && (i.tm.operand_types[0].bitfield.jumpabsolute |
6159 | || i.tm.opcode_modifier.jumpbyte | |
6160 | || i.tm.opcode_modifier.jumpintersegment | |
64e74474 AM |
6161 | || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */ |
6162 | && i.tm.extension_opcode <= 3))) | |
9306ca4a JB |
6163 | { |
6164 | switch (flag_code) | |
6165 | { | |
6166 | case CODE_64BIT: | |
40fb9820 | 6167 | if (!i.tm.opcode_modifier.no_qsuf) |
9306ca4a JB |
6168 | { |
6169 | i.suffix = QWORD_MNEM_SUFFIX; | |
6170 | break; | |
6171 | } | |
1a0670f3 | 6172 | /* Fall through. */ |
9306ca4a | 6173 | case CODE_32BIT: |
40fb9820 | 6174 | if (!i.tm.opcode_modifier.no_lsuf) |
9306ca4a JB |
6175 | i.suffix = LONG_MNEM_SUFFIX; |
6176 | break; | |
6177 | case CODE_16BIT: | |
40fb9820 | 6178 | if (!i.tm.opcode_modifier.no_wsuf) |
9306ca4a JB |
6179 | i.suffix = WORD_MNEM_SUFFIX; |
6180 | break; | |
6181 | } | |
6182 | } | |
252b5132 | 6183 | |
9306ca4a | 6184 | if (!i.suffix) |
29b0f896 | 6185 | { |
9306ca4a JB |
6186 | if (!intel_syntax) |
6187 | { | |
40fb9820 | 6188 | if (i.tm.opcode_modifier.w) |
9306ca4a | 6189 | { |
4eed87de AM |
6190 | as_bad (_("no instruction mnemonic suffix given and " |
6191 | "no register operands; can't size instruction")); | |
9306ca4a JB |
6192 | return 0; |
6193 | } | |
6194 | } | |
6195 | else | |
6196 | { | |
40fb9820 | 6197 | unsigned int suffixes; |
7ab9ffdd | 6198 | |
40fb9820 L |
6199 | suffixes = !i.tm.opcode_modifier.no_bsuf; |
6200 | if (!i.tm.opcode_modifier.no_wsuf) | |
6201 | suffixes |= 1 << 1; | |
6202 | if (!i.tm.opcode_modifier.no_lsuf) | |
6203 | suffixes |= 1 << 2; | |
fc4adea1 | 6204 | if (!i.tm.opcode_modifier.no_ldsuf) |
40fb9820 L |
6205 | suffixes |= 1 << 3; |
6206 | if (!i.tm.opcode_modifier.no_ssuf) | |
6207 | suffixes |= 1 << 4; | |
c2b9da16 | 6208 | if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf) |
40fb9820 L |
6209 | suffixes |= 1 << 5; |
6210 | ||
6211 | /* There are more than suffix matches. */ | |
6212 | if (i.tm.opcode_modifier.w | |
9306ca4a | 6213 | || ((suffixes & (suffixes - 1)) |
40fb9820 L |
6214 | && !i.tm.opcode_modifier.defaultsize |
6215 | && !i.tm.opcode_modifier.ignoresize)) | |
9306ca4a JB |
6216 | { |
6217 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); | |
6218 | return 0; | |
6219 | } | |
6220 | } | |
29b0f896 | 6221 | } |
252b5132 | 6222 | |
d2224064 JB |
6223 | /* Change the opcode based on the operand size given by i.suffix. */ |
6224 | switch (i.suffix) | |
29b0f896 | 6225 | { |
d2224064 JB |
6226 | /* Size floating point instruction. */ |
6227 | case LONG_MNEM_SUFFIX: | |
6228 | if (i.tm.opcode_modifier.floatmf) | |
6229 | { | |
6230 | i.tm.base_opcode ^= 4; | |
6231 | break; | |
6232 | } | |
6233 | /* fall through */ | |
6234 | case WORD_MNEM_SUFFIX: | |
6235 | case QWORD_MNEM_SUFFIX: | |
29b0f896 | 6236 | /* It's not a byte, select word/dword operation. */ |
40fb9820 | 6237 | if (i.tm.opcode_modifier.w) |
29b0f896 | 6238 | { |
40fb9820 | 6239 | if (i.tm.opcode_modifier.shortform) |
29b0f896 AM |
6240 | i.tm.base_opcode |= 8; |
6241 | else | |
6242 | i.tm.base_opcode |= 1; | |
6243 | } | |
d2224064 JB |
6244 | /* fall through */ |
6245 | case SHORT_MNEM_SUFFIX: | |
29b0f896 AM |
6246 | /* Now select between word & dword operations via the operand |
6247 | size prefix, except for instructions that will ignore this | |
6248 | prefix anyway. */ | |
75c0a438 L |
6249 | if (i.reg_operands > 0 |
6250 | && i.types[0].bitfield.reg | |
6251 | && i.tm.opcode_modifier.addrprefixopreg | |
6252 | && (i.tm.opcode_modifier.immext | |
6253 | || i.operands == 1)) | |
cb712a9e | 6254 | { |
ca61edf2 L |
6255 | /* The address size override prefix changes the size of the |
6256 | first operand. */ | |
40fb9820 | 6257 | if ((flag_code == CODE_32BIT |
75c0a438 | 6258 | && i.op[0].regs->reg_type.bitfield.word) |
40fb9820 | 6259 | || (flag_code != CODE_32BIT |
75c0a438 | 6260 | && i.op[0].regs->reg_type.bitfield.dword)) |
cb712a9e L |
6261 | if (!add_prefix (ADDR_PREFIX_OPCODE)) |
6262 | return 0; | |
6263 | } | |
6264 | else if (i.suffix != QWORD_MNEM_SUFFIX | |
40fb9820 L |
6265 | && !i.tm.opcode_modifier.ignoresize |
6266 | && !i.tm.opcode_modifier.floatmf | |
7a8655d2 JB |
6267 | && !i.tm.opcode_modifier.vex |
6268 | && !i.tm.opcode_modifier.vexopcode | |
6269 | && !is_evex_encoding (&i.tm) | |
cb712a9e L |
6270 | && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT) |
6271 | || (flag_code == CODE_64BIT | |
40fb9820 | 6272 | && i.tm.opcode_modifier.jumpbyte))) |
24eab124 AM |
6273 | { |
6274 | unsigned int prefix = DATA_PREFIX_OPCODE; | |
543613e9 | 6275 | |
40fb9820 | 6276 | if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */ |
29b0f896 | 6277 | prefix = ADDR_PREFIX_OPCODE; |
252b5132 | 6278 | |
29b0f896 AM |
6279 | if (!add_prefix (prefix)) |
6280 | return 0; | |
24eab124 | 6281 | } |
252b5132 | 6282 | |
29b0f896 AM |
6283 | /* Set mode64 for an operand. */ |
6284 | if (i.suffix == QWORD_MNEM_SUFFIX | |
9146926a | 6285 | && flag_code == CODE_64BIT |
d2224064 | 6286 | && !i.tm.opcode_modifier.norex64 |
46e883c5 | 6287 | /* Special case for xchg %rax,%rax. It is NOP and doesn't |
d2224064 JB |
6288 | need rex64. */ |
6289 | && ! (i.operands == 2 | |
6290 | && i.tm.base_opcode == 0x90 | |
6291 | && i.tm.extension_opcode == None | |
6292 | && operand_type_equal (&i.types [0], &acc64) | |
6293 | && operand_type_equal (&i.types [1], &acc64))) | |
6294 | i.rex |= REX_W; | |
3e73aa7c | 6295 | |
d2224064 | 6296 | break; |
29b0f896 | 6297 | } |
7ecd2f8b | 6298 | |
c0a30a9f L |
6299 | if (i.reg_operands != 0 |
6300 | && i.operands > 1 | |
6301 | && i.tm.opcode_modifier.addrprefixopreg | |
6302 | && !i.tm.opcode_modifier.immext) | |
6303 | { | |
6304 | /* Check invalid register operand when the address size override | |
6305 | prefix changes the size of register operands. */ | |
6306 | unsigned int op; | |
6307 | enum { need_word, need_dword, need_qword } need; | |
6308 | ||
6309 | if (flag_code == CODE_32BIT) | |
6310 | need = i.prefix[ADDR_PREFIX] ? need_word : need_dword; | |
6311 | else | |
6312 | { | |
6313 | if (i.prefix[ADDR_PREFIX]) | |
6314 | need = need_dword; | |
6315 | else | |
6316 | need = flag_code == CODE_64BIT ? need_qword : need_word; | |
6317 | } | |
6318 | ||
6319 | for (op = 0; op < i.operands; op++) | |
6320 | if (i.types[op].bitfield.reg | |
6321 | && ((need == need_word | |
6322 | && !i.op[op].regs->reg_type.bitfield.word) | |
6323 | || (need == need_dword | |
6324 | && !i.op[op].regs->reg_type.bitfield.dword) | |
6325 | || (need == need_qword | |
6326 | && !i.op[op].regs->reg_type.bitfield.qword))) | |
6327 | { | |
6328 | as_bad (_("invalid register operand size for `%s'"), | |
6329 | i.tm.name); | |
6330 | return 0; | |
6331 | } | |
6332 | } | |
6333 | ||
29b0f896 AM |
6334 | return 1; |
6335 | } | |
3e73aa7c | 6336 | |
29b0f896 | 6337 | static int |
543613e9 | 6338 | check_byte_reg (void) |
29b0f896 AM |
6339 | { |
6340 | int op; | |
543613e9 | 6341 | |
29b0f896 AM |
6342 | for (op = i.operands; --op >= 0;) |
6343 | { | |
dc821c5f JB |
6344 | /* Skip non-register operands. */ |
6345 | if (!i.types[op].bitfield.reg) | |
6346 | continue; | |
6347 | ||
29b0f896 AM |
6348 | /* If this is an eight bit register, it's OK. If it's the 16 or |
6349 | 32 bit version of an eight bit register, we will just use the | |
6350 | low portion, and that's OK too. */ | |
dc821c5f | 6351 | if (i.types[op].bitfield.byte) |
29b0f896 AM |
6352 | continue; |
6353 | ||
5a819eb9 JB |
6354 | /* I/O port address operands are OK too. */ |
6355 | if (i.tm.operand_types[op].bitfield.inoutportreg) | |
6356 | continue; | |
6357 | ||
9344ff29 L |
6358 | /* crc32 doesn't generate this warning. */ |
6359 | if (i.tm.base_opcode == 0xf20f38f0) | |
6360 | continue; | |
6361 | ||
dc821c5f JB |
6362 | if ((i.types[op].bitfield.word |
6363 | || i.types[op].bitfield.dword | |
6364 | || i.types[op].bitfield.qword) | |
5a819eb9 JB |
6365 | && i.op[op].regs->reg_num < 4 |
6366 | /* Prohibit these changes in 64bit mode, since the lowering | |
6367 | would be more complicated. */ | |
6368 | && flag_code != CODE_64BIT) | |
29b0f896 | 6369 | { |
29b0f896 | 6370 | #if REGISTER_WARNINGS |
5a819eb9 | 6371 | if (!quiet_warnings) |
a540244d L |
6372 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
6373 | register_prefix, | |
dc821c5f | 6374 | (i.op[op].regs + (i.types[op].bitfield.word |
29b0f896 AM |
6375 | ? REGNAM_AL - REGNAM_AX |
6376 | : REGNAM_AL - REGNAM_EAX))->reg_name, | |
a540244d | 6377 | register_prefix, |
29b0f896 AM |
6378 | i.op[op].regs->reg_name, |
6379 | i.suffix); | |
6380 | #endif | |
6381 | continue; | |
6382 | } | |
6383 | /* Any other register is bad. */ | |
dc821c5f | 6384 | if (i.types[op].bitfield.reg |
40fb9820 | 6385 | || i.types[op].bitfield.regmmx |
1b54b8d7 | 6386 | || i.types[op].bitfield.regsimd |
40fb9820 L |
6387 | || i.types[op].bitfield.sreg2 |
6388 | || i.types[op].bitfield.sreg3 | |
6389 | || i.types[op].bitfield.control | |
6390 | || i.types[op].bitfield.debug | |
ca0d63fe | 6391 | || i.types[op].bitfield.test) |
29b0f896 | 6392 | { |
a540244d L |
6393 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
6394 | register_prefix, | |
29b0f896 AM |
6395 | i.op[op].regs->reg_name, |
6396 | i.tm.name, | |
6397 | i.suffix); | |
6398 | return 0; | |
6399 | } | |
6400 | } | |
6401 | return 1; | |
6402 | } | |
6403 | ||
6404 | static int | |
e3bb37b5 | 6405 | check_long_reg (void) |
29b0f896 AM |
6406 | { |
6407 | int op; | |
6408 | ||
6409 | for (op = i.operands; --op >= 0;) | |
dc821c5f JB |
6410 | /* Skip non-register operands. */ |
6411 | if (!i.types[op].bitfield.reg) | |
6412 | continue; | |
29b0f896 AM |
6413 | /* Reject eight bit registers, except where the template requires |
6414 | them. (eg. movzb) */ | |
dc821c5f JB |
6415 | else if (i.types[op].bitfield.byte |
6416 | && (i.tm.operand_types[op].bitfield.reg | |
6417 | || i.tm.operand_types[op].bitfield.acc) | |
6418 | && (i.tm.operand_types[op].bitfield.word | |
6419 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 6420 | { |
a540244d L |
6421 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
6422 | register_prefix, | |
29b0f896 AM |
6423 | i.op[op].regs->reg_name, |
6424 | i.tm.name, | |
6425 | i.suffix); | |
6426 | return 0; | |
6427 | } | |
e4630f71 | 6428 | /* Warn if the e prefix on a general reg is missing. */ |
29b0f896 | 6429 | else if ((!quiet_warnings || flag_code == CODE_64BIT) |
dc821c5f JB |
6430 | && i.types[op].bitfield.word |
6431 | && (i.tm.operand_types[op].bitfield.reg | |
6432 | || i.tm.operand_types[op].bitfield.acc) | |
6433 | && i.tm.operand_types[op].bitfield.dword) | |
29b0f896 AM |
6434 | { |
6435 | /* Prohibit these changes in the 64bit mode, since the | |
6436 | lowering is more complicated. */ | |
6437 | if (flag_code == CODE_64BIT) | |
252b5132 | 6438 | { |
2b5d6a91 | 6439 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
2ca3ace5 | 6440 | register_prefix, i.op[op].regs->reg_name, |
29b0f896 AM |
6441 | i.suffix); |
6442 | return 0; | |
252b5132 | 6443 | } |
29b0f896 | 6444 | #if REGISTER_WARNINGS |
cecf1424 JB |
6445 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
6446 | register_prefix, | |
6447 | (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name, | |
6448 | register_prefix, i.op[op].regs->reg_name, i.suffix); | |
29b0f896 | 6449 | #endif |
252b5132 | 6450 | } |
e4630f71 | 6451 | /* Warn if the r prefix on a general reg is present. */ |
dc821c5f JB |
6452 | else if (i.types[op].bitfield.qword |
6453 | && (i.tm.operand_types[op].bitfield.reg | |
6454 | || i.tm.operand_types[op].bitfield.acc) | |
6455 | && i.tm.operand_types[op].bitfield.dword) | |
252b5132 | 6456 | { |
34828aad | 6457 | if (intel_syntax |
ca61edf2 | 6458 | && i.tm.opcode_modifier.toqword |
1b54b8d7 | 6459 | && !i.types[0].bitfield.regsimd) |
34828aad | 6460 | { |
ca61edf2 | 6461 | /* Convert to QWORD. We want REX byte. */ |
34828aad L |
6462 | i.suffix = QWORD_MNEM_SUFFIX; |
6463 | } | |
6464 | else | |
6465 | { | |
2b5d6a91 | 6466 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
34828aad L |
6467 | register_prefix, i.op[op].regs->reg_name, |
6468 | i.suffix); | |
6469 | return 0; | |
6470 | } | |
29b0f896 AM |
6471 | } |
6472 | return 1; | |
6473 | } | |
252b5132 | 6474 | |
29b0f896 | 6475 | static int |
e3bb37b5 | 6476 | check_qword_reg (void) |
29b0f896 AM |
6477 | { |
6478 | int op; | |
252b5132 | 6479 | |
29b0f896 | 6480 | for (op = i.operands; --op >= 0; ) |
dc821c5f JB |
6481 | /* Skip non-register operands. */ |
6482 | if (!i.types[op].bitfield.reg) | |
6483 | continue; | |
29b0f896 AM |
6484 | /* Reject eight bit registers, except where the template requires |
6485 | them. (eg. movzb) */ | |
dc821c5f JB |
6486 | else if (i.types[op].bitfield.byte |
6487 | && (i.tm.operand_types[op].bitfield.reg | |
6488 | || i.tm.operand_types[op].bitfield.acc) | |
6489 | && (i.tm.operand_types[op].bitfield.word | |
6490 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 6491 | { |
a540244d L |
6492 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
6493 | register_prefix, | |
29b0f896 AM |
6494 | i.op[op].regs->reg_name, |
6495 | i.tm.name, | |
6496 | i.suffix); | |
6497 | return 0; | |
6498 | } | |
e4630f71 | 6499 | /* Warn if the r prefix on a general reg is missing. */ |
dc821c5f JB |
6500 | else if ((i.types[op].bitfield.word |
6501 | || i.types[op].bitfield.dword) | |
6502 | && (i.tm.operand_types[op].bitfield.reg | |
6503 | || i.tm.operand_types[op].bitfield.acc) | |
6504 | && i.tm.operand_types[op].bitfield.qword) | |
29b0f896 AM |
6505 | { |
6506 | /* Prohibit these changes in the 64bit mode, since the | |
6507 | lowering is more complicated. */ | |
34828aad | 6508 | if (intel_syntax |
ca61edf2 | 6509 | && i.tm.opcode_modifier.todword |
1b54b8d7 | 6510 | && !i.types[0].bitfield.regsimd) |
34828aad | 6511 | { |
ca61edf2 | 6512 | /* Convert to DWORD. We don't want REX byte. */ |
34828aad L |
6513 | i.suffix = LONG_MNEM_SUFFIX; |
6514 | } | |
6515 | else | |
6516 | { | |
2b5d6a91 | 6517 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
34828aad L |
6518 | register_prefix, i.op[op].regs->reg_name, |
6519 | i.suffix); | |
6520 | return 0; | |
6521 | } | |
252b5132 | 6522 | } |
29b0f896 AM |
6523 | return 1; |
6524 | } | |
252b5132 | 6525 | |
29b0f896 | 6526 | static int |
e3bb37b5 | 6527 | check_word_reg (void) |
29b0f896 AM |
6528 | { |
6529 | int op; | |
6530 | for (op = i.operands; --op >= 0;) | |
dc821c5f JB |
6531 | /* Skip non-register operands. */ |
6532 | if (!i.types[op].bitfield.reg) | |
6533 | continue; | |
29b0f896 AM |
6534 | /* Reject eight bit registers, except where the template requires |
6535 | them. (eg. movzb) */ | |
dc821c5f JB |
6536 | else if (i.types[op].bitfield.byte |
6537 | && (i.tm.operand_types[op].bitfield.reg | |
6538 | || i.tm.operand_types[op].bitfield.acc) | |
6539 | && (i.tm.operand_types[op].bitfield.word | |
6540 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 6541 | { |
a540244d L |
6542 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
6543 | register_prefix, | |
29b0f896 AM |
6544 | i.op[op].regs->reg_name, |
6545 | i.tm.name, | |
6546 | i.suffix); | |
6547 | return 0; | |
6548 | } | |
e4630f71 | 6549 | /* Warn if the e or r prefix on a general reg is present. */ |
29b0f896 | 6550 | else if ((!quiet_warnings || flag_code == CODE_64BIT) |
dc821c5f JB |
6551 | && (i.types[op].bitfield.dword |
6552 | || i.types[op].bitfield.qword) | |
6553 | && (i.tm.operand_types[op].bitfield.reg | |
6554 | || i.tm.operand_types[op].bitfield.acc) | |
6555 | && i.tm.operand_types[op].bitfield.word) | |
252b5132 | 6556 | { |
29b0f896 AM |
6557 | /* Prohibit these changes in the 64bit mode, since the |
6558 | lowering is more complicated. */ | |
6559 | if (flag_code == CODE_64BIT) | |
252b5132 | 6560 | { |
2b5d6a91 | 6561 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
2ca3ace5 | 6562 | register_prefix, i.op[op].regs->reg_name, |
29b0f896 AM |
6563 | i.suffix); |
6564 | return 0; | |
252b5132 | 6565 | } |
29b0f896 | 6566 | #if REGISTER_WARNINGS |
cecf1424 JB |
6567 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
6568 | register_prefix, | |
6569 | (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name, | |
6570 | register_prefix, i.op[op].regs->reg_name, i.suffix); | |
29b0f896 AM |
6571 | #endif |
6572 | } | |
6573 | return 1; | |
6574 | } | |
252b5132 | 6575 | |
29b0f896 | 6576 | static int |
40fb9820 | 6577 | update_imm (unsigned int j) |
29b0f896 | 6578 | { |
bc0844ae | 6579 | i386_operand_type overlap = i.types[j]; |
40fb9820 L |
6580 | if ((overlap.bitfield.imm8 |
6581 | || overlap.bitfield.imm8s | |
6582 | || overlap.bitfield.imm16 | |
6583 | || overlap.bitfield.imm32 | |
6584 | || overlap.bitfield.imm32s | |
6585 | || overlap.bitfield.imm64) | |
0dfbf9d7 L |
6586 | && !operand_type_equal (&overlap, &imm8) |
6587 | && !operand_type_equal (&overlap, &imm8s) | |
6588 | && !operand_type_equal (&overlap, &imm16) | |
6589 | && !operand_type_equal (&overlap, &imm32) | |
6590 | && !operand_type_equal (&overlap, &imm32s) | |
6591 | && !operand_type_equal (&overlap, &imm64)) | |
29b0f896 AM |
6592 | { |
6593 | if (i.suffix) | |
6594 | { | |
40fb9820 L |
6595 | i386_operand_type temp; |
6596 | ||
0dfbf9d7 | 6597 | operand_type_set (&temp, 0); |
7ab9ffdd | 6598 | if (i.suffix == BYTE_MNEM_SUFFIX) |
40fb9820 L |
6599 | { |
6600 | temp.bitfield.imm8 = overlap.bitfield.imm8; | |
6601 | temp.bitfield.imm8s = overlap.bitfield.imm8s; | |
6602 | } | |
6603 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
6604 | temp.bitfield.imm16 = overlap.bitfield.imm16; | |
6605 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
6606 | { | |
6607 | temp.bitfield.imm64 = overlap.bitfield.imm64; | |
6608 | temp.bitfield.imm32s = overlap.bitfield.imm32s; | |
6609 | } | |
6610 | else | |
6611 | temp.bitfield.imm32 = overlap.bitfield.imm32; | |
6612 | overlap = temp; | |
29b0f896 | 6613 | } |
0dfbf9d7 L |
6614 | else if (operand_type_equal (&overlap, &imm16_32_32s) |
6615 | || operand_type_equal (&overlap, &imm16_32) | |
6616 | || operand_type_equal (&overlap, &imm16_32s)) | |
29b0f896 | 6617 | { |
40fb9820 | 6618 | if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) |
65da13b5 | 6619 | overlap = imm16; |
40fb9820 | 6620 | else |
65da13b5 | 6621 | overlap = imm32s; |
29b0f896 | 6622 | } |
0dfbf9d7 L |
6623 | if (!operand_type_equal (&overlap, &imm8) |
6624 | && !operand_type_equal (&overlap, &imm8s) | |
6625 | && !operand_type_equal (&overlap, &imm16) | |
6626 | && !operand_type_equal (&overlap, &imm32) | |
6627 | && !operand_type_equal (&overlap, &imm32s) | |
6628 | && !operand_type_equal (&overlap, &imm64)) | |
29b0f896 | 6629 | { |
4eed87de AM |
6630 | as_bad (_("no instruction mnemonic suffix given; " |
6631 | "can't determine immediate size")); | |
29b0f896 AM |
6632 | return 0; |
6633 | } | |
6634 | } | |
40fb9820 | 6635 | i.types[j] = overlap; |
29b0f896 | 6636 | |
40fb9820 L |
6637 | return 1; |
6638 | } | |
6639 | ||
6640 | static int | |
6641 | finalize_imm (void) | |
6642 | { | |
bc0844ae | 6643 | unsigned int j, n; |
29b0f896 | 6644 | |
bc0844ae L |
6645 | /* Update the first 2 immediate operands. */ |
6646 | n = i.operands > 2 ? 2 : i.operands; | |
6647 | if (n) | |
6648 | { | |
6649 | for (j = 0; j < n; j++) | |
6650 | if (update_imm (j) == 0) | |
6651 | return 0; | |
40fb9820 | 6652 | |
bc0844ae L |
6653 | /* The 3rd operand can't be immediate operand. */ |
6654 | gas_assert (operand_type_check (i.types[2], imm) == 0); | |
6655 | } | |
29b0f896 AM |
6656 | |
6657 | return 1; | |
6658 | } | |
6659 | ||
6660 | static int | |
e3bb37b5 | 6661 | process_operands (void) |
29b0f896 AM |
6662 | { |
6663 | /* Default segment register this instruction will use for memory | |
6664 | accesses. 0 means unknown. This is only for optimizing out | |
6665 | unnecessary segment overrides. */ | |
6666 | const seg_entry *default_seg = 0; | |
6667 | ||
2426c15f | 6668 | if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv) |
29b0f896 | 6669 | { |
91d6fa6a NC |
6670 | unsigned int dupl = i.operands; |
6671 | unsigned int dest = dupl - 1; | |
9fcfb3d7 L |
6672 | unsigned int j; |
6673 | ||
c0f3af97 | 6674 | /* The destination must be an xmm register. */ |
9c2799c2 | 6675 | gas_assert (i.reg_operands |
91d6fa6a | 6676 | && MAX_OPERANDS > dupl |
7ab9ffdd | 6677 | && operand_type_equal (&i.types[dest], ®xmm)); |
c0f3af97 | 6678 | |
1b54b8d7 JB |
6679 | if (i.tm.operand_types[0].bitfield.acc |
6680 | && i.tm.operand_types[0].bitfield.xmmword) | |
e2ec9d29 | 6681 | { |
8cd7925b | 6682 | if (i.tm.opcode_modifier.vexsources == VEX3SOURCES) |
c0f3af97 L |
6683 | { |
6684 | /* Keep xmm0 for instructions with VEX prefix and 3 | |
6685 | sources. */ | |
1b54b8d7 JB |
6686 | i.tm.operand_types[0].bitfield.acc = 0; |
6687 | i.tm.operand_types[0].bitfield.regsimd = 1; | |
c0f3af97 L |
6688 | goto duplicate; |
6689 | } | |
e2ec9d29 | 6690 | else |
c0f3af97 L |
6691 | { |
6692 | /* We remove the first xmm0 and keep the number of | |
6693 | operands unchanged, which in fact duplicates the | |
6694 | destination. */ | |
6695 | for (j = 1; j < i.operands; j++) | |
6696 | { | |
6697 | i.op[j - 1] = i.op[j]; | |
6698 | i.types[j - 1] = i.types[j]; | |
6699 | i.tm.operand_types[j - 1] = i.tm.operand_types[j]; | |
6700 | } | |
6701 | } | |
6702 | } | |
6703 | else if (i.tm.opcode_modifier.implicit1stxmm0) | |
7ab9ffdd | 6704 | { |
91d6fa6a | 6705 | gas_assert ((MAX_OPERANDS - 1) > dupl |
8cd7925b L |
6706 | && (i.tm.opcode_modifier.vexsources |
6707 | == VEX3SOURCES)); | |
c0f3af97 L |
6708 | |
6709 | /* Add the implicit xmm0 for instructions with VEX prefix | |
6710 | and 3 sources. */ | |
6711 | for (j = i.operands; j > 0; j--) | |
6712 | { | |
6713 | i.op[j] = i.op[j - 1]; | |
6714 | i.types[j] = i.types[j - 1]; | |
6715 | i.tm.operand_types[j] = i.tm.operand_types[j - 1]; | |
6716 | } | |
6717 | i.op[0].regs | |
6718 | = (const reg_entry *) hash_find (reg_hash, "xmm0"); | |
7ab9ffdd | 6719 | i.types[0] = regxmm; |
c0f3af97 L |
6720 | i.tm.operand_types[0] = regxmm; |
6721 | ||
6722 | i.operands += 2; | |
6723 | i.reg_operands += 2; | |
6724 | i.tm.operands += 2; | |
6725 | ||
91d6fa6a | 6726 | dupl++; |
c0f3af97 | 6727 | dest++; |
91d6fa6a NC |
6728 | i.op[dupl] = i.op[dest]; |
6729 | i.types[dupl] = i.types[dest]; | |
6730 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
e2ec9d29 | 6731 | } |
c0f3af97 L |
6732 | else |
6733 | { | |
6734 | duplicate: | |
6735 | i.operands++; | |
6736 | i.reg_operands++; | |
6737 | i.tm.operands++; | |
6738 | ||
91d6fa6a NC |
6739 | i.op[dupl] = i.op[dest]; |
6740 | i.types[dupl] = i.types[dest]; | |
6741 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
c0f3af97 L |
6742 | } |
6743 | ||
6744 | if (i.tm.opcode_modifier.immext) | |
6745 | process_immext (); | |
6746 | } | |
1b54b8d7 JB |
6747 | else if (i.tm.operand_types[0].bitfield.acc |
6748 | && i.tm.operand_types[0].bitfield.xmmword) | |
c0f3af97 L |
6749 | { |
6750 | unsigned int j; | |
6751 | ||
9fcfb3d7 L |
6752 | for (j = 1; j < i.operands; j++) |
6753 | { | |
6754 | i.op[j - 1] = i.op[j]; | |
6755 | i.types[j - 1] = i.types[j]; | |
6756 | ||
6757 | /* We need to adjust fields in i.tm since they are used by | |
6758 | build_modrm_byte. */ | |
6759 | i.tm.operand_types [j - 1] = i.tm.operand_types [j]; | |
6760 | } | |
6761 | ||
e2ec9d29 L |
6762 | i.operands--; |
6763 | i.reg_operands--; | |
e2ec9d29 L |
6764 | i.tm.operands--; |
6765 | } | |
920d2ddc IT |
6766 | else if (i.tm.opcode_modifier.implicitquadgroup) |
6767 | { | |
a477a8c4 JB |
6768 | unsigned int regnum, first_reg_in_group, last_reg_in_group; |
6769 | ||
920d2ddc | 6770 | /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */ |
10c17abd | 6771 | gas_assert (i.operands >= 2 && i.types[1].bitfield.regsimd); |
a477a8c4 JB |
6772 | regnum = register_number (i.op[1].regs); |
6773 | first_reg_in_group = regnum & ~3; | |
6774 | last_reg_in_group = first_reg_in_group + 3; | |
6775 | if (regnum != first_reg_in_group) | |
6776 | as_warn (_("source register `%s%s' implicitly denotes" | |
6777 | " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"), | |
6778 | register_prefix, i.op[1].regs->reg_name, | |
6779 | register_prefix, i.op[1].regs->reg_name, first_reg_in_group, | |
6780 | register_prefix, i.op[1].regs->reg_name, last_reg_in_group, | |
6781 | i.tm.name); | |
6782 | } | |
e2ec9d29 L |
6783 | else if (i.tm.opcode_modifier.regkludge) |
6784 | { | |
6785 | /* The imul $imm, %reg instruction is converted into | |
6786 | imul $imm, %reg, %reg, and the clr %reg instruction | |
6787 | is converted into xor %reg, %reg. */ | |
6788 | ||
6789 | unsigned int first_reg_op; | |
6790 | ||
6791 | if (operand_type_check (i.types[0], reg)) | |
6792 | first_reg_op = 0; | |
6793 | else | |
6794 | first_reg_op = 1; | |
6795 | /* Pretend we saw the extra register operand. */ | |
9c2799c2 | 6796 | gas_assert (i.reg_operands == 1 |
7ab9ffdd | 6797 | && i.op[first_reg_op + 1].regs == 0); |
e2ec9d29 L |
6798 | i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; |
6799 | i.types[first_reg_op + 1] = i.types[first_reg_op]; | |
6800 | i.operands++; | |
6801 | i.reg_operands++; | |
29b0f896 AM |
6802 | } |
6803 | ||
40fb9820 | 6804 | if (i.tm.opcode_modifier.shortform) |
29b0f896 | 6805 | { |
40fb9820 L |
6806 | if (i.types[0].bitfield.sreg2 |
6807 | || i.types[0].bitfield.sreg3) | |
29b0f896 | 6808 | { |
4eed87de AM |
6809 | if (i.tm.base_opcode == POP_SEG_SHORT |
6810 | && i.op[0].regs->reg_num == 1) | |
29b0f896 | 6811 | { |
a87af027 | 6812 | as_bad (_("you can't `pop %scs'"), register_prefix); |
4eed87de | 6813 | return 0; |
29b0f896 | 6814 | } |
4eed87de AM |
6815 | i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); |
6816 | if ((i.op[0].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 6817 | i.rex |= REX_B; |
4eed87de AM |
6818 | } |
6819 | else | |
6820 | { | |
7ab9ffdd | 6821 | /* The register or float register operand is in operand |
85f10a01 | 6822 | 0 or 1. */ |
40fb9820 | 6823 | unsigned int op; |
7ab9ffdd | 6824 | |
ca0d63fe | 6825 | if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte) |
7ab9ffdd L |
6826 | || operand_type_check (i.types[0], reg)) |
6827 | op = 0; | |
6828 | else | |
6829 | op = 1; | |
4eed87de AM |
6830 | /* Register goes in low 3 bits of opcode. */ |
6831 | i.tm.base_opcode |= i.op[op].regs->reg_num; | |
6832 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 6833 | i.rex |= REX_B; |
40fb9820 | 6834 | if (!quiet_warnings && i.tm.opcode_modifier.ugh) |
29b0f896 | 6835 | { |
4eed87de AM |
6836 | /* Warn about some common errors, but press on regardless. |
6837 | The first case can be generated by gcc (<= 2.8.1). */ | |
6838 | if (i.operands == 2) | |
6839 | { | |
6840 | /* Reversed arguments on faddp, fsubp, etc. */ | |
a540244d | 6841 | as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name, |
d8a1b51e JB |
6842 | register_prefix, i.op[!intel_syntax].regs->reg_name, |
6843 | register_prefix, i.op[intel_syntax].regs->reg_name); | |
4eed87de AM |
6844 | } |
6845 | else | |
6846 | { | |
6847 | /* Extraneous `l' suffix on fp insn. */ | |
a540244d L |
6848 | as_warn (_("translating to `%s %s%s'"), i.tm.name, |
6849 | register_prefix, i.op[0].regs->reg_name); | |
4eed87de | 6850 | } |
29b0f896 AM |
6851 | } |
6852 | } | |
6853 | } | |
40fb9820 | 6854 | else if (i.tm.opcode_modifier.modrm) |
29b0f896 AM |
6855 | { |
6856 | /* The opcode is completed (modulo i.tm.extension_opcode which | |
52271982 AM |
6857 | must be put into the modrm byte). Now, we make the modrm and |
6858 | index base bytes based on all the info we've collected. */ | |
29b0f896 AM |
6859 | |
6860 | default_seg = build_modrm_byte (); | |
6861 | } | |
8a2ed489 | 6862 | else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32) |
29b0f896 AM |
6863 | { |
6864 | default_seg = &ds; | |
6865 | } | |
40fb9820 | 6866 | else if (i.tm.opcode_modifier.isstring) |
29b0f896 AM |
6867 | { |
6868 | /* For the string instructions that allow a segment override | |
6869 | on one of their operands, the default segment is ds. */ | |
6870 | default_seg = &ds; | |
6871 | } | |
6872 | ||
75178d9d L |
6873 | if (i.tm.base_opcode == 0x8d /* lea */ |
6874 | && i.seg[0] | |
6875 | && !quiet_warnings) | |
30123838 | 6876 | as_warn (_("segment override on `%s' is ineffectual"), i.tm.name); |
52271982 AM |
6877 | |
6878 | /* If a segment was explicitly specified, and the specified segment | |
6879 | is not the default, use an opcode prefix to select it. If we | |
6880 | never figured out what the default segment is, then default_seg | |
6881 | will be zero at this point, and the specified segment prefix will | |
6882 | always be used. */ | |
29b0f896 AM |
6883 | if ((i.seg[0]) && (i.seg[0] != default_seg)) |
6884 | { | |
6885 | if (!add_prefix (i.seg[0]->seg_prefix)) | |
6886 | return 0; | |
6887 | } | |
6888 | return 1; | |
6889 | } | |
6890 | ||
6891 | static const seg_entry * | |
e3bb37b5 | 6892 | build_modrm_byte (void) |
29b0f896 AM |
6893 | { |
6894 | const seg_entry *default_seg = 0; | |
c0f3af97 | 6895 | unsigned int source, dest; |
8cd7925b | 6896 | int vex_3_sources; |
c0f3af97 | 6897 | |
8cd7925b | 6898 | vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES; |
c0f3af97 L |
6899 | if (vex_3_sources) |
6900 | { | |
91d6fa6a | 6901 | unsigned int nds, reg_slot; |
4c2c6516 | 6902 | expressionS *exp; |
c0f3af97 | 6903 | |
6b8d3588 | 6904 | dest = i.operands - 1; |
c0f3af97 | 6905 | nds = dest - 1; |
922d8de8 | 6906 | |
a683cc34 | 6907 | /* There are 2 kinds of instructions: |
bed3d976 JB |
6908 | 1. 5 operands: 4 register operands or 3 register operands |
6909 | plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and | |
6910 | VexW0 or VexW1. The destination must be either XMM, YMM or | |
43234a1e | 6911 | ZMM register. |
bed3d976 | 6912 | 2. 4 operands: 4 register operands or 3 register operands |
2f1bada2 | 6913 | plus 1 memory operand, with VexXDS. */ |
922d8de8 | 6914 | gas_assert ((i.reg_operands == 4 |
bed3d976 JB |
6915 | || (i.reg_operands == 3 && i.mem_operands == 1)) |
6916 | && i.tm.opcode_modifier.vexvvvv == VEXXDS | |
dcd7e323 JB |
6917 | && i.tm.opcode_modifier.vexw |
6918 | && i.tm.operand_types[dest].bitfield.regsimd); | |
a683cc34 | 6919 | |
48db9223 JB |
6920 | /* If VexW1 is set, the first non-immediate operand is the source and |
6921 | the second non-immediate one is encoded in the immediate operand. */ | |
6922 | if (i.tm.opcode_modifier.vexw == VEXW1) | |
6923 | { | |
6924 | source = i.imm_operands; | |
6925 | reg_slot = i.imm_operands + 1; | |
6926 | } | |
6927 | else | |
6928 | { | |
6929 | source = i.imm_operands + 1; | |
6930 | reg_slot = i.imm_operands; | |
6931 | } | |
6932 | ||
a683cc34 | 6933 | if (i.imm_operands == 0) |
bed3d976 JB |
6934 | { |
6935 | /* When there is no immediate operand, generate an 8bit | |
6936 | immediate operand to encode the first operand. */ | |
6937 | exp = &im_expressions[i.imm_operands++]; | |
6938 | i.op[i.operands].imms = exp; | |
6939 | i.types[i.operands] = imm8; | |
6940 | i.operands++; | |
6941 | ||
6942 | gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd); | |
6943 | exp->X_op = O_constant; | |
6944 | exp->X_add_number = register_number (i.op[reg_slot].regs) << 4; | |
43234a1e L |
6945 | gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); |
6946 | } | |
922d8de8 | 6947 | else |
bed3d976 JB |
6948 | { |
6949 | unsigned int imm_slot; | |
a683cc34 | 6950 | |
2f1bada2 JB |
6951 | gas_assert (i.imm_operands == 1 && i.types[0].bitfield.vec_imm4); |
6952 | ||
bed3d976 JB |
6953 | if (i.tm.opcode_modifier.immext) |
6954 | { | |
6955 | /* When ImmExt is set, the immediate byte is the last | |
6956 | operand. */ | |
6957 | imm_slot = i.operands - 1; | |
6958 | source--; | |
6959 | reg_slot--; | |
6960 | } | |
6961 | else | |
6962 | { | |
6963 | imm_slot = 0; | |
6964 | ||
6965 | /* Turn on Imm8 so that output_imm will generate it. */ | |
6966 | i.types[imm_slot].bitfield.imm8 = 1; | |
6967 | } | |
6968 | ||
6969 | gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd); | |
6970 | i.op[imm_slot].imms->X_add_number | |
6971 | |= register_number (i.op[reg_slot].regs) << 4; | |
43234a1e | 6972 | gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); |
bed3d976 | 6973 | } |
a683cc34 | 6974 | |
10c17abd | 6975 | gas_assert (i.tm.operand_types[nds].bitfield.regsimd); |
dae39acc | 6976 | i.vex.register_specifier = i.op[nds].regs; |
c0f3af97 L |
6977 | } |
6978 | else | |
6979 | source = dest = 0; | |
29b0f896 AM |
6980 | |
6981 | /* i.reg_operands MUST be the number of real register operands; | |
c0f3af97 L |
6982 | implicit registers do not count. If there are 3 register |
6983 | operands, it must be a instruction with VexNDS. For a | |
6984 | instruction with VexNDD, the destination register is encoded | |
6985 | in VEX prefix. If there are 4 register operands, it must be | |
6986 | a instruction with VEX prefix and 3 sources. */ | |
7ab9ffdd L |
6987 | if (i.mem_operands == 0 |
6988 | && ((i.reg_operands == 2 | |
2426c15f | 6989 | && i.tm.opcode_modifier.vexvvvv <= VEXXDS) |
7ab9ffdd | 6990 | || (i.reg_operands == 3 |
2426c15f | 6991 | && i.tm.opcode_modifier.vexvvvv == VEXXDS) |
7ab9ffdd | 6992 | || (i.reg_operands == 4 && vex_3_sources))) |
29b0f896 | 6993 | { |
cab737b9 L |
6994 | switch (i.operands) |
6995 | { | |
6996 | case 2: | |
6997 | source = 0; | |
6998 | break; | |
6999 | case 3: | |
c81128dc L |
7000 | /* When there are 3 operands, one of them may be immediate, |
7001 | which may be the first or the last operand. Otherwise, | |
c0f3af97 L |
7002 | the first operand must be shift count register (cl) or it |
7003 | is an instruction with VexNDS. */ | |
9c2799c2 | 7004 | gas_assert (i.imm_operands == 1 |
7ab9ffdd | 7005 | || (i.imm_operands == 0 |
2426c15f | 7006 | && (i.tm.opcode_modifier.vexvvvv == VEXXDS |
7ab9ffdd | 7007 | || i.types[0].bitfield.shiftcount))); |
40fb9820 L |
7008 | if (operand_type_check (i.types[0], imm) |
7009 | || i.types[0].bitfield.shiftcount) | |
7010 | source = 1; | |
7011 | else | |
7012 | source = 0; | |
cab737b9 L |
7013 | break; |
7014 | case 4: | |
368d64cc L |
7015 | /* When there are 4 operands, the first two must be 8bit |
7016 | immediate operands. The source operand will be the 3rd | |
c0f3af97 L |
7017 | one. |
7018 | ||
7019 | For instructions with VexNDS, if the first operand | |
7020 | an imm8, the source operand is the 2nd one. If the last | |
7021 | operand is imm8, the source operand is the first one. */ | |
9c2799c2 | 7022 | gas_assert ((i.imm_operands == 2 |
7ab9ffdd L |
7023 | && i.types[0].bitfield.imm8 |
7024 | && i.types[1].bitfield.imm8) | |
2426c15f | 7025 | || (i.tm.opcode_modifier.vexvvvv == VEXXDS |
7ab9ffdd L |
7026 | && i.imm_operands == 1 |
7027 | && (i.types[0].bitfield.imm8 | |
43234a1e L |
7028 | || i.types[i.operands - 1].bitfield.imm8 |
7029 | || i.rounding))); | |
9f2670f2 L |
7030 | if (i.imm_operands == 2) |
7031 | source = 2; | |
7032 | else | |
c0f3af97 L |
7033 | { |
7034 | if (i.types[0].bitfield.imm8) | |
7035 | source = 1; | |
7036 | else | |
7037 | source = 0; | |
7038 | } | |
c0f3af97 L |
7039 | break; |
7040 | case 5: | |
e771e7c9 | 7041 | if (is_evex_encoding (&i.tm)) |
43234a1e L |
7042 | { |
7043 | /* For EVEX instructions, when there are 5 operands, the | |
7044 | first one must be immediate operand. If the second one | |
7045 | is immediate operand, the source operand is the 3th | |
7046 | one. If the last one is immediate operand, the source | |
7047 | operand is the 2nd one. */ | |
7048 | gas_assert (i.imm_operands == 2 | |
7049 | && i.tm.opcode_modifier.sae | |
7050 | && operand_type_check (i.types[0], imm)); | |
7051 | if (operand_type_check (i.types[1], imm)) | |
7052 | source = 2; | |
7053 | else if (operand_type_check (i.types[4], imm)) | |
7054 | source = 1; | |
7055 | else | |
7056 | abort (); | |
7057 | } | |
cab737b9 L |
7058 | break; |
7059 | default: | |
7060 | abort (); | |
7061 | } | |
7062 | ||
c0f3af97 L |
7063 | if (!vex_3_sources) |
7064 | { | |
7065 | dest = source + 1; | |
7066 | ||
43234a1e L |
7067 | /* RC/SAE operand could be between DEST and SRC. That happens |
7068 | when one operand is GPR and the other one is XMM/YMM/ZMM | |
7069 | register. */ | |
7070 | if (i.rounding && i.rounding->operand == (int) dest) | |
7071 | dest++; | |
7072 | ||
2426c15f | 7073 | if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
c0f3af97 | 7074 | { |
43234a1e | 7075 | /* For instructions with VexNDS, the register-only source |
c5d0745b | 7076 | operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask |
43234a1e L |
7077 | register. It is encoded in VEX prefix. We need to |
7078 | clear RegMem bit before calling operand_type_equal. */ | |
f12dc422 L |
7079 | |
7080 | i386_operand_type op; | |
7081 | unsigned int vvvv; | |
7082 | ||
7083 | /* Check register-only source operand when two source | |
7084 | operands are swapped. */ | |
7085 | if (!i.tm.operand_types[source].bitfield.baseindex | |
7086 | && i.tm.operand_types[dest].bitfield.baseindex) | |
7087 | { | |
7088 | vvvv = source; | |
7089 | source = dest; | |
7090 | } | |
7091 | else | |
7092 | vvvv = dest; | |
7093 | ||
7094 | op = i.tm.operand_types[vvvv]; | |
fa99fab2 | 7095 | op.bitfield.regmem = 0; |
c0f3af97 | 7096 | if ((dest + 1) >= i.operands |
dc821c5f JB |
7097 | || ((!op.bitfield.reg |
7098 | || (!op.bitfield.dword && !op.bitfield.qword)) | |
10c17abd | 7099 | && !op.bitfield.regsimd |
43234a1e | 7100 | && !operand_type_equal (&op, ®mask))) |
c0f3af97 | 7101 | abort (); |
f12dc422 | 7102 | i.vex.register_specifier = i.op[vvvv].regs; |
c0f3af97 L |
7103 | dest++; |
7104 | } | |
7105 | } | |
29b0f896 AM |
7106 | |
7107 | i.rm.mode = 3; | |
7108 | /* One of the register operands will be encoded in the i.tm.reg | |
7109 | field, the other in the combined i.tm.mode and i.tm.regmem | |
7110 | fields. If no form of this instruction supports a memory | |
7111 | destination operand, then we assume the source operand may | |
7112 | sometimes be a memory operand and so we need to store the | |
7113 | destination in the i.rm.reg field. */ | |
40fb9820 L |
7114 | if (!i.tm.operand_types[dest].bitfield.regmem |
7115 | && operand_type_check (i.tm.operand_types[dest], anymem) == 0) | |
29b0f896 AM |
7116 | { |
7117 | i.rm.reg = i.op[dest].regs->reg_num; | |
7118 | i.rm.regmem = i.op[source].regs->reg_num; | |
b4a3a7b4 L |
7119 | if (i.op[dest].regs->reg_type.bitfield.regmmx |
7120 | || i.op[source].regs->reg_type.bitfield.regmmx) | |
7121 | i.has_regmmx = TRUE; | |
7122 | else if (i.op[dest].regs->reg_type.bitfield.regsimd | |
7123 | || i.op[source].regs->reg_type.bitfield.regsimd) | |
7124 | { | |
7125 | if (i.types[dest].bitfield.zmmword | |
7126 | || i.types[source].bitfield.zmmword) | |
7127 | i.has_regzmm = TRUE; | |
7128 | else if (i.types[dest].bitfield.ymmword | |
7129 | || i.types[source].bitfield.ymmword) | |
7130 | i.has_regymm = TRUE; | |
7131 | else | |
7132 | i.has_regxmm = TRUE; | |
7133 | } | |
29b0f896 | 7134 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) |
161a04f6 | 7135 | i.rex |= REX_R; |
43234a1e L |
7136 | if ((i.op[dest].regs->reg_flags & RegVRex) != 0) |
7137 | i.vrex |= REX_R; | |
29b0f896 | 7138 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
161a04f6 | 7139 | i.rex |= REX_B; |
43234a1e L |
7140 | if ((i.op[source].regs->reg_flags & RegVRex) != 0) |
7141 | i.vrex |= REX_B; | |
29b0f896 AM |
7142 | } |
7143 | else | |
7144 | { | |
7145 | i.rm.reg = i.op[source].regs->reg_num; | |
7146 | i.rm.regmem = i.op[dest].regs->reg_num; | |
7147 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 7148 | i.rex |= REX_B; |
43234a1e L |
7149 | if ((i.op[dest].regs->reg_flags & RegVRex) != 0) |
7150 | i.vrex |= REX_B; | |
29b0f896 | 7151 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
161a04f6 | 7152 | i.rex |= REX_R; |
43234a1e L |
7153 | if ((i.op[source].regs->reg_flags & RegVRex) != 0) |
7154 | i.vrex |= REX_R; | |
29b0f896 | 7155 | } |
e0c7f900 | 7156 | if (flag_code != CODE_64BIT && (i.rex & REX_R)) |
c4a530c5 | 7157 | { |
e0c7f900 | 7158 | if (!i.types[i.tm.operand_types[0].bitfield.regmem].bitfield.control) |
c4a530c5 | 7159 | abort (); |
e0c7f900 | 7160 | i.rex &= ~REX_R; |
c4a530c5 JB |
7161 | add_prefix (LOCK_PREFIX_OPCODE); |
7162 | } | |
29b0f896 AM |
7163 | } |
7164 | else | |
7165 | { /* If it's not 2 reg operands... */ | |
c0f3af97 L |
7166 | unsigned int mem; |
7167 | ||
29b0f896 AM |
7168 | if (i.mem_operands) |
7169 | { | |
7170 | unsigned int fake_zero_displacement = 0; | |
99018f42 | 7171 | unsigned int op; |
4eed87de | 7172 | |
7ab9ffdd L |
7173 | for (op = 0; op < i.operands; op++) |
7174 | if (operand_type_check (i.types[op], anymem)) | |
7175 | break; | |
7ab9ffdd | 7176 | gas_assert (op < i.operands); |
29b0f896 | 7177 | |
6c30d220 L |
7178 | if (i.tm.opcode_modifier.vecsib) |
7179 | { | |
e968fc9b | 7180 | if (i.index_reg->reg_num == RegIZ) |
6c30d220 L |
7181 | abort (); |
7182 | ||
7183 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
7184 | if (!i.base_reg) | |
7185 | { | |
7186 | i.sib.base = NO_BASE_REGISTER; | |
7187 | i.sib.scale = i.log2_scale_factor; | |
7188 | i.types[op].bitfield.disp8 = 0; | |
7189 | i.types[op].bitfield.disp16 = 0; | |
7190 | i.types[op].bitfield.disp64 = 0; | |
43083a50 | 7191 | if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX]) |
6c30d220 L |
7192 | { |
7193 | /* Must be 32 bit */ | |
7194 | i.types[op].bitfield.disp32 = 1; | |
7195 | i.types[op].bitfield.disp32s = 0; | |
7196 | } | |
7197 | else | |
7198 | { | |
7199 | i.types[op].bitfield.disp32 = 0; | |
7200 | i.types[op].bitfield.disp32s = 1; | |
7201 | } | |
7202 | } | |
7203 | i.sib.index = i.index_reg->reg_num; | |
7204 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
7205 | i.rex |= REX_X; | |
43234a1e L |
7206 | if ((i.index_reg->reg_flags & RegVRex) != 0) |
7207 | i.vrex |= REX_X; | |
6c30d220 L |
7208 | } |
7209 | ||
29b0f896 AM |
7210 | default_seg = &ds; |
7211 | ||
7212 | if (i.base_reg == 0) | |
7213 | { | |
7214 | i.rm.mode = 0; | |
7215 | if (!i.disp_operands) | |
9bb129e8 | 7216 | fake_zero_displacement = 1; |
29b0f896 AM |
7217 | if (i.index_reg == 0) |
7218 | { | |
73053c1f JB |
7219 | i386_operand_type newdisp; |
7220 | ||
6c30d220 | 7221 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 | 7222 | /* Operand is just <disp> */ |
20f0a1fc | 7223 | if (flag_code == CODE_64BIT) |
29b0f896 AM |
7224 | { |
7225 | /* 64bit mode overwrites the 32bit absolute | |
7226 | addressing by RIP relative addressing and | |
7227 | absolute addressing is encoded by one of the | |
7228 | redundant SIB forms. */ | |
7229 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
7230 | i.sib.base = NO_BASE_REGISTER; | |
7231 | i.sib.index = NO_INDEX_REGISTER; | |
73053c1f | 7232 | newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32); |
20f0a1fc | 7233 | } |
fc225355 L |
7234 | else if ((flag_code == CODE_16BIT) |
7235 | ^ (i.prefix[ADDR_PREFIX] != 0)) | |
20f0a1fc NC |
7236 | { |
7237 | i.rm.regmem = NO_BASE_REGISTER_16; | |
73053c1f | 7238 | newdisp = disp16; |
20f0a1fc NC |
7239 | } |
7240 | else | |
7241 | { | |
7242 | i.rm.regmem = NO_BASE_REGISTER; | |
73053c1f | 7243 | newdisp = disp32; |
29b0f896 | 7244 | } |
73053c1f JB |
7245 | i.types[op] = operand_type_and_not (i.types[op], anydisp); |
7246 | i.types[op] = operand_type_or (i.types[op], newdisp); | |
29b0f896 | 7247 | } |
6c30d220 | 7248 | else if (!i.tm.opcode_modifier.vecsib) |
29b0f896 | 7249 | { |
6c30d220 | 7250 | /* !i.base_reg && i.index_reg */ |
e968fc9b | 7251 | if (i.index_reg->reg_num == RegIZ) |
db51cc60 L |
7252 | i.sib.index = NO_INDEX_REGISTER; |
7253 | else | |
7254 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
7255 | i.sib.base = NO_BASE_REGISTER; |
7256 | i.sib.scale = i.log2_scale_factor; | |
7257 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
40fb9820 L |
7258 | i.types[op].bitfield.disp8 = 0; |
7259 | i.types[op].bitfield.disp16 = 0; | |
7260 | i.types[op].bitfield.disp64 = 0; | |
43083a50 | 7261 | if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX]) |
40fb9820 L |
7262 | { |
7263 | /* Must be 32 bit */ | |
7264 | i.types[op].bitfield.disp32 = 1; | |
7265 | i.types[op].bitfield.disp32s = 0; | |
7266 | } | |
29b0f896 | 7267 | else |
40fb9820 L |
7268 | { |
7269 | i.types[op].bitfield.disp32 = 0; | |
7270 | i.types[op].bitfield.disp32s = 1; | |
7271 | } | |
29b0f896 | 7272 | if ((i.index_reg->reg_flags & RegRex) != 0) |
161a04f6 | 7273 | i.rex |= REX_X; |
29b0f896 AM |
7274 | } |
7275 | } | |
7276 | /* RIP addressing for 64bit mode. */ | |
e968fc9b | 7277 | else if (i.base_reg->reg_num == RegIP) |
29b0f896 | 7278 | { |
6c30d220 | 7279 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 | 7280 | i.rm.regmem = NO_BASE_REGISTER; |
40fb9820 L |
7281 | i.types[op].bitfield.disp8 = 0; |
7282 | i.types[op].bitfield.disp16 = 0; | |
7283 | i.types[op].bitfield.disp32 = 0; | |
7284 | i.types[op].bitfield.disp32s = 1; | |
7285 | i.types[op].bitfield.disp64 = 0; | |
71903a11 | 7286 | i.flags[op] |= Operand_PCrel; |
20f0a1fc NC |
7287 | if (! i.disp_operands) |
7288 | fake_zero_displacement = 1; | |
29b0f896 | 7289 | } |
dc821c5f | 7290 | else if (i.base_reg->reg_type.bitfield.word) |
29b0f896 | 7291 | { |
6c30d220 | 7292 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 AM |
7293 | switch (i.base_reg->reg_num) |
7294 | { | |
7295 | case 3: /* (%bx) */ | |
7296 | if (i.index_reg == 0) | |
7297 | i.rm.regmem = 7; | |
7298 | else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ | |
7299 | i.rm.regmem = i.index_reg->reg_num - 6; | |
7300 | break; | |
7301 | case 5: /* (%bp) */ | |
7302 | default_seg = &ss; | |
7303 | if (i.index_reg == 0) | |
7304 | { | |
7305 | i.rm.regmem = 6; | |
40fb9820 | 7306 | if (operand_type_check (i.types[op], disp) == 0) |
29b0f896 AM |
7307 | { |
7308 | /* fake (%bp) into 0(%bp) */ | |
b5014f7a | 7309 | i.types[op].bitfield.disp8 = 1; |
252b5132 | 7310 | fake_zero_displacement = 1; |
29b0f896 AM |
7311 | } |
7312 | } | |
7313 | else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ | |
7314 | i.rm.regmem = i.index_reg->reg_num - 6 + 2; | |
7315 | break; | |
7316 | default: /* (%si) -> 4 or (%di) -> 5 */ | |
7317 | i.rm.regmem = i.base_reg->reg_num - 6 + 4; | |
7318 | } | |
7319 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
7320 | } | |
7321 | else /* i.base_reg and 32/64 bit mode */ | |
7322 | { | |
7323 | if (flag_code == CODE_64BIT | |
40fb9820 L |
7324 | && operand_type_check (i.types[op], disp)) |
7325 | { | |
73053c1f JB |
7326 | i.types[op].bitfield.disp16 = 0; |
7327 | i.types[op].bitfield.disp64 = 0; | |
40fb9820 | 7328 | if (i.prefix[ADDR_PREFIX] == 0) |
73053c1f JB |
7329 | { |
7330 | i.types[op].bitfield.disp32 = 0; | |
7331 | i.types[op].bitfield.disp32s = 1; | |
7332 | } | |
40fb9820 | 7333 | else |
73053c1f JB |
7334 | { |
7335 | i.types[op].bitfield.disp32 = 1; | |
7336 | i.types[op].bitfield.disp32s = 0; | |
7337 | } | |
40fb9820 | 7338 | } |
20f0a1fc | 7339 | |
6c30d220 L |
7340 | if (!i.tm.opcode_modifier.vecsib) |
7341 | i.rm.regmem = i.base_reg->reg_num; | |
29b0f896 | 7342 | if ((i.base_reg->reg_flags & RegRex) != 0) |
161a04f6 | 7343 | i.rex |= REX_B; |
29b0f896 AM |
7344 | i.sib.base = i.base_reg->reg_num; |
7345 | /* x86-64 ignores REX prefix bit here to avoid decoder | |
7346 | complications. */ | |
848930b2 JB |
7347 | if (!(i.base_reg->reg_flags & RegRex) |
7348 | && (i.base_reg->reg_num == EBP_REG_NUM | |
7349 | || i.base_reg->reg_num == ESP_REG_NUM)) | |
29b0f896 | 7350 | default_seg = &ss; |
848930b2 | 7351 | if (i.base_reg->reg_num == 5 && i.disp_operands == 0) |
29b0f896 | 7352 | { |
848930b2 | 7353 | fake_zero_displacement = 1; |
b5014f7a | 7354 | i.types[op].bitfield.disp8 = 1; |
29b0f896 AM |
7355 | } |
7356 | i.sib.scale = i.log2_scale_factor; | |
7357 | if (i.index_reg == 0) | |
7358 | { | |
6c30d220 | 7359 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 AM |
7360 | /* <disp>(%esp) becomes two byte modrm with no index |
7361 | register. We've already stored the code for esp | |
7362 | in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. | |
7363 | Any base register besides %esp will not use the | |
7364 | extra modrm byte. */ | |
7365 | i.sib.index = NO_INDEX_REGISTER; | |
29b0f896 | 7366 | } |
6c30d220 | 7367 | else if (!i.tm.opcode_modifier.vecsib) |
29b0f896 | 7368 | { |
e968fc9b | 7369 | if (i.index_reg->reg_num == RegIZ) |
db51cc60 L |
7370 | i.sib.index = NO_INDEX_REGISTER; |
7371 | else | |
7372 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
7373 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
7374 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
161a04f6 | 7375 | i.rex |= REX_X; |
29b0f896 | 7376 | } |
67a4f2b7 AO |
7377 | |
7378 | if (i.disp_operands | |
7379 | && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL | |
7380 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)) | |
7381 | i.rm.mode = 0; | |
7382 | else | |
a501d77e L |
7383 | { |
7384 | if (!fake_zero_displacement | |
7385 | && !i.disp_operands | |
7386 | && i.disp_encoding) | |
7387 | { | |
7388 | fake_zero_displacement = 1; | |
7389 | if (i.disp_encoding == disp_encoding_8bit) | |
7390 | i.types[op].bitfield.disp8 = 1; | |
7391 | else | |
7392 | i.types[op].bitfield.disp32 = 1; | |
7393 | } | |
7394 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
7395 | } | |
29b0f896 | 7396 | } |
252b5132 | 7397 | |
29b0f896 AM |
7398 | if (fake_zero_displacement) |
7399 | { | |
7400 | /* Fakes a zero displacement assuming that i.types[op] | |
7401 | holds the correct displacement size. */ | |
7402 | expressionS *exp; | |
7403 | ||
9c2799c2 | 7404 | gas_assert (i.op[op].disps == 0); |
29b0f896 AM |
7405 | exp = &disp_expressions[i.disp_operands++]; |
7406 | i.op[op].disps = exp; | |
7407 | exp->X_op = O_constant; | |
7408 | exp->X_add_number = 0; | |
7409 | exp->X_add_symbol = (symbolS *) 0; | |
7410 | exp->X_op_symbol = (symbolS *) 0; | |
7411 | } | |
c0f3af97 L |
7412 | |
7413 | mem = op; | |
29b0f896 | 7414 | } |
c0f3af97 L |
7415 | else |
7416 | mem = ~0; | |
252b5132 | 7417 | |
8c43a48b | 7418 | if (i.tm.opcode_modifier.vexsources == XOP2SOURCES) |
5dd85c99 SP |
7419 | { |
7420 | if (operand_type_check (i.types[0], imm)) | |
7421 | i.vex.register_specifier = NULL; | |
7422 | else | |
7423 | { | |
7424 | /* VEX.vvvv encodes one of the sources when the first | |
7425 | operand is not an immediate. */ | |
1ef99a7b | 7426 | if (i.tm.opcode_modifier.vexw == VEXW0) |
5dd85c99 SP |
7427 | i.vex.register_specifier = i.op[0].regs; |
7428 | else | |
7429 | i.vex.register_specifier = i.op[1].regs; | |
7430 | } | |
7431 | ||
7432 | /* Destination is a XMM register encoded in the ModRM.reg | |
7433 | and VEX.R bit. */ | |
7434 | i.rm.reg = i.op[2].regs->reg_num; | |
7435 | if ((i.op[2].regs->reg_flags & RegRex) != 0) | |
7436 | i.rex |= REX_R; | |
7437 | ||
7438 | /* ModRM.rm and VEX.B encodes the other source. */ | |
7439 | if (!i.mem_operands) | |
7440 | { | |
7441 | i.rm.mode = 3; | |
7442 | ||
1ef99a7b | 7443 | if (i.tm.opcode_modifier.vexw == VEXW0) |
5dd85c99 SP |
7444 | i.rm.regmem = i.op[1].regs->reg_num; |
7445 | else | |
7446 | i.rm.regmem = i.op[0].regs->reg_num; | |
7447 | ||
7448 | if ((i.op[1].regs->reg_flags & RegRex) != 0) | |
7449 | i.rex |= REX_B; | |
7450 | } | |
7451 | } | |
2426c15f | 7452 | else if (i.tm.opcode_modifier.vexvvvv == VEXLWP) |
f88c9eb0 SP |
7453 | { |
7454 | i.vex.register_specifier = i.op[2].regs; | |
7455 | if (!i.mem_operands) | |
7456 | { | |
7457 | i.rm.mode = 3; | |
7458 | i.rm.regmem = i.op[1].regs->reg_num; | |
7459 | if ((i.op[1].regs->reg_flags & RegRex) != 0) | |
7460 | i.rex |= REX_B; | |
7461 | } | |
7462 | } | |
29b0f896 AM |
7463 | /* Fill in i.rm.reg or i.rm.regmem field with register operand |
7464 | (if any) based on i.tm.extension_opcode. Again, we must be | |
7465 | careful to make sure that segment/control/debug/test/MMX | |
7466 | registers are coded into the i.rm.reg field. */ | |
f88c9eb0 | 7467 | else if (i.reg_operands) |
29b0f896 | 7468 | { |
99018f42 | 7469 | unsigned int op; |
7ab9ffdd L |
7470 | unsigned int vex_reg = ~0; |
7471 | ||
7472 | for (op = 0; op < i.operands; op++) | |
b4a3a7b4 L |
7473 | { |
7474 | if (i.types[op].bitfield.reg | |
7475 | || i.types[op].bitfield.regbnd | |
7476 | || i.types[op].bitfield.regmask | |
7477 | || i.types[op].bitfield.sreg2 | |
7478 | || i.types[op].bitfield.sreg3 | |
7479 | || i.types[op].bitfield.control | |
7480 | || i.types[op].bitfield.debug | |
7481 | || i.types[op].bitfield.test) | |
7482 | break; | |
7483 | if (i.types[op].bitfield.regsimd) | |
7484 | { | |
7485 | if (i.types[op].bitfield.zmmword) | |
7486 | i.has_regzmm = TRUE; | |
7487 | else if (i.types[op].bitfield.ymmword) | |
7488 | i.has_regymm = TRUE; | |
7489 | else | |
7490 | i.has_regxmm = TRUE; | |
7491 | break; | |
7492 | } | |
7493 | if (i.types[op].bitfield.regmmx) | |
7494 | { | |
7495 | i.has_regmmx = TRUE; | |
7496 | break; | |
7497 | } | |
7498 | } | |
c0209578 | 7499 | |
7ab9ffdd L |
7500 | if (vex_3_sources) |
7501 | op = dest; | |
2426c15f | 7502 | else if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
7ab9ffdd L |
7503 | { |
7504 | /* For instructions with VexNDS, the register-only | |
7505 | source operand is encoded in VEX prefix. */ | |
7506 | gas_assert (mem != (unsigned int) ~0); | |
c0f3af97 | 7507 | |
7ab9ffdd | 7508 | if (op > mem) |
c0f3af97 | 7509 | { |
7ab9ffdd L |
7510 | vex_reg = op++; |
7511 | gas_assert (op < i.operands); | |
c0f3af97 L |
7512 | } |
7513 | else | |
c0f3af97 | 7514 | { |
f12dc422 L |
7515 | /* Check register-only source operand when two source |
7516 | operands are swapped. */ | |
7517 | if (!i.tm.operand_types[op].bitfield.baseindex | |
7518 | && i.tm.operand_types[op + 1].bitfield.baseindex) | |
7519 | { | |
7520 | vex_reg = op; | |
7521 | op += 2; | |
7522 | gas_assert (mem == (vex_reg + 1) | |
7523 | && op < i.operands); | |
7524 | } | |
7525 | else | |
7526 | { | |
7527 | vex_reg = op + 1; | |
7528 | gas_assert (vex_reg < i.operands); | |
7529 | } | |
c0f3af97 | 7530 | } |
7ab9ffdd | 7531 | } |
2426c15f | 7532 | else if (i.tm.opcode_modifier.vexvvvv == VEXNDD) |
7ab9ffdd | 7533 | { |
f12dc422 | 7534 | /* For instructions with VexNDD, the register destination |
7ab9ffdd | 7535 | is encoded in VEX prefix. */ |
f12dc422 L |
7536 | if (i.mem_operands == 0) |
7537 | { | |
7538 | /* There is no memory operand. */ | |
7539 | gas_assert ((op + 2) == i.operands); | |
7540 | vex_reg = op + 1; | |
7541 | } | |
7542 | else | |
8d63c93e | 7543 | { |
ed438a93 JB |
7544 | /* There are only 2 non-immediate operands. */ |
7545 | gas_assert (op < i.imm_operands + 2 | |
7546 | && i.operands == i.imm_operands + 2); | |
7547 | vex_reg = i.imm_operands + 1; | |
f12dc422 | 7548 | } |
7ab9ffdd L |
7549 | } |
7550 | else | |
7551 | gas_assert (op < i.operands); | |
99018f42 | 7552 | |
7ab9ffdd L |
7553 | if (vex_reg != (unsigned int) ~0) |
7554 | { | |
f12dc422 | 7555 | i386_operand_type *type = &i.tm.operand_types[vex_reg]; |
7ab9ffdd | 7556 | |
dc821c5f JB |
7557 | if ((!type->bitfield.reg |
7558 | || (!type->bitfield.dword && !type->bitfield.qword)) | |
10c17abd | 7559 | && !type->bitfield.regsimd |
43234a1e | 7560 | && !operand_type_equal (type, ®mask)) |
7ab9ffdd | 7561 | abort (); |
f88c9eb0 | 7562 | |
7ab9ffdd L |
7563 | i.vex.register_specifier = i.op[vex_reg].regs; |
7564 | } | |
7565 | ||
1b9f0c97 L |
7566 | /* Don't set OP operand twice. */ |
7567 | if (vex_reg != op) | |
7ab9ffdd | 7568 | { |
1b9f0c97 L |
7569 | /* If there is an extension opcode to put here, the |
7570 | register number must be put into the regmem field. */ | |
7571 | if (i.tm.extension_opcode != None) | |
7572 | { | |
7573 | i.rm.regmem = i.op[op].regs->reg_num; | |
7574 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
7575 | i.rex |= REX_B; | |
43234a1e L |
7576 | if ((i.op[op].regs->reg_flags & RegVRex) != 0) |
7577 | i.vrex |= REX_B; | |
1b9f0c97 L |
7578 | } |
7579 | else | |
7580 | { | |
7581 | i.rm.reg = i.op[op].regs->reg_num; | |
7582 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
7583 | i.rex |= REX_R; | |
43234a1e L |
7584 | if ((i.op[op].regs->reg_flags & RegVRex) != 0) |
7585 | i.vrex |= REX_R; | |
1b9f0c97 | 7586 | } |
7ab9ffdd | 7587 | } |
252b5132 | 7588 | |
29b0f896 AM |
7589 | /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we |
7590 | must set it to 3 to indicate this is a register operand | |
7591 | in the regmem field. */ | |
7592 | if (!i.mem_operands) | |
7593 | i.rm.mode = 3; | |
7594 | } | |
252b5132 | 7595 | |
29b0f896 | 7596 | /* Fill in i.rm.reg field with extension opcode (if any). */ |
c1e679ec | 7597 | if (i.tm.extension_opcode != None) |
29b0f896 AM |
7598 | i.rm.reg = i.tm.extension_opcode; |
7599 | } | |
7600 | return default_seg; | |
7601 | } | |
252b5132 | 7602 | |
29b0f896 | 7603 | static void |
e3bb37b5 | 7604 | output_branch (void) |
29b0f896 AM |
7605 | { |
7606 | char *p; | |
f8a5c266 | 7607 | int size; |
29b0f896 AM |
7608 | int code16; |
7609 | int prefix; | |
7610 | relax_substateT subtype; | |
7611 | symbolS *sym; | |
7612 | offsetT off; | |
7613 | ||
f8a5c266 | 7614 | code16 = flag_code == CODE_16BIT ? CODE16 : 0; |
a501d77e | 7615 | size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL; |
29b0f896 AM |
7616 | |
7617 | prefix = 0; | |
7618 | if (i.prefix[DATA_PREFIX] != 0) | |
252b5132 | 7619 | { |
29b0f896 AM |
7620 | prefix = 1; |
7621 | i.prefixes -= 1; | |
7622 | code16 ^= CODE16; | |
252b5132 | 7623 | } |
29b0f896 AM |
7624 | /* Pentium4 branch hints. */ |
7625 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
7626 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
2f66722d | 7627 | { |
29b0f896 AM |
7628 | prefix++; |
7629 | i.prefixes--; | |
7630 | } | |
7631 | if (i.prefix[REX_PREFIX] != 0) | |
7632 | { | |
7633 | prefix++; | |
7634 | i.prefixes--; | |
2f66722d AM |
7635 | } |
7636 | ||
7e8b059b L |
7637 | /* BND prefixed jump. */ |
7638 | if (i.prefix[BND_PREFIX] != 0) | |
7639 | { | |
7640 | FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]); | |
7641 | i.prefixes -= 1; | |
7642 | } | |
7643 | ||
29b0f896 AM |
7644 | if (i.prefixes != 0 && !intel_syntax) |
7645 | as_warn (_("skipping prefixes on this instruction")); | |
7646 | ||
7647 | /* It's always a symbol; End frag & setup for relax. | |
7648 | Make sure there is enough room in this frag for the largest | |
7649 | instruction we may generate in md_convert_frag. This is 2 | |
7650 | bytes for the opcode and room for the prefix and largest | |
7651 | displacement. */ | |
7652 | frag_grow (prefix + 2 + 4); | |
7653 | /* Prefix and 1 opcode byte go in fr_fix. */ | |
7654 | p = frag_more (prefix + 1); | |
7655 | if (i.prefix[DATA_PREFIX] != 0) | |
7656 | *p++ = DATA_PREFIX_OPCODE; | |
7657 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE | |
7658 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE) | |
7659 | *p++ = i.prefix[SEG_PREFIX]; | |
7660 | if (i.prefix[REX_PREFIX] != 0) | |
7661 | *p++ = i.prefix[REX_PREFIX]; | |
7662 | *p = i.tm.base_opcode; | |
7663 | ||
7664 | if ((unsigned char) *p == JUMP_PC_RELATIVE) | |
f8a5c266 | 7665 | subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size); |
40fb9820 | 7666 | else if (cpu_arch_flags.bitfield.cpui386) |
f8a5c266 | 7667 | subtype = ENCODE_RELAX_STATE (COND_JUMP, size); |
29b0f896 | 7668 | else |
f8a5c266 | 7669 | subtype = ENCODE_RELAX_STATE (COND_JUMP86, size); |
29b0f896 | 7670 | subtype |= code16; |
3e73aa7c | 7671 | |
29b0f896 AM |
7672 | sym = i.op[0].disps->X_add_symbol; |
7673 | off = i.op[0].disps->X_add_number; | |
3e73aa7c | 7674 | |
29b0f896 AM |
7675 | if (i.op[0].disps->X_op != O_constant |
7676 | && i.op[0].disps->X_op != O_symbol) | |
3e73aa7c | 7677 | { |
29b0f896 AM |
7678 | /* Handle complex expressions. */ |
7679 | sym = make_expr_symbol (i.op[0].disps); | |
7680 | off = 0; | |
7681 | } | |
3e73aa7c | 7682 | |
29b0f896 AM |
7683 | /* 1 possible extra opcode + 4 byte displacement go in var part. |
7684 | Pass reloc in fr_var. */ | |
d258b828 | 7685 | frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p); |
29b0f896 | 7686 | } |
3e73aa7c | 7687 | |
bd7ab16b L |
7688 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
7689 | /* Return TRUE iff PLT32 relocation should be used for branching to | |
7690 | symbol S. */ | |
7691 | ||
7692 | static bfd_boolean | |
7693 | need_plt32_p (symbolS *s) | |
7694 | { | |
7695 | /* PLT32 relocation is ELF only. */ | |
7696 | if (!IS_ELF) | |
7697 | return FALSE; | |
7698 | ||
7699 | /* Since there is no need to prepare for PLT branch on x86-64, we | |
7700 | can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can | |
7701 | be used as a marker for 32-bit PC-relative branches. */ | |
7702 | if (!object_64bit) | |
7703 | return FALSE; | |
7704 | ||
7705 | /* Weak or undefined symbol need PLT32 relocation. */ | |
7706 | if (S_IS_WEAK (s) || !S_IS_DEFINED (s)) | |
7707 | return TRUE; | |
7708 | ||
7709 | /* Non-global symbol doesn't need PLT32 relocation. */ | |
7710 | if (! S_IS_EXTERNAL (s)) | |
7711 | return FALSE; | |
7712 | ||
7713 | /* Other global symbols need PLT32 relocation. NB: Symbol with | |
7714 | non-default visibilities are treated as normal global symbol | |
7715 | so that PLT32 relocation can be used as a marker for 32-bit | |
7716 | PC-relative branches. It is useful for linker relaxation. */ | |
7717 | return TRUE; | |
7718 | } | |
7719 | #endif | |
7720 | ||
29b0f896 | 7721 | static void |
e3bb37b5 | 7722 | output_jump (void) |
29b0f896 AM |
7723 | { |
7724 | char *p; | |
7725 | int size; | |
3e02c1cc | 7726 | fixS *fixP; |
bd7ab16b | 7727 | bfd_reloc_code_real_type jump_reloc = i.reloc[0]; |
29b0f896 | 7728 | |
40fb9820 | 7729 | if (i.tm.opcode_modifier.jumpbyte) |
29b0f896 AM |
7730 | { |
7731 | /* This is a loop or jecxz type instruction. */ | |
7732 | size = 1; | |
7733 | if (i.prefix[ADDR_PREFIX] != 0) | |
7734 | { | |
7735 | FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE); | |
7736 | i.prefixes -= 1; | |
7737 | } | |
7738 | /* Pentium4 branch hints. */ | |
7739 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
7740 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
7741 | { | |
7742 | FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]); | |
7743 | i.prefixes--; | |
3e73aa7c JH |
7744 | } |
7745 | } | |
29b0f896 AM |
7746 | else |
7747 | { | |
7748 | int code16; | |
3e73aa7c | 7749 | |
29b0f896 AM |
7750 | code16 = 0; |
7751 | if (flag_code == CODE_16BIT) | |
7752 | code16 = CODE16; | |
3e73aa7c | 7753 | |
29b0f896 AM |
7754 | if (i.prefix[DATA_PREFIX] != 0) |
7755 | { | |
7756 | FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE); | |
7757 | i.prefixes -= 1; | |
7758 | code16 ^= CODE16; | |
7759 | } | |
252b5132 | 7760 | |
29b0f896 AM |
7761 | size = 4; |
7762 | if (code16) | |
7763 | size = 2; | |
7764 | } | |
9fcc94b6 | 7765 | |
29b0f896 AM |
7766 | if (i.prefix[REX_PREFIX] != 0) |
7767 | { | |
7768 | FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]); | |
7769 | i.prefixes -= 1; | |
7770 | } | |
252b5132 | 7771 | |
7e8b059b L |
7772 | /* BND prefixed jump. */ |
7773 | if (i.prefix[BND_PREFIX] != 0) | |
7774 | { | |
7775 | FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]); | |
7776 | i.prefixes -= 1; | |
7777 | } | |
7778 | ||
29b0f896 AM |
7779 | if (i.prefixes != 0 && !intel_syntax) |
7780 | as_warn (_("skipping prefixes on this instruction")); | |
e0890092 | 7781 | |
42164a71 L |
7782 | p = frag_more (i.tm.opcode_length + size); |
7783 | switch (i.tm.opcode_length) | |
7784 | { | |
7785 | case 2: | |
7786 | *p++ = i.tm.base_opcode >> 8; | |
1a0670f3 | 7787 | /* Fall through. */ |
42164a71 L |
7788 | case 1: |
7789 | *p++ = i.tm.base_opcode; | |
7790 | break; | |
7791 | default: | |
7792 | abort (); | |
7793 | } | |
e0890092 | 7794 | |
bd7ab16b L |
7795 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
7796 | if (size == 4 | |
7797 | && jump_reloc == NO_RELOC | |
7798 | && need_plt32_p (i.op[0].disps->X_add_symbol)) | |
7799 | jump_reloc = BFD_RELOC_X86_64_PLT32; | |
7800 | #endif | |
7801 | ||
7802 | jump_reloc = reloc (size, 1, 1, jump_reloc); | |
7803 | ||
3e02c1cc | 7804 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
bd7ab16b | 7805 | i.op[0].disps, 1, jump_reloc); |
3e02c1cc AM |
7806 | |
7807 | /* All jumps handled here are signed, but don't use a signed limit | |
7808 | check for 32 and 16 bit jumps as we want to allow wrap around at | |
7809 | 4G and 64k respectively. */ | |
7810 | if (size == 1) | |
7811 | fixP->fx_signed = 1; | |
29b0f896 | 7812 | } |
e0890092 | 7813 | |
29b0f896 | 7814 | static void |
e3bb37b5 | 7815 | output_interseg_jump (void) |
29b0f896 AM |
7816 | { |
7817 | char *p; | |
7818 | int size; | |
7819 | int prefix; | |
7820 | int code16; | |
252b5132 | 7821 | |
29b0f896 AM |
7822 | code16 = 0; |
7823 | if (flag_code == CODE_16BIT) | |
7824 | code16 = CODE16; | |
a217f122 | 7825 | |
29b0f896 AM |
7826 | prefix = 0; |
7827 | if (i.prefix[DATA_PREFIX] != 0) | |
7828 | { | |
7829 | prefix = 1; | |
7830 | i.prefixes -= 1; | |
7831 | code16 ^= CODE16; | |
7832 | } | |
7833 | if (i.prefix[REX_PREFIX] != 0) | |
7834 | { | |
7835 | prefix++; | |
7836 | i.prefixes -= 1; | |
7837 | } | |
252b5132 | 7838 | |
29b0f896 AM |
7839 | size = 4; |
7840 | if (code16) | |
7841 | size = 2; | |
252b5132 | 7842 | |
29b0f896 AM |
7843 | if (i.prefixes != 0 && !intel_syntax) |
7844 | as_warn (_("skipping prefixes on this instruction")); | |
252b5132 | 7845 | |
29b0f896 AM |
7846 | /* 1 opcode; 2 segment; offset */ |
7847 | p = frag_more (prefix + 1 + 2 + size); | |
3e73aa7c | 7848 | |
29b0f896 AM |
7849 | if (i.prefix[DATA_PREFIX] != 0) |
7850 | *p++ = DATA_PREFIX_OPCODE; | |
252b5132 | 7851 | |
29b0f896 AM |
7852 | if (i.prefix[REX_PREFIX] != 0) |
7853 | *p++ = i.prefix[REX_PREFIX]; | |
252b5132 | 7854 | |
29b0f896 AM |
7855 | *p++ = i.tm.base_opcode; |
7856 | if (i.op[1].imms->X_op == O_constant) | |
7857 | { | |
7858 | offsetT n = i.op[1].imms->X_add_number; | |
252b5132 | 7859 | |
29b0f896 AM |
7860 | if (size == 2 |
7861 | && !fits_in_unsigned_word (n) | |
7862 | && !fits_in_signed_word (n)) | |
7863 | { | |
7864 | as_bad (_("16-bit jump out of range")); | |
7865 | return; | |
7866 | } | |
7867 | md_number_to_chars (p, n, size); | |
7868 | } | |
7869 | else | |
7870 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
d258b828 | 7871 | i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1])); |
29b0f896 AM |
7872 | if (i.op[0].imms->X_op != O_constant) |
7873 | as_bad (_("can't handle non absolute segment in `%s'"), | |
7874 | i.tm.name); | |
7875 | md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2); | |
7876 | } | |
a217f122 | 7877 | |
b4a3a7b4 L |
7878 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
7879 | void | |
7880 | x86_cleanup (void) | |
7881 | { | |
7882 | char *p; | |
7883 | asection *seg = now_seg; | |
7884 | subsegT subseg = now_subseg; | |
7885 | asection *sec; | |
7886 | unsigned int alignment, align_size_1; | |
7887 | unsigned int isa_1_descsz, feature_2_descsz, descsz; | |
7888 | unsigned int isa_1_descsz_raw, feature_2_descsz_raw; | |
7889 | unsigned int padding; | |
7890 | ||
7891 | if (!IS_ELF || !x86_used_note) | |
7892 | return; | |
7893 | ||
7894 | x86_isa_1_used |= GNU_PROPERTY_X86_UINT32_VALID; | |
7895 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X86; | |
7896 | ||
7897 | /* The .note.gnu.property section layout: | |
7898 | ||
7899 | Field Length Contents | |
7900 | ---- ---- ---- | |
7901 | n_namsz 4 4 | |
7902 | n_descsz 4 The note descriptor size | |
7903 | n_type 4 NT_GNU_PROPERTY_TYPE_0 | |
7904 | n_name 4 "GNU" | |
7905 | n_desc n_descsz The program property array | |
7906 | .... .... .... | |
7907 | */ | |
7908 | ||
7909 | /* Create the .note.gnu.property section. */ | |
7910 | sec = subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME, 0); | |
7911 | bfd_set_section_flags (stdoutput, sec, | |
7912 | (SEC_ALLOC | |
7913 | | SEC_LOAD | |
7914 | | SEC_DATA | |
7915 | | SEC_HAS_CONTENTS | |
7916 | | SEC_READONLY)); | |
7917 | ||
7918 | if (get_elf_backend_data (stdoutput)->s->elfclass == ELFCLASS64) | |
7919 | { | |
7920 | align_size_1 = 7; | |
7921 | alignment = 3; | |
7922 | } | |
7923 | else | |
7924 | { | |
7925 | align_size_1 = 3; | |
7926 | alignment = 2; | |
7927 | } | |
7928 | ||
7929 | bfd_set_section_alignment (stdoutput, sec, alignment); | |
7930 | elf_section_type (sec) = SHT_NOTE; | |
7931 | ||
7932 | /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size | |
7933 | + 4-byte data */ | |
7934 | isa_1_descsz_raw = 4 + 4 + 4; | |
7935 | /* Align GNU_PROPERTY_X86_ISA_1_USED. */ | |
7936 | isa_1_descsz = (isa_1_descsz_raw + align_size_1) & ~align_size_1; | |
7937 | ||
7938 | feature_2_descsz_raw = isa_1_descsz; | |
7939 | /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size | |
7940 | + 4-byte data */ | |
7941 | feature_2_descsz_raw += 4 + 4 + 4; | |
7942 | /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */ | |
7943 | feature_2_descsz = ((feature_2_descsz_raw + align_size_1) | |
7944 | & ~align_size_1); | |
7945 | ||
7946 | descsz = feature_2_descsz; | |
7947 | /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */ | |
7948 | p = frag_more (4 + 4 + 4 + 4 + descsz); | |
7949 | ||
7950 | /* Write n_namsz. */ | |
7951 | md_number_to_chars (p, (valueT) 4, 4); | |
7952 | ||
7953 | /* Write n_descsz. */ | |
7954 | md_number_to_chars (p + 4, (valueT) descsz, 4); | |
7955 | ||
7956 | /* Write n_type. */ | |
7957 | md_number_to_chars (p + 4 * 2, (valueT) NT_GNU_PROPERTY_TYPE_0, 4); | |
7958 | ||
7959 | /* Write n_name. */ | |
7960 | memcpy (p + 4 * 3, "GNU", 4); | |
7961 | ||
7962 | /* Write 4-byte type. */ | |
7963 | md_number_to_chars (p + 4 * 4, | |
7964 | (valueT) GNU_PROPERTY_X86_ISA_1_USED, 4); | |
7965 | ||
7966 | /* Write 4-byte data size. */ | |
7967 | md_number_to_chars (p + 4 * 5, (valueT) 4, 4); | |
7968 | ||
7969 | /* Write 4-byte data. */ | |
7970 | md_number_to_chars (p + 4 * 6, (valueT) x86_isa_1_used, 4); | |
7971 | ||
7972 | /* Zero out paddings. */ | |
7973 | padding = isa_1_descsz - isa_1_descsz_raw; | |
7974 | if (padding) | |
7975 | memset (p + 4 * 7, 0, padding); | |
7976 | ||
7977 | /* Write 4-byte type. */ | |
7978 | md_number_to_chars (p + isa_1_descsz + 4 * 4, | |
7979 | (valueT) GNU_PROPERTY_X86_FEATURE_2_USED, 4); | |
7980 | ||
7981 | /* Write 4-byte data size. */ | |
7982 | md_number_to_chars (p + isa_1_descsz + 4 * 5, (valueT) 4, 4); | |
7983 | ||
7984 | /* Write 4-byte data. */ | |
7985 | md_number_to_chars (p + isa_1_descsz + 4 * 6, | |
7986 | (valueT) x86_feature_2_used, 4); | |
7987 | ||
7988 | /* Zero out paddings. */ | |
7989 | padding = feature_2_descsz - feature_2_descsz_raw; | |
7990 | if (padding) | |
7991 | memset (p + isa_1_descsz + 4 * 7, 0, padding); | |
7992 | ||
7993 | /* We probably can't restore the current segment, for there likely | |
7994 | isn't one yet... */ | |
7995 | if (seg && subseg) | |
7996 | subseg_set (seg, subseg); | |
7997 | } | |
7998 | #endif | |
7999 | ||
29b0f896 | 8000 | static void |
e3bb37b5 | 8001 | output_insn (void) |
29b0f896 | 8002 | { |
2bbd9c25 JJ |
8003 | fragS *insn_start_frag; |
8004 | offsetT insn_start_off; | |
8005 | ||
b4a3a7b4 L |
8006 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8007 | if (IS_ELF && x86_used_note) | |
8008 | { | |
8009 | if (i.tm.cpu_flags.bitfield.cpucmov) | |
8010 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_CMOV; | |
8011 | if (i.tm.cpu_flags.bitfield.cpusse) | |
8012 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE; | |
8013 | if (i.tm.cpu_flags.bitfield.cpusse2) | |
8014 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE2; | |
8015 | if (i.tm.cpu_flags.bitfield.cpusse3) | |
8016 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE3; | |
8017 | if (i.tm.cpu_flags.bitfield.cpussse3) | |
8018 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSSE3; | |
8019 | if (i.tm.cpu_flags.bitfield.cpusse4_1) | |
8020 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE4_1; | |
8021 | if (i.tm.cpu_flags.bitfield.cpusse4_2) | |
8022 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE4_2; | |
8023 | if (i.tm.cpu_flags.bitfield.cpuavx) | |
8024 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX; | |
8025 | if (i.tm.cpu_flags.bitfield.cpuavx2) | |
8026 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX2; | |
8027 | if (i.tm.cpu_flags.bitfield.cpufma) | |
8028 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_FMA; | |
8029 | if (i.tm.cpu_flags.bitfield.cpuavx512f) | |
8030 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512F; | |
8031 | if (i.tm.cpu_flags.bitfield.cpuavx512cd) | |
8032 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512CD; | |
8033 | if (i.tm.cpu_flags.bitfield.cpuavx512er) | |
8034 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512ER; | |
8035 | if (i.tm.cpu_flags.bitfield.cpuavx512pf) | |
8036 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512PF; | |
8037 | if (i.tm.cpu_flags.bitfield.cpuavx512vl) | |
8038 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512VL; | |
8039 | if (i.tm.cpu_flags.bitfield.cpuavx512dq) | |
8040 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512DQ; | |
8041 | if (i.tm.cpu_flags.bitfield.cpuavx512bw) | |
8042 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512BW; | |
8043 | if (i.tm.cpu_flags.bitfield.cpuavx512_4fmaps) | |
8044 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS; | |
8045 | if (i.tm.cpu_flags.bitfield.cpuavx512_4vnniw) | |
8046 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW; | |
8047 | if (i.tm.cpu_flags.bitfield.cpuavx512_bitalg) | |
8048 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG; | |
8049 | if (i.tm.cpu_flags.bitfield.cpuavx512ifma) | |
8050 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA; | |
8051 | if (i.tm.cpu_flags.bitfield.cpuavx512vbmi) | |
8052 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI; | |
8053 | if (i.tm.cpu_flags.bitfield.cpuavx512_vbmi2) | |
8054 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2; | |
8055 | if (i.tm.cpu_flags.bitfield.cpuavx512_vnni) | |
8056 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI; | |
8057 | ||
8058 | if (i.tm.cpu_flags.bitfield.cpu8087 | |
8059 | || i.tm.cpu_flags.bitfield.cpu287 | |
8060 | || i.tm.cpu_flags.bitfield.cpu387 | |
8061 | || i.tm.cpu_flags.bitfield.cpu687 | |
8062 | || i.tm.cpu_flags.bitfield.cpufisttp) | |
8063 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X87; | |
8064 | /* Don't set GNU_PROPERTY_X86_FEATURE_2_MMX for prefetchtXXX nor | |
8065 | Xfence instructions. */ | |
8066 | if (i.tm.base_opcode != 0xf18 | |
8067 | && i.tm.base_opcode != 0xf0d | |
8068 | && i.tm.base_opcode != 0xfae | |
8069 | && (i.has_regmmx | |
8070 | || i.tm.cpu_flags.bitfield.cpummx | |
8071 | || i.tm.cpu_flags.bitfield.cpua3dnow | |
8072 | || i.tm.cpu_flags.bitfield.cpua3dnowa)) | |
8073 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_MMX; | |
8074 | if (i.has_regxmm) | |
8075 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XMM; | |
8076 | if (i.has_regymm) | |
8077 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_YMM; | |
8078 | if (i.has_regzmm) | |
8079 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_ZMM; | |
8080 | if (i.tm.cpu_flags.bitfield.cpufxsr) | |
8081 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_FXSR; | |
8082 | if (i.tm.cpu_flags.bitfield.cpuxsave) | |
8083 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVE; | |
8084 | if (i.tm.cpu_flags.bitfield.cpuxsaveopt) | |
8085 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT; | |
8086 | if (i.tm.cpu_flags.bitfield.cpuxsavec) | |
8087 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEC; | |
8088 | } | |
8089 | #endif | |
8090 | ||
29b0f896 AM |
8091 | /* Tie dwarf2 debug info to the address at the start of the insn. |
8092 | We can't do this after the insn has been output as the current | |
8093 | frag may have been closed off. eg. by frag_var. */ | |
8094 | dwarf2_emit_insn (0); | |
8095 | ||
2bbd9c25 JJ |
8096 | insn_start_frag = frag_now; |
8097 | insn_start_off = frag_now_fix (); | |
8098 | ||
29b0f896 | 8099 | /* Output jumps. */ |
40fb9820 | 8100 | if (i.tm.opcode_modifier.jump) |
29b0f896 | 8101 | output_branch (); |
40fb9820 L |
8102 | else if (i.tm.opcode_modifier.jumpbyte |
8103 | || i.tm.opcode_modifier.jumpdword) | |
29b0f896 | 8104 | output_jump (); |
40fb9820 | 8105 | else if (i.tm.opcode_modifier.jumpintersegment) |
29b0f896 AM |
8106 | output_interseg_jump (); |
8107 | else | |
8108 | { | |
8109 | /* Output normal instructions here. */ | |
8110 | char *p; | |
8111 | unsigned char *q; | |
47465058 | 8112 | unsigned int j; |
331d2d0d | 8113 | unsigned int prefix; |
4dffcebc | 8114 | |
e4e00185 AS |
8115 | if (avoid_fence |
8116 | && i.tm.base_opcode == 0xfae | |
8117 | && i.operands == 1 | |
8118 | && i.imm_operands == 1 | |
8119 | && (i.op[0].imms->X_add_number == 0xe8 | |
8120 | || i.op[0].imms->X_add_number == 0xf0 | |
8121 | || i.op[0].imms->X_add_number == 0xf8)) | |
8122 | { | |
8123 | /* Encode lfence, mfence, and sfence as | |
8124 | f0 83 04 24 00 lock addl $0x0, (%{re}sp). */ | |
8125 | offsetT val = 0x240483f0ULL; | |
8126 | p = frag_more (5); | |
8127 | md_number_to_chars (p, val, 5); | |
8128 | return; | |
8129 | } | |
8130 | ||
d022bddd IT |
8131 | /* Some processors fail on LOCK prefix. This options makes |
8132 | assembler ignore LOCK prefix and serves as a workaround. */ | |
8133 | if (omit_lock_prefix) | |
8134 | { | |
8135 | if (i.tm.base_opcode == LOCK_PREFIX_OPCODE) | |
8136 | return; | |
8137 | i.prefix[LOCK_PREFIX] = 0; | |
8138 | } | |
8139 | ||
43234a1e L |
8140 | /* Since the VEX/EVEX prefix contains the implicit prefix, we |
8141 | don't need the explicit prefix. */ | |
8142 | if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex) | |
bc4bd9ab | 8143 | { |
c0f3af97 | 8144 | switch (i.tm.opcode_length) |
bc4bd9ab | 8145 | { |
c0f3af97 L |
8146 | case 3: |
8147 | if (i.tm.base_opcode & 0xff000000) | |
4dffcebc | 8148 | { |
c0f3af97 | 8149 | prefix = (i.tm.base_opcode >> 24) & 0xff; |
bd59a631 | 8150 | add_prefix (prefix); |
c0f3af97 L |
8151 | } |
8152 | break; | |
8153 | case 2: | |
8154 | if ((i.tm.base_opcode & 0xff0000) != 0) | |
8155 | { | |
8156 | prefix = (i.tm.base_opcode >> 16) & 0xff; | |
bd59a631 JB |
8157 | if (!i.tm.cpu_flags.bitfield.cpupadlock |
8158 | || prefix != REPE_PREFIX_OPCODE | |
8159 | || (i.prefix[REP_PREFIX] != REPE_PREFIX_OPCODE)) | |
4dffcebc L |
8160 | add_prefix (prefix); |
8161 | } | |
c0f3af97 L |
8162 | break; |
8163 | case 1: | |
8164 | break; | |
390c91cf L |
8165 | case 0: |
8166 | /* Check for pseudo prefixes. */ | |
8167 | as_bad_where (insn_start_frag->fr_file, | |
8168 | insn_start_frag->fr_line, | |
8169 | _("pseudo prefix without instruction")); | |
8170 | return; | |
c0f3af97 L |
8171 | default: |
8172 | abort (); | |
bc4bd9ab | 8173 | } |
c0f3af97 | 8174 | |
6d19a37a | 8175 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
cf61b747 L |
8176 | /* For x32, add a dummy REX_OPCODE prefix for mov/add with |
8177 | R_X86_64_GOTTPOFF relocation so that linker can safely | |
8178 | perform IE->LE optimization. */ | |
8179 | if (x86_elf_abi == X86_64_X32_ABI | |
8180 | && i.operands == 2 | |
8181 | && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF | |
8182 | && i.prefix[REX_PREFIX] == 0) | |
8183 | add_prefix (REX_OPCODE); | |
6d19a37a | 8184 | #endif |
cf61b747 | 8185 | |
c0f3af97 L |
8186 | /* The prefix bytes. */ |
8187 | for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++) | |
8188 | if (*q) | |
8189 | FRAG_APPEND_1_CHAR (*q); | |
0f10071e | 8190 | } |
ae5c1c7b | 8191 | else |
c0f3af97 L |
8192 | { |
8193 | for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++) | |
8194 | if (*q) | |
8195 | switch (j) | |
8196 | { | |
8197 | case REX_PREFIX: | |
8198 | /* REX byte is encoded in VEX prefix. */ | |
8199 | break; | |
8200 | case SEG_PREFIX: | |
8201 | case ADDR_PREFIX: | |
8202 | FRAG_APPEND_1_CHAR (*q); | |
8203 | break; | |
8204 | default: | |
8205 | /* There should be no other prefixes for instructions | |
8206 | with VEX prefix. */ | |
8207 | abort (); | |
8208 | } | |
8209 | ||
43234a1e L |
8210 | /* For EVEX instructions i.vrex should become 0 after |
8211 | build_evex_prefix. For VEX instructions upper 16 registers | |
8212 | aren't available, so VREX should be 0. */ | |
8213 | if (i.vrex) | |
8214 | abort (); | |
c0f3af97 L |
8215 | /* Now the VEX prefix. */ |
8216 | p = frag_more (i.vex.length); | |
8217 | for (j = 0; j < i.vex.length; j++) | |
8218 | p[j] = i.vex.bytes[j]; | |
8219 | } | |
252b5132 | 8220 | |
29b0f896 | 8221 | /* Now the opcode; be careful about word order here! */ |
4dffcebc | 8222 | if (i.tm.opcode_length == 1) |
29b0f896 AM |
8223 | { |
8224 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); | |
8225 | } | |
8226 | else | |
8227 | { | |
4dffcebc | 8228 | switch (i.tm.opcode_length) |
331d2d0d | 8229 | { |
43234a1e L |
8230 | case 4: |
8231 | p = frag_more (4); | |
8232 | *p++ = (i.tm.base_opcode >> 24) & 0xff; | |
8233 | *p++ = (i.tm.base_opcode >> 16) & 0xff; | |
8234 | break; | |
4dffcebc | 8235 | case 3: |
331d2d0d L |
8236 | p = frag_more (3); |
8237 | *p++ = (i.tm.base_opcode >> 16) & 0xff; | |
4dffcebc L |
8238 | break; |
8239 | case 2: | |
8240 | p = frag_more (2); | |
8241 | break; | |
8242 | default: | |
8243 | abort (); | |
8244 | break; | |
331d2d0d | 8245 | } |
0f10071e | 8246 | |
29b0f896 AM |
8247 | /* Put out high byte first: can't use md_number_to_chars! */ |
8248 | *p++ = (i.tm.base_opcode >> 8) & 0xff; | |
8249 | *p = i.tm.base_opcode & 0xff; | |
8250 | } | |
3e73aa7c | 8251 | |
29b0f896 | 8252 | /* Now the modrm byte and sib byte (if present). */ |
40fb9820 | 8253 | if (i.tm.opcode_modifier.modrm) |
29b0f896 | 8254 | { |
4a3523fa L |
8255 | FRAG_APPEND_1_CHAR ((i.rm.regmem << 0 |
8256 | | i.rm.reg << 3 | |
8257 | | i.rm.mode << 6)); | |
29b0f896 AM |
8258 | /* If i.rm.regmem == ESP (4) |
8259 | && i.rm.mode != (Register mode) | |
8260 | && not 16 bit | |
8261 | ==> need second modrm byte. */ | |
8262 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING | |
8263 | && i.rm.mode != 3 | |
dc821c5f | 8264 | && !(i.base_reg && i.base_reg->reg_type.bitfield.word)) |
4a3523fa L |
8265 | FRAG_APPEND_1_CHAR ((i.sib.base << 0 |
8266 | | i.sib.index << 3 | |
8267 | | i.sib.scale << 6)); | |
29b0f896 | 8268 | } |
3e73aa7c | 8269 | |
29b0f896 | 8270 | if (i.disp_operands) |
2bbd9c25 | 8271 | output_disp (insn_start_frag, insn_start_off); |
3e73aa7c | 8272 | |
29b0f896 | 8273 | if (i.imm_operands) |
2bbd9c25 | 8274 | output_imm (insn_start_frag, insn_start_off); |
29b0f896 | 8275 | } |
252b5132 | 8276 | |
29b0f896 AM |
8277 | #ifdef DEBUG386 |
8278 | if (flag_debug) | |
8279 | { | |
7b81dfbb | 8280 | pi ("" /*line*/, &i); |
29b0f896 AM |
8281 | } |
8282 | #endif /* DEBUG386 */ | |
8283 | } | |
252b5132 | 8284 | |
e205caa7 L |
8285 | /* Return the size of the displacement operand N. */ |
8286 | ||
8287 | static int | |
8288 | disp_size (unsigned int n) | |
8289 | { | |
8290 | int size = 4; | |
43234a1e | 8291 | |
b5014f7a | 8292 | if (i.types[n].bitfield.disp64) |
40fb9820 L |
8293 | size = 8; |
8294 | else if (i.types[n].bitfield.disp8) | |
8295 | size = 1; | |
8296 | else if (i.types[n].bitfield.disp16) | |
8297 | size = 2; | |
e205caa7 L |
8298 | return size; |
8299 | } | |
8300 | ||
8301 | /* Return the size of the immediate operand N. */ | |
8302 | ||
8303 | static int | |
8304 | imm_size (unsigned int n) | |
8305 | { | |
8306 | int size = 4; | |
40fb9820 L |
8307 | if (i.types[n].bitfield.imm64) |
8308 | size = 8; | |
8309 | else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s) | |
8310 | size = 1; | |
8311 | else if (i.types[n].bitfield.imm16) | |
8312 | size = 2; | |
e205caa7 L |
8313 | return size; |
8314 | } | |
8315 | ||
29b0f896 | 8316 | static void |
64e74474 | 8317 | output_disp (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
8318 | { |
8319 | char *p; | |
8320 | unsigned int n; | |
252b5132 | 8321 | |
29b0f896 AM |
8322 | for (n = 0; n < i.operands; n++) |
8323 | { | |
b5014f7a | 8324 | if (operand_type_check (i.types[n], disp)) |
29b0f896 AM |
8325 | { |
8326 | if (i.op[n].disps->X_op == O_constant) | |
8327 | { | |
e205caa7 | 8328 | int size = disp_size (n); |
43234a1e | 8329 | offsetT val = i.op[n].disps->X_add_number; |
252b5132 | 8330 | |
629cfaf1 JB |
8331 | val = offset_in_range (val >> (size == 1 ? i.memshift : 0), |
8332 | size); | |
29b0f896 AM |
8333 | p = frag_more (size); |
8334 | md_number_to_chars (p, val, size); | |
8335 | } | |
8336 | else | |
8337 | { | |
f86103b7 | 8338 | enum bfd_reloc_code_real reloc_type; |
e205caa7 | 8339 | int size = disp_size (n); |
40fb9820 | 8340 | int sign = i.types[n].bitfield.disp32s; |
29b0f896 | 8341 | int pcrel = (i.flags[n] & Operand_PCrel) != 0; |
02a86693 | 8342 | fixS *fixP; |
29b0f896 | 8343 | |
e205caa7 | 8344 | /* We can't have 8 bit displacement here. */ |
9c2799c2 | 8345 | gas_assert (!i.types[n].bitfield.disp8); |
e205caa7 | 8346 | |
29b0f896 AM |
8347 | /* The PC relative address is computed relative |
8348 | to the instruction boundary, so in case immediate | |
8349 | fields follows, we need to adjust the value. */ | |
8350 | if (pcrel && i.imm_operands) | |
8351 | { | |
29b0f896 | 8352 | unsigned int n1; |
e205caa7 | 8353 | int sz = 0; |
252b5132 | 8354 | |
29b0f896 | 8355 | for (n1 = 0; n1 < i.operands; n1++) |
40fb9820 | 8356 | if (operand_type_check (i.types[n1], imm)) |
252b5132 | 8357 | { |
e205caa7 L |
8358 | /* Only one immediate is allowed for PC |
8359 | relative address. */ | |
9c2799c2 | 8360 | gas_assert (sz == 0); |
e205caa7 L |
8361 | sz = imm_size (n1); |
8362 | i.op[n].disps->X_add_number -= sz; | |
252b5132 | 8363 | } |
29b0f896 | 8364 | /* We should find the immediate. */ |
9c2799c2 | 8365 | gas_assert (sz != 0); |
29b0f896 | 8366 | } |
520dc8e8 | 8367 | |
29b0f896 | 8368 | p = frag_more (size); |
d258b828 | 8369 | reloc_type = reloc (size, pcrel, sign, i.reloc[n]); |
d6ab8113 | 8370 | if (GOT_symbol |
2bbd9c25 | 8371 | && GOT_symbol == i.op[n].disps->X_add_symbol |
d6ab8113 | 8372 | && (((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
8373 | || reloc_type == BFD_RELOC_X86_64_32S |
8374 | || (reloc_type == BFD_RELOC_64 | |
8375 | && object_64bit)) | |
d6ab8113 JB |
8376 | && (i.op[n].disps->X_op == O_symbol |
8377 | || (i.op[n].disps->X_op == O_add | |
8378 | && ((symbol_get_value_expression | |
8379 | (i.op[n].disps->X_op_symbol)->X_op) | |
8380 | == O_subtract)))) | |
8381 | || reloc_type == BFD_RELOC_32_PCREL)) | |
2bbd9c25 JJ |
8382 | { |
8383 | offsetT add; | |
8384 | ||
8385 | if (insn_start_frag == frag_now) | |
8386 | add = (p - frag_now->fr_literal) - insn_start_off; | |
8387 | else | |
8388 | { | |
8389 | fragS *fr; | |
8390 | ||
8391 | add = insn_start_frag->fr_fix - insn_start_off; | |
8392 | for (fr = insn_start_frag->fr_next; | |
8393 | fr && fr != frag_now; fr = fr->fr_next) | |
8394 | add += fr->fr_fix; | |
8395 | add += p - frag_now->fr_literal; | |
8396 | } | |
8397 | ||
4fa24527 | 8398 | if (!object_64bit) |
7b81dfbb AJ |
8399 | { |
8400 | reloc_type = BFD_RELOC_386_GOTPC; | |
8401 | i.op[n].imms->X_add_number += add; | |
8402 | } | |
8403 | else if (reloc_type == BFD_RELOC_64) | |
8404 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
d6ab8113 | 8405 | else |
7b81dfbb AJ |
8406 | /* Don't do the adjustment for x86-64, as there |
8407 | the pcrel addressing is relative to the _next_ | |
8408 | insn, and that is taken care of in other code. */ | |
d6ab8113 | 8409 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
2bbd9c25 | 8410 | } |
02a86693 L |
8411 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, |
8412 | size, i.op[n].disps, pcrel, | |
8413 | reloc_type); | |
8414 | /* Check for "call/jmp *mem", "mov mem, %reg", | |
8415 | "test %reg, mem" and "binop mem, %reg" where binop | |
8416 | is one of adc, add, and, cmp, or, sbb, sub, xor | |
0cb4071e L |
8417 | instructions. Always generate R_386_GOT32X for |
8418 | "sym*GOT" operand in 32-bit mode. */ | |
8419 | if ((generate_relax_relocations | |
8420 | || (!object_64bit | |
8421 | && i.rm.mode == 0 | |
8422 | && i.rm.regmem == 5)) | |
8423 | && (i.rm.mode == 2 | |
8424 | || (i.rm.mode == 0 && i.rm.regmem == 5)) | |
02a86693 L |
8425 | && ((i.operands == 1 |
8426 | && i.tm.base_opcode == 0xff | |
8427 | && (i.rm.reg == 2 || i.rm.reg == 4)) | |
8428 | || (i.operands == 2 | |
8429 | && (i.tm.base_opcode == 0x8b | |
8430 | || i.tm.base_opcode == 0x85 | |
8431 | || (i.tm.base_opcode & 0xc7) == 0x03)))) | |
8432 | { | |
8433 | if (object_64bit) | |
8434 | { | |
8435 | fixP->fx_tcbit = i.rex != 0; | |
8436 | if (i.base_reg | |
e968fc9b | 8437 | && (i.base_reg->reg_num == RegIP)) |
02a86693 L |
8438 | fixP->fx_tcbit2 = 1; |
8439 | } | |
8440 | else | |
8441 | fixP->fx_tcbit2 = 1; | |
8442 | } | |
29b0f896 AM |
8443 | } |
8444 | } | |
8445 | } | |
8446 | } | |
252b5132 | 8447 | |
29b0f896 | 8448 | static void |
64e74474 | 8449 | output_imm (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
8450 | { |
8451 | char *p; | |
8452 | unsigned int n; | |
252b5132 | 8453 | |
29b0f896 AM |
8454 | for (n = 0; n < i.operands; n++) |
8455 | { | |
43234a1e L |
8456 | /* Skip SAE/RC Imm operand in EVEX. They are already handled. */ |
8457 | if (i.rounding && (int) n == i.rounding->operand) | |
8458 | continue; | |
8459 | ||
40fb9820 | 8460 | if (operand_type_check (i.types[n], imm)) |
29b0f896 AM |
8461 | { |
8462 | if (i.op[n].imms->X_op == O_constant) | |
8463 | { | |
e205caa7 | 8464 | int size = imm_size (n); |
29b0f896 | 8465 | offsetT val; |
b4cac588 | 8466 | |
29b0f896 AM |
8467 | val = offset_in_range (i.op[n].imms->X_add_number, |
8468 | size); | |
8469 | p = frag_more (size); | |
8470 | md_number_to_chars (p, val, size); | |
8471 | } | |
8472 | else | |
8473 | { | |
8474 | /* Not absolute_section. | |
8475 | Need a 32-bit fixup (don't support 8bit | |
8476 | non-absolute imms). Try to support other | |
8477 | sizes ... */ | |
f86103b7 | 8478 | enum bfd_reloc_code_real reloc_type; |
e205caa7 L |
8479 | int size = imm_size (n); |
8480 | int sign; | |
29b0f896 | 8481 | |
40fb9820 | 8482 | if (i.types[n].bitfield.imm32s |
a7d61044 | 8483 | && (i.suffix == QWORD_MNEM_SUFFIX |
40fb9820 | 8484 | || (!i.suffix && i.tm.opcode_modifier.no_lsuf))) |
29b0f896 | 8485 | sign = 1; |
e205caa7 L |
8486 | else |
8487 | sign = 0; | |
520dc8e8 | 8488 | |
29b0f896 | 8489 | p = frag_more (size); |
d258b828 | 8490 | reloc_type = reloc (size, 0, sign, i.reloc[n]); |
f86103b7 | 8491 | |
2bbd9c25 JJ |
8492 | /* This is tough to explain. We end up with this one if we |
8493 | * have operands that look like | |
8494 | * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to | |
8495 | * obtain the absolute address of the GOT, and it is strongly | |
8496 | * preferable from a performance point of view to avoid using | |
8497 | * a runtime relocation for this. The actual sequence of | |
8498 | * instructions often look something like: | |
8499 | * | |
8500 | * call .L66 | |
8501 | * .L66: | |
8502 | * popl %ebx | |
8503 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx | |
8504 | * | |
8505 | * The call and pop essentially return the absolute address | |
8506 | * of the label .L66 and store it in %ebx. The linker itself | |
8507 | * will ultimately change the first operand of the addl so | |
8508 | * that %ebx points to the GOT, but to keep things simple, the | |
8509 | * .o file must have this operand set so that it generates not | |
8510 | * the absolute address of .L66, but the absolute address of | |
8511 | * itself. This allows the linker itself simply treat a GOTPC | |
8512 | * relocation as asking for a pcrel offset to the GOT to be | |
8513 | * added in, and the addend of the relocation is stored in the | |
8514 | * operand field for the instruction itself. | |
8515 | * | |
8516 | * Our job here is to fix the operand so that it would add | |
8517 | * the correct offset so that %ebx would point to itself. The | |
8518 | * thing that is tricky is that .-.L66 will point to the | |
8519 | * beginning of the instruction, so we need to further modify | |
8520 | * the operand so that it will point to itself. There are | |
8521 | * other cases where you have something like: | |
8522 | * | |
8523 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] | |
8524 | * | |
8525 | * and here no correction would be required. Internally in | |
8526 | * the assembler we treat operands of this form as not being | |
8527 | * pcrel since the '.' is explicitly mentioned, and I wonder | |
8528 | * whether it would simplify matters to do it this way. Who | |
8529 | * knows. In earlier versions of the PIC patches, the | |
8530 | * pcrel_adjust field was used to store the correction, but | |
8531 | * since the expression is not pcrel, I felt it would be | |
8532 | * confusing to do it this way. */ | |
8533 | ||
d6ab8113 | 8534 | if ((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
8535 | || reloc_type == BFD_RELOC_X86_64_32S |
8536 | || reloc_type == BFD_RELOC_64) | |
29b0f896 AM |
8537 | && GOT_symbol |
8538 | && GOT_symbol == i.op[n].imms->X_add_symbol | |
8539 | && (i.op[n].imms->X_op == O_symbol | |
8540 | || (i.op[n].imms->X_op == O_add | |
8541 | && ((symbol_get_value_expression | |
8542 | (i.op[n].imms->X_op_symbol)->X_op) | |
8543 | == O_subtract)))) | |
8544 | { | |
2bbd9c25 JJ |
8545 | offsetT add; |
8546 | ||
8547 | if (insn_start_frag == frag_now) | |
8548 | add = (p - frag_now->fr_literal) - insn_start_off; | |
8549 | else | |
8550 | { | |
8551 | fragS *fr; | |
8552 | ||
8553 | add = insn_start_frag->fr_fix - insn_start_off; | |
8554 | for (fr = insn_start_frag->fr_next; | |
8555 | fr && fr != frag_now; fr = fr->fr_next) | |
8556 | add += fr->fr_fix; | |
8557 | add += p - frag_now->fr_literal; | |
8558 | } | |
8559 | ||
4fa24527 | 8560 | if (!object_64bit) |
d6ab8113 | 8561 | reloc_type = BFD_RELOC_386_GOTPC; |
7b81dfbb | 8562 | else if (size == 4) |
d6ab8113 | 8563 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
7b81dfbb AJ |
8564 | else if (size == 8) |
8565 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
2bbd9c25 | 8566 | i.op[n].imms->X_add_number += add; |
29b0f896 | 8567 | } |
29b0f896 AM |
8568 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
8569 | i.op[n].imms, 0, reloc_type); | |
8570 | } | |
8571 | } | |
8572 | } | |
252b5132 RH |
8573 | } |
8574 | \f | |
d182319b JB |
8575 | /* x86_cons_fix_new is called via the expression parsing code when a |
8576 | reloc is needed. We use this hook to get the correct .got reloc. */ | |
d182319b JB |
8577 | static int cons_sign = -1; |
8578 | ||
8579 | void | |
e3bb37b5 | 8580 | x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len, |
62ebcb5c | 8581 | expressionS *exp, bfd_reloc_code_real_type r) |
d182319b | 8582 | { |
d258b828 | 8583 | r = reloc (len, 0, cons_sign, r); |
d182319b JB |
8584 | |
8585 | #ifdef TE_PE | |
8586 | if (exp->X_op == O_secrel) | |
8587 | { | |
8588 | exp->X_op = O_symbol; | |
8589 | r = BFD_RELOC_32_SECREL; | |
8590 | } | |
8591 | #endif | |
8592 | ||
8593 | fix_new_exp (frag, off, len, exp, 0, r); | |
8594 | } | |
8595 | ||
357d1bd8 L |
8596 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
8597 | purpose of the `.dc.a' internal pseudo-op. */ | |
8598 | ||
8599 | int | |
8600 | x86_address_bytes (void) | |
8601 | { | |
8602 | if ((stdoutput->arch_info->mach & bfd_mach_x64_32)) | |
8603 | return 4; | |
8604 | return stdoutput->arch_info->bits_per_address / 8; | |
8605 | } | |
8606 | ||
d382c579 TG |
8607 | #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \ |
8608 | || defined (LEX_AT) | |
d258b828 | 8609 | # define lex_got(reloc, adjust, types) NULL |
718ddfc0 | 8610 | #else |
f3c180ae AM |
8611 | /* Parse operands of the form |
8612 | <symbol>@GOTOFF+<nnn> | |
8613 | and similar .plt or .got references. | |
8614 | ||
8615 | If we find one, set up the correct relocation in RELOC and copy the | |
8616 | input string, minus the `@GOTOFF' into a malloc'd buffer for | |
8617 | parsing by the calling routine. Return this buffer, and if ADJUST | |
8618 | is non-null set it to the length of the string we removed from the | |
8619 | input line. Otherwise return NULL. */ | |
8620 | static char * | |
91d6fa6a | 8621 | lex_got (enum bfd_reloc_code_real *rel, |
64e74474 | 8622 | int *adjust, |
d258b828 | 8623 | i386_operand_type *types) |
f3c180ae | 8624 | { |
7b81dfbb AJ |
8625 | /* Some of the relocations depend on the size of what field is to |
8626 | be relocated. But in our callers i386_immediate and i386_displacement | |
8627 | we don't yet know the operand size (this will be set by insn | |
8628 | matching). Hence we record the word32 relocation here, | |
8629 | and adjust the reloc according to the real size in reloc(). */ | |
f3c180ae AM |
8630 | static const struct { |
8631 | const char *str; | |
cff8d58a | 8632 | int len; |
4fa24527 | 8633 | const enum bfd_reloc_code_real rel[2]; |
40fb9820 | 8634 | const i386_operand_type types64; |
f3c180ae | 8635 | } gotrel[] = { |
8ce3d284 | 8636 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
8637 | { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32, |
8638 | BFD_RELOC_SIZE32 }, | |
8639 | OPERAND_TYPE_IMM32_64 }, | |
8ce3d284 | 8640 | #endif |
cff8d58a L |
8641 | { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real, |
8642 | BFD_RELOC_X86_64_PLTOFF64 }, | |
40fb9820 | 8643 | OPERAND_TYPE_IMM64 }, |
cff8d58a L |
8644 | { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32, |
8645 | BFD_RELOC_X86_64_PLT32 }, | |
40fb9820 | 8646 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
8647 | { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real, |
8648 | BFD_RELOC_X86_64_GOTPLT64 }, | |
40fb9820 | 8649 | OPERAND_TYPE_IMM64_DISP64 }, |
cff8d58a L |
8650 | { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF, |
8651 | BFD_RELOC_X86_64_GOTOFF64 }, | |
40fb9820 | 8652 | OPERAND_TYPE_IMM64_DISP64 }, |
cff8d58a L |
8653 | { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real, |
8654 | BFD_RELOC_X86_64_GOTPCREL }, | |
40fb9820 | 8655 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
8656 | { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD, |
8657 | BFD_RELOC_X86_64_TLSGD }, | |
40fb9820 | 8658 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
8659 | { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM, |
8660 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 8661 | OPERAND_TYPE_NONE }, |
cff8d58a L |
8662 | { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real, |
8663 | BFD_RELOC_X86_64_TLSLD }, | |
40fb9820 | 8664 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
8665 | { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32, |
8666 | BFD_RELOC_X86_64_GOTTPOFF }, | |
40fb9820 | 8667 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
8668 | { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32, |
8669 | BFD_RELOC_X86_64_TPOFF32 }, | |
40fb9820 | 8670 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
cff8d58a L |
8671 | { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE, |
8672 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 8673 | OPERAND_TYPE_NONE }, |
cff8d58a L |
8674 | { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32, |
8675 | BFD_RELOC_X86_64_DTPOFF32 }, | |
40fb9820 | 8676 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
cff8d58a L |
8677 | { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE, |
8678 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 8679 | OPERAND_TYPE_NONE }, |
cff8d58a L |
8680 | { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE, |
8681 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 8682 | OPERAND_TYPE_NONE }, |
cff8d58a L |
8683 | { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32, |
8684 | BFD_RELOC_X86_64_GOT32 }, | |
40fb9820 | 8685 | OPERAND_TYPE_IMM32_32S_64_DISP32 }, |
cff8d58a L |
8686 | { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC, |
8687 | BFD_RELOC_X86_64_GOTPC32_TLSDESC }, | |
40fb9820 | 8688 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
8689 | { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL, |
8690 | BFD_RELOC_X86_64_TLSDESC_CALL }, | |
40fb9820 | 8691 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
f3c180ae AM |
8692 | }; |
8693 | char *cp; | |
8694 | unsigned int j; | |
8695 | ||
d382c579 | 8696 | #if defined (OBJ_MAYBE_ELF) |
718ddfc0 JB |
8697 | if (!IS_ELF) |
8698 | return NULL; | |
d382c579 | 8699 | #endif |
718ddfc0 | 8700 | |
f3c180ae | 8701 | for (cp = input_line_pointer; *cp != '@'; cp++) |
67c11a9b | 8702 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') |
f3c180ae AM |
8703 | return NULL; |
8704 | ||
47465058 | 8705 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) |
f3c180ae | 8706 | { |
cff8d58a | 8707 | int len = gotrel[j].len; |
28f81592 | 8708 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) |
f3c180ae | 8709 | { |
4fa24527 | 8710 | if (gotrel[j].rel[object_64bit] != 0) |
f3c180ae | 8711 | { |
28f81592 AM |
8712 | int first, second; |
8713 | char *tmpbuf, *past_reloc; | |
f3c180ae | 8714 | |
91d6fa6a | 8715 | *rel = gotrel[j].rel[object_64bit]; |
f3c180ae | 8716 | |
3956db08 JB |
8717 | if (types) |
8718 | { | |
8719 | if (flag_code != CODE_64BIT) | |
40fb9820 L |
8720 | { |
8721 | types->bitfield.imm32 = 1; | |
8722 | types->bitfield.disp32 = 1; | |
8723 | } | |
3956db08 JB |
8724 | else |
8725 | *types = gotrel[j].types64; | |
8726 | } | |
8727 | ||
8fd4256d | 8728 | if (j != 0 && GOT_symbol == NULL) |
f3c180ae AM |
8729 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); |
8730 | ||
28f81592 | 8731 | /* The length of the first part of our input line. */ |
f3c180ae | 8732 | first = cp - input_line_pointer; |
28f81592 AM |
8733 | |
8734 | /* The second part goes from after the reloc token until | |
67c11a9b | 8735 | (and including) an end_of_line char or comma. */ |
28f81592 | 8736 | past_reloc = cp + 1 + len; |
67c11a9b AM |
8737 | cp = past_reloc; |
8738 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') | |
8739 | ++cp; | |
8740 | second = cp + 1 - past_reloc; | |
28f81592 AM |
8741 | |
8742 | /* Allocate and copy string. The trailing NUL shouldn't | |
8743 | be necessary, but be safe. */ | |
add39d23 | 8744 | tmpbuf = XNEWVEC (char, first + second + 2); |
f3c180ae | 8745 | memcpy (tmpbuf, input_line_pointer, first); |
0787a12d AM |
8746 | if (second != 0 && *past_reloc != ' ') |
8747 | /* Replace the relocation token with ' ', so that | |
8748 | errors like foo@GOTOFF1 will be detected. */ | |
8749 | tmpbuf[first++] = ' '; | |
af89796a L |
8750 | else |
8751 | /* Increment length by 1 if the relocation token is | |
8752 | removed. */ | |
8753 | len++; | |
8754 | if (adjust) | |
8755 | *adjust = len; | |
0787a12d AM |
8756 | memcpy (tmpbuf + first, past_reloc, second); |
8757 | tmpbuf[first + second] = '\0'; | |
f3c180ae AM |
8758 | return tmpbuf; |
8759 | } | |
8760 | ||
4fa24527 JB |
8761 | as_bad (_("@%s reloc is not supported with %d-bit output format"), |
8762 | gotrel[j].str, 1 << (5 + object_64bit)); | |
f3c180ae AM |
8763 | return NULL; |
8764 | } | |
8765 | } | |
8766 | ||
8767 | /* Might be a symbol version string. Don't as_bad here. */ | |
8768 | return NULL; | |
8769 | } | |
4e4f7c87 | 8770 | #endif |
f3c180ae | 8771 | |
a988325c NC |
8772 | #ifdef TE_PE |
8773 | #ifdef lex_got | |
8774 | #undef lex_got | |
8775 | #endif | |
8776 | /* Parse operands of the form | |
8777 | <symbol>@SECREL32+<nnn> | |
8778 | ||
8779 | If we find one, set up the correct relocation in RELOC and copy the | |
8780 | input string, minus the `@SECREL32' into a malloc'd buffer for | |
8781 | parsing by the calling routine. Return this buffer, and if ADJUST | |
8782 | is non-null set it to the length of the string we removed from the | |
34bca508 L |
8783 | input line. Otherwise return NULL. |
8784 | ||
a988325c NC |
8785 | This function is copied from the ELF version above adjusted for PE targets. */ |
8786 | ||
8787 | static char * | |
8788 | lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED, | |
8789 | int *adjust ATTRIBUTE_UNUSED, | |
d258b828 | 8790 | i386_operand_type *types) |
a988325c NC |
8791 | { |
8792 | static const struct | |
8793 | { | |
8794 | const char *str; | |
8795 | int len; | |
8796 | const enum bfd_reloc_code_real rel[2]; | |
8797 | const i386_operand_type types64; | |
8798 | } | |
8799 | gotrel[] = | |
8800 | { | |
8801 | { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL, | |
8802 | BFD_RELOC_32_SECREL }, | |
8803 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, | |
8804 | }; | |
8805 | ||
8806 | char *cp; | |
8807 | unsigned j; | |
8808 | ||
8809 | for (cp = input_line_pointer; *cp != '@'; cp++) | |
8810 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') | |
8811 | return NULL; | |
8812 | ||
8813 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) | |
8814 | { | |
8815 | int len = gotrel[j].len; | |
8816 | ||
8817 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) | |
8818 | { | |
8819 | if (gotrel[j].rel[object_64bit] != 0) | |
8820 | { | |
8821 | int first, second; | |
8822 | char *tmpbuf, *past_reloc; | |
8823 | ||
8824 | *rel = gotrel[j].rel[object_64bit]; | |
8825 | if (adjust) | |
8826 | *adjust = len; | |
8827 | ||
8828 | if (types) | |
8829 | { | |
8830 | if (flag_code != CODE_64BIT) | |
8831 | { | |
8832 | types->bitfield.imm32 = 1; | |
8833 | types->bitfield.disp32 = 1; | |
8834 | } | |
8835 | else | |
8836 | *types = gotrel[j].types64; | |
8837 | } | |
8838 | ||
8839 | /* The length of the first part of our input line. */ | |
8840 | first = cp - input_line_pointer; | |
8841 | ||
8842 | /* The second part goes from after the reloc token until | |
8843 | (and including) an end_of_line char or comma. */ | |
8844 | past_reloc = cp + 1 + len; | |
8845 | cp = past_reloc; | |
8846 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') | |
8847 | ++cp; | |
8848 | second = cp + 1 - past_reloc; | |
8849 | ||
8850 | /* Allocate and copy string. The trailing NUL shouldn't | |
8851 | be necessary, but be safe. */ | |
add39d23 | 8852 | tmpbuf = XNEWVEC (char, first + second + 2); |
a988325c NC |
8853 | memcpy (tmpbuf, input_line_pointer, first); |
8854 | if (second != 0 && *past_reloc != ' ') | |
8855 | /* Replace the relocation token with ' ', so that | |
8856 | errors like foo@SECLREL321 will be detected. */ | |
8857 | tmpbuf[first++] = ' '; | |
8858 | memcpy (tmpbuf + first, past_reloc, second); | |
8859 | tmpbuf[first + second] = '\0'; | |
8860 | return tmpbuf; | |
8861 | } | |
8862 | ||
8863 | as_bad (_("@%s reloc is not supported with %d-bit output format"), | |
8864 | gotrel[j].str, 1 << (5 + object_64bit)); | |
8865 | return NULL; | |
8866 | } | |
8867 | } | |
8868 | ||
8869 | /* Might be a symbol version string. Don't as_bad here. */ | |
8870 | return NULL; | |
8871 | } | |
8872 | ||
8873 | #endif /* TE_PE */ | |
8874 | ||
62ebcb5c | 8875 | bfd_reloc_code_real_type |
e3bb37b5 | 8876 | x86_cons (expressionS *exp, int size) |
f3c180ae | 8877 | { |
62ebcb5c AM |
8878 | bfd_reloc_code_real_type got_reloc = NO_RELOC; |
8879 | ||
ee86248c JB |
8880 | intel_syntax = -intel_syntax; |
8881 | ||
3c7b9c2c | 8882 | exp->X_md = 0; |
4fa24527 | 8883 | if (size == 4 || (object_64bit && size == 8)) |
f3c180ae AM |
8884 | { |
8885 | /* Handle @GOTOFF and the like in an expression. */ | |
8886 | char *save; | |
8887 | char *gotfree_input_line; | |
4a57f2cf | 8888 | int adjust = 0; |
f3c180ae AM |
8889 | |
8890 | save = input_line_pointer; | |
d258b828 | 8891 | gotfree_input_line = lex_got (&got_reloc, &adjust, NULL); |
f3c180ae AM |
8892 | if (gotfree_input_line) |
8893 | input_line_pointer = gotfree_input_line; | |
8894 | ||
8895 | expression (exp); | |
8896 | ||
8897 | if (gotfree_input_line) | |
8898 | { | |
8899 | /* expression () has merrily parsed up to the end of line, | |
8900 | or a comma - in the wrong buffer. Transfer how far | |
8901 | input_line_pointer has moved to the right buffer. */ | |
8902 | input_line_pointer = (save | |
8903 | + (input_line_pointer - gotfree_input_line) | |
8904 | + adjust); | |
8905 | free (gotfree_input_line); | |
3992d3b7 AM |
8906 | if (exp->X_op == O_constant |
8907 | || exp->X_op == O_absent | |
8908 | || exp->X_op == O_illegal | |
0398aac5 | 8909 | || exp->X_op == O_register |
3992d3b7 AM |
8910 | || exp->X_op == O_big) |
8911 | { | |
8912 | char c = *input_line_pointer; | |
8913 | *input_line_pointer = 0; | |
8914 | as_bad (_("missing or invalid expression `%s'"), save); | |
8915 | *input_line_pointer = c; | |
8916 | } | |
f3c180ae AM |
8917 | } |
8918 | } | |
8919 | else | |
8920 | expression (exp); | |
ee86248c JB |
8921 | |
8922 | intel_syntax = -intel_syntax; | |
8923 | ||
8924 | if (intel_syntax) | |
8925 | i386_intel_simplify (exp); | |
62ebcb5c AM |
8926 | |
8927 | return got_reloc; | |
f3c180ae | 8928 | } |
f3c180ae | 8929 | |
9f32dd5b L |
8930 | static void |
8931 | signed_cons (int size) | |
6482c264 | 8932 | { |
d182319b JB |
8933 | if (flag_code == CODE_64BIT) |
8934 | cons_sign = 1; | |
8935 | cons (size); | |
8936 | cons_sign = -1; | |
6482c264 NC |
8937 | } |
8938 | ||
d182319b | 8939 | #ifdef TE_PE |
6482c264 | 8940 | static void |
7016a5d5 | 8941 | pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) |
6482c264 NC |
8942 | { |
8943 | expressionS exp; | |
8944 | ||
8945 | do | |
8946 | { | |
8947 | expression (&exp); | |
8948 | if (exp.X_op == O_symbol) | |
8949 | exp.X_op = O_secrel; | |
8950 | ||
8951 | emit_expr (&exp, 4); | |
8952 | } | |
8953 | while (*input_line_pointer++ == ','); | |
8954 | ||
8955 | input_line_pointer--; | |
8956 | demand_empty_rest_of_line (); | |
8957 | } | |
6482c264 NC |
8958 | #endif |
8959 | ||
43234a1e L |
8960 | /* Handle Vector operations. */ |
8961 | ||
8962 | static char * | |
8963 | check_VecOperations (char *op_string, char *op_end) | |
8964 | { | |
8965 | const reg_entry *mask; | |
8966 | const char *saved; | |
8967 | char *end_op; | |
8968 | ||
8969 | while (*op_string | |
8970 | && (op_end == NULL || op_string < op_end)) | |
8971 | { | |
8972 | saved = op_string; | |
8973 | if (*op_string == '{') | |
8974 | { | |
8975 | op_string++; | |
8976 | ||
8977 | /* Check broadcasts. */ | |
8978 | if (strncmp (op_string, "1to", 3) == 0) | |
8979 | { | |
8980 | int bcst_type; | |
8981 | ||
8982 | if (i.broadcast) | |
8983 | goto duplicated_vec_op; | |
8984 | ||
8985 | op_string += 3; | |
8986 | if (*op_string == '8') | |
8e6e0792 | 8987 | bcst_type = 8; |
b28d1bda | 8988 | else if (*op_string == '4') |
8e6e0792 | 8989 | bcst_type = 4; |
b28d1bda | 8990 | else if (*op_string == '2') |
8e6e0792 | 8991 | bcst_type = 2; |
43234a1e L |
8992 | else if (*op_string == '1' |
8993 | && *(op_string+1) == '6') | |
8994 | { | |
8e6e0792 | 8995 | bcst_type = 16; |
43234a1e L |
8996 | op_string++; |
8997 | } | |
8998 | else | |
8999 | { | |
9000 | as_bad (_("Unsupported broadcast: `%s'"), saved); | |
9001 | return NULL; | |
9002 | } | |
9003 | op_string++; | |
9004 | ||
9005 | broadcast_op.type = bcst_type; | |
9006 | broadcast_op.operand = this_operand; | |
1f75763a | 9007 | broadcast_op.bytes = 0; |
43234a1e L |
9008 | i.broadcast = &broadcast_op; |
9009 | } | |
9010 | /* Check masking operation. */ | |
9011 | else if ((mask = parse_register (op_string, &end_op)) != NULL) | |
9012 | { | |
9013 | /* k0 can't be used for write mask. */ | |
6d2cd6b2 | 9014 | if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0) |
43234a1e | 9015 | { |
6d2cd6b2 JB |
9016 | as_bad (_("`%s%s' can't be used for write mask"), |
9017 | register_prefix, mask->reg_name); | |
43234a1e L |
9018 | return NULL; |
9019 | } | |
9020 | ||
9021 | if (!i.mask) | |
9022 | { | |
9023 | mask_op.mask = mask; | |
9024 | mask_op.zeroing = 0; | |
9025 | mask_op.operand = this_operand; | |
9026 | i.mask = &mask_op; | |
9027 | } | |
9028 | else | |
9029 | { | |
9030 | if (i.mask->mask) | |
9031 | goto duplicated_vec_op; | |
9032 | ||
9033 | i.mask->mask = mask; | |
9034 | ||
9035 | /* Only "{z}" is allowed here. No need to check | |
9036 | zeroing mask explicitly. */ | |
9037 | if (i.mask->operand != this_operand) | |
9038 | { | |
9039 | as_bad (_("invalid write mask `%s'"), saved); | |
9040 | return NULL; | |
9041 | } | |
9042 | } | |
9043 | ||
9044 | op_string = end_op; | |
9045 | } | |
9046 | /* Check zeroing-flag for masking operation. */ | |
9047 | else if (*op_string == 'z') | |
9048 | { | |
9049 | if (!i.mask) | |
9050 | { | |
9051 | mask_op.mask = NULL; | |
9052 | mask_op.zeroing = 1; | |
9053 | mask_op.operand = this_operand; | |
9054 | i.mask = &mask_op; | |
9055 | } | |
9056 | else | |
9057 | { | |
9058 | if (i.mask->zeroing) | |
9059 | { | |
9060 | duplicated_vec_op: | |
9061 | as_bad (_("duplicated `%s'"), saved); | |
9062 | return NULL; | |
9063 | } | |
9064 | ||
9065 | i.mask->zeroing = 1; | |
9066 | ||
9067 | /* Only "{%k}" is allowed here. No need to check mask | |
9068 | register explicitly. */ | |
9069 | if (i.mask->operand != this_operand) | |
9070 | { | |
9071 | as_bad (_("invalid zeroing-masking `%s'"), | |
9072 | saved); | |
9073 | return NULL; | |
9074 | } | |
9075 | } | |
9076 | ||
9077 | op_string++; | |
9078 | } | |
9079 | else | |
9080 | goto unknown_vec_op; | |
9081 | ||
9082 | if (*op_string != '}') | |
9083 | { | |
9084 | as_bad (_("missing `}' in `%s'"), saved); | |
9085 | return NULL; | |
9086 | } | |
9087 | op_string++; | |
0ba3a731 L |
9088 | |
9089 | /* Strip whitespace since the addition of pseudo prefixes | |
9090 | changed how the scrubber treats '{'. */ | |
9091 | if (is_space_char (*op_string)) | |
9092 | ++op_string; | |
9093 | ||
43234a1e L |
9094 | continue; |
9095 | } | |
9096 | unknown_vec_op: | |
9097 | /* We don't know this one. */ | |
9098 | as_bad (_("unknown vector operation: `%s'"), saved); | |
9099 | return NULL; | |
9100 | } | |
9101 | ||
6d2cd6b2 JB |
9102 | if (i.mask && i.mask->zeroing && !i.mask->mask) |
9103 | { | |
9104 | as_bad (_("zeroing-masking only allowed with write mask")); | |
9105 | return NULL; | |
9106 | } | |
9107 | ||
43234a1e L |
9108 | return op_string; |
9109 | } | |
9110 | ||
252b5132 | 9111 | static int |
70e41ade | 9112 | i386_immediate (char *imm_start) |
252b5132 RH |
9113 | { |
9114 | char *save_input_line_pointer; | |
f3c180ae | 9115 | char *gotfree_input_line; |
252b5132 | 9116 | segT exp_seg = 0; |
47926f60 | 9117 | expressionS *exp; |
40fb9820 L |
9118 | i386_operand_type types; |
9119 | ||
0dfbf9d7 | 9120 | operand_type_set (&types, ~0); |
252b5132 RH |
9121 | |
9122 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) | |
9123 | { | |
31b2323c L |
9124 | as_bad (_("at most %d immediate operands are allowed"), |
9125 | MAX_IMMEDIATE_OPERANDS); | |
252b5132 RH |
9126 | return 0; |
9127 | } | |
9128 | ||
9129 | exp = &im_expressions[i.imm_operands++]; | |
520dc8e8 | 9130 | i.op[this_operand].imms = exp; |
252b5132 RH |
9131 | |
9132 | if (is_space_char (*imm_start)) | |
9133 | ++imm_start; | |
9134 | ||
9135 | save_input_line_pointer = input_line_pointer; | |
9136 | input_line_pointer = imm_start; | |
9137 | ||
d258b828 | 9138 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
9139 | if (gotfree_input_line) |
9140 | input_line_pointer = gotfree_input_line; | |
252b5132 RH |
9141 | |
9142 | exp_seg = expression (exp); | |
9143 | ||
83183c0c | 9144 | SKIP_WHITESPACE (); |
43234a1e L |
9145 | |
9146 | /* Handle vector operations. */ | |
9147 | if (*input_line_pointer == '{') | |
9148 | { | |
9149 | input_line_pointer = check_VecOperations (input_line_pointer, | |
9150 | NULL); | |
9151 | if (input_line_pointer == NULL) | |
9152 | return 0; | |
9153 | } | |
9154 | ||
252b5132 | 9155 | if (*input_line_pointer) |
f3c180ae | 9156 | as_bad (_("junk `%s' after expression"), input_line_pointer); |
252b5132 RH |
9157 | |
9158 | input_line_pointer = save_input_line_pointer; | |
f3c180ae | 9159 | if (gotfree_input_line) |
ee86248c JB |
9160 | { |
9161 | free (gotfree_input_line); | |
9162 | ||
9163 | if (exp->X_op == O_constant || exp->X_op == O_register) | |
9164 | exp->X_op = O_illegal; | |
9165 | } | |
9166 | ||
9167 | return i386_finalize_immediate (exp_seg, exp, types, imm_start); | |
9168 | } | |
252b5132 | 9169 | |
ee86248c JB |
9170 | static int |
9171 | i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
9172 | i386_operand_type types, const char *imm_start) | |
9173 | { | |
9174 | if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big) | |
252b5132 | 9175 | { |
313c53d1 L |
9176 | if (imm_start) |
9177 | as_bad (_("missing or invalid immediate expression `%s'"), | |
9178 | imm_start); | |
3992d3b7 | 9179 | return 0; |
252b5132 | 9180 | } |
3e73aa7c | 9181 | else if (exp->X_op == O_constant) |
252b5132 | 9182 | { |
47926f60 | 9183 | /* Size it properly later. */ |
40fb9820 | 9184 | i.types[this_operand].bitfield.imm64 = 1; |
13f864ae L |
9185 | /* If not 64bit, sign extend val. */ |
9186 | if (flag_code != CODE_64BIT | |
4eed87de AM |
9187 | && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0) |
9188 | exp->X_add_number | |
9189 | = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
252b5132 | 9190 | } |
4c63da97 | 9191 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
f86103b7 | 9192 | else if (OUTPUT_FLAVOR == bfd_target_aout_flavour |
31312f95 | 9193 | && exp_seg != absolute_section |
47926f60 | 9194 | && exp_seg != text_section |
24eab124 AM |
9195 | && exp_seg != data_section |
9196 | && exp_seg != bss_section | |
9197 | && exp_seg != undefined_section | |
f86103b7 | 9198 | && !bfd_is_com_section (exp_seg)) |
252b5132 | 9199 | { |
d0b47220 | 9200 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
252b5132 RH |
9201 | return 0; |
9202 | } | |
9203 | #endif | |
a841bdf5 | 9204 | else if (!intel_syntax && exp_seg == reg_section) |
bb8f5920 | 9205 | { |
313c53d1 L |
9206 | if (imm_start) |
9207 | as_bad (_("illegal immediate register operand %s"), imm_start); | |
bb8f5920 L |
9208 | return 0; |
9209 | } | |
252b5132 RH |
9210 | else |
9211 | { | |
9212 | /* This is an address. The size of the address will be | |
24eab124 | 9213 | determined later, depending on destination register, |
3e73aa7c | 9214 | suffix, or the default for the section. */ |
40fb9820 L |
9215 | i.types[this_operand].bitfield.imm8 = 1; |
9216 | i.types[this_operand].bitfield.imm16 = 1; | |
9217 | i.types[this_operand].bitfield.imm32 = 1; | |
9218 | i.types[this_operand].bitfield.imm32s = 1; | |
9219 | i.types[this_operand].bitfield.imm64 = 1; | |
c6fb90c8 L |
9220 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
9221 | types); | |
252b5132 RH |
9222 | } |
9223 | ||
9224 | return 1; | |
9225 | } | |
9226 | ||
551c1ca1 | 9227 | static char * |
e3bb37b5 | 9228 | i386_scale (char *scale) |
252b5132 | 9229 | { |
551c1ca1 AM |
9230 | offsetT val; |
9231 | char *save = input_line_pointer; | |
252b5132 | 9232 | |
551c1ca1 AM |
9233 | input_line_pointer = scale; |
9234 | val = get_absolute_expression (); | |
9235 | ||
9236 | switch (val) | |
252b5132 | 9237 | { |
551c1ca1 | 9238 | case 1: |
252b5132 RH |
9239 | i.log2_scale_factor = 0; |
9240 | break; | |
551c1ca1 | 9241 | case 2: |
252b5132 RH |
9242 | i.log2_scale_factor = 1; |
9243 | break; | |
551c1ca1 | 9244 | case 4: |
252b5132 RH |
9245 | i.log2_scale_factor = 2; |
9246 | break; | |
551c1ca1 | 9247 | case 8: |
252b5132 RH |
9248 | i.log2_scale_factor = 3; |
9249 | break; | |
9250 | default: | |
a724f0f4 JB |
9251 | { |
9252 | char sep = *input_line_pointer; | |
9253 | ||
9254 | *input_line_pointer = '\0'; | |
9255 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), | |
9256 | scale); | |
9257 | *input_line_pointer = sep; | |
9258 | input_line_pointer = save; | |
9259 | return NULL; | |
9260 | } | |
252b5132 | 9261 | } |
29b0f896 | 9262 | if (i.log2_scale_factor != 0 && i.index_reg == 0) |
252b5132 RH |
9263 | { |
9264 | as_warn (_("scale factor of %d without an index register"), | |
24eab124 | 9265 | 1 << i.log2_scale_factor); |
252b5132 | 9266 | i.log2_scale_factor = 0; |
252b5132 | 9267 | } |
551c1ca1 AM |
9268 | scale = input_line_pointer; |
9269 | input_line_pointer = save; | |
9270 | return scale; | |
252b5132 RH |
9271 | } |
9272 | ||
252b5132 | 9273 | static int |
e3bb37b5 | 9274 | i386_displacement (char *disp_start, char *disp_end) |
252b5132 | 9275 | { |
29b0f896 | 9276 | expressionS *exp; |
252b5132 RH |
9277 | segT exp_seg = 0; |
9278 | char *save_input_line_pointer; | |
f3c180ae | 9279 | char *gotfree_input_line; |
40fb9820 L |
9280 | int override; |
9281 | i386_operand_type bigdisp, types = anydisp; | |
3992d3b7 | 9282 | int ret; |
252b5132 | 9283 | |
31b2323c L |
9284 | if (i.disp_operands == MAX_MEMORY_OPERANDS) |
9285 | { | |
9286 | as_bad (_("at most %d displacement operands are allowed"), | |
9287 | MAX_MEMORY_OPERANDS); | |
9288 | return 0; | |
9289 | } | |
9290 | ||
0dfbf9d7 | 9291 | operand_type_set (&bigdisp, 0); |
40fb9820 L |
9292 | if ((i.types[this_operand].bitfield.jumpabsolute) |
9293 | || (!current_templates->start->opcode_modifier.jump | |
9294 | && !current_templates->start->opcode_modifier.jumpdword)) | |
e05278af | 9295 | { |
40fb9820 | 9296 | bigdisp.bitfield.disp32 = 1; |
e05278af | 9297 | override = (i.prefix[ADDR_PREFIX] != 0); |
40fb9820 L |
9298 | if (flag_code == CODE_64BIT) |
9299 | { | |
9300 | if (!override) | |
9301 | { | |
9302 | bigdisp.bitfield.disp32s = 1; | |
9303 | bigdisp.bitfield.disp64 = 1; | |
9304 | } | |
9305 | } | |
9306 | else if ((flag_code == CODE_16BIT) ^ override) | |
9307 | { | |
9308 | bigdisp.bitfield.disp32 = 0; | |
9309 | bigdisp.bitfield.disp16 = 1; | |
9310 | } | |
e05278af JB |
9311 | } |
9312 | else | |
9313 | { | |
9314 | /* For PC-relative branches, the width of the displacement | |
9315 | is dependent upon data size, not address size. */ | |
e05278af | 9316 | override = (i.prefix[DATA_PREFIX] != 0); |
40fb9820 L |
9317 | if (flag_code == CODE_64BIT) |
9318 | { | |
9319 | if (override || i.suffix == WORD_MNEM_SUFFIX) | |
9320 | bigdisp.bitfield.disp16 = 1; | |
9321 | else | |
9322 | { | |
9323 | bigdisp.bitfield.disp32 = 1; | |
9324 | bigdisp.bitfield.disp32s = 1; | |
9325 | } | |
9326 | } | |
9327 | else | |
e05278af JB |
9328 | { |
9329 | if (!override) | |
9330 | override = (i.suffix == (flag_code != CODE_16BIT | |
9331 | ? WORD_MNEM_SUFFIX | |
9332 | : LONG_MNEM_SUFFIX)); | |
40fb9820 L |
9333 | bigdisp.bitfield.disp32 = 1; |
9334 | if ((flag_code == CODE_16BIT) ^ override) | |
9335 | { | |
9336 | bigdisp.bitfield.disp32 = 0; | |
9337 | bigdisp.bitfield.disp16 = 1; | |
9338 | } | |
e05278af | 9339 | } |
e05278af | 9340 | } |
c6fb90c8 L |
9341 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
9342 | bigdisp); | |
252b5132 RH |
9343 | |
9344 | exp = &disp_expressions[i.disp_operands]; | |
520dc8e8 | 9345 | i.op[this_operand].disps = exp; |
252b5132 RH |
9346 | i.disp_operands++; |
9347 | save_input_line_pointer = input_line_pointer; | |
9348 | input_line_pointer = disp_start; | |
9349 | END_STRING_AND_SAVE (disp_end); | |
9350 | ||
9351 | #ifndef GCC_ASM_O_HACK | |
9352 | #define GCC_ASM_O_HACK 0 | |
9353 | #endif | |
9354 | #if GCC_ASM_O_HACK | |
9355 | END_STRING_AND_SAVE (disp_end + 1); | |
40fb9820 | 9356 | if (i.types[this_operand].bitfield.baseIndex |
24eab124 | 9357 | && displacement_string_end[-1] == '+') |
252b5132 RH |
9358 | { |
9359 | /* This hack is to avoid a warning when using the "o" | |
24eab124 AM |
9360 | constraint within gcc asm statements. |
9361 | For instance: | |
9362 | ||
9363 | #define _set_tssldt_desc(n,addr,limit,type) \ | |
9364 | __asm__ __volatile__ ( \ | |
9365 | "movw %w2,%0\n\t" \ | |
9366 | "movw %w1,2+%0\n\t" \ | |
9367 | "rorl $16,%1\n\t" \ | |
9368 | "movb %b1,4+%0\n\t" \ | |
9369 | "movb %4,5+%0\n\t" \ | |
9370 | "movb $0,6+%0\n\t" \ | |
9371 | "movb %h1,7+%0\n\t" \ | |
9372 | "rorl $16,%1" \ | |
9373 | : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) | |
9374 | ||
9375 | This works great except that the output assembler ends | |
9376 | up looking a bit weird if it turns out that there is | |
9377 | no offset. You end up producing code that looks like: | |
9378 | ||
9379 | #APP | |
9380 | movw $235,(%eax) | |
9381 | movw %dx,2+(%eax) | |
9382 | rorl $16,%edx | |
9383 | movb %dl,4+(%eax) | |
9384 | movb $137,5+(%eax) | |
9385 | movb $0,6+(%eax) | |
9386 | movb %dh,7+(%eax) | |
9387 | rorl $16,%edx | |
9388 | #NO_APP | |
9389 | ||
47926f60 | 9390 | So here we provide the missing zero. */ |
24eab124 AM |
9391 | |
9392 | *displacement_string_end = '0'; | |
252b5132 RH |
9393 | } |
9394 | #endif | |
d258b828 | 9395 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
9396 | if (gotfree_input_line) |
9397 | input_line_pointer = gotfree_input_line; | |
252b5132 | 9398 | |
24eab124 | 9399 | exp_seg = expression (exp); |
252b5132 | 9400 | |
636c26b0 AM |
9401 | SKIP_WHITESPACE (); |
9402 | if (*input_line_pointer) | |
9403 | as_bad (_("junk `%s' after expression"), input_line_pointer); | |
9404 | #if GCC_ASM_O_HACK | |
9405 | RESTORE_END_STRING (disp_end + 1); | |
9406 | #endif | |
636c26b0 | 9407 | input_line_pointer = save_input_line_pointer; |
636c26b0 | 9408 | if (gotfree_input_line) |
ee86248c JB |
9409 | { |
9410 | free (gotfree_input_line); | |
9411 | ||
9412 | if (exp->X_op == O_constant || exp->X_op == O_register) | |
9413 | exp->X_op = O_illegal; | |
9414 | } | |
9415 | ||
9416 | ret = i386_finalize_displacement (exp_seg, exp, types, disp_start); | |
9417 | ||
9418 | RESTORE_END_STRING (disp_end); | |
9419 | ||
9420 | return ret; | |
9421 | } | |
9422 | ||
9423 | static int | |
9424 | i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
9425 | i386_operand_type types, const char *disp_start) | |
9426 | { | |
9427 | i386_operand_type bigdisp; | |
9428 | int ret = 1; | |
636c26b0 | 9429 | |
24eab124 AM |
9430 | /* We do this to make sure that the section symbol is in |
9431 | the symbol table. We will ultimately change the relocation | |
47926f60 | 9432 | to be relative to the beginning of the section. */ |
1ae12ab7 | 9433 | if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF |
d6ab8113 JB |
9434 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL |
9435 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) | |
24eab124 | 9436 | { |
636c26b0 | 9437 | if (exp->X_op != O_symbol) |
3992d3b7 | 9438 | goto inv_disp; |
636c26b0 | 9439 | |
e5cb08ac | 9440 | if (S_IS_LOCAL (exp->X_add_symbol) |
c64efb4b L |
9441 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section |
9442 | && S_GET_SEGMENT (exp->X_add_symbol) != expr_section) | |
24eab124 | 9443 | section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); |
24eab124 AM |
9444 | exp->X_op = O_subtract; |
9445 | exp->X_op_symbol = GOT_symbol; | |
1ae12ab7 | 9446 | if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) |
29b0f896 | 9447 | i.reloc[this_operand] = BFD_RELOC_32_PCREL; |
d6ab8113 JB |
9448 | else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) |
9449 | i.reloc[this_operand] = BFD_RELOC_64; | |
23df1078 | 9450 | else |
29b0f896 | 9451 | i.reloc[this_operand] = BFD_RELOC_32; |
24eab124 | 9452 | } |
252b5132 | 9453 | |
3992d3b7 AM |
9454 | else if (exp->X_op == O_absent |
9455 | || exp->X_op == O_illegal | |
ee86248c | 9456 | || exp->X_op == O_big) |
2daf4fd8 | 9457 | { |
3992d3b7 AM |
9458 | inv_disp: |
9459 | as_bad (_("missing or invalid displacement expression `%s'"), | |
2daf4fd8 | 9460 | disp_start); |
3992d3b7 | 9461 | ret = 0; |
2daf4fd8 AM |
9462 | } |
9463 | ||
0e1147d9 L |
9464 | else if (flag_code == CODE_64BIT |
9465 | && !i.prefix[ADDR_PREFIX] | |
9466 | && exp->X_op == O_constant) | |
9467 | { | |
9468 | /* Since displacement is signed extended to 64bit, don't allow | |
9469 | disp32 and turn off disp32s if they are out of range. */ | |
9470 | i.types[this_operand].bitfield.disp32 = 0; | |
9471 | if (!fits_in_signed_long (exp->X_add_number)) | |
9472 | { | |
9473 | i.types[this_operand].bitfield.disp32s = 0; | |
9474 | if (i.types[this_operand].bitfield.baseindex) | |
9475 | { | |
9476 | as_bad (_("0x%lx out range of signed 32bit displacement"), | |
9477 | (long) exp->X_add_number); | |
9478 | ret = 0; | |
9479 | } | |
9480 | } | |
9481 | } | |
9482 | ||
4c63da97 | 9483 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
3992d3b7 AM |
9484 | else if (exp->X_op != O_constant |
9485 | && OUTPUT_FLAVOR == bfd_target_aout_flavour | |
9486 | && exp_seg != absolute_section | |
9487 | && exp_seg != text_section | |
9488 | && exp_seg != data_section | |
9489 | && exp_seg != bss_section | |
9490 | && exp_seg != undefined_section | |
9491 | && !bfd_is_com_section (exp_seg)) | |
24eab124 | 9492 | { |
d0b47220 | 9493 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
3992d3b7 | 9494 | ret = 0; |
24eab124 | 9495 | } |
252b5132 | 9496 | #endif |
3956db08 | 9497 | |
40fb9820 L |
9498 | /* Check if this is a displacement only operand. */ |
9499 | bigdisp = i.types[this_operand]; | |
9500 | bigdisp.bitfield.disp8 = 0; | |
9501 | bigdisp.bitfield.disp16 = 0; | |
9502 | bigdisp.bitfield.disp32 = 0; | |
9503 | bigdisp.bitfield.disp32s = 0; | |
9504 | bigdisp.bitfield.disp64 = 0; | |
0dfbf9d7 | 9505 | if (operand_type_all_zero (&bigdisp)) |
c6fb90c8 L |
9506 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
9507 | types); | |
3956db08 | 9508 | |
3992d3b7 | 9509 | return ret; |
252b5132 RH |
9510 | } |
9511 | ||
2abc2bec JB |
9512 | /* Return the active addressing mode, taking address override and |
9513 | registers forming the address into consideration. Update the | |
9514 | address override prefix if necessary. */ | |
47926f60 | 9515 | |
2abc2bec JB |
9516 | static enum flag_code |
9517 | i386_addressing_mode (void) | |
252b5132 | 9518 | { |
be05d201 L |
9519 | enum flag_code addr_mode; |
9520 | ||
9521 | if (i.prefix[ADDR_PREFIX]) | |
9522 | addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT; | |
9523 | else | |
9524 | { | |
9525 | addr_mode = flag_code; | |
9526 | ||
24eab124 | 9527 | #if INFER_ADDR_PREFIX |
be05d201 L |
9528 | if (i.mem_operands == 0) |
9529 | { | |
9530 | /* Infer address prefix from the first memory operand. */ | |
9531 | const reg_entry *addr_reg = i.base_reg; | |
9532 | ||
9533 | if (addr_reg == NULL) | |
9534 | addr_reg = i.index_reg; | |
eecb386c | 9535 | |
be05d201 L |
9536 | if (addr_reg) |
9537 | { | |
e968fc9b | 9538 | if (addr_reg->reg_type.bitfield.dword) |
be05d201 L |
9539 | addr_mode = CODE_32BIT; |
9540 | else if (flag_code != CODE_64BIT | |
dc821c5f | 9541 | && addr_reg->reg_type.bitfield.word) |
be05d201 L |
9542 | addr_mode = CODE_16BIT; |
9543 | ||
9544 | if (addr_mode != flag_code) | |
9545 | { | |
9546 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
9547 | i.prefixes += 1; | |
9548 | /* Change the size of any displacement too. At most one | |
9549 | of Disp16 or Disp32 is set. | |
9550 | FIXME. There doesn't seem to be any real need for | |
9551 | separate Disp16 and Disp32 flags. The same goes for | |
9552 | Imm16 and Imm32. Removing them would probably clean | |
9553 | up the code quite a lot. */ | |
9554 | if (flag_code != CODE_64BIT | |
9555 | && (i.types[this_operand].bitfield.disp16 | |
9556 | || i.types[this_operand].bitfield.disp32)) | |
9557 | i.types[this_operand] | |
9558 | = operand_type_xor (i.types[this_operand], disp16_32); | |
9559 | } | |
9560 | } | |
9561 | } | |
24eab124 | 9562 | #endif |
be05d201 L |
9563 | } |
9564 | ||
2abc2bec JB |
9565 | return addr_mode; |
9566 | } | |
9567 | ||
9568 | /* Make sure the memory operand we've been dealt is valid. | |
9569 | Return 1 on success, 0 on a failure. */ | |
9570 | ||
9571 | static int | |
9572 | i386_index_check (const char *operand_string) | |
9573 | { | |
9574 | const char *kind = "base/index"; | |
9575 | enum flag_code addr_mode = i386_addressing_mode (); | |
9576 | ||
fc0763e6 JB |
9577 | if (current_templates->start->opcode_modifier.isstring |
9578 | && !current_templates->start->opcode_modifier.immext | |
9579 | && (current_templates->end[-1].opcode_modifier.isstring | |
9580 | || i.mem_operands)) | |
9581 | { | |
9582 | /* Memory operands of string insns are special in that they only allow | |
9583 | a single register (rDI, rSI, or rBX) as their memory address. */ | |
be05d201 L |
9584 | const reg_entry *expected_reg; |
9585 | static const char *di_si[][2] = | |
9586 | { | |
9587 | { "esi", "edi" }, | |
9588 | { "si", "di" }, | |
9589 | { "rsi", "rdi" } | |
9590 | }; | |
9591 | static const char *bx[] = { "ebx", "bx", "rbx" }; | |
fc0763e6 JB |
9592 | |
9593 | kind = "string address"; | |
9594 | ||
8325cc63 | 9595 | if (current_templates->start->opcode_modifier.repprefixok) |
fc0763e6 JB |
9596 | { |
9597 | i386_operand_type type = current_templates->end[-1].operand_types[0]; | |
9598 | ||
9599 | if (!type.bitfield.baseindex | |
9600 | || ((!i.mem_operands != !intel_syntax) | |
9601 | && current_templates->end[-1].operand_types[1] | |
9602 | .bitfield.baseindex)) | |
9603 | type = current_templates->end[-1].operand_types[1]; | |
be05d201 L |
9604 | expected_reg = hash_find (reg_hash, |
9605 | di_si[addr_mode][type.bitfield.esseg]); | |
9606 | ||
fc0763e6 JB |
9607 | } |
9608 | else | |
be05d201 | 9609 | expected_reg = hash_find (reg_hash, bx[addr_mode]); |
fc0763e6 | 9610 | |
be05d201 L |
9611 | if (i.base_reg != expected_reg |
9612 | || i.index_reg | |
fc0763e6 | 9613 | || operand_type_check (i.types[this_operand], disp)) |
fc0763e6 | 9614 | { |
be05d201 L |
9615 | /* The second memory operand must have the same size as |
9616 | the first one. */ | |
9617 | if (i.mem_operands | |
9618 | && i.base_reg | |
9619 | && !((addr_mode == CODE_64BIT | |
dc821c5f | 9620 | && i.base_reg->reg_type.bitfield.qword) |
be05d201 | 9621 | || (addr_mode == CODE_32BIT |
dc821c5f JB |
9622 | ? i.base_reg->reg_type.bitfield.dword |
9623 | : i.base_reg->reg_type.bitfield.word))) | |
be05d201 L |
9624 | goto bad_address; |
9625 | ||
fc0763e6 JB |
9626 | as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"), |
9627 | operand_string, | |
9628 | intel_syntax ? '[' : '(', | |
9629 | register_prefix, | |
be05d201 | 9630 | expected_reg->reg_name, |
fc0763e6 | 9631 | intel_syntax ? ']' : ')'); |
be05d201 | 9632 | return 1; |
fc0763e6 | 9633 | } |
be05d201 L |
9634 | else |
9635 | return 1; | |
9636 | ||
9637 | bad_address: | |
9638 | as_bad (_("`%s' is not a valid %s expression"), | |
9639 | operand_string, kind); | |
9640 | return 0; | |
3e73aa7c JH |
9641 | } |
9642 | else | |
9643 | { | |
be05d201 L |
9644 | if (addr_mode != CODE_16BIT) |
9645 | { | |
9646 | /* 32-bit/64-bit checks. */ | |
9647 | if ((i.base_reg | |
e968fc9b JB |
9648 | && ((addr_mode == CODE_64BIT |
9649 | ? !i.base_reg->reg_type.bitfield.qword | |
9650 | : !i.base_reg->reg_type.bitfield.dword) | |
9651 | || (i.index_reg && i.base_reg->reg_num == RegIP) | |
9652 | || i.base_reg->reg_num == RegIZ)) | |
be05d201 | 9653 | || (i.index_reg |
1b54b8d7 JB |
9654 | && !i.index_reg->reg_type.bitfield.xmmword |
9655 | && !i.index_reg->reg_type.bitfield.ymmword | |
9656 | && !i.index_reg->reg_type.bitfield.zmmword | |
be05d201 | 9657 | && ((addr_mode == CODE_64BIT |
e968fc9b JB |
9658 | ? !i.index_reg->reg_type.bitfield.qword |
9659 | : !i.index_reg->reg_type.bitfield.dword) | |
be05d201 L |
9660 | || !i.index_reg->reg_type.bitfield.baseindex))) |
9661 | goto bad_address; | |
8178be5b JB |
9662 | |
9663 | /* bndmk, bndldx, and bndstx have special restrictions. */ | |
9664 | if (current_templates->start->base_opcode == 0xf30f1b | |
9665 | || (current_templates->start->base_opcode & ~1) == 0x0f1a) | |
9666 | { | |
9667 | /* They cannot use RIP-relative addressing. */ | |
e968fc9b | 9668 | if (i.base_reg && i.base_reg->reg_num == RegIP) |
8178be5b JB |
9669 | { |
9670 | as_bad (_("`%s' cannot be used here"), operand_string); | |
9671 | return 0; | |
9672 | } | |
9673 | ||
9674 | /* bndldx and bndstx ignore their scale factor. */ | |
9675 | if (current_templates->start->base_opcode != 0xf30f1b | |
9676 | && i.log2_scale_factor) | |
9677 | as_warn (_("register scaling is being ignored here")); | |
9678 | } | |
be05d201 L |
9679 | } |
9680 | else | |
3e73aa7c | 9681 | { |
be05d201 | 9682 | /* 16-bit checks. */ |
3e73aa7c | 9683 | if ((i.base_reg |
dc821c5f | 9684 | && (!i.base_reg->reg_type.bitfield.word |
40fb9820 | 9685 | || !i.base_reg->reg_type.bitfield.baseindex)) |
3e73aa7c | 9686 | || (i.index_reg |
dc821c5f | 9687 | && (!i.index_reg->reg_type.bitfield.word |
40fb9820 | 9688 | || !i.index_reg->reg_type.bitfield.baseindex |
29b0f896 AM |
9689 | || !(i.base_reg |
9690 | && i.base_reg->reg_num < 6 | |
9691 | && i.index_reg->reg_num >= 6 | |
9692 | && i.log2_scale_factor == 0)))) | |
be05d201 | 9693 | goto bad_address; |
3e73aa7c JH |
9694 | } |
9695 | } | |
be05d201 | 9696 | return 1; |
24eab124 | 9697 | } |
252b5132 | 9698 | |
43234a1e L |
9699 | /* Handle vector immediates. */ |
9700 | ||
9701 | static int | |
9702 | RC_SAE_immediate (const char *imm_start) | |
9703 | { | |
9704 | unsigned int match_found, j; | |
9705 | const char *pstr = imm_start; | |
9706 | expressionS *exp; | |
9707 | ||
9708 | if (*pstr != '{') | |
9709 | return 0; | |
9710 | ||
9711 | pstr++; | |
9712 | match_found = 0; | |
9713 | for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++) | |
9714 | { | |
9715 | if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len)) | |
9716 | { | |
9717 | if (!i.rounding) | |
9718 | { | |
9719 | rc_op.type = RC_NamesTable[j].type; | |
9720 | rc_op.operand = this_operand; | |
9721 | i.rounding = &rc_op; | |
9722 | } | |
9723 | else | |
9724 | { | |
9725 | as_bad (_("duplicated `%s'"), imm_start); | |
9726 | return 0; | |
9727 | } | |
9728 | pstr += RC_NamesTable[j].len; | |
9729 | match_found = 1; | |
9730 | break; | |
9731 | } | |
9732 | } | |
9733 | if (!match_found) | |
9734 | return 0; | |
9735 | ||
9736 | if (*pstr++ != '}') | |
9737 | { | |
9738 | as_bad (_("Missing '}': '%s'"), imm_start); | |
9739 | return 0; | |
9740 | } | |
9741 | /* RC/SAE immediate string should contain nothing more. */; | |
9742 | if (*pstr != 0) | |
9743 | { | |
9744 | as_bad (_("Junk after '}': '%s'"), imm_start); | |
9745 | return 0; | |
9746 | } | |
9747 | ||
9748 | exp = &im_expressions[i.imm_operands++]; | |
9749 | i.op[this_operand].imms = exp; | |
9750 | ||
9751 | exp->X_op = O_constant; | |
9752 | exp->X_add_number = 0; | |
9753 | exp->X_add_symbol = (symbolS *) 0; | |
9754 | exp->X_op_symbol = (symbolS *) 0; | |
9755 | ||
9756 | i.types[this_operand].bitfield.imm8 = 1; | |
9757 | return 1; | |
9758 | } | |
9759 | ||
8325cc63 JB |
9760 | /* Only string instructions can have a second memory operand, so |
9761 | reduce current_templates to just those if it contains any. */ | |
9762 | static int | |
9763 | maybe_adjust_templates (void) | |
9764 | { | |
9765 | const insn_template *t; | |
9766 | ||
9767 | gas_assert (i.mem_operands == 1); | |
9768 | ||
9769 | for (t = current_templates->start; t < current_templates->end; ++t) | |
9770 | if (t->opcode_modifier.isstring) | |
9771 | break; | |
9772 | ||
9773 | if (t < current_templates->end) | |
9774 | { | |
9775 | static templates aux_templates; | |
9776 | bfd_boolean recheck; | |
9777 | ||
9778 | aux_templates.start = t; | |
9779 | for (; t < current_templates->end; ++t) | |
9780 | if (!t->opcode_modifier.isstring) | |
9781 | break; | |
9782 | aux_templates.end = t; | |
9783 | ||
9784 | /* Determine whether to re-check the first memory operand. */ | |
9785 | recheck = (aux_templates.start != current_templates->start | |
9786 | || t != current_templates->end); | |
9787 | ||
9788 | current_templates = &aux_templates; | |
9789 | ||
9790 | if (recheck) | |
9791 | { | |
9792 | i.mem_operands = 0; | |
9793 | if (i.memop1_string != NULL | |
9794 | && i386_index_check (i.memop1_string) == 0) | |
9795 | return 0; | |
9796 | i.mem_operands = 1; | |
9797 | } | |
9798 | } | |
9799 | ||
9800 | return 1; | |
9801 | } | |
9802 | ||
fc0763e6 | 9803 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero |
47926f60 | 9804 | on error. */ |
252b5132 | 9805 | |
252b5132 | 9806 | static int |
a7619375 | 9807 | i386_att_operand (char *operand_string) |
252b5132 | 9808 | { |
af6bdddf AM |
9809 | const reg_entry *r; |
9810 | char *end_op; | |
24eab124 | 9811 | char *op_string = operand_string; |
252b5132 | 9812 | |
24eab124 | 9813 | if (is_space_char (*op_string)) |
252b5132 RH |
9814 | ++op_string; |
9815 | ||
24eab124 | 9816 | /* We check for an absolute prefix (differentiating, |
47926f60 | 9817 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ |
24eab124 AM |
9818 | if (*op_string == ABSOLUTE_PREFIX) |
9819 | { | |
9820 | ++op_string; | |
9821 | if (is_space_char (*op_string)) | |
9822 | ++op_string; | |
40fb9820 | 9823 | i.types[this_operand].bitfield.jumpabsolute = 1; |
24eab124 | 9824 | } |
252b5132 | 9825 | |
47926f60 | 9826 | /* Check if operand is a register. */ |
4d1bb795 | 9827 | if ((r = parse_register (op_string, &end_op)) != NULL) |
24eab124 | 9828 | { |
40fb9820 L |
9829 | i386_operand_type temp; |
9830 | ||
24eab124 AM |
9831 | /* Check for a segment override by searching for ':' after a |
9832 | segment register. */ | |
9833 | op_string = end_op; | |
9834 | if (is_space_char (*op_string)) | |
9835 | ++op_string; | |
40fb9820 L |
9836 | if (*op_string == ':' |
9837 | && (r->reg_type.bitfield.sreg2 | |
9838 | || r->reg_type.bitfield.sreg3)) | |
24eab124 AM |
9839 | { |
9840 | switch (r->reg_num) | |
9841 | { | |
9842 | case 0: | |
9843 | i.seg[i.mem_operands] = &es; | |
9844 | break; | |
9845 | case 1: | |
9846 | i.seg[i.mem_operands] = &cs; | |
9847 | break; | |
9848 | case 2: | |
9849 | i.seg[i.mem_operands] = &ss; | |
9850 | break; | |
9851 | case 3: | |
9852 | i.seg[i.mem_operands] = &ds; | |
9853 | break; | |
9854 | case 4: | |
9855 | i.seg[i.mem_operands] = &fs; | |
9856 | break; | |
9857 | case 5: | |
9858 | i.seg[i.mem_operands] = &gs; | |
9859 | break; | |
9860 | } | |
252b5132 | 9861 | |
24eab124 | 9862 | /* Skip the ':' and whitespace. */ |
252b5132 RH |
9863 | ++op_string; |
9864 | if (is_space_char (*op_string)) | |
24eab124 | 9865 | ++op_string; |
252b5132 | 9866 | |
24eab124 AM |
9867 | if (!is_digit_char (*op_string) |
9868 | && !is_identifier_char (*op_string) | |
9869 | && *op_string != '(' | |
9870 | && *op_string != ABSOLUTE_PREFIX) | |
9871 | { | |
9872 | as_bad (_("bad memory operand `%s'"), op_string); | |
9873 | return 0; | |
9874 | } | |
47926f60 | 9875 | /* Handle case of %es:*foo. */ |
24eab124 AM |
9876 | if (*op_string == ABSOLUTE_PREFIX) |
9877 | { | |
9878 | ++op_string; | |
9879 | if (is_space_char (*op_string)) | |
9880 | ++op_string; | |
40fb9820 | 9881 | i.types[this_operand].bitfield.jumpabsolute = 1; |
24eab124 AM |
9882 | } |
9883 | goto do_memory_reference; | |
9884 | } | |
43234a1e L |
9885 | |
9886 | /* Handle vector operations. */ | |
9887 | if (*op_string == '{') | |
9888 | { | |
9889 | op_string = check_VecOperations (op_string, NULL); | |
9890 | if (op_string == NULL) | |
9891 | return 0; | |
9892 | } | |
9893 | ||
24eab124 AM |
9894 | if (*op_string) |
9895 | { | |
d0b47220 | 9896 | as_bad (_("junk `%s' after register"), op_string); |
24eab124 AM |
9897 | return 0; |
9898 | } | |
40fb9820 L |
9899 | temp = r->reg_type; |
9900 | temp.bitfield.baseindex = 0; | |
c6fb90c8 L |
9901 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
9902 | temp); | |
7d5e4556 | 9903 | i.types[this_operand].bitfield.unspecified = 0; |
520dc8e8 | 9904 | i.op[this_operand].regs = r; |
24eab124 AM |
9905 | i.reg_operands++; |
9906 | } | |
af6bdddf AM |
9907 | else if (*op_string == REGISTER_PREFIX) |
9908 | { | |
9909 | as_bad (_("bad register name `%s'"), op_string); | |
9910 | return 0; | |
9911 | } | |
24eab124 | 9912 | else if (*op_string == IMMEDIATE_PREFIX) |
ce8a8b2f | 9913 | { |
24eab124 | 9914 | ++op_string; |
40fb9820 | 9915 | if (i.types[this_operand].bitfield.jumpabsolute) |
24eab124 | 9916 | { |
d0b47220 | 9917 | as_bad (_("immediate operand illegal with absolute jump")); |
24eab124 AM |
9918 | return 0; |
9919 | } | |
9920 | if (!i386_immediate (op_string)) | |
9921 | return 0; | |
9922 | } | |
43234a1e L |
9923 | else if (RC_SAE_immediate (operand_string)) |
9924 | { | |
9925 | /* If it is a RC or SAE immediate, do nothing. */ | |
9926 | ; | |
9927 | } | |
24eab124 AM |
9928 | else if (is_digit_char (*op_string) |
9929 | || is_identifier_char (*op_string) | |
d02603dc | 9930 | || *op_string == '"' |
e5cb08ac | 9931 | || *op_string == '(') |
24eab124 | 9932 | { |
47926f60 | 9933 | /* This is a memory reference of some sort. */ |
af6bdddf | 9934 | char *base_string; |
252b5132 | 9935 | |
47926f60 | 9936 | /* Start and end of displacement string expression (if found). */ |
eecb386c AM |
9937 | char *displacement_string_start; |
9938 | char *displacement_string_end; | |
43234a1e | 9939 | char *vop_start; |
252b5132 | 9940 | |
24eab124 | 9941 | do_memory_reference: |
8325cc63 JB |
9942 | if (i.mem_operands == 1 && !maybe_adjust_templates ()) |
9943 | return 0; | |
24eab124 | 9944 | if ((i.mem_operands == 1 |
40fb9820 | 9945 | && !current_templates->start->opcode_modifier.isstring) |
24eab124 AM |
9946 | || i.mem_operands == 2) |
9947 | { | |
9948 | as_bad (_("too many memory references for `%s'"), | |
9949 | current_templates->start->name); | |
9950 | return 0; | |
9951 | } | |
252b5132 | 9952 | |
24eab124 AM |
9953 | /* Check for base index form. We detect the base index form by |
9954 | looking for an ')' at the end of the operand, searching | |
9955 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' | |
9956 | after the '('. */ | |
af6bdddf | 9957 | base_string = op_string + strlen (op_string); |
c3332e24 | 9958 | |
43234a1e L |
9959 | /* Handle vector operations. */ |
9960 | vop_start = strchr (op_string, '{'); | |
9961 | if (vop_start && vop_start < base_string) | |
9962 | { | |
9963 | if (check_VecOperations (vop_start, base_string) == NULL) | |
9964 | return 0; | |
9965 | base_string = vop_start; | |
9966 | } | |
9967 | ||
af6bdddf AM |
9968 | --base_string; |
9969 | if (is_space_char (*base_string)) | |
9970 | --base_string; | |
252b5132 | 9971 | |
47926f60 | 9972 | /* If we only have a displacement, set-up for it to be parsed later. */ |
af6bdddf AM |
9973 | displacement_string_start = op_string; |
9974 | displacement_string_end = base_string + 1; | |
252b5132 | 9975 | |
24eab124 AM |
9976 | if (*base_string == ')') |
9977 | { | |
af6bdddf | 9978 | char *temp_string; |
24eab124 AM |
9979 | unsigned int parens_balanced = 1; |
9980 | /* We've already checked that the number of left & right ()'s are | |
47926f60 | 9981 | equal, so this loop will not be infinite. */ |
24eab124 AM |
9982 | do |
9983 | { | |
9984 | base_string--; | |
9985 | if (*base_string == ')') | |
9986 | parens_balanced++; | |
9987 | if (*base_string == '(') | |
9988 | parens_balanced--; | |
9989 | } | |
9990 | while (parens_balanced); | |
c3332e24 | 9991 | |
af6bdddf | 9992 | temp_string = base_string; |
c3332e24 | 9993 | |
24eab124 | 9994 | /* Skip past '(' and whitespace. */ |
252b5132 RH |
9995 | ++base_string; |
9996 | if (is_space_char (*base_string)) | |
24eab124 | 9997 | ++base_string; |
252b5132 | 9998 | |
af6bdddf | 9999 | if (*base_string == ',' |
4eed87de AM |
10000 | || ((i.base_reg = parse_register (base_string, &end_op)) |
10001 | != NULL)) | |
252b5132 | 10002 | { |
af6bdddf | 10003 | displacement_string_end = temp_string; |
252b5132 | 10004 | |
40fb9820 | 10005 | i.types[this_operand].bitfield.baseindex = 1; |
252b5132 | 10006 | |
af6bdddf | 10007 | if (i.base_reg) |
24eab124 | 10008 | { |
24eab124 AM |
10009 | base_string = end_op; |
10010 | if (is_space_char (*base_string)) | |
10011 | ++base_string; | |
af6bdddf AM |
10012 | } |
10013 | ||
10014 | /* There may be an index reg or scale factor here. */ | |
10015 | if (*base_string == ',') | |
10016 | { | |
10017 | ++base_string; | |
10018 | if (is_space_char (*base_string)) | |
10019 | ++base_string; | |
10020 | ||
4eed87de AM |
10021 | if ((i.index_reg = parse_register (base_string, &end_op)) |
10022 | != NULL) | |
24eab124 | 10023 | { |
af6bdddf | 10024 | base_string = end_op; |
24eab124 AM |
10025 | if (is_space_char (*base_string)) |
10026 | ++base_string; | |
af6bdddf AM |
10027 | if (*base_string == ',') |
10028 | { | |
10029 | ++base_string; | |
10030 | if (is_space_char (*base_string)) | |
10031 | ++base_string; | |
10032 | } | |
e5cb08ac | 10033 | else if (*base_string != ')') |
af6bdddf | 10034 | { |
4eed87de AM |
10035 | as_bad (_("expecting `,' or `)' " |
10036 | "after index register in `%s'"), | |
af6bdddf AM |
10037 | operand_string); |
10038 | return 0; | |
10039 | } | |
24eab124 | 10040 | } |
af6bdddf | 10041 | else if (*base_string == REGISTER_PREFIX) |
24eab124 | 10042 | { |
f76bf5e0 L |
10043 | end_op = strchr (base_string, ','); |
10044 | if (end_op) | |
10045 | *end_op = '\0'; | |
af6bdddf | 10046 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 AM |
10047 | return 0; |
10048 | } | |
252b5132 | 10049 | |
47926f60 | 10050 | /* Check for scale factor. */ |
551c1ca1 | 10051 | if (*base_string != ')') |
af6bdddf | 10052 | { |
551c1ca1 AM |
10053 | char *end_scale = i386_scale (base_string); |
10054 | ||
10055 | if (!end_scale) | |
af6bdddf | 10056 | return 0; |
24eab124 | 10057 | |
551c1ca1 | 10058 | base_string = end_scale; |
af6bdddf AM |
10059 | if (is_space_char (*base_string)) |
10060 | ++base_string; | |
10061 | if (*base_string != ')') | |
10062 | { | |
4eed87de AM |
10063 | as_bad (_("expecting `)' " |
10064 | "after scale factor in `%s'"), | |
af6bdddf AM |
10065 | operand_string); |
10066 | return 0; | |
10067 | } | |
10068 | } | |
10069 | else if (!i.index_reg) | |
24eab124 | 10070 | { |
4eed87de AM |
10071 | as_bad (_("expecting index register or scale factor " |
10072 | "after `,'; got '%c'"), | |
af6bdddf | 10073 | *base_string); |
24eab124 AM |
10074 | return 0; |
10075 | } | |
10076 | } | |
af6bdddf | 10077 | else if (*base_string != ')') |
24eab124 | 10078 | { |
4eed87de AM |
10079 | as_bad (_("expecting `,' or `)' " |
10080 | "after base register in `%s'"), | |
af6bdddf | 10081 | operand_string); |
24eab124 AM |
10082 | return 0; |
10083 | } | |
c3332e24 | 10084 | } |
af6bdddf | 10085 | else if (*base_string == REGISTER_PREFIX) |
c3332e24 | 10086 | { |
f76bf5e0 L |
10087 | end_op = strchr (base_string, ','); |
10088 | if (end_op) | |
10089 | *end_op = '\0'; | |
af6bdddf | 10090 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 | 10091 | return 0; |
c3332e24 | 10092 | } |
24eab124 AM |
10093 | } |
10094 | ||
10095 | /* If there's an expression beginning the operand, parse it, | |
10096 | assuming displacement_string_start and | |
10097 | displacement_string_end are meaningful. */ | |
10098 | if (displacement_string_start != displacement_string_end) | |
10099 | { | |
10100 | if (!i386_displacement (displacement_string_start, | |
10101 | displacement_string_end)) | |
10102 | return 0; | |
10103 | } | |
10104 | ||
10105 | /* Special case for (%dx) while doing input/output op. */ | |
10106 | if (i.base_reg | |
2fb5be8d | 10107 | && i.base_reg->reg_type.bitfield.inoutportreg |
24eab124 AM |
10108 | && i.index_reg == 0 |
10109 | && i.log2_scale_factor == 0 | |
10110 | && i.seg[i.mem_operands] == 0 | |
40fb9820 | 10111 | && !operand_type_check (i.types[this_operand], disp)) |
24eab124 | 10112 | { |
2fb5be8d | 10113 | i.types[this_operand] = i.base_reg->reg_type; |
24eab124 AM |
10114 | return 1; |
10115 | } | |
10116 | ||
eecb386c AM |
10117 | if (i386_index_check (operand_string) == 0) |
10118 | return 0; | |
c48dadc9 | 10119 | i.flags[this_operand] |= Operand_Mem; |
8325cc63 JB |
10120 | if (i.mem_operands == 0) |
10121 | i.memop1_string = xstrdup (operand_string); | |
24eab124 AM |
10122 | i.mem_operands++; |
10123 | } | |
10124 | else | |
ce8a8b2f AM |
10125 | { |
10126 | /* It's not a memory operand; argh! */ | |
24eab124 AM |
10127 | as_bad (_("invalid char %s beginning operand %d `%s'"), |
10128 | output_invalid (*op_string), | |
10129 | this_operand + 1, | |
10130 | op_string); | |
10131 | return 0; | |
10132 | } | |
47926f60 | 10133 | return 1; /* Normal return. */ |
252b5132 RH |
10134 | } |
10135 | \f | |
fa94de6b RM |
10136 | /* Calculate the maximum variable size (i.e., excluding fr_fix) |
10137 | that an rs_machine_dependent frag may reach. */ | |
10138 | ||
10139 | unsigned int | |
10140 | i386_frag_max_var (fragS *frag) | |
10141 | { | |
10142 | /* The only relaxable frags are for jumps. | |
10143 | Unconditional jumps can grow by 4 bytes and others by 5 bytes. */ | |
10144 | gas_assert (frag->fr_type == rs_machine_dependent); | |
10145 | return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5; | |
10146 | } | |
10147 | ||
b084df0b L |
10148 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
10149 | static int | |
8dcea932 | 10150 | elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var) |
b084df0b L |
10151 | { |
10152 | /* STT_GNU_IFUNC symbol must go through PLT. */ | |
10153 | if ((symbol_get_bfdsym (fr_symbol)->flags | |
10154 | & BSF_GNU_INDIRECT_FUNCTION) != 0) | |
10155 | return 0; | |
10156 | ||
10157 | if (!S_IS_EXTERNAL (fr_symbol)) | |
10158 | /* Symbol may be weak or local. */ | |
10159 | return !S_IS_WEAK (fr_symbol); | |
10160 | ||
8dcea932 L |
10161 | /* Global symbols with non-default visibility can't be preempted. */ |
10162 | if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT) | |
10163 | return 1; | |
10164 | ||
10165 | if (fr_var != NO_RELOC) | |
10166 | switch ((enum bfd_reloc_code_real) fr_var) | |
10167 | { | |
10168 | case BFD_RELOC_386_PLT32: | |
10169 | case BFD_RELOC_X86_64_PLT32: | |
33eaf5de | 10170 | /* Symbol with PLT relocation may be preempted. */ |
8dcea932 L |
10171 | return 0; |
10172 | default: | |
10173 | abort (); | |
10174 | } | |
10175 | ||
b084df0b L |
10176 | /* Global symbols with default visibility in a shared library may be |
10177 | preempted by another definition. */ | |
8dcea932 | 10178 | return !shared; |
b084df0b L |
10179 | } |
10180 | #endif | |
10181 | ||
ee7fcc42 AM |
10182 | /* md_estimate_size_before_relax() |
10183 | ||
10184 | Called just before relax() for rs_machine_dependent frags. The x86 | |
10185 | assembler uses these frags to handle variable size jump | |
10186 | instructions. | |
10187 | ||
10188 | Any symbol that is now undefined will not become defined. | |
10189 | Return the correct fr_subtype in the frag. | |
10190 | Return the initial "guess for variable size of frag" to caller. | |
10191 | The guess is actually the growth beyond the fixed part. Whatever | |
10192 | we do to grow the fixed or variable part contributes to our | |
10193 | returned value. */ | |
10194 | ||
252b5132 | 10195 | int |
7016a5d5 | 10196 | md_estimate_size_before_relax (fragS *fragP, segT segment) |
252b5132 | 10197 | { |
252b5132 | 10198 | /* We've already got fragP->fr_subtype right; all we have to do is |
b98ef147 AM |
10199 | check for un-relaxable symbols. On an ELF system, we can't relax |
10200 | an externally visible symbol, because it may be overridden by a | |
10201 | shared library. */ | |
10202 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment | |
6d249963 | 10203 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 10204 | || (IS_ELF |
8dcea932 L |
10205 | && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol, |
10206 | fragP->fr_var)) | |
fbeb56a4 DK |
10207 | #endif |
10208 | #if defined (OBJ_COFF) && defined (TE_PE) | |
7ab9ffdd | 10209 | || (OUTPUT_FLAVOR == bfd_target_coff_flavour |
fbeb56a4 | 10210 | && S_IS_WEAK (fragP->fr_symbol)) |
b98ef147 AM |
10211 | #endif |
10212 | ) | |
252b5132 | 10213 | { |
b98ef147 AM |
10214 | /* Symbol is undefined in this segment, or we need to keep a |
10215 | reloc so that weak symbols can be overridden. */ | |
10216 | int size = (fragP->fr_subtype & CODE16) ? 2 : 4; | |
f86103b7 | 10217 | enum bfd_reloc_code_real reloc_type; |
ee7fcc42 AM |
10218 | unsigned char *opcode; |
10219 | int old_fr_fix; | |
f6af82bd | 10220 | |
ee7fcc42 | 10221 | if (fragP->fr_var != NO_RELOC) |
1e9cc1c2 | 10222 | reloc_type = (enum bfd_reloc_code_real) fragP->fr_var; |
b98ef147 | 10223 | else if (size == 2) |
f6af82bd | 10224 | reloc_type = BFD_RELOC_16_PCREL; |
bd7ab16b L |
10225 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
10226 | else if (need_plt32_p (fragP->fr_symbol)) | |
10227 | reloc_type = BFD_RELOC_X86_64_PLT32; | |
10228 | #endif | |
f6af82bd AM |
10229 | else |
10230 | reloc_type = BFD_RELOC_32_PCREL; | |
252b5132 | 10231 | |
ee7fcc42 AM |
10232 | old_fr_fix = fragP->fr_fix; |
10233 | opcode = (unsigned char *) fragP->fr_opcode; | |
10234 | ||
fddf5b5b | 10235 | switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)) |
252b5132 | 10236 | { |
fddf5b5b AM |
10237 | case UNCOND_JUMP: |
10238 | /* Make jmp (0xeb) a (d)word displacement jump. */ | |
47926f60 | 10239 | opcode[0] = 0xe9; |
252b5132 | 10240 | fragP->fr_fix += size; |
062cd5e7 AS |
10241 | fix_new (fragP, old_fr_fix, size, |
10242 | fragP->fr_symbol, | |
10243 | fragP->fr_offset, 1, | |
10244 | reloc_type); | |
252b5132 RH |
10245 | break; |
10246 | ||
fddf5b5b | 10247 | case COND_JUMP86: |
412167cb AM |
10248 | if (size == 2 |
10249 | && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC)) | |
fddf5b5b AM |
10250 | { |
10251 | /* Negate the condition, and branch past an | |
10252 | unconditional jump. */ | |
10253 | opcode[0] ^= 1; | |
10254 | opcode[1] = 3; | |
10255 | /* Insert an unconditional jump. */ | |
10256 | opcode[2] = 0xe9; | |
10257 | /* We added two extra opcode bytes, and have a two byte | |
10258 | offset. */ | |
10259 | fragP->fr_fix += 2 + 2; | |
062cd5e7 AS |
10260 | fix_new (fragP, old_fr_fix + 2, 2, |
10261 | fragP->fr_symbol, | |
10262 | fragP->fr_offset, 1, | |
10263 | reloc_type); | |
fddf5b5b AM |
10264 | break; |
10265 | } | |
10266 | /* Fall through. */ | |
10267 | ||
10268 | case COND_JUMP: | |
412167cb AM |
10269 | if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC) |
10270 | { | |
3e02c1cc AM |
10271 | fixS *fixP; |
10272 | ||
412167cb | 10273 | fragP->fr_fix += 1; |
3e02c1cc AM |
10274 | fixP = fix_new (fragP, old_fr_fix, 1, |
10275 | fragP->fr_symbol, | |
10276 | fragP->fr_offset, 1, | |
10277 | BFD_RELOC_8_PCREL); | |
10278 | fixP->fx_signed = 1; | |
412167cb AM |
10279 | break; |
10280 | } | |
93c2a809 | 10281 | |
24eab124 | 10282 | /* This changes the byte-displacement jump 0x7N |
fddf5b5b | 10283 | to the (d)word-displacement jump 0x0f,0x8N. */ |
252b5132 | 10284 | opcode[1] = opcode[0] + 0x10; |
f6af82bd | 10285 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
47926f60 KH |
10286 | /* We've added an opcode byte. */ |
10287 | fragP->fr_fix += 1 + size; | |
062cd5e7 AS |
10288 | fix_new (fragP, old_fr_fix + 1, size, |
10289 | fragP->fr_symbol, | |
10290 | fragP->fr_offset, 1, | |
10291 | reloc_type); | |
252b5132 | 10292 | break; |
fddf5b5b AM |
10293 | |
10294 | default: | |
10295 | BAD_CASE (fragP->fr_subtype); | |
10296 | break; | |
252b5132 RH |
10297 | } |
10298 | frag_wane (fragP); | |
ee7fcc42 | 10299 | return fragP->fr_fix - old_fr_fix; |
252b5132 | 10300 | } |
93c2a809 | 10301 | |
93c2a809 AM |
10302 | /* Guess size depending on current relax state. Initially the relax |
10303 | state will correspond to a short jump and we return 1, because | |
10304 | the variable part of the frag (the branch offset) is one byte | |
10305 | long. However, we can relax a section more than once and in that | |
10306 | case we must either set fr_subtype back to the unrelaxed state, | |
10307 | or return the value for the appropriate branch. */ | |
10308 | return md_relax_table[fragP->fr_subtype].rlx_length; | |
ee7fcc42 AM |
10309 | } |
10310 | ||
47926f60 KH |
10311 | /* Called after relax() is finished. |
10312 | ||
10313 | In: Address of frag. | |
10314 | fr_type == rs_machine_dependent. | |
10315 | fr_subtype is what the address relaxed to. | |
10316 | ||
10317 | Out: Any fixSs and constants are set up. | |
10318 | Caller will turn frag into a ".space 0". */ | |
10319 | ||
252b5132 | 10320 | void |
7016a5d5 TG |
10321 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED, |
10322 | fragS *fragP) | |
252b5132 | 10323 | { |
29b0f896 | 10324 | unsigned char *opcode; |
252b5132 | 10325 | unsigned char *where_to_put_displacement = NULL; |
847f7ad4 AM |
10326 | offsetT target_address; |
10327 | offsetT opcode_address; | |
252b5132 | 10328 | unsigned int extension = 0; |
847f7ad4 | 10329 | offsetT displacement_from_opcode_start; |
252b5132 RH |
10330 | |
10331 | opcode = (unsigned char *) fragP->fr_opcode; | |
10332 | ||
47926f60 | 10333 | /* Address we want to reach in file space. */ |
252b5132 | 10334 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; |
252b5132 | 10335 | |
47926f60 | 10336 | /* Address opcode resides at in file space. */ |
252b5132 RH |
10337 | opcode_address = fragP->fr_address + fragP->fr_fix; |
10338 | ||
47926f60 | 10339 | /* Displacement from opcode start to fill into instruction. */ |
252b5132 RH |
10340 | displacement_from_opcode_start = target_address - opcode_address; |
10341 | ||
fddf5b5b | 10342 | if ((fragP->fr_subtype & BIG) == 0) |
252b5132 | 10343 | { |
47926f60 KH |
10344 | /* Don't have to change opcode. */ |
10345 | extension = 1; /* 1 opcode + 1 displacement */ | |
252b5132 | 10346 | where_to_put_displacement = &opcode[1]; |
fddf5b5b AM |
10347 | } |
10348 | else | |
10349 | { | |
10350 | if (no_cond_jump_promotion | |
10351 | && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP) | |
4eed87de AM |
10352 | as_warn_where (fragP->fr_file, fragP->fr_line, |
10353 | _("long jump required")); | |
252b5132 | 10354 | |
fddf5b5b AM |
10355 | switch (fragP->fr_subtype) |
10356 | { | |
10357 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): | |
10358 | extension = 4; /* 1 opcode + 4 displacement */ | |
10359 | opcode[0] = 0xe9; | |
10360 | where_to_put_displacement = &opcode[1]; | |
10361 | break; | |
252b5132 | 10362 | |
fddf5b5b AM |
10363 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): |
10364 | extension = 2; /* 1 opcode + 2 displacement */ | |
10365 | opcode[0] = 0xe9; | |
10366 | where_to_put_displacement = &opcode[1]; | |
10367 | break; | |
252b5132 | 10368 | |
fddf5b5b AM |
10369 | case ENCODE_RELAX_STATE (COND_JUMP, BIG): |
10370 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG): | |
10371 | extension = 5; /* 2 opcode + 4 displacement */ | |
10372 | opcode[1] = opcode[0] + 0x10; | |
10373 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
10374 | where_to_put_displacement = &opcode[2]; | |
10375 | break; | |
252b5132 | 10376 | |
fddf5b5b AM |
10377 | case ENCODE_RELAX_STATE (COND_JUMP, BIG16): |
10378 | extension = 3; /* 2 opcode + 2 displacement */ | |
10379 | opcode[1] = opcode[0] + 0x10; | |
10380 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
10381 | where_to_put_displacement = &opcode[2]; | |
10382 | break; | |
252b5132 | 10383 | |
fddf5b5b AM |
10384 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG16): |
10385 | extension = 4; | |
10386 | opcode[0] ^= 1; | |
10387 | opcode[1] = 3; | |
10388 | opcode[2] = 0xe9; | |
10389 | where_to_put_displacement = &opcode[3]; | |
10390 | break; | |
10391 | ||
10392 | default: | |
10393 | BAD_CASE (fragP->fr_subtype); | |
10394 | break; | |
10395 | } | |
252b5132 | 10396 | } |
fddf5b5b | 10397 | |
7b81dfbb AJ |
10398 | /* If size if less then four we are sure that the operand fits, |
10399 | but if it's 4, then it could be that the displacement is larger | |
10400 | then -/+ 2GB. */ | |
10401 | if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4 | |
10402 | && object_64bit | |
10403 | && ((addressT) (displacement_from_opcode_start - extension | |
4eed87de AM |
10404 | + ((addressT) 1 << 31)) |
10405 | > (((addressT) 2 << 31) - 1))) | |
7b81dfbb AJ |
10406 | { |
10407 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
10408 | _("jump target out of range")); | |
10409 | /* Make us emit 0. */ | |
10410 | displacement_from_opcode_start = extension; | |
10411 | } | |
47926f60 | 10412 | /* Now put displacement after opcode. */ |
252b5132 RH |
10413 | md_number_to_chars ((char *) where_to_put_displacement, |
10414 | (valueT) (displacement_from_opcode_start - extension), | |
fddf5b5b | 10415 | DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); |
252b5132 RH |
10416 | fragP->fr_fix += extension; |
10417 | } | |
10418 | \f | |
7016a5d5 | 10419 | /* Apply a fixup (fixP) to segment data, once it has been determined |
252b5132 RH |
10420 | by our caller that we have all the info we need to fix it up. |
10421 | ||
7016a5d5 TG |
10422 | Parameter valP is the pointer to the value of the bits. |
10423 | ||
252b5132 RH |
10424 | On the 386, immediates, displacements, and data pointers are all in |
10425 | the same (little-endian) format, so we don't need to care about which | |
10426 | we are handling. */ | |
10427 | ||
94f592af | 10428 | void |
7016a5d5 | 10429 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 10430 | { |
94f592af | 10431 | char *p = fixP->fx_where + fixP->fx_frag->fr_literal; |
c6682705 | 10432 | valueT value = *valP; |
252b5132 | 10433 | |
f86103b7 | 10434 | #if !defined (TE_Mach) |
93382f6d AM |
10435 | if (fixP->fx_pcrel) |
10436 | { | |
10437 | switch (fixP->fx_r_type) | |
10438 | { | |
5865bb77 ILT |
10439 | default: |
10440 | break; | |
10441 | ||
d6ab8113 JB |
10442 | case BFD_RELOC_64: |
10443 | fixP->fx_r_type = BFD_RELOC_64_PCREL; | |
10444 | break; | |
93382f6d | 10445 | case BFD_RELOC_32: |
ae8887b5 | 10446 | case BFD_RELOC_X86_64_32S: |
93382f6d AM |
10447 | fixP->fx_r_type = BFD_RELOC_32_PCREL; |
10448 | break; | |
10449 | case BFD_RELOC_16: | |
10450 | fixP->fx_r_type = BFD_RELOC_16_PCREL; | |
10451 | break; | |
10452 | case BFD_RELOC_8: | |
10453 | fixP->fx_r_type = BFD_RELOC_8_PCREL; | |
10454 | break; | |
10455 | } | |
10456 | } | |
252b5132 | 10457 | |
a161fe53 | 10458 | if (fixP->fx_addsy != NULL |
31312f95 | 10459 | && (fixP->fx_r_type == BFD_RELOC_32_PCREL |
d6ab8113 | 10460 | || fixP->fx_r_type == BFD_RELOC_64_PCREL |
31312f95 | 10461 | || fixP->fx_r_type == BFD_RELOC_16_PCREL |
d258b828 | 10462 | || fixP->fx_r_type == BFD_RELOC_8_PCREL) |
31312f95 | 10463 | && !use_rela_relocations) |
252b5132 | 10464 | { |
31312f95 AM |
10465 | /* This is a hack. There should be a better way to handle this. |
10466 | This covers for the fact that bfd_install_relocation will | |
10467 | subtract the current location (for partial_inplace, PC relative | |
10468 | relocations); see more below. */ | |
252b5132 | 10469 | #ifndef OBJ_AOUT |
718ddfc0 | 10470 | if (IS_ELF |
252b5132 RH |
10471 | #ifdef TE_PE |
10472 | || OUTPUT_FLAVOR == bfd_target_coff_flavour | |
10473 | #endif | |
10474 | ) | |
10475 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
10476 | #endif | |
10477 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
718ddfc0 | 10478 | if (IS_ELF) |
252b5132 | 10479 | { |
6539b54b | 10480 | segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy); |
2f66722d | 10481 | |
6539b54b | 10482 | if ((sym_seg == seg |
2f66722d | 10483 | || (symbol_section_p (fixP->fx_addsy) |
6539b54b | 10484 | && sym_seg != absolute_section)) |
af65af87 | 10485 | && !generic_force_reloc (fixP)) |
2f66722d AM |
10486 | { |
10487 | /* Yes, we add the values in twice. This is because | |
6539b54b AM |
10488 | bfd_install_relocation subtracts them out again. I think |
10489 | bfd_install_relocation is broken, but I don't dare change | |
2f66722d AM |
10490 | it. FIXME. */ |
10491 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
10492 | } | |
252b5132 RH |
10493 | } |
10494 | #endif | |
10495 | #if defined (OBJ_COFF) && defined (TE_PE) | |
977cdf5a NC |
10496 | /* For some reason, the PE format does not store a |
10497 | section address offset for a PC relative symbol. */ | |
10498 | if (S_GET_SEGMENT (fixP->fx_addsy) != seg | |
7be1c489 | 10499 | || S_IS_WEAK (fixP->fx_addsy)) |
252b5132 RH |
10500 | value += md_pcrel_from (fixP); |
10501 | #endif | |
10502 | } | |
fbeb56a4 | 10503 | #if defined (OBJ_COFF) && defined (TE_PE) |
f01c1a09 NC |
10504 | if (fixP->fx_addsy != NULL |
10505 | && S_IS_WEAK (fixP->fx_addsy) | |
10506 | /* PR 16858: Do not modify weak function references. */ | |
10507 | && ! fixP->fx_pcrel) | |
fbeb56a4 | 10508 | { |
296a8689 NC |
10509 | #if !defined (TE_PEP) |
10510 | /* For x86 PE weak function symbols are neither PC-relative | |
10511 | nor do they set S_IS_FUNCTION. So the only reliable way | |
10512 | to detect them is to check the flags of their containing | |
10513 | section. */ | |
10514 | if (S_GET_SEGMENT (fixP->fx_addsy) != NULL | |
10515 | && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE) | |
10516 | ; | |
10517 | else | |
10518 | #endif | |
fbeb56a4 DK |
10519 | value -= S_GET_VALUE (fixP->fx_addsy); |
10520 | } | |
10521 | #endif | |
252b5132 RH |
10522 | |
10523 | /* Fix a few things - the dynamic linker expects certain values here, | |
0234cb7c | 10524 | and we must not disappoint it. */ |
252b5132 | 10525 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 10526 | if (IS_ELF && fixP->fx_addsy) |
47926f60 KH |
10527 | switch (fixP->fx_r_type) |
10528 | { | |
10529 | case BFD_RELOC_386_PLT32: | |
3e73aa7c | 10530 | case BFD_RELOC_X86_64_PLT32: |
47926f60 KH |
10531 | /* Make the jump instruction point to the address of the operand. At |
10532 | runtime we merely add the offset to the actual PLT entry. */ | |
10533 | value = -4; | |
10534 | break; | |
31312f95 | 10535 | |
13ae64f3 JJ |
10536 | case BFD_RELOC_386_TLS_GD: |
10537 | case BFD_RELOC_386_TLS_LDM: | |
13ae64f3 | 10538 | case BFD_RELOC_386_TLS_IE_32: |
37e55690 JJ |
10539 | case BFD_RELOC_386_TLS_IE: |
10540 | case BFD_RELOC_386_TLS_GOTIE: | |
67a4f2b7 | 10541 | case BFD_RELOC_386_TLS_GOTDESC: |
bffbf940 JJ |
10542 | case BFD_RELOC_X86_64_TLSGD: |
10543 | case BFD_RELOC_X86_64_TLSLD: | |
10544 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 | 10545 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
00f7efb6 JJ |
10546 | value = 0; /* Fully resolved at runtime. No addend. */ |
10547 | /* Fallthrough */ | |
10548 | case BFD_RELOC_386_TLS_LE: | |
10549 | case BFD_RELOC_386_TLS_LDO_32: | |
10550 | case BFD_RELOC_386_TLS_LE_32: | |
10551 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 10552 | case BFD_RELOC_X86_64_DTPOFF64: |
00f7efb6 | 10553 | case BFD_RELOC_X86_64_TPOFF32: |
d6ab8113 | 10554 | case BFD_RELOC_X86_64_TPOFF64: |
00f7efb6 JJ |
10555 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
10556 | break; | |
10557 | ||
67a4f2b7 AO |
10558 | case BFD_RELOC_386_TLS_DESC_CALL: |
10559 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
10560 | value = 0; /* Fully resolved at runtime. No addend. */ | |
10561 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
10562 | fixP->fx_done = 0; | |
10563 | return; | |
10564 | ||
47926f60 KH |
10565 | case BFD_RELOC_VTABLE_INHERIT: |
10566 | case BFD_RELOC_VTABLE_ENTRY: | |
10567 | fixP->fx_done = 0; | |
94f592af | 10568 | return; |
47926f60 KH |
10569 | |
10570 | default: | |
10571 | break; | |
10572 | } | |
10573 | #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ | |
c6682705 | 10574 | *valP = value; |
f86103b7 | 10575 | #endif /* !defined (TE_Mach) */ |
3e73aa7c | 10576 | |
3e73aa7c | 10577 | /* Are we finished with this relocation now? */ |
c6682705 | 10578 | if (fixP->fx_addsy == NULL) |
3e73aa7c | 10579 | fixP->fx_done = 1; |
fbeb56a4 DK |
10580 | #if defined (OBJ_COFF) && defined (TE_PE) |
10581 | else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy)) | |
10582 | { | |
10583 | fixP->fx_done = 0; | |
10584 | /* Remember value for tc_gen_reloc. */ | |
10585 | fixP->fx_addnumber = value; | |
10586 | /* Clear out the frag for now. */ | |
10587 | value = 0; | |
10588 | } | |
10589 | #endif | |
3e73aa7c JH |
10590 | else if (use_rela_relocations) |
10591 | { | |
10592 | fixP->fx_no_overflow = 1; | |
062cd5e7 AS |
10593 | /* Remember value for tc_gen_reloc. */ |
10594 | fixP->fx_addnumber = value; | |
3e73aa7c JH |
10595 | value = 0; |
10596 | } | |
f86103b7 | 10597 | |
94f592af | 10598 | md_number_to_chars (p, value, fixP->fx_size); |
252b5132 | 10599 | } |
252b5132 | 10600 | \f |
6d4af3c2 | 10601 | const char * |
499ac353 | 10602 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 10603 | { |
499ac353 NC |
10604 | /* This outputs the LITTLENUMs in REVERSE order; |
10605 | in accord with the bigendian 386. */ | |
10606 | return ieee_md_atof (type, litP, sizeP, FALSE); | |
252b5132 RH |
10607 | } |
10608 | \f | |
2d545b82 | 10609 | static char output_invalid_buf[sizeof (unsigned char) * 2 + 6]; |
252b5132 | 10610 | |
252b5132 | 10611 | static char * |
e3bb37b5 | 10612 | output_invalid (int c) |
252b5132 | 10613 | { |
3882b010 | 10614 | if (ISPRINT (c)) |
f9f21a03 L |
10615 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
10616 | "'%c'", c); | |
252b5132 | 10617 | else |
f9f21a03 | 10618 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
2d545b82 | 10619 | "(0x%x)", (unsigned char) c); |
252b5132 RH |
10620 | return output_invalid_buf; |
10621 | } | |
10622 | ||
af6bdddf | 10623 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
252b5132 RH |
10624 | |
10625 | static const reg_entry * | |
4d1bb795 | 10626 | parse_real_register (char *reg_string, char **end_op) |
252b5132 | 10627 | { |
af6bdddf AM |
10628 | char *s = reg_string; |
10629 | char *p; | |
252b5132 RH |
10630 | char reg_name_given[MAX_REG_NAME_SIZE + 1]; |
10631 | const reg_entry *r; | |
10632 | ||
10633 | /* Skip possible REGISTER_PREFIX and possible whitespace. */ | |
10634 | if (*s == REGISTER_PREFIX) | |
10635 | ++s; | |
10636 | ||
10637 | if (is_space_char (*s)) | |
10638 | ++s; | |
10639 | ||
10640 | p = reg_name_given; | |
af6bdddf | 10641 | while ((*p++ = register_chars[(unsigned char) *s]) != '\0') |
252b5132 RH |
10642 | { |
10643 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) | |
af6bdddf AM |
10644 | return (const reg_entry *) NULL; |
10645 | s++; | |
252b5132 RH |
10646 | } |
10647 | ||
6588847e DN |
10648 | /* For naked regs, make sure that we are not dealing with an identifier. |
10649 | This prevents confusing an identifier like `eax_var' with register | |
10650 | `eax'. */ | |
10651 | if (allow_naked_reg && identifier_chars[(unsigned char) *s]) | |
10652 | return (const reg_entry *) NULL; | |
10653 | ||
af6bdddf | 10654 | *end_op = s; |
252b5132 RH |
10655 | |
10656 | r = (const reg_entry *) hash_find (reg_hash, reg_name_given); | |
10657 | ||
5f47d35b | 10658 | /* Handle floating point regs, allowing spaces in the (i) part. */ |
47926f60 | 10659 | if (r == i386_regtab /* %st is first entry of table */) |
5f47d35b | 10660 | { |
0e0eea78 JB |
10661 | if (!cpu_arch_flags.bitfield.cpu8087 |
10662 | && !cpu_arch_flags.bitfield.cpu287 | |
10663 | && !cpu_arch_flags.bitfield.cpu387) | |
10664 | return (const reg_entry *) NULL; | |
10665 | ||
5f47d35b AM |
10666 | if (is_space_char (*s)) |
10667 | ++s; | |
10668 | if (*s == '(') | |
10669 | { | |
af6bdddf | 10670 | ++s; |
5f47d35b AM |
10671 | if (is_space_char (*s)) |
10672 | ++s; | |
10673 | if (*s >= '0' && *s <= '7') | |
10674 | { | |
db557034 | 10675 | int fpr = *s - '0'; |
af6bdddf | 10676 | ++s; |
5f47d35b AM |
10677 | if (is_space_char (*s)) |
10678 | ++s; | |
10679 | if (*s == ')') | |
10680 | { | |
10681 | *end_op = s + 1; | |
1e9cc1c2 | 10682 | r = (const reg_entry *) hash_find (reg_hash, "st(0)"); |
db557034 AM |
10683 | know (r); |
10684 | return r + fpr; | |
5f47d35b | 10685 | } |
5f47d35b | 10686 | } |
47926f60 | 10687 | /* We have "%st(" then garbage. */ |
5f47d35b AM |
10688 | return (const reg_entry *) NULL; |
10689 | } | |
10690 | } | |
10691 | ||
a60de03c JB |
10692 | if (r == NULL || allow_pseudo_reg) |
10693 | return r; | |
10694 | ||
0dfbf9d7 | 10695 | if (operand_type_all_zero (&r->reg_type)) |
a60de03c JB |
10696 | return (const reg_entry *) NULL; |
10697 | ||
dc821c5f | 10698 | if ((r->reg_type.bitfield.dword |
192dc9c6 JB |
10699 | || r->reg_type.bitfield.sreg3 |
10700 | || r->reg_type.bitfield.control | |
10701 | || r->reg_type.bitfield.debug | |
10702 | || r->reg_type.bitfield.test) | |
10703 | && !cpu_arch_flags.bitfield.cpui386) | |
10704 | return (const reg_entry *) NULL; | |
10705 | ||
6e041cf4 | 10706 | if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx) |
192dc9c6 JB |
10707 | return (const reg_entry *) NULL; |
10708 | ||
6e041cf4 JB |
10709 | if (!cpu_arch_flags.bitfield.cpuavx512f) |
10710 | { | |
10711 | if (r->reg_type.bitfield.zmmword || r->reg_type.bitfield.regmask) | |
10712 | return (const reg_entry *) NULL; | |
40f12533 | 10713 | |
6e041cf4 JB |
10714 | if (!cpu_arch_flags.bitfield.cpuavx) |
10715 | { | |
10716 | if (r->reg_type.bitfield.ymmword) | |
10717 | return (const reg_entry *) NULL; | |
1848e567 | 10718 | |
6e041cf4 JB |
10719 | if (!cpu_arch_flags.bitfield.cpusse && r->reg_type.bitfield.xmmword) |
10720 | return (const reg_entry *) NULL; | |
10721 | } | |
10722 | } | |
43234a1e | 10723 | |
1adf7f56 JB |
10724 | if (r->reg_type.bitfield.regbnd && !cpu_arch_flags.bitfield.cpumpx) |
10725 | return (const reg_entry *) NULL; | |
10726 | ||
db51cc60 | 10727 | /* Don't allow fake index register unless allow_index_reg isn't 0. */ |
e968fc9b | 10728 | if (!allow_index_reg && r->reg_num == RegIZ) |
db51cc60 L |
10729 | return (const reg_entry *) NULL; |
10730 | ||
1d3f8286 JB |
10731 | /* Upper 16 vector registers are only available with VREX in 64bit |
10732 | mode, and require EVEX encoding. */ | |
10733 | if (r->reg_flags & RegVRex) | |
43234a1e | 10734 | { |
e951d5ca | 10735 | if (!cpu_arch_flags.bitfield.cpuavx512f |
43234a1e L |
10736 | || flag_code != CODE_64BIT) |
10737 | return (const reg_entry *) NULL; | |
1d3f8286 JB |
10738 | |
10739 | i.vec_encoding = vex_encoding_evex; | |
43234a1e L |
10740 | } |
10741 | ||
4787f4a5 JB |
10742 | if (((r->reg_flags & (RegRex64 | RegRex)) || r->reg_type.bitfield.qword) |
10743 | && (!cpu_arch_flags.bitfield.cpulm || !r->reg_type.bitfield.control) | |
1ae00879 | 10744 | && flag_code != CODE_64BIT) |
20f0a1fc | 10745 | return (const reg_entry *) NULL; |
1ae00879 | 10746 | |
b7240065 JB |
10747 | if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax) |
10748 | return (const reg_entry *) NULL; | |
10749 | ||
252b5132 RH |
10750 | return r; |
10751 | } | |
4d1bb795 JB |
10752 | |
10753 | /* REG_STRING starts *before* REGISTER_PREFIX. */ | |
10754 | ||
10755 | static const reg_entry * | |
10756 | parse_register (char *reg_string, char **end_op) | |
10757 | { | |
10758 | const reg_entry *r; | |
10759 | ||
10760 | if (*reg_string == REGISTER_PREFIX || allow_naked_reg) | |
10761 | r = parse_real_register (reg_string, end_op); | |
10762 | else | |
10763 | r = NULL; | |
10764 | if (!r) | |
10765 | { | |
10766 | char *save = input_line_pointer; | |
10767 | char c; | |
10768 | symbolS *symbolP; | |
10769 | ||
10770 | input_line_pointer = reg_string; | |
d02603dc | 10771 | c = get_symbol_name (®_string); |
4d1bb795 JB |
10772 | symbolP = symbol_find (reg_string); |
10773 | if (symbolP && S_GET_SEGMENT (symbolP) == reg_section) | |
10774 | { | |
10775 | const expressionS *e = symbol_get_value_expression (symbolP); | |
10776 | ||
0398aac5 | 10777 | know (e->X_op == O_register); |
4eed87de | 10778 | know (e->X_add_number >= 0 |
c3fe08fa | 10779 | && (valueT) e->X_add_number < i386_regtab_size); |
4d1bb795 | 10780 | r = i386_regtab + e->X_add_number; |
d3bb6b49 | 10781 | if ((r->reg_flags & RegVRex)) |
86fa6981 | 10782 | i.vec_encoding = vex_encoding_evex; |
4d1bb795 JB |
10783 | *end_op = input_line_pointer; |
10784 | } | |
10785 | *input_line_pointer = c; | |
10786 | input_line_pointer = save; | |
10787 | } | |
10788 | return r; | |
10789 | } | |
10790 | ||
10791 | int | |
10792 | i386_parse_name (char *name, expressionS *e, char *nextcharP) | |
10793 | { | |
10794 | const reg_entry *r; | |
10795 | char *end = input_line_pointer; | |
10796 | ||
10797 | *end = *nextcharP; | |
10798 | r = parse_register (name, &input_line_pointer); | |
10799 | if (r && end <= input_line_pointer) | |
10800 | { | |
10801 | *nextcharP = *input_line_pointer; | |
10802 | *input_line_pointer = 0; | |
10803 | e->X_op = O_register; | |
10804 | e->X_add_number = r - i386_regtab; | |
10805 | return 1; | |
10806 | } | |
10807 | input_line_pointer = end; | |
10808 | *end = 0; | |
ee86248c | 10809 | return intel_syntax ? i386_intel_parse_name (name, e) : 0; |
4d1bb795 JB |
10810 | } |
10811 | ||
10812 | void | |
10813 | md_operand (expressionS *e) | |
10814 | { | |
ee86248c JB |
10815 | char *end; |
10816 | const reg_entry *r; | |
4d1bb795 | 10817 | |
ee86248c JB |
10818 | switch (*input_line_pointer) |
10819 | { | |
10820 | case REGISTER_PREFIX: | |
10821 | r = parse_real_register (input_line_pointer, &end); | |
4d1bb795 JB |
10822 | if (r) |
10823 | { | |
10824 | e->X_op = O_register; | |
10825 | e->X_add_number = r - i386_regtab; | |
10826 | input_line_pointer = end; | |
10827 | } | |
ee86248c JB |
10828 | break; |
10829 | ||
10830 | case '[': | |
9c2799c2 | 10831 | gas_assert (intel_syntax); |
ee86248c JB |
10832 | end = input_line_pointer++; |
10833 | expression (e); | |
10834 | if (*input_line_pointer == ']') | |
10835 | { | |
10836 | ++input_line_pointer; | |
10837 | e->X_op_symbol = make_expr_symbol (e); | |
10838 | e->X_add_symbol = NULL; | |
10839 | e->X_add_number = 0; | |
10840 | e->X_op = O_index; | |
10841 | } | |
10842 | else | |
10843 | { | |
10844 | e->X_op = O_absent; | |
10845 | input_line_pointer = end; | |
10846 | } | |
10847 | break; | |
4d1bb795 JB |
10848 | } |
10849 | } | |
10850 | ||
252b5132 | 10851 | \f |
4cc782b5 | 10852 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
b6f8c7c4 | 10853 | const char *md_shortopts = "kVQ:sqnO::"; |
252b5132 | 10854 | #else |
b6f8c7c4 | 10855 | const char *md_shortopts = "qnO::"; |
252b5132 | 10856 | #endif |
6e0b89ee | 10857 | |
3e73aa7c | 10858 | #define OPTION_32 (OPTION_MD_BASE + 0) |
b3b91714 AM |
10859 | #define OPTION_64 (OPTION_MD_BASE + 1) |
10860 | #define OPTION_DIVIDE (OPTION_MD_BASE + 2) | |
9103f4f4 L |
10861 | #define OPTION_MARCH (OPTION_MD_BASE + 3) |
10862 | #define OPTION_MTUNE (OPTION_MD_BASE + 4) | |
1efbbeb4 L |
10863 | #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5) |
10864 | #define OPTION_MSYNTAX (OPTION_MD_BASE + 6) | |
10865 | #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7) | |
10866 | #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8) | |
bd5dea88 | 10867 | #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9) |
c0f3af97 | 10868 | #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10) |
daf50ae7 | 10869 | #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11) |
7bab8ab5 JB |
10870 | #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12) |
10871 | #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13) | |
10872 | #define OPTION_X32 (OPTION_MD_BASE + 14) | |
7e8b059b | 10873 | #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15) |
43234a1e L |
10874 | #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16) |
10875 | #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17) | |
167ad85b | 10876 | #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18) |
d1982f93 | 10877 | #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19) |
d3d3c6db | 10878 | #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20) |
8dcea932 | 10879 | #define OPTION_MSHARED (OPTION_MD_BASE + 21) |
5db04b09 L |
10880 | #define OPTION_MAMD64 (OPTION_MD_BASE + 22) |
10881 | #define OPTION_MINTEL64 (OPTION_MD_BASE + 23) | |
e4e00185 | 10882 | #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24) |
b4a3a7b4 | 10883 | #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25) |
b3b91714 | 10884 | |
99ad8390 NC |
10885 | struct option md_longopts[] = |
10886 | { | |
3e73aa7c | 10887 | {"32", no_argument, NULL, OPTION_32}, |
321098a5 | 10888 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 10889 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c | 10890 | {"64", no_argument, NULL, OPTION_64}, |
351f65ca L |
10891 | #endif |
10892 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
570561f7 | 10893 | {"x32", no_argument, NULL, OPTION_X32}, |
8dcea932 | 10894 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
b4a3a7b4 | 10895 | {"mx86-used-note", required_argument, NULL, OPTION_X86_USED_NOTE}, |
6e0b89ee | 10896 | #endif |
b3b91714 | 10897 | {"divide", no_argument, NULL, OPTION_DIVIDE}, |
9103f4f4 L |
10898 | {"march", required_argument, NULL, OPTION_MARCH}, |
10899 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
1efbbeb4 L |
10900 | {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC}, |
10901 | {"msyntax", required_argument, NULL, OPTION_MSYNTAX}, | |
10902 | {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG}, | |
10903 | {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG}, | |
c0f3af97 | 10904 | {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX}, |
daf50ae7 | 10905 | {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK}, |
7bab8ab5 | 10906 | {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK}, |
539f890d | 10907 | {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR}, |
7e8b059b | 10908 | {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX}, |
43234a1e L |
10909 | {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG}, |
10910 | {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG}, | |
167ad85b TG |
10911 | # if defined (TE_PE) || defined (TE_PEP) |
10912 | {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ}, | |
10913 | #endif | |
d1982f93 | 10914 | {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX}, |
e4e00185 | 10915 | {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD}, |
0cb4071e | 10916 | {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS}, |
d3d3c6db | 10917 | {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG}, |
5db04b09 L |
10918 | {"mamd64", no_argument, NULL, OPTION_MAMD64}, |
10919 | {"mintel64", no_argument, NULL, OPTION_MINTEL64}, | |
252b5132 RH |
10920 | {NULL, no_argument, NULL, 0} |
10921 | }; | |
10922 | size_t md_longopts_size = sizeof (md_longopts); | |
10923 | ||
10924 | int | |
17b9d67d | 10925 | md_parse_option (int c, const char *arg) |
252b5132 | 10926 | { |
91d6fa6a | 10927 | unsigned int j; |
293f5f65 | 10928 | char *arch, *next, *saved; |
9103f4f4 | 10929 | |
252b5132 RH |
10930 | switch (c) |
10931 | { | |
12b55ccc L |
10932 | case 'n': |
10933 | optimize_align_code = 0; | |
10934 | break; | |
10935 | ||
a38cf1db AM |
10936 | case 'q': |
10937 | quiet_warnings = 1; | |
252b5132 RH |
10938 | break; |
10939 | ||
10940 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
a38cf1db AM |
10941 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section |
10942 | should be emitted or not. FIXME: Not implemented. */ | |
10943 | case 'Q': | |
252b5132 RH |
10944 | break; |
10945 | ||
10946 | /* -V: SVR4 argument to print version ID. */ | |
10947 | case 'V': | |
10948 | print_version_id (); | |
10949 | break; | |
10950 | ||
a38cf1db AM |
10951 | /* -k: Ignore for FreeBSD compatibility. */ |
10952 | case 'k': | |
252b5132 | 10953 | break; |
4cc782b5 ILT |
10954 | |
10955 | case 's': | |
10956 | /* -s: On i386 Solaris, this tells the native assembler to use | |
29b0f896 | 10957 | .stab instead of .stab.excl. We always use .stab anyhow. */ |
4cc782b5 | 10958 | break; |
8dcea932 L |
10959 | |
10960 | case OPTION_MSHARED: | |
10961 | shared = 1; | |
10962 | break; | |
b4a3a7b4 L |
10963 | |
10964 | case OPTION_X86_USED_NOTE: | |
10965 | if (strcasecmp (arg, "yes") == 0) | |
10966 | x86_used_note = 1; | |
10967 | else if (strcasecmp (arg, "no") == 0) | |
10968 | x86_used_note = 0; | |
10969 | else | |
10970 | as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg); | |
10971 | break; | |
10972 | ||
10973 | ||
99ad8390 | 10974 | #endif |
321098a5 | 10975 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 10976 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c JH |
10977 | case OPTION_64: |
10978 | { | |
10979 | const char **list, **l; | |
10980 | ||
3e73aa7c JH |
10981 | list = bfd_target_list (); |
10982 | for (l = list; *l != NULL; l++) | |
8620418b | 10983 | if (CONST_STRNEQ (*l, "elf64-x86-64") |
99ad8390 NC |
10984 | || strcmp (*l, "coff-x86-64") == 0 |
10985 | || strcmp (*l, "pe-x86-64") == 0 | |
d382c579 TG |
10986 | || strcmp (*l, "pei-x86-64") == 0 |
10987 | || strcmp (*l, "mach-o-x86-64") == 0) | |
6e0b89ee AM |
10988 | { |
10989 | default_arch = "x86_64"; | |
10990 | break; | |
10991 | } | |
3e73aa7c | 10992 | if (*l == NULL) |
2b5d6a91 | 10993 | as_fatal (_("no compiled in support for x86_64")); |
3e73aa7c JH |
10994 | free (list); |
10995 | } | |
10996 | break; | |
10997 | #endif | |
252b5132 | 10998 | |
351f65ca | 10999 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
570561f7 | 11000 | case OPTION_X32: |
351f65ca L |
11001 | if (IS_ELF) |
11002 | { | |
11003 | const char **list, **l; | |
11004 | ||
11005 | list = bfd_target_list (); | |
11006 | for (l = list; *l != NULL; l++) | |
11007 | if (CONST_STRNEQ (*l, "elf32-x86-64")) | |
11008 | { | |
11009 | default_arch = "x86_64:32"; | |
11010 | break; | |
11011 | } | |
11012 | if (*l == NULL) | |
2b5d6a91 | 11013 | as_fatal (_("no compiled in support for 32bit x86_64")); |
351f65ca L |
11014 | free (list); |
11015 | } | |
11016 | else | |
11017 | as_fatal (_("32bit x86_64 is only supported for ELF")); | |
11018 | break; | |
11019 | #endif | |
11020 | ||
6e0b89ee AM |
11021 | case OPTION_32: |
11022 | default_arch = "i386"; | |
11023 | break; | |
11024 | ||
b3b91714 AM |
11025 | case OPTION_DIVIDE: |
11026 | #ifdef SVR4_COMMENT_CHARS | |
11027 | { | |
11028 | char *n, *t; | |
11029 | const char *s; | |
11030 | ||
add39d23 | 11031 | n = XNEWVEC (char, strlen (i386_comment_chars) + 1); |
b3b91714 AM |
11032 | t = n; |
11033 | for (s = i386_comment_chars; *s != '\0'; s++) | |
11034 | if (*s != '/') | |
11035 | *t++ = *s; | |
11036 | *t = '\0'; | |
11037 | i386_comment_chars = n; | |
11038 | } | |
11039 | #endif | |
11040 | break; | |
11041 | ||
9103f4f4 | 11042 | case OPTION_MARCH: |
293f5f65 L |
11043 | saved = xstrdup (arg); |
11044 | arch = saved; | |
11045 | /* Allow -march=+nosse. */ | |
11046 | if (*arch == '+') | |
11047 | arch++; | |
6305a203 | 11048 | do |
9103f4f4 | 11049 | { |
6305a203 | 11050 | if (*arch == '.') |
2b5d6a91 | 11051 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
11052 | next = strchr (arch, '+'); |
11053 | if (next) | |
11054 | *next++ = '\0'; | |
91d6fa6a | 11055 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 11056 | { |
91d6fa6a | 11057 | if (strcmp (arch, cpu_arch [j].name) == 0) |
ccc9c027 | 11058 | { |
6305a203 | 11059 | /* Processor. */ |
1ded5609 JB |
11060 | if (! cpu_arch[j].flags.bitfield.cpui386) |
11061 | continue; | |
11062 | ||
91d6fa6a | 11063 | cpu_arch_name = cpu_arch[j].name; |
6305a203 | 11064 | cpu_sub_arch_name = NULL; |
91d6fa6a NC |
11065 | cpu_arch_flags = cpu_arch[j].flags; |
11066 | cpu_arch_isa = cpu_arch[j].type; | |
11067 | cpu_arch_isa_flags = cpu_arch[j].flags; | |
6305a203 L |
11068 | if (!cpu_arch_tune_set) |
11069 | { | |
11070 | cpu_arch_tune = cpu_arch_isa; | |
11071 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
11072 | } | |
11073 | break; | |
11074 | } | |
91d6fa6a NC |
11075 | else if (*cpu_arch [j].name == '.' |
11076 | && strcmp (arch, cpu_arch [j].name + 1) == 0) | |
6305a203 | 11077 | { |
33eaf5de | 11078 | /* ISA extension. */ |
6305a203 | 11079 | i386_cpu_flags flags; |
309d3373 | 11080 | |
293f5f65 L |
11081 | flags = cpu_flags_or (cpu_arch_flags, |
11082 | cpu_arch[j].flags); | |
81486035 | 11083 | |
5b64d091 | 11084 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
6305a203 L |
11085 | { |
11086 | if (cpu_sub_arch_name) | |
11087 | { | |
11088 | char *name = cpu_sub_arch_name; | |
11089 | cpu_sub_arch_name = concat (name, | |
91d6fa6a | 11090 | cpu_arch[j].name, |
1bf57e9f | 11091 | (const char *) NULL); |
6305a203 L |
11092 | free (name); |
11093 | } | |
11094 | else | |
91d6fa6a | 11095 | cpu_sub_arch_name = xstrdup (cpu_arch[j].name); |
6305a203 | 11096 | cpu_arch_flags = flags; |
a586129e | 11097 | cpu_arch_isa_flags = flags; |
6305a203 | 11098 | } |
0089dace L |
11099 | else |
11100 | cpu_arch_isa_flags | |
11101 | = cpu_flags_or (cpu_arch_isa_flags, | |
11102 | cpu_arch[j].flags); | |
6305a203 | 11103 | break; |
ccc9c027 | 11104 | } |
9103f4f4 | 11105 | } |
6305a203 | 11106 | |
293f5f65 L |
11107 | if (j >= ARRAY_SIZE (cpu_arch)) |
11108 | { | |
33eaf5de | 11109 | /* Disable an ISA extension. */ |
293f5f65 L |
11110 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) |
11111 | if (strcmp (arch, cpu_noarch [j].name) == 0) | |
11112 | { | |
11113 | i386_cpu_flags flags; | |
11114 | ||
11115 | flags = cpu_flags_and_not (cpu_arch_flags, | |
11116 | cpu_noarch[j].flags); | |
11117 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) | |
11118 | { | |
11119 | if (cpu_sub_arch_name) | |
11120 | { | |
11121 | char *name = cpu_sub_arch_name; | |
11122 | cpu_sub_arch_name = concat (arch, | |
11123 | (const char *) NULL); | |
11124 | free (name); | |
11125 | } | |
11126 | else | |
11127 | cpu_sub_arch_name = xstrdup (arch); | |
11128 | cpu_arch_flags = flags; | |
11129 | cpu_arch_isa_flags = flags; | |
11130 | } | |
11131 | break; | |
11132 | } | |
11133 | ||
11134 | if (j >= ARRAY_SIZE (cpu_noarch)) | |
11135 | j = ARRAY_SIZE (cpu_arch); | |
11136 | } | |
11137 | ||
91d6fa6a | 11138 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 11139 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
11140 | |
11141 | arch = next; | |
9103f4f4 | 11142 | } |
293f5f65 L |
11143 | while (next != NULL); |
11144 | free (saved); | |
9103f4f4 L |
11145 | break; |
11146 | ||
11147 | case OPTION_MTUNE: | |
11148 | if (*arg == '.') | |
2b5d6a91 | 11149 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
91d6fa6a | 11150 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 11151 | { |
91d6fa6a | 11152 | if (strcmp (arg, cpu_arch [j].name) == 0) |
9103f4f4 | 11153 | { |
ccc9c027 | 11154 | cpu_arch_tune_set = 1; |
91d6fa6a NC |
11155 | cpu_arch_tune = cpu_arch [j].type; |
11156 | cpu_arch_tune_flags = cpu_arch[j].flags; | |
9103f4f4 L |
11157 | break; |
11158 | } | |
11159 | } | |
91d6fa6a | 11160 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 11161 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
9103f4f4 L |
11162 | break; |
11163 | ||
1efbbeb4 L |
11164 | case OPTION_MMNEMONIC: |
11165 | if (strcasecmp (arg, "att") == 0) | |
11166 | intel_mnemonic = 0; | |
11167 | else if (strcasecmp (arg, "intel") == 0) | |
11168 | intel_mnemonic = 1; | |
11169 | else | |
2b5d6a91 | 11170 | as_fatal (_("invalid -mmnemonic= option: `%s'"), arg); |
1efbbeb4 L |
11171 | break; |
11172 | ||
11173 | case OPTION_MSYNTAX: | |
11174 | if (strcasecmp (arg, "att") == 0) | |
11175 | intel_syntax = 0; | |
11176 | else if (strcasecmp (arg, "intel") == 0) | |
11177 | intel_syntax = 1; | |
11178 | else | |
2b5d6a91 | 11179 | as_fatal (_("invalid -msyntax= option: `%s'"), arg); |
1efbbeb4 L |
11180 | break; |
11181 | ||
11182 | case OPTION_MINDEX_REG: | |
11183 | allow_index_reg = 1; | |
11184 | break; | |
11185 | ||
11186 | case OPTION_MNAKED_REG: | |
11187 | allow_naked_reg = 1; | |
11188 | break; | |
11189 | ||
c0f3af97 L |
11190 | case OPTION_MSSE2AVX: |
11191 | sse2avx = 1; | |
11192 | break; | |
11193 | ||
daf50ae7 L |
11194 | case OPTION_MSSE_CHECK: |
11195 | if (strcasecmp (arg, "error") == 0) | |
7bab8ab5 | 11196 | sse_check = check_error; |
daf50ae7 | 11197 | else if (strcasecmp (arg, "warning") == 0) |
7bab8ab5 | 11198 | sse_check = check_warning; |
daf50ae7 | 11199 | else if (strcasecmp (arg, "none") == 0) |
7bab8ab5 | 11200 | sse_check = check_none; |
daf50ae7 | 11201 | else |
2b5d6a91 | 11202 | as_fatal (_("invalid -msse-check= option: `%s'"), arg); |
daf50ae7 L |
11203 | break; |
11204 | ||
7bab8ab5 JB |
11205 | case OPTION_MOPERAND_CHECK: |
11206 | if (strcasecmp (arg, "error") == 0) | |
11207 | operand_check = check_error; | |
11208 | else if (strcasecmp (arg, "warning") == 0) | |
11209 | operand_check = check_warning; | |
11210 | else if (strcasecmp (arg, "none") == 0) | |
11211 | operand_check = check_none; | |
11212 | else | |
11213 | as_fatal (_("invalid -moperand-check= option: `%s'"), arg); | |
11214 | break; | |
11215 | ||
539f890d L |
11216 | case OPTION_MAVXSCALAR: |
11217 | if (strcasecmp (arg, "128") == 0) | |
11218 | avxscalar = vex128; | |
11219 | else if (strcasecmp (arg, "256") == 0) | |
11220 | avxscalar = vex256; | |
11221 | else | |
2b5d6a91 | 11222 | as_fatal (_("invalid -mavxscalar= option: `%s'"), arg); |
539f890d L |
11223 | break; |
11224 | ||
7e8b059b L |
11225 | case OPTION_MADD_BND_PREFIX: |
11226 | add_bnd_prefix = 1; | |
11227 | break; | |
11228 | ||
43234a1e L |
11229 | case OPTION_MEVEXLIG: |
11230 | if (strcmp (arg, "128") == 0) | |
11231 | evexlig = evexl128; | |
11232 | else if (strcmp (arg, "256") == 0) | |
11233 | evexlig = evexl256; | |
11234 | else if (strcmp (arg, "512") == 0) | |
11235 | evexlig = evexl512; | |
11236 | else | |
11237 | as_fatal (_("invalid -mevexlig= option: `%s'"), arg); | |
11238 | break; | |
11239 | ||
d3d3c6db IT |
11240 | case OPTION_MEVEXRCIG: |
11241 | if (strcmp (arg, "rne") == 0) | |
11242 | evexrcig = rne; | |
11243 | else if (strcmp (arg, "rd") == 0) | |
11244 | evexrcig = rd; | |
11245 | else if (strcmp (arg, "ru") == 0) | |
11246 | evexrcig = ru; | |
11247 | else if (strcmp (arg, "rz") == 0) | |
11248 | evexrcig = rz; | |
11249 | else | |
11250 | as_fatal (_("invalid -mevexrcig= option: `%s'"), arg); | |
11251 | break; | |
11252 | ||
43234a1e L |
11253 | case OPTION_MEVEXWIG: |
11254 | if (strcmp (arg, "0") == 0) | |
11255 | evexwig = evexw0; | |
11256 | else if (strcmp (arg, "1") == 0) | |
11257 | evexwig = evexw1; | |
11258 | else | |
11259 | as_fatal (_("invalid -mevexwig= option: `%s'"), arg); | |
11260 | break; | |
11261 | ||
167ad85b TG |
11262 | # if defined (TE_PE) || defined (TE_PEP) |
11263 | case OPTION_MBIG_OBJ: | |
11264 | use_big_obj = 1; | |
11265 | break; | |
11266 | #endif | |
11267 | ||
d1982f93 | 11268 | case OPTION_MOMIT_LOCK_PREFIX: |
d022bddd IT |
11269 | if (strcasecmp (arg, "yes") == 0) |
11270 | omit_lock_prefix = 1; | |
11271 | else if (strcasecmp (arg, "no") == 0) | |
11272 | omit_lock_prefix = 0; | |
11273 | else | |
11274 | as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg); | |
11275 | break; | |
11276 | ||
e4e00185 AS |
11277 | case OPTION_MFENCE_AS_LOCK_ADD: |
11278 | if (strcasecmp (arg, "yes") == 0) | |
11279 | avoid_fence = 1; | |
11280 | else if (strcasecmp (arg, "no") == 0) | |
11281 | avoid_fence = 0; | |
11282 | else | |
11283 | as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg); | |
11284 | break; | |
11285 | ||
0cb4071e L |
11286 | case OPTION_MRELAX_RELOCATIONS: |
11287 | if (strcasecmp (arg, "yes") == 0) | |
11288 | generate_relax_relocations = 1; | |
11289 | else if (strcasecmp (arg, "no") == 0) | |
11290 | generate_relax_relocations = 0; | |
11291 | else | |
11292 | as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg); | |
11293 | break; | |
11294 | ||
5db04b09 | 11295 | case OPTION_MAMD64: |
e89c5eaa | 11296 | intel64 = 0; |
5db04b09 L |
11297 | break; |
11298 | ||
11299 | case OPTION_MINTEL64: | |
e89c5eaa | 11300 | intel64 = 1; |
5db04b09 L |
11301 | break; |
11302 | ||
b6f8c7c4 L |
11303 | case 'O': |
11304 | if (arg == NULL) | |
11305 | { | |
11306 | optimize = 1; | |
11307 | /* Turn off -Os. */ | |
11308 | optimize_for_space = 0; | |
11309 | } | |
11310 | else if (*arg == 's') | |
11311 | { | |
11312 | optimize_for_space = 1; | |
11313 | /* Turn on all encoding optimizations. */ | |
11314 | optimize = -1; | |
11315 | } | |
11316 | else | |
11317 | { | |
11318 | optimize = atoi (arg); | |
11319 | /* Turn off -Os. */ | |
11320 | optimize_for_space = 0; | |
11321 | } | |
11322 | break; | |
11323 | ||
252b5132 RH |
11324 | default: |
11325 | return 0; | |
11326 | } | |
11327 | return 1; | |
11328 | } | |
11329 | ||
8a2c8fef L |
11330 | #define MESSAGE_TEMPLATE \ |
11331 | " " | |
11332 | ||
293f5f65 L |
11333 | static char * |
11334 | output_message (FILE *stream, char *p, char *message, char *start, | |
11335 | int *left_p, const char *name, int len) | |
11336 | { | |
11337 | int size = sizeof (MESSAGE_TEMPLATE); | |
11338 | int left = *left_p; | |
11339 | ||
11340 | /* Reserve 2 spaces for ", " or ",\0" */ | |
11341 | left -= len + 2; | |
11342 | ||
11343 | /* Check if there is any room. */ | |
11344 | if (left >= 0) | |
11345 | { | |
11346 | if (p != start) | |
11347 | { | |
11348 | *p++ = ','; | |
11349 | *p++ = ' '; | |
11350 | } | |
11351 | p = mempcpy (p, name, len); | |
11352 | } | |
11353 | else | |
11354 | { | |
11355 | /* Output the current message now and start a new one. */ | |
11356 | *p++ = ','; | |
11357 | *p = '\0'; | |
11358 | fprintf (stream, "%s\n", message); | |
11359 | p = start; | |
11360 | left = size - (start - message) - len - 2; | |
11361 | ||
11362 | gas_assert (left >= 0); | |
11363 | ||
11364 | p = mempcpy (p, name, len); | |
11365 | } | |
11366 | ||
11367 | *left_p = left; | |
11368 | return p; | |
11369 | } | |
11370 | ||
8a2c8fef | 11371 | static void |
1ded5609 | 11372 | show_arch (FILE *stream, int ext, int check) |
8a2c8fef L |
11373 | { |
11374 | static char message[] = MESSAGE_TEMPLATE; | |
11375 | char *start = message + 27; | |
11376 | char *p; | |
11377 | int size = sizeof (MESSAGE_TEMPLATE); | |
11378 | int left; | |
11379 | const char *name; | |
11380 | int len; | |
11381 | unsigned int j; | |
11382 | ||
11383 | p = start; | |
11384 | left = size - (start - message); | |
11385 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) | |
11386 | { | |
11387 | /* Should it be skipped? */ | |
11388 | if (cpu_arch [j].skip) | |
11389 | continue; | |
11390 | ||
11391 | name = cpu_arch [j].name; | |
11392 | len = cpu_arch [j].len; | |
11393 | if (*name == '.') | |
11394 | { | |
11395 | /* It is an extension. Skip if we aren't asked to show it. */ | |
11396 | if (ext) | |
11397 | { | |
11398 | name++; | |
11399 | len--; | |
11400 | } | |
11401 | else | |
11402 | continue; | |
11403 | } | |
11404 | else if (ext) | |
11405 | { | |
11406 | /* It is an processor. Skip if we show only extension. */ | |
11407 | continue; | |
11408 | } | |
1ded5609 JB |
11409 | else if (check && ! cpu_arch[j].flags.bitfield.cpui386) |
11410 | { | |
11411 | /* It is an impossible processor - skip. */ | |
11412 | continue; | |
11413 | } | |
8a2c8fef | 11414 | |
293f5f65 | 11415 | p = output_message (stream, p, message, start, &left, name, len); |
8a2c8fef L |
11416 | } |
11417 | ||
293f5f65 L |
11418 | /* Display disabled extensions. */ |
11419 | if (ext) | |
11420 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) | |
11421 | { | |
11422 | name = cpu_noarch [j].name; | |
11423 | len = cpu_noarch [j].len; | |
11424 | p = output_message (stream, p, message, start, &left, name, | |
11425 | len); | |
11426 | } | |
11427 | ||
8a2c8fef L |
11428 | *p = '\0'; |
11429 | fprintf (stream, "%s\n", message); | |
11430 | } | |
11431 | ||
252b5132 | 11432 | void |
8a2c8fef | 11433 | md_show_usage (FILE *stream) |
252b5132 | 11434 | { |
4cc782b5 ILT |
11435 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
11436 | fprintf (stream, _("\ | |
a38cf1db AM |
11437 | -Q ignored\n\ |
11438 | -V print assembler version number\n\ | |
b3b91714 AM |
11439 | -k ignored\n")); |
11440 | #endif | |
11441 | fprintf (stream, _("\ | |
12b55ccc | 11442 | -n Do not optimize code alignment\n\ |
b3b91714 AM |
11443 | -q quieten some warnings\n")); |
11444 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
11445 | fprintf (stream, _("\ | |
a38cf1db | 11446 | -s ignored\n")); |
b3b91714 | 11447 | #endif |
d7f449c0 L |
11448 | #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
11449 | || defined (TE_PE) || defined (TE_PEP)) | |
751d281c | 11450 | fprintf (stream, _("\ |
570561f7 | 11451 | --32/--64/--x32 generate 32bit/64bit/x32 code\n")); |
751d281c | 11452 | #endif |
b3b91714 AM |
11453 | #ifdef SVR4_COMMENT_CHARS |
11454 | fprintf (stream, _("\ | |
11455 | --divide do not treat `/' as a comment character\n")); | |
a38cf1db AM |
11456 | #else |
11457 | fprintf (stream, _("\ | |
b3b91714 | 11458 | --divide ignored\n")); |
4cc782b5 | 11459 | #endif |
9103f4f4 | 11460 | fprintf (stream, _("\ |
6305a203 | 11461 | -march=CPU[,+EXTENSION...]\n\ |
8a2c8fef | 11462 | generate code for CPU and EXTENSION, CPU is one of:\n")); |
1ded5609 | 11463 | show_arch (stream, 0, 1); |
8a2c8fef L |
11464 | fprintf (stream, _("\ |
11465 | EXTENSION is combination of:\n")); | |
1ded5609 | 11466 | show_arch (stream, 1, 0); |
6305a203 | 11467 | fprintf (stream, _("\ |
8a2c8fef | 11468 | -mtune=CPU optimize for CPU, CPU is one of:\n")); |
1ded5609 | 11469 | show_arch (stream, 0, 0); |
ba104c83 | 11470 | fprintf (stream, _("\ |
c0f3af97 L |
11471 | -msse2avx encode SSE instructions with VEX prefix\n")); |
11472 | fprintf (stream, _("\ | |
7c5c05ef | 11473 | -msse-check=[none|error|warning] (default: warning)\n\ |
daf50ae7 L |
11474 | check SSE instructions\n")); |
11475 | fprintf (stream, _("\ | |
7c5c05ef | 11476 | -moperand-check=[none|error|warning] (default: warning)\n\ |
7bab8ab5 JB |
11477 | check operand combinations for validity\n")); |
11478 | fprintf (stream, _("\ | |
7c5c05ef L |
11479 | -mavxscalar=[128|256] (default: 128)\n\ |
11480 | encode scalar AVX instructions with specific vector\n\ | |
539f890d L |
11481 | length\n")); |
11482 | fprintf (stream, _("\ | |
7c5c05ef L |
11483 | -mevexlig=[128|256|512] (default: 128)\n\ |
11484 | encode scalar EVEX instructions with specific vector\n\ | |
43234a1e L |
11485 | length\n")); |
11486 | fprintf (stream, _("\ | |
7c5c05ef L |
11487 | -mevexwig=[0|1] (default: 0)\n\ |
11488 | encode EVEX instructions with specific EVEX.W value\n\ | |
43234a1e L |
11489 | for EVEX.W bit ignored instructions\n")); |
11490 | fprintf (stream, _("\ | |
7c5c05ef | 11491 | -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\ |
d3d3c6db IT |
11492 | encode EVEX instructions with specific EVEX.RC value\n\ |
11493 | for SAE-only ignored instructions\n")); | |
11494 | fprintf (stream, _("\ | |
7c5c05ef L |
11495 | -mmnemonic=[att|intel] ")); |
11496 | if (SYSV386_COMPAT) | |
11497 | fprintf (stream, _("(default: att)\n")); | |
11498 | else | |
11499 | fprintf (stream, _("(default: intel)\n")); | |
11500 | fprintf (stream, _("\ | |
11501 | use AT&T/Intel mnemonic\n")); | |
ba104c83 | 11502 | fprintf (stream, _("\ |
7c5c05ef L |
11503 | -msyntax=[att|intel] (default: att)\n\ |
11504 | use AT&T/Intel syntax\n")); | |
ba104c83 L |
11505 | fprintf (stream, _("\ |
11506 | -mindex-reg support pseudo index registers\n")); | |
11507 | fprintf (stream, _("\ | |
11508 | -mnaked-reg don't require `%%' prefix for registers\n")); | |
11509 | fprintf (stream, _("\ | |
7e8b059b | 11510 | -madd-bnd-prefix add BND prefix for all valid branches\n")); |
b4a3a7b4 | 11511 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8dcea932 L |
11512 | fprintf (stream, _("\ |
11513 | -mshared disable branch optimization for shared code\n")); | |
b4a3a7b4 L |
11514 | fprintf (stream, _("\ |
11515 | -mx86-used-note=[no|yes] ")); | |
11516 | if (DEFAULT_X86_USED_NOTE) | |
11517 | fprintf (stream, _("(default: yes)\n")); | |
11518 | else | |
11519 | fprintf (stream, _("(default: no)\n")); | |
11520 | fprintf (stream, _("\ | |
11521 | generate x86 used ISA and feature properties\n")); | |
11522 | #endif | |
11523 | #if defined (TE_PE) || defined (TE_PEP) | |
167ad85b TG |
11524 | fprintf (stream, _("\ |
11525 | -mbig-obj generate big object files\n")); | |
11526 | #endif | |
d022bddd | 11527 | fprintf (stream, _("\ |
7c5c05ef | 11528 | -momit-lock-prefix=[no|yes] (default: no)\n\ |
d022bddd | 11529 | strip all lock prefixes\n")); |
5db04b09 | 11530 | fprintf (stream, _("\ |
7c5c05ef | 11531 | -mfence-as-lock-add=[no|yes] (default: no)\n\ |
e4e00185 AS |
11532 | encode lfence, mfence and sfence as\n\ |
11533 | lock addl $0x0, (%%{re}sp)\n")); | |
11534 | fprintf (stream, _("\ | |
7c5c05ef L |
11535 | -mrelax-relocations=[no|yes] ")); |
11536 | if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS) | |
11537 | fprintf (stream, _("(default: yes)\n")); | |
11538 | else | |
11539 | fprintf (stream, _("(default: no)\n")); | |
11540 | fprintf (stream, _("\ | |
0cb4071e L |
11541 | generate relax relocations\n")); |
11542 | fprintf (stream, _("\ | |
7c5c05ef | 11543 | -mamd64 accept only AMD64 ISA [default]\n")); |
5db04b09 L |
11544 | fprintf (stream, _("\ |
11545 | -mintel64 accept only Intel64 ISA\n")); | |
252b5132 RH |
11546 | } |
11547 | ||
3e73aa7c | 11548 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
321098a5 | 11549 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
e57f8c65 | 11550 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
252b5132 RH |
11551 | |
11552 | /* Pick the target format to use. */ | |
11553 | ||
47926f60 | 11554 | const char * |
e3bb37b5 | 11555 | i386_target_format (void) |
252b5132 | 11556 | { |
351f65ca L |
11557 | if (!strncmp (default_arch, "x86_64", 6)) |
11558 | { | |
11559 | update_code_flag (CODE_64BIT, 1); | |
11560 | if (default_arch[6] == '\0') | |
7f56bc95 | 11561 | x86_elf_abi = X86_64_ABI; |
351f65ca | 11562 | else |
7f56bc95 | 11563 | x86_elf_abi = X86_64_X32_ABI; |
351f65ca | 11564 | } |
3e73aa7c | 11565 | else if (!strcmp (default_arch, "i386")) |
78f12dd3 | 11566 | update_code_flag (CODE_32BIT, 1); |
5197d474 L |
11567 | else if (!strcmp (default_arch, "iamcu")) |
11568 | { | |
11569 | update_code_flag (CODE_32BIT, 1); | |
11570 | if (cpu_arch_isa == PROCESSOR_UNKNOWN) | |
11571 | { | |
11572 | static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS; | |
11573 | cpu_arch_name = "iamcu"; | |
11574 | cpu_sub_arch_name = NULL; | |
11575 | cpu_arch_flags = iamcu_flags; | |
11576 | cpu_arch_isa = PROCESSOR_IAMCU; | |
11577 | cpu_arch_isa_flags = iamcu_flags; | |
11578 | if (!cpu_arch_tune_set) | |
11579 | { | |
11580 | cpu_arch_tune = cpu_arch_isa; | |
11581 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
11582 | } | |
11583 | } | |
8d471ec1 | 11584 | else if (cpu_arch_isa != PROCESSOR_IAMCU) |
5197d474 L |
11585 | as_fatal (_("Intel MCU doesn't support `%s' architecture"), |
11586 | cpu_arch_name); | |
11587 | } | |
3e73aa7c | 11588 | else |
2b5d6a91 | 11589 | as_fatal (_("unknown architecture")); |
89507696 JB |
11590 | |
11591 | if (cpu_flags_all_zero (&cpu_arch_isa_flags)) | |
11592 | cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags; | |
11593 | if (cpu_flags_all_zero (&cpu_arch_tune_flags)) | |
11594 | cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags; | |
11595 | ||
252b5132 RH |
11596 | switch (OUTPUT_FLAVOR) |
11597 | { | |
9384f2ff | 11598 | #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT) |
4c63da97 | 11599 | case bfd_target_aout_flavour: |
47926f60 | 11600 | return AOUT_TARGET_FORMAT; |
4c63da97 | 11601 | #endif |
9384f2ff AM |
11602 | #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF) |
11603 | # if defined (TE_PE) || defined (TE_PEP) | |
11604 | case bfd_target_coff_flavour: | |
167ad85b TG |
11605 | if (flag_code == CODE_64BIT) |
11606 | return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64"; | |
11607 | else | |
11608 | return "pe-i386"; | |
9384f2ff | 11609 | # elif defined (TE_GO32) |
0561d57c JK |
11610 | case bfd_target_coff_flavour: |
11611 | return "coff-go32"; | |
9384f2ff | 11612 | # else |
252b5132 RH |
11613 | case bfd_target_coff_flavour: |
11614 | return "coff-i386"; | |
9384f2ff | 11615 | # endif |
4c63da97 | 11616 | #endif |
3e73aa7c | 11617 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
252b5132 | 11618 | case bfd_target_elf_flavour: |
3e73aa7c | 11619 | { |
351f65ca L |
11620 | const char *format; |
11621 | ||
11622 | switch (x86_elf_abi) | |
4fa24527 | 11623 | { |
351f65ca L |
11624 | default: |
11625 | format = ELF_TARGET_FORMAT; | |
11626 | break; | |
7f56bc95 | 11627 | case X86_64_ABI: |
351f65ca | 11628 | use_rela_relocations = 1; |
4fa24527 | 11629 | object_64bit = 1; |
351f65ca L |
11630 | format = ELF_TARGET_FORMAT64; |
11631 | break; | |
7f56bc95 | 11632 | case X86_64_X32_ABI: |
4fa24527 | 11633 | use_rela_relocations = 1; |
351f65ca | 11634 | object_64bit = 1; |
862be3fb | 11635 | disallow_64bit_reloc = 1; |
351f65ca L |
11636 | format = ELF_TARGET_FORMAT32; |
11637 | break; | |
4fa24527 | 11638 | } |
3632d14b | 11639 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 | 11640 | { |
7f56bc95 | 11641 | if (x86_elf_abi != X86_64_ABI) |
8a9036a4 L |
11642 | as_fatal (_("Intel L1OM is 64bit only")); |
11643 | return ELF_TARGET_L1OM_FORMAT; | |
11644 | } | |
b49f93f6 | 11645 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
7a9068fe L |
11646 | { |
11647 | if (x86_elf_abi != X86_64_ABI) | |
11648 | as_fatal (_("Intel K1OM is 64bit only")); | |
11649 | return ELF_TARGET_K1OM_FORMAT; | |
11650 | } | |
81486035 L |
11651 | else if (cpu_arch_isa == PROCESSOR_IAMCU) |
11652 | { | |
11653 | if (x86_elf_abi != I386_ABI) | |
11654 | as_fatal (_("Intel MCU is 32bit only")); | |
11655 | return ELF_TARGET_IAMCU_FORMAT; | |
11656 | } | |
8a9036a4 | 11657 | else |
351f65ca | 11658 | return format; |
3e73aa7c | 11659 | } |
e57f8c65 TG |
11660 | #endif |
11661 | #if defined (OBJ_MACH_O) | |
11662 | case bfd_target_mach_o_flavour: | |
d382c579 TG |
11663 | if (flag_code == CODE_64BIT) |
11664 | { | |
11665 | use_rela_relocations = 1; | |
11666 | object_64bit = 1; | |
11667 | return "mach-o-x86-64"; | |
11668 | } | |
11669 | else | |
11670 | return "mach-o-i386"; | |
4c63da97 | 11671 | #endif |
252b5132 RH |
11672 | default: |
11673 | abort (); | |
11674 | return NULL; | |
11675 | } | |
11676 | } | |
11677 | ||
47926f60 | 11678 | #endif /* OBJ_MAYBE_ more than one */ |
252b5132 | 11679 | \f |
252b5132 | 11680 | symbolS * |
7016a5d5 | 11681 | md_undefined_symbol (char *name) |
252b5132 | 11682 | { |
18dc2407 ILT |
11683 | if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] |
11684 | && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] | |
11685 | && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] | |
11686 | && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) | |
24eab124 AM |
11687 | { |
11688 | if (!GOT_symbol) | |
11689 | { | |
11690 | if (symbol_find (name)) | |
11691 | as_bad (_("GOT already in symbol table")); | |
11692 | GOT_symbol = symbol_new (name, undefined_section, | |
11693 | (valueT) 0, &zero_address_frag); | |
11694 | }; | |
11695 | return GOT_symbol; | |
11696 | } | |
252b5132 RH |
11697 | return 0; |
11698 | } | |
11699 | ||
11700 | /* Round up a section size to the appropriate boundary. */ | |
47926f60 | 11701 | |
252b5132 | 11702 | valueT |
7016a5d5 | 11703 | md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) |
252b5132 | 11704 | { |
4c63da97 AM |
11705 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
11706 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
11707 | { | |
11708 | /* For a.out, force the section size to be aligned. If we don't do | |
11709 | this, BFD will align it for us, but it will not write out the | |
11710 | final bytes of the section. This may be a bug in BFD, but it is | |
11711 | easier to fix it here since that is how the other a.out targets | |
11712 | work. */ | |
11713 | int align; | |
11714 | ||
11715 | align = bfd_get_section_alignment (stdoutput, segment); | |
8d3842cd | 11716 | size = ((size + (1 << align) - 1) & (-((valueT) 1 << align))); |
4c63da97 | 11717 | } |
252b5132 RH |
11718 | #endif |
11719 | ||
11720 | return size; | |
11721 | } | |
11722 | ||
11723 | /* On the i386, PC-relative offsets are relative to the start of the | |
11724 | next instruction. That is, the address of the offset, plus its | |
11725 | size, since the offset is always the last part of the insn. */ | |
11726 | ||
11727 | long | |
e3bb37b5 | 11728 | md_pcrel_from (fixS *fixP) |
252b5132 RH |
11729 | { |
11730 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
11731 | } | |
11732 | ||
11733 | #ifndef I386COFF | |
11734 | ||
11735 | static void | |
e3bb37b5 | 11736 | s_bss (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 11737 | { |
29b0f896 | 11738 | int temp; |
252b5132 | 11739 | |
8a75718c JB |
11740 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
11741 | if (IS_ELF) | |
11742 | obj_elf_section_change_hook (); | |
11743 | #endif | |
252b5132 RH |
11744 | temp = get_absolute_expression (); |
11745 | subseg_set (bss_section, (subsegT) temp); | |
11746 | demand_empty_rest_of_line (); | |
11747 | } | |
11748 | ||
11749 | #endif | |
11750 | ||
252b5132 | 11751 | void |
e3bb37b5 | 11752 | i386_validate_fix (fixS *fixp) |
252b5132 | 11753 | { |
02a86693 | 11754 | if (fixp->fx_subsy) |
252b5132 | 11755 | { |
02a86693 | 11756 | if (fixp->fx_subsy == GOT_symbol) |
23df1078 | 11757 | { |
02a86693 L |
11758 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) |
11759 | { | |
11760 | if (!object_64bit) | |
11761 | abort (); | |
11762 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
11763 | if (fixp->fx_tcbit2) | |
56ceb5b5 L |
11764 | fixp->fx_r_type = (fixp->fx_tcbit |
11765 | ? BFD_RELOC_X86_64_REX_GOTPCRELX | |
11766 | : BFD_RELOC_X86_64_GOTPCRELX); | |
02a86693 L |
11767 | else |
11768 | #endif | |
11769 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; | |
11770 | } | |
d6ab8113 | 11771 | else |
02a86693 L |
11772 | { |
11773 | if (!object_64bit) | |
11774 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; | |
11775 | else | |
11776 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64; | |
11777 | } | |
11778 | fixp->fx_subsy = 0; | |
23df1078 | 11779 | } |
252b5132 | 11780 | } |
02a86693 L |
11781 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
11782 | else if (!object_64bit) | |
11783 | { | |
11784 | if (fixp->fx_r_type == BFD_RELOC_386_GOT32 | |
11785 | && fixp->fx_tcbit2) | |
11786 | fixp->fx_r_type = BFD_RELOC_386_GOT32X; | |
11787 | } | |
11788 | #endif | |
252b5132 RH |
11789 | } |
11790 | ||
252b5132 | 11791 | arelent * |
7016a5d5 | 11792 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
11793 | { |
11794 | arelent *rel; | |
11795 | bfd_reloc_code_real_type code; | |
11796 | ||
11797 | switch (fixp->fx_r_type) | |
11798 | { | |
8ce3d284 | 11799 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
11800 | case BFD_RELOC_SIZE32: |
11801 | case BFD_RELOC_SIZE64: | |
11802 | if (S_IS_DEFINED (fixp->fx_addsy) | |
11803 | && !S_IS_EXTERNAL (fixp->fx_addsy)) | |
11804 | { | |
11805 | /* Resolve size relocation against local symbol to size of | |
11806 | the symbol plus addend. */ | |
11807 | valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset; | |
11808 | if (fixp->fx_r_type == BFD_RELOC_SIZE32 | |
11809 | && !fits_in_unsigned_long (value)) | |
11810 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
11811 | _("symbol size computation overflow")); | |
11812 | fixp->fx_addsy = NULL; | |
11813 | fixp->fx_subsy = NULL; | |
11814 | md_apply_fix (fixp, (valueT *) &value, NULL); | |
11815 | return NULL; | |
11816 | } | |
8ce3d284 | 11817 | #endif |
1a0670f3 | 11818 | /* Fall through. */ |
8fd4256d | 11819 | |
3e73aa7c JH |
11820 | case BFD_RELOC_X86_64_PLT32: |
11821 | case BFD_RELOC_X86_64_GOT32: | |
11822 | case BFD_RELOC_X86_64_GOTPCREL: | |
56ceb5b5 L |
11823 | case BFD_RELOC_X86_64_GOTPCRELX: |
11824 | case BFD_RELOC_X86_64_REX_GOTPCRELX: | |
252b5132 RH |
11825 | case BFD_RELOC_386_PLT32: |
11826 | case BFD_RELOC_386_GOT32: | |
02a86693 | 11827 | case BFD_RELOC_386_GOT32X: |
252b5132 RH |
11828 | case BFD_RELOC_386_GOTOFF: |
11829 | case BFD_RELOC_386_GOTPC: | |
13ae64f3 JJ |
11830 | case BFD_RELOC_386_TLS_GD: |
11831 | case BFD_RELOC_386_TLS_LDM: | |
11832 | case BFD_RELOC_386_TLS_LDO_32: | |
11833 | case BFD_RELOC_386_TLS_IE_32: | |
37e55690 JJ |
11834 | case BFD_RELOC_386_TLS_IE: |
11835 | case BFD_RELOC_386_TLS_GOTIE: | |
13ae64f3 JJ |
11836 | case BFD_RELOC_386_TLS_LE_32: |
11837 | case BFD_RELOC_386_TLS_LE: | |
67a4f2b7 AO |
11838 | case BFD_RELOC_386_TLS_GOTDESC: |
11839 | case BFD_RELOC_386_TLS_DESC_CALL: | |
bffbf940 JJ |
11840 | case BFD_RELOC_X86_64_TLSGD: |
11841 | case BFD_RELOC_X86_64_TLSLD: | |
11842 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 11843 | case BFD_RELOC_X86_64_DTPOFF64: |
bffbf940 JJ |
11844 | case BFD_RELOC_X86_64_GOTTPOFF: |
11845 | case BFD_RELOC_X86_64_TPOFF32: | |
d6ab8113 JB |
11846 | case BFD_RELOC_X86_64_TPOFF64: |
11847 | case BFD_RELOC_X86_64_GOTOFF64: | |
11848 | case BFD_RELOC_X86_64_GOTPC32: | |
7b81dfbb AJ |
11849 | case BFD_RELOC_X86_64_GOT64: |
11850 | case BFD_RELOC_X86_64_GOTPCREL64: | |
11851 | case BFD_RELOC_X86_64_GOTPC64: | |
11852 | case BFD_RELOC_X86_64_GOTPLT64: | |
11853 | case BFD_RELOC_X86_64_PLTOFF64: | |
67a4f2b7 AO |
11854 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
11855 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
252b5132 RH |
11856 | case BFD_RELOC_RVA: |
11857 | case BFD_RELOC_VTABLE_ENTRY: | |
11858 | case BFD_RELOC_VTABLE_INHERIT: | |
6482c264 NC |
11859 | #ifdef TE_PE |
11860 | case BFD_RELOC_32_SECREL: | |
11861 | #endif | |
252b5132 RH |
11862 | code = fixp->fx_r_type; |
11863 | break; | |
dbbaec26 L |
11864 | case BFD_RELOC_X86_64_32S: |
11865 | if (!fixp->fx_pcrel) | |
11866 | { | |
11867 | /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */ | |
11868 | code = fixp->fx_r_type; | |
11869 | break; | |
11870 | } | |
1a0670f3 | 11871 | /* Fall through. */ |
252b5132 | 11872 | default: |
93382f6d | 11873 | if (fixp->fx_pcrel) |
252b5132 | 11874 | { |
93382f6d AM |
11875 | switch (fixp->fx_size) |
11876 | { | |
11877 | default: | |
b091f402 AM |
11878 | as_bad_where (fixp->fx_file, fixp->fx_line, |
11879 | _("can not do %d byte pc-relative relocation"), | |
11880 | fixp->fx_size); | |
93382f6d AM |
11881 | code = BFD_RELOC_32_PCREL; |
11882 | break; | |
11883 | case 1: code = BFD_RELOC_8_PCREL; break; | |
11884 | case 2: code = BFD_RELOC_16_PCREL; break; | |
d258b828 | 11885 | case 4: code = BFD_RELOC_32_PCREL; break; |
d6ab8113 JB |
11886 | #ifdef BFD64 |
11887 | case 8: code = BFD_RELOC_64_PCREL; break; | |
11888 | #endif | |
93382f6d AM |
11889 | } |
11890 | } | |
11891 | else | |
11892 | { | |
11893 | switch (fixp->fx_size) | |
11894 | { | |
11895 | default: | |
b091f402 AM |
11896 | as_bad_where (fixp->fx_file, fixp->fx_line, |
11897 | _("can not do %d byte relocation"), | |
11898 | fixp->fx_size); | |
93382f6d AM |
11899 | code = BFD_RELOC_32; |
11900 | break; | |
11901 | case 1: code = BFD_RELOC_8; break; | |
11902 | case 2: code = BFD_RELOC_16; break; | |
11903 | case 4: code = BFD_RELOC_32; break; | |
937149dd | 11904 | #ifdef BFD64 |
3e73aa7c | 11905 | case 8: code = BFD_RELOC_64; break; |
937149dd | 11906 | #endif |
93382f6d | 11907 | } |
252b5132 RH |
11908 | } |
11909 | break; | |
11910 | } | |
252b5132 | 11911 | |
d182319b JB |
11912 | if ((code == BFD_RELOC_32 |
11913 | || code == BFD_RELOC_32_PCREL | |
11914 | || code == BFD_RELOC_X86_64_32S) | |
252b5132 RH |
11915 | && GOT_symbol |
11916 | && fixp->fx_addsy == GOT_symbol) | |
3e73aa7c | 11917 | { |
4fa24527 | 11918 | if (!object_64bit) |
d6ab8113 JB |
11919 | code = BFD_RELOC_386_GOTPC; |
11920 | else | |
11921 | code = BFD_RELOC_X86_64_GOTPC32; | |
3e73aa7c | 11922 | } |
7b81dfbb AJ |
11923 | if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL) |
11924 | && GOT_symbol | |
11925 | && fixp->fx_addsy == GOT_symbol) | |
11926 | { | |
11927 | code = BFD_RELOC_X86_64_GOTPC64; | |
11928 | } | |
252b5132 | 11929 | |
add39d23 TS |
11930 | rel = XNEW (arelent); |
11931 | rel->sym_ptr_ptr = XNEW (asymbol *); | |
49309057 | 11932 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
252b5132 RH |
11933 | |
11934 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
c87db184 | 11935 | |
3e73aa7c JH |
11936 | if (!use_rela_relocations) |
11937 | { | |
11938 | /* HACK: Since i386 ELF uses Rel instead of Rela, encode the | |
11939 | vtable entry to be used in the relocation's section offset. */ | |
11940 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
11941 | rel->address = fixp->fx_offset; | |
fbeb56a4 DK |
11942 | #if defined (OBJ_COFF) && defined (TE_PE) |
11943 | else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy)) | |
11944 | rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2); | |
11945 | else | |
11946 | #endif | |
c6682705 | 11947 | rel->addend = 0; |
3e73aa7c JH |
11948 | } |
11949 | /* Use the rela in 64bit mode. */ | |
252b5132 | 11950 | else |
3e73aa7c | 11951 | { |
862be3fb L |
11952 | if (disallow_64bit_reloc) |
11953 | switch (code) | |
11954 | { | |
862be3fb L |
11955 | case BFD_RELOC_X86_64_DTPOFF64: |
11956 | case BFD_RELOC_X86_64_TPOFF64: | |
11957 | case BFD_RELOC_64_PCREL: | |
11958 | case BFD_RELOC_X86_64_GOTOFF64: | |
11959 | case BFD_RELOC_X86_64_GOT64: | |
11960 | case BFD_RELOC_X86_64_GOTPCREL64: | |
11961 | case BFD_RELOC_X86_64_GOTPC64: | |
11962 | case BFD_RELOC_X86_64_GOTPLT64: | |
11963 | case BFD_RELOC_X86_64_PLTOFF64: | |
11964 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
11965 | _("cannot represent relocation type %s in x32 mode"), | |
11966 | bfd_get_reloc_code_name (code)); | |
11967 | break; | |
11968 | default: | |
11969 | break; | |
11970 | } | |
11971 | ||
062cd5e7 AS |
11972 | if (!fixp->fx_pcrel) |
11973 | rel->addend = fixp->fx_offset; | |
11974 | else | |
11975 | switch (code) | |
11976 | { | |
11977 | case BFD_RELOC_X86_64_PLT32: | |
11978 | case BFD_RELOC_X86_64_GOT32: | |
11979 | case BFD_RELOC_X86_64_GOTPCREL: | |
56ceb5b5 L |
11980 | case BFD_RELOC_X86_64_GOTPCRELX: |
11981 | case BFD_RELOC_X86_64_REX_GOTPCRELX: | |
bffbf940 JJ |
11982 | case BFD_RELOC_X86_64_TLSGD: |
11983 | case BFD_RELOC_X86_64_TLSLD: | |
11984 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 AO |
11985 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
11986 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
062cd5e7 AS |
11987 | rel->addend = fixp->fx_offset - fixp->fx_size; |
11988 | break; | |
11989 | default: | |
11990 | rel->addend = (section->vma | |
11991 | - fixp->fx_size | |
11992 | + fixp->fx_addnumber | |
11993 | + md_pcrel_from (fixp)); | |
11994 | break; | |
11995 | } | |
3e73aa7c JH |
11996 | } |
11997 | ||
252b5132 RH |
11998 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); |
11999 | if (rel->howto == NULL) | |
12000 | { | |
12001 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
d0b47220 | 12002 | _("cannot represent relocation type %s"), |
252b5132 RH |
12003 | bfd_get_reloc_code_name (code)); |
12004 | /* Set howto to a garbage value so that we can keep going. */ | |
12005 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); | |
9c2799c2 | 12006 | gas_assert (rel->howto != NULL); |
252b5132 RH |
12007 | } |
12008 | ||
12009 | return rel; | |
12010 | } | |
12011 | ||
ee86248c | 12012 | #include "tc-i386-intel.c" |
54cfded0 | 12013 | |
a60de03c JB |
12014 | void |
12015 | tc_x86_parse_to_dw2regnum (expressionS *exp) | |
54cfded0 | 12016 | { |
a60de03c JB |
12017 | int saved_naked_reg; |
12018 | char saved_register_dot; | |
54cfded0 | 12019 | |
a60de03c JB |
12020 | saved_naked_reg = allow_naked_reg; |
12021 | allow_naked_reg = 1; | |
12022 | saved_register_dot = register_chars['.']; | |
12023 | register_chars['.'] = '.'; | |
12024 | allow_pseudo_reg = 1; | |
12025 | expression_and_evaluate (exp); | |
12026 | allow_pseudo_reg = 0; | |
12027 | register_chars['.'] = saved_register_dot; | |
12028 | allow_naked_reg = saved_naked_reg; | |
12029 | ||
e96d56a1 | 12030 | if (exp->X_op == O_register && exp->X_add_number >= 0) |
54cfded0 | 12031 | { |
a60de03c JB |
12032 | if ((addressT) exp->X_add_number < i386_regtab_size) |
12033 | { | |
12034 | exp->X_op = O_constant; | |
12035 | exp->X_add_number = i386_regtab[exp->X_add_number] | |
12036 | .dw2_regnum[flag_code >> 1]; | |
12037 | } | |
12038 | else | |
12039 | exp->X_op = O_illegal; | |
54cfded0 | 12040 | } |
54cfded0 AM |
12041 | } |
12042 | ||
12043 | void | |
12044 | tc_x86_frame_initial_instructions (void) | |
12045 | { | |
a60de03c JB |
12046 | static unsigned int sp_regno[2]; |
12047 | ||
12048 | if (!sp_regno[flag_code >> 1]) | |
12049 | { | |
12050 | char *saved_input = input_line_pointer; | |
12051 | char sp[][4] = {"esp", "rsp"}; | |
12052 | expressionS exp; | |
a4447b93 | 12053 | |
a60de03c JB |
12054 | input_line_pointer = sp[flag_code >> 1]; |
12055 | tc_x86_parse_to_dw2regnum (&exp); | |
9c2799c2 | 12056 | gas_assert (exp.X_op == O_constant); |
a60de03c JB |
12057 | sp_regno[flag_code >> 1] = exp.X_add_number; |
12058 | input_line_pointer = saved_input; | |
12059 | } | |
a4447b93 | 12060 | |
61ff971f L |
12061 | cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment); |
12062 | cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment); | |
54cfded0 | 12063 | } |
d2b2c203 | 12064 | |
d7921315 L |
12065 | int |
12066 | x86_dwarf2_addr_size (void) | |
12067 | { | |
12068 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) | |
12069 | if (x86_elf_abi == X86_64_X32_ABI) | |
12070 | return 4; | |
12071 | #endif | |
12072 | return bfd_arch_bits_per_address (stdoutput) / 8; | |
12073 | } | |
12074 | ||
d2b2c203 DJ |
12075 | int |
12076 | i386_elf_section_type (const char *str, size_t len) | |
12077 | { | |
12078 | if (flag_code == CODE_64BIT | |
12079 | && len == sizeof ("unwind") - 1 | |
12080 | && strncmp (str, "unwind", 6) == 0) | |
12081 | return SHT_X86_64_UNWIND; | |
12082 | ||
12083 | return -1; | |
12084 | } | |
bb41ade5 | 12085 | |
ad5fec3b EB |
12086 | #ifdef TE_SOLARIS |
12087 | void | |
12088 | i386_solaris_fix_up_eh_frame (segT sec) | |
12089 | { | |
12090 | if (flag_code == CODE_64BIT) | |
12091 | elf_section_type (sec) = SHT_X86_64_UNWIND; | |
12092 | } | |
12093 | #endif | |
12094 | ||
bb41ade5 AM |
12095 | #ifdef TE_PE |
12096 | void | |
12097 | tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) | |
12098 | { | |
91d6fa6a | 12099 | expressionS exp; |
bb41ade5 | 12100 | |
91d6fa6a NC |
12101 | exp.X_op = O_secrel; |
12102 | exp.X_add_symbol = symbol; | |
12103 | exp.X_add_number = 0; | |
12104 | emit_expr (&exp, size); | |
bb41ade5 AM |
12105 | } |
12106 | #endif | |
3b22753a L |
12107 | |
12108 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
12109 | /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */ | |
12110 | ||
01e1a5bc | 12111 | bfd_vma |
6d4af3c2 | 12112 | x86_64_section_letter (int letter, const char **ptr_msg) |
3b22753a L |
12113 | { |
12114 | if (flag_code == CODE_64BIT) | |
12115 | { | |
12116 | if (letter == 'l') | |
12117 | return SHF_X86_64_LARGE; | |
12118 | ||
8f3bae45 | 12119 | *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string"); |
64e74474 | 12120 | } |
3b22753a | 12121 | else |
8f3bae45 | 12122 | *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string"); |
3b22753a L |
12123 | return -1; |
12124 | } | |
12125 | ||
01e1a5bc | 12126 | bfd_vma |
3b22753a L |
12127 | x86_64_section_word (char *str, size_t len) |
12128 | { | |
8620418b | 12129 | if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large")) |
3b22753a L |
12130 | return SHF_X86_64_LARGE; |
12131 | ||
12132 | return -1; | |
12133 | } | |
12134 | ||
12135 | static void | |
12136 | handle_large_common (int small ATTRIBUTE_UNUSED) | |
12137 | { | |
12138 | if (flag_code != CODE_64BIT) | |
12139 | { | |
12140 | s_comm_internal (0, elf_common_parse); | |
12141 | as_warn (_(".largecomm supported only in 64bit mode, producing .comm")); | |
12142 | } | |
12143 | else | |
12144 | { | |
12145 | static segT lbss_section; | |
12146 | asection *saved_com_section_ptr = elf_com_section_ptr; | |
12147 | asection *saved_bss_section = bss_section; | |
12148 | ||
12149 | if (lbss_section == NULL) | |
12150 | { | |
12151 | flagword applicable; | |
12152 | segT seg = now_seg; | |
12153 | subsegT subseg = now_subseg; | |
12154 | ||
12155 | /* The .lbss section is for local .largecomm symbols. */ | |
12156 | lbss_section = subseg_new (".lbss", 0); | |
12157 | applicable = bfd_applicable_section_flags (stdoutput); | |
12158 | bfd_set_section_flags (stdoutput, lbss_section, | |
12159 | applicable & SEC_ALLOC); | |
12160 | seg_info (lbss_section)->bss = 1; | |
12161 | ||
12162 | subseg_set (seg, subseg); | |
12163 | } | |
12164 | ||
12165 | elf_com_section_ptr = &_bfd_elf_large_com_section; | |
12166 | bss_section = lbss_section; | |
12167 | ||
12168 | s_comm_internal (0, elf_common_parse); | |
12169 | ||
12170 | elf_com_section_ptr = saved_com_section_ptr; | |
12171 | bss_section = saved_bss_section; | |
12172 | } | |
12173 | } | |
12174 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |