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i386: Add support to get/set/migrate Intel Processor Trace feature
[qemu.git] / target / i386 / kvm.c
CommitLineData
05330448
AL		 1/*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <[email protected]>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
b6a0aa05 15#include "qemu/osdep.h"
da34e65c 16#include "qapi/error.h"
05330448 17#include <sys/ioctl.h>
25d2e361 18#include <sys/utsname.h>
05330448
AL		 19
20#include <linux/kvm.h>
5802e066 21#include <linux/kvm_para.h>
05330448
AL		 22
23#include "qemu-common.h"
33c11879 24#include "cpu.h"
9c17d615 25#include "sysemu/sysemu.h"
b3946626 26#include "sysemu/hw_accel.h"
6410848b 27#include "sysemu/kvm_int.h"
1d31f66b 28#include "kvm_i386.h"
50efe82c 29#include "hyperv.h"
5e953812 30#include "hyperv-proto.h"
50efe82c 31
022c62cb 32#include "exec/gdbstub.h"
1de7afc9
PB		 33#include "qemu/host-utils.h"
34#include "qemu/config-file.h"
1c4a55db 35#include "qemu/error-report.h"
0d09e41a
PB		 36#include "hw/i386/pc.h"
37#include "hw/i386/apic.h"
e0723c45
PB		 38#include "hw/i386/apic_internal.h"
39#include "hw/i386/apic-msidef.h"
8b5ed7df 40#include "hw/i386/intel_iommu.h"
e1d4fb2d 41#include "hw/i386/x86-iommu.h"
50efe82c 42
022c62cb 43#include "exec/ioport.h"
a2cb15b0 44#include "hw/pci/pci.h"
15eafc2e 45#include "hw/pci/msi.h"
fd563564 46#include "hw/pci/msix.h"
795c40b8 47#include "migration/blocker.h"
4c663752 48#include "exec/memattrs.h"
8b5ed7df 49#include "trace.h"
05330448
AL		 50
51//#define DEBUG_KVM
52
53#ifdef DEBUG_KVM
8c0d577e 54#define DPRINTF(fmt, ...) \
05330448
AL		 55 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
56#else
8c0d577e 57#define DPRINTF(fmt, ...) \
05330448
AL		 58 do { } while (0)
59#endif
60
1a03675d
GC		 61#define MSR_KVM_WALL_CLOCK 0x11
62#define MSR_KVM_SYSTEM_TIME 0x12
63
d1138251
EH		 64/* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
65 * 255 kvm_msr_entry structs */
66#define MSR_BUF_SIZE 4096
d71b62a1 67
94a8d39a
JK		 68const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
69 KVM_CAP_INFO(SET_TSS_ADDR),
70 KVM_CAP_INFO(EXT_CPUID),
71 KVM_CAP_INFO(MP_STATE),
72 KVM_CAP_LAST_INFO
73};
25d2e361 74
c3a3a7d3
JK		 75static bool has_msr_star;
76static bool has_msr_hsave_pa;
c9b8f6b6 77static bool has_msr_tsc_aux;
f28558d3 78static bool has_msr_tsc_adjust;
aa82ba54 79static bool has_msr_tsc_deadline;
df67696e 80static bool has_msr_feature_control;
21e87c46 81static bool has_msr_misc_enable;
fc12d72e 82static bool has_msr_smbase;
79e9ebeb 83static bool has_msr_bndcfgs;
25d2e361 84static int lm_capable_kernel;
7bc3d711 85static bool has_msr_hv_hypercall;
f2a53c9e 86static bool has_msr_hv_crash;
744b8a94 87static bool has_msr_hv_reset;
8c145d7c 88static bool has_msr_hv_vpindex;
46eb8f98 89static bool has_msr_hv_runtime;
866eea9a 90static bool has_msr_hv_synic;
ff99aa64 91static bool has_msr_hv_stimer;
d72bc7f6 92static bool has_msr_hv_frequencies;
18cd2c17 93static bool has_msr_xss;
a33a2cfe 94static bool has_msr_spec_ctrl;
b827df58 95
0b368a10
JD		 96static uint32_t has_architectural_pmu_version;
97static uint32_t num_architectural_pmu_gp_counters;
98static uint32_t num_architectural_pmu_fixed_counters;
0d894367 99
28143b40
TH		 100static int has_xsave;
101static int has_xcrs;
102static int has_pit_state2;
103
87f8b626
AR		 104static bool has_msr_mcg_ext_ctl;
105
494e95e9
CP		 106static struct kvm_cpuid2 *cpuid_cache;
107
28143b40
TH		 108int kvm_has_pit_state2(void)
109{
110 return has_pit_state2;
111}
112
355023f2
PB		 113bool kvm_has_smm(void)
114{
115 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
116}
117
6053a86f
MT		 118bool kvm_has_adjust_clock_stable(void)
119{
120 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
121
122 return (ret == KVM_CLOCK_TSC_STABLE);
123}
124
1d31f66b
PM		 125bool kvm_allows_irq0_override(void)
126{
127 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
128}
129
fb506e70
RK		 130static bool kvm_x2apic_api_set_flags(uint64_t flags)
131{
132 KVMState *s = KVM_STATE(current_machine->accelerator);
133
134 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
135}
136
e391c009 137#define MEMORIZE(fn, _result) \
2a138ec3 138 ({ \
2a138ec3
RK		 139 static bool _memorized; \
140 \
141 if (_memorized) { \
142 return _result; \
143 } \
144 _memorized = true; \
145 _result = fn; \
146 })
147
e391c009
IM		 148static bool has_x2apic_api;
149
150bool kvm_has_x2apic_api(void)
151{
152 return has_x2apic_api;
153}
154
fb506e70
RK		 155bool kvm_enable_x2apic(void)
156{
2a138ec3
RK		 157 return MEMORIZE(
158 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
e391c009
IM		 159 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
160 has_x2apic_api);
fb506e70
RK		 161}
162
0fd7e098
LL		 163static int kvm_get_tsc(CPUState *cs)
164{
165 X86CPU *cpu = X86_CPU(cs);
166 CPUX86State *env = &cpu->env;
167 struct {
168 struct kvm_msrs info;
169 struct kvm_msr_entry entries[1];
170 } msr_data;
171 int ret;
172
173 if (env->tsc_valid) {
174 return 0;
175 }
176
177 msr_data.info.nmsrs = 1;
178 msr_data.entries[0].index = MSR_IA32_TSC;
179 env->tsc_valid = !runstate_is_running();
180
181 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
182 if (ret < 0) {
183 return ret;
184 }
185
48e1a45c 186 assert(ret == 1);
0fd7e098
LL		 187 env->tsc = msr_data.entries[0].data;
188 return 0;
189}
190
14e6fe12 191static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
0fd7e098 192{
0fd7e098
LL		 193 kvm_get_tsc(cpu);
194}
195
196void kvm_synchronize_all_tsc(void)
197{
198 CPUState *cpu;
199
200 if (kvm_enabled()) {
201 CPU_FOREACH(cpu) {
14e6fe12 202 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
0fd7e098
LL		 203 }
204 }
205}
206
b827df58
AK		 207static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
208{
209 struct kvm_cpuid2 *cpuid;
210 int r, size;
211
212 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
e42a92ae 213 cpuid = g_malloc0(size);
b827df58
AK		 214 cpuid->nent = max;
215 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
76ae317f
MM		 216 if (r == 0 && cpuid->nent >= max) {
217 r = -E2BIG;
218 }
b827df58
AK		 219 if (r < 0) {
220 if (r == -E2BIG) {
7267c094 221 g_free(cpuid);
b827df58
AK		 222 return NULL;
223 } else {
224 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
225 strerror(-r));
226 exit(1);
227 }
228 }
229 return cpuid;
230}
231
dd87f8a6
EH		 232/* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
233 * for all entries.
234 */
235static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
236{
237 struct kvm_cpuid2 *cpuid;
238 int max = 1;
494e95e9
CP		 239
240 if (cpuid_cache != NULL) {
241 return cpuid_cache;
242 }
dd87f8a6
EH		 243 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
244 max *= 2;
245 }
494e95e9 246 cpuid_cache = cpuid;
dd87f8a6
EH		 247 return cpuid;
248}
249
a443bc34 250static const struct kvm_para_features {
0c31b744
GC		 251 int cap;
252 int feature;
253} para_features[] = {
254 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
255 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
256 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
0c31b744 257 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
0c31b744
GC		 258};
259
ba9bc59e 260static int get_para_features(KVMState *s)
0c31b744
GC		 261{
262 int i, features = 0;
263
8e03c100 264 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
ba9bc59e 265 if (kvm_check_extension(s, para_features[i].cap)) {
0c31b744
GC		 266 features |= (1 << para_features[i].feature);
267 }
268 }
269
270 return features;
271}
0c31b744 272
40e80ee4
EH		 273static bool host_tsx_blacklisted(void)
274{
275 int family, model, stepping;\
276 char vendor[CPUID_VENDOR_SZ + 1];
277
278 host_vendor_fms(vendor, &family, &model, &stepping);
279
280 /* Check if we are running on a Haswell host known to have broken TSX */
281 return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
282 (family == 6) &&
283 ((model == 63 && stepping < 4) ||
284 model == 60 || model == 69 || model == 70);
285}
0c31b744 286
829ae2f9
EH		 287/* Returns the value for a specific register on the cpuid entry
288 */
289static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
290{
291 uint32_t ret = 0;
292 switch (reg) {
293 case R_EAX:
294 ret = entry->eax;
295 break;
296 case R_EBX:
297 ret = entry->ebx;
298 break;
299 case R_ECX:
300 ret = entry->ecx;
301 break;
302 case R_EDX:
303 ret = entry->edx;
304 break;
305 }
306 return ret;
307}
308
4fb73f1d
EH		 309/* Find matching entry for function/index on kvm_cpuid2 struct
310 */
311static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
312 uint32_t function,
313 uint32_t index)
314{
315 int i;
316 for (i = 0; i < cpuid->nent; ++i) {
317 if (cpuid->entries[i].function == function &&
318 cpuid->entries[i].index == index) {
319 return &cpuid->entries[i];
320 }
321 }
322 /* not found: */
323 return NULL;
324}
325
ba9bc59e 326uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
c958a8bd 327 uint32_t index, int reg)
b827df58
AK		 328{
329 struct kvm_cpuid2 *cpuid;
b827df58
AK		 330 uint32_t ret = 0;
331 uint32_t cpuid_1_edx;
8c723b79 332 bool found = false;
b827df58 333
dd87f8a6 334 cpuid = get_supported_cpuid(s);
b827df58 335
4fb73f1d
EH		 336 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
337 if (entry) {
338 found = true;
339 ret = cpuid_entry_get_reg(entry, reg);
b827df58
AK		 340 }
341
7b46e5ce
EH		 342 /* Fixups for the data returned by KVM, below */
343
c2acb022
EH		 344 if (function == 1 && reg == R_EDX) {
345 /* KVM before 2.6.30 misreports the following features */
346 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
84bd945c
EH		 347 } else if (function == 1 && reg == R_ECX) {
348 /* We can set the hypervisor flag, even if KVM does not return it on
349 * GET_SUPPORTED_CPUID
350 */
351 ret |= CPUID_EXT_HYPERVISOR;
ac67ee26
EH		 352 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
353 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
354 * and the irqchip is in the kernel.
355 */
356 if (kvm_irqchip_in_kernel() &&
357 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
358 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
359 }
41e5e76d
EH		 360
361 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
362 * without the in-kernel irqchip
363 */
364 if (!kvm_irqchip_in_kernel()) {
365 ret &= ~CPUID_EXT_X2APIC;
b827df58 366 }
28b8e4d0
JK		 367 } else if (function == 6 && reg == R_EAX) {
368 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
40e80ee4
EH		 369 } else if (function == 7 && index == 0 && reg == R_EBX) {
370 if (host_tsx_blacklisted()) {
371 ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
372 }
c2acb022
EH		 373 } else if (function == 0x80000001 && reg == R_EDX) {
374 /* On Intel, kvm returns cpuid according to the Intel spec,
375 * so add missing bits according to the AMD spec:
376 */
377 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
378 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
64877477
EH		 379 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
380 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
381 * be enabled without the in-kernel irqchip
382 */
383 if (!kvm_irqchip_in_kernel()) {
384 ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
385 }
be777326
WL		 386 } else if (function == KVM_CPUID_FEATURES && reg == R_EDX) {
387 ret |= KVM_HINTS_DEDICATED;
388 found = 1;
b827df58
AK		 389 }
390
0c31b744 391 /* fallback for older kernels */
8c723b79 392 if ((function == KVM_CPUID_FEATURES) && !found) {
ba9bc59e 393 ret = get_para_features(s);
b9bec74b 394 }
0c31b744
GC		 395
396 return ret;
bb0300dc 397}
bb0300dc 398
3c85e74f
HY		 399typedef struct HWPoisonPage {
400 ram_addr_t ram_addr;
401 QLIST_ENTRY(HWPoisonPage) list;
402} HWPoisonPage;
403
404static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
405 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
406
407static void kvm_unpoison_all(void *param)
408{
409 HWPoisonPage *page, *next_page;
410
411 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
412 QLIST_REMOVE(page, list);
413 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
7267c094 414 g_free(page);
3c85e74f
HY		 415 }
416}
417
3c85e74f
HY		 418static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
419{
420 HWPoisonPage *page;
421
422 QLIST_FOREACH(page, &hwpoison_page_list, list) {
423 if (page->ram_addr == ram_addr) {
424 return;
425 }
426 }
ab3ad07f 427 page = g_new(HWPoisonPage, 1);
3c85e74f
HY		 428 page->ram_addr = ram_addr;
429 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
430}
431
e7701825
MT		 432static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
433 int *max_banks)
434{
435 int r;
436
14a09518 437 r = kvm_check_extension(s, KVM_CAP_MCE);
e7701825
MT		 438 if (r > 0) {
439 *max_banks = r;
440 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
441 }
442 return -ENOSYS;
443}
444
bee615d4 445static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
e7701825 446{
87f8b626 447 CPUState *cs = CPU(cpu);
bee615d4 448 CPUX86State *env = &cpu->env;
c34d440a
JK		 449 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
450 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
451 uint64_t mcg_status = MCG_STATUS_MCIP;
87f8b626 452 int flags = 0;
e7701825 453
c34d440a
JK		 454 if (code == BUS_MCEERR_AR) {
455 status |= MCI_STATUS_AR | 0x134;
456 mcg_status |= MCG_STATUS_EIPV;
457 } else {
458 status |= 0xc0;
459 mcg_status |= MCG_STATUS_RIPV;
419fb20a 460 }
87f8b626
AR		 461
462 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
463 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
464 * guest kernel back into env->mcg_ext_ctl.
465 */
466 cpu_synchronize_state(cs);
467 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
468 mcg_status |= MCG_STATUS_LMCE;
469 flags = 0;
470 }
471
8c5cf3b6 472 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
87f8b626 473 (MCM_ADDR_PHYS << 6) | 0xc, flags);
419fb20a 474}
419fb20a
JK		 475
476static void hardware_memory_error(void)
477{
478 fprintf(stderr, "Hardware memory error!\n");
479 exit(1);
480}
481
2ae41db2 482void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
419fb20a 483{
20d695a9
AF		 484 X86CPU *cpu = X86_CPU(c);
485 CPUX86State *env = &cpu->env;
419fb20a 486 ram_addr_t ram_addr;
a8170e5e 487 hwaddr paddr;
419fb20a 488
4d39892c
PB		 489 /* If we get an action required MCE, it has been injected by KVM
490 * while the VM was running. An action optional MCE instead should
491 * be coming from the main thread, which qemu_init_sigbus identifies
492 * as the "early kill" thread.
493 */
a16fc07e 494 assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
20e0ff59 495
20e0ff59 496 if ((env->mcg_cap & MCG_SER_P) && addr) {
07bdaa41 497 ram_addr = qemu_ram_addr_from_host(addr);
20e0ff59
PB		 498 if (ram_addr != RAM_ADDR_INVALID &&
499 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
500 kvm_hwpoison_page_add(ram_addr);
501 kvm_mce_inject(cpu, paddr, code);
2ae41db2 502 return;
419fb20a 503 }
20e0ff59
PB		 504
505 fprintf(stderr, "Hardware memory error for memory used by "
506 "QEMU itself instead of guest system!\n");
419fb20a 507 }
20e0ff59
PB		 508
509 if (code == BUS_MCEERR_AR) {
510 hardware_memory_error();
511 }
512
513 /* Hope we are lucky for AO MCE */
419fb20a
JK		 514}
515
1bc22652 516static int kvm_inject_mce_oldstyle(X86CPU *cpu)
ab443475 517{
1bc22652
AF		 518 CPUX86State *env = &cpu->env;
519
ab443475
JK		 520 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
521 unsigned int bank, bank_num = env->mcg_cap & 0xff;
522 struct kvm_x86_mce mce;
523
524 env->exception_injected = -1;
525
526 /*
527 * There must be at least one bank in use if an MCE is pending.
528 * Find it and use its values for the event injection.
529 */
530 for (bank = 0; bank < bank_num; bank++) {
531 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
532 break;
533 }
534 }
535 assert(bank < bank_num);
536
537 mce.bank = bank;
538 mce.status = env->mce_banks[bank * 4 + 1];
539 mce.mcg_status = env->mcg_status;
540 mce.addr = env->mce_banks[bank * 4 + 2];
541 mce.misc = env->mce_banks[bank * 4 + 3];
542
1bc22652 543 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
ab443475 544 }
ab443475
JK		 545 return 0;
546}
547
1dfb4dd9 548static void cpu_update_state(void *opaque, int running, RunState state)
b8cc45d6 549{
317ac620 550 CPUX86State *env = opaque;
b8cc45d6
GC		 551
552 if (running) {
553 env->tsc_valid = false;
554 }
555}
556
83b17af5 557unsigned long kvm_arch_vcpu_id(CPUState *cs)
b164e48e 558{
83b17af5 559 X86CPU *cpu = X86_CPU(cs);
7e72a45c 560 return cpu->apic_id;
b164e48e
EH		 561}
562
92067bf4
IM		 563#ifndef KVM_CPUID_SIGNATURE_NEXT
564#define KVM_CPUID_SIGNATURE_NEXT 0x40000100
565#endif
566
567static bool hyperv_hypercall_available(X86CPU *cpu)
568{
569 return cpu->hyperv_vapic ||
570 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
571}
572
573static bool hyperv_enabled(X86CPU *cpu)
574{
7bc3d711
PB		 575 CPUState *cs = CPU(cpu);
576 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
577 (hyperv_hypercall_available(cpu) ||
48a5f3bc 578 cpu->hyperv_time ||
f2a53c9e 579 cpu->hyperv_relaxed_timing ||
744b8a94 580 cpu->hyperv_crash ||
8c145d7c 581 cpu->hyperv_reset ||
46eb8f98 582 cpu->hyperv_vpindex ||
866eea9a 583 cpu->hyperv_runtime ||
ff99aa64
AS		 584 cpu->hyperv_synic ||
585 cpu->hyperv_stimer);
92067bf4
IM		 586}
587
5031283d
HZ		 588static int kvm_arch_set_tsc_khz(CPUState *cs)
589{
590 X86CPU *cpu = X86_CPU(cs);
591 CPUX86State *env = &cpu->env;
592 int r;
593
594 if (!env->tsc_khz) {
595 return 0;
596 }
597
598 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
599 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
600 -ENOTSUP;
601 if (r < 0) {
602 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
603 * TSC frequency doesn't match the one we want.
604 */
605 int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
606 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
607 -ENOTSUP;
608 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
3dc6f869
AF		 609 warn_report("TSC frequency mismatch between "
610 "VM (%" PRId64 " kHz) and host (%d kHz), "
611 "and TSC scaling unavailable",
612 env->tsc_khz, cur_freq);
5031283d
HZ		 613 return r;
614 }
615 }
616
617 return 0;
618}
619
4bb95b82
LP		 620static bool tsc_is_stable_and_known(CPUX86State *env)
621{
622 if (!env->tsc_khz) {
623 return false;
624 }
625 return (env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
626 || env->user_tsc_khz;
627}
628
c35bd19a
EY		 629static int hyperv_handle_properties(CPUState *cs)
630{
631 X86CPU *cpu = X86_CPU(cs);
632 CPUX86State *env = &cpu->env;
633
3ddcd2ed
EH		 634 if (cpu->hyperv_time &&
635 kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) <= 0) {
636 cpu->hyperv_time = false;
637 }
638
c35bd19a 639 if (cpu->hyperv_relaxed_timing) {
5e953812 640 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
c35bd19a
EY		 641 }
642 if (cpu->hyperv_vapic) {
5e953812
RK		 643 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
644 env->features[FEAT_HYPERV_EAX] |= HV_APIC_ACCESS_AVAILABLE;
c35bd19a 645 }
3ddcd2ed 646 if (cpu->hyperv_time) {
5e953812
RK		 647 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
648 env->features[FEAT_HYPERV_EAX] |= HV_TIME_REF_COUNT_AVAILABLE;
649 env->features[FEAT_HYPERV_EAX] |= HV_REFERENCE_TSC_AVAILABLE;
d72bc7f6
LP		 650
651 if (has_msr_hv_frequencies && tsc_is_stable_and_known(env)) {
5e953812
RK		 652 env->features[FEAT_HYPERV_EAX] |= HV_ACCESS_FREQUENCY_MSRS;
653 env->features[FEAT_HYPERV_EDX] |= HV_FREQUENCY_MSRS_AVAILABLE;
d72bc7f6 654 }
c35bd19a
EY		 655 }
656 if (cpu->hyperv_crash && has_msr_hv_crash) {
5e953812 657 env->features[FEAT_HYPERV_EDX] |= HV_GUEST_CRASH_MSR_AVAILABLE;
c35bd19a 658 }
5e953812 659 env->features[FEAT_HYPERV_EDX] |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
c35bd19a 660 if (cpu->hyperv_reset && has_msr_hv_reset) {
5e953812 661 env->features[FEAT_HYPERV_EAX] |= HV_RESET_AVAILABLE;
c35bd19a
EY		 662 }
663 if (cpu->hyperv_vpindex && has_msr_hv_vpindex) {
5e953812 664 env->features[FEAT_HYPERV_EAX] |= HV_VP_INDEX_AVAILABLE;
c35bd19a
EY		 665 }
666 if (cpu->hyperv_runtime && has_msr_hv_runtime) {
5e953812 667 env->features[FEAT_HYPERV_EAX] |= HV_VP_RUNTIME_AVAILABLE;
c35bd19a
EY		 668 }
669 if (cpu->hyperv_synic) {
c35bd19a
EY		 670 if (!has_msr_hv_synic ||
671 kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_SYNIC, 0)) {
672 fprintf(stderr, "Hyper-V SynIC is not supported by kernel\n");
673 return -ENOSYS;
674 }
675
5e953812 676 env->features[FEAT_HYPERV_EAX] |= HV_SYNIC_AVAILABLE;
c35bd19a
EY		 677 }
678 if (cpu->hyperv_stimer) {
679 if (!has_msr_hv_stimer) {
680 fprintf(stderr, "Hyper-V timers aren't supported by kernel\n");
681 return -ENOSYS;
682 }
5e953812 683 env->features[FEAT_HYPERV_EAX] |= HV_SYNTIMERS_AVAILABLE;
c35bd19a
EY		 684 }
685 return 0;
686}
687
68bfd0ad
MT		 688static Error *invtsc_mig_blocker;
689
f8bb0565 690#define KVM_MAX_CPUID_ENTRIES 100
0893d460 691
20d695a9 692int kvm_arch_init_vcpu(CPUState *cs)
05330448
AL		 693{
694 struct {
486bd5a2 695 struct kvm_cpuid2 cpuid;
f8bb0565 696 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
541dc0d4 697 } QEMU_PACKED cpuid_data;
20d695a9
AF		 698 X86CPU *cpu = X86_CPU(cs);
699 CPUX86State *env = &cpu->env;
486bd5a2 700 uint32_t limit, i, j, cpuid_i;
a33609ca 701 uint32_t unused;
bb0300dc 702 struct kvm_cpuid_entry2 *c;
bb0300dc 703 uint32_t signature[3];
234cc647 704 int kvm_base = KVM_CPUID_SIGNATURE;
e7429073 705 int r;
fe44dc91 706 Error *local_err = NULL;
05330448 707
ef4cbe14
SW		 708 memset(&cpuid_data, 0, sizeof(cpuid_data));
709
05330448
AL		 710 cpuid_i = 0;
711
ddb98b5a
LP		 712 r = kvm_arch_set_tsc_khz(cs);
713 if (r < 0) {
714 goto fail;
715 }
716
717 /* vcpu's TSC frequency is either specified by user, or following
718 * the value used by KVM if the former is not present. In the
719 * latter case, we query it from KVM and record in env->tsc_khz,
720 * so that vcpu's TSC frequency can be migrated later via this field.
721 */
722 if (!env->tsc_khz) {
723 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
724 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
725 -ENOTSUP;
726 if (r > 0) {
727 env->tsc_khz = r;
728 }
729 }
730
bb0300dc 731 /* Paravirtualization CPUIDs */
234cc647
PB		 732 if (hyperv_enabled(cpu)) {
733 c = &cpuid_data.entries[cpuid_i++];
5e953812 734 c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
1c4a55db
AW		 735 if (!cpu->hyperv_vendor_id) {
736 memcpy(signature, "Microsoft Hv", 12);
737 } else {
738 size_t len = strlen(cpu->hyperv_vendor_id);
739
740 if (len > 12) {
741 error_report("hv-vendor-id truncated to 12 characters");
742 len = 12;
743 }
744 memset(signature, 0, 12);
745 memcpy(signature, cpu->hyperv_vendor_id, len);
746 }
5e953812 747 c->eax = HV_CPUID_MIN;
234cc647
PB		 748 c->ebx = signature[0];
749 c->ecx = signature[1];
750 c->edx = signature[2];
0c31b744 751
234cc647 752 c = &cpuid_data.entries[cpuid_i++];
5e953812 753 c->function = HV_CPUID_INTERFACE;
eab70139
VR		 754 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
755 c->eax = signature[0];
234cc647
PB		 756 c->ebx = 0;
757 c->ecx = 0;
758 c->edx = 0;
eab70139
VR		 759
760 c = &cpuid_data.entries[cpuid_i++];
5e953812 761 c->function = HV_CPUID_VERSION;
eab70139
VR		 762 c->eax = 0x00001bbc;
763 c->ebx = 0x00060001;
764
765 c = &cpuid_data.entries[cpuid_i++];
5e953812 766 c->function = HV_CPUID_FEATURES;
c35bd19a
EY		 767 r = hyperv_handle_properties(cs);
768 if (r) {
769 return r;
46eb8f98 770 }
c35bd19a
EY		 771 c->eax = env->features[FEAT_HYPERV_EAX];
772 c->ebx = env->features[FEAT_HYPERV_EBX];
773 c->edx = env->features[FEAT_HYPERV_EDX];
866eea9a 774
eab70139 775 c = &cpuid_data.entries[cpuid_i++];
5e953812 776 c->function = HV_CPUID_ENLIGHTMENT_INFO;
92067bf4 777 if (cpu->hyperv_relaxed_timing) {
5e953812 778 c->eax |= HV_RELAXED_TIMING_RECOMMENDED;
eab70139 779 }
2d5aa872 780 if (cpu->hyperv_vapic) {
5e953812 781 c->eax |= HV_APIC_ACCESS_RECOMMENDED;
eab70139 782 }
92067bf4 783 c->ebx = cpu->hyperv_spinlock_attempts;
eab70139
VR		 784
785 c = &cpuid_data.entries[cpuid_i++];
5e953812 786 c->function = HV_CPUID_IMPLEMENT_LIMITS;
6c69dfb6
GA		 787
788 c->eax = cpu->hv_max_vps;
eab70139
VR		 789 c->ebx = 0x40;
790
234cc647 791 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
7bc3d711 792 has_msr_hv_hypercall = true;
eab70139
VR		 793 }
794
f522d2ac
AW		 795 if (cpu->expose_kvm) {
796 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
797 c = &cpuid_data.entries[cpuid_i++];
798 c->function = KVM_CPUID_SIGNATURE | kvm_base;
79b6f2f6 799 c->eax = KVM_CPUID_FEATURES | kvm_base;
f522d2ac
AW		 800 c->ebx = signature[0];
801 c->ecx = signature[1];
802 c->edx = signature[2];
234cc647 803
f522d2ac
AW		 804 c = &cpuid_data.entries[cpuid_i++];
805 c->function = KVM_CPUID_FEATURES | kvm_base;
806 c->eax = env->features[FEAT_KVM];
be777326 807 c->edx = env->features[FEAT_KVM_HINTS];
f522d2ac 808 }
917367aa 809
a33609ca 810 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
05330448
AL		 811
812 for (i = 0; i <= limit; i++) {
f8bb0565
IM		 813 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
814 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
815 abort();
816 }
bb0300dc 817 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 818
819 switch (i) {
a36b1029
AL		 820 case 2: {
821 /* Keep reading function 2 till all the input is received */
822 int times;
823
a36b1029 824 c->function = i;
a33609ca
AL		 825 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
826 KVM_CPUID_FLAG_STATE_READ_NEXT;
827 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
828 times = c->eax & 0xff;
a36b1029
AL		 829
830 for (j = 1; j < times; ++j) {
f8bb0565
IM		 831 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
832 fprintf(stderr, "cpuid_data is full, no space for "
833 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
834 abort();
835 }
a33609ca 836 c = &cpuid_data.entries[cpuid_i++];
a36b1029 837 c->function = i;
a33609ca
AL		 838 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
839 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
a36b1029
AL		 840 }
841 break;
842 }
486bd5a2
AL		 843 case 4:
844 case 0xb:
845 case 0xd:
846 for (j = 0; ; j++) {
31e8c696
AP		 847 if (i == 0xd && j == 64) {
848 break;
849 }
486bd5a2
AL		 850 c->function = i;
851 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
852 c->index = j;
a33609ca 853 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2 854
b9bec74b 855 if (i == 4 && c->eax == 0) {
486bd5a2 856 break;
b9bec74b
JK		 857 }
858 if (i == 0xb && !(c->ecx & 0xff00)) {
486bd5a2 859 break;
b9bec74b
JK		 860 }
861 if (i == 0xd && c->eax == 0) {
31e8c696 862 continue;
b9bec74b 863 }
f8bb0565
IM		 864 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
865 fprintf(stderr, "cpuid_data is full, no space for "
866 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
867 abort();
868 }
a33609ca 869 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 870 }
871 break;
e37a5c7f
CP		 872 case 0x14: {
873 uint32_t times;
874
875 c->function = i;
876 c->index = 0;
877 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
878 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
879 times = c->eax;
880
881 for (j = 1; j <= times; ++j) {
882 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
883 fprintf(stderr, "cpuid_data is full, no space for "
884 "cpuid(eax:0x14,ecx:0x%x)\n", j);
885 abort();
886 }
887 c = &cpuid_data.entries[cpuid_i++];
888 c->function = i;
889 c->index = j;
890 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
891 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
892 }
893 break;
894 }
486bd5a2 895 default:
486bd5a2 896 c->function = i;
a33609ca
AL		 897 c->flags = 0;
898 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2
AL		 899 break;
900 }
05330448 901 }
0d894367
PB		 902
903 if (limit >= 0x0a) {
0b368a10 904 uint32_t eax, edx;
0d894367 905
0b368a10
JD		 906 cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx);
907
908 has_architectural_pmu_version = eax & 0xff;
909 if (has_architectural_pmu_version > 0) {
910 num_architectural_pmu_gp_counters = (eax & 0xff00) >> 8;
0d894367
PB		 911
912 /* Shouldn't be more than 32, since that's the number of bits
913 * available in EBX to tell us _which_ counters are available.
914 * Play it safe.
915 */
0b368a10
JD		 916 if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) {
917 num_architectural_pmu_gp_counters = MAX_GP_COUNTERS;
918 }
919
920 if (has_architectural_pmu_version > 1) {
921 num_architectural_pmu_fixed_counters = edx & 0x1f;
922
923 if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNTERS) {
924 num_architectural_pmu_fixed_counters = MAX_FIXED_COUNTERS;
925 }
0d894367
PB		 926 }
927 }
928 }
929
a33609ca 930 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
05330448
AL		 931
932 for (i = 0x80000000; i <= limit; i++) {
f8bb0565
IM		 933 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
934 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
935 abort();
936 }
bb0300dc 937 c = &cpuid_data.entries[cpuid_i++];
05330448 938
05330448 939 c->function = i;
a33609ca
AL		 940 c->flags = 0;
941 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
05330448
AL		 942 }
943
b3baa152
BW		 944 /* Call Centaur's CPUID instructions they are supported. */
945 if (env->cpuid_xlevel2 > 0) {
b3baa152
BW		 946 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
947
948 for (i = 0xC0000000; i <= limit; i++) {
f8bb0565
IM		 949 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
950 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
951 abort();
952 }
b3baa152
BW		 953 c = &cpuid_data.entries[cpuid_i++];
954
955 c->function = i;
956 c->flags = 0;
957 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
958 }
959 }
960
05330448
AL		 961 cpuid_data.cpuid.nent = cpuid_i;
962
e7701825 963 if (((env->cpuid_version >> 8)&0xF) >= 6
0514ef2f 964 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
fc7a504c 965 (CPUID_MCE | CPUID_MCA)
a60f24b5 966 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
5120901a 967 uint64_t mcg_cap, unsupported_caps;
e7701825 968 int banks;
32a42024 969 int ret;
e7701825 970
a60f24b5 971 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
75d49497
JK		 972 if (ret < 0) {
973 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
974 return ret;
e7701825 975 }
75d49497 976
2590f15b 977 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
49b69cbf 978 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
2590f15b 979 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
49b69cbf 980 return -ENOTSUP;
75d49497 981 }
49b69cbf 982
5120901a
EH		 983 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
984 if (unsupported_caps) {
87f8b626
AR		 985 if (unsupported_caps & MCG_LMCE_P) {
986 error_report("kvm: LMCE not supported");
987 return -ENOTSUP;
988 }
3dc6f869
AF		 989 warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64,
990 unsupported_caps);
5120901a
EH		 991 }
992
2590f15b
EH		 993 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
994 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
75d49497
JK		 995 if (ret < 0) {
996 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
997 return ret;
998 }
e7701825 999 }
e7701825 1000
b8cc45d6
GC		 1001 qemu_add_vm_change_state_handler(cpu_update_state, env);
1002
df67696e
LJ		 1003 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
1004 if (c) {
1005 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
1006 !!(c->ecx & CPUID_EXT_SMX);
1007 }
1008
87f8b626
AR		 1009 if (env->mcg_cap & MCG_LMCE_P) {
1010 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
1011 }
1012
d99569d9
EH		 1013 if (!env->user_tsc_khz) {
1014 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
1015 invtsc_mig_blocker == NULL) {
1016 /* for migration */
1017 error_setg(&invtsc_mig_blocker,
1018 "State blocked by non-migratable CPU device"
1019 " (invtsc flag)");
fe44dc91
AA		 1020 r = migrate_add_blocker(invtsc_mig_blocker, &local_err);
1021 if (local_err) {
1022 error_report_err(local_err);
1023 error_free(invtsc_mig_blocker);
1024 goto fail;
1025 }
d99569d9
EH		 1026 /* for savevm */
1027 vmstate_x86_cpu.unmigratable = 1;
1028 }
68bfd0ad
MT		 1029 }
1030
9954a158
PDJ		 1031 if (cpu->vmware_cpuid_freq
1032 /* Guests depend on 0x40000000 to detect this feature, so only expose
1033 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
1034 && cpu->expose_kvm
1035 && kvm_base == KVM_CPUID_SIGNATURE
1036 /* TSC clock must be stable and known for this feature. */
4bb95b82 1037 && tsc_is_stable_and_known(env)) {
9954a158
PDJ		 1038
1039 c = &cpuid_data.entries[cpuid_i++];
1040 c->function = KVM_CPUID_SIGNATURE | 0x10;
1041 c->eax = env->tsc_khz;
1042 /* LAPIC resolution of 1ns (freq: 1GHz) is hardcoded in KVM's
1043 * APIC_BUS_CYCLE_NS */
1044 c->ebx = 1000000;
1045 c->ecx = c->edx = 0;
1046
1047 c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
1048 c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
1049 }
1050
1051 cpuid_data.cpuid.nent = cpuid_i;
1052
1053 cpuid_data.cpuid.padding = 0;
1054 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
1055 if (r) {
1056 goto fail;
1057 }
1058
28143b40 1059 if (has_xsave) {
fabacc0f
JK		 1060 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
1061 }
d71b62a1 1062 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
fabacc0f 1063
273c515c
PB		 1064 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
1065 has_msr_tsc_aux = false;
1066 }
d1ae67f6 1067
e7429073 1068 return 0;
fe44dc91
AA		 1069
1070 fail:
1071 migrate_del_blocker(invtsc_mig_blocker);
1072 return r;
05330448
AL		 1073}
1074
50a2c6e5 1075void kvm_arch_reset_vcpu(X86CPU *cpu)
caa5af0f 1076{
20d695a9 1077 CPUX86State *env = &cpu->env;
dd673288 1078
1a5e9d2f 1079 env->xcr0 = 1;
ddced198 1080 if (kvm_irqchip_in_kernel()) {
dd673288 1081 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
ddced198
MT		 1082 KVM_MP_STATE_UNINITIALIZED;
1083 } else {
1084 env->mp_state = KVM_MP_STATE_RUNNABLE;
1085 }
689141dd
RK		 1086
1087 if (cpu->hyperv_synic) {
1088 int i;
1089 for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) {
1090 env->msr_hv_synic_sint[i] = HV_SINT_MASKED;
1091 }
1092 }
caa5af0f
JK		 1093}
1094
e0723c45
PB		 1095void kvm_arch_do_init_vcpu(X86CPU *cpu)
1096{
1097 CPUX86State *env = &cpu->env;
1098
1099 /* APs get directly into wait-for-SIPI state. */
1100 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
1101 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
1102 }
1103}
1104
c3a3a7d3 1105static int kvm_get_supported_msrs(KVMState *s)
05330448 1106{
75b10c43 1107 static int kvm_supported_msrs;
c3a3a7d3 1108 int ret = 0;
05330448
AL		 1109
1110 /* first time */
75b10c43 1111 if (kvm_supported_msrs == 0) {
05330448
AL		 1112 struct kvm_msr_list msr_list, *kvm_msr_list;
1113
75b10c43 1114 kvm_supported_msrs = -1;
05330448
AL		 1115
1116 /* Obtain MSR list from KVM. These are the MSRs that we must
1117 * save/restore */
4c9f7372 1118 msr_list.nmsrs = 0;
c3a3a7d3 1119 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
6fb6d245 1120 if (ret < 0 && ret != -E2BIG) {
c3a3a7d3 1121 return ret;
6fb6d245 1122 }
d9db889f
JK		 1123 /* Old kernel modules had a bug and could write beyond the provided
1124 memory. Allocate at least a safe amount of 1K. */
7267c094 1125 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
d9db889f
JK		 1126 msr_list.nmsrs *
1127 sizeof(msr_list.indices[0])));
05330448 1128
55308450 1129 kvm_msr_list->nmsrs = msr_list.nmsrs;
c3a3a7d3 1130 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
05330448
AL		 1131 if (ret >= 0) {
1132 int i;
1133
1134 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
1d268dec
LP		 1135 switch (kvm_msr_list->indices[i]) {
1136 case MSR_STAR:
c3a3a7d3 1137 has_msr_star = true;
1d268dec
LP		 1138 break;
1139 case MSR_VM_HSAVE_PA:
c3a3a7d3 1140 has_msr_hsave_pa = true;
1d268dec
LP		 1141 break;
1142 case MSR_TSC_AUX:
c9b8f6b6 1143 has_msr_tsc_aux = true;
1d268dec
LP		 1144 break;
1145 case MSR_TSC_ADJUST:
f28558d3 1146 has_msr_tsc_adjust = true;
1d268dec
LP		 1147 break;
1148 case MSR_IA32_TSCDEADLINE:
aa82ba54 1149 has_msr_tsc_deadline = true;
1d268dec
LP		 1150 break;
1151 case MSR_IA32_SMBASE:
fc12d72e 1152 has_msr_smbase = true;
1d268dec
LP		 1153 break;
1154 case MSR_IA32_MISC_ENABLE:
21e87c46 1155 has_msr_misc_enable = true;
1d268dec
LP		 1156 break;
1157 case MSR_IA32_BNDCFGS:
79e9ebeb 1158 has_msr_bndcfgs = true;
1d268dec
LP		 1159 break;
1160 case MSR_IA32_XSS:
18cd2c17 1161 has_msr_xss = true;
3c254ab8 1162 break;
1d268dec 1163 case HV_X64_MSR_CRASH_CTL:
f2a53c9e 1164 has_msr_hv_crash = true;
1d268dec
LP		 1165 break;
1166 case HV_X64_MSR_RESET:
744b8a94 1167 has_msr_hv_reset = true;
1d268dec
LP		 1168 break;
1169 case HV_X64_MSR_VP_INDEX:
8c145d7c 1170 has_msr_hv_vpindex = true;
1d268dec
LP		 1171 break;
1172 case HV_X64_MSR_VP_RUNTIME:
46eb8f98 1173 has_msr_hv_runtime = true;
1d268dec
LP		 1174 break;
1175 case HV_X64_MSR_SCONTROL:
866eea9a 1176 has_msr_hv_synic = true;
1d268dec
LP		 1177 break;
1178 case HV_X64_MSR_STIMER0_CONFIG:
ff99aa64 1179 has_msr_hv_stimer = true;
1d268dec 1180 break;
d72bc7f6
LP		 1181 case HV_X64_MSR_TSC_FREQUENCY:
1182 has_msr_hv_frequencies = true;
1183 break;
a33a2cfe
PB		 1184 case MSR_IA32_SPEC_CTRL:
1185 has_msr_spec_ctrl = true;
1186 break;
ff99aa64 1187 }
05330448
AL		 1188 }
1189 }
1190
7267c094 1191 g_free(kvm_msr_list);
05330448
AL		 1192 }
1193
c3a3a7d3 1194 return ret;
05330448
AL		 1195}
1196
6410848b
PB		 1197static Notifier smram_machine_done;
1198static KVMMemoryListener smram_listener;
1199static AddressSpace smram_address_space;
1200static MemoryRegion smram_as_root;
1201static MemoryRegion smram_as_mem;
1202
1203static void register_smram_listener(Notifier *n, void *unused)
1204{
1205 MemoryRegion *smram =
1206 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1207
1208 /* Outer container... */
1209 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1210 memory_region_set_enabled(&smram_as_root, true);
1211
1212 /* ... with two regions inside: normal system memory with low
1213 * priority, and...
1214 */
1215 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1216 get_system_memory(), 0, ~0ull);
1217 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1218 memory_region_set_enabled(&smram_as_mem, true);
1219
1220 if (smram) {
1221 /* ... SMRAM with higher priority */
1222 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1223 memory_region_set_enabled(smram, true);
1224 }
1225
1226 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1227 kvm_memory_listener_register(kvm_state, &smram_listener,
1228 &smram_address_space, 1);
1229}
1230
b16565b3 1231int kvm_arch_init(MachineState *ms, KVMState *s)
20420430 1232{
11076198 1233 uint64_t identity_base = 0xfffbc000;
39d6960a 1234 uint64_t shadow_mem;
20420430 1235 int ret;
25d2e361 1236 struct utsname utsname;
20420430 1237
28143b40
TH		 1238#ifdef KVM_CAP_XSAVE
1239 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
1240#endif
1241
1242#ifdef KVM_CAP_XCRS
1243 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
1244#endif
1245
1246#ifdef KVM_CAP_PIT_STATE2
1247 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
1248#endif
1249
c3a3a7d3 1250 ret = kvm_get_supported_msrs(s);
20420430 1251 if (ret < 0) {
20420430
SY		 1252 return ret;
1253 }
25d2e361
MT		 1254
1255 uname(&utsname);
1256 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1257
4c5b10b7 1258 /*
11076198
JK		 1259 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1260 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
1261 * Since these must be part of guest physical memory, we need to allocate
1262 * them, both by setting their start addresses in the kernel and by
1263 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1264 *
1265 * Older KVM versions may not support setting the identity map base. In
1266 * that case we need to stick with the default, i.e. a 256K maximum BIOS
1267 * size.
4c5b10b7 1268 */
11076198
JK		 1269 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1270 /* Allows up to 16M BIOSes. */
1271 identity_base = 0xfeffc000;
1272
1273 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1274 if (ret < 0) {
1275 return ret;
1276 }
4c5b10b7 1277 }
e56ff191 1278
11076198
JK		 1279 /* Set TSS base one page after EPT identity map. */
1280 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
20420430
SY		 1281 if (ret < 0) {
1282 return ret;
1283 }
1284
11076198
JK		 1285 /* Tell fw_cfg to notify the BIOS to reserve the range. */
1286 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
20420430 1287 if (ret < 0) {
11076198 1288 fprintf(stderr, "e820_add_entry() table is full\n");
20420430
SY		 1289 return ret;
1290 }
3c85e74f 1291 qemu_register_reset(kvm_unpoison_all, NULL);
20420430 1292
4689b77b 1293 shadow_mem = machine_kvm_shadow_mem(ms);
36ad0e94
MA		 1294 if (shadow_mem != -1) {
1295 shadow_mem /= 4096;
1296 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1297 if (ret < 0) {
1298 return ret;
39d6960a
JK		 1299 }
1300 }
6410848b 1301
d870cfde
GA		 1302 if (kvm_check_extension(s, KVM_CAP_X86_SMM) &&
1303 object_dynamic_cast(OBJECT(ms), TYPE_PC_MACHINE) &&
1304 pc_machine_is_smm_enabled(PC_MACHINE(ms))) {
6410848b
PB		 1305 smram_machine_done.notify = register_smram_listener;
1306 qemu_add_machine_init_done_notifier(&smram_machine_done);
1307 }
11076198 1308 return 0;
05330448 1309}
b9bec74b 1310
05330448
AL		 1311static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1312{
1313 lhs->selector = rhs->selector;
1314 lhs->base = rhs->base;
1315 lhs->limit = rhs->limit;
1316 lhs->type = 3;
1317 lhs->present = 1;
1318 lhs->dpl = 3;
1319 lhs->db = 0;
1320 lhs->s = 1;
1321 lhs->l = 0;
1322 lhs->g = 0;
1323 lhs->avl = 0;
1324 lhs->unusable = 0;
1325}
1326
1327static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1328{
1329 unsigned flags = rhs->flags;
1330 lhs->selector = rhs->selector;
1331 lhs->base = rhs->base;
1332 lhs->limit = rhs->limit;
1333 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
1334 lhs->present = (flags & DESC_P_MASK) != 0;
acaa7550 1335 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
05330448
AL		 1336 lhs->db = (flags >> DESC_B_SHIFT) & 1;
1337 lhs->s = (flags & DESC_S_MASK) != 0;
1338 lhs->l = (flags >> DESC_L_SHIFT) & 1;
1339 lhs->g = (flags & DESC_G_MASK) != 0;
1340 lhs->avl = (flags & DESC_AVL_MASK) != 0;
4cae9c97 1341 lhs->unusable = !lhs->present;
7e680753 1342 lhs->padding = 0;
05330448
AL		 1343}
1344
1345static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
1346{
1347 lhs->selector = rhs->selector;
1348 lhs->base = rhs->base;
1349 lhs->limit = rhs->limit;
d45fc087
RP		 1350 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
1351 ((rhs->present && !rhs->unusable) * DESC_P_MASK) |
1352 (rhs->dpl << DESC_DPL_SHIFT) |
1353 (rhs->db << DESC_B_SHIFT) |
1354 (rhs->s * DESC_S_MASK) |
1355 (rhs->l << DESC_L_SHIFT) |
1356 (rhs->g * DESC_G_MASK) |
1357 (rhs->avl * DESC_AVL_MASK);
05330448
AL		 1358}
1359
1360static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
1361{
b9bec74b 1362 if (set) {
05330448 1363 *kvm_reg = *qemu_reg;
b9bec74b 1364 } else {
05330448 1365 *qemu_reg = *kvm_reg;
b9bec74b 1366 }
05330448
AL		 1367}
1368
1bc22652 1369static int kvm_getput_regs(X86CPU *cpu, int set)
05330448 1370{
1bc22652 1371 CPUX86State *env = &cpu->env;
05330448
AL		 1372 struct kvm_regs regs;
1373 int ret = 0;
1374
1375 if (!set) {
1bc22652 1376 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
b9bec74b 1377 if (ret < 0) {
05330448 1378 return ret;
b9bec74b 1379 }
05330448
AL		 1380 }
1381
1382 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
1383 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
1384 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
1385 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
1386 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
1387 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
1388 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
1389 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
1390#ifdef TARGET_X86_64
1391 kvm_getput_reg(&regs.r8, &env->regs[8], set);
1392 kvm_getput_reg(&regs.r9, &env->regs[9], set);
1393 kvm_getput_reg(&regs.r10, &env->regs[10], set);
1394 kvm_getput_reg(&regs.r11, &env->regs[11], set);
1395 kvm_getput_reg(&regs.r12, &env->regs[12], set);
1396 kvm_getput_reg(&regs.r13, &env->regs[13], set);
1397 kvm_getput_reg(&regs.r14, &env->regs[14], set);
1398 kvm_getput_reg(&regs.r15, &env->regs[15], set);
1399#endif
1400
1401 kvm_getput_reg(&regs.rflags, &env->eflags, set);
1402 kvm_getput_reg(&regs.rip, &env->eip, set);
1403
b9bec74b 1404 if (set) {
1bc22652 1405 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
b9bec74b 1406 }
05330448
AL		 1407
1408 return ret;
1409}
1410
1bc22652 1411static int kvm_put_fpu(X86CPU *cpu)
05330448 1412{
1bc22652 1413 CPUX86State *env = &cpu->env;
05330448
AL		 1414 struct kvm_fpu fpu;
1415 int i;
1416
1417 memset(&fpu, 0, sizeof fpu);
1418 fpu.fsw = env->fpus & ~(7 << 11);
1419 fpu.fsw |= (env->fpstt & 7) << 11;
1420 fpu.fcw = env->fpuc;
42cc8fa6
JK		 1421 fpu.last_opcode = env->fpop;
1422 fpu.last_ip = env->fpip;
1423 fpu.last_dp = env->fpdp;
b9bec74b
JK		 1424 for (i = 0; i < 8; ++i) {
1425 fpu.ftwx |= (!env->fptags[i]) << i;
1426 }
05330448 1427 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
bee81887 1428 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 1429 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
1430 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
bee81887 1431 }
05330448
AL		 1432 fpu.mxcsr = env->mxcsr;
1433
1bc22652 1434 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
05330448
AL		 1435}
1436
6b42494b
JK		 1437#define XSAVE_FCW_FSW 0
1438#define XSAVE_FTW_FOP 1
f1665b21
SY		 1439#define XSAVE_CWD_RIP 2
1440#define XSAVE_CWD_RDP 4
1441#define XSAVE_MXCSR 6
1442#define XSAVE_ST_SPACE 8
1443#define XSAVE_XMM_SPACE 40
1444#define XSAVE_XSTATE_BV 128
1445#define XSAVE_YMMH_SPACE 144
79e9ebeb
LJ		 1446#define XSAVE_BNDREGS 240
1447#define XSAVE_BNDCSR 256
9aecd6f8
CP		 1448#define XSAVE_OPMASK 272
1449#define XSAVE_ZMM_Hi256 288
1450#define XSAVE_Hi16_ZMM 416
f74eefe0 1451#define XSAVE_PKRU 672
f1665b21 1452
b503717d
EH		 1453#define XSAVE_BYTE_OFFSET(word_offset) \
1454 ((word_offset) * sizeof(((struct kvm_xsave *)0)->region[0]))
1455
1456#define ASSERT_OFFSET(word_offset, field) \
1457 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
1458 offsetof(X86XSaveArea, field))
1459
1460ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
1461ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
1462ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
1463ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
1464ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
1465ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
1466ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
1467ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
1468ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
1469ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
1470ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
1471ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
1472ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
1473ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
1474ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
1475
1bc22652 1476static int kvm_put_xsave(X86CPU *cpu)
f1665b21 1477{
1bc22652 1478 CPUX86State *env = &cpu->env;
86cd2ea0 1479 X86XSaveArea *xsave = env->kvm_xsave_buf;
f1665b21 1480
28143b40 1481 if (!has_xsave) {
1bc22652 1482 return kvm_put_fpu(cpu);
b9bec74b 1483 }
86a57621 1484 x86_cpu_xsave_all_areas(cpu, xsave);
f1665b21 1485
9be38598 1486 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
f1665b21
SY		 1487}
1488
1bc22652 1489static int kvm_put_xcrs(X86CPU *cpu)
f1665b21 1490{
1bc22652 1491 CPUX86State *env = &cpu->env;
bdfc8480 1492 struct kvm_xcrs xcrs = {};
f1665b21 1493
28143b40 1494 if (!has_xcrs) {
f1665b21 1495 return 0;
b9bec74b 1496 }
f1665b21
SY		 1497
1498 xcrs.nr_xcrs = 1;
1499 xcrs.flags = 0;
1500 xcrs.xcrs[0].xcr = 0;
1501 xcrs.xcrs[0].value = env->xcr0;
1bc22652 1502 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
f1665b21
SY		 1503}
1504
1bc22652 1505static int kvm_put_sregs(X86CPU *cpu)
05330448 1506{
1bc22652 1507 CPUX86State *env = &cpu->env;
05330448
AL		 1508 struct kvm_sregs sregs;
1509
0e607a80
JK		 1510 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1511 if (env->interrupt_injected >= 0) {
1512 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1513 (uint64_t)1 << (env->interrupt_injected % 64);
1514 }
05330448
AL		 1515
1516 if ((env->eflags & VM_MASK)) {
b9bec74b
JK		 1517 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1518 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1519 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1520 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1521 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1522 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
05330448 1523 } else {
b9bec74b
JK		 1524 set_seg(&sregs.cs, &env->segs[R_CS]);
1525 set_seg(&sregs.ds, &env->segs[R_DS]);
1526 set_seg(&sregs.es, &env->segs[R_ES]);
1527 set_seg(&sregs.fs, &env->segs[R_FS]);
1528 set_seg(&sregs.gs, &env->segs[R_GS]);
1529 set_seg(&sregs.ss, &env->segs[R_SS]);
05330448
AL		 1530 }
1531
1532 set_seg(&sregs.tr, &env->tr);
1533 set_seg(&sregs.ldt, &env->ldt);
1534
1535 sregs.idt.limit = env->idt.limit;
1536 sregs.idt.base = env->idt.base;
7e680753 1537 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
05330448
AL		 1538 sregs.gdt.limit = env->gdt.limit;
1539 sregs.gdt.base = env->gdt.base;
7e680753 1540 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
05330448
AL		 1541
1542 sregs.cr0 = env->cr[0];
1543 sregs.cr2 = env->cr[2];
1544 sregs.cr3 = env->cr[3];
1545 sregs.cr4 = env->cr[4];
1546
02e51483
CF		 1547 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1548 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
05330448
AL		 1549
1550 sregs.efer = env->efer;
1551
1bc22652 1552 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
05330448
AL		 1553}
1554
d71b62a1
EH		 1555static void kvm_msr_buf_reset(X86CPU *cpu)
1556{
1557 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
1558}
1559
9c600a84
EH		 1560static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
1561{
1562 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
1563 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
1564 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
1565
1566 assert((void *)(entry + 1) <= limit);
1567
1abc2cae
EH		 1568 entry->index = index;
1569 entry->reserved = 0;
1570 entry->data = value;
9c600a84
EH		 1571 msrs->nmsrs++;
1572}
1573
73e1b8f2
PB		 1574static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
1575{
1576 kvm_msr_buf_reset(cpu);
1577 kvm_msr_entry_add(cpu, index, value);
1578
1579 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1580}
1581
f8d9ccf8
DDAG		 1582void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
1583{
1584 int ret;
1585
1586 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
1587 assert(ret == 1);
1588}
1589
7477cd38
MT		 1590static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1591{
1592 CPUX86State *env = &cpu->env;
48e1a45c 1593 int ret;
7477cd38
MT		 1594
1595 if (!has_msr_tsc_deadline) {
1596 return 0;
1597 }
1598
73e1b8f2 1599 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
48e1a45c
PB		 1600 if (ret < 0) {
1601 return ret;
1602 }
1603
1604 assert(ret == 1);
1605 return 0;
7477cd38
MT		 1606}
1607
6bdf863d
JK		 1608/*
1609 * Provide a separate write service for the feature control MSR in order to
1610 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1611 * before writing any other state because forcibly leaving nested mode
1612 * invalidates the VCPU state.
1613 */
1614static int kvm_put_msr_feature_control(X86CPU *cpu)
1615{
48e1a45c
PB		 1616 int ret;
1617
1618 if (!has_msr_feature_control) {
1619 return 0;
1620 }
6bdf863d 1621
73e1b8f2
PB		 1622 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
1623 cpu->env.msr_ia32_feature_control);
48e1a45c
PB		 1624 if (ret < 0) {
1625 return ret;
1626 }
1627
1628 assert(ret == 1);
1629 return 0;
6bdf863d
JK		 1630}
1631
1bc22652 1632static int kvm_put_msrs(X86CPU *cpu, int level)
05330448 1633{
1bc22652 1634 CPUX86State *env = &cpu->env;
9c600a84 1635 int i;
48e1a45c 1636 int ret;
05330448 1637
d71b62a1
EH		 1638 kvm_msr_buf_reset(cpu);
1639
9c600a84
EH		 1640 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1641 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1642 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1643 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
c3a3a7d3 1644 if (has_msr_star) {
9c600a84 1645 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
b9bec74b 1646 }
c3a3a7d3 1647 if (has_msr_hsave_pa) {
9c600a84 1648 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
b9bec74b 1649 }
c9b8f6b6 1650 if (has_msr_tsc_aux) {
9c600a84 1651 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
c9b8f6b6 1652 }
f28558d3 1653 if (has_msr_tsc_adjust) {
9c600a84 1654 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
f28558d3 1655 }
21e87c46 1656 if (has_msr_misc_enable) {
9c600a84 1657 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
21e87c46
AK		 1658 env->msr_ia32_misc_enable);
1659 }
fc12d72e 1660 if (has_msr_smbase) {
9c600a84 1661 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
fc12d72e 1662 }
439d19f2 1663 if (has_msr_bndcfgs) {
9c600a84 1664 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
439d19f2 1665 }
18cd2c17 1666 if (has_msr_xss) {
9c600a84 1667 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
18cd2c17 1668 }
a33a2cfe
PB		 1669 if (has_msr_spec_ctrl) {
1670 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
1671 }
05330448 1672#ifdef TARGET_X86_64
25d2e361 1673 if (lm_capable_kernel) {
9c600a84
EH		 1674 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
1675 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
1676 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
1677 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
25d2e361 1678 }
05330448 1679#endif
a33a2cfe 1680
ff5c186b 1681 /*
0d894367
PB		 1682 * The following MSRs have side effects on the guest or are too heavy
1683 * for normal writeback. Limit them to reset or full state updates.
ff5c186b
JK		 1684 */
1685 if (level >= KVM_PUT_RESET_STATE) {
9c600a84
EH		 1686 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
1687 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
1688 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
55c911a5 1689 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
9c600a84 1690 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
c5999bfc 1691 }
55c911a5 1692 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 1693 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
bc9a839d 1694 }
55c911a5 1695 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 1696 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
917367aa 1697 }
0b368a10
JD		 1698 if (has_architectural_pmu_version > 0) {
1699 if (has_architectural_pmu_version > 1) {
1700 /* Stop the counter. */
1701 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1702 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
1703 }
0d894367
PB		 1704
1705 /* Set the counter values. */
0b368a10 1706 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
9c600a84 1707 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
0d894367
PB		 1708 env->msr_fixed_counters[i]);
1709 }
0b368a10 1710 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
9c600a84 1711 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
0d894367 1712 env->msr_gp_counters[i]);
9c600a84 1713 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
0d894367
PB		 1714 env->msr_gp_evtsel[i]);
1715 }
0b368a10
JD		 1716 if (has_architectural_pmu_version > 1) {
1717 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
1718 env->msr_global_status);
1719 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1720 env->msr_global_ovf_ctrl);
1721
1722 /* Now start the PMU. */
1723 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
1724 env->msr_fixed_ctr_ctrl);
1725 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
1726 env->msr_global_ctrl);
1727 }
0d894367 1728 }
da1cc323
EY		 1729 /*
1730 * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add,
1731 * only sync them to KVM on the first cpu
1732 */
1733 if (current_cpu == first_cpu) {
1734 if (has_msr_hv_hypercall) {
1735 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
1736 env->msr_hv_guest_os_id);
1737 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
1738 env->msr_hv_hypercall);
1739 }
1740 if (cpu->hyperv_time) {
1741 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC,
1742 env->msr_hv_tsc);
1743 }
eab70139 1744 }
2d5aa872 1745 if (cpu->hyperv_vapic) {
9c600a84 1746 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
5ef68987 1747 env->msr_hv_vapic);
eab70139 1748 }
f2a53c9e
AS		 1749 if (has_msr_hv_crash) {
1750 int j;
1751
5e953812 1752 for (j = 0; j < HV_CRASH_PARAMS; j++)
9c600a84 1753 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
f2a53c9e
AS		 1754 env->msr_hv_crash_params[j]);
1755
5e953812 1756 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_NOTIFY);
f2a53c9e 1757 }
46eb8f98 1758 if (has_msr_hv_runtime) {
9c600a84 1759 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
46eb8f98 1760 }
866eea9a
AS		 1761 if (cpu->hyperv_synic) {
1762 int j;
1763
09df29b6
RK		 1764 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, HV_SYNIC_VERSION);
1765
9c600a84 1766 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
866eea9a 1767 env->msr_hv_synic_control);
9c600a84 1768 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
866eea9a 1769 env->msr_hv_synic_evt_page);
9c600a84 1770 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
866eea9a
AS		 1771 env->msr_hv_synic_msg_page);
1772
1773 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
9c600a84 1774 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
866eea9a
AS		 1775 env->msr_hv_synic_sint[j]);
1776 }
1777 }
ff99aa64
AS		 1778 if (has_msr_hv_stimer) {
1779 int j;
1780
1781 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
9c600a84 1782 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
ff99aa64
AS		 1783 env->msr_hv_stimer_config[j]);
1784 }
1785
1786 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
9c600a84 1787 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
ff99aa64
AS		 1788 env->msr_hv_stimer_count[j]);
1789 }
1790 }
1eabfce6 1791 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
112dad69
DDAG		 1792 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
1793
9c600a84
EH		 1794 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
1795 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
1796 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
1797 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
1798 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
1799 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
1800 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
1801 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
1802 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
1803 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
1804 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
1805 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
d1ae67f6 1806 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
112dad69
DDAG		 1807 /* The CPU GPs if we write to a bit above the physical limit of
1808 * the host CPU (and KVM emulates that)
1809 */
1810 uint64_t mask = env->mtrr_var[i].mask;
1811 mask &= phys_mask;
1812
9c600a84
EH		 1813 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
1814 env->mtrr_var[i].base);
112dad69 1815 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
d1ae67f6
AW		 1816 }
1817 }
b77146e9
CP		 1818 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
1819 int addr_num = kvm_arch_get_supported_cpuid(kvm_state,
1820 0x14, 1, R_EAX) & 0x7;
1821
1822 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL,
1823 env->msr_rtit_ctrl);
1824 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS,
1825 env->msr_rtit_status);
1826 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE,
1827 env->msr_rtit_output_base);
1828 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK,
1829 env->msr_rtit_output_mask);
1830 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH,
1831 env->msr_rtit_cr3_match);
1832 for (i = 0; i < addr_num; i++) {
1833 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i,
1834 env->msr_rtit_addrs[i]);
1835 }
1836 }
6bdf863d
JK		 1837
1838 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1839 * kvm_put_msr_feature_control. */
ea643051 1840 }
57780495 1841 if (env->mcg_cap) {
d8da8574 1842 int i;
b9bec74b 1843
9c600a84
EH		 1844 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
1845 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
87f8b626
AR		 1846 if (has_msr_mcg_ext_ctl) {
1847 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
1848 }
c34d440a 1849 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 1850 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
57780495
MT		 1851 }
1852 }
1a03675d 1853
d71b62a1 1854 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
48e1a45c
PB		 1855 if (ret < 0) {
1856 return ret;
1857 }
05330448 1858
c70b11d1
EH		 1859 if (ret < cpu->kvm_msr_buf->nmsrs) {
1860 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
1861 error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
1862 (uint32_t)e->index, (uint64_t)e->data);
1863 }
1864
9c600a84 1865 assert(ret == cpu->kvm_msr_buf->nmsrs);
48e1a45c 1866 return 0;
05330448
AL		 1867}
1868
1869
1bc22652 1870static int kvm_get_fpu(X86CPU *cpu)
05330448 1871{
1bc22652 1872 CPUX86State *env = &cpu->env;
05330448
AL		 1873 struct kvm_fpu fpu;
1874 int i, ret;
1875
1bc22652 1876 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
b9bec74b 1877 if (ret < 0) {
05330448 1878 return ret;
b9bec74b 1879 }
05330448
AL		 1880
1881 env->fpstt = (fpu.fsw >> 11) & 7;
1882 env->fpus = fpu.fsw;
1883 env->fpuc = fpu.fcw;
42cc8fa6
JK		 1884 env->fpop = fpu.last_opcode;
1885 env->fpip = fpu.last_ip;
1886 env->fpdp = fpu.last_dp;
b9bec74b
JK		 1887 for (i = 0; i < 8; ++i) {
1888 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1889 }
05330448 1890 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
bee81887 1891 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 1892 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
1893 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
bee81887 1894 }
05330448
AL		 1895 env->mxcsr = fpu.mxcsr;
1896
1897 return 0;
1898}
1899
1bc22652 1900static int kvm_get_xsave(X86CPU *cpu)
f1665b21 1901{
1bc22652 1902 CPUX86State *env = &cpu->env;
86cd2ea0 1903 X86XSaveArea *xsave = env->kvm_xsave_buf;
86a57621 1904 int ret;
f1665b21 1905
28143b40 1906 if (!has_xsave) {
1bc22652 1907 return kvm_get_fpu(cpu);
b9bec74b 1908 }
f1665b21 1909
1bc22652 1910 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
0f53994f 1911 if (ret < 0) {
f1665b21 1912 return ret;
0f53994f 1913 }
86a57621 1914 x86_cpu_xrstor_all_areas(cpu, xsave);
f1665b21 1915
f1665b21 1916 return 0;
f1665b21
SY		 1917}
1918
1bc22652 1919static int kvm_get_xcrs(X86CPU *cpu)
f1665b21 1920{
1bc22652 1921 CPUX86State *env = &cpu->env;
f1665b21
SY		 1922 int i, ret;
1923 struct kvm_xcrs xcrs;
1924
28143b40 1925 if (!has_xcrs) {
f1665b21 1926 return 0;
b9bec74b 1927 }
f1665b21 1928
1bc22652 1929 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
b9bec74b 1930 if (ret < 0) {
f1665b21 1931 return ret;
b9bec74b 1932 }
f1665b21 1933
b9bec74b 1934 for (i = 0; i < xcrs.nr_xcrs; i++) {
f1665b21 1935 /* Only support xcr0 now */
0fd53fec
PB		 1936 if (xcrs.xcrs[i].xcr == 0) {
1937 env->xcr0 = xcrs.xcrs[i].value;
f1665b21
SY		 1938 break;
1939 }
b9bec74b 1940 }
f1665b21 1941 return 0;
f1665b21
SY		 1942}
1943
1bc22652 1944static int kvm_get_sregs(X86CPU *cpu)
05330448 1945{
1bc22652 1946 CPUX86State *env = &cpu->env;
05330448 1947 struct kvm_sregs sregs;
0e607a80 1948 int bit, i, ret;
05330448 1949
1bc22652 1950 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
b9bec74b 1951 if (ret < 0) {
05330448 1952 return ret;
b9bec74b 1953 }
05330448 1954
0e607a80
JK		 1955 /* There can only be one pending IRQ set in the bitmap at a time, so try
1956 to find it and save its number instead (-1 for none). */
1957 env->interrupt_injected = -1;
1958 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1959 if (sregs.interrupt_bitmap[i]) {
1960 bit = ctz64(sregs.interrupt_bitmap[i]);
1961 env->interrupt_injected = i * 64 + bit;
1962 break;
1963 }
1964 }
05330448
AL		 1965
1966 get_seg(&env->segs[R_CS], &sregs.cs);
1967 get_seg(&env->segs[R_DS], &sregs.ds);
1968 get_seg(&env->segs[R_ES], &sregs.es);
1969 get_seg(&env->segs[R_FS], &sregs.fs);
1970 get_seg(&env->segs[R_GS], &sregs.gs);
1971 get_seg(&env->segs[R_SS], &sregs.ss);
1972
1973 get_seg(&env->tr, &sregs.tr);
1974 get_seg(&env->ldt, &sregs.ldt);
1975
1976 env->idt.limit = sregs.idt.limit;
1977 env->idt.base = sregs.idt.base;
1978 env->gdt.limit = sregs.gdt.limit;
1979 env->gdt.base = sregs.gdt.base;
1980
1981 env->cr[0] = sregs.cr0;
1982 env->cr[2] = sregs.cr2;
1983 env->cr[3] = sregs.cr3;
1984 env->cr[4] = sregs.cr4;
1985
05330448 1986 env->efer = sregs.efer;
cce47516
JK		 1987
1988 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
35b1b927 1989 x86_update_hflags(env);
05330448
AL		 1990
1991 return 0;
1992}
1993
1bc22652 1994static int kvm_get_msrs(X86CPU *cpu)
05330448 1995{
1bc22652 1996 CPUX86State *env = &cpu->env;
d71b62a1 1997 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
9c600a84 1998 int ret, i;
fcc35e7c 1999 uint64_t mtrr_top_bits;
05330448 2000
d71b62a1
EH		 2001 kvm_msr_buf_reset(cpu);
2002
9c600a84
EH		 2003 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
2004 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
2005 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
2006 kvm_msr_entry_add(cpu, MSR_PAT, 0);
c3a3a7d3 2007 if (has_msr_star) {
9c600a84 2008 kvm_msr_entry_add(cpu, MSR_STAR, 0);
b9bec74b 2009 }
c3a3a7d3 2010 if (has_msr_hsave_pa) {
9c600a84 2011 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
b9bec74b 2012 }
c9b8f6b6 2013 if (has_msr_tsc_aux) {
9c600a84 2014 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
c9b8f6b6 2015 }
f28558d3 2016 if (has_msr_tsc_adjust) {
9c600a84 2017 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
f28558d3 2018 }
aa82ba54 2019 if (has_msr_tsc_deadline) {
9c600a84 2020 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
aa82ba54 2021 }
21e87c46 2022 if (has_msr_misc_enable) {
9c600a84 2023 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
21e87c46 2024 }
fc12d72e 2025 if (has_msr_smbase) {
9c600a84 2026 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
fc12d72e 2027 }
df67696e 2028 if (has_msr_feature_control) {
9c600a84 2029 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
df67696e 2030 }
79e9ebeb 2031 if (has_msr_bndcfgs) {
9c600a84 2032 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
79e9ebeb 2033 }
18cd2c17 2034 if (has_msr_xss) {
9c600a84 2035 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
18cd2c17 2036 }
a33a2cfe
PB		 2037 if (has_msr_spec_ctrl) {
2038 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
2039 }
18cd2c17 2040
b8cc45d6
GC		 2041
2042 if (!env->tsc_valid) {
9c600a84 2043 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
1354869c 2044 env->tsc_valid = !runstate_is_running();
b8cc45d6
GC		 2045 }
2046
05330448 2047#ifdef TARGET_X86_64
25d2e361 2048 if (lm_capable_kernel) {
9c600a84
EH		 2049 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
2050 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
2051 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
2052 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
25d2e361 2053 }
05330448 2054#endif
9c600a84
EH		 2055 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
2056 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
55c911a5 2057 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
9c600a84 2058 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
c5999bfc 2059 }
55c911a5 2060 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 2061 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
bc9a839d 2062 }
55c911a5 2063 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 2064 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
917367aa 2065 }
0b368a10
JD		 2066 if (has_architectural_pmu_version > 0) {
2067 if (has_architectural_pmu_version > 1) {
2068 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2069 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2070 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
2071 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
2072 }
2073 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
9c600a84 2074 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
0d894367 2075 }
0b368a10 2076 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
9c600a84
EH		 2077 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
2078 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
0d894367
PB		 2079 }
2080 }
1a03675d 2081
57780495 2082 if (env->mcg_cap) {
9c600a84
EH		 2083 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
2084 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
87f8b626
AR		 2085 if (has_msr_mcg_ext_ctl) {
2086 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
2087 }
b9bec74b 2088 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 2089 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
b9bec74b 2090 }
57780495 2091 }
57780495 2092
1c90ef26 2093 if (has_msr_hv_hypercall) {
9c600a84
EH		 2094 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
2095 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
1c90ef26 2096 }
2d5aa872 2097 if (cpu->hyperv_vapic) {
9c600a84 2098 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
5ef68987 2099 }
3ddcd2ed 2100 if (cpu->hyperv_time) {
9c600a84 2101 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
48a5f3bc 2102 }
f2a53c9e
AS		 2103 if (has_msr_hv_crash) {
2104 int j;
2105
5e953812 2106 for (j = 0; j < HV_CRASH_PARAMS; j++) {
9c600a84 2107 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
f2a53c9e
AS		 2108 }
2109 }
46eb8f98 2110 if (has_msr_hv_runtime) {
9c600a84 2111 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
46eb8f98 2112 }
866eea9a
AS		 2113 if (cpu->hyperv_synic) {
2114 uint32_t msr;
2115
9c600a84 2116 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
9c600a84
EH		 2117 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
2118 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
866eea9a 2119 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
9c600a84 2120 kvm_msr_entry_add(cpu, msr, 0);
866eea9a
AS		 2121 }
2122 }
ff99aa64
AS		 2123 if (has_msr_hv_stimer) {
2124 uint32_t msr;
2125
2126 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2127 msr++) {
9c600a84 2128 kvm_msr_entry_add(cpu, msr, 0);
ff99aa64
AS		 2129 }
2130 }
1eabfce6 2131 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
9c600a84
EH		 2132 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
2133 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
2134 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
2135 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
2136 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
2137 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
2138 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
2139 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
2140 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
2141 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
2142 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
2143 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
d1ae67f6 2144 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
9c600a84
EH		 2145 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
2146 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
d1ae67f6
AW		 2147 }
2148 }
5ef68987 2149
b77146e9
CP		 2150 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
2151 int addr_num =
2152 kvm_arch_get_supported_cpuid(kvm_state, 0x14, 1, R_EAX) & 0x7;
2153
2154 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 0);
2155 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 0);
2156 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, 0);
2157 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, 0);
2158 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, 0);
2159 for (i = 0; i < addr_num; i++) {
2160 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 0);
2161 }
2162 }
2163
d71b62a1 2164 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
b9bec74b 2165 if (ret < 0) {
05330448 2166 return ret;
b9bec74b 2167 }
05330448 2168
c70b11d1
EH		 2169 if (ret < cpu->kvm_msr_buf->nmsrs) {
2170 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2171 error_report("error: failed to get MSR 0x%" PRIx32,
2172 (uint32_t)e->index);
2173 }
2174
9c600a84 2175 assert(ret == cpu->kvm_msr_buf->nmsrs);
fcc35e7c
DDAG		 2176 /*
2177 * MTRR masks: Each mask consists of 5 parts
2178 * a 10..0: must be zero
2179 * b 11 : valid bit
2180 * c n-1.12: actual mask bits
2181 * d 51..n: reserved must be zero
2182 * e 63.52: reserved must be zero
2183 *
2184 * 'n' is the number of physical bits supported by the CPU and is
2185 * apparently always <= 52. We know our 'n' but don't know what
2186 * the destinations 'n' is; it might be smaller, in which case
2187 * it masks (c) on loading. It might be larger, in which case
2188 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
2189 * we're migrating to.
2190 */
2191
2192 if (cpu->fill_mtrr_mask) {
2193 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
2194 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
2195 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
2196 } else {
2197 mtrr_top_bits = 0;
2198 }
2199
05330448 2200 for (i = 0; i < ret; i++) {
0d894367
PB		 2201 uint32_t index = msrs[i].index;
2202 switch (index) {
05330448
AL		 2203 case MSR_IA32_SYSENTER_CS:
2204 env->sysenter_cs = msrs[i].data;
2205 break;
2206 case MSR_IA32_SYSENTER_ESP:
2207 env->sysenter_esp = msrs[i].data;
2208 break;
2209 case MSR_IA32_SYSENTER_EIP:
2210 env->sysenter_eip = msrs[i].data;
2211 break;
0c03266a
JK		 2212 case MSR_PAT:
2213 env->pat = msrs[i].data;
2214 break;
05330448
AL		 2215 case MSR_STAR:
2216 env->star = msrs[i].data;
2217 break;
2218#ifdef TARGET_X86_64
2219 case MSR_CSTAR:
2220 env->cstar = msrs[i].data;
2221 break;
2222 case MSR_KERNELGSBASE:
2223 env->kernelgsbase = msrs[i].data;
2224 break;
2225 case MSR_FMASK:
2226 env->fmask = msrs[i].data;
2227 break;
2228 case MSR_LSTAR:
2229 env->lstar = msrs[i].data;
2230 break;
2231#endif
2232 case MSR_IA32_TSC:
2233 env->tsc = msrs[i].data;
2234 break;
c9b8f6b6
AS		 2235 case MSR_TSC_AUX:
2236 env->tsc_aux = msrs[i].data;
2237 break;
f28558d3
WA		 2238 case MSR_TSC_ADJUST:
2239 env->tsc_adjust = msrs[i].data;
2240 break;
aa82ba54
LJ		 2241 case MSR_IA32_TSCDEADLINE:
2242 env->tsc_deadline = msrs[i].data;
2243 break;
aa851e36
MT		 2244 case MSR_VM_HSAVE_PA:
2245 env->vm_hsave = msrs[i].data;
2246 break;
1a03675d
GC		 2247 case MSR_KVM_SYSTEM_TIME:
2248 env->system_time_msr = msrs[i].data;
2249 break;
2250 case MSR_KVM_WALL_CLOCK:
2251 env->wall_clock_msr = msrs[i].data;
2252 break;
57780495
MT		 2253 case MSR_MCG_STATUS:
2254 env->mcg_status = msrs[i].data;
2255 break;
2256 case MSR_MCG_CTL:
2257 env->mcg_ctl = msrs[i].data;
2258 break;
87f8b626
AR		 2259 case MSR_MCG_EXT_CTL:
2260 env->mcg_ext_ctl = msrs[i].data;
2261 break;
21e87c46
AK		 2262 case MSR_IA32_MISC_ENABLE:
2263 env->msr_ia32_misc_enable = msrs[i].data;
2264 break;
fc12d72e
PB		 2265 case MSR_IA32_SMBASE:
2266 env->smbase = msrs[i].data;
2267 break;
0779caeb
ACL		 2268 case MSR_IA32_FEATURE_CONTROL:
2269 env->msr_ia32_feature_control = msrs[i].data;
df67696e 2270 break;
79e9ebeb
LJ		 2271 case MSR_IA32_BNDCFGS:
2272 env->msr_bndcfgs = msrs[i].data;
2273 break;
18cd2c17
WL		 2274 case MSR_IA32_XSS:
2275 env->xss = msrs[i].data;
2276 break;
57780495 2277 default:
57780495
MT		 2278 if (msrs[i].index >= MSR_MC0_CTL &&
2279 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
2280 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
57780495 2281 }
d8da8574 2282 break;
f6584ee2
GN		 2283 case MSR_KVM_ASYNC_PF_EN:
2284 env->async_pf_en_msr = msrs[i].data;
2285 break;
bc9a839d
MT		 2286 case MSR_KVM_PV_EOI_EN:
2287 env->pv_eoi_en_msr = msrs[i].data;
2288 break;
917367aa
MT		 2289 case MSR_KVM_STEAL_TIME:
2290 env->steal_time_msr = msrs[i].data;
2291 break;
0d894367
PB		 2292 case MSR_CORE_PERF_FIXED_CTR_CTRL:
2293 env->msr_fixed_ctr_ctrl = msrs[i].data;
2294 break;
2295 case MSR_CORE_PERF_GLOBAL_CTRL:
2296 env->msr_global_ctrl = msrs[i].data;
2297 break;
2298 case MSR_CORE_PERF_GLOBAL_STATUS:
2299 env->msr_global_status = msrs[i].data;
2300 break;
2301 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
2302 env->msr_global_ovf_ctrl = msrs[i].data;
2303 break;
2304 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
2305 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
2306 break;
2307 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
2308 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
2309 break;
2310 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
2311 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
2312 break;
1c90ef26
VR		 2313 case HV_X64_MSR_HYPERCALL:
2314 env->msr_hv_hypercall = msrs[i].data;
2315 break;
2316 case HV_X64_MSR_GUEST_OS_ID:
2317 env->msr_hv_guest_os_id = msrs[i].data;
2318 break;
5ef68987
VR		 2319 case HV_X64_MSR_APIC_ASSIST_PAGE:
2320 env->msr_hv_vapic = msrs[i].data;
2321 break;
48a5f3bc
VR		 2322 case HV_X64_MSR_REFERENCE_TSC:
2323 env->msr_hv_tsc = msrs[i].data;
2324 break;
f2a53c9e
AS		 2325 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2326 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
2327 break;
46eb8f98
AS		 2328 case HV_X64_MSR_VP_RUNTIME:
2329 env->msr_hv_runtime = msrs[i].data;
2330 break;
866eea9a
AS		 2331 case HV_X64_MSR_SCONTROL:
2332 env->msr_hv_synic_control = msrs[i].data;
2333 break;
866eea9a
AS		 2334 case HV_X64_MSR_SIEFP:
2335 env->msr_hv_synic_evt_page = msrs[i].data;
2336 break;
2337 case HV_X64_MSR_SIMP:
2338 env->msr_hv_synic_msg_page = msrs[i].data;
2339 break;
2340 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
2341 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
ff99aa64
AS		 2342 break;
2343 case HV_X64_MSR_STIMER0_CONFIG:
2344 case HV_X64_MSR_STIMER1_CONFIG:
2345 case HV_X64_MSR_STIMER2_CONFIG:
2346 case HV_X64_MSR_STIMER3_CONFIG:
2347 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
2348 msrs[i].data;
2349 break;
2350 case HV_X64_MSR_STIMER0_COUNT:
2351 case HV_X64_MSR_STIMER1_COUNT:
2352 case HV_X64_MSR_STIMER2_COUNT:
2353 case HV_X64_MSR_STIMER3_COUNT:
2354 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
2355 msrs[i].data;
866eea9a 2356 break;
d1ae67f6
AW		 2357 case MSR_MTRRdefType:
2358 env->mtrr_deftype = msrs[i].data;
2359 break;
2360 case MSR_MTRRfix64K_00000:
2361 env->mtrr_fixed[0] = msrs[i].data;
2362 break;
2363 case MSR_MTRRfix16K_80000:
2364 env->mtrr_fixed[1] = msrs[i].data;
2365 break;
2366 case MSR_MTRRfix16K_A0000:
2367 env->mtrr_fixed[2] = msrs[i].data;
2368 break;
2369 case MSR_MTRRfix4K_C0000:
2370 env->mtrr_fixed[3] = msrs[i].data;
2371 break;
2372 case MSR_MTRRfix4K_C8000:
2373 env->mtrr_fixed[4] = msrs[i].data;
2374 break;
2375 case MSR_MTRRfix4K_D0000:
2376 env->mtrr_fixed[5] = msrs[i].data;
2377 break;
2378 case MSR_MTRRfix4K_D8000:
2379 env->mtrr_fixed[6] = msrs[i].data;
2380 break;
2381 case MSR_MTRRfix4K_E0000:
2382 env->mtrr_fixed[7] = msrs[i].data;
2383 break;
2384 case MSR_MTRRfix4K_E8000:
2385 env->mtrr_fixed[8] = msrs[i].data;
2386 break;
2387 case MSR_MTRRfix4K_F0000:
2388 env->mtrr_fixed[9] = msrs[i].data;
2389 break;
2390 case MSR_MTRRfix4K_F8000:
2391 env->mtrr_fixed[10] = msrs[i].data;
2392 break;
2393 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
2394 if (index & 1) {
fcc35e7c
DDAG		 2395 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
2396 mtrr_top_bits;
d1ae67f6
AW		 2397 } else {
2398 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
2399 }
2400 break;
a33a2cfe
PB		 2401 case MSR_IA32_SPEC_CTRL:
2402 env->spec_ctrl = msrs[i].data;
2403 break;
b77146e9
CP		 2404 case MSR_IA32_RTIT_CTL:
2405 env->msr_rtit_ctrl = msrs[i].data;
2406 break;
2407 case MSR_IA32_RTIT_STATUS:
2408 env->msr_rtit_status = msrs[i].data;
2409 break;
2410 case MSR_IA32_RTIT_OUTPUT_BASE:
2411 env->msr_rtit_output_base = msrs[i].data;
2412 break;
2413 case MSR_IA32_RTIT_OUTPUT_MASK:
2414 env->msr_rtit_output_mask = msrs[i].data;
2415 break;
2416 case MSR_IA32_RTIT_CR3_MATCH:
2417 env->msr_rtit_cr3_match = msrs[i].data;
2418 break;
2419 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
2420 env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] = msrs[i].data;
2421 break;
05330448
AL		 2422 }
2423 }
2424
2425 return 0;
2426}
2427
1bc22652 2428static int kvm_put_mp_state(X86CPU *cpu)
9bdbe550 2429{
1bc22652 2430 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
9bdbe550 2431
1bc22652 2432 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
9bdbe550
HB		 2433}
2434
23d02d9b 2435static int kvm_get_mp_state(X86CPU *cpu)
9bdbe550 2436{
259186a7 2437 CPUState *cs = CPU(cpu);
23d02d9b 2438 CPUX86State *env = &cpu->env;
9bdbe550
HB		 2439 struct kvm_mp_state mp_state;
2440 int ret;
2441
259186a7 2442 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
9bdbe550
HB		 2443 if (ret < 0) {
2444 return ret;
2445 }
2446 env->mp_state = mp_state.mp_state;
c14750e8 2447 if (kvm_irqchip_in_kernel()) {
259186a7 2448 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
c14750e8 2449 }
9bdbe550
HB		 2450 return 0;
2451}
2452
1bc22652 2453static int kvm_get_apic(X86CPU *cpu)
680c1c6f 2454{
02e51483 2455 DeviceState *apic = cpu->apic_state;
680c1c6f
JK		 2456 struct kvm_lapic_state kapic;
2457 int ret;
2458
3d4b2649 2459 if (apic && kvm_irqchip_in_kernel()) {
1bc22652 2460 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
680c1c6f
JK		 2461 if (ret < 0) {
2462 return ret;
2463 }
2464
2465 kvm_get_apic_state(apic, &kapic);
2466 }
2467 return 0;
2468}
2469
1bc22652 2470static int kvm_put_vcpu_events(X86CPU *cpu, int level)
a0fb002c 2471{
fc12d72e 2472 CPUState *cs = CPU(cpu);
1bc22652 2473 CPUX86State *env = &cpu->env;
076796f8 2474 struct kvm_vcpu_events events = {};
a0fb002c
JK		 2475
2476 if (!kvm_has_vcpu_events()) {
2477 return 0;
2478 }
2479
31827373
JK		 2480 events.exception.injected = (env->exception_injected >= 0);
2481 events.exception.nr = env->exception_injected;
a0fb002c
JK		 2482 events.exception.has_error_code = env->has_error_code;
2483 events.exception.error_code = env->error_code;
7e680753 2484 events.exception.pad = 0;
a0fb002c
JK		 2485
2486 events.interrupt.injected = (env->interrupt_injected >= 0);
2487 events.interrupt.nr = env->interrupt_injected;
2488 events.interrupt.soft = env->soft_interrupt;
2489
2490 events.nmi.injected = env->nmi_injected;
2491 events.nmi.pending = env->nmi_pending;
2492 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
7e680753 2493 events.nmi.pad = 0;
a0fb002c
JK		 2494
2495 events.sipi_vector = env->sipi_vector;
68c6efe0 2496 events.flags = 0;
a0fb002c 2497
fc12d72e
PB		 2498 if (has_msr_smbase) {
2499 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
2500 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
2501 if (kvm_irqchip_in_kernel()) {
2502 /* As soon as these are moved to the kernel, remove them
2503 * from cs->interrupt_request.
2504 */
2505 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
2506 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
2507 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
2508 } else {
2509 /* Keep these in cs->interrupt_request. */
2510 events.smi.pending = 0;
2511 events.smi.latched_init = 0;
2512 }
fc3a1fd7
DDAG		 2513 /* Stop SMI delivery on old machine types to avoid a reboot
2514 * on an inward migration of an old VM.
2515 */
2516 if (!cpu->kvm_no_smi_migration) {
2517 events.flags |= KVM_VCPUEVENT_VALID_SMM;
2518 }
fc12d72e
PB		 2519 }
2520
ea643051 2521 if (level >= KVM_PUT_RESET_STATE) {
4fadfa00
PH		 2522 events.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING;
2523 if (env->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
2524 events.flags |= KVM_VCPUEVENT_VALID_SIPI_VECTOR;
2525 }
ea643051 2526 }
aee028b9 2527
1bc22652 2528 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
a0fb002c
JK		 2529}
2530
1bc22652 2531static int kvm_get_vcpu_events(X86CPU *cpu)
a0fb002c 2532{
1bc22652 2533 CPUX86State *env = &cpu->env;
a0fb002c
JK		 2534 struct kvm_vcpu_events events;
2535 int ret;
2536
2537 if (!kvm_has_vcpu_events()) {
2538 return 0;
2539 }
2540
fc12d72e 2541 memset(&events, 0, sizeof(events));
1bc22652 2542 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
a0fb002c
JK		 2543 if (ret < 0) {
2544 return ret;
2545 }
31827373 2546 env->exception_injected =
a0fb002c
JK		 2547 events.exception.injected ? events.exception.nr : -1;
2548 env->has_error_code = events.exception.has_error_code;
2549 env->error_code = events.exception.error_code;
2550
2551 env->interrupt_injected =
2552 events.interrupt.injected ? events.interrupt.nr : -1;
2553 env->soft_interrupt = events.interrupt.soft;
2554
2555 env->nmi_injected = events.nmi.injected;
2556 env->nmi_pending = events.nmi.pending;
2557 if (events.nmi.masked) {
2558 env->hflags2 |= HF2_NMI_MASK;
2559 } else {
2560 env->hflags2 &= ~HF2_NMI_MASK;
2561 }
2562
fc12d72e
PB		 2563 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2564 if (events.smi.smm) {
2565 env->hflags |= HF_SMM_MASK;
2566 } else {
2567 env->hflags &= ~HF_SMM_MASK;
2568 }
2569 if (events.smi.pending) {
2570 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2571 } else {
2572 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2573 }
2574 if (events.smi.smm_inside_nmi) {
2575 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2576 } else {
2577 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2578 }
2579 if (events.smi.latched_init) {
2580 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2581 } else {
2582 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2583 }
2584 }
2585
a0fb002c 2586 env->sipi_vector = events.sipi_vector;
a0fb002c
JK		 2587
2588 return 0;
2589}
2590
1bc22652 2591static int kvm_guest_debug_workarounds(X86CPU *cpu)
b0b1d690 2592{
ed2803da 2593 CPUState *cs = CPU(cpu);
1bc22652 2594 CPUX86State *env = &cpu->env;
b0b1d690 2595 int ret = 0;
b0b1d690
JK		 2596 unsigned long reinject_trap = 0;
2597
2598 if (!kvm_has_vcpu_events()) {
2599 if (env->exception_injected == 1) {
2600 reinject_trap = KVM_GUESTDBG_INJECT_DB;
2601 } else if (env->exception_injected == 3) {
2602 reinject_trap = KVM_GUESTDBG_INJECT_BP;
2603 }
2604 env->exception_injected = -1;
2605 }
2606
2607 /*
2608 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2609 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2610 * by updating the debug state once again if single-stepping is on.
2611 * Another reason to call kvm_update_guest_debug here is a pending debug
2612 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2613 * reinject them via SET_GUEST_DEBUG.
2614 */
2615 if (reinject_trap ||
ed2803da 2616 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
38e478ec 2617 ret = kvm_update_guest_debug(cs, reinject_trap);
b0b1d690 2618 }
b0b1d690
JK		 2619 return ret;
2620}
2621
1bc22652 2622static int kvm_put_debugregs(X86CPU *cpu)
ff44f1a3 2623{
1bc22652 2624 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 2625 struct kvm_debugregs dbgregs;
2626 int i;
2627
2628 if (!kvm_has_debugregs()) {
2629 return 0;
2630 }
2631
2632 for (i = 0; i < 4; i++) {
2633 dbgregs.db[i] = env->dr[i];
2634 }
2635 dbgregs.dr6 = env->dr[6];
2636 dbgregs.dr7 = env->dr[7];
2637 dbgregs.flags = 0;
2638
1bc22652 2639 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
ff44f1a3
JK		 2640}
2641
1bc22652 2642static int kvm_get_debugregs(X86CPU *cpu)
ff44f1a3 2643{
1bc22652 2644 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 2645 struct kvm_debugregs dbgregs;
2646 int i, ret;
2647
2648 if (!kvm_has_debugregs()) {
2649 return 0;
2650 }
2651
1bc22652 2652 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
ff44f1a3 2653 if (ret < 0) {
b9bec74b 2654 return ret;
ff44f1a3
JK		 2655 }
2656 for (i = 0; i < 4; i++) {
2657 env->dr[i] = dbgregs.db[i];
2658 }
2659 env->dr[4] = env->dr[6] = dbgregs.dr6;
2660 env->dr[5] = env->dr[7] = dbgregs.dr7;
ff44f1a3
JK		 2661
2662 return 0;
2663}
2664
20d695a9 2665int kvm_arch_put_registers(CPUState *cpu, int level)
05330448 2666{
20d695a9 2667 X86CPU *x86_cpu = X86_CPU(cpu);
05330448
AL		 2668 int ret;
2669
2fa45344 2670 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
dbaa07c4 2671
48e1a45c 2672 if (level >= KVM_PUT_RESET_STATE) {
6bdf863d
JK		 2673 ret = kvm_put_msr_feature_control(x86_cpu);
2674 if (ret < 0) {
2675 return ret;
2676 }
2677 }
2678
36f96c4b
HZ		 2679 if (level == KVM_PUT_FULL_STATE) {
2680 /* We don't check for kvm_arch_set_tsc_khz() errors here,
2681 * because TSC frequency mismatch shouldn't abort migration,
2682 * unless the user explicitly asked for a more strict TSC
2683 * setting (e.g. using an explicit "tsc-freq" option).
2684 */
2685 kvm_arch_set_tsc_khz(cpu);
2686 }
2687
1bc22652 2688 ret = kvm_getput_regs(x86_cpu, 1);
b9bec74b 2689 if (ret < 0) {
05330448 2690 return ret;
b9bec74b 2691 }
1bc22652 2692 ret = kvm_put_xsave(x86_cpu);
b9bec74b 2693 if (ret < 0) {
f1665b21 2694 return ret;
b9bec74b 2695 }
1bc22652 2696 ret = kvm_put_xcrs(x86_cpu);
b9bec74b 2697 if (ret < 0) {
05330448 2698 return ret;
b9bec74b 2699 }
1bc22652 2700 ret = kvm_put_sregs(x86_cpu);
b9bec74b 2701 if (ret < 0) {
05330448 2702 return ret;
b9bec74b 2703 }
ab443475 2704 /* must be before kvm_put_msrs */
1bc22652 2705 ret = kvm_inject_mce_oldstyle(x86_cpu);
ab443475
JK		 2706 if (ret < 0) {
2707 return ret;
2708 }
1bc22652 2709 ret = kvm_put_msrs(x86_cpu, level);
b9bec74b 2710 if (ret < 0) {
05330448 2711 return ret;
b9bec74b 2712 }
4fadfa00
PH		 2713 ret = kvm_put_vcpu_events(x86_cpu, level);
2714 if (ret < 0) {
2715 return ret;
2716 }
ea643051 2717 if (level >= KVM_PUT_RESET_STATE) {
1bc22652 2718 ret = kvm_put_mp_state(x86_cpu);
b9bec74b 2719 if (ret < 0) {
680c1c6f
JK		 2720 return ret;
2721 }
ea643051 2722 }
7477cd38
MT		 2723
2724 ret = kvm_put_tscdeadline_msr(x86_cpu);
2725 if (ret < 0) {
2726 return ret;
2727 }
1bc22652 2728 ret = kvm_put_debugregs(x86_cpu);
b9bec74b 2729 if (ret < 0) {
b0b1d690 2730 return ret;
b9bec74b 2731 }
b0b1d690 2732 /* must be last */
1bc22652 2733 ret = kvm_guest_debug_workarounds(x86_cpu);
b9bec74b 2734 if (ret < 0) {
ff44f1a3 2735 return ret;
b9bec74b 2736 }
05330448
AL		 2737 return 0;
2738}
2739
20d695a9 2740int kvm_arch_get_registers(CPUState *cs)
05330448 2741{
20d695a9 2742 X86CPU *cpu = X86_CPU(cs);
05330448
AL		 2743 int ret;
2744
20d695a9 2745 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
dbaa07c4 2746
4fadfa00 2747 ret = kvm_get_vcpu_events(cpu);
b9bec74b 2748 if (ret < 0) {
f4f1110e 2749 goto out;
b9bec74b 2750 }
4fadfa00
PH		 2751 /*
2752 * KVM_GET_MPSTATE can modify CS and RIP, call it before
2753 * KVM_GET_REGS and KVM_GET_SREGS.
2754 */
2755 ret = kvm_get_mp_state(cpu);
b9bec74b 2756 if (ret < 0) {
f4f1110e 2757 goto out;
b9bec74b 2758 }
4fadfa00 2759 ret = kvm_getput_regs(cpu, 0);
b9bec74b 2760 if (ret < 0) {
f4f1110e 2761 goto out;
b9bec74b 2762 }
4fadfa00 2763 ret = kvm_get_xsave(cpu);
b9bec74b 2764 if (ret < 0) {
f4f1110e 2765 goto out;
b9bec74b 2766 }
4fadfa00 2767 ret = kvm_get_xcrs(cpu);
b9bec74b 2768 if (ret < 0) {
f4f1110e 2769 goto out;
b9bec74b 2770 }
4fadfa00 2771 ret = kvm_get_sregs(cpu);
b9bec74b 2772 if (ret < 0) {
f4f1110e 2773 goto out;
b9bec74b 2774 }
4fadfa00 2775 ret = kvm_get_msrs(cpu);
680c1c6f 2776 if (ret < 0) {
f4f1110e 2777 goto out;
680c1c6f 2778 }
4fadfa00 2779 ret = kvm_get_apic(cpu);
b9bec74b 2780 if (ret < 0) {
f4f1110e 2781 goto out;
b9bec74b 2782 }
1bc22652 2783 ret = kvm_get_debugregs(cpu);
b9bec74b 2784 if (ret < 0) {
f4f1110e 2785 goto out;
b9bec74b 2786 }
f4f1110e
RH		 2787 ret = 0;
2788 out:
2789 cpu_sync_bndcs_hflags(&cpu->env);
2790 return ret;
05330448
AL		 2791}
2792
20d695a9 2793void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
05330448 2794{
20d695a9
AF		 2795 X86CPU *x86_cpu = X86_CPU(cpu);
2796 CPUX86State *env = &x86_cpu->env;
ce377af3
JK		 2797 int ret;
2798
276ce815 2799 /* Inject NMI */
fc12d72e
PB		 2800 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
2801 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
2802 qemu_mutex_lock_iothread();
2803 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
2804 qemu_mutex_unlock_iothread();
2805 DPRINTF("injected NMI\n");
2806 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
2807 if (ret < 0) {
2808 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
2809 strerror(-ret));
2810 }
2811 }
2812 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
2813 qemu_mutex_lock_iothread();
2814 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
2815 qemu_mutex_unlock_iothread();
2816 DPRINTF("injected SMI\n");
2817 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
2818 if (ret < 0) {
2819 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
2820 strerror(-ret));
2821 }
ce377af3 2822 }
276ce815
LJ		 2823 }
2824
15eafc2e 2825 if (!kvm_pic_in_kernel()) {
4b8523ee
JK		 2826 qemu_mutex_lock_iothread();
2827 }
2828
e0723c45
PB		 2829 /* Force the VCPU out of its inner loop to process any INIT requests
2830 * or (for userspace APIC, but it is cheap to combine the checks here)
2831 * pending TPR access reports.
2832 */
2833 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
fc12d72e
PB		 2834 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
2835 !(env->hflags & HF_SMM_MASK)) {
2836 cpu->exit_request = 1;
2837 }
2838 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
2839 cpu->exit_request = 1;
2840 }
e0723c45 2841 }
05330448 2842
15eafc2e 2843 if (!kvm_pic_in_kernel()) {
db1669bc
JK		 2844 /* Try to inject an interrupt if the guest can accept it */
2845 if (run->ready_for_interrupt_injection &&
259186a7 2846 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
db1669bc
JK		 2847 (env->eflags & IF_MASK)) {
2848 int irq;
2849
259186a7 2850 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
db1669bc
JK		 2851 irq = cpu_get_pic_interrupt(env);
2852 if (irq >= 0) {
2853 struct kvm_interrupt intr;
2854
2855 intr.irq = irq;
db1669bc 2856 DPRINTF("injected interrupt %d\n", irq);
1bc22652 2857 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
ce377af3
JK		 2858 if (ret < 0) {
2859 fprintf(stderr,
2860 "KVM: injection failed, interrupt lost (%s)\n",
2861 strerror(-ret));
2862 }
db1669bc
JK		 2863 }
2864 }
05330448 2865
db1669bc
JK		 2866 /* If we have an interrupt but the guest is not ready to receive an
2867 * interrupt, request an interrupt window exit. This will
2868 * cause a return to userspace as soon as the guest is ready to
2869 * receive interrupts. */
259186a7 2870 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
db1669bc
JK		 2871 run->request_interrupt_window = 1;
2872 } else {
2873 run->request_interrupt_window = 0;
2874 }
2875
2876 DPRINTF("setting tpr\n");
02e51483 2877 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
4b8523ee
JK		 2878
2879 qemu_mutex_unlock_iothread();
db1669bc 2880 }
05330448
AL		 2881}
2882
4c663752 2883MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
05330448 2884{
20d695a9
AF		 2885 X86CPU *x86_cpu = X86_CPU(cpu);
2886 CPUX86State *env = &x86_cpu->env;
2887
fc12d72e
PB		 2888 if (run->flags & KVM_RUN_X86_SMM) {
2889 env->hflags |= HF_SMM_MASK;
2890 } else {
f5c052b9 2891 env->hflags &= ~HF_SMM_MASK;
fc12d72e 2892 }
b9bec74b 2893 if (run->if_flag) {
05330448 2894 env->eflags |= IF_MASK;
b9bec74b 2895 } else {
05330448 2896 env->eflags &= ~IF_MASK;
b9bec74b 2897 }
4b8523ee
JK		 2898
2899 /* We need to protect the apic state against concurrent accesses from
2900 * different threads in case the userspace irqchip is used. */
2901 if (!kvm_irqchip_in_kernel()) {
2902 qemu_mutex_lock_iothread();
2903 }
02e51483
CF		 2904 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
2905 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
4b8523ee
JK		 2906 if (!kvm_irqchip_in_kernel()) {
2907 qemu_mutex_unlock_iothread();
2908 }
f794aa4a 2909 return cpu_get_mem_attrs(env);
05330448
AL		 2910}
2911
20d695a9 2912int kvm_arch_process_async_events(CPUState *cs)
0af691d7 2913{
20d695a9
AF		 2914 X86CPU *cpu = X86_CPU(cs);
2915 CPUX86State *env = &cpu->env;
232fc23b 2916
259186a7 2917 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
ab443475
JK		 2918 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
2919 assert(env->mcg_cap);
2920
259186a7 2921 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
ab443475 2922
dd1750d7 2923 kvm_cpu_synchronize_state(cs);
ab443475
JK		 2924
2925 if (env->exception_injected == EXCP08_DBLE) {
2926 /* this means triple fault */
cf83f140 2927 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
fcd7d003 2928 cs->exit_request = 1;
ab443475
JK		 2929 return 0;
2930 }
2931 env->exception_injected = EXCP12_MCHK;
2932 env->has_error_code = 0;
2933
259186a7 2934 cs->halted = 0;
ab443475
JK		 2935 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
2936 env->mp_state = KVM_MP_STATE_RUNNABLE;
2937 }
2938 }
2939
fc12d72e
PB		 2940 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
2941 !(env->hflags & HF_SMM_MASK)) {
e0723c45
PB		 2942 kvm_cpu_synchronize_state(cs);
2943 do_cpu_init(cpu);
2944 }
2945
db1669bc
JK		 2946 if (kvm_irqchip_in_kernel()) {
2947 return 0;
2948 }
2949
259186a7
AF		 2950 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2951 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
02e51483 2952 apic_poll_irq(cpu->apic_state);
5d62c43a 2953 }
259186a7 2954 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
4601f7b0 2955 (env->eflags & IF_MASK)) ||
259186a7
AF		 2956 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2957 cs->halted = 0;
6792a57b 2958 }
259186a7 2959 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
dd1750d7 2960 kvm_cpu_synchronize_state(cs);
232fc23b 2961 do_cpu_sipi(cpu);
0af691d7 2962 }
259186a7
AF		 2963 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
2964 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
dd1750d7 2965 kvm_cpu_synchronize_state(cs);
02e51483 2966 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
d362e757
JK		 2967 env->tpr_access_type);
2968 }
0af691d7 2969
259186a7 2970 return cs->halted;
0af691d7
MT		 2971}
2972
839b5630 2973static int kvm_handle_halt(X86CPU *cpu)
05330448 2974{
259186a7 2975 CPUState *cs = CPU(cpu);
839b5630
AF		 2976 CPUX86State *env = &cpu->env;
2977
259186a7 2978 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
05330448 2979 (env->eflags & IF_MASK)) &&
259186a7
AF		 2980 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2981 cs->halted = 1;
bb4ea393 2982 return EXCP_HLT;
05330448
AL		 2983 }
2984
bb4ea393 2985 return 0;
05330448
AL		 2986}
2987
f7575c96 2988static int kvm_handle_tpr_access(X86CPU *cpu)
d362e757 2989{
f7575c96
AF		 2990 CPUState *cs = CPU(cpu);
2991 struct kvm_run *run = cs->kvm_run;
d362e757 2992
02e51483 2993 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
d362e757
JK		 2994 run->tpr_access.is_write ? TPR_ACCESS_WRITE
2995 : TPR_ACCESS_READ);
2996 return 1;
2997}
2998
f17ec444 2999int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9 3000{
38972938 3001 static const uint8_t int3 = 0xcc;
64bf3f4e 3002
f17ec444
AF		 3003 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
3004 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
e22a25c9 3005 return -EINVAL;
b9bec74b 3006 }
e22a25c9
AL		 3007 return 0;
3008}
3009
f17ec444 3010int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9
AL		 3011{
3012 uint8_t int3;
3013
f17ec444
AF		 3014 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
3015 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
e22a25c9 3016 return -EINVAL;
b9bec74b 3017 }
e22a25c9
AL		 3018 return 0;
3019}
3020
3021static struct {
3022 target_ulong addr;
3023 int len;
3024 int type;
3025} hw_breakpoint[4];
3026
3027static int nb_hw_breakpoint;
3028
3029static int find_hw_breakpoint(target_ulong addr, int len, int type)
3030{
3031 int n;
3032
b9bec74b 3033 for (n = 0; n < nb_hw_breakpoint; n++) {
e22a25c9 3034 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
b9bec74b 3035 (hw_breakpoint[n].len == len || len == -1)) {
e22a25c9 3036 return n;
b9bec74b
JK		 3037 }
3038 }
e22a25c9
AL		 3039 return -1;
3040}
3041
3042int kvm_arch_insert_hw_breakpoint(target_ulong addr,
3043 target_ulong len, int type)
3044{
3045 switch (type) {
3046 case GDB_BREAKPOINT_HW:
3047 len = 1;
3048 break;
3049 case GDB_WATCHPOINT_WRITE:
3050 case GDB_WATCHPOINT_ACCESS:
3051 switch (len) {
3052 case 1:
3053 break;
3054 case 2:
3055 case 4:
3056 case 8:
b9bec74b 3057 if (addr & (len - 1)) {
e22a25c9 3058 return -EINVAL;
b9bec74b 3059 }
e22a25c9
AL		 3060 break;
3061 default:
3062 return -EINVAL;
3063 }
3064 break;
3065 default:
3066 return -ENOSYS;
3067 }
3068
b9bec74b 3069 if (nb_hw_breakpoint == 4) {
e22a25c9 3070 return -ENOBUFS;
b9bec74b
JK		 3071 }
3072 if (find_hw_breakpoint(addr, len, type) >= 0) {
e22a25c9 3073 return -EEXIST;
b9bec74b 3074 }
e22a25c9
AL		 3075 hw_breakpoint[nb_hw_breakpoint].addr = addr;
3076 hw_breakpoint[nb_hw_breakpoint].len = len;
3077 hw_breakpoint[nb_hw_breakpoint].type = type;
3078 nb_hw_breakpoint++;
3079
3080 return 0;
3081}
3082
3083int kvm_arch_remove_hw_breakpoint(target_ulong addr,
3084 target_ulong len, int type)
3085{
3086 int n;
3087
3088 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
b9bec74b 3089 if (n < 0) {
e22a25c9 3090 return -ENOENT;
b9bec74b 3091 }
e22a25c9
AL		 3092 nb_hw_breakpoint--;
3093 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
3094
3095 return 0;
3096}
3097
3098void kvm_arch_remove_all_hw_breakpoints(void)
3099{
3100 nb_hw_breakpoint = 0;
3101}
3102
3103static CPUWatchpoint hw_watchpoint;
3104
a60f24b5 3105static int kvm_handle_debug(X86CPU *cpu,
48405526 3106 struct kvm_debug_exit_arch *arch_info)
e22a25c9 3107{
ed2803da 3108 CPUState *cs = CPU(cpu);
a60f24b5 3109 CPUX86State *env = &cpu->env;
f2574737 3110 int ret = 0;
e22a25c9
AL		 3111 int n;
3112
3113 if (arch_info->exception == 1) {
3114 if (arch_info->dr6 & (1 << 14)) {
ed2803da 3115 if (cs->singlestep_enabled) {
f2574737 3116 ret = EXCP_DEBUG;
b9bec74b 3117 }
e22a25c9 3118 } else {
b9bec74b
JK		 3119 for (n = 0; n < 4; n++) {
3120 if (arch_info->dr6 & (1 << n)) {
e22a25c9
AL		 3121 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
3122 case 0x0:
f2574737 3123 ret = EXCP_DEBUG;
e22a25c9
AL		 3124 break;
3125 case 0x1:
f2574737 3126 ret = EXCP_DEBUG;
ff4700b0 3127 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 3128 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3129 hw_watchpoint.flags = BP_MEM_WRITE;
3130 break;
3131 case 0x3:
f2574737 3132 ret = EXCP_DEBUG;
ff4700b0 3133 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 3134 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3135 hw_watchpoint.flags = BP_MEM_ACCESS;
3136 break;
3137 }
b9bec74b
JK		 3138 }
3139 }
e22a25c9 3140 }
ff4700b0 3141 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
f2574737 3142 ret = EXCP_DEBUG;
b9bec74b 3143 }
f2574737 3144 if (ret == 0) {
ff4700b0 3145 cpu_synchronize_state(cs);
48405526 3146 assert(env->exception_injected == -1);
b0b1d690 3147
f2574737 3148 /* pass to guest */
48405526
BS		 3149 env->exception_injected = arch_info->exception;
3150 env->has_error_code = 0;
b0b1d690 3151 }
e22a25c9 3152
f2574737 3153 return ret;
e22a25c9
AL		 3154}
3155
20d695a9 3156void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
e22a25c9
AL		 3157{
3158 const uint8_t type_code[] = {
3159 [GDB_BREAKPOINT_HW] = 0x0,
3160 [GDB_WATCHPOINT_WRITE] = 0x1,
3161 [GDB_WATCHPOINT_ACCESS] = 0x3
3162 };
3163 const uint8_t len_code[] = {
3164 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
3165 };
3166 int n;
3167
a60f24b5 3168 if (kvm_sw_breakpoints_active(cpu)) {
e22a25c9 3169 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
b9bec74b 3170 }
e22a25c9
AL		 3171 if (nb_hw_breakpoint > 0) {
3172 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
3173 dbg->arch.debugreg[7] = 0x0600;
3174 for (n = 0; n < nb_hw_breakpoint; n++) {
3175 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
3176 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
3177 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
95c077c9 3178 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
e22a25c9
AL		 3179 }
3180 }
3181}
4513d923 3182
2a4dac83
JK		 3183static bool host_supports_vmx(void)
3184{
3185 uint32_t ecx, unused;
3186
3187 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
3188 return ecx & CPUID_EXT_VMX;
3189}
3190
3191#define VMX_INVALID_GUEST_STATE 0x80000021
3192
20d695a9 3193int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2a4dac83 3194{
20d695a9 3195 X86CPU *cpu = X86_CPU(cs);
2a4dac83
JK		 3196 uint64_t code;
3197 int ret;
3198
3199 switch (run->exit_reason) {
3200 case KVM_EXIT_HLT:
3201 DPRINTF("handle_hlt\n");
4b8523ee 3202 qemu_mutex_lock_iothread();
839b5630 3203 ret = kvm_handle_halt(cpu);
4b8523ee 3204 qemu_mutex_unlock_iothread();
2a4dac83
JK		 3205 break;
3206 case KVM_EXIT_SET_TPR:
3207 ret = 0;
3208 break;
d362e757 3209 case KVM_EXIT_TPR_ACCESS:
4b8523ee 3210 qemu_mutex_lock_iothread();
f7575c96 3211 ret = kvm_handle_tpr_access(cpu);
4b8523ee 3212 qemu_mutex_unlock_iothread();
d362e757 3213 break;
2a4dac83
JK		 3214 case KVM_EXIT_FAIL_ENTRY:
3215 code = run->fail_entry.hardware_entry_failure_reason;
3216 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
3217 code);
3218 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
3219 fprintf(stderr,
12619721 3220 "\nIf you're running a guest on an Intel machine without "
2a4dac83
JK		 3221 "unrestricted mode\n"
3222 "support, the failure can be most likely due to the guest "
3223 "entering an invalid\n"
3224 "state for Intel VT. For example, the guest maybe running "
3225 "in big real mode\n"
3226 "which is not supported on less recent Intel processors."
3227 "\n\n");
3228 }
3229 ret = -1;
3230 break;
3231 case KVM_EXIT_EXCEPTION:
3232 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
3233 run->ex.exception, run->ex.error_code);
3234 ret = -1;
3235 break;
f2574737
JK		 3236 case KVM_EXIT_DEBUG:
3237 DPRINTF("kvm_exit_debug\n");
4b8523ee 3238 qemu_mutex_lock_iothread();
a60f24b5 3239 ret = kvm_handle_debug(cpu, &run->debug.arch);
4b8523ee 3240 qemu_mutex_unlock_iothread();
f2574737 3241 break;
50efe82c
AS		 3242 case KVM_EXIT_HYPERV:
3243 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
3244 break;
15eafc2e
PB		 3245 case KVM_EXIT_IOAPIC_EOI:
3246 ioapic_eoi_broadcast(run->eoi.vector);
3247 ret = 0;
3248 break;
2a4dac83
JK		 3249 default:
3250 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
3251 ret = -1;
3252 break;
3253 }
3254
3255 return ret;
3256}
3257
20d695a9 3258bool kvm_arch_stop_on_emulation_error(CPUState *cs)
4513d923 3259{
20d695a9
AF		 3260 X86CPU *cpu = X86_CPU(cs);
3261 CPUX86State *env = &cpu->env;
3262
dd1750d7 3263 kvm_cpu_synchronize_state(cs);
b9bec74b
JK		 3264 return !(env->cr[0] & CR0_PE_MASK) ||
3265 ((env->segs[R_CS].selector & 3) != 3);
4513d923 3266}
84b058d7
JK		 3267
3268void kvm_arch_init_irq_routing(KVMState *s)
3269{
3270 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
3271 /* If kernel can't do irq routing, interrupt source
3272 * override 0->2 cannot be set up as required by HPET.
3273 * So we have to disable it.
3274 */
3275 no_hpet = 1;
3276 }
cc7e0ddf 3277 /* We know at this point that we're using the in-kernel
614e41bc 3278 * irqchip, so we can use irqfds, and on x86 we know
f3e1bed8 3279 * we can use msi via irqfd and GSI routing.
cc7e0ddf 3280 */
614e41bc 3281 kvm_msi_via_irqfd_allowed = true;
f3e1bed8 3282 kvm_gsi_routing_allowed = true;
15eafc2e
PB		 3283
3284 if (kvm_irqchip_is_split()) {
3285 int i;
3286
3287 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
3288 MSI routes for signaling interrupts to the local apics. */
3289 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
d1f6af6a 3290 if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
15eafc2e
PB		 3291 error_report("Could not enable split IRQ mode.");
3292 exit(1);
3293 }
3294 }
3295 }
3296}
3297
3298int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
3299{
3300 int ret;
3301 if (machine_kernel_irqchip_split(ms)) {
3302 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
3303 if (ret) {
df3c286c 3304 error_report("Could not enable split irqchip mode: %s",
15eafc2e
PB		 3305 strerror(-ret));
3306 exit(1);
3307 } else {
3308 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
3309 kvm_split_irqchip = true;
3310 return 1;
3311 }
3312 } else {
3313 return 0;
3314 }
84b058d7 3315}
b139bd30
JK		 3316
3317/* Classic KVM device assignment interface. Will remain x86 only. */
3318int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
3319 uint32_t flags, uint32_t *dev_id)
3320{
3321 struct kvm_assigned_pci_dev dev_data = {
3322 .segnr = dev_addr->domain,
3323 .busnr = dev_addr->bus,
3324 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
3325 .flags = flags,
3326 };
3327 int ret;
3328
3329 dev_data.assigned_dev_id =
3330 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
3331
3332 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
3333 if (ret < 0) {
3334 return ret;
3335 }
3336
3337 *dev_id = dev_data.assigned_dev_id;
3338
3339 return 0;
3340}
3341
3342int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
3343{
3344 struct kvm_assigned_pci_dev dev_data = {
3345 .assigned_dev_id = dev_id,
3346 };
3347
3348 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
3349}
3350
3351static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
3352 uint32_t irq_type, uint32_t guest_irq)
3353{
3354 struct kvm_assigned_irq assigned_irq = {
3355 .assigned_dev_id = dev_id,
3356 .guest_irq = guest_irq,
3357 .flags = irq_type,
3358 };
3359
3360 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
3361 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
3362 } else {
3363 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
3364 }
3365}
3366
3367int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
3368 uint32_t guest_irq)
3369{
3370 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
3371 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
3372
3373 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
3374}
3375
3376int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
3377{
3378 struct kvm_assigned_pci_dev dev_data = {
3379 .assigned_dev_id = dev_id,
3380 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
3381 };
3382
3383 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
3384}
3385
3386static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
3387 uint32_t type)
3388{
3389 struct kvm_assigned_irq assigned_irq = {
3390 .assigned_dev_id = dev_id,
3391 .flags = type,
3392 };
3393
3394 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
3395}
3396
3397int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
3398{
3399 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
3400 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
3401}
3402
3403int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
3404{
3405 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
3406 KVM_DEV_IRQ_GUEST_MSI, virq);
3407}
3408
3409int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
3410{
3411 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
3412 KVM_DEV_IRQ_HOST_MSI);
3413}
3414
3415bool kvm_device_msix_supported(KVMState *s)
3416{
3417 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
3418 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
3419 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
3420}
3421
3422int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
3423 uint32_t nr_vectors)
3424{
3425 struct kvm_assigned_msix_nr msix_nr = {
3426 .assigned_dev_id = dev_id,
3427 .entry_nr = nr_vectors,
3428 };
3429
3430 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
3431}
3432
3433int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
3434 int virq)
3435{
3436 struct kvm_assigned_msix_entry msix_entry = {
3437 .assigned_dev_id = dev_id,
3438 .gsi = virq,
3439 .entry = vector,
3440 };
3441
3442 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
3443}
3444
3445int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
3446{
3447 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
3448 KVM_DEV_IRQ_GUEST_MSIX, 0);
3449}
3450
3451int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
3452{
3453 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
3454 KVM_DEV_IRQ_HOST_MSIX);
3455}
9e03a040
FB		 3456
3457int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
dc9f06ca 3458 uint64_t address, uint32_t data, PCIDevice *dev)
9e03a040 3459{
8b5ed7df
PX		 3460 X86IOMMUState *iommu = x86_iommu_get_default();
3461
3462 if (iommu) {
3463 int ret;
3464 MSIMessage src, dst;
3465 X86IOMMUClass *class = X86_IOMMU_GET_CLASS(iommu);
3466
3467 src.address = route->u.msi.address_hi;
3468 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
3469 src.address |= route->u.msi.address_lo;
3470 src.data = route->u.msi.data;
3471
3472 ret = class->int_remap(iommu, &src, &dst, dev ? \
3473 pci_requester_id(dev) : \
3474 X86_IOMMU_SID_INVALID);
3475 if (ret) {
3476 trace_kvm_x86_fixup_msi_error(route->gsi);
3477 return 1;
3478 }
3479
3480 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
3481 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
3482 route->u.msi.data = dst.data;
3483 }
3484
9e03a040
FB		 3485 return 0;
3486}
1850b6b7 3487
38d87493
PX		 3488typedef struct MSIRouteEntry MSIRouteEntry;
3489
3490struct MSIRouteEntry {
3491 PCIDevice *dev; /* Device pointer */
3492 int vector; /* MSI/MSIX vector index */
3493 int virq; /* Virtual IRQ index */
3494 QLIST_ENTRY(MSIRouteEntry) list;
3495};
3496
3497/* List of used GSI routes */
3498static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
3499 QLIST_HEAD_INITIALIZER(msi_route_list);
3500
e1d4fb2d
PX		 3501static void kvm_update_msi_routes_all(void *private, bool global,
3502 uint32_t index, uint32_t mask)
3503{
3504 int cnt = 0;
3505 MSIRouteEntry *entry;
3506 MSIMessage msg;
fd563564
PX		 3507 PCIDevice *dev;
3508
e1d4fb2d
PX		 3509 /* TODO: explicit route update */
3510 QLIST_FOREACH(entry, &msi_route_list, list) {
3511 cnt++;
fd563564
PX		 3512 dev = entry->dev;
3513 if (!msix_enabled(dev) && !msi_enabled(dev)) {
3514 continue;
3515 }
3516 msg = pci_get_msi_message(dev, entry->vector);
3517 kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev);
e1d4fb2d 3518 }
3f1fea0f 3519 kvm_irqchip_commit_routes(kvm_state);
e1d4fb2d
PX		 3520 trace_kvm_x86_update_msi_routes(cnt);
3521}
3522
38d87493
PX		 3523int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
3524 int vector, PCIDevice *dev)
3525{
e1d4fb2d 3526 static bool notify_list_inited = false;
38d87493
PX		 3527 MSIRouteEntry *entry;
3528
3529 if (!dev) {
3530 /* These are (possibly) IOAPIC routes only used for split
3531 * kernel irqchip mode, while what we are housekeeping are
3532 * PCI devices only. */
3533 return 0;
3534 }
3535
3536 entry = g_new0(MSIRouteEntry, 1);
3537 entry->dev = dev;
3538 entry->vector = vector;
3539 entry->virq = route->gsi;
3540 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
3541
3542 trace_kvm_x86_add_msi_route(route->gsi);
e1d4fb2d
PX		 3543
3544 if (!notify_list_inited) {
3545 /* For the first time we do add route, add ourselves into
3546 * IOMMU's IEC notify list if needed. */
3547 X86IOMMUState *iommu = x86_iommu_get_default();
3548 if (iommu) {
3549 x86_iommu_iec_register_notifier(iommu,
3550 kvm_update_msi_routes_all,
3551 NULL);
3552 }
3553 notify_list_inited = true;
3554 }
38d87493
PX		 3555 return 0;
3556}
3557
3558int kvm_arch_release_virq_post(int virq)
3559{
3560 MSIRouteEntry *entry, *next;
3561 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
3562 if (entry->virq == virq) {
3563 trace_kvm_x86_remove_msi_route(virq);
3564 QLIST_REMOVE(entry, list);
01960e6d 3565 g_free(entry);
38d87493
PX		 3566 break;
3567 }
3568 }
9e03a040
FB		 3569 return 0;
3570}
1850b6b7
EA		 3571
3572int kvm_arch_msi_data_to_gsi(uint32_t data)
3573{
3574 abort();
3575}
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