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Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging
[qemu.git] / target / i386 / kvm.c
CommitLineData
05330448
AL		 1/*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <[email protected]>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
b6a0aa05 15#include "qemu/osdep.h"
da34e65c 16#include "qapi/error.h"
05330448 17#include <sys/ioctl.h>
25d2e361 18#include <sys/utsname.h>
05330448
AL		 19
20#include <linux/kvm.h>
5802e066 21#include <linux/kvm_para.h>
05330448
AL		 22
23#include "qemu-common.h"
33c11879 24#include "cpu.h"
9c17d615 25#include "sysemu/sysemu.h"
b3946626 26#include "sysemu/hw_accel.h"
6410848b 27#include "sysemu/kvm_int.h"
1d31f66b 28#include "kvm_i386.h"
50efe82c 29#include "hyperv.h"
5e953812 30#include "hyperv-proto.h"
50efe82c 31
022c62cb 32#include "exec/gdbstub.h"
1de7afc9
PB		 33#include "qemu/host-utils.h"
34#include "qemu/config-file.h"
1c4a55db 35#include "qemu/error-report.h"
0d09e41a
PB		 36#include "hw/i386/pc.h"
37#include "hw/i386/apic.h"
e0723c45
PB		 38#include "hw/i386/apic_internal.h"
39#include "hw/i386/apic-msidef.h"
8b5ed7df 40#include "hw/i386/intel_iommu.h"
e1d4fb2d 41#include "hw/i386/x86-iommu.h"
50efe82c 42
022c62cb 43#include "exec/ioport.h"
a2cb15b0 44#include "hw/pci/pci.h"
15eafc2e 45#include "hw/pci/msi.h"
fd563564 46#include "hw/pci/msix.h"
795c40b8 47#include "migration/blocker.h"
4c663752 48#include "exec/memattrs.h"
8b5ed7df 49#include "trace.h"
05330448
AL		 50
51//#define DEBUG_KVM
52
53#ifdef DEBUG_KVM
8c0d577e 54#define DPRINTF(fmt, ...) \
05330448
AL		 55 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
56#else
8c0d577e 57#define DPRINTF(fmt, ...) \
05330448
AL		 58 do { } while (0)
59#endif
60
1a03675d
GC		 61#define MSR_KVM_WALL_CLOCK 0x11
62#define MSR_KVM_SYSTEM_TIME 0x12
63
d1138251
EH		 64/* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
65 * 255 kvm_msr_entry structs */
66#define MSR_BUF_SIZE 4096
d71b62a1 67
94a8d39a
JK		 68const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
69 KVM_CAP_INFO(SET_TSS_ADDR),
70 KVM_CAP_INFO(EXT_CPUID),
71 KVM_CAP_INFO(MP_STATE),
72 KVM_CAP_LAST_INFO
73};
25d2e361 74
c3a3a7d3
JK		 75static bool has_msr_star;
76static bool has_msr_hsave_pa;
c9b8f6b6 77static bool has_msr_tsc_aux;
f28558d3 78static bool has_msr_tsc_adjust;
aa82ba54 79static bool has_msr_tsc_deadline;
df67696e 80static bool has_msr_feature_control;
21e87c46 81static bool has_msr_misc_enable;
fc12d72e 82static bool has_msr_smbase;
79e9ebeb 83static bool has_msr_bndcfgs;
25d2e361 84static int lm_capable_kernel;
7bc3d711 85static bool has_msr_hv_hypercall;
f2a53c9e 86static bool has_msr_hv_crash;
744b8a94 87static bool has_msr_hv_reset;
8c145d7c 88static bool has_msr_hv_vpindex;
46eb8f98 89static bool has_msr_hv_runtime;
866eea9a 90static bool has_msr_hv_synic;
ff99aa64 91static bool has_msr_hv_stimer;
d72bc7f6 92static bool has_msr_hv_frequencies;
18cd2c17 93static bool has_msr_xss;
b827df58 94
0d894367
PB		 95static bool has_msr_architectural_pmu;
96static uint32_t num_architectural_pmu_counters;
97
28143b40
TH		 98static int has_xsave;
99static int has_xcrs;
100static int has_pit_state2;
101
87f8b626
AR		 102static bool has_msr_mcg_ext_ctl;
103
494e95e9
CP		 104static struct kvm_cpuid2 *cpuid_cache;
105
28143b40
TH		 106int kvm_has_pit_state2(void)
107{
108 return has_pit_state2;
109}
110
355023f2
PB		 111bool kvm_has_smm(void)
112{
113 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
114}
115
6053a86f
MT		 116bool kvm_has_adjust_clock_stable(void)
117{
118 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
119
120 return (ret == KVM_CLOCK_TSC_STABLE);
121}
122
1d31f66b
PM		 123bool kvm_allows_irq0_override(void)
124{
125 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
126}
127
fb506e70
RK		 128static bool kvm_x2apic_api_set_flags(uint64_t flags)
129{
130 KVMState *s = KVM_STATE(current_machine->accelerator);
131
132 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
133}
134
e391c009 135#define MEMORIZE(fn, _result) \
2a138ec3 136 ({ \
2a138ec3
RK		 137 static bool _memorized; \
138 \
139 if (_memorized) { \
140 return _result; \
141 } \
142 _memorized = true; \
143 _result = fn; \
144 })
145
e391c009
IM		 146static bool has_x2apic_api;
147
148bool kvm_has_x2apic_api(void)
149{
150 return has_x2apic_api;
151}
152
fb506e70
RK		 153bool kvm_enable_x2apic(void)
154{
2a138ec3
RK		 155 return MEMORIZE(
156 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
e391c009
IM		 157 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
158 has_x2apic_api);
fb506e70
RK		 159}
160
0fd7e098
LL		 161static int kvm_get_tsc(CPUState *cs)
162{
163 X86CPU *cpu = X86_CPU(cs);
164 CPUX86State *env = &cpu->env;
165 struct {
166 struct kvm_msrs info;
167 struct kvm_msr_entry entries[1];
168 } msr_data;
169 int ret;
170
171 if (env->tsc_valid) {
172 return 0;
173 }
174
175 msr_data.info.nmsrs = 1;
176 msr_data.entries[0].index = MSR_IA32_TSC;
177 env->tsc_valid = !runstate_is_running();
178
179 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
180 if (ret < 0) {
181 return ret;
182 }
183
48e1a45c 184 assert(ret == 1);
0fd7e098
LL		 185 env->tsc = msr_data.entries[0].data;
186 return 0;
187}
188
14e6fe12 189static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
0fd7e098 190{
0fd7e098
LL		 191 kvm_get_tsc(cpu);
192}
193
194void kvm_synchronize_all_tsc(void)
195{
196 CPUState *cpu;
197
198 if (kvm_enabled()) {
199 CPU_FOREACH(cpu) {
14e6fe12 200 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
0fd7e098
LL		 201 }
202 }
203}
204
b827df58
AK		 205static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
206{
207 struct kvm_cpuid2 *cpuid;
208 int r, size;
209
210 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
e42a92ae 211 cpuid = g_malloc0(size);
b827df58
AK		 212 cpuid->nent = max;
213 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
76ae317f
MM		 214 if (r == 0 && cpuid->nent >= max) {
215 r = -E2BIG;
216 }
b827df58
AK		 217 if (r < 0) {
218 if (r == -E2BIG) {
7267c094 219 g_free(cpuid);
b827df58
AK		 220 return NULL;
221 } else {
222 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
223 strerror(-r));
224 exit(1);
225 }
226 }
227 return cpuid;
228}
229
dd87f8a6
EH		 230/* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
231 * for all entries.
232 */
233static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
234{
235 struct kvm_cpuid2 *cpuid;
236 int max = 1;
494e95e9
CP		 237
238 if (cpuid_cache != NULL) {
239 return cpuid_cache;
240 }
dd87f8a6
EH		 241 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
242 max *= 2;
243 }
494e95e9 244 cpuid_cache = cpuid;
dd87f8a6
EH		 245 return cpuid;
246}
247
a443bc34 248static const struct kvm_para_features {
0c31b744
GC		 249 int cap;
250 int feature;
251} para_features[] = {
252 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
253 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
254 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
0c31b744 255 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
0c31b744
GC		 256};
257
ba9bc59e 258static int get_para_features(KVMState *s)
0c31b744
GC		 259{
260 int i, features = 0;
261
8e03c100 262 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
ba9bc59e 263 if (kvm_check_extension(s, para_features[i].cap)) {
0c31b744
GC		 264 features |= (1 << para_features[i].feature);
265 }
266 }
267
268 return features;
269}
0c31b744 270
40e80ee4
EH		 271static bool host_tsx_blacklisted(void)
272{
273 int family, model, stepping;\
274 char vendor[CPUID_VENDOR_SZ + 1];
275
276 host_vendor_fms(vendor, &family, &model, &stepping);
277
278 /* Check if we are running on a Haswell host known to have broken TSX */
279 return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
280 (family == 6) &&
281 ((model == 63 && stepping < 4) ||
282 model == 60 || model == 69 || model == 70);
283}
0c31b744 284
829ae2f9
EH		 285/* Returns the value for a specific register on the cpuid entry
286 */
287static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
288{
289 uint32_t ret = 0;
290 switch (reg) {
291 case R_EAX:
292 ret = entry->eax;
293 break;
294 case R_EBX:
295 ret = entry->ebx;
296 break;
297 case R_ECX:
298 ret = entry->ecx;
299 break;
300 case R_EDX:
301 ret = entry->edx;
302 break;
303 }
304 return ret;
305}
306
4fb73f1d
EH		 307/* Find matching entry for function/index on kvm_cpuid2 struct
308 */
309static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
310 uint32_t function,
311 uint32_t index)
312{
313 int i;
314 for (i = 0; i < cpuid->nent; ++i) {
315 if (cpuid->entries[i].function == function &&
316 cpuid->entries[i].index == index) {
317 return &cpuid->entries[i];
318 }
319 }
320 /* not found: */
321 return NULL;
322}
323
ba9bc59e 324uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
c958a8bd 325 uint32_t index, int reg)
b827df58
AK		 326{
327 struct kvm_cpuid2 *cpuid;
b827df58
AK		 328 uint32_t ret = 0;
329 uint32_t cpuid_1_edx;
8c723b79 330 bool found = false;
b827df58 331
dd87f8a6 332 cpuid = get_supported_cpuid(s);
b827df58 333
4fb73f1d
EH		 334 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
335 if (entry) {
336 found = true;
337 ret = cpuid_entry_get_reg(entry, reg);
b827df58
AK		 338 }
339
7b46e5ce
EH		 340 /* Fixups for the data returned by KVM, below */
341
c2acb022
EH		 342 if (function == 1 && reg == R_EDX) {
343 /* KVM before 2.6.30 misreports the following features */
344 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
84bd945c
EH		 345 } else if (function == 1 && reg == R_ECX) {
346 /* We can set the hypervisor flag, even if KVM does not return it on
347 * GET_SUPPORTED_CPUID
348 */
349 ret |= CPUID_EXT_HYPERVISOR;
ac67ee26
EH		 350 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
351 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
352 * and the irqchip is in the kernel.
353 */
354 if (kvm_irqchip_in_kernel() &&
355 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
356 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
357 }
41e5e76d
EH		 358
359 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
360 * without the in-kernel irqchip
361 */
362 if (!kvm_irqchip_in_kernel()) {
363 ret &= ~CPUID_EXT_X2APIC;
b827df58 364 }
28b8e4d0
JK		 365 } else if (function == 6 && reg == R_EAX) {
366 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
40e80ee4
EH		 367 } else if (function == 7 && index == 0 && reg == R_EBX) {
368 if (host_tsx_blacklisted()) {
369 ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
370 }
c2acb022
EH		 371 } else if (function == 0x80000001 && reg == R_EDX) {
372 /* On Intel, kvm returns cpuid according to the Intel spec,
373 * so add missing bits according to the AMD spec:
374 */
375 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
376 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
64877477
EH		 377 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
378 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
379 * be enabled without the in-kernel irqchip
380 */
381 if (!kvm_irqchip_in_kernel()) {
382 ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
383 }
b827df58
AK		 384 }
385
0c31b744 386 /* fallback for older kernels */
8c723b79 387 if ((function == KVM_CPUID_FEATURES) && !found) {
ba9bc59e 388 ret = get_para_features(s);
b9bec74b 389 }
0c31b744
GC		 390
391 return ret;
bb0300dc 392}
bb0300dc 393
3c85e74f
HY		 394typedef struct HWPoisonPage {
395 ram_addr_t ram_addr;
396 QLIST_ENTRY(HWPoisonPage) list;
397} HWPoisonPage;
398
399static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
400 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
401
402static void kvm_unpoison_all(void *param)
403{
404 HWPoisonPage *page, *next_page;
405
406 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
407 QLIST_REMOVE(page, list);
408 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
7267c094 409 g_free(page);
3c85e74f
HY		 410 }
411}
412
3c85e74f
HY		 413static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
414{
415 HWPoisonPage *page;
416
417 QLIST_FOREACH(page, &hwpoison_page_list, list) {
418 if (page->ram_addr == ram_addr) {
419 return;
420 }
421 }
ab3ad07f 422 page = g_new(HWPoisonPage, 1);
3c85e74f
HY		 423 page->ram_addr = ram_addr;
424 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
425}
426
e7701825
MT		 427static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
428 int *max_banks)
429{
430 int r;
431
14a09518 432 r = kvm_check_extension(s, KVM_CAP_MCE);
e7701825
MT		 433 if (r > 0) {
434 *max_banks = r;
435 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
436 }
437 return -ENOSYS;
438}
439
bee615d4 440static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
e7701825 441{
87f8b626 442 CPUState *cs = CPU(cpu);
bee615d4 443 CPUX86State *env = &cpu->env;
c34d440a
JK		 444 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
445 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
446 uint64_t mcg_status = MCG_STATUS_MCIP;
87f8b626 447 int flags = 0;
e7701825 448
c34d440a
JK		 449 if (code == BUS_MCEERR_AR) {
450 status |= MCI_STATUS_AR | 0x134;
451 mcg_status |= MCG_STATUS_EIPV;
452 } else {
453 status |= 0xc0;
454 mcg_status |= MCG_STATUS_RIPV;
419fb20a 455 }
87f8b626
AR		 456
457 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
458 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
459 * guest kernel back into env->mcg_ext_ctl.
460 */
461 cpu_synchronize_state(cs);
462 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
463 mcg_status |= MCG_STATUS_LMCE;
464 flags = 0;
465 }
466
8c5cf3b6 467 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
87f8b626 468 (MCM_ADDR_PHYS << 6) | 0xc, flags);
419fb20a 469}
419fb20a
JK		 470
471static void hardware_memory_error(void)
472{
473 fprintf(stderr, "Hardware memory error!\n");
474 exit(1);
475}
476
2ae41db2 477void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
419fb20a 478{
20d695a9
AF		 479 X86CPU *cpu = X86_CPU(c);
480 CPUX86State *env = &cpu->env;
419fb20a 481 ram_addr_t ram_addr;
a8170e5e 482 hwaddr paddr;
419fb20a 483
4d39892c
PB		 484 /* If we get an action required MCE, it has been injected by KVM
485 * while the VM was running. An action optional MCE instead should
486 * be coming from the main thread, which qemu_init_sigbus identifies
487 * as the "early kill" thread.
488 */
a16fc07e 489 assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
20e0ff59 490
20e0ff59 491 if ((env->mcg_cap & MCG_SER_P) && addr) {
07bdaa41 492 ram_addr = qemu_ram_addr_from_host(addr);
20e0ff59
PB		 493 if (ram_addr != RAM_ADDR_INVALID &&
494 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
495 kvm_hwpoison_page_add(ram_addr);
496 kvm_mce_inject(cpu, paddr, code);
2ae41db2 497 return;
419fb20a 498 }
20e0ff59
PB		 499
500 fprintf(stderr, "Hardware memory error for memory used by "
501 "QEMU itself instead of guest system!\n");
419fb20a 502 }
20e0ff59
PB		 503
504 if (code == BUS_MCEERR_AR) {
505 hardware_memory_error();
506 }
507
508 /* Hope we are lucky for AO MCE */
419fb20a
JK		 509}
510
1bc22652 511static int kvm_inject_mce_oldstyle(X86CPU *cpu)
ab443475 512{
1bc22652
AF		 513 CPUX86State *env = &cpu->env;
514
ab443475
JK		 515 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
516 unsigned int bank, bank_num = env->mcg_cap & 0xff;
517 struct kvm_x86_mce mce;
518
519 env->exception_injected = -1;
520
521 /*
522 * There must be at least one bank in use if an MCE is pending.
523 * Find it and use its values for the event injection.
524 */
525 for (bank = 0; bank < bank_num; bank++) {
526 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
527 break;
528 }
529 }
530 assert(bank < bank_num);
531
532 mce.bank = bank;
533 mce.status = env->mce_banks[bank * 4 + 1];
534 mce.mcg_status = env->mcg_status;
535 mce.addr = env->mce_banks[bank * 4 + 2];
536 mce.misc = env->mce_banks[bank * 4 + 3];
537
1bc22652 538 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
ab443475 539 }
ab443475
JK		 540 return 0;
541}
542
1dfb4dd9 543static void cpu_update_state(void *opaque, int running, RunState state)
b8cc45d6 544{
317ac620 545 CPUX86State *env = opaque;
b8cc45d6
GC		 546
547 if (running) {
548 env->tsc_valid = false;
549 }
550}
551
83b17af5 552unsigned long kvm_arch_vcpu_id(CPUState *cs)
b164e48e 553{
83b17af5 554 X86CPU *cpu = X86_CPU(cs);
7e72a45c 555 return cpu->apic_id;
b164e48e
EH		 556}
557
92067bf4
IM		 558#ifndef KVM_CPUID_SIGNATURE_NEXT
559#define KVM_CPUID_SIGNATURE_NEXT 0x40000100
560#endif
561
562static bool hyperv_hypercall_available(X86CPU *cpu)
563{
564 return cpu->hyperv_vapic ||
565 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
566}
567
568static bool hyperv_enabled(X86CPU *cpu)
569{
7bc3d711
PB		 570 CPUState *cs = CPU(cpu);
571 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
572 (hyperv_hypercall_available(cpu) ||
48a5f3bc 573 cpu->hyperv_time ||
f2a53c9e 574 cpu->hyperv_relaxed_timing ||
744b8a94 575 cpu->hyperv_crash ||
8c145d7c 576 cpu->hyperv_reset ||
46eb8f98 577 cpu->hyperv_vpindex ||
866eea9a 578 cpu->hyperv_runtime ||
ff99aa64
AS		 579 cpu->hyperv_synic ||
580 cpu->hyperv_stimer);
92067bf4
IM		 581}
582
5031283d
HZ		 583static int kvm_arch_set_tsc_khz(CPUState *cs)
584{
585 X86CPU *cpu = X86_CPU(cs);
586 CPUX86State *env = &cpu->env;
587 int r;
588
589 if (!env->tsc_khz) {
590 return 0;
591 }
592
593 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
594 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
595 -ENOTSUP;
596 if (r < 0) {
597 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
598 * TSC frequency doesn't match the one we want.
599 */
600 int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
601 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
602 -ENOTSUP;
603 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
3dc6f869
AF		 604 warn_report("TSC frequency mismatch between "
605 "VM (%" PRId64 " kHz) and host (%d kHz), "
606 "and TSC scaling unavailable",
607 env->tsc_khz, cur_freq);
5031283d
HZ		 608 return r;
609 }
610 }
611
612 return 0;
613}
614
4bb95b82
LP		 615static bool tsc_is_stable_and_known(CPUX86State *env)
616{
617 if (!env->tsc_khz) {
618 return false;
619 }
620 return (env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
621 || env->user_tsc_khz;
622}
623
c35bd19a
EY		 624static int hyperv_handle_properties(CPUState *cs)
625{
626 X86CPU *cpu = X86_CPU(cs);
627 CPUX86State *env = &cpu->env;
628
3ddcd2ed
EH		 629 if (cpu->hyperv_time &&
630 kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) <= 0) {
631 cpu->hyperv_time = false;
632 }
633
c35bd19a 634 if (cpu->hyperv_relaxed_timing) {
5e953812 635 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
c35bd19a
EY		 636 }
637 if (cpu->hyperv_vapic) {
5e953812
RK		 638 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
639 env->features[FEAT_HYPERV_EAX] |= HV_APIC_ACCESS_AVAILABLE;
c35bd19a 640 }
3ddcd2ed 641 if (cpu->hyperv_time) {
5e953812
RK		 642 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
643 env->features[FEAT_HYPERV_EAX] |= HV_TIME_REF_COUNT_AVAILABLE;
644 env->features[FEAT_HYPERV_EAX] |= HV_REFERENCE_TSC_AVAILABLE;
d72bc7f6
LP		 645
646 if (has_msr_hv_frequencies && tsc_is_stable_and_known(env)) {
5e953812
RK		 647 env->features[FEAT_HYPERV_EAX] |= HV_ACCESS_FREQUENCY_MSRS;
648 env->features[FEAT_HYPERV_EDX] |= HV_FREQUENCY_MSRS_AVAILABLE;
d72bc7f6 649 }
c35bd19a
EY		 650 }
651 if (cpu->hyperv_crash && has_msr_hv_crash) {
5e953812 652 env->features[FEAT_HYPERV_EDX] |= HV_GUEST_CRASH_MSR_AVAILABLE;
c35bd19a 653 }
5e953812 654 env->features[FEAT_HYPERV_EDX] |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
c35bd19a 655 if (cpu->hyperv_reset && has_msr_hv_reset) {
5e953812 656 env->features[FEAT_HYPERV_EAX] |= HV_RESET_AVAILABLE;
c35bd19a
EY		 657 }
658 if (cpu->hyperv_vpindex && has_msr_hv_vpindex) {
5e953812 659 env->features[FEAT_HYPERV_EAX] |= HV_VP_INDEX_AVAILABLE;
c35bd19a
EY		 660 }
661 if (cpu->hyperv_runtime && has_msr_hv_runtime) {
5e953812 662 env->features[FEAT_HYPERV_EAX] |= HV_VP_RUNTIME_AVAILABLE;
c35bd19a
EY		 663 }
664 if (cpu->hyperv_synic) {
665 int sint;
666
667 if (!has_msr_hv_synic ||
668 kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_SYNIC, 0)) {
669 fprintf(stderr, "Hyper-V SynIC is not supported by kernel\n");
670 return -ENOSYS;
671 }
672
5e953812
RK		 673 env->features[FEAT_HYPERV_EAX] |= HV_SYNIC_AVAILABLE;
674 env->msr_hv_synic_version = HV_SYNIC_VERSION;
c35bd19a 675 for (sint = 0; sint < ARRAY_SIZE(env->msr_hv_synic_sint); sint++) {
5e953812 676 env->msr_hv_synic_sint[sint] = HV_SINT_MASKED;
c35bd19a
EY		 677 }
678 }
679 if (cpu->hyperv_stimer) {
680 if (!has_msr_hv_stimer) {
681 fprintf(stderr, "Hyper-V timers aren't supported by kernel\n");
682 return -ENOSYS;
683 }
5e953812 684 env->features[FEAT_HYPERV_EAX] |= HV_SYNTIMERS_AVAILABLE;
c35bd19a
EY		 685 }
686 return 0;
687}
688
68bfd0ad
MT		 689static Error *invtsc_mig_blocker;
690
f8bb0565 691#define KVM_MAX_CPUID_ENTRIES 100
0893d460 692
20d695a9 693int kvm_arch_init_vcpu(CPUState *cs)
05330448
AL		 694{
695 struct {
486bd5a2 696 struct kvm_cpuid2 cpuid;
f8bb0565 697 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
541dc0d4 698 } QEMU_PACKED cpuid_data;
20d695a9
AF		 699 X86CPU *cpu = X86_CPU(cs);
700 CPUX86State *env = &cpu->env;
486bd5a2 701 uint32_t limit, i, j, cpuid_i;
a33609ca 702 uint32_t unused;
bb0300dc 703 struct kvm_cpuid_entry2 *c;
bb0300dc 704 uint32_t signature[3];
234cc647 705 int kvm_base = KVM_CPUID_SIGNATURE;
e7429073 706 int r;
fe44dc91 707 Error *local_err = NULL;
05330448 708
ef4cbe14
SW		 709 memset(&cpuid_data, 0, sizeof(cpuid_data));
710
05330448
AL		 711 cpuid_i = 0;
712
ddb98b5a
LP		 713 r = kvm_arch_set_tsc_khz(cs);
714 if (r < 0) {
715 goto fail;
716 }
717
718 /* vcpu's TSC frequency is either specified by user, or following
719 * the value used by KVM if the former is not present. In the
720 * latter case, we query it from KVM and record in env->tsc_khz,
721 * so that vcpu's TSC frequency can be migrated later via this field.
722 */
723 if (!env->tsc_khz) {
724 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
725 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
726 -ENOTSUP;
727 if (r > 0) {
728 env->tsc_khz = r;
729 }
730 }
731
bb0300dc 732 /* Paravirtualization CPUIDs */
234cc647
PB		 733 if (hyperv_enabled(cpu)) {
734 c = &cpuid_data.entries[cpuid_i++];
5e953812 735 c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
1c4a55db
AW		 736 if (!cpu->hyperv_vendor_id) {
737 memcpy(signature, "Microsoft Hv", 12);
738 } else {
739 size_t len = strlen(cpu->hyperv_vendor_id);
740
741 if (len > 12) {
742 error_report("hv-vendor-id truncated to 12 characters");
743 len = 12;
744 }
745 memset(signature, 0, 12);
746 memcpy(signature, cpu->hyperv_vendor_id, len);
747 }
5e953812 748 c->eax = HV_CPUID_MIN;
234cc647
PB		 749 c->ebx = signature[0];
750 c->ecx = signature[1];
751 c->edx = signature[2];
0c31b744 752
234cc647 753 c = &cpuid_data.entries[cpuid_i++];
5e953812 754 c->function = HV_CPUID_INTERFACE;
eab70139
VR		 755 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
756 c->eax = signature[0];
234cc647
PB		 757 c->ebx = 0;
758 c->ecx = 0;
759 c->edx = 0;
eab70139
VR		 760
761 c = &cpuid_data.entries[cpuid_i++];
5e953812 762 c->function = HV_CPUID_VERSION;
eab70139
VR		 763 c->eax = 0x00001bbc;
764 c->ebx = 0x00060001;
765
766 c = &cpuid_data.entries[cpuid_i++];
5e953812 767 c->function = HV_CPUID_FEATURES;
c35bd19a
EY		 768 r = hyperv_handle_properties(cs);
769 if (r) {
770 return r;
46eb8f98 771 }
c35bd19a
EY		 772 c->eax = env->features[FEAT_HYPERV_EAX];
773 c->ebx = env->features[FEAT_HYPERV_EBX];
774 c->edx = env->features[FEAT_HYPERV_EDX];
866eea9a 775
eab70139 776 c = &cpuid_data.entries[cpuid_i++];
5e953812 777 c->function = HV_CPUID_ENLIGHTMENT_INFO;
92067bf4 778 if (cpu->hyperv_relaxed_timing) {
5e953812 779 c->eax |= HV_RELAXED_TIMING_RECOMMENDED;
eab70139 780 }
2d5aa872 781 if (cpu->hyperv_vapic) {
5e953812 782 c->eax |= HV_APIC_ACCESS_RECOMMENDED;
eab70139 783 }
92067bf4 784 c->ebx = cpu->hyperv_spinlock_attempts;
eab70139
VR		 785
786 c = &cpuid_data.entries[cpuid_i++];
5e953812 787 c->function = HV_CPUID_IMPLEMENT_LIMITS;
6c69dfb6
GA		 788
789 c->eax = cpu->hv_max_vps;
eab70139
VR		 790 c->ebx = 0x40;
791
234cc647 792 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
7bc3d711 793 has_msr_hv_hypercall = true;
eab70139
VR		 794 }
795
f522d2ac
AW		 796 if (cpu->expose_kvm) {
797 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
798 c = &cpuid_data.entries[cpuid_i++];
799 c->function = KVM_CPUID_SIGNATURE | kvm_base;
79b6f2f6 800 c->eax = KVM_CPUID_FEATURES | kvm_base;
f522d2ac
AW		 801 c->ebx = signature[0];
802 c->ecx = signature[1];
803 c->edx = signature[2];
234cc647 804
f522d2ac
AW		 805 c = &cpuid_data.entries[cpuid_i++];
806 c->function = KVM_CPUID_FEATURES | kvm_base;
807 c->eax = env->features[FEAT_KVM];
f522d2ac 808 }
917367aa 809
a33609ca 810 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
05330448
AL		 811
812 for (i = 0; i <= limit; i++) {
f8bb0565
IM		 813 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
814 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
815 abort();
816 }
bb0300dc 817 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 818
819 switch (i) {
a36b1029
AL		 820 case 2: {
821 /* Keep reading function 2 till all the input is received */
822 int times;
823
a36b1029 824 c->function = i;
a33609ca
AL		 825 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
826 KVM_CPUID_FLAG_STATE_READ_NEXT;
827 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
828 times = c->eax & 0xff;
a36b1029
AL		 829
830 for (j = 1; j < times; ++j) {
f8bb0565
IM		 831 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
832 fprintf(stderr, "cpuid_data is full, no space for "
833 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
834 abort();
835 }
a33609ca 836 c = &cpuid_data.entries[cpuid_i++];
a36b1029 837 c->function = i;
a33609ca
AL		 838 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
839 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
a36b1029
AL		 840 }
841 break;
842 }
486bd5a2
AL		 843 case 4:
844 case 0xb:
845 case 0xd:
846 for (j = 0; ; j++) {
31e8c696
AP		 847 if (i == 0xd && j == 64) {
848 break;
849 }
486bd5a2
AL		 850 c->function = i;
851 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
852 c->index = j;
a33609ca 853 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2 854
b9bec74b 855 if (i == 4 && c->eax == 0) {
486bd5a2 856 break;
b9bec74b
JK		 857 }
858 if (i == 0xb && !(c->ecx & 0xff00)) {
486bd5a2 859 break;
b9bec74b
JK		 860 }
861 if (i == 0xd && c->eax == 0) {
31e8c696 862 continue;
b9bec74b 863 }
f8bb0565
IM		 864 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
865 fprintf(stderr, "cpuid_data is full, no space for "
866 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
867 abort();
868 }
a33609ca 869 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 870 }
871 break;
872 default:
486bd5a2 873 c->function = i;
a33609ca
AL		 874 c->flags = 0;
875 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2
AL		 876 break;
877 }
05330448 878 }
0d894367
PB		 879
880 if (limit >= 0x0a) {
881 uint32_t ver;
882
883 cpu_x86_cpuid(env, 0x0a, 0, &ver, &unused, &unused, &unused);
884 if ((ver & 0xff) > 0) {
885 has_msr_architectural_pmu = true;
886 num_architectural_pmu_counters = (ver & 0xff00) >> 8;
887
888 /* Shouldn't be more than 32, since that's the number of bits
889 * available in EBX to tell us _which_ counters are available.
890 * Play it safe.
891 */
892 if (num_architectural_pmu_counters > MAX_GP_COUNTERS) {
893 num_architectural_pmu_counters = MAX_GP_COUNTERS;
894 }
895 }
896 }
897
a33609ca 898 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
05330448
AL		 899
900 for (i = 0x80000000; i <= limit; i++) {
f8bb0565
IM		 901 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
902 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
903 abort();
904 }
bb0300dc 905 c = &cpuid_data.entries[cpuid_i++];
05330448 906
05330448 907 c->function = i;
a33609ca
AL		 908 c->flags = 0;
909 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
05330448
AL		 910 }
911
b3baa152
BW		 912 /* Call Centaur's CPUID instructions they are supported. */
913 if (env->cpuid_xlevel2 > 0) {
b3baa152
BW		 914 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
915
916 for (i = 0xC0000000; i <= limit; i++) {
f8bb0565
IM		 917 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
918 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
919 abort();
920 }
b3baa152
BW		 921 c = &cpuid_data.entries[cpuid_i++];
922
923 c->function = i;
924 c->flags = 0;
925 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
926 }
927 }
928
05330448
AL		 929 cpuid_data.cpuid.nent = cpuid_i;
930
e7701825 931 if (((env->cpuid_version >> 8)&0xF) >= 6
0514ef2f 932 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
fc7a504c 933 (CPUID_MCE | CPUID_MCA)
a60f24b5 934 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
5120901a 935 uint64_t mcg_cap, unsupported_caps;
e7701825 936 int banks;
32a42024 937 int ret;
e7701825 938
a60f24b5 939 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
75d49497
JK		 940 if (ret < 0) {
941 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
942 return ret;
e7701825 943 }
75d49497 944
2590f15b 945 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
49b69cbf 946 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
2590f15b 947 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
49b69cbf 948 return -ENOTSUP;
75d49497 949 }
49b69cbf 950
5120901a
EH		 951 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
952 if (unsupported_caps) {
87f8b626
AR		 953 if (unsupported_caps & MCG_LMCE_P) {
954 error_report("kvm: LMCE not supported");
955 return -ENOTSUP;
956 }
3dc6f869
AF		 957 warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64,
958 unsupported_caps);
5120901a
EH		 959 }
960
2590f15b
EH		 961 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
962 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
75d49497
JK		 963 if (ret < 0) {
964 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
965 return ret;
966 }
e7701825 967 }
e7701825 968
b8cc45d6
GC		 969 qemu_add_vm_change_state_handler(cpu_update_state, env);
970
df67696e
LJ		 971 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
972 if (c) {
973 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
974 !!(c->ecx & CPUID_EXT_SMX);
975 }
976
87f8b626
AR		 977 if (env->mcg_cap & MCG_LMCE_P) {
978 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
979 }
980
d99569d9
EH		 981 if (!env->user_tsc_khz) {
982 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
983 invtsc_mig_blocker == NULL) {
984 /* for migration */
985 error_setg(&invtsc_mig_blocker,
986 "State blocked by non-migratable CPU device"
987 " (invtsc flag)");
fe44dc91
AA		 988 r = migrate_add_blocker(invtsc_mig_blocker, &local_err);
989 if (local_err) {
990 error_report_err(local_err);
991 error_free(invtsc_mig_blocker);
992 goto fail;
993 }
d99569d9
EH		 994 /* for savevm */
995 vmstate_x86_cpu.unmigratable = 1;
996 }
68bfd0ad
MT		 997 }
998
9954a158
PDJ		 999 if (cpu->vmware_cpuid_freq
1000 /* Guests depend on 0x40000000 to detect this feature, so only expose
1001 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
1002 && cpu->expose_kvm
1003 && kvm_base == KVM_CPUID_SIGNATURE
1004 /* TSC clock must be stable and known for this feature. */
4bb95b82 1005 && tsc_is_stable_and_known(env)) {
9954a158
PDJ		 1006
1007 c = &cpuid_data.entries[cpuid_i++];
1008 c->function = KVM_CPUID_SIGNATURE | 0x10;
1009 c->eax = env->tsc_khz;
1010 /* LAPIC resolution of 1ns (freq: 1GHz) is hardcoded in KVM's
1011 * APIC_BUS_CYCLE_NS */
1012 c->ebx = 1000000;
1013 c->ecx = c->edx = 0;
1014
1015 c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
1016 c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
1017 }
1018
1019 cpuid_data.cpuid.nent = cpuid_i;
1020
1021 cpuid_data.cpuid.padding = 0;
1022 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
1023 if (r) {
1024 goto fail;
1025 }
1026
28143b40 1027 if (has_xsave) {
fabacc0f
JK		 1028 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
1029 }
d71b62a1 1030 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
fabacc0f 1031
273c515c
PB		 1032 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
1033 has_msr_tsc_aux = false;
1034 }
d1ae67f6 1035
e7429073 1036 return 0;
fe44dc91
AA		 1037
1038 fail:
1039 migrate_del_blocker(invtsc_mig_blocker);
1040 return r;
05330448
AL		 1041}
1042
50a2c6e5 1043void kvm_arch_reset_vcpu(X86CPU *cpu)
caa5af0f 1044{
20d695a9 1045 CPUX86State *env = &cpu->env;
dd673288 1046
e73223a5 1047 env->exception_injected = -1;
0e607a80 1048 env->interrupt_injected = -1;
1a5e9d2f 1049 env->xcr0 = 1;
ddced198 1050 if (kvm_irqchip_in_kernel()) {
dd673288 1051 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
ddced198
MT		 1052 KVM_MP_STATE_UNINITIALIZED;
1053 } else {
1054 env->mp_state = KVM_MP_STATE_RUNNABLE;
1055 }
caa5af0f
JK		 1056}
1057
e0723c45
PB		 1058void kvm_arch_do_init_vcpu(X86CPU *cpu)
1059{
1060 CPUX86State *env = &cpu->env;
1061
1062 /* APs get directly into wait-for-SIPI state. */
1063 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
1064 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
1065 }
1066}
1067
c3a3a7d3 1068static int kvm_get_supported_msrs(KVMState *s)
05330448 1069{
75b10c43 1070 static int kvm_supported_msrs;
c3a3a7d3 1071 int ret = 0;
05330448
AL		 1072
1073 /* first time */
75b10c43 1074 if (kvm_supported_msrs == 0) {
05330448
AL		 1075 struct kvm_msr_list msr_list, *kvm_msr_list;
1076
75b10c43 1077 kvm_supported_msrs = -1;
05330448
AL		 1078
1079 /* Obtain MSR list from KVM. These are the MSRs that we must
1080 * save/restore */
4c9f7372 1081 msr_list.nmsrs = 0;
c3a3a7d3 1082 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
6fb6d245 1083 if (ret < 0 && ret != -E2BIG) {
c3a3a7d3 1084 return ret;
6fb6d245 1085 }
d9db889f
JK		 1086 /* Old kernel modules had a bug and could write beyond the provided
1087 memory. Allocate at least a safe amount of 1K. */
7267c094 1088 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
d9db889f
JK		 1089 msr_list.nmsrs *
1090 sizeof(msr_list.indices[0])));
05330448 1091
55308450 1092 kvm_msr_list->nmsrs = msr_list.nmsrs;
c3a3a7d3 1093 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
05330448
AL		 1094 if (ret >= 0) {
1095 int i;
1096
1097 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
1d268dec
LP		 1098 switch (kvm_msr_list->indices[i]) {
1099 case MSR_STAR:
c3a3a7d3 1100 has_msr_star = true;
1d268dec
LP		 1101 break;
1102 case MSR_VM_HSAVE_PA:
c3a3a7d3 1103 has_msr_hsave_pa = true;
1d268dec
LP		 1104 break;
1105 case MSR_TSC_AUX:
c9b8f6b6 1106 has_msr_tsc_aux = true;
1d268dec
LP		 1107 break;
1108 case MSR_TSC_ADJUST:
f28558d3 1109 has_msr_tsc_adjust = true;
1d268dec
LP		 1110 break;
1111 case MSR_IA32_TSCDEADLINE:
aa82ba54 1112 has_msr_tsc_deadline = true;
1d268dec
LP		 1113 break;
1114 case MSR_IA32_SMBASE:
fc12d72e 1115 has_msr_smbase = true;
1d268dec
LP		 1116 break;
1117 case MSR_IA32_MISC_ENABLE:
21e87c46 1118 has_msr_misc_enable = true;
1d268dec
LP		 1119 break;
1120 case MSR_IA32_BNDCFGS:
79e9ebeb 1121 has_msr_bndcfgs = true;
1d268dec
LP		 1122 break;
1123 case MSR_IA32_XSS:
18cd2c17 1124 has_msr_xss = true;
1d268dec
LP		 1125 break;;
1126 case HV_X64_MSR_CRASH_CTL:
f2a53c9e 1127 has_msr_hv_crash = true;
1d268dec
LP		 1128 break;
1129 case HV_X64_MSR_RESET:
744b8a94 1130 has_msr_hv_reset = true;
1d268dec
LP		 1131 break;
1132 case HV_X64_MSR_VP_INDEX:
8c145d7c 1133 has_msr_hv_vpindex = true;
1d268dec
LP		 1134 break;
1135 case HV_X64_MSR_VP_RUNTIME:
46eb8f98 1136 has_msr_hv_runtime = true;
1d268dec
LP		 1137 break;
1138 case HV_X64_MSR_SCONTROL:
866eea9a 1139 has_msr_hv_synic = true;
1d268dec
LP		 1140 break;
1141 case HV_X64_MSR_STIMER0_CONFIG:
ff99aa64 1142 has_msr_hv_stimer = true;
1d268dec 1143 break;
d72bc7f6
LP		 1144 case HV_X64_MSR_TSC_FREQUENCY:
1145 has_msr_hv_frequencies = true;
1146 break;
ff99aa64 1147 }
05330448
AL		 1148 }
1149 }
1150
7267c094 1151 g_free(kvm_msr_list);
05330448
AL		 1152 }
1153
c3a3a7d3 1154 return ret;
05330448
AL		 1155}
1156
6410848b
PB		 1157static Notifier smram_machine_done;
1158static KVMMemoryListener smram_listener;
1159static AddressSpace smram_address_space;
1160static MemoryRegion smram_as_root;
1161static MemoryRegion smram_as_mem;
1162
1163static void register_smram_listener(Notifier *n, void *unused)
1164{
1165 MemoryRegion *smram =
1166 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1167
1168 /* Outer container... */
1169 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1170 memory_region_set_enabled(&smram_as_root, true);
1171
1172 /* ... with two regions inside: normal system memory with low
1173 * priority, and...
1174 */
1175 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1176 get_system_memory(), 0, ~0ull);
1177 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1178 memory_region_set_enabled(&smram_as_mem, true);
1179
1180 if (smram) {
1181 /* ... SMRAM with higher priority */
1182 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1183 memory_region_set_enabled(smram, true);
1184 }
1185
1186 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1187 kvm_memory_listener_register(kvm_state, &smram_listener,
1188 &smram_address_space, 1);
1189}
1190
b16565b3 1191int kvm_arch_init(MachineState *ms, KVMState *s)
20420430 1192{
11076198 1193 uint64_t identity_base = 0xfffbc000;
39d6960a 1194 uint64_t shadow_mem;
20420430 1195 int ret;
25d2e361 1196 struct utsname utsname;
20420430 1197
28143b40
TH		 1198#ifdef KVM_CAP_XSAVE
1199 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
1200#endif
1201
1202#ifdef KVM_CAP_XCRS
1203 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
1204#endif
1205
1206#ifdef KVM_CAP_PIT_STATE2
1207 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
1208#endif
1209
c3a3a7d3 1210 ret = kvm_get_supported_msrs(s);
20420430 1211 if (ret < 0) {
20420430
SY		 1212 return ret;
1213 }
25d2e361
MT		 1214
1215 uname(&utsname);
1216 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1217
4c5b10b7 1218 /*
11076198
JK		 1219 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1220 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
1221 * Since these must be part of guest physical memory, we need to allocate
1222 * them, both by setting their start addresses in the kernel and by
1223 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1224 *
1225 * Older KVM versions may not support setting the identity map base. In
1226 * that case we need to stick with the default, i.e. a 256K maximum BIOS
1227 * size.
4c5b10b7 1228 */
11076198
JK		 1229 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1230 /* Allows up to 16M BIOSes. */
1231 identity_base = 0xfeffc000;
1232
1233 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1234 if (ret < 0) {
1235 return ret;
1236 }
4c5b10b7 1237 }
e56ff191 1238
11076198
JK		 1239 /* Set TSS base one page after EPT identity map. */
1240 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
20420430
SY		 1241 if (ret < 0) {
1242 return ret;
1243 }
1244
11076198
JK		 1245 /* Tell fw_cfg to notify the BIOS to reserve the range. */
1246 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
20420430 1247 if (ret < 0) {
11076198 1248 fprintf(stderr, "e820_add_entry() table is full\n");
20420430
SY		 1249 return ret;
1250 }
3c85e74f 1251 qemu_register_reset(kvm_unpoison_all, NULL);
20420430 1252
4689b77b 1253 shadow_mem = machine_kvm_shadow_mem(ms);
36ad0e94
MA		 1254 if (shadow_mem != -1) {
1255 shadow_mem /= 4096;
1256 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1257 if (ret < 0) {
1258 return ret;
39d6960a
JK		 1259 }
1260 }
6410848b 1261
d870cfde
GA		 1262 if (kvm_check_extension(s, KVM_CAP_X86_SMM) &&
1263 object_dynamic_cast(OBJECT(ms), TYPE_PC_MACHINE) &&
1264 pc_machine_is_smm_enabled(PC_MACHINE(ms))) {
6410848b
PB		 1265 smram_machine_done.notify = register_smram_listener;
1266 qemu_add_machine_init_done_notifier(&smram_machine_done);
1267 }
11076198 1268 return 0;
05330448 1269}
b9bec74b 1270
05330448
AL		 1271static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1272{
1273 lhs->selector = rhs->selector;
1274 lhs->base = rhs->base;
1275 lhs->limit = rhs->limit;
1276 lhs->type = 3;
1277 lhs->present = 1;
1278 lhs->dpl = 3;
1279 lhs->db = 0;
1280 lhs->s = 1;
1281 lhs->l = 0;
1282 lhs->g = 0;
1283 lhs->avl = 0;
1284 lhs->unusable = 0;
1285}
1286
1287static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1288{
1289 unsigned flags = rhs->flags;
1290 lhs->selector = rhs->selector;
1291 lhs->base = rhs->base;
1292 lhs->limit = rhs->limit;
1293 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
1294 lhs->present = (flags & DESC_P_MASK) != 0;
acaa7550 1295 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
05330448
AL		 1296 lhs->db = (flags >> DESC_B_SHIFT) & 1;
1297 lhs->s = (flags & DESC_S_MASK) != 0;
1298 lhs->l = (flags >> DESC_L_SHIFT) & 1;
1299 lhs->g = (flags & DESC_G_MASK) != 0;
1300 lhs->avl = (flags & DESC_AVL_MASK) != 0;
4cae9c97 1301 lhs->unusable = !lhs->present;
7e680753 1302 lhs->padding = 0;
05330448
AL		 1303}
1304
1305static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
1306{
1307 lhs->selector = rhs->selector;
1308 lhs->base = rhs->base;
1309 lhs->limit = rhs->limit;
d45fc087
RP		 1310 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
1311 ((rhs->present && !rhs->unusable) * DESC_P_MASK) |
1312 (rhs->dpl << DESC_DPL_SHIFT) |
1313 (rhs->db << DESC_B_SHIFT) |
1314 (rhs->s * DESC_S_MASK) |
1315 (rhs->l << DESC_L_SHIFT) |
1316 (rhs->g * DESC_G_MASK) |
1317 (rhs->avl * DESC_AVL_MASK);
05330448
AL		 1318}
1319
1320static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
1321{
b9bec74b 1322 if (set) {
05330448 1323 *kvm_reg = *qemu_reg;
b9bec74b 1324 } else {
05330448 1325 *qemu_reg = *kvm_reg;
b9bec74b 1326 }
05330448
AL		 1327}
1328
1bc22652 1329static int kvm_getput_regs(X86CPU *cpu, int set)
05330448 1330{
1bc22652 1331 CPUX86State *env = &cpu->env;
05330448
AL		 1332 struct kvm_regs regs;
1333 int ret = 0;
1334
1335 if (!set) {
1bc22652 1336 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
b9bec74b 1337 if (ret < 0) {
05330448 1338 return ret;
b9bec74b 1339 }
05330448
AL		 1340 }
1341
1342 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
1343 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
1344 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
1345 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
1346 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
1347 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
1348 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
1349 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
1350#ifdef TARGET_X86_64
1351 kvm_getput_reg(&regs.r8, &env->regs[8], set);
1352 kvm_getput_reg(&regs.r9, &env->regs[9], set);
1353 kvm_getput_reg(&regs.r10, &env->regs[10], set);
1354 kvm_getput_reg(&regs.r11, &env->regs[11], set);
1355 kvm_getput_reg(&regs.r12, &env->regs[12], set);
1356 kvm_getput_reg(&regs.r13, &env->regs[13], set);
1357 kvm_getput_reg(&regs.r14, &env->regs[14], set);
1358 kvm_getput_reg(&regs.r15, &env->regs[15], set);
1359#endif
1360
1361 kvm_getput_reg(&regs.rflags, &env->eflags, set);
1362 kvm_getput_reg(&regs.rip, &env->eip, set);
1363
b9bec74b 1364 if (set) {
1bc22652 1365 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
b9bec74b 1366 }
05330448
AL		 1367
1368 return ret;
1369}
1370
1bc22652 1371static int kvm_put_fpu(X86CPU *cpu)
05330448 1372{
1bc22652 1373 CPUX86State *env = &cpu->env;
05330448
AL		 1374 struct kvm_fpu fpu;
1375 int i;
1376
1377 memset(&fpu, 0, sizeof fpu);
1378 fpu.fsw = env->fpus & ~(7 << 11);
1379 fpu.fsw |= (env->fpstt & 7) << 11;
1380 fpu.fcw = env->fpuc;
42cc8fa6
JK		 1381 fpu.last_opcode = env->fpop;
1382 fpu.last_ip = env->fpip;
1383 fpu.last_dp = env->fpdp;
b9bec74b
JK		 1384 for (i = 0; i < 8; ++i) {
1385 fpu.ftwx |= (!env->fptags[i]) << i;
1386 }
05330448 1387 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
bee81887 1388 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 1389 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
1390 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
bee81887 1391 }
05330448
AL		 1392 fpu.mxcsr = env->mxcsr;
1393
1bc22652 1394 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
05330448
AL		 1395}
1396
6b42494b
JK		 1397#define XSAVE_FCW_FSW 0
1398#define XSAVE_FTW_FOP 1
f1665b21
SY		 1399#define XSAVE_CWD_RIP 2
1400#define XSAVE_CWD_RDP 4
1401#define XSAVE_MXCSR 6
1402#define XSAVE_ST_SPACE 8
1403#define XSAVE_XMM_SPACE 40
1404#define XSAVE_XSTATE_BV 128
1405#define XSAVE_YMMH_SPACE 144
79e9ebeb
LJ		 1406#define XSAVE_BNDREGS 240
1407#define XSAVE_BNDCSR 256
9aecd6f8
CP		 1408#define XSAVE_OPMASK 272
1409#define XSAVE_ZMM_Hi256 288
1410#define XSAVE_Hi16_ZMM 416
f74eefe0 1411#define XSAVE_PKRU 672
f1665b21 1412
b503717d
EH		 1413#define XSAVE_BYTE_OFFSET(word_offset) \
1414 ((word_offset) * sizeof(((struct kvm_xsave *)0)->region[0]))
1415
1416#define ASSERT_OFFSET(word_offset, field) \
1417 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
1418 offsetof(X86XSaveArea, field))
1419
1420ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
1421ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
1422ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
1423ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
1424ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
1425ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
1426ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
1427ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
1428ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
1429ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
1430ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
1431ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
1432ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
1433ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
1434ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
1435
1bc22652 1436static int kvm_put_xsave(X86CPU *cpu)
f1665b21 1437{
1bc22652 1438 CPUX86State *env = &cpu->env;
86cd2ea0 1439 X86XSaveArea *xsave = env->kvm_xsave_buf;
f1665b21 1440
28143b40 1441 if (!has_xsave) {
1bc22652 1442 return kvm_put_fpu(cpu);
b9bec74b 1443 }
86a57621 1444 x86_cpu_xsave_all_areas(cpu, xsave);
f1665b21 1445
9be38598 1446 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
f1665b21
SY		 1447}
1448
1bc22652 1449static int kvm_put_xcrs(X86CPU *cpu)
f1665b21 1450{
1bc22652 1451 CPUX86State *env = &cpu->env;
bdfc8480 1452 struct kvm_xcrs xcrs = {};
f1665b21 1453
28143b40 1454 if (!has_xcrs) {
f1665b21 1455 return 0;
b9bec74b 1456 }
f1665b21
SY		 1457
1458 xcrs.nr_xcrs = 1;
1459 xcrs.flags = 0;
1460 xcrs.xcrs[0].xcr = 0;
1461 xcrs.xcrs[0].value = env->xcr0;
1bc22652 1462 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
f1665b21
SY		 1463}
1464
1bc22652 1465static int kvm_put_sregs(X86CPU *cpu)
05330448 1466{
1bc22652 1467 CPUX86State *env = &cpu->env;
05330448
AL		 1468 struct kvm_sregs sregs;
1469
0e607a80
JK		 1470 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1471 if (env->interrupt_injected >= 0) {
1472 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1473 (uint64_t)1 << (env->interrupt_injected % 64);
1474 }
05330448
AL		 1475
1476 if ((env->eflags & VM_MASK)) {
b9bec74b
JK		 1477 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1478 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1479 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1480 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1481 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1482 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
05330448 1483 } else {
b9bec74b
JK		 1484 set_seg(&sregs.cs, &env->segs[R_CS]);
1485 set_seg(&sregs.ds, &env->segs[R_DS]);
1486 set_seg(&sregs.es, &env->segs[R_ES]);
1487 set_seg(&sregs.fs, &env->segs[R_FS]);
1488 set_seg(&sregs.gs, &env->segs[R_GS]);
1489 set_seg(&sregs.ss, &env->segs[R_SS]);
05330448
AL		 1490 }
1491
1492 set_seg(&sregs.tr, &env->tr);
1493 set_seg(&sregs.ldt, &env->ldt);
1494
1495 sregs.idt.limit = env->idt.limit;
1496 sregs.idt.base = env->idt.base;
7e680753 1497 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
05330448
AL		 1498 sregs.gdt.limit = env->gdt.limit;
1499 sregs.gdt.base = env->gdt.base;
7e680753 1500 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
05330448
AL		 1501
1502 sregs.cr0 = env->cr[0];
1503 sregs.cr2 = env->cr[2];
1504 sregs.cr3 = env->cr[3];
1505 sregs.cr4 = env->cr[4];
1506
02e51483
CF		 1507 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1508 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
05330448
AL		 1509
1510 sregs.efer = env->efer;
1511
1bc22652 1512 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
05330448
AL		 1513}
1514
d71b62a1
EH		 1515static void kvm_msr_buf_reset(X86CPU *cpu)
1516{
1517 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
1518}
1519
9c600a84
EH		 1520static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
1521{
1522 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
1523 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
1524 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
1525
1526 assert((void *)(entry + 1) <= limit);
1527
1abc2cae
EH		 1528 entry->index = index;
1529 entry->reserved = 0;
1530 entry->data = value;
9c600a84
EH		 1531 msrs->nmsrs++;
1532}
1533
73e1b8f2
PB		 1534static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
1535{
1536 kvm_msr_buf_reset(cpu);
1537 kvm_msr_entry_add(cpu, index, value);
1538
1539 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1540}
1541
f8d9ccf8
DDAG		 1542void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
1543{
1544 int ret;
1545
1546 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
1547 assert(ret == 1);
1548}
1549
7477cd38
MT		 1550static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1551{
1552 CPUX86State *env = &cpu->env;
48e1a45c 1553 int ret;
7477cd38
MT		 1554
1555 if (!has_msr_tsc_deadline) {
1556 return 0;
1557 }
1558
73e1b8f2 1559 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
48e1a45c
PB		 1560 if (ret < 0) {
1561 return ret;
1562 }
1563
1564 assert(ret == 1);
1565 return 0;
7477cd38
MT		 1566}
1567
6bdf863d
JK		 1568/*
1569 * Provide a separate write service for the feature control MSR in order to
1570 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1571 * before writing any other state because forcibly leaving nested mode
1572 * invalidates the VCPU state.
1573 */
1574static int kvm_put_msr_feature_control(X86CPU *cpu)
1575{
48e1a45c
PB		 1576 int ret;
1577
1578 if (!has_msr_feature_control) {
1579 return 0;
1580 }
6bdf863d 1581
73e1b8f2
PB		 1582 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
1583 cpu->env.msr_ia32_feature_control);
48e1a45c
PB		 1584 if (ret < 0) {
1585 return ret;
1586 }
1587
1588 assert(ret == 1);
1589 return 0;
6bdf863d
JK		 1590}
1591
1bc22652 1592static int kvm_put_msrs(X86CPU *cpu, int level)
05330448 1593{
1bc22652 1594 CPUX86State *env = &cpu->env;
9c600a84 1595 int i;
48e1a45c 1596 int ret;
05330448 1597
d71b62a1
EH		 1598 kvm_msr_buf_reset(cpu);
1599
9c600a84
EH		 1600 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1601 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1602 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1603 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
c3a3a7d3 1604 if (has_msr_star) {
9c600a84 1605 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
b9bec74b 1606 }
c3a3a7d3 1607 if (has_msr_hsave_pa) {
9c600a84 1608 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
b9bec74b 1609 }
c9b8f6b6 1610 if (has_msr_tsc_aux) {
9c600a84 1611 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
c9b8f6b6 1612 }
f28558d3 1613 if (has_msr_tsc_adjust) {
9c600a84 1614 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
f28558d3 1615 }
21e87c46 1616 if (has_msr_misc_enable) {
9c600a84 1617 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
21e87c46
AK		 1618 env->msr_ia32_misc_enable);
1619 }
fc12d72e 1620 if (has_msr_smbase) {
9c600a84 1621 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
fc12d72e 1622 }
439d19f2 1623 if (has_msr_bndcfgs) {
9c600a84 1624 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
439d19f2 1625 }
18cd2c17 1626 if (has_msr_xss) {
9c600a84 1627 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
18cd2c17 1628 }
05330448 1629#ifdef TARGET_X86_64
25d2e361 1630 if (lm_capable_kernel) {
9c600a84
EH		 1631 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
1632 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
1633 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
1634 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
25d2e361 1635 }
05330448 1636#endif
ff5c186b 1637 /*
0d894367
PB		 1638 * The following MSRs have side effects on the guest or are too heavy
1639 * for normal writeback. Limit them to reset or full state updates.
ff5c186b
JK		 1640 */
1641 if (level >= KVM_PUT_RESET_STATE) {
9c600a84
EH		 1642 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
1643 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
1644 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
55c911a5 1645 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
9c600a84 1646 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
c5999bfc 1647 }
55c911a5 1648 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 1649 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
bc9a839d 1650 }
55c911a5 1651 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 1652 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
917367aa 1653 }
0d894367
PB		 1654 if (has_msr_architectural_pmu) {
1655 /* Stop the counter. */
9c600a84
EH		 1656 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1657 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
0d894367
PB		 1658
1659 /* Set the counter values. */
1660 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
9c600a84 1661 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
0d894367
PB		 1662 env->msr_fixed_counters[i]);
1663 }
1664 for (i = 0; i < num_architectural_pmu_counters; i++) {
9c600a84 1665 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
0d894367 1666 env->msr_gp_counters[i]);
9c600a84 1667 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
0d894367
PB		 1668 env->msr_gp_evtsel[i]);
1669 }
9c600a84 1670 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
0d894367 1671 env->msr_global_status);
9c600a84 1672 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
0d894367
PB		 1673 env->msr_global_ovf_ctrl);
1674
1675 /* Now start the PMU. */
9c600a84 1676 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
0d894367 1677 env->msr_fixed_ctr_ctrl);
9c600a84 1678 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
0d894367
PB		 1679 env->msr_global_ctrl);
1680 }
7bc3d711 1681 if (has_msr_hv_hypercall) {
9c600a84 1682 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
1c90ef26 1683 env->msr_hv_guest_os_id);
9c600a84 1684 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
1c90ef26 1685 env->msr_hv_hypercall);
eab70139 1686 }
2d5aa872 1687 if (cpu->hyperv_vapic) {
9c600a84 1688 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
5ef68987 1689 env->msr_hv_vapic);
eab70139 1690 }
3ddcd2ed 1691 if (cpu->hyperv_time) {
9c600a84 1692 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, env->msr_hv_tsc);
48a5f3bc 1693 }
f2a53c9e
AS		 1694 if (has_msr_hv_crash) {
1695 int j;
1696
5e953812 1697 for (j = 0; j < HV_CRASH_PARAMS; j++)
9c600a84 1698 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
f2a53c9e
AS		 1699 env->msr_hv_crash_params[j]);
1700
5e953812 1701 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_NOTIFY);
f2a53c9e 1702 }
46eb8f98 1703 if (has_msr_hv_runtime) {
9c600a84 1704 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
46eb8f98 1705 }
866eea9a
AS		 1706 if (cpu->hyperv_synic) {
1707 int j;
1708
9c600a84 1709 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
866eea9a 1710 env->msr_hv_synic_control);
9c600a84 1711 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION,
866eea9a 1712 env->msr_hv_synic_version);
9c600a84 1713 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
866eea9a 1714 env->msr_hv_synic_evt_page);
9c600a84 1715 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
866eea9a
AS		 1716 env->msr_hv_synic_msg_page);
1717
1718 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
9c600a84 1719 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
866eea9a
AS		 1720 env->msr_hv_synic_sint[j]);
1721 }
1722 }
ff99aa64
AS		 1723 if (has_msr_hv_stimer) {
1724 int j;
1725
1726 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
9c600a84 1727 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
ff99aa64
AS		 1728 env->msr_hv_stimer_config[j]);
1729 }
1730
1731 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
9c600a84 1732 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
ff99aa64
AS		 1733 env->msr_hv_stimer_count[j]);
1734 }
1735 }
1eabfce6 1736 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
112dad69
DDAG		 1737 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
1738
9c600a84
EH		 1739 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
1740 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
1741 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
1742 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
1743 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
1744 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
1745 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
1746 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
1747 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
1748 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
1749 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
1750 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
d1ae67f6 1751 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
112dad69
DDAG		 1752 /* The CPU GPs if we write to a bit above the physical limit of
1753 * the host CPU (and KVM emulates that)
1754 */
1755 uint64_t mask = env->mtrr_var[i].mask;
1756 mask &= phys_mask;
1757
9c600a84
EH		 1758 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
1759 env->mtrr_var[i].base);
112dad69 1760 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
d1ae67f6
AW		 1761 }
1762 }
6bdf863d
JK		 1763
1764 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1765 * kvm_put_msr_feature_control. */
ea643051 1766 }
57780495 1767 if (env->mcg_cap) {
d8da8574 1768 int i;
b9bec74b 1769
9c600a84
EH		 1770 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
1771 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
87f8b626
AR		 1772 if (has_msr_mcg_ext_ctl) {
1773 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
1774 }
c34d440a 1775 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 1776 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
57780495
MT		 1777 }
1778 }
1a03675d 1779
d71b62a1 1780 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
48e1a45c
PB		 1781 if (ret < 0) {
1782 return ret;
1783 }
05330448 1784
c70b11d1
EH		 1785 if (ret < cpu->kvm_msr_buf->nmsrs) {
1786 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
1787 error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
1788 (uint32_t)e->index, (uint64_t)e->data);
1789 }
1790
9c600a84 1791 assert(ret == cpu->kvm_msr_buf->nmsrs);
48e1a45c 1792 return 0;
05330448
AL		 1793}
1794
1795
1bc22652 1796static int kvm_get_fpu(X86CPU *cpu)
05330448 1797{
1bc22652 1798 CPUX86State *env = &cpu->env;
05330448
AL		 1799 struct kvm_fpu fpu;
1800 int i, ret;
1801
1bc22652 1802 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
b9bec74b 1803 if (ret < 0) {
05330448 1804 return ret;
b9bec74b 1805 }
05330448
AL		 1806
1807 env->fpstt = (fpu.fsw >> 11) & 7;
1808 env->fpus = fpu.fsw;
1809 env->fpuc = fpu.fcw;
42cc8fa6
JK		 1810 env->fpop = fpu.last_opcode;
1811 env->fpip = fpu.last_ip;
1812 env->fpdp = fpu.last_dp;
b9bec74b
JK		 1813 for (i = 0; i < 8; ++i) {
1814 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1815 }
05330448 1816 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
bee81887 1817 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 1818 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
1819 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
bee81887 1820 }
05330448
AL		 1821 env->mxcsr = fpu.mxcsr;
1822
1823 return 0;
1824}
1825
1bc22652 1826static int kvm_get_xsave(X86CPU *cpu)
f1665b21 1827{
1bc22652 1828 CPUX86State *env = &cpu->env;
86cd2ea0 1829 X86XSaveArea *xsave = env->kvm_xsave_buf;
86a57621 1830 int ret;
f1665b21 1831
28143b40 1832 if (!has_xsave) {
1bc22652 1833 return kvm_get_fpu(cpu);
b9bec74b 1834 }
f1665b21 1835
1bc22652 1836 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
0f53994f 1837 if (ret < 0) {
f1665b21 1838 return ret;
0f53994f 1839 }
86a57621 1840 x86_cpu_xrstor_all_areas(cpu, xsave);
f1665b21 1841
f1665b21 1842 return 0;
f1665b21
SY		 1843}
1844
1bc22652 1845static int kvm_get_xcrs(X86CPU *cpu)
f1665b21 1846{
1bc22652 1847 CPUX86State *env = &cpu->env;
f1665b21
SY		 1848 int i, ret;
1849 struct kvm_xcrs xcrs;
1850
28143b40 1851 if (!has_xcrs) {
f1665b21 1852 return 0;
b9bec74b 1853 }
f1665b21 1854
1bc22652 1855 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
b9bec74b 1856 if (ret < 0) {
f1665b21 1857 return ret;
b9bec74b 1858 }
f1665b21 1859
b9bec74b 1860 for (i = 0; i < xcrs.nr_xcrs; i++) {
f1665b21 1861 /* Only support xcr0 now */
0fd53fec
PB		 1862 if (xcrs.xcrs[i].xcr == 0) {
1863 env->xcr0 = xcrs.xcrs[i].value;
f1665b21
SY		 1864 break;
1865 }
b9bec74b 1866 }
f1665b21 1867 return 0;
f1665b21
SY		 1868}
1869
1bc22652 1870static int kvm_get_sregs(X86CPU *cpu)
05330448 1871{
1bc22652 1872 CPUX86State *env = &cpu->env;
05330448
AL		 1873 struct kvm_sregs sregs;
1874 uint32_t hflags;
0e607a80 1875 int bit, i, ret;
05330448 1876
1bc22652 1877 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
b9bec74b 1878 if (ret < 0) {
05330448 1879 return ret;
b9bec74b 1880 }
05330448 1881
0e607a80
JK		 1882 /* There can only be one pending IRQ set in the bitmap at a time, so try
1883 to find it and save its number instead (-1 for none). */
1884 env->interrupt_injected = -1;
1885 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1886 if (sregs.interrupt_bitmap[i]) {
1887 bit = ctz64(sregs.interrupt_bitmap[i]);
1888 env->interrupt_injected = i * 64 + bit;
1889 break;
1890 }
1891 }
05330448
AL		 1892
1893 get_seg(&env->segs[R_CS], &sregs.cs);
1894 get_seg(&env->segs[R_DS], &sregs.ds);
1895 get_seg(&env->segs[R_ES], &sregs.es);
1896 get_seg(&env->segs[R_FS], &sregs.fs);
1897 get_seg(&env->segs[R_GS], &sregs.gs);
1898 get_seg(&env->segs[R_SS], &sregs.ss);
1899
1900 get_seg(&env->tr, &sregs.tr);
1901 get_seg(&env->ldt, &sregs.ldt);
1902
1903 env->idt.limit = sregs.idt.limit;
1904 env->idt.base = sregs.idt.base;
1905 env->gdt.limit = sregs.gdt.limit;
1906 env->gdt.base = sregs.gdt.base;
1907
1908 env->cr[0] = sregs.cr0;
1909 env->cr[2] = sregs.cr2;
1910 env->cr[3] = sregs.cr3;
1911 env->cr[4] = sregs.cr4;
1912
05330448 1913 env->efer = sregs.efer;
cce47516
JK		 1914
1915 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
05330448 1916
b9bec74b
JK		 1917#define HFLAG_COPY_MASK \
1918 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1919 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1920 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1921 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
05330448 1922
19dc85db
RH		 1923 hflags = env->hflags & HFLAG_COPY_MASK;
1924 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
05330448
AL		 1925 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1926 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
b9bec74b 1927 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
05330448 1928 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
19dc85db
RH		 1929
1930 if (env->cr[4] & CR4_OSFXSR_MASK) {
1931 hflags |= HF_OSFXSR_MASK;
1932 }
05330448
AL		 1933
1934 if (env->efer & MSR_EFER_LMA) {
1935 hflags |= HF_LMA_MASK;
1936 }
1937
1938 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1939 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1940 } else {
1941 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
b9bec74b 1942 (DESC_B_SHIFT - HF_CS32_SHIFT);
05330448 1943 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
b9bec74b
JK		 1944 (DESC_B_SHIFT - HF_SS32_SHIFT);
1945 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1946 !(hflags & HF_CS32_MASK)) {
1947 hflags |= HF_ADDSEG_MASK;
1948 } else {
1949 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1950 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1951 }
05330448 1952 }
19dc85db 1953 env->hflags = hflags;
05330448
AL		 1954
1955 return 0;
1956}
1957
1bc22652 1958static int kvm_get_msrs(X86CPU *cpu)
05330448 1959{
1bc22652 1960 CPUX86State *env = &cpu->env;
d71b62a1 1961 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
9c600a84 1962 int ret, i;
fcc35e7c 1963 uint64_t mtrr_top_bits;
05330448 1964
d71b62a1
EH		 1965 kvm_msr_buf_reset(cpu);
1966
9c600a84
EH		 1967 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
1968 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
1969 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
1970 kvm_msr_entry_add(cpu, MSR_PAT, 0);
c3a3a7d3 1971 if (has_msr_star) {
9c600a84 1972 kvm_msr_entry_add(cpu, MSR_STAR, 0);
b9bec74b 1973 }
c3a3a7d3 1974 if (has_msr_hsave_pa) {
9c600a84 1975 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
b9bec74b 1976 }
c9b8f6b6 1977 if (has_msr_tsc_aux) {
9c600a84 1978 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
c9b8f6b6 1979 }
f28558d3 1980 if (has_msr_tsc_adjust) {
9c600a84 1981 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
f28558d3 1982 }
aa82ba54 1983 if (has_msr_tsc_deadline) {
9c600a84 1984 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
aa82ba54 1985 }
21e87c46 1986 if (has_msr_misc_enable) {
9c600a84 1987 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
21e87c46 1988 }
fc12d72e 1989 if (has_msr_smbase) {
9c600a84 1990 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
fc12d72e 1991 }
df67696e 1992 if (has_msr_feature_control) {
9c600a84 1993 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
df67696e 1994 }
79e9ebeb 1995 if (has_msr_bndcfgs) {
9c600a84 1996 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
79e9ebeb 1997 }
18cd2c17 1998 if (has_msr_xss) {
9c600a84 1999 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
18cd2c17
WL		 2000 }
2001
b8cc45d6
GC		 2002
2003 if (!env->tsc_valid) {
9c600a84 2004 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
1354869c 2005 env->tsc_valid = !runstate_is_running();
b8cc45d6
GC		 2006 }
2007
05330448 2008#ifdef TARGET_X86_64
25d2e361 2009 if (lm_capable_kernel) {
9c600a84
EH		 2010 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
2011 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
2012 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
2013 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
25d2e361 2014 }
05330448 2015#endif
9c600a84
EH		 2016 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
2017 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
55c911a5 2018 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
9c600a84 2019 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
c5999bfc 2020 }
55c911a5 2021 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 2022 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
bc9a839d 2023 }
55c911a5 2024 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 2025 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
917367aa 2026 }
0d894367 2027 if (has_msr_architectural_pmu) {
9c600a84
EH		 2028 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2029 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2030 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
2031 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
0d894367 2032 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
9c600a84 2033 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
0d894367
PB		 2034 }
2035 for (i = 0; i < num_architectural_pmu_counters; i++) {
9c600a84
EH		 2036 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
2037 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
0d894367
PB		 2038 }
2039 }
1a03675d 2040
57780495 2041 if (env->mcg_cap) {
9c600a84
EH		 2042 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
2043 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
87f8b626
AR		 2044 if (has_msr_mcg_ext_ctl) {
2045 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
2046 }
b9bec74b 2047 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 2048 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
b9bec74b 2049 }
57780495 2050 }
57780495 2051
1c90ef26 2052 if (has_msr_hv_hypercall) {
9c600a84
EH		 2053 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
2054 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
1c90ef26 2055 }
2d5aa872 2056 if (cpu->hyperv_vapic) {
9c600a84 2057 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
5ef68987 2058 }
3ddcd2ed 2059 if (cpu->hyperv_time) {
9c600a84 2060 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
48a5f3bc 2061 }
f2a53c9e
AS		 2062 if (has_msr_hv_crash) {
2063 int j;
2064
5e953812 2065 for (j = 0; j < HV_CRASH_PARAMS; j++) {
9c600a84 2066 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
f2a53c9e
AS		 2067 }
2068 }
46eb8f98 2069 if (has_msr_hv_runtime) {
9c600a84 2070 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
46eb8f98 2071 }
866eea9a
AS		 2072 if (cpu->hyperv_synic) {
2073 uint32_t msr;
2074
9c600a84
EH		 2075 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
2076 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, 0);
2077 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
2078 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
866eea9a 2079 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
9c600a84 2080 kvm_msr_entry_add(cpu, msr, 0);
866eea9a
AS		 2081 }
2082 }
ff99aa64
AS		 2083 if (has_msr_hv_stimer) {
2084 uint32_t msr;
2085
2086 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2087 msr++) {
9c600a84 2088 kvm_msr_entry_add(cpu, msr, 0);
ff99aa64
AS		 2089 }
2090 }
1eabfce6 2091 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
9c600a84
EH		 2092 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
2093 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
2094 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
2095 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
2096 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
2097 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
2098 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
2099 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
2100 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
2101 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
2102 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
2103 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
d1ae67f6 2104 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
9c600a84
EH		 2105 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
2106 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
d1ae67f6
AW		 2107 }
2108 }
5ef68987 2109
d71b62a1 2110 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
b9bec74b 2111 if (ret < 0) {
05330448 2112 return ret;
b9bec74b 2113 }
05330448 2114
c70b11d1
EH		 2115 if (ret < cpu->kvm_msr_buf->nmsrs) {
2116 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2117 error_report("error: failed to get MSR 0x%" PRIx32,
2118 (uint32_t)e->index);
2119 }
2120
9c600a84 2121 assert(ret == cpu->kvm_msr_buf->nmsrs);
fcc35e7c
DDAG		 2122 /*
2123 * MTRR masks: Each mask consists of 5 parts
2124 * a 10..0: must be zero
2125 * b 11 : valid bit
2126 * c n-1.12: actual mask bits
2127 * d 51..n: reserved must be zero
2128 * e 63.52: reserved must be zero
2129 *
2130 * 'n' is the number of physical bits supported by the CPU and is
2131 * apparently always <= 52. We know our 'n' but don't know what
2132 * the destinations 'n' is; it might be smaller, in which case
2133 * it masks (c) on loading. It might be larger, in which case
2134 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
2135 * we're migrating to.
2136 */
2137
2138 if (cpu->fill_mtrr_mask) {
2139 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
2140 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
2141 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
2142 } else {
2143 mtrr_top_bits = 0;
2144 }
2145
05330448 2146 for (i = 0; i < ret; i++) {
0d894367
PB		 2147 uint32_t index = msrs[i].index;
2148 switch (index) {
05330448
AL		 2149 case MSR_IA32_SYSENTER_CS:
2150 env->sysenter_cs = msrs[i].data;
2151 break;
2152 case MSR_IA32_SYSENTER_ESP:
2153 env->sysenter_esp = msrs[i].data;
2154 break;
2155 case MSR_IA32_SYSENTER_EIP:
2156 env->sysenter_eip = msrs[i].data;
2157 break;
0c03266a
JK		 2158 case MSR_PAT:
2159 env->pat = msrs[i].data;
2160 break;
05330448
AL		 2161 case MSR_STAR:
2162 env->star = msrs[i].data;
2163 break;
2164#ifdef TARGET_X86_64
2165 case MSR_CSTAR:
2166 env->cstar = msrs[i].data;
2167 break;
2168 case MSR_KERNELGSBASE:
2169 env->kernelgsbase = msrs[i].data;
2170 break;
2171 case MSR_FMASK:
2172 env->fmask = msrs[i].data;
2173 break;
2174 case MSR_LSTAR:
2175 env->lstar = msrs[i].data;
2176 break;
2177#endif
2178 case MSR_IA32_TSC:
2179 env->tsc = msrs[i].data;
2180 break;
c9b8f6b6
AS		 2181 case MSR_TSC_AUX:
2182 env->tsc_aux = msrs[i].data;
2183 break;
f28558d3
WA		 2184 case MSR_TSC_ADJUST:
2185 env->tsc_adjust = msrs[i].data;
2186 break;
aa82ba54
LJ		 2187 case MSR_IA32_TSCDEADLINE:
2188 env->tsc_deadline = msrs[i].data;
2189 break;
aa851e36
MT		 2190 case MSR_VM_HSAVE_PA:
2191 env->vm_hsave = msrs[i].data;
2192 break;
1a03675d
GC		 2193 case MSR_KVM_SYSTEM_TIME:
2194 env->system_time_msr = msrs[i].data;
2195 break;
2196 case MSR_KVM_WALL_CLOCK:
2197 env->wall_clock_msr = msrs[i].data;
2198 break;
57780495
MT		 2199 case MSR_MCG_STATUS:
2200 env->mcg_status = msrs[i].data;
2201 break;
2202 case MSR_MCG_CTL:
2203 env->mcg_ctl = msrs[i].data;
2204 break;
87f8b626
AR		 2205 case MSR_MCG_EXT_CTL:
2206 env->mcg_ext_ctl = msrs[i].data;
2207 break;
21e87c46
AK		 2208 case MSR_IA32_MISC_ENABLE:
2209 env->msr_ia32_misc_enable = msrs[i].data;
2210 break;
fc12d72e
PB		 2211 case MSR_IA32_SMBASE:
2212 env->smbase = msrs[i].data;
2213 break;
0779caeb
ACL		 2214 case MSR_IA32_FEATURE_CONTROL:
2215 env->msr_ia32_feature_control = msrs[i].data;
df67696e 2216 break;
79e9ebeb
LJ		 2217 case MSR_IA32_BNDCFGS:
2218 env->msr_bndcfgs = msrs[i].data;
2219 break;
18cd2c17
WL		 2220 case MSR_IA32_XSS:
2221 env->xss = msrs[i].data;
2222 break;
57780495 2223 default:
57780495
MT		 2224 if (msrs[i].index >= MSR_MC0_CTL &&
2225 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
2226 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
57780495 2227 }
d8da8574 2228 break;
f6584ee2
GN		 2229 case MSR_KVM_ASYNC_PF_EN:
2230 env->async_pf_en_msr = msrs[i].data;
2231 break;
bc9a839d
MT		 2232 case MSR_KVM_PV_EOI_EN:
2233 env->pv_eoi_en_msr = msrs[i].data;
2234 break;
917367aa
MT		 2235 case MSR_KVM_STEAL_TIME:
2236 env->steal_time_msr = msrs[i].data;
2237 break;
0d894367
PB		 2238 case MSR_CORE_PERF_FIXED_CTR_CTRL:
2239 env->msr_fixed_ctr_ctrl = msrs[i].data;
2240 break;
2241 case MSR_CORE_PERF_GLOBAL_CTRL:
2242 env->msr_global_ctrl = msrs[i].data;
2243 break;
2244 case MSR_CORE_PERF_GLOBAL_STATUS:
2245 env->msr_global_status = msrs[i].data;
2246 break;
2247 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
2248 env->msr_global_ovf_ctrl = msrs[i].data;
2249 break;
2250 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
2251 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
2252 break;
2253 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
2254 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
2255 break;
2256 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
2257 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
2258 break;
1c90ef26
VR		 2259 case HV_X64_MSR_HYPERCALL:
2260 env->msr_hv_hypercall = msrs[i].data;
2261 break;
2262 case HV_X64_MSR_GUEST_OS_ID:
2263 env->msr_hv_guest_os_id = msrs[i].data;
2264 break;
5ef68987
VR		 2265 case HV_X64_MSR_APIC_ASSIST_PAGE:
2266 env->msr_hv_vapic = msrs[i].data;
2267 break;
48a5f3bc
VR		 2268 case HV_X64_MSR_REFERENCE_TSC:
2269 env->msr_hv_tsc = msrs[i].data;
2270 break;
f2a53c9e
AS		 2271 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2272 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
2273 break;
46eb8f98
AS		 2274 case HV_X64_MSR_VP_RUNTIME:
2275 env->msr_hv_runtime = msrs[i].data;
2276 break;
866eea9a
AS		 2277 case HV_X64_MSR_SCONTROL:
2278 env->msr_hv_synic_control = msrs[i].data;
2279 break;
2280 case HV_X64_MSR_SVERSION:
2281 env->msr_hv_synic_version = msrs[i].data;
2282 break;
2283 case HV_X64_MSR_SIEFP:
2284 env->msr_hv_synic_evt_page = msrs[i].data;
2285 break;
2286 case HV_X64_MSR_SIMP:
2287 env->msr_hv_synic_msg_page = msrs[i].data;
2288 break;
2289 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
2290 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
ff99aa64
AS		 2291 break;
2292 case HV_X64_MSR_STIMER0_CONFIG:
2293 case HV_X64_MSR_STIMER1_CONFIG:
2294 case HV_X64_MSR_STIMER2_CONFIG:
2295 case HV_X64_MSR_STIMER3_CONFIG:
2296 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
2297 msrs[i].data;
2298 break;
2299 case HV_X64_MSR_STIMER0_COUNT:
2300 case HV_X64_MSR_STIMER1_COUNT:
2301 case HV_X64_MSR_STIMER2_COUNT:
2302 case HV_X64_MSR_STIMER3_COUNT:
2303 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
2304 msrs[i].data;
866eea9a 2305 break;
d1ae67f6
AW		 2306 case MSR_MTRRdefType:
2307 env->mtrr_deftype = msrs[i].data;
2308 break;
2309 case MSR_MTRRfix64K_00000:
2310 env->mtrr_fixed[0] = msrs[i].data;
2311 break;
2312 case MSR_MTRRfix16K_80000:
2313 env->mtrr_fixed[1] = msrs[i].data;
2314 break;
2315 case MSR_MTRRfix16K_A0000:
2316 env->mtrr_fixed[2] = msrs[i].data;
2317 break;
2318 case MSR_MTRRfix4K_C0000:
2319 env->mtrr_fixed[3] = msrs[i].data;
2320 break;
2321 case MSR_MTRRfix4K_C8000:
2322 env->mtrr_fixed[4] = msrs[i].data;
2323 break;
2324 case MSR_MTRRfix4K_D0000:
2325 env->mtrr_fixed[5] = msrs[i].data;
2326 break;
2327 case MSR_MTRRfix4K_D8000:
2328 env->mtrr_fixed[6] = msrs[i].data;
2329 break;
2330 case MSR_MTRRfix4K_E0000:
2331 env->mtrr_fixed[7] = msrs[i].data;
2332 break;
2333 case MSR_MTRRfix4K_E8000:
2334 env->mtrr_fixed[8] = msrs[i].data;
2335 break;
2336 case MSR_MTRRfix4K_F0000:
2337 env->mtrr_fixed[9] = msrs[i].data;
2338 break;
2339 case MSR_MTRRfix4K_F8000:
2340 env->mtrr_fixed[10] = msrs[i].data;
2341 break;
2342 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
2343 if (index & 1) {
fcc35e7c
DDAG		 2344 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
2345 mtrr_top_bits;
d1ae67f6
AW		 2346 } else {
2347 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
2348 }
2349 break;
05330448
AL		 2350 }
2351 }
2352
2353 return 0;
2354}
2355
1bc22652 2356static int kvm_put_mp_state(X86CPU *cpu)
9bdbe550 2357{
1bc22652 2358 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
9bdbe550 2359
1bc22652 2360 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
9bdbe550
HB		 2361}
2362
23d02d9b 2363static int kvm_get_mp_state(X86CPU *cpu)
9bdbe550 2364{
259186a7 2365 CPUState *cs = CPU(cpu);
23d02d9b 2366 CPUX86State *env = &cpu->env;
9bdbe550
HB		 2367 struct kvm_mp_state mp_state;
2368 int ret;
2369
259186a7 2370 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
9bdbe550
HB		 2371 if (ret < 0) {
2372 return ret;
2373 }
2374 env->mp_state = mp_state.mp_state;
c14750e8 2375 if (kvm_irqchip_in_kernel()) {
259186a7 2376 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
c14750e8 2377 }
9bdbe550
HB		 2378 return 0;
2379}
2380
1bc22652 2381static int kvm_get_apic(X86CPU *cpu)
680c1c6f 2382{
02e51483 2383 DeviceState *apic = cpu->apic_state;
680c1c6f
JK		 2384 struct kvm_lapic_state kapic;
2385 int ret;
2386
3d4b2649 2387 if (apic && kvm_irqchip_in_kernel()) {
1bc22652 2388 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
680c1c6f
JK		 2389 if (ret < 0) {
2390 return ret;
2391 }
2392
2393 kvm_get_apic_state(apic, &kapic);
2394 }
2395 return 0;
2396}
2397
1bc22652 2398static int kvm_put_vcpu_events(X86CPU *cpu, int level)
a0fb002c 2399{
fc12d72e 2400 CPUState *cs = CPU(cpu);
1bc22652 2401 CPUX86State *env = &cpu->env;
076796f8 2402 struct kvm_vcpu_events events = {};
a0fb002c
JK		 2403
2404 if (!kvm_has_vcpu_events()) {
2405 return 0;
2406 }
2407
31827373
JK		 2408 events.exception.injected = (env->exception_injected >= 0);
2409 events.exception.nr = env->exception_injected;
a0fb002c
JK		 2410 events.exception.has_error_code = env->has_error_code;
2411 events.exception.error_code = env->error_code;
7e680753 2412 events.exception.pad = 0;
a0fb002c
JK		 2413
2414 events.interrupt.injected = (env->interrupt_injected >= 0);
2415 events.interrupt.nr = env->interrupt_injected;
2416 events.interrupt.soft = env->soft_interrupt;
2417
2418 events.nmi.injected = env->nmi_injected;
2419 events.nmi.pending = env->nmi_pending;
2420 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
7e680753 2421 events.nmi.pad = 0;
a0fb002c
JK		 2422
2423 events.sipi_vector = env->sipi_vector;
68c6efe0 2424 events.flags = 0;
a0fb002c 2425
fc12d72e
PB		 2426 if (has_msr_smbase) {
2427 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
2428 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
2429 if (kvm_irqchip_in_kernel()) {
2430 /* As soon as these are moved to the kernel, remove them
2431 * from cs->interrupt_request.
2432 */
2433 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
2434 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
2435 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
2436 } else {
2437 /* Keep these in cs->interrupt_request. */
2438 events.smi.pending = 0;
2439 events.smi.latched_init = 0;
2440 }
fc3a1fd7
DDAG		 2441 /* Stop SMI delivery on old machine types to avoid a reboot
2442 * on an inward migration of an old VM.
2443 */
2444 if (!cpu->kvm_no_smi_migration) {
2445 events.flags |= KVM_VCPUEVENT_VALID_SMM;
2446 }
fc12d72e
PB		 2447 }
2448
ea643051 2449 if (level >= KVM_PUT_RESET_STATE) {
4fadfa00
PH		 2450 events.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING;
2451 if (env->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
2452 events.flags |= KVM_VCPUEVENT_VALID_SIPI_VECTOR;
2453 }
ea643051 2454 }
aee028b9 2455
1bc22652 2456 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
a0fb002c
JK		 2457}
2458
1bc22652 2459static int kvm_get_vcpu_events(X86CPU *cpu)
a0fb002c 2460{
1bc22652 2461 CPUX86State *env = &cpu->env;
a0fb002c
JK		 2462 struct kvm_vcpu_events events;
2463 int ret;
2464
2465 if (!kvm_has_vcpu_events()) {
2466 return 0;
2467 }
2468
fc12d72e 2469 memset(&events, 0, sizeof(events));
1bc22652 2470 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
a0fb002c
JK		 2471 if (ret < 0) {
2472 return ret;
2473 }
31827373 2474 env->exception_injected =
a0fb002c
JK		 2475 events.exception.injected ? events.exception.nr : -1;
2476 env->has_error_code = events.exception.has_error_code;
2477 env->error_code = events.exception.error_code;
2478
2479 env->interrupt_injected =
2480 events.interrupt.injected ? events.interrupt.nr : -1;
2481 env->soft_interrupt = events.interrupt.soft;
2482
2483 env->nmi_injected = events.nmi.injected;
2484 env->nmi_pending = events.nmi.pending;
2485 if (events.nmi.masked) {
2486 env->hflags2 |= HF2_NMI_MASK;
2487 } else {
2488 env->hflags2 &= ~HF2_NMI_MASK;
2489 }
2490
fc12d72e
PB		 2491 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2492 if (events.smi.smm) {
2493 env->hflags |= HF_SMM_MASK;
2494 } else {
2495 env->hflags &= ~HF_SMM_MASK;
2496 }
2497 if (events.smi.pending) {
2498 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2499 } else {
2500 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2501 }
2502 if (events.smi.smm_inside_nmi) {
2503 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2504 } else {
2505 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2506 }
2507 if (events.smi.latched_init) {
2508 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2509 } else {
2510 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2511 }
2512 }
2513
a0fb002c 2514 env->sipi_vector = events.sipi_vector;
a0fb002c
JK		 2515
2516 return 0;
2517}
2518
1bc22652 2519static int kvm_guest_debug_workarounds(X86CPU *cpu)
b0b1d690 2520{
ed2803da 2521 CPUState *cs = CPU(cpu);
1bc22652 2522 CPUX86State *env = &cpu->env;
b0b1d690 2523 int ret = 0;
b0b1d690
JK		 2524 unsigned long reinject_trap = 0;
2525
2526 if (!kvm_has_vcpu_events()) {
2527 if (env->exception_injected == 1) {
2528 reinject_trap = KVM_GUESTDBG_INJECT_DB;
2529 } else if (env->exception_injected == 3) {
2530 reinject_trap = KVM_GUESTDBG_INJECT_BP;
2531 }
2532 env->exception_injected = -1;
2533 }
2534
2535 /*
2536 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2537 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2538 * by updating the debug state once again if single-stepping is on.
2539 * Another reason to call kvm_update_guest_debug here is a pending debug
2540 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2541 * reinject them via SET_GUEST_DEBUG.
2542 */
2543 if (reinject_trap ||
ed2803da 2544 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
38e478ec 2545 ret = kvm_update_guest_debug(cs, reinject_trap);
b0b1d690 2546 }
b0b1d690
JK		 2547 return ret;
2548}
2549
1bc22652 2550static int kvm_put_debugregs(X86CPU *cpu)
ff44f1a3 2551{
1bc22652 2552 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 2553 struct kvm_debugregs dbgregs;
2554 int i;
2555
2556 if (!kvm_has_debugregs()) {
2557 return 0;
2558 }
2559
2560 for (i = 0; i < 4; i++) {
2561 dbgregs.db[i] = env->dr[i];
2562 }
2563 dbgregs.dr6 = env->dr[6];
2564 dbgregs.dr7 = env->dr[7];
2565 dbgregs.flags = 0;
2566
1bc22652 2567 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
ff44f1a3
JK		 2568}
2569
1bc22652 2570static int kvm_get_debugregs(X86CPU *cpu)
ff44f1a3 2571{
1bc22652 2572 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 2573 struct kvm_debugregs dbgregs;
2574 int i, ret;
2575
2576 if (!kvm_has_debugregs()) {
2577 return 0;
2578 }
2579
1bc22652 2580 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
ff44f1a3 2581 if (ret < 0) {
b9bec74b 2582 return ret;
ff44f1a3
JK		 2583 }
2584 for (i = 0; i < 4; i++) {
2585 env->dr[i] = dbgregs.db[i];
2586 }
2587 env->dr[4] = env->dr[6] = dbgregs.dr6;
2588 env->dr[5] = env->dr[7] = dbgregs.dr7;
ff44f1a3
JK		 2589
2590 return 0;
2591}
2592
20d695a9 2593int kvm_arch_put_registers(CPUState *cpu, int level)
05330448 2594{
20d695a9 2595 X86CPU *x86_cpu = X86_CPU(cpu);
05330448
AL		 2596 int ret;
2597
2fa45344 2598 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
dbaa07c4 2599
48e1a45c 2600 if (level >= KVM_PUT_RESET_STATE) {
6bdf863d
JK		 2601 ret = kvm_put_msr_feature_control(x86_cpu);
2602 if (ret < 0) {
2603 return ret;
2604 }
2605 }
2606
36f96c4b
HZ		 2607 if (level == KVM_PUT_FULL_STATE) {
2608 /* We don't check for kvm_arch_set_tsc_khz() errors here,
2609 * because TSC frequency mismatch shouldn't abort migration,
2610 * unless the user explicitly asked for a more strict TSC
2611 * setting (e.g. using an explicit "tsc-freq" option).
2612 */
2613 kvm_arch_set_tsc_khz(cpu);
2614 }
2615
1bc22652 2616 ret = kvm_getput_regs(x86_cpu, 1);
b9bec74b 2617 if (ret < 0) {
05330448 2618 return ret;
b9bec74b 2619 }
1bc22652 2620 ret = kvm_put_xsave(x86_cpu);
b9bec74b 2621 if (ret < 0) {
f1665b21 2622 return ret;
b9bec74b 2623 }
1bc22652 2624 ret = kvm_put_xcrs(x86_cpu);
b9bec74b 2625 if (ret < 0) {
05330448 2626 return ret;
b9bec74b 2627 }
1bc22652 2628 ret = kvm_put_sregs(x86_cpu);
b9bec74b 2629 if (ret < 0) {
05330448 2630 return ret;
b9bec74b 2631 }
ab443475 2632 /* must be before kvm_put_msrs */
1bc22652 2633 ret = kvm_inject_mce_oldstyle(x86_cpu);
ab443475
JK		 2634 if (ret < 0) {
2635 return ret;
2636 }
1bc22652 2637 ret = kvm_put_msrs(x86_cpu, level);
b9bec74b 2638 if (ret < 0) {
05330448 2639 return ret;
b9bec74b 2640 }
4fadfa00
PH		 2641 ret = kvm_put_vcpu_events(x86_cpu, level);
2642 if (ret < 0) {
2643 return ret;
2644 }
ea643051 2645 if (level >= KVM_PUT_RESET_STATE) {
1bc22652 2646 ret = kvm_put_mp_state(x86_cpu);
b9bec74b 2647 if (ret < 0) {
680c1c6f
JK		 2648 return ret;
2649 }
ea643051 2650 }
7477cd38
MT		 2651
2652 ret = kvm_put_tscdeadline_msr(x86_cpu);
2653 if (ret < 0) {
2654 return ret;
2655 }
1bc22652 2656 ret = kvm_put_debugregs(x86_cpu);
b9bec74b 2657 if (ret < 0) {
b0b1d690 2658 return ret;
b9bec74b 2659 }
b0b1d690 2660 /* must be last */
1bc22652 2661 ret = kvm_guest_debug_workarounds(x86_cpu);
b9bec74b 2662 if (ret < 0) {
ff44f1a3 2663 return ret;
b9bec74b 2664 }
05330448
AL		 2665 return 0;
2666}
2667
20d695a9 2668int kvm_arch_get_registers(CPUState *cs)
05330448 2669{
20d695a9 2670 X86CPU *cpu = X86_CPU(cs);
05330448
AL		 2671 int ret;
2672
20d695a9 2673 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
dbaa07c4 2674
4fadfa00 2675 ret = kvm_get_vcpu_events(cpu);
b9bec74b 2676 if (ret < 0) {
f4f1110e 2677 goto out;
b9bec74b 2678 }
4fadfa00
PH		 2679 /*
2680 * KVM_GET_MPSTATE can modify CS and RIP, call it before
2681 * KVM_GET_REGS and KVM_GET_SREGS.
2682 */
2683 ret = kvm_get_mp_state(cpu);
b9bec74b 2684 if (ret < 0) {
f4f1110e 2685 goto out;
b9bec74b 2686 }
4fadfa00 2687 ret = kvm_getput_regs(cpu, 0);
b9bec74b 2688 if (ret < 0) {
f4f1110e 2689 goto out;
b9bec74b 2690 }
4fadfa00 2691 ret = kvm_get_xsave(cpu);
b9bec74b 2692 if (ret < 0) {
f4f1110e 2693 goto out;
b9bec74b 2694 }
4fadfa00 2695 ret = kvm_get_xcrs(cpu);
b9bec74b 2696 if (ret < 0) {
f4f1110e 2697 goto out;
b9bec74b 2698 }
4fadfa00 2699 ret = kvm_get_sregs(cpu);
b9bec74b 2700 if (ret < 0) {
f4f1110e 2701 goto out;
b9bec74b 2702 }
4fadfa00 2703 ret = kvm_get_msrs(cpu);
680c1c6f 2704 if (ret < 0) {
f4f1110e 2705 goto out;
680c1c6f 2706 }
4fadfa00 2707 ret = kvm_get_apic(cpu);
b9bec74b 2708 if (ret < 0) {
f4f1110e 2709 goto out;
b9bec74b 2710 }
1bc22652 2711 ret = kvm_get_debugregs(cpu);
b9bec74b 2712 if (ret < 0) {
f4f1110e 2713 goto out;
b9bec74b 2714 }
f4f1110e
RH		 2715 ret = 0;
2716 out:
2717 cpu_sync_bndcs_hflags(&cpu->env);
2718 return ret;
05330448
AL		 2719}
2720
20d695a9 2721void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
05330448 2722{
20d695a9
AF		 2723 X86CPU *x86_cpu = X86_CPU(cpu);
2724 CPUX86State *env = &x86_cpu->env;
ce377af3
JK		 2725 int ret;
2726
276ce815 2727 /* Inject NMI */
fc12d72e
PB		 2728 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
2729 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
2730 qemu_mutex_lock_iothread();
2731 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
2732 qemu_mutex_unlock_iothread();
2733 DPRINTF("injected NMI\n");
2734 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
2735 if (ret < 0) {
2736 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
2737 strerror(-ret));
2738 }
2739 }
2740 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
2741 qemu_mutex_lock_iothread();
2742 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
2743 qemu_mutex_unlock_iothread();
2744 DPRINTF("injected SMI\n");
2745 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
2746 if (ret < 0) {
2747 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
2748 strerror(-ret));
2749 }
ce377af3 2750 }
276ce815
LJ		 2751 }
2752
15eafc2e 2753 if (!kvm_pic_in_kernel()) {
4b8523ee
JK		 2754 qemu_mutex_lock_iothread();
2755 }
2756
e0723c45
PB		 2757 /* Force the VCPU out of its inner loop to process any INIT requests
2758 * or (for userspace APIC, but it is cheap to combine the checks here)
2759 * pending TPR access reports.
2760 */
2761 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
fc12d72e
PB		 2762 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
2763 !(env->hflags & HF_SMM_MASK)) {
2764 cpu->exit_request = 1;
2765 }
2766 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
2767 cpu->exit_request = 1;
2768 }
e0723c45 2769 }
05330448 2770
15eafc2e 2771 if (!kvm_pic_in_kernel()) {
db1669bc
JK		 2772 /* Try to inject an interrupt if the guest can accept it */
2773 if (run->ready_for_interrupt_injection &&
259186a7 2774 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
db1669bc
JK		 2775 (env->eflags & IF_MASK)) {
2776 int irq;
2777
259186a7 2778 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
db1669bc
JK		 2779 irq = cpu_get_pic_interrupt(env);
2780 if (irq >= 0) {
2781 struct kvm_interrupt intr;
2782
2783 intr.irq = irq;
db1669bc 2784 DPRINTF("injected interrupt %d\n", irq);
1bc22652 2785 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
ce377af3
JK		 2786 if (ret < 0) {
2787 fprintf(stderr,
2788 "KVM: injection failed, interrupt lost (%s)\n",
2789 strerror(-ret));
2790 }
db1669bc
JK		 2791 }
2792 }
05330448 2793
db1669bc
JK		 2794 /* If we have an interrupt but the guest is not ready to receive an
2795 * interrupt, request an interrupt window exit. This will
2796 * cause a return to userspace as soon as the guest is ready to
2797 * receive interrupts. */
259186a7 2798 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
db1669bc
JK		 2799 run->request_interrupt_window = 1;
2800 } else {
2801 run->request_interrupt_window = 0;
2802 }
2803
2804 DPRINTF("setting tpr\n");
02e51483 2805 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
4b8523ee
JK		 2806
2807 qemu_mutex_unlock_iothread();
db1669bc 2808 }
05330448
AL		 2809}
2810
4c663752 2811MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
05330448 2812{
20d695a9
AF		 2813 X86CPU *x86_cpu = X86_CPU(cpu);
2814 CPUX86State *env = &x86_cpu->env;
2815
fc12d72e
PB		 2816 if (run->flags & KVM_RUN_X86_SMM) {
2817 env->hflags |= HF_SMM_MASK;
2818 } else {
f5c052b9 2819 env->hflags &= ~HF_SMM_MASK;
fc12d72e 2820 }
b9bec74b 2821 if (run->if_flag) {
05330448 2822 env->eflags |= IF_MASK;
b9bec74b 2823 } else {
05330448 2824 env->eflags &= ~IF_MASK;
b9bec74b 2825 }
4b8523ee
JK		 2826
2827 /* We need to protect the apic state against concurrent accesses from
2828 * different threads in case the userspace irqchip is used. */
2829 if (!kvm_irqchip_in_kernel()) {
2830 qemu_mutex_lock_iothread();
2831 }
02e51483
CF		 2832 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
2833 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
4b8523ee
JK		 2834 if (!kvm_irqchip_in_kernel()) {
2835 qemu_mutex_unlock_iothread();
2836 }
f794aa4a 2837 return cpu_get_mem_attrs(env);
05330448
AL		 2838}
2839
20d695a9 2840int kvm_arch_process_async_events(CPUState *cs)
0af691d7 2841{
20d695a9
AF		 2842 X86CPU *cpu = X86_CPU(cs);
2843 CPUX86State *env = &cpu->env;
232fc23b 2844
259186a7 2845 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
ab443475
JK		 2846 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
2847 assert(env->mcg_cap);
2848
259186a7 2849 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
ab443475 2850
dd1750d7 2851 kvm_cpu_synchronize_state(cs);
ab443475
JK		 2852
2853 if (env->exception_injected == EXCP08_DBLE) {
2854 /* this means triple fault */
cf83f140 2855 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
fcd7d003 2856 cs->exit_request = 1;
ab443475
JK		 2857 return 0;
2858 }
2859 env->exception_injected = EXCP12_MCHK;
2860 env->has_error_code = 0;
2861
259186a7 2862 cs->halted = 0;
ab443475
JK		 2863 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
2864 env->mp_state = KVM_MP_STATE_RUNNABLE;
2865 }
2866 }
2867
fc12d72e
PB		 2868 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
2869 !(env->hflags & HF_SMM_MASK)) {
e0723c45
PB		 2870 kvm_cpu_synchronize_state(cs);
2871 do_cpu_init(cpu);
2872 }
2873
db1669bc
JK		 2874 if (kvm_irqchip_in_kernel()) {
2875 return 0;
2876 }
2877
259186a7
AF		 2878 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2879 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
02e51483 2880 apic_poll_irq(cpu->apic_state);
5d62c43a 2881 }
259186a7 2882 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
4601f7b0 2883 (env->eflags & IF_MASK)) ||
259186a7
AF		 2884 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2885 cs->halted = 0;
6792a57b 2886 }
259186a7 2887 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
dd1750d7 2888 kvm_cpu_synchronize_state(cs);
232fc23b 2889 do_cpu_sipi(cpu);
0af691d7 2890 }
259186a7
AF		 2891 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
2892 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
dd1750d7 2893 kvm_cpu_synchronize_state(cs);
02e51483 2894 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
d362e757
JK		 2895 env->tpr_access_type);
2896 }
0af691d7 2897
259186a7 2898 return cs->halted;
0af691d7
MT		 2899}
2900
839b5630 2901static int kvm_handle_halt(X86CPU *cpu)
05330448 2902{
259186a7 2903 CPUState *cs = CPU(cpu);
839b5630
AF		 2904 CPUX86State *env = &cpu->env;
2905
259186a7 2906 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
05330448 2907 (env->eflags & IF_MASK)) &&
259186a7
AF		 2908 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2909 cs->halted = 1;
bb4ea393 2910 return EXCP_HLT;
05330448
AL		 2911 }
2912
bb4ea393 2913 return 0;
05330448
AL		 2914}
2915
f7575c96 2916static int kvm_handle_tpr_access(X86CPU *cpu)
d362e757 2917{
f7575c96
AF		 2918 CPUState *cs = CPU(cpu);
2919 struct kvm_run *run = cs->kvm_run;
d362e757 2920
02e51483 2921 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
d362e757
JK		 2922 run->tpr_access.is_write ? TPR_ACCESS_WRITE
2923 : TPR_ACCESS_READ);
2924 return 1;
2925}
2926
f17ec444 2927int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9 2928{
38972938 2929 static const uint8_t int3 = 0xcc;
64bf3f4e 2930
f17ec444
AF		 2931 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
2932 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
e22a25c9 2933 return -EINVAL;
b9bec74b 2934 }
e22a25c9
AL		 2935 return 0;
2936}
2937
f17ec444 2938int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9
AL		 2939{
2940 uint8_t int3;
2941
f17ec444
AF		 2942 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
2943 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
e22a25c9 2944 return -EINVAL;
b9bec74b 2945 }
e22a25c9
AL		 2946 return 0;
2947}
2948
2949static struct {
2950 target_ulong addr;
2951 int len;
2952 int type;
2953} hw_breakpoint[4];
2954
2955static int nb_hw_breakpoint;
2956
2957static int find_hw_breakpoint(target_ulong addr, int len, int type)
2958{
2959 int n;
2960
b9bec74b 2961 for (n = 0; n < nb_hw_breakpoint; n++) {
e22a25c9 2962 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
b9bec74b 2963 (hw_breakpoint[n].len == len || len == -1)) {
e22a25c9 2964 return n;
b9bec74b
JK		 2965 }
2966 }
e22a25c9
AL		 2967 return -1;
2968}
2969
2970int kvm_arch_insert_hw_breakpoint(target_ulong addr,
2971 target_ulong len, int type)
2972{
2973 switch (type) {
2974 case GDB_BREAKPOINT_HW:
2975 len = 1;
2976 break;
2977 case GDB_WATCHPOINT_WRITE:
2978 case GDB_WATCHPOINT_ACCESS:
2979 switch (len) {
2980 case 1:
2981 break;
2982 case 2:
2983 case 4:
2984 case 8:
b9bec74b 2985 if (addr & (len - 1)) {
e22a25c9 2986 return -EINVAL;
b9bec74b 2987 }
e22a25c9
AL		 2988 break;
2989 default:
2990 return -EINVAL;
2991 }
2992 break;
2993 default:
2994 return -ENOSYS;
2995 }
2996
b9bec74b 2997 if (nb_hw_breakpoint == 4) {
e22a25c9 2998 return -ENOBUFS;
b9bec74b
JK		 2999 }
3000 if (find_hw_breakpoint(addr, len, type) >= 0) {
e22a25c9 3001 return -EEXIST;
b9bec74b 3002 }
e22a25c9
AL		 3003 hw_breakpoint[nb_hw_breakpoint].addr = addr;
3004 hw_breakpoint[nb_hw_breakpoint].len = len;
3005 hw_breakpoint[nb_hw_breakpoint].type = type;
3006 nb_hw_breakpoint++;
3007
3008 return 0;
3009}
3010
3011int kvm_arch_remove_hw_breakpoint(target_ulong addr,
3012 target_ulong len, int type)
3013{
3014 int n;
3015
3016 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
b9bec74b 3017 if (n < 0) {
e22a25c9 3018 return -ENOENT;
b9bec74b 3019 }
e22a25c9
AL		 3020 nb_hw_breakpoint--;
3021 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
3022
3023 return 0;
3024}
3025
3026void kvm_arch_remove_all_hw_breakpoints(void)
3027{
3028 nb_hw_breakpoint = 0;
3029}
3030
3031static CPUWatchpoint hw_watchpoint;
3032
a60f24b5 3033static int kvm_handle_debug(X86CPU *cpu,
48405526 3034 struct kvm_debug_exit_arch *arch_info)
e22a25c9 3035{
ed2803da 3036 CPUState *cs = CPU(cpu);
a60f24b5 3037 CPUX86State *env = &cpu->env;
f2574737 3038 int ret = 0;
e22a25c9
AL		 3039 int n;
3040
3041 if (arch_info->exception == 1) {
3042 if (arch_info->dr6 & (1 << 14)) {
ed2803da 3043 if (cs->singlestep_enabled) {
f2574737 3044 ret = EXCP_DEBUG;
b9bec74b 3045 }
e22a25c9 3046 } else {
b9bec74b
JK		 3047 for (n = 0; n < 4; n++) {
3048 if (arch_info->dr6 & (1 << n)) {
e22a25c9
AL		 3049 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
3050 case 0x0:
f2574737 3051 ret = EXCP_DEBUG;
e22a25c9
AL		 3052 break;
3053 case 0x1:
f2574737 3054 ret = EXCP_DEBUG;
ff4700b0 3055 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 3056 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3057 hw_watchpoint.flags = BP_MEM_WRITE;
3058 break;
3059 case 0x3:
f2574737 3060 ret = EXCP_DEBUG;
ff4700b0 3061 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 3062 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3063 hw_watchpoint.flags = BP_MEM_ACCESS;
3064 break;
3065 }
b9bec74b
JK		 3066 }
3067 }
e22a25c9 3068 }
ff4700b0 3069 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
f2574737 3070 ret = EXCP_DEBUG;
b9bec74b 3071 }
f2574737 3072 if (ret == 0) {
ff4700b0 3073 cpu_synchronize_state(cs);
48405526 3074 assert(env->exception_injected == -1);
b0b1d690 3075
f2574737 3076 /* pass to guest */
48405526
BS		 3077 env->exception_injected = arch_info->exception;
3078 env->has_error_code = 0;
b0b1d690 3079 }
e22a25c9 3080
f2574737 3081 return ret;
e22a25c9
AL		 3082}
3083
20d695a9 3084void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
e22a25c9
AL		 3085{
3086 const uint8_t type_code[] = {
3087 [GDB_BREAKPOINT_HW] = 0x0,
3088 [GDB_WATCHPOINT_WRITE] = 0x1,
3089 [GDB_WATCHPOINT_ACCESS] = 0x3
3090 };
3091 const uint8_t len_code[] = {
3092 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
3093 };
3094 int n;
3095
a60f24b5 3096 if (kvm_sw_breakpoints_active(cpu)) {
e22a25c9 3097 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
b9bec74b 3098 }
e22a25c9
AL		 3099 if (nb_hw_breakpoint > 0) {
3100 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
3101 dbg->arch.debugreg[7] = 0x0600;
3102 for (n = 0; n < nb_hw_breakpoint; n++) {
3103 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
3104 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
3105 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
95c077c9 3106 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
e22a25c9
AL		 3107 }
3108 }
3109}
4513d923 3110
2a4dac83
JK		 3111static bool host_supports_vmx(void)
3112{
3113 uint32_t ecx, unused;
3114
3115 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
3116 return ecx & CPUID_EXT_VMX;
3117}
3118
3119#define VMX_INVALID_GUEST_STATE 0x80000021
3120
20d695a9 3121int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2a4dac83 3122{
20d695a9 3123 X86CPU *cpu = X86_CPU(cs);
2a4dac83
JK		 3124 uint64_t code;
3125 int ret;
3126
3127 switch (run->exit_reason) {
3128 case KVM_EXIT_HLT:
3129 DPRINTF("handle_hlt\n");
4b8523ee 3130 qemu_mutex_lock_iothread();
839b5630 3131 ret = kvm_handle_halt(cpu);
4b8523ee 3132 qemu_mutex_unlock_iothread();
2a4dac83
JK		 3133 break;
3134 case KVM_EXIT_SET_TPR:
3135 ret = 0;
3136 break;
d362e757 3137 case KVM_EXIT_TPR_ACCESS:
4b8523ee 3138 qemu_mutex_lock_iothread();
f7575c96 3139 ret = kvm_handle_tpr_access(cpu);
4b8523ee 3140 qemu_mutex_unlock_iothread();
d362e757 3141 break;
2a4dac83
JK		 3142 case KVM_EXIT_FAIL_ENTRY:
3143 code = run->fail_entry.hardware_entry_failure_reason;
3144 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
3145 code);
3146 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
3147 fprintf(stderr,
12619721 3148 "\nIf you're running a guest on an Intel machine without "
2a4dac83
JK		 3149 "unrestricted mode\n"
3150 "support, the failure can be most likely due to the guest "
3151 "entering an invalid\n"
3152 "state for Intel VT. For example, the guest maybe running "
3153 "in big real mode\n"
3154 "which is not supported on less recent Intel processors."
3155 "\n\n");
3156 }
3157 ret = -1;
3158 break;
3159 case KVM_EXIT_EXCEPTION:
3160 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
3161 run->ex.exception, run->ex.error_code);
3162 ret = -1;
3163 break;
f2574737
JK		 3164 case KVM_EXIT_DEBUG:
3165 DPRINTF("kvm_exit_debug\n");
4b8523ee 3166 qemu_mutex_lock_iothread();
a60f24b5 3167 ret = kvm_handle_debug(cpu, &run->debug.arch);
4b8523ee 3168 qemu_mutex_unlock_iothread();
f2574737 3169 break;
50efe82c
AS		 3170 case KVM_EXIT_HYPERV:
3171 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
3172 break;
15eafc2e
PB		 3173 case KVM_EXIT_IOAPIC_EOI:
3174 ioapic_eoi_broadcast(run->eoi.vector);
3175 ret = 0;
3176 break;
2a4dac83
JK		 3177 default:
3178 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
3179 ret = -1;
3180 break;
3181 }
3182
3183 return ret;
3184}
3185
20d695a9 3186bool kvm_arch_stop_on_emulation_error(CPUState *cs)
4513d923 3187{
20d695a9
AF		 3188 X86CPU *cpu = X86_CPU(cs);
3189 CPUX86State *env = &cpu->env;
3190
dd1750d7 3191 kvm_cpu_synchronize_state(cs);
b9bec74b
JK		 3192 return !(env->cr[0] & CR0_PE_MASK) ||
3193 ((env->segs[R_CS].selector & 3) != 3);
4513d923 3194}
84b058d7
JK		 3195
3196void kvm_arch_init_irq_routing(KVMState *s)
3197{
3198 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
3199 /* If kernel can't do irq routing, interrupt source
3200 * override 0->2 cannot be set up as required by HPET.
3201 * So we have to disable it.
3202 */
3203 no_hpet = 1;
3204 }
cc7e0ddf 3205 /* We know at this point that we're using the in-kernel
614e41bc 3206 * irqchip, so we can use irqfds, and on x86 we know
f3e1bed8 3207 * we can use msi via irqfd and GSI routing.
cc7e0ddf 3208 */
614e41bc 3209 kvm_msi_via_irqfd_allowed = true;
f3e1bed8 3210 kvm_gsi_routing_allowed = true;
15eafc2e
PB		 3211
3212 if (kvm_irqchip_is_split()) {
3213 int i;
3214
3215 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
3216 MSI routes for signaling interrupts to the local apics. */
3217 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
d1f6af6a 3218 if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
15eafc2e
PB		 3219 error_report("Could not enable split IRQ mode.");
3220 exit(1);
3221 }
3222 }
3223 }
3224}
3225
3226int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
3227{
3228 int ret;
3229 if (machine_kernel_irqchip_split(ms)) {
3230 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
3231 if (ret) {
df3c286c 3232 error_report("Could not enable split irqchip mode: %s",
15eafc2e
PB		 3233 strerror(-ret));
3234 exit(1);
3235 } else {
3236 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
3237 kvm_split_irqchip = true;
3238 return 1;
3239 }
3240 } else {
3241 return 0;
3242 }
84b058d7 3243}
b139bd30
JK		 3244
3245/* Classic KVM device assignment interface. Will remain x86 only. */
3246int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
3247 uint32_t flags, uint32_t *dev_id)
3248{
3249 struct kvm_assigned_pci_dev dev_data = {
3250 .segnr = dev_addr->domain,
3251 .busnr = dev_addr->bus,
3252 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
3253 .flags = flags,
3254 };
3255 int ret;
3256
3257 dev_data.assigned_dev_id =
3258 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
3259
3260 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
3261 if (ret < 0) {
3262 return ret;
3263 }
3264
3265 *dev_id = dev_data.assigned_dev_id;
3266
3267 return 0;
3268}
3269
3270int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
3271{
3272 struct kvm_assigned_pci_dev dev_data = {
3273 .assigned_dev_id = dev_id,
3274 };
3275
3276 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
3277}
3278
3279static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
3280 uint32_t irq_type, uint32_t guest_irq)
3281{
3282 struct kvm_assigned_irq assigned_irq = {
3283 .assigned_dev_id = dev_id,
3284 .guest_irq = guest_irq,
3285 .flags = irq_type,
3286 };
3287
3288 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
3289 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
3290 } else {
3291 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
3292 }
3293}
3294
3295int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
3296 uint32_t guest_irq)
3297{
3298 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
3299 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
3300
3301 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
3302}
3303
3304int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
3305{
3306 struct kvm_assigned_pci_dev dev_data = {
3307 .assigned_dev_id = dev_id,
3308 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
3309 };
3310
3311 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
3312}
3313
3314static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
3315 uint32_t type)
3316{
3317 struct kvm_assigned_irq assigned_irq = {
3318 .assigned_dev_id = dev_id,
3319 .flags = type,
3320 };
3321
3322 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
3323}
3324
3325int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
3326{
3327 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
3328 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
3329}
3330
3331int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
3332{
3333 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
3334 KVM_DEV_IRQ_GUEST_MSI, virq);
3335}
3336
3337int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
3338{
3339 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
3340 KVM_DEV_IRQ_HOST_MSI);
3341}
3342
3343bool kvm_device_msix_supported(KVMState *s)
3344{
3345 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
3346 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
3347 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
3348}
3349
3350int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
3351 uint32_t nr_vectors)
3352{
3353 struct kvm_assigned_msix_nr msix_nr = {
3354 .assigned_dev_id = dev_id,
3355 .entry_nr = nr_vectors,
3356 };
3357
3358 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
3359}
3360
3361int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
3362 int virq)
3363{
3364 struct kvm_assigned_msix_entry msix_entry = {
3365 .assigned_dev_id = dev_id,
3366 .gsi = virq,
3367 .entry = vector,
3368 };
3369
3370 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
3371}
3372
3373int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
3374{
3375 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
3376 KVM_DEV_IRQ_GUEST_MSIX, 0);
3377}
3378
3379int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
3380{
3381 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
3382 KVM_DEV_IRQ_HOST_MSIX);
3383}
9e03a040
FB		 3384
3385int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
dc9f06ca 3386 uint64_t address, uint32_t data, PCIDevice *dev)
9e03a040 3387{
8b5ed7df
PX		 3388 X86IOMMUState *iommu = x86_iommu_get_default();
3389
3390 if (iommu) {
3391 int ret;
3392 MSIMessage src, dst;
3393 X86IOMMUClass *class = X86_IOMMU_GET_CLASS(iommu);
3394
3395 src.address = route->u.msi.address_hi;
3396 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
3397 src.address |= route->u.msi.address_lo;
3398 src.data = route->u.msi.data;
3399
3400 ret = class->int_remap(iommu, &src, &dst, dev ? \
3401 pci_requester_id(dev) : \
3402 X86_IOMMU_SID_INVALID);
3403 if (ret) {
3404 trace_kvm_x86_fixup_msi_error(route->gsi);
3405 return 1;
3406 }
3407
3408 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
3409 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
3410 route->u.msi.data = dst.data;
3411 }
3412
9e03a040
FB		 3413 return 0;
3414}
1850b6b7 3415
38d87493
PX		 3416typedef struct MSIRouteEntry MSIRouteEntry;
3417
3418struct MSIRouteEntry {
3419 PCIDevice *dev; /* Device pointer */
3420 int vector; /* MSI/MSIX vector index */
3421 int virq; /* Virtual IRQ index */
3422 QLIST_ENTRY(MSIRouteEntry) list;
3423};
3424
3425/* List of used GSI routes */
3426static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
3427 QLIST_HEAD_INITIALIZER(msi_route_list);
3428
e1d4fb2d
PX		 3429static void kvm_update_msi_routes_all(void *private, bool global,
3430 uint32_t index, uint32_t mask)
3431{
3432 int cnt = 0;
3433 MSIRouteEntry *entry;
3434 MSIMessage msg;
fd563564
PX		 3435 PCIDevice *dev;
3436
e1d4fb2d
PX		 3437 /* TODO: explicit route update */
3438 QLIST_FOREACH(entry, &msi_route_list, list) {
3439 cnt++;
fd563564
PX		 3440 dev = entry->dev;
3441 if (!msix_enabled(dev) && !msi_enabled(dev)) {
3442 continue;
3443 }
3444 msg = pci_get_msi_message(dev, entry->vector);
3445 kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev);
e1d4fb2d 3446 }
3f1fea0f 3447 kvm_irqchip_commit_routes(kvm_state);
e1d4fb2d
PX		 3448 trace_kvm_x86_update_msi_routes(cnt);
3449}
3450
38d87493
PX		 3451int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
3452 int vector, PCIDevice *dev)
3453{
e1d4fb2d 3454 static bool notify_list_inited = false;
38d87493
PX		 3455 MSIRouteEntry *entry;
3456
3457 if (!dev) {
3458 /* These are (possibly) IOAPIC routes only used for split
3459 * kernel irqchip mode, while what we are housekeeping are
3460 * PCI devices only. */
3461 return 0;
3462 }
3463
3464 entry = g_new0(MSIRouteEntry, 1);
3465 entry->dev = dev;
3466 entry->vector = vector;
3467 entry->virq = route->gsi;
3468 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
3469
3470 trace_kvm_x86_add_msi_route(route->gsi);
e1d4fb2d
PX		 3471
3472 if (!notify_list_inited) {
3473 /* For the first time we do add route, add ourselves into
3474 * IOMMU's IEC notify list if needed. */
3475 X86IOMMUState *iommu = x86_iommu_get_default();
3476 if (iommu) {
3477 x86_iommu_iec_register_notifier(iommu,
3478 kvm_update_msi_routes_all,
3479 NULL);
3480 }
3481 notify_list_inited = true;
3482 }
38d87493
PX		 3483 return 0;
3484}
3485
3486int kvm_arch_release_virq_post(int virq)
3487{
3488 MSIRouteEntry *entry, *next;
3489 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
3490 if (entry->virq == virq) {
3491 trace_kvm_x86_remove_msi_route(virq);
3492 QLIST_REMOVE(entry, list);
3493 break;
3494 }
3495 }
9e03a040
FB		 3496 return 0;
3497}
1850b6b7
EA		 3498
3499int kvm_arch_msi_data_to_gsi(uint32_t data)
3500{
3501 abort();
3502}
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