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Merge remote-tracking branch 'remotes/mjt/tags/trivial-patches-2014-02-02' into staging
[qemu.git] / target-arm / helper.c
CommitLineData
b5ff1b31 1#include "cpu.h"
022c62cb 2#include "exec/gdbstub.h"
7b59220e 3#include "helper.h"
1de7afc9 4#include "qemu/host-utils.h"
78027bb6 5#include "sysemu/arch_init.h"
9c17d615 6#include "sysemu/sysemu.h"
1de7afc9 7#include "qemu/bitops.h"
0b03bdfc 8
4a501606
PM		 9#ifndef CONFIG_USER_ONLY
10static inline int get_phys_addr(CPUARMState *env, uint32_t address,
11 int access_type, int is_user,
a8170e5e 12 hwaddr *phys_ptr, int *prot,
4a501606
PM		 13 target_ulong *page_size);
14#endif
15
0ecb72a5 16static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
56aebc89
PB		 17{
18 int nregs;
19
20 /* VFP data registers are always little-endian. */
21 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
22 if (reg < nregs) {
23 stfq_le_p(buf, env->vfp.regs[reg]);
24 return 8;
25 }
26 if (arm_feature(env, ARM_FEATURE_NEON)) {
27 /* Aliases for Q regs. */
28 nregs += 16;
29 if (reg < nregs) {
30 stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
31 stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
32 return 16;
33 }
34 }
35 switch (reg - nregs) {
36 case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
37 case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
38 case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
39 }
40 return 0;
41}
42
0ecb72a5 43static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
56aebc89
PB		 44{
45 int nregs;
46
47 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
48 if (reg < nregs) {
49 env->vfp.regs[reg] = ldfq_le_p(buf);
50 return 8;
51 }
52 if (arm_feature(env, ARM_FEATURE_NEON)) {
53 nregs += 16;
54 if (reg < nregs) {
55 env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
56 env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
57 return 16;
58 }
59 }
60 switch (reg - nregs) {
61 case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
62 case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
71b3c3de 63 case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
56aebc89
PB		 64 }
65 return 0;
66}
67
6a669427
PM		 68static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
69{
70 switch (reg) {
71 case 0 ... 31:
72 /* 128 bit FP register */
73 stfq_le_p(buf, env->vfp.regs[reg * 2]);
74 stfq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]);
75 return 16;
76 case 32:
77 /* FPSR */
78 stl_p(buf, vfp_get_fpsr(env));
79 return 4;
80 case 33:
81 /* FPCR */
82 stl_p(buf, vfp_get_fpcr(env));
83 return 4;
84 default:
85 return 0;
86 }
87}
88
89static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
90{
91 switch (reg) {
92 case 0 ... 31:
93 /* 128 bit FP register */
94 env->vfp.regs[reg * 2] = ldfq_le_p(buf);
95 env->vfp.regs[reg * 2 + 1] = ldfq_le_p(buf + 8);
96 return 16;
97 case 32:
98 /* FPSR */
99 vfp_set_fpsr(env, ldl_p(buf));
100 return 4;
101 case 33:
102 /* FPCR */
103 vfp_set_fpcr(env, ldl_p(buf));
104 return 4;
105 default:
106 return 0;
107 }
108}
109
d4e6df63
PM		 110static int raw_read(CPUARMState *env, const ARMCPRegInfo *ri,
111 uint64_t *value)
112{
22d9e1a9
PM		 113 if (ri->type & ARM_CP_64BIT) {
114 *value = CPREG_FIELD64(env, ri);
115 } else {
116 *value = CPREG_FIELD32(env, ri);
117 }
d4e6df63
PM		 118 return 0;
119}
120
121static int raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
122 uint64_t value)
123{
22d9e1a9
PM		 124 if (ri->type & ARM_CP_64BIT) {
125 CPREG_FIELD64(env, ri) = value;
126 } else {
127 CPREG_FIELD32(env, ri) = value;
128 }
d4e6df63
PM		 129 return 0;
130}
131
721fae12
PM		 132static bool read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
133 uint64_t *v)
134{
135 /* Raw read of a coprocessor register (as needed for migration, etc)
136 * return true on success, false if the read is impossible for some reason.
137 */
138 if (ri->type & ARM_CP_CONST) {
139 *v = ri->resetvalue;
140 } else if (ri->raw_readfn) {
141 return (ri->raw_readfn(env, ri, v) == 0);
142 } else if (ri->readfn) {
143 return (ri->readfn(env, ri, v) == 0);
144 } else {
afb2530f 145 raw_read(env, ri, v);
721fae12
PM		 146 }
147 return true;
148}
149
150static bool write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
151 int64_t v)
152{
153 /* Raw write of a coprocessor register (as needed for migration, etc).
154 * Return true on success, false if the write is impossible for some reason.
155 * Note that constant registers are treated as write-ignored; the
156 * caller should check for success by whether a readback gives the
157 * value written.
158 */
159 if (ri->type & ARM_CP_CONST) {
160 return true;
161 } else if (ri->raw_writefn) {
162 return (ri->raw_writefn(env, ri, v) == 0);
163 } else if (ri->writefn) {
164 return (ri->writefn(env, ri, v) == 0);
165 } else {
afb2530f 166 raw_write(env, ri, v);
721fae12
PM		 167 }
168 return true;
169}
170
171bool write_cpustate_to_list(ARMCPU *cpu)
172{
173 /* Write the coprocessor state from cpu->env to the (index,value) list. */
174 int i;
175 bool ok = true;
176
177 for (i = 0; i < cpu->cpreg_array_len; i++) {
178 uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
179 const ARMCPRegInfo *ri;
180 uint64_t v;
60322b39 181 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
721fae12
PM		 182 if (!ri) {
183 ok = false;
184 continue;
185 }
186 if (ri->type & ARM_CP_NO_MIGRATE) {
187 continue;
188 }
189 if (!read_raw_cp_reg(&cpu->env, ri, &v)) {
190 ok = false;
191 continue;
192 }
193 cpu->cpreg_values[i] = v;
194 }
195 return ok;
196}
197
198bool write_list_to_cpustate(ARMCPU *cpu)
199{
200 int i;
201 bool ok = true;
202
203 for (i = 0; i < cpu->cpreg_array_len; i++) {
204 uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
205 uint64_t v = cpu->cpreg_values[i];
206 uint64_t readback;
207 const ARMCPRegInfo *ri;
208
60322b39 209 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
721fae12
PM		 210 if (!ri) {
211 ok = false;
212 continue;
213 }
214 if (ri->type & ARM_CP_NO_MIGRATE) {
215 continue;
216 }
217 /* Write value and confirm it reads back as written
218 * (to catch read-only registers and partially read-only
219 * registers where the incoming migration value doesn't match)
220 */
221 if (!write_raw_cp_reg(&cpu->env, ri, v) ||
222 !read_raw_cp_reg(&cpu->env, ri, &readback) ||
223 readback != v) {
224 ok = false;
225 }
226 }
227 return ok;
228}
229
230static void add_cpreg_to_list(gpointer key, gpointer opaque)
231{
232 ARMCPU *cpu = opaque;
233 uint64_t regidx;
234 const ARMCPRegInfo *ri;
235
236 regidx = *(uint32_t *)key;
60322b39 237 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
721fae12
PM		 238
239 if (!(ri->type & ARM_CP_NO_MIGRATE)) {
240 cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
241 /* The value array need not be initialized at this point */
242 cpu->cpreg_array_len++;
243 }
244}
245
246static void count_cpreg(gpointer key, gpointer opaque)
247{
248 ARMCPU *cpu = opaque;
249 uint64_t regidx;
250 const ARMCPRegInfo *ri;
251
252 regidx = *(uint32_t *)key;
60322b39 253 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
721fae12
PM		 254
255 if (!(ri->type & ARM_CP_NO_MIGRATE)) {
256 cpu->cpreg_array_len++;
257 }
258}
259
260static gint cpreg_key_compare(gconstpointer a, gconstpointer b)
261{
cbf239b7
AR		 262 uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a);
263 uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b);
721fae12 264
cbf239b7
AR		 265 if (aidx > bidx) {
266 return 1;
267 }
268 if (aidx < bidx) {
269 return -1;
270 }
271 return 0;
721fae12
PM		 272}
273
82a3a118
PM		 274static void cpreg_make_keylist(gpointer key, gpointer value, gpointer udata)
275{
276 GList **plist = udata;
277
278 *plist = g_list_prepend(*plist, key);
279}
280
721fae12
PM		 281void init_cpreg_list(ARMCPU *cpu)
282{
283 /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
284 * Note that we require cpreg_tuples[] to be sorted by key ID.
285 */
82a3a118 286 GList *keys = NULL;
721fae12
PM		 287 int arraylen;
288
82a3a118
PM		 289 g_hash_table_foreach(cpu->cp_regs, cpreg_make_keylist, &keys);
290
721fae12
PM		 291 keys = g_list_sort(keys, cpreg_key_compare);
292
293 cpu->cpreg_array_len = 0;
294
295 g_list_foreach(keys, count_cpreg, cpu);
296
297 arraylen = cpu->cpreg_array_len;
298 cpu->cpreg_indexes = g_new(uint64_t, arraylen);
299 cpu->cpreg_values = g_new(uint64_t, arraylen);
300 cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen);
301 cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen);
302 cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
303 cpu->cpreg_array_len = 0;
304
305 g_list_foreach(keys, add_cpreg_to_list, cpu);
306
307 assert(cpu->cpreg_array_len == arraylen);
308
309 g_list_free(keys);
310}
311
c983fe6c
PM		 312static int dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
313{
314 env->cp15.c3 = value;
315 tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */
316 return 0;
317}
318
08de207b
PM		 319static int fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
320{
321 if (env->cp15.c13_fcse != value) {
322 /* Unlike real hardware the qemu TLB uses virtual addresses,
323 * not modified virtual addresses, so this causes a TLB flush.
324 */
325 tlb_flush(env, 1);
326 env->cp15.c13_fcse = value;
327 }
328 return 0;
329}
330static int contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
331 uint64_t value)
332{
333 if (env->cp15.c13_context != value && !arm_feature(env, ARM_FEATURE_MPU)) {
334 /* For VMSA (when not using the LPAE long descriptor page table
335 * format) this register includes the ASID, so do a TLB flush.
336 * For PMSA it is purely a process ID and no action is needed.
337 */
338 tlb_flush(env, 1);
339 }
340 env->cp15.c13_context = value;
341 return 0;
342}
343
d929823f
PM		 344static int tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
345 uint64_t value)
346{
347 /* Invalidate all (TLBIALL) */
348 tlb_flush(env, 1);
349 return 0;
350}
351
352static int tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
353 uint64_t value)
354{
355 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
356 tlb_flush_page(env, value & TARGET_PAGE_MASK);
357 return 0;
358}
359
360static int tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
361 uint64_t value)
362{
363 /* Invalidate by ASID (TLBIASID) */
364 tlb_flush(env, value == 0);
365 return 0;
366}
367
368static int tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
369 uint64_t value)
370{
371 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
372 tlb_flush_page(env, value & TARGET_PAGE_MASK);
373 return 0;
374}
375
e9aa6c21
PM		 376static const ARMCPRegInfo cp_reginfo[] = {
377 /* DBGDIDR: just RAZ. In particular this means the "debug architecture
378 * version" bits will read as a reserved value, which should cause
379 * Linux to not try to use the debug hardware.
380 */
381 { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
382 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
c983fe6c
PM		 383 /* MMU Domain access control / MPU write buffer control */
384 { .name = "DACR", .cp = 15,
385 .crn = 3, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
386 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3),
d4e6df63 387 .resetvalue = 0, .writefn = dacr_write, .raw_writefn = raw_write, },
08de207b
PM		 388 { .name = "FCSEIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 0,
389 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
d4e6df63 390 .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
08de207b 391 { .name = "CONTEXTIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 1,
a4f0cec6 392 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_context),
d4e6df63 393 .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
4fdd17dd
PM		 394 /* ??? This covers not just the impdef TLB lockdown registers but also
395 * some v7VMSA registers relating to TEX remap, so it is overly broad.
396 */
397 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = CP_ANY,
398 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
d929823f
PM		 399 /* MMU TLB control. Note that the wildcarding means we cover not just
400 * the unified TLB ops but also the dside/iside/inner-shareable variants.
401 */
402 { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
d4e6df63
PM		 403 .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write,
404 .type = ARM_CP_NO_MIGRATE },
d929823f 405 { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY,
d4e6df63
PM		 406 .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write,
407 .type = ARM_CP_NO_MIGRATE },
d929823f 408 { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY,
d4e6df63
PM		 409 .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write,
410 .type = ARM_CP_NO_MIGRATE },
d929823f 411 { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY,
d4e6df63
PM		 412 .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write,
413 .type = ARM_CP_NO_MIGRATE },
c4804214
PM		 414 /* Cache maintenance ops; some of this space may be overridden later. */
415 { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
416 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
417 .type = ARM_CP_NOP | ARM_CP_OVERRIDE },
e9aa6c21
PM		 418 REGINFO_SENTINEL
419};
420
7d57f408
PM		 421static const ARMCPRegInfo not_v6_cp_reginfo[] = {
422 /* Not all pre-v6 cores implemented this WFI, so this is slightly
423 * over-broad.
424 */
425 { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
426 .access = PL1_W, .type = ARM_CP_WFI },
427 REGINFO_SENTINEL
428};
429
430static const ARMCPRegInfo not_v7_cp_reginfo[] = {
431 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
432 * is UNPREDICTABLE; we choose to NOP as most implementations do).
433 */
434 { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
435 .access = PL1_W, .type = ARM_CP_WFI },
34f90529
PM		 436 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
437 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
438 * OMAPCP will override this space.
439 */
440 { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0,
441 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data),
442 .resetvalue = 0 },
443 { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1,
444 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn),
445 .resetvalue = 0 },
776d4e5c
PM		 446 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
447 { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
d4e6df63
PM		 448 .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
449 .resetvalue = 0 },
7d57f408
PM		 450 REGINFO_SENTINEL
451};
452
2771db27
PM		 453static int cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
454{
455 if (env->cp15.c1_coproc != value) {
456 env->cp15.c1_coproc = value;
457 /* ??? Is this safe when called from within a TB? */
458 tb_flush(env);
459 }
460 return 0;
461}
462
7d57f408
PM		 463static const ARMCPRegInfo v6_cp_reginfo[] = {
464 /* prefetch by MVA in v6, NOP in v7 */
465 { .name = "MVA_prefetch",
466 .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
467 .access = PL1_W, .type = ARM_CP_NOP },
468 { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
469 .access = PL0_W, .type = ARM_CP_NOP },
091fd17c 470 { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
7d57f408 471 .access = PL0_W, .type = ARM_CP_NOP },
091fd17c 472 { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
7d57f408 473 .access = PL0_W, .type = ARM_CP_NOP },
06d76f31
PM		 474 { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
475 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_insn),
476 .resetvalue = 0, },
477 /* Watchpoint Fault Address Register : should actually only be present
478 * for 1136, 1176, 11MPCore.
479 */
480 { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
481 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
2771db27
PM		 482 { .name = "CPACR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2,
483 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_coproc),
484 .resetvalue = 0, .writefn = cpacr_write },
7d57f408
PM		 485 REGINFO_SENTINEL
486};
487
d4e6df63 488
200ac0ef
PM		 489static int pmreg_read(CPUARMState *env, const ARMCPRegInfo *ri,
490 uint64_t *value)
491{
492 /* Generic performance monitor register read function for where
493 * user access may be allowed by PMUSERENR.
494 */
495 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
496 return EXCP_UDEF;
497 }
498 *value = CPREG_FIELD32(env, ri);
499 return 0;
500}
501
502static int pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
503 uint64_t value)
504{
505 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
506 return EXCP_UDEF;
507 }
508 /* only the DP, X, D and E bits are writable */
509 env->cp15.c9_pmcr &= ~0x39;
510 env->cp15.c9_pmcr |= (value & 0x39);
511 return 0;
512}
513
514static int pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
515 uint64_t value)
516{
517 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
518 return EXCP_UDEF;
519 }
520 value &= (1 << 31);
521 env->cp15.c9_pmcnten |= value;
522 return 0;
523}
524
525static int pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
526 uint64_t value)
527{
528 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
529 return EXCP_UDEF;
530 }
531 value &= (1 << 31);
532 env->cp15.c9_pmcnten &= ~value;
533 return 0;
534}
535
536static int pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
537 uint64_t value)
538{
539 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
540 return EXCP_UDEF;
541 }
542 env->cp15.c9_pmovsr &= ~value;
543 return 0;
544}
545
546static int pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
547 uint64_t value)
548{
549 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
550 return EXCP_UDEF;
551 }
552 env->cp15.c9_pmxevtyper = value & 0xff;
553 return 0;
554}
555
556static int pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
557 uint64_t value)
558{
559 env->cp15.c9_pmuserenr = value & 1;
560 return 0;
561}
562
563static int pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
564 uint64_t value)
565{
566 /* We have no event counters so only the C bit can be changed */
567 value &= (1 << 31);
568 env->cp15.c9_pminten |= value;
569 return 0;
570}
571
572static int pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
573 uint64_t value)
574{
575 value &= (1 << 31);
576 env->cp15.c9_pminten &= ~value;
577 return 0;
578}
579
8641136c
NR		 580static int vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
581 uint64_t value)
582{
583 env->cp15.c12_vbar = value & ~0x1Ful;
584 return 0;
585}
586
776d4e5c
PM		 587static int ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri,
588 uint64_t *value)
589{
590 ARMCPU *cpu = arm_env_get_cpu(env);
591 *value = cpu->ccsidr[env->cp15.c0_cssel];
592 return 0;
593}
594
595static int csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
596 uint64_t value)
597{
598 env->cp15.c0_cssel = value & 0xf;
599 return 0;
600}
601
e9aa6c21
PM		 602static const ARMCPRegInfo v7_cp_reginfo[] = {
603 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
604 * debug components
605 */
606 { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
607 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
091fd17c 608 { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
e9aa6c21 609 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
7d57f408
PM		 610 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
611 { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
612 .access = PL1_W, .type = ARM_CP_NOP },
200ac0ef
PM		 613 /* Performance monitors are implementation defined in v7,
614 * but with an ARM recommended set of registers, which we
615 * follow (although we don't actually implement any counters)
616 *
617 * Performance registers fall into three categories:
618 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
619 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
620 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
621 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
622 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
623 */
624 { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
625 .access = PL0_RW, .resetvalue = 0,
626 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
d4e6df63
PM		 627 .readfn = pmreg_read, .writefn = pmcntenset_write,
628 .raw_readfn = raw_read, .raw_writefn = raw_write },
200ac0ef
PM		 629 { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
630 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
d4e6df63
PM		 631 .readfn = pmreg_read, .writefn = pmcntenclr_write,
632 .type = ARM_CP_NO_MIGRATE },
200ac0ef
PM		 633 { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
634 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
d4e6df63
PM		 635 .readfn = pmreg_read, .writefn = pmovsr_write,
636 .raw_readfn = raw_read, .raw_writefn = raw_write },
200ac0ef
PM		 637 /* Unimplemented so WI. Strictly speaking write accesses in PL0 should
638 * respect PMUSERENR.
639 */
640 { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
641 .access = PL0_W, .type = ARM_CP_NOP },
642 /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
643 * We choose to RAZ/WI. XXX should respect PMUSERENR.
644 */
645 { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
646 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
647 /* Unimplemented, RAZ/WI. XXX PMUSERENR */
648 { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
649 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
650 { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
651 .access = PL0_RW,
652 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
d4e6df63
PM		 653 .readfn = pmreg_read, .writefn = pmxevtyper_write,
654 .raw_readfn = raw_read, .raw_writefn = raw_write },
200ac0ef
PM		 655 /* Unimplemented, RAZ/WI. XXX PMUSERENR */
656 { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
657 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
658 { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
659 .access = PL0_R | PL1_RW,
660 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
661 .resetvalue = 0,
d4e6df63 662 .writefn = pmuserenr_write, .raw_writefn = raw_write },
200ac0ef
PM		 663 { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
664 .access = PL1_RW,
665 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
666 .resetvalue = 0,
d4e6df63 667 .writefn = pmintenset_write, .raw_writefn = raw_write },
200ac0ef 668 { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
d4e6df63 669 .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
200ac0ef 670 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
d4e6df63 671 .resetvalue = 0, .writefn = pmintenclr_write, },
8641136c
NR		 672 { .name = "VBAR", .cp = 15, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
673 .access = PL1_RW, .writefn = vbar_write,
674 .fieldoffset = offsetof(CPUARMState, cp15.c12_vbar),
675 .resetvalue = 0 },
2771db27
PM		 676 { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
677 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr),
678 .resetvalue = 0, },
776d4e5c 679 { .name = "CCSIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
d4e6df63 680 .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE },
776d4e5c
PM		 681 { .name = "CSSELR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
682 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c0_cssel),
683 .writefn = csselr_write, .resetvalue = 0 },
684 /* Auxiliary ID register: this actually has an IMPDEF value but for now
685 * just RAZ for all cores:
686 */
687 { .name = "AIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 7,
688 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
e9aa6c21
PM		 689 REGINFO_SENTINEL
690};
691
c326b979
PM		 692static int teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
693{
694 value &= 1;
695 env->teecr = value;
696 return 0;
697}
698
699static int teehbr_read(CPUARMState *env, const ARMCPRegInfo *ri,
700 uint64_t *value)
701{
702 /* This is a helper function because the user access rights
703 * depend on the value of the TEECR.
704 */
705 if (arm_current_pl(env) == 0 && (env->teecr & 1)) {
706 return EXCP_UDEF;
707 }
708 *value = env->teehbr;
709 return 0;
710}
711
712static int teehbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
713 uint64_t value)
714{
715 if (arm_current_pl(env) == 0 && (env->teecr & 1)) {
716 return EXCP_UDEF;
717 }
718 env->teehbr = value;
719 return 0;
720}
721
722static const ARMCPRegInfo t2ee_cp_reginfo[] = {
723 { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
724 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
725 .resetvalue = 0,
726 .writefn = teecr_write },
727 { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
728 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
d4e6df63 729 .resetvalue = 0, .raw_readfn = raw_read, .raw_writefn = raw_write,
c326b979
PM		 730 .readfn = teehbr_read, .writefn = teehbr_write },
731 REGINFO_SENTINEL
732};
733
4d31c596 734static const ARMCPRegInfo v6k_cp_reginfo[] = {
e4fe830b
PM		 735 { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64,
736 .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0,
737 .access = PL0_RW,
738 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el0), .resetvalue = 0 },
4d31c596
PM		 739 { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
740 .access = PL0_RW,
e4fe830b
PM		 741 .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidr_el0),
742 .resetfn = arm_cp_reset_ignore },
743 { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64,
744 .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0,
745 .access = PL0_R|PL1_W,
746 .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el0), .resetvalue = 0 },
4d31c596
PM		 747 { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
748 .access = PL0_R|PL1_W,
e4fe830b
PM		 749 .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidrro_el0),
750 .resetfn = arm_cp_reset_ignore },
751 { .name = "TPIDR_EL1", .state = ARM_CP_STATE_BOTH,
752 .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0,
4d31c596 753 .access = PL1_RW,
e4fe830b 754 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el1), .resetvalue = 0 },
4d31c596
PM		 755 REGINFO_SENTINEL
756};
757
55d284af
PM		 758#ifndef CONFIG_USER_ONLY
759
760static uint64_t gt_get_countervalue(CPUARMState *env)
761{
bc72ad67 762 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE;
55d284af
PM		 763}
764
765static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
766{
767 ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
768
769 if (gt->ctl & 1) {
770 /* Timer enabled: calculate and set current ISTATUS, irq, and
771 * reset timer to when ISTATUS next has to change
772 */
773 uint64_t count = gt_get_countervalue(&cpu->env);
774 /* Note that this must be unsigned 64 bit arithmetic: */
775 int istatus = count >= gt->cval;
776 uint64_t nexttick;
777
778 gt->ctl = deposit32(gt->ctl, 2, 1, istatus);
779 qemu_set_irq(cpu->gt_timer_outputs[timeridx],
780 (istatus && !(gt->ctl & 2)));
781 if (istatus) {
782 /* Next transition is when count rolls back over to zero */
783 nexttick = UINT64_MAX;
784 } else {
785 /* Next transition is when we hit cval */
786 nexttick = gt->cval;
787 }
788 /* Note that the desired next expiry time might be beyond the
789 * signed-64-bit range of a QEMUTimer -- in this case we just
790 * set the timer for as far in the future as possible. When the
791 * timer expires we will reset the timer for any remaining period.
792 */
793 if (nexttick > INT64_MAX / GTIMER_SCALE) {
794 nexttick = INT64_MAX / GTIMER_SCALE;
795 }
bc72ad67 796 timer_mod(cpu->gt_timer[timeridx], nexttick);
55d284af
PM		 797 } else {
798 /* Timer disabled: ISTATUS and timer output always clear */
799 gt->ctl &= ~4;
800 qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0);
bc72ad67 801 timer_del(cpu->gt_timer[timeridx]);
55d284af
PM		 802 }
803}
804
805static int gt_cntfrq_read(CPUARMState *env, const ARMCPRegInfo *ri,
806 uint64_t *value)
807{
808 /* Not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero */
809 if (arm_current_pl(env) == 0 && !extract32(env->cp15.c14_cntkctl, 0, 2)) {
810 return EXCP_UDEF;
811 }
812 *value = env->cp15.c14_cntfrq;
813 return 0;
814}
815
816static void gt_cnt_reset(CPUARMState *env, const ARMCPRegInfo *ri)
817{
818 ARMCPU *cpu = arm_env_get_cpu(env);
819 int timeridx = ri->opc1 & 1;
820
bc72ad67 821 timer_del(cpu->gt_timer[timeridx]);
55d284af
PM		 822}
823
824static int gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri,
825 uint64_t *value)
826{
827 int timeridx = ri->opc1 & 1;
828
829 if (arm_current_pl(env) == 0 &&
830 !extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
831 return EXCP_UDEF;
832 }
833 *value = gt_get_countervalue(env);
834 return 0;
835}
836
837static int gt_cval_read(CPUARMState *env, const ARMCPRegInfo *ri,
838 uint64_t *value)
839{
840 int timeridx = ri->opc1 & 1;
841
842 if (arm_current_pl(env) == 0 &&
843 !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
844 return EXCP_UDEF;
845 }
846 *value = env->cp15.c14_timer[timeridx].cval;
847 return 0;
848}
849
850static int gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
851 uint64_t value)
852{
853 int timeridx = ri->opc1 & 1;
854
855 env->cp15.c14_timer[timeridx].cval = value;
856 gt_recalc_timer(arm_env_get_cpu(env), timeridx);
857 return 0;
858}
859static int gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri,
860 uint64_t *value)
861{
862 int timeridx = ri->crm & 1;
863
864 if (arm_current_pl(env) == 0 &&
865 !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
866 return EXCP_UDEF;
867 }
868 *value = (uint32_t)(env->cp15.c14_timer[timeridx].cval -
869 gt_get_countervalue(env));
870 return 0;
871}
872
873static int gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
874 uint64_t value)
875{
876 int timeridx = ri->crm & 1;
877
878 env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) +
879 + sextract64(value, 0, 32);
880 gt_recalc_timer(arm_env_get_cpu(env), timeridx);
881 return 0;
882}
883
884static int gt_ctl_read(CPUARMState *env, const ARMCPRegInfo *ri,
885 uint64_t *value)
886{
887 int timeridx = ri->crm & 1;
888
889 if (arm_current_pl(env) == 0 &&
890 !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
891 return EXCP_UDEF;
892 }
893 *value = env->cp15.c14_timer[timeridx].ctl;
894 return 0;
895}
896
897static int gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
898 uint64_t value)
899{
900 ARMCPU *cpu = arm_env_get_cpu(env);
901 int timeridx = ri->crm & 1;
902 uint32_t oldval = env->cp15.c14_timer[timeridx].ctl;
903
904 env->cp15.c14_timer[timeridx].ctl = value & 3;
905 if ((oldval ^ value) & 1) {
906 /* Enable toggled */
907 gt_recalc_timer(cpu, timeridx);
908 } else if ((oldval & value) & 2) {
909 /* IMASK toggled: don't need to recalculate,
910 * just set the interrupt line based on ISTATUS
911 */
912 qemu_set_irq(cpu->gt_timer_outputs[timeridx],
913 (oldval & 4) && (value & 2));
914 }
915 return 0;
916}
917
918void arm_gt_ptimer_cb(void *opaque)
919{
920 ARMCPU *cpu = opaque;
921
922 gt_recalc_timer(cpu, GTIMER_PHYS);
923}
924
925void arm_gt_vtimer_cb(void *opaque)
926{
927 ARMCPU *cpu = opaque;
928
929 gt_recalc_timer(cpu, GTIMER_VIRT);
930}
931
932static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
933 /* Note that CNTFRQ is purely reads-as-written for the benefit
934 * of software; writing it doesn't actually change the timer frequency.
935 * Our reset value matches the fixed frequency we implement the timer at.
936 */
937 { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0,
938 .access = PL1_RW | PL0_R,
939 .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq),
940 .resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE,
941 .readfn = gt_cntfrq_read, .raw_readfn = raw_read,
942 },
943 /* overall control: mostly access permissions */
944 { .name = "CNTKCTL", .cp = 15, .crn = 14, .crm = 1, .opc1 = 0, .opc2 = 0,
945 .access = PL1_RW,
946 .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl),
947 .resetvalue = 0,
948 },
949 /* per-timer control */
950 { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
951 .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
952 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
953 .resetvalue = 0,
954 .readfn = gt_ctl_read, .writefn = gt_ctl_write,
955 .raw_readfn = raw_read, .raw_writefn = raw_write,
956 },
957 { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1,
958 .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
959 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
960 .resetvalue = 0,
961 .readfn = gt_ctl_read, .writefn = gt_ctl_write,
962 .raw_readfn = raw_read, .raw_writefn = raw_write,
963 },
964 /* TimerValue views: a 32 bit downcounting view of the underlying state */
965 { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
966 .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
967 .readfn = gt_tval_read, .writefn = gt_tval_write,
968 },
969 { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0,
970 .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
971 .readfn = gt_tval_read, .writefn = gt_tval_write,
972 },
973 /* The counter itself */
974 { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0,
975 .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO,
976 .readfn = gt_cnt_read, .resetfn = gt_cnt_reset,
977 },
978 { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1,
979 .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO,
980 .readfn = gt_cnt_read, .resetfn = gt_cnt_reset,
981 },
982 /* Comparison value, indicating when the timer goes off */
983 { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2,
984 .access = PL1_RW | PL0_R,
985 .type = ARM_CP_64BIT | ARM_CP_IO,
986 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
987 .resetvalue = 0,
988 .readfn = gt_cval_read, .writefn = gt_cval_write,
989 .raw_readfn = raw_read, .raw_writefn = raw_write,
990 },
991 { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3,
992 .access = PL1_RW | PL0_R,
993 .type = ARM_CP_64BIT | ARM_CP_IO,
994 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
995 .resetvalue = 0,
996 .readfn = gt_cval_read, .writefn = gt_cval_write,
997 .raw_readfn = raw_read, .raw_writefn = raw_write,
998 },
999 REGINFO_SENTINEL
1000};
1001
1002#else
1003/* In user-mode none of the generic timer registers are accessible,
bc72ad67 1004 * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs,
55d284af
PM		 1005 * so instead just don't register any of them.
1006 */
6cc7a3ae 1007static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
6cc7a3ae
PM		 1008 REGINFO_SENTINEL
1009};
1010
55d284af
PM		 1011#endif
1012
4a501606
PM		 1013static int par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1014{
891a2fe7
PM		 1015 if (arm_feature(env, ARM_FEATURE_LPAE)) {
1016 env->cp15.c7_par = value;
1017 } else if (arm_feature(env, ARM_FEATURE_V7)) {
4a501606
PM		 1018 env->cp15.c7_par = value & 0xfffff6ff;
1019 } else {
1020 env->cp15.c7_par = value & 0xfffff1ff;
1021 }
1022 return 0;
1023}
1024
1025#ifndef CONFIG_USER_ONLY
1026/* get_phys_addr() isn't present for user-mode-only targets */
702a9357
PM		 1027
1028/* Return true if extended addresses are enabled, ie this is an
1029 * LPAE implementation and we are using the long-descriptor translation
1030 * table format because the TTBCR EAE bit is set.
1031 */
1032static inline bool extended_addresses_enabled(CPUARMState *env)
1033{
1034 return arm_feature(env, ARM_FEATURE_LPAE)
78dbbbe4 1035 && (env->cp15.c2_control & (1U << 31));
702a9357
PM		 1036}
1037
4a501606
PM		 1038static int ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1039{
a8170e5e 1040 hwaddr phys_addr;
4a501606
PM		 1041 target_ulong page_size;
1042 int prot;
1043 int ret, is_user = ri->opc2 & 2;
1044 int access_type = ri->opc2 & 1;
1045
1046 if (ri->opc2 & 4) {
1047 /* Other states are only available with TrustZone */
1048 return EXCP_UDEF;
1049 }
1050 ret = get_phys_addr(env, value, access_type, is_user,
1051 &phys_addr, &prot, &page_size);
702a9357
PM		 1052 if (extended_addresses_enabled(env)) {
1053 /* ret is a DFSR/IFSR value for the long descriptor
1054 * translation table format, but with WnR always clear.
1055 * Convert it to a 64-bit PAR.
1056 */
1057 uint64_t par64 = (1 << 11); /* LPAE bit always set */
1058 if (ret == 0) {
1059 par64 |= phys_addr & ~0xfffULL;
1060 /* We don't set the ATTR or SH fields in the PAR. */
4a501606 1061 } else {
702a9357
PM		 1062 par64 |= 1; /* F */
1063 par64 |= (ret & 0x3f) << 1; /* FS */
1064 /* Note that S2WLK and FSTAGE are always zero, because we don't
1065 * implement virtualization and therefore there can't be a stage 2
1066 * fault.
1067 */
4a501606 1068 }
702a9357
PM		 1069 env->cp15.c7_par = par64;
1070 env->cp15.c7_par_hi = par64 >> 32;
4a501606 1071 } else {
702a9357
PM		 1072 /* ret is a DFSR/IFSR value for the short descriptor
1073 * translation table format (with WnR always clear).
1074 * Convert it to a 32-bit PAR.
1075 */
1076 if (ret == 0) {
1077 /* We do not set any attribute bits in the PAR */
1078 if (page_size == (1 << 24)
1079 && arm_feature(env, ARM_FEATURE_V7)) {
1080 env->cp15.c7_par = (phys_addr & 0xff000000) | 1 << 1;
1081 } else {
1082 env->cp15.c7_par = phys_addr & 0xfffff000;
1083 }
1084 } else {
1085 env->cp15.c7_par = ((ret & (10 << 1)) >> 5) |
1086 ((ret & (12 << 1)) >> 6) |
1087 ((ret & 0xf) << 1) | 1;
1088 }
1089 env->cp15.c7_par_hi = 0;
4a501606
PM		 1090 }
1091 return 0;
1092}
1093#endif
1094
1095static const ARMCPRegInfo vapa_cp_reginfo[] = {
1096 { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
1097 .access = PL1_RW, .resetvalue = 0,
1098 .fieldoffset = offsetof(CPUARMState, cp15.c7_par),
1099 .writefn = par_write },
1100#ifndef CONFIG_USER_ONLY
1101 { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
d4e6df63 1102 .access = PL1_W, .writefn = ats_write, .type = ARM_CP_NO_MIGRATE },
4a501606
PM		 1103#endif
1104 REGINFO_SENTINEL
1105};
1106
18032bec
PM		 1107/* Return basic MPU access permission bits. */
1108static uint32_t simple_mpu_ap_bits(uint32_t val)
1109{
1110 uint32_t ret;
1111 uint32_t mask;
1112 int i;
1113 ret = 0;
1114 mask = 3;
1115 for (i = 0; i < 16; i += 2) {
1116 ret |= (val >> i) & mask;
1117 mask <<= 2;
1118 }
1119 return ret;
1120}
1121
1122/* Pad basic MPU access permission bits to extended format. */
1123static uint32_t extended_mpu_ap_bits(uint32_t val)
1124{
1125 uint32_t ret;
1126 uint32_t mask;
1127 int i;
1128 ret = 0;
1129 mask = 3;
1130 for (i = 0; i < 16; i += 2) {
1131 ret |= (val & mask) << i;
1132 mask <<= 2;
1133 }
1134 return ret;
1135}
1136
1137static int pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
1138 uint64_t value)
1139{
1140 env->cp15.c5_data = extended_mpu_ap_bits(value);
1141 return 0;
1142}
1143
1144static int pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri,
1145 uint64_t *value)
1146{
1147 *value = simple_mpu_ap_bits(env->cp15.c5_data);
1148 return 0;
1149}
1150
1151static int pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
1152 uint64_t value)
1153{
1154 env->cp15.c5_insn = extended_mpu_ap_bits(value);
1155 return 0;
1156}
1157
1158static int pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri,
1159 uint64_t *value)
1160{
1161 *value = simple_mpu_ap_bits(env->cp15.c5_insn);
1162 return 0;
1163}
1164
06d76f31
PM		 1165static int arm946_prbs_read(CPUARMState *env, const ARMCPRegInfo *ri,
1166 uint64_t *value)
1167{
599d64f6 1168 if (ri->crm >= 8) {
06d76f31
PM		 1169 return EXCP_UDEF;
1170 }
1171 *value = env->cp15.c6_region[ri->crm];
1172 return 0;
1173}
1174
1175static int arm946_prbs_write(CPUARMState *env, const ARMCPRegInfo *ri,
1176 uint64_t value)
1177{
599d64f6 1178 if (ri->crm >= 8) {
06d76f31
PM		 1179 return EXCP_UDEF;
1180 }
1181 env->cp15.c6_region[ri->crm] = value;
1182 return 0;
1183}
1184
18032bec
PM		 1185static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
1186 { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
d4e6df63 1187 .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
18032bec
PM		 1188 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0,
1189 .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, },
1190 { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
d4e6df63 1191 .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
18032bec
PM		 1192 .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0,
1193 .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, },
1194 { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2,
1195 .access = PL1_RW,
1196 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
1197 { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3,
1198 .access = PL1_RW,
1199 .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, },
ecce5c3c
PM		 1200 { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
1201 .access = PL1_RW,
1202 .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, },
1203 { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
1204 .access = PL1_RW,
1205 .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
06d76f31
PM		 1206 /* Protection region base and size registers */
1207 { .name = "946_PRBS", .cp = 15, .crn = 6, .crm = CP_ANY, .opc1 = 0,
1208 .opc2 = CP_ANY, .access = PL1_RW,
1209 .readfn = arm946_prbs_read, .writefn = arm946_prbs_write, },
18032bec
PM		 1210 REGINFO_SENTINEL
1211};
1212
d4e6df63
PM		 1213static int vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
1214 uint64_t value)
ecce5c3c 1215{
2ebcebe2
PM		 1216 int maskshift = extract32(value, 0, 3);
1217
74f1c6dd 1218 if (arm_feature(env, ARM_FEATURE_LPAE) && (value & (1 << 31))) {
e42c4db3 1219 value &= ~((7 << 19) | (3 << 14) | (0xf << 3));
e42c4db3
PM		 1220 } else {
1221 value &= 7;
1222 }
1223 /* Note that we always calculate c2_mask and c2_base_mask, but
1224 * they are only used for short-descriptor tables (ie if EAE is 0);
1225 * for long-descriptor tables the TTBCR fields are used differently
1226 * and the c2_mask and c2_base_mask values are meaningless.
1227 */
ecce5c3c 1228 env->cp15.c2_control = value;
2ebcebe2
PM		 1229 env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> maskshift);
1230 env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> maskshift);
ecce5c3c
PM		 1231 return 0;
1232}
1233
d4e6df63
PM		 1234static int vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1235 uint64_t value)
1236{
1237 if (arm_feature(env, ARM_FEATURE_LPAE)) {
1238 /* With LPAE the TTBCR could result in a change of ASID
1239 * via the TTBCR.A1 bit, so do a TLB flush.
1240 */
1241 tlb_flush(env, 1);
1242 }
1243 return vmsa_ttbcr_raw_write(env, ri, value);
1244}
1245
ecce5c3c
PM		 1246static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1247{
1248 env->cp15.c2_base_mask = 0xffffc000u;
1249 env->cp15.c2_control = 0;
1250 env->cp15.c2_mask = 0;
1251}
1252
18032bec
PM		 1253static const ARMCPRegInfo vmsa_cp_reginfo[] = {
1254 { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
1255 .access = PL1_RW,
1256 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
1257 { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
1258 .access = PL1_RW,
1259 .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, },
ecce5c3c
PM		 1260 { .name = "TTBR0", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
1261 .access = PL1_RW,
1262 .fieldoffset = offsetof(CPUARMState, cp15.c2_base0), .resetvalue = 0, },
1263 { .name = "TTBR1", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
1264 .access = PL1_RW,
81a60ada 1265 .fieldoffset = offsetof(CPUARMState, cp15.c2_base1), .resetvalue = 0, },
ecce5c3c
PM		 1266 { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
1267 .access = PL1_RW, .writefn = vmsa_ttbcr_write,
d4e6df63 1268 .resetfn = vmsa_ttbcr_reset, .raw_writefn = vmsa_ttbcr_raw_write,
ecce5c3c 1269 .fieldoffset = offsetof(CPUARMState, cp15.c2_control) },
06d76f31
PM		 1270 { .name = "DFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
1271 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_data),
1272 .resetvalue = 0, },
18032bec
PM		 1273 REGINFO_SENTINEL
1274};
1275
1047b9d7
PM		 1276static int omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
1277 uint64_t value)
1278{
1279 env->cp15.c15_ticonfig = value & 0xe7;
1280 /* The OS_TYPE bit in this register changes the reported CPUID! */
1281 env->cp15.c0_cpuid = (value & (1 << 5)) ?
1282 ARM_CPUID_TI915T : ARM_CPUID_TI925T;
1283 return 0;
1284}
1285
1286static int omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,
1287 uint64_t value)
1288{
1289 env->cp15.c15_threadid = value & 0xffff;
1290 return 0;
1291}
1292
1293static int omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
1294 uint64_t value)
1295{
1296 /* Wait-for-interrupt (deprecated) */
c3affe56 1297 cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT);
1047b9d7
PM		 1298 return 0;
1299}
1300
c4804214
PM		 1301static int omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
1302 uint64_t value)
1303{
1304 /* On OMAP there are registers indicating the max/min index of dcache lines
1305 * containing a dirty line; cache flush operations have to reset these.
1306 */
1307 env->cp15.c15_i_max = 0x000;
1308 env->cp15.c15_i_min = 0xff0;
1309 return 0;
1310}
1311
18032bec
PM		 1312static const ARMCPRegInfo omap_cp_reginfo[] = {
1313 { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
1314 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,
1315 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
1047b9d7
PM		 1316 { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
1317 .access = PL1_RW, .type = ARM_CP_NOP },
1318 { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
1319 .access = PL1_RW,
1320 .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,
1321 .writefn = omap_ticonfig_write },
1322 { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,
1323 .access = PL1_RW,
1324 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },
1325 { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,
1326 .access = PL1_RW, .resetvalue = 0xff0,
1327 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },
1328 { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,
1329 .access = PL1_RW,
1330 .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,
1331 .writefn = omap_threadid_write },
1332 { .name = "TI925T_STATUS", .cp = 15, .crn = 15,
1333 .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
d4e6df63 1334 .type = ARM_CP_NO_MIGRATE,
1047b9d7
PM		 1335 .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
1336 /* TODO: Peripheral port remap register:
1337 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
1338 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
1339 * when MMU is off.
1340 */
c4804214 1341 { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
d4e6df63
PM		 1342 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
1343 .type = ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE,
c4804214 1344 .writefn = omap_cachemaint_write },
34f90529
PM		 1345 { .name = "C9", .cp = 15, .crn = 9,
1346 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
1347 .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
1047b9d7
PM		 1348 REGINFO_SENTINEL
1349};
1350
1351static int xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
1352 uint64_t value)
1353{
1354 value &= 0x3fff;
1355 if (env->cp15.c15_cpar != value) {
1356 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
1357 tb_flush(env);
1358 env->cp15.c15_cpar = value;
1359 }
1360 return 0;
1361}
1362
1363static const ARMCPRegInfo xscale_cp_reginfo[] = {
1364 { .name = "XSCALE_CPAR",
1365 .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
1366 .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
1367 .writefn = xscale_cpar_write, },
2771db27
PM		 1368 { .name = "XSCALE_AUXCR",
1369 .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
1370 .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
1371 .resetvalue = 0, },
1047b9d7
PM		 1372 REGINFO_SENTINEL
1373};
1374
1375static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
1376 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
1377 * implementation of this implementation-defined space.
1378 * Ideally this should eventually disappear in favour of actually
1379 * implementing the correct behaviour for all cores.
1380 */
1381 { .name = "C15_IMPDEF", .cp = 15, .crn = 15,
1382 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
3671cd87
PC		 1383 .access = PL1_RW,
1384 .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE | ARM_CP_OVERRIDE,
d4e6df63 1385 .resetvalue = 0 },
18032bec
PM		 1386 REGINFO_SENTINEL
1387};
1388
c4804214
PM		 1389static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
1390 /* Cache status: RAZ because we have no cache so it's always clean */
1391 { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
d4e6df63
PM		 1392 .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1393 .resetvalue = 0 },
c4804214
PM		 1394 REGINFO_SENTINEL
1395};
1396
1397static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
1398 /* We never have a a block transfer operation in progress */
1399 { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
d4e6df63
PM		 1400 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1401 .resetvalue = 0 },
30b05bba
PM		 1402 /* The cache ops themselves: these all NOP for QEMU */
1403 { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
1404 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1405 { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
1406 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1407 { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
1408 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1409 { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
1410 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1411 { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
1412 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1413 { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
1414 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
c4804214
PM		 1415 REGINFO_SENTINEL
1416};
1417
1418static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
1419 /* The cache test-and-clean instructions always return (1 << 30)
1420 * to indicate that there are no dirty cache lines.
1421 */
1422 { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
d4e6df63
PM		 1423 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1424 .resetvalue = (1 << 30) },
c4804214 1425 { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
d4e6df63
PM		 1426 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1427 .resetvalue = (1 << 30) },
c4804214
PM		 1428 REGINFO_SENTINEL
1429};
1430
34f90529
PM		 1431static const ARMCPRegInfo strongarm_cp_reginfo[] = {
1432 /* Ignore ReadBuffer accesses */
1433 { .name = "C9_READBUFFER", .cp = 15, .crn = 9,
1434 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
d4e6df63
PM		 1435 .access = PL1_RW, .resetvalue = 0,
1436 .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE },
34f90529
PM		 1437 REGINFO_SENTINEL
1438};
1439
81bdde9d
PM		 1440static int mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri,
1441 uint64_t *value)
1442{
55e5c285
AF		 1443 CPUState *cs = CPU(arm_env_get_cpu(env));
1444 uint32_t mpidr = cs->cpu_index;
81bdde9d
PM		 1445 /* We don't support setting cluster ID ([8..11])
1446 * so these bits always RAZ.
1447 */
1448 if (arm_feature(env, ARM_FEATURE_V7MP)) {
78dbbbe4 1449 mpidr |= (1U << 31);
81bdde9d
PM		 1450 /* Cores which are uniprocessor (non-coherent)
1451 * but still implement the MP extensions set
1452 * bit 30. (For instance, A9UP.) However we do
1453 * not currently model any of those cores.
1454 */
1455 }
1456 *value = mpidr;
1457 return 0;
1458}
1459
1460static const ARMCPRegInfo mpidr_cp_reginfo[] = {
1461 { .name = "MPIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
d4e6df63 1462 .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_MIGRATE },
81bdde9d
PM		 1463 REGINFO_SENTINEL
1464};
1465
891a2fe7
PM		 1466static int par64_read(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value)
1467{
1468 *value = ((uint64_t)env->cp15.c7_par_hi << 32) | env->cp15.c7_par;
1469 return 0;
1470}
1471
1472static int par64_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1473{
1474 env->cp15.c7_par_hi = value >> 32;
1475 env->cp15.c7_par = value;
1476 return 0;
1477}
1478
1479static void par64_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1480{
1481 env->cp15.c7_par_hi = 0;
1482 env->cp15.c7_par = 0;
1483}
1484
1485static int ttbr064_read(CPUARMState *env, const ARMCPRegInfo *ri,
1486 uint64_t *value)
1487{
1488 *value = ((uint64_t)env->cp15.c2_base0_hi << 32) | env->cp15.c2_base0;
1489 return 0;
1490}
1491
d4e6df63
PM		 1492static int ttbr064_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
1493 uint64_t value)
891a2fe7
PM		 1494{
1495 env->cp15.c2_base0_hi = value >> 32;
1496 env->cp15.c2_base0 = value;
d4e6df63
PM		 1497 return 0;
1498}
1499
1500static int ttbr064_write(CPUARMState *env, const ARMCPRegInfo *ri,
1501 uint64_t value)
1502{
891a2fe7
PM		 1503 /* Writes to the 64 bit format TTBRs may change the ASID */
1504 tlb_flush(env, 1);
d4e6df63 1505 return ttbr064_raw_write(env, ri, value);
891a2fe7
PM		 1506}
1507
1508static void ttbr064_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1509{
1510 env->cp15.c2_base0_hi = 0;
1511 env->cp15.c2_base0 = 0;
1512}
1513
1514static int ttbr164_read(CPUARMState *env, const ARMCPRegInfo *ri,
1515 uint64_t *value)
1516{
1517 *value = ((uint64_t)env->cp15.c2_base1_hi << 32) | env->cp15.c2_base1;
1518 return 0;
1519}
1520
1521static int ttbr164_write(CPUARMState *env, const ARMCPRegInfo *ri,
1522 uint64_t value)
1523{
1524 env->cp15.c2_base1_hi = value >> 32;
1525 env->cp15.c2_base1 = value;
1526 return 0;
1527}
1528
1529static void ttbr164_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1530{
1531 env->cp15.c2_base1_hi = 0;
1532 env->cp15.c2_base1 = 0;
1533}
1534
7ac681cf 1535static const ARMCPRegInfo lpae_cp_reginfo[] = {
b90372ad 1536 /* NOP AMAIR0/1: the override is because these clash with the rather
7ac681cf
PM		 1537 * broadly specified TLB_LOCKDOWN entry in the generic cp_reginfo.
1538 */
1539 { .name = "AMAIR0", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
1540 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
1541 .resetvalue = 0 },
1542 { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
1543 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
1544 .resetvalue = 0 },
f9fc619a
PM		 1545 /* 64 bit access versions of the (dummy) debug registers */
1546 { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
1547 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
1548 { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
1549 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
891a2fe7
PM		 1550 { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0,
1551 .access = PL1_RW, .type = ARM_CP_64BIT,
1552 .readfn = par64_read, .writefn = par64_write, .resetfn = par64_reset },
1553 { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0,
1554 .access = PL1_RW, .type = ARM_CP_64BIT, .readfn = ttbr064_read,
d4e6df63
PM		 1555 .writefn = ttbr064_write, .raw_writefn = ttbr064_raw_write,
1556 .resetfn = ttbr064_reset },
891a2fe7
PM		 1557 { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
1558 .access = PL1_RW, .type = ARM_CP_64BIT, .readfn = ttbr164_read,
1559 .writefn = ttbr164_write, .resetfn = ttbr164_reset },
7ac681cf
PM		 1560 REGINFO_SENTINEL
1561};
1562
b0d2b7d0
PM		 1563static int aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri,
1564 uint64_t *value)
1565{
1566 *value = vfp_get_fpcr(env);
1567 return 0;
1568}
1569
1570static int aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1571 uint64_t value)
1572{
1573 vfp_set_fpcr(env, value);
1574 return 0;
1575}
1576
1577static int aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri,
1578 uint64_t *value)
1579{
1580 *value = vfp_get_fpsr(env);
1581 return 0;
1582}
1583
1584static int aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1585 uint64_t value)
1586{
1587 vfp_set_fpsr(env, value);
1588 return 0;
1589}
1590
1591static const ARMCPRegInfo v8_cp_reginfo[] = {
1592 /* Minimal set of EL0-visible registers. This will need to be expanded
1593 * significantly for system emulation of AArch64 CPUs.
1594 */
1595 { .name = "NZCV", .state = ARM_CP_STATE_AA64,
1596 .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2,
1597 .access = PL0_RW, .type = ARM_CP_NZCV },
1598 { .name = "FPCR", .state = ARM_CP_STATE_AA64,
1599 .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4,
1600 .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write },
1601 { .name = "FPSR", .state = ARM_CP_STATE_AA64,
1602 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4,
1603 .access = PL0_RW, .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write },
1604 /* This claims a 32 byte cacheline size for icache and dcache, VIPT icache.
1605 * It will eventually need to have a CPU-specified reset value.
1606 */
1607 { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64,
1608 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0,
1609 .access = PL0_R, .type = ARM_CP_CONST,
1610 .resetvalue = 0x80030003 },
1611 /* Prohibit use of DC ZVA. OPTME: implement DC ZVA and allow its use.
1612 * For system mode the DZP bit here will need to be computed, not constant.
1613 */
1614 { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64,
1615 .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0,
1616 .access = PL0_R, .type = ARM_CP_CONST,
1617 .resetvalue = 0x10 },
1618 REGINFO_SENTINEL
1619};
1620
2771db27
PM		 1621static int sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1622{
1623 env->cp15.c1_sys = value;
1624 /* ??? Lots of these bits are not implemented. */
1625 /* This may enable/disable the MMU, so do a TLB flush. */
1626 tlb_flush(env, 1);
1627 return 0;
1628}
1629
2ceb98c0
PM		 1630void register_cp_regs_for_features(ARMCPU *cpu)
1631{
1632 /* Register all the coprocessor registers based on feature bits */
1633 CPUARMState *env = &cpu->env;
1634 if (arm_feature(env, ARM_FEATURE_M)) {
1635 /* M profile has no coprocessor registers */
1636 return;
1637 }
1638
e9aa6c21 1639 define_arm_cp_regs(cpu, cp_reginfo);
7d57f408 1640 if (arm_feature(env, ARM_FEATURE_V6)) {
8515a092
PM		 1641 /* The ID registers all have impdef reset values */
1642 ARMCPRegInfo v6_idregs[] = {
1643 { .name = "ID_PFR0", .cp = 15, .crn = 0, .crm = 1,
1644 .opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST,
1645 .resetvalue = cpu->id_pfr0 },
1646 { .name = "ID_PFR1", .cp = 15, .crn = 0, .crm = 1,
1647 .opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST,
1648 .resetvalue = cpu->id_pfr1 },
1649 { .name = "ID_DFR0", .cp = 15, .crn = 0, .crm = 1,
1650 .opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST,
1651 .resetvalue = cpu->id_dfr0 },
1652 { .name = "ID_AFR0", .cp = 15, .crn = 0, .crm = 1,
1653 .opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST,
1654 .resetvalue = cpu->id_afr0 },
1655 { .name = "ID_MMFR0", .cp = 15, .crn = 0, .crm = 1,
1656 .opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST,
1657 .resetvalue = cpu->id_mmfr0 },
1658 { .name = "ID_MMFR1", .cp = 15, .crn = 0, .crm = 1,
1659 .opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST,
1660 .resetvalue = cpu->id_mmfr1 },
1661 { .name = "ID_MMFR2", .cp = 15, .crn = 0, .crm = 1,
1662 .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
1663 .resetvalue = cpu->id_mmfr2 },
1664 { .name = "ID_MMFR3", .cp = 15, .crn = 0, .crm = 1,
1665 .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
1666 .resetvalue = cpu->id_mmfr3 },
1667 { .name = "ID_ISAR0", .cp = 15, .crn = 0, .crm = 2,
1668 .opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST,
1669 .resetvalue = cpu->id_isar0 },
1670 { .name = "ID_ISAR1", .cp = 15, .crn = 0, .crm = 2,
1671 .opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST,
1672 .resetvalue = cpu->id_isar1 },
1673 { .name = "ID_ISAR2", .cp = 15, .crn = 0, .crm = 2,
1674 .opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST,
1675 .resetvalue = cpu->id_isar2 },
1676 { .name = "ID_ISAR3", .cp = 15, .crn = 0, .crm = 2,
1677 .opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST,
1678 .resetvalue = cpu->id_isar3 },
1679 { .name = "ID_ISAR4", .cp = 15, .crn = 0, .crm = 2,
1680 .opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST,
1681 .resetvalue = cpu->id_isar4 },
1682 { .name = "ID_ISAR5", .cp = 15, .crn = 0, .crm = 2,
1683 .opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST,
1684 .resetvalue = cpu->id_isar5 },
1685 /* 6..7 are as yet unallocated and must RAZ */
1686 { .name = "ID_ISAR6", .cp = 15, .crn = 0, .crm = 2,
1687 .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
1688 .resetvalue = 0 },
1689 { .name = "ID_ISAR7", .cp = 15, .crn = 0, .crm = 2,
1690 .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
1691 .resetvalue = 0 },
1692 REGINFO_SENTINEL
1693 };
1694 define_arm_cp_regs(cpu, v6_idregs);
7d57f408
PM		 1695 define_arm_cp_regs(cpu, v6_cp_reginfo);
1696 } else {
1697 define_arm_cp_regs(cpu, not_v6_cp_reginfo);
1698 }
4d31c596
PM		 1699 if (arm_feature(env, ARM_FEATURE_V6K)) {
1700 define_arm_cp_regs(cpu, v6k_cp_reginfo);
1701 }
e9aa6c21 1702 if (arm_feature(env, ARM_FEATURE_V7)) {
200ac0ef
PM		 1703 /* v7 performance monitor control register: same implementor
1704 * field as main ID register, and we implement no event counters.
1705 */
1706 ARMCPRegInfo pmcr = {
1707 .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
1708 .access = PL0_RW, .resetvalue = cpu->midr & 0xff000000,
1709 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
d4e6df63
PM		 1710 .readfn = pmreg_read, .writefn = pmcr_write,
1711 .raw_readfn = raw_read, .raw_writefn = raw_write,
200ac0ef 1712 };
776d4e5c
PM		 1713 ARMCPRegInfo clidr = {
1714 .name = "CLIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
1715 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr
1716 };
200ac0ef 1717 define_one_arm_cp_reg(cpu, &pmcr);
776d4e5c 1718 define_one_arm_cp_reg(cpu, &clidr);
e9aa6c21 1719 define_arm_cp_regs(cpu, v7_cp_reginfo);
7d57f408
PM		 1720 } else {
1721 define_arm_cp_regs(cpu, not_v7_cp_reginfo);
e9aa6c21 1722 }
b0d2b7d0
PM		 1723 if (arm_feature(env, ARM_FEATURE_V8)) {
1724 define_arm_cp_regs(cpu, v8_cp_reginfo);
1725 }
18032bec
PM		 1726 if (arm_feature(env, ARM_FEATURE_MPU)) {
1727 /* These are the MPU registers prior to PMSAv6. Any new
1728 * PMSA core later than the ARM946 will require that we
1729 * implement the PMSAv6 or PMSAv7 registers, which are
1730 * completely different.
1731 */
1732 assert(!arm_feature(env, ARM_FEATURE_V6));
1733 define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
1734 } else {
1735 define_arm_cp_regs(cpu, vmsa_cp_reginfo);
1736 }
c326b979
PM		 1737 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
1738 define_arm_cp_regs(cpu, t2ee_cp_reginfo);
1739 }
6cc7a3ae
PM		 1740 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
1741 define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
1742 }
4a501606
PM		 1743 if (arm_feature(env, ARM_FEATURE_VAPA)) {
1744 define_arm_cp_regs(cpu, vapa_cp_reginfo);
1745 }
c4804214
PM		 1746 if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) {
1747 define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo);
1748 }
1749 if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) {
1750 define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo);
1751 }
1752 if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) {
1753 define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo);
1754 }
18032bec
PM		 1755 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
1756 define_arm_cp_regs(cpu, omap_cp_reginfo);
1757 }
34f90529
PM		 1758 if (arm_feature(env, ARM_FEATURE_STRONGARM)) {
1759 define_arm_cp_regs(cpu, strongarm_cp_reginfo);
1760 }
1047b9d7
PM		 1761 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1762 define_arm_cp_regs(cpu, xscale_cp_reginfo);
1763 }
1764 if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
1765 define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
1766 }
7ac681cf
PM		 1767 if (arm_feature(env, ARM_FEATURE_LPAE)) {
1768 define_arm_cp_regs(cpu, lpae_cp_reginfo);
1769 }
7884849c
PM		 1770 /* Slightly awkwardly, the OMAP and StrongARM cores need all of
1771 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
1772 * be read-only (ie write causes UNDEF exception).
1773 */
1774 {
1775 ARMCPRegInfo id_cp_reginfo[] = {
1776 /* Note that the MIDR isn't a simple constant register because
1777 * of the TI925 behaviour where writes to another register can
1778 * cause the MIDR value to change.
97ce8d61
PC		 1779 *
1780 * Unimplemented registers in the c15 0 0 0 space default to
1781 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
1782 * and friends override accordingly.
7884849c
PM		 1783 */
1784 { .name = "MIDR",
97ce8d61 1785 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY,
7884849c 1786 .access = PL1_R, .resetvalue = cpu->midr,
d4e6df63 1787 .writefn = arm_cp_write_ignore, .raw_writefn = raw_write,
97ce8d61
PC		 1788 .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
1789 .type = ARM_CP_OVERRIDE },
7884849c
PM		 1790 { .name = "CTR",
1791 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
1792 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
1793 { .name = "TCMTR",
1794 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2,
1795 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1796 { .name = "TLBTR",
1797 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3,
1798 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1799 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
1800 { .name = "DUMMY",
1801 .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY,
1802 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1803 { .name = "DUMMY",
1804 .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY,
1805 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1806 { .name = "DUMMY",
1807 .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY,
1808 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1809 { .name = "DUMMY",
1810 .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY,
1811 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1812 { .name = "DUMMY",
1813 .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
1814 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1815 REGINFO_SENTINEL
1816 };
1817 ARMCPRegInfo crn0_wi_reginfo = {
1818 .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
1819 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
1820 .type = ARM_CP_NOP | ARM_CP_OVERRIDE
1821 };
1822 if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
1823 arm_feature(env, ARM_FEATURE_STRONGARM)) {
1824 ARMCPRegInfo *r;
1825 /* Register the blanket "writes ignored" value first to cover the
a703eda1
PC		 1826 * whole space. Then update the specific ID registers to allow write
1827 * access, so that they ignore writes rather than causing them to
1828 * UNDEF.
7884849c
PM		 1829 */
1830 define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
1831 for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
1832 r->access = PL1_RW;
7884849c 1833 }
7884849c 1834 }
a703eda1 1835 define_arm_cp_regs(cpu, id_cp_reginfo);
7884849c
PM		 1836 }
1837
97ce8d61
PC		 1838 if (arm_feature(env, ARM_FEATURE_MPIDR)) {
1839 define_arm_cp_regs(cpu, mpidr_cp_reginfo);
1840 }
1841
2771db27
PM		 1842 if (arm_feature(env, ARM_FEATURE_AUXCR)) {
1843 ARMCPRegInfo auxcr = {
1844 .name = "AUXCR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1,
1845 .access = PL1_RW, .type = ARM_CP_CONST,
1846 .resetvalue = cpu->reset_auxcr
1847 };
1848 define_one_arm_cp_reg(cpu, &auxcr);
1849 }
1850
d8ba780b
PC		 1851 if (arm_feature(env, ARM_FEATURE_CBAR)) {
1852 ARMCPRegInfo cbar = {
1853 .name = "CBAR", .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
1854 .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
1855 .fieldoffset = offsetof(CPUARMState, cp15.c15_config_base_address)
1856 };
1857 define_one_arm_cp_reg(cpu, &cbar);
1858 }
1859
2771db27
PM		 1860 /* Generic registers whose values depend on the implementation */
1861 {
1862 ARMCPRegInfo sctlr = {
1863 .name = "SCTLR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
1864 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_sys),
d4e6df63
PM		 1865 .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,
1866 .raw_writefn = raw_write,
2771db27
PM		 1867 };
1868 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1869 /* Normally we would always end the TB on an SCTLR write, but Linux
1870 * arch/arm/mach-pxa/sleep.S expects two instructions following
1871 * an MMU enable to execute from cache. Imitate this behaviour.
1872 */
1873 sctlr.type |= ARM_CP_SUPPRESS_TB_END;
1874 }
1875 define_one_arm_cp_reg(cpu, &sctlr);
1876 }
2ceb98c0
PM		 1877}
1878
778c3a06 1879ARMCPU *cpu_arm_init(const char *cpu_model)
40f137e1 1880{
dec9c2d4 1881 ARMCPU *cpu;
5900d6b2 1882 ObjectClass *oc;
40f137e1 1883
5900d6b2
AF		 1884 oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
1885 if (!oc) {
aaed909a 1886 return NULL;
777dc784 1887 }
5900d6b2 1888 cpu = ARM_CPU(object_new(object_class_get_name(oc)));
14969266
AF		 1889
1890 /* TODO this should be set centrally, once possible */
1891 object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
777dc784 1892
14969266
AF		 1893 return cpu;
1894}
1895
1896void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
1897{
22169d41 1898 CPUState *cs = CPU(cpu);
14969266
AF		 1899 CPUARMState *env = &cpu->env;
1900
6a669427
PM		 1901 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
1902 gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
1903 aarch64_fpu_gdb_set_reg,
1904 34, "aarch64-fpu.xml", 0);
1905 } else if (arm_feature(env, ARM_FEATURE_NEON)) {
22169d41 1906 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
56aebc89
PB		 1907 51, "arm-neon.xml", 0);
1908 } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
22169d41 1909 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
56aebc89
PB		 1910 35, "arm-vfp3.xml", 0);
1911 } else if (arm_feature(env, ARM_FEATURE_VFP)) {
22169d41 1912 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
56aebc89
PB		 1913 19, "arm-vfp.xml", 0);
1914 }
40f137e1
PB		 1915}
1916
777dc784
PM		 1917/* Sort alphabetically by type name, except for "any". */
1918static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
5adb4839 1919{
777dc784
PM		 1920 ObjectClass *class_a = (ObjectClass *)a;
1921 ObjectClass *class_b = (ObjectClass *)b;
1922 const char *name_a, *name_b;
5adb4839 1923
777dc784
PM		 1924 name_a = object_class_get_name(class_a);
1925 name_b = object_class_get_name(class_b);
51492fd1 1926 if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) {
777dc784 1927 return 1;
51492fd1 1928 } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) {
777dc784
PM		 1929 return -1;
1930 } else {
1931 return strcmp(name_a, name_b);
5adb4839
PB		 1932 }
1933}
1934
777dc784 1935static void arm_cpu_list_entry(gpointer data, gpointer user_data)
40f137e1 1936{
777dc784 1937 ObjectClass *oc = data;
92a31361 1938 CPUListState *s = user_data;
51492fd1
AF		 1939 const char *typename;
1940 char *name;
3371d272 1941
51492fd1
AF		 1942 typename = object_class_get_name(oc);
1943 name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU));
777dc784 1944 (*s->cpu_fprintf)(s->file, " %s\n",
51492fd1
AF		 1945 name);
1946 g_free(name);
777dc784
PM		 1947}
1948
1949void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1950{
92a31361 1951 CPUListState s = {
777dc784
PM		 1952 .file = f,
1953 .cpu_fprintf = cpu_fprintf,
1954 };
1955 GSList *list;
1956
1957 list = object_class_get_list(TYPE_ARM_CPU, false);
1958 list = g_slist_sort(list, arm_cpu_list_compare);
1959 (*cpu_fprintf)(f, "Available CPUs:\n");
1960 g_slist_foreach(list, arm_cpu_list_entry, &s);
1961 g_slist_free(list);
a96c0514
PM		 1962#ifdef CONFIG_KVM
1963 /* The 'host' CPU type is dynamically registered only if KVM is
1964 * enabled, so we have to special-case it here:
1965 */
1966 (*cpu_fprintf)(f, " host (only available in KVM mode)\n");
1967#endif
40f137e1
PB		 1968}
1969
78027bb6
CR		 1970static void arm_cpu_add_definition(gpointer data, gpointer user_data)
1971{
1972 ObjectClass *oc = data;
1973 CpuDefinitionInfoList **cpu_list = user_data;
1974 CpuDefinitionInfoList *entry;
1975 CpuDefinitionInfo *info;
1976 const char *typename;
1977
1978 typename = object_class_get_name(oc);
1979 info = g_malloc0(sizeof(*info));
1980 info->name = g_strndup(typename,
1981 strlen(typename) - strlen("-" TYPE_ARM_CPU));
1982
1983 entry = g_malloc0(sizeof(*entry));
1984 entry->value = info;
1985 entry->next = *cpu_list;
1986 *cpu_list = entry;
1987}
1988
1989CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
1990{
1991 CpuDefinitionInfoList *cpu_list = NULL;
1992 GSList *list;
1993
1994 list = object_class_get_list(TYPE_ARM_CPU, false);
1995 g_slist_foreach(list, arm_cpu_add_definition, &cpu_list);
1996 g_slist_free(list);
1997
1998 return cpu_list;
1999}
2000
6e6efd61 2001static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
f5a0a5a5
PM		 2002 void *opaque, int state,
2003 int crm, int opc1, int opc2)
6e6efd61
PM		 2004{
2005 /* Private utility function for define_one_arm_cp_reg_with_opaque():
2006 * add a single reginfo struct to the hash table.
2007 */
2008 uint32_t *key = g_new(uint32_t, 1);
2009 ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
2010 int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
f5a0a5a5
PM		 2011 if (r->state == ARM_CP_STATE_BOTH && state == ARM_CP_STATE_AA32) {
2012 /* The AArch32 view of a shared register sees the lower 32 bits
2013 * of a 64 bit backing field. It is not migratable as the AArch64
2014 * view handles that. AArch64 also handles reset.
2015 * We assume it is a cp15 register.
2016 */
2017 r2->cp = 15;
2018 r2->type |= ARM_CP_NO_MIGRATE;
2019 r2->resetfn = arm_cp_reset_ignore;
2020#ifdef HOST_WORDS_BIGENDIAN
2021 if (r2->fieldoffset) {
2022 r2->fieldoffset += sizeof(uint32_t);
2023 }
2024#endif
2025 }
2026 if (state == ARM_CP_STATE_AA64) {
2027 /* To allow abbreviation of ARMCPRegInfo
2028 * definitions, we treat cp == 0 as equivalent to
2029 * the value for "standard guest-visible sysreg".
2030 */
2031 if (r->cp == 0) {
2032 r2->cp = CP_REG_ARM64_SYSREG_CP;
2033 }
2034 *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
2035 r2->opc0, opc1, opc2);
2036 } else {
2037 *key = ENCODE_CP_REG(r2->cp, is64, r2->crn, crm, opc1, opc2);
2038 }
6e6efd61
PM		 2039 if (opaque) {
2040 r2->opaque = opaque;
2041 }
2042 /* Make sure reginfo passed to helpers for wildcarded regs
2043 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
2044 */
2045 r2->crm = crm;
2046 r2->opc1 = opc1;
2047 r2->opc2 = opc2;
2048 /* By convention, for wildcarded registers only the first
2049 * entry is used for migration; the others are marked as
2050 * NO_MIGRATE so we don't try to transfer the register
2051 * multiple times. Special registers (ie NOP/WFI) are
2052 * never migratable.
2053 */
2054 if ((r->type & ARM_CP_SPECIAL) ||
2055 ((r->crm == CP_ANY) && crm != 0) ||
2056 ((r->opc1 == CP_ANY) && opc1 != 0) ||
2057 ((r->opc2 == CP_ANY) && opc2 != 0)) {
2058 r2->type |= ARM_CP_NO_MIGRATE;
2059 }
2060
2061 /* Overriding of an existing definition must be explicitly
2062 * requested.
2063 */
2064 if (!(r->type & ARM_CP_OVERRIDE)) {
2065 ARMCPRegInfo *oldreg;
2066 oldreg = g_hash_table_lookup(cpu->cp_regs, key);
2067 if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
2068 fprintf(stderr, "Register redefined: cp=%d %d bit "
2069 "crn=%d crm=%d opc1=%d opc2=%d, "
2070 "was %s, now %s\n", r2->cp, 32 + 32 * is64,
2071 r2->crn, r2->crm, r2->opc1, r2->opc2,
2072 oldreg->name, r2->name);
2073 g_assert_not_reached();
2074 }
2075 }
2076 g_hash_table_insert(cpu->cp_regs, key, r2);
2077}
2078
2079
4b6a83fb
PM		 2080void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
2081 const ARMCPRegInfo *r, void *opaque)
2082{
2083 /* Define implementations of coprocessor registers.
2084 * We store these in a hashtable because typically
2085 * there are less than 150 registers in a space which
2086 * is 16*16*16*8*8 = 262144 in size.
2087 * Wildcarding is supported for the crm, opc1 and opc2 fields.
2088 * If a register is defined twice then the second definition is
2089 * used, so this can be used to define some generic registers and
2090 * then override them with implementation specific variations.
2091 * At least one of the original and the second definition should
2092 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
2093 * against accidental use.
f5a0a5a5
PM		 2094 *
2095 * The state field defines whether the register is to be
2096 * visible in the AArch32 or AArch64 execution state. If the
2097 * state is set to ARM_CP_STATE_BOTH then we synthesise a
2098 * reginfo structure for the AArch32 view, which sees the lower
2099 * 32 bits of the 64 bit register.
2100 *
2101 * Only registers visible in AArch64 may set r->opc0; opc0 cannot
2102 * be wildcarded. AArch64 registers are always considered to be 64
2103 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
2104 * the register, if any.
4b6a83fb 2105 */
f5a0a5a5 2106 int crm, opc1, opc2, state;
4b6a83fb
PM		 2107 int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
2108 int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
2109 int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
2110 int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
2111 int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
2112 int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
2113 /* 64 bit registers have only CRm and Opc1 fields */
2114 assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
f5a0a5a5
PM		 2115 /* op0 only exists in the AArch64 encodings */
2116 assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0));
2117 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
2118 assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT));
2119 /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
2120 * encodes a minimum access level for the register. We roll this
2121 * runtime check into our general permission check code, so check
2122 * here that the reginfo's specified permissions are strict enough
2123 * to encompass the generic architectural permission check.
2124 */
2125 if (r->state != ARM_CP_STATE_AA32) {
2126 int mask = 0;
2127 switch (r->opc1) {
2128 case 0: case 1: case 2:
2129 /* min_EL EL1 */
2130 mask = PL1_RW;
2131 break;
2132 case 3:
2133 /* min_EL EL0 */
2134 mask = PL0_RW;
2135 break;
2136 case 4:
2137 /* min_EL EL2 */
2138 mask = PL2_RW;
2139 break;
2140 case 5:
2141 /* unallocated encoding, so not possible */
2142 assert(false);
2143 break;
2144 case 6:
2145 /* min_EL EL3 */
2146 mask = PL3_RW;
2147 break;
2148 case 7:
2149 /* min_EL EL1, secure mode only (we don't check the latter) */
2150 mask = PL1_RW;
2151 break;
2152 default:
2153 /* broken reginfo with out-of-range opc1 */
2154 assert(false);
2155 break;
2156 }
2157 /* assert our permissions are not too lax (stricter is fine) */
2158 assert((r->access & ~mask) == 0);
2159 }
2160
4b6a83fb
PM		 2161 /* Check that the register definition has enough info to handle
2162 * reads and writes if they are permitted.
2163 */
2164 if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
2165 if (r->access & PL3_R) {
2166 assert(r->fieldoffset || r->readfn);
2167 }
2168 if (r->access & PL3_W) {
2169 assert(r->fieldoffset || r->writefn);
2170 }
2171 }
2172 /* Bad type field probably means missing sentinel at end of reg list */
2173 assert(cptype_valid(r->type));
2174 for (crm = crmmin; crm <= crmmax; crm++) {
2175 for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
2176 for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
f5a0a5a5
PM		 2177 for (state = ARM_CP_STATE_AA32;
2178 state <= ARM_CP_STATE_AA64; state++) {
2179 if (r->state != state && r->state != ARM_CP_STATE_BOTH) {
2180 continue;
2181 }
2182 add_cpreg_to_hashtable(cpu, r, opaque, state,
2183 crm, opc1, opc2);
2184 }
4b6a83fb
PM		 2185 }
2186 }
2187 }
2188}
2189
2190void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
2191 const ARMCPRegInfo *regs, void *opaque)
2192{
2193 /* Define a whole list of registers */
2194 const ARMCPRegInfo *r;
2195 for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
2196 define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
2197 }
2198}
2199
60322b39 2200const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp)
4b6a83fb 2201{
60322b39 2202 return g_hash_table_lookup(cpregs, &encoded_cp);
4b6a83fb
PM		 2203}
2204
2205int arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
2206 uint64_t value)
2207{
2208 /* Helper coprocessor write function for write-ignore registers */
2209 return 0;
2210}
2211
2212int arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value)
2213{
2214 /* Helper coprocessor write function for read-as-zero registers */
2215 *value = 0;
2216 return 0;
2217}
2218
f5a0a5a5
PM		 2219void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque)
2220{
2221 /* Helper coprocessor reset function for do-nothing-on-reset registers */
2222}
2223
0ecb72a5 2224static int bad_mode_switch(CPUARMState *env, int mode)
37064a8b
PM		 2225{
2226 /* Return true if it is not valid for us to switch to
2227 * this CPU mode (ie all the UNPREDICTABLE cases in
2228 * the ARM ARM CPSRWriteByInstr pseudocode).
2229 */
2230 switch (mode) {
2231 case ARM_CPU_MODE_USR:
2232 case ARM_CPU_MODE_SYS:
2233 case ARM_CPU_MODE_SVC:
2234 case ARM_CPU_MODE_ABT:
2235 case ARM_CPU_MODE_UND:
2236 case ARM_CPU_MODE_IRQ:
2237 case ARM_CPU_MODE_FIQ:
2238 return 0;
2239 default:
2240 return 1;
2241 }
2242}
2243
2f4a40e5
AZ		 2244uint32_t cpsr_read(CPUARMState *env)
2245{
2246 int ZF;
6fbe23d5
PB		 2247 ZF = (env->ZF == 0);
2248 return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
2f4a40e5
AZ		 2249 (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
2250 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
2251 | ((env->condexec_bits & 0xfc) << 8)
2252 | (env->GE << 16);
2253}
2254
2255void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
2256{
2f4a40e5 2257 if (mask & CPSR_NZCV) {
6fbe23d5
PB		 2258 env->ZF = (~val) & CPSR_Z;
2259 env->NF = val;
2f4a40e5
AZ		 2260 env->CF = (val >> 29) & 1;
2261 env->VF = (val << 3) & 0x80000000;
2262 }
2263 if (mask & CPSR_Q)
2264 env->QF = ((val & CPSR_Q) != 0);
2265 if (mask & CPSR_T)
2266 env->thumb = ((val & CPSR_T) != 0);
2267 if (mask & CPSR_IT_0_1) {
2268 env->condexec_bits &= ~3;
2269 env->condexec_bits |= (val >> 25) & 3;
2270 }
2271 if (mask & CPSR_IT_2_7) {
2272 env->condexec_bits &= 3;
2273 env->condexec_bits |= (val >> 8) & 0xfc;
2274 }
2275 if (mask & CPSR_GE) {
2276 env->GE = (val >> 16) & 0xf;
2277 }
2278
2279 if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
37064a8b
PM		 2280 if (bad_mode_switch(env, val & CPSR_M)) {
2281 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
2282 * We choose to ignore the attempt and leave the CPSR M field
2283 * untouched.
2284 */
2285 mask &= ~CPSR_M;
2286 } else {
2287 switch_mode(env, val & CPSR_M);
2288 }
2f4a40e5
AZ		 2289 }
2290 mask &= ~CACHED_CPSR_BITS;
2291 env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
2292}
2293
b26eefb6
PB		 2294/* Sign/zero extend */
2295uint32_t HELPER(sxtb16)(uint32_t x)
2296{
2297 uint32_t res;
2298 res = (uint16_t)(int8_t)x;
2299 res |= (uint32_t)(int8_t)(x >> 16) << 16;
2300 return res;
2301}
2302
2303uint32_t HELPER(uxtb16)(uint32_t x)
2304{
2305 uint32_t res;
2306 res = (uint16_t)(uint8_t)x;
2307 res |= (uint32_t)(uint8_t)(x >> 16) << 16;
2308 return res;
2309}
2310
f51bbbfe
PB		 2311uint32_t HELPER(clz)(uint32_t x)
2312{
7bbcb0af 2313 return clz32(x);
f51bbbfe
PB		 2314}
2315
3670669c
PB		 2316int32_t HELPER(sdiv)(int32_t num, int32_t den)
2317{
2318 if (den == 0)
2319 return 0;
686eeb93
AJ		 2320 if (num == INT_MIN && den == -1)
2321 return INT_MIN;
3670669c
PB		 2322 return num / den;
2323}
2324
2325uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
2326{
2327 if (den == 0)
2328 return 0;
2329 return num / den;
2330}
2331
2332uint32_t HELPER(rbit)(uint32_t x)
2333{
2334 x = ((x & 0xff000000) >> 24)
2335 | ((x & 0x00ff0000) >> 8)
2336 | ((x & 0x0000ff00) << 8)
2337 | ((x & 0x000000ff) << 24);
2338 x = ((x & 0xf0f0f0f0) >> 4)
2339 | ((x & 0x0f0f0f0f) << 4);
2340 x = ((x & 0x88888888) >> 3)
2341 | ((x & 0x44444444) >> 1)
2342 | ((x & 0x22222222) << 1)
2343 | ((x & 0x11111111) << 3);
2344 return x;
2345}
2346
5fafdf24 2347#if defined(CONFIG_USER_ONLY)
b5ff1b31 2348
97a8ea5a 2349void arm_cpu_do_interrupt(CPUState *cs)
b5ff1b31 2350{
97a8ea5a
AF		 2351 ARMCPU *cpu = ARM_CPU(cs);
2352 CPUARMState *env = &cpu->env;
2353
b5ff1b31
FB		 2354 env->exception_index = -1;
2355}
2356
0ecb72a5 2357int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
97b348e7 2358 int mmu_idx)
b5ff1b31
FB		 2359{
2360 if (rw == 2) {
2361 env->exception_index = EXCP_PREFETCH_ABORT;
2362 env->cp15.c6_insn = address;
2363 } else {
2364 env->exception_index = EXCP_DATA_ABORT;
2365 env->cp15.c6_data = address;
2366 }
2367 return 1;
2368}
2369
9ee6e8bb 2370/* These should probably raise undefined insn exceptions. */
0ecb72a5 2371void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
9ee6e8bb
PB		 2372{
2373 cpu_abort(env, "v7m_mrs %d\n", reg);
2374}
2375
0ecb72a5 2376uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
9ee6e8bb
PB		 2377{
2378 cpu_abort(env, "v7m_mrs %d\n", reg);
2379 return 0;
2380}
2381
0ecb72a5 2382void switch_mode(CPUARMState *env, int mode)
b5ff1b31
FB		 2383{
2384 if (mode != ARM_CPU_MODE_USR)
2385 cpu_abort(env, "Tried to switch out of user mode\n");
2386}
2387
0ecb72a5 2388void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
9ee6e8bb
PB		 2389{
2390 cpu_abort(env, "banked r13 write\n");
2391}
2392
0ecb72a5 2393uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
9ee6e8bb
PB		 2394{
2395 cpu_abort(env, "banked r13 read\n");
2396 return 0;
2397}
2398
b5ff1b31
FB		 2399#else
2400
2401/* Map CPU modes onto saved register banks. */
494b00c7 2402int bank_number(int mode)
b5ff1b31
FB		 2403{
2404 switch (mode) {
2405 case ARM_CPU_MODE_USR:
2406 case ARM_CPU_MODE_SYS:
2407 return 0;
2408 case ARM_CPU_MODE_SVC:
2409 return 1;
2410 case ARM_CPU_MODE_ABT:
2411 return 2;
2412 case ARM_CPU_MODE_UND:
2413 return 3;
2414 case ARM_CPU_MODE_IRQ:
2415 return 4;
2416 case ARM_CPU_MODE_FIQ:
2417 return 5;
2418 }
f5206413 2419 hw_error("bank number requested for bad CPSR mode value 0x%x\n", mode);
b5ff1b31
FB		 2420}
2421
0ecb72a5 2422void switch_mode(CPUARMState *env, int mode)
b5ff1b31
FB		 2423{
2424 int old_mode;
2425 int i;
2426
2427 old_mode = env->uncached_cpsr & CPSR_M;
2428 if (mode == old_mode)
2429 return;
2430
2431 if (old_mode == ARM_CPU_MODE_FIQ) {
2432 memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
8637c67f 2433 memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
b5ff1b31
FB		 2434 } else if (mode == ARM_CPU_MODE_FIQ) {
2435 memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
8637c67f 2436 memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
b5ff1b31
FB		 2437 }
2438
f5206413 2439 i = bank_number(old_mode);
b5ff1b31
FB		 2440 env->banked_r13[i] = env->regs[13];
2441 env->banked_r14[i] = env->regs[14];
2442 env->banked_spsr[i] = env->spsr;
2443
f5206413 2444 i = bank_number(mode);
b5ff1b31
FB		 2445 env->regs[13] = env->banked_r13[i];
2446 env->regs[14] = env->banked_r14[i];
2447 env->spsr = env->banked_spsr[i];
2448}
2449
9ee6e8bb
PB		 2450static void v7m_push(CPUARMState *env, uint32_t val)
2451{
2452 env->regs[13] -= 4;
2453 stl_phys(env->regs[13], val);
2454}
2455
2456static uint32_t v7m_pop(CPUARMState *env)
2457{
2458 uint32_t val;
2459 val = ldl_phys(env->regs[13]);
2460 env->regs[13] += 4;
2461 return val;
2462}
2463
2464/* Switch to V7M main or process stack pointer. */
2465static void switch_v7m_sp(CPUARMState *env, int process)
2466{
2467 uint32_t tmp;
2468 if (env->v7m.current_sp != process) {
2469 tmp = env->v7m.other_sp;
2470 env->v7m.other_sp = env->regs[13];
2471 env->regs[13] = tmp;
2472 env->v7m.current_sp = process;
2473 }
2474}
2475
2476static void do_v7m_exception_exit(CPUARMState *env)
2477{
2478 uint32_t type;
2479 uint32_t xpsr;
2480
2481 type = env->regs[15];
2482 if (env->v7m.exception != 0)
983fe826 2483 armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
9ee6e8bb
PB		 2484
2485 /* Switch to the target stack. */
2486 switch_v7m_sp(env, (type & 4) != 0);
2487 /* Pop registers. */
2488 env->regs[0] = v7m_pop(env);
2489 env->regs[1] = v7m_pop(env);
2490 env->regs[2] = v7m_pop(env);
2491 env->regs[3] = v7m_pop(env);
2492 env->regs[12] = v7m_pop(env);
2493 env->regs[14] = v7m_pop(env);
2494 env->regs[15] = v7m_pop(env);
2495 xpsr = v7m_pop(env);
2496 xpsr_write(env, xpsr, 0xfffffdff);
2497 /* Undo stack alignment. */
2498 if (xpsr & 0x200)
2499 env->regs[13] |= 4;
2500 /* ??? The exception return type specifies Thread/Handler mode. However
2501 this is also implied by the xPSR value. Not sure what to do
2502 if there is a mismatch. */
2503 /* ??? Likewise for mismatches between the CONTROL register and the stack
2504 pointer. */
2505}
2506
3f1beaca
PM		 2507/* Exception names for debug logging; note that not all of these
2508 * precisely correspond to architectural exceptions.
2509 */
2510static const char * const excnames[] = {
2511 [EXCP_UDEF] = "Undefined Instruction",
2512 [EXCP_SWI] = "SVC",
2513 [EXCP_PREFETCH_ABORT] = "Prefetch Abort",
2514 [EXCP_DATA_ABORT] = "Data Abort",
2515 [EXCP_IRQ] = "IRQ",
2516 [EXCP_FIQ] = "FIQ",
2517 [EXCP_BKPT] = "Breakpoint",
2518 [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit",
2519 [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage",
2520 [EXCP_STREX] = "QEMU intercept of STREX",
2521};
2522
2523static inline void arm_log_exception(int idx)
2524{
2525 if (qemu_loglevel_mask(CPU_LOG_INT)) {
2526 const char *exc = NULL;
2527
2528 if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
2529 exc = excnames[idx];
2530 }
2531 if (!exc) {
2532 exc = "unknown";
2533 }
2534 qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc);
2535 }
2536}
2537
e6f010cc 2538void arm_v7m_cpu_do_interrupt(CPUState *cs)
9ee6e8bb 2539{
e6f010cc
AF		 2540 ARMCPU *cpu = ARM_CPU(cs);
2541 CPUARMState *env = &cpu->env;
9ee6e8bb
PB		 2542 uint32_t xpsr = xpsr_read(env);
2543 uint32_t lr;
2544 uint32_t addr;
2545
3f1beaca
PM		 2546 arm_log_exception(env->exception_index);
2547
9ee6e8bb
PB		 2548 lr = 0xfffffff1;
2549 if (env->v7m.current_sp)
2550 lr |= 4;
2551 if (env->v7m.exception == 0)
2552 lr |= 8;
2553
2554 /* For exceptions we just mark as pending on the NVIC, and let that
2555 handle it. */
2556 /* TODO: Need to escalate if the current priority is higher than the
2557 one we're raising. */
2558 switch (env->exception_index) {
2559 case EXCP_UDEF:
983fe826 2560 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
9ee6e8bb
PB		 2561 return;
2562 case EXCP_SWI:
314e2296 2563 /* The PC already points to the next instruction. */
983fe826 2564 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
9ee6e8bb
PB		 2565 return;
2566 case EXCP_PREFETCH_ABORT:
2567 case EXCP_DATA_ABORT:
983fe826 2568 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
9ee6e8bb
PB		 2569 return;
2570 case EXCP_BKPT:
2ad207d4
PB		 2571 if (semihosting_enabled) {
2572 int nr;
d31dd73e 2573 nr = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
2ad207d4
PB		 2574 if (nr == 0xab) {
2575 env->regs[15] += 2;
2576 env->regs[0] = do_arm_semihosting(env);
3f1beaca 2577 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
2ad207d4
PB		 2578 return;
2579 }
2580 }
983fe826 2581 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
9ee6e8bb
PB		 2582 return;
2583 case EXCP_IRQ:
983fe826 2584 env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
9ee6e8bb
PB		 2585 break;
2586 case EXCP_EXCEPTION_EXIT:
2587 do_v7m_exception_exit(env);
2588 return;
2589 default:
2590 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
2591 return; /* Never happens. Keep compiler happy. */
2592 }
2593
2594 /* Align stack pointer. */
2595 /* ??? Should only do this if Configuration Control Register
2596 STACKALIGN bit is set. */
2597 if (env->regs[13] & 4) {
ab19b0ec 2598 env->regs[13] -= 4;
9ee6e8bb
PB		 2599 xpsr |= 0x200;
2600 }
6c95676b 2601 /* Switch to the handler mode. */
9ee6e8bb
PB		 2602 v7m_push(env, xpsr);
2603 v7m_push(env, env->regs[15]);
2604 v7m_push(env, env->regs[14]);
2605 v7m_push(env, env->regs[12]);
2606 v7m_push(env, env->regs[3]);
2607 v7m_push(env, env->regs[2]);
2608 v7m_push(env, env->regs[1]);
2609 v7m_push(env, env->regs[0]);
2610 switch_v7m_sp(env, 0);
c98d174c
PM		 2611 /* Clear IT bits */
2612 env->condexec_bits = 0;
9ee6e8bb
PB		 2613 env->regs[14] = lr;
2614 addr = ldl_phys(env->v7m.vecbase + env->v7m.exception * 4);
2615 env->regs[15] = addr & 0xfffffffe;
2616 env->thumb = addr & 1;
2617}
2618
b5ff1b31 2619/* Handle a CPU exception. */
97a8ea5a 2620void arm_cpu_do_interrupt(CPUState *cs)
b5ff1b31 2621{
97a8ea5a
AF		 2622 ARMCPU *cpu = ARM_CPU(cs);
2623 CPUARMState *env = &cpu->env;
b5ff1b31
FB		 2624 uint32_t addr;
2625 uint32_t mask;
2626 int new_mode;
2627 uint32_t offset;
2628
e6f010cc
AF		 2629 assert(!IS_M(env));
2630
3f1beaca
PM		 2631 arm_log_exception(env->exception_index);
2632
b5ff1b31
FB		 2633 /* TODO: Vectored interrupt controller. */
2634 switch (env->exception_index) {
2635 case EXCP_UDEF:
2636 new_mode = ARM_CPU_MODE_UND;
2637 addr = 0x04;
2638 mask = CPSR_I;
2639 if (env->thumb)
2640 offset = 2;
2641 else
2642 offset = 4;
2643 break;
2644 case EXCP_SWI:
8e71621f
PB		 2645 if (semihosting_enabled) {
2646 /* Check for semihosting interrupt. */
2647 if (env->thumb) {
d31dd73e
BS		 2648 mask = arm_lduw_code(env, env->regs[15] - 2, env->bswap_code)
2649 & 0xff;
8e71621f 2650 } else {
d31dd73e 2651 mask = arm_ldl_code(env, env->regs[15] - 4, env->bswap_code)
d8fd2954 2652 & 0xffffff;
8e71621f
PB		 2653 }
2654 /* Only intercept calls from privileged modes, to provide some
2655 semblance of security. */
2656 if (((mask == 0x123456 && !env->thumb)
2657 || (mask == 0xab && env->thumb))
2658 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
2659 env->regs[0] = do_arm_semihosting(env);
3f1beaca 2660 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
8e71621f
PB		 2661 return;
2662 }
2663 }
b5ff1b31
FB		 2664 new_mode = ARM_CPU_MODE_SVC;
2665 addr = 0x08;
2666 mask = CPSR_I;
601d70b9 2667 /* The PC already points to the next instruction. */
b5ff1b31
FB		 2668 offset = 0;
2669 break;
06c949e6 2670 case EXCP_BKPT:
9ee6e8bb 2671 /* See if this is a semihosting syscall. */
2ad207d4 2672 if (env->thumb && semihosting_enabled) {
d31dd73e 2673 mask = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
9ee6e8bb
PB		 2674 if (mask == 0xab
2675 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
2676 env->regs[15] += 2;
2677 env->regs[0] = do_arm_semihosting(env);
3f1beaca 2678 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
9ee6e8bb
PB		 2679 return;
2680 }
2681 }
81c05daf 2682 env->cp15.c5_insn = 2;
9ee6e8bb
PB		 2683 /* Fall through to prefetch abort. */
2684 case EXCP_PREFETCH_ABORT:
3f1beaca
PM		 2685 qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n",
2686 env->cp15.c5_insn, env->cp15.c6_insn);
b5ff1b31
FB		 2687 new_mode = ARM_CPU_MODE_ABT;
2688 addr = 0x0c;
2689 mask = CPSR_A | CPSR_I;
2690 offset = 4;
2691 break;
2692 case EXCP_DATA_ABORT:
3f1beaca
PM		 2693 qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n",
2694 env->cp15.c5_data, env->cp15.c6_data);
b5ff1b31
FB		 2695 new_mode = ARM_CPU_MODE_ABT;
2696 addr = 0x10;
2697 mask = CPSR_A | CPSR_I;
2698 offset = 8;
2699 break;
2700 case EXCP_IRQ:
2701 new_mode = ARM_CPU_MODE_IRQ;
2702 addr = 0x18;
2703 /* Disable IRQ and imprecise data aborts. */
2704 mask = CPSR_A | CPSR_I;
2705 offset = 4;
2706 break;
2707 case EXCP_FIQ:
2708 new_mode = ARM_CPU_MODE_FIQ;
2709 addr = 0x1c;
2710 /* Disable FIQ, IRQ and imprecise data aborts. */
2711 mask = CPSR_A | CPSR_I | CPSR_F;
2712 offset = 4;
2713 break;
2714 default:
2715 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
2716 return; /* Never happens. Keep compiler happy. */
2717 }
2718 /* High vectors. */
2719 if (env->cp15.c1_sys & (1 << 13)) {
8641136c 2720 /* when enabled, base address cannot be remapped. */
b5ff1b31 2721 addr += 0xffff0000;
8641136c
NR		 2722 } else {
2723 /* ARM v7 architectures provide a vector base address register to remap
2724 * the interrupt vector table.
2725 * This register is only followed in non-monitor mode, and has a secure
2726 * and un-secure copy. Since the cpu is always in a un-secure operation
2727 * and is never in monitor mode this feature is always active.
2728 * Note: only bits 31:5 are valid.
2729 */
2730 addr += env->cp15.c12_vbar;
b5ff1b31
FB		 2731 }
2732 switch_mode (env, new_mode);
2733 env->spsr = cpsr_read(env);
9ee6e8bb
PB		 2734 /* Clear IT bits. */
2735 env->condexec_bits = 0;
30a8cac1 2736 /* Switch to the new mode, and to the correct instruction set. */
6d7e6326 2737 env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
b5ff1b31 2738 env->uncached_cpsr |= mask;
be5e7a76
DES		 2739 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
2740 * and we should just guard the thumb mode on V4 */
2741 if (arm_feature(env, ARM_FEATURE_V4T)) {
2742 env->thumb = (env->cp15.c1_sys & (1 << 30)) != 0;
2743 }
b5ff1b31
FB		 2744 env->regs[14] = env->regs[15] + offset;
2745 env->regs[15] = addr;
259186a7 2746 cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
b5ff1b31
FB		 2747}
2748
2749/* Check section/page access permissions.
2750 Returns the page protection flags, or zero if the access is not
2751 permitted. */
0ecb72a5 2752static inline int check_ap(CPUARMState *env, int ap, int domain_prot,
dd4ebc2e 2753 int access_type, int is_user)
b5ff1b31 2754{
9ee6e8bb
PB		 2755 int prot_ro;
2756
dd4ebc2e 2757 if (domain_prot == 3) {
b5ff1b31 2758 return PAGE_READ | PAGE_WRITE;
dd4ebc2e 2759 }
b5ff1b31 2760
9ee6e8bb
PB		 2761 if (access_type == 1)
2762 prot_ro = 0;
2763 else
2764 prot_ro = PAGE_READ;
2765
b5ff1b31
FB		 2766 switch (ap) {
2767 case 0:
78600320 2768 if (access_type == 1)
b5ff1b31
FB		 2769 return 0;
2770 switch ((env->cp15.c1_sys >> 8) & 3) {
2771 case 1:
2772 return is_user ? 0 : PAGE_READ;
2773 case 2:
2774 return PAGE_READ;
2775 default:
2776 return 0;
2777 }
2778 case 1:
2779 return is_user ? 0 : PAGE_READ | PAGE_WRITE;
2780 case 2:
2781 if (is_user)
9ee6e8bb 2782 return prot_ro;
b5ff1b31
FB		 2783 else
2784 return PAGE_READ | PAGE_WRITE;
2785 case 3:
2786 return PAGE_READ | PAGE_WRITE;
d4934d18 2787 case 4: /* Reserved. */
9ee6e8bb
PB		 2788 return 0;
2789 case 5:
2790 return is_user ? 0 : prot_ro;
2791 case 6:
2792 return prot_ro;
d4934d18 2793 case 7:
0ab06d83 2794 if (!arm_feature (env, ARM_FEATURE_V6K))
d4934d18
PB		 2795 return 0;
2796 return prot_ro;
b5ff1b31
FB		 2797 default:
2798 abort();
2799 }
2800}
2801
0ecb72a5 2802static uint32_t get_level1_table_address(CPUARMState *env, uint32_t address)
b2fa1797
PB		 2803{
2804 uint32_t table;
2805
2806 if (address & env->cp15.c2_mask)
2807 table = env->cp15.c2_base1 & 0xffffc000;
2808 else
2809 table = env->cp15.c2_base0 & env->cp15.c2_base_mask;
2810
2811 table |= (address >> 18) & 0x3ffc;
2812 return table;
2813}
2814
0ecb72a5 2815static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type,
a8170e5e 2816 int is_user, hwaddr *phys_ptr,
77a71dd1 2817 int *prot, target_ulong *page_size)
b5ff1b31
FB		 2818{
2819 int code;
2820 uint32_t table;
2821 uint32_t desc;
2822 int type;
2823 int ap;
2824 int domain;
dd4ebc2e 2825 int domain_prot;
a8170e5e 2826 hwaddr phys_addr;
b5ff1b31 2827
9ee6e8bb
PB		 2828 /* Pagetable walk. */
2829 /* Lookup l1 descriptor. */
b2fa1797 2830 table = get_level1_table_address(env, address);
9ee6e8bb
PB		 2831 desc = ldl_phys(table);
2832 type = (desc & 3);
dd4ebc2e
JCD		 2833 domain = (desc >> 5) & 0x0f;
2834 domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
9ee6e8bb 2835 if (type == 0) {
601d70b9 2836 /* Section translation fault. */
9ee6e8bb
PB		 2837 code = 5;
2838 goto do_fault;
2839 }
dd4ebc2e 2840 if (domain_prot == 0 || domain_prot == 2) {
9ee6e8bb
PB		 2841 if (type == 2)
2842 code = 9; /* Section domain fault. */
2843 else
2844 code = 11; /* Page domain fault. */
2845 goto do_fault;
2846 }
2847 if (type == 2) {
2848 /* 1Mb section. */
2849 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
2850 ap = (desc >> 10) & 3;
2851 code = 13;
d4c430a8 2852 *page_size = 1024 * 1024;
9ee6e8bb
PB		 2853 } else {
2854 /* Lookup l2 entry. */
2855 if (type == 1) {
2856 /* Coarse pagetable. */
2857 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
2858 } else {
2859 /* Fine pagetable. */
2860 table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
2861 }
2862 desc = ldl_phys(table);
2863 switch (desc & 3) {
2864 case 0: /* Page translation fault. */
2865 code = 7;
2866 goto do_fault;
2867 case 1: /* 64k page. */
2868 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
2869 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
d4c430a8 2870 *page_size = 0x10000;
ce819861 2871 break;
9ee6e8bb
PB		 2872 case 2: /* 4k page. */
2873 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
2874 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
d4c430a8 2875 *page_size = 0x1000;
ce819861 2876 break;
9ee6e8bb
PB		 2877 case 3: /* 1k page. */
2878 if (type == 1) {
2879 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
2880 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
2881 } else {
2882 /* Page translation fault. */
2883 code = 7;
2884 goto do_fault;
2885 }
2886 } else {
2887 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
2888 }
2889 ap = (desc >> 4) & 3;
d4c430a8 2890 *page_size = 0x400;
ce819861
PB		 2891 break;
2892 default:
9ee6e8bb
PB		 2893 /* Never happens, but compiler isn't smart enough to tell. */
2894 abort();
ce819861 2895 }
9ee6e8bb
PB		 2896 code = 15;
2897 }
dd4ebc2e 2898 *prot = check_ap(env, ap, domain_prot, access_type, is_user);
9ee6e8bb
PB		 2899 if (!*prot) {
2900 /* Access permission fault. */
2901 goto do_fault;
2902 }
3ad493fc 2903 *prot |= PAGE_EXEC;
9ee6e8bb
PB		 2904 *phys_ptr = phys_addr;
2905 return 0;
2906do_fault:
2907 return code | (domain << 4);
2908}
2909
0ecb72a5 2910static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type,
a8170e5e 2911 int is_user, hwaddr *phys_ptr,
77a71dd1 2912 int *prot, target_ulong *page_size)
9ee6e8bb
PB		 2913{
2914 int code;
2915 uint32_t table;
2916 uint32_t desc;
2917 uint32_t xn;
de9b05b8 2918 uint32_t pxn = 0;
9ee6e8bb
PB		 2919 int type;
2920 int ap;
de9b05b8 2921 int domain = 0;
dd4ebc2e 2922 int domain_prot;
a8170e5e 2923 hwaddr phys_addr;
9ee6e8bb
PB		 2924
2925 /* Pagetable walk. */
2926 /* Lookup l1 descriptor. */
b2fa1797 2927 table = get_level1_table_address(env, address);
9ee6e8bb
PB		 2928 desc = ldl_phys(table);
2929 type = (desc & 3);
de9b05b8
PM		 2930 if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
2931 /* Section translation fault, or attempt to use the encoding
2932 * which is Reserved on implementations without PXN.
2933 */
9ee6e8bb 2934 code = 5;
9ee6e8bb 2935 goto do_fault;
de9b05b8
PM		 2936 }
2937 if ((type == 1) || !(desc & (1 << 18))) {
2938 /* Page or Section. */
dd4ebc2e 2939 domain = (desc >> 5) & 0x0f;
9ee6e8bb 2940 }
dd4ebc2e
JCD		 2941 domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
2942 if (domain_prot == 0 || domain_prot == 2) {
de9b05b8 2943 if (type != 1) {
9ee6e8bb 2944 code = 9; /* Section domain fault. */
de9b05b8 2945 } else {
9ee6e8bb 2946 code = 11; /* Page domain fault. */
de9b05b8 2947 }
9ee6e8bb
PB		 2948 goto do_fault;
2949 }
de9b05b8 2950 if (type != 1) {
9ee6e8bb
PB		 2951 if (desc & (1 << 18)) {
2952 /* Supersection. */
2953 phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
d4c430a8 2954 *page_size = 0x1000000;
b5ff1b31 2955 } else {
9ee6e8bb
PB		 2956 /* Section. */
2957 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
d4c430a8 2958 *page_size = 0x100000;
b5ff1b31 2959 }
9ee6e8bb
PB		 2960 ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
2961 xn = desc & (1 << 4);
de9b05b8 2962 pxn = desc & 1;
9ee6e8bb
PB		 2963 code = 13;
2964 } else {
de9b05b8
PM		 2965 if (arm_feature(env, ARM_FEATURE_PXN)) {
2966 pxn = (desc >> 2) & 1;
2967 }
9ee6e8bb
PB		 2968 /* Lookup l2 entry. */
2969 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
2970 desc = ldl_phys(table);
2971 ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
2972 switch (desc & 3) {
2973 case 0: /* Page translation fault. */
2974 code = 7;
b5ff1b31 2975 goto do_fault;
9ee6e8bb
PB		 2976 case 1: /* 64k page. */
2977 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
2978 xn = desc & (1 << 15);
d4c430a8 2979 *page_size = 0x10000;
9ee6e8bb
PB		 2980 break;
2981 case 2: case 3: /* 4k page. */
2982 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
2983 xn = desc & 1;
d4c430a8 2984 *page_size = 0x1000;
9ee6e8bb
PB		 2985 break;
2986 default:
2987 /* Never happens, but compiler isn't smart enough to tell. */
2988 abort();
b5ff1b31 2989 }
9ee6e8bb
PB		 2990 code = 15;
2991 }
dd4ebc2e 2992 if (domain_prot == 3) {
c0034328
JR		 2993 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
2994 } else {
de9b05b8
PM		 2995 if (pxn && !is_user) {
2996 xn = 1;
2997 }
c0034328
JR		 2998 if (xn && access_type == 2)
2999 goto do_fault;
9ee6e8bb 3000
c0034328
JR		 3001 /* The simplified model uses AP[0] as an access control bit. */
3002 if ((env->cp15.c1_sys & (1 << 29)) && (ap & 1) == 0) {
3003 /* Access flag fault. */
3004 code = (code == 15) ? 6 : 3;
3005 goto do_fault;
3006 }
dd4ebc2e 3007 *prot = check_ap(env, ap, domain_prot, access_type, is_user);
c0034328
JR		 3008 if (!*prot) {
3009 /* Access permission fault. */
3010 goto do_fault;
3011 }
3012 if (!xn) {
3013 *prot |= PAGE_EXEC;
3014 }
3ad493fc 3015 }
9ee6e8bb 3016 *phys_ptr = phys_addr;
b5ff1b31
FB		 3017 return 0;
3018do_fault:
3019 return code | (domain << 4);
3020}
3021
3dde962f
PM		 3022/* Fault type for long-descriptor MMU fault reporting; this corresponds
3023 * to bits [5..2] in the STATUS field in long-format DFSR/IFSR.
3024 */
3025typedef enum {
3026 translation_fault = 1,
3027 access_fault = 2,
3028 permission_fault = 3,
3029} MMUFaultType;
3030
3031static int get_phys_addr_lpae(CPUARMState *env, uint32_t address,
3032 int access_type, int is_user,
a8170e5e 3033 hwaddr *phys_ptr, int *prot,
3dde962f
PM		 3034 target_ulong *page_size_ptr)
3035{
3036 /* Read an LPAE long-descriptor translation table. */
3037 MMUFaultType fault_type = translation_fault;
3038 uint32_t level = 1;
3039 uint32_t epd;
3040 uint32_t tsz;
3041 uint64_t ttbr;
3042 int ttbr_select;
3043 int n;
a8170e5e 3044 hwaddr descaddr;
3dde962f
PM		 3045 uint32_t tableattrs;
3046 target_ulong page_size;
3047 uint32_t attrs;
3048
3049 /* Determine whether this address is in the region controlled by
3050 * TTBR0 or TTBR1 (or if it is in neither region and should fault).
3051 * This is a Non-secure PL0/1 stage 1 translation, so controlled by
3052 * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
3053 */
3054 uint32_t t0sz = extract32(env->cp15.c2_control, 0, 3);
3055 uint32_t t1sz = extract32(env->cp15.c2_control, 16, 3);
3056 if (t0sz && !extract32(address, 32 - t0sz, t0sz)) {
3057 /* there is a ttbr0 region and we are in it (high bits all zero) */
3058 ttbr_select = 0;
3059 } else if (t1sz && !extract32(~address, 32 - t1sz, t1sz)) {
3060 /* there is a ttbr1 region and we are in it (high bits all one) */
3061 ttbr_select = 1;
3062 } else if (!t0sz) {
3063 /* ttbr0 region is "everything not in the ttbr1 region" */
3064 ttbr_select = 0;
3065 } else if (!t1sz) {
3066 /* ttbr1 region is "everything not in the ttbr0 region" */
3067 ttbr_select = 1;
3068 } else {
3069 /* in the gap between the two regions, this is a Translation fault */
3070 fault_type = translation_fault;
3071 goto do_fault;
3072 }
3073
3074 /* Note that QEMU ignores shareability and cacheability attributes,
3075 * so we don't need to do anything with the SH, ORGN, IRGN fields
3076 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
3077 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
3078 * implement any ASID-like capability so we can ignore it (instead
3079 * we will always flush the TLB any time the ASID is changed).
3080 */
3081 if (ttbr_select == 0) {
3082 ttbr = ((uint64_t)env->cp15.c2_base0_hi << 32) | env->cp15.c2_base0;
3083 epd = extract32(env->cp15.c2_control, 7, 1);
3084 tsz = t0sz;
3085 } else {
3086 ttbr = ((uint64_t)env->cp15.c2_base1_hi << 32) | env->cp15.c2_base1;
3087 epd = extract32(env->cp15.c2_control, 23, 1);
3088 tsz = t1sz;
3089 }
3090
3091 if (epd) {
3092 /* Translation table walk disabled => Translation fault on TLB miss */
3093 goto do_fault;
3094 }
3095
3096 /* If the region is small enough we will skip straight to a 2nd level
3097 * lookup. This affects the number of bits of the address used in
3098 * combination with the TTBR to find the first descriptor. ('n' here
3099 * matches the usage in the ARM ARM sB3.6.6, where bits [39..n] are
3100 * from the TTBR, [n-1..3] from the vaddr, and [2..0] always zero).
3101 */
3102 if (tsz > 1) {
3103 level = 2;
3104 n = 14 - tsz;
3105 } else {
3106 n = 5 - tsz;
3107 }
3108
3109 /* Clear the vaddr bits which aren't part of the within-region address,
3110 * so that we don't have to special case things when calculating the
3111 * first descriptor address.
3112 */
3113 address &= (0xffffffffU >> tsz);
3114
3115 /* Now we can extract the actual base address from the TTBR */
3116 descaddr = extract64(ttbr, 0, 40);
3117 descaddr &= ~((1ULL << n) - 1);
3118
3119 tableattrs = 0;
3120 for (;;) {
3121 uint64_t descriptor;
3122
3123 descaddr |= ((address >> (9 * (4 - level))) & 0xff8);
3124 descriptor = ldq_phys(descaddr);
3125 if (!(descriptor & 1) ||
3126 (!(descriptor & 2) && (level == 3))) {
3127 /* Invalid, or the Reserved level 3 encoding */
3128 goto do_fault;
3129 }
3130 descaddr = descriptor & 0xfffffff000ULL;
3131
3132 if ((descriptor & 2) && (level < 3)) {
3133 /* Table entry. The top five bits are attributes which may
3134 * propagate down through lower levels of the table (and
3135 * which are all arranged so that 0 means "no effect", so
3136 * we can gather them up by ORing in the bits at each level).
3137 */
3138 tableattrs |= extract64(descriptor, 59, 5);
3139 level++;
3140 continue;
3141 }
3142 /* Block entry at level 1 or 2, or page entry at level 3.
3143 * These are basically the same thing, although the number
3144 * of bits we pull in from the vaddr varies.
3145 */
3146 page_size = (1 << (39 - (9 * level)));
3147 descaddr |= (address & (page_size - 1));
3148 /* Extract attributes from the descriptor and merge with table attrs */
3149 attrs = extract64(descriptor, 2, 10)
3150 | (extract64(descriptor, 52, 12) << 10);
3151 attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */
3152 attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */
3153 /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
3154 * means "force PL1 access only", which means forcing AP[1] to 0.
3155 */
3156 if (extract32(tableattrs, 2, 1)) {
3157 attrs &= ~(1 << 4);
3158 }
3159 /* Since we're always in the Non-secure state, NSTable is ignored. */
3160 break;
3161 }
3162 /* Here descaddr is the final physical address, and attributes
3163 * are all in attrs.
3164 */
3165 fault_type = access_fault;
3166 if ((attrs & (1 << 8)) == 0) {
3167 /* Access flag */
3168 goto do_fault;
3169 }
3170 fault_type = permission_fault;
3171 if (is_user && !(attrs & (1 << 4))) {
3172 /* Unprivileged access not enabled */
3173 goto do_fault;
3174 }
3175 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
3176 if (attrs & (1 << 12) || (!is_user && (attrs & (1 << 11)))) {
3177 /* XN or PXN */
3178 if (access_type == 2) {
3179 goto do_fault;
3180 }
3181 *prot &= ~PAGE_EXEC;
3182 }
3183 if (attrs & (1 << 5)) {
3184 /* Write access forbidden */
3185 if (access_type == 1) {
3186 goto do_fault;
3187 }
3188 *prot &= ~PAGE_WRITE;
3189 }
3190
3191 *phys_ptr = descaddr;
3192 *page_size_ptr = page_size;
3193 return 0;
3194
3195do_fault:
3196 /* Long-descriptor format IFSR/DFSR value */
3197 return (1 << 9) | (fault_type << 2) | level;
3198}
3199
77a71dd1
PM		 3200static int get_phys_addr_mpu(CPUARMState *env, uint32_t address,
3201 int access_type, int is_user,
a8170e5e 3202 hwaddr *phys_ptr, int *prot)
9ee6e8bb
PB		 3203{
3204 int n;
3205 uint32_t mask;
3206 uint32_t base;
3207
3208 *phys_ptr = address;
3209 for (n = 7; n >= 0; n--) {
3210 base = env->cp15.c6_region[n];
3211 if ((base & 1) == 0)
3212 continue;
3213 mask = 1 << ((base >> 1) & 0x1f);
3214 /* Keep this shift separate from the above to avoid an
3215 (undefined) << 32. */
3216 mask = (mask << 1) - 1;
3217 if (((base ^ address) & ~mask) == 0)
3218 break;
3219 }
3220 if (n < 0)
3221 return 2;
3222
3223 if (access_type == 2) {
3224 mask = env->cp15.c5_insn;
3225 } else {
3226 mask = env->cp15.c5_data;
3227 }
3228 mask = (mask >> (n * 4)) & 0xf;
3229 switch (mask) {
3230 case 0:
3231 return 1;
3232 case 1:
3233 if (is_user)
3234 return 1;
3235 *prot = PAGE_READ | PAGE_WRITE;
3236 break;
3237 case 2:
3238 *prot = PAGE_READ;
3239 if (!is_user)
3240 *prot |= PAGE_WRITE;
3241 break;
3242 case 3:
3243 *prot = PAGE_READ | PAGE_WRITE;
3244 break;
3245 case 5:
3246 if (is_user)
3247 return 1;
3248 *prot = PAGE_READ;
3249 break;
3250 case 6:
3251 *prot = PAGE_READ;
3252 break;
3253 default:
3254 /* Bad permission. */
3255 return 1;
3256 }
3ad493fc 3257 *prot |= PAGE_EXEC;
9ee6e8bb
PB		 3258 return 0;
3259}
3260
702a9357
PM		 3261/* get_phys_addr - get the physical address for this virtual address
3262 *
3263 * Find the physical address corresponding to the given virtual address,
3264 * by doing a translation table walk on MMU based systems or using the
3265 * MPU state on MPU based systems.
3266 *
3267 * Returns 0 if the translation was successful. Otherwise, phys_ptr,
3268 * prot and page_size are not filled in, and the return value provides
3269 * information on why the translation aborted, in the format of a
3270 * DFSR/IFSR fault register, with the following caveats:
3271 * * we honour the short vs long DFSR format differences.
3272 * * the WnR bit is never set (the caller must do this).
3273 * * for MPU based systems we don't bother to return a full FSR format
3274 * value.
3275 *
3276 * @env: CPUARMState
3277 * @address: virtual address to get physical address for
3278 * @access_type: 0 for read, 1 for write, 2 for execute
3279 * @is_user: 0 for privileged access, 1 for user
3280 * @phys_ptr: set to the physical address corresponding to the virtual address
3281 * @prot: set to the permissions for the page containing phys_ptr
3282 * @page_size: set to the size of the page containing phys_ptr
3283 */
0ecb72a5 3284static inline int get_phys_addr(CPUARMState *env, uint32_t address,
9ee6e8bb 3285 int access_type, int is_user,
a8170e5e 3286 hwaddr *phys_ptr, int *prot,
d4c430a8 3287 target_ulong *page_size)
9ee6e8bb
PB		 3288{
3289 /* Fast Context Switch Extension. */
3290 if (address < 0x02000000)
3291 address += env->cp15.c13_fcse;
3292
3293 if ((env->cp15.c1_sys & 1) == 0) {
3294 /* MMU/MPU disabled. */
3295 *phys_ptr = address;
3ad493fc 3296 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
d4c430a8 3297 *page_size = TARGET_PAGE_SIZE;
9ee6e8bb
PB		 3298 return 0;
3299 } else if (arm_feature(env, ARM_FEATURE_MPU)) {
d4c430a8 3300 *page_size = TARGET_PAGE_SIZE;
9ee6e8bb
PB		 3301 return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr,
3302 prot);
3dde962f
PM		 3303 } else if (extended_addresses_enabled(env)) {
3304 return get_phys_addr_lpae(env, address, access_type, is_user, phys_ptr,
3305 prot, page_size);
9ee6e8bb
PB		 3306 } else if (env->cp15.c1_sys & (1 << 23)) {
3307 return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr,
d4c430a8 3308 prot, page_size);
9ee6e8bb
PB		 3309 } else {
3310 return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr,
d4c430a8 3311 prot, page_size);
9ee6e8bb
PB		 3312 }
3313}
3314
0ecb72a5 3315int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address,
97b348e7 3316 int access_type, int mmu_idx)
b5ff1b31 3317{
a8170e5e 3318 hwaddr phys_addr;
d4c430a8 3319 target_ulong page_size;
b5ff1b31 3320 int prot;
6ebbf390 3321 int ret, is_user;
b5ff1b31 3322
6ebbf390 3323 is_user = mmu_idx == MMU_USER_IDX;
d4c430a8
PB		 3324 ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot,
3325 &page_size);
b5ff1b31
FB		 3326 if (ret == 0) {
3327 /* Map a single [sub]page. */
a8170e5e 3328 phys_addr &= ~(hwaddr)0x3ff;
b5ff1b31 3329 address &= ~(uint32_t)0x3ff;
3ad493fc 3330 tlb_set_page (env, address, phys_addr, prot, mmu_idx, page_size);
d4c430a8 3331 return 0;
b5ff1b31
FB		 3332 }
3333
3334 if (access_type == 2) {
3335 env->cp15.c5_insn = ret;
3336 env->cp15.c6_insn = address;
3337 env->exception_index = EXCP_PREFETCH_ABORT;
3338 } else {
3339 env->cp15.c5_data = ret;
9ee6e8bb
PB		 3340 if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6))
3341 env->cp15.c5_data |= (1 << 11);
b5ff1b31
FB		 3342 env->cp15.c6_data = address;
3343 env->exception_index = EXCP_DATA_ABORT;
3344 }
3345 return 1;
3346}
3347
00b941e5 3348hwaddr arm_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
b5ff1b31 3349{
00b941e5 3350 ARMCPU *cpu = ARM_CPU(cs);
a8170e5e 3351 hwaddr phys_addr;
d4c430a8 3352 target_ulong page_size;
b5ff1b31
FB		 3353 int prot;
3354 int ret;
3355
00b941e5 3356 ret = get_phys_addr(&cpu->env, addr, 0, 0, &phys_addr, &prot, &page_size);
b5ff1b31 3357
00b941e5 3358 if (ret != 0) {
b5ff1b31 3359 return -1;
00b941e5 3360 }
b5ff1b31
FB		 3361
3362 return phys_addr;
3363}
3364
0ecb72a5 3365void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
9ee6e8bb 3366{
39ea3d4e
PM		 3367 if ((env->uncached_cpsr & CPSR_M) == mode) {
3368 env->regs[13] = val;
3369 } else {
f5206413 3370 env->banked_r13[bank_number(mode)] = val;
39ea3d4e 3371 }
9ee6e8bb
PB		 3372}
3373
0ecb72a5 3374uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
9ee6e8bb 3375{
39ea3d4e
PM		 3376 if ((env->uncached_cpsr & CPSR_M) == mode) {
3377 return env->regs[13];
3378 } else {
f5206413 3379 return env->banked_r13[bank_number(mode)];
39ea3d4e 3380 }
9ee6e8bb
PB		 3381}
3382
0ecb72a5 3383uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
9ee6e8bb
PB		 3384{
3385 switch (reg) {
3386 case 0: /* APSR */
3387 return xpsr_read(env) & 0xf8000000;
3388 case 1: /* IAPSR */
3389 return xpsr_read(env) & 0xf80001ff;
3390 case 2: /* EAPSR */
3391 return xpsr_read(env) & 0xff00fc00;
3392 case 3: /* xPSR */
3393 return xpsr_read(env) & 0xff00fdff;
3394 case 5: /* IPSR */
3395 return xpsr_read(env) & 0x000001ff;
3396 case 6: /* EPSR */
3397 return xpsr_read(env) & 0x0700fc00;
3398 case 7: /* IEPSR */
3399 return xpsr_read(env) & 0x0700edff;
3400 case 8: /* MSP */
3401 return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
3402 case 9: /* PSP */
3403 return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
3404 case 16: /* PRIMASK */
3405 return (env->uncached_cpsr & CPSR_I) != 0;
82845826
SH		 3406 case 17: /* BASEPRI */
3407 case 18: /* BASEPRI_MAX */
9ee6e8bb 3408 return env->v7m.basepri;
82845826
SH		 3409 case 19: /* FAULTMASK */
3410 return (env->uncached_cpsr & CPSR_F) != 0;
9ee6e8bb
PB		 3411 case 20: /* CONTROL */
3412 return env->v7m.control;
3413 default:
3414 /* ??? For debugging only. */
3415 cpu_abort(env, "Unimplemented system register read (%d)\n", reg);
3416 return 0;
3417 }
3418}
3419
0ecb72a5 3420void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
9ee6e8bb
PB		 3421{
3422 switch (reg) {
3423 case 0: /* APSR */
3424 xpsr_write(env, val, 0xf8000000);
3425 break;
3426 case 1: /* IAPSR */
3427 xpsr_write(env, val, 0xf8000000);
3428 break;
3429 case 2: /* EAPSR */
3430 xpsr_write(env, val, 0xfe00fc00);
3431 break;
3432 case 3: /* xPSR */
3433 xpsr_write(env, val, 0xfe00fc00);
3434 break;
3435 case 5: /* IPSR */
3436 /* IPSR bits are readonly. */
3437 break;
3438 case 6: /* EPSR */
3439 xpsr_write(env, val, 0x0600fc00);
3440 break;
3441 case 7: /* IEPSR */
3442 xpsr_write(env, val, 0x0600fc00);
3443 break;
3444 case 8: /* MSP */
3445 if (env->v7m.current_sp)
3446 env->v7m.other_sp = val;
3447 else
3448 env->regs[13] = val;
3449 break;
3450 case 9: /* PSP */
3451 if (env->v7m.current_sp)
3452 env->regs[13] = val;
3453 else
3454 env->v7m.other_sp = val;
3455 break;
3456 case 16: /* PRIMASK */
3457 if (val & 1)
3458 env->uncached_cpsr |= CPSR_I;
3459 else
3460 env->uncached_cpsr &= ~CPSR_I;
3461 break;
82845826 3462 case 17: /* BASEPRI */
9ee6e8bb
PB		 3463 env->v7m.basepri = val & 0xff;
3464 break;
82845826 3465 case 18: /* BASEPRI_MAX */
9ee6e8bb
PB		 3466 val &= 0xff;
3467 if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
3468 env->v7m.basepri = val;
3469 break;
82845826
SH		 3470 case 19: /* FAULTMASK */
3471 if (val & 1)
3472 env->uncached_cpsr |= CPSR_F;
3473 else
3474 env->uncached_cpsr &= ~CPSR_F;
3475 break;
9ee6e8bb
PB		 3476 case 20: /* CONTROL */
3477 env->v7m.control = val & 3;
3478 switch_v7m_sp(env, (val & 2) != 0);
3479 break;
3480 default:
3481 /* ??? For debugging only. */
3482 cpu_abort(env, "Unimplemented system register write (%d)\n", reg);
3483 return;
3484 }
3485}
3486
b5ff1b31 3487#endif
6ddbc6e4
PB		 3488
3489/* Note that signed overflow is undefined in C. The following routines are
3490 careful to use unsigned types where modulo arithmetic is required.
3491 Failure to do so _will_ break on newer gcc. */
3492
3493/* Signed saturating arithmetic. */
3494
1654b2d6 3495/* Perform 16-bit signed saturating addition. */
6ddbc6e4
PB		 3496static inline uint16_t add16_sat(uint16_t a, uint16_t b)
3497{
3498 uint16_t res;
3499
3500 res = a + b;
3501 if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
3502 if (a & 0x8000)
3503 res = 0x8000;
3504 else
3505 res = 0x7fff;
3506 }
3507 return res;
3508}
3509
1654b2d6 3510/* Perform 8-bit signed saturating addition. */
6ddbc6e4
PB		 3511static inline uint8_t add8_sat(uint8_t a, uint8_t b)
3512{
3513 uint8_t res;
3514
3515 res = a + b;
3516 if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
3517 if (a & 0x80)
3518 res = 0x80;
3519 else
3520 res = 0x7f;
3521 }
3522 return res;
3523}
3524
1654b2d6 3525/* Perform 16-bit signed saturating subtraction. */
6ddbc6e4
PB		 3526static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
3527{
3528 uint16_t res;
3529
3530 res = a - b;
3531 if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
3532 if (a & 0x8000)
3533 res = 0x8000;
3534 else
3535 res = 0x7fff;
3536 }
3537 return res;
3538}
3539
1654b2d6 3540/* Perform 8-bit signed saturating subtraction. */
6ddbc6e4
PB		 3541static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
3542{
3543 uint8_t res;
3544
3545 res = a - b;
3546 if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
3547 if (a & 0x80)
3548 res = 0x80;
3549 else
3550 res = 0x7f;
3551 }
3552 return res;
3553}
3554
3555#define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
3556#define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
3557#define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
3558#define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
3559#define PFX q
3560
3561#include "op_addsub.h"
3562
3563/* Unsigned saturating arithmetic. */
460a09c1 3564static inline uint16_t add16_usat(uint16_t a, uint16_t b)
6ddbc6e4
PB		 3565{
3566 uint16_t res;
3567 res = a + b;
3568 if (res < a)
3569 res = 0xffff;
3570 return res;
3571}
3572
460a09c1 3573static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
6ddbc6e4 3574{
4c4fd3f8 3575 if (a > b)
6ddbc6e4
PB		 3576 return a - b;
3577 else
3578 return 0;
3579}
3580
3581static inline uint8_t add8_usat(uint8_t a, uint8_t b)
3582{
3583 uint8_t res;
3584 res = a + b;
3585 if (res < a)
3586 res = 0xff;
3587 return res;
3588}
3589
3590static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
3591{
4c4fd3f8 3592 if (a > b)
6ddbc6e4
PB		 3593 return a - b;
3594 else
3595 return 0;
3596}
3597
3598#define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
3599#define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
3600#define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
3601#define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
3602#define PFX uq
3603
3604#include "op_addsub.h"
3605
3606/* Signed modulo arithmetic. */
3607#define SARITH16(a, b, n, op) do { \
3608 int32_t sum; \
db6e2e65 3609 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
6ddbc6e4
PB		 3610 RESULT(sum, n, 16); \
3611 if (sum >= 0) \
3612 ge |= 3 << (n * 2); \
3613 } while(0)
3614
3615#define SARITH8(a, b, n, op) do { \
3616 int32_t sum; \
db6e2e65 3617 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
6ddbc6e4
PB		 3618 RESULT(sum, n, 8); \
3619 if (sum >= 0) \
3620 ge |= 1 << n; \
3621 } while(0)
3622
3623
3624#define ADD16(a, b, n) SARITH16(a, b, n, +)
3625#define SUB16(a, b, n) SARITH16(a, b, n, -)
3626#define ADD8(a, b, n) SARITH8(a, b, n, +)
3627#define SUB8(a, b, n) SARITH8(a, b, n, -)
3628#define PFX s
3629#define ARITH_GE
3630
3631#include "op_addsub.h"
3632
3633/* Unsigned modulo arithmetic. */
3634#define ADD16(a, b, n) do { \
3635 uint32_t sum; \
3636 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
3637 RESULT(sum, n, 16); \
a87aa10b 3638 if ((sum >> 16) == 1) \
6ddbc6e4
PB		 3639 ge |= 3 << (n * 2); \
3640 } while(0)
3641
3642#define ADD8(a, b, n) do { \
3643 uint32_t sum; \
3644 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
3645 RESULT(sum, n, 8); \
a87aa10b
AZ		 3646 if ((sum >> 8) == 1) \
3647 ge |= 1 << n; \
6ddbc6e4
PB		 3648 } while(0)
3649
3650#define SUB16(a, b, n) do { \
3651 uint32_t sum; \
3652 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
3653 RESULT(sum, n, 16); \
3654 if ((sum >> 16) == 0) \
3655 ge |= 3 << (n * 2); \
3656 } while(0)
3657
3658#define SUB8(a, b, n) do { \
3659 uint32_t sum; \
3660 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
3661 RESULT(sum, n, 8); \
3662 if ((sum >> 8) == 0) \
a87aa10b 3663 ge |= 1 << n; \
6ddbc6e4
PB		 3664 } while(0)
3665
3666#define PFX u
3667#define ARITH_GE
3668
3669#include "op_addsub.h"
3670
3671/* Halved signed arithmetic. */
3672#define ADD16(a, b, n) \
3673 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
3674#define SUB16(a, b, n) \
3675 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
3676#define ADD8(a, b, n) \
3677 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
3678#define SUB8(a, b, n) \
3679 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
3680#define PFX sh
3681
3682#include "op_addsub.h"
3683
3684/* Halved unsigned arithmetic. */
3685#define ADD16(a, b, n) \
3686 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
3687#define SUB16(a, b, n) \
3688 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
3689#define ADD8(a, b, n) \
3690 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
3691#define SUB8(a, b, n) \
3692 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
3693#define PFX uh
3694
3695#include "op_addsub.h"
3696
3697static inline uint8_t do_usad(uint8_t a, uint8_t b)
3698{
3699 if (a > b)
3700 return a - b;
3701 else
3702 return b - a;
3703}
3704
3705/* Unsigned sum of absolute byte differences. */
3706uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
3707{
3708 uint32_t sum;
3709 sum = do_usad(a, b);
3710 sum += do_usad(a >> 8, b >> 8);
3711 sum += do_usad(a >> 16, b >>16);
3712 sum += do_usad(a >> 24, b >> 24);
3713 return sum;
3714}
3715
3716/* For ARMv6 SEL instruction. */
3717uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
3718{
3719 uint32_t mask;
3720
3721 mask = 0;
3722 if (flags & 1)
3723 mask |= 0xff;
3724 if (flags & 2)
3725 mask |= 0xff00;
3726 if (flags & 4)
3727 mask |= 0xff0000;
3728 if (flags & 8)
3729 mask |= 0xff000000;
3730 return (a & mask) | (b & ~mask);
3731}
3732
b90372ad
PM		 3733/* VFP support. We follow the convention used for VFP instructions:
3734 Single precision routines have a "s" suffix, double precision a
4373f3ce
PB		 3735 "d" suffix. */
3736
3737/* Convert host exception flags to vfp form. */
3738static inline int vfp_exceptbits_from_host(int host_bits)
3739{
3740 int target_bits = 0;
3741
3742 if (host_bits & float_flag_invalid)
3743 target_bits |= 1;
3744 if (host_bits & float_flag_divbyzero)
3745 target_bits |= 2;
3746 if (host_bits & float_flag_overflow)
3747 target_bits |= 4;
36802b6b 3748 if (host_bits & (float_flag_underflow | float_flag_output_denormal))
4373f3ce
PB		 3749 target_bits |= 8;
3750 if (host_bits & float_flag_inexact)
3751 target_bits |= 0x10;
cecd8504
PM		 3752 if (host_bits & float_flag_input_denormal)
3753 target_bits |= 0x80;
4373f3ce
PB		 3754 return target_bits;
3755}
3756
0ecb72a5 3757uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
4373f3ce
PB		 3758{
3759 int i;
3760 uint32_t fpscr;
3761
3762 fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
3763 | (env->vfp.vec_len << 16)
3764 | (env->vfp.vec_stride << 20);
3765 i = get_float_exception_flags(&env->vfp.fp_status);
3a492f3a 3766 i |= get_float_exception_flags(&env->vfp.standard_fp_status);
4373f3ce
PB		 3767 fpscr |= vfp_exceptbits_from_host(i);
3768 return fpscr;
3769}
3770
0ecb72a5 3771uint32_t vfp_get_fpscr(CPUARMState *env)
01653295
PM		 3772{
3773 return HELPER(vfp_get_fpscr)(env);
3774}
3775
4373f3ce
PB		 3776/* Convert vfp exception flags to target form. */
3777static inline int vfp_exceptbits_to_host(int target_bits)
3778{
3779 int host_bits = 0;
3780
3781 if (target_bits & 1)
3782 host_bits |= float_flag_invalid;
3783 if (target_bits & 2)
3784 host_bits |= float_flag_divbyzero;
3785 if (target_bits & 4)
3786 host_bits |= float_flag_overflow;
3787 if (target_bits & 8)
3788 host_bits |= float_flag_underflow;
3789 if (target_bits & 0x10)
3790 host_bits |= float_flag_inexact;
cecd8504
PM		 3791 if (target_bits & 0x80)
3792 host_bits |= float_flag_input_denormal;
4373f3ce
PB		 3793 return host_bits;
3794}
3795
0ecb72a5 3796void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
4373f3ce
PB		 3797{
3798 int i;
3799 uint32_t changed;
3800
3801 changed = env->vfp.xregs[ARM_VFP_FPSCR];
3802 env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
3803 env->vfp.vec_len = (val >> 16) & 7;
3804 env->vfp.vec_stride = (val >> 20) & 3;
3805
3806 changed ^= val;
3807 if (changed & (3 << 22)) {
3808 i = (val >> 22) & 3;
3809 switch (i) {
4d3da0f3 3810 case FPROUNDING_TIEEVEN:
4373f3ce
PB		 3811 i = float_round_nearest_even;
3812 break;
4d3da0f3 3813 case FPROUNDING_POSINF:
4373f3ce
PB		 3814 i = float_round_up;
3815 break;
4d3da0f3 3816 case FPROUNDING_NEGINF:
4373f3ce
PB		 3817 i = float_round_down;
3818 break;
4d3da0f3 3819 case FPROUNDING_ZERO:
4373f3ce
PB		 3820 i = float_round_to_zero;
3821 break;
3822 }
3823 set_float_rounding_mode(i, &env->vfp.fp_status);
3824 }
cecd8504 3825 if (changed & (1 << 24)) {
fe76d976 3826 set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
cecd8504
PM		 3827 set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
3828 }
5c7908ed
PB		 3829 if (changed & (1 << 25))
3830 set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
4373f3ce 3831
b12c390b 3832 i = vfp_exceptbits_to_host(val);
4373f3ce 3833 set_float_exception_flags(i, &env->vfp.fp_status);
3a492f3a 3834 set_float_exception_flags(0, &env->vfp.standard_fp_status);
4373f3ce
PB		 3835}
3836
0ecb72a5 3837void vfp_set_fpscr(CPUARMState *env, uint32_t val)
01653295
PM		 3838{
3839 HELPER(vfp_set_fpscr)(env, val);
3840}
3841
4373f3ce
PB		 3842#define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
3843
3844#define VFP_BINOP(name) \
ae1857ec 3845float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
4373f3ce 3846{ \
ae1857ec
PM		 3847 float_status *fpst = fpstp; \
3848 return float32_ ## name(a, b, fpst); \
4373f3ce 3849} \
ae1857ec 3850float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
4373f3ce 3851{ \
ae1857ec
PM		 3852 float_status *fpst = fpstp; \
3853 return float64_ ## name(a, b, fpst); \
4373f3ce
PB		 3854}
3855VFP_BINOP(add)
3856VFP_BINOP(sub)
3857VFP_BINOP(mul)
3858VFP_BINOP(div)
f71a2ae5
PM		 3859VFP_BINOP(min)
3860VFP_BINOP(max)
3861VFP_BINOP(minnum)
3862VFP_BINOP(maxnum)
4373f3ce
PB		 3863#undef VFP_BINOP
3864
3865float32 VFP_HELPER(neg, s)(float32 a)
3866{
3867 return float32_chs(a);
3868}
3869
3870float64 VFP_HELPER(neg, d)(float64 a)
3871{
66230e0d 3872 return float64_chs(a);
4373f3ce
PB		 3873}
3874
3875float32 VFP_HELPER(abs, s)(float32 a)
3876{
3877 return float32_abs(a);
3878}
3879
3880float64 VFP_HELPER(abs, d)(float64 a)
3881{
66230e0d 3882 return float64_abs(a);
4373f3ce
PB		 3883}
3884
0ecb72a5 3885float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
4373f3ce
PB		 3886{
3887 return float32_sqrt(a, &env->vfp.fp_status);
3888}
3889
0ecb72a5 3890float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
4373f3ce
PB		 3891{
3892 return float64_sqrt(a, &env->vfp.fp_status);
3893}
3894
3895/* XXX: check quiet/signaling case */
3896#define DO_VFP_cmp(p, type) \
0ecb72a5 3897void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
4373f3ce
PB		 3898{ \
3899 uint32_t flags; \
3900 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
3901 case 0: flags = 0x6; break; \
3902 case -1: flags = 0x8; break; \
3903 case 1: flags = 0x2; break; \
3904 default: case 2: flags = 0x3; break; \
3905 } \
3906 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
3907 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
3908} \
0ecb72a5 3909void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
4373f3ce
PB		 3910{ \
3911 uint32_t flags; \
3912 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
3913 case 0: flags = 0x6; break; \
3914 case -1: flags = 0x8; break; \
3915 case 1: flags = 0x2; break; \
3916 default: case 2: flags = 0x3; break; \
3917 } \
3918 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
3919 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
3920}
3921DO_VFP_cmp(s, float32)
3922DO_VFP_cmp(d, float64)
3923#undef DO_VFP_cmp
3924
5500b06c 3925/* Integer to float and float to integer conversions */
4373f3ce 3926
5500b06c
PM		 3927#define CONV_ITOF(name, fsz, sign) \
3928 float##fsz HELPER(name)(uint32_t x, void *fpstp) \
3929{ \
3930 float_status *fpst = fpstp; \
85836979 3931 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
4373f3ce
PB		 3932}
3933
5500b06c
PM		 3934#define CONV_FTOI(name, fsz, sign, round) \
3935uint32_t HELPER(name)(float##fsz x, void *fpstp) \
3936{ \
3937 float_status *fpst = fpstp; \
3938 if (float##fsz##_is_any_nan(x)) { \
3939 float_raise(float_flag_invalid, fpst); \
3940 return 0; \
3941 } \
3942 return float##fsz##_to_##sign##int32##round(x, fpst); \
4373f3ce
PB		 3943}
3944
5500b06c
PM		 3945#define FLOAT_CONVS(name, p, fsz, sign) \
3946CONV_ITOF(vfp_##name##to##p, fsz, sign) \
3947CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
3948CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
4373f3ce 3949
5500b06c
PM		 3950FLOAT_CONVS(si, s, 32, )
3951FLOAT_CONVS(si, d, 64, )
3952FLOAT_CONVS(ui, s, 32, u)
3953FLOAT_CONVS(ui, d, 64, u)
4373f3ce 3954
5500b06c
PM		 3955#undef CONV_ITOF
3956#undef CONV_FTOI
3957#undef FLOAT_CONVS
4373f3ce
PB		 3958
3959/* floating point conversion */
0ecb72a5 3960float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
4373f3ce 3961{
2d627737
PM		 3962 float64 r = float32_to_float64(x, &env->vfp.fp_status);
3963 /* ARM requires that S<->D conversion of any kind of NaN generates
3964 * a quiet NaN by forcing the most significant frac bit to 1.
3965 */
3966 return float64_maybe_silence_nan(r);
4373f3ce
PB		 3967}
3968
0ecb72a5 3969float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
4373f3ce 3970{
2d627737
PM		 3971 float32 r = float64_to_float32(x, &env->vfp.fp_status);
3972 /* ARM requires that S<->D conversion of any kind of NaN generates
3973 * a quiet NaN by forcing the most significant frac bit to 1.
3974 */
3975 return float32_maybe_silence_nan(r);
4373f3ce
PB		 3976}
3977
3978/* VFP3 fixed point conversion. */
16d5b3ca 3979#define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
8ed697e8
WN		 3980float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \
3981 void *fpstp) \
4373f3ce 3982{ \
5500b06c 3983 float_status *fpst = fpstp; \
622465e1 3984 float##fsz tmp; \
8ed697e8 3985 tmp = itype##_to_##float##fsz(x, fpst); \
5500b06c 3986 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
16d5b3ca
WN		 3987}
3988
abe66f70
PM		 3989/* Notice that we want only input-denormal exception flags from the
3990 * scalbn operation: the other possible flags (overflow+inexact if
3991 * we overflow to infinity, output-denormal) aren't correct for the
3992 * complete scale-and-convert operation.
3993 */
16d5b3ca
WN		 3994#define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, round) \
3995uint##isz##_t HELPER(vfp_to##name##p##round)(float##fsz x, \
3996 uint32_t shift, \
3997 void *fpstp) \
4373f3ce 3998{ \
5500b06c 3999 float_status *fpst = fpstp; \
abe66f70 4000 int old_exc_flags = get_float_exception_flags(fpst); \
622465e1
PM		 4001 float##fsz tmp; \
4002 if (float##fsz##_is_any_nan(x)) { \
5500b06c 4003 float_raise(float_flag_invalid, fpst); \
622465e1 4004 return 0; \
09d9487f 4005 } \
5500b06c 4006 tmp = float##fsz##_scalbn(x, shift, fpst); \
abe66f70
PM		 4007 old_exc_flags |= get_float_exception_flags(fpst) \
4008 & float_flag_input_denormal; \
4009 set_float_exception_flags(old_exc_flags, fpst); \
16d5b3ca 4010 return float##fsz##_to_##itype##round(tmp, fpst); \
622465e1
PM		 4011}
4012
16d5b3ca
WN		 4013#define VFP_CONV_FIX(name, p, fsz, isz, itype) \
4014VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
3c6a074a
WN		 4015VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, _round_to_zero) \
4016VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
4017
4018#define VFP_CONV_FIX_A64(name, p, fsz, isz, itype) \
4019VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
4020VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
16d5b3ca 4021
8ed697e8
WN		 4022VFP_CONV_FIX(sh, d, 64, 64, int16)
4023VFP_CONV_FIX(sl, d, 64, 64, int32)
3c6a074a 4024VFP_CONV_FIX_A64(sq, d, 64, 64, int64)
8ed697e8
WN		 4025VFP_CONV_FIX(uh, d, 64, 64, uint16)
4026VFP_CONV_FIX(ul, d, 64, 64, uint32)
3c6a074a 4027VFP_CONV_FIX_A64(uq, d, 64, 64, uint64)
8ed697e8
WN		 4028VFP_CONV_FIX(sh, s, 32, 32, int16)
4029VFP_CONV_FIX(sl, s, 32, 32, int32)
3c6a074a 4030VFP_CONV_FIX_A64(sq, s, 32, 64, int64)
8ed697e8
WN		 4031VFP_CONV_FIX(uh, s, 32, 32, uint16)
4032VFP_CONV_FIX(ul, s, 32, 32, uint32)
3c6a074a 4033VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
4373f3ce 4034#undef VFP_CONV_FIX
16d5b3ca
WN		 4035#undef VFP_CONV_FIX_FLOAT
4036#undef VFP_CONV_FLOAT_FIX_ROUND
4373f3ce 4037
52a1f6a3
AG		 4038/* Set the current fp rounding mode and return the old one.
4039 * The argument is a softfloat float_round_ value.
4040 */
4041uint32_t HELPER(set_rmode)(uint32_t rmode, CPUARMState *env)
4042{
4043 float_status *fp_status = &env->vfp.fp_status;
4044
4045 uint32_t prev_rmode = get_float_rounding_mode(fp_status);
4046 set_float_rounding_mode(rmode, fp_status);
4047
4048 return prev_rmode;
4049}
4050
43630e58
WN		 4051/* Set the current fp rounding mode in the standard fp status and return
4052 * the old one. This is for NEON instructions that need to change the
4053 * rounding mode but wish to use the standard FPSCR values for everything
4054 * else. Always set the rounding mode back to the correct value after
4055 * modifying it.
4056 * The argument is a softfloat float_round_ value.
4057 */
4058uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env)
4059{
4060 float_status *fp_status = &env->vfp.standard_fp_status;
4061
4062 uint32_t prev_rmode = get_float_rounding_mode(fp_status);
4063 set_float_rounding_mode(rmode, fp_status);
4064
4065 return prev_rmode;
4066}
4067
60011498 4068/* Half precision conversions. */
0ecb72a5 4069static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s)
60011498 4070{
60011498 4071 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
fb91678d
PM		 4072 float32 r = float16_to_float32(make_float16(a), ieee, s);
4073 if (ieee) {
4074 return float32_maybe_silence_nan(r);
4075 }
4076 return r;
60011498
PB		 4077}
4078
0ecb72a5 4079static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s)
60011498 4080{
60011498 4081 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
fb91678d
PM		 4082 float16 r = float32_to_float16(a, ieee, s);
4083 if (ieee) {
4084 r = float16_maybe_silence_nan(r);
4085 }
4086 return float16_val(r);
60011498
PB		 4087}
4088
0ecb72a5 4089float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
2d981da7
PM		 4090{
4091 return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
4092}
4093
0ecb72a5 4094uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
2d981da7
PM		 4095{
4096 return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
4097}
4098
0ecb72a5 4099float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
2d981da7
PM		 4100{
4101 return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
4102}
4103
0ecb72a5 4104uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
2d981da7
PM		 4105{
4106 return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
4107}
4108
8900aad2
PM		 4109float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, CPUARMState *env)
4110{
4111 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
4112 float64 r = float16_to_float64(make_float16(a), ieee, &env->vfp.fp_status);
4113 if (ieee) {
4114 return float64_maybe_silence_nan(r);
4115 }
4116 return r;
4117}
4118
4119uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, CPUARMState *env)
4120{
4121 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
4122 float16 r = float64_to_float16(a, ieee, &env->vfp.fp_status);
4123 if (ieee) {
4124 r = float16_maybe_silence_nan(r);
4125 }
4126 return float16_val(r);
4127}
4128
dda3ec49 4129#define float32_two make_float32(0x40000000)
6aae3df1
PM		 4130#define float32_three make_float32(0x40400000)
4131#define float32_one_point_five make_float32(0x3fc00000)
dda3ec49 4132
0ecb72a5 4133float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env)
4373f3ce 4134{
dda3ec49
PM		 4135 float_status *s = &env->vfp.standard_fp_status;
4136 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
4137 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
43fe9bdb
PM		 4138 if (!(float32_is_zero(a) || float32_is_zero(b))) {
4139 float_raise(float_flag_input_denormal, s);
4140 }
dda3ec49
PM		 4141 return float32_two;
4142 }
4143 return float32_sub(float32_two, float32_mul(a, b, s), s);
4373f3ce
PB		 4144}
4145
0ecb72a5 4146float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
4373f3ce 4147{
71826966 4148 float_status *s = &env->vfp.standard_fp_status;
9ea62f57
PM		 4149 float32 product;
4150 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
4151 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
43fe9bdb
PM		 4152 if (!(float32_is_zero(a) || float32_is_zero(b))) {
4153 float_raise(float_flag_input_denormal, s);
4154 }
6aae3df1 4155 return float32_one_point_five;
9ea62f57 4156 }
6aae3df1
PM		 4157 product = float32_mul(a, b, s);
4158 return float32_div(float32_sub(float32_three, product, s), float32_two, s);
4373f3ce
PB		 4159}
4160
8f8e3aa4
PB		 4161/* NEON helpers. */
4162
56bf4fe2
CL		 4163/* Constants 256 and 512 are used in some helpers; we avoid relying on
4164 * int->float conversions at run-time. */
4165#define float64_256 make_float64(0x4070000000000000LL)
4166#define float64_512 make_float64(0x4080000000000000LL)
4167
fe0e4872
CL		 4168/* The algorithm that must be used to calculate the estimate
4169 * is specified by the ARM ARM.
4170 */
0ecb72a5 4171static float64 recip_estimate(float64 a, CPUARMState *env)
fe0e4872 4172{
1146a817
PM		 4173 /* These calculations mustn't set any fp exception flags,
4174 * so we use a local copy of the fp_status.
4175 */
4176 float_status dummy_status = env->vfp.standard_fp_status;
4177 float_status *s = &dummy_status;
fe0e4872
CL		 4178 /* q = (int)(a * 512.0) */
4179 float64 q = float64_mul(float64_512, a, s);
4180 int64_t q_int = float64_to_int64_round_to_zero(q, s);
4181
4182 /* r = 1.0 / (((double)q + 0.5) / 512.0) */
4183 q = int64_to_float64(q_int, s);
4184 q = float64_add(q, float64_half, s);
4185 q = float64_div(q, float64_512, s);
4186 q = float64_div(float64_one, q, s);
4187
4188 /* s = (int)(256.0 * r + 0.5) */
4189 q = float64_mul(q, float64_256, s);
4190 q = float64_add(q, float64_half, s);
4191 q_int = float64_to_int64_round_to_zero(q, s);
4192
4193 /* return (double)s / 256.0 */
4194 return float64_div(int64_to_float64(q_int, s), float64_256, s);
4195}
4196
0ecb72a5 4197float32 HELPER(recpe_f32)(float32 a, CPUARMState *env)
4373f3ce 4198{
fe0e4872
CL		 4199 float_status *s = &env->vfp.standard_fp_status;
4200 float64 f64;
4201 uint32_t val32 = float32_val(a);
4202
4203 int result_exp;
4204 int a_exp = (val32 & 0x7f800000) >> 23;
4205 int sign = val32 & 0x80000000;
4206
4207 if (float32_is_any_nan(a)) {
4208 if (float32_is_signaling_nan(a)) {
4209 float_raise(float_flag_invalid, s);
4210 }
4211 return float32_default_nan;
4212 } else if (float32_is_infinity(a)) {
4213 return float32_set_sign(float32_zero, float32_is_neg(a));
4214 } else if (float32_is_zero_or_denormal(a)) {
43fe9bdb
PM		 4215 if (!float32_is_zero(a)) {
4216 float_raise(float_flag_input_denormal, s);
4217 }
fe0e4872
CL		 4218 float_raise(float_flag_divbyzero, s);
4219 return float32_set_sign(float32_infinity, float32_is_neg(a));
4220 } else if (a_exp >= 253) {
4221 float_raise(float_flag_underflow, s);
4222 return float32_set_sign(float32_zero, float32_is_neg(a));
4223 }
4224
4225 f64 = make_float64((0x3feULL << 52)
4226 | ((int64_t)(val32 & 0x7fffff) << 29));
4227
4228 result_exp = 253 - a_exp;
4229
4230 f64 = recip_estimate(f64, env);
4231
4232 val32 = sign
4233 | ((result_exp & 0xff) << 23)
4234 | ((float64_val(f64) >> 29) & 0x7fffff);
4235 return make_float32(val32);
4373f3ce
PB		 4236}
4237
e07be5d2
CL		 4238/* The algorithm that must be used to calculate the estimate
4239 * is specified by the ARM ARM.
4240 */
0ecb72a5 4241static float64 recip_sqrt_estimate(float64 a, CPUARMState *env)
e07be5d2 4242{
1146a817
PM		 4243 /* These calculations mustn't set any fp exception flags,
4244 * so we use a local copy of the fp_status.
4245 */
4246 float_status dummy_status = env->vfp.standard_fp_status;
4247 float_status *s = &dummy_status;
e07be5d2
CL		 4248 float64 q;
4249 int64_t q_int;
4250
4251 if (float64_lt(a, float64_half, s)) {
4252 /* range 0.25 <= a < 0.5 */
4253
4254 /* a in units of 1/512 rounded down */
4255 /* q0 = (int)(a * 512.0); */
4256 q = float64_mul(float64_512, a, s);
4257 q_int = float64_to_int64_round_to_zero(q, s);
4258
4259 /* reciprocal root r */
4260 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
4261 q = int64_to_float64(q_int, s);
4262 q = float64_add(q, float64_half, s);
4263 q = float64_div(q, float64_512, s);
4264 q = float64_sqrt(q, s);
4265 q = float64_div(float64_one, q, s);
4266 } else {
4267 /* range 0.5 <= a < 1.0 */
4268
4269 /* a in units of 1/256 rounded down */
4270 /* q1 = (int)(a * 256.0); */
4271 q = float64_mul(float64_256, a, s);
4272 int64_t q_int = float64_to_int64_round_to_zero(q, s);
4273
4274 /* reciprocal root r */
4275 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
4276 q = int64_to_float64(q_int, s);
4277 q = float64_add(q, float64_half, s);
4278 q = float64_div(q, float64_256, s);
4279 q = float64_sqrt(q, s);
4280 q = float64_div(float64_one, q, s);
4281 }
4282 /* r in units of 1/256 rounded to nearest */
4283 /* s = (int)(256.0 * r + 0.5); */
4284
4285 q = float64_mul(q, float64_256,s );
4286 q = float64_add(q, float64_half, s);
4287 q_int = float64_to_int64_round_to_zero(q, s);
4288
4289 /* return (double)s / 256.0;*/
4290 return float64_div(int64_to_float64(q_int, s), float64_256, s);
4291}
4292
0ecb72a5 4293float32 HELPER(rsqrte_f32)(float32 a, CPUARMState *env)
4373f3ce 4294{
e07be5d2
CL		 4295 float_status *s = &env->vfp.standard_fp_status;
4296 int result_exp;
4297 float64 f64;
4298 uint32_t val;
4299 uint64_t val64;
4300
4301 val = float32_val(a);
4302
4303 if (float32_is_any_nan(a)) {
4304 if (float32_is_signaling_nan(a)) {
4305 float_raise(float_flag_invalid, s);
4306 }
4307 return float32_default_nan;
4308 } else if (float32_is_zero_or_denormal(a)) {
43fe9bdb
PM		 4309 if (!float32_is_zero(a)) {
4310 float_raise(float_flag_input_denormal, s);
4311 }
e07be5d2
CL		 4312 float_raise(float_flag_divbyzero, s);
4313 return float32_set_sign(float32_infinity, float32_is_neg(a));
4314 } else if (float32_is_neg(a)) {
4315 float_raise(float_flag_invalid, s);
4316 return float32_default_nan;
4317 } else if (float32_is_infinity(a)) {
4318 return float32_zero;
4319 }
4320
4321 /* Normalize to a double-precision value between 0.25 and 1.0,
4322 * preserving the parity of the exponent. */
4323 if ((val & 0x800000) == 0) {
4324 f64 = make_float64(((uint64_t)(val & 0x80000000) << 32)
4325 | (0x3feULL << 52)
4326 | ((uint64_t)(val & 0x7fffff) << 29));
4327 } else {
4328 f64 = make_float64(((uint64_t)(val & 0x80000000) << 32)
4329 | (0x3fdULL << 52)
4330 | ((uint64_t)(val & 0x7fffff) << 29));
4331 }
4332
4333 result_exp = (380 - ((val & 0x7f800000) >> 23)) / 2;
4334
4335 f64 = recip_sqrt_estimate(f64, env);
4336
4337 val64 = float64_val(f64);
4338
26cc6abf 4339 val = ((result_exp & 0xff) << 23)
e07be5d2
CL		 4340 | ((val64 >> 29) & 0x7fffff);
4341 return make_float32(val);
4373f3ce
PB		 4342}
4343
0ecb72a5 4344uint32_t HELPER(recpe_u32)(uint32_t a, CPUARMState *env)
4373f3ce 4345{
fe0e4872
CL		 4346 float64 f64;
4347
4348 if ((a & 0x80000000) == 0) {
4349 return 0xffffffff;
4350 }
4351
4352 f64 = make_float64((0x3feULL << 52)
4353 | ((int64_t)(a & 0x7fffffff) << 21));
4354
4355 f64 = recip_estimate (f64, env);
4356
4357 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
4373f3ce
PB		 4358}
4359
0ecb72a5 4360uint32_t HELPER(rsqrte_u32)(uint32_t a, CPUARMState *env)
4373f3ce 4361{
e07be5d2
CL		 4362 float64 f64;
4363
4364 if ((a & 0xc0000000) == 0) {
4365 return 0xffffffff;
4366 }
4367
4368 if (a & 0x80000000) {
4369 f64 = make_float64((0x3feULL << 52)
4370 | ((uint64_t)(a & 0x7fffffff) << 21));
4371 } else { /* bits 31-30 == '01' */
4372 f64 = make_float64((0x3fdULL << 52)
4373 | ((uint64_t)(a & 0x3fffffff) << 22));
4374 }
4375
4376 f64 = recip_sqrt_estimate(f64, env);
4377
4378 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
4373f3ce 4379}
fe1479c3 4380
da97f52c
PM		 4381/* VFPv4 fused multiply-accumulate */
4382float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
4383{
4384 float_status *fpst = fpstp;
4385 return float32_muladd(a, b, c, 0, fpst);
4386}
4387
4388float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
4389{
4390 float_status *fpst = fpstp;
4391 return float64_muladd(a, b, c, 0, fpst);
4392}
d9b0848d
PM		 4393
4394/* ARMv8 round to integral */
4395float32 HELPER(rints_exact)(float32 x, void *fp_status)
4396{
4397 return float32_round_to_int(x, fp_status);
4398}
4399
4400float64 HELPER(rintd_exact)(float64 x, void *fp_status)
4401{
4402 return float64_round_to_int(x, fp_status);
4403}
4404
4405float32 HELPER(rints)(float32 x, void *fp_status)
4406{
4407 int old_flags = get_float_exception_flags(fp_status), new_flags;
4408 float32 ret;
4409
4410 ret = float32_round_to_int(x, fp_status);
4411
4412 /* Suppress any inexact exceptions the conversion produced */
4413 if (!(old_flags & float_flag_inexact)) {
4414 new_flags = get_float_exception_flags(fp_status);
4415 set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
4416 }
4417
4418 return ret;
4419}
4420
4421float64 HELPER(rintd)(float64 x, void *fp_status)
4422{
4423 int old_flags = get_float_exception_flags(fp_status), new_flags;
4424 float64 ret;
4425
4426 ret = float64_round_to_int(x, fp_status);
4427
4428 new_flags = get_float_exception_flags(fp_status);
4429
4430 /* Suppress any inexact exceptions the conversion produced */
4431 if (!(old_flags & float_flag_inexact)) {
4432 new_flags = get_float_exception_flags(fp_status);
4433 set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
4434 }
4435
4436 return ret;
4437}
9972da66
WN		 4438
4439/* Convert ARM rounding mode to softfloat */
4440int arm_rmode_to_sf(int rmode)
4441{
4442 switch (rmode) {
4443 case FPROUNDING_TIEAWAY:
4444 rmode = float_round_ties_away;
4445 break;
4446 case FPROUNDING_ODD:
4447 /* FIXME: add support for TIEAWAY and ODD */
4448 qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n",
4449 rmode);
4450 case FPROUNDING_TIEEVEN:
4451 default:
4452 rmode = float_round_nearest_even;
4453 break;
4454 case FPROUNDING_POSINF:
4455 rmode = float_round_up;
4456 break;
4457 case FPROUNDING_NEGINF:
4458 rmode = float_round_down;
4459 break;
4460 case FPROUNDING_ZERO:
4461 rmode = float_round_to_zero;
4462 break;
4463 }
4464 return rmode;
4465}
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