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target-arm: Convert cp15 crn=0 crm={1,2} feature registers
[qemu.git] / target-arm / helper.c
CommitLineData
b5ff1b31 1#include "cpu.h"
9ee6e8bb 2#include "gdbstub.h"
7b59220e 3#include "helper.h"
7bbcb0af 4#include "host-utils.h"
0b03bdfc
PM		 5#include "sysemu.h"
6
4a501606
PM		 7#ifndef CONFIG_USER_ONLY
8static inline int get_phys_addr(CPUARMState *env, uint32_t address,
9 int access_type, int is_user,
10 uint32_t *phys_ptr, int *prot,
11 target_ulong *page_size);
12#endif
13
0ecb72a5 14static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
56aebc89
PB		 15{
16 int nregs;
17
18 /* VFP data registers are always little-endian. */
19 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
20 if (reg < nregs) {
21 stfq_le_p(buf, env->vfp.regs[reg]);
22 return 8;
23 }
24 if (arm_feature(env, ARM_FEATURE_NEON)) {
25 /* Aliases for Q regs. */
26 nregs += 16;
27 if (reg < nregs) {
28 stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
29 stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
30 return 16;
31 }
32 }
33 switch (reg - nregs) {
34 case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
35 case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
36 case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
37 }
38 return 0;
39}
40
0ecb72a5 41static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
56aebc89
PB		 42{
43 int nregs;
44
45 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
46 if (reg < nregs) {
47 env->vfp.regs[reg] = ldfq_le_p(buf);
48 return 8;
49 }
50 if (arm_feature(env, ARM_FEATURE_NEON)) {
51 nregs += 16;
52 if (reg < nregs) {
53 env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
54 env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
55 return 16;
56 }
57 }
58 switch (reg - nregs) {
59 case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
60 case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
71b3c3de 61 case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
56aebc89
PB		 62 }
63 return 0;
64}
65
c983fe6c
PM		 66static int dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
67{
68 env->cp15.c3 = value;
69 tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */
70 return 0;
71}
72
08de207b
PM		 73static int fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
74{
75 if (env->cp15.c13_fcse != value) {
76 /* Unlike real hardware the qemu TLB uses virtual addresses,
77 * not modified virtual addresses, so this causes a TLB flush.
78 */
79 tlb_flush(env, 1);
80 env->cp15.c13_fcse = value;
81 }
82 return 0;
83}
84static int contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
85 uint64_t value)
86{
87 if (env->cp15.c13_context != value && !arm_feature(env, ARM_FEATURE_MPU)) {
88 /* For VMSA (when not using the LPAE long descriptor page table
89 * format) this register includes the ASID, so do a TLB flush.
90 * For PMSA it is purely a process ID and no action is needed.
91 */
92 tlb_flush(env, 1);
93 }
94 env->cp15.c13_context = value;
95 return 0;
96}
97
d929823f
PM		 98static int tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
99 uint64_t value)
100{
101 /* Invalidate all (TLBIALL) */
102 tlb_flush(env, 1);
103 return 0;
104}
105
106static int tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
107 uint64_t value)
108{
109 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
110 tlb_flush_page(env, value & TARGET_PAGE_MASK);
111 return 0;
112}
113
114static int tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
115 uint64_t value)
116{
117 /* Invalidate by ASID (TLBIASID) */
118 tlb_flush(env, value == 0);
119 return 0;
120}
121
122static int tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
123 uint64_t value)
124{
125 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
126 tlb_flush_page(env, value & TARGET_PAGE_MASK);
127 return 0;
128}
129
e9aa6c21
PM		 130static const ARMCPRegInfo cp_reginfo[] = {
131 /* DBGDIDR: just RAZ. In particular this means the "debug architecture
132 * version" bits will read as a reserved value, which should cause
133 * Linux to not try to use the debug hardware.
134 */
135 { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
136 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
c983fe6c
PM		 137 /* MMU Domain access control / MPU write buffer control */
138 { .name = "DACR", .cp = 15,
139 .crn = 3, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
140 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3),
141 .resetvalue = 0, .writefn = dacr_write },
08de207b
PM		 142 { .name = "FCSEIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 0,
143 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
144 .resetvalue = 0, .writefn = fcse_write },
145 { .name = "CONTEXTIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 1,
146 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
147 .resetvalue = 0, .writefn = contextidr_write },
4fdd17dd
PM		 148 /* ??? This covers not just the impdef TLB lockdown registers but also
149 * some v7VMSA registers relating to TEX remap, so it is overly broad.
150 */
151 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = CP_ANY,
152 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
d929823f
PM		 153 /* MMU TLB control. Note that the wildcarding means we cover not just
154 * the unified TLB ops but also the dside/iside/inner-shareable variants.
155 */
156 { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
157 .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write, },
158 { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY,
159 .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write, },
160 { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY,
161 .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write, },
162 { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY,
163 .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write, },
c4804214
PM		 164 /* Cache maintenance ops; some of this space may be overridden later. */
165 { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
166 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
167 .type = ARM_CP_NOP | ARM_CP_OVERRIDE },
e9aa6c21
PM		 168 REGINFO_SENTINEL
169};
170
7d57f408
PM		 171static const ARMCPRegInfo not_v6_cp_reginfo[] = {
172 /* Not all pre-v6 cores implemented this WFI, so this is slightly
173 * over-broad.
174 */
175 { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
176 .access = PL1_W, .type = ARM_CP_WFI },
177 REGINFO_SENTINEL
178};
179
180static const ARMCPRegInfo not_v7_cp_reginfo[] = {
181 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
182 * is UNPREDICTABLE; we choose to NOP as most implementations do).
183 */
184 { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
185 .access = PL1_W, .type = ARM_CP_WFI },
34f90529
PM		 186 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
187 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
188 * OMAPCP will override this space.
189 */
190 { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0,
191 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data),
192 .resetvalue = 0 },
193 { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1,
194 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn),
195 .resetvalue = 0 },
7d57f408
PM		 196 REGINFO_SENTINEL
197};
198
2771db27
PM		 199static int cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
200{
201 if (env->cp15.c1_coproc != value) {
202 env->cp15.c1_coproc = value;
203 /* ??? Is this safe when called from within a TB? */
204 tb_flush(env);
205 }
206 return 0;
207}
208
7d57f408
PM		 209static const ARMCPRegInfo v6_cp_reginfo[] = {
210 /* prefetch by MVA in v6, NOP in v7 */
211 { .name = "MVA_prefetch",
212 .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
213 .access = PL1_W, .type = ARM_CP_NOP },
214 { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
215 .access = PL0_W, .type = ARM_CP_NOP },
216 { .name = "ISB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
217 .access = PL0_W, .type = ARM_CP_NOP },
218 { .name = "ISB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
219 .access = PL0_W, .type = ARM_CP_NOP },
06d76f31
PM		 220 { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
221 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_insn),
222 .resetvalue = 0, },
223 /* Watchpoint Fault Address Register : should actually only be present
224 * for 1136, 1176, 11MPCore.
225 */
226 { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
227 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
2771db27
PM		 228 { .name = "CPACR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2,
229 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_coproc),
230 .resetvalue = 0, .writefn = cpacr_write },
7d57f408
PM		 231 REGINFO_SENTINEL
232};
233
200ac0ef
PM		 234static int pmreg_read(CPUARMState *env, const ARMCPRegInfo *ri,
235 uint64_t *value)
236{
237 /* Generic performance monitor register read function for where
238 * user access may be allowed by PMUSERENR.
239 */
240 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
241 return EXCP_UDEF;
242 }
243 *value = CPREG_FIELD32(env, ri);
244 return 0;
245}
246
247static int pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
248 uint64_t value)
249{
250 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
251 return EXCP_UDEF;
252 }
253 /* only the DP, X, D and E bits are writable */
254 env->cp15.c9_pmcr &= ~0x39;
255 env->cp15.c9_pmcr |= (value & 0x39);
256 return 0;
257}
258
259static int pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
260 uint64_t value)
261{
262 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
263 return EXCP_UDEF;
264 }
265 value &= (1 << 31);
266 env->cp15.c9_pmcnten |= value;
267 return 0;
268}
269
270static int pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
271 uint64_t value)
272{
273 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
274 return EXCP_UDEF;
275 }
276 value &= (1 << 31);
277 env->cp15.c9_pmcnten &= ~value;
278 return 0;
279}
280
281static int pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
282 uint64_t value)
283{
284 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
285 return EXCP_UDEF;
286 }
287 env->cp15.c9_pmovsr &= ~value;
288 return 0;
289}
290
291static int pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
292 uint64_t value)
293{
294 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
295 return EXCP_UDEF;
296 }
297 env->cp15.c9_pmxevtyper = value & 0xff;
298 return 0;
299}
300
301static int pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
302 uint64_t value)
303{
304 env->cp15.c9_pmuserenr = value & 1;
305 return 0;
306}
307
308static int pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
309 uint64_t value)
310{
311 /* We have no event counters so only the C bit can be changed */
312 value &= (1 << 31);
313 env->cp15.c9_pminten |= value;
314 return 0;
315}
316
317static int pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
318 uint64_t value)
319{
320 value &= (1 << 31);
321 env->cp15.c9_pminten &= ~value;
322 return 0;
323}
324
e9aa6c21
PM		 325static const ARMCPRegInfo v7_cp_reginfo[] = {
326 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
327 * debug components
328 */
329 { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
330 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
331 { .name = "DBGDRAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
332 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
7d57f408
PM		 333 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
334 { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
335 .access = PL1_W, .type = ARM_CP_NOP },
200ac0ef
PM		 336 /* Performance monitors are implementation defined in v7,
337 * but with an ARM recommended set of registers, which we
338 * follow (although we don't actually implement any counters)
339 *
340 * Performance registers fall into three categories:
341 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
342 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
343 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
344 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
345 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
346 */
347 { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
348 .access = PL0_RW, .resetvalue = 0,
349 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
350 .readfn = pmreg_read, .writefn = pmcntenset_write },
351 { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
352 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
353 .readfn = pmreg_read, .writefn = pmcntenclr_write },
354 { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
355 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
356 .readfn = pmreg_read, .writefn = pmovsr_write },
357 /* Unimplemented so WI. Strictly speaking write accesses in PL0 should
358 * respect PMUSERENR.
359 */
360 { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
361 .access = PL0_W, .type = ARM_CP_NOP },
362 /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
363 * We choose to RAZ/WI. XXX should respect PMUSERENR.
364 */
365 { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
366 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
367 /* Unimplemented, RAZ/WI. XXX PMUSERENR */
368 { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
369 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
370 { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
371 .access = PL0_RW,
372 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
373 .readfn = pmreg_read, .writefn = pmxevtyper_write },
374 /* Unimplemented, RAZ/WI. XXX PMUSERENR */
375 { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
376 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
377 { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
378 .access = PL0_R | PL1_RW,
379 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
380 .resetvalue = 0,
381 .writefn = pmuserenr_write },
382 { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
383 .access = PL1_RW,
384 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
385 .resetvalue = 0,
386 .writefn = pmintenset_write },
387 { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
388 .access = PL1_RW,
389 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
390 .resetvalue = 0,
391 .writefn = pmintenclr_write },
2771db27
PM		 392 { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
393 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr),
394 .resetvalue = 0, },
e9aa6c21
PM		 395 REGINFO_SENTINEL
396};
397
c326b979
PM		 398static int teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
399{
400 value &= 1;
401 env->teecr = value;
402 return 0;
403}
404
405static int teehbr_read(CPUARMState *env, const ARMCPRegInfo *ri,
406 uint64_t *value)
407{
408 /* This is a helper function because the user access rights
409 * depend on the value of the TEECR.
410 */
411 if (arm_current_pl(env) == 0 && (env->teecr & 1)) {
412 return EXCP_UDEF;
413 }
414 *value = env->teehbr;
415 return 0;
416}
417
418static int teehbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
419 uint64_t value)
420{
421 if (arm_current_pl(env) == 0 && (env->teecr & 1)) {
422 return EXCP_UDEF;
423 }
424 env->teehbr = value;
425 return 0;
426}
427
428static const ARMCPRegInfo t2ee_cp_reginfo[] = {
429 { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
430 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
431 .resetvalue = 0,
432 .writefn = teecr_write },
433 { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
434 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
435 .resetvalue = 0,
436 .readfn = teehbr_read, .writefn = teehbr_write },
437 REGINFO_SENTINEL
438};
439
4d31c596
PM		 440static const ARMCPRegInfo v6k_cp_reginfo[] = {
441 { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
442 .access = PL0_RW,
443 .fieldoffset = offsetof(CPUARMState, cp15.c13_tls1),
444 .resetvalue = 0 },
445 { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
446 .access = PL0_R|PL1_W,
447 .fieldoffset = offsetof(CPUARMState, cp15.c13_tls2),
448 .resetvalue = 0 },
449 { .name = "TPIDRPRW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 4,
450 .access = PL1_RW,
451 .fieldoffset = offsetof(CPUARMState, cp15.c13_tls3),
452 .resetvalue = 0 },
453 REGINFO_SENTINEL
454};
455
6cc7a3ae
PM		 456static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
457 /* Dummy implementation: RAZ/WI the whole crn=14 space */
458 { .name = "GENERIC_TIMER", .cp = 15, .crn = 14,
459 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
460 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
461 REGINFO_SENTINEL
462};
463
4a501606
PM		 464static int par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
465{
466 if (arm_feature(env, ARM_FEATURE_V7)) {
467 env->cp15.c7_par = value & 0xfffff6ff;
468 } else {
469 env->cp15.c7_par = value & 0xfffff1ff;
470 }
471 return 0;
472}
473
474#ifndef CONFIG_USER_ONLY
475/* get_phys_addr() isn't present for user-mode-only targets */
476static int ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
477{
478 uint32_t phys_addr;
479 target_ulong page_size;
480 int prot;
481 int ret, is_user = ri->opc2 & 2;
482 int access_type = ri->opc2 & 1;
483
484 if (ri->opc2 & 4) {
485 /* Other states are only available with TrustZone */
486 return EXCP_UDEF;
487 }
488 ret = get_phys_addr(env, value, access_type, is_user,
489 &phys_addr, &prot, &page_size);
490 if (ret == 0) {
491 /* We do not set any attribute bits in the PAR */
492 if (page_size == (1 << 24)
493 && arm_feature(env, ARM_FEATURE_V7)) {
494 env->cp15.c7_par = (phys_addr & 0xff000000) | 1 << 1;
495 } else {
496 env->cp15.c7_par = phys_addr & 0xfffff000;
497 }
498 } else {
499 env->cp15.c7_par = ((ret & (10 << 1)) >> 5) |
500 ((ret & (12 << 1)) >> 6) |
501 ((ret & 0xf) << 1) | 1;
502 }
503 return 0;
504}
505#endif
506
507static const ARMCPRegInfo vapa_cp_reginfo[] = {
508 { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
509 .access = PL1_RW, .resetvalue = 0,
510 .fieldoffset = offsetof(CPUARMState, cp15.c7_par),
511 .writefn = par_write },
512#ifndef CONFIG_USER_ONLY
513 { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
514 .access = PL1_W, .writefn = ats_write },
515#endif
516 REGINFO_SENTINEL
517};
518
18032bec
PM		 519/* Return basic MPU access permission bits. */
520static uint32_t simple_mpu_ap_bits(uint32_t val)
521{
522 uint32_t ret;
523 uint32_t mask;
524 int i;
525 ret = 0;
526 mask = 3;
527 for (i = 0; i < 16; i += 2) {
528 ret |= (val >> i) & mask;
529 mask <<= 2;
530 }
531 return ret;
532}
533
534/* Pad basic MPU access permission bits to extended format. */
535static uint32_t extended_mpu_ap_bits(uint32_t val)
536{
537 uint32_t ret;
538 uint32_t mask;
539 int i;
540 ret = 0;
541 mask = 3;
542 for (i = 0; i < 16; i += 2) {
543 ret |= (val & mask) << i;
544 mask <<= 2;
545 }
546 return ret;
547}
548
549static int pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
550 uint64_t value)
551{
552 env->cp15.c5_data = extended_mpu_ap_bits(value);
553 return 0;
554}
555
556static int pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri,
557 uint64_t *value)
558{
559 *value = simple_mpu_ap_bits(env->cp15.c5_data);
560 return 0;
561}
562
563static int pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
564 uint64_t value)
565{
566 env->cp15.c5_insn = extended_mpu_ap_bits(value);
567 return 0;
568}
569
570static int pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri,
571 uint64_t *value)
572{
573 *value = simple_mpu_ap_bits(env->cp15.c5_insn);
574 return 0;
575}
576
06d76f31
PM		 577static int arm946_prbs_read(CPUARMState *env, const ARMCPRegInfo *ri,
578 uint64_t *value)
579{
580 if (ri->crm > 8) {
581 return EXCP_UDEF;
582 }
583 *value = env->cp15.c6_region[ri->crm];
584 return 0;
585}
586
587static int arm946_prbs_write(CPUARMState *env, const ARMCPRegInfo *ri,
588 uint64_t value)
589{
590 if (ri->crm > 8) {
591 return EXCP_UDEF;
592 }
593 env->cp15.c6_region[ri->crm] = value;
594 return 0;
595}
596
18032bec
PM		 597static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
598 { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
599 .access = PL1_RW,
600 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0,
601 .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, },
602 { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
603 .access = PL1_RW,
604 .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0,
605 .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, },
606 { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2,
607 .access = PL1_RW,
608 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
609 { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3,
610 .access = PL1_RW,
611 .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, },
ecce5c3c
PM		 612 { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
613 .access = PL1_RW,
614 .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, },
615 { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
616 .access = PL1_RW,
617 .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
06d76f31
PM		 618 /* Protection region base and size registers */
619 { .name = "946_PRBS", .cp = 15, .crn = 6, .crm = CP_ANY, .opc1 = 0,
620 .opc2 = CP_ANY, .access = PL1_RW,
621 .readfn = arm946_prbs_read, .writefn = arm946_prbs_write, },
18032bec
PM		 622 REGINFO_SENTINEL
623};
624
ecce5c3c
PM		 625static int vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
626 uint64_t value)
627{
628 value &= 7;
629 env->cp15.c2_control = value;
630 env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> value);
631 env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> value);
632 return 0;
633}
634
635static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
636{
637 env->cp15.c2_base_mask = 0xffffc000u;
638 env->cp15.c2_control = 0;
639 env->cp15.c2_mask = 0;
640}
641
18032bec
PM		 642static const ARMCPRegInfo vmsa_cp_reginfo[] = {
643 { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
644 .access = PL1_RW,
645 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
646 { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
647 .access = PL1_RW,
648 .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, },
ecce5c3c
PM		 649 { .name = "TTBR0", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
650 .access = PL1_RW,
651 .fieldoffset = offsetof(CPUARMState, cp15.c2_base0), .resetvalue = 0, },
652 { .name = "TTBR1", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
653 .access = PL1_RW,
654 .fieldoffset = offsetof(CPUARMState, cp15.c2_base0), .resetvalue = 0, },
655 { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
656 .access = PL1_RW, .writefn = vmsa_ttbcr_write,
657 .resetfn = vmsa_ttbcr_reset,
658 .fieldoffset = offsetof(CPUARMState, cp15.c2_control) },
06d76f31
PM		 659 { .name = "DFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
660 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_data),
661 .resetvalue = 0, },
18032bec
PM		 662 REGINFO_SENTINEL
663};
664
1047b9d7
PM		 665static int omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
666 uint64_t value)
667{
668 env->cp15.c15_ticonfig = value & 0xe7;
669 /* The OS_TYPE bit in this register changes the reported CPUID! */
670 env->cp15.c0_cpuid = (value & (1 << 5)) ?
671 ARM_CPUID_TI915T : ARM_CPUID_TI925T;
672 return 0;
673}
674
675static int omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,
676 uint64_t value)
677{
678 env->cp15.c15_threadid = value & 0xffff;
679 return 0;
680}
681
682static int omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
683 uint64_t value)
684{
685 /* Wait-for-interrupt (deprecated) */
686 cpu_interrupt(env, CPU_INTERRUPT_HALT);
687 return 0;
688}
689
c4804214
PM		 690static int omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
691 uint64_t value)
692{
693 /* On OMAP there are registers indicating the max/min index of dcache lines
694 * containing a dirty line; cache flush operations have to reset these.
695 */
696 env->cp15.c15_i_max = 0x000;
697 env->cp15.c15_i_min = 0xff0;
698 return 0;
699}
700
18032bec
PM		 701static const ARMCPRegInfo omap_cp_reginfo[] = {
702 { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
703 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,
704 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
1047b9d7
PM		 705 { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
706 .access = PL1_RW, .type = ARM_CP_NOP },
707 { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
708 .access = PL1_RW,
709 .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,
710 .writefn = omap_ticonfig_write },
711 { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,
712 .access = PL1_RW,
713 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },
714 { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,
715 .access = PL1_RW, .resetvalue = 0xff0,
716 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },
717 { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,
718 .access = PL1_RW,
719 .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,
720 .writefn = omap_threadid_write },
721 { .name = "TI925T_STATUS", .cp = 15, .crn = 15,
722 .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
723 .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
724 /* TODO: Peripheral port remap register:
725 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
726 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
727 * when MMU is off.
728 */
c4804214
PM		 729 { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
730 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, .type = ARM_CP_OVERRIDE,
731 .writefn = omap_cachemaint_write },
34f90529
PM		 732 { .name = "C9", .cp = 15, .crn = 9,
733 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
734 .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
1047b9d7
PM		 735 REGINFO_SENTINEL
736};
737
738static int xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
739 uint64_t value)
740{
741 value &= 0x3fff;
742 if (env->cp15.c15_cpar != value) {
743 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
744 tb_flush(env);
745 env->cp15.c15_cpar = value;
746 }
747 return 0;
748}
749
750static const ARMCPRegInfo xscale_cp_reginfo[] = {
751 { .name = "XSCALE_CPAR",
752 .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
753 .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
754 .writefn = xscale_cpar_write, },
2771db27
PM		 755 { .name = "XSCALE_AUXCR",
756 .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
757 .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
758 .resetvalue = 0, },
1047b9d7
PM		 759 REGINFO_SENTINEL
760};
761
762static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
763 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
764 * implementation of this implementation-defined space.
765 * Ideally this should eventually disappear in favour of actually
766 * implementing the correct behaviour for all cores.
767 */
768 { .name = "C15_IMPDEF", .cp = 15, .crn = 15,
769 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
770 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
18032bec
PM		 771 REGINFO_SENTINEL
772};
773
c4804214
PM		 774static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
775 /* Cache status: RAZ because we have no cache so it's always clean */
776 { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
777 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
778 REGINFO_SENTINEL
779};
780
781static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
782 /* We never have a a block transfer operation in progress */
783 { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
784 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
785 REGINFO_SENTINEL
786};
787
788static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
789 /* The cache test-and-clean instructions always return (1 << 30)
790 * to indicate that there are no dirty cache lines.
791 */
792 { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
793 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = (1 << 30) },
794 { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
795 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = (1 << 30) },
796 REGINFO_SENTINEL
797};
798
34f90529
PM		 799static const ARMCPRegInfo strongarm_cp_reginfo[] = {
800 /* Ignore ReadBuffer accesses */
801 { .name = "C9_READBUFFER", .cp = 15, .crn = 9,
802 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
803 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
804 .resetvalue = 0 },
805 REGINFO_SENTINEL
806};
807
2771db27
PM		 808static int sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
809{
810 env->cp15.c1_sys = value;
811 /* ??? Lots of these bits are not implemented. */
812 /* This may enable/disable the MMU, so do a TLB flush. */
813 tlb_flush(env, 1);
814 return 0;
815}
816
2ceb98c0
PM		 817void register_cp_regs_for_features(ARMCPU *cpu)
818{
819 /* Register all the coprocessor registers based on feature bits */
820 CPUARMState *env = &cpu->env;
821 if (arm_feature(env, ARM_FEATURE_M)) {
822 /* M profile has no coprocessor registers */
823 return;
824 }
825
e9aa6c21 826 define_arm_cp_regs(cpu, cp_reginfo);
7d57f408 827 if (arm_feature(env, ARM_FEATURE_V6)) {
8515a092
PM		 828 /* The ID registers all have impdef reset values */
829 ARMCPRegInfo v6_idregs[] = {
830 { .name = "ID_PFR0", .cp = 15, .crn = 0, .crm = 1,
831 .opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST,
832 .resetvalue = cpu->id_pfr0 },
833 { .name = "ID_PFR1", .cp = 15, .crn = 0, .crm = 1,
834 .opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST,
835 .resetvalue = cpu->id_pfr1 },
836 { .name = "ID_DFR0", .cp = 15, .crn = 0, .crm = 1,
837 .opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST,
838 .resetvalue = cpu->id_dfr0 },
839 { .name = "ID_AFR0", .cp = 15, .crn = 0, .crm = 1,
840 .opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST,
841 .resetvalue = cpu->id_afr0 },
842 { .name = "ID_MMFR0", .cp = 15, .crn = 0, .crm = 1,
843 .opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST,
844 .resetvalue = cpu->id_mmfr0 },
845 { .name = "ID_MMFR1", .cp = 15, .crn = 0, .crm = 1,
846 .opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST,
847 .resetvalue = cpu->id_mmfr1 },
848 { .name = "ID_MMFR2", .cp = 15, .crn = 0, .crm = 1,
849 .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
850 .resetvalue = cpu->id_mmfr2 },
851 { .name = "ID_MMFR3", .cp = 15, .crn = 0, .crm = 1,
852 .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
853 .resetvalue = cpu->id_mmfr3 },
854 { .name = "ID_ISAR0", .cp = 15, .crn = 0, .crm = 2,
855 .opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST,
856 .resetvalue = cpu->id_isar0 },
857 { .name = "ID_ISAR1", .cp = 15, .crn = 0, .crm = 2,
858 .opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST,
859 .resetvalue = cpu->id_isar1 },
860 { .name = "ID_ISAR2", .cp = 15, .crn = 0, .crm = 2,
861 .opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST,
862 .resetvalue = cpu->id_isar2 },
863 { .name = "ID_ISAR3", .cp = 15, .crn = 0, .crm = 2,
864 .opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST,
865 .resetvalue = cpu->id_isar3 },
866 { .name = "ID_ISAR4", .cp = 15, .crn = 0, .crm = 2,
867 .opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST,
868 .resetvalue = cpu->id_isar4 },
869 { .name = "ID_ISAR5", .cp = 15, .crn = 0, .crm = 2,
870 .opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST,
871 .resetvalue = cpu->id_isar5 },
872 /* 6..7 are as yet unallocated and must RAZ */
873 { .name = "ID_ISAR6", .cp = 15, .crn = 0, .crm = 2,
874 .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
875 .resetvalue = 0 },
876 { .name = "ID_ISAR7", .cp = 15, .crn = 0, .crm = 2,
877 .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
878 .resetvalue = 0 },
879 REGINFO_SENTINEL
880 };
881 define_arm_cp_regs(cpu, v6_idregs);
7d57f408
PM		 882 define_arm_cp_regs(cpu, v6_cp_reginfo);
883 } else {
884 define_arm_cp_regs(cpu, not_v6_cp_reginfo);
885 }
4d31c596
PM		 886 if (arm_feature(env, ARM_FEATURE_V6K)) {
887 define_arm_cp_regs(cpu, v6k_cp_reginfo);
888 }
e9aa6c21 889 if (arm_feature(env, ARM_FEATURE_V7)) {
200ac0ef
PM		 890 /* v7 performance monitor control register: same implementor
891 * field as main ID register, and we implement no event counters.
892 */
893 ARMCPRegInfo pmcr = {
894 .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
895 .access = PL0_RW, .resetvalue = cpu->midr & 0xff000000,
896 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
897 .readfn = pmreg_read, .writefn = pmcr_write
898 };
899 define_one_arm_cp_reg(cpu, &pmcr);
e9aa6c21 900 define_arm_cp_regs(cpu, v7_cp_reginfo);
7d57f408
PM		 901 } else {
902 define_arm_cp_regs(cpu, not_v7_cp_reginfo);
e9aa6c21 903 }
18032bec
PM		 904 if (arm_feature(env, ARM_FEATURE_MPU)) {
905 /* These are the MPU registers prior to PMSAv6. Any new
906 * PMSA core later than the ARM946 will require that we
907 * implement the PMSAv6 or PMSAv7 registers, which are
908 * completely different.
909 */
910 assert(!arm_feature(env, ARM_FEATURE_V6));
911 define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
912 } else {
913 define_arm_cp_regs(cpu, vmsa_cp_reginfo);
914 }
c326b979
PM		 915 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
916 define_arm_cp_regs(cpu, t2ee_cp_reginfo);
917 }
6cc7a3ae
PM		 918 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
919 define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
920 }
4a501606
PM		 921 if (arm_feature(env, ARM_FEATURE_VAPA)) {
922 define_arm_cp_regs(cpu, vapa_cp_reginfo);
923 }
c4804214
PM		 924 if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) {
925 define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo);
926 }
927 if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) {
928 define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo);
929 }
930 if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) {
931 define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo);
932 }
18032bec
PM		 933 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
934 define_arm_cp_regs(cpu, omap_cp_reginfo);
935 }
34f90529
PM		 936 if (arm_feature(env, ARM_FEATURE_STRONGARM)) {
937 define_arm_cp_regs(cpu, strongarm_cp_reginfo);
938 }
1047b9d7
PM		 939 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
940 define_arm_cp_regs(cpu, xscale_cp_reginfo);
941 }
942 if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
943 define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
944 }
2771db27
PM		 945 if (arm_feature(env, ARM_FEATURE_AUXCR)) {
946 ARMCPRegInfo auxcr = {
947 .name = "AUXCR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1,
948 .access = PL1_RW, .type = ARM_CP_CONST,
949 .resetvalue = cpu->reset_auxcr
950 };
951 define_one_arm_cp_reg(cpu, &auxcr);
952 }
953
954 /* Generic registers whose values depend on the implementation */
955 {
956 ARMCPRegInfo sctlr = {
957 .name = "SCTLR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
958 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_sys),
959 .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr
960 };
961 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
962 /* Normally we would always end the TB on an SCTLR write, but Linux
963 * arch/arm/mach-pxa/sleep.S expects two instructions following
964 * an MMU enable to execute from cache. Imitate this behaviour.
965 */
966 sctlr.type |= ARM_CP_SUPPRESS_TB_END;
967 }
968 define_one_arm_cp_reg(cpu, &sctlr);
969 }
2ceb98c0
PM		 970}
971
778c3a06 972ARMCPU *cpu_arm_init(const char *cpu_model)
40f137e1 973{
dec9c2d4 974 ARMCPU *cpu;
40f137e1 975 CPUARMState *env;
b26eefb6 976 static int inited = 0;
40f137e1 977
777dc784 978 if (!object_class_by_name(cpu_model)) {
aaed909a 979 return NULL;
777dc784
PM		 980 }
981 cpu = ARM_CPU(object_new(cpu_model));
dec9c2d4 982 env = &cpu->env;
777dc784 983 env->cpu_model_str = cpu_model;
581be094 984 arm_cpu_realize(cpu);
777dc784 985
f4fc247b 986 if (tcg_enabled() && !inited) {
b26eefb6
PB		 987 inited = 1;
988 arm_translate_init();
989 }
990
df90dadb 991 cpu_reset(CPU(cpu));
56aebc89
PB		 992 if (arm_feature(env, ARM_FEATURE_NEON)) {
993 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
994 51, "arm-neon.xml", 0);
995 } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
996 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
997 35, "arm-vfp3.xml", 0);
998 } else if (arm_feature(env, ARM_FEATURE_VFP)) {
999 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
1000 19, "arm-vfp.xml", 0);
1001 }
0bf46a40 1002 qemu_init_vcpu(env);
778c3a06 1003 return cpu;
40f137e1
PB		 1004}
1005
777dc784
PM		 1006typedef struct ARMCPUListState {
1007 fprintf_function cpu_fprintf;
1008 FILE *file;
1009} ARMCPUListState;
3371d272 1010
777dc784
PM		 1011/* Sort alphabetically by type name, except for "any". */
1012static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
5adb4839 1013{
777dc784
PM		 1014 ObjectClass *class_a = (ObjectClass *)a;
1015 ObjectClass *class_b = (ObjectClass *)b;
1016 const char *name_a, *name_b;
5adb4839 1017
777dc784
PM		 1018 name_a = object_class_get_name(class_a);
1019 name_b = object_class_get_name(class_b);
1020 if (strcmp(name_a, "any") == 0) {
1021 return 1;
1022 } else if (strcmp(name_b, "any") == 0) {
1023 return -1;
1024 } else {
1025 return strcmp(name_a, name_b);
5adb4839
PB		 1026 }
1027}
1028
777dc784 1029static void arm_cpu_list_entry(gpointer data, gpointer user_data)
40f137e1 1030{
777dc784
PM		 1031 ObjectClass *oc = data;
1032 ARMCPUListState *s = user_data;
3371d272 1033
777dc784
PM		 1034 (*s->cpu_fprintf)(s->file, " %s\n",
1035 object_class_get_name(oc));
1036}
1037
1038void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1039{
1040 ARMCPUListState s = {
1041 .file = f,
1042 .cpu_fprintf = cpu_fprintf,
1043 };
1044 GSList *list;
1045
1046 list = object_class_get_list(TYPE_ARM_CPU, false);
1047 list = g_slist_sort(list, arm_cpu_list_compare);
1048 (*cpu_fprintf)(f, "Available CPUs:\n");
1049 g_slist_foreach(list, arm_cpu_list_entry, &s);
1050 g_slist_free(list);
40f137e1
PB		 1051}
1052
4b6a83fb
PM		 1053void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
1054 const ARMCPRegInfo *r, void *opaque)
1055{
1056 /* Define implementations of coprocessor registers.
1057 * We store these in a hashtable because typically
1058 * there are less than 150 registers in a space which
1059 * is 16*16*16*8*8 = 262144 in size.
1060 * Wildcarding is supported for the crm, opc1 and opc2 fields.
1061 * If a register is defined twice then the second definition is
1062 * used, so this can be used to define some generic registers and
1063 * then override them with implementation specific variations.
1064 * At least one of the original and the second definition should
1065 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
1066 * against accidental use.
1067 */
1068 int crm, opc1, opc2;
1069 int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
1070 int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
1071 int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
1072 int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
1073 int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
1074 int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
1075 /* 64 bit registers have only CRm and Opc1 fields */
1076 assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
1077 /* Check that the register definition has enough info to handle
1078 * reads and writes if they are permitted.
1079 */
1080 if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
1081 if (r->access & PL3_R) {
1082 assert(r->fieldoffset || r->readfn);
1083 }
1084 if (r->access & PL3_W) {
1085 assert(r->fieldoffset || r->writefn);
1086 }
1087 }
1088 /* Bad type field probably means missing sentinel at end of reg list */
1089 assert(cptype_valid(r->type));
1090 for (crm = crmmin; crm <= crmmax; crm++) {
1091 for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
1092 for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
1093 uint32_t *key = g_new(uint32_t, 1);
1094 ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
1095 int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
1096 *key = ENCODE_CP_REG(r->cp, is64, r->crn, crm, opc1, opc2);
1097 r2->opaque = opaque;
1098 /* Make sure reginfo passed to helpers for wildcarded regs
1099 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
1100 */
1101 r2->crm = crm;
1102 r2->opc1 = opc1;
1103 r2->opc2 = opc2;
1104 /* Overriding of an existing definition must be explicitly
1105 * requested.
1106 */
1107 if (!(r->type & ARM_CP_OVERRIDE)) {
1108 ARMCPRegInfo *oldreg;
1109 oldreg = g_hash_table_lookup(cpu->cp_regs, key);
1110 if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
1111 fprintf(stderr, "Register redefined: cp=%d %d bit "
1112 "crn=%d crm=%d opc1=%d opc2=%d, "
1113 "was %s, now %s\n", r2->cp, 32 + 32 * is64,
1114 r2->crn, r2->crm, r2->opc1, r2->opc2,
1115 oldreg->name, r2->name);
1116 assert(0);
1117 }
1118 }
1119 g_hash_table_insert(cpu->cp_regs, key, r2);
1120 }
1121 }
1122 }
1123}
1124
1125void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
1126 const ARMCPRegInfo *regs, void *opaque)
1127{
1128 /* Define a whole list of registers */
1129 const ARMCPRegInfo *r;
1130 for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
1131 define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
1132 }
1133}
1134
1135const ARMCPRegInfo *get_arm_cp_reginfo(ARMCPU *cpu, uint32_t encoded_cp)
1136{
1137 return g_hash_table_lookup(cpu->cp_regs, &encoded_cp);
1138}
1139
1140int arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
1141 uint64_t value)
1142{
1143 /* Helper coprocessor write function for write-ignore registers */
1144 return 0;
1145}
1146
1147int arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value)
1148{
1149 /* Helper coprocessor write function for read-as-zero registers */
1150 *value = 0;
1151 return 0;
1152}
1153
0ecb72a5 1154static int bad_mode_switch(CPUARMState *env, int mode)
37064a8b
PM		 1155{
1156 /* Return true if it is not valid for us to switch to
1157 * this CPU mode (ie all the UNPREDICTABLE cases in
1158 * the ARM ARM CPSRWriteByInstr pseudocode).
1159 */
1160 switch (mode) {
1161 case ARM_CPU_MODE_USR:
1162 case ARM_CPU_MODE_SYS:
1163 case ARM_CPU_MODE_SVC:
1164 case ARM_CPU_MODE_ABT:
1165 case ARM_CPU_MODE_UND:
1166 case ARM_CPU_MODE_IRQ:
1167 case ARM_CPU_MODE_FIQ:
1168 return 0;
1169 default:
1170 return 1;
1171 }
1172}
1173
2f4a40e5
AZ		 1174uint32_t cpsr_read(CPUARMState *env)
1175{
1176 int ZF;
6fbe23d5
PB		 1177 ZF = (env->ZF == 0);
1178 return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
2f4a40e5
AZ		 1179 (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
1180 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
1181 | ((env->condexec_bits & 0xfc) << 8)
1182 | (env->GE << 16);
1183}
1184
1185void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
1186{
2f4a40e5 1187 if (mask & CPSR_NZCV) {
6fbe23d5
PB		 1188 env->ZF = (~val) & CPSR_Z;
1189 env->NF = val;
2f4a40e5
AZ		 1190 env->CF = (val >> 29) & 1;
1191 env->VF = (val << 3) & 0x80000000;
1192 }
1193 if (mask & CPSR_Q)
1194 env->QF = ((val & CPSR_Q) != 0);
1195 if (mask & CPSR_T)
1196 env->thumb = ((val & CPSR_T) != 0);
1197 if (mask & CPSR_IT_0_1) {
1198 env->condexec_bits &= ~3;
1199 env->condexec_bits |= (val >> 25) & 3;
1200 }
1201 if (mask & CPSR_IT_2_7) {
1202 env->condexec_bits &= 3;
1203 env->condexec_bits |= (val >> 8) & 0xfc;
1204 }
1205 if (mask & CPSR_GE) {
1206 env->GE = (val >> 16) & 0xf;
1207 }
1208
1209 if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
37064a8b
PM		 1210 if (bad_mode_switch(env, val & CPSR_M)) {
1211 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
1212 * We choose to ignore the attempt and leave the CPSR M field
1213 * untouched.
1214 */
1215 mask &= ~CPSR_M;
1216 } else {
1217 switch_mode(env, val & CPSR_M);
1218 }
2f4a40e5
AZ		 1219 }
1220 mask &= ~CACHED_CPSR_BITS;
1221 env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
1222}
1223
b26eefb6
PB		 1224/* Sign/zero extend */
1225uint32_t HELPER(sxtb16)(uint32_t x)
1226{
1227 uint32_t res;
1228 res = (uint16_t)(int8_t)x;
1229 res |= (uint32_t)(int8_t)(x >> 16) << 16;
1230 return res;
1231}
1232
1233uint32_t HELPER(uxtb16)(uint32_t x)
1234{
1235 uint32_t res;
1236 res = (uint16_t)(uint8_t)x;
1237 res |= (uint32_t)(uint8_t)(x >> 16) << 16;
1238 return res;
1239}
1240
f51bbbfe
PB		 1241uint32_t HELPER(clz)(uint32_t x)
1242{
7bbcb0af 1243 return clz32(x);
f51bbbfe
PB		 1244}
1245
3670669c
PB		 1246int32_t HELPER(sdiv)(int32_t num, int32_t den)
1247{
1248 if (den == 0)
1249 return 0;
686eeb93
AJ		 1250 if (num == INT_MIN && den == -1)
1251 return INT_MIN;
3670669c
PB		 1252 return num / den;
1253}
1254
1255uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
1256{
1257 if (den == 0)
1258 return 0;
1259 return num / den;
1260}
1261
1262uint32_t HELPER(rbit)(uint32_t x)
1263{
1264 x = ((x & 0xff000000) >> 24)
1265 | ((x & 0x00ff0000) >> 8)
1266 | ((x & 0x0000ff00) << 8)
1267 | ((x & 0x000000ff) << 24);
1268 x = ((x & 0xf0f0f0f0) >> 4)
1269 | ((x & 0x0f0f0f0f) << 4);
1270 x = ((x & 0x88888888) >> 3)
1271 | ((x & 0x44444444) >> 1)
1272 | ((x & 0x22222222) << 1)
1273 | ((x & 0x11111111) << 3);
1274 return x;
1275}
1276
ad69471c
PB		 1277uint32_t HELPER(abs)(uint32_t x)
1278{
1279 return ((int32_t)x < 0) ? -x : x;
1280}
1281
5fafdf24 1282#if defined(CONFIG_USER_ONLY)
b5ff1b31 1283
0ecb72a5 1284void do_interrupt (CPUARMState *env)
b5ff1b31
FB		 1285{
1286 env->exception_index = -1;
1287}
1288
0ecb72a5 1289int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
97b348e7 1290 int mmu_idx)
b5ff1b31
FB		 1291{
1292 if (rw == 2) {
1293 env->exception_index = EXCP_PREFETCH_ABORT;
1294 env->cp15.c6_insn = address;
1295 } else {
1296 env->exception_index = EXCP_DATA_ABORT;
1297 env->cp15.c6_data = address;
1298 }
1299 return 1;
1300}
1301
0ecb72a5 1302void HELPER(set_cp15)(CPUARMState *env, uint32_t insn, uint32_t val)
b5ff1b31
FB		 1303{
1304 cpu_abort(env, "cp15 insn %08x\n", insn);
1305}
1306
0ecb72a5 1307uint32_t HELPER(get_cp15)(CPUARMState *env, uint32_t insn)
b5ff1b31
FB		 1308{
1309 cpu_abort(env, "cp15 insn %08x\n", insn);
b5ff1b31
FB		 1310}
1311
9ee6e8bb 1312/* These should probably raise undefined insn exceptions. */
0ecb72a5 1313void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
9ee6e8bb
PB		 1314{
1315 cpu_abort(env, "v7m_mrs %d\n", reg);
1316}
1317
0ecb72a5 1318uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
9ee6e8bb
PB		 1319{
1320 cpu_abort(env, "v7m_mrs %d\n", reg);
1321 return 0;
1322}
1323
0ecb72a5 1324void switch_mode(CPUARMState *env, int mode)
b5ff1b31
FB		 1325{
1326 if (mode != ARM_CPU_MODE_USR)
1327 cpu_abort(env, "Tried to switch out of user mode\n");
1328}
1329
0ecb72a5 1330void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
9ee6e8bb
PB		 1331{
1332 cpu_abort(env, "banked r13 write\n");
1333}
1334
0ecb72a5 1335uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
9ee6e8bb
PB		 1336{
1337 cpu_abort(env, "banked r13 read\n");
1338 return 0;
1339}
1340
b5ff1b31
FB		 1341#else
1342
1343/* Map CPU modes onto saved register banks. */
0ecb72a5 1344static inline int bank_number(CPUARMState *env, int mode)
b5ff1b31
FB		 1345{
1346 switch (mode) {
1347 case ARM_CPU_MODE_USR:
1348 case ARM_CPU_MODE_SYS:
1349 return 0;
1350 case ARM_CPU_MODE_SVC:
1351 return 1;
1352 case ARM_CPU_MODE_ABT:
1353 return 2;
1354 case ARM_CPU_MODE_UND:
1355 return 3;
1356 case ARM_CPU_MODE_IRQ:
1357 return 4;
1358 case ARM_CPU_MODE_FIQ:
1359 return 5;
1360 }
1b9e01c1 1361 cpu_abort(env, "Bad mode %x\n", mode);
b5ff1b31
FB		 1362 return -1;
1363}
1364
0ecb72a5 1365void switch_mode(CPUARMState *env, int mode)
b5ff1b31
FB		 1366{
1367 int old_mode;
1368 int i;
1369
1370 old_mode = env->uncached_cpsr & CPSR_M;
1371 if (mode == old_mode)
1372 return;
1373
1374 if (old_mode == ARM_CPU_MODE_FIQ) {
1375 memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
8637c67f 1376 memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
b5ff1b31
FB		 1377 } else if (mode == ARM_CPU_MODE_FIQ) {
1378 memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
8637c67f 1379 memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
b5ff1b31
FB		 1380 }
1381
1b9e01c1 1382 i = bank_number(env, old_mode);
b5ff1b31
FB		 1383 env->banked_r13[i] = env->regs[13];
1384 env->banked_r14[i] = env->regs[14];
1385 env->banked_spsr[i] = env->spsr;
1386
1b9e01c1 1387 i = bank_number(env, mode);
b5ff1b31
FB		 1388 env->regs[13] = env->banked_r13[i];
1389 env->regs[14] = env->banked_r14[i];
1390 env->spsr = env->banked_spsr[i];
1391}
1392
9ee6e8bb
PB		 1393static void v7m_push(CPUARMState *env, uint32_t val)
1394{
1395 env->regs[13] -= 4;
1396 stl_phys(env->regs[13], val);
1397}
1398
1399static uint32_t v7m_pop(CPUARMState *env)
1400{
1401 uint32_t val;
1402 val = ldl_phys(env->regs[13]);
1403 env->regs[13] += 4;
1404 return val;
1405}
1406
1407/* Switch to V7M main or process stack pointer. */
1408static void switch_v7m_sp(CPUARMState *env, int process)
1409{
1410 uint32_t tmp;
1411 if (env->v7m.current_sp != process) {
1412 tmp = env->v7m.other_sp;
1413 env->v7m.other_sp = env->regs[13];
1414 env->regs[13] = tmp;
1415 env->v7m.current_sp = process;
1416 }
1417}
1418
1419static void do_v7m_exception_exit(CPUARMState *env)
1420{
1421 uint32_t type;
1422 uint32_t xpsr;
1423
1424 type = env->regs[15];
1425 if (env->v7m.exception != 0)
983fe826 1426 armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
9ee6e8bb
PB		 1427
1428 /* Switch to the target stack. */
1429 switch_v7m_sp(env, (type & 4) != 0);
1430 /* Pop registers. */
1431 env->regs[0] = v7m_pop(env);
1432 env->regs[1] = v7m_pop(env);
1433 env->regs[2] = v7m_pop(env);
1434 env->regs[3] = v7m_pop(env);
1435 env->regs[12] = v7m_pop(env);
1436 env->regs[14] = v7m_pop(env);
1437 env->regs[15] = v7m_pop(env);
1438 xpsr = v7m_pop(env);
1439 xpsr_write(env, xpsr, 0xfffffdff);
1440 /* Undo stack alignment. */
1441 if (xpsr & 0x200)
1442 env->regs[13] |= 4;
1443 /* ??? The exception return type specifies Thread/Handler mode. However
1444 this is also implied by the xPSR value. Not sure what to do
1445 if there is a mismatch. */
1446 /* ??? Likewise for mismatches between the CONTROL register and the stack
1447 pointer. */
1448}
1449
2b3ea315 1450static void do_interrupt_v7m(CPUARMState *env)
9ee6e8bb
PB		 1451{
1452 uint32_t xpsr = xpsr_read(env);
1453 uint32_t lr;
1454 uint32_t addr;
1455
1456 lr = 0xfffffff1;
1457 if (env->v7m.current_sp)
1458 lr |= 4;
1459 if (env->v7m.exception == 0)
1460 lr |= 8;
1461
1462 /* For exceptions we just mark as pending on the NVIC, and let that
1463 handle it. */
1464 /* TODO: Need to escalate if the current priority is higher than the
1465 one we're raising. */
1466 switch (env->exception_index) {
1467 case EXCP_UDEF:
983fe826 1468 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
9ee6e8bb
PB		 1469 return;
1470 case EXCP_SWI:
1471 env->regs[15] += 2;
983fe826 1472 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
9ee6e8bb
PB		 1473 return;
1474 case EXCP_PREFETCH_ABORT:
1475 case EXCP_DATA_ABORT:
983fe826 1476 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
9ee6e8bb
PB		 1477 return;
1478 case EXCP_BKPT:
2ad207d4
PB		 1479 if (semihosting_enabled) {
1480 int nr;
d8fd2954 1481 nr = arm_lduw_code(env->regs[15], env->bswap_code) & 0xff;
2ad207d4
PB		 1482 if (nr == 0xab) {
1483 env->regs[15] += 2;
1484 env->regs[0] = do_arm_semihosting(env);
1485 return;
1486 }
1487 }
983fe826 1488 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
9ee6e8bb
PB		 1489 return;
1490 case EXCP_IRQ:
983fe826 1491 env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
9ee6e8bb
PB		 1492 break;
1493 case EXCP_EXCEPTION_EXIT:
1494 do_v7m_exception_exit(env);
1495 return;
1496 default:
1497 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
1498 return; /* Never happens. Keep compiler happy. */
1499 }
1500
1501 /* Align stack pointer. */
1502 /* ??? Should only do this if Configuration Control Register
1503 STACKALIGN bit is set. */
1504 if (env->regs[13] & 4) {
ab19b0ec 1505 env->regs[13] -= 4;
9ee6e8bb
PB		 1506 xpsr |= 0x200;
1507 }
6c95676b 1508 /* Switch to the handler mode. */
9ee6e8bb
PB		 1509 v7m_push(env, xpsr);
1510 v7m_push(env, env->regs[15]);
1511 v7m_push(env, env->regs[14]);
1512 v7m_push(env, env->regs[12]);
1513 v7m_push(env, env->regs[3]);
1514 v7m_push(env, env->regs[2]);
1515 v7m_push(env, env->regs[1]);
1516 v7m_push(env, env->regs[0]);
1517 switch_v7m_sp(env, 0);
c98d174c
PM		 1518 /* Clear IT bits */
1519 env->condexec_bits = 0;
9ee6e8bb
PB		 1520 env->regs[14] = lr;
1521 addr = ldl_phys(env->v7m.vecbase + env->v7m.exception * 4);
1522 env->regs[15] = addr & 0xfffffffe;
1523 env->thumb = addr & 1;
1524}
1525
b5ff1b31
FB		 1526/* Handle a CPU exception. */
1527void do_interrupt(CPUARMState *env)
1528{
1529 uint32_t addr;
1530 uint32_t mask;
1531 int new_mode;
1532 uint32_t offset;
1533
9ee6e8bb
PB		 1534 if (IS_M(env)) {
1535 do_interrupt_v7m(env);
1536 return;
1537 }
b5ff1b31
FB		 1538 /* TODO: Vectored interrupt controller. */
1539 switch (env->exception_index) {
1540 case EXCP_UDEF:
1541 new_mode = ARM_CPU_MODE_UND;
1542 addr = 0x04;
1543 mask = CPSR_I;
1544 if (env->thumb)
1545 offset = 2;
1546 else
1547 offset = 4;
1548 break;
1549 case EXCP_SWI:
8e71621f
PB		 1550 if (semihosting_enabled) {
1551 /* Check for semihosting interrupt. */
1552 if (env->thumb) {
d8fd2954 1553 mask = arm_lduw_code(env->regs[15] - 2, env->bswap_code) & 0xff;
8e71621f 1554 } else {
d8fd2954
PB		 1555 mask = arm_ldl_code(env->regs[15] - 4, env->bswap_code)
1556 & 0xffffff;
8e71621f
PB		 1557 }
1558 /* Only intercept calls from privileged modes, to provide some
1559 semblance of security. */
1560 if (((mask == 0x123456 && !env->thumb)
1561 || (mask == 0xab && env->thumb))
1562 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
1563 env->regs[0] = do_arm_semihosting(env);
1564 return;
1565 }
1566 }
b5ff1b31
FB		 1567 new_mode = ARM_CPU_MODE_SVC;
1568 addr = 0x08;
1569 mask = CPSR_I;
601d70b9 1570 /* The PC already points to the next instruction. */
b5ff1b31
FB		 1571 offset = 0;
1572 break;
06c949e6 1573 case EXCP_BKPT:
9ee6e8bb 1574 /* See if this is a semihosting syscall. */
2ad207d4 1575 if (env->thumb && semihosting_enabled) {
d8fd2954 1576 mask = arm_lduw_code(env->regs[15], env->bswap_code) & 0xff;
9ee6e8bb
PB		 1577 if (mask == 0xab
1578 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
1579 env->regs[15] += 2;
1580 env->regs[0] = do_arm_semihosting(env);
1581 return;
1582 }
1583 }
81c05daf 1584 env->cp15.c5_insn = 2;
9ee6e8bb
PB		 1585 /* Fall through to prefetch abort. */
1586 case EXCP_PREFETCH_ABORT:
b5ff1b31
FB		 1587 new_mode = ARM_CPU_MODE_ABT;
1588 addr = 0x0c;
1589 mask = CPSR_A | CPSR_I;
1590 offset = 4;
1591 break;
1592 case EXCP_DATA_ABORT:
1593 new_mode = ARM_CPU_MODE_ABT;
1594 addr = 0x10;
1595 mask = CPSR_A | CPSR_I;
1596 offset = 8;
1597 break;
1598 case EXCP_IRQ:
1599 new_mode = ARM_CPU_MODE_IRQ;
1600 addr = 0x18;
1601 /* Disable IRQ and imprecise data aborts. */
1602 mask = CPSR_A | CPSR_I;
1603 offset = 4;
1604 break;
1605 case EXCP_FIQ:
1606 new_mode = ARM_CPU_MODE_FIQ;
1607 addr = 0x1c;
1608 /* Disable FIQ, IRQ and imprecise data aborts. */
1609 mask = CPSR_A | CPSR_I | CPSR_F;
1610 offset = 4;
1611 break;
1612 default:
1613 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
1614 return; /* Never happens. Keep compiler happy. */
1615 }
1616 /* High vectors. */
1617 if (env->cp15.c1_sys & (1 << 13)) {
1618 addr += 0xffff0000;
1619 }
1620 switch_mode (env, new_mode);
1621 env->spsr = cpsr_read(env);
9ee6e8bb
PB		 1622 /* Clear IT bits. */
1623 env->condexec_bits = 0;
30a8cac1 1624 /* Switch to the new mode, and to the correct instruction set. */
6d7e6326 1625 env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
b5ff1b31 1626 env->uncached_cpsr |= mask;
be5e7a76
DES		 1627 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
1628 * and we should just guard the thumb mode on V4 */
1629 if (arm_feature(env, ARM_FEATURE_V4T)) {
1630 env->thumb = (env->cp15.c1_sys & (1 << 30)) != 0;
1631 }
b5ff1b31
FB		 1632 env->regs[14] = env->regs[15] + offset;
1633 env->regs[15] = addr;
1634 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1635}
1636
1637/* Check section/page access permissions.
1638 Returns the page protection flags, or zero if the access is not
1639 permitted. */
0ecb72a5 1640static inline int check_ap(CPUARMState *env, int ap, int domain_prot,
dd4ebc2e 1641 int access_type, int is_user)
b5ff1b31 1642{
9ee6e8bb
PB		 1643 int prot_ro;
1644
dd4ebc2e 1645 if (domain_prot == 3) {
b5ff1b31 1646 return PAGE_READ | PAGE_WRITE;
dd4ebc2e 1647 }
b5ff1b31 1648
9ee6e8bb
PB		 1649 if (access_type == 1)
1650 prot_ro = 0;
1651 else
1652 prot_ro = PAGE_READ;
1653
b5ff1b31
FB		 1654 switch (ap) {
1655 case 0:
78600320 1656 if (access_type == 1)
b5ff1b31
FB		 1657 return 0;
1658 switch ((env->cp15.c1_sys >> 8) & 3) {
1659 case 1:
1660 return is_user ? 0 : PAGE_READ;
1661 case 2:
1662 return PAGE_READ;
1663 default:
1664 return 0;
1665 }
1666 case 1:
1667 return is_user ? 0 : PAGE_READ | PAGE_WRITE;
1668 case 2:
1669 if (is_user)
9ee6e8bb 1670 return prot_ro;
b5ff1b31
FB		 1671 else
1672 return PAGE_READ | PAGE_WRITE;
1673 case 3:
1674 return PAGE_READ | PAGE_WRITE;
d4934d18 1675 case 4: /* Reserved. */
9ee6e8bb
PB		 1676 return 0;
1677 case 5:
1678 return is_user ? 0 : prot_ro;
1679 case 6:
1680 return prot_ro;
d4934d18 1681 case 7:
0ab06d83 1682 if (!arm_feature (env, ARM_FEATURE_V6K))
d4934d18
PB		 1683 return 0;
1684 return prot_ro;
b5ff1b31
FB		 1685 default:
1686 abort();
1687 }
1688}
1689
0ecb72a5 1690static uint32_t get_level1_table_address(CPUARMState *env, uint32_t address)
b2fa1797
PB		 1691{
1692 uint32_t table;
1693
1694 if (address & env->cp15.c2_mask)
1695 table = env->cp15.c2_base1 & 0xffffc000;
1696 else
1697 table = env->cp15.c2_base0 & env->cp15.c2_base_mask;
1698
1699 table |= (address >> 18) & 0x3ffc;
1700 return table;
1701}
1702
0ecb72a5 1703static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type,
d4c430a8
PB		 1704 int is_user, uint32_t *phys_ptr, int *prot,
1705 target_ulong *page_size)
b5ff1b31
FB		 1706{
1707 int code;
1708 uint32_t table;
1709 uint32_t desc;
1710 int type;
1711 int ap;
1712 int domain;
dd4ebc2e 1713 int domain_prot;
b5ff1b31
FB		 1714 uint32_t phys_addr;
1715
9ee6e8bb
PB		 1716 /* Pagetable walk. */
1717 /* Lookup l1 descriptor. */
b2fa1797 1718 table = get_level1_table_address(env, address);
9ee6e8bb
PB		 1719 desc = ldl_phys(table);
1720 type = (desc & 3);
dd4ebc2e
JCD		 1721 domain = (desc >> 5) & 0x0f;
1722 domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
9ee6e8bb 1723 if (type == 0) {
601d70b9 1724 /* Section translation fault. */
9ee6e8bb
PB		 1725 code = 5;
1726 goto do_fault;
1727 }
dd4ebc2e 1728 if (domain_prot == 0 || domain_prot == 2) {
9ee6e8bb
PB		 1729 if (type == 2)
1730 code = 9; /* Section domain fault. */
1731 else
1732 code = 11; /* Page domain fault. */
1733 goto do_fault;
1734 }
1735 if (type == 2) {
1736 /* 1Mb section. */
1737 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
1738 ap = (desc >> 10) & 3;
1739 code = 13;
d4c430a8 1740 *page_size = 1024 * 1024;
9ee6e8bb
PB		 1741 } else {
1742 /* Lookup l2 entry. */
1743 if (type == 1) {
1744 /* Coarse pagetable. */
1745 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
1746 } else {
1747 /* Fine pagetable. */
1748 table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
1749 }
1750 desc = ldl_phys(table);
1751 switch (desc & 3) {
1752 case 0: /* Page translation fault. */
1753 code = 7;
1754 goto do_fault;
1755 case 1: /* 64k page. */
1756 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
1757 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
d4c430a8 1758 *page_size = 0x10000;
ce819861 1759 break;
9ee6e8bb
PB		 1760 case 2: /* 4k page. */
1761 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
1762 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
d4c430a8 1763 *page_size = 0x1000;
ce819861 1764 break;
9ee6e8bb
PB		 1765 case 3: /* 1k page. */
1766 if (type == 1) {
1767 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1768 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
1769 } else {
1770 /* Page translation fault. */
1771 code = 7;
1772 goto do_fault;
1773 }
1774 } else {
1775 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
1776 }
1777 ap = (desc >> 4) & 3;
d4c430a8 1778 *page_size = 0x400;
ce819861
PB		 1779 break;
1780 default:
9ee6e8bb
PB		 1781 /* Never happens, but compiler isn't smart enough to tell. */
1782 abort();
ce819861 1783 }
9ee6e8bb
PB		 1784 code = 15;
1785 }
dd4ebc2e 1786 *prot = check_ap(env, ap, domain_prot, access_type, is_user);
9ee6e8bb
PB		 1787 if (!*prot) {
1788 /* Access permission fault. */
1789 goto do_fault;
1790 }
3ad493fc 1791 *prot |= PAGE_EXEC;
9ee6e8bb
PB		 1792 *phys_ptr = phys_addr;
1793 return 0;
1794do_fault:
1795 return code | (domain << 4);
1796}
1797
0ecb72a5 1798static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type,
d4c430a8
PB		 1799 int is_user, uint32_t *phys_ptr, int *prot,
1800 target_ulong *page_size)
9ee6e8bb
PB		 1801{
1802 int code;
1803 uint32_t table;
1804 uint32_t desc;
1805 uint32_t xn;
1806 int type;
1807 int ap;
1808 int domain;
dd4ebc2e 1809 int domain_prot;
9ee6e8bb
PB		 1810 uint32_t phys_addr;
1811
1812 /* Pagetable walk. */
1813 /* Lookup l1 descriptor. */
b2fa1797 1814 table = get_level1_table_address(env, address);
9ee6e8bb
PB		 1815 desc = ldl_phys(table);
1816 type = (desc & 3);
1817 if (type == 0) {
601d70b9 1818 /* Section translation fault. */
9ee6e8bb
PB		 1819 code = 5;
1820 domain = 0;
1821 goto do_fault;
1822 } else if (type == 2 && (desc & (1 << 18))) {
1823 /* Supersection. */
1824 domain = 0;
b5ff1b31 1825 } else {
9ee6e8bb 1826 /* Section or page. */
dd4ebc2e 1827 domain = (desc >> 5) & 0x0f;
9ee6e8bb 1828 }
dd4ebc2e
JCD		 1829 domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
1830 if (domain_prot == 0 || domain_prot == 2) {
9ee6e8bb
PB		 1831 if (type == 2)
1832 code = 9; /* Section domain fault. */
1833 else
1834 code = 11; /* Page domain fault. */
1835 goto do_fault;
1836 }
1837 if (type == 2) {
1838 if (desc & (1 << 18)) {
1839 /* Supersection. */
1840 phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
d4c430a8 1841 *page_size = 0x1000000;
b5ff1b31 1842 } else {
9ee6e8bb
PB		 1843 /* Section. */
1844 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
d4c430a8 1845 *page_size = 0x100000;
b5ff1b31 1846 }
9ee6e8bb
PB		 1847 ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
1848 xn = desc & (1 << 4);
1849 code = 13;
1850 } else {
1851 /* Lookup l2 entry. */
1852 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
1853 desc = ldl_phys(table);
1854 ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
1855 switch (desc & 3) {
1856 case 0: /* Page translation fault. */
1857 code = 7;
b5ff1b31 1858 goto do_fault;
9ee6e8bb
PB		 1859 case 1: /* 64k page. */
1860 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
1861 xn = desc & (1 << 15);
d4c430a8 1862 *page_size = 0x10000;
9ee6e8bb
PB		 1863 break;
1864 case 2: case 3: /* 4k page. */
1865 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
1866 xn = desc & 1;
d4c430a8 1867 *page_size = 0x1000;
9ee6e8bb
PB		 1868 break;
1869 default:
1870 /* Never happens, but compiler isn't smart enough to tell. */
1871 abort();
b5ff1b31 1872 }
9ee6e8bb
PB		 1873 code = 15;
1874 }
dd4ebc2e 1875 if (domain_prot == 3) {
c0034328
JR		 1876 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
1877 } else {
1878 if (xn && access_type == 2)
1879 goto do_fault;
9ee6e8bb 1880
c0034328
JR		 1881 /* The simplified model uses AP[0] as an access control bit. */
1882 if ((env->cp15.c1_sys & (1 << 29)) && (ap & 1) == 0) {
1883 /* Access flag fault. */
1884 code = (code == 15) ? 6 : 3;
1885 goto do_fault;
1886 }
dd4ebc2e 1887 *prot = check_ap(env, ap, domain_prot, access_type, is_user);
c0034328
JR		 1888 if (!*prot) {
1889 /* Access permission fault. */
1890 goto do_fault;
1891 }
1892 if (!xn) {
1893 *prot |= PAGE_EXEC;
1894 }
3ad493fc 1895 }
9ee6e8bb 1896 *phys_ptr = phys_addr;
b5ff1b31
FB		 1897 return 0;
1898do_fault:
1899 return code | (domain << 4);
1900}
1901
0ecb72a5 1902static int get_phys_addr_mpu(CPUARMState *env, uint32_t address, int access_type,
9ee6e8bb
PB		 1903 int is_user, uint32_t *phys_ptr, int *prot)
1904{
1905 int n;
1906 uint32_t mask;
1907 uint32_t base;
1908
1909 *phys_ptr = address;
1910 for (n = 7; n >= 0; n--) {
1911 base = env->cp15.c6_region[n];
1912 if ((base & 1) == 0)
1913 continue;
1914 mask = 1 << ((base >> 1) & 0x1f);
1915 /* Keep this shift separate from the above to avoid an
1916 (undefined) << 32. */
1917 mask = (mask << 1) - 1;
1918 if (((base ^ address) & ~mask) == 0)
1919 break;
1920 }
1921 if (n < 0)
1922 return 2;
1923
1924 if (access_type == 2) {
1925 mask = env->cp15.c5_insn;
1926 } else {
1927 mask = env->cp15.c5_data;
1928 }
1929 mask = (mask >> (n * 4)) & 0xf;
1930 switch (mask) {
1931 case 0:
1932 return 1;
1933 case 1:
1934 if (is_user)
1935 return 1;
1936 *prot = PAGE_READ | PAGE_WRITE;
1937 break;
1938 case 2:
1939 *prot = PAGE_READ;
1940 if (!is_user)
1941 *prot |= PAGE_WRITE;
1942 break;
1943 case 3:
1944 *prot = PAGE_READ | PAGE_WRITE;
1945 break;
1946 case 5:
1947 if (is_user)
1948 return 1;
1949 *prot = PAGE_READ;
1950 break;
1951 case 6:
1952 *prot = PAGE_READ;
1953 break;
1954 default:
1955 /* Bad permission. */
1956 return 1;
1957 }
3ad493fc 1958 *prot |= PAGE_EXEC;
9ee6e8bb
PB		 1959 return 0;
1960}
1961
0ecb72a5 1962static inline int get_phys_addr(CPUARMState *env, uint32_t address,
9ee6e8bb 1963 int access_type, int is_user,
d4c430a8
PB		 1964 uint32_t *phys_ptr, int *prot,
1965 target_ulong *page_size)
9ee6e8bb
PB		 1966{
1967 /* Fast Context Switch Extension. */
1968 if (address < 0x02000000)
1969 address += env->cp15.c13_fcse;
1970
1971 if ((env->cp15.c1_sys & 1) == 0) {
1972 /* MMU/MPU disabled. */
1973 *phys_ptr = address;
3ad493fc 1974 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
d4c430a8 1975 *page_size = TARGET_PAGE_SIZE;
9ee6e8bb
PB		 1976 return 0;
1977 } else if (arm_feature(env, ARM_FEATURE_MPU)) {
d4c430a8 1978 *page_size = TARGET_PAGE_SIZE;
9ee6e8bb
PB		 1979 return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr,
1980 prot);
1981 } else if (env->cp15.c1_sys & (1 << 23)) {
1982 return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr,
d4c430a8 1983 prot, page_size);
9ee6e8bb
PB		 1984 } else {
1985 return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr,
d4c430a8 1986 prot, page_size);
9ee6e8bb
PB		 1987 }
1988}
1989
0ecb72a5 1990int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address,
97b348e7 1991 int access_type, int mmu_idx)
b5ff1b31
FB		 1992{
1993 uint32_t phys_addr;
d4c430a8 1994 target_ulong page_size;
b5ff1b31 1995 int prot;
6ebbf390 1996 int ret, is_user;
b5ff1b31 1997
6ebbf390 1998 is_user = mmu_idx == MMU_USER_IDX;
d4c430a8
PB		 1999 ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot,
2000 &page_size);
b5ff1b31
FB		 2001 if (ret == 0) {
2002 /* Map a single [sub]page. */
2003 phys_addr &= ~(uint32_t)0x3ff;
2004 address &= ~(uint32_t)0x3ff;
3ad493fc 2005 tlb_set_page (env, address, phys_addr, prot, mmu_idx, page_size);
d4c430a8 2006 return 0;
b5ff1b31
FB		 2007 }
2008
2009 if (access_type == 2) {
2010 env->cp15.c5_insn = ret;
2011 env->cp15.c6_insn = address;
2012 env->exception_index = EXCP_PREFETCH_ABORT;
2013 } else {
2014 env->cp15.c5_data = ret;
9ee6e8bb
PB		 2015 if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6))
2016 env->cp15.c5_data |= (1 << 11);
b5ff1b31
FB		 2017 env->cp15.c6_data = address;
2018 env->exception_index = EXCP_DATA_ABORT;
2019 }
2020 return 1;
2021}
2022
0ecb72a5 2023target_phys_addr_t cpu_get_phys_page_debug(CPUARMState *env, target_ulong addr)
b5ff1b31
FB		 2024{
2025 uint32_t phys_addr;
d4c430a8 2026 target_ulong page_size;
b5ff1b31
FB		 2027 int prot;
2028 int ret;
2029
d4c430a8 2030 ret = get_phys_addr(env, addr, 0, 0, &phys_addr, &prot, &page_size);
b5ff1b31
FB		 2031
2032 if (ret != 0)
2033 return -1;
2034
2035 return phys_addr;
2036}
2037
0ecb72a5 2038void HELPER(set_cp15)(CPUARMState *env, uint32_t insn, uint32_t val)
b5ff1b31 2039{
9ee6e8bb
PB		 2040 int op1;
2041 int op2;
2042 int crm;
b5ff1b31 2043
9ee6e8bb 2044 op1 = (insn >> 21) & 7;
b5ff1b31 2045 op2 = (insn >> 5) & 7;
ce819861 2046 crm = insn & 0xf;
b5ff1b31 2047 switch ((insn >> 16) & 0xf) {
9ee6e8bb 2048 case 0:
9ee6e8bb 2049 /* ID codes. */
610c3c8a
AZ		 2050 if (arm_feature(env, ARM_FEATURE_XSCALE))
2051 break;
c3d2689d
AZ		 2052 if (arm_feature(env, ARM_FEATURE_OMAPCP))
2053 break;
a49ea279
PB		 2054 if (arm_feature(env, ARM_FEATURE_V7)
2055 && op1 == 2 && crm == 0 && op2 == 0) {
2056 env->cp15.c0_cssel = val & 0xf;
2057 break;
2058 }
b5ff1b31 2059 goto bad_reg;
b5ff1b31
FB		 2060 case 4: /* Reserved. */
2061 goto bad_reg;
b5ff1b31
FB		 2062 case 12: /* Reserved. */
2063 goto bad_reg;
b5ff1b31
FB		 2064 }
2065 return;
2066bad_reg:
2067 /* ??? For debugging only. Should raise illegal instruction exception. */
9ee6e8bb
PB		 2068 cpu_abort(env, "Unimplemented cp15 register write (c%d, c%d, {%d, %d})\n",
2069 (insn >> 16) & 0xf, crm, op1, op2);
b5ff1b31
FB		 2070}
2071
0ecb72a5 2072uint32_t HELPER(get_cp15)(CPUARMState *env, uint32_t insn)
b5ff1b31 2073{
9ee6e8bb
PB		 2074 int op1;
2075 int op2;
2076 int crm;
b5ff1b31 2077
9ee6e8bb 2078 op1 = (insn >> 21) & 7;
b5ff1b31 2079 op2 = (insn >> 5) & 7;
c3d2689d 2080 crm = insn & 0xf;
b5ff1b31
FB		 2081 switch ((insn >> 16) & 0xf) {
2082 case 0: /* ID codes. */
9ee6e8bb
PB		 2083 switch (op1) {
2084 case 0:
2085 switch (crm) {
2086 case 0:
2087 switch (op2) {
2088 case 0: /* Device ID. */
2089 return env->cp15.c0_cpuid;
2090 case 1: /* Cache Type. */
2091 return env->cp15.c0_cachetype;
2092 case 2: /* TCM status. */
2093 return 0;
2094 case 3: /* TLB type register. */
2095 return 0; /* No lockable TLB entries. */
607b4b08
PM		 2096 case 5: /* MPIDR */
2097 /* The MPIDR was standardised in v7; prior to
2098 * this it was implemented only in the 11MPCore.
2099 * For all other pre-v7 cores it does not exist.
2100 */
2101 if (arm_feature(env, ARM_FEATURE_V7) ||
2102 ARM_CPUID(env) == ARM_CPUID_ARM11MPCORE) {
2103 int mpidr = env->cpu_index;
2104 /* We don't support setting cluster ID ([8..11])
2105 * so these bits always RAZ.
2106 */
2107 if (arm_feature(env, ARM_FEATURE_V7MP)) {
2108 mpidr |= (1 << 31);
2109 /* Cores which are uniprocessor (non-coherent)
2110 * but still implement the MP extensions set
2111 * bit 30. (For instance, A9UP.) However we do
2112 * not currently model any of those cores.
2113 */
2114 }
2115 return mpidr;
10055562 2116 }
607b4b08 2117 /* otherwise fall through to the unimplemented-reg case */
9ee6e8bb
PB		 2118 default:
2119 goto bad_reg;
2120 }
9ee6e8bb
PB		 2121 case 3: case 4: case 5: case 6: case 7:
2122 return 0;
2123 default:
2124 goto bad_reg;
2125 }
2126 case 1:
2127 /* These registers aren't documented on arm11 cores. However
2128 Linux looks at them anyway. */
2129 if (!arm_feature(env, ARM_FEATURE_V6))
2130 goto bad_reg;
2131 if (crm != 0)
2132 goto bad_reg;
a49ea279
PB		 2133 if (!arm_feature(env, ARM_FEATURE_V7))
2134 return 0;
2135
2136 switch (op2) {
2137 case 0:
2138 return env->cp15.c0_ccsid[env->cp15.c0_cssel];
2139 case 1:
2140 return env->cp15.c0_clid;
2141 case 7:
2142 return 0;
2143 }
2144 goto bad_reg;
2145 case 2:
2146 if (op2 != 0 || crm != 0)
610c3c8a 2147 goto bad_reg;
a49ea279 2148 return env->cp15.c0_cssel;
9ee6e8bb
PB		 2149 default:
2150 goto bad_reg;
b5ff1b31 2151 }
b5ff1b31
FB		 2152 case 4: /* Reserved. */
2153 goto bad_reg;
b5ff1b31
FB		 2154 case 11: /* TCM DMA control. */
2155 case 12: /* Reserved. */
2156 goto bad_reg;
b5ff1b31
FB		 2157 }
2158bad_reg:
2159 /* ??? For debugging only. Should raise illegal instruction exception. */
9ee6e8bb
PB		 2160 cpu_abort(env, "Unimplemented cp15 register read (c%d, c%d, {%d, %d})\n",
2161 (insn >> 16) & 0xf, crm, op1, op2);
b5ff1b31
FB		 2162 return 0;
2163}
2164
0ecb72a5 2165void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
9ee6e8bb 2166{
39ea3d4e
PM		 2167 if ((env->uncached_cpsr & CPSR_M) == mode) {
2168 env->regs[13] = val;
2169 } else {
1b9e01c1 2170 env->banked_r13[bank_number(env, mode)] = val;
39ea3d4e 2171 }
9ee6e8bb
PB		 2172}
2173
0ecb72a5 2174uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
9ee6e8bb 2175{
39ea3d4e
PM		 2176 if ((env->uncached_cpsr & CPSR_M) == mode) {
2177 return env->regs[13];
2178 } else {
1b9e01c1 2179 return env->banked_r13[bank_number(env, mode)];
39ea3d4e 2180 }
9ee6e8bb
PB		 2181}
2182
0ecb72a5 2183uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
9ee6e8bb
PB		 2184{
2185 switch (reg) {
2186 case 0: /* APSR */
2187 return xpsr_read(env) & 0xf8000000;
2188 case 1: /* IAPSR */
2189 return xpsr_read(env) & 0xf80001ff;
2190 case 2: /* EAPSR */
2191 return xpsr_read(env) & 0xff00fc00;
2192 case 3: /* xPSR */
2193 return xpsr_read(env) & 0xff00fdff;
2194 case 5: /* IPSR */
2195 return xpsr_read(env) & 0x000001ff;
2196 case 6: /* EPSR */
2197 return xpsr_read(env) & 0x0700fc00;
2198 case 7: /* IEPSR */
2199 return xpsr_read(env) & 0x0700edff;
2200 case 8: /* MSP */
2201 return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
2202 case 9: /* PSP */
2203 return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
2204 case 16: /* PRIMASK */
2205 return (env->uncached_cpsr & CPSR_I) != 0;
82845826
SH		 2206 case 17: /* BASEPRI */
2207 case 18: /* BASEPRI_MAX */
9ee6e8bb 2208 return env->v7m.basepri;
82845826
SH		 2209 case 19: /* FAULTMASK */
2210 return (env->uncached_cpsr & CPSR_F) != 0;
9ee6e8bb
PB		 2211 case 20: /* CONTROL */
2212 return env->v7m.control;
2213 default:
2214 /* ??? For debugging only. */
2215 cpu_abort(env, "Unimplemented system register read (%d)\n", reg);
2216 return 0;
2217 }
2218}
2219
0ecb72a5 2220void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
9ee6e8bb
PB		 2221{
2222 switch (reg) {
2223 case 0: /* APSR */
2224 xpsr_write(env, val, 0xf8000000);
2225 break;
2226 case 1: /* IAPSR */
2227 xpsr_write(env, val, 0xf8000000);
2228 break;
2229 case 2: /* EAPSR */
2230 xpsr_write(env, val, 0xfe00fc00);
2231 break;
2232 case 3: /* xPSR */
2233 xpsr_write(env, val, 0xfe00fc00);
2234 break;
2235 case 5: /* IPSR */
2236 /* IPSR bits are readonly. */
2237 break;
2238 case 6: /* EPSR */
2239 xpsr_write(env, val, 0x0600fc00);
2240 break;
2241 case 7: /* IEPSR */
2242 xpsr_write(env, val, 0x0600fc00);
2243 break;
2244 case 8: /* MSP */
2245 if (env->v7m.current_sp)
2246 env->v7m.other_sp = val;
2247 else
2248 env->regs[13] = val;
2249 break;
2250 case 9: /* PSP */
2251 if (env->v7m.current_sp)
2252 env->regs[13] = val;
2253 else
2254 env->v7m.other_sp = val;
2255 break;
2256 case 16: /* PRIMASK */
2257 if (val & 1)
2258 env->uncached_cpsr |= CPSR_I;
2259 else
2260 env->uncached_cpsr &= ~CPSR_I;
2261 break;
82845826 2262 case 17: /* BASEPRI */
9ee6e8bb
PB		 2263 env->v7m.basepri = val & 0xff;
2264 break;
82845826 2265 case 18: /* BASEPRI_MAX */
9ee6e8bb
PB		 2266 val &= 0xff;
2267 if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
2268 env->v7m.basepri = val;
2269 break;
82845826
SH		 2270 case 19: /* FAULTMASK */
2271 if (val & 1)
2272 env->uncached_cpsr |= CPSR_F;
2273 else
2274 env->uncached_cpsr &= ~CPSR_F;
2275 break;
9ee6e8bb
PB		 2276 case 20: /* CONTROL */
2277 env->v7m.control = val & 3;
2278 switch_v7m_sp(env, (val & 2) != 0);
2279 break;
2280 default:
2281 /* ??? For debugging only. */
2282 cpu_abort(env, "Unimplemented system register write (%d)\n", reg);
2283 return;
2284 }
2285}
2286
b5ff1b31 2287#endif
6ddbc6e4
PB		 2288
2289/* Note that signed overflow is undefined in C. The following routines are
2290 careful to use unsigned types where modulo arithmetic is required.
2291 Failure to do so _will_ break on newer gcc. */
2292
2293/* Signed saturating arithmetic. */
2294
1654b2d6 2295/* Perform 16-bit signed saturating addition. */
6ddbc6e4
PB		 2296static inline uint16_t add16_sat(uint16_t a, uint16_t b)
2297{
2298 uint16_t res;
2299
2300 res = a + b;
2301 if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
2302 if (a & 0x8000)
2303 res = 0x8000;
2304 else
2305 res = 0x7fff;
2306 }
2307 return res;
2308}
2309
1654b2d6 2310/* Perform 8-bit signed saturating addition. */
6ddbc6e4
PB		 2311static inline uint8_t add8_sat(uint8_t a, uint8_t b)
2312{
2313 uint8_t res;
2314
2315 res = a + b;
2316 if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
2317 if (a & 0x80)
2318 res = 0x80;
2319 else
2320 res = 0x7f;
2321 }
2322 return res;
2323}
2324
1654b2d6 2325/* Perform 16-bit signed saturating subtraction. */
6ddbc6e4
PB		 2326static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
2327{
2328 uint16_t res;
2329
2330 res = a - b;
2331 if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
2332 if (a & 0x8000)
2333 res = 0x8000;
2334 else
2335 res = 0x7fff;
2336 }
2337 return res;
2338}
2339
1654b2d6 2340/* Perform 8-bit signed saturating subtraction. */
6ddbc6e4
PB		 2341static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
2342{
2343 uint8_t res;
2344
2345 res = a - b;
2346 if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
2347 if (a & 0x80)
2348 res = 0x80;
2349 else
2350 res = 0x7f;
2351 }
2352 return res;
2353}
2354
2355#define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
2356#define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
2357#define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
2358#define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
2359#define PFX q
2360
2361#include "op_addsub.h"
2362
2363/* Unsigned saturating arithmetic. */
460a09c1 2364static inline uint16_t add16_usat(uint16_t a, uint16_t b)
6ddbc6e4
PB		 2365{
2366 uint16_t res;
2367 res = a + b;
2368 if (res < a)
2369 res = 0xffff;
2370 return res;
2371}
2372
460a09c1 2373static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
6ddbc6e4 2374{
4c4fd3f8 2375 if (a > b)
6ddbc6e4
PB		 2376 return a - b;
2377 else
2378 return 0;
2379}
2380
2381static inline uint8_t add8_usat(uint8_t a, uint8_t b)
2382{
2383 uint8_t res;
2384 res = a + b;
2385 if (res < a)
2386 res = 0xff;
2387 return res;
2388}
2389
2390static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
2391{
4c4fd3f8 2392 if (a > b)
6ddbc6e4
PB		 2393 return a - b;
2394 else
2395 return 0;
2396}
2397
2398#define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
2399#define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
2400#define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
2401#define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
2402#define PFX uq
2403
2404#include "op_addsub.h"
2405
2406/* Signed modulo arithmetic. */
2407#define SARITH16(a, b, n, op) do { \
2408 int32_t sum; \
db6e2e65 2409 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
6ddbc6e4
PB		 2410 RESULT(sum, n, 16); \
2411 if (sum >= 0) \
2412 ge |= 3 << (n * 2); \
2413 } while(0)
2414
2415#define SARITH8(a, b, n, op) do { \
2416 int32_t sum; \
db6e2e65 2417 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
6ddbc6e4
PB		 2418 RESULT(sum, n, 8); \
2419 if (sum >= 0) \
2420 ge |= 1 << n; \
2421 } while(0)
2422
2423
2424#define ADD16(a, b, n) SARITH16(a, b, n, +)
2425#define SUB16(a, b, n) SARITH16(a, b, n, -)
2426#define ADD8(a, b, n) SARITH8(a, b, n, +)
2427#define SUB8(a, b, n) SARITH8(a, b, n, -)
2428#define PFX s
2429#define ARITH_GE
2430
2431#include "op_addsub.h"
2432
2433/* Unsigned modulo arithmetic. */
2434#define ADD16(a, b, n) do { \
2435 uint32_t sum; \
2436 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
2437 RESULT(sum, n, 16); \
a87aa10b 2438 if ((sum >> 16) == 1) \
6ddbc6e4
PB		 2439 ge |= 3 << (n * 2); \
2440 } while(0)
2441
2442#define ADD8(a, b, n) do { \
2443 uint32_t sum; \
2444 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
2445 RESULT(sum, n, 8); \
a87aa10b
AZ		 2446 if ((sum >> 8) == 1) \
2447 ge |= 1 << n; \
6ddbc6e4
PB		 2448 } while(0)
2449
2450#define SUB16(a, b, n) do { \
2451 uint32_t sum; \
2452 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
2453 RESULT(sum, n, 16); \
2454 if ((sum >> 16) == 0) \
2455 ge |= 3 << (n * 2); \
2456 } while(0)
2457
2458#define SUB8(a, b, n) do { \
2459 uint32_t sum; \
2460 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
2461 RESULT(sum, n, 8); \
2462 if ((sum >> 8) == 0) \
a87aa10b 2463 ge |= 1 << n; \
6ddbc6e4
PB		 2464 } while(0)
2465
2466#define PFX u
2467#define ARITH_GE
2468
2469#include "op_addsub.h"
2470
2471/* Halved signed arithmetic. */
2472#define ADD16(a, b, n) \
2473 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
2474#define SUB16(a, b, n) \
2475 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
2476#define ADD8(a, b, n) \
2477 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
2478#define SUB8(a, b, n) \
2479 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
2480#define PFX sh
2481
2482#include "op_addsub.h"
2483
2484/* Halved unsigned arithmetic. */
2485#define ADD16(a, b, n) \
2486 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2487#define SUB16(a, b, n) \
2488 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2489#define ADD8(a, b, n) \
2490 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2491#define SUB8(a, b, n) \
2492 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2493#define PFX uh
2494
2495#include "op_addsub.h"
2496
2497static inline uint8_t do_usad(uint8_t a, uint8_t b)
2498{
2499 if (a > b)
2500 return a - b;
2501 else
2502 return b - a;
2503}
2504
2505/* Unsigned sum of absolute byte differences. */
2506uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
2507{
2508 uint32_t sum;
2509 sum = do_usad(a, b);
2510 sum += do_usad(a >> 8, b >> 8);
2511 sum += do_usad(a >> 16, b >>16);
2512 sum += do_usad(a >> 24, b >> 24);
2513 return sum;
2514}
2515
2516/* For ARMv6 SEL instruction. */
2517uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
2518{
2519 uint32_t mask;
2520
2521 mask = 0;
2522 if (flags & 1)
2523 mask |= 0xff;
2524 if (flags & 2)
2525 mask |= 0xff00;
2526 if (flags & 4)
2527 mask |= 0xff0000;
2528 if (flags & 8)
2529 mask |= 0xff000000;
2530 return (a & mask) | (b & ~mask);
2531}
2532
5e3f878a
PB		 2533uint32_t HELPER(logicq_cc)(uint64_t val)
2534{
2535 return (val >> 32) | (val != 0);
2536}
4373f3ce
PB		 2537
2538/* VFP support. We follow the convention used for VFP instrunctions:
2539 Single precition routines have a "s" suffix, double precision a
2540 "d" suffix. */
2541
2542/* Convert host exception flags to vfp form. */
2543static inline int vfp_exceptbits_from_host(int host_bits)
2544{
2545 int target_bits = 0;
2546
2547 if (host_bits & float_flag_invalid)
2548 target_bits |= 1;
2549 if (host_bits & float_flag_divbyzero)
2550 target_bits |= 2;
2551 if (host_bits & float_flag_overflow)
2552 target_bits |= 4;
36802b6b 2553 if (host_bits & (float_flag_underflow | float_flag_output_denormal))
4373f3ce
PB		 2554 target_bits |= 8;
2555 if (host_bits & float_flag_inexact)
2556 target_bits |= 0x10;
cecd8504
PM		 2557 if (host_bits & float_flag_input_denormal)
2558 target_bits |= 0x80;
4373f3ce
PB		 2559 return target_bits;
2560}
2561
0ecb72a5 2562uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
4373f3ce
PB		 2563{
2564 int i;
2565 uint32_t fpscr;
2566
2567 fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
2568 | (env->vfp.vec_len << 16)
2569 | (env->vfp.vec_stride << 20);
2570 i = get_float_exception_flags(&env->vfp.fp_status);
3a492f3a 2571 i |= get_float_exception_flags(&env->vfp.standard_fp_status);
4373f3ce
PB		 2572 fpscr |= vfp_exceptbits_from_host(i);
2573 return fpscr;
2574}
2575
0ecb72a5 2576uint32_t vfp_get_fpscr(CPUARMState *env)
01653295
PM		 2577{
2578 return HELPER(vfp_get_fpscr)(env);
2579}
2580
4373f3ce
PB		 2581/* Convert vfp exception flags to target form. */
2582static inline int vfp_exceptbits_to_host(int target_bits)
2583{
2584 int host_bits = 0;
2585
2586 if (target_bits & 1)
2587 host_bits |= float_flag_invalid;
2588 if (target_bits & 2)
2589 host_bits |= float_flag_divbyzero;
2590 if (target_bits & 4)
2591 host_bits |= float_flag_overflow;
2592 if (target_bits & 8)
2593 host_bits |= float_flag_underflow;
2594 if (target_bits & 0x10)
2595 host_bits |= float_flag_inexact;
cecd8504
PM		 2596 if (target_bits & 0x80)
2597 host_bits |= float_flag_input_denormal;
4373f3ce
PB		 2598 return host_bits;
2599}
2600
0ecb72a5 2601void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
4373f3ce
PB		 2602{
2603 int i;
2604 uint32_t changed;
2605
2606 changed = env->vfp.xregs[ARM_VFP_FPSCR];
2607 env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
2608 env->vfp.vec_len = (val >> 16) & 7;
2609 env->vfp.vec_stride = (val >> 20) & 3;
2610
2611 changed ^= val;
2612 if (changed & (3 << 22)) {
2613 i = (val >> 22) & 3;
2614 switch (i) {
2615 case 0:
2616 i = float_round_nearest_even;
2617 break;
2618 case 1:
2619 i = float_round_up;
2620 break;
2621 case 2:
2622 i = float_round_down;
2623 break;
2624 case 3:
2625 i = float_round_to_zero;
2626 break;
2627 }
2628 set_float_rounding_mode(i, &env->vfp.fp_status);
2629 }
cecd8504 2630 if (changed & (1 << 24)) {
fe76d976 2631 set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
cecd8504
PM		 2632 set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
2633 }
5c7908ed
PB		 2634 if (changed & (1 << 25))
2635 set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
4373f3ce 2636
b12c390b 2637 i = vfp_exceptbits_to_host(val);
4373f3ce 2638 set_float_exception_flags(i, &env->vfp.fp_status);
3a492f3a 2639 set_float_exception_flags(0, &env->vfp.standard_fp_status);
4373f3ce
PB		 2640}
2641
0ecb72a5 2642void vfp_set_fpscr(CPUARMState *env, uint32_t val)
01653295
PM		 2643{
2644 HELPER(vfp_set_fpscr)(env, val);
2645}
2646
4373f3ce
PB		 2647#define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
2648
2649#define VFP_BINOP(name) \
ae1857ec 2650float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
4373f3ce 2651{ \
ae1857ec
PM		 2652 float_status *fpst = fpstp; \
2653 return float32_ ## name(a, b, fpst); \
4373f3ce 2654} \
ae1857ec 2655float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
4373f3ce 2656{ \
ae1857ec
PM		 2657 float_status *fpst = fpstp; \
2658 return float64_ ## name(a, b, fpst); \
4373f3ce
PB		 2659}
2660VFP_BINOP(add)
2661VFP_BINOP(sub)
2662VFP_BINOP(mul)
2663VFP_BINOP(div)
2664#undef VFP_BINOP
2665
2666float32 VFP_HELPER(neg, s)(float32 a)
2667{
2668 return float32_chs(a);
2669}
2670
2671float64 VFP_HELPER(neg, d)(float64 a)
2672{
66230e0d 2673 return float64_chs(a);
4373f3ce
PB		 2674}
2675
2676float32 VFP_HELPER(abs, s)(float32 a)
2677{
2678 return float32_abs(a);
2679}
2680
2681float64 VFP_HELPER(abs, d)(float64 a)
2682{
66230e0d 2683 return float64_abs(a);
4373f3ce
PB		 2684}
2685
0ecb72a5 2686float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
4373f3ce
PB		 2687{
2688 return float32_sqrt(a, &env->vfp.fp_status);
2689}
2690
0ecb72a5 2691float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
4373f3ce
PB		 2692{
2693 return float64_sqrt(a, &env->vfp.fp_status);
2694}
2695
2696/* XXX: check quiet/signaling case */
2697#define DO_VFP_cmp(p, type) \
0ecb72a5 2698void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
4373f3ce
PB		 2699{ \
2700 uint32_t flags; \
2701 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
2702 case 0: flags = 0x6; break; \
2703 case -1: flags = 0x8; break; \
2704 case 1: flags = 0x2; break; \
2705 default: case 2: flags = 0x3; break; \
2706 } \
2707 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2708 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2709} \
0ecb72a5 2710void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
4373f3ce
PB		 2711{ \
2712 uint32_t flags; \
2713 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
2714 case 0: flags = 0x6; break; \
2715 case -1: flags = 0x8; break; \
2716 case 1: flags = 0x2; break; \
2717 default: case 2: flags = 0x3; break; \
2718 } \
2719 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2720 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2721}
2722DO_VFP_cmp(s, float32)
2723DO_VFP_cmp(d, float64)
2724#undef DO_VFP_cmp
2725
5500b06c 2726/* Integer to float and float to integer conversions */
4373f3ce 2727
5500b06c
PM		 2728#define CONV_ITOF(name, fsz, sign) \
2729 float##fsz HELPER(name)(uint32_t x, void *fpstp) \
2730{ \
2731 float_status *fpst = fpstp; \
85836979 2732 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
4373f3ce
PB		 2733}
2734
5500b06c
PM		 2735#define CONV_FTOI(name, fsz, sign, round) \
2736uint32_t HELPER(name)(float##fsz x, void *fpstp) \
2737{ \
2738 float_status *fpst = fpstp; \
2739 if (float##fsz##_is_any_nan(x)) { \
2740 float_raise(float_flag_invalid, fpst); \
2741 return 0; \
2742 } \
2743 return float##fsz##_to_##sign##int32##round(x, fpst); \
4373f3ce
PB		 2744}
2745
5500b06c
PM		 2746#define FLOAT_CONVS(name, p, fsz, sign) \
2747CONV_ITOF(vfp_##name##to##p, fsz, sign) \
2748CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
2749CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
4373f3ce 2750
5500b06c
PM		 2751FLOAT_CONVS(si, s, 32, )
2752FLOAT_CONVS(si, d, 64, )
2753FLOAT_CONVS(ui, s, 32, u)
2754FLOAT_CONVS(ui, d, 64, u)
4373f3ce 2755
5500b06c
PM		 2756#undef CONV_ITOF
2757#undef CONV_FTOI
2758#undef FLOAT_CONVS
4373f3ce
PB		 2759
2760/* floating point conversion */
0ecb72a5 2761float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
4373f3ce 2762{
2d627737
PM		 2763 float64 r = float32_to_float64(x, &env->vfp.fp_status);
2764 /* ARM requires that S<->D conversion of any kind of NaN generates
2765 * a quiet NaN by forcing the most significant frac bit to 1.
2766 */
2767 return float64_maybe_silence_nan(r);
4373f3ce
PB		 2768}
2769
0ecb72a5 2770float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
4373f3ce 2771{
2d627737
PM		 2772 float32 r = float64_to_float32(x, &env->vfp.fp_status);
2773 /* ARM requires that S<->D conversion of any kind of NaN generates
2774 * a quiet NaN by forcing the most significant frac bit to 1.
2775 */
2776 return float32_maybe_silence_nan(r);
4373f3ce
PB		 2777}
2778
2779/* VFP3 fixed point conversion. */
622465e1 2780#define VFP_CONV_FIX(name, p, fsz, itype, sign) \
5500b06c
PM		 2781float##fsz HELPER(vfp_##name##to##p)(uint##fsz##_t x, uint32_t shift, \
2782 void *fpstp) \
4373f3ce 2783{ \
5500b06c 2784 float_status *fpst = fpstp; \
622465e1 2785 float##fsz tmp; \
5500b06c
PM		 2786 tmp = sign##int32_to_##float##fsz((itype##_t)x, fpst); \
2787 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
4373f3ce 2788} \
5500b06c
PM		 2789uint##fsz##_t HELPER(vfp_to##name##p)(float##fsz x, uint32_t shift, \
2790 void *fpstp) \
4373f3ce 2791{ \
5500b06c 2792 float_status *fpst = fpstp; \
622465e1
PM		 2793 float##fsz tmp; \
2794 if (float##fsz##_is_any_nan(x)) { \
5500b06c 2795 float_raise(float_flag_invalid, fpst); \
622465e1 2796 return 0; \
09d9487f 2797 } \
5500b06c
PM		 2798 tmp = float##fsz##_scalbn(x, shift, fpst); \
2799 return float##fsz##_to_##itype##_round_to_zero(tmp, fpst); \
622465e1
PM		 2800}
2801
2802VFP_CONV_FIX(sh, d, 64, int16, )
2803VFP_CONV_FIX(sl, d, 64, int32, )
2804VFP_CONV_FIX(uh, d, 64, uint16, u)
2805VFP_CONV_FIX(ul, d, 64, uint32, u)
2806VFP_CONV_FIX(sh, s, 32, int16, )
2807VFP_CONV_FIX(sl, s, 32, int32, )
2808VFP_CONV_FIX(uh, s, 32, uint16, u)
2809VFP_CONV_FIX(ul, s, 32, uint32, u)
4373f3ce
PB		 2810#undef VFP_CONV_FIX
2811
60011498 2812/* Half precision conversions. */
0ecb72a5 2813static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s)
60011498 2814{
60011498 2815 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
fb91678d
PM		 2816 float32 r = float16_to_float32(make_float16(a), ieee, s);
2817 if (ieee) {
2818 return float32_maybe_silence_nan(r);
2819 }
2820 return r;
60011498
PB		 2821}
2822
0ecb72a5 2823static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s)
60011498 2824{
60011498 2825 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
fb91678d
PM		 2826 float16 r = float32_to_float16(a, ieee, s);
2827 if (ieee) {
2828 r = float16_maybe_silence_nan(r);
2829 }
2830 return float16_val(r);
60011498
PB		 2831}
2832
0ecb72a5 2833float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
2d981da7
PM		 2834{
2835 return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
2836}
2837
0ecb72a5 2838uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
2d981da7
PM		 2839{
2840 return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
2841}
2842
0ecb72a5 2843float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
2d981da7
PM		 2844{
2845 return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
2846}
2847
0ecb72a5 2848uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
2d981da7
PM		 2849{
2850 return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
2851}
2852
dda3ec49 2853#define float32_two make_float32(0x40000000)
6aae3df1
PM		 2854#define float32_three make_float32(0x40400000)
2855#define float32_one_point_five make_float32(0x3fc00000)
dda3ec49 2856
0ecb72a5 2857float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env)
4373f3ce 2858{
dda3ec49
PM		 2859 float_status *s = &env->vfp.standard_fp_status;
2860 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
2861 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
43fe9bdb
PM		 2862 if (!(float32_is_zero(a) || float32_is_zero(b))) {
2863 float_raise(float_flag_input_denormal, s);
2864 }
dda3ec49
PM		 2865 return float32_two;
2866 }
2867 return float32_sub(float32_two, float32_mul(a, b, s), s);
4373f3ce
PB		 2868}
2869
0ecb72a5 2870float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
4373f3ce 2871{
71826966 2872 float_status *s = &env->vfp.standard_fp_status;
9ea62f57
PM		 2873 float32 product;
2874 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
2875 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
43fe9bdb
PM		 2876 if (!(float32_is_zero(a) || float32_is_zero(b))) {
2877 float_raise(float_flag_input_denormal, s);
2878 }
6aae3df1 2879 return float32_one_point_five;
9ea62f57 2880 }
6aae3df1
PM		 2881 product = float32_mul(a, b, s);
2882 return float32_div(float32_sub(float32_three, product, s), float32_two, s);
4373f3ce
PB		 2883}
2884
8f8e3aa4
PB		 2885/* NEON helpers. */
2886
56bf4fe2
CL		 2887/* Constants 256 and 512 are used in some helpers; we avoid relying on
2888 * int->float conversions at run-time. */
2889#define float64_256 make_float64(0x4070000000000000LL)
2890#define float64_512 make_float64(0x4080000000000000LL)
2891
fe0e4872
CL		 2892/* The algorithm that must be used to calculate the estimate
2893 * is specified by the ARM ARM.
2894 */
0ecb72a5 2895static float64 recip_estimate(float64 a, CPUARMState *env)
fe0e4872 2896{
1146a817
PM		 2897 /* These calculations mustn't set any fp exception flags,
2898 * so we use a local copy of the fp_status.
2899 */
2900 float_status dummy_status = env->vfp.standard_fp_status;
2901 float_status *s = &dummy_status;
fe0e4872
CL		 2902 /* q = (int)(a * 512.0) */
2903 float64 q = float64_mul(float64_512, a, s);
2904 int64_t q_int = float64_to_int64_round_to_zero(q, s);
2905
2906 /* r = 1.0 / (((double)q + 0.5) / 512.0) */
2907 q = int64_to_float64(q_int, s);
2908 q = float64_add(q, float64_half, s);
2909 q = float64_div(q, float64_512, s);
2910 q = float64_div(float64_one, q, s);
2911
2912 /* s = (int)(256.0 * r + 0.5) */
2913 q = float64_mul(q, float64_256, s);
2914 q = float64_add(q, float64_half, s);
2915 q_int = float64_to_int64_round_to_zero(q, s);
2916
2917 /* return (double)s / 256.0 */
2918 return float64_div(int64_to_float64(q_int, s), float64_256, s);
2919}
2920
0ecb72a5 2921float32 HELPER(recpe_f32)(float32 a, CPUARMState *env)
4373f3ce 2922{
fe0e4872
CL		 2923 float_status *s = &env->vfp.standard_fp_status;
2924 float64 f64;
2925 uint32_t val32 = float32_val(a);
2926
2927 int result_exp;
2928 int a_exp = (val32 & 0x7f800000) >> 23;
2929 int sign = val32 & 0x80000000;
2930
2931 if (float32_is_any_nan(a)) {
2932 if (float32_is_signaling_nan(a)) {
2933 float_raise(float_flag_invalid, s);
2934 }
2935 return float32_default_nan;
2936 } else if (float32_is_infinity(a)) {
2937 return float32_set_sign(float32_zero, float32_is_neg(a));
2938 } else if (float32_is_zero_or_denormal(a)) {
43fe9bdb
PM		 2939 if (!float32_is_zero(a)) {
2940 float_raise(float_flag_input_denormal, s);
2941 }
fe0e4872
CL		 2942 float_raise(float_flag_divbyzero, s);
2943 return float32_set_sign(float32_infinity, float32_is_neg(a));
2944 } else if (a_exp >= 253) {
2945 float_raise(float_flag_underflow, s);
2946 return float32_set_sign(float32_zero, float32_is_neg(a));
2947 }
2948
2949 f64 = make_float64((0x3feULL << 52)
2950 | ((int64_t)(val32 & 0x7fffff) << 29));
2951
2952 result_exp = 253 - a_exp;
2953
2954 f64 = recip_estimate(f64, env);
2955
2956 val32 = sign
2957 | ((result_exp & 0xff) << 23)
2958 | ((float64_val(f64) >> 29) & 0x7fffff);
2959 return make_float32(val32);
4373f3ce
PB		 2960}
2961
e07be5d2
CL		 2962/* The algorithm that must be used to calculate the estimate
2963 * is specified by the ARM ARM.
2964 */
0ecb72a5 2965static float64 recip_sqrt_estimate(float64 a, CPUARMState *env)
e07be5d2 2966{
1146a817
PM		 2967 /* These calculations mustn't set any fp exception flags,
2968 * so we use a local copy of the fp_status.
2969 */
2970 float_status dummy_status = env->vfp.standard_fp_status;
2971 float_status *s = &dummy_status;
e07be5d2
CL		 2972 float64 q;
2973 int64_t q_int;
2974
2975 if (float64_lt(a, float64_half, s)) {
2976 /* range 0.25 <= a < 0.5 */
2977
2978 /* a in units of 1/512 rounded down */
2979 /* q0 = (int)(a * 512.0); */
2980 q = float64_mul(float64_512, a, s);
2981 q_int = float64_to_int64_round_to_zero(q, s);
2982
2983 /* reciprocal root r */
2984 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
2985 q = int64_to_float64(q_int, s);
2986 q = float64_add(q, float64_half, s);
2987 q = float64_div(q, float64_512, s);
2988 q = float64_sqrt(q, s);
2989 q = float64_div(float64_one, q, s);
2990 } else {
2991 /* range 0.5 <= a < 1.0 */
2992
2993 /* a in units of 1/256 rounded down */
2994 /* q1 = (int)(a * 256.0); */
2995 q = float64_mul(float64_256, a, s);
2996 int64_t q_int = float64_to_int64_round_to_zero(q, s);
2997
2998 /* reciprocal root r */
2999 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
3000 q = int64_to_float64(q_int, s);
3001 q = float64_add(q, float64_half, s);
3002 q = float64_div(q, float64_256, s);
3003 q = float64_sqrt(q, s);
3004 q = float64_div(float64_one, q, s);
3005 }
3006 /* r in units of 1/256 rounded to nearest */
3007 /* s = (int)(256.0 * r + 0.5); */
3008
3009 q = float64_mul(q, float64_256,s );
3010 q = float64_add(q, float64_half, s);
3011 q_int = float64_to_int64_round_to_zero(q, s);
3012
3013 /* return (double)s / 256.0;*/
3014 return float64_div(int64_to_float64(q_int, s), float64_256, s);
3015}
3016
0ecb72a5 3017float32 HELPER(rsqrte_f32)(float32 a, CPUARMState *env)
4373f3ce 3018{
e07be5d2
CL		 3019 float_status *s = &env->vfp.standard_fp_status;
3020 int result_exp;
3021 float64 f64;
3022 uint32_t val;
3023 uint64_t val64;
3024
3025 val = float32_val(a);
3026
3027 if (float32_is_any_nan(a)) {
3028 if (float32_is_signaling_nan(a)) {
3029 float_raise(float_flag_invalid, s);
3030 }
3031 return float32_default_nan;
3032 } else if (float32_is_zero_or_denormal(a)) {
43fe9bdb
PM		 3033 if (!float32_is_zero(a)) {
3034 float_raise(float_flag_input_denormal, s);
3035 }
e07be5d2
CL		 3036 float_raise(float_flag_divbyzero, s);
3037 return float32_set_sign(float32_infinity, float32_is_neg(a));
3038 } else if (float32_is_neg(a)) {
3039 float_raise(float_flag_invalid, s);
3040 return float32_default_nan;
3041 } else if (float32_is_infinity(a)) {
3042 return float32_zero;
3043 }
3044
3045 /* Normalize to a double-precision value between 0.25 and 1.0,
3046 * preserving the parity of the exponent. */
3047 if ((val & 0x800000) == 0) {
3048 f64 = make_float64(((uint64_t)(val & 0x80000000) << 32)
3049 | (0x3feULL << 52)
3050 | ((uint64_t)(val & 0x7fffff) << 29));
3051 } else {
3052 f64 = make_float64(((uint64_t)(val & 0x80000000) << 32)
3053 | (0x3fdULL << 52)
3054 | ((uint64_t)(val & 0x7fffff) << 29));
3055 }
3056
3057 result_exp = (380 - ((val & 0x7f800000) >> 23)) / 2;
3058
3059 f64 = recip_sqrt_estimate(f64, env);
3060
3061 val64 = float64_val(f64);
3062
26cc6abf 3063 val = ((result_exp & 0xff) << 23)
e07be5d2
CL		 3064 | ((val64 >> 29) & 0x7fffff);
3065 return make_float32(val);
4373f3ce
PB		 3066}
3067
0ecb72a5 3068uint32_t HELPER(recpe_u32)(uint32_t a, CPUARMState *env)
4373f3ce 3069{
fe0e4872
CL		 3070 float64 f64;
3071
3072 if ((a & 0x80000000) == 0) {
3073 return 0xffffffff;
3074 }
3075
3076 f64 = make_float64((0x3feULL << 52)
3077 | ((int64_t)(a & 0x7fffffff) << 21));
3078
3079 f64 = recip_estimate (f64, env);
3080
3081 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
4373f3ce
PB		 3082}
3083
0ecb72a5 3084uint32_t HELPER(rsqrte_u32)(uint32_t a, CPUARMState *env)
4373f3ce 3085{
e07be5d2
CL		 3086 float64 f64;
3087
3088 if ((a & 0xc0000000) == 0) {
3089 return 0xffffffff;
3090 }
3091
3092 if (a & 0x80000000) {
3093 f64 = make_float64((0x3feULL << 52)
3094 | ((uint64_t)(a & 0x7fffffff) << 21));
3095 } else { /* bits 31-30 == '01' */
3096 f64 = make_float64((0x3fdULL << 52)
3097 | ((uint64_t)(a & 0x3fffffff) << 22));
3098 }
3099
3100 f64 = recip_sqrt_estimate(f64, env);
3101
3102 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
4373f3ce 3103}
fe1479c3 3104
da97f52c
PM		 3105/* VFPv4 fused multiply-accumulate */
3106float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
3107{
3108 float_status *fpst = fpstp;
3109 return float32_muladd(a, b, c, 0, fpst);
3110}
3111
3112float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
3113{
3114 float_status *fpst = fpstp;
3115 return float64_muladd(a, b, c, 0, fpst);
3116}
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