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target-arm: Fix TCG temporary leaks for scalar VMULL
[qemu.git] / target-arm / helper.c
CommitLineData
b5ff1b31
FB		 1#include <stdio.h>
2#include <stdlib.h>
3#include <string.h>
4
5#include "cpu.h"
6#include "exec-all.h"
9ee6e8bb 7#include "gdbstub.h"
b26eefb6 8#include "helpers.h"
ca10f867 9#include "qemu-common.h"
7bbcb0af 10#include "host-utils.h"
4f78c9ad 11#if !defined(CONFIG_USER_ONLY)
983fe826 12#include "hw/loader.h"
4f78c9ad 13#endif
9ee6e8bb 14
10055562
PB		 15static uint32_t cortexa9_cp15_c0_c1[8] =
16{ 0x1031, 0x11, 0x000, 0, 0x00100103, 0x20000000, 0x01230000, 0x00002111 };
17
18static uint32_t cortexa9_cp15_c0_c2[8] =
19{ 0x00101111, 0x13112111, 0x21232041, 0x11112131, 0x00111142, 0, 0, 0 };
20
9ee6e8bb
PB		 21static uint32_t cortexa8_cp15_c0_c1[8] =
22{ 0x1031, 0x11, 0x400, 0, 0x31100003, 0x20000000, 0x01202000, 0x11 };
23
24static uint32_t cortexa8_cp15_c0_c2[8] =
25{ 0x00101111, 0x12112111, 0x21232031, 0x11112131, 0x00111142, 0, 0, 0 };
26
27static uint32_t mpcore_cp15_c0_c1[8] =
28{ 0x111, 0x1, 0, 0x2, 0x01100103, 0x10020302, 0x01222000, 0 };
29
30static uint32_t mpcore_cp15_c0_c2[8] =
31{ 0x00100011, 0x12002111, 0x11221011, 0x01102131, 0x141, 0, 0, 0 };
32
33static uint32_t arm1136_cp15_c0_c1[8] =
34{ 0x111, 0x1, 0x2, 0x3, 0x01130003, 0x10030302, 0x01222110, 0 };
35
36static uint32_t arm1136_cp15_c0_c2[8] =
37{ 0x00140011, 0x12002111, 0x11231111, 0x01102131, 0x141, 0, 0, 0 };
b5ff1b31 38
aaed909a
FB		 39static uint32_t cpu_arm_find_by_name(const char *name);
40
f3d6b95e
PB		 41static inline void set_feature(CPUARMState *env, int feature)
42{
43 env->features |= 1u << feature;
44}
45
46static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
47{
48 env->cp15.c0_cpuid = id;
49 switch (id) {
50 case ARM_CPUID_ARM926:
51 set_feature(env, ARM_FEATURE_VFP);
52 env->vfp.xregs[ARM_VFP_FPSID] = 0x41011090;
c1713132 53 env->cp15.c0_cachetype = 0x1dd20d2;
610c3c8a 54 env->cp15.c1_sys = 0x00090078;
f3d6b95e 55 break;
ce819861
PB		 56 case ARM_CPUID_ARM946:
57 set_feature(env, ARM_FEATURE_MPU);
58 env->cp15.c0_cachetype = 0x0f004006;
610c3c8a 59 env->cp15.c1_sys = 0x00000078;
ce819861 60 break;
f3d6b95e
PB		 61 case ARM_CPUID_ARM1026:
62 set_feature(env, ARM_FEATURE_VFP);
63 set_feature(env, ARM_FEATURE_AUXCR);
64 env->vfp.xregs[ARM_VFP_FPSID] = 0x410110a0;
c1713132 65 env->cp15.c0_cachetype = 0x1dd20d2;
610c3c8a 66 env->cp15.c1_sys = 0x00090078;
c1713132 67 break;
827df9f3 68 case ARM_CPUID_ARM1136_R2:
9ee6e8bb
PB		 69 case ARM_CPUID_ARM1136:
70 set_feature(env, ARM_FEATURE_V6);
71 set_feature(env, ARM_FEATURE_VFP);
72 set_feature(env, ARM_FEATURE_AUXCR);
73 env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
74 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
75 env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
76 memcpy(env->cp15.c0_c1, arm1136_cp15_c0_c1, 8 * sizeof(uint32_t));
22478e79 77 memcpy(env->cp15.c0_c2, arm1136_cp15_c0_c2, 8 * sizeof(uint32_t));
9ee6e8bb 78 env->cp15.c0_cachetype = 0x1dd20d2;
16440c5f 79 env->cp15.c1_sys = 0x00050078;
9ee6e8bb
PB		 80 break;
81 case ARM_CPUID_ARM11MPCORE:
82 set_feature(env, ARM_FEATURE_V6);
83 set_feature(env, ARM_FEATURE_V6K);
84 set_feature(env, ARM_FEATURE_VFP);
85 set_feature(env, ARM_FEATURE_AUXCR);
86 env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
87 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
88 env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
89 memcpy(env->cp15.c0_c1, mpcore_cp15_c0_c1, 8 * sizeof(uint32_t));
22478e79 90 memcpy(env->cp15.c0_c2, mpcore_cp15_c0_c2, 8 * sizeof(uint32_t));
9ee6e8bb
PB		 91 env->cp15.c0_cachetype = 0x1dd20d2;
92 break;
93 case ARM_CPUID_CORTEXA8:
94 set_feature(env, ARM_FEATURE_V6);
95 set_feature(env, ARM_FEATURE_V6K);
96 set_feature(env, ARM_FEATURE_V7);
97 set_feature(env, ARM_FEATURE_AUXCR);
98 set_feature(env, ARM_FEATURE_THUMB2);
99 set_feature(env, ARM_FEATURE_VFP);
100 set_feature(env, ARM_FEATURE_VFP3);
101 set_feature(env, ARM_FEATURE_NEON);
fe1479c3 102 set_feature(env, ARM_FEATURE_THUMB2EE);
9ee6e8bb
PB		 103 env->vfp.xregs[ARM_VFP_FPSID] = 0x410330c0;
104 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
105 env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100;
106 memcpy(env->cp15.c0_c1, cortexa8_cp15_c0_c1, 8 * sizeof(uint32_t));
22478e79 107 memcpy(env->cp15.c0_c2, cortexa8_cp15_c0_c2, 8 * sizeof(uint32_t));
a49ea279
PB		 108 env->cp15.c0_cachetype = 0x82048004;
109 env->cp15.c0_clid = (1 << 27) | (2 << 24) | 3;
110 env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */
111 env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */
112 env->cp15.c0_ccsid[2] = 0xf0000000; /* No L2 icache. */
9c486ad6 113 env->cp15.c1_sys = 0x00c50078;
9ee6e8bb 114 break;
10055562
PB		 115 case ARM_CPUID_CORTEXA9:
116 set_feature(env, ARM_FEATURE_V6);
117 set_feature(env, ARM_FEATURE_V6K);
118 set_feature(env, ARM_FEATURE_V7);
119 set_feature(env, ARM_FEATURE_AUXCR);
120 set_feature(env, ARM_FEATURE_THUMB2);
121 set_feature(env, ARM_FEATURE_VFP);
122 set_feature(env, ARM_FEATURE_VFP3);
123 set_feature(env, ARM_FEATURE_VFP_FP16);
124 set_feature(env, ARM_FEATURE_NEON);
125 set_feature(env, ARM_FEATURE_THUMB2EE);
e1bbf446
PM		 126 /* Note that A9 supports the MP extensions even for
127 * A9UP and single-core A9MP (which are both different
128 * and valid configurations; we don't model A9UP).
129 */
130 set_feature(env, ARM_FEATURE_V7MP);
10055562
PB		 131 env->vfp.xregs[ARM_VFP_FPSID] = 0x41034000; /* Guess */
132 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
133 env->vfp.xregs[ARM_VFP_MVFR1] = 0x01111111;
134 memcpy(env->cp15.c0_c1, cortexa9_cp15_c0_c1, 8 * sizeof(uint32_t));
135 memcpy(env->cp15.c0_c2, cortexa9_cp15_c0_c2, 8 * sizeof(uint32_t));
136 env->cp15.c0_cachetype = 0x80038003;
137 env->cp15.c0_clid = (1 << 27) | (1 << 24) | 3;
138 env->cp15.c0_ccsid[0] = 0xe00fe015; /* 16k L1 dcache. */
139 env->cp15.c0_ccsid[1] = 0x200fe015; /* 16k L1 icache. */
16440c5f 140 env->cp15.c1_sys = 0x00c50078;
10055562 141 break;
9ee6e8bb
PB		 142 case ARM_CPUID_CORTEXM3:
143 set_feature(env, ARM_FEATURE_V6);
144 set_feature(env, ARM_FEATURE_THUMB2);
145 set_feature(env, ARM_FEATURE_V7);
146 set_feature(env, ARM_FEATURE_M);
147 set_feature(env, ARM_FEATURE_DIV);
148 break;
149 case ARM_CPUID_ANY: /* For userspace emulation. */
150 set_feature(env, ARM_FEATURE_V6);
151 set_feature(env, ARM_FEATURE_V6K);
152 set_feature(env, ARM_FEATURE_V7);
153 set_feature(env, ARM_FEATURE_THUMB2);
154 set_feature(env, ARM_FEATURE_VFP);
155 set_feature(env, ARM_FEATURE_VFP3);
60011498 156 set_feature(env, ARM_FEATURE_VFP_FP16);
9ee6e8bb 157 set_feature(env, ARM_FEATURE_NEON);
fe1479c3 158 set_feature(env, ARM_FEATURE_THUMB2EE);
9ee6e8bb 159 set_feature(env, ARM_FEATURE_DIV);
e1bbf446 160 set_feature(env, ARM_FEATURE_V7MP);
9ee6e8bb 161 break;
c3d2689d
AZ		 162 case ARM_CPUID_TI915T:
163 case ARM_CPUID_TI925T:
164 set_feature(env, ARM_FEATURE_OMAPCP);
165 env->cp15.c0_cpuid = ARM_CPUID_TI925T; /* Depends on wiring. */
166 env->cp15.c0_cachetype = 0x5109149;
167 env->cp15.c1_sys = 0x00000070;
168 env->cp15.c15_i_max = 0x000;
169 env->cp15.c15_i_min = 0xff0;
170 break;
c1713132
AZ		 171 case ARM_CPUID_PXA250:
172 case ARM_CPUID_PXA255:
173 case ARM_CPUID_PXA260:
174 case ARM_CPUID_PXA261:
175 case ARM_CPUID_PXA262:
176 set_feature(env, ARM_FEATURE_XSCALE);
177 /* JTAG_ID is ((id << 28) | 0x09265013) */
178 env->cp15.c0_cachetype = 0xd172172;
610c3c8a 179 env->cp15.c1_sys = 0x00000078;
c1713132
AZ		 180 break;
181 case ARM_CPUID_PXA270_A0:
182 case ARM_CPUID_PXA270_A1:
183 case ARM_CPUID_PXA270_B0:
184 case ARM_CPUID_PXA270_B1:
185 case ARM_CPUID_PXA270_C0:
186 case ARM_CPUID_PXA270_C5:
187 set_feature(env, ARM_FEATURE_XSCALE);
188 /* JTAG_ID is ((id << 28) | 0x09265013) */
18c9b560
AZ		 189 set_feature(env, ARM_FEATURE_IWMMXT);
190 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
c1713132 191 env->cp15.c0_cachetype = 0xd172172;
610c3c8a 192 env->cp15.c1_sys = 0x00000078;
f3d6b95e
PB		 193 break;
194 default:
195 cpu_abort(env, "Bad CPU ID: %x\n", id);
196 break;
197 }
198}
199
40f137e1
PB		 200void cpu_reset(CPUARMState *env)
201{
f3d6b95e 202 uint32_t id;
eca1bdf4
AL		 203
204 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
205 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
206 log_cpu_state(env, 0);
207 }
208
f3d6b95e
PB		 209 id = env->cp15.c0_cpuid;
210 memset(env, 0, offsetof(CPUARMState, breakpoints));
211 if (id)
212 cpu_reset_model_id(env, id);
40f137e1
PB		 213#if defined (CONFIG_USER_ONLY)
214 env->uncached_cpsr = ARM_CPU_MODE_USR;
3a807dec 215 /* For user mode we must enable access to coprocessors */
40f137e1 216 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
3a807dec
PM		 217 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
218 env->cp15.c15_cpar = 3;
219 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
220 env->cp15.c15_cpar = 1;
221 }
40f137e1
PB		 222#else
223 /* SVC mode with interrupts disabled. */
224 env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
9ee6e8bb 225 /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
983fe826
PB		 226 clear at reset. Initial SP and PC are loaded from ROM. */
227 if (IS_M(env)) {
228 uint32_t pc;
229 uint8_t *rom;
9ee6e8bb 230 env->uncached_cpsr &= ~CPSR_I;
983fe826
PB		 231 rom = rom_ptr(0);
232 if (rom) {
233 /* We should really use ldl_phys here, in case the guest
234 modified flash and reset itself. However images
235 loaded via -kenrel have not been copied yet, so load the
236 values directly from there. */
237 env->regs[13] = ldl_p(rom);
238 pc = ldl_p(rom + 4);
239 env->thumb = pc & 1;
240 env->regs[15] = pc & ~1;
241 }
242 }
40f137e1 243 env->vfp.xregs[ARM_VFP_FPEXC] = 0;
b2fa1797 244 env->cp15.c2_base_mask = 0xffffc000u;
40f137e1 245#endif
3a492f3a
PM		 246 set_flush_to_zero(1, &env->vfp.standard_fp_status);
247 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
248 set_default_nan_mode(1, &env->vfp.standard_fp_status);
f3d6b95e 249 tlb_flush(env, 1);
40f137e1
PB		 250}
251
56aebc89
PB		 252static int vfp_gdb_get_reg(CPUState *env, uint8_t *buf, int reg)
253{
254 int nregs;
255
256 /* VFP data registers are always little-endian. */
257 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
258 if (reg < nregs) {
259 stfq_le_p(buf, env->vfp.regs[reg]);
260 return 8;
261 }
262 if (arm_feature(env, ARM_FEATURE_NEON)) {
263 /* Aliases for Q regs. */
264 nregs += 16;
265 if (reg < nregs) {
266 stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
267 stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
268 return 16;
269 }
270 }
271 switch (reg - nregs) {
272 case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
273 case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
274 case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
275 }
276 return 0;
277}
278
279static int vfp_gdb_set_reg(CPUState *env, uint8_t *buf, int reg)
280{
281 int nregs;
282
283 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
284 if (reg < nregs) {
285 env->vfp.regs[reg] = ldfq_le_p(buf);
286 return 8;
287 }
288 if (arm_feature(env, ARM_FEATURE_NEON)) {
289 nregs += 16;
290 if (reg < nregs) {
291 env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
292 env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
293 return 16;
294 }
295 }
296 switch (reg - nregs) {
297 case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
298 case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
71b3c3de 299 case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
56aebc89
PB		 300 }
301 return 0;
302}
303
aaed909a 304CPUARMState *cpu_arm_init(const char *cpu_model)
40f137e1
PB		 305{
306 CPUARMState *env;
aaed909a 307 uint32_t id;
b26eefb6 308 static int inited = 0;
40f137e1 309
aaed909a
FB		 310 id = cpu_arm_find_by_name(cpu_model);
311 if (id == 0)
312 return NULL;
40f137e1 313 env = qemu_mallocz(sizeof(CPUARMState));
40f137e1 314 cpu_exec_init(env);
b26eefb6
PB		 315 if (!inited) {
316 inited = 1;
317 arm_translate_init();
318 }
319
01ba9816 320 env->cpu_model_str = cpu_model;
aaed909a 321 env->cp15.c0_cpuid = id;
40f137e1 322 cpu_reset(env);
56aebc89
PB		 323 if (arm_feature(env, ARM_FEATURE_NEON)) {
324 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
325 51, "arm-neon.xml", 0);
326 } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
327 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
328 35, "arm-vfp3.xml", 0);
329 } else if (arm_feature(env, ARM_FEATURE_VFP)) {
330 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
331 19, "arm-vfp.xml", 0);
332 }
0bf46a40 333 qemu_init_vcpu(env);
40f137e1
PB		 334 return env;
335}
336
3371d272
PB		 337struct arm_cpu_t {
338 uint32_t id;
339 const char *name;
340};
341
342static const struct arm_cpu_t arm_cpu_names[] = {
343 { ARM_CPUID_ARM926, "arm926"},
ce819861 344 { ARM_CPUID_ARM946, "arm946"},
3371d272 345 { ARM_CPUID_ARM1026, "arm1026"},
9ee6e8bb 346 { ARM_CPUID_ARM1136, "arm1136"},
827df9f3 347 { ARM_CPUID_ARM1136_R2, "arm1136-r2"},
9ee6e8bb
PB		 348 { ARM_CPUID_ARM11MPCORE, "arm11mpcore"},
349 { ARM_CPUID_CORTEXM3, "cortex-m3"},
350 { ARM_CPUID_CORTEXA8, "cortex-a8"},
10055562 351 { ARM_CPUID_CORTEXA9, "cortex-a9"},
c3d2689d 352 { ARM_CPUID_TI925T, "ti925t" },
c1713132
AZ		 353 { ARM_CPUID_PXA250, "pxa250" },
354 { ARM_CPUID_PXA255, "pxa255" },
355 { ARM_CPUID_PXA260, "pxa260" },
356 { ARM_CPUID_PXA261, "pxa261" },
357 { ARM_CPUID_PXA262, "pxa262" },
358 { ARM_CPUID_PXA270, "pxa270" },
359 { ARM_CPUID_PXA270_A0, "pxa270-a0" },
360 { ARM_CPUID_PXA270_A1, "pxa270-a1" },
361 { ARM_CPUID_PXA270_B0, "pxa270-b0" },
362 { ARM_CPUID_PXA270_B1, "pxa270-b1" },
363 { ARM_CPUID_PXA270_C0, "pxa270-c0" },
364 { ARM_CPUID_PXA270_C5, "pxa270-c5" },
9ee6e8bb 365 { ARM_CPUID_ANY, "any"},
3371d272
PB		 366 { 0, NULL}
367};
368
9a78eead 369void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
5adb4839
PB		 370{
371 int i;
372
c732abe2 373 (*cpu_fprintf)(f, "Available CPUs:\n");
5adb4839 374 for (i = 0; arm_cpu_names[i].name; i++) {
c732abe2 375 (*cpu_fprintf)(f, " %s\n", arm_cpu_names[i].name);
5adb4839
PB		 376 }
377}
378
aaed909a
FB		 379/* return 0 if not found */
380static uint32_t cpu_arm_find_by_name(const char *name)
40f137e1 381{
3371d272
PB		 382 int i;
383 uint32_t id;
384
385 id = 0;
3371d272
PB		 386 for (i = 0; arm_cpu_names[i].name; i++) {
387 if (strcmp(name, arm_cpu_names[i].name) == 0) {
388 id = arm_cpu_names[i].id;
389 break;
390 }
391 }
aaed909a 392 return id;
40f137e1
PB		 393}
394
395void cpu_arm_close(CPUARMState *env)
396{
397 free(env);
398}
399
2f4a40e5
AZ		 400uint32_t cpsr_read(CPUARMState *env)
401{
402 int ZF;
6fbe23d5
PB		 403 ZF = (env->ZF == 0);
404 return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
2f4a40e5
AZ		 405 (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
406 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
407 | ((env->condexec_bits & 0xfc) << 8)
408 | (env->GE << 16);
409}
410
411void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
412{
2f4a40e5 413 if (mask & CPSR_NZCV) {
6fbe23d5
PB		 414 env->ZF = (~val) & CPSR_Z;
415 env->NF = val;
2f4a40e5
AZ		 416 env->CF = (val >> 29) & 1;
417 env->VF = (val << 3) & 0x80000000;
418 }
419 if (mask & CPSR_Q)
420 env->QF = ((val & CPSR_Q) != 0);
421 if (mask & CPSR_T)
422 env->thumb = ((val & CPSR_T) != 0);
423 if (mask & CPSR_IT_0_1) {
424 env->condexec_bits &= ~3;
425 env->condexec_bits |= (val >> 25) & 3;
426 }
427 if (mask & CPSR_IT_2_7) {
428 env->condexec_bits &= 3;
429 env->condexec_bits |= (val >> 8) & 0xfc;
430 }
431 if (mask & CPSR_GE) {
432 env->GE = (val >> 16) & 0xf;
433 }
434
435 if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
436 switch_mode(env, val & CPSR_M);
437 }
438 mask &= ~CACHED_CPSR_BITS;
439 env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
440}
441
b26eefb6
PB		 442/* Sign/zero extend */
443uint32_t HELPER(sxtb16)(uint32_t x)
444{
445 uint32_t res;
446 res = (uint16_t)(int8_t)x;
447 res |= (uint32_t)(int8_t)(x >> 16) << 16;
448 return res;
449}
450
451uint32_t HELPER(uxtb16)(uint32_t x)
452{
453 uint32_t res;
454 res = (uint16_t)(uint8_t)x;
455 res |= (uint32_t)(uint8_t)(x >> 16) << 16;
456 return res;
457}
458
f51bbbfe
PB		 459uint32_t HELPER(clz)(uint32_t x)
460{
7bbcb0af 461 return clz32(x);
f51bbbfe
PB		 462}
463
3670669c
PB		 464int32_t HELPER(sdiv)(int32_t num, int32_t den)
465{
466 if (den == 0)
467 return 0;
686eeb93
AJ		 468 if (num == INT_MIN && den == -1)
469 return INT_MIN;
3670669c
PB		 470 return num / den;
471}
472
473uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
474{
475 if (den == 0)
476 return 0;
477 return num / den;
478}
479
480uint32_t HELPER(rbit)(uint32_t x)
481{
482 x = ((x & 0xff000000) >> 24)
483 | ((x & 0x00ff0000) >> 8)
484 | ((x & 0x0000ff00) << 8)
485 | ((x & 0x000000ff) << 24);
486 x = ((x & 0xf0f0f0f0) >> 4)
487 | ((x & 0x0f0f0f0f) << 4);
488 x = ((x & 0x88888888) >> 3)
489 | ((x & 0x44444444) >> 1)
490 | ((x & 0x22222222) << 1)
491 | ((x & 0x11111111) << 3);
492 return x;
493}
494
ad69471c
PB		 495uint32_t HELPER(abs)(uint32_t x)
496{
497 return ((int32_t)x < 0) ? -x : x;
498}
499
5fafdf24 500#if defined(CONFIG_USER_ONLY)
b5ff1b31
FB		 501
502void do_interrupt (CPUState *env)
503{
504 env->exception_index = -1;
505}
506
507int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
6ebbf390 508 int mmu_idx, int is_softmmu)
b5ff1b31
FB		 509{
510 if (rw == 2) {
511 env->exception_index = EXCP_PREFETCH_ABORT;
512 env->cp15.c6_insn = address;
513 } else {
514 env->exception_index = EXCP_DATA_ABORT;
515 env->cp15.c6_data = address;
516 }
517 return 1;
518}
519
b5ff1b31 520/* These should probably raise undefined insn exceptions. */
8984bd2e 521void HELPER(set_cp)(CPUState *env, uint32_t insn, uint32_t val)
c1713132
AZ		 522{
523 int op1 = (insn >> 8) & 0xf;
524 cpu_abort(env, "cp%i insn %08x\n", op1, insn);
525 return;
526}
527
8984bd2e 528uint32_t HELPER(get_cp)(CPUState *env, uint32_t insn)
c1713132
AZ		 529{
530 int op1 = (insn >> 8) & 0xf;
531 cpu_abort(env, "cp%i insn %08x\n", op1, insn);
532 return 0;
533}
534
8984bd2e 535void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
b5ff1b31
FB		 536{
537 cpu_abort(env, "cp15 insn %08x\n", insn);
538}
539
8984bd2e 540uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
b5ff1b31
FB		 541{
542 cpu_abort(env, "cp15 insn %08x\n", insn);
b5ff1b31
FB		 543}
544
9ee6e8bb 545/* These should probably raise undefined insn exceptions. */
8984bd2e 546void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val)
9ee6e8bb
PB		 547{
548 cpu_abort(env, "v7m_mrs %d\n", reg);
549}
550
8984bd2e 551uint32_t HELPER(v7m_mrs)(CPUState *env, uint32_t reg)
9ee6e8bb
PB		 552{
553 cpu_abort(env, "v7m_mrs %d\n", reg);
554 return 0;
555}
556
b5ff1b31
FB		 557void switch_mode(CPUState *env, int mode)
558{
559 if (mode != ARM_CPU_MODE_USR)
560 cpu_abort(env, "Tried to switch out of user mode\n");
561}
562
b0109805 563void HELPER(set_r13_banked)(CPUState *env, uint32_t mode, uint32_t val)
9ee6e8bb
PB		 564{
565 cpu_abort(env, "banked r13 write\n");
566}
567
b0109805 568uint32_t HELPER(get_r13_banked)(CPUState *env, uint32_t mode)
9ee6e8bb
PB		 569{
570 cpu_abort(env, "banked r13 read\n");
571 return 0;
572}
573
b5ff1b31
FB		 574#else
575
8e71621f
PB		 576extern int semihosting_enabled;
577
b5ff1b31
FB		 578/* Map CPU modes onto saved register banks. */
579static inline int bank_number (int mode)
580{
581 switch (mode) {
582 case ARM_CPU_MODE_USR:
583 case ARM_CPU_MODE_SYS:
584 return 0;
585 case ARM_CPU_MODE_SVC:
586 return 1;
587 case ARM_CPU_MODE_ABT:
588 return 2;
589 case ARM_CPU_MODE_UND:
590 return 3;
591 case ARM_CPU_MODE_IRQ:
592 return 4;
593 case ARM_CPU_MODE_FIQ:
594 return 5;
595 }
596 cpu_abort(cpu_single_env, "Bad mode %x\n", mode);
597 return -1;
598}
599
600void switch_mode(CPUState *env, int mode)
601{
602 int old_mode;
603 int i;
604
605 old_mode = env->uncached_cpsr & CPSR_M;
606 if (mode == old_mode)
607 return;
608
609 if (old_mode == ARM_CPU_MODE_FIQ) {
610 memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
8637c67f 611 memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
b5ff1b31
FB		 612 } else if (mode == ARM_CPU_MODE_FIQ) {
613 memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
8637c67f 614 memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
b5ff1b31
FB		 615 }
616
617 i = bank_number(old_mode);
618 env->banked_r13[i] = env->regs[13];
619 env->banked_r14[i] = env->regs[14];
620 env->banked_spsr[i] = env->spsr;
621
622 i = bank_number(mode);
623 env->regs[13] = env->banked_r13[i];
624 env->regs[14] = env->banked_r14[i];
625 env->spsr = env->banked_spsr[i];
626}
627
9ee6e8bb
PB		 628static void v7m_push(CPUARMState *env, uint32_t val)
629{
630 env->regs[13] -= 4;
631 stl_phys(env->regs[13], val);
632}
633
634static uint32_t v7m_pop(CPUARMState *env)
635{
636 uint32_t val;
637 val = ldl_phys(env->regs[13]);
638 env->regs[13] += 4;
639 return val;
640}
641
642/* Switch to V7M main or process stack pointer. */
643static void switch_v7m_sp(CPUARMState *env, int process)
644{
645 uint32_t tmp;
646 if (env->v7m.current_sp != process) {
647 tmp = env->v7m.other_sp;
648 env->v7m.other_sp = env->regs[13];
649 env->regs[13] = tmp;
650 env->v7m.current_sp = process;
651 }
652}
653
654static void do_v7m_exception_exit(CPUARMState *env)
655{
656 uint32_t type;
657 uint32_t xpsr;
658
659 type = env->regs[15];
660 if (env->v7m.exception != 0)
983fe826 661 armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
9ee6e8bb
PB		 662
663 /* Switch to the target stack. */
664 switch_v7m_sp(env, (type & 4) != 0);
665 /* Pop registers. */
666 env->regs[0] = v7m_pop(env);
667 env->regs[1] = v7m_pop(env);
668 env->regs[2] = v7m_pop(env);
669 env->regs[3] = v7m_pop(env);
670 env->regs[12] = v7m_pop(env);
671 env->regs[14] = v7m_pop(env);
672 env->regs[15] = v7m_pop(env);
673 xpsr = v7m_pop(env);
674 xpsr_write(env, xpsr, 0xfffffdff);
675 /* Undo stack alignment. */
676 if (xpsr & 0x200)
677 env->regs[13] |= 4;
678 /* ??? The exception return type specifies Thread/Handler mode. However
679 this is also implied by the xPSR value. Not sure what to do
680 if there is a mismatch. */
681 /* ??? Likewise for mismatches between the CONTROL register and the stack
682 pointer. */
683}
684
2b3ea315 685static void do_interrupt_v7m(CPUARMState *env)
9ee6e8bb
PB		 686{
687 uint32_t xpsr = xpsr_read(env);
688 uint32_t lr;
689 uint32_t addr;
690
691 lr = 0xfffffff1;
692 if (env->v7m.current_sp)
693 lr |= 4;
694 if (env->v7m.exception == 0)
695 lr |= 8;
696
697 /* For exceptions we just mark as pending on the NVIC, and let that
698 handle it. */
699 /* TODO: Need to escalate if the current priority is higher than the
700 one we're raising. */
701 switch (env->exception_index) {
702 case EXCP_UDEF:
983fe826 703 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
9ee6e8bb
PB		 704 return;
705 case EXCP_SWI:
706 env->regs[15] += 2;
983fe826 707 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
9ee6e8bb
PB		 708 return;
709 case EXCP_PREFETCH_ABORT:
710 case EXCP_DATA_ABORT:
983fe826 711 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
9ee6e8bb
PB		 712 return;
713 case EXCP_BKPT:
2ad207d4
PB		 714 if (semihosting_enabled) {
715 int nr;
716 nr = lduw_code(env->regs[15]) & 0xff;
717 if (nr == 0xab) {
718 env->regs[15] += 2;
719 env->regs[0] = do_arm_semihosting(env);
720 return;
721 }
722 }
983fe826 723 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
9ee6e8bb
PB		 724 return;
725 case EXCP_IRQ:
983fe826 726 env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
9ee6e8bb
PB		 727 break;
728 case EXCP_EXCEPTION_EXIT:
729 do_v7m_exception_exit(env);
730 return;
731 default:
732 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
733 return; /* Never happens. Keep compiler happy. */
734 }
735
736 /* Align stack pointer. */
737 /* ??? Should only do this if Configuration Control Register
738 STACKALIGN bit is set. */
739 if (env->regs[13] & 4) {
ab19b0ec 740 env->regs[13] -= 4;
9ee6e8bb
PB		 741 xpsr |= 0x200;
742 }
6c95676b 743 /* Switch to the handler mode. */
9ee6e8bb
PB		 744 v7m_push(env, xpsr);
745 v7m_push(env, env->regs[15]);
746 v7m_push(env, env->regs[14]);
747 v7m_push(env, env->regs[12]);
748 v7m_push(env, env->regs[3]);
749 v7m_push(env, env->regs[2]);
750 v7m_push(env, env->regs[1]);
751 v7m_push(env, env->regs[0]);
752 switch_v7m_sp(env, 0);
753 env->uncached_cpsr &= ~CPSR_IT;
754 env->regs[14] = lr;
755 addr = ldl_phys(env->v7m.vecbase + env->v7m.exception * 4);
756 env->regs[15] = addr & 0xfffffffe;
757 env->thumb = addr & 1;
758}
759
b5ff1b31
FB		 760/* Handle a CPU exception. */
761void do_interrupt(CPUARMState *env)
762{
763 uint32_t addr;
764 uint32_t mask;
765 int new_mode;
766 uint32_t offset;
767
9ee6e8bb
PB		 768 if (IS_M(env)) {
769 do_interrupt_v7m(env);
770 return;
771 }
b5ff1b31
FB		 772 /* TODO: Vectored interrupt controller. */
773 switch (env->exception_index) {
774 case EXCP_UDEF:
775 new_mode = ARM_CPU_MODE_UND;
776 addr = 0x04;
777 mask = CPSR_I;
778 if (env->thumb)
779 offset = 2;
780 else
781 offset = 4;
782 break;
783 case EXCP_SWI:
8e71621f
PB		 784 if (semihosting_enabled) {
785 /* Check for semihosting interrupt. */
786 if (env->thumb) {
787 mask = lduw_code(env->regs[15] - 2) & 0xff;
788 } else {
789 mask = ldl_code(env->regs[15] - 4) & 0xffffff;
790 }
791 /* Only intercept calls from privileged modes, to provide some
792 semblance of security. */
793 if (((mask == 0x123456 && !env->thumb)
794 || (mask == 0xab && env->thumb))
795 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
796 env->regs[0] = do_arm_semihosting(env);
797 return;
798 }
799 }
b5ff1b31
FB		 800 new_mode = ARM_CPU_MODE_SVC;
801 addr = 0x08;
802 mask = CPSR_I;
601d70b9 803 /* The PC already points to the next instruction. */
b5ff1b31
FB		 804 offset = 0;
805 break;
06c949e6 806 case EXCP_BKPT:
9ee6e8bb 807 /* See if this is a semihosting syscall. */
2ad207d4 808 if (env->thumb && semihosting_enabled) {
9ee6e8bb
PB		 809 mask = lduw_code(env->regs[15]) & 0xff;
810 if (mask == 0xab
811 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
812 env->regs[15] += 2;
813 env->regs[0] = do_arm_semihosting(env);
814 return;
815 }
816 }
817 /* Fall through to prefetch abort. */
818 case EXCP_PREFETCH_ABORT:
b5ff1b31
FB		 819 new_mode = ARM_CPU_MODE_ABT;
820 addr = 0x0c;
821 mask = CPSR_A | CPSR_I;
822 offset = 4;
823 break;
824 case EXCP_DATA_ABORT:
825 new_mode = ARM_CPU_MODE_ABT;
826 addr = 0x10;
827 mask = CPSR_A | CPSR_I;
828 offset = 8;
829 break;
830 case EXCP_IRQ:
831 new_mode = ARM_CPU_MODE_IRQ;
832 addr = 0x18;
833 /* Disable IRQ and imprecise data aborts. */
834 mask = CPSR_A | CPSR_I;
835 offset = 4;
836 break;
837 case EXCP_FIQ:
838 new_mode = ARM_CPU_MODE_FIQ;
839 addr = 0x1c;
840 /* Disable FIQ, IRQ and imprecise data aborts. */
841 mask = CPSR_A | CPSR_I | CPSR_F;
842 offset = 4;
843 break;
844 default:
845 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
846 return; /* Never happens. Keep compiler happy. */
847 }
848 /* High vectors. */
849 if (env->cp15.c1_sys & (1 << 13)) {
850 addr += 0xffff0000;
851 }
852 switch_mode (env, new_mode);
853 env->spsr = cpsr_read(env);
9ee6e8bb
PB		 854 /* Clear IT bits. */
855 env->condexec_bits = 0;
30a8cac1 856 /* Switch to the new mode, and to the correct instruction set. */
6d7e6326 857 env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
b5ff1b31 858 env->uncached_cpsr |= mask;
30a8cac1 859 env->thumb = (env->cp15.c1_sys & (1 << 30)) != 0;
b5ff1b31
FB		 860 env->regs[14] = env->regs[15] + offset;
861 env->regs[15] = addr;
862 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
863}
864
865/* Check section/page access permissions.
866 Returns the page protection flags, or zero if the access is not
867 permitted. */
868static inline int check_ap(CPUState *env, int ap, int domain, int access_type,
869 int is_user)
870{
9ee6e8bb
PB		 871 int prot_ro;
872
b5ff1b31
FB		 873 if (domain == 3)
874 return PAGE_READ | PAGE_WRITE;
875
9ee6e8bb
PB		 876 if (access_type == 1)
877 prot_ro = 0;
878 else
879 prot_ro = PAGE_READ;
880
b5ff1b31
FB		 881 switch (ap) {
882 case 0:
78600320 883 if (access_type == 1)
b5ff1b31
FB		 884 return 0;
885 switch ((env->cp15.c1_sys >> 8) & 3) {
886 case 1:
887 return is_user ? 0 : PAGE_READ;
888 case 2:
889 return PAGE_READ;
890 default:
891 return 0;
892 }
893 case 1:
894 return is_user ? 0 : PAGE_READ | PAGE_WRITE;
895 case 2:
896 if (is_user)
9ee6e8bb 897 return prot_ro;
b5ff1b31
FB		 898 else
899 return PAGE_READ | PAGE_WRITE;
900 case 3:
901 return PAGE_READ | PAGE_WRITE;
d4934d18 902 case 4: /* Reserved. */
9ee6e8bb
PB		 903 return 0;
904 case 5:
905 return is_user ? 0 : prot_ro;
906 case 6:
907 return prot_ro;
d4934d18
PB		 908 case 7:
909 if (!arm_feature (env, ARM_FEATURE_V7))
910 return 0;
911 return prot_ro;
b5ff1b31
FB		 912 default:
913 abort();
914 }
915}
916
b2fa1797
PB		 917static uint32_t get_level1_table_address(CPUState *env, uint32_t address)
918{
919 uint32_t table;
920
921 if (address & env->cp15.c2_mask)
922 table = env->cp15.c2_base1 & 0xffffc000;
923 else
924 table = env->cp15.c2_base0 & env->cp15.c2_base_mask;
925
926 table |= (address >> 18) & 0x3ffc;
927 return table;
928}
929
9ee6e8bb 930static int get_phys_addr_v5(CPUState *env, uint32_t address, int access_type,
d4c430a8
PB		 931 int is_user, uint32_t *phys_ptr, int *prot,
932 target_ulong *page_size)
b5ff1b31
FB		 933{
934 int code;
935 uint32_t table;
936 uint32_t desc;
937 int type;
938 int ap;
939 int domain;
940 uint32_t phys_addr;
941
9ee6e8bb
PB		 942 /* Pagetable walk. */
943 /* Lookup l1 descriptor. */
b2fa1797 944 table = get_level1_table_address(env, address);
9ee6e8bb
PB		 945 desc = ldl_phys(table);
946 type = (desc & 3);
947 domain = (env->cp15.c3 >> ((desc >> 4) & 0x1e)) & 3;
948 if (type == 0) {
601d70b9 949 /* Section translation fault. */
9ee6e8bb
PB		 950 code = 5;
951 goto do_fault;
952 }
953 if (domain == 0 || domain == 2) {
954 if (type == 2)
955 code = 9; /* Section domain fault. */
956 else
957 code = 11; /* Page domain fault. */
958 goto do_fault;
959 }
960 if (type == 2) {
961 /* 1Mb section. */
962 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
963 ap = (desc >> 10) & 3;
964 code = 13;
d4c430a8 965 *page_size = 1024 * 1024;
9ee6e8bb
PB		 966 } else {
967 /* Lookup l2 entry. */
968 if (type == 1) {
969 /* Coarse pagetable. */
970 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
971 } else {
972 /* Fine pagetable. */
973 table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
974 }
975 desc = ldl_phys(table);
976 switch (desc & 3) {
977 case 0: /* Page translation fault. */
978 code = 7;
979 goto do_fault;
980 case 1: /* 64k page. */
981 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
982 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
d4c430a8 983 *page_size = 0x10000;
ce819861 984 break;
9ee6e8bb
PB		 985 case 2: /* 4k page. */
986 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
987 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
d4c430a8 988 *page_size = 0x1000;
ce819861 989 break;
9ee6e8bb
PB		 990 case 3: /* 1k page. */
991 if (type == 1) {
992 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
993 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
994 } else {
995 /* Page translation fault. */
996 code = 7;
997 goto do_fault;
998 }
999 } else {
1000 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
1001 }
1002 ap = (desc >> 4) & 3;
d4c430a8 1003 *page_size = 0x400;
ce819861
PB		 1004 break;
1005 default:
9ee6e8bb
PB		 1006 /* Never happens, but compiler isn't smart enough to tell. */
1007 abort();
ce819861 1008 }
9ee6e8bb
PB		 1009 code = 15;
1010 }
1011 *prot = check_ap(env, ap, domain, access_type, is_user);
1012 if (!*prot) {
1013 /* Access permission fault. */
1014 goto do_fault;
1015 }
3ad493fc 1016 *prot |= PAGE_EXEC;
9ee6e8bb
PB		 1017 *phys_ptr = phys_addr;
1018 return 0;
1019do_fault:
1020 return code | (domain << 4);
1021}
1022
1023static int get_phys_addr_v6(CPUState *env, uint32_t address, int access_type,
d4c430a8
PB		 1024 int is_user, uint32_t *phys_ptr, int *prot,
1025 target_ulong *page_size)
9ee6e8bb
PB		 1026{
1027 int code;
1028 uint32_t table;
1029 uint32_t desc;
1030 uint32_t xn;
1031 int type;
1032 int ap;
1033 int domain;
1034 uint32_t phys_addr;
1035
1036 /* Pagetable walk. */
1037 /* Lookup l1 descriptor. */
b2fa1797 1038 table = get_level1_table_address(env, address);
9ee6e8bb
PB		 1039 desc = ldl_phys(table);
1040 type = (desc & 3);
1041 if (type == 0) {
601d70b9 1042 /* Section translation fault. */
9ee6e8bb
PB		 1043 code = 5;
1044 domain = 0;
1045 goto do_fault;
1046 } else if (type == 2 && (desc & (1 << 18))) {
1047 /* Supersection. */
1048 domain = 0;
b5ff1b31 1049 } else {
9ee6e8bb
PB		 1050 /* Section or page. */
1051 domain = (desc >> 4) & 0x1e;
1052 }
1053 domain = (env->cp15.c3 >> domain) & 3;
1054 if (domain == 0 || domain == 2) {
1055 if (type == 2)
1056 code = 9; /* Section domain fault. */
1057 else
1058 code = 11; /* Page domain fault. */
1059 goto do_fault;
1060 }
1061 if (type == 2) {
1062 if (desc & (1 << 18)) {
1063 /* Supersection. */
1064 phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
d4c430a8 1065 *page_size = 0x1000000;
b5ff1b31 1066 } else {
9ee6e8bb
PB		 1067 /* Section. */
1068 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
d4c430a8 1069 *page_size = 0x100000;
b5ff1b31 1070 }
9ee6e8bb
PB		 1071 ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
1072 xn = desc & (1 << 4);
1073 code = 13;
1074 } else {
1075 /* Lookup l2 entry. */
1076 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
1077 desc = ldl_phys(table);
1078 ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
1079 switch (desc & 3) {
1080 case 0: /* Page translation fault. */
1081 code = 7;
b5ff1b31 1082 goto do_fault;
9ee6e8bb
PB		 1083 case 1: /* 64k page. */
1084 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
1085 xn = desc & (1 << 15);
d4c430a8 1086 *page_size = 0x10000;
9ee6e8bb
PB		 1087 break;
1088 case 2: case 3: /* 4k page. */
1089 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
1090 xn = desc & 1;
d4c430a8 1091 *page_size = 0x1000;
9ee6e8bb
PB		 1092 break;
1093 default:
1094 /* Never happens, but compiler isn't smart enough to tell. */
1095 abort();
b5ff1b31 1096 }
9ee6e8bb
PB		 1097 code = 15;
1098 }
c0034328
JR		 1099 if (domain == 3) {
1100 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
1101 } else {
1102 if (xn && access_type == 2)
1103 goto do_fault;
9ee6e8bb 1104
c0034328
JR		 1105 /* The simplified model uses AP[0] as an access control bit. */
1106 if ((env->cp15.c1_sys & (1 << 29)) && (ap & 1) == 0) {
1107 /* Access flag fault. */
1108 code = (code == 15) ? 6 : 3;
1109 goto do_fault;
1110 }
1111 *prot = check_ap(env, ap, domain, access_type, is_user);
1112 if (!*prot) {
1113 /* Access permission fault. */
1114 goto do_fault;
1115 }
1116 if (!xn) {
1117 *prot |= PAGE_EXEC;
1118 }
3ad493fc 1119 }
9ee6e8bb 1120 *phys_ptr = phys_addr;
b5ff1b31
FB		 1121 return 0;
1122do_fault:
1123 return code | (domain << 4);
1124}
1125
9ee6e8bb
PB		 1126static int get_phys_addr_mpu(CPUState *env, uint32_t address, int access_type,
1127 int is_user, uint32_t *phys_ptr, int *prot)
1128{
1129 int n;
1130 uint32_t mask;
1131 uint32_t base;
1132
1133 *phys_ptr = address;
1134 for (n = 7; n >= 0; n--) {
1135 base = env->cp15.c6_region[n];
1136 if ((base & 1) == 0)
1137 continue;
1138 mask = 1 << ((base >> 1) & 0x1f);
1139 /* Keep this shift separate from the above to avoid an
1140 (undefined) << 32. */
1141 mask = (mask << 1) - 1;
1142 if (((base ^ address) & ~mask) == 0)
1143 break;
1144 }
1145 if (n < 0)
1146 return 2;
1147
1148 if (access_type == 2) {
1149 mask = env->cp15.c5_insn;
1150 } else {
1151 mask = env->cp15.c5_data;
1152 }
1153 mask = (mask >> (n * 4)) & 0xf;
1154 switch (mask) {
1155 case 0:
1156 return 1;
1157 case 1:
1158 if (is_user)
1159 return 1;
1160 *prot = PAGE_READ | PAGE_WRITE;
1161 break;
1162 case 2:
1163 *prot = PAGE_READ;
1164 if (!is_user)
1165 *prot |= PAGE_WRITE;
1166 break;
1167 case 3:
1168 *prot = PAGE_READ | PAGE_WRITE;
1169 break;
1170 case 5:
1171 if (is_user)
1172 return 1;
1173 *prot = PAGE_READ;
1174 break;
1175 case 6:
1176 *prot = PAGE_READ;
1177 break;
1178 default:
1179 /* Bad permission. */
1180 return 1;
1181 }
3ad493fc 1182 *prot |= PAGE_EXEC;
9ee6e8bb
PB		 1183 return 0;
1184}
1185
1186static inline int get_phys_addr(CPUState *env, uint32_t address,
1187 int access_type, int is_user,
d4c430a8
PB		 1188 uint32_t *phys_ptr, int *prot,
1189 target_ulong *page_size)
9ee6e8bb
PB		 1190{
1191 /* Fast Context Switch Extension. */
1192 if (address < 0x02000000)
1193 address += env->cp15.c13_fcse;
1194
1195 if ((env->cp15.c1_sys & 1) == 0) {
1196 /* MMU/MPU disabled. */
1197 *phys_ptr = address;
3ad493fc 1198 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
d4c430a8 1199 *page_size = TARGET_PAGE_SIZE;
9ee6e8bb
PB		 1200 return 0;
1201 } else if (arm_feature(env, ARM_FEATURE_MPU)) {
d4c430a8 1202 *page_size = TARGET_PAGE_SIZE;
9ee6e8bb
PB		 1203 return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr,
1204 prot);
1205 } else if (env->cp15.c1_sys & (1 << 23)) {
1206 return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr,
d4c430a8 1207 prot, page_size);
9ee6e8bb
PB		 1208 } else {
1209 return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr,
d4c430a8 1210 prot, page_size);
9ee6e8bb
PB		 1211 }
1212}
1213
b5ff1b31 1214int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address,
6ebbf390 1215 int access_type, int mmu_idx, int is_softmmu)
b5ff1b31
FB		 1216{
1217 uint32_t phys_addr;
d4c430a8 1218 target_ulong page_size;
b5ff1b31 1219 int prot;
6ebbf390 1220 int ret, is_user;
b5ff1b31 1221
6ebbf390 1222 is_user = mmu_idx == MMU_USER_IDX;
d4c430a8
PB		 1223 ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot,
1224 &page_size);
b5ff1b31
FB		 1225 if (ret == 0) {
1226 /* Map a single [sub]page. */
1227 phys_addr &= ~(uint32_t)0x3ff;
1228 address &= ~(uint32_t)0x3ff;
3ad493fc 1229 tlb_set_page (env, address, phys_addr, prot, mmu_idx, page_size);
d4c430a8 1230 return 0;
b5ff1b31
FB		 1231 }
1232
1233 if (access_type == 2) {
1234 env->cp15.c5_insn = ret;
1235 env->cp15.c6_insn = address;
1236 env->exception_index = EXCP_PREFETCH_ABORT;
1237 } else {
1238 env->cp15.c5_data = ret;
9ee6e8bb
PB		 1239 if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6))
1240 env->cp15.c5_data |= (1 << 11);
b5ff1b31
FB		 1241 env->cp15.c6_data = address;
1242 env->exception_index = EXCP_DATA_ABORT;
1243 }
1244 return 1;
1245}
1246
c227f099 1247target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
b5ff1b31
FB		 1248{
1249 uint32_t phys_addr;
d4c430a8 1250 target_ulong page_size;
b5ff1b31
FB		 1251 int prot;
1252 int ret;
1253
d4c430a8 1254 ret = get_phys_addr(env, addr, 0, 0, &phys_addr, &prot, &page_size);
b5ff1b31
FB		 1255
1256 if (ret != 0)
1257 return -1;
1258
1259 return phys_addr;
1260}
1261
8984bd2e 1262void HELPER(set_cp)(CPUState *env, uint32_t insn, uint32_t val)
c1713132
AZ		 1263{
1264 int cp_num = (insn >> 8) & 0xf;
1265 int cp_info = (insn >> 5) & 7;
1266 int src = (insn >> 16) & 0xf;
1267 int operand = insn & 0xf;
1268
1269 if (env->cp[cp_num].cp_write)
1270 env->cp[cp_num].cp_write(env->cp[cp_num].opaque,
1271 cp_info, src, operand, val);
1272}
1273
8984bd2e 1274uint32_t HELPER(get_cp)(CPUState *env, uint32_t insn)
c1713132
AZ		 1275{
1276 int cp_num = (insn >> 8) & 0xf;
1277 int cp_info = (insn >> 5) & 7;
1278 int dest = (insn >> 16) & 0xf;
1279 int operand = insn & 0xf;
1280
1281 if (env->cp[cp_num].cp_read)
1282 return env->cp[cp_num].cp_read(env->cp[cp_num].opaque,
1283 cp_info, dest, operand);
1284 return 0;
1285}
1286
ce819861
PB		 1287/* Return basic MPU access permission bits. */
1288static uint32_t simple_mpu_ap_bits(uint32_t val)
1289{
1290 uint32_t ret;
1291 uint32_t mask;
1292 int i;
1293 ret = 0;
1294 mask = 3;
1295 for (i = 0; i < 16; i += 2) {
1296 ret |= (val >> i) & mask;
1297 mask <<= 2;
1298 }
1299 return ret;
1300}
1301
1302/* Pad basic MPU access permission bits to extended format. */
1303static uint32_t extended_mpu_ap_bits(uint32_t val)
1304{
1305 uint32_t ret;
1306 uint32_t mask;
1307 int i;
1308 ret = 0;
1309 mask = 3;
1310 for (i = 0; i < 16; i += 2) {
1311 ret |= (val & mask) << i;
1312 mask <<= 2;
1313 }
1314 return ret;
1315}
1316
8984bd2e 1317void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
b5ff1b31 1318{
9ee6e8bb
PB		 1319 int op1;
1320 int op2;
1321 int crm;
b5ff1b31 1322
9ee6e8bb 1323 op1 = (insn >> 21) & 7;
b5ff1b31 1324 op2 = (insn >> 5) & 7;
ce819861 1325 crm = insn & 0xf;
b5ff1b31 1326 switch ((insn >> 16) & 0xf) {
9ee6e8bb 1327 case 0:
9ee6e8bb 1328 /* ID codes. */
610c3c8a
AZ		 1329 if (arm_feature(env, ARM_FEATURE_XSCALE))
1330 break;
c3d2689d
AZ		 1331 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1332 break;
a49ea279
PB		 1333 if (arm_feature(env, ARM_FEATURE_V7)
1334 && op1 == 2 && crm == 0 && op2 == 0) {
1335 env->cp15.c0_cssel = val & 0xf;
1336 break;
1337 }
b5ff1b31
FB		 1338 goto bad_reg;
1339 case 1: /* System configuration. */
c3d2689d
AZ		 1340 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1341 op2 = 0;
b5ff1b31
FB		 1342 switch (op2) {
1343 case 0:
ce819861 1344 if (!arm_feature(env, ARM_FEATURE_XSCALE) || crm == 0)
c1713132 1345 env->cp15.c1_sys = val;
b5ff1b31
FB		 1346 /* ??? Lots of these bits are not implemented. */
1347 /* This may enable/disable the MMU, so do a TLB flush. */
1348 tlb_flush(env, 1);
1349 break;
9ee6e8bb 1350 case 1: /* Auxiliary cotrol register. */
610c3c8a
AZ		 1351 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1352 env->cp15.c1_xscaleauxcr = val;
c1713132 1353 break;
610c3c8a 1354 }
9ee6e8bb
PB		 1355 /* Not implemented. */
1356 break;
b5ff1b31 1357 case 2:
610c3c8a
AZ		 1358 if (arm_feature(env, ARM_FEATURE_XSCALE))
1359 goto bad_reg;
4be27dbb
PB		 1360 if (env->cp15.c1_coproc != val) {
1361 env->cp15.c1_coproc = val;
1362 /* ??? Is this safe when called from within a TB? */
1363 tb_flush(env);
1364 }
c1713132 1365 break;
b5ff1b31
FB		 1366 default:
1367 goto bad_reg;
1368 }
1369 break;
ce819861
PB		 1370 case 2: /* MMU Page table control / MPU cache control. */
1371 if (arm_feature(env, ARM_FEATURE_MPU)) {
1372 switch (op2) {
1373 case 0:
1374 env->cp15.c2_data = val;
1375 break;
1376 case 1:
1377 env->cp15.c2_insn = val;
1378 break;
1379 default:
1380 goto bad_reg;
1381 }
1382 } else {
9ee6e8bb
PB		 1383 switch (op2) {
1384 case 0:
1385 env->cp15.c2_base0 = val;
1386 break;
1387 case 1:
1388 env->cp15.c2_base1 = val;
1389 break;
1390 case 2:
b2fa1797
PB		 1391 val &= 7;
1392 env->cp15.c2_control = val;
9ee6e8bb 1393 env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> val);
b2fa1797 1394 env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> val);
9ee6e8bb
PB		 1395 break;
1396 default:
1397 goto bad_reg;
1398 }
ce819861 1399 }
b5ff1b31 1400 break;
ce819861 1401 case 3: /* MMU Domain access control / MPU write buffer control. */
b5ff1b31 1402 env->cp15.c3 = val;
405ee3ad 1403 tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */
b5ff1b31
FB		 1404 break;
1405 case 4: /* Reserved. */
1406 goto bad_reg;
ce819861 1407 case 5: /* MMU Fault status / MPU access permission. */
c3d2689d
AZ		 1408 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1409 op2 = 0;
b5ff1b31
FB		 1410 switch (op2) {
1411 case 0:
ce819861
PB		 1412 if (arm_feature(env, ARM_FEATURE_MPU))
1413 val = extended_mpu_ap_bits(val);
b5ff1b31
FB		 1414 env->cp15.c5_data = val;
1415 break;
1416 case 1:
ce819861
PB		 1417 if (arm_feature(env, ARM_FEATURE_MPU))
1418 val = extended_mpu_ap_bits(val);
b5ff1b31
FB		 1419 env->cp15.c5_insn = val;
1420 break;
ce819861
PB		 1421 case 2:
1422 if (!arm_feature(env, ARM_FEATURE_MPU))
1423 goto bad_reg;
1424 env->cp15.c5_data = val;
b5ff1b31 1425 break;
ce819861
PB		 1426 case 3:
1427 if (!arm_feature(env, ARM_FEATURE_MPU))
1428 goto bad_reg;
1429 env->cp15.c5_insn = val;
b5ff1b31
FB		 1430 break;
1431 default:
1432 goto bad_reg;
1433 }
1434 break;
ce819861
PB		 1435 case 6: /* MMU Fault address / MPU base/size. */
1436 if (arm_feature(env, ARM_FEATURE_MPU)) {
1437 if (crm >= 8)
1438 goto bad_reg;
1439 env->cp15.c6_region[crm] = val;
1440 } else {
c3d2689d
AZ		 1441 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1442 op2 = 0;
ce819861
PB		 1443 switch (op2) {
1444 case 0:
1445 env->cp15.c6_data = val;
1446 break;
9ee6e8bb
PB		 1447 case 1: /* ??? This is WFAR on armv6 */
1448 case 2:
ce819861
PB		 1449 env->cp15.c6_insn = val;
1450 break;
1451 default:
1452 goto bad_reg;
1453 }
1454 }
1455 break;
b5ff1b31 1456 case 7: /* Cache control. */
c3d2689d
AZ		 1457 env->cp15.c15_i_max = 0x000;
1458 env->cp15.c15_i_min = 0xff0;
f8bf8606
AL		 1459 if (op1 != 0) {
1460 goto bad_reg;
1461 }
1462 /* No cache, so nothing to do except VA->PA translations. */
1463 if (arm_feature(env, ARM_FEATURE_V6K)) {
1464 switch (crm) {
1465 case 4:
1466 if (arm_feature(env, ARM_FEATURE_V7)) {
1467 env->cp15.c7_par = val & 0xfffff6ff;
1468 } else {
1469 env->cp15.c7_par = val & 0xfffff1ff;
1470 }
1471 break;
1472 case 8: {
1473 uint32_t phys_addr;
1474 target_ulong page_size;
1475 int prot;
1476 int ret, is_user = op2 & 2;
1477 int access_type = op2 & 1;
1478
1479 if (op2 & 4) {
1480 /* Other states are only available with TrustZone */
1481 goto bad_reg;
1482 }
1483 ret = get_phys_addr(env, val, access_type, is_user,
1484 &phys_addr, &prot, &page_size);
1485 if (ret == 0) {
1486 /* We do not set any attribute bits in the PAR */
1487 if (page_size == (1 << 24)
1488 && arm_feature(env, ARM_FEATURE_V7)) {
1489 env->cp15.c7_par = (phys_addr & 0xff000000) | 1 << 1;
1490 } else {
1491 env->cp15.c7_par = phys_addr & 0xfffff000;
1492 }
1493 } else {
1494 env->cp15.c7_par = ((ret & (10 << 1)) >> 5) |
1495 ((ret & (12 << 1)) >> 6) |
1496 ((ret & 0xf) << 1) | 1;
1497 }
1498 break;
1499 }
1500 }
1501 }
b5ff1b31
FB		 1502 break;
1503 case 8: /* MMU TLB control. */
1504 switch (op2) {
1505 case 0: /* Invalidate all. */
1506 tlb_flush(env, 0);
1507 break;
1508 case 1: /* Invalidate single TLB entry. */
d4c430a8 1509 tlb_flush_page(env, val & TARGET_PAGE_MASK);
b5ff1b31 1510 break;
9ee6e8bb
PB		 1511 case 2: /* Invalidate on ASID. */
1512 tlb_flush(env, val == 0);
1513 break;
1514 case 3: /* Invalidate single entry on MVA. */
1515 /* ??? This is like case 1, but ignores ASID. */
1516 tlb_flush(env, 1);
1517 break;
b5ff1b31
FB		 1518 default:
1519 goto bad_reg;
1520 }
1521 break;
ce819861 1522 case 9:
c3d2689d
AZ		 1523 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1524 break;
ce819861
PB		 1525 switch (crm) {
1526 case 0: /* Cache lockdown. */
9ee6e8bb
PB		 1527 switch (op1) {
1528 case 0: /* L1 cache. */
1529 switch (op2) {
1530 case 0:
1531 env->cp15.c9_data = val;
1532 break;
1533 case 1:
1534 env->cp15.c9_insn = val;
1535 break;
1536 default:
1537 goto bad_reg;
1538 }
1539 break;
1540 case 1: /* L2 cache. */
1541 /* Ignore writes to L2 lockdown/auxiliary registers. */
1542 break;
1543 default:
1544 goto bad_reg;
1545 }
1546 break;
ce819861
PB		 1547 case 1: /* TCM memory region registers. */
1548 /* Not implemented. */
1549 goto bad_reg;
b5ff1b31
FB		 1550 default:
1551 goto bad_reg;
1552 }
1553 break;
1554 case 10: /* MMU TLB lockdown. */
1555 /* ??? TLB lockdown not implemented. */
1556 break;
b5ff1b31
FB		 1557 case 12: /* Reserved. */
1558 goto bad_reg;
1559 case 13: /* Process ID. */
1560 switch (op2) {
1561 case 0:
d07edbfa
PB		 1562 /* Unlike real hardware the qemu TLB uses virtual addresses,
1563 not modified virtual addresses, so this causes a TLB flush.
1564 */
1565 if (env->cp15.c13_fcse != val)
1566 tlb_flush(env, 1);
1567 env->cp15.c13_fcse = val;
b5ff1b31
FB		 1568 break;
1569 case 1:
d07edbfa 1570 /* This changes the ASID, so do a TLB flush. */
ce819861
PB		 1571 if (env->cp15.c13_context != val
1572 && !arm_feature(env, ARM_FEATURE_MPU))
d07edbfa
PB		 1573 tlb_flush(env, 0);
1574 env->cp15.c13_context = val;
b5ff1b31
FB		 1575 break;
1576 default:
1577 goto bad_reg;
1578 }
1579 break;
1580 case 14: /* Reserved. */
1581 goto bad_reg;
1582 case 15: /* Implementation specific. */
c1713132 1583 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
ce819861 1584 if (op2 == 0 && crm == 1) {
2e23213f
AZ		 1585 if (env->cp15.c15_cpar != (val & 0x3fff)) {
1586 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
1587 tb_flush(env);
1588 env->cp15.c15_cpar = val & 0x3fff;
1589 }
c1713132
AZ		 1590 break;
1591 }
1592 goto bad_reg;
1593 }
c3d2689d
AZ		 1594 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
1595 switch (crm) {
1596 case 0:
1597 break;
1598 case 1: /* Set TI925T configuration. */
1599 env->cp15.c15_ticonfig = val & 0xe7;
1600 env->cp15.c0_cpuid = (val & (1 << 5)) ? /* OS_TYPE bit */
1601 ARM_CPUID_TI915T : ARM_CPUID_TI925T;
1602 break;
1603 case 2: /* Set I_max. */
1604 env->cp15.c15_i_max = val;
1605 break;
1606 case 3: /* Set I_min. */
1607 env->cp15.c15_i_min = val;
1608 break;
1609 case 4: /* Set thread-ID. */
1610 env->cp15.c15_threadid = val & 0xffff;
1611 break;
1612 case 8: /* Wait-for-interrupt (deprecated). */
1613 cpu_interrupt(env, CPU_INTERRUPT_HALT);
1614 break;
1615 default:
1616 goto bad_reg;
1617 }
1618 }
b5ff1b31
FB		 1619 break;
1620 }
1621 return;
1622bad_reg:
1623 /* ??? For debugging only. Should raise illegal instruction exception. */
9ee6e8bb
PB		 1624 cpu_abort(env, "Unimplemented cp15 register write (c%d, c%d, {%d, %d})\n",
1625 (insn >> 16) & 0xf, crm, op1, op2);
b5ff1b31
FB		 1626}
1627
8984bd2e 1628uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
b5ff1b31 1629{
9ee6e8bb
PB		 1630 int op1;
1631 int op2;
1632 int crm;
b5ff1b31 1633
9ee6e8bb 1634 op1 = (insn >> 21) & 7;
b5ff1b31 1635 op2 = (insn >> 5) & 7;
c3d2689d 1636 crm = insn & 0xf;
b5ff1b31
FB		 1637 switch ((insn >> 16) & 0xf) {
1638 case 0: /* ID codes. */
9ee6e8bb
PB		 1639 switch (op1) {
1640 case 0:
1641 switch (crm) {
1642 case 0:
1643 switch (op2) {
1644 case 0: /* Device ID. */
1645 return env->cp15.c0_cpuid;
1646 case 1: /* Cache Type. */
1647 return env->cp15.c0_cachetype;
1648 case 2: /* TCM status. */
1649 return 0;
1650 case 3: /* TLB type register. */
1651 return 0; /* No lockable TLB entries. */
607b4b08
PM		 1652 case 5: /* MPIDR */
1653 /* The MPIDR was standardised in v7; prior to
1654 * this it was implemented only in the 11MPCore.
1655 * For all other pre-v7 cores it does not exist.
1656 */
1657 if (arm_feature(env, ARM_FEATURE_V7) ||
1658 ARM_CPUID(env) == ARM_CPUID_ARM11MPCORE) {
1659 int mpidr = env->cpu_index;
1660 /* We don't support setting cluster ID ([8..11])
1661 * so these bits always RAZ.
1662 */
1663 if (arm_feature(env, ARM_FEATURE_V7MP)) {
1664 mpidr |= (1 << 31);
1665 /* Cores which are uniprocessor (non-coherent)
1666 * but still implement the MP extensions set
1667 * bit 30. (For instance, A9UP.) However we do
1668 * not currently model any of those cores.
1669 */
1670 }
1671 return mpidr;
10055562 1672 }
607b4b08 1673 /* otherwise fall through to the unimplemented-reg case */
9ee6e8bb
PB		 1674 default:
1675 goto bad_reg;
1676 }
1677 case 1:
1678 if (!arm_feature(env, ARM_FEATURE_V6))
1679 goto bad_reg;
1680 return env->cp15.c0_c1[op2];
1681 case 2:
1682 if (!arm_feature(env, ARM_FEATURE_V6))
1683 goto bad_reg;
1684 return env->cp15.c0_c2[op2];
1685 case 3: case 4: case 5: case 6: case 7:
1686 return 0;
1687 default:
1688 goto bad_reg;
1689 }
1690 case 1:
1691 /* These registers aren't documented on arm11 cores. However
1692 Linux looks at them anyway. */
1693 if (!arm_feature(env, ARM_FEATURE_V6))
1694 goto bad_reg;
1695 if (crm != 0)
1696 goto bad_reg;
a49ea279
PB		 1697 if (!arm_feature(env, ARM_FEATURE_V7))
1698 return 0;
1699
1700 switch (op2) {
1701 case 0:
1702 return env->cp15.c0_ccsid[env->cp15.c0_cssel];
1703 case 1:
1704 return env->cp15.c0_clid;
1705 case 7:
1706 return 0;
1707 }
1708 goto bad_reg;
1709 case 2:
1710 if (op2 != 0 || crm != 0)
610c3c8a 1711 goto bad_reg;
a49ea279 1712 return env->cp15.c0_cssel;
9ee6e8bb
PB		 1713 default:
1714 goto bad_reg;
b5ff1b31
FB		 1715 }
1716 case 1: /* System configuration. */
c3d2689d
AZ		 1717 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1718 op2 = 0;
b5ff1b31
FB		 1719 switch (op2) {
1720 case 0: /* Control register. */
1721 return env->cp15.c1_sys;
1722 case 1: /* Auxiliary control register. */
c1713132 1723 if (arm_feature(env, ARM_FEATURE_XSCALE))
610c3c8a 1724 return env->cp15.c1_xscaleauxcr;
9ee6e8bb
PB		 1725 if (!arm_feature(env, ARM_FEATURE_AUXCR))
1726 goto bad_reg;
1727 switch (ARM_CPUID(env)) {
1728 case ARM_CPUID_ARM1026:
1729 return 1;
1730 case ARM_CPUID_ARM1136:
827df9f3 1731 case ARM_CPUID_ARM1136_R2:
9ee6e8bb
PB		 1732 return 7;
1733 case ARM_CPUID_ARM11MPCORE:
1734 return 1;
1735 case ARM_CPUID_CORTEXA8:
533d177a 1736 return 2;
10055562
PB		 1737 case ARM_CPUID_CORTEXA9:
1738 return 0;
9ee6e8bb
PB		 1739 default:
1740 goto bad_reg;
1741 }
b5ff1b31 1742 case 2: /* Coprocessor access register. */
610c3c8a
AZ		 1743 if (arm_feature(env, ARM_FEATURE_XSCALE))
1744 goto bad_reg;
b5ff1b31
FB		 1745 return env->cp15.c1_coproc;
1746 default:
1747 goto bad_reg;
1748 }
ce819861
PB		 1749 case 2: /* MMU Page table control / MPU cache control. */
1750 if (arm_feature(env, ARM_FEATURE_MPU)) {
1751 switch (op2) {
1752 case 0:
1753 return env->cp15.c2_data;
1754 break;
1755 case 1:
1756 return env->cp15.c2_insn;
1757 break;
1758 default:
1759 goto bad_reg;
1760 }
1761 } else {
9ee6e8bb
PB		 1762 switch (op2) {
1763 case 0:
1764 return env->cp15.c2_base0;
1765 case 1:
1766 return env->cp15.c2_base1;
1767 case 2:
b2fa1797 1768 return env->cp15.c2_control;
9ee6e8bb
PB		 1769 default:
1770 goto bad_reg;
1771 }
1772 }
ce819861 1773 case 3: /* MMU Domain access control / MPU write buffer control. */
b5ff1b31
FB		 1774 return env->cp15.c3;
1775 case 4: /* Reserved. */
1776 goto bad_reg;
ce819861 1777 case 5: /* MMU Fault status / MPU access permission. */
c3d2689d
AZ		 1778 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1779 op2 = 0;
b5ff1b31
FB		 1780 switch (op2) {
1781 case 0:
ce819861
PB		 1782 if (arm_feature(env, ARM_FEATURE_MPU))
1783 return simple_mpu_ap_bits(env->cp15.c5_data);
b5ff1b31
FB		 1784 return env->cp15.c5_data;
1785 case 1:
ce819861
PB		 1786 if (arm_feature(env, ARM_FEATURE_MPU))
1787 return simple_mpu_ap_bits(env->cp15.c5_data);
1788 return env->cp15.c5_insn;
1789 case 2:
1790 if (!arm_feature(env, ARM_FEATURE_MPU))
1791 goto bad_reg;
1792 return env->cp15.c5_data;
1793 case 3:
1794 if (!arm_feature(env, ARM_FEATURE_MPU))
1795 goto bad_reg;
b5ff1b31
FB		 1796 return env->cp15.c5_insn;
1797 default:
1798 goto bad_reg;
1799 }
9ee6e8bb 1800 case 6: /* MMU Fault address. */
ce819861 1801 if (arm_feature(env, ARM_FEATURE_MPU)) {
9ee6e8bb 1802 if (crm >= 8)
ce819861 1803 goto bad_reg;
9ee6e8bb 1804 return env->cp15.c6_region[crm];
ce819861 1805 } else {
c3d2689d
AZ		 1806 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1807 op2 = 0;
9ee6e8bb
PB		 1808 switch (op2) {
1809 case 0:
1810 return env->cp15.c6_data;
1811 case 1:
1812 if (arm_feature(env, ARM_FEATURE_V6)) {
1813 /* Watchpoint Fault Adrress. */
1814 return 0; /* Not implemented. */
1815 } else {
1816 /* Instruction Fault Adrress. */
1817 /* Arm9 doesn't have an IFAR, but implementing it anyway
1818 shouldn't do any harm. */
1819 return env->cp15.c6_insn;
1820 }
1821 case 2:
1822 if (arm_feature(env, ARM_FEATURE_V6)) {
1823 /* Instruction Fault Adrress. */
1824 return env->cp15.c6_insn;
1825 } else {
1826 goto bad_reg;
1827 }
1828 default:
1829 goto bad_reg;
1830 }
b5ff1b31
FB		 1831 }
1832 case 7: /* Cache control. */
f8bf8606
AL		 1833 if (crm == 4 && op1 == 0 && op2 == 0) {
1834 return env->cp15.c7_par;
1835 }
6fbe23d5
PB		 1836 /* FIXME: Should only clear Z flag if destination is r15. */
1837 env->ZF = 0;
b5ff1b31
FB		 1838 return 0;
1839 case 8: /* MMU TLB control. */
1840 goto bad_reg;
1841 case 9: /* Cache lockdown. */
9ee6e8bb
PB		 1842 switch (op1) {
1843 case 0: /* L1 cache. */
1844 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1845 return 0;
1846 switch (op2) {
1847 case 0:
1848 return env->cp15.c9_data;
1849 case 1:
1850 return env->cp15.c9_insn;
1851 default:
1852 goto bad_reg;
1853 }
1854 case 1: /* L2 cache */
1855 if (crm != 0)
1856 goto bad_reg;
1857 /* L2 Lockdown and Auxiliary control. */
c3d2689d 1858 return 0;
b5ff1b31
FB		 1859 default:
1860 goto bad_reg;
1861 }
1862 case 10: /* MMU TLB lockdown. */
1863 /* ??? TLB lockdown not implemented. */
1864 return 0;
1865 case 11: /* TCM DMA control. */
1866 case 12: /* Reserved. */
1867 goto bad_reg;
1868 case 13: /* Process ID. */
1869 switch (op2) {
1870 case 0:
1871 return env->cp15.c13_fcse;
1872 case 1:
1873 return env->cp15.c13_context;
1874 default:
1875 goto bad_reg;
1876 }
1877 case 14: /* Reserved. */
1878 goto bad_reg;
1879 case 15: /* Implementation specific. */
c1713132 1880 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
c3d2689d 1881 if (op2 == 0 && crm == 1)
c1713132
AZ		 1882 return env->cp15.c15_cpar;
1883
1884 goto bad_reg;
1885 }
c3d2689d
AZ		 1886 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
1887 switch (crm) {
1888 case 0:
1889 return 0;
1890 case 1: /* Read TI925T configuration. */
1891 return env->cp15.c15_ticonfig;
1892 case 2: /* Read I_max. */
1893 return env->cp15.c15_i_max;
1894 case 3: /* Read I_min. */
1895 return env->cp15.c15_i_min;
1896 case 4: /* Read thread-ID. */
1897 return env->cp15.c15_threadid;
1898 case 8: /* TI925T_status */
1899 return 0;
1900 }
827df9f3
AZ		 1901 /* TODO: Peripheral port remap register:
1902 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt
1903 * controller base address at $rn & ~0xfff and map size of
1904 * 0x200 << ($rn & 0xfff), when MMU is off. */
c3d2689d
AZ		 1905 goto bad_reg;
1906 }
b5ff1b31
FB		 1907 return 0;
1908 }
1909bad_reg:
1910 /* ??? For debugging only. Should raise illegal instruction exception. */
9ee6e8bb
PB		 1911 cpu_abort(env, "Unimplemented cp15 register read (c%d, c%d, {%d, %d})\n",
1912 (insn >> 16) & 0xf, crm, op1, op2);
b5ff1b31
FB		 1913 return 0;
1914}
1915
b0109805 1916void HELPER(set_r13_banked)(CPUState *env, uint32_t mode, uint32_t val)
9ee6e8bb 1917{
39ea3d4e
PM		 1918 if ((env->uncached_cpsr & CPSR_M) == mode) {
1919 env->regs[13] = val;
1920 } else {
1921 env->banked_r13[bank_number(mode)] = val;
1922 }
9ee6e8bb
PB		 1923}
1924
b0109805 1925uint32_t HELPER(get_r13_banked)(CPUState *env, uint32_t mode)
9ee6e8bb 1926{
39ea3d4e
PM		 1927 if ((env->uncached_cpsr & CPSR_M) == mode) {
1928 return env->regs[13];
1929 } else {
1930 return env->banked_r13[bank_number(mode)];
1931 }
9ee6e8bb
PB		 1932}
1933
8984bd2e 1934uint32_t HELPER(v7m_mrs)(CPUState *env, uint32_t reg)
9ee6e8bb
PB		 1935{
1936 switch (reg) {
1937 case 0: /* APSR */
1938 return xpsr_read(env) & 0xf8000000;
1939 case 1: /* IAPSR */
1940 return xpsr_read(env) & 0xf80001ff;
1941 case 2: /* EAPSR */
1942 return xpsr_read(env) & 0xff00fc00;
1943 case 3: /* xPSR */
1944 return xpsr_read(env) & 0xff00fdff;
1945 case 5: /* IPSR */
1946 return xpsr_read(env) & 0x000001ff;
1947 case 6: /* EPSR */
1948 return xpsr_read(env) & 0x0700fc00;
1949 case 7: /* IEPSR */
1950 return xpsr_read(env) & 0x0700edff;
1951 case 8: /* MSP */
1952 return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
1953 case 9: /* PSP */
1954 return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
1955 case 16: /* PRIMASK */
1956 return (env->uncached_cpsr & CPSR_I) != 0;
1957 case 17: /* FAULTMASK */
1958 return (env->uncached_cpsr & CPSR_F) != 0;
1959 case 18: /* BASEPRI */
1960 case 19: /* BASEPRI_MAX */
1961 return env->v7m.basepri;
1962 case 20: /* CONTROL */
1963 return env->v7m.control;
1964 default:
1965 /* ??? For debugging only. */
1966 cpu_abort(env, "Unimplemented system register read (%d)\n", reg);
1967 return 0;
1968 }
1969}
1970
8984bd2e 1971void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val)
9ee6e8bb
PB		 1972{
1973 switch (reg) {
1974 case 0: /* APSR */
1975 xpsr_write(env, val, 0xf8000000);
1976 break;
1977 case 1: /* IAPSR */
1978 xpsr_write(env, val, 0xf8000000);
1979 break;
1980 case 2: /* EAPSR */
1981 xpsr_write(env, val, 0xfe00fc00);
1982 break;
1983 case 3: /* xPSR */
1984 xpsr_write(env, val, 0xfe00fc00);
1985 break;
1986 case 5: /* IPSR */
1987 /* IPSR bits are readonly. */
1988 break;
1989 case 6: /* EPSR */
1990 xpsr_write(env, val, 0x0600fc00);
1991 break;
1992 case 7: /* IEPSR */
1993 xpsr_write(env, val, 0x0600fc00);
1994 break;
1995 case 8: /* MSP */
1996 if (env->v7m.current_sp)
1997 env->v7m.other_sp = val;
1998 else
1999 env->regs[13] = val;
2000 break;
2001 case 9: /* PSP */
2002 if (env->v7m.current_sp)
2003 env->regs[13] = val;
2004 else
2005 env->v7m.other_sp = val;
2006 break;
2007 case 16: /* PRIMASK */
2008 if (val & 1)
2009 env->uncached_cpsr |= CPSR_I;
2010 else
2011 env->uncached_cpsr &= ~CPSR_I;
2012 break;
2013 case 17: /* FAULTMASK */
2014 if (val & 1)
2015 env->uncached_cpsr |= CPSR_F;
2016 else
2017 env->uncached_cpsr &= ~CPSR_F;
2018 break;
2019 case 18: /* BASEPRI */
2020 env->v7m.basepri = val & 0xff;
2021 break;
2022 case 19: /* BASEPRI_MAX */
2023 val &= 0xff;
2024 if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
2025 env->v7m.basepri = val;
2026 break;
2027 case 20: /* CONTROL */
2028 env->v7m.control = val & 3;
2029 switch_v7m_sp(env, (val & 2) != 0);
2030 break;
2031 default:
2032 /* ??? For debugging only. */
2033 cpu_abort(env, "Unimplemented system register write (%d)\n", reg);
2034 return;
2035 }
2036}
2037
c1713132
AZ		 2038void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
2039 ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write,
2040 void *opaque)
2041{
2042 if (cpnum < 0 || cpnum > 14) {
2043 cpu_abort(env, "Bad coprocessor number: %i\n", cpnum);
2044 return;
2045 }
2046
2047 env->cp[cpnum].cp_read = cp_read;
2048 env->cp[cpnum].cp_write = cp_write;
2049 env->cp[cpnum].opaque = opaque;
2050}
2051
b5ff1b31 2052#endif
6ddbc6e4
PB		 2053
2054/* Note that signed overflow is undefined in C. The following routines are
2055 careful to use unsigned types where modulo arithmetic is required.
2056 Failure to do so _will_ break on newer gcc. */
2057
2058/* Signed saturating arithmetic. */
2059
1654b2d6 2060/* Perform 16-bit signed saturating addition. */
6ddbc6e4
PB		 2061static inline uint16_t add16_sat(uint16_t a, uint16_t b)
2062{
2063 uint16_t res;
2064
2065 res = a + b;
2066 if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
2067 if (a & 0x8000)
2068 res = 0x8000;
2069 else
2070 res = 0x7fff;
2071 }
2072 return res;
2073}
2074
1654b2d6 2075/* Perform 8-bit signed saturating addition. */
6ddbc6e4
PB		 2076static inline uint8_t add8_sat(uint8_t a, uint8_t b)
2077{
2078 uint8_t res;
2079
2080 res = a + b;
2081 if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
2082 if (a & 0x80)
2083 res = 0x80;
2084 else
2085 res = 0x7f;
2086 }
2087 return res;
2088}
2089
1654b2d6 2090/* Perform 16-bit signed saturating subtraction. */
6ddbc6e4
PB		 2091static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
2092{
2093 uint16_t res;
2094
2095 res = a - b;
2096 if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
2097 if (a & 0x8000)
2098 res = 0x8000;
2099 else
2100 res = 0x7fff;
2101 }
2102 return res;
2103}
2104
1654b2d6 2105/* Perform 8-bit signed saturating subtraction. */
6ddbc6e4
PB		 2106static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
2107{
2108 uint8_t res;
2109
2110 res = a - b;
2111 if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
2112 if (a & 0x80)
2113 res = 0x80;
2114 else
2115 res = 0x7f;
2116 }
2117 return res;
2118}
2119
2120#define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
2121#define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
2122#define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
2123#define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
2124#define PFX q
2125
2126#include "op_addsub.h"
2127
2128/* Unsigned saturating arithmetic. */
460a09c1 2129static inline uint16_t add16_usat(uint16_t a, uint16_t b)
6ddbc6e4
PB		 2130{
2131 uint16_t res;
2132 res = a + b;
2133 if (res < a)
2134 res = 0xffff;
2135 return res;
2136}
2137
460a09c1 2138static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
6ddbc6e4 2139{
4c4fd3f8 2140 if (a > b)
6ddbc6e4
PB		 2141 return a - b;
2142 else
2143 return 0;
2144}
2145
2146static inline uint8_t add8_usat(uint8_t a, uint8_t b)
2147{
2148 uint8_t res;
2149 res = a + b;
2150 if (res < a)
2151 res = 0xff;
2152 return res;
2153}
2154
2155static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
2156{
4c4fd3f8 2157 if (a > b)
6ddbc6e4
PB		 2158 return a - b;
2159 else
2160 return 0;
2161}
2162
2163#define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
2164#define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
2165#define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
2166#define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
2167#define PFX uq
2168
2169#include "op_addsub.h"
2170
2171/* Signed modulo arithmetic. */
2172#define SARITH16(a, b, n, op) do { \
2173 int32_t sum; \
db6e2e65 2174 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
6ddbc6e4
PB		 2175 RESULT(sum, n, 16); \
2176 if (sum >= 0) \
2177 ge |= 3 << (n * 2); \
2178 } while(0)
2179
2180#define SARITH8(a, b, n, op) do { \
2181 int32_t sum; \
db6e2e65 2182 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
6ddbc6e4
PB		 2183 RESULT(sum, n, 8); \
2184 if (sum >= 0) \
2185 ge |= 1 << n; \
2186 } while(0)
2187
2188
2189#define ADD16(a, b, n) SARITH16(a, b, n, +)
2190#define SUB16(a, b, n) SARITH16(a, b, n, -)
2191#define ADD8(a, b, n) SARITH8(a, b, n, +)
2192#define SUB8(a, b, n) SARITH8(a, b, n, -)
2193#define PFX s
2194#define ARITH_GE
2195
2196#include "op_addsub.h"
2197
2198/* Unsigned modulo arithmetic. */
2199#define ADD16(a, b, n) do { \
2200 uint32_t sum; \
2201 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
2202 RESULT(sum, n, 16); \
a87aa10b 2203 if ((sum >> 16) == 1) \
6ddbc6e4
PB		 2204 ge |= 3 << (n * 2); \
2205 } while(0)
2206
2207#define ADD8(a, b, n) do { \
2208 uint32_t sum; \
2209 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
2210 RESULT(sum, n, 8); \
a87aa10b
AZ		 2211 if ((sum >> 8) == 1) \
2212 ge |= 1 << n; \
6ddbc6e4
PB		 2213 } while(0)
2214
2215#define SUB16(a, b, n) do { \
2216 uint32_t sum; \
2217 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
2218 RESULT(sum, n, 16); \
2219 if ((sum >> 16) == 0) \
2220 ge |= 3 << (n * 2); \
2221 } while(0)
2222
2223#define SUB8(a, b, n) do { \
2224 uint32_t sum; \
2225 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
2226 RESULT(sum, n, 8); \
2227 if ((sum >> 8) == 0) \
a87aa10b 2228 ge |= 1 << n; \
6ddbc6e4
PB		 2229 } while(0)
2230
2231#define PFX u
2232#define ARITH_GE
2233
2234#include "op_addsub.h"
2235
2236/* Halved signed arithmetic. */
2237#define ADD16(a, b, n) \
2238 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
2239#define SUB16(a, b, n) \
2240 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
2241#define ADD8(a, b, n) \
2242 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
2243#define SUB8(a, b, n) \
2244 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
2245#define PFX sh
2246
2247#include "op_addsub.h"
2248
2249/* Halved unsigned arithmetic. */
2250#define ADD16(a, b, n) \
2251 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2252#define SUB16(a, b, n) \
2253 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2254#define ADD8(a, b, n) \
2255 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2256#define SUB8(a, b, n) \
2257 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2258#define PFX uh
2259
2260#include "op_addsub.h"
2261
2262static inline uint8_t do_usad(uint8_t a, uint8_t b)
2263{
2264 if (a > b)
2265 return a - b;
2266 else
2267 return b - a;
2268}
2269
2270/* Unsigned sum of absolute byte differences. */
2271uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
2272{
2273 uint32_t sum;
2274 sum = do_usad(a, b);
2275 sum += do_usad(a >> 8, b >> 8);
2276 sum += do_usad(a >> 16, b >>16);
2277 sum += do_usad(a >> 24, b >> 24);
2278 return sum;
2279}
2280
2281/* For ARMv6 SEL instruction. */
2282uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
2283{
2284 uint32_t mask;
2285
2286 mask = 0;
2287 if (flags & 1)
2288 mask |= 0xff;
2289 if (flags & 2)
2290 mask |= 0xff00;
2291 if (flags & 4)
2292 mask |= 0xff0000;
2293 if (flags & 8)
2294 mask |= 0xff000000;
2295 return (a & mask) | (b & ~mask);
2296}
2297
5e3f878a
PB		 2298uint32_t HELPER(logicq_cc)(uint64_t val)
2299{
2300 return (val >> 32) | (val != 0);
2301}
4373f3ce
PB		 2302
2303/* VFP support. We follow the convention used for VFP instrunctions:
2304 Single precition routines have a "s" suffix, double precision a
2305 "d" suffix. */
2306
2307/* Convert host exception flags to vfp form. */
2308static inline int vfp_exceptbits_from_host(int host_bits)
2309{
2310 int target_bits = 0;
2311
2312 if (host_bits & float_flag_invalid)
2313 target_bits |= 1;
2314 if (host_bits & float_flag_divbyzero)
2315 target_bits |= 2;
2316 if (host_bits & float_flag_overflow)
2317 target_bits |= 4;
2318 if (host_bits & float_flag_underflow)
2319 target_bits |= 8;
2320 if (host_bits & float_flag_inexact)
2321 target_bits |= 0x10;
cecd8504
PM		 2322 if (host_bits & float_flag_input_denormal)
2323 target_bits |= 0x80;
4373f3ce
PB		 2324 return target_bits;
2325}
2326
2327uint32_t HELPER(vfp_get_fpscr)(CPUState *env)
2328{
2329 int i;
2330 uint32_t fpscr;
2331
2332 fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
2333 | (env->vfp.vec_len << 16)
2334 | (env->vfp.vec_stride << 20);
2335 i = get_float_exception_flags(&env->vfp.fp_status);
3a492f3a 2336 i |= get_float_exception_flags(&env->vfp.standard_fp_status);
4373f3ce
PB		 2337 fpscr |= vfp_exceptbits_from_host(i);
2338 return fpscr;
2339}
2340
01653295
PM		 2341uint32_t vfp_get_fpscr(CPUState *env)
2342{
2343 return HELPER(vfp_get_fpscr)(env);
2344}
2345
4373f3ce
PB		 2346/* Convert vfp exception flags to target form. */
2347static inline int vfp_exceptbits_to_host(int target_bits)
2348{
2349 int host_bits = 0;
2350
2351 if (target_bits & 1)
2352 host_bits |= float_flag_invalid;
2353 if (target_bits & 2)
2354 host_bits |= float_flag_divbyzero;
2355 if (target_bits & 4)
2356 host_bits |= float_flag_overflow;
2357 if (target_bits & 8)
2358 host_bits |= float_flag_underflow;
2359 if (target_bits & 0x10)
2360 host_bits |= float_flag_inexact;
cecd8504
PM		 2361 if (target_bits & 0x80)
2362 host_bits |= float_flag_input_denormal;
4373f3ce
PB		 2363 return host_bits;
2364}
2365
2366void HELPER(vfp_set_fpscr)(CPUState *env, uint32_t val)
2367{
2368 int i;
2369 uint32_t changed;
2370
2371 changed = env->vfp.xregs[ARM_VFP_FPSCR];
2372 env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
2373 env->vfp.vec_len = (val >> 16) & 7;
2374 env->vfp.vec_stride = (val >> 20) & 3;
2375
2376 changed ^= val;
2377 if (changed & (3 << 22)) {
2378 i = (val >> 22) & 3;
2379 switch (i) {
2380 case 0:
2381 i = float_round_nearest_even;
2382 break;
2383 case 1:
2384 i = float_round_up;
2385 break;
2386 case 2:
2387 i = float_round_down;
2388 break;
2389 case 3:
2390 i = float_round_to_zero;
2391 break;
2392 }
2393 set_float_rounding_mode(i, &env->vfp.fp_status);
2394 }
cecd8504 2395 if (changed & (1 << 24)) {
fe76d976 2396 set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
cecd8504
PM		 2397 set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
2398 }
5c7908ed
PB		 2399 if (changed & (1 << 25))
2400 set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
4373f3ce 2401
b12c390b 2402 i = vfp_exceptbits_to_host(val);
4373f3ce 2403 set_float_exception_flags(i, &env->vfp.fp_status);
3a492f3a 2404 set_float_exception_flags(0, &env->vfp.standard_fp_status);
4373f3ce
PB		 2405}
2406
01653295
PM		 2407void vfp_set_fpscr(CPUState *env, uint32_t val)
2408{
2409 HELPER(vfp_set_fpscr)(env, val);
2410}
2411
4373f3ce
PB		 2412#define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
2413
2414#define VFP_BINOP(name) \
2415float32 VFP_HELPER(name, s)(float32 a, float32 b, CPUState *env) \
2416{ \
2417 return float32_ ## name (a, b, &env->vfp.fp_status); \
2418} \
2419float64 VFP_HELPER(name, d)(float64 a, float64 b, CPUState *env) \
2420{ \
2421 return float64_ ## name (a, b, &env->vfp.fp_status); \
2422}
2423VFP_BINOP(add)
2424VFP_BINOP(sub)
2425VFP_BINOP(mul)
2426VFP_BINOP(div)
2427#undef VFP_BINOP
2428
2429float32 VFP_HELPER(neg, s)(float32 a)
2430{
2431 return float32_chs(a);
2432}
2433
2434float64 VFP_HELPER(neg, d)(float64 a)
2435{
66230e0d 2436 return float64_chs(a);
4373f3ce
PB		 2437}
2438
2439float32 VFP_HELPER(abs, s)(float32 a)
2440{
2441 return float32_abs(a);
2442}
2443
2444float64 VFP_HELPER(abs, d)(float64 a)
2445{
66230e0d 2446 return float64_abs(a);
4373f3ce
PB		 2447}
2448
2449float32 VFP_HELPER(sqrt, s)(float32 a, CPUState *env)
2450{
2451 return float32_sqrt(a, &env->vfp.fp_status);
2452}
2453
2454float64 VFP_HELPER(sqrt, d)(float64 a, CPUState *env)
2455{
2456 return float64_sqrt(a, &env->vfp.fp_status);
2457}
2458
2459/* XXX: check quiet/signaling case */
2460#define DO_VFP_cmp(p, type) \
2461void VFP_HELPER(cmp, p)(type a, type b, CPUState *env) \
2462{ \
2463 uint32_t flags; \
2464 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
2465 case 0: flags = 0x6; break; \
2466 case -1: flags = 0x8; break; \
2467 case 1: flags = 0x2; break; \
2468 default: case 2: flags = 0x3; break; \
2469 } \
2470 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2471 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2472} \
2473void VFP_HELPER(cmpe, p)(type a, type b, CPUState *env) \
2474{ \
2475 uint32_t flags; \
2476 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
2477 case 0: flags = 0x6; break; \
2478 case -1: flags = 0x8; break; \
2479 case 1: flags = 0x2; break; \
2480 default: case 2: flags = 0x3; break; \
2481 } \
2482 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2483 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2484}
2485DO_VFP_cmp(s, float32)
2486DO_VFP_cmp(d, float64)
2487#undef DO_VFP_cmp
2488
2489/* Helper routines to perform bitwise copies between float and int. */
2490static inline float32 vfp_itos(uint32_t i)
2491{
2492 union {
2493 uint32_t i;
2494 float32 s;
2495 } v;
2496
2497 v.i = i;
2498 return v.s;
2499}
2500
2501static inline uint32_t vfp_stoi(float32 s)
2502{
2503 union {
2504 uint32_t i;
2505 float32 s;
2506 } v;
2507
2508 v.s = s;
2509 return v.i;
2510}
2511
2512static inline float64 vfp_itod(uint64_t i)
2513{
2514 union {
2515 uint64_t i;
2516 float64 d;
2517 } v;
2518
2519 v.i = i;
2520 return v.d;
2521}
2522
2523static inline uint64_t vfp_dtoi(float64 d)
2524{
2525 union {
2526 uint64_t i;
2527 float64 d;
2528 } v;
2529
2530 v.d = d;
2531 return v.i;
2532}
2533
2534/* Integer to float conversion. */
2535float32 VFP_HELPER(uito, s)(float32 x, CPUState *env)
2536{
2537 return uint32_to_float32(vfp_stoi(x), &env->vfp.fp_status);
2538}
2539
2540float64 VFP_HELPER(uito, d)(float32 x, CPUState *env)
2541{
2542 return uint32_to_float64(vfp_stoi(x), &env->vfp.fp_status);
2543}
2544
2545float32 VFP_HELPER(sito, s)(float32 x, CPUState *env)
2546{
2547 return int32_to_float32(vfp_stoi(x), &env->vfp.fp_status);
2548}
2549
2550float64 VFP_HELPER(sito, d)(float32 x, CPUState *env)
2551{
2552 return int32_to_float64(vfp_stoi(x), &env->vfp.fp_status);
2553}
2554
2555/* Float to integer conversion. */
2556float32 VFP_HELPER(toui, s)(float32 x, CPUState *env)
2557{
09d9487f
PM		 2558 if (float32_is_any_nan(x)) {
2559 return float32_zero;
2560 }
4373f3ce
PB		 2561 return vfp_itos(float32_to_uint32(x, &env->vfp.fp_status));
2562}
2563
2564float32 VFP_HELPER(toui, d)(float64 x, CPUState *env)
2565{
09d9487f
PM		 2566 if (float64_is_any_nan(x)) {
2567 return float32_zero;
2568 }
4373f3ce
PB		 2569 return vfp_itos(float64_to_uint32(x, &env->vfp.fp_status));
2570}
2571
2572float32 VFP_HELPER(tosi, s)(float32 x, CPUState *env)
2573{
09d9487f
PM		 2574 if (float32_is_any_nan(x)) {
2575 return float32_zero;
2576 }
4373f3ce
PB		 2577 return vfp_itos(float32_to_int32(x, &env->vfp.fp_status));
2578}
2579
2580float32 VFP_HELPER(tosi, d)(float64 x, CPUState *env)
2581{
09d9487f
PM		 2582 if (float64_is_any_nan(x)) {
2583 return float32_zero;
2584 }
4373f3ce
PB		 2585 return vfp_itos(float64_to_int32(x, &env->vfp.fp_status));
2586}
2587
2588float32 VFP_HELPER(touiz, s)(float32 x, CPUState *env)
2589{
09d9487f
PM		 2590 if (float32_is_any_nan(x)) {
2591 return float32_zero;
2592 }
4373f3ce
PB		 2593 return vfp_itos(float32_to_uint32_round_to_zero(x, &env->vfp.fp_status));
2594}
2595
2596float32 VFP_HELPER(touiz, d)(float64 x, CPUState *env)
2597{
09d9487f
PM		 2598 if (float64_is_any_nan(x)) {
2599 return float32_zero;
2600 }
4373f3ce
PB		 2601 return vfp_itos(float64_to_uint32_round_to_zero(x, &env->vfp.fp_status));
2602}
2603
2604float32 VFP_HELPER(tosiz, s)(float32 x, CPUState *env)
2605{
09d9487f
PM		 2606 if (float32_is_any_nan(x)) {
2607 return float32_zero;
2608 }
4373f3ce
PB		 2609 return vfp_itos(float32_to_int32_round_to_zero(x, &env->vfp.fp_status));
2610}
2611
2612float32 VFP_HELPER(tosiz, d)(float64 x, CPUState *env)
2613{
09d9487f
PM		 2614 if (float64_is_any_nan(x)) {
2615 return float32_zero;
2616 }
4373f3ce
PB		 2617 return vfp_itos(float64_to_int32_round_to_zero(x, &env->vfp.fp_status));
2618}
2619
2620/* floating point conversion */
2621float64 VFP_HELPER(fcvtd, s)(float32 x, CPUState *env)
2622{
2d627737
PM		 2623 float64 r = float32_to_float64(x, &env->vfp.fp_status);
2624 /* ARM requires that S<->D conversion of any kind of NaN generates
2625 * a quiet NaN by forcing the most significant frac bit to 1.
2626 */
2627 return float64_maybe_silence_nan(r);
4373f3ce
PB		 2628}
2629
2630float32 VFP_HELPER(fcvts, d)(float64 x, CPUState *env)
2631{
2d627737
PM		 2632 float32 r = float64_to_float32(x, &env->vfp.fp_status);
2633 /* ARM requires that S<->D conversion of any kind of NaN generates
2634 * a quiet NaN by forcing the most significant frac bit to 1.
2635 */
2636 return float32_maybe_silence_nan(r);
4373f3ce
PB		 2637}
2638
2639/* VFP3 fixed point conversion. */
2640#define VFP_CONV_FIX(name, p, ftype, itype, sign) \
2641ftype VFP_HELPER(name##to, p)(ftype x, uint32_t shift, CPUState *env) \
2642{ \
2643 ftype tmp; \
26a5e69a 2644 tmp = sign##int32_to_##ftype ((itype##_t)vfp_##p##toi(x), \
4373f3ce 2645 &env->vfp.fp_status); \
644ad806 2646 return ftype##_scalbn(tmp, -(int)shift, &env->vfp.fp_status); \
4373f3ce
PB		 2647} \
2648ftype VFP_HELPER(to##name, p)(ftype x, uint32_t shift, CPUState *env) \
2649{ \
2650 ftype tmp; \
09d9487f
PM		 2651 if (ftype##_is_any_nan(x)) { \
2652 return ftype##_zero; \
2653 } \
4373f3ce 2654 tmp = ftype##_scalbn(x, shift, &env->vfp.fp_status); \
72f24d15 2655 return vfp_ito##p(ftype##_to_##itype##_round_to_zero(tmp, \
4373f3ce
PB		 2656 &env->vfp.fp_status)); \
2657}
2658
2659VFP_CONV_FIX(sh, d, float64, int16, )
2660VFP_CONV_FIX(sl, d, float64, int32, )
2661VFP_CONV_FIX(uh, d, float64, uint16, u)
2662VFP_CONV_FIX(ul, d, float64, uint32, u)
2663VFP_CONV_FIX(sh, s, float32, int16, )
2664VFP_CONV_FIX(sl, s, float32, int32, )
2665VFP_CONV_FIX(uh, s, float32, uint16, u)
2666VFP_CONV_FIX(ul, s, float32, uint32, u)
2667#undef VFP_CONV_FIX
2668
60011498 2669/* Half precision conversions. */
2d981da7 2670static float32 do_fcvt_f16_to_f32(uint32_t a, CPUState *env, float_status *s)
60011498 2671{
60011498 2672 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
fb91678d
PM		 2673 float32 r = float16_to_float32(make_float16(a), ieee, s);
2674 if (ieee) {
2675 return float32_maybe_silence_nan(r);
2676 }
2677 return r;
60011498
PB		 2678}
2679
2d981da7 2680static uint32_t do_fcvt_f32_to_f16(float32 a, CPUState *env, float_status *s)
60011498 2681{
60011498 2682 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
fb91678d
PM		 2683 float16 r = float32_to_float16(a, ieee, s);
2684 if (ieee) {
2685 r = float16_maybe_silence_nan(r);
2686 }
2687 return float16_val(r);
60011498
PB		 2688}
2689
2d981da7
PM		 2690float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUState *env)
2691{
2692 return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
2693}
2694
2695uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUState *env)
2696{
2697 return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
2698}
2699
2700float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUState *env)
2701{
2702 return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
2703}
2704
2705uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUState *env)
2706{
2707 return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
2708}
2709
4373f3ce
PB		 2710float32 HELPER(recps_f32)(float32 a, float32 b, CPUState *env)
2711{
2712 float_status *s = &env->vfp.fp_status;
2713 float32 two = int32_to_float32(2, s);
2714 return float32_sub(two, float32_mul(a, b, s), s);
2715}
2716
2717float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUState *env)
2718{
71826966 2719 float_status *s = &env->vfp.standard_fp_status;
9ea62f57 2720 float32 two = int32_to_float32(2, s);
4373f3ce 2721 float32 three = int32_to_float32(3, s);
9ea62f57
PM		 2722 float32 product;
2723 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
2724 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
2725 product = float32_zero;
2726 } else {
2727 product = float32_mul(a, b, s);
2728 }
2729 return float32_div(float32_sub(three, product, s), two, s);
4373f3ce
PB		 2730}
2731
8f8e3aa4
PB		 2732/* NEON helpers. */
2733
56bf4fe2
CL		 2734/* Constants 256 and 512 are used in some helpers; we avoid relying on
2735 * int->float conversions at run-time. */
2736#define float64_256 make_float64(0x4070000000000000LL)
2737#define float64_512 make_float64(0x4080000000000000LL)
2738
fe0e4872
CL		 2739/* The algorithm that must be used to calculate the estimate
2740 * is specified by the ARM ARM.
2741 */
2742static float64 recip_estimate(float64 a, CPUState *env)
2743{
2744 float_status *s = &env->vfp.standard_fp_status;
2745 /* q = (int)(a * 512.0) */
2746 float64 q = float64_mul(float64_512, a, s);
2747 int64_t q_int = float64_to_int64_round_to_zero(q, s);
2748
2749 /* r = 1.0 / (((double)q + 0.5) / 512.0) */
2750 q = int64_to_float64(q_int, s);
2751 q = float64_add(q, float64_half, s);
2752 q = float64_div(q, float64_512, s);
2753 q = float64_div(float64_one, q, s);
2754
2755 /* s = (int)(256.0 * r + 0.5) */
2756 q = float64_mul(q, float64_256, s);
2757 q = float64_add(q, float64_half, s);
2758 q_int = float64_to_int64_round_to_zero(q, s);
2759
2760 /* return (double)s / 256.0 */
2761 return float64_div(int64_to_float64(q_int, s), float64_256, s);
2762}
2763
4373f3ce
PB		 2764float32 HELPER(recpe_f32)(float32 a, CPUState *env)
2765{
fe0e4872
CL		 2766 float_status *s = &env->vfp.standard_fp_status;
2767 float64 f64;
2768 uint32_t val32 = float32_val(a);
2769
2770 int result_exp;
2771 int a_exp = (val32 & 0x7f800000) >> 23;
2772 int sign = val32 & 0x80000000;
2773
2774 if (float32_is_any_nan(a)) {
2775 if (float32_is_signaling_nan(a)) {
2776 float_raise(float_flag_invalid, s);
2777 }
2778 return float32_default_nan;
2779 } else if (float32_is_infinity(a)) {
2780 return float32_set_sign(float32_zero, float32_is_neg(a));
2781 } else if (float32_is_zero_or_denormal(a)) {
2782 float_raise(float_flag_divbyzero, s);
2783 return float32_set_sign(float32_infinity, float32_is_neg(a));
2784 } else if (a_exp >= 253) {
2785 float_raise(float_flag_underflow, s);
2786 return float32_set_sign(float32_zero, float32_is_neg(a));
2787 }
2788
2789 f64 = make_float64((0x3feULL << 52)
2790 | ((int64_t)(val32 & 0x7fffff) << 29));
2791
2792 result_exp = 253 - a_exp;
2793
2794 f64 = recip_estimate(f64, env);
2795
2796 val32 = sign
2797 | ((result_exp & 0xff) << 23)
2798 | ((float64_val(f64) >> 29) & 0x7fffff);
2799 return make_float32(val32);
4373f3ce
PB		 2800}
2801
e07be5d2
CL		 2802/* The algorithm that must be used to calculate the estimate
2803 * is specified by the ARM ARM.
2804 */
2805static float64 recip_sqrt_estimate(float64 a, CPUState *env)
2806{
2807 float_status *s = &env->vfp.standard_fp_status;
2808 float64 q;
2809 int64_t q_int;
2810
2811 if (float64_lt(a, float64_half, s)) {
2812 /* range 0.25 <= a < 0.5 */
2813
2814 /* a in units of 1/512 rounded down */
2815 /* q0 = (int)(a * 512.0); */
2816 q = float64_mul(float64_512, a, s);
2817 q_int = float64_to_int64_round_to_zero(q, s);
2818
2819 /* reciprocal root r */
2820 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
2821 q = int64_to_float64(q_int, s);
2822 q = float64_add(q, float64_half, s);
2823 q = float64_div(q, float64_512, s);
2824 q = float64_sqrt(q, s);
2825 q = float64_div(float64_one, q, s);
2826 } else {
2827 /* range 0.5 <= a < 1.0 */
2828
2829 /* a in units of 1/256 rounded down */
2830 /* q1 = (int)(a * 256.0); */
2831 q = float64_mul(float64_256, a, s);
2832 int64_t q_int = float64_to_int64_round_to_zero(q, s);
2833
2834 /* reciprocal root r */
2835 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
2836 q = int64_to_float64(q_int, s);
2837 q = float64_add(q, float64_half, s);
2838 q = float64_div(q, float64_256, s);
2839 q = float64_sqrt(q, s);
2840 q = float64_div(float64_one, q, s);
2841 }
2842 /* r in units of 1/256 rounded to nearest */
2843 /* s = (int)(256.0 * r + 0.5); */
2844
2845 q = float64_mul(q, float64_256,s );
2846 q = float64_add(q, float64_half, s);
2847 q_int = float64_to_int64_round_to_zero(q, s);
2848
2849 /* return (double)s / 256.0;*/
2850 return float64_div(int64_to_float64(q_int, s), float64_256, s);
2851}
2852
4373f3ce
PB		 2853float32 HELPER(rsqrte_f32)(float32 a, CPUState *env)
2854{
e07be5d2
CL		 2855 float_status *s = &env->vfp.standard_fp_status;
2856 int result_exp;
2857 float64 f64;
2858 uint32_t val;
2859 uint64_t val64;
2860
2861 val = float32_val(a);
2862
2863 if (float32_is_any_nan(a)) {
2864 if (float32_is_signaling_nan(a)) {
2865 float_raise(float_flag_invalid, s);
2866 }
2867 return float32_default_nan;
2868 } else if (float32_is_zero_or_denormal(a)) {
2869 float_raise(float_flag_divbyzero, s);
2870 return float32_set_sign(float32_infinity, float32_is_neg(a));
2871 } else if (float32_is_neg(a)) {
2872 float_raise(float_flag_invalid, s);
2873 return float32_default_nan;
2874 } else if (float32_is_infinity(a)) {
2875 return float32_zero;
2876 }
2877
2878 /* Normalize to a double-precision value between 0.25 and 1.0,
2879 * preserving the parity of the exponent. */
2880 if ((val & 0x800000) == 0) {
2881 f64 = make_float64(((uint64_t)(val & 0x80000000) << 32)
2882 | (0x3feULL << 52)
2883 | ((uint64_t)(val & 0x7fffff) << 29));
2884 } else {
2885 f64 = make_float64(((uint64_t)(val & 0x80000000) << 32)
2886 | (0x3fdULL << 52)
2887 | ((uint64_t)(val & 0x7fffff) << 29));
2888 }
2889
2890 result_exp = (380 - ((val & 0x7f800000) >> 23)) / 2;
2891
2892 f64 = recip_sqrt_estimate(f64, env);
2893
2894 val64 = float64_val(f64);
2895
2896 val = ((val64 >> 63) & 0x80000000)
2897 | ((result_exp & 0xff) << 23)
2898 | ((val64 >> 29) & 0x7fffff);
2899 return make_float32(val);
4373f3ce
PB		 2900}
2901
2902uint32_t HELPER(recpe_u32)(uint32_t a, CPUState *env)
2903{
fe0e4872
CL		 2904 float64 f64;
2905
2906 if ((a & 0x80000000) == 0) {
2907 return 0xffffffff;
2908 }
2909
2910 f64 = make_float64((0x3feULL << 52)
2911 | ((int64_t)(a & 0x7fffffff) << 21));
2912
2913 f64 = recip_estimate (f64, env);
2914
2915 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
4373f3ce
PB		 2916}
2917
2918uint32_t HELPER(rsqrte_u32)(uint32_t a, CPUState *env)
2919{
e07be5d2
CL		 2920 float64 f64;
2921
2922 if ((a & 0xc0000000) == 0) {
2923 return 0xffffffff;
2924 }
2925
2926 if (a & 0x80000000) {
2927 f64 = make_float64((0x3feULL << 52)
2928 | ((uint64_t)(a & 0x7fffffff) << 21));
2929 } else { /* bits 31-30 == '01' */
2930 f64 = make_float64((0x3fdULL << 52)
2931 | ((uint64_t)(a & 0x3fffffff) << 22));
2932 }
2933
2934 f64 = recip_sqrt_estimate(f64, env);
2935
2936 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
4373f3ce 2937}
fe1479c3
PB		 2938
2939void HELPER(set_teecr)(CPUState *env, uint32_t val)
2940{
2941 val &= 1;
2942 if (env->teecr != val) {
2943 env->teecr = val;
2944 tb_flush(env);
2945 }
2946}
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