]> Git Repo - qemu.git/blame - hw/ppc/spapr.c
projects / qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
spapr: Maximum (HPT) pagesize property
[qemu.git] / hw / ppc / spapr.c
CommitLineData
9fdf0c29
DG		 1/*
2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
3 *
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 *
26 */
0d75590d 27#include "qemu/osdep.h"
da34e65c 28#include "qapi/error.h"
fa98fbfc 29#include "qapi/visitor.h"
9c17d615 30#include "sysemu/sysemu.h"
e35704ba 31#include "sysemu/numa.h"
83c9f4ca 32#include "hw/hw.h"
03dd024f 33#include "qemu/log.h"
71461b0f 34#include "hw/fw-path-provider.h"
9fdf0c29 35#include "elf.h"
1422e32d 36#include "net/net.h"
ad440b4a 37#include "sysemu/device_tree.h"
9c17d615 38#include "sysemu/cpus.h"
b3946626 39#include "sysemu/hw_accel.h"
e97c3636 40#include "kvm_ppc.h"
c4b63b7c 41#include "migration/misc.h"
84a899de 42#include "migration/global_state.h"
f2a8f0a6 43#include "migration/register.h"
4be21d56 44#include "mmu-hash64.h"
b4db5413 45#include "mmu-book3s-v3.h"
7abd43ba 46#include "cpu-models.h"
3794d548 47#include "qom/cpu.h"
9fdf0c29
DG		 48
49#include "hw/boards.h"
0d09e41a 50#include "hw/ppc/ppc.h"
9fdf0c29
DG		 51#include "hw/loader.h"
52
7804c353 53#include "hw/ppc/fdt.h"
0d09e41a
PB		 54#include "hw/ppc/spapr.h"
55#include "hw/ppc/spapr_vio.h"
56#include "hw/pci-host/spapr.h"
57#include "hw/ppc/xics.h"
a2cb15b0 58#include "hw/pci/msi.h"
9fdf0c29 59
83c9f4ca 60#include "hw/pci/pci.h"
71461b0f
AK		 61#include "hw/scsi/scsi.h"
62#include "hw/virtio/virtio-scsi.h"
c4e13492 63#include "hw/virtio/vhost-scsi-common.h"
f61b4bed 64
022c62cb 65#include "exec/address-spaces.h"
2309832a 66#include "exec/ram_addr.h"
35139a59 67#include "hw/usb.h"
1de7afc9 68#include "qemu/config-file.h"
135a129a 69#include "qemu/error-report.h"
2a6593cb 70#include "trace.h"
34316482 71#include "hw/nmi.h"
6449da45 72#include "hw/intc/intc.h"
890c2b77 73
68a27b20 74#include "hw/compat.h"
f348b6d1 75#include "qemu/cutils.h"
94a94e4c 76#include "hw/ppc/spapr_cpu_core.h"
2cc0e2e8 77#include "hw/mem/memory-device.h"
68a27b20 78
9fdf0c29
DG		 79#include <libfdt.h>
80
4d8d5467
BH		 81/* SLOF memory layout:
82 *
83 * SLOF raw image loaded at 0, copies its romfs right below the flat
84 * device-tree, then position SLOF itself 31M below that
85 *
86 * So we set FW_OVERHEAD to 40MB which should account for all of that
87 * and more
88 *
89 * We load our kernel at 4M, leaving space for SLOF initial image
90 */
38b02bd8 91#define FDT_MAX_SIZE 0x100000
39ac8455 92#define RTAS_MAX_SIZE 0x10000
b7d1f77a 93#define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */
a9f8ad8f
DG		 94#define FW_MAX_SIZE 0x400000
95#define FW_FILE_NAME "slof.bin"
4d8d5467
BH		 96#define FW_OVERHEAD 0x2800000
97#define KERNEL_LOAD_ADDR FW_MAX_SIZE
a9f8ad8f 98
4d8d5467 99#define MIN_RMA_SLOF 128UL
9fdf0c29 100
0c103f8e
DG		 101#define PHANDLE_XICP 0x00001111
102
5d0fb150
GK		 103/* These two functions implement the VCPU id numbering: one to compute them
104 * all and one to identify thread 0 of a VCORE. Any change to the first one
105 * is likely to have an impact on the second one, so let's keep them close.
106 */
107static int spapr_vcpu_id(sPAPRMachineState *spapr, int cpu_index)
108{
1a5008fc 109 assert(spapr->vsmt);
5d0fb150
GK		 110 return
111 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads;
112}
113static bool spapr_is_thread0_in_vcore(sPAPRMachineState *spapr,
114 PowerPCCPU *cpu)
115{
1a5008fc 116 assert(spapr->vsmt);
5d0fb150
GK		 117 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0;
118}
119
71cd4dac
CLG		 120static ICSState *spapr_ics_create(sPAPRMachineState *spapr,
121 const char *type_ics,
122 int nr_irqs, Error **errp)
c04d6cfa 123{
175d2aa0 124 Error *local_err = NULL;
71cd4dac 125 Object *obj;
4e4169f7 126
71cd4dac 127 obj = object_new(type_ics);
175d2aa0 128 object_property_add_child(OBJECT(spapr), "ics", obj, &error_abort);
ad265631
GK		 129 object_property_add_const_link(obj, ICS_PROP_XICS, OBJECT(spapr),
130 &error_abort);
175d2aa0
GK		 131 object_property_set_int(obj, nr_irqs, "nr-irqs", &local_err);
132 if (local_err) {
133 goto error;
134 }
71cd4dac 135 object_property_set_bool(obj, true, "realized", &local_err);
175d2aa0
GK		 136 if (local_err) {
137 goto error;
4e4169f7 138 }
4e4169f7 139
71cd4dac 140 return ICS_SIMPLE(obj);
175d2aa0
GK		 141
142error:
143 error_propagate(errp, local_err);
144 return NULL;
c04d6cfa
AL		 145}
146
46f7afa3
GK		 147static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque)
148{
149 /* Dummy entries correspond to unused ICPState objects in older QEMUs,
150 * and newer QEMUs don't even have them. In both cases, we don't want
151 * to send anything on the wire.
152 */
153 return false;
154}
155
156static const VMStateDescription pre_2_10_vmstate_dummy_icp = {
157 .name = "icp/server",
158 .version_id = 1,
159 .minimum_version_id = 1,
160 .needed = pre_2_10_vmstate_dummy_icp_needed,
161 .fields = (VMStateField[]) {
162 VMSTATE_UNUSED(4), /* uint32_t xirr */
163 VMSTATE_UNUSED(1), /* uint8_t pending_priority */
164 VMSTATE_UNUSED(1), /* uint8_t mfrr */
165 VMSTATE_END_OF_LIST()
166 },
167};
168
169static void pre_2_10_vmstate_register_dummy_icp(int i)
170{
171 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp,
172 (void *)(uintptr_t) i);
173}
174
175static void pre_2_10_vmstate_unregister_dummy_icp(int i)
176{
177 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp,
178 (void *)(uintptr_t) i);
179}
180
72194664 181static int xics_max_server_number(sPAPRMachineState *spapr)
46f7afa3 182{
1a5008fc 183 assert(spapr->vsmt);
72194664 184 return DIV_ROUND_UP(max_cpus * spapr->vsmt, smp_threads);
46f7afa3
GK		 185}
186
71cd4dac 187static void xics_system_init(MachineState *machine, int nr_irqs, Error **errp)
c04d6cfa 188{
71cd4dac 189 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
844afc54 190 Error *local_err = NULL;
c04d6cfa 191
11ad93f6 192 if (kvm_enabled()) {
2192a930 193 if (machine_kernel_irqchip_allowed(machine) &&
844afc54 194 !xics_kvm_init(spapr, &local_err)) {
71cd4dac 195 spapr->icp_type = TYPE_KVM_ICP;
844afc54
GK		 196 spapr->ics = spapr_ics_create(spapr, TYPE_ICS_KVM, nr_irqs,
197 &local_err);
11ad93f6 198 }
71cd4dac 199 if (machine_kernel_irqchip_required(machine) && !spapr->ics) {
844afc54
GK		 200 error_prepend(&local_err,
201 "kernel_irqchip requested but unavailable: ");
202 goto error;
11ad93f6 203 }
844afc54
GK		 204 error_free(local_err);
205 local_err = NULL;
11ad93f6
DG		 206 }
207
71cd4dac 208 if (!spapr->ics) {
f63ebfe0 209 xics_spapr_init(spapr);
71cd4dac 210 spapr->icp_type = TYPE_ICP;
844afc54
GK		 211 spapr->ics = spapr_ics_create(spapr, TYPE_ICS_SIMPLE, nr_irqs,
212 &local_err);
c04d6cfa 213 }
844afc54
GK		 214
215error:
216 error_propagate(errp, local_err);
c04d6cfa
AL		 217}
218
833d4668
AK		 219static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
220 int smt_threads)
221{
222 int i, ret = 0;
223 uint32_t servers_prop[smt_threads];
224 uint32_t gservers_prop[smt_threads * 2];
14bb4486 225 int index = spapr_get_vcpu_id(cpu);
833d4668 226
d6e166c0
DG		 227 if (cpu->compat_pvr) {
228 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr);
6d9412ea
AK		 229 if (ret < 0) {
230 return ret;
231 }
232 }
233
833d4668
AK		 234 /* Build interrupt servers and gservers properties */
235 for (i = 0; i < smt_threads; i++) {
236 servers_prop[i] = cpu_to_be32(index + i);
237 /* Hack, direct the group queues back to cpu 0 */
238 gservers_prop[i*2] = cpu_to_be32(index + i);
239 gservers_prop[i*2 + 1] = 0;
240 }
241 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
242 servers_prop, sizeof(servers_prop));
243 if (ret < 0) {
244 return ret;
245 }
246 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s",
247 gservers_prop, sizeof(gservers_prop));
248
249 return ret;
250}
251
99861ecb 252static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu)
0da6f3fe 253{
14bb4486 254 int index = spapr_get_vcpu_id(cpu);
0da6f3fe
BR		 255 uint32_t associativity[] = {cpu_to_be32(0x5),
256 cpu_to_be32(0x0),
257 cpu_to_be32(0x0),
258 cpu_to_be32(0x0),
15f8b142 259 cpu_to_be32(cpu->node_id),
0da6f3fe
BR		 260 cpu_to_be32(index)};
261
262 /* Advertise NUMA via ibm,associativity */
99861ecb 263 return fdt_setprop(fdt, offset, "ibm,associativity", associativity,
0da6f3fe 264 sizeof(associativity));
0da6f3fe
BR		 265}
266
86d5771a 267/* Populate the "ibm,pa-features" property */
ee76a09f
DG		 268static void spapr_populate_pa_features(sPAPRMachineState *spapr,
269 PowerPCCPU *cpu,
270 void *fdt, int offset,
7abd43ba 271 bool legacy_guest)
86d5771a
SB		 272{
273 uint8_t pa_features_206[] = { 6, 0,
274 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
275 uint8_t pa_features_207[] = { 24, 0,
276 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
277 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
278 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
279 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
9fb4541f
SB		 280 uint8_t pa_features_300[] = { 66, 0,
281 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
282 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */
283 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */
284 /* 6: DS207 */
285 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
286 /* 16: Vector */
86d5771a 287 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
9fb4541f 288 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */
9bf502fe 289 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
9fb4541f
SB		 290 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
291 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
292 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */
293 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
294 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */
295 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */
296 /* 42: PM, 44: PC RA, 46: SC vec'd */
297 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
298 /* 48: SIMD, 50: QP BFP, 52: String */
299 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
300 /* 54: DecFP, 56: DecI, 58: SHA */
301 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
302 /* 60: NM atomic, 62: RNG */
303 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
304 };
7abd43ba 305 uint8_t *pa_features = NULL;
86d5771a
SB		 306 size_t pa_size;
307
7abd43ba 308 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) {
86d5771a
SB		 309 pa_features = pa_features_206;
310 pa_size = sizeof(pa_features_206);
7abd43ba
SJS		 311 }
312 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) {
86d5771a
SB		 313 pa_features = pa_features_207;
314 pa_size = sizeof(pa_features_207);
7abd43ba
SJS		 315 }
316 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) {
86d5771a
SB		 317 pa_features = pa_features_300;
318 pa_size = sizeof(pa_features_300);
7abd43ba
SJS		 319 }
320 if (!pa_features) {
86d5771a
SB		 321 return;
322 }
323
26cd35b8 324 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) {
86d5771a
SB		 325 /*
326 * Note: we keep CI large pages off by default because a 64K capable
327 * guest provisioned with large pages might otherwise try to map a qemu
328 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages
329 * even if that qemu runs on a 4k host.
330 * We dd this bit back here if we are confident this is not an issue
331 */
332 pa_features[3] |= 0x20;
333 }
4e5fe368 334 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) {
86d5771a
SB		 335 pa_features[24] |= 0x80; /* Transactional memory support */
336 }
e957f6a9
SB		 337 if (legacy_guest && pa_size > 40) {
338 /* Workaround for broken kernels that attempt (guest) radix
339 * mode when they can't handle it, if they see the radix bit set
340 * in pa-features. So hide it from them. */
341 pa_features[40 + 2] &= ~0x80; /* Radix MMU */
342 }
86d5771a
SB		 343
344 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size)));
345}
346
28e02042 347static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr)
6e806cc3 348{
82677ed2
AK		 349 int ret = 0, offset, cpus_offset;
350 CPUState *cs;
6e806cc3 351 char cpu_model[32];
7f763a5d 352 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
6e806cc3 353
82677ed2
AK		 354 CPU_FOREACH(cs) {
355 PowerPCCPU *cpu = POWERPC_CPU(cs);
356 DeviceClass *dc = DEVICE_GET_CLASS(cs);
14bb4486 357 int index = spapr_get_vcpu_id(cpu);
abbc1247 358 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu));
6e806cc3 359
5d0fb150 360 if (!spapr_is_thread0_in_vcore(spapr, cpu)) {
6e806cc3
BR		 361 continue;
362 }
363
82677ed2 364 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index);
6e806cc3 365
82677ed2
AK		 366 cpus_offset = fdt_path_offset(fdt, "/cpus");
367 if (cpus_offset < 0) {
a4f3885c 368 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
82677ed2
AK		 369 if (cpus_offset < 0) {
370 return cpus_offset;
371 }
372 }
373 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model);
6e806cc3 374 if (offset < 0) {
82677ed2
AK		 375 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model);
376 if (offset < 0) {
377 return offset;
378 }
6e806cc3
BR		 379 }
380
7f763a5d
DG		 381 ret = fdt_setprop(fdt, offset, "ibm,pft-size",
382 pft_size_prop, sizeof(pft_size_prop));
6e806cc3
BR		 383 if (ret < 0) {
384 return ret;
385 }
833d4668 386
99861ecb
IM		 387 if (nb_numa_nodes > 1) {
388 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cpu);
389 if (ret < 0) {
390 return ret;
391 }
0da6f3fe
BR		 392 }
393
12dbeb16 394 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt);
833d4668
AK		 395 if (ret < 0) {
396 return ret;
397 }
e957f6a9 398
ee76a09f
DG		 399 spapr_populate_pa_features(spapr, cpu, fdt, offset,
400 spapr->cas_legacy_guest_workaround);
6e806cc3
BR		 401 }
402 return ret;
403}
404
c86c1aff 405static hwaddr spapr_node0_size(MachineState *machine)
b082d65a
AK		 406{
407 if (nb_numa_nodes) {
408 int i;
409 for (i = 0; i < nb_numa_nodes; ++i) {
410 if (numa_info[i].node_mem) {
fb164994
DG		 411 return MIN(pow2floor(numa_info[i].node_mem),
412 machine->ram_size);
b082d65a
AK		 413 }
414 }
415 }
fb164994 416 return machine->ram_size;
b082d65a
AK		 417}
418
a1d59c0f
AK		 419static void add_str(GString *s, const gchar *s1)
420{
421 g_string_append_len(s, s1, strlen(s1) + 1);
422}
7f763a5d 423
03d196b7 424static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start,
26a8c353
AK		 425 hwaddr size)
426{
427 uint32_t associativity[] = {
428 cpu_to_be32(0x4), /* length */
429 cpu_to_be32(0x0), cpu_to_be32(0x0),
c3b4f589 430 cpu_to_be32(0x0), cpu_to_be32(nodeid)
26a8c353
AK		 431 };
432 char mem_name[32];
433 uint64_t mem_reg_property[2];
434 int off;
435
436 mem_reg_property[0] = cpu_to_be64(start);
437 mem_reg_property[1] = cpu_to_be64(size);
438
439 sprintf(mem_name, "memory@" TARGET_FMT_lx, start);
440 off = fdt_add_subnode(fdt, 0, mem_name);
441 _FDT(off);
442 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
443 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
444 sizeof(mem_reg_property))));
445 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,
446 sizeof(associativity))));
03d196b7 447 return off;
26a8c353
AK		 448}
449
28e02042 450static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt)
7f763a5d 451{
fb164994 452 MachineState *machine = MACHINE(spapr);
7db8a127
AK		 453 hwaddr mem_start, node_size;
454 int i, nb_nodes = nb_numa_nodes;
455 NodeInfo *nodes = numa_info;
456 NodeInfo ramnode;
457
458 /* No NUMA nodes, assume there is just one node with whole RAM */
459 if (!nb_numa_nodes) {
460 nb_nodes = 1;
fb164994 461 ramnode.node_mem = machine->ram_size;
7db8a127 462 nodes = &ramnode;
5fe269b1 463 }
7f763a5d 464
7db8a127
AK		 465 for (i = 0, mem_start = 0; i < nb_nodes; ++i) {
466 if (!nodes[i].node_mem) {
467 continue;
468 }
fb164994 469 if (mem_start >= machine->ram_size) {
5fe269b1
PM		 470 node_size = 0;
471 } else {
7db8a127 472 node_size = nodes[i].node_mem;
fb164994
DG		 473 if (node_size > machine->ram_size - mem_start) {
474 node_size = machine->ram_size - mem_start;
5fe269b1
PM		 475 }
476 }
7db8a127 477 if (!mem_start) {
b472b1a7
DHB		 478 /* spapr_machine_init() checks for rma_size <= node0_size
479 * already */
e8f986fc 480 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size);
7db8a127
AK		 481 mem_start += spapr->rma_size;
482 node_size -= spapr->rma_size;
483 }
6010818c
AK		 484 for ( ; node_size; ) {
485 hwaddr sizetmp = pow2floor(node_size);
486
487 /* mem_start != 0 here */
488 if (ctzl(mem_start) < ctzl(sizetmp)) {
489 sizetmp = 1ULL << ctzl(mem_start);
490 }
491
492 spapr_populate_memory_node(fdt, i, mem_start, sizetmp);
493 node_size -= sizetmp;
494 mem_start += sizetmp;
495 }
7f763a5d
DG		 496 }
497
498 return 0;
499}
500
0da6f3fe
BR		 501static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
502 sPAPRMachineState *spapr)
503{
504 PowerPCCPU *cpu = POWERPC_CPU(cs);
505 CPUPPCState *env = &cpu->env;
506 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
14bb4486 507 int index = spapr_get_vcpu_id(cpu);
0da6f3fe
BR		 508 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
509 0xffffffff, 0xffffffff};
afd10a0f
BR		 510 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq()
511 : SPAPR_TIMEBASE_FREQ;
0da6f3fe
BR		 512 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
513 uint32_t page_sizes_prop[64];
514 size_t page_sizes_prop_size;
22419c2a 515 uint32_t vcpus_per_socket = smp_threads * smp_cores;
0da6f3fe 516 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
abbc1247 517 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu));
af81cf32 518 sPAPRDRConnector *drc;
af81cf32 519 int drc_index;
c64abd1f
SB		 520 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ];
521 int i;
af81cf32 522
fbf55397 523 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index);
af81cf32 524 if (drc) {
0b55aa91 525 drc_index = spapr_drc_index(drc);
af81cf32
BR		 526 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index)));
527 }
0da6f3fe
BR		 528
529 _FDT((fdt_setprop_cell(fdt, offset, "reg", index)));
530 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
531
532 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
533 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
534 env->dcache_line_size)));
535 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
536 env->dcache_line_size)));
537 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
538 env->icache_line_size)));
539 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
540 env->icache_line_size)));
541
542 if (pcc->l1_dcache_size) {
543 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
544 pcc->l1_dcache_size)));
545 } else {
3dc6f869 546 warn_report("Unknown L1 dcache size for cpu");
0da6f3fe
BR		 547 }
548 if (pcc->l1_icache_size) {
549 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
550 pcc->l1_icache_size)));
551 } else {
3dc6f869 552 warn_report("Unknown L1 icache size for cpu");
0da6f3fe
BR		 553 }
554
555 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
556 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
67d7d66f
DG		 557 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size)));
558 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size)));
0da6f3fe
BR		 559 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
560 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
561
562 if (env->spr_cb[SPR_PURR].oea_read) {
563 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
564 }
565
58969eee 566 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) {
0da6f3fe
BR		 567 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
568 segs, sizeof(segs))));
569 }
570
29386642 571 /* Advertise VSX (vector extensions) if available
0da6f3fe 572 * 1 == VMX / Altivec available
29386642
DG		 573 * 2 == VSX available
574 *
575 * Only CPUs for which we create core types in spapr_cpu_core.c
576 * are possible, and all of those have VMX */
4e5fe368 577 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) {
29386642
DG		 578 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2)));
579 } else {
580 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1)));
0da6f3fe
BR		 581 }
582
583 /* Advertise DFP (Decimal Floating Point) if available
584 * 0 / no property == no DFP
585 * 1 == DFP available */
4e5fe368 586 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) {
0da6f3fe
BR		 587 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
588 }
589
644a2c99
DG		 590 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop,
591 sizeof(page_sizes_prop));
0da6f3fe
BR		 592 if (page_sizes_prop_size) {
593 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
594 page_sizes_prop, page_sizes_prop_size)));
595 }
596
ee76a09f 597 spapr_populate_pa_features(spapr, cpu, fdt, offset, false);
90da0d5a 598
0da6f3fe 599 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id",
22419c2a 600 cs->cpu_index / vcpus_per_socket)));
0da6f3fe
BR		 601
602 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size",
603 pft_size_prop, sizeof(pft_size_prop))));
604
99861ecb
IM		 605 if (nb_numa_nodes > 1) {
606 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu));
607 }
0da6f3fe 608
12dbeb16 609 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt));
c64abd1f
SB		 610
611 if (pcc->radix_page_info) {
612 for (i = 0; i < pcc->radix_page_info->count; i++) {
613 radix_AP_encodings[i] =
614 cpu_to_be32(pcc->radix_page_info->entries[i]);
615 }
616 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings",
617 radix_AP_encodings,
618 pcc->radix_page_info->count *
619 sizeof(radix_AP_encodings[0]))));
620 }
0da6f3fe
BR		 621}
622
623static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr)
624{
625 CPUState *cs;
626 int cpus_offset;
627 char *nodename;
0da6f3fe
BR		 628
629 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
630 _FDT(cpus_offset);
631 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
632 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
633
634 /*
635 * We walk the CPUs in reverse order to ensure that CPU DT nodes
636 * created by fdt_add_subnode() end up in the right order in FDT
637 * for the guest kernel the enumerate the CPUs correctly.
638 */
639 CPU_FOREACH_REVERSE(cs) {
640 PowerPCCPU *cpu = POWERPC_CPU(cs);
14bb4486 641 int index = spapr_get_vcpu_id(cpu);
0da6f3fe
BR		 642 DeviceClass *dc = DEVICE_GET_CLASS(cs);
643 int offset;
644
5d0fb150 645 if (!spapr_is_thread0_in_vcore(spapr, cpu)) {
0da6f3fe
BR		 646 continue;
647 }
648
649 nodename = g_strdup_printf("%s@%x", dc->fw_name, index);
650 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
651 g_free(nodename);
652 _FDT(offset);
653 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
654 }
655
656}
657
f47bd1c8
IM		 658static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr)
659{
660 MemoryDeviceInfoList *info;
661
662 for (info = list; info; info = info->next) {
663 MemoryDeviceInfo *value = info->value;
664
665 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) {
666 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data;
667
668 if (pcdimm_info->addr >= addr &&
669 addr < (pcdimm_info->addr + pcdimm_info->size)) {
670 return pcdimm_info->node;
671 }
672 }
673 }
674
675 return -1;
676}
677
a324d6f1
BR		 678struct sPAPRDrconfCellV2 {
679 uint32_t seq_lmbs;
680 uint64_t base_addr;
681 uint32_t drc_index;
682 uint32_t aa_index;
683 uint32_t flags;
684} QEMU_PACKED;
685
686typedef struct DrconfCellQueue {
687 struct sPAPRDrconfCellV2 cell;
688 QSIMPLEQ_ENTRY(DrconfCellQueue) entry;
689} DrconfCellQueue;
690
691static DrconfCellQueue *
692spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr,
693 uint32_t drc_index, uint32_t aa_index,
694 uint32_t flags)
03d196b7 695{
a324d6f1
BR		 696 DrconfCellQueue *elem;
697
698 elem = g_malloc0(sizeof(*elem));
699 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs);
700 elem->cell.base_addr = cpu_to_be64(base_addr);
701 elem->cell.drc_index = cpu_to_be32(drc_index);
702 elem->cell.aa_index = cpu_to_be32(aa_index);
703 elem->cell.flags = cpu_to_be32(flags);
704
705 return elem;
706}
707
708/* ibm,dynamic-memory-v2 */
709static int spapr_populate_drmem_v2(sPAPRMachineState *spapr, void *fdt,
710 int offset, MemoryDeviceInfoList *dimms)
711{
b0c14ec4 712 MachineState *machine = MACHINE(spapr);
a324d6f1
BR		 713 uint8_t *int_buf, *cur_index, buf_len;
714 int ret;
715 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
716 uint64_t addr, cur_addr, size;
b0c14ec4
DH		 717 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size);
718 uint64_t mem_end = machine->device_memory->base +
719 memory_region_size(&machine->device_memory->mr);
a324d6f1
BR		 720 uint32_t node, nr_entries = 0;
721 sPAPRDRConnector *drc;
722 DrconfCellQueue *elem, *next;
723 MemoryDeviceInfoList *info;
724 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue
725 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue);
726
727 /* Entry to cover RAM and the gap area */
728 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1,
729 SPAPR_LMB_FLAGS_RESERVED |
730 SPAPR_LMB_FLAGS_DRC_INVALID);
731 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
732 nr_entries++;
733
b0c14ec4 734 cur_addr = machine->device_memory->base;
a324d6f1
BR		 735 for (info = dimms; info; info = info->next) {
736 PCDIMMDeviceInfo *di = info->value->u.dimm.data;
737
738 addr = di->addr;
739 size = di->size;
740 node = di->node;
741
742 /* Entry for hot-pluggable area */
743 if (cur_addr < addr) {
744 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size);
745 g_assert(drc);
746 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size,
747 cur_addr, spapr_drc_index(drc), -1, 0);
748 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
749 nr_entries++;
750 }
751
752 /* Entry for DIMM */
753 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size);
754 g_assert(drc);
755 elem = spapr_get_drconf_cell(size / lmb_size, addr,
756 spapr_drc_index(drc), node,
757 SPAPR_LMB_FLAGS_ASSIGNED);
758 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
759 nr_entries++;
760 cur_addr = addr + size;
761 }
762
763 /* Entry for remaining hotpluggable area */
764 if (cur_addr < mem_end) {
765 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size);
766 g_assert(drc);
767 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size,
768 cur_addr, spapr_drc_index(drc), -1, 0);
769 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
770 nr_entries++;
771 }
772
773 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t);
774 int_buf = cur_index = g_malloc0(buf_len);
775 *(uint32_t *)int_buf = cpu_to_be32(nr_entries);
776 cur_index += sizeof(nr_entries);
777
778 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) {
779 memcpy(cur_index, &elem->cell, sizeof(elem->cell));
780 cur_index += sizeof(elem->cell);
781 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry);
782 g_free(elem);
783 }
784
785 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len);
786 g_free(int_buf);
787 if (ret < 0) {
788 return -1;
789 }
790 return 0;
791}
792
793/* ibm,dynamic-memory */
794static int spapr_populate_drmem_v1(sPAPRMachineState *spapr, void *fdt,
795 int offset, MemoryDeviceInfoList *dimms)
796{
b0c14ec4 797 MachineState *machine = MACHINE(spapr);
a324d6f1 798 int i, ret;
03d196b7 799 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
0c9269a5 800 uint32_t device_lmb_start = machine->device_memory->base / lmb_size;
b0c14ec4
DH		 801 uint32_t nr_lmbs = (machine->device_memory->base +
802 memory_region_size(&machine->device_memory->mr)) /
d0e5a8f2 803 lmb_size;
03d196b7 804 uint32_t *int_buf, *cur_index, buf_len;
16c25aef 805
ef001f06
TH		 806 /*
807 * Allocate enough buffer size to fit in ibm,dynamic-memory
ef001f06 808 */
a324d6f1 809 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t);
03d196b7 810 cur_index = int_buf = g_malloc0(buf_len);
03d196b7
BR		 811 int_buf[0] = cpu_to_be32(nr_lmbs);
812 cur_index++;
813 for (i = 0; i < nr_lmbs; i++) {
d0e5a8f2 814 uint64_t addr = i * lmb_size;
03d196b7
BR		 815 uint32_t *dynamic_memory = cur_index;
816
0c9269a5 817 if (i >= device_lmb_start) {
d0e5a8f2 818 sPAPRDRConnector *drc;
d0e5a8f2 819
fbf55397 820 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i);
d0e5a8f2 821 g_assert(drc);
d0e5a8f2
BR		 822
823 dynamic_memory[0] = cpu_to_be32(addr >> 32);
824 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
0b55aa91 825 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc));
d0e5a8f2 826 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
f47bd1c8 827 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr));
d0e5a8f2
BR		 828 if (memory_region_present(get_system_memory(), addr)) {
829 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED);
830 } else {
831 dynamic_memory[5] = cpu_to_be32(0);
832 }
03d196b7 833 } else {
d0e5a8f2
BR		 834 /*
835 * LMB information for RMA, boot time RAM and gap b/n RAM and
0c9269a5 836 * device memory region -- all these are marked as reserved
d0e5a8f2
BR		 837 * and as having no valid DRC.
838 */
839 dynamic_memory[0] = cpu_to_be32(addr >> 32);
840 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
841 dynamic_memory[2] = cpu_to_be32(0);
842 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
843 dynamic_memory[4] = cpu_to_be32(-1);
844 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED |
845 SPAPR_LMB_FLAGS_DRC_INVALID);
03d196b7
BR		 846 }
847
848 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE;
849 }
850 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len);
a324d6f1 851 g_free(int_buf);
03d196b7 852 if (ret < 0) {
a324d6f1
BR		 853 return -1;
854 }
855 return 0;
856}
857
858/*
859 * Adds ibm,dynamic-reconfiguration-memory node.
860 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation
861 * of this device tree node.
862 */
863static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt)
864{
865 MachineState *machine = MACHINE(spapr);
866 int ret, i, offset;
867 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
868 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)};
869 uint32_t *int_buf, *cur_index, buf_len;
870 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1;
871 MemoryDeviceInfoList *dimms = NULL;
872
873 /*
0c9269a5 874 * Don't create the node if there is no device memory
a324d6f1
BR		 875 */
876 if (machine->ram_size == machine->maxram_size) {
877 return 0;
878 }
879
880 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory");
881
882 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size,
883 sizeof(prop_lmb_size));
884 if (ret < 0) {
885 return ret;
886 }
887
888 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff);
889 if (ret < 0) {
890 return ret;
891 }
892
893 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0);
894 if (ret < 0) {
895 return ret;
896 }
897
898 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */
2cc0e2e8 899 dimms = qmp_memory_device_list();
a324d6f1
BR		 900 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) {
901 ret = spapr_populate_drmem_v2(spapr, fdt, offset, dimms);
902 } else {
903 ret = spapr_populate_drmem_v1(spapr, fdt, offset, dimms);
904 }
905 qapi_free_MemoryDeviceInfoList(dimms);
906
907 if (ret < 0) {
908 return ret;
03d196b7
BR		 909 }
910
911 /* ibm,associativity-lookup-arrays */
a324d6f1
BR		 912 buf_len = (nr_nodes * 4 + 2) * sizeof(uint32_t);
913 cur_index = int_buf = g_malloc0(buf_len);
914
03d196b7 915 cur_index = int_buf;
6663864e 916 int_buf[0] = cpu_to_be32(nr_nodes);
03d196b7
BR		 917 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */
918 cur_index += 2;
6663864e 919 for (i = 0; i < nr_nodes; i++) {
03d196b7
BR		 920 uint32_t associativity[] = {
921 cpu_to_be32(0x0),
922 cpu_to_be32(0x0),
923 cpu_to_be32(0x0),
924 cpu_to_be32(i)
925 };
926 memcpy(cur_index, associativity, sizeof(associativity));
927 cur_index += 4;
928 }
929 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf,
930 (cur_index - int_buf) * sizeof(uint32_t));
03d196b7 931 g_free(int_buf);
a324d6f1 932
03d196b7
BR		 933 return ret;
934}
935
6787d27b
MR		 936static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt,
937 sPAPROptionVector *ov5_updates)
938{
939 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
417ece33 940 int ret = 0, offset;
6787d27b
MR		 941
942 /* Generate ibm,dynamic-reconfiguration-memory node if required */
943 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) {
944 g_assert(smc->dr_lmb_enabled);
945 ret = spapr_populate_drconf_memory(spapr, fdt);
417ece33
MR		 946 if (ret) {
947 goto out;
948 }
6787d27b
MR		 949 }
950
417ece33
MR		 951 offset = fdt_path_offset(fdt, "/chosen");
952 if (offset < 0) {
953 offset = fdt_add_subnode(fdt, 0, "chosen");
954 if (offset < 0) {
955 return offset;
956 }
957 }
958 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas,
959 "ibm,architecture-vec-5");
960
961out:
6787d27b
MR		 962 return ret;
963}
964
10f12e64
DHB		 965static bool spapr_hotplugged_dev_before_cas(void)
966{
967 Object *drc_container, *obj;
968 ObjectProperty *prop;
969 ObjectPropertyIterator iter;
970
971 drc_container = container_get(object_get_root(), "/dr-connector");
972 object_property_iter_init(&iter, drc_container);
973 while ((prop = object_property_iter_next(&iter))) {
974 if (!strstart(prop->type, "link<", NULL)) {
975 continue;
976 }
977 obj = object_property_get_link(drc_container, prop->name, NULL);
978 if (spapr_drc_needed(obj)) {
979 return true;
980 }
981 }
982 return false;
983}
984
03d196b7
BR		 985int spapr_h_cas_compose_response(sPAPRMachineState *spapr,
986 target_ulong addr, target_ulong size,
6787d27b 987 sPAPROptionVector *ov5_updates)
03d196b7
BR		 988{
989 void *fdt, *fdt_skel;
990 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 };
03d196b7 991
10f12e64
DHB		 992 if (spapr_hotplugged_dev_before_cas()) {
993 return 1;
994 }
995
827b17c4
GK		 996 if (size < sizeof(hdr) || size > FW_MAX_SIZE) {
997 error_report("SLOF provided an unexpected CAS buffer size "
998 TARGET_FMT_lu " (min: %zu, max: %u)",
999 size, sizeof(hdr), FW_MAX_SIZE);
1000 exit(EXIT_FAILURE);
1001 }
1002
03d196b7
BR		 1003 size -= sizeof(hdr);
1004
10f12e64 1005 /* Create skeleton */
03d196b7
BR		 1006 fdt_skel = g_malloc0(size);
1007 _FDT((fdt_create(fdt_skel, size)));
127f03e4 1008 _FDT((fdt_finish_reservemap(fdt_skel)));
03d196b7
BR		 1009 _FDT((fdt_begin_node(fdt_skel, "")));
1010 _FDT((fdt_end_node(fdt_skel)));
1011 _FDT((fdt_finish(fdt_skel)));
1012 fdt = g_malloc0(size);
1013 _FDT((fdt_open_into(fdt_skel, fdt, size)));
1014 g_free(fdt_skel);
1015
1016 /* Fixup cpu nodes */
5b120785 1017 _FDT((spapr_fixup_cpu_dt(fdt, spapr)));
03d196b7 1018
6787d27b
MR		 1019 if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) {
1020 return -1;
03d196b7
BR		 1021 }
1022
1023 /* Pack resulting tree */
1024 _FDT((fdt_pack(fdt)));
1025
1026 if (fdt_totalsize(fdt) + sizeof(hdr) > size) {
1027 trace_spapr_cas_failed(size);
1028 return -1;
1029 }
1030
1031 cpu_physical_memory_write(addr, &hdr, sizeof(hdr));
1032 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt));
1033 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr));
1034 g_free(fdt);
1035
1036 return 0;
1037}
1038
3f5dabce
DG		 1039static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt)
1040{
1041 int rtas;
1042 GString *hypertas = g_string_sized_new(256);
1043 GString *qemu_hypertas = g_string_sized_new(256);
1044 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) };
0c9269a5 1045 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base +
b0c14ec4 1046 memory_region_size(&MACHINE(spapr)->device_memory->mr);
3f5dabce 1047 uint32_t lrdr_capacity[] = {
0c9269a5
DH		 1048 cpu_to_be32(max_device_addr >> 32),
1049 cpu_to_be32(max_device_addr & 0xffffffff),
3f5dabce
DG		 1050 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE),
1051 cpu_to_be32(max_cpus / smp_threads),
1052 };
da9f80fb
SP		 1053 uint32_t maxdomains[] = {
1054 cpu_to_be32(4),
1055 cpu_to_be32(0),
1056 cpu_to_be32(0),
1057 cpu_to_be32(0),
1058 cpu_to_be32(nb_numa_nodes ? nb_numa_nodes - 1 : 0),
1059 };
3f5dabce
DG		 1060
1061 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas"));
1062
1063 /* hypertas */
1064 add_str(hypertas, "hcall-pft");
1065 add_str(hypertas, "hcall-term");
1066 add_str(hypertas, "hcall-dabr");
1067 add_str(hypertas, "hcall-interrupt");
1068 add_str(hypertas, "hcall-tce");
1069 add_str(hypertas, "hcall-vio");
1070 add_str(hypertas, "hcall-splpar");
1071 add_str(hypertas, "hcall-bulk");
1072 add_str(hypertas, "hcall-set-mode");
1073 add_str(hypertas, "hcall-sprg0");
1074 add_str(hypertas, "hcall-copy");
1075 add_str(hypertas, "hcall-debug");
1076 add_str(qemu_hypertas, "hcall-memop1");
1077
1078 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
1079 add_str(hypertas, "hcall-multi-tce");
1080 }
30f4b05b
DG		 1081
1082 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) {
1083 add_str(hypertas, "hcall-hpt-resize");
1084 }
1085
3f5dabce
DG		 1086 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions",
1087 hypertas->str, hypertas->len));
1088 g_string_free(hypertas, TRUE);
1089 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions",
1090 qemu_hypertas->str, qemu_hypertas->len));
1091 g_string_free(qemu_hypertas, TRUE);
1092
1093 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points",
1094 refpoints, sizeof(refpoints)));
1095
da9f80fb
SP		 1096 _FDT(fdt_setprop(fdt, rtas, "ibm,max-associativity-domains",
1097 maxdomains, sizeof(maxdomains)));
1098
3f5dabce
DG		 1099 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max",
1100 RTAS_ERROR_LOG_MAX));
1101 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate",
1102 RTAS_EVENT_SCAN_RATE));
1103
4f441474
DG		 1104 g_assert(msi_nonbroken);
1105 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0));
3f5dabce
DG		 1106
1107 /*
1108 * According to PAPR, rtas ibm,os-term does not guarantee a return
1109 * back to the guest cpu.
1110 *
1111 * While an additional ibm,extended-os-term property indicates
1112 * that rtas call return will always occur. Set this property.
1113 */
1114 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0));
1115
1116 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity",
1117 lrdr_capacity, sizeof(lrdr_capacity)));
1118
1119 spapr_dt_rtas_tokens(fdt, rtas);
1120}
1121
9fb4541f
SB		 1122/* Prepare ibm,arch-vec-5-platform-support, which indicates the MMU features
1123 * that the guest may request and thus the valid values for bytes 24..26 of
1124 * option vector 5: */
1125static void spapr_dt_ov5_platform_support(void *fdt, int chosen)
1126{
545d6e2b
SJS		 1127 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu);
1128
f2b14e3a 1129 char val[2 * 4] = {
21f3f8db 1130 23, 0x00, /* Xive mode, filled in below. */
9fb4541f
SB		 1131 24, 0x00, /* Hash/Radix, filled in below. */
1132 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */
1133 26, 0x40, /* Radix options: GTSE == yes. */
1134 };
1135
7abd43ba
SJS		 1136 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0,
1137 first_ppc_cpu->compat_pvr)) {
1138 /* If we're in a pre POWER9 compat mode then the guest should do hash */
1139 val[3] = 0x00; /* Hash */
1140 } else if (kvm_enabled()) {
9fb4541f 1141 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) {
f2b14e3a 1142 val[3] = 0x80; /* OV5_MMU_BOTH */
9fb4541f 1143 } else if (kvmppc_has_cap_mmu_radix()) {
f2b14e3a 1144 val[3] = 0x40; /* OV5_MMU_RADIX_300 */
9fb4541f 1145 } else {
f2b14e3a 1146 val[3] = 0x00; /* Hash */
9fb4541f
SB		 1147 }
1148 } else {
7abd43ba
SJS		 1149 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */
1150 val[3] = 0xC0;
9fb4541f
SB		 1151 }
1152 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support",
1153 val, sizeof(val)));
1154}
1155
7c866c6a
DG		 1156static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt)
1157{
1158 MachineState *machine = MACHINE(spapr);
1159 int chosen;
1160 const char *boot_device = machine->boot_order;
1161 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus);
1162 size_t cb = 0;
1163 char *bootlist = get_boot_devices_list(&cb, true);
7c866c6a
DG		 1164
1165 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen"));
1166
7c866c6a
DG		 1167 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline));
1168 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start",
1169 spapr->initrd_base));
1170 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end",
1171 spapr->initrd_base + spapr->initrd_size));
1172
1173 if (spapr->kernel_size) {
1174 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR),
1175 cpu_to_be64(spapr->kernel_size) };
1176
1177 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel",
1178 &kprop, sizeof(kprop)));
1179 if (spapr->kernel_le) {
1180 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0));
1181 }
1182 }
1183 if (boot_menu) {
1184 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu)));
1185 }
1186 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width));
1187 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height));
1188 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth));
1189
1190 if (cb && bootlist) {
1191 int i;
1192
1193 for (i = 0; i < cb; i++) {
1194 if (bootlist[i] == '\n') {
1195 bootlist[i] = ' ';
1196 }
1197 }
1198 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist));
1199 }
1200
1201 if (boot_device && strlen(boot_device)) {
1202 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device));
1203 }
1204
1205 if (!spapr->has_graphics && stdout_path) {
90ee4e01
ND		 1206 /*
1207 * "linux,stdout-path" and "stdout" properties are deprecated by linux
1208 * kernel. New platforms should only use the "stdout-path" property. Set
1209 * the new property and continue using older property to remain
1210 * compatible with the existing firmware.
1211 */
7c866c6a 1212 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path));
90ee4e01 1213 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path));
7c866c6a
DG		 1214 }
1215
9fb4541f
SB		 1216 spapr_dt_ov5_platform_support(fdt, chosen);
1217
7c866c6a
DG		 1218 g_free(stdout_path);
1219 g_free(bootlist);
1220}
1221
fca5f2dc
DG		 1222static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt)
1223{
1224 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR
1225 * KVM to work under pHyp with some guest co-operation */
1226 int hypervisor;
1227 uint8_t hypercall[16];
1228
1229 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor"));
1230 /* indicate KVM hypercall interface */
1231 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm"));
1232 if (kvmppc_has_cap_fixup_hcalls()) {
1233 /*
1234 * Older KVM versions with older guest kernels were broken
1235 * with the magic page, don't allow the guest to map it.
1236 */
1237 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall,
1238 sizeof(hypercall))) {
1239 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions",
1240 hypercall, sizeof(hypercall)));
1241 }
1242 }
1243}
1244
997b6cfc
DG		 1245static void *spapr_build_fdt(sPAPRMachineState *spapr,
1246 hwaddr rtas_addr,
1247 hwaddr rtas_size)
a3467baa 1248{
c86c1aff 1249 MachineState *machine = MACHINE(spapr);
3c0c47e3 1250 MachineClass *mc = MACHINE_GET_CLASS(machine);
c20d332a 1251 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
7c866c6a 1252 int ret;
a3467baa 1253 void *fdt;
3384f95c 1254 sPAPRPHBState *phb;
398a0bd5 1255 char *buf;
a3467baa 1256
398a0bd5
DG		 1257 fdt = g_malloc0(FDT_MAX_SIZE);
1258 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
a3467baa 1259
398a0bd5
DG		 1260 /* Root node */
1261 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp"));
1262 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)"));
1263 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries"));
1264
1265 /*
1266 * Add info to guest to indentify which host is it being run on
1267 * and what is the uuid of the guest
1268 */
1269 if (kvmppc_get_host_model(&buf)) {
1270 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf));
1271 g_free(buf);
1272 }
1273 if (kvmppc_get_host_serial(&buf)) {
1274 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf));
1275 g_free(buf);
1276 }
1277
1278 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
1279
1280 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf));
1281 if (qemu_uuid_set) {
1282 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf));
1283 }
1284 g_free(buf);
1285
1286 if (qemu_get_vm_name()) {
1287 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name",
1288 qemu_get_vm_name()));
1289 }
1290
1291 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2));
1292 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2));
4040ab72 1293
fc7e0765 1294 /* /interrupt controller */
72194664 1295 spapr_dt_xics(xics_max_server_number(spapr), fdt, PHANDLE_XICP);
fc7e0765 1296
e8f986fc
BR		 1297 ret = spapr_populate_memory(spapr, fdt);
1298 if (ret < 0) {
ce9863b7 1299 error_report("couldn't setup memory nodes in fdt");
e8f986fc 1300 exit(1);
7f763a5d
DG		 1301 }
1302
bf5a6696
DG		 1303 /* /vdevice */
1304 spapr_dt_vdevice(spapr->vio_bus, fdt);
4040ab72 1305
4d9392be
TH		 1306 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) {
1307 ret = spapr_rng_populate_dt(fdt);
1308 if (ret < 0) {
ce9863b7 1309 error_report("could not set up rng device in the fdt");
4d9392be
TH		 1310 exit(1);
1311 }
1312 }
1313
3384f95c 1314 QLIST_FOREACH(phb, &spapr->phbs, list) {
e0fdbd7c 1315 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt);
da34fed7
TH		 1316 if (ret < 0) {
1317 error_report("couldn't setup PCI devices in fdt");
1318 exit(1);
1319 }
3384f95c
DG		 1320 }
1321
0da6f3fe
BR		 1322 /* cpus */
1323 spapr_populate_cpus_dt_node(fdt, spapr);
6e806cc3 1324
c20d332a
BR		 1325 if (smc->dr_lmb_enabled) {
1326 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB));
1327 }
1328
c5514d0e 1329 if (mc->has_hotpluggable_cpus) {
af81cf32
BR		 1330 int offset = fdt_path_offset(fdt, "/cpus");
1331 ret = spapr_drc_populate_dt(fdt, offset, NULL,
1332 SPAPR_DR_CONNECTOR_TYPE_CPU);
1333 if (ret < 0) {
1334 error_report("Couldn't set up CPU DR device tree properties");
1335 exit(1);
1336 }
1337 }
1338
ffb1e275 1339 /* /event-sources */
ffbb1705 1340 spapr_dt_events(spapr, fdt);
ffb1e275 1341
3f5dabce
DG		 1342 /* /rtas */
1343 spapr_dt_rtas(spapr, fdt);
1344
7c866c6a
DG		 1345 /* /chosen */
1346 spapr_dt_chosen(spapr, fdt);
cf6e5223 1347
fca5f2dc
DG		 1348 /* /hypervisor */
1349 if (kvm_enabled()) {
1350 spapr_dt_hypervisor(spapr, fdt);
1351 }
1352
cf6e5223
DG		 1353 /* Build memory reserve map */
1354 if (spapr->kernel_size) {
1355 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size)));
1356 }
1357 if (spapr->initrd_size) {
1358 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size)));
1359 }
1360
6787d27b
MR		 1361 /* ibm,client-architecture-support updates */
1362 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas);
1363 if (ret < 0) {
1364 error_report("couldn't setup CAS properties fdt");
1365 exit(1);
1366 }
1367
997b6cfc 1368 return fdt;
9fdf0c29
DG		 1369}
1370
1371static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
1372{
1373 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
1374}
1375
1d1be34d
DG		 1376static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp,
1377 PowerPCCPU *cpu)
9fdf0c29 1378{
1b14670a
AF		 1379 CPUPPCState *env = &cpu->env;
1380
8d04fb55
JK		 1381 /* The TCG path should also be holding the BQL at this point */
1382 g_assert(qemu_mutex_iothread_locked());
1383
efcb9383
DG		 1384 if (msr_pr) {
1385 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1386 env->gpr[3] = H_PRIVILEGE;
1387 } else {
aa100fa4 1388 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]);
efcb9383 1389 }
9fdf0c29
DG		 1390}
1391
9861bb3e
SJS		 1392static uint64_t spapr_get_patbe(PPCVirtualHypervisor *vhyp)
1393{
1394 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1395
1396 return spapr->patb_entry;
1397}
1398
e6b8fd24
SMJ		 1399#define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1400#define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1401#define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1402#define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1403#define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1404
715c5407
DG		 1405/*
1406 * Get the fd to access the kernel htab, re-opening it if necessary
1407 */
1408static int get_htab_fd(sPAPRMachineState *spapr)
1409{
14b0d748
GK		 1410 Error *local_err = NULL;
1411
715c5407
DG		 1412 if (spapr->htab_fd >= 0) {
1413 return spapr->htab_fd;
1414 }
1415
14b0d748 1416 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err);
715c5407 1417 if (spapr->htab_fd < 0) {
14b0d748 1418 error_report_err(local_err);
715c5407
DG		 1419 }
1420
1421 return spapr->htab_fd;
1422}
1423
b4db5413 1424void close_htab_fd(sPAPRMachineState *spapr)
715c5407
DG		 1425{
1426 if (spapr->htab_fd >= 0) {
1427 close(spapr->htab_fd);
1428 }
1429 spapr->htab_fd = -1;
1430}
1431
e57ca75c
DG		 1432static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp)
1433{
1434 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1435
1436 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1;
1437}
1438
1ec26c75
GK		 1439static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp)
1440{
1441 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1442
1443 assert(kvm_enabled());
1444
1445 if (!spapr->htab) {
1446 return 0;
1447 }
1448
1449 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18);
1450}
1451
e57ca75c
DG		 1452static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp,
1453 hwaddr ptex, int n)
1454{
1455 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1456 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64;
1457
1458 if (!spapr->htab) {
1459 /*
1460 * HTAB is controlled by KVM. Fetch into temporary buffer
1461 */
1462 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64);
1463 kvmppc_read_hptes(hptes, ptex, n);
1464 return hptes;
1465 }
1466
1467 /*
1468 * HTAB is controlled by QEMU. Just point to the internally
1469 * accessible PTEG.
1470 */
1471 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset);
1472}
1473
1474static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp,
1475 const ppc_hash_pte64_t *hptes,
1476 hwaddr ptex, int n)
1477{
1478 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1479
1480 if (!spapr->htab) {
1481 g_free((void *)hptes);
1482 }
1483
1484 /* Nothing to do for qemu managed HPT */
1485}
1486
1487static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex,
1488 uint64_t pte0, uint64_t pte1)
1489{
1490 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1491 hwaddr offset = ptex * HASH_PTE_SIZE_64;
1492
1493 if (!spapr->htab) {
1494 kvmppc_write_hpte(ptex, pte0, pte1);
1495 } else {
1496 stq_p(spapr->htab + offset, pte0);
1497 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1);
1498 }
1499}
1500
0b0b8310 1501int spapr_hpt_shift_for_ramsize(uint64_t ramsize)
8dfe8e7f
DG		 1502{
1503 int shift;
1504
1505 /* We aim for a hash table of size 1/128 the size of RAM (rounded
1506 * up). The PAPR recommendation is actually 1/64 of RAM size, but
1507 * that's much more than is needed for Linux guests */
1508 shift = ctz64(pow2ceil(ramsize)) - 7;
1509 shift = MAX(shift, 18); /* Minimum architected size */
1510 shift = MIN(shift, 46); /* Maximum architected size */
1511 return shift;
1512}
1513
06ec79e8
BR		 1514void spapr_free_hpt(sPAPRMachineState *spapr)
1515{
1516 g_free(spapr->htab);
1517 spapr->htab = NULL;
1518 spapr->htab_shift = 0;
1519 close_htab_fd(spapr);
1520}
1521
2772cf6b
DG		 1522void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift,
1523 Error **errp)
7f763a5d 1524{
c5f54f3e
DG		 1525 long rc;
1526
1527 /* Clean up any HPT info from a previous boot */
06ec79e8 1528 spapr_free_hpt(spapr);
c5f54f3e
DG		 1529
1530 rc = kvmppc_reset_htab(shift);
1531 if (rc < 0) {
1532 /* kernel-side HPT needed, but couldn't allocate one */
1533 error_setg_errno(errp, errno,
1534 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)",
1535 shift);
1536 /* This is almost certainly fatal, but if the caller really
1537 * wants to carry on with shift == 0, it's welcome to try */
1538 } else if (rc > 0) {
1539 /* kernel-side HPT allocated */
1540 if (rc != shift) {
1541 error_setg(errp,
1542 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)",
1543 shift, rc);
7735feda
BR		 1544 }
1545
7f763a5d 1546 spapr->htab_shift = shift;
c18ad9a5 1547 spapr->htab = NULL;
b817772a 1548 } else {
c5f54f3e
DG		 1549 /* kernel-side HPT not needed, allocate in userspace instead */
1550 size_t size = 1ULL << shift;
1551 int i;
b817772a 1552
c5f54f3e
DG		 1553 spapr->htab = qemu_memalign(size, size);
1554 if (!spapr->htab) {
1555 error_setg_errno(errp, errno,
1556 "Could not allocate HPT of order %d", shift);
1557 return;
7735feda
BR		 1558 }
1559
c5f54f3e
DG		 1560 memset(spapr->htab, 0, size);
1561 spapr->htab_shift = shift;
e6b8fd24 1562
c5f54f3e
DG		 1563 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) {
1564 DIRTY_HPTE(HPTE(spapr->htab, i));
e6b8fd24 1565 }
7f763a5d 1566 }
ee4d9ecc
SJS		 1567 /* We're setting up a hash table, so that means we're not radix */
1568 spapr->patb_entry = 0;
9fdf0c29
DG		 1569}
1570
b4db5413
SJS		 1571void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr)
1572{
2772cf6b
DG		 1573 int hpt_shift;
1574
1575 if ((spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED)
1576 || (spapr->cas_reboot
1577 && !spapr_ovec_test(spapr->ov5_cas, OV5_HPT_RESIZE))) {
1578 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size);
1579 } else {
768a20f3
DG		 1580 uint64_t current_ram_size;
1581
1582 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size();
1583 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size);
2772cf6b
DG		 1584 }
1585 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal);
1586
b4db5413 1587 if (spapr->vrma_adjust) {
c86c1aff 1588 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(MACHINE(spapr)),
b4db5413
SJS		 1589 spapr->htab_shift);
1590 }
b4db5413
SJS		 1591}
1592
82512483
GK		 1593static int spapr_reset_drcs(Object *child, void *opaque)
1594{
1595 sPAPRDRConnector *drc =
1596 (sPAPRDRConnector *) object_dynamic_cast(child,
1597 TYPE_SPAPR_DR_CONNECTOR);
1598
1599 if (drc) {
1600 spapr_drc_reset(drc);
1601 }
1602
1603 return 0;
1604}
1605
bcb5ce08 1606static void spapr_machine_reset(void)
a3467baa 1607{
c5f54f3e
DG		 1608 MachineState *machine = MACHINE(qdev_get_machine());
1609 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
182735ef 1610 PowerPCCPU *first_ppc_cpu;
b7d1f77a 1611 uint32_t rtas_limit;
cae172ab 1612 hwaddr rtas_addr, fdt_addr;
997b6cfc
DG		 1613 void *fdt;
1614 int rc;
259186a7 1615
9f6edd06 1616 spapr_caps_apply(spapr);
33face6b 1617
1481fe5f
LV		 1618 first_ppc_cpu = POWERPC_CPU(first_cpu);
1619 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() &&
ad99d04c
DG		 1620 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0,
1621 spapr->max_compat_pvr)) {
b4db5413
SJS		 1622 /* If using KVM with radix mode available, VCPUs can be started
1623 * without a HPT because KVM will start them in radix mode.
1624 * Set the GR bit in PATB so that we know there is no HPT. */
1625 spapr->patb_entry = PATBE1_GR;
1626 } else {
b4db5413 1627 spapr_setup_hpt_and_vrma(spapr);
c5f54f3e 1628 }
a3467baa 1629
9012a53f
GK		 1630 /* if this reset wasn't generated by CAS, we should reset our
1631 * negotiated options and start from scratch */
1632 if (!spapr->cas_reboot) {
1633 spapr_ovec_cleanup(spapr->ov5_cas);
1634 spapr->ov5_cas = spapr_ovec_new();
1635
1636 ppc_set_compat(first_ppc_cpu, spapr->max_compat_pvr, &error_fatal);
1637 }
1638
c8787ad4 1639 qemu_devices_reset();
82512483
GK		 1640
1641 /* DRC reset may cause a device to be unplugged. This will cause troubles
1642 * if this device is used by another device (eg, a running vhost backend
1643 * will crash QEMU if the DIMM holding the vring goes away). To avoid such
1644 * situations, we reset DRCs after all devices have been reset.
1645 */
1646 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL);
1647
56258174 1648 spapr_clear_pending_events(spapr);
a3467baa 1649
b7d1f77a
BH		 1650 /*
1651 * We place the device tree and RTAS just below either the top of the RMA,
1652 * or just below 2GB, whichever is lowere, so that it can be
1653 * processed with 32-bit real mode code if necessary
1654 */
1655 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR);
cae172ab
DG		 1656 rtas_addr = rtas_limit - RTAS_MAX_SIZE;
1657 fdt_addr = rtas_addr - FDT_MAX_SIZE;
b7d1f77a 1658
cae172ab 1659 fdt = spapr_build_fdt(spapr, rtas_addr, spapr->rtas_size);
a3467baa 1660
2cac78c1 1661 spapr_load_rtas(spapr, fdt, rtas_addr);
b7d1f77a 1662
997b6cfc
DG		 1663 rc = fdt_pack(fdt);
1664
1665 /* Should only fail if we've built a corrupted tree */
1666 assert(rc == 0);
1667
1668 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) {
1669 error_report("FDT too big ! 0x%x bytes (max is 0x%x)",
1670 fdt_totalsize(fdt), FDT_MAX_SIZE);
1671 exit(1);
1672 }
1673
1674 /* Load the fdt */
1675 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
cae172ab 1676 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt));
997b6cfc
DG		 1677 g_free(fdt);
1678
a3467baa 1679 /* Set up the entry state */
84369f63 1680 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, fdt_addr);
182735ef 1681 first_ppc_cpu->env.gpr[5] = 0;
a3467baa 1682
6787d27b 1683 spapr->cas_reboot = false;
a3467baa
DG		 1684}
1685
28e02042 1686static void spapr_create_nvram(sPAPRMachineState *spapr)
639e8102 1687{
2ff3de68 1688 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram");
3978b863 1689 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
639e8102 1690
3978b863 1691 if (dinfo) {
6231a6da
MA		 1692 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
1693 &error_fatal);
639e8102
DG		 1694 }
1695
1696 qdev_init_nofail(dev);
1697
1698 spapr->nvram = (struct sPAPRNVRAM *)dev;
1699}
1700
28e02042 1701static void spapr_rtc_create(sPAPRMachineState *spapr)
28df36a1 1702{
147ff807
CLG		 1703 object_initialize(&spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC);
1704 object_property_add_child(OBJECT(spapr), "rtc", OBJECT(&spapr->rtc),
1705 &error_fatal);
1706 object_property_set_bool(OBJECT(&spapr->rtc), true, "realized",
1707 &error_fatal);
1708 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc),
1709 "date", &error_fatal);
28df36a1
DG		 1710}
1711
8c57b867 1712/* Returns whether we want to use VGA or not */
14c6a894 1713static bool spapr_vga_init(PCIBus *pci_bus, Error **errp)
f28359d8 1714{
8c57b867 1715 switch (vga_interface_type) {
8c57b867 1716 case VGA_NONE:
7effdaa3
MW		 1717 return false;
1718 case VGA_DEVICE:
1719 return true;
1ddcae82 1720 case VGA_STD:
b798c190 1721 case VGA_VIRTIO:
1ddcae82 1722 return pci_vga_init(pci_bus) != NULL;
8c57b867 1723 default:
14c6a894
DG		 1724 error_setg(errp,
1725 "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1726 return false;
f28359d8 1727 }
f28359d8
LZ		 1728}
1729
4e5fe368
SJS		 1730static int spapr_pre_load(void *opaque)
1731{
1732 int rc;
1733
1734 rc = spapr_caps_pre_load(opaque);
1735 if (rc) {
1736 return rc;
1737 }
1738
1739 return 0;
1740}
1741
880ae7de
DG		 1742static int spapr_post_load(void *opaque, int version_id)
1743{
28e02042 1744 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque;
880ae7de
DG		 1745 int err = 0;
1746
be85537d
DG		 1747 err = spapr_caps_post_migration(spapr);
1748 if (err) {
1749 return err;
1750 }
1751
a7ff1212 1752 if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) {
5bc8d26d
CLG		 1753 CPUState *cs;
1754 CPU_FOREACH(cs) {
1755 PowerPCCPU *cpu = POWERPC_CPU(cs);
1756 icp_resend(ICP(cpu->intc));
a7ff1212
CLG		 1757 }
1758 }
1759
631b22ea 1760 /* In earlier versions, there was no separate qdev for the PAPR
880ae7de
DG		 1761 * RTC, so the RTC offset was stored directly in sPAPREnvironment.
1762 * So when migrating from those versions, poke the incoming offset
1763 * value into the RTC device */
1764 if (version_id < 3) {
147ff807 1765 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset);
880ae7de
DG		 1766 }
1767
0c86b2df 1768 if (kvm_enabled() && spapr->patb_entry) {
d39c90f5
BR		 1769 PowerPCCPU *cpu = POWERPC_CPU(first_cpu);
1770 bool radix = !!(spapr->patb_entry & PATBE1_GR);
1771 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE);
1772
1773 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry);
1774 if (err) {
1775 error_report("Process table config unsupported by the host");
1776 return -EINVAL;
1777 }
1778 }
1779
880ae7de
DG		 1780 return err;
1781}
1782
4e5fe368
SJS		 1783static int spapr_pre_save(void *opaque)
1784{
1785 int rc;
1786
1787 rc = spapr_caps_pre_save(opaque);
1788 if (rc) {
1789 return rc;
1790 }
1791
1792 return 0;
1793}
1794
880ae7de
DG		 1795static bool version_before_3(void *opaque, int version_id)
1796{
1797 return version_id < 3;
1798}
1799
fd38804b
DHB		 1800static bool spapr_pending_events_needed(void *opaque)
1801{
1802 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque;
1803 return !QTAILQ_EMPTY(&spapr->pending_events);
1804}
1805
1806static const VMStateDescription vmstate_spapr_event_entry = {
1807 .name = "spapr_event_log_entry",
1808 .version_id = 1,
1809 .minimum_version_id = 1,
1810 .fields = (VMStateField[]) {
5341258e
DG		 1811 VMSTATE_UINT32(summary, sPAPREventLogEntry),
1812 VMSTATE_UINT32(extended_length, sPAPREventLogEntry),
fd38804b 1813 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, sPAPREventLogEntry, 0,
5341258e 1814 NULL, extended_length),
fd38804b
DHB		 1815 VMSTATE_END_OF_LIST()
1816 },
1817};
1818
1819static const VMStateDescription vmstate_spapr_pending_events = {
1820 .name = "spapr_pending_events",
1821 .version_id = 1,
1822 .minimum_version_id = 1,
1823 .needed = spapr_pending_events_needed,
1824 .fields = (VMStateField[]) {
1825 VMSTATE_QTAILQ_V(pending_events, sPAPRMachineState, 1,
1826 vmstate_spapr_event_entry, sPAPREventLogEntry, next),
1827 VMSTATE_END_OF_LIST()
1828 },
1829};
1830
62ef3760
MR		 1831static bool spapr_ov5_cas_needed(void *opaque)
1832{
1833 sPAPRMachineState *spapr = opaque;
1834 sPAPROptionVector *ov5_mask = spapr_ovec_new();
1835 sPAPROptionVector *ov5_legacy = spapr_ovec_new();
1836 sPAPROptionVector *ov5_removed = spapr_ovec_new();
1837 bool cas_needed;
1838
1839 /* Prior to the introduction of sPAPROptionVector, we had two option
1840 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY.
1841 * Both of these options encode machine topology into the device-tree
1842 * in such a way that the now-booted OS should still be able to interact
1843 * appropriately with QEMU regardless of what options were actually
1844 * negotiatied on the source side.
1845 *
1846 * As such, we can avoid migrating the CAS-negotiated options if these
1847 * are the only options available on the current machine/platform.
1848 * Since these are the only options available for pseries-2.7 and
1849 * earlier, this allows us to maintain old->new/new->old migration
1850 * compatibility.
1851 *
1852 * For QEMU 2.8+, there are additional CAS-negotiatable options available
1853 * via default pseries-2.8 machines and explicit command-line parameters.
1854 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware
1855 * of the actual CAS-negotiated values to continue working properly. For
1856 * example, availability of memory unplug depends on knowing whether
1857 * OV5_HP_EVT was negotiated via CAS.
1858 *
1859 * Thus, for any cases where the set of available CAS-negotiatable
1860 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we
aef19c04
GK		 1861 * include the CAS-negotiated options in the migration stream, unless
1862 * if they affect boot time behaviour only.
62ef3760
MR		 1863 */
1864 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY);
1865 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY);
aef19c04 1866 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2);
62ef3760
MR		 1867
1868 /* spapr_ovec_diff returns true if bits were removed. we avoid using
1869 * the mask itself since in the future it's possible "legacy" bits may be
1870 * removed via machine options, which could generate a false positive
1871 * that breaks migration.
1872 */
1873 spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask);
1874 cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy);
1875
1876 spapr_ovec_cleanup(ov5_mask);
1877 spapr_ovec_cleanup(ov5_legacy);
1878 spapr_ovec_cleanup(ov5_removed);
1879
1880 return cas_needed;
1881}
1882
1883static const VMStateDescription vmstate_spapr_ov5_cas = {
1884 .name = "spapr_option_vector_ov5_cas",
1885 .version_id = 1,
1886 .minimum_version_id = 1,
1887 .needed = spapr_ov5_cas_needed,
1888 .fields = (VMStateField[]) {
1889 VMSTATE_STRUCT_POINTER_V(ov5_cas, sPAPRMachineState, 1,
1890 vmstate_spapr_ovec, sPAPROptionVector),
1891 VMSTATE_END_OF_LIST()
1892 },
1893};
1894
9861bb3e
SJS		 1895static bool spapr_patb_entry_needed(void *opaque)
1896{
1897 sPAPRMachineState *spapr = opaque;
1898
1899 return !!spapr->patb_entry;
1900}
1901
1902static const VMStateDescription vmstate_spapr_patb_entry = {
1903 .name = "spapr_patb_entry",
1904 .version_id = 1,
1905 .minimum_version_id = 1,
1906 .needed = spapr_patb_entry_needed,
1907 .fields = (VMStateField[]) {
1908 VMSTATE_UINT64(patb_entry, sPAPRMachineState),
1909 VMSTATE_END_OF_LIST()
1910 },
1911};
1912
4be21d56
DG		 1913static const VMStateDescription vmstate_spapr = {
1914 .name = "spapr",
880ae7de 1915 .version_id = 3,
4be21d56 1916 .minimum_version_id = 1,
4e5fe368 1917 .pre_load = spapr_pre_load,
880ae7de 1918 .post_load = spapr_post_load,
4e5fe368 1919 .pre_save = spapr_pre_save,
3aff6c2f 1920 .fields = (VMStateField[]) {
880ae7de
DG		 1921 /* used to be @next_irq */
1922 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4),
4be21d56
DG		 1923
1924 /* RTC offset */
28e02042 1925 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3),
880ae7de 1926
28e02042 1927 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2),
4be21d56
DG		 1928 VMSTATE_END_OF_LIST()
1929 },
62ef3760
MR		 1930 .subsections = (const VMStateDescription*[]) {
1931 &vmstate_spapr_ov5_cas,
9861bb3e 1932 &vmstate_spapr_patb_entry,
fd38804b 1933 &vmstate_spapr_pending_events,
4e5fe368
SJS		 1934 &vmstate_spapr_cap_htm,
1935 &vmstate_spapr_cap_vsx,
1936 &vmstate_spapr_cap_dfp,
8f38eaf8 1937 &vmstate_spapr_cap_cfpc,
09114fd8 1938 &vmstate_spapr_cap_sbbc,
4be8d4e7 1939 &vmstate_spapr_cap_ibs,
62ef3760
MR		 1940 NULL
1941 }
4be21d56
DG		 1942};
1943
4be21d56
DG		 1944static int htab_save_setup(QEMUFile *f, void *opaque)
1945{
28e02042 1946 sPAPRMachineState *spapr = opaque;
4be21d56 1947
4be21d56 1948 /* "Iteration" header */
3a384297
BR		 1949 if (!spapr->htab_shift) {
1950 qemu_put_be32(f, -1);
1951 } else {
1952 qemu_put_be32(f, spapr->htab_shift);
1953 }
4be21d56 1954
e68cb8b4
AK		 1955 if (spapr->htab) {
1956 spapr->htab_save_index = 0;
1957 spapr->htab_first_pass = true;
1958 } else {
3a384297
BR		 1959 if (spapr->htab_shift) {
1960 assert(kvm_enabled());
1961 }
e68cb8b4
AK		 1962 }
1963
1964
4be21d56
DG		 1965 return 0;
1966}
1967
332f7721
GK		 1968static void htab_save_chunk(QEMUFile *f, sPAPRMachineState *spapr,
1969 int chunkstart, int n_valid, int n_invalid)
1970{
1971 qemu_put_be32(f, chunkstart);
1972 qemu_put_be16(f, n_valid);
1973 qemu_put_be16(f, n_invalid);
1974 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1975 HASH_PTE_SIZE_64 * n_valid);
1976}
1977
1978static void htab_save_end_marker(QEMUFile *f)
1979{
1980 qemu_put_be32(f, 0);
1981 qemu_put_be16(f, 0);
1982 qemu_put_be16(f, 0);
1983}
1984
28e02042 1985static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr,
4be21d56
DG		 1986 int64_t max_ns)
1987{
378bc217 1988 bool has_timeout = max_ns != -1;
4be21d56
DG		 1989 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1990 int index = spapr->htab_save_index;
bc72ad67 1991 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
4be21d56
DG		 1992
1993 assert(spapr->htab_first_pass);
1994
1995 do {
1996 int chunkstart;
1997
1998 /* Consume invalid HPTEs */
1999 while ((index < htabslots)
2000 && !HPTE_VALID(HPTE(spapr->htab, index))) {
4be21d56 2001 CLEAN_HPTE(HPTE(spapr->htab, index));
24ec2863 2002 index++;
4be21d56
DG		 2003 }
2004
2005 /* Consume valid HPTEs */
2006 chunkstart = index;
338c25b6 2007 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
4be21d56 2008 && HPTE_VALID(HPTE(spapr->htab, index))) {
4be21d56 2009 CLEAN_HPTE(HPTE(spapr->htab, index));
24ec2863 2010 index++;
4be21d56
DG		 2011 }
2012
2013 if (index > chunkstart) {
2014 int n_valid = index - chunkstart;
2015
332f7721 2016 htab_save_chunk(f, spapr, chunkstart, n_valid, 0);
4be21d56 2017
378bc217
DG		 2018 if (has_timeout &&
2019 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
4be21d56
DG		 2020 break;
2021 }
2022 }
2023 } while ((index < htabslots) && !qemu_file_rate_limit(f));
2024
2025 if (index >= htabslots) {
2026 assert(index == htabslots);
2027 index = 0;
2028 spapr->htab_first_pass = false;
2029 }
2030 spapr->htab_save_index = index;
2031}
2032
28e02042 2033static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr,
e68cb8b4 2034 int64_t max_ns)
4be21d56
DG		 2035{
2036 bool final = max_ns < 0;
2037 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
2038 int examined = 0, sent = 0;
2039 int index = spapr->htab_save_index;
bc72ad67 2040 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
4be21d56
DG		 2041
2042 assert(!spapr->htab_first_pass);
2043
2044 do {
2045 int chunkstart, invalidstart;
2046
2047 /* Consume non-dirty HPTEs */
2048 while ((index < htabslots)
2049 && !HPTE_DIRTY(HPTE(spapr->htab, index))) {
2050 index++;
2051 examined++;
2052 }
2053
2054 chunkstart = index;
2055 /* Consume valid dirty HPTEs */
338c25b6 2056 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
4be21d56
DG		 2057 && HPTE_DIRTY(HPTE(spapr->htab, index))
2058 && HPTE_VALID(HPTE(spapr->htab, index))) {
2059 CLEAN_HPTE(HPTE(spapr->htab, index));
2060 index++;
2061 examined++;
2062 }
2063
2064 invalidstart = index;
2065 /* Consume invalid dirty HPTEs */
338c25b6 2066 while ((index < htabslots) && (index - invalidstart < USHRT_MAX)
4be21d56
DG		 2067 && HPTE_DIRTY(HPTE(spapr->htab, index))
2068 && !HPTE_VALID(HPTE(spapr->htab, index))) {
2069 CLEAN_HPTE(HPTE(spapr->htab, index));
2070 index++;
2071 examined++;
2072 }
2073
2074 if (index > chunkstart) {
2075 int n_valid = invalidstart - chunkstart;
2076 int n_invalid = index - invalidstart;
2077
332f7721 2078 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid);
4be21d56
DG		 2079 sent += index - chunkstart;
2080
bc72ad67 2081 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
4be21d56
DG		 2082 break;
2083 }
2084 }
2085
2086 if (examined >= htabslots) {
2087 break;
2088 }
2089
2090 if (index >= htabslots) {
2091 assert(index == htabslots);
2092 index = 0;
2093 }
2094 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final));
2095
2096 if (index >= htabslots) {
2097 assert(index == htabslots);
2098 index = 0;
2099 }
2100
2101 spapr->htab_save_index = index;
2102
e68cb8b4 2103 return (examined >= htabslots) && (sent == 0) ? 1 : 0;
4be21d56
DG		 2104}
2105
e68cb8b4
AK		 2106#define MAX_ITERATION_NS 5000000 /* 5 ms */
2107#define MAX_KVM_BUF_SIZE 2048
2108
4be21d56
DG		 2109static int htab_save_iterate(QEMUFile *f, void *opaque)
2110{
28e02042 2111 sPAPRMachineState *spapr = opaque;
715c5407 2112 int fd;
e68cb8b4 2113 int rc = 0;
4be21d56
DG		 2114
2115 /* Iteration header */
3a384297
BR		 2116 if (!spapr->htab_shift) {
2117 qemu_put_be32(f, -1);
e8cd4247 2118 return 1;
3a384297
BR		 2119 } else {
2120 qemu_put_be32(f, 0);
2121 }
4be21d56 2122
e68cb8b4
AK		 2123 if (!spapr->htab) {
2124 assert(kvm_enabled());
2125
715c5407
DG		 2126 fd = get_htab_fd(spapr);
2127 if (fd < 0) {
2128 return fd;
01a57972
SMJ		 2129 }
2130
715c5407 2131 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS);
e68cb8b4
AK		 2132 if (rc < 0) {
2133 return rc;
2134 }
2135 } else if (spapr->htab_first_pass) {
4be21d56
DG		 2136 htab_save_first_pass(f, spapr, MAX_ITERATION_NS);
2137 } else {
e68cb8b4 2138 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS);
4be21d56
DG		 2139 }
2140
332f7721 2141 htab_save_end_marker(f);
4be21d56 2142
e68cb8b4 2143 return rc;
4be21d56
DG		 2144}
2145
2146static int htab_save_complete(QEMUFile *f, void *opaque)
2147{
28e02042 2148 sPAPRMachineState *spapr = opaque;
715c5407 2149 int fd;
4be21d56
DG		 2150
2151 /* Iteration header */
3a384297
BR		 2152 if (!spapr->htab_shift) {
2153 qemu_put_be32(f, -1);
2154 return 0;
2155 } else {
2156 qemu_put_be32(f, 0);
2157 }
4be21d56 2158
e68cb8b4
AK		 2159 if (!spapr->htab) {
2160 int rc;
2161
2162 assert(kvm_enabled());
2163
715c5407
DG		 2164 fd = get_htab_fd(spapr);
2165 if (fd < 0) {
2166 return fd;
01a57972
SMJ		 2167 }
2168
715c5407 2169 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1);
e68cb8b4
AK		 2170 if (rc < 0) {
2171 return rc;
2172 }
e68cb8b4 2173 } else {
378bc217
DG		 2174 if (spapr->htab_first_pass) {
2175 htab_save_first_pass(f, spapr, -1);
2176 }
e68cb8b4
AK		 2177 htab_save_later_pass(f, spapr, -1);
2178 }
4be21d56
DG		 2179
2180 /* End marker */
332f7721 2181 htab_save_end_marker(f);
4be21d56
DG		 2182
2183 return 0;
2184}
2185
2186static int htab_load(QEMUFile *f, void *opaque, int version_id)
2187{
28e02042 2188 sPAPRMachineState *spapr = opaque;
4be21d56 2189 uint32_t section_hdr;
e68cb8b4 2190 int fd = -1;
14b0d748 2191 Error *local_err = NULL;
4be21d56
DG		 2192
2193 if (version_id < 1 || version_id > 1) {
98a5d100 2194 error_report("htab_load() bad version");
4be21d56
DG		 2195 return -EINVAL;
2196 }
2197
2198 section_hdr = qemu_get_be32(f);
2199
3a384297
BR		 2200 if (section_hdr == -1) {
2201 spapr_free_hpt(spapr);
2202 return 0;
2203 }
2204
4be21d56 2205 if (section_hdr) {
c5f54f3e
DG		 2206 /* First section gives the htab size */
2207 spapr_reallocate_hpt(spapr, section_hdr, &local_err);
2208 if (local_err) {
2209 error_report_err(local_err);
4be21d56
DG		 2210 return -EINVAL;
2211 }
2212 return 0;
2213 }
2214
e68cb8b4
AK		 2215 if (!spapr->htab) {
2216 assert(kvm_enabled());
2217
14b0d748 2218 fd = kvmppc_get_htab_fd(true, 0, &local_err);
e68cb8b4 2219 if (fd < 0) {
14b0d748 2220 error_report_err(local_err);
82be8e73 2221 return fd;
e68cb8b4
AK		 2222 }
2223 }
2224
4be21d56
DG		 2225 while (true) {
2226 uint32_t index;
2227 uint16_t n_valid, n_invalid;
2228
2229 index = qemu_get_be32(f);
2230 n_valid = qemu_get_be16(f);
2231 n_invalid = qemu_get_be16(f);
2232
2233 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) {
2234 /* End of Stream */
2235 break;
2236 }
2237
e68cb8b4 2238 if ((index + n_valid + n_invalid) >
4be21d56
DG		 2239 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) {
2240 /* Bad index in stream */
98a5d100
DG		 2241 error_report(
2242 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
2243 index, n_valid, n_invalid, spapr->htab_shift);
4be21d56
DG		 2244 return -EINVAL;
2245 }
2246
e68cb8b4
AK		 2247 if (spapr->htab) {
2248 if (n_valid) {
2249 qemu_get_buffer(f, HPTE(spapr->htab, index),
2250 HASH_PTE_SIZE_64 * n_valid);
2251 }
2252 if (n_invalid) {
2253 memset(HPTE(spapr->htab, index + n_valid), 0,
2254 HASH_PTE_SIZE_64 * n_invalid);
2255 }
2256 } else {
2257 int rc;
2258
2259 assert(fd >= 0);
2260
2261 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid);
2262 if (rc < 0) {
2263 return rc;
2264 }
4be21d56
DG		 2265 }
2266 }
2267
e68cb8b4
AK		 2268 if (!spapr->htab) {
2269 assert(fd >= 0);
2270 close(fd);
2271 }
2272
4be21d56
DG		 2273 return 0;
2274}
2275
70f794fc 2276static void htab_save_cleanup(void *opaque)
c573fc03
TH		 2277{
2278 sPAPRMachineState *spapr = opaque;
2279
2280 close_htab_fd(spapr);
2281}
2282
4be21d56 2283static SaveVMHandlers savevm_htab_handlers = {
9907e842 2284 .save_setup = htab_save_setup,
4be21d56 2285 .save_live_iterate = htab_save_iterate,
a3e06c3d 2286 .save_live_complete_precopy = htab_save_complete,
70f794fc 2287 .save_cleanup = htab_save_cleanup,
4be21d56
DG		 2288 .load_state = htab_load,
2289};
2290
5b2128d2
AG		 2291static void spapr_boot_set(void *opaque, const char *boot_device,
2292 Error **errp)
2293{
c86c1aff 2294 MachineState *machine = MACHINE(opaque);
5b2128d2
AG		 2295 machine->boot_order = g_strdup(boot_device);
2296}
2297
224245bf
DG		 2298static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr)
2299{
2300 MachineState *machine = MACHINE(spapr);
2301 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
e8f986fc 2302 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size;
224245bf
DG		 2303 int i;
2304
2305 for (i = 0; i < nr_lmbs; i++) {
224245bf
DG		 2306 uint64_t addr;
2307
b0c14ec4 2308 addr = i * lmb_size + machine->device_memory->base;
6caf3ac6
DG		 2309 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB,
2310 addr / lmb_size);
224245bf
DG		 2311 }
2312}
2313
2314/*
2315 * If RAM size, maxmem size and individual node mem sizes aren't aligned
2316 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest
2317 * since we can't support such unaligned sizes with DRCONF_MEMORY.
2318 */
7c150d6f 2319static void spapr_validate_node_memory(MachineState *machine, Error **errp)
224245bf
DG		 2320{
2321 int i;
2322
7c150d6f
DG		 2323 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) {
2324 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT
2325 " is not aligned to %llu MiB",
2326 machine->ram_size,
2327 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
2328 return;
2329 }
2330
2331 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) {
2332 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT
2333 " is not aligned to %llu MiB",
2334 machine->ram_size,
2335 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
2336 return;
224245bf
DG		 2337 }
2338
2339 for (i = 0; i < nb_numa_nodes; i++) {
2340 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) {
7c150d6f
DG		 2341 error_setg(errp,
2342 "Node %d memory size 0x%" PRIx64
2343 " is not aligned to %llu MiB",
2344 i, numa_info[i].node_mem,
2345 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
2346 return;
224245bf
DG		 2347 }
2348 }
2349}
2350
535455fd
IM		 2351/* find cpu slot in machine->possible_cpus by core_id */
2352static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
2353{
2354 int index = id / smp_threads;
2355
2356 if (index >= ms->possible_cpus->len) {
2357 return NULL;
2358 }
2359 if (idx) {
2360 *idx = index;
2361 }
2362 return &ms->possible_cpus->cpus[index];
2363}
2364
fa98fbfc
SB		 2365static void spapr_set_vsmt_mode(sPAPRMachineState *spapr, Error **errp)
2366{
2367 Error *local_err = NULL;
2368 bool vsmt_user = !!spapr->vsmt;
2369 int kvm_smt = kvmppc_smt_threads();
2370 int ret;
2371
2372 if (!kvm_enabled() && (smp_threads > 1)) {
2373 error_setg(&local_err, "TCG cannot support more than 1 thread/core "
2374 "on a pseries machine");
2375 goto out;
2376 }
2377 if (!is_power_of_2(smp_threads)) {
2378 error_setg(&local_err, "Cannot support %d threads/core on a pseries "
2379 "machine because it must be a power of 2", smp_threads);
2380 goto out;
2381 }
2382
2383 /* Detemine the VSMT mode to use: */
2384 if (vsmt_user) {
2385 if (spapr->vsmt < smp_threads) {
2386 error_setg(&local_err, "Cannot support VSMT mode %d"
2387 " because it must be >= threads/core (%d)",
2388 spapr->vsmt, smp_threads);
2389 goto out;
2390 }
2391 /* In this case, spapr->vsmt has been set by the command line */
2392 } else {
8904e5a7
DG		 2393 /*
2394 * Default VSMT value is tricky, because we need it to be as
2395 * consistent as possible (for migration), but this requires
2396 * changing it for at least some existing cases. We pick 8 as
2397 * the value that we'd get with KVM on POWER8, the
2398 * overwhelmingly common case in production systems.
2399 */
4ad64cbd 2400 spapr->vsmt = MAX(8, smp_threads);
fa98fbfc
SB		 2401 }
2402
2403 /* KVM: If necessary, set the SMT mode: */
2404 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) {
2405 ret = kvmppc_set_smt_threads(spapr->vsmt);
2406 if (ret) {
1f20f2e0 2407 /* Looks like KVM isn't able to change VSMT mode */
fa98fbfc
SB		 2408 error_setg(&local_err,
2409 "Failed to set KVM's VSMT mode to %d (errno %d)",
2410 spapr->vsmt, ret);
1f20f2e0
DG		 2411 /* We can live with that if the default one is big enough
2412 * for the number of threads, and a submultiple of the one
2413 * we want. In this case we'll waste some vcpu ids, but
2414 * behaviour will be correct */
2415 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) {
2416 warn_report_err(local_err);
2417 local_err = NULL;
2418 goto out;
2419 } else {
2420 if (!vsmt_user) {
2421 error_append_hint(&local_err,
2422 "On PPC, a VM with %d threads/core"
2423 " on a host with %d threads/core"
2424 " requires the use of VSMT mode %d.\n",
2425 smp_threads, kvm_smt, spapr->vsmt);
2426 }
2427 kvmppc_hint_smt_possible(&local_err);
2428 goto out;
fa98fbfc 2429 }
fa98fbfc
SB		 2430 }
2431 }
2432 /* else TCG: nothing to do currently */
2433out:
2434 error_propagate(errp, local_err);
2435}
2436
1a5008fc
GK		 2437static void spapr_init_cpus(sPAPRMachineState *spapr)
2438{
2439 MachineState *machine = MACHINE(spapr);
2440 MachineClass *mc = MACHINE_GET_CLASS(machine);
2441 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
2442 const char *type = spapr_get_cpu_core_type(machine->cpu_type);
2443 const CPUArchIdList *possible_cpus;
2444 int boot_cores_nr = smp_cpus / smp_threads;
2445 int i;
2446
2447 possible_cpus = mc->possible_cpu_arch_ids(machine);
2448 if (mc->has_hotpluggable_cpus) {
2449 if (smp_cpus % smp_threads) {
2450 error_report("smp_cpus (%u) must be multiple of threads (%u)",
2451 smp_cpus, smp_threads);
2452 exit(1);
2453 }
2454 if (max_cpus % smp_threads) {
2455 error_report("max_cpus (%u) must be multiple of threads (%u)",
2456 max_cpus, smp_threads);
2457 exit(1);
2458 }
2459 } else {
2460 if (max_cpus != smp_cpus) {
2461 error_report("This machine version does not support CPU hotplug");
2462 exit(1);
2463 }
2464 boot_cores_nr = possible_cpus->len;
2465 }
2466
2467 /* VSMT must be set in order to be able to compute VCPU ids, ie to
2468 * call xics_max_server_number() or spapr_vcpu_id().
2469 */
2470 spapr_set_vsmt_mode(spapr, &error_fatal);
2471
2472 if (smc->pre_2_10_has_unused_icps) {
2473 int i;
2474
2475 for (i = 0; i < xics_max_server_number(spapr); i++) {
2476 /* Dummy entries get deregistered when real ICPState objects
2477 * are registered during CPU core hotplug.
2478 */
2479 pre_2_10_vmstate_register_dummy_icp(i);
2480 }
2481 }
2482
2483 for (i = 0; i < possible_cpus->len; i++) {
2484 int core_id = i * smp_threads;
2485
2486 if (mc->has_hotpluggable_cpus) {
2487 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU,
2488 spapr_vcpu_id(spapr, core_id));
2489 }
2490
2491 if (i < boot_cores_nr) {
2492 Object *core = object_new(type);
2493 int nr_threads = smp_threads;
2494
2495 /* Handle the partially filled core for older machine types */
2496 if ((i + 1) * smp_threads >= smp_cpus) {
2497 nr_threads = smp_cpus - i * smp_threads;
2498 }
2499
2500 object_property_set_int(core, nr_threads, "nr-threads",
2501 &error_fatal);
2502 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID,
2503 &error_fatal);
2504 object_property_set_bool(core, true, "realized", &error_fatal);
2505 }
2506 }
2507}
2508
9fdf0c29 2509/* pSeries LPAR / sPAPR hardware init */
bcb5ce08 2510static void spapr_machine_init(MachineState *machine)
9fdf0c29 2511{
28e02042 2512 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
224245bf 2513 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
3ef96221 2514 const char *kernel_filename = machine->kernel_filename;
3ef96221 2515 const char *initrd_filename = machine->initrd_filename;
8c9f64df 2516 PCIHostState *phb;
9fdf0c29 2517 int i;
890c2b77
AK		 2518 MemoryRegion *sysmem = get_system_memory();
2519 MemoryRegion *ram = g_new(MemoryRegion, 1);
c86c1aff 2520 hwaddr node0_size = spapr_node0_size(machine);
b7d1f77a 2521 long load_limit, fw_size;
39ac8455 2522 char *filename;
30f4b05b 2523 Error *resize_hpt_err = NULL;
9fdf0c29 2524
226419d6 2525 msi_nonbroken = true;
0ee2c058 2526
d43b45e2 2527 QLIST_INIT(&spapr->phbs);
0cffce56 2528 QTAILQ_INIT(&spapr->pending_dimm_unplugs);
d43b45e2 2529
9f6edd06
DG		 2530 /* Determine capabilities to run with */
2531 spapr_caps_init(spapr);
2532
30f4b05b
DG		 2533 kvmppc_check_papr_resize_hpt(&resize_hpt_err);
2534 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) {
2535 /*
2536 * If the user explicitly requested a mode we should either
2537 * supply it, or fail completely (which we do below). But if
2538 * it's not set explicitly, we reset our mode to something
2539 * that works
2540 */
2541 if (resize_hpt_err) {
2542 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED;
2543 error_free(resize_hpt_err);
2544 resize_hpt_err = NULL;
2545 } else {
2546 spapr->resize_hpt = smc->resize_hpt_default;
2547 }
2548 }
2549
2550 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT);
2551
2552 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) {
2553 /*
2554 * User requested HPT resize, but this host can't supply it. Bail out
2555 */
2556 error_report_err(resize_hpt_err);
2557 exit(1);
2558 }
2559
090052aa 2560 spapr->rma_size = node0_size;
354ac20a 2561
090052aa
DG		 2562 /* With KVM, we don't actually know whether KVM supports an
2563 * unbounded RMA (PR KVM) or is limited by the hash table size
2564 * (HV KVM using VRMA), so we always assume the latter
2565 *
2566 * In that case, we also limit the initial allocations for RTAS
2567 * etc... to 256M since we have no way to know what the VRMA size
2568 * is going to be as it depends on the size of the hash table
2569 * which isn't determined yet.
2570 */
2571 if (kvm_enabled()) {
2572 spapr->vrma_adjust = 1;
2573 spapr->rma_size = MIN(spapr->rma_size, 0x10000000);
354ac20a 2574 }
7f763a5d 2575
090052aa
DG		 2576 /* Actually we don't support unbounded RMA anymore since we added
2577 * proper emulation of HV mode. The max we can get is 16G which
2578 * also happens to be what we configure for PAPR mode so make sure
2579 * we don't do anything bigger than that
2580 */
2581 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull);
354ac20a 2582
c4177479 2583 if (spapr->rma_size > node0_size) {
d54e4d76
DG		 2584 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")",
2585 spapr->rma_size);
c4177479
AK		 2586 exit(1);
2587 }
2588
b7d1f77a
BH		 2589 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */
2590 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD;
9fdf0c29 2591
7b565160 2592 /* Set up Interrupt Controller before we create the VCPUs */
71cd4dac 2593 xics_system_init(machine, XICS_IRQS_SPAPR, &error_fatal);
7b565160 2594
dc1b5eee
GK		 2595 /* Set up containers for ibm,client-architecture-support negotiated options
2596 */
facdb8b6
MR		 2597 spapr->ov5 = spapr_ovec_new();
2598 spapr->ov5_cas = spapr_ovec_new();
2599
224245bf 2600 if (smc->dr_lmb_enabled) {
facdb8b6 2601 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY);
7c150d6f 2602 spapr_validate_node_memory(machine, &error_fatal);
224245bf
DG		 2603 }
2604
417ece33
MR		 2605 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY);
2606
ffbb1705
MR		 2607 /* advertise support for dedicated HP event source to guests */
2608 if (spapr->use_hotplug_event_source) {
2609 spapr_ovec_set(spapr->ov5, OV5_HP_EVT);
2610 }
2611
2772cf6b
DG		 2612 /* advertise support for HPT resizing */
2613 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) {
2614 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE);
2615 }
2616
a324d6f1
BR		 2617 /* advertise support for ibm,dyamic-memory-v2 */
2618 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2);
2619
9fdf0c29 2620 /* init CPUs */
0c86d0fd 2621 spapr_init_cpus(spapr);
9fdf0c29 2622
0550b120 2623 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) &&
ad99d04c
DG		 2624 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0,
2625 spapr->max_compat_pvr)) {
0550b120
GK		 2626 /* KVM and TCG always allow GTSE with radix... */
2627 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE);
2628 }
2629 /* ... but not with hash (currently). */
2630
026bfd89
DG		 2631 if (kvm_enabled()) {
2632 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */
2633 kvmppc_enable_logical_ci_hcalls();
ef9971dd 2634 kvmppc_enable_set_mode_hcall();
5145ad4f
NW		 2635
2636 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */
2637 kvmppc_enable_clear_ref_mod_hcalls();
026bfd89
DG		 2638 }
2639
9fdf0c29 2640 /* allocate RAM */
f92f5da1 2641 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram",
fb164994 2642 machine->ram_size);
f92f5da1 2643 memory_region_add_subregion(sysmem, 0, ram);
9fdf0c29 2644
b0c14ec4
DH		 2645 /* always allocate the device memory information */
2646 machine->device_memory = g_malloc0(sizeof(*machine->device_memory));
2647
4a1c9cf0
BR		 2648 /* initialize hotplug memory address space */
2649 if (machine->ram_size < machine->maxram_size) {
0c9269a5 2650 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size;
71c9a3dd
BR		 2651 /*
2652 * Limit the number of hotpluggable memory slots to half the number
2653 * slots that KVM supports, leaving the other half for PCI and other
2654 * devices. However ensure that number of slots doesn't drop below 32.
2655 */
2656 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 :
2657 SPAPR_MAX_RAM_SLOTS;
4a1c9cf0 2658
71c9a3dd
BR		 2659 if (max_memslots < SPAPR_MAX_RAM_SLOTS) {
2660 max_memslots = SPAPR_MAX_RAM_SLOTS;
2661 }
2662 if (machine->ram_slots > max_memslots) {
d54e4d76
DG		 2663 error_report("Specified number of memory slots %"
2664 PRIu64" exceeds max supported %d",
71c9a3dd 2665 machine->ram_slots, max_memslots);
d54e4d76 2666 exit(1);
4a1c9cf0
BR		 2667 }
2668
b0c14ec4 2669 machine->device_memory->base = ROUND_UP(machine->ram_size,
0c9269a5 2670 SPAPR_DEVICE_MEM_ALIGN);
b0c14ec4 2671 memory_region_init(&machine->device_memory->mr, OBJECT(spapr),
0c9269a5 2672 "device-memory", device_mem_size);
b0c14ec4
DH		 2673 memory_region_add_subregion(sysmem, machine->device_memory->base,
2674 &machine->device_memory->mr);
4a1c9cf0
BR		 2675 }
2676
224245bf
DG		 2677 if (smc->dr_lmb_enabled) {
2678 spapr_create_lmb_dr_connectors(spapr);
2679 }
2680
39ac8455 2681 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
4c56440d 2682 if (!filename) {
730fce59 2683 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin");
4c56440d
SW		 2684 exit(1);
2685 }
b7d1f77a 2686 spapr->rtas_size = get_image_size(filename);
8afc22a2
ZJ		 2687 if (spapr->rtas_size < 0) {
2688 error_report("Could not get size of LPAR rtas '%s'", filename);
2689 exit(1);
2690 }
b7d1f77a
BH		 2691 spapr->rtas_blob = g_malloc(spapr->rtas_size);
2692 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) {
730fce59 2693 error_report("Could not load LPAR rtas '%s'", filename);
39ac8455
DG		 2694 exit(1);
2695 }
4d8d5467 2696 if (spapr->rtas_size > RTAS_MAX_SIZE) {
730fce59
TH		 2697 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)",
2698 (size_t)spapr->rtas_size, RTAS_MAX_SIZE);
4d8d5467
BH		 2699 exit(1);
2700 }
7267c094 2701 g_free(filename);
39ac8455 2702
ffbb1705 2703 /* Set up RTAS event infrastructure */
74d042e5
DG		 2704 spapr_events_init(spapr);
2705
12f42174 2706 /* Set up the RTC RTAS interfaces */
28df36a1 2707 spapr_rtc_create(spapr);
12f42174 2708
b5cec4c5 2709 /* Set up VIO bus */
4040ab72
DG		 2710 spapr->vio_bus = spapr_vio_bus_init();
2711
b8846a4d 2712 for (i = 0; i < serial_max_hds(); i++) {
9bca0edb
PM		 2713 if (serial_hd(i)) {
2714 spapr_vty_create(spapr->vio_bus, serial_hd(i));
4040ab72
DG		 2715 }
2716 }
9fdf0c29 2717
639e8102
DG		 2718 /* We always have at least the nvram device on VIO */
2719 spapr_create_nvram(spapr);
2720
3384f95c 2721 /* Set up PCI */
fa28f71b
AK		 2722 spapr_pci_rtas_init();
2723
89dfd6e1 2724 phb = spapr_create_phb(spapr, 0);
3384f95c 2725
277f9acf 2726 for (i = 0; i < nb_nics; i++) {
8d90ad90
DG		 2727 NICInfo *nd = &nd_table[i];
2728
2729 if (!nd->model) {
3c3a4e7a 2730 nd->model = g_strdup("spapr-vlan");
8d90ad90
DG		 2731 }
2732
3c3a4e7a
TH		 2733 if (g_str_equal(nd->model, "spapr-vlan") ||
2734 g_str_equal(nd->model, "ibmveth")) {
d601fac4 2735 spapr_vlan_create(spapr->vio_bus, nd);
8d90ad90 2736 } else {
29b358f9 2737 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL);
8d90ad90
DG		 2738 }
2739 }
2740
6e270446 2741 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) {
d601fac4 2742 spapr_vscsi_create(spapr->vio_bus);
6e270446
BH		 2743 }
2744
f28359d8 2745 /* Graphics */
14c6a894 2746 if (spapr_vga_init(phb->bus, &error_fatal)) {
3fc5acde 2747 spapr->has_graphics = true;
c6e76503 2748 machine->usb |= defaults_enabled() && !machine->usb_disabled;
f28359d8
LZ		 2749 }
2750
4ee9ced9 2751 if (machine->usb) {
57040d45
TH		 2752 if (smc->use_ohci_by_default) {
2753 pci_create_simple(phb->bus, -1, "pci-ohci");
2754 } else {
2755 pci_create_simple(phb->bus, -1, "nec-usb-xhci");
2756 }
c86580b8 2757
35139a59 2758 if (spapr->has_graphics) {
c86580b8
MA		 2759 USBBus *usb_bus = usb_bus_find(-1);
2760
2761 usb_create_simple(usb_bus, "usb-kbd");
2762 usb_create_simple(usb_bus, "usb-mouse");
35139a59
DG		 2763 }
2764 }
2765
7f763a5d 2766 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) {
d54e4d76
DG		 2767 error_report(
2768 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)",
2769 MIN_RMA_SLOF);
4d8d5467
BH		 2770 exit(1);
2771 }
2772
9fdf0c29
DG		 2773 if (kernel_filename) {
2774 uint64_t lowaddr = 0;
2775
a19f7fb0
DG		 2776 spapr->kernel_size = load_elf(kernel_filename, translate_kernel_address,
2777 NULL, NULL, &lowaddr, NULL, 1,
2778 PPC_ELF_MACHINE, 0, 0);
2779 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) {
2780 spapr->kernel_size = load_elf(kernel_filename,
2781 translate_kernel_address, NULL, NULL,
2782 &lowaddr, NULL, 0, PPC_ELF_MACHINE,
2783 0, 0);
2784 spapr->kernel_le = spapr->kernel_size > 0;
16457e7f 2785 }
a19f7fb0
DG		 2786 if (spapr->kernel_size < 0) {
2787 error_report("error loading %s: %s", kernel_filename,
2788 load_elf_strerror(spapr->kernel_size));
9fdf0c29
DG		 2789 exit(1);
2790 }
2791
2792 /* load initrd */
2793 if (initrd_filename) {
4d8d5467
BH		 2794 /* Try to locate the initrd in the gap between the kernel
2795 * and the firmware. Add a bit of space just in case
2796 */
a19f7fb0
DG		 2797 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size
2798 + 0x1ffff) & ~0xffff;
2799 spapr->initrd_size = load_image_targphys(initrd_filename,
2800 spapr->initrd_base,
2801 load_limit
2802 - spapr->initrd_base);
2803 if (spapr->initrd_size < 0) {
d54e4d76
DG		 2804 error_report("could not load initial ram disk '%s'",
2805 initrd_filename);
9fdf0c29
DG		 2806 exit(1);
2807 }
9fdf0c29 2808 }
4d8d5467 2809 }
a3467baa 2810
8e7ea787
AF		 2811 if (bios_name == NULL) {
2812 bios_name = FW_FILE_NAME;
2813 }
2814 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
4c56440d 2815 if (!filename) {
68fea5a0 2816 error_report("Could not find LPAR firmware '%s'", bios_name);
4c56440d
SW		 2817 exit(1);
2818 }
4d8d5467 2819 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
68fea5a0
TH		 2820 if (fw_size <= 0) {
2821 error_report("Could not load LPAR firmware '%s'", filename);
4d8d5467
BH		 2822 exit(1);
2823 }
2824 g_free(filename);
4d8d5467 2825
28e02042
DG		 2826 /* FIXME: Should register things through the MachineState's qdev
2827 * interface, this is a legacy from the sPAPREnvironment structure
2828 * which predated MachineState but had a similar function */
4be21d56
DG		 2829 vmstate_register(NULL, 0, &vmstate_spapr, spapr);
2830 register_savevm_live(NULL, "spapr/htab", -1, 1,
2831 &savevm_htab_handlers, spapr);
2832
5b2128d2 2833 qemu_register_boot_set(spapr_boot_set, spapr);
42043e4f 2834
42043e4f 2835 if (kvm_enabled()) {
3dc410ae 2836 /* to stop and start vmclock */
42043e4f
LV		 2837 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change,
2838 &spapr->tb);
3dc410ae
AK		 2839
2840 kvmppc_spapr_enable_inkernel_multitce();
42043e4f 2841 }
9fdf0c29
DG		 2842}
2843
135a129a
AK		 2844static int spapr_kvm_type(const char *vm_type)
2845{
2846 if (!vm_type) {
2847 return 0;
2848 }
2849
2850 if (!strcmp(vm_type, "HV")) {
2851 return 1;
2852 }
2853
2854 if (!strcmp(vm_type, "PR")) {
2855 return 2;
2856 }
2857
2858 error_report("Unknown kvm-type specified '%s'", vm_type);
2859 exit(1);
2860}
2861
71461b0f 2862/*
627b84f4 2863 * Implementation of an interface to adjust firmware path
71461b0f
AK		 2864 * for the bootindex property handling.
2865 */
2866static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus,
2867 DeviceState *dev)
2868{
2869#define CAST(type, obj, name) \
2870 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
2871 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE);
2872 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE);
c4e13492 2873 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON);
71461b0f
AK		 2874
2875 if (d) {
2876 void *spapr = CAST(void, bus->parent, "spapr-vscsi");
2877 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI);
2878 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE);
2879
2880 if (spapr) {
2881 /*
2882 * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
2883 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun
2884 * in the top 16 bits of the 64-bit LUN
2885 */
2886 unsigned id = 0x8000 | (d->id << 8) | d->lun;
2887 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2888 (uint64_t)id << 48);
2889 } else if (virtio) {
2890 /*
2891 * We use SRP luns of the form 01000000 | (target << 8) | lun
2892 * in the top 32 bits of the 64-bit LUN
2893 * Note: the quote above is from SLOF and it is wrong,
2894 * the actual binding is:
2895 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
2896 */
2897 unsigned id = 0x1000000 | (d->id << 16) | d->lun;
bac658d1
TH		 2898 if (d->lun >= 256) {
2899 /* Use the LUN "flat space addressing method" */
2900 id |= 0x4000;
2901 }
71461b0f
AK		 2902 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2903 (uint64_t)id << 32);
2904 } else if (usb) {
2905 /*
2906 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
2907 * in the top 32 bits of the 64-bit LUN
2908 */
2909 unsigned usb_port = atoi(usb->port->path);
2910 unsigned id = 0x1000000 | (usb_port << 16) | d->lun;
2911 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2912 (uint64_t)id << 32);
2913 }
2914 }
2915
b99260eb
TH		 2916 /*
2917 * SLOF probes the USB devices, and if it recognizes that the device is a
2918 * storage device, it changes its name to "storage" instead of "usb-host",
2919 * and additionally adds a child node for the SCSI LUN, so the correct
2920 * boot path in SLOF is something like .../storage@1/disk@xxx" instead.
2921 */
2922 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) {
2923 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE);
2924 if (usb_host_dev_is_scsi_storage(usbdev)) {
2925 return g_strdup_printf("storage@%s/disk", usbdev->port->path);
2926 }
2927 }
2928
71461b0f
AK		 2929 if (phb) {
2930 /* Replace "pci" with "pci@800000020000000" */
2931 return g_strdup_printf("pci@%"PRIX64, phb->buid);
2932 }
2933
c4e13492
FF		 2934 if (vsc) {
2935 /* Same logic as virtio above */
2936 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun;
2937 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32);
2938 }
2939
4871dd4c
TH		 2940 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) {
2941 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */
2942 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE);
2943 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn));
2944 }
2945
71461b0f
AK		 2946 return NULL;
2947}
2948
23825581
EH		 2949static char *spapr_get_kvm_type(Object *obj, Error **errp)
2950{
28e02042 2951 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
23825581 2952
28e02042 2953 return g_strdup(spapr->kvm_type);
23825581
EH		 2954}
2955
2956static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp)
2957{
28e02042 2958 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
23825581 2959
28e02042
DG		 2960 g_free(spapr->kvm_type);
2961 spapr->kvm_type = g_strdup(value);
23825581
EH		 2962}
2963
f6229214
MR		 2964static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp)
2965{
2966 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2967
2968 return spapr->use_hotplug_event_source;
2969}
2970
2971static void spapr_set_modern_hotplug_events(Object *obj, bool value,
2972 Error **errp)
2973{
2974 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2975
2976 spapr->use_hotplug_event_source = value;
2977}
2978
fcad0d21
AK		 2979static bool spapr_get_msix_emulation(Object *obj, Error **errp)
2980{
2981 return true;
2982}
2983
30f4b05b
DG		 2984static char *spapr_get_resize_hpt(Object *obj, Error **errp)
2985{
2986 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2987
2988 switch (spapr->resize_hpt) {
2989 case SPAPR_RESIZE_HPT_DEFAULT:
2990 return g_strdup("default");
2991 case SPAPR_RESIZE_HPT_DISABLED:
2992 return g_strdup("disabled");
2993 case SPAPR_RESIZE_HPT_ENABLED:
2994 return g_strdup("enabled");
2995 case SPAPR_RESIZE_HPT_REQUIRED:
2996 return g_strdup("required");
2997 }
2998 g_assert_not_reached();
2999}
3000
3001static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp)
3002{
3003 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
3004
3005 if (strcmp(value, "default") == 0) {
3006 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT;
3007 } else if (strcmp(value, "disabled") == 0) {
3008 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED;
3009 } else if (strcmp(value, "enabled") == 0) {
3010 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED;
3011 } else if (strcmp(value, "required") == 0) {
3012 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED;
3013 } else {
3014 error_setg(errp, "Bad value for \"resize-hpt\" property");
3015 }
3016}
3017
fa98fbfc
SB		 3018static void spapr_get_vsmt(Object *obj, Visitor *v, const char *name,
3019 void *opaque, Error **errp)
3020{
3021 visit_type_uint32(v, name, (uint32_t *)opaque, errp);
3022}
3023
3024static void spapr_set_vsmt(Object *obj, Visitor *v, const char *name,
3025 void *opaque, Error **errp)
3026{
3027 visit_type_uint32(v, name, (uint32_t *)opaque, errp);
3028}
3029
bcb5ce08 3030static void spapr_instance_init(Object *obj)
23825581 3031{
715c5407
DG		 3032 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
3033
3034 spapr->htab_fd = -1;
f6229214 3035 spapr->use_hotplug_event_source = true;
23825581
EH		 3036 object_property_add_str(obj, "kvm-type",
3037 spapr_get_kvm_type, spapr_set_kvm_type, NULL);
49d2e648
MA		 3038 object_property_set_description(obj, "kvm-type",
3039 "Specifies the KVM virtualization mode (HV, PR)",
3040 NULL);
f6229214
MR		 3041 object_property_add_bool(obj, "modern-hotplug-events",
3042 spapr_get_modern_hotplug_events,
3043 spapr_set_modern_hotplug_events,
3044 NULL);
3045 object_property_set_description(obj, "modern-hotplug-events",
3046 "Use dedicated hotplug event mechanism in"
3047 " place of standard EPOW events when possible"
3048 " (required for memory hot-unplug support)",
3049 NULL);
7843c0d6
DG		 3050 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr,
3051 "Maximum permitted CPU compatibility mode",
3052 &error_fatal);
30f4b05b
DG		 3053
3054 object_property_add_str(obj, "resize-hpt",
3055 spapr_get_resize_hpt, spapr_set_resize_hpt, NULL);
3056 object_property_set_description(obj, "resize-hpt",
3057 "Resizing of the Hash Page Table (enabled, disabled, required)",
3058 NULL);
fa98fbfc
SB		 3059 object_property_add(obj, "vsmt", "uint32", spapr_get_vsmt,
3060 spapr_set_vsmt, NULL, &spapr->vsmt, &error_abort);
3061 object_property_set_description(obj, "vsmt",
3062 "Virtual SMT: KVM behaves as if this were"
3063 " the host's SMT mode", &error_abort);
fcad0d21
AK		 3064 object_property_add_bool(obj, "vfio-no-msix-emulation",
3065 spapr_get_msix_emulation, NULL, NULL);
23825581
EH		 3066}
3067
87bbdd9c
DG		 3068static void spapr_machine_finalizefn(Object *obj)
3069{
3070 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
3071
3072 g_free(spapr->kvm_type);
3073}
3074
1c7ad77e 3075void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg)
34316482 3076{
34316482
AK		 3077 cpu_synchronize_state(cs);
3078 ppc_cpu_do_system_reset(cs);
3079}
3080
3081static void spapr_nmi(NMIState *n, int cpu_index, Error **errp)
3082{
3083 CPUState *cs;
3084
3085 CPU_FOREACH(cs) {
1c7ad77e 3086 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL);
34316482
AK		 3087 }
3088}
3089
79b78a6b
MR		 3090static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size,
3091 uint32_t node, bool dedicated_hp_event_source,
3092 Error **errp)
c20d332a
BR		 3093{
3094 sPAPRDRConnector *drc;
c20d332a
BR		 3095 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE;
3096 int i, fdt_offset, fdt_size;
3097 void *fdt;
79b78a6b 3098 uint64_t addr = addr_start;
94fd9cba 3099 bool hotplugged = spapr_drc_hotplugged(dev);
160bb678 3100 Error *local_err = NULL;
c20d332a 3101
c20d332a 3102 for (i = 0; i < nr_lmbs; i++) {
fbf55397
DG		 3103 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3104 addr / SPAPR_MEMORY_BLOCK_SIZE);
c20d332a
BR		 3105 g_assert(drc);
3106
3107 fdt = create_device_tree(&fdt_size);
3108 fdt_offset = spapr_populate_memory_node(fdt, node, addr,
3109 SPAPR_MEMORY_BLOCK_SIZE);
3110
160bb678
GK		 3111 spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err);
3112 if (local_err) {
3113 while (addr > addr_start) {
3114 addr -= SPAPR_MEMORY_BLOCK_SIZE;
3115 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3116 addr / SPAPR_MEMORY_BLOCK_SIZE);
a8dc47fd 3117 spapr_drc_detach(drc);
160bb678
GK		 3118 }
3119 g_free(fdt);
3120 error_propagate(errp, local_err);
3121 return;
3122 }
94fd9cba
LV		 3123 if (!hotplugged) {
3124 spapr_drc_reset(drc);
3125 }
c20d332a
BR		 3126 addr += SPAPR_MEMORY_BLOCK_SIZE;
3127 }
5dd5238c
JD		 3128 /* send hotplug notification to the
3129 * guest only in case of hotplugged memory
3130 */
94fd9cba 3131 if (hotplugged) {
79b78a6b 3132 if (dedicated_hp_event_source) {
fbf55397
DG		 3133 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3134 addr_start / SPAPR_MEMORY_BLOCK_SIZE);
79b78a6b
MR		 3135 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB,
3136 nr_lmbs,
0b55aa91 3137 spapr_drc_index(drc));
79b78a6b
MR		 3138 } else {
3139 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB,
3140 nr_lmbs);
3141 }
5dd5238c 3142 }
c20d332a
BR		 3143}
3144
3145static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
81985f3b 3146 Error **errp)
c20d332a
BR		 3147{
3148 Error *local_err = NULL;
3149 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev);
3150 PCDIMMDevice *dimm = PC_DIMM(dev);
3151 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
04790978
TH		 3152 MemoryRegion *mr;
3153 uint64_t align, size, addr;
81985f3b 3154 uint32_t node;
04790978
TH		 3155
3156 mr = ddc->get_memory_region(dimm, &local_err);
3157 if (local_err) {
3158 goto out;
3159 }
3160 align = memory_region_get_alignment(mr);
3161 size = memory_region_size(mr);
df587133 3162
bd6c3e4a 3163 pc_dimm_memory_plug(dev, MACHINE(ms), align, &local_err);
c20d332a
BR		 3164 if (local_err) {
3165 goto out;
3166 }
3167
9ed442b8
MAL		 3168 addr = object_property_get_uint(OBJECT(dimm),
3169 PC_DIMM_ADDR_PROP, &local_err);
c20d332a 3170 if (local_err) {
160bb678 3171 goto out_unplug;
c20d332a
BR		 3172 }
3173
81985f3b
DH		 3174 node = object_property_get_uint(OBJECT(dev), PC_DIMM_NODE_PROP,
3175 &error_abort);
79b78a6b
MR		 3176 spapr_add_lmbs(dev, addr, size, node,
3177 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT),
160bb678
GK		 3178 &local_err);
3179 if (local_err) {
3180 goto out_unplug;
3181 }
3182
3183 return;
c20d332a 3184
160bb678 3185out_unplug:
bd6c3e4a 3186 pc_dimm_memory_unplug(dev, MACHINE(ms));
c20d332a
BR		 3187out:
3188 error_propagate(errp, local_err);
3189}
3190
c871bc70
LV		 3191static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3192 Error **errp)
3193{
4e8a01bd 3194 const sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev);
c871bc70
LV		 3195 PCDIMMDevice *dimm = PC_DIMM(dev);
3196 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
04790978
TH		 3197 MemoryRegion *mr;
3198 uint64_t size;
c871bc70
LV		 3199 char *mem_dev;
3200
4e8a01bd
DH		 3201 if (!smc->dr_lmb_enabled) {
3202 error_setg(errp, "Memory hotplug not supported for this machine");
3203 return;
3204 }
3205
04790978
TH		 3206 mr = ddc->get_memory_region(dimm, errp);
3207 if (!mr) {
3208 return;
3209 }
3210 size = memory_region_size(mr);
3211
c871bc70
LV		 3212 if (size % SPAPR_MEMORY_BLOCK_SIZE) {
3213 error_setg(errp, "Hotplugged memory size must be a multiple of "
3214 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
3215 return;
3216 }
3217
3218 mem_dev = object_property_get_str(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, NULL);
3219 if (mem_dev && !kvmppc_is_mem_backend_page_size_ok(mem_dev)) {
3220 error_setg(errp, "Memory backend has bad page size. "
3221 "Use 'memory-backend-file' with correct mem-path.");
8a9e0e7b 3222 goto out;
c871bc70 3223 }
8a9e0e7b
GK		 3224
3225out:
3226 g_free(mem_dev);
c871bc70
LV		 3227}
3228
0cffce56
DG		 3229struct sPAPRDIMMState {
3230 PCDIMMDevice *dimm;
cf632463 3231 uint32_t nr_lmbs;
0cffce56
DG		 3232 QTAILQ_ENTRY(sPAPRDIMMState) next;
3233};
3234
3235static sPAPRDIMMState *spapr_pending_dimm_unplugs_find(sPAPRMachineState *s,
3236 PCDIMMDevice *dimm)
3237{
3238 sPAPRDIMMState *dimm_state = NULL;
3239
3240 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) {
3241 if (dimm_state->dimm == dimm) {
3242 break;
3243 }
3244 }
3245 return dimm_state;
3246}
3247
8d5981c4
BR		 3248static sPAPRDIMMState *spapr_pending_dimm_unplugs_add(sPAPRMachineState *spapr,
3249 uint32_t nr_lmbs,
3250 PCDIMMDevice *dimm)
0cffce56 3251{
8d5981c4
BR		 3252 sPAPRDIMMState *ds = NULL;
3253
3254 /*
3255 * If this request is for a DIMM whose removal had failed earlier
3256 * (due to guest's refusal to remove the LMBs), we would have this
3257 * dimm already in the pending_dimm_unplugs list. In that
3258 * case don't add again.
3259 */
3260 ds = spapr_pending_dimm_unplugs_find(spapr, dimm);
3261 if (!ds) {
3262 ds = g_malloc0(sizeof(sPAPRDIMMState));
3263 ds->nr_lmbs = nr_lmbs;
3264 ds->dimm = dimm;
3265 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next);
3266 }
3267 return ds;
0cffce56
DG		 3268}
3269
3270static void spapr_pending_dimm_unplugs_remove(sPAPRMachineState *spapr,
3271 sPAPRDIMMState *dimm_state)
3272{
3273 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next);
3274 g_free(dimm_state);
3275}
cf632463 3276
16ee9980
DHB		 3277static sPAPRDIMMState *spapr_recover_pending_dimm_state(sPAPRMachineState *ms,
3278 PCDIMMDevice *dimm)
3279{
3280 sPAPRDRConnector *drc;
3281 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
04790978 3282 MemoryRegion *mr = ddc->get_memory_region(dimm, &error_abort);
16ee9980
DHB		 3283 uint64_t size = memory_region_size(mr);
3284 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE;
3285 uint32_t avail_lmbs = 0;
3286 uint64_t addr_start, addr;
3287 int i;
16ee9980
DHB		 3288
3289 addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP,
3290 &error_abort);
3291
3292 addr = addr_start;
3293 for (i = 0; i < nr_lmbs; i++) {
fbf55397
DG		 3294 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3295 addr / SPAPR_MEMORY_BLOCK_SIZE);
16ee9980 3296 g_assert(drc);
454b580a 3297 if (drc->dev) {
16ee9980
DHB		 3298 avail_lmbs++;
3299 }
3300 addr += SPAPR_MEMORY_BLOCK_SIZE;
3301 }
3302
8d5981c4 3303 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm);
16ee9980
DHB		 3304}
3305
31834723
DHB		 3306/* Callback to be called during DRC release. */
3307void spapr_lmb_release(DeviceState *dev)
cf632463 3308{
3ec71474
DH		 3309 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev);
3310 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl);
0cffce56 3311 sPAPRDIMMState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev));
cf632463 3312
16ee9980
DHB		 3313 /* This information will get lost if a migration occurs
3314 * during the unplug process. In this case recover it. */
3315 if (ds == NULL) {
3316 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev));
8d5981c4 3317 g_assert(ds);
454b580a
DG		 3318 /* The DRC being examined by the caller at least must be counted */
3319 g_assert(ds->nr_lmbs);
3320 }
3321
3322 if (--ds->nr_lmbs) {
cf632463
BR		 3323 return;
3324 }
3325
cf632463
BR		 3326 /*
3327 * Now that all the LMBs have been removed by the guest, call the
3ec71474 3328 * unplug handler chain. This can never fail.
cf632463 3329 */
3ec71474
DH		 3330 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort);
3331}
3332
3333static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev)
3334{
3335 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev);
3336 sPAPRDIMMState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev));
3337
3338 pc_dimm_memory_unplug(dev, MACHINE(hotplug_dev));
cf632463 3339 object_unparent(OBJECT(dev));
2a129767 3340 spapr_pending_dimm_unplugs_remove(spapr, ds);
cf632463
BR		 3341}
3342
3343static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev,
3344 DeviceState *dev, Error **errp)
3345{
0cffce56 3346 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev);
cf632463
BR		 3347 Error *local_err = NULL;
3348 PCDIMMDevice *dimm = PC_DIMM(dev);
3349 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
04790978
TH		 3350 MemoryRegion *mr;
3351 uint32_t nr_lmbs;
3352 uint64_t size, addr_start, addr;
0cffce56
DG		 3353 int i;
3354 sPAPRDRConnector *drc;
04790978
TH		 3355
3356 mr = ddc->get_memory_region(dimm, &local_err);
3357 if (local_err) {
3358 goto out;
3359 }
3360 size = memory_region_size(mr);
3361 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE;
3362
9ed442b8 3363 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP,
0cffce56 3364 &local_err);
cf632463
BR		 3365 if (local_err) {
3366 goto out;
3367 }
3368
2a129767
DHB		 3369 /*
3370 * An existing pending dimm state for this DIMM means that there is an
3371 * unplug operation in progress, waiting for the spapr_lmb_release
3372 * callback to complete the job (BQL can't cover that far). In this case,
3373 * bail out to avoid detaching DRCs that were already released.
3374 */
3375 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) {
3376 error_setg(&local_err,
3377 "Memory unplug already in progress for device %s",
3378 dev->id);
3379 goto out;
3380 }
3381
8d5981c4 3382 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm);
0cffce56
DG		 3383
3384 addr = addr_start;
3385 for (i = 0; i < nr_lmbs; i++) {
fbf55397
DG		 3386 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3387 addr / SPAPR_MEMORY_BLOCK_SIZE);
0cffce56
DG		 3388 g_assert(drc);
3389
a8dc47fd 3390 spapr_drc_detach(drc);
0cffce56
DG		 3391 addr += SPAPR_MEMORY_BLOCK_SIZE;
3392 }
3393
fbf55397
DG		 3394 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3395 addr_start / SPAPR_MEMORY_BLOCK_SIZE);
0cffce56 3396 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB,
0b55aa91 3397 nr_lmbs, spapr_drc_index(drc));
cf632463
BR		 3398out:
3399 error_propagate(errp, local_err);
3400}
3401
04d0ffbd
GK		 3402static void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset,
3403 sPAPRMachineState *spapr)
af81cf32
BR		 3404{
3405 PowerPCCPU *cpu = POWERPC_CPU(cs);
3406 DeviceClass *dc = DEVICE_GET_CLASS(cs);
14bb4486 3407 int id = spapr_get_vcpu_id(cpu);
af81cf32
BR		 3408 void *fdt;
3409 int offset, fdt_size;
3410 char *nodename;
3411
3412 fdt = create_device_tree(&fdt_size);
3413 nodename = g_strdup_printf("%s@%x", dc->fw_name, id);
3414 offset = fdt_add_subnode(fdt, 0, nodename);
3415
3416 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
3417 g_free(nodename);
3418
3419 *fdt_offset = offset;
3420 return fdt;
3421}
3422
765d1bdd
DG		 3423/* Callback to be called during DRC release. */
3424void spapr_core_release(DeviceState *dev)
ff9006dd 3425{
a4261be1
DH		 3426 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev);
3427
3428 /* Call the unplug handler chain. This can never fail. */
3429 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort);
3430}
3431
3432static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev)
3433{
3434 MachineState *ms = MACHINE(hotplug_dev);
46f7afa3 3435 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms);
ff9006dd 3436 CPUCore *cc = CPU_CORE(dev);
535455fd 3437 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL);
ff9006dd 3438
46f7afa3
GK		 3439 if (smc->pre_2_10_has_unused_icps) {
3440 sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
46f7afa3
GK		 3441 int i;
3442
3443 for (i = 0; i < cc->nr_threads; i++) {
94ad93bd 3444 CPUState *cs = CPU(sc->threads[i]);
46f7afa3
GK		 3445
3446 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index);
3447 }
3448 }
3449
07572c06 3450 assert(core_slot);
535455fd 3451 core_slot->cpu = NULL;
ff9006dd
IM		 3452 object_unparent(OBJECT(dev));
3453}
3454
115debf2
IM		 3455static
3456void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev,
3457 Error **errp)
ff9006dd 3458{
72194664 3459 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
535455fd
IM		 3460 int index;
3461 sPAPRDRConnector *drc;
535455fd 3462 CPUCore *cc = CPU_CORE(dev);
ff9006dd 3463
535455fd
IM		 3464 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) {
3465 error_setg(errp, "Unable to find CPU core with core-id: %d",
3466 cc->core_id);
3467 return;
3468 }
ff9006dd
IM		 3469 if (index == 0) {
3470 error_setg(errp, "Boot CPU core may not be unplugged");
3471 return;
3472 }
3473
5d0fb150
GK		 3474 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU,
3475 spapr_vcpu_id(spapr, cc->core_id));
ff9006dd
IM		 3476 g_assert(drc);
3477
a8dc47fd 3478 spapr_drc_detach(drc);
ff9006dd
IM		 3479
3480 spapr_hotplug_req_remove_by_index(drc);
3481}
3482
3483static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3484 Error **errp)
3485{
3486 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
3487 MachineClass *mc = MACHINE_GET_CLASS(spapr);
46f7afa3 3488 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
ff9006dd
IM		 3489 sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev));
3490 CPUCore *cc = CPU_CORE(dev);
94ad93bd 3491 CPUState *cs = CPU(core->threads[0]);
ff9006dd
IM		 3492 sPAPRDRConnector *drc;
3493 Error *local_err = NULL;
535455fd
IM		 3494 CPUArchId *core_slot;
3495 int index;
94fd9cba 3496 bool hotplugged = spapr_drc_hotplugged(dev);
ff9006dd 3497
535455fd
IM		 3498 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index);
3499 if (!core_slot) {
3500 error_setg(errp, "Unable to find CPU core with core-id: %d",
3501 cc->core_id);
3502 return;
3503 }
5d0fb150
GK		 3504 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU,
3505 spapr_vcpu_id(spapr, cc->core_id));
ff9006dd 3506
c5514d0e 3507 g_assert(drc || !mc->has_hotpluggable_cpus);
ff9006dd 3508
ff9006dd 3509 if (drc) {
e49c63d5
GK		 3510 void *fdt;
3511 int fdt_offset;
3512
3513 fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr);
3514
5c1da812 3515 spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err);
ff9006dd
IM		 3516 if (local_err) {
3517 g_free(fdt);
ff9006dd
IM		 3518 error_propagate(errp, local_err);
3519 return;
3520 }
ff9006dd 3521
94fd9cba
LV		 3522 if (hotplugged) {
3523 /*
3524 * Send hotplug notification interrupt to the guest only
3525 * in case of hotplugged CPUs.
3526 */
3527 spapr_hotplug_req_add_by_index(drc);
3528 } else {
3529 spapr_drc_reset(drc);
3530 }
ff9006dd 3531 }
94fd9cba 3532
535455fd 3533 core_slot->cpu = OBJECT(dev);
46f7afa3
GK		 3534
3535 if (smc->pre_2_10_has_unused_icps) {
46f7afa3
GK		 3536 int i;
3537
3538 for (i = 0; i < cc->nr_threads; i++) {
bc877283 3539 cs = CPU(core->threads[i]);
46f7afa3
GK		 3540 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index);
3541 }
3542 }
ff9006dd
IM		 3543}
3544
3545static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3546 Error **errp)
3547{
3548 MachineState *machine = MACHINE(OBJECT(hotplug_dev));
3549 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev);
ff9006dd
IM		 3550 Error *local_err = NULL;
3551 CPUCore *cc = CPU_CORE(dev);
2e9c10eb 3552 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type);
ff9006dd 3553 const char *type = object_get_typename(OBJECT(dev));
535455fd
IM		 3554 CPUArchId *core_slot;
3555 int index;
ff9006dd 3556
c5514d0e 3557 if (dev->hotplugged && !mc->has_hotpluggable_cpus) {
ff9006dd
IM		 3558 error_setg(&local_err, "CPU hotplug not supported for this machine");
3559 goto out;
3560 }
3561
3562 if (strcmp(base_core_type, type)) {
3563 error_setg(&local_err, "CPU core type should be %s", base_core_type);
3564 goto out;
3565 }
3566
3567 if (cc->core_id % smp_threads) {
3568 error_setg(&local_err, "invalid core id %d", cc->core_id);
3569 goto out;
3570 }
3571
459264ef
DG		 3572 /*
3573 * In general we should have homogeneous threads-per-core, but old
3574 * (pre hotplug support) machine types allow the last core to have
3575 * reduced threads as a compatibility hack for when we allowed
3576 * total vcpus not a multiple of threads-per-core.
3577 */
3578 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) {
df8658de 3579 error_setg(&local_err, "invalid nr-threads %d, must be %d",
8149e299 3580 cc->nr_threads, smp_threads);
df8658de 3581 goto out;
8149e299
DG		 3582 }
3583
535455fd
IM		 3584 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index);
3585 if (!core_slot) {
ff9006dd
IM		 3586 error_setg(&local_err, "core id %d out of range", cc->core_id);
3587 goto out;
3588 }
3589
535455fd 3590 if (core_slot->cpu) {
ff9006dd
IM		 3591 error_setg(&local_err, "core %d already populated", cc->core_id);
3592 goto out;
3593 }
3594
a0ceb640 3595 numa_cpu_pre_plug(core_slot, dev, &local_err);
0b8497f0 3596
ff9006dd 3597out:
ff9006dd
IM		 3598 error_propagate(errp, local_err);
3599}
3600
c20d332a
BR		 3601static void spapr_machine_device_plug(HotplugHandler *hotplug_dev,
3602 DeviceState *dev, Error **errp)
3603{
c20d332a 3604 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
81985f3b 3605 spapr_memory_plug(hotplug_dev, dev, errp);
af81cf32
BR		 3606 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
3607 spapr_core_plug(hotplug_dev, dev, errp);
c20d332a
BR		 3608 }
3609}
3610
88432f44
DH		 3611static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev,
3612 DeviceState *dev, Error **errp)
3613{
3ec71474
DH		 3614 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
3615 spapr_memory_unplug(hotplug_dev, dev);
a4261be1
DH		 3616 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
3617 spapr_core_unplug(hotplug_dev, dev);
3ec71474 3618 }
88432f44
DH		 3619}
3620
cf632463
BR		 3621static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev,
3622 DeviceState *dev, Error **errp)
3623{
c86c1aff
DHB		 3624 sPAPRMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev));
3625 MachineClass *mc = MACHINE_GET_CLASS(sms);
cf632463
BR		 3626
3627 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
3628 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) {
3629 spapr_memory_unplug_request(hotplug_dev, dev, errp);
3630 } else {
3631 /* NOTE: this means there is a window after guest reset, prior to
3632 * CAS negotiation, where unplug requests will fail due to the
3633 * capability not being detected yet. This is a bit different than
3634 * the case with PCI unplug, where the events will be queued and
3635 * eventually handled by the guest after boot
3636 */
3637 error_setg(errp, "Memory hot unplug not supported for this guest");
3638 }
6f4b5c3e 3639 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
c5514d0e 3640 if (!mc->has_hotpluggable_cpus) {
6f4b5c3e
BR		 3641 error_setg(errp, "CPU hot unplug not supported on this machine");
3642 return;
3643 }
115debf2 3644 spapr_core_unplug_request(hotplug_dev, dev, errp);
c20d332a
BR		 3645 }
3646}
3647
94a94e4c
BR		 3648static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev,
3649 DeviceState *dev, Error **errp)
3650{
c871bc70
LV		 3651 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
3652 spapr_memory_pre_plug(hotplug_dev, dev, errp);
3653 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
94a94e4c
BR		 3654 spapr_core_pre_plug(hotplug_dev, dev, errp);
3655 }
3656}
3657
7ebaf795
BR		 3658static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine,
3659 DeviceState *dev)
c20d332a 3660{
94a94e4c
BR		 3661 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
3662 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
c20d332a
BR		 3663 return HOTPLUG_HANDLER(machine);
3664 }
3665 return NULL;
3666}
3667
ea089eeb
IM		 3668static CpuInstanceProperties
3669spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index)
20bb648d 3670{
ea089eeb
IM		 3671 CPUArchId *core_slot;
3672 MachineClass *mc = MACHINE_GET_CLASS(machine);
3673
3674 /* make sure possible_cpu are intialized */
3675 mc->possible_cpu_arch_ids(machine);
3676 /* get CPU core slot containing thread that matches cpu_index */
3677 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL);
3678 assert(core_slot);
3679 return core_slot->props;
20bb648d
DG		 3680}
3681
79e07936
IM		 3682static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx)
3683{
3684 return idx / smp_cores % nb_numa_nodes;
3685}
3686
535455fd
IM		 3687static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine)
3688{
3689 int i;
d342eb76 3690 const char *core_type;
535455fd
IM		 3691 int spapr_max_cores = max_cpus / smp_threads;
3692 MachineClass *mc = MACHINE_GET_CLASS(machine);
3693
c5514d0e 3694 if (!mc->has_hotpluggable_cpus) {
535455fd
IM		 3695 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads;
3696 }
3697 if (machine->possible_cpus) {
3698 assert(machine->possible_cpus->len == spapr_max_cores);
3699 return machine->possible_cpus;
3700 }
3701
d342eb76
IM		 3702 core_type = spapr_get_cpu_core_type(machine->cpu_type);
3703 if (!core_type) {
3704 error_report("Unable to find sPAPR CPU Core definition");
3705 exit(1);
3706 }
3707
535455fd
IM		 3708 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
3709 sizeof(CPUArchId) * spapr_max_cores);
3710 machine->possible_cpus->len = spapr_max_cores;
3711 for (i = 0; i < machine->possible_cpus->len; i++) {
3712 int core_id = i * smp_threads;
3713
d342eb76 3714 machine->possible_cpus->cpus[i].type = core_type;
f2d672c2 3715 machine->possible_cpus->cpus[i].vcpus_count = smp_threads;
535455fd
IM		 3716 machine->possible_cpus->cpus[i].arch_id = core_id;
3717 machine->possible_cpus->cpus[i].props.has_core_id = true;
3718 machine->possible_cpus->cpus[i].props.core_id = core_id;
535455fd
IM		 3719 }
3720 return machine->possible_cpus;
3721}
3722
6737d9ad 3723static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index,
daa23699
DG		 3724 uint64_t *buid, hwaddr *pio,
3725 hwaddr *mmio32, hwaddr *mmio64,
6737d9ad
DG		 3726 unsigned n_dma, uint32_t *liobns, Error **errp)
3727{
357d1e3b
DG		 3728 /*
3729 * New-style PHB window placement.
3730 *
3731 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window
3732 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO
3733 * windows.
3734 *
3735 * Some guest kernels can't work with MMIO windows above 1<<46
3736 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB
3737 *
3738 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each
3739 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the
3740 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the
3741 * 1TiB 64-bit MMIO windows for each PHB.
3742 */
6737d9ad 3743 const uint64_t base_buid = 0x800000020000000ULL;
25e6a118
MT		 3744#define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \
3745 SPAPR_PCI_MEM64_WIN_SIZE - 1)
6737d9ad
DG		 3746 int i;
3747
357d1e3b
DG		 3748 /* Sanity check natural alignments */
3749 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0);
3750 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0);
3751 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0);
3752 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0);
3753 /* Sanity check bounds */
25e6a118
MT		 3754 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) >
3755 SPAPR_PCI_MEM32_WIN_SIZE);
3756 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) >
3757 SPAPR_PCI_MEM64_WIN_SIZE);
3758
3759 if (index >= SPAPR_MAX_PHBS) {
3760 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)",
3761 SPAPR_MAX_PHBS - 1);
6737d9ad
DG		 3762 return;
3763 }
3764
3765 *buid = base_buid + index;
3766 for (i = 0; i < n_dma; ++i) {
3767 liobns[i] = SPAPR_PCI_LIOBN(index, i);
3768 }
3769
357d1e3b
DG		 3770 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE;
3771 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE;
3772 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE;
6737d9ad
DG		 3773}
3774
7844e12b
CLG		 3775static ICSState *spapr_ics_get(XICSFabric *dev, int irq)
3776{
3777 sPAPRMachineState *spapr = SPAPR_MACHINE(dev);
3778
3779 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL;
3780}
3781
3782static void spapr_ics_resend(XICSFabric *dev)
3783{
3784 sPAPRMachineState *spapr = SPAPR_MACHINE(dev);
3785
3786 ics_resend(spapr->ics);
3787}
3788
81210c20 3789static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id)
b2fc59aa 3790{
2e886fb3 3791 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id);
b2fc59aa 3792
5bc8d26d 3793 return cpu ? ICP(cpu->intc) : NULL;
b2fc59aa
CLG		 3794}
3795
60c6823b
CLG		 3796#define ICS_IRQ_FREE(ics, srcno) \
3797 (!((ics)->irqs[(srcno)].flags & (XICS_FLAGS_IRQ_MASK)))
3798
3799static int ics_find_free_block(ICSState *ics, int num, int alignnum)
3800{
3801 int first, i;
3802
3803 for (first = 0; first < ics->nr_irqs; first += alignnum) {
3804 if (num > (ics->nr_irqs - first)) {
3805 return -1;
3806 }
3807 for (i = first; i < first + num; ++i) {
3808 if (!ICS_IRQ_FREE(ics, i)) {
3809 break;
3810 }
3811 }
3812 if (i == (first + num)) {
3813 return first;
3814 }
3815 }
3816
3817 return -1;
3818}
3819
4fe75a8c
CLG		 3820int spapr_irq_find(sPAPRMachineState *spapr, int num, bool align, Error **errp)
3821{
3822 ICSState *ics = spapr->ics;
3823 int first = -1;
3824
3825 assert(ics);
3826
3827 /*
3828 * MSIMesage::data is used for storing VIRQ so
3829 * it has to be aligned to num to support multiple
3830 * MSI vectors. MSI-X is not affected by this.
3831 * The hint is used for the first IRQ, the rest should
3832 * be allocated continuously.
3833 */
3834 if (align) {
3835 assert((num == 1) || (num == 2) || (num == 4) ||
3836 (num == 8) || (num == 16) || (num == 32));
3837 first = ics_find_free_block(ics, num, num);
3838 } else {
3839 first = ics_find_free_block(ics, num, 1);
3840 }
3841
3842 if (first < 0) {
3843 error_setg(errp, "can't find a free %d-IRQ block", num);
3844 return -1;
3845 }
3846
3847 return first + ics->offset;
3848}
3849
4fe75a8c
CLG		 3850int spapr_irq_claim(sPAPRMachineState *spapr, int irq, bool lsi, Error **errp)
3851{
3852 ICSState *ics = spapr->ics;
3853
3854 assert(ics);
3855
3856 if (!ics_valid_irq(ics, irq)) {
3857 error_setg(errp, "IRQ %d is invalid", irq);
3858 return -1;
3859 }
3860
3861 if (!ICS_IRQ_FREE(ics, irq - ics->offset)) {
3862 error_setg(errp, "IRQ %d is not free", irq);
3863 return -1;
3864 }
3865
71b5c8d2 3866 ics_set_irq_type(ics, irq - ics->offset, lsi);
4fe75a8c
CLG		 3867 return 0;
3868}
3869
60c6823b
CLG		 3870void spapr_irq_free(sPAPRMachineState *spapr, int irq, int num)
3871{
3872 ICSState *ics = spapr->ics;
3873 int srcno = irq - ics->offset;
3874 int i;
3875
3876 if (ics_valid_irq(ics, irq)) {
3877 trace_spapr_irq_free(0, irq, num);
3878 for (i = srcno; i < srcno + num; ++i) {
3879 if (ICS_IRQ_FREE(ics, i)) {
3880 trace_spapr_irq_free_warn(0, i + ics->offset);
3881 }
3882 memset(&ics->irqs[i], 0, sizeof(ICSIRQState));
3883 }
3884 }
3885}
3886
77183755
CLG		 3887qemu_irq spapr_qirq(sPAPRMachineState *spapr, int irq)
3888{
3889 ICSState *ics = spapr->ics;
3890
3891 if (ics_valid_irq(ics, irq)) {
3892 return ics->qirqs[irq - ics->offset];
3893 }
3894
3895 return NULL;
3896}
3897
6449da45
CLG		 3898static void spapr_pic_print_info(InterruptStatsProvider *obj,
3899 Monitor *mon)
3900{
3901 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
5bc8d26d
CLG		 3902 CPUState *cs;
3903
3904 CPU_FOREACH(cs) {
3905 PowerPCCPU *cpu = POWERPC_CPU(cs);
6449da45 3906
5bc8d26d 3907 icp_pic_print_info(ICP(cpu->intc), mon);
6449da45
CLG		 3908 }
3909
3910 ics_pic_print_info(spapr->ics, mon);
3911}
3912
14bb4486 3913int spapr_get_vcpu_id(PowerPCCPU *cpu)
2e886fb3 3914{
b1a568c1 3915 return cpu->vcpu_id;
2e886fb3
SB		 3916}
3917
648edb64
GK		 3918void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp)
3919{
3920 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
3921 int vcpu_id;
3922
5d0fb150 3923 vcpu_id = spapr_vcpu_id(spapr, cpu_index);
648edb64
GK		 3924
3925 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) {
3926 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id);
3927 error_append_hint(errp, "Adjust the number of cpus to %d "
3928 "or try to raise the number of threads per core\n",
3929 vcpu_id * smp_threads / spapr->vsmt);
3930 return;
3931 }
3932
3933 cpu->vcpu_id = vcpu_id;
3934}
3935
2e886fb3
SB		 3936PowerPCCPU *spapr_find_cpu(int vcpu_id)
3937{
3938 CPUState *cs;
3939
3940 CPU_FOREACH(cs) {
3941 PowerPCCPU *cpu = POWERPC_CPU(cs);
3942
14bb4486 3943 if (spapr_get_vcpu_id(cpu) == vcpu_id) {
2e886fb3
SB		 3944 return cpu;
3945 }
3946 }
3947
3948 return NULL;
3949}
3950
29ee3247
AK		 3951static void spapr_machine_class_init(ObjectClass *oc, void *data)
3952{
3953 MachineClass *mc = MACHINE_CLASS(oc);
224245bf 3954 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc);
71461b0f 3955 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
34316482 3956 NMIClass *nc = NMI_CLASS(oc);
c20d332a 3957 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
1d1be34d 3958 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc);
7844e12b 3959 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
6449da45 3960 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
958db90c 3961
0eb9054c 3962 mc->desc = "pSeries Logical Partition (PAPR compliant)";
fc9f38c3
DG		 3963
3964 /*
3965 * We set up the default / latest behaviour here. The class_init
3966 * functions for the specific versioned machine types can override
3967 * these details for backwards compatibility
3968 */
bcb5ce08
DG		 3969 mc->init = spapr_machine_init;
3970 mc->reset = spapr_machine_reset;
958db90c 3971 mc->block_default_type = IF_SCSI;
6244bb7e 3972 mc->max_cpus = 1024;
958db90c 3973 mc->no_parallel = 1;
5b2128d2 3974 mc->default_boot_order = "";
a34944fe 3975 mc->default_ram_size = 512 * M_BYTE;
958db90c 3976 mc->kvm_type = spapr_kvm_type;
7da79a16 3977 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE);
e4024630 3978 mc->pci_allow_0_address = true;
debbdc00 3979 assert(!mc->get_hotplug_handler);
7ebaf795 3980 mc->get_hotplug_handler = spapr_get_hotplug_handler;
94a94e4c 3981 hc->pre_plug = spapr_machine_device_pre_plug;
c20d332a 3982 hc->plug = spapr_machine_device_plug;
ea089eeb 3983 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props;
79e07936 3984 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id;
535455fd 3985 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids;
cf632463 3986 hc->unplug_request = spapr_machine_device_unplug_request;
88432f44 3987 hc->unplug = spapr_machine_device_unplug;
00b4fbe2 3988
fc9f38c3 3989 smc->dr_lmb_enabled = true;
2e9c10eb 3990 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0");
c5514d0e 3991 mc->has_hotpluggable_cpus = true;
52b81ab5 3992 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED;
71461b0f 3993 fwc->get_dev_path = spapr_get_fw_dev_path;
34316482 3994 nc->nmi_monitor_handler = spapr_nmi;
6737d9ad 3995 smc->phb_placement = spapr_phb_placement;
1d1be34d 3996 vhc->hypercall = emulate_spapr_hypercall;
e57ca75c
DG		 3997 vhc->hpt_mask = spapr_hpt_mask;
3998 vhc->map_hptes = spapr_map_hptes;
3999 vhc->unmap_hptes = spapr_unmap_hptes;
4000 vhc->store_hpte = spapr_store_hpte;
9861bb3e 4001 vhc->get_patbe = spapr_get_patbe;
1ec26c75 4002 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr;
7844e12b
CLG		 4003 xic->ics_get = spapr_ics_get;
4004 xic->ics_resend = spapr_ics_resend;
b2fc59aa 4005 xic->icp_get = spapr_icp_get;
6449da45 4006 ispc->print_info = spapr_pic_print_info;
55641213
LV		 4007 /* Force NUMA node memory size to be a multiple of
4008 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity
4009 * in which LMBs are represented and hot-added
4010 */
4011 mc->numa_mem_align_shift = 28;
33face6b 4012
4e5fe368
SJS		 4013 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF;
4014 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON;
4015 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON;
8f38eaf8 4016 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN;
09114fd8 4017 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN;
4be8d4e7 4018 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN;
2309832a 4019 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */
33face6b 4020 spapr_caps_add_properties(smc, &error_abort);
29ee3247
AK		 4021}
4022
4023static const TypeInfo spapr_machine_info = {
4024 .name = TYPE_SPAPR_MACHINE,
4025 .parent = TYPE_MACHINE,
4aee7362 4026 .abstract = true,
6ca1502e 4027 .instance_size = sizeof(sPAPRMachineState),
bcb5ce08 4028 .instance_init = spapr_instance_init,
87bbdd9c 4029 .instance_finalize = spapr_machine_finalizefn,
183930c0 4030 .class_size = sizeof(sPAPRMachineClass),
29ee3247 4031 .class_init = spapr_machine_class_init,
71461b0f
AK		 4032 .interfaces = (InterfaceInfo[]) {
4033 { TYPE_FW_PATH_PROVIDER },
34316482 4034 { TYPE_NMI },
c20d332a 4035 { TYPE_HOTPLUG_HANDLER },
1d1be34d 4036 { TYPE_PPC_VIRTUAL_HYPERVISOR },
7844e12b 4037 { TYPE_XICS_FABRIC },
6449da45 4038 { TYPE_INTERRUPT_STATS_PROVIDER },
71461b0f
AK		 4039 { }
4040 },
29ee3247
AK		 4041};
4042
fccbc785 4043#define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \
5013c547
DG		 4044 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \
4045 void *data) \
4046 { \
4047 MachineClass *mc = MACHINE_CLASS(oc); \
4048 spapr_machine_##suffix##_class_options(mc); \
fccbc785
DG		 4049 if (latest) { \
4050 mc->alias = "pseries"; \
4051 mc->is_default = 1; \
4052 } \
5013c547
DG		 4053 } \
4054 static void spapr_machine_##suffix##_instance_init(Object *obj) \
4055 { \
4056 MachineState *machine = MACHINE(obj); \
4057 spapr_machine_##suffix##_instance_options(machine); \
4058 } \
4059 static const TypeInfo spapr_machine_##suffix##_info = { \
4060 .name = MACHINE_TYPE_NAME("pseries-" verstr), \
4061 .parent = TYPE_SPAPR_MACHINE, \
4062 .class_init = spapr_machine_##suffix##_class_init, \
4063 .instance_init = spapr_machine_##suffix##_instance_init, \
4064 }; \
4065 static void spapr_machine_register_##suffix(void) \
4066 { \
4067 type_register(&spapr_machine_##suffix##_info); \
4068 } \
0e6aac87 4069 type_init(spapr_machine_register_##suffix)
5013c547 4070
8a4fd427 4071/*
d8c0c7af 4072 * pseries-3.0
8a4fd427 4073 */
d8c0c7af 4074static void spapr_machine_3_0_instance_options(MachineState *machine)
8a4fd427
DG		 4075{
4076}
4077
d8c0c7af 4078static void spapr_machine_3_0_class_options(MachineClass *mc)
8a4fd427
DG		 4079{
4080 /* Defaults for the latest behaviour inherited from the base class */
4081}
4082
d8c0c7af 4083DEFINE_SPAPR_MACHINE(3_0, "3.0", true);
8a4fd427 4084
2b615412
DG		 4085/*
4086 * pseries-2.12
4087 */
8a4fd427 4088#define SPAPR_COMPAT_2_12 \
67d7d66f
DG		 4089 HW_COMPAT_2_12 \
4090 { \
4091 .driver = TYPE_POWERPC_CPU, \
b9402026
GK		 4092 .property = "pre-3.0-migration", \
4093 .value = "on", \
4094 }, \
4095 { \
4096 .driver = TYPE_SPAPR_CPU_CORE, \
4097 .property = "pre-3.0-migration", \
67d7d66f
DG		 4098 .value = "on", \
4099 },
8a4fd427 4100
2b615412
DG		 4101static void spapr_machine_2_12_instance_options(MachineState *machine)
4102{
d8c0c7af 4103 spapr_machine_3_0_instance_options(machine);
2b615412
DG		 4104}
4105
4106static void spapr_machine_2_12_class_options(MachineClass *mc)
4107{
2309832a
DG		 4108 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4109 uint8_t mps;
4110
d8c0c7af 4111 spapr_machine_3_0_class_options(mc);
8a4fd427 4112 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_12);
2309832a
DG		 4113
4114 if (kvmppc_hpt_needs_host_contiguous_pages()) {
4115 mps = ctz64(qemu_getrampagesize());
4116 } else {
4117 mps = 34; /* allow everything up to 16GiB, i.e. everything */
4118 }
4119 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = mps;
2b615412
DG		 4120}
4121
8a4fd427 4122DEFINE_SPAPR_MACHINE(2_12, "2.12", false);
2b615412 4123
813f3cf6
SJS		 4124static void spapr_machine_2_12_sxxm_instance_options(MachineState *machine)
4125{
4126 spapr_machine_2_12_instance_options(machine);
4127}
4128
4129static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc)
4130{
4131 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4132
4133 spapr_machine_2_12_class_options(mc);
4134 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND;
4135 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND;
4136 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD;
4137}
4138
4139DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false);
4140
e2676b16
GK		 4141/*
4142 * pseries-2.11
4143 */
2b615412
DG		 4144#define SPAPR_COMPAT_2_11 \
4145 HW_COMPAT_2_11
4146
e2676b16
GK		 4147static void spapr_machine_2_11_instance_options(MachineState *machine)
4148{
2b615412 4149 spapr_machine_2_12_instance_options(machine);
e2676b16
GK		 4150}
4151
4152static void spapr_machine_2_11_class_options(MachineClass *mc)
4153{
ee76a09f
DG		 4154 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4155
2b615412 4156 spapr_machine_2_12_class_options(mc);
4e5fe368 4157 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON;
2b615412 4158 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_11);
e2676b16
GK		 4159}
4160
2b615412 4161DEFINE_SPAPR_MACHINE(2_11, "2.11", false);
e2676b16 4162
3fa14fbe
DG		 4163/*
4164 * pseries-2.10
4165 */
e2676b16 4166#define SPAPR_COMPAT_2_10 \
2b615412 4167 HW_COMPAT_2_10
e2676b16 4168
3fa14fbe
DG		 4169static void spapr_machine_2_10_instance_options(MachineState *machine)
4170{
2b615412 4171 spapr_machine_2_11_instance_options(machine);
3fa14fbe
DG		 4172}
4173
4174static void spapr_machine_2_10_class_options(MachineClass *mc)
4175{
e2676b16
GK		 4176 spapr_machine_2_11_class_options(mc);
4177 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_10);
3fa14fbe
DG		 4178}
4179
e2676b16 4180DEFINE_SPAPR_MACHINE(2_10, "2.10", false);
3fa14fbe 4181
fa325e6c
DG		 4182/*
4183 * pseries-2.9
4184 */
3fa14fbe 4185#define SPAPR_COMPAT_2_9 \
d5fc133e
DG		 4186 HW_COMPAT_2_9 \
4187 { \
4188 .driver = TYPE_POWERPC_CPU, \
4189 .property = "pre-2.10-migration", \
4190 .value = "on", \
4191 }, \
3fa14fbe 4192
fa325e6c
DG		 4193static void spapr_machine_2_9_instance_options(MachineState *machine)
4194{
3fa14fbe 4195 spapr_machine_2_10_instance_options(machine);
fa325e6c
DG		 4196}
4197
4198static void spapr_machine_2_9_class_options(MachineClass *mc)
4199{
46f7afa3
GK		 4200 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4201
3fa14fbe
DG		 4202 spapr_machine_2_10_class_options(mc);
4203 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_9);
3bfe5716 4204 mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram;
46f7afa3 4205 smc->pre_2_10_has_unused_icps = true;
52b81ab5 4206 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED;
fa325e6c
DG		 4207}
4208
3fa14fbe 4209DEFINE_SPAPR_MACHINE(2_9, "2.9", false);
fa325e6c 4210
db800b21
DG		 4211/*
4212 * pseries-2.8
4213 */
82516263
DG		 4214#define SPAPR_COMPAT_2_8 \
4215 HW_COMPAT_2_8 \
4216 { \
4217 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
4218 .property = "pcie-extended-configuration-space", \
4219 .value = "off", \
4220 },
fa325e6c 4221
db800b21
DG		 4222static void spapr_machine_2_8_instance_options(MachineState *machine)
4223{
fa325e6c 4224 spapr_machine_2_9_instance_options(machine);
db800b21
DG		 4225}
4226
4227static void spapr_machine_2_8_class_options(MachineClass *mc)
4228{
fa325e6c
DG		 4229 spapr_machine_2_9_class_options(mc);
4230 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_8);
55641213 4231 mc->numa_mem_align_shift = 23;
db800b21
DG		 4232}
4233
fa325e6c 4234DEFINE_SPAPR_MACHINE(2_8, "2.8", false);
db800b21 4235
1ea1eefc
BR		 4236/*
4237 * pseries-2.7
4238 */
357d1e3b
DG		 4239#define SPAPR_COMPAT_2_7 \
4240 HW_COMPAT_2_7 \
4241 { \
4242 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
4243 .property = "mem_win_size", \
4244 .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\
4245 }, \
4246 { \
4247 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
4248 .property = "mem64_win_size", \
4249 .value = "0", \
146c11f1
DG		 4250 }, \
4251 { \
4252 .driver = TYPE_POWERPC_CPU, \
4253 .property = "pre-2.8-migration", \
4254 .value = "on", \
5c4537bd
DG		 4255 }, \
4256 { \
4257 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
4258 .property = "pre-2.8-migration", \
4259 .value = "on", \
357d1e3b
DG		 4260 },
4261
4262static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index,
4263 uint64_t *buid, hwaddr *pio,
4264 hwaddr *mmio32, hwaddr *mmio64,
4265 unsigned n_dma, uint32_t *liobns, Error **errp)
4266{
4267 /* Legacy PHB placement for pseries-2.7 and earlier machine types */
4268 const uint64_t base_buid = 0x800000020000000ULL;
4269 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */
4270 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */
4271 const hwaddr pio_offset = 0x80000000; /* 2 GiB */
4272 const uint32_t max_index = 255;
4273 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */
4274
4275 uint64_t ram_top = MACHINE(spapr)->ram_size;
4276 hwaddr phb0_base, phb_base;
4277 int i;
4278
0c9269a5 4279 /* Do we have device memory? */
357d1e3b
DG		 4280 if (MACHINE(spapr)->maxram_size > ram_top) {
4281 /* Can't just use maxram_size, because there may be an
0c9269a5
DH		 4282 * alignment gap between normal and device memory regions
4283 */
b0c14ec4
DH		 4284 ram_top = MACHINE(spapr)->device_memory->base +
4285 memory_region_size(&MACHINE(spapr)->device_memory->mr);
357d1e3b
DG		 4286 }
4287
4288 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment);
4289
4290 if (index > max_index) {
4291 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)",
4292 max_index);
4293 return;
4294 }
4295
4296 *buid = base_buid + index;
4297 for (i = 0; i < n_dma; ++i) {
4298 liobns[i] = SPAPR_PCI_LIOBN(index, i);
4299 }
4300
4301 phb_base = phb0_base + index * phb_spacing;
4302 *pio = phb_base + pio_offset;
4303 *mmio32 = phb_base + mmio_offset;
4304 /*
4305 * We don't set the 64-bit MMIO window, relying on the PHB's
4306 * fallback behaviour of automatically splitting a large "32-bit"
4307 * window into contiguous 32-bit and 64-bit windows
4308 */
4309}
db800b21 4310
1ea1eefc
BR		 4311static void spapr_machine_2_7_instance_options(MachineState *machine)
4312{
f6229214
MR		 4313 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
4314
672de881 4315 spapr_machine_2_8_instance_options(machine);
f6229214 4316 spapr->use_hotplug_event_source = false;
1ea1eefc
BR		 4317}
4318
4319static void spapr_machine_2_7_class_options(MachineClass *mc)
4320{
3daa4a9f
TH		 4321 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4322
db800b21 4323 spapr_machine_2_8_class_options(mc);
2e9c10eb 4324 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3");
db800b21 4325 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7);
357d1e3b 4326 smc->phb_placement = phb_placement_2_7;
1ea1eefc
BR		 4327}
4328
db800b21 4329DEFINE_SPAPR_MACHINE(2_7, "2.7", false);
1ea1eefc 4330
4b23699c
DG		 4331/*
4332 * pseries-2.6
4333 */
1ea1eefc 4334#define SPAPR_COMPAT_2_6 \
ae4de14c
AK		 4335 HW_COMPAT_2_6 \
4336 { \
4337 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
4338 .property = "ddw",\
4339 .value = stringify(off),\
4340 },
1ea1eefc 4341
4b23699c
DG		 4342static void spapr_machine_2_6_instance_options(MachineState *machine)
4343{
672de881 4344 spapr_machine_2_7_instance_options(machine);
4b23699c
DG		 4345}
4346
4347static void spapr_machine_2_6_class_options(MachineClass *mc)
4348{
1ea1eefc 4349 spapr_machine_2_7_class_options(mc);
c5514d0e 4350 mc->has_hotpluggable_cpus = false;
1ea1eefc 4351 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6);
4b23699c
DG		 4352}
4353
1ea1eefc 4354DEFINE_SPAPR_MACHINE(2_6, "2.6", false);
4b23699c 4355
1c5f29bb
DG		 4356/*
4357 * pseries-2.5
4358 */
4b23699c 4359#define SPAPR_COMPAT_2_5 \
57c522f4
TH		 4360 HW_COMPAT_2_5 \
4361 { \
4362 .driver = "spapr-vlan", \
4363 .property = "use-rx-buffer-pools", \
4364 .value = "off", \
4365 },
4b23699c 4366
5013c547 4367static void spapr_machine_2_5_instance_options(MachineState *machine)
1c5f29bb 4368{
672de881 4369 spapr_machine_2_6_instance_options(machine);
5013c547
DG		 4370}
4371
4372static void spapr_machine_2_5_class_options(MachineClass *mc)
4373{
57040d45
TH		 4374 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4375
4b23699c 4376 spapr_machine_2_6_class_options(mc);
57040d45 4377 smc->use_ohci_by_default = true;
4b23699c 4378 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5);
1c5f29bb
DG		 4379}
4380
4b23699c 4381DEFINE_SPAPR_MACHINE(2_5, "2.5", false);
1c5f29bb
DG		 4382
4383/*
4384 * pseries-2.4
4385 */
80fd50f9
CH		 4386#define SPAPR_COMPAT_2_4 \
4387 HW_COMPAT_2_4
4388
5013c547 4389static void spapr_machine_2_4_instance_options(MachineState *machine)
1c5f29bb 4390{
5013c547
DG		 4391 spapr_machine_2_5_instance_options(machine);
4392}
1c5f29bb 4393
5013c547
DG		 4394static void spapr_machine_2_4_class_options(MachineClass *mc)
4395{
fc9f38c3
DG		 4396 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4397
4398 spapr_machine_2_5_class_options(mc);
fc9f38c3 4399 smc->dr_lmb_enabled = false;
f949b4e5 4400 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4);
1c5f29bb
DG		 4401}
4402
fccbc785 4403DEFINE_SPAPR_MACHINE(2_4, "2.4", false);
1c5f29bb
DG		 4404
4405/*
4406 * pseries-2.3
4407 */
38ff32c6 4408#define SPAPR_COMPAT_2_3 \
7619c7b0
MR		 4409 HW_COMPAT_2_3 \
4410 {\
4411 .driver = "spapr-pci-host-bridge",\
4412 .property = "dynamic-reconfiguration",\
4413 .value = "off",\
4414 },
38ff32c6 4415
5013c547 4416static void spapr_machine_2_3_instance_options(MachineState *machine)
d25228e7 4417{
5013c547 4418 spapr_machine_2_4_instance_options(machine);
d25228e7
JW		 4419}
4420
5013c547 4421static void spapr_machine_2_3_class_options(MachineClass *mc)
6026db45 4422{
fc9f38c3 4423 spapr_machine_2_4_class_options(mc);
f949b4e5 4424 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3);
6026db45 4425}
fccbc785 4426DEFINE_SPAPR_MACHINE(2_3, "2.3", false);
6026db45 4427
1c5f29bb
DG		 4428/*
4429 * pseries-2.2
4430 */
4431
4432#define SPAPR_COMPAT_2_2 \
1c5f29bb
DG		 4433 HW_COMPAT_2_2 \
4434 {\
4435 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
4436 .property = "mem_win_size",\
4437 .value = "0x20000000",\
4438 },
4439
5013c547 4440static void spapr_machine_2_2_instance_options(MachineState *machine)
1c5f29bb 4441{
5013c547 4442 spapr_machine_2_3_instance_options(machine);
cba0e779 4443 machine->suppress_vmdesc = true;
1c5f29bb
DG		 4444}
4445
5013c547 4446static void spapr_machine_2_2_class_options(MachineClass *mc)
4aee7362 4447{
fc9f38c3 4448 spapr_machine_2_3_class_options(mc);
f949b4e5 4449 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2);
4aee7362 4450}
fccbc785 4451DEFINE_SPAPR_MACHINE(2_2, "2.2", false);
4aee7362 4452
1c5f29bb
DG		 4453/*
4454 * pseries-2.1
4455 */
4456#define SPAPR_COMPAT_2_1 \
1c5f29bb 4457 HW_COMPAT_2_1
3dab0244 4458
5013c547 4459static void spapr_machine_2_1_instance_options(MachineState *machine)
1c5f29bb 4460{
5013c547 4461 spapr_machine_2_2_instance_options(machine);
1c5f29bb 4462}
d25228e7 4463
5013c547 4464static void spapr_machine_2_1_class_options(MachineClass *mc)
d25228e7 4465{
fc9f38c3 4466 spapr_machine_2_2_class_options(mc);
f949b4e5 4467 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1);
d25228e7 4468}
fccbc785 4469DEFINE_SPAPR_MACHINE(2_1, "2.1", false);
fb0fc8f6 4470
29ee3247 4471static void spapr_machine_register_types(void)
9fdf0c29 4472{
29ee3247 4473 type_register_static(&spapr_machine_info);
9fdf0c29
DG		 4474}
4475
29ee3247 4476type_init(spapr_machine_register_types)
Empty description
This page took 1.488709 seconds and 4 git commands to generate.