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spapr: Abstract CPU core device and type specific core devices
[qemu.git] / hw / ppc / spapr.c
CommitLineData
9fdf0c29
DG		 1/*
2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
3 *
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 *
26 */
0d75590d 27#include "qemu/osdep.h"
da34e65c 28#include "qapi/error.h"
9c17d615 29#include "sysemu/sysemu.h"
e35704ba 30#include "sysemu/numa.h"
83c9f4ca 31#include "hw/hw.h"
03dd024f 32#include "qemu/log.h"
71461b0f 33#include "hw/fw-path-provider.h"
9fdf0c29 34#include "elf.h"
1422e32d 35#include "net/net.h"
ad440b4a 36#include "sysemu/device_tree.h"
fa1d36df 37#include "sysemu/block-backend.h"
9c17d615
PB		 38#include "sysemu/cpus.h"
39#include "sysemu/kvm.h"
c20d332a 40#include "sysemu/device_tree.h"
e97c3636 41#include "kvm_ppc.h"
ff14e817 42#include "migration/migration.h"
4be21d56 43#include "mmu-hash64.h"
3794d548 44#include "qom/cpu.h"
9fdf0c29
DG		 45
46#include "hw/boards.h"
0d09e41a 47#include "hw/ppc/ppc.h"
9fdf0c29
DG		 48#include "hw/loader.h"
49
0d09e41a
PB		 50#include "hw/ppc/spapr.h"
51#include "hw/ppc/spapr_vio.h"
52#include "hw/pci-host/spapr.h"
53#include "hw/ppc/xics.h"
a2cb15b0 54#include "hw/pci/msi.h"
9fdf0c29 55
83c9f4ca 56#include "hw/pci/pci.h"
71461b0f
AK		 57#include "hw/scsi/scsi.h"
58#include "hw/virtio/virtio-scsi.h"
f61b4bed 59
022c62cb 60#include "exec/address-spaces.h"
35139a59 61#include "hw/usb.h"
1de7afc9 62#include "qemu/config-file.h"
135a129a 63#include "qemu/error-report.h"
2a6593cb 64#include "trace.h"
34316482 65#include "hw/nmi.h"
890c2b77 66
68a27b20 67#include "hw/compat.h"
f348b6d1 68#include "qemu/cutils.h"
68a27b20 69
9fdf0c29
DG		 70#include <libfdt.h>
71
4d8d5467
BH		 72/* SLOF memory layout:
73 *
74 * SLOF raw image loaded at 0, copies its romfs right below the flat
75 * device-tree, then position SLOF itself 31M below that
76 *
77 * So we set FW_OVERHEAD to 40MB which should account for all of that
78 * and more
79 *
80 * We load our kernel at 4M, leaving space for SLOF initial image
81 */
38b02bd8 82#define FDT_MAX_SIZE 0x100000
39ac8455 83#define RTAS_MAX_SIZE 0x10000
b7d1f77a 84#define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */
a9f8ad8f
DG		 85#define FW_MAX_SIZE 0x400000
86#define FW_FILE_NAME "slof.bin"
4d8d5467
BH		 87#define FW_OVERHEAD 0x2800000
88#define KERNEL_LOAD_ADDR FW_MAX_SIZE
a9f8ad8f 89
4d8d5467 90#define MIN_RMA_SLOF 128UL
9fdf0c29
DG		 91
92#define TIMEBASE_FREQ 512000000ULL
93
0c103f8e
DG		 94#define PHANDLE_XICP 0x00001111
95
7f763a5d
DG		 96#define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift))
97
c04d6cfa 98static XICSState *try_create_xics(const char *type, int nr_servers,
34f2af3d 99 int nr_irqs, Error **errp)
c04d6cfa 100{
34f2af3d 101 Error *err = NULL;
c04d6cfa
AL		 102 DeviceState *dev;
103
104 dev = qdev_create(NULL, type);
105 qdev_prop_set_uint32(dev, "nr_servers", nr_servers);
106 qdev_prop_set_uint32(dev, "nr_irqs", nr_irqs);
34f2af3d
MA		 107 object_property_set_bool(OBJECT(dev), true, "realized", &err);
108 if (err) {
109 error_propagate(errp, err);
110 object_unparent(OBJECT(dev));
c04d6cfa
AL		 111 return NULL;
112 }
5a3d7b23 113 return XICS_COMMON(dev);
c04d6cfa
AL		 114}
115
446f16a6 116static XICSState *xics_system_init(MachineState *machine,
1e49182d 117 int nr_servers, int nr_irqs, Error **errp)
c04d6cfa
AL		 118{
119 XICSState *icp = NULL;
120
11ad93f6 121 if (kvm_enabled()) {
34f2af3d
MA		 122 Error *err = NULL;
123
446f16a6 124 if (machine_kernel_irqchip_allowed(machine)) {
34f2af3d 125 icp = try_create_xics(TYPE_KVM_XICS, nr_servers, nr_irqs, &err);
11ad93f6 126 }
446f16a6 127 if (machine_kernel_irqchip_required(machine) && !icp) {
b83baa60
MA		 128 error_reportf_err(err,
129 "kernel_irqchip requested but unavailable: ");
130 } else {
131 error_free(err);
11ad93f6
DG		 132 }
133 }
134
135 if (!icp) {
1e49182d 136 icp = try_create_xics(TYPE_XICS, nr_servers, nr_irqs, errp);
c04d6cfa
AL		 137 }
138
139 return icp;
140}
141
833d4668
AK		 142static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
143 int smt_threads)
144{
145 int i, ret = 0;
146 uint32_t servers_prop[smt_threads];
147 uint32_t gservers_prop[smt_threads * 2];
148 int index = ppc_get_vcpu_dt_id(cpu);
149
6d9412ea 150 if (cpu->cpu_version) {
4bce526e 151 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->cpu_version);
6d9412ea
AK		 152 if (ret < 0) {
153 return ret;
154 }
155 }
156
833d4668
AK		 157 /* Build interrupt servers and gservers properties */
158 for (i = 0; i < smt_threads; i++) {
159 servers_prop[i] = cpu_to_be32(index + i);
160 /* Hack, direct the group queues back to cpu 0 */
161 gservers_prop[i*2] = cpu_to_be32(index + i);
162 gservers_prop[i*2 + 1] = 0;
163 }
164 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
165 servers_prop, sizeof(servers_prop));
166 if (ret < 0) {
167 return ret;
168 }
169 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s",
170 gservers_prop, sizeof(gservers_prop));
171
172 return ret;
173}
174
0da6f3fe
BR		 175static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, CPUState *cs)
176{
177 int ret = 0;
178 PowerPCCPU *cpu = POWERPC_CPU(cs);
179 int index = ppc_get_vcpu_dt_id(cpu);
180 uint32_t associativity[] = {cpu_to_be32(0x5),
181 cpu_to_be32(0x0),
182 cpu_to_be32(0x0),
183 cpu_to_be32(0x0),
184 cpu_to_be32(cs->numa_node),
185 cpu_to_be32(index)};
186
187 /* Advertise NUMA via ibm,associativity */
188 if (nb_numa_nodes > 1) {
189 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity,
190 sizeof(associativity));
191 }
192
193 return ret;
194}
195
28e02042 196static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr)
6e806cc3 197{
82677ed2
AK		 198 int ret = 0, offset, cpus_offset;
199 CPUState *cs;
6e806cc3
BR		 200 char cpu_model[32];
201 int smt = kvmppc_smt_threads();
7f763a5d 202 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
6e806cc3 203
82677ed2
AK		 204 CPU_FOREACH(cs) {
205 PowerPCCPU *cpu = POWERPC_CPU(cs);
206 DeviceClass *dc = DEVICE_GET_CLASS(cs);
207 int index = ppc_get_vcpu_dt_id(cpu);
6e806cc3 208
0f20ba62 209 if ((index % smt) != 0) {
6e806cc3
BR		 210 continue;
211 }
212
82677ed2 213 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index);
6e806cc3 214
82677ed2
AK		 215 cpus_offset = fdt_path_offset(fdt, "/cpus");
216 if (cpus_offset < 0) {
217 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"),
218 "cpus");
219 if (cpus_offset < 0) {
220 return cpus_offset;
221 }
222 }
223 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model);
6e806cc3 224 if (offset < 0) {
82677ed2
AK		 225 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model);
226 if (offset < 0) {
227 return offset;
228 }
6e806cc3
BR		 229 }
230
7f763a5d
DG		 231 ret = fdt_setprop(fdt, offset, "ibm,pft-size",
232 pft_size_prop, sizeof(pft_size_prop));
6e806cc3
BR		 233 if (ret < 0) {
234 return ret;
235 }
833d4668 236
0da6f3fe
BR		 237 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cs);
238 if (ret < 0) {
239 return ret;
240 }
241
82677ed2 242 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu,
2a48d993 243 ppc_get_compat_smt_threads(cpu));
833d4668
AK		 244 if (ret < 0) {
245 return ret;
246 }
6e806cc3
BR		 247 }
248 return ret;
249}
250
5af9873d
BH		 251
252static size_t create_page_sizes_prop(CPUPPCState *env, uint32_t *prop,
253 size_t maxsize)
254{
255 size_t maxcells = maxsize / sizeof(uint32_t);
256 int i, j, count;
257 uint32_t *p = prop;
258
259 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
260 struct ppc_one_seg_page_size *sps = &env->sps.sps[i];
261
262 if (!sps->page_shift) {
263 break;
264 }
265 for (count = 0; count < PPC_PAGE_SIZES_MAX_SZ; count++) {
266 if (sps->enc[count].page_shift == 0) {
267 break;
268 }
269 }
270 if ((p - prop) >= (maxcells - 3 - count * 2)) {
271 break;
272 }
273 *(p++) = cpu_to_be32(sps->page_shift);
274 *(p++) = cpu_to_be32(sps->slb_enc);
275 *(p++) = cpu_to_be32(count);
276 for (j = 0; j < count; j++) {
277 *(p++) = cpu_to_be32(sps->enc[j].page_shift);
278 *(p++) = cpu_to_be32(sps->enc[j].pte_enc);
279 }
280 }
281
282 return (p - prop) * sizeof(uint32_t);
283}
284
b082d65a
AK		 285static hwaddr spapr_node0_size(void)
286{
fb164994
DG		 287 MachineState *machine = MACHINE(qdev_get_machine());
288
b082d65a
AK		 289 if (nb_numa_nodes) {
290 int i;
291 for (i = 0; i < nb_numa_nodes; ++i) {
292 if (numa_info[i].node_mem) {
fb164994
DG		 293 return MIN(pow2floor(numa_info[i].node_mem),
294 machine->ram_size);
b082d65a
AK		 295 }
296 }
297 }
fb164994 298 return machine->ram_size;
b082d65a
AK		 299}
300
7f763a5d
DG		 301#define _FDT(exp) \
302 do { \
303 int ret = (exp); \
304 if (ret < 0) { \
305 fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \
306 #exp, fdt_strerror(ret)); \
307 exit(1); \
308 } \
309 } while (0)
310
a1d59c0f
AK		 311static void add_str(GString *s, const gchar *s1)
312{
313 g_string_append_len(s, s1, strlen(s1) + 1);
314}
7f763a5d 315
3bbf37f2 316static void *spapr_create_fdt_skel(hwaddr initrd_base,
a8170e5e
AK		 317 hwaddr initrd_size,
318 hwaddr kernel_size,
16457e7f 319 bool little_endian,
74d042e5
DG		 320 const char *kernel_cmdline,
321 uint32_t epow_irq)
9fdf0c29
DG		 322{
323 void *fdt;
9fdf0c29
DG		 324 uint32_t start_prop = cpu_to_be32(initrd_base);
325 uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size);
a1d59c0f
AK		 326 GString *hypertas = g_string_sized_new(256);
327 GString *qemu_hypertas = g_string_sized_new(256);
7f763a5d 328 uint32_t refpoints[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)};
9e734e3d 329 uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(max_cpus)};
6e806cc3 330 unsigned char vec5[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80};
ef951443 331 char *buf;
9fdf0c29 332
a1d59c0f
AK		 333 add_str(hypertas, "hcall-pft");
334 add_str(hypertas, "hcall-term");
335 add_str(hypertas, "hcall-dabr");
336 add_str(hypertas, "hcall-interrupt");
337 add_str(hypertas, "hcall-tce");
338 add_str(hypertas, "hcall-vio");
339 add_str(hypertas, "hcall-splpar");
340 add_str(hypertas, "hcall-bulk");
341 add_str(hypertas, "hcall-set-mode");
342 add_str(qemu_hypertas, "hcall-memop1");
343
7267c094 344 fdt = g_malloc0(FDT_MAX_SIZE);
9fdf0c29
DG		 345 _FDT((fdt_create(fdt, FDT_MAX_SIZE)));
346
4d8d5467
BH		 347 if (kernel_size) {
348 _FDT((fdt_add_reservemap_entry(fdt, KERNEL_LOAD_ADDR, kernel_size)));
349 }
350 if (initrd_size) {
351 _FDT((fdt_add_reservemap_entry(fdt, initrd_base, initrd_size)));
352 }
9fdf0c29
DG		 353 _FDT((fdt_finish_reservemap(fdt)));
354
355 /* Root node */
356 _FDT((fdt_begin_node(fdt, "")));
357 _FDT((fdt_property_string(fdt, "device_type", "chrp")));
5d73dd66 358 _FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)")));
d63919c9 359 _FDT((fdt_property_string(fdt, "compatible", "qemu,pseries")));
9fdf0c29 360
ef951443
ND		 361 /*
362 * Add info to guest to indentify which host is it being run on
363 * and what is the uuid of the guest
364 */
365 if (kvmppc_get_host_model(&buf)) {
366 _FDT((fdt_property_string(fdt, "host-model", buf)));
367 g_free(buf);
368 }
369 if (kvmppc_get_host_serial(&buf)) {
370 _FDT((fdt_property_string(fdt, "host-serial", buf)));
371 g_free(buf);
372 }
373
374 buf = g_strdup_printf(UUID_FMT, qemu_uuid[0], qemu_uuid[1],
375 qemu_uuid[2], qemu_uuid[3], qemu_uuid[4],
376 qemu_uuid[5], qemu_uuid[6], qemu_uuid[7],
377 qemu_uuid[8], qemu_uuid[9], qemu_uuid[10],
378 qemu_uuid[11], qemu_uuid[12], qemu_uuid[13],
379 qemu_uuid[14], qemu_uuid[15]);
380
381 _FDT((fdt_property_string(fdt, "vm,uuid", buf)));
3dc0a66d
AK		 382 if (qemu_uuid_set) {
383 _FDT((fdt_property_string(fdt, "system-id", buf)));
384 }
ef951443
ND		 385 g_free(buf);
386
2c1aaa81
SB		 387 if (qemu_get_vm_name()) {
388 _FDT((fdt_property_string(fdt, "ibm,partition-name",
389 qemu_get_vm_name())));
390 }
391
9fdf0c29
DG		 392 _FDT((fdt_property_cell(fdt, "#address-cells", 0x2)));
393 _FDT((fdt_property_cell(fdt, "#size-cells", 0x2)));
394
395 /* /chosen */
396 _FDT((fdt_begin_node(fdt, "chosen")));
397
6e806cc3
BR		 398 /* Set Form1_affinity */
399 _FDT((fdt_property(fdt, "ibm,architecture-vec-5", vec5, sizeof(vec5))));
400
9fdf0c29
DG		 401 _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline)));
402 _FDT((fdt_property(fdt, "linux,initrd-start",
403 &start_prop, sizeof(start_prop))));
404 _FDT((fdt_property(fdt, "linux,initrd-end",
405 &end_prop, sizeof(end_prop))));
4d8d5467
BH		 406 if (kernel_size) {
407 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR),
408 cpu_to_be64(kernel_size) };
9fdf0c29 409
4d8d5467 410 _FDT((fdt_property(fdt, "qemu,boot-kernel", &kprop, sizeof(kprop))));
16457e7f
BH		 411 if (little_endian) {
412 _FDT((fdt_property(fdt, "qemu,boot-kernel-le", NULL, 0)));
413 }
4d8d5467 414 }
cc84c0f3
AS		 415 if (boot_menu) {
416 _FDT((fdt_property_cell(fdt, "qemu,boot-menu", boot_menu)));
417 }
f28359d8
LZ		 418 _FDT((fdt_property_cell(fdt, "qemu,graphic-width", graphic_width)));
419 _FDT((fdt_property_cell(fdt, "qemu,graphic-height", graphic_height)));
420 _FDT((fdt_property_cell(fdt, "qemu,graphic-depth", graphic_depth)));
3384f95c 421
9fdf0c29
DG		 422 _FDT((fdt_end_node(fdt)));
423
f43e3525
DG		 424 /* RTAS */
425 _FDT((fdt_begin_node(fdt, "rtas")));
426
da95324e
AK		 427 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
428 add_str(hypertas, "hcall-multi-tce");
429 }
a1d59c0f
AK		 430 _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas->str,
431 hypertas->len)));
432 g_string_free(hypertas, TRUE);
433 _FDT((fdt_property(fdt, "qemu,hypertas-functions", qemu_hypertas->str,
434 qemu_hypertas->len)));
435 g_string_free(qemu_hypertas, TRUE);
f43e3525 436
6e806cc3
BR		 437 _FDT((fdt_property(fdt, "ibm,associativity-reference-points",
438 refpoints, sizeof(refpoints))));
439
74d042e5 440 _FDT((fdt_property_cell(fdt, "rtas-error-log-max", RTAS_ERROR_LOG_MAX)));
79853e18
TD		 441 _FDT((fdt_property_cell(fdt, "rtas-event-scan-rate",
442 RTAS_EVENT_SCAN_RATE)));
74d042e5 443
226419d6 444 if (msi_nonbroken) {
a95f9922
SB		 445 _FDT((fdt_property(fdt, "ibm,change-msix-capable", NULL, 0)));
446 }
447
2e14072f 448 /*
9d632f5f 449 * According to PAPR, rtas ibm,os-term does not guarantee a return
2e14072f
ND		 450 * back to the guest cpu.
451 *
452 * While an additional ibm,extended-os-term property indicates that
453 * rtas call return will always occur. Set this property.
454 */
455 _FDT((fdt_property(fdt, "ibm,extended-os-term", NULL, 0)));
456
f43e3525
DG		 457 _FDT((fdt_end_node(fdt)));
458
b5cec4c5 459 /* interrupt controller */
9dfef5aa 460 _FDT((fdt_begin_node(fdt, "interrupt-controller")));
b5cec4c5
DG		 461
462 _FDT((fdt_property_string(fdt, "device_type",
463 "PowerPC-External-Interrupt-Presentation")));
464 _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp")));
b5cec4c5
DG		 465 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));
466 _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges",
467 interrupt_server_ranges_prop,
468 sizeof(interrupt_server_ranges_prop))));
0c103f8e
DG		 469 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 2)));
470 _FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP)));
471 _FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP)));
b5cec4c5
DG		 472
473 _FDT((fdt_end_node(fdt)));
474
4040ab72
DG		 475 /* vdevice */
476 _FDT((fdt_begin_node(fdt, "vdevice")));
477
478 _FDT((fdt_property_string(fdt, "device_type", "vdevice")));
479 _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice")));
480 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1)));
481 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0)));
b5cec4c5
DG		 482 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2)));
483 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));
4040ab72
DG		 484
485 _FDT((fdt_end_node(fdt)));
486
74d042e5
DG		 487 /* event-sources */
488 spapr_events_fdt_skel(fdt, epow_irq);
489
f7d69146
AG		 490 /* /hypervisor node */
491 if (kvm_enabled()) {
492 uint8_t hypercall[16];
493
494 /* indicate KVM hypercall interface */
495 _FDT((fdt_begin_node(fdt, "hypervisor")));
496 _FDT((fdt_property_string(fdt, "compatible", "linux,kvm")));
497 if (kvmppc_has_cap_fixup_hcalls()) {
498 /*
499 * Older KVM versions with older guest kernels were broken with the
500 * magic page, don't allow the guest to map it.
501 */
0ddbd053
AK		 502 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall,
503 sizeof(hypercall))) {
504 _FDT((fdt_property(fdt, "hcall-instructions", hypercall,
505 sizeof(hypercall))));
506 }
f7d69146
AG		 507 }
508 _FDT((fdt_end_node(fdt)));
509 }
510
9fdf0c29
DG		 511 _FDT((fdt_end_node(fdt))); /* close root node */
512 _FDT((fdt_finish(fdt)));
513
a3467baa
DG		 514 return fdt;
515}
516
03d196b7 517static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start,
26a8c353
AK		 518 hwaddr size)
519{
520 uint32_t associativity[] = {
521 cpu_to_be32(0x4), /* length */
522 cpu_to_be32(0x0), cpu_to_be32(0x0),
c3b4f589 523 cpu_to_be32(0x0), cpu_to_be32(nodeid)
26a8c353
AK		 524 };
525 char mem_name[32];
526 uint64_t mem_reg_property[2];
527 int off;
528
529 mem_reg_property[0] = cpu_to_be64(start);
530 mem_reg_property[1] = cpu_to_be64(size);
531
532 sprintf(mem_name, "memory@" TARGET_FMT_lx, start);
533 off = fdt_add_subnode(fdt, 0, mem_name);
534 _FDT(off);
535 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
536 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
537 sizeof(mem_reg_property))));
538 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,
539 sizeof(associativity))));
03d196b7 540 return off;
26a8c353
AK		 541}
542
28e02042 543static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt)
7f763a5d 544{
fb164994 545 MachineState *machine = MACHINE(spapr);
7db8a127
AK		 546 hwaddr mem_start, node_size;
547 int i, nb_nodes = nb_numa_nodes;
548 NodeInfo *nodes = numa_info;
549 NodeInfo ramnode;
550
551 /* No NUMA nodes, assume there is just one node with whole RAM */
552 if (!nb_numa_nodes) {
553 nb_nodes = 1;
fb164994 554 ramnode.node_mem = machine->ram_size;
7db8a127 555 nodes = &ramnode;
5fe269b1 556 }
7f763a5d 557
7db8a127
AK		 558 for (i = 0, mem_start = 0; i < nb_nodes; ++i) {
559 if (!nodes[i].node_mem) {
560 continue;
561 }
fb164994 562 if (mem_start >= machine->ram_size) {
5fe269b1
PM		 563 node_size = 0;
564 } else {
7db8a127 565 node_size = nodes[i].node_mem;
fb164994
DG		 566 if (node_size > machine->ram_size - mem_start) {
567 node_size = machine->ram_size - mem_start;
5fe269b1
PM		 568 }
569 }
7db8a127
AK		 570 if (!mem_start) {
571 /* ppc_spapr_init() checks for rma_size <= node0_size already */
e8f986fc 572 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size);
7db8a127
AK		 573 mem_start += spapr->rma_size;
574 node_size -= spapr->rma_size;
575 }
6010818c
AK		 576 for ( ; node_size; ) {
577 hwaddr sizetmp = pow2floor(node_size);
578
579 /* mem_start != 0 here */
580 if (ctzl(mem_start) < ctzl(sizetmp)) {
581 sizetmp = 1ULL << ctzl(mem_start);
582 }
583
584 spapr_populate_memory_node(fdt, i, mem_start, sizetmp);
585 node_size -= sizetmp;
586 mem_start += sizetmp;
587 }
7f763a5d
DG		 588 }
589
590 return 0;
591}
592
0da6f3fe
BR		 593static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
594 sPAPRMachineState *spapr)
595{
596 PowerPCCPU *cpu = POWERPC_CPU(cs);
597 CPUPPCState *env = &cpu->env;
598 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
599 int index = ppc_get_vcpu_dt_id(cpu);
600 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
601 0xffffffff, 0xffffffff};
602 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ;
603 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
604 uint32_t page_sizes_prop[64];
605 size_t page_sizes_prop_size;
22419c2a 606 uint32_t vcpus_per_socket = smp_threads * smp_cores;
0da6f3fe
BR		 607 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
608
90da0d5a
BH		 609 /* Note: we keep CI large pages off for now because a 64K capable guest
610 * provisioned with large pages might otherwise try to map a qemu
611 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages
612 * even if that qemu runs on a 4k host.
613 *
614 * We can later add this bit back when we are confident this is not
615 * an issue (!HV KVM or 64K host)
616 */
617 uint8_t pa_features_206[] = { 6, 0,
618 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
619 uint8_t pa_features_207[] = { 24, 0,
620 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
621 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
622 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
623 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
624 uint8_t *pa_features;
625 size_t pa_size;
626
0da6f3fe
BR		 627 _FDT((fdt_setprop_cell(fdt, offset, "reg", index)));
628 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
629
630 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
631 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
632 env->dcache_line_size)));
633 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
634 env->dcache_line_size)));
635 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
636 env->icache_line_size)));
637 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
638 env->icache_line_size)));
639
640 if (pcc->l1_dcache_size) {
641 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
642 pcc->l1_dcache_size)));
643 } else {
644 fprintf(stderr, "Warning: Unknown L1 dcache size for cpu\n");
645 }
646 if (pcc->l1_icache_size) {
647 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
648 pcc->l1_icache_size)));
649 } else {
650 fprintf(stderr, "Warning: Unknown L1 icache size for cpu\n");
651 }
652
653 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
654 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
fd5da5c4 655 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr)));
0da6f3fe
BR		 656 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr)));
657 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
658 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
659
660 if (env->spr_cb[SPR_PURR].oea_read) {
661 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
662 }
663
664 if (env->mmu_model & POWERPC_MMU_1TSEG) {
665 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
666 segs, sizeof(segs))));
667 }
668
669 /* Advertise VMX/VSX (vector extensions) if available
670 * 0 / no property == no vector extensions
671 * 1 == VMX / Altivec available
672 * 2 == VSX available */
673 if (env->insns_flags & PPC_ALTIVEC) {
674 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
675
676 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
677 }
678
679 /* Advertise DFP (Decimal Floating Point) if available
680 * 0 / no property == no DFP
681 * 1 == DFP available */
682 if (env->insns_flags2 & PPC2_DFP) {
683 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
684 }
685
686 page_sizes_prop_size = create_page_sizes_prop(env, page_sizes_prop,
687 sizeof(page_sizes_prop));
688 if (page_sizes_prop_size) {
689 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
690 page_sizes_prop, page_sizes_prop_size)));
691 }
692
90da0d5a
BH		 693 /* Do the ibm,pa-features property, adjust it for ci-large-pages */
694 if (env->mmu_model == POWERPC_MMU_2_06) {
695 pa_features = pa_features_206;
696 pa_size = sizeof(pa_features_206);
697 } else /* env->mmu_model == POWERPC_MMU_2_07 */ {
698 pa_features = pa_features_207;
699 pa_size = sizeof(pa_features_207);
700 }
701 if (env->ci_large_pages) {
702 pa_features[3] |= 0x20;
703 }
704 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size)));
705
0da6f3fe 706 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id",
22419c2a 707 cs->cpu_index / vcpus_per_socket)));
0da6f3fe
BR		 708
709 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size",
710 pft_size_prop, sizeof(pft_size_prop))));
711
712 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cs));
713
714 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu,
715 ppc_get_compat_smt_threads(cpu)));
716}
717
718static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr)
719{
720 CPUState *cs;
721 int cpus_offset;
722 char *nodename;
723 int smt = kvmppc_smt_threads();
724
725 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
726 _FDT(cpus_offset);
727 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
728 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
729
730 /*
731 * We walk the CPUs in reverse order to ensure that CPU DT nodes
732 * created by fdt_add_subnode() end up in the right order in FDT
733 * for the guest kernel the enumerate the CPUs correctly.
734 */
735 CPU_FOREACH_REVERSE(cs) {
736 PowerPCCPU *cpu = POWERPC_CPU(cs);
737 int index = ppc_get_vcpu_dt_id(cpu);
738 DeviceClass *dc = DEVICE_GET_CLASS(cs);
739 int offset;
740
741 if ((index % smt) != 0) {
742 continue;
743 }
744
745 nodename = g_strdup_printf("%s@%x", dc->fw_name, index);
746 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
747 g_free(nodename);
748 _FDT(offset);
749 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
750 }
751
752}
753
03d196b7
BR		 754/*
755 * Adds ibm,dynamic-reconfiguration-memory node.
756 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation
757 * of this device tree node.
758 */
759static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt)
760{
761 MachineState *machine = MACHINE(spapr);
762 int ret, i, offset;
763 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
764 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)};
d0e5a8f2
BR		 765 uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size;
766 uint32_t nr_lmbs = (spapr->hotplug_memory.base +
767 memory_region_size(&spapr->hotplug_memory.mr)) /
768 lmb_size;
03d196b7 769 uint32_t *int_buf, *cur_index, buf_len;
6663864e 770 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1;
03d196b7 771
16c25aef 772 /*
d0e5a8f2 773 * Don't create the node if there is no hotpluggable memory
16c25aef 774 */
d0e5a8f2 775 if (machine->ram_size == machine->maxram_size) {
16c25aef
BR		 776 return 0;
777 }
778
ef001f06
TH		 779 /*
780 * Allocate enough buffer size to fit in ibm,dynamic-memory
781 * or ibm,associativity-lookup-arrays
782 */
783 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2)
784 * sizeof(uint32_t);
03d196b7
BR		 785 cur_index = int_buf = g_malloc0(buf_len);
786
787 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory");
788
789 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size,
790 sizeof(prop_lmb_size));
791 if (ret < 0) {
792 goto out;
793 }
794
795 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff);
796 if (ret < 0) {
797 goto out;
798 }
799
800 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0);
801 if (ret < 0) {
802 goto out;
803 }
804
805 /* ibm,dynamic-memory */
806 int_buf[0] = cpu_to_be32(nr_lmbs);
807 cur_index++;
808 for (i = 0; i < nr_lmbs; i++) {
d0e5a8f2 809 uint64_t addr = i * lmb_size;
03d196b7
BR		 810 uint32_t *dynamic_memory = cur_index;
811
d0e5a8f2
BR		 812 if (i >= hotplug_lmb_start) {
813 sPAPRDRConnector *drc;
814 sPAPRDRConnectorClass *drck;
815
816 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, i);
817 g_assert(drc);
818 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
819
820 dynamic_memory[0] = cpu_to_be32(addr >> 32);
821 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
822 dynamic_memory[2] = cpu_to_be32(drck->get_index(drc));
823 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
824 dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL));
825 if (memory_region_present(get_system_memory(), addr)) {
826 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED);
827 } else {
828 dynamic_memory[5] = cpu_to_be32(0);
829 }
03d196b7 830 } else {
d0e5a8f2
BR		 831 /*
832 * LMB information for RMA, boot time RAM and gap b/n RAM and
833 * hotplug memory region -- all these are marked as reserved
834 * and as having no valid DRC.
835 */
836 dynamic_memory[0] = cpu_to_be32(addr >> 32);
837 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
838 dynamic_memory[2] = cpu_to_be32(0);
839 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
840 dynamic_memory[4] = cpu_to_be32(-1);
841 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED |
842 SPAPR_LMB_FLAGS_DRC_INVALID);
03d196b7
BR		 843 }
844
845 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE;
846 }
847 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len);
848 if (ret < 0) {
849 goto out;
850 }
851
852 /* ibm,associativity-lookup-arrays */
853 cur_index = int_buf;
6663864e 854 int_buf[0] = cpu_to_be32(nr_nodes);
03d196b7
BR		 855 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */
856 cur_index += 2;
6663864e 857 for (i = 0; i < nr_nodes; i++) {
03d196b7
BR		 858 uint32_t associativity[] = {
859 cpu_to_be32(0x0),
860 cpu_to_be32(0x0),
861 cpu_to_be32(0x0),
862 cpu_to_be32(i)
863 };
864 memcpy(cur_index, associativity, sizeof(associativity));
865 cur_index += 4;
866 }
867 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf,
868 (cur_index - int_buf) * sizeof(uint32_t));
869out:
870 g_free(int_buf);
871 return ret;
872}
873
874int spapr_h_cas_compose_response(sPAPRMachineState *spapr,
875 target_ulong addr, target_ulong size,
876 bool cpu_update, bool memory_update)
877{
878 void *fdt, *fdt_skel;
879 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 };
880 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine());
881
882 size -= sizeof(hdr);
883
884 /* Create sceleton */
885 fdt_skel = g_malloc0(size);
886 _FDT((fdt_create(fdt_skel, size)));
887 _FDT((fdt_begin_node(fdt_skel, "")));
888 _FDT((fdt_end_node(fdt_skel)));
889 _FDT((fdt_finish(fdt_skel)));
890 fdt = g_malloc0(size);
891 _FDT((fdt_open_into(fdt_skel, fdt, size)));
892 g_free(fdt_skel);
893
894 /* Fixup cpu nodes */
895 if (cpu_update) {
896 _FDT((spapr_fixup_cpu_dt(fdt, spapr)));
897 }
898
16c25aef 899 /* Generate ibm,dynamic-reconfiguration-memory node if required */
03d196b7
BR		 900 if (memory_update && smc->dr_lmb_enabled) {
901 _FDT((spapr_populate_drconf_memory(spapr, fdt)));
03d196b7
BR		 902 }
903
904 /* Pack resulting tree */
905 _FDT((fdt_pack(fdt)));
906
907 if (fdt_totalsize(fdt) + sizeof(hdr) > size) {
908 trace_spapr_cas_failed(size);
909 return -1;
910 }
911
912 cpu_physical_memory_write(addr, &hdr, sizeof(hdr));
913 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt));
914 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr));
915 g_free(fdt);
916
917 return 0;
918}
919
28e02042 920static void spapr_finalize_fdt(sPAPRMachineState *spapr,
a8170e5e
AK		 921 hwaddr fdt_addr,
922 hwaddr rtas_addr,
923 hwaddr rtas_size)
a3467baa 924{
5b2128d2 925 MachineState *machine = MACHINE(qdev_get_machine());
c20d332a 926 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
5b2128d2 927 const char *boot_device = machine->boot_order;
71461b0f
AK		 928 int ret, i;
929 size_t cb = 0;
930 char *bootlist;
a3467baa 931 void *fdt;
3384f95c 932 sPAPRPHBState *phb;
a3467baa 933
7267c094 934 fdt = g_malloc(FDT_MAX_SIZE);
a3467baa
DG		 935
936 /* open out the base tree into a temp buffer for the final tweaks */
937 _FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE)));
4040ab72 938
e8f986fc
BR		 939 ret = spapr_populate_memory(spapr, fdt);
940 if (ret < 0) {
941 fprintf(stderr, "couldn't setup memory nodes in fdt\n");
942 exit(1);
7f763a5d
DG		 943 }
944
4040ab72
DG		 945 ret = spapr_populate_vdevice(spapr->vio_bus, fdt);
946 if (ret < 0) {
947 fprintf(stderr, "couldn't setup vio devices in fdt\n");
948 exit(1);
949 }
950
4d9392be
TH		 951 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) {
952 ret = spapr_rng_populate_dt(fdt);
953 if (ret < 0) {
954 fprintf(stderr, "could not set up rng device in the fdt\n");
955 exit(1);
956 }
957 }
958
3384f95c 959 QLIST_FOREACH(phb, &spapr->phbs, list) {
e0fdbd7c 960 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt);
da34fed7
TH		 961 if (ret < 0) {
962 error_report("couldn't setup PCI devices in fdt");
963 exit(1);
964 }
3384f95c
DG		 965 }
966
39ac8455
DG		 967 /* RTAS */
968 ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size);
969 if (ret < 0) {
970 fprintf(stderr, "Couldn't set up RTAS device tree properties\n");
971 }
972
0da6f3fe
BR		 973 /* cpus */
974 spapr_populate_cpus_dt_node(fdt, spapr);
6e806cc3 975
71461b0f
AK		 976 bootlist = get_boot_devices_list(&cb, true);
977 if (cb && bootlist) {
978 int offset = fdt_path_offset(fdt, "/chosen");
979 if (offset < 0) {
980 exit(1);
981 }
982 for (i = 0; i < cb; i++) {
983 if (bootlist[i] == '\n') {
984 bootlist[i] = ' ';
985 }
986
987 }
988 ret = fdt_setprop_string(fdt, offset, "qemu,boot-list", bootlist);
989 }
990
5b2128d2
AG		 991 if (boot_device && strlen(boot_device)) {
992 int offset = fdt_path_offset(fdt, "/chosen");
993
994 if (offset < 0) {
995 exit(1);
996 }
997 fdt_setprop_string(fdt, offset, "qemu,boot-device", boot_device);
998 }
999
3fc5acde 1000 if (!spapr->has_graphics) {
f28359d8
LZ		 1001 spapr_populate_chosen_stdout(fdt, spapr->vio_bus);
1002 }
68f3a94c 1003
c20d332a
BR		 1004 if (smc->dr_lmb_enabled) {
1005 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB));
1006 }
1007
4040ab72
DG		 1008 _FDT((fdt_pack(fdt)));
1009
4d8d5467 1010 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) {
730fce59
TH		 1011 error_report("FDT too big ! 0x%x bytes (max is 0x%x)",
1012 fdt_totalsize(fdt), FDT_MAX_SIZE);
4d8d5467
BH		 1013 exit(1);
1014 }
1015
ad440b4a 1016 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
a3467baa 1017 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt));
9fdf0c29 1018
a21a7a70 1019 g_free(bootlist);
7267c094 1020 g_free(fdt);
9fdf0c29
DG		 1021}
1022
1023static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
1024{
1025 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
1026}
1027
1b14670a 1028static void emulate_spapr_hypercall(PowerPCCPU *cpu)
9fdf0c29 1029{
1b14670a
AF		 1030 CPUPPCState *env = &cpu->env;
1031
efcb9383
DG		 1032 if (msr_pr) {
1033 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1034 env->gpr[3] = H_PRIVILEGE;
1035 } else {
aa100fa4 1036 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]);
efcb9383 1037 }
9fdf0c29
DG		 1038}
1039
e6b8fd24
SMJ		 1040#define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1041#define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1042#define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1043#define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1044#define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1045
715c5407
DG		 1046/*
1047 * Get the fd to access the kernel htab, re-opening it if necessary
1048 */
1049static int get_htab_fd(sPAPRMachineState *spapr)
1050{
1051 if (spapr->htab_fd >= 0) {
1052 return spapr->htab_fd;
1053 }
1054
1055 spapr->htab_fd = kvmppc_get_htab_fd(false);
1056 if (spapr->htab_fd < 0) {
1057 error_report("Unable to open fd for reading hash table from KVM: %s",
1058 strerror(errno));
1059 }
1060
1061 return spapr->htab_fd;
1062}
1063
1064static void close_htab_fd(sPAPRMachineState *spapr)
1065{
1066 if (spapr->htab_fd >= 0) {
1067 close(spapr->htab_fd);
1068 }
1069 spapr->htab_fd = -1;
1070}
1071
8dfe8e7f
DG		 1072static int spapr_hpt_shift_for_ramsize(uint64_t ramsize)
1073{
1074 int shift;
1075
1076 /* We aim for a hash table of size 1/128 the size of RAM (rounded
1077 * up). The PAPR recommendation is actually 1/64 of RAM size, but
1078 * that's much more than is needed for Linux guests */
1079 shift = ctz64(pow2ceil(ramsize)) - 7;
1080 shift = MAX(shift, 18); /* Minimum architected size */
1081 shift = MIN(shift, 46); /* Maximum architected size */
1082 return shift;
1083}
1084
c5f54f3e
DG		 1085static void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift,
1086 Error **errp)
7f763a5d 1087{
c5f54f3e
DG		 1088 long rc;
1089
1090 /* Clean up any HPT info from a previous boot */
1091 g_free(spapr->htab);
1092 spapr->htab = NULL;
1093 spapr->htab_shift = 0;
1094 close_htab_fd(spapr);
1095
1096 rc = kvmppc_reset_htab(shift);
1097 if (rc < 0) {
1098 /* kernel-side HPT needed, but couldn't allocate one */
1099 error_setg_errno(errp, errno,
1100 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)",
1101 shift);
1102 /* This is almost certainly fatal, but if the caller really
1103 * wants to carry on with shift == 0, it's welcome to try */
1104 } else if (rc > 0) {
1105 /* kernel-side HPT allocated */
1106 if (rc != shift) {
1107 error_setg(errp,
1108 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)",
1109 shift, rc);
7735feda
BR		 1110 }
1111
7f763a5d 1112 spapr->htab_shift = shift;
c18ad9a5 1113 spapr->htab = NULL;
b817772a 1114 } else {
c5f54f3e
DG		 1115 /* kernel-side HPT not needed, allocate in userspace instead */
1116 size_t size = 1ULL << shift;
1117 int i;
b817772a 1118
c5f54f3e
DG		 1119 spapr->htab = qemu_memalign(size, size);
1120 if (!spapr->htab) {
1121 error_setg_errno(errp, errno,
1122 "Could not allocate HPT of order %d", shift);
1123 return;
7735feda
BR		 1124 }
1125
c5f54f3e
DG		 1126 memset(spapr->htab, 0, size);
1127 spapr->htab_shift = shift;
e6b8fd24 1128
c5f54f3e
DG		 1129 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) {
1130 DIRTY_HPTE(HPTE(spapr->htab, i));
e6b8fd24 1131 }
7f763a5d 1132 }
9fdf0c29
DG		 1133}
1134
9e3f9733
AG		 1135static int find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque)
1136{
1137 bool matched = false;
1138
1139 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
1140 matched = true;
1141 }
1142
1143 if (!matched) {
1144 error_report("Device %s is not supported by this machine yet.",
1145 qdev_fw_name(DEVICE(sbdev)));
1146 exit(1);
1147 }
1148
1149 return 0;
1150}
1151
c8787ad4 1152static void ppc_spapr_reset(void)
a3467baa 1153{
c5f54f3e
DG		 1154 MachineState *machine = MACHINE(qdev_get_machine());
1155 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
182735ef 1156 PowerPCCPU *first_ppc_cpu;
b7d1f77a 1157 uint32_t rtas_limit;
259186a7 1158
9e3f9733
AG		 1159 /* Check for unknown sysbus devices */
1160 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL);
1161
c5f54f3e
DG		 1162 /* Allocate and/or reset the hash page table */
1163 spapr_reallocate_hpt(spapr,
1164 spapr_hpt_shift_for_ramsize(machine->maxram_size),
1165 &error_fatal);
1166
1167 /* Update the RMA size if necessary */
1168 if (spapr->vrma_adjust) {
1169 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(),
1170 spapr->htab_shift);
1171 }
a3467baa 1172
c8787ad4 1173 qemu_devices_reset();
a3467baa 1174
b7d1f77a
BH		 1175 /*
1176 * We place the device tree and RTAS just below either the top of the RMA,
1177 * or just below 2GB, whichever is lowere, so that it can be
1178 * processed with 32-bit real mode code if necessary
1179 */
1180 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR);
1181 spapr->rtas_addr = rtas_limit - RTAS_MAX_SIZE;
1182 spapr->fdt_addr = spapr->rtas_addr - FDT_MAX_SIZE;
1183
a3467baa
DG		 1184 /* Load the fdt */
1185 spapr_finalize_fdt(spapr, spapr->fdt_addr, spapr->rtas_addr,
1186 spapr->rtas_size);
1187
b7d1f77a
BH		 1188 /* Copy RTAS over */
1189 cpu_physical_memory_write(spapr->rtas_addr, spapr->rtas_blob,
1190 spapr->rtas_size);
1191
a3467baa 1192 /* Set up the entry state */
182735ef
AF		 1193 first_ppc_cpu = POWERPC_CPU(first_cpu);
1194 first_ppc_cpu->env.gpr[3] = spapr->fdt_addr;
1195 first_ppc_cpu->env.gpr[5] = 0;
1196 first_cpu->halted = 0;
1b718907 1197 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT;
a3467baa
DG		 1198
1199}
1200
1bba0dc9
AF		 1201static void spapr_cpu_reset(void *opaque)
1202{
28e02042 1203 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
5b2038e0 1204 PowerPCCPU *cpu = opaque;
259186a7 1205 CPUState *cs = CPU(cpu);
048706d9 1206 CPUPPCState *env = &cpu->env;
1bba0dc9 1207
259186a7 1208 cpu_reset(cs);
048706d9
DG		 1209
1210 /* All CPUs start halted. CPU0 is unhalted from the machine level
1211 * reset code and the rest are explicitly started up by the guest
1212 * using an RTAS call */
259186a7 1213 cs->halted = 1;
048706d9
DG		 1214
1215 env->spr[SPR_HIOR] = 0;
7f763a5d 1216
e5c0d3ce
DG		 1217 ppc_hash64_set_external_hpt(cpu, spapr->htab, spapr->htab_shift,
1218 &error_fatal);
1bba0dc9
AF		 1219}
1220
28e02042 1221static void spapr_create_nvram(sPAPRMachineState *spapr)
639e8102 1222{
2ff3de68 1223 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram");
3978b863 1224 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
639e8102 1225
3978b863 1226 if (dinfo) {
6231a6da
MA		 1227 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
1228 &error_fatal);
639e8102
DG		 1229 }
1230
1231 qdev_init_nofail(dev);
1232
1233 spapr->nvram = (struct sPAPRNVRAM *)dev;
1234}
1235
28e02042 1236static void spapr_rtc_create(sPAPRMachineState *spapr)
28df36a1
DG		 1237{
1238 DeviceState *dev = qdev_create(NULL, TYPE_SPAPR_RTC);
1239
1240 qdev_init_nofail(dev);
1241 spapr->rtc = dev;
74e5ae28
DG		 1242
1243 object_property_add_alias(qdev_get_machine(), "rtc-time",
1244 OBJECT(spapr->rtc), "date", NULL);
28df36a1
DG		 1245}
1246
8c57b867 1247/* Returns whether we want to use VGA or not */
14c6a894 1248static bool spapr_vga_init(PCIBus *pci_bus, Error **errp)
f28359d8 1249{
8c57b867 1250 switch (vga_interface_type) {
8c57b867 1251 case VGA_NONE:
7effdaa3
MW		 1252 return false;
1253 case VGA_DEVICE:
1254 return true;
1ddcae82 1255 case VGA_STD:
b798c190 1256 case VGA_VIRTIO:
1ddcae82 1257 return pci_vga_init(pci_bus) != NULL;
8c57b867 1258 default:
14c6a894
DG		 1259 error_setg(errp,
1260 "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1261 return false;
f28359d8 1262 }
f28359d8
LZ		 1263}
1264
880ae7de
DG		 1265static int spapr_post_load(void *opaque, int version_id)
1266{
28e02042 1267 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque;
880ae7de
DG		 1268 int err = 0;
1269
631b22ea 1270 /* In earlier versions, there was no separate qdev for the PAPR
880ae7de
DG		 1271 * RTC, so the RTC offset was stored directly in sPAPREnvironment.
1272 * So when migrating from those versions, poke the incoming offset
1273 * value into the RTC device */
1274 if (version_id < 3) {
1275 err = spapr_rtc_import_offset(spapr->rtc, spapr->rtc_offset);
1276 }
1277
1278 return err;
1279}
1280
1281static bool version_before_3(void *opaque, int version_id)
1282{
1283 return version_id < 3;
1284}
1285
4be21d56
DG		 1286static const VMStateDescription vmstate_spapr = {
1287 .name = "spapr",
880ae7de 1288 .version_id = 3,
4be21d56 1289 .minimum_version_id = 1,
880ae7de 1290 .post_load = spapr_post_load,
3aff6c2f 1291 .fields = (VMStateField[]) {
880ae7de
DG		 1292 /* used to be @next_irq */
1293 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4),
4be21d56
DG		 1294
1295 /* RTC offset */
28e02042 1296 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3),
880ae7de 1297
28e02042 1298 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2),
4be21d56
DG		 1299 VMSTATE_END_OF_LIST()
1300 },
1301};
1302
4be21d56
DG		 1303static int htab_save_setup(QEMUFile *f, void *opaque)
1304{
28e02042 1305 sPAPRMachineState *spapr = opaque;
4be21d56 1306
4be21d56
DG		 1307 /* "Iteration" header */
1308 qemu_put_be32(f, spapr->htab_shift);
1309
e68cb8b4
AK		 1310 if (spapr->htab) {
1311 spapr->htab_save_index = 0;
1312 spapr->htab_first_pass = true;
1313 } else {
1314 assert(kvm_enabled());
e68cb8b4
AK		 1315 }
1316
1317
4be21d56
DG		 1318 return 0;
1319}
1320
28e02042 1321static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr,
4be21d56
DG		 1322 int64_t max_ns)
1323{
378bc217 1324 bool has_timeout = max_ns != -1;
4be21d56
DG		 1325 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1326 int index = spapr->htab_save_index;
bc72ad67 1327 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
4be21d56
DG		 1328
1329 assert(spapr->htab_first_pass);
1330
1331 do {
1332 int chunkstart;
1333
1334 /* Consume invalid HPTEs */
1335 while ((index < htabslots)
1336 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1337 index++;
1338 CLEAN_HPTE(HPTE(spapr->htab, index));
1339 }
1340
1341 /* Consume valid HPTEs */
1342 chunkstart = index;
338c25b6 1343 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
4be21d56
DG		 1344 && HPTE_VALID(HPTE(spapr->htab, index))) {
1345 index++;
1346 CLEAN_HPTE(HPTE(spapr->htab, index));
1347 }
1348
1349 if (index > chunkstart) {
1350 int n_valid = index - chunkstart;
1351
1352 qemu_put_be32(f, chunkstart);
1353 qemu_put_be16(f, n_valid);
1354 qemu_put_be16(f, 0);
1355 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1356 HASH_PTE_SIZE_64 * n_valid);
1357
378bc217
DG		 1358 if (has_timeout &&
1359 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
4be21d56
DG		 1360 break;
1361 }
1362 }
1363 } while ((index < htabslots) && !qemu_file_rate_limit(f));
1364
1365 if (index >= htabslots) {
1366 assert(index == htabslots);
1367 index = 0;
1368 spapr->htab_first_pass = false;
1369 }
1370 spapr->htab_save_index = index;
1371}
1372
28e02042 1373static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr,
e68cb8b4 1374 int64_t max_ns)
4be21d56
DG		 1375{
1376 bool final = max_ns < 0;
1377 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1378 int examined = 0, sent = 0;
1379 int index = spapr->htab_save_index;
bc72ad67 1380 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
4be21d56
DG		 1381
1382 assert(!spapr->htab_first_pass);
1383
1384 do {
1385 int chunkstart, invalidstart;
1386
1387 /* Consume non-dirty HPTEs */
1388 while ((index < htabslots)
1389 && !HPTE_DIRTY(HPTE(spapr->htab, index))) {
1390 index++;
1391 examined++;
1392 }
1393
1394 chunkstart = index;
1395 /* Consume valid dirty HPTEs */
338c25b6 1396 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
4be21d56
DG		 1397 && HPTE_DIRTY(HPTE(spapr->htab, index))
1398 && HPTE_VALID(HPTE(spapr->htab, index))) {
1399 CLEAN_HPTE(HPTE(spapr->htab, index));
1400 index++;
1401 examined++;
1402 }
1403
1404 invalidstart = index;
1405 /* Consume invalid dirty HPTEs */
338c25b6 1406 while ((index < htabslots) && (index - invalidstart < USHRT_MAX)
4be21d56
DG		 1407 && HPTE_DIRTY(HPTE(spapr->htab, index))
1408 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1409 CLEAN_HPTE(HPTE(spapr->htab, index));
1410 index++;
1411 examined++;
1412 }
1413
1414 if (index > chunkstart) {
1415 int n_valid = invalidstart - chunkstart;
1416 int n_invalid = index - invalidstart;
1417
1418 qemu_put_be32(f, chunkstart);
1419 qemu_put_be16(f, n_valid);
1420 qemu_put_be16(f, n_invalid);
1421 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1422 HASH_PTE_SIZE_64 * n_valid);
1423 sent += index - chunkstart;
1424
bc72ad67 1425 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
4be21d56
DG		 1426 break;
1427 }
1428 }
1429
1430 if (examined >= htabslots) {
1431 break;
1432 }
1433
1434 if (index >= htabslots) {
1435 assert(index == htabslots);
1436 index = 0;
1437 }
1438 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final));
1439
1440 if (index >= htabslots) {
1441 assert(index == htabslots);
1442 index = 0;
1443 }
1444
1445 spapr->htab_save_index = index;
1446
e68cb8b4 1447 return (examined >= htabslots) && (sent == 0) ? 1 : 0;
4be21d56
DG		 1448}
1449
e68cb8b4
AK		 1450#define MAX_ITERATION_NS 5000000 /* 5 ms */
1451#define MAX_KVM_BUF_SIZE 2048
1452
4be21d56
DG		 1453static int htab_save_iterate(QEMUFile *f, void *opaque)
1454{
28e02042 1455 sPAPRMachineState *spapr = opaque;
715c5407 1456 int fd;
e68cb8b4 1457 int rc = 0;
4be21d56
DG		 1458
1459 /* Iteration header */
1460 qemu_put_be32(f, 0);
1461
e68cb8b4
AK		 1462 if (!spapr->htab) {
1463 assert(kvm_enabled());
1464
715c5407
DG		 1465 fd = get_htab_fd(spapr);
1466 if (fd < 0) {
1467 return fd;
01a57972
SMJ		 1468 }
1469
715c5407 1470 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS);
e68cb8b4
AK		 1471 if (rc < 0) {
1472 return rc;
1473 }
1474 } else if (spapr->htab_first_pass) {
4be21d56
DG		 1475 htab_save_first_pass(f, spapr, MAX_ITERATION_NS);
1476 } else {
e68cb8b4 1477 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS);
4be21d56
DG		 1478 }
1479
1480 /* End marker */
1481 qemu_put_be32(f, 0);
1482 qemu_put_be16(f, 0);
1483 qemu_put_be16(f, 0);
1484
e68cb8b4 1485 return rc;
4be21d56
DG		 1486}
1487
1488static int htab_save_complete(QEMUFile *f, void *opaque)
1489{
28e02042 1490 sPAPRMachineState *spapr = opaque;
715c5407 1491 int fd;
4be21d56
DG		 1492
1493 /* Iteration header */
1494 qemu_put_be32(f, 0);
1495
e68cb8b4
AK		 1496 if (!spapr->htab) {
1497 int rc;
1498
1499 assert(kvm_enabled());
1500
715c5407
DG		 1501 fd = get_htab_fd(spapr);
1502 if (fd < 0) {
1503 return fd;
01a57972
SMJ		 1504 }
1505
715c5407 1506 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1);
e68cb8b4
AK		 1507 if (rc < 0) {
1508 return rc;
1509 }
715c5407 1510 close_htab_fd(spapr);
e68cb8b4 1511 } else {
378bc217
DG		 1512 if (spapr->htab_first_pass) {
1513 htab_save_first_pass(f, spapr, -1);
1514 }
e68cb8b4
AK		 1515 htab_save_later_pass(f, spapr, -1);
1516 }
4be21d56
DG		 1517
1518 /* End marker */
1519 qemu_put_be32(f, 0);
1520 qemu_put_be16(f, 0);
1521 qemu_put_be16(f, 0);
1522
1523 return 0;
1524}
1525
1526static int htab_load(QEMUFile *f, void *opaque, int version_id)
1527{
28e02042 1528 sPAPRMachineState *spapr = opaque;
4be21d56 1529 uint32_t section_hdr;
e68cb8b4 1530 int fd = -1;
4be21d56
DG		 1531
1532 if (version_id < 1 || version_id > 1) {
98a5d100 1533 error_report("htab_load() bad version");
4be21d56
DG		 1534 return -EINVAL;
1535 }
1536
1537 section_hdr = qemu_get_be32(f);
1538
1539 if (section_hdr) {
9897e462 1540 Error *local_err = NULL;
c5f54f3e
DG		 1541
1542 /* First section gives the htab size */
1543 spapr_reallocate_hpt(spapr, section_hdr, &local_err);
1544 if (local_err) {
1545 error_report_err(local_err);
4be21d56
DG		 1546 return -EINVAL;
1547 }
1548 return 0;
1549 }
1550
e68cb8b4
AK		 1551 if (!spapr->htab) {
1552 assert(kvm_enabled());
1553
1554 fd = kvmppc_get_htab_fd(true);
1555 if (fd < 0) {
98a5d100
DG		 1556 error_report("Unable to open fd to restore KVM hash table: %s",
1557 strerror(errno));
e68cb8b4
AK		 1558 }
1559 }
1560
4be21d56
DG		 1561 while (true) {
1562 uint32_t index;
1563 uint16_t n_valid, n_invalid;
1564
1565 index = qemu_get_be32(f);
1566 n_valid = qemu_get_be16(f);
1567 n_invalid = qemu_get_be16(f);
1568
1569 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) {
1570 /* End of Stream */
1571 break;
1572 }
1573
e68cb8b4 1574 if ((index + n_valid + n_invalid) >
4be21d56
DG		 1575 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) {
1576 /* Bad index in stream */
98a5d100
DG		 1577 error_report(
1578 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
1579 index, n_valid, n_invalid, spapr->htab_shift);
4be21d56
DG		 1580 return -EINVAL;
1581 }
1582
e68cb8b4
AK		 1583 if (spapr->htab) {
1584 if (n_valid) {
1585 qemu_get_buffer(f, HPTE(spapr->htab, index),
1586 HASH_PTE_SIZE_64 * n_valid);
1587 }
1588 if (n_invalid) {
1589 memset(HPTE(spapr->htab, index + n_valid), 0,
1590 HASH_PTE_SIZE_64 * n_invalid);
1591 }
1592 } else {
1593 int rc;
1594
1595 assert(fd >= 0);
1596
1597 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid);
1598 if (rc < 0) {
1599 return rc;
1600 }
4be21d56
DG		 1601 }
1602 }
1603
e68cb8b4
AK		 1604 if (!spapr->htab) {
1605 assert(fd >= 0);
1606 close(fd);
1607 }
1608
4be21d56
DG		 1609 return 0;
1610}
1611
1612static SaveVMHandlers savevm_htab_handlers = {
1613 .save_live_setup = htab_save_setup,
1614 .save_live_iterate = htab_save_iterate,
a3e06c3d 1615 .save_live_complete_precopy = htab_save_complete,
4be21d56
DG		 1616 .load_state = htab_load,
1617};
1618
5b2128d2
AG		 1619static void spapr_boot_set(void *opaque, const char *boot_device,
1620 Error **errp)
1621{
1622 MachineState *machine = MACHINE(qdev_get_machine());
1623 machine->boot_order = g_strdup(boot_device);
1624}
1625
3b542549 1626void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu, Error **errp)
bab99ea0
BR		 1627{
1628 CPUPPCState *env = &cpu->env;
1629
1630 /* Set time-base frequency to 512 MHz */
1631 cpu_ppc_tb_init(env, TIMEBASE_FREQ);
1632
26a7f129
BH		 1633 /* Enable PAPR mode in TCG or KVM */
1634 cpu_ppc_set_papr(cpu);
bab99ea0
BR		 1635
1636 if (cpu->max_compat) {
569f4967
DG		 1637 Error *local_err = NULL;
1638
1639 ppc_set_compat(cpu, cpu->max_compat, &local_err);
1640 if (local_err) {
1641 error_propagate(errp, local_err);
1642 return;
1643 }
bab99ea0
BR		 1644 }
1645
1646 xics_cpu_setup(spapr->icp, cpu);
1647
1648 qemu_register_reset(spapr_cpu_reset, cpu);
1649}
1650
224245bf
DG		 1651/*
1652 * Reset routine for LMB DR devices.
1653 *
1654 * Unlike PCI DR devices, LMB DR devices explicitly register this reset
1655 * routine. Reset for PCI DR devices will be handled by PHB reset routine
1656 * when it walks all its children devices. LMB devices reset occurs
1657 * as part of spapr_ppc_reset().
1658 */
1659static void spapr_drc_reset(void *opaque)
1660{
1661 sPAPRDRConnector *drc = opaque;
1662 DeviceState *d = DEVICE(drc);
1663
1664 if (d) {
1665 device_reset(d);
1666 }
1667}
1668
1669static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr)
1670{
1671 MachineState *machine = MACHINE(spapr);
1672 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
e8f986fc 1673 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size;
224245bf
DG		 1674 int i;
1675
1676 for (i = 0; i < nr_lmbs; i++) {
1677 sPAPRDRConnector *drc;
1678 uint64_t addr;
1679
e8f986fc 1680 addr = i * lmb_size + spapr->hotplug_memory.base;
224245bf
DG		 1681 drc = spapr_dr_connector_new(OBJECT(spapr), SPAPR_DR_CONNECTOR_TYPE_LMB,
1682 addr/lmb_size);
1683 qemu_register_reset(spapr_drc_reset, drc);
1684 }
1685}
1686
1687/*
1688 * If RAM size, maxmem size and individual node mem sizes aren't aligned
1689 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest
1690 * since we can't support such unaligned sizes with DRCONF_MEMORY.
1691 */
7c150d6f 1692static void spapr_validate_node_memory(MachineState *machine, Error **errp)
224245bf
DG		 1693{
1694 int i;
1695
7c150d6f
DG		 1696 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) {
1697 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT
1698 " is not aligned to %llu MiB",
1699 machine->ram_size,
1700 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1701 return;
1702 }
1703
1704 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) {
1705 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT
1706 " is not aligned to %llu MiB",
1707 machine->ram_size,
1708 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1709 return;
224245bf
DG		 1710 }
1711
1712 for (i = 0; i < nb_numa_nodes; i++) {
1713 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) {
7c150d6f
DG		 1714 error_setg(errp,
1715 "Node %d memory size 0x%" PRIx64
1716 " is not aligned to %llu MiB",
1717 i, numa_info[i].node_mem,
1718 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1719 return;
224245bf
DG		 1720 }
1721 }
1722}
1723
9fdf0c29 1724/* pSeries LPAR / sPAPR hardware init */
3ef96221 1725static void ppc_spapr_init(MachineState *machine)
9fdf0c29 1726{
28e02042 1727 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
224245bf 1728 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
3ef96221
MA		 1729 const char *kernel_filename = machine->kernel_filename;
1730 const char *kernel_cmdline = machine->kernel_cmdline;
1731 const char *initrd_filename = machine->initrd_filename;
05769733 1732 PowerPCCPU *cpu;
8c9f64df 1733 PCIHostState *phb;
9fdf0c29 1734 int i;
890c2b77
AK		 1735 MemoryRegion *sysmem = get_system_memory();
1736 MemoryRegion *ram = g_new(MemoryRegion, 1);
658fa66b
AK		 1737 MemoryRegion *rma_region;
1738 void *rma = NULL;
a8170e5e 1739 hwaddr rma_alloc_size;
b082d65a 1740 hwaddr node0_size = spapr_node0_size();
4d8d5467
BH		 1741 uint32_t initrd_base = 0;
1742 long kernel_size = 0, initrd_size = 0;
b7d1f77a 1743 long load_limit, fw_size;
16457e7f 1744 bool kernel_le = false;
39ac8455 1745 char *filename;
9fdf0c29 1746
226419d6 1747 msi_nonbroken = true;
0ee2c058 1748
d43b45e2
DG		 1749 QLIST_INIT(&spapr->phbs);
1750
9fdf0c29
DG		 1751 cpu_ppc_hypercall = emulate_spapr_hypercall;
1752
354ac20a 1753 /* Allocate RMA if necessary */
658fa66b 1754 rma_alloc_size = kvmppc_alloc_rma(&rma);
354ac20a
DG		 1755
1756 if (rma_alloc_size == -1) {
730fce59 1757 error_report("Unable to create RMA");
354ac20a
DG		 1758 exit(1);
1759 }
7f763a5d 1760
c4177479 1761 if (rma_alloc_size && (rma_alloc_size < node0_size)) {
7f763a5d 1762 spapr->rma_size = rma_alloc_size;
354ac20a 1763 } else {
c4177479 1764 spapr->rma_size = node0_size;
7f763a5d
DG		 1765
1766 /* With KVM, we don't actually know whether KVM supports an
1767 * unbounded RMA (PR KVM) or is limited by the hash table size
1768 * (HV KVM using VRMA), so we always assume the latter
1769 *
1770 * In that case, we also limit the initial allocations for RTAS
1771 * etc... to 256M since we have no way to know what the VRMA size
1772 * is going to be as it depends on the size of the hash table
1773 * isn't determined yet.
1774 */
1775 if (kvm_enabled()) {
1776 spapr->vrma_adjust = 1;
1777 spapr->rma_size = MIN(spapr->rma_size, 0x10000000);
1778 }
354ac20a
DG		 1779 }
1780
c4177479 1781 if (spapr->rma_size > node0_size) {
d54e4d76
DG		 1782 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")",
1783 spapr->rma_size);
c4177479
AK		 1784 exit(1);
1785 }
1786
b7d1f77a
BH		 1787 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */
1788 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD;
9fdf0c29 1789
7b565160 1790 /* Set up Interrupt Controller before we create the VCPUs */
446f16a6 1791 spapr->icp = xics_system_init(machine,
9e734e3d 1792 DIV_ROUND_UP(max_cpus * kvmppc_smt_threads(),
f303f117 1793 smp_threads),
1e49182d 1794 XICS_IRQS, &error_fatal);
7b565160 1795
224245bf 1796 if (smc->dr_lmb_enabled) {
7c150d6f 1797 spapr_validate_node_memory(machine, &error_fatal);
224245bf
DG		 1798 }
1799
9fdf0c29 1800 /* init CPUs */
19fb2c36
BR		 1801 if (machine->cpu_model == NULL) {
1802 machine->cpu_model = kvm_enabled() ? "host" : "POWER7";
9fdf0c29
DG		 1803 }
1804 for (i = 0; i < smp_cpus; i++) {
19fb2c36 1805 cpu = cpu_ppc_init(machine->cpu_model);
05769733 1806 if (cpu == NULL) {
569f4967 1807 error_report("Unable to find PowerPC CPU definition");
9fdf0c29
DG		 1808 exit(1);
1809 }
569f4967 1810 spapr_cpu_init(spapr, cpu, &error_fatal);
9fdf0c29
DG		 1811 }
1812
026bfd89
DG		 1813 if (kvm_enabled()) {
1814 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */
1815 kvmppc_enable_logical_ci_hcalls();
ef9971dd 1816 kvmppc_enable_set_mode_hcall();
026bfd89
DG		 1817 }
1818
9fdf0c29 1819 /* allocate RAM */
f92f5da1 1820 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram",
fb164994 1821 machine->ram_size);
f92f5da1 1822 memory_region_add_subregion(sysmem, 0, ram);
9fdf0c29 1823
658fa66b
AK		 1824 if (rma_alloc_size && rma) {
1825 rma_region = g_new(MemoryRegion, 1);
1826 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma",
1827 rma_alloc_size, rma);
1828 vmstate_register_ram_global(rma_region);
1829 memory_region_add_subregion(sysmem, 0, rma_region);
1830 }
1831
4a1c9cf0
BR		 1832 /* initialize hotplug memory address space */
1833 if (machine->ram_size < machine->maxram_size) {
1834 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size;
71c9a3dd
BR		 1835 /*
1836 * Limit the number of hotpluggable memory slots to half the number
1837 * slots that KVM supports, leaving the other half for PCI and other
1838 * devices. However ensure that number of slots doesn't drop below 32.
1839 */
1840 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 :
1841 SPAPR_MAX_RAM_SLOTS;
4a1c9cf0 1842
71c9a3dd
BR		 1843 if (max_memslots < SPAPR_MAX_RAM_SLOTS) {
1844 max_memslots = SPAPR_MAX_RAM_SLOTS;
1845 }
1846 if (machine->ram_slots > max_memslots) {
d54e4d76
DG		 1847 error_report("Specified number of memory slots %"
1848 PRIu64" exceeds max supported %d",
71c9a3dd 1849 machine->ram_slots, max_memslots);
d54e4d76 1850 exit(1);
4a1c9cf0
BR		 1851 }
1852
1853 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size,
1854 SPAPR_HOTPLUG_MEM_ALIGN);
1855 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr),
1856 "hotplug-memory", hotplug_mem_size);
1857 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base,
1858 &spapr->hotplug_memory.mr);
1859 }
1860
224245bf
DG		 1861 if (smc->dr_lmb_enabled) {
1862 spapr_create_lmb_dr_connectors(spapr);
1863 }
1864
39ac8455 1865 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
4c56440d 1866 if (!filename) {
730fce59 1867 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin");
4c56440d
SW		 1868 exit(1);
1869 }
b7d1f77a 1870 spapr->rtas_size = get_image_size(filename);
8afc22a2
ZJ		 1871 if (spapr->rtas_size < 0) {
1872 error_report("Could not get size of LPAR rtas '%s'", filename);
1873 exit(1);
1874 }
b7d1f77a
BH		 1875 spapr->rtas_blob = g_malloc(spapr->rtas_size);
1876 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) {
730fce59 1877 error_report("Could not load LPAR rtas '%s'", filename);
39ac8455
DG		 1878 exit(1);
1879 }
4d8d5467 1880 if (spapr->rtas_size > RTAS_MAX_SIZE) {
730fce59
TH		 1881 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)",
1882 (size_t)spapr->rtas_size, RTAS_MAX_SIZE);
4d8d5467
BH		 1883 exit(1);
1884 }
7267c094 1885 g_free(filename);
39ac8455 1886
74d042e5
DG		 1887 /* Set up EPOW events infrastructure */
1888 spapr_events_init(spapr);
1889
12f42174 1890 /* Set up the RTC RTAS interfaces */
28df36a1 1891 spapr_rtc_create(spapr);
12f42174 1892
b5cec4c5 1893 /* Set up VIO bus */
4040ab72
DG		 1894 spapr->vio_bus = spapr_vio_bus_init();
1895
277f9acf 1896 for (i = 0; i < MAX_SERIAL_PORTS; i++) {
4040ab72 1897 if (serial_hds[i]) {
d601fac4 1898 spapr_vty_create(spapr->vio_bus, serial_hds[i]);
4040ab72
DG		 1899 }
1900 }
9fdf0c29 1901
639e8102
DG		 1902 /* We always have at least the nvram device on VIO */
1903 spapr_create_nvram(spapr);
1904
3384f95c 1905 /* Set up PCI */
fa28f71b
AK		 1906 spapr_pci_rtas_init();
1907
89dfd6e1 1908 phb = spapr_create_phb(spapr, 0);
3384f95c 1909
277f9acf 1910 for (i = 0; i < nb_nics; i++) {
8d90ad90
DG		 1911 NICInfo *nd = &nd_table[i];
1912
1913 if (!nd->model) {
7267c094 1914 nd->model = g_strdup("ibmveth");
8d90ad90
DG		 1915 }
1916
1917 if (strcmp(nd->model, "ibmveth") == 0) {
d601fac4 1918 spapr_vlan_create(spapr->vio_bus, nd);
8d90ad90 1919 } else {
29b358f9 1920 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL);
8d90ad90
DG		 1921 }
1922 }
1923
6e270446 1924 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) {
d601fac4 1925 spapr_vscsi_create(spapr->vio_bus);
6e270446
BH		 1926 }
1927
f28359d8 1928 /* Graphics */
14c6a894 1929 if (spapr_vga_init(phb->bus, &error_fatal)) {
3fc5acde 1930 spapr->has_graphics = true;
c6e76503 1931 machine->usb |= defaults_enabled() && !machine->usb_disabled;
f28359d8
LZ		 1932 }
1933
4ee9ced9 1934 if (machine->usb) {
57040d45
TH		 1935 if (smc->use_ohci_by_default) {
1936 pci_create_simple(phb->bus, -1, "pci-ohci");
1937 } else {
1938 pci_create_simple(phb->bus, -1, "nec-usb-xhci");
1939 }
c86580b8 1940
35139a59 1941 if (spapr->has_graphics) {
c86580b8
MA		 1942 USBBus *usb_bus = usb_bus_find(-1);
1943
1944 usb_create_simple(usb_bus, "usb-kbd");
1945 usb_create_simple(usb_bus, "usb-mouse");
35139a59
DG		 1946 }
1947 }
1948
7f763a5d 1949 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) {
d54e4d76
DG		 1950 error_report(
1951 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)",
1952 MIN_RMA_SLOF);
4d8d5467
BH		 1953 exit(1);
1954 }
1955
9fdf0c29
DG		 1956 if (kernel_filename) {
1957 uint64_t lowaddr = 0;
1958
9fdf0c29 1959 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
7ef295ea
PC		 1960 NULL, &lowaddr, NULL, 1, PPC_ELF_MACHINE,
1961 0, 0);
3b66da82 1962 if (kernel_size == ELF_LOAD_WRONG_ENDIAN) {
16457e7f
BH		 1963 kernel_size = load_elf(kernel_filename,
1964 translate_kernel_address, NULL,
7ef295ea
PC		 1965 NULL, &lowaddr, NULL, 0, PPC_ELF_MACHINE,
1966 0, 0);
16457e7f
BH		 1967 kernel_le = kernel_size > 0;
1968 }
9fdf0c29 1969 if (kernel_size < 0) {
d54e4d76
DG		 1970 error_report("error loading %s: %s",
1971 kernel_filename, load_elf_strerror(kernel_size));
9fdf0c29
DG		 1972 exit(1);
1973 }
1974
1975 /* load initrd */
1976 if (initrd_filename) {
4d8d5467
BH		 1977 /* Try to locate the initrd in the gap between the kernel
1978 * and the firmware. Add a bit of space just in case
1979 */
1980 initrd_base = (KERNEL_LOAD_ADDR + kernel_size + 0x1ffff) & ~0xffff;
9fdf0c29 1981 initrd_size = load_image_targphys(initrd_filename, initrd_base,
4d8d5467 1982 load_limit - initrd_base);
9fdf0c29 1983 if (initrd_size < 0) {
d54e4d76
DG		 1984 error_report("could not load initial ram disk '%s'",
1985 initrd_filename);
9fdf0c29
DG		 1986 exit(1);
1987 }
1988 } else {
1989 initrd_base = 0;
1990 initrd_size = 0;
1991 }
4d8d5467 1992 }
a3467baa 1993
8e7ea787
AF		 1994 if (bios_name == NULL) {
1995 bios_name = FW_FILE_NAME;
1996 }
1997 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
4c56440d 1998 if (!filename) {
68fea5a0 1999 error_report("Could not find LPAR firmware '%s'", bios_name);
4c56440d
SW		 2000 exit(1);
2001 }
4d8d5467 2002 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
68fea5a0
TH		 2003 if (fw_size <= 0) {
2004 error_report("Could not load LPAR firmware '%s'", filename);
4d8d5467
BH		 2005 exit(1);
2006 }
2007 g_free(filename);
4d8d5467 2008
28e02042
DG		 2009 /* FIXME: Should register things through the MachineState's qdev
2010 * interface, this is a legacy from the sPAPREnvironment structure
2011 * which predated MachineState but had a similar function */
4be21d56
DG		 2012 vmstate_register(NULL, 0, &vmstate_spapr, spapr);
2013 register_savevm_live(NULL, "spapr/htab", -1, 1,
2014 &savevm_htab_handlers, spapr);
2015
9fdf0c29 2016 /* Prepare the device tree */
3bbf37f2 2017 spapr->fdt_skel = spapr_create_fdt_skel(initrd_base, initrd_size,
16457e7f 2018 kernel_size, kernel_le,
31fe14d1
NF		 2019 kernel_cmdline,
2020 spapr->check_exception_irq);
a3467baa 2021 assert(spapr->fdt_skel != NULL);
5b2128d2 2022
46503c2b
MR		 2023 /* used by RTAS */
2024 QTAILQ_INIT(&spapr->ccs_list);
2025 qemu_register_reset(spapr_ccs_reset_hook, spapr);
2026
5b2128d2 2027 qemu_register_boot_set(spapr_boot_set, spapr);
9fdf0c29
DG		 2028}
2029
135a129a
AK		 2030static int spapr_kvm_type(const char *vm_type)
2031{
2032 if (!vm_type) {
2033 return 0;
2034 }
2035
2036 if (!strcmp(vm_type, "HV")) {
2037 return 1;
2038 }
2039
2040 if (!strcmp(vm_type, "PR")) {
2041 return 2;
2042 }
2043
2044 error_report("Unknown kvm-type specified '%s'", vm_type);
2045 exit(1);
2046}
2047
71461b0f 2048/*
627b84f4 2049 * Implementation of an interface to adjust firmware path
71461b0f
AK		 2050 * for the bootindex property handling.
2051 */
2052static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus,
2053 DeviceState *dev)
2054{
2055#define CAST(type, obj, name) \
2056 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
2057 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE);
2058 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE);
2059
2060 if (d) {
2061 void *spapr = CAST(void, bus->parent, "spapr-vscsi");
2062 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI);
2063 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE);
2064
2065 if (spapr) {
2066 /*
2067 * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
2068 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun
2069 * in the top 16 bits of the 64-bit LUN
2070 */
2071 unsigned id = 0x8000 | (d->id << 8) | d->lun;
2072 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2073 (uint64_t)id << 48);
2074 } else if (virtio) {
2075 /*
2076 * We use SRP luns of the form 01000000 | (target << 8) | lun
2077 * in the top 32 bits of the 64-bit LUN
2078 * Note: the quote above is from SLOF and it is wrong,
2079 * the actual binding is:
2080 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
2081 */
2082 unsigned id = 0x1000000 | (d->id << 16) | d->lun;
2083 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2084 (uint64_t)id << 32);
2085 } else if (usb) {
2086 /*
2087 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
2088 * in the top 32 bits of the 64-bit LUN
2089 */
2090 unsigned usb_port = atoi(usb->port->path);
2091 unsigned id = 0x1000000 | (usb_port << 16) | d->lun;
2092 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2093 (uint64_t)id << 32);
2094 }
2095 }
2096
2097 if (phb) {
2098 /* Replace "pci" with "pci@800000020000000" */
2099 return g_strdup_printf("pci@%"PRIX64, phb->buid);
2100 }
2101
2102 return NULL;
2103}
2104
23825581
EH		 2105static char *spapr_get_kvm_type(Object *obj, Error **errp)
2106{
28e02042 2107 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
23825581 2108
28e02042 2109 return g_strdup(spapr->kvm_type);
23825581
EH		 2110}
2111
2112static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp)
2113{
28e02042 2114 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
23825581 2115
28e02042
DG		 2116 g_free(spapr->kvm_type);
2117 spapr->kvm_type = g_strdup(value);
23825581
EH		 2118}
2119
2120static void spapr_machine_initfn(Object *obj)
2121{
715c5407
DG		 2122 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2123
2124 spapr->htab_fd = -1;
23825581
EH		 2125 object_property_add_str(obj, "kvm-type",
2126 spapr_get_kvm_type, spapr_set_kvm_type, NULL);
49d2e648
MA		 2127 object_property_set_description(obj, "kvm-type",
2128 "Specifies the KVM virtualization mode (HV, PR)",
2129 NULL);
23825581
EH		 2130}
2131
87bbdd9c
DG		 2132static void spapr_machine_finalizefn(Object *obj)
2133{
2134 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2135
2136 g_free(spapr->kvm_type);
2137}
2138
34316482
AK		 2139static void ppc_cpu_do_nmi_on_cpu(void *arg)
2140{
2141 CPUState *cs = arg;
2142
2143 cpu_synchronize_state(cs);
2144 ppc_cpu_do_system_reset(cs);
2145}
2146
2147static void spapr_nmi(NMIState *n, int cpu_index, Error **errp)
2148{
2149 CPUState *cs;
2150
2151 CPU_FOREACH(cs) {
2152 async_run_on_cpu(cs, ppc_cpu_do_nmi_on_cpu, cs);
2153 }
2154}
2155
c20d332a
BR		 2156static void spapr_add_lmbs(DeviceState *dev, uint64_t addr, uint64_t size,
2157 uint32_t node, Error **errp)
2158{
2159 sPAPRDRConnector *drc;
2160 sPAPRDRConnectorClass *drck;
2161 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE;
2162 int i, fdt_offset, fdt_size;
2163 void *fdt;
2164
c20d332a
BR		 2165 for (i = 0; i < nr_lmbs; i++) {
2166 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB,
2167 addr/SPAPR_MEMORY_BLOCK_SIZE);
2168 g_assert(drc);
2169
2170 fdt = create_device_tree(&fdt_size);
2171 fdt_offset = spapr_populate_memory_node(fdt, node, addr,
2172 SPAPR_MEMORY_BLOCK_SIZE);
2173
2174 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2175 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, errp);
c20d332a
BR		 2176 addr += SPAPR_MEMORY_BLOCK_SIZE;
2177 }
5dd5238c
JD		 2178 /* send hotplug notification to the
2179 * guest only in case of hotplugged memory
2180 */
2181 if (dev->hotplugged) {
2182 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, nr_lmbs);
2183 }
c20d332a
BR		 2184}
2185
2186static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2187 uint32_t node, Error **errp)
2188{
2189 Error *local_err = NULL;
2190 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev);
2191 PCDIMMDevice *dimm = PC_DIMM(dev);
2192 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
2193 MemoryRegion *mr = ddc->get_memory_region(dimm);
2194 uint64_t align = memory_region_get_alignment(mr);
2195 uint64_t size = memory_region_size(mr);
2196 uint64_t addr;
2197
2198 if (size % SPAPR_MEMORY_BLOCK_SIZE) {
2199 error_setg(&local_err, "Hotplugged memory size must be a multiple of "
2200 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE/M_BYTE);
2201 goto out;
2202 }
2203
d6a9b0b8 2204 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err);
c20d332a
BR		 2205 if (local_err) {
2206 goto out;
2207 }
2208
2209 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err);
2210 if (local_err) {
2211 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr);
2212 goto out;
2213 }
2214
2215 spapr_add_lmbs(dev, addr, size, node, &error_abort);
2216
2217out:
2218 error_propagate(errp, local_err);
2219}
2220
2221static void spapr_machine_device_plug(HotplugHandler *hotplug_dev,
2222 DeviceState *dev, Error **errp)
2223{
2224 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine());
2225
2226 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
b556854b 2227 int node;
c20d332a
BR		 2228
2229 if (!smc->dr_lmb_enabled) {
2230 error_setg(errp, "Memory hotplug not supported for this machine");
2231 return;
2232 }
2233 node = object_property_get_int(OBJECT(dev), PC_DIMM_NODE_PROP, errp);
2234 if (*errp) {
2235 return;
2236 }
1a5512bb
GA		 2237 if (node < 0 || node >= MAX_NODES) {
2238 error_setg(errp, "Invaild node %d", node);
2239 return;
2240 }
c20d332a 2241
b556854b
BR		 2242 /*
2243 * Currently PowerPC kernel doesn't allow hot-adding memory to
2244 * memory-less node, but instead will silently add the memory
2245 * to the first node that has some memory. This causes two
2246 * unexpected behaviours for the user.
2247 *
2248 * - Memory gets hotplugged to a different node than what the user
2249 * specified.
2250 * - Since pc-dimm subsystem in QEMU still thinks that memory belongs
2251 * to memory-less node, a reboot will set things accordingly
2252 * and the previously hotplugged memory now ends in the right node.
2253 * This appears as if some memory moved from one node to another.
2254 *
2255 * So until kernel starts supporting memory hotplug to memory-less
2256 * nodes, just prevent such attempts upfront in QEMU.
2257 */
2258 if (nb_numa_nodes && !numa_info[node].node_mem) {
2259 error_setg(errp, "Can't hotplug memory to memory-less node %d",
2260 node);
2261 return;
2262 }
2263
c20d332a
BR		 2264 spapr_memory_plug(hotplug_dev, dev, node, errp);
2265 }
2266}
2267
2268static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev,
2269 DeviceState *dev, Error **errp)
2270{
2271 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2272 error_setg(errp, "Memory hot unplug not supported by sPAPR");
2273 }
2274}
2275
2276static HotplugHandler *spapr_get_hotpug_handler(MachineState *machine,
2277 DeviceState *dev)
2278{
2279 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2280 return HOTPLUG_HANDLER(machine);
2281 }
2282 return NULL;
2283}
2284
20bb648d
DG		 2285static unsigned spapr_cpu_index_to_socket_id(unsigned cpu_index)
2286{
2287 /* Allocate to NUMA nodes on a "socket" basis (not that concept of
2288 * socket means much for the paravirtualized PAPR platform) */
2289 return cpu_index / smp_threads / smp_cores;
2290}
2291
29ee3247
AK		 2292static void spapr_machine_class_init(ObjectClass *oc, void *data)
2293{
2294 MachineClass *mc = MACHINE_CLASS(oc);
224245bf 2295 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc);
71461b0f 2296 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
34316482 2297 NMIClass *nc = NMI_CLASS(oc);
c20d332a 2298 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
958db90c 2299
0eb9054c 2300 mc->desc = "pSeries Logical Partition (PAPR compliant)";
fc9f38c3
DG		 2301
2302 /*
2303 * We set up the default / latest behaviour here. The class_init
2304 * functions for the specific versioned machine types can override
2305 * these details for backwards compatibility
2306 */
958db90c
MA		 2307 mc->init = ppc_spapr_init;
2308 mc->reset = ppc_spapr_reset;
2309 mc->block_default_type = IF_SCSI;
38b02bd8 2310 mc->max_cpus = MAX_CPUMASK_BITS;
958db90c 2311 mc->no_parallel = 1;
5b2128d2 2312 mc->default_boot_order = "";
a34944fe 2313 mc->default_ram_size = 512 * M_BYTE;
958db90c 2314 mc->kvm_type = spapr_kvm_type;
9e3f9733 2315 mc->has_dynamic_sysbus = true;
e4024630 2316 mc->pci_allow_0_address = true;
c20d332a
BR		 2317 mc->get_hotplug_handler = spapr_get_hotpug_handler;
2318 hc->plug = spapr_machine_device_plug;
2319 hc->unplug = spapr_machine_device_unplug;
20bb648d 2320 mc->cpu_index_to_socket_id = spapr_cpu_index_to_socket_id;
00b4fbe2 2321
fc9f38c3 2322 smc->dr_lmb_enabled = true;
71461b0f 2323 fwc->get_dev_path = spapr_get_fw_dev_path;
34316482 2324 nc->nmi_monitor_handler = spapr_nmi;
29ee3247
AK		 2325}
2326
2327static const TypeInfo spapr_machine_info = {
2328 .name = TYPE_SPAPR_MACHINE,
2329 .parent = TYPE_MACHINE,
4aee7362 2330 .abstract = true,
6ca1502e 2331 .instance_size = sizeof(sPAPRMachineState),
23825581 2332 .instance_init = spapr_machine_initfn,
87bbdd9c 2333 .instance_finalize = spapr_machine_finalizefn,
183930c0 2334 .class_size = sizeof(sPAPRMachineClass),
29ee3247 2335 .class_init = spapr_machine_class_init,
71461b0f
AK		 2336 .interfaces = (InterfaceInfo[]) {
2337 { TYPE_FW_PATH_PROVIDER },
34316482 2338 { TYPE_NMI },
c20d332a 2339 { TYPE_HOTPLUG_HANDLER },
71461b0f
AK		 2340 { }
2341 },
29ee3247
AK		 2342};
2343
fccbc785 2344#define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \
5013c547
DG		 2345 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \
2346 void *data) \
2347 { \
2348 MachineClass *mc = MACHINE_CLASS(oc); \
2349 spapr_machine_##suffix##_class_options(mc); \
fccbc785
DG		 2350 if (latest) { \
2351 mc->alias = "pseries"; \
2352 mc->is_default = 1; \
2353 } \
5013c547
DG		 2354 } \
2355 static void spapr_machine_##suffix##_instance_init(Object *obj) \
2356 { \
2357 MachineState *machine = MACHINE(obj); \
2358 spapr_machine_##suffix##_instance_options(machine); \
2359 } \
2360 static const TypeInfo spapr_machine_##suffix##_info = { \
2361 .name = MACHINE_TYPE_NAME("pseries-" verstr), \
2362 .parent = TYPE_SPAPR_MACHINE, \
2363 .class_init = spapr_machine_##suffix##_class_init, \
2364 .instance_init = spapr_machine_##suffix##_instance_init, \
2365 }; \
2366 static void spapr_machine_register_##suffix(void) \
2367 { \
2368 type_register(&spapr_machine_##suffix##_info); \
2369 } \
0e6aac87 2370 type_init(spapr_machine_register_##suffix)
5013c547 2371
1ea1eefc
BR		 2372/*
2373 * pseries-2.7
2374 */
2375static void spapr_machine_2_7_instance_options(MachineState *machine)
2376{
2377}
2378
2379static void spapr_machine_2_7_class_options(MachineClass *mc)
2380{
2381 /* Defaults for the latest behaviour inherited from the base class */
2382}
2383
2384DEFINE_SPAPR_MACHINE(2_7, "2.7", true);
2385
4b23699c
DG		 2386/*
2387 * pseries-2.6
2388 */
1ea1eefc
BR		 2389#define SPAPR_COMPAT_2_6 \
2390 HW_COMPAT_2_6
2391
4b23699c
DG		 2392static void spapr_machine_2_6_instance_options(MachineState *machine)
2393{
2394}
2395
2396static void spapr_machine_2_6_class_options(MachineClass *mc)
2397{
1ea1eefc
BR		 2398 spapr_machine_2_7_class_options(mc);
2399 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6);
4b23699c
DG		 2400}
2401
1ea1eefc 2402DEFINE_SPAPR_MACHINE(2_6, "2.6", false);
4b23699c 2403
1c5f29bb
DG		 2404/*
2405 * pseries-2.5
2406 */
4b23699c 2407#define SPAPR_COMPAT_2_5 \
57c522f4
TH		 2408 HW_COMPAT_2_5 \
2409 { \
2410 .driver = "spapr-vlan", \
2411 .property = "use-rx-buffer-pools", \
2412 .value = "off", \
2413 },
4b23699c 2414
5013c547 2415static void spapr_machine_2_5_instance_options(MachineState *machine)
1c5f29bb 2416{
5013c547
DG		 2417}
2418
2419static void spapr_machine_2_5_class_options(MachineClass *mc)
2420{
57040d45
TH		 2421 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
2422
4b23699c 2423 spapr_machine_2_6_class_options(mc);
57040d45 2424 smc->use_ohci_by_default = true;
4b23699c 2425 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5);
1c5f29bb
DG		 2426}
2427
4b23699c 2428DEFINE_SPAPR_MACHINE(2_5, "2.5", false);
1c5f29bb
DG		 2429
2430/*
2431 * pseries-2.4
2432 */
80fd50f9
CH		 2433#define SPAPR_COMPAT_2_4 \
2434 HW_COMPAT_2_4
2435
5013c547 2436static void spapr_machine_2_4_instance_options(MachineState *machine)
1c5f29bb 2437{
5013c547
DG		 2438 spapr_machine_2_5_instance_options(machine);
2439}
1c5f29bb 2440
5013c547
DG		 2441static void spapr_machine_2_4_class_options(MachineClass *mc)
2442{
fc9f38c3
DG		 2443 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
2444
2445 spapr_machine_2_5_class_options(mc);
fc9f38c3 2446 smc->dr_lmb_enabled = false;
f949b4e5 2447 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4);
1c5f29bb
DG		 2448}
2449
fccbc785 2450DEFINE_SPAPR_MACHINE(2_4, "2.4", false);
1c5f29bb
DG		 2451
2452/*
2453 * pseries-2.3
2454 */
38ff32c6 2455#define SPAPR_COMPAT_2_3 \
7619c7b0
MR		 2456 HW_COMPAT_2_3 \
2457 {\
2458 .driver = "spapr-pci-host-bridge",\
2459 .property = "dynamic-reconfiguration",\
2460 .value = "off",\
2461 },
38ff32c6 2462
5013c547 2463static void spapr_machine_2_3_instance_options(MachineState *machine)
d25228e7 2464{
5013c547 2465 spapr_machine_2_4_instance_options(machine);
ff14e817 2466 savevm_skip_section_footers();
13d16814 2467 global_state_set_optional();
09b5e30d 2468 savevm_skip_configuration();
d25228e7
JW		 2469}
2470
5013c547 2471static void spapr_machine_2_3_class_options(MachineClass *mc)
6026db45 2472{
fc9f38c3 2473 spapr_machine_2_4_class_options(mc);
f949b4e5 2474 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3);
6026db45 2475}
fccbc785 2476DEFINE_SPAPR_MACHINE(2_3, "2.3", false);
6026db45 2477
1c5f29bb
DG		 2478/*
2479 * pseries-2.2
2480 */
2481
2482#define SPAPR_COMPAT_2_2 \
1c5f29bb
DG		 2483 HW_COMPAT_2_2 \
2484 {\
2485 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
2486 .property = "mem_win_size",\
2487 .value = "0x20000000",\
2488 },
2489
5013c547 2490static void spapr_machine_2_2_instance_options(MachineState *machine)
1c5f29bb 2491{
5013c547 2492 spapr_machine_2_3_instance_options(machine);
cba0e779 2493 machine->suppress_vmdesc = true;
1c5f29bb
DG		 2494}
2495
5013c547 2496static void spapr_machine_2_2_class_options(MachineClass *mc)
4aee7362 2497{
fc9f38c3 2498 spapr_machine_2_3_class_options(mc);
f949b4e5 2499 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2);
4aee7362 2500}
fccbc785 2501DEFINE_SPAPR_MACHINE(2_2, "2.2", false);
4aee7362 2502
1c5f29bb
DG		 2503/*
2504 * pseries-2.1
2505 */
2506#define SPAPR_COMPAT_2_1 \
1c5f29bb 2507 HW_COMPAT_2_1
3dab0244 2508
5013c547 2509static void spapr_machine_2_1_instance_options(MachineState *machine)
1c5f29bb 2510{
5013c547 2511 spapr_machine_2_2_instance_options(machine);
1c5f29bb 2512}
d25228e7 2513
5013c547 2514static void spapr_machine_2_1_class_options(MachineClass *mc)
d25228e7 2515{
fc9f38c3 2516 spapr_machine_2_2_class_options(mc);
f949b4e5 2517 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1);
d25228e7 2518}
fccbc785 2519DEFINE_SPAPR_MACHINE(2_1, "2.1", false);
fb0fc8f6 2520
29ee3247 2521static void spapr_machine_register_types(void)
9fdf0c29 2522{
29ee3247 2523 type_register_static(&spapr_machine_info);
9fdf0c29
DG		 2524}
2525
29ee3247 2526type_init(spapr_machine_register_types)
Empty description
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