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spapr: Move spapr_cpu_init() to spapr_cpu_core.c
[qemu.git] / hw / ppc / spapr.c
CommitLineData
9fdf0c29
DG		 1/*
2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
3 *
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 *
26 */
0d75590d 27#include "qemu/osdep.h"
da34e65c 28#include "qapi/error.h"
9c17d615 29#include "sysemu/sysemu.h"
e35704ba 30#include "sysemu/numa.h"
83c9f4ca 31#include "hw/hw.h"
03dd024f 32#include "qemu/log.h"
71461b0f 33#include "hw/fw-path-provider.h"
9fdf0c29 34#include "elf.h"
1422e32d 35#include "net/net.h"
ad440b4a 36#include "sysemu/device_tree.h"
fa1d36df 37#include "sysemu/block-backend.h"
9c17d615
PB		 38#include "sysemu/cpus.h"
39#include "sysemu/kvm.h"
c20d332a 40#include "sysemu/device_tree.h"
e97c3636 41#include "kvm_ppc.h"
ff14e817 42#include "migration/migration.h"
4be21d56 43#include "mmu-hash64.h"
3794d548 44#include "qom/cpu.h"
9fdf0c29
DG		 45
46#include "hw/boards.h"
0d09e41a 47#include "hw/ppc/ppc.h"
9fdf0c29
DG		 48#include "hw/loader.h"
49
0d09e41a
PB		 50#include "hw/ppc/spapr.h"
51#include "hw/ppc/spapr_vio.h"
52#include "hw/pci-host/spapr.h"
53#include "hw/ppc/xics.h"
a2cb15b0 54#include "hw/pci/msi.h"
9fdf0c29 55
83c9f4ca 56#include "hw/pci/pci.h"
71461b0f
AK		 57#include "hw/scsi/scsi.h"
58#include "hw/virtio/virtio-scsi.h"
f61b4bed 59
022c62cb 60#include "exec/address-spaces.h"
35139a59 61#include "hw/usb.h"
1de7afc9 62#include "qemu/config-file.h"
135a129a 63#include "qemu/error-report.h"
2a6593cb 64#include "trace.h"
34316482 65#include "hw/nmi.h"
890c2b77 66
68a27b20 67#include "hw/compat.h"
f348b6d1 68#include "qemu/cutils.h"
68a27b20 69
9fdf0c29
DG		 70#include <libfdt.h>
71
4d8d5467
BH		 72/* SLOF memory layout:
73 *
74 * SLOF raw image loaded at 0, copies its romfs right below the flat
75 * device-tree, then position SLOF itself 31M below that
76 *
77 * So we set FW_OVERHEAD to 40MB which should account for all of that
78 * and more
79 *
80 * We load our kernel at 4M, leaving space for SLOF initial image
81 */
38b02bd8 82#define FDT_MAX_SIZE 0x100000
39ac8455 83#define RTAS_MAX_SIZE 0x10000
b7d1f77a 84#define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */
a9f8ad8f
DG		 85#define FW_MAX_SIZE 0x400000
86#define FW_FILE_NAME "slof.bin"
4d8d5467
BH		 87#define FW_OVERHEAD 0x2800000
88#define KERNEL_LOAD_ADDR FW_MAX_SIZE
a9f8ad8f 89
4d8d5467 90#define MIN_RMA_SLOF 128UL
9fdf0c29 91
0c103f8e
DG		 92#define PHANDLE_XICP 0x00001111
93
7f763a5d
DG		 94#define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift))
95
c04d6cfa 96static XICSState *try_create_xics(const char *type, int nr_servers,
34f2af3d 97 int nr_irqs, Error **errp)
c04d6cfa 98{
34f2af3d 99 Error *err = NULL;
c04d6cfa
AL		 100 DeviceState *dev;
101
102 dev = qdev_create(NULL, type);
103 qdev_prop_set_uint32(dev, "nr_servers", nr_servers);
104 qdev_prop_set_uint32(dev, "nr_irqs", nr_irqs);
34f2af3d
MA		 105 object_property_set_bool(OBJECT(dev), true, "realized", &err);
106 if (err) {
107 error_propagate(errp, err);
108 object_unparent(OBJECT(dev));
c04d6cfa
AL		 109 return NULL;
110 }
5a3d7b23 111 return XICS_COMMON(dev);
c04d6cfa
AL		 112}
113
446f16a6 114static XICSState *xics_system_init(MachineState *machine,
1e49182d 115 int nr_servers, int nr_irqs, Error **errp)
c04d6cfa
AL		 116{
117 XICSState *icp = NULL;
118
11ad93f6 119 if (kvm_enabled()) {
34f2af3d
MA		 120 Error *err = NULL;
121
446f16a6 122 if (machine_kernel_irqchip_allowed(machine)) {
34f2af3d 123 icp = try_create_xics(TYPE_KVM_XICS, nr_servers, nr_irqs, &err);
11ad93f6 124 }
446f16a6 125 if (machine_kernel_irqchip_required(machine) && !icp) {
b83baa60
MA		 126 error_reportf_err(err,
127 "kernel_irqchip requested but unavailable: ");
128 } else {
129 error_free(err);
11ad93f6
DG		 130 }
131 }
132
133 if (!icp) {
1e49182d 134 icp = try_create_xics(TYPE_XICS, nr_servers, nr_irqs, errp);
c04d6cfa
AL		 135 }
136
137 return icp;
138}
139
833d4668
AK		 140static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
141 int smt_threads)
142{
143 int i, ret = 0;
144 uint32_t servers_prop[smt_threads];
145 uint32_t gservers_prop[smt_threads * 2];
146 int index = ppc_get_vcpu_dt_id(cpu);
147
6d9412ea 148 if (cpu->cpu_version) {
4bce526e 149 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->cpu_version);
6d9412ea
AK		 150 if (ret < 0) {
151 return ret;
152 }
153 }
154
833d4668
AK		 155 /* Build interrupt servers and gservers properties */
156 for (i = 0; i < smt_threads; i++) {
157 servers_prop[i] = cpu_to_be32(index + i);
158 /* Hack, direct the group queues back to cpu 0 */
159 gservers_prop[i*2] = cpu_to_be32(index + i);
160 gservers_prop[i*2 + 1] = 0;
161 }
162 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
163 servers_prop, sizeof(servers_prop));
164 if (ret < 0) {
165 return ret;
166 }
167 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s",
168 gservers_prop, sizeof(gservers_prop));
169
170 return ret;
171}
172
0da6f3fe
BR		 173static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, CPUState *cs)
174{
175 int ret = 0;
176 PowerPCCPU *cpu = POWERPC_CPU(cs);
177 int index = ppc_get_vcpu_dt_id(cpu);
178 uint32_t associativity[] = {cpu_to_be32(0x5),
179 cpu_to_be32(0x0),
180 cpu_to_be32(0x0),
181 cpu_to_be32(0x0),
182 cpu_to_be32(cs->numa_node),
183 cpu_to_be32(index)};
184
185 /* Advertise NUMA via ibm,associativity */
186 if (nb_numa_nodes > 1) {
187 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity,
188 sizeof(associativity));
189 }
190
191 return ret;
192}
193
28e02042 194static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr)
6e806cc3 195{
82677ed2
AK		 196 int ret = 0, offset, cpus_offset;
197 CPUState *cs;
6e806cc3
BR		 198 char cpu_model[32];
199 int smt = kvmppc_smt_threads();
7f763a5d 200 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
6e806cc3 201
82677ed2
AK		 202 CPU_FOREACH(cs) {
203 PowerPCCPU *cpu = POWERPC_CPU(cs);
204 DeviceClass *dc = DEVICE_GET_CLASS(cs);
205 int index = ppc_get_vcpu_dt_id(cpu);
6e806cc3 206
0f20ba62 207 if ((index % smt) != 0) {
6e806cc3
BR		 208 continue;
209 }
210
82677ed2 211 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index);
6e806cc3 212
82677ed2
AK		 213 cpus_offset = fdt_path_offset(fdt, "/cpus");
214 if (cpus_offset < 0) {
215 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"),
216 "cpus");
217 if (cpus_offset < 0) {
218 return cpus_offset;
219 }
220 }
221 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model);
6e806cc3 222 if (offset < 0) {
82677ed2
AK		 223 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model);
224 if (offset < 0) {
225 return offset;
226 }
6e806cc3
BR		 227 }
228
7f763a5d
DG		 229 ret = fdt_setprop(fdt, offset, "ibm,pft-size",
230 pft_size_prop, sizeof(pft_size_prop));
6e806cc3
BR		 231 if (ret < 0) {
232 return ret;
233 }
833d4668 234
0da6f3fe
BR		 235 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cs);
236 if (ret < 0) {
237 return ret;
238 }
239
82677ed2 240 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu,
2a48d993 241 ppc_get_compat_smt_threads(cpu));
833d4668
AK		 242 if (ret < 0) {
243 return ret;
244 }
6e806cc3
BR		 245 }
246 return ret;
247}
248
5af9873d
BH		 249
250static size_t create_page_sizes_prop(CPUPPCState *env, uint32_t *prop,
251 size_t maxsize)
252{
253 size_t maxcells = maxsize / sizeof(uint32_t);
254 int i, j, count;
255 uint32_t *p = prop;
256
257 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
258 struct ppc_one_seg_page_size *sps = &env->sps.sps[i];
259
260 if (!sps->page_shift) {
261 break;
262 }
263 for (count = 0; count < PPC_PAGE_SIZES_MAX_SZ; count++) {
264 if (sps->enc[count].page_shift == 0) {
265 break;
266 }
267 }
268 if ((p - prop) >= (maxcells - 3 - count * 2)) {
269 break;
270 }
271 *(p++) = cpu_to_be32(sps->page_shift);
272 *(p++) = cpu_to_be32(sps->slb_enc);
273 *(p++) = cpu_to_be32(count);
274 for (j = 0; j < count; j++) {
275 *(p++) = cpu_to_be32(sps->enc[j].page_shift);
276 *(p++) = cpu_to_be32(sps->enc[j].pte_enc);
277 }
278 }
279
280 return (p - prop) * sizeof(uint32_t);
281}
282
b082d65a
AK		 283static hwaddr spapr_node0_size(void)
284{
fb164994
DG		 285 MachineState *machine = MACHINE(qdev_get_machine());
286
b082d65a
AK		 287 if (nb_numa_nodes) {
288 int i;
289 for (i = 0; i < nb_numa_nodes; ++i) {
290 if (numa_info[i].node_mem) {
fb164994
DG		 291 return MIN(pow2floor(numa_info[i].node_mem),
292 machine->ram_size);
b082d65a
AK		 293 }
294 }
295 }
fb164994 296 return machine->ram_size;
b082d65a
AK		 297}
298
7f763a5d
DG		 299#define _FDT(exp) \
300 do { \
301 int ret = (exp); \
302 if (ret < 0) { \
303 fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \
304 #exp, fdt_strerror(ret)); \
305 exit(1); \
306 } \
307 } while (0)
308
a1d59c0f
AK		 309static void add_str(GString *s, const gchar *s1)
310{
311 g_string_append_len(s, s1, strlen(s1) + 1);
312}
7f763a5d 313
3bbf37f2 314static void *spapr_create_fdt_skel(hwaddr initrd_base,
a8170e5e
AK		 315 hwaddr initrd_size,
316 hwaddr kernel_size,
16457e7f 317 bool little_endian,
74d042e5
DG		 318 const char *kernel_cmdline,
319 uint32_t epow_irq)
9fdf0c29
DG		 320{
321 void *fdt;
9fdf0c29
DG		 322 uint32_t start_prop = cpu_to_be32(initrd_base);
323 uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size);
a1d59c0f
AK		 324 GString *hypertas = g_string_sized_new(256);
325 GString *qemu_hypertas = g_string_sized_new(256);
7f763a5d 326 uint32_t refpoints[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)};
9e734e3d 327 uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(max_cpus)};
6e806cc3 328 unsigned char vec5[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80};
ef951443 329 char *buf;
9fdf0c29 330
a1d59c0f
AK		 331 add_str(hypertas, "hcall-pft");
332 add_str(hypertas, "hcall-term");
333 add_str(hypertas, "hcall-dabr");
334 add_str(hypertas, "hcall-interrupt");
335 add_str(hypertas, "hcall-tce");
336 add_str(hypertas, "hcall-vio");
337 add_str(hypertas, "hcall-splpar");
338 add_str(hypertas, "hcall-bulk");
339 add_str(hypertas, "hcall-set-mode");
340 add_str(qemu_hypertas, "hcall-memop1");
341
7267c094 342 fdt = g_malloc0(FDT_MAX_SIZE);
9fdf0c29
DG		 343 _FDT((fdt_create(fdt, FDT_MAX_SIZE)));
344
4d8d5467
BH		 345 if (kernel_size) {
346 _FDT((fdt_add_reservemap_entry(fdt, KERNEL_LOAD_ADDR, kernel_size)));
347 }
348 if (initrd_size) {
349 _FDT((fdt_add_reservemap_entry(fdt, initrd_base, initrd_size)));
350 }
9fdf0c29
DG		 351 _FDT((fdt_finish_reservemap(fdt)));
352
353 /* Root node */
354 _FDT((fdt_begin_node(fdt, "")));
355 _FDT((fdt_property_string(fdt, "device_type", "chrp")));
5d73dd66 356 _FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)")));
d63919c9 357 _FDT((fdt_property_string(fdt, "compatible", "qemu,pseries")));
9fdf0c29 358
ef951443
ND		 359 /*
360 * Add info to guest to indentify which host is it being run on
361 * and what is the uuid of the guest
362 */
363 if (kvmppc_get_host_model(&buf)) {
364 _FDT((fdt_property_string(fdt, "host-model", buf)));
365 g_free(buf);
366 }
367 if (kvmppc_get_host_serial(&buf)) {
368 _FDT((fdt_property_string(fdt, "host-serial", buf)));
369 g_free(buf);
370 }
371
372 buf = g_strdup_printf(UUID_FMT, qemu_uuid[0], qemu_uuid[1],
373 qemu_uuid[2], qemu_uuid[3], qemu_uuid[4],
374 qemu_uuid[5], qemu_uuid[6], qemu_uuid[7],
375 qemu_uuid[8], qemu_uuid[9], qemu_uuid[10],
376 qemu_uuid[11], qemu_uuid[12], qemu_uuid[13],
377 qemu_uuid[14], qemu_uuid[15]);
378
379 _FDT((fdt_property_string(fdt, "vm,uuid", buf)));
3dc0a66d
AK		 380 if (qemu_uuid_set) {
381 _FDT((fdt_property_string(fdt, "system-id", buf)));
382 }
ef951443
ND		 383 g_free(buf);
384
2c1aaa81
SB		 385 if (qemu_get_vm_name()) {
386 _FDT((fdt_property_string(fdt, "ibm,partition-name",
387 qemu_get_vm_name())));
388 }
389
9fdf0c29
DG		 390 _FDT((fdt_property_cell(fdt, "#address-cells", 0x2)));
391 _FDT((fdt_property_cell(fdt, "#size-cells", 0x2)));
392
393 /* /chosen */
394 _FDT((fdt_begin_node(fdt, "chosen")));
395
6e806cc3
BR		 396 /* Set Form1_affinity */
397 _FDT((fdt_property(fdt, "ibm,architecture-vec-5", vec5, sizeof(vec5))));
398
9fdf0c29
DG		 399 _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline)));
400 _FDT((fdt_property(fdt, "linux,initrd-start",
401 &start_prop, sizeof(start_prop))));
402 _FDT((fdt_property(fdt, "linux,initrd-end",
403 &end_prop, sizeof(end_prop))));
4d8d5467
BH		 404 if (kernel_size) {
405 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR),
406 cpu_to_be64(kernel_size) };
9fdf0c29 407
4d8d5467 408 _FDT((fdt_property(fdt, "qemu,boot-kernel", &kprop, sizeof(kprop))));
16457e7f
BH		 409 if (little_endian) {
410 _FDT((fdt_property(fdt, "qemu,boot-kernel-le", NULL, 0)));
411 }
4d8d5467 412 }
cc84c0f3
AS		 413 if (boot_menu) {
414 _FDT((fdt_property_cell(fdt, "qemu,boot-menu", boot_menu)));
415 }
f28359d8
LZ		 416 _FDT((fdt_property_cell(fdt, "qemu,graphic-width", graphic_width)));
417 _FDT((fdt_property_cell(fdt, "qemu,graphic-height", graphic_height)));
418 _FDT((fdt_property_cell(fdt, "qemu,graphic-depth", graphic_depth)));
3384f95c 419
9fdf0c29
DG		 420 _FDT((fdt_end_node(fdt)));
421
f43e3525
DG		 422 /* RTAS */
423 _FDT((fdt_begin_node(fdt, "rtas")));
424
da95324e
AK		 425 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
426 add_str(hypertas, "hcall-multi-tce");
427 }
a1d59c0f
AK		 428 _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas->str,
429 hypertas->len)));
430 g_string_free(hypertas, TRUE);
431 _FDT((fdt_property(fdt, "qemu,hypertas-functions", qemu_hypertas->str,
432 qemu_hypertas->len)));
433 g_string_free(qemu_hypertas, TRUE);
f43e3525 434
6e806cc3
BR		 435 _FDT((fdt_property(fdt, "ibm,associativity-reference-points",
436 refpoints, sizeof(refpoints))));
437
74d042e5 438 _FDT((fdt_property_cell(fdt, "rtas-error-log-max", RTAS_ERROR_LOG_MAX)));
79853e18
TD		 439 _FDT((fdt_property_cell(fdt, "rtas-event-scan-rate",
440 RTAS_EVENT_SCAN_RATE)));
74d042e5 441
226419d6 442 if (msi_nonbroken) {
a95f9922
SB		 443 _FDT((fdt_property(fdt, "ibm,change-msix-capable", NULL, 0)));
444 }
445
2e14072f 446 /*
9d632f5f 447 * According to PAPR, rtas ibm,os-term does not guarantee a return
2e14072f
ND		 448 * back to the guest cpu.
449 *
450 * While an additional ibm,extended-os-term property indicates that
451 * rtas call return will always occur. Set this property.
452 */
453 _FDT((fdt_property(fdt, "ibm,extended-os-term", NULL, 0)));
454
f43e3525
DG		 455 _FDT((fdt_end_node(fdt)));
456
b5cec4c5 457 /* interrupt controller */
9dfef5aa 458 _FDT((fdt_begin_node(fdt, "interrupt-controller")));
b5cec4c5
DG		 459
460 _FDT((fdt_property_string(fdt, "device_type",
461 "PowerPC-External-Interrupt-Presentation")));
462 _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp")));
b5cec4c5
DG		 463 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));
464 _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges",
465 interrupt_server_ranges_prop,
466 sizeof(interrupt_server_ranges_prop))));
0c103f8e
DG		 467 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 2)));
468 _FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP)));
469 _FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP)));
b5cec4c5
DG		 470
471 _FDT((fdt_end_node(fdt)));
472
4040ab72
DG		 473 /* vdevice */
474 _FDT((fdt_begin_node(fdt, "vdevice")));
475
476 _FDT((fdt_property_string(fdt, "device_type", "vdevice")));
477 _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice")));
478 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1)));
479 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0)));
b5cec4c5
DG		 480 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2)));
481 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));
4040ab72
DG		 482
483 _FDT((fdt_end_node(fdt)));
484
74d042e5
DG		 485 /* event-sources */
486 spapr_events_fdt_skel(fdt, epow_irq);
487
f7d69146
AG		 488 /* /hypervisor node */
489 if (kvm_enabled()) {
490 uint8_t hypercall[16];
491
492 /* indicate KVM hypercall interface */
493 _FDT((fdt_begin_node(fdt, "hypervisor")));
494 _FDT((fdt_property_string(fdt, "compatible", "linux,kvm")));
495 if (kvmppc_has_cap_fixup_hcalls()) {
496 /*
497 * Older KVM versions with older guest kernels were broken with the
498 * magic page, don't allow the guest to map it.
499 */
0ddbd053
AK		 500 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall,
501 sizeof(hypercall))) {
502 _FDT((fdt_property(fdt, "hcall-instructions", hypercall,
503 sizeof(hypercall))));
504 }
f7d69146
AG		 505 }
506 _FDT((fdt_end_node(fdt)));
507 }
508
9fdf0c29
DG		 509 _FDT((fdt_end_node(fdt))); /* close root node */
510 _FDT((fdt_finish(fdt)));
511
a3467baa
DG		 512 return fdt;
513}
514
03d196b7 515static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start,
26a8c353
AK		 516 hwaddr size)
517{
518 uint32_t associativity[] = {
519 cpu_to_be32(0x4), /* length */
520 cpu_to_be32(0x0), cpu_to_be32(0x0),
c3b4f589 521 cpu_to_be32(0x0), cpu_to_be32(nodeid)
26a8c353
AK		 522 };
523 char mem_name[32];
524 uint64_t mem_reg_property[2];
525 int off;
526
527 mem_reg_property[0] = cpu_to_be64(start);
528 mem_reg_property[1] = cpu_to_be64(size);
529
530 sprintf(mem_name, "memory@" TARGET_FMT_lx, start);
531 off = fdt_add_subnode(fdt, 0, mem_name);
532 _FDT(off);
533 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
534 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
535 sizeof(mem_reg_property))));
536 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,
537 sizeof(associativity))));
03d196b7 538 return off;
26a8c353
AK		 539}
540
28e02042 541static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt)
7f763a5d 542{
fb164994 543 MachineState *machine = MACHINE(spapr);
7db8a127
AK		 544 hwaddr mem_start, node_size;
545 int i, nb_nodes = nb_numa_nodes;
546 NodeInfo *nodes = numa_info;
547 NodeInfo ramnode;
548
549 /* No NUMA nodes, assume there is just one node with whole RAM */
550 if (!nb_numa_nodes) {
551 nb_nodes = 1;
fb164994 552 ramnode.node_mem = machine->ram_size;
7db8a127 553 nodes = &ramnode;
5fe269b1 554 }
7f763a5d 555
7db8a127
AK		 556 for (i = 0, mem_start = 0; i < nb_nodes; ++i) {
557 if (!nodes[i].node_mem) {
558 continue;
559 }
fb164994 560 if (mem_start >= machine->ram_size) {
5fe269b1
PM		 561 node_size = 0;
562 } else {
7db8a127 563 node_size = nodes[i].node_mem;
fb164994
DG		 564 if (node_size > machine->ram_size - mem_start) {
565 node_size = machine->ram_size - mem_start;
5fe269b1
PM		 566 }
567 }
7db8a127
AK		 568 if (!mem_start) {
569 /* ppc_spapr_init() checks for rma_size <= node0_size already */
e8f986fc 570 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size);
7db8a127
AK		 571 mem_start += spapr->rma_size;
572 node_size -= spapr->rma_size;
573 }
6010818c
AK		 574 for ( ; node_size; ) {
575 hwaddr sizetmp = pow2floor(node_size);
576
577 /* mem_start != 0 here */
578 if (ctzl(mem_start) < ctzl(sizetmp)) {
579 sizetmp = 1ULL << ctzl(mem_start);
580 }
581
582 spapr_populate_memory_node(fdt, i, mem_start, sizetmp);
583 node_size -= sizetmp;
584 mem_start += sizetmp;
585 }
7f763a5d
DG		 586 }
587
588 return 0;
589}
590
0da6f3fe
BR		 591static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
592 sPAPRMachineState *spapr)
593{
594 PowerPCCPU *cpu = POWERPC_CPU(cs);
595 CPUPPCState *env = &cpu->env;
596 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
597 int index = ppc_get_vcpu_dt_id(cpu);
598 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
599 0xffffffff, 0xffffffff};
afd10a0f
BR		 600 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq()
601 : SPAPR_TIMEBASE_FREQ;
0da6f3fe
BR		 602 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
603 uint32_t page_sizes_prop[64];
604 size_t page_sizes_prop_size;
22419c2a 605 uint32_t vcpus_per_socket = smp_threads * smp_cores;
0da6f3fe
BR		 606 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
607
90da0d5a
BH		 608 /* Note: we keep CI large pages off for now because a 64K capable guest
609 * provisioned with large pages might otherwise try to map a qemu
610 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages
611 * even if that qemu runs on a 4k host.
612 *
613 * We can later add this bit back when we are confident this is not
614 * an issue (!HV KVM or 64K host)
615 */
616 uint8_t pa_features_206[] = { 6, 0,
617 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
618 uint8_t pa_features_207[] = { 24, 0,
619 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
620 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
621 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
622 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
623 uint8_t *pa_features;
624 size_t pa_size;
625
0da6f3fe
BR		 626 _FDT((fdt_setprop_cell(fdt, offset, "reg", index)));
627 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
628
629 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
630 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
631 env->dcache_line_size)));
632 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
633 env->dcache_line_size)));
634 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
635 env->icache_line_size)));
636 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
637 env->icache_line_size)));
638
639 if (pcc->l1_dcache_size) {
640 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
641 pcc->l1_dcache_size)));
642 } else {
643 fprintf(stderr, "Warning: Unknown L1 dcache size for cpu\n");
644 }
645 if (pcc->l1_icache_size) {
646 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
647 pcc->l1_icache_size)));
648 } else {
649 fprintf(stderr, "Warning: Unknown L1 icache size for cpu\n");
650 }
651
652 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
653 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
fd5da5c4 654 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr)));
0da6f3fe
BR		 655 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr)));
656 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
657 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
658
659 if (env->spr_cb[SPR_PURR].oea_read) {
660 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
661 }
662
663 if (env->mmu_model & POWERPC_MMU_1TSEG) {
664 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
665 segs, sizeof(segs))));
666 }
667
668 /* Advertise VMX/VSX (vector extensions) if available
669 * 0 / no property == no vector extensions
670 * 1 == VMX / Altivec available
671 * 2 == VSX available */
672 if (env->insns_flags & PPC_ALTIVEC) {
673 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
674
675 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
676 }
677
678 /* Advertise DFP (Decimal Floating Point) if available
679 * 0 / no property == no DFP
680 * 1 == DFP available */
681 if (env->insns_flags2 & PPC2_DFP) {
682 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
683 }
684
685 page_sizes_prop_size = create_page_sizes_prop(env, page_sizes_prop,
686 sizeof(page_sizes_prop));
687 if (page_sizes_prop_size) {
688 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
689 page_sizes_prop, page_sizes_prop_size)));
690 }
691
90da0d5a
BH		 692 /* Do the ibm,pa-features property, adjust it for ci-large-pages */
693 if (env->mmu_model == POWERPC_MMU_2_06) {
694 pa_features = pa_features_206;
695 pa_size = sizeof(pa_features_206);
696 } else /* env->mmu_model == POWERPC_MMU_2_07 */ {
697 pa_features = pa_features_207;
698 pa_size = sizeof(pa_features_207);
699 }
700 if (env->ci_large_pages) {
701 pa_features[3] |= 0x20;
702 }
703 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size)));
704
0da6f3fe 705 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id",
22419c2a 706 cs->cpu_index / vcpus_per_socket)));
0da6f3fe
BR		 707
708 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size",
709 pft_size_prop, sizeof(pft_size_prop))));
710
711 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cs));
712
713 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu,
714 ppc_get_compat_smt_threads(cpu)));
715}
716
717static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr)
718{
719 CPUState *cs;
720 int cpus_offset;
721 char *nodename;
722 int smt = kvmppc_smt_threads();
723
724 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
725 _FDT(cpus_offset);
726 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
727 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
728
729 /*
730 * We walk the CPUs in reverse order to ensure that CPU DT nodes
731 * created by fdt_add_subnode() end up in the right order in FDT
732 * for the guest kernel the enumerate the CPUs correctly.
733 */
734 CPU_FOREACH_REVERSE(cs) {
735 PowerPCCPU *cpu = POWERPC_CPU(cs);
736 int index = ppc_get_vcpu_dt_id(cpu);
737 DeviceClass *dc = DEVICE_GET_CLASS(cs);
738 int offset;
739
740 if ((index % smt) != 0) {
741 continue;
742 }
743
744 nodename = g_strdup_printf("%s@%x", dc->fw_name, index);
745 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
746 g_free(nodename);
747 _FDT(offset);
748 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
749 }
750
751}
752
03d196b7
BR		 753/*
754 * Adds ibm,dynamic-reconfiguration-memory node.
755 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation
756 * of this device tree node.
757 */
758static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt)
759{
760 MachineState *machine = MACHINE(spapr);
761 int ret, i, offset;
762 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
763 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)};
d0e5a8f2
BR		 764 uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size;
765 uint32_t nr_lmbs = (spapr->hotplug_memory.base +
766 memory_region_size(&spapr->hotplug_memory.mr)) /
767 lmb_size;
03d196b7 768 uint32_t *int_buf, *cur_index, buf_len;
6663864e 769 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1;
03d196b7 770
16c25aef 771 /*
d0e5a8f2 772 * Don't create the node if there is no hotpluggable memory
16c25aef 773 */
d0e5a8f2 774 if (machine->ram_size == machine->maxram_size) {
16c25aef
BR		 775 return 0;
776 }
777
ef001f06
TH		 778 /*
779 * Allocate enough buffer size to fit in ibm,dynamic-memory
780 * or ibm,associativity-lookup-arrays
781 */
782 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2)
783 * sizeof(uint32_t);
03d196b7
BR		 784 cur_index = int_buf = g_malloc0(buf_len);
785
786 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory");
787
788 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size,
789 sizeof(prop_lmb_size));
790 if (ret < 0) {
791 goto out;
792 }
793
794 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff);
795 if (ret < 0) {
796 goto out;
797 }
798
799 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0);
800 if (ret < 0) {
801 goto out;
802 }
803
804 /* ibm,dynamic-memory */
805 int_buf[0] = cpu_to_be32(nr_lmbs);
806 cur_index++;
807 for (i = 0; i < nr_lmbs; i++) {
d0e5a8f2 808 uint64_t addr = i * lmb_size;
03d196b7
BR		 809 uint32_t *dynamic_memory = cur_index;
810
d0e5a8f2
BR		 811 if (i >= hotplug_lmb_start) {
812 sPAPRDRConnector *drc;
813 sPAPRDRConnectorClass *drck;
814
815 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, i);
816 g_assert(drc);
817 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
818
819 dynamic_memory[0] = cpu_to_be32(addr >> 32);
820 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
821 dynamic_memory[2] = cpu_to_be32(drck->get_index(drc));
822 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
823 dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL));
824 if (memory_region_present(get_system_memory(), addr)) {
825 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED);
826 } else {
827 dynamic_memory[5] = cpu_to_be32(0);
828 }
03d196b7 829 } else {
d0e5a8f2
BR		 830 /*
831 * LMB information for RMA, boot time RAM and gap b/n RAM and
832 * hotplug memory region -- all these are marked as reserved
833 * and as having no valid DRC.
834 */
835 dynamic_memory[0] = cpu_to_be32(addr >> 32);
836 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
837 dynamic_memory[2] = cpu_to_be32(0);
838 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
839 dynamic_memory[4] = cpu_to_be32(-1);
840 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED |
841 SPAPR_LMB_FLAGS_DRC_INVALID);
03d196b7
BR		 842 }
843
844 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE;
845 }
846 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len);
847 if (ret < 0) {
848 goto out;
849 }
850
851 /* ibm,associativity-lookup-arrays */
852 cur_index = int_buf;
6663864e 853 int_buf[0] = cpu_to_be32(nr_nodes);
03d196b7
BR		 854 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */
855 cur_index += 2;
6663864e 856 for (i = 0; i < nr_nodes; i++) {
03d196b7
BR		 857 uint32_t associativity[] = {
858 cpu_to_be32(0x0),
859 cpu_to_be32(0x0),
860 cpu_to_be32(0x0),
861 cpu_to_be32(i)
862 };
863 memcpy(cur_index, associativity, sizeof(associativity));
864 cur_index += 4;
865 }
866 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf,
867 (cur_index - int_buf) * sizeof(uint32_t));
868out:
869 g_free(int_buf);
870 return ret;
871}
872
873int spapr_h_cas_compose_response(sPAPRMachineState *spapr,
874 target_ulong addr, target_ulong size,
875 bool cpu_update, bool memory_update)
876{
877 void *fdt, *fdt_skel;
878 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 };
879 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine());
880
881 size -= sizeof(hdr);
882
883 /* Create sceleton */
884 fdt_skel = g_malloc0(size);
885 _FDT((fdt_create(fdt_skel, size)));
886 _FDT((fdt_begin_node(fdt_skel, "")));
887 _FDT((fdt_end_node(fdt_skel)));
888 _FDT((fdt_finish(fdt_skel)));
889 fdt = g_malloc0(size);
890 _FDT((fdt_open_into(fdt_skel, fdt, size)));
891 g_free(fdt_skel);
892
893 /* Fixup cpu nodes */
894 if (cpu_update) {
895 _FDT((spapr_fixup_cpu_dt(fdt, spapr)));
896 }
897
16c25aef 898 /* Generate ibm,dynamic-reconfiguration-memory node if required */
03d196b7
BR		 899 if (memory_update && smc->dr_lmb_enabled) {
900 _FDT((spapr_populate_drconf_memory(spapr, fdt)));
03d196b7
BR		 901 }
902
903 /* Pack resulting tree */
904 _FDT((fdt_pack(fdt)));
905
906 if (fdt_totalsize(fdt) + sizeof(hdr) > size) {
907 trace_spapr_cas_failed(size);
908 return -1;
909 }
910
911 cpu_physical_memory_write(addr, &hdr, sizeof(hdr));
912 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt));
913 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr));
914 g_free(fdt);
915
916 return 0;
917}
918
28e02042 919static void spapr_finalize_fdt(sPAPRMachineState *spapr,
a8170e5e
AK		 920 hwaddr fdt_addr,
921 hwaddr rtas_addr,
922 hwaddr rtas_size)
a3467baa 923{
5b2128d2 924 MachineState *machine = MACHINE(qdev_get_machine());
c20d332a 925 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
5b2128d2 926 const char *boot_device = machine->boot_order;
71461b0f
AK		 927 int ret, i;
928 size_t cb = 0;
929 char *bootlist;
a3467baa 930 void *fdt;
3384f95c 931 sPAPRPHBState *phb;
a3467baa 932
7267c094 933 fdt = g_malloc(FDT_MAX_SIZE);
a3467baa
DG		 934
935 /* open out the base tree into a temp buffer for the final tweaks */
936 _FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE)));
4040ab72 937
e8f986fc
BR		 938 ret = spapr_populate_memory(spapr, fdt);
939 if (ret < 0) {
940 fprintf(stderr, "couldn't setup memory nodes in fdt\n");
941 exit(1);
7f763a5d
DG		 942 }
943
4040ab72
DG		 944 ret = spapr_populate_vdevice(spapr->vio_bus, fdt);
945 if (ret < 0) {
946 fprintf(stderr, "couldn't setup vio devices in fdt\n");
947 exit(1);
948 }
949
4d9392be
TH		 950 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) {
951 ret = spapr_rng_populate_dt(fdt);
952 if (ret < 0) {
953 fprintf(stderr, "could not set up rng device in the fdt\n");
954 exit(1);
955 }
956 }
957
3384f95c 958 QLIST_FOREACH(phb, &spapr->phbs, list) {
e0fdbd7c 959 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt);
da34fed7
TH		 960 if (ret < 0) {
961 error_report("couldn't setup PCI devices in fdt");
962 exit(1);
963 }
3384f95c
DG		 964 }
965
39ac8455
DG		 966 /* RTAS */
967 ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size);
968 if (ret < 0) {
969 fprintf(stderr, "Couldn't set up RTAS device tree properties\n");
970 }
971
0da6f3fe
BR		 972 /* cpus */
973 spapr_populate_cpus_dt_node(fdt, spapr);
6e806cc3 974
71461b0f
AK		 975 bootlist = get_boot_devices_list(&cb, true);
976 if (cb && bootlist) {
977 int offset = fdt_path_offset(fdt, "/chosen");
978 if (offset < 0) {
979 exit(1);
980 }
981 for (i = 0; i < cb; i++) {
982 if (bootlist[i] == '\n') {
983 bootlist[i] = ' ';
984 }
985
986 }
987 ret = fdt_setprop_string(fdt, offset, "qemu,boot-list", bootlist);
988 }
989
5b2128d2
AG		 990 if (boot_device && strlen(boot_device)) {
991 int offset = fdt_path_offset(fdt, "/chosen");
992
993 if (offset < 0) {
994 exit(1);
995 }
996 fdt_setprop_string(fdt, offset, "qemu,boot-device", boot_device);
997 }
998
3fc5acde 999 if (!spapr->has_graphics) {
f28359d8
LZ		 1000 spapr_populate_chosen_stdout(fdt, spapr->vio_bus);
1001 }
68f3a94c 1002
c20d332a
BR		 1003 if (smc->dr_lmb_enabled) {
1004 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB));
1005 }
1006
4040ab72
DG		 1007 _FDT((fdt_pack(fdt)));
1008
4d8d5467 1009 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) {
730fce59
TH		 1010 error_report("FDT too big ! 0x%x bytes (max is 0x%x)",
1011 fdt_totalsize(fdt), FDT_MAX_SIZE);
4d8d5467
BH		 1012 exit(1);
1013 }
1014
ad440b4a 1015 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
a3467baa 1016 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt));
9fdf0c29 1017
a21a7a70 1018 g_free(bootlist);
7267c094 1019 g_free(fdt);
9fdf0c29
DG		 1020}
1021
1022static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
1023{
1024 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
1025}
1026
1b14670a 1027static void emulate_spapr_hypercall(PowerPCCPU *cpu)
9fdf0c29 1028{
1b14670a
AF		 1029 CPUPPCState *env = &cpu->env;
1030
efcb9383
DG		 1031 if (msr_pr) {
1032 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1033 env->gpr[3] = H_PRIVILEGE;
1034 } else {
aa100fa4 1035 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]);
efcb9383 1036 }
9fdf0c29
DG		 1037}
1038
e6b8fd24
SMJ		 1039#define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1040#define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1041#define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1042#define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1043#define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1044
715c5407
DG		 1045/*
1046 * Get the fd to access the kernel htab, re-opening it if necessary
1047 */
1048static int get_htab_fd(sPAPRMachineState *spapr)
1049{
1050 if (spapr->htab_fd >= 0) {
1051 return spapr->htab_fd;
1052 }
1053
1054 spapr->htab_fd = kvmppc_get_htab_fd(false);
1055 if (spapr->htab_fd < 0) {
1056 error_report("Unable to open fd for reading hash table from KVM: %s",
1057 strerror(errno));
1058 }
1059
1060 return spapr->htab_fd;
1061}
1062
1063static void close_htab_fd(sPAPRMachineState *spapr)
1064{
1065 if (spapr->htab_fd >= 0) {
1066 close(spapr->htab_fd);
1067 }
1068 spapr->htab_fd = -1;
1069}
1070
8dfe8e7f
DG		 1071static int spapr_hpt_shift_for_ramsize(uint64_t ramsize)
1072{
1073 int shift;
1074
1075 /* We aim for a hash table of size 1/128 the size of RAM (rounded
1076 * up). The PAPR recommendation is actually 1/64 of RAM size, but
1077 * that's much more than is needed for Linux guests */
1078 shift = ctz64(pow2ceil(ramsize)) - 7;
1079 shift = MAX(shift, 18); /* Minimum architected size */
1080 shift = MIN(shift, 46); /* Maximum architected size */
1081 return shift;
1082}
1083
c5f54f3e
DG		 1084static void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift,
1085 Error **errp)
7f763a5d 1086{
c5f54f3e
DG		 1087 long rc;
1088
1089 /* Clean up any HPT info from a previous boot */
1090 g_free(spapr->htab);
1091 spapr->htab = NULL;
1092 spapr->htab_shift = 0;
1093 close_htab_fd(spapr);
1094
1095 rc = kvmppc_reset_htab(shift);
1096 if (rc < 0) {
1097 /* kernel-side HPT needed, but couldn't allocate one */
1098 error_setg_errno(errp, errno,
1099 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)",
1100 shift);
1101 /* This is almost certainly fatal, but if the caller really
1102 * wants to carry on with shift == 0, it's welcome to try */
1103 } else if (rc > 0) {
1104 /* kernel-side HPT allocated */
1105 if (rc != shift) {
1106 error_setg(errp,
1107 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)",
1108 shift, rc);
7735feda
BR		 1109 }
1110
7f763a5d 1111 spapr->htab_shift = shift;
c18ad9a5 1112 spapr->htab = NULL;
b817772a 1113 } else {
c5f54f3e
DG		 1114 /* kernel-side HPT not needed, allocate in userspace instead */
1115 size_t size = 1ULL << shift;
1116 int i;
b817772a 1117
c5f54f3e
DG		 1118 spapr->htab = qemu_memalign(size, size);
1119 if (!spapr->htab) {
1120 error_setg_errno(errp, errno,
1121 "Could not allocate HPT of order %d", shift);
1122 return;
7735feda
BR		 1123 }
1124
c5f54f3e
DG		 1125 memset(spapr->htab, 0, size);
1126 spapr->htab_shift = shift;
e6b8fd24 1127
c5f54f3e
DG		 1128 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) {
1129 DIRTY_HPTE(HPTE(spapr->htab, i));
e6b8fd24 1130 }
7f763a5d 1131 }
9fdf0c29
DG		 1132}
1133
9e3f9733
AG		 1134static int find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque)
1135{
1136 bool matched = false;
1137
1138 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
1139 matched = true;
1140 }
1141
1142 if (!matched) {
1143 error_report("Device %s is not supported by this machine yet.",
1144 qdev_fw_name(DEVICE(sbdev)));
1145 exit(1);
1146 }
1147
1148 return 0;
1149}
1150
c8787ad4 1151static void ppc_spapr_reset(void)
a3467baa 1152{
c5f54f3e
DG		 1153 MachineState *machine = MACHINE(qdev_get_machine());
1154 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
182735ef 1155 PowerPCCPU *first_ppc_cpu;
b7d1f77a 1156 uint32_t rtas_limit;
259186a7 1157
9e3f9733
AG		 1158 /* Check for unknown sysbus devices */
1159 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL);
1160
c5f54f3e
DG		 1161 /* Allocate and/or reset the hash page table */
1162 spapr_reallocate_hpt(spapr,
1163 spapr_hpt_shift_for_ramsize(machine->maxram_size),
1164 &error_fatal);
1165
1166 /* Update the RMA size if necessary */
1167 if (spapr->vrma_adjust) {
1168 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(),
1169 spapr->htab_shift);
1170 }
a3467baa 1171
c8787ad4 1172 qemu_devices_reset();
a3467baa 1173
b7d1f77a
BH		 1174 /*
1175 * We place the device tree and RTAS just below either the top of the RMA,
1176 * or just below 2GB, whichever is lowere, so that it can be
1177 * processed with 32-bit real mode code if necessary
1178 */
1179 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR);
1180 spapr->rtas_addr = rtas_limit - RTAS_MAX_SIZE;
1181 spapr->fdt_addr = spapr->rtas_addr - FDT_MAX_SIZE;
1182
a3467baa
DG		 1183 /* Load the fdt */
1184 spapr_finalize_fdt(spapr, spapr->fdt_addr, spapr->rtas_addr,
1185 spapr->rtas_size);
1186
b7d1f77a
BH		 1187 /* Copy RTAS over */
1188 cpu_physical_memory_write(spapr->rtas_addr, spapr->rtas_blob,
1189 spapr->rtas_size);
1190
a3467baa 1191 /* Set up the entry state */
182735ef
AF		 1192 first_ppc_cpu = POWERPC_CPU(first_cpu);
1193 first_ppc_cpu->env.gpr[3] = spapr->fdt_addr;
1194 first_ppc_cpu->env.gpr[5] = 0;
1195 first_cpu->halted = 0;
1b718907 1196 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT;
a3467baa
DG		 1197
1198}
1199
28e02042 1200static void spapr_create_nvram(sPAPRMachineState *spapr)
639e8102 1201{
2ff3de68 1202 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram");
3978b863 1203 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
639e8102 1204
3978b863 1205 if (dinfo) {
6231a6da
MA		 1206 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
1207 &error_fatal);
639e8102
DG		 1208 }
1209
1210 qdev_init_nofail(dev);
1211
1212 spapr->nvram = (struct sPAPRNVRAM *)dev;
1213}
1214
28e02042 1215static void spapr_rtc_create(sPAPRMachineState *spapr)
28df36a1
DG		 1216{
1217 DeviceState *dev = qdev_create(NULL, TYPE_SPAPR_RTC);
1218
1219 qdev_init_nofail(dev);
1220 spapr->rtc = dev;
74e5ae28
DG		 1221
1222 object_property_add_alias(qdev_get_machine(), "rtc-time",
1223 OBJECT(spapr->rtc), "date", NULL);
28df36a1
DG		 1224}
1225
8c57b867 1226/* Returns whether we want to use VGA or not */
14c6a894 1227static bool spapr_vga_init(PCIBus *pci_bus, Error **errp)
f28359d8 1228{
8c57b867 1229 switch (vga_interface_type) {
8c57b867 1230 case VGA_NONE:
7effdaa3
MW		 1231 return false;
1232 case VGA_DEVICE:
1233 return true;
1ddcae82 1234 case VGA_STD:
b798c190 1235 case VGA_VIRTIO:
1ddcae82 1236 return pci_vga_init(pci_bus) != NULL;
8c57b867 1237 default:
14c6a894
DG		 1238 error_setg(errp,
1239 "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1240 return false;
f28359d8 1241 }
f28359d8
LZ		 1242}
1243
880ae7de
DG		 1244static int spapr_post_load(void *opaque, int version_id)
1245{
28e02042 1246 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque;
880ae7de
DG		 1247 int err = 0;
1248
631b22ea 1249 /* In earlier versions, there was no separate qdev for the PAPR
880ae7de
DG		 1250 * RTC, so the RTC offset was stored directly in sPAPREnvironment.
1251 * So when migrating from those versions, poke the incoming offset
1252 * value into the RTC device */
1253 if (version_id < 3) {
1254 err = spapr_rtc_import_offset(spapr->rtc, spapr->rtc_offset);
1255 }
1256
1257 return err;
1258}
1259
1260static bool version_before_3(void *opaque, int version_id)
1261{
1262 return version_id < 3;
1263}
1264
4be21d56
DG		 1265static const VMStateDescription vmstate_spapr = {
1266 .name = "spapr",
880ae7de 1267 .version_id = 3,
4be21d56 1268 .minimum_version_id = 1,
880ae7de 1269 .post_load = spapr_post_load,
3aff6c2f 1270 .fields = (VMStateField[]) {
880ae7de
DG		 1271 /* used to be @next_irq */
1272 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4),
4be21d56
DG		 1273
1274 /* RTC offset */
28e02042 1275 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3),
880ae7de 1276
28e02042 1277 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2),
4be21d56
DG		 1278 VMSTATE_END_OF_LIST()
1279 },
1280};
1281
4be21d56
DG		 1282static int htab_save_setup(QEMUFile *f, void *opaque)
1283{
28e02042 1284 sPAPRMachineState *spapr = opaque;
4be21d56 1285
4be21d56
DG		 1286 /* "Iteration" header */
1287 qemu_put_be32(f, spapr->htab_shift);
1288
e68cb8b4
AK		 1289 if (spapr->htab) {
1290 spapr->htab_save_index = 0;
1291 spapr->htab_first_pass = true;
1292 } else {
1293 assert(kvm_enabled());
e68cb8b4
AK		 1294 }
1295
1296
4be21d56
DG		 1297 return 0;
1298}
1299
28e02042 1300static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr,
4be21d56
DG		 1301 int64_t max_ns)
1302{
378bc217 1303 bool has_timeout = max_ns != -1;
4be21d56
DG		 1304 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1305 int index = spapr->htab_save_index;
bc72ad67 1306 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
4be21d56
DG		 1307
1308 assert(spapr->htab_first_pass);
1309
1310 do {
1311 int chunkstart;
1312
1313 /* Consume invalid HPTEs */
1314 while ((index < htabslots)
1315 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1316 index++;
1317 CLEAN_HPTE(HPTE(spapr->htab, index));
1318 }
1319
1320 /* Consume valid HPTEs */
1321 chunkstart = index;
338c25b6 1322 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
4be21d56
DG		 1323 && HPTE_VALID(HPTE(spapr->htab, index))) {
1324 index++;
1325 CLEAN_HPTE(HPTE(spapr->htab, index));
1326 }
1327
1328 if (index > chunkstart) {
1329 int n_valid = index - chunkstart;
1330
1331 qemu_put_be32(f, chunkstart);
1332 qemu_put_be16(f, n_valid);
1333 qemu_put_be16(f, 0);
1334 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1335 HASH_PTE_SIZE_64 * n_valid);
1336
378bc217
DG		 1337 if (has_timeout &&
1338 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
4be21d56
DG		 1339 break;
1340 }
1341 }
1342 } while ((index < htabslots) && !qemu_file_rate_limit(f));
1343
1344 if (index >= htabslots) {
1345 assert(index == htabslots);
1346 index = 0;
1347 spapr->htab_first_pass = false;
1348 }
1349 spapr->htab_save_index = index;
1350}
1351
28e02042 1352static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr,
e68cb8b4 1353 int64_t max_ns)
4be21d56
DG		 1354{
1355 bool final = max_ns < 0;
1356 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1357 int examined = 0, sent = 0;
1358 int index = spapr->htab_save_index;
bc72ad67 1359 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
4be21d56
DG		 1360
1361 assert(!spapr->htab_first_pass);
1362
1363 do {
1364 int chunkstart, invalidstart;
1365
1366 /* Consume non-dirty HPTEs */
1367 while ((index < htabslots)
1368 && !HPTE_DIRTY(HPTE(spapr->htab, index))) {
1369 index++;
1370 examined++;
1371 }
1372
1373 chunkstart = index;
1374 /* Consume valid dirty HPTEs */
338c25b6 1375 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
4be21d56
DG		 1376 && HPTE_DIRTY(HPTE(spapr->htab, index))
1377 && HPTE_VALID(HPTE(spapr->htab, index))) {
1378 CLEAN_HPTE(HPTE(spapr->htab, index));
1379 index++;
1380 examined++;
1381 }
1382
1383 invalidstart = index;
1384 /* Consume invalid dirty HPTEs */
338c25b6 1385 while ((index < htabslots) && (index - invalidstart < USHRT_MAX)
4be21d56
DG		 1386 && HPTE_DIRTY(HPTE(spapr->htab, index))
1387 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1388 CLEAN_HPTE(HPTE(spapr->htab, index));
1389 index++;
1390 examined++;
1391 }
1392
1393 if (index > chunkstart) {
1394 int n_valid = invalidstart - chunkstart;
1395 int n_invalid = index - invalidstart;
1396
1397 qemu_put_be32(f, chunkstart);
1398 qemu_put_be16(f, n_valid);
1399 qemu_put_be16(f, n_invalid);
1400 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1401 HASH_PTE_SIZE_64 * n_valid);
1402 sent += index - chunkstart;
1403
bc72ad67 1404 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
4be21d56
DG		 1405 break;
1406 }
1407 }
1408
1409 if (examined >= htabslots) {
1410 break;
1411 }
1412
1413 if (index >= htabslots) {
1414 assert(index == htabslots);
1415 index = 0;
1416 }
1417 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final));
1418
1419 if (index >= htabslots) {
1420 assert(index == htabslots);
1421 index = 0;
1422 }
1423
1424 spapr->htab_save_index = index;
1425
e68cb8b4 1426 return (examined >= htabslots) && (sent == 0) ? 1 : 0;
4be21d56
DG		 1427}
1428
e68cb8b4
AK		 1429#define MAX_ITERATION_NS 5000000 /* 5 ms */
1430#define MAX_KVM_BUF_SIZE 2048
1431
4be21d56
DG		 1432static int htab_save_iterate(QEMUFile *f, void *opaque)
1433{
28e02042 1434 sPAPRMachineState *spapr = opaque;
715c5407 1435 int fd;
e68cb8b4 1436 int rc = 0;
4be21d56
DG		 1437
1438 /* Iteration header */
1439 qemu_put_be32(f, 0);
1440
e68cb8b4
AK		 1441 if (!spapr->htab) {
1442 assert(kvm_enabled());
1443
715c5407
DG		 1444 fd = get_htab_fd(spapr);
1445 if (fd < 0) {
1446 return fd;
01a57972
SMJ		 1447 }
1448
715c5407 1449 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS);
e68cb8b4
AK		 1450 if (rc < 0) {
1451 return rc;
1452 }
1453 } else if (spapr->htab_first_pass) {
4be21d56
DG		 1454 htab_save_first_pass(f, spapr, MAX_ITERATION_NS);
1455 } else {
e68cb8b4 1456 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS);
4be21d56
DG		 1457 }
1458
1459 /* End marker */
1460 qemu_put_be32(f, 0);
1461 qemu_put_be16(f, 0);
1462 qemu_put_be16(f, 0);
1463
e68cb8b4 1464 return rc;
4be21d56
DG		 1465}
1466
1467static int htab_save_complete(QEMUFile *f, void *opaque)
1468{
28e02042 1469 sPAPRMachineState *spapr = opaque;
715c5407 1470 int fd;
4be21d56
DG		 1471
1472 /* Iteration header */
1473 qemu_put_be32(f, 0);
1474
e68cb8b4
AK		 1475 if (!spapr->htab) {
1476 int rc;
1477
1478 assert(kvm_enabled());
1479
715c5407
DG		 1480 fd = get_htab_fd(spapr);
1481 if (fd < 0) {
1482 return fd;
01a57972
SMJ		 1483 }
1484
715c5407 1485 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1);
e68cb8b4
AK		 1486 if (rc < 0) {
1487 return rc;
1488 }
715c5407 1489 close_htab_fd(spapr);
e68cb8b4 1490 } else {
378bc217
DG		 1491 if (spapr->htab_first_pass) {
1492 htab_save_first_pass(f, spapr, -1);
1493 }
e68cb8b4
AK		 1494 htab_save_later_pass(f, spapr, -1);
1495 }
4be21d56
DG		 1496
1497 /* End marker */
1498 qemu_put_be32(f, 0);
1499 qemu_put_be16(f, 0);
1500 qemu_put_be16(f, 0);
1501
1502 return 0;
1503}
1504
1505static int htab_load(QEMUFile *f, void *opaque, int version_id)
1506{
28e02042 1507 sPAPRMachineState *spapr = opaque;
4be21d56 1508 uint32_t section_hdr;
e68cb8b4 1509 int fd = -1;
4be21d56
DG		 1510
1511 if (version_id < 1 || version_id > 1) {
98a5d100 1512 error_report("htab_load() bad version");
4be21d56
DG		 1513 return -EINVAL;
1514 }
1515
1516 section_hdr = qemu_get_be32(f);
1517
1518 if (section_hdr) {
9897e462 1519 Error *local_err = NULL;
c5f54f3e
DG		 1520
1521 /* First section gives the htab size */
1522 spapr_reallocate_hpt(spapr, section_hdr, &local_err);
1523 if (local_err) {
1524 error_report_err(local_err);
4be21d56
DG		 1525 return -EINVAL;
1526 }
1527 return 0;
1528 }
1529
e68cb8b4
AK		 1530 if (!spapr->htab) {
1531 assert(kvm_enabled());
1532
1533 fd = kvmppc_get_htab_fd(true);
1534 if (fd < 0) {
98a5d100
DG		 1535 error_report("Unable to open fd to restore KVM hash table: %s",
1536 strerror(errno));
e68cb8b4
AK		 1537 }
1538 }
1539
4be21d56
DG		 1540 while (true) {
1541 uint32_t index;
1542 uint16_t n_valid, n_invalid;
1543
1544 index = qemu_get_be32(f);
1545 n_valid = qemu_get_be16(f);
1546 n_invalid = qemu_get_be16(f);
1547
1548 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) {
1549 /* End of Stream */
1550 break;
1551 }
1552
e68cb8b4 1553 if ((index + n_valid + n_invalid) >
4be21d56
DG		 1554 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) {
1555 /* Bad index in stream */
98a5d100
DG		 1556 error_report(
1557 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
1558 index, n_valid, n_invalid, spapr->htab_shift);
4be21d56
DG		 1559 return -EINVAL;
1560 }
1561
e68cb8b4
AK		 1562 if (spapr->htab) {
1563 if (n_valid) {
1564 qemu_get_buffer(f, HPTE(spapr->htab, index),
1565 HASH_PTE_SIZE_64 * n_valid);
1566 }
1567 if (n_invalid) {
1568 memset(HPTE(spapr->htab, index + n_valid), 0,
1569 HASH_PTE_SIZE_64 * n_invalid);
1570 }
1571 } else {
1572 int rc;
1573
1574 assert(fd >= 0);
1575
1576 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid);
1577 if (rc < 0) {
1578 return rc;
1579 }
4be21d56
DG		 1580 }
1581 }
1582
e68cb8b4
AK		 1583 if (!spapr->htab) {
1584 assert(fd >= 0);
1585 close(fd);
1586 }
1587
4be21d56
DG		 1588 return 0;
1589}
1590
1591static SaveVMHandlers savevm_htab_handlers = {
1592 .save_live_setup = htab_save_setup,
1593 .save_live_iterate = htab_save_iterate,
a3e06c3d 1594 .save_live_complete_precopy = htab_save_complete,
4be21d56
DG		 1595 .load_state = htab_load,
1596};
1597
5b2128d2
AG		 1598static void spapr_boot_set(void *opaque, const char *boot_device,
1599 Error **errp)
1600{
1601 MachineState *machine = MACHINE(qdev_get_machine());
1602 machine->boot_order = g_strdup(boot_device);
1603}
1604
224245bf
DG		 1605/*
1606 * Reset routine for LMB DR devices.
1607 *
1608 * Unlike PCI DR devices, LMB DR devices explicitly register this reset
1609 * routine. Reset for PCI DR devices will be handled by PHB reset routine
1610 * when it walks all its children devices. LMB devices reset occurs
1611 * as part of spapr_ppc_reset().
1612 */
1613static void spapr_drc_reset(void *opaque)
1614{
1615 sPAPRDRConnector *drc = opaque;
1616 DeviceState *d = DEVICE(drc);
1617
1618 if (d) {
1619 device_reset(d);
1620 }
1621}
1622
1623static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr)
1624{
1625 MachineState *machine = MACHINE(spapr);
1626 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
e8f986fc 1627 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size;
224245bf
DG		 1628 int i;
1629
1630 for (i = 0; i < nr_lmbs; i++) {
1631 sPAPRDRConnector *drc;
1632 uint64_t addr;
1633
e8f986fc 1634 addr = i * lmb_size + spapr->hotplug_memory.base;
224245bf
DG		 1635 drc = spapr_dr_connector_new(OBJECT(spapr), SPAPR_DR_CONNECTOR_TYPE_LMB,
1636 addr/lmb_size);
1637 qemu_register_reset(spapr_drc_reset, drc);
1638 }
1639}
1640
1641/*
1642 * If RAM size, maxmem size and individual node mem sizes aren't aligned
1643 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest
1644 * since we can't support such unaligned sizes with DRCONF_MEMORY.
1645 */
7c150d6f 1646static void spapr_validate_node_memory(MachineState *machine, Error **errp)
224245bf
DG		 1647{
1648 int i;
1649
7c150d6f
DG		 1650 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) {
1651 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT
1652 " is not aligned to %llu MiB",
1653 machine->ram_size,
1654 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1655 return;
1656 }
1657
1658 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) {
1659 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT
1660 " is not aligned to %llu MiB",
1661 machine->ram_size,
1662 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1663 return;
224245bf
DG		 1664 }
1665
1666 for (i = 0; i < nb_numa_nodes; i++) {
1667 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) {
7c150d6f
DG		 1668 error_setg(errp,
1669 "Node %d memory size 0x%" PRIx64
1670 " is not aligned to %llu MiB",
1671 i, numa_info[i].node_mem,
1672 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1673 return;
224245bf
DG		 1674 }
1675 }
1676}
1677
9fdf0c29 1678/* pSeries LPAR / sPAPR hardware init */
3ef96221 1679static void ppc_spapr_init(MachineState *machine)
9fdf0c29 1680{
28e02042 1681 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
224245bf 1682 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
3ef96221
MA		 1683 const char *kernel_filename = machine->kernel_filename;
1684 const char *kernel_cmdline = machine->kernel_cmdline;
1685 const char *initrd_filename = machine->initrd_filename;
05769733 1686 PowerPCCPU *cpu;
8c9f64df 1687 PCIHostState *phb;
9fdf0c29 1688 int i;
890c2b77
AK		 1689 MemoryRegion *sysmem = get_system_memory();
1690 MemoryRegion *ram = g_new(MemoryRegion, 1);
658fa66b
AK		 1691 MemoryRegion *rma_region;
1692 void *rma = NULL;
a8170e5e 1693 hwaddr rma_alloc_size;
b082d65a 1694 hwaddr node0_size = spapr_node0_size();
4d8d5467
BH		 1695 uint32_t initrd_base = 0;
1696 long kernel_size = 0, initrd_size = 0;
b7d1f77a 1697 long load_limit, fw_size;
16457e7f 1698 bool kernel_le = false;
39ac8455 1699 char *filename;
9fdf0c29 1700
226419d6 1701 msi_nonbroken = true;
0ee2c058 1702
d43b45e2
DG		 1703 QLIST_INIT(&spapr->phbs);
1704
9fdf0c29
DG		 1705 cpu_ppc_hypercall = emulate_spapr_hypercall;
1706
354ac20a 1707 /* Allocate RMA if necessary */
658fa66b 1708 rma_alloc_size = kvmppc_alloc_rma(&rma);
354ac20a
DG		 1709
1710 if (rma_alloc_size == -1) {
730fce59 1711 error_report("Unable to create RMA");
354ac20a
DG		 1712 exit(1);
1713 }
7f763a5d 1714
c4177479 1715 if (rma_alloc_size && (rma_alloc_size < node0_size)) {
7f763a5d 1716 spapr->rma_size = rma_alloc_size;
354ac20a 1717 } else {
c4177479 1718 spapr->rma_size = node0_size;
7f763a5d
DG		 1719
1720 /* With KVM, we don't actually know whether KVM supports an
1721 * unbounded RMA (PR KVM) or is limited by the hash table size
1722 * (HV KVM using VRMA), so we always assume the latter
1723 *
1724 * In that case, we also limit the initial allocations for RTAS
1725 * etc... to 256M since we have no way to know what the VRMA size
1726 * is going to be as it depends on the size of the hash table
1727 * isn't determined yet.
1728 */
1729 if (kvm_enabled()) {
1730 spapr->vrma_adjust = 1;
1731 spapr->rma_size = MIN(spapr->rma_size, 0x10000000);
1732 }
354ac20a
DG		 1733 }
1734
c4177479 1735 if (spapr->rma_size > node0_size) {
d54e4d76
DG		 1736 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")",
1737 spapr->rma_size);
c4177479
AK		 1738 exit(1);
1739 }
1740
b7d1f77a
BH		 1741 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */
1742 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD;
9fdf0c29 1743
7b565160 1744 /* Set up Interrupt Controller before we create the VCPUs */
446f16a6 1745 spapr->icp = xics_system_init(machine,
9e734e3d 1746 DIV_ROUND_UP(max_cpus * kvmppc_smt_threads(),
f303f117 1747 smp_threads),
1e49182d 1748 XICS_IRQS, &error_fatal);
7b565160 1749
224245bf 1750 if (smc->dr_lmb_enabled) {
7c150d6f 1751 spapr_validate_node_memory(machine, &error_fatal);
224245bf
DG		 1752 }
1753
9fdf0c29 1754 /* init CPUs */
19fb2c36
BR		 1755 if (machine->cpu_model == NULL) {
1756 machine->cpu_model = kvm_enabled() ? "host" : "POWER7";
9fdf0c29
DG		 1757 }
1758 for (i = 0; i < smp_cpus; i++) {
19fb2c36 1759 cpu = cpu_ppc_init(machine->cpu_model);
05769733 1760 if (cpu == NULL) {
569f4967 1761 error_report("Unable to find PowerPC CPU definition");
9fdf0c29
DG		 1762 exit(1);
1763 }
569f4967 1764 spapr_cpu_init(spapr, cpu, &error_fatal);
9fdf0c29
DG		 1765 }
1766
026bfd89
DG		 1767 if (kvm_enabled()) {
1768 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */
1769 kvmppc_enable_logical_ci_hcalls();
ef9971dd 1770 kvmppc_enable_set_mode_hcall();
026bfd89
DG		 1771 }
1772
9fdf0c29 1773 /* allocate RAM */
f92f5da1 1774 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram",
fb164994 1775 machine->ram_size);
f92f5da1 1776 memory_region_add_subregion(sysmem, 0, ram);
9fdf0c29 1777
658fa66b
AK		 1778 if (rma_alloc_size && rma) {
1779 rma_region = g_new(MemoryRegion, 1);
1780 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma",
1781 rma_alloc_size, rma);
1782 vmstate_register_ram_global(rma_region);
1783 memory_region_add_subregion(sysmem, 0, rma_region);
1784 }
1785
4a1c9cf0
BR		 1786 /* initialize hotplug memory address space */
1787 if (machine->ram_size < machine->maxram_size) {
1788 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size;
71c9a3dd
BR		 1789 /*
1790 * Limit the number of hotpluggable memory slots to half the number
1791 * slots that KVM supports, leaving the other half for PCI and other
1792 * devices. However ensure that number of slots doesn't drop below 32.
1793 */
1794 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 :
1795 SPAPR_MAX_RAM_SLOTS;
4a1c9cf0 1796
71c9a3dd
BR		 1797 if (max_memslots < SPAPR_MAX_RAM_SLOTS) {
1798 max_memslots = SPAPR_MAX_RAM_SLOTS;
1799 }
1800 if (machine->ram_slots > max_memslots) {
d54e4d76
DG		 1801 error_report("Specified number of memory slots %"
1802 PRIu64" exceeds max supported %d",
71c9a3dd 1803 machine->ram_slots, max_memslots);
d54e4d76 1804 exit(1);
4a1c9cf0
BR		 1805 }
1806
1807 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size,
1808 SPAPR_HOTPLUG_MEM_ALIGN);
1809 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr),
1810 "hotplug-memory", hotplug_mem_size);
1811 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base,
1812 &spapr->hotplug_memory.mr);
1813 }
1814
224245bf
DG		 1815 if (smc->dr_lmb_enabled) {
1816 spapr_create_lmb_dr_connectors(spapr);
1817 }
1818
39ac8455 1819 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
4c56440d 1820 if (!filename) {
730fce59 1821 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin");
4c56440d
SW		 1822 exit(1);
1823 }
b7d1f77a 1824 spapr->rtas_size = get_image_size(filename);
8afc22a2
ZJ		 1825 if (spapr->rtas_size < 0) {
1826 error_report("Could not get size of LPAR rtas '%s'", filename);
1827 exit(1);
1828 }
b7d1f77a
BH		 1829 spapr->rtas_blob = g_malloc(spapr->rtas_size);
1830 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) {
730fce59 1831 error_report("Could not load LPAR rtas '%s'", filename);
39ac8455
DG		 1832 exit(1);
1833 }
4d8d5467 1834 if (spapr->rtas_size > RTAS_MAX_SIZE) {
730fce59
TH		 1835 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)",
1836 (size_t)spapr->rtas_size, RTAS_MAX_SIZE);
4d8d5467
BH		 1837 exit(1);
1838 }
7267c094 1839 g_free(filename);
39ac8455 1840
74d042e5
DG		 1841 /* Set up EPOW events infrastructure */
1842 spapr_events_init(spapr);
1843
12f42174 1844 /* Set up the RTC RTAS interfaces */
28df36a1 1845 spapr_rtc_create(spapr);
12f42174 1846
b5cec4c5 1847 /* Set up VIO bus */
4040ab72
DG		 1848 spapr->vio_bus = spapr_vio_bus_init();
1849
277f9acf 1850 for (i = 0; i < MAX_SERIAL_PORTS; i++) {
4040ab72 1851 if (serial_hds[i]) {
d601fac4 1852 spapr_vty_create(spapr->vio_bus, serial_hds[i]);
4040ab72
DG		 1853 }
1854 }
9fdf0c29 1855
639e8102
DG		 1856 /* We always have at least the nvram device on VIO */
1857 spapr_create_nvram(spapr);
1858
3384f95c 1859 /* Set up PCI */
fa28f71b
AK		 1860 spapr_pci_rtas_init();
1861
89dfd6e1 1862 phb = spapr_create_phb(spapr, 0);
3384f95c 1863
277f9acf 1864 for (i = 0; i < nb_nics; i++) {
8d90ad90
DG		 1865 NICInfo *nd = &nd_table[i];
1866
1867 if (!nd->model) {
7267c094 1868 nd->model = g_strdup("ibmveth");
8d90ad90
DG		 1869 }
1870
1871 if (strcmp(nd->model, "ibmveth") == 0) {
d601fac4 1872 spapr_vlan_create(spapr->vio_bus, nd);
8d90ad90 1873 } else {
29b358f9 1874 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL);
8d90ad90
DG		 1875 }
1876 }
1877
6e270446 1878 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) {
d601fac4 1879 spapr_vscsi_create(spapr->vio_bus);
6e270446
BH		 1880 }
1881
f28359d8 1882 /* Graphics */
14c6a894 1883 if (spapr_vga_init(phb->bus, &error_fatal)) {
3fc5acde 1884 spapr->has_graphics = true;
c6e76503 1885 machine->usb |= defaults_enabled() && !machine->usb_disabled;
f28359d8
LZ		 1886 }
1887
4ee9ced9 1888 if (machine->usb) {
57040d45
TH		 1889 if (smc->use_ohci_by_default) {
1890 pci_create_simple(phb->bus, -1, "pci-ohci");
1891 } else {
1892 pci_create_simple(phb->bus, -1, "nec-usb-xhci");
1893 }
c86580b8 1894
35139a59 1895 if (spapr->has_graphics) {
c86580b8
MA		 1896 USBBus *usb_bus = usb_bus_find(-1);
1897
1898 usb_create_simple(usb_bus, "usb-kbd");
1899 usb_create_simple(usb_bus, "usb-mouse");
35139a59
DG		 1900 }
1901 }
1902
7f763a5d 1903 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) {
d54e4d76
DG		 1904 error_report(
1905 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)",
1906 MIN_RMA_SLOF);
4d8d5467
BH		 1907 exit(1);
1908 }
1909
9fdf0c29
DG		 1910 if (kernel_filename) {
1911 uint64_t lowaddr = 0;
1912
9fdf0c29 1913 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
7ef295ea
PC		 1914 NULL, &lowaddr, NULL, 1, PPC_ELF_MACHINE,
1915 0, 0);
3b66da82 1916 if (kernel_size == ELF_LOAD_WRONG_ENDIAN) {
16457e7f
BH		 1917 kernel_size = load_elf(kernel_filename,
1918 translate_kernel_address, NULL,
7ef295ea
PC		 1919 NULL, &lowaddr, NULL, 0, PPC_ELF_MACHINE,
1920 0, 0);
16457e7f
BH		 1921 kernel_le = kernel_size > 0;
1922 }
9fdf0c29 1923 if (kernel_size < 0) {
d54e4d76
DG		 1924 error_report("error loading %s: %s",
1925 kernel_filename, load_elf_strerror(kernel_size));
9fdf0c29
DG		 1926 exit(1);
1927 }
1928
1929 /* load initrd */
1930 if (initrd_filename) {
4d8d5467
BH		 1931 /* Try to locate the initrd in the gap between the kernel
1932 * and the firmware. Add a bit of space just in case
1933 */
1934 initrd_base = (KERNEL_LOAD_ADDR + kernel_size + 0x1ffff) & ~0xffff;
9fdf0c29 1935 initrd_size = load_image_targphys(initrd_filename, initrd_base,
4d8d5467 1936 load_limit - initrd_base);
9fdf0c29 1937 if (initrd_size < 0) {
d54e4d76
DG		 1938 error_report("could not load initial ram disk '%s'",
1939 initrd_filename);
9fdf0c29
DG		 1940 exit(1);
1941 }
1942 } else {
1943 initrd_base = 0;
1944 initrd_size = 0;
1945 }
4d8d5467 1946 }
a3467baa 1947
8e7ea787
AF		 1948 if (bios_name == NULL) {
1949 bios_name = FW_FILE_NAME;
1950 }
1951 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
4c56440d 1952 if (!filename) {
68fea5a0 1953 error_report("Could not find LPAR firmware '%s'", bios_name);
4c56440d
SW		 1954 exit(1);
1955 }
4d8d5467 1956 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
68fea5a0
TH		 1957 if (fw_size <= 0) {
1958 error_report("Could not load LPAR firmware '%s'", filename);
4d8d5467
BH		 1959 exit(1);
1960 }
1961 g_free(filename);
4d8d5467 1962
28e02042
DG		 1963 /* FIXME: Should register things through the MachineState's qdev
1964 * interface, this is a legacy from the sPAPREnvironment structure
1965 * which predated MachineState but had a similar function */
4be21d56
DG		 1966 vmstate_register(NULL, 0, &vmstate_spapr, spapr);
1967 register_savevm_live(NULL, "spapr/htab", -1, 1,
1968 &savevm_htab_handlers, spapr);
1969
9fdf0c29 1970 /* Prepare the device tree */
3bbf37f2 1971 spapr->fdt_skel = spapr_create_fdt_skel(initrd_base, initrd_size,
16457e7f 1972 kernel_size, kernel_le,
31fe14d1
NF		 1973 kernel_cmdline,
1974 spapr->check_exception_irq);
a3467baa 1975 assert(spapr->fdt_skel != NULL);
5b2128d2 1976
46503c2b
MR		 1977 /* used by RTAS */
1978 QTAILQ_INIT(&spapr->ccs_list);
1979 qemu_register_reset(spapr_ccs_reset_hook, spapr);
1980
5b2128d2 1981 qemu_register_boot_set(spapr_boot_set, spapr);
9fdf0c29
DG		 1982}
1983
135a129a
AK		 1984static int spapr_kvm_type(const char *vm_type)
1985{
1986 if (!vm_type) {
1987 return 0;
1988 }
1989
1990 if (!strcmp(vm_type, "HV")) {
1991 return 1;
1992 }
1993
1994 if (!strcmp(vm_type, "PR")) {
1995 return 2;
1996 }
1997
1998 error_report("Unknown kvm-type specified '%s'", vm_type);
1999 exit(1);
2000}
2001
71461b0f 2002/*
627b84f4 2003 * Implementation of an interface to adjust firmware path
71461b0f
AK		 2004 * for the bootindex property handling.
2005 */
2006static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus,
2007 DeviceState *dev)
2008{
2009#define CAST(type, obj, name) \
2010 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
2011 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE);
2012 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE);
2013
2014 if (d) {
2015 void *spapr = CAST(void, bus->parent, "spapr-vscsi");
2016 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI);
2017 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE);
2018
2019 if (spapr) {
2020 /*
2021 * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
2022 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun
2023 * in the top 16 bits of the 64-bit LUN
2024 */
2025 unsigned id = 0x8000 | (d->id << 8) | d->lun;
2026 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2027 (uint64_t)id << 48);
2028 } else if (virtio) {
2029 /*
2030 * We use SRP luns of the form 01000000 | (target << 8) | lun
2031 * in the top 32 bits of the 64-bit LUN
2032 * Note: the quote above is from SLOF and it is wrong,
2033 * the actual binding is:
2034 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
2035 */
2036 unsigned id = 0x1000000 | (d->id << 16) | d->lun;
2037 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2038 (uint64_t)id << 32);
2039 } else if (usb) {
2040 /*
2041 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
2042 * in the top 32 bits of the 64-bit LUN
2043 */
2044 unsigned usb_port = atoi(usb->port->path);
2045 unsigned id = 0x1000000 | (usb_port << 16) | d->lun;
2046 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2047 (uint64_t)id << 32);
2048 }
2049 }
2050
2051 if (phb) {
2052 /* Replace "pci" with "pci@800000020000000" */
2053 return g_strdup_printf("pci@%"PRIX64, phb->buid);
2054 }
2055
2056 return NULL;
2057}
2058
23825581
EH		 2059static char *spapr_get_kvm_type(Object *obj, Error **errp)
2060{
28e02042 2061 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
23825581 2062
28e02042 2063 return g_strdup(spapr->kvm_type);
23825581
EH		 2064}
2065
2066static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp)
2067{
28e02042 2068 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
23825581 2069
28e02042
DG		 2070 g_free(spapr->kvm_type);
2071 spapr->kvm_type = g_strdup(value);
23825581
EH		 2072}
2073
2074static void spapr_machine_initfn(Object *obj)
2075{
715c5407
DG		 2076 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2077
2078 spapr->htab_fd = -1;
23825581
EH		 2079 object_property_add_str(obj, "kvm-type",
2080 spapr_get_kvm_type, spapr_set_kvm_type, NULL);
49d2e648
MA		 2081 object_property_set_description(obj, "kvm-type",
2082 "Specifies the KVM virtualization mode (HV, PR)",
2083 NULL);
23825581
EH		 2084}
2085
87bbdd9c
DG		 2086static void spapr_machine_finalizefn(Object *obj)
2087{
2088 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2089
2090 g_free(spapr->kvm_type);
2091}
2092
34316482
AK		 2093static void ppc_cpu_do_nmi_on_cpu(void *arg)
2094{
2095 CPUState *cs = arg;
2096
2097 cpu_synchronize_state(cs);
2098 ppc_cpu_do_system_reset(cs);
2099}
2100
2101static void spapr_nmi(NMIState *n, int cpu_index, Error **errp)
2102{
2103 CPUState *cs;
2104
2105 CPU_FOREACH(cs) {
2106 async_run_on_cpu(cs, ppc_cpu_do_nmi_on_cpu, cs);
2107 }
2108}
2109
c20d332a
BR		 2110static void spapr_add_lmbs(DeviceState *dev, uint64_t addr, uint64_t size,
2111 uint32_t node, Error **errp)
2112{
2113 sPAPRDRConnector *drc;
2114 sPAPRDRConnectorClass *drck;
2115 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE;
2116 int i, fdt_offset, fdt_size;
2117 void *fdt;
2118
c20d332a
BR		 2119 for (i = 0; i < nr_lmbs; i++) {
2120 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB,
2121 addr/SPAPR_MEMORY_BLOCK_SIZE);
2122 g_assert(drc);
2123
2124 fdt = create_device_tree(&fdt_size);
2125 fdt_offset = spapr_populate_memory_node(fdt, node, addr,
2126 SPAPR_MEMORY_BLOCK_SIZE);
2127
2128 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2129 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, errp);
c20d332a
BR		 2130 addr += SPAPR_MEMORY_BLOCK_SIZE;
2131 }
5dd5238c
JD		 2132 /* send hotplug notification to the
2133 * guest only in case of hotplugged memory
2134 */
2135 if (dev->hotplugged) {
2136 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, nr_lmbs);
2137 }
c20d332a
BR		 2138}
2139
2140static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2141 uint32_t node, Error **errp)
2142{
2143 Error *local_err = NULL;
2144 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev);
2145 PCDIMMDevice *dimm = PC_DIMM(dev);
2146 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
2147 MemoryRegion *mr = ddc->get_memory_region(dimm);
2148 uint64_t align = memory_region_get_alignment(mr);
2149 uint64_t size = memory_region_size(mr);
2150 uint64_t addr;
2151
2152 if (size % SPAPR_MEMORY_BLOCK_SIZE) {
2153 error_setg(&local_err, "Hotplugged memory size must be a multiple of "
2154 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE/M_BYTE);
2155 goto out;
2156 }
2157
d6a9b0b8 2158 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err);
c20d332a
BR		 2159 if (local_err) {
2160 goto out;
2161 }
2162
2163 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err);
2164 if (local_err) {
2165 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr);
2166 goto out;
2167 }
2168
2169 spapr_add_lmbs(dev, addr, size, node, &error_abort);
2170
2171out:
2172 error_propagate(errp, local_err);
2173}
2174
2175static void spapr_machine_device_plug(HotplugHandler *hotplug_dev,
2176 DeviceState *dev, Error **errp)
2177{
2178 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine());
2179
2180 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
b556854b 2181 int node;
c20d332a
BR		 2182
2183 if (!smc->dr_lmb_enabled) {
2184 error_setg(errp, "Memory hotplug not supported for this machine");
2185 return;
2186 }
2187 node = object_property_get_int(OBJECT(dev), PC_DIMM_NODE_PROP, errp);
2188 if (*errp) {
2189 return;
2190 }
1a5512bb
GA		 2191 if (node < 0 || node >= MAX_NODES) {
2192 error_setg(errp, "Invaild node %d", node);
2193 return;
2194 }
c20d332a 2195
b556854b
BR		 2196 /*
2197 * Currently PowerPC kernel doesn't allow hot-adding memory to
2198 * memory-less node, but instead will silently add the memory
2199 * to the first node that has some memory. This causes two
2200 * unexpected behaviours for the user.
2201 *
2202 * - Memory gets hotplugged to a different node than what the user
2203 * specified.
2204 * - Since pc-dimm subsystem in QEMU still thinks that memory belongs
2205 * to memory-less node, a reboot will set things accordingly
2206 * and the previously hotplugged memory now ends in the right node.
2207 * This appears as if some memory moved from one node to another.
2208 *
2209 * So until kernel starts supporting memory hotplug to memory-less
2210 * nodes, just prevent such attempts upfront in QEMU.
2211 */
2212 if (nb_numa_nodes && !numa_info[node].node_mem) {
2213 error_setg(errp, "Can't hotplug memory to memory-less node %d",
2214 node);
2215 return;
2216 }
2217
c20d332a
BR		 2218 spapr_memory_plug(hotplug_dev, dev, node, errp);
2219 }
2220}
2221
2222static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev,
2223 DeviceState *dev, Error **errp)
2224{
2225 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2226 error_setg(errp, "Memory hot unplug not supported by sPAPR");
2227 }
2228}
2229
2230static HotplugHandler *spapr_get_hotpug_handler(MachineState *machine,
2231 DeviceState *dev)
2232{
2233 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2234 return HOTPLUG_HANDLER(machine);
2235 }
2236 return NULL;
2237}
2238
20bb648d
DG		 2239static unsigned spapr_cpu_index_to_socket_id(unsigned cpu_index)
2240{
2241 /* Allocate to NUMA nodes on a "socket" basis (not that concept of
2242 * socket means much for the paravirtualized PAPR platform) */
2243 return cpu_index / smp_threads / smp_cores;
2244}
2245
29ee3247
AK		 2246static void spapr_machine_class_init(ObjectClass *oc, void *data)
2247{
2248 MachineClass *mc = MACHINE_CLASS(oc);
224245bf 2249 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc);
71461b0f 2250 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
34316482 2251 NMIClass *nc = NMI_CLASS(oc);
c20d332a 2252 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
958db90c 2253
0eb9054c 2254 mc->desc = "pSeries Logical Partition (PAPR compliant)";
fc9f38c3
DG		 2255
2256 /*
2257 * We set up the default / latest behaviour here. The class_init
2258 * functions for the specific versioned machine types can override
2259 * these details for backwards compatibility
2260 */
958db90c
MA		 2261 mc->init = ppc_spapr_init;
2262 mc->reset = ppc_spapr_reset;
2263 mc->block_default_type = IF_SCSI;
38b02bd8 2264 mc->max_cpus = MAX_CPUMASK_BITS;
958db90c 2265 mc->no_parallel = 1;
5b2128d2 2266 mc->default_boot_order = "";
a34944fe 2267 mc->default_ram_size = 512 * M_BYTE;
958db90c 2268 mc->kvm_type = spapr_kvm_type;
9e3f9733 2269 mc->has_dynamic_sysbus = true;
e4024630 2270 mc->pci_allow_0_address = true;
c20d332a
BR		 2271 mc->get_hotplug_handler = spapr_get_hotpug_handler;
2272 hc->plug = spapr_machine_device_plug;
2273 hc->unplug = spapr_machine_device_unplug;
20bb648d 2274 mc->cpu_index_to_socket_id = spapr_cpu_index_to_socket_id;
00b4fbe2 2275
fc9f38c3 2276 smc->dr_lmb_enabled = true;
71461b0f 2277 fwc->get_dev_path = spapr_get_fw_dev_path;
34316482 2278 nc->nmi_monitor_handler = spapr_nmi;
29ee3247
AK		 2279}
2280
2281static const TypeInfo spapr_machine_info = {
2282 .name = TYPE_SPAPR_MACHINE,
2283 .parent = TYPE_MACHINE,
4aee7362 2284 .abstract = true,
6ca1502e 2285 .instance_size = sizeof(sPAPRMachineState),
23825581 2286 .instance_init = spapr_machine_initfn,
87bbdd9c 2287 .instance_finalize = spapr_machine_finalizefn,
183930c0 2288 .class_size = sizeof(sPAPRMachineClass),
29ee3247 2289 .class_init = spapr_machine_class_init,
71461b0f
AK		 2290 .interfaces = (InterfaceInfo[]) {
2291 { TYPE_FW_PATH_PROVIDER },
34316482 2292 { TYPE_NMI },
c20d332a 2293 { TYPE_HOTPLUG_HANDLER },
71461b0f
AK		 2294 { }
2295 },
29ee3247
AK		 2296};
2297
fccbc785 2298#define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \
5013c547
DG		 2299 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \
2300 void *data) \
2301 { \
2302 MachineClass *mc = MACHINE_CLASS(oc); \
2303 spapr_machine_##suffix##_class_options(mc); \
fccbc785
DG		 2304 if (latest) { \
2305 mc->alias = "pseries"; \
2306 mc->is_default = 1; \
2307 } \
5013c547
DG		 2308 } \
2309 static void spapr_machine_##suffix##_instance_init(Object *obj) \
2310 { \
2311 MachineState *machine = MACHINE(obj); \
2312 spapr_machine_##suffix##_instance_options(machine); \
2313 } \
2314 static const TypeInfo spapr_machine_##suffix##_info = { \
2315 .name = MACHINE_TYPE_NAME("pseries-" verstr), \
2316 .parent = TYPE_SPAPR_MACHINE, \
2317 .class_init = spapr_machine_##suffix##_class_init, \
2318 .instance_init = spapr_machine_##suffix##_instance_init, \
2319 }; \
2320 static void spapr_machine_register_##suffix(void) \
2321 { \
2322 type_register(&spapr_machine_##suffix##_info); \
2323 } \
0e6aac87 2324 type_init(spapr_machine_register_##suffix)
5013c547 2325
1ea1eefc
BR		 2326/*
2327 * pseries-2.7
2328 */
2329static void spapr_machine_2_7_instance_options(MachineState *machine)
2330{
2331}
2332
2333static void spapr_machine_2_7_class_options(MachineClass *mc)
2334{
2335 /* Defaults for the latest behaviour inherited from the base class */
2336}
2337
2338DEFINE_SPAPR_MACHINE(2_7, "2.7", true);
2339
4b23699c
DG		 2340/*
2341 * pseries-2.6
2342 */
1ea1eefc
BR		 2343#define SPAPR_COMPAT_2_6 \
2344 HW_COMPAT_2_6
2345
4b23699c
DG		 2346static void spapr_machine_2_6_instance_options(MachineState *machine)
2347{
2348}
2349
2350static void spapr_machine_2_6_class_options(MachineClass *mc)
2351{
1ea1eefc
BR		 2352 spapr_machine_2_7_class_options(mc);
2353 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6);
4b23699c
DG		 2354}
2355
1ea1eefc 2356DEFINE_SPAPR_MACHINE(2_6, "2.6", false);
4b23699c 2357
1c5f29bb
DG		 2358/*
2359 * pseries-2.5
2360 */
4b23699c 2361#define SPAPR_COMPAT_2_5 \
57c522f4
TH		 2362 HW_COMPAT_2_5 \
2363 { \
2364 .driver = "spapr-vlan", \
2365 .property = "use-rx-buffer-pools", \
2366 .value = "off", \
2367 },
4b23699c 2368
5013c547 2369static void spapr_machine_2_5_instance_options(MachineState *machine)
1c5f29bb 2370{
5013c547
DG		 2371}
2372
2373static void spapr_machine_2_5_class_options(MachineClass *mc)
2374{
57040d45
TH		 2375 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
2376
4b23699c 2377 spapr_machine_2_6_class_options(mc);
57040d45 2378 smc->use_ohci_by_default = true;
4b23699c 2379 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5);
1c5f29bb
DG		 2380}
2381
4b23699c 2382DEFINE_SPAPR_MACHINE(2_5, "2.5", false);
1c5f29bb
DG		 2383
2384/*
2385 * pseries-2.4
2386 */
80fd50f9
CH		 2387#define SPAPR_COMPAT_2_4 \
2388 HW_COMPAT_2_4
2389
5013c547 2390static void spapr_machine_2_4_instance_options(MachineState *machine)
1c5f29bb 2391{
5013c547
DG		 2392 spapr_machine_2_5_instance_options(machine);
2393}
1c5f29bb 2394
5013c547
DG		 2395static void spapr_machine_2_4_class_options(MachineClass *mc)
2396{
fc9f38c3
DG		 2397 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
2398
2399 spapr_machine_2_5_class_options(mc);
fc9f38c3 2400 smc->dr_lmb_enabled = false;
f949b4e5 2401 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4);
1c5f29bb
DG		 2402}
2403
fccbc785 2404DEFINE_SPAPR_MACHINE(2_4, "2.4", false);
1c5f29bb
DG		 2405
2406/*
2407 * pseries-2.3
2408 */
38ff32c6 2409#define SPAPR_COMPAT_2_3 \
7619c7b0
MR		 2410 HW_COMPAT_2_3 \
2411 {\
2412 .driver = "spapr-pci-host-bridge",\
2413 .property = "dynamic-reconfiguration",\
2414 .value = "off",\
2415 },
38ff32c6 2416
5013c547 2417static void spapr_machine_2_3_instance_options(MachineState *machine)
d25228e7 2418{
5013c547 2419 spapr_machine_2_4_instance_options(machine);
ff14e817 2420 savevm_skip_section_footers();
13d16814 2421 global_state_set_optional();
09b5e30d 2422 savevm_skip_configuration();
d25228e7
JW		 2423}
2424
5013c547 2425static void spapr_machine_2_3_class_options(MachineClass *mc)
6026db45 2426{
fc9f38c3 2427 spapr_machine_2_4_class_options(mc);
f949b4e5 2428 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3);
6026db45 2429}
fccbc785 2430DEFINE_SPAPR_MACHINE(2_3, "2.3", false);
6026db45 2431
1c5f29bb
DG		 2432/*
2433 * pseries-2.2
2434 */
2435
2436#define SPAPR_COMPAT_2_2 \
1c5f29bb
DG		 2437 HW_COMPAT_2_2 \
2438 {\
2439 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
2440 .property = "mem_win_size",\
2441 .value = "0x20000000",\
2442 },
2443
5013c547 2444static void spapr_machine_2_2_instance_options(MachineState *machine)
1c5f29bb 2445{
5013c547 2446 spapr_machine_2_3_instance_options(machine);
cba0e779 2447 machine->suppress_vmdesc = true;
1c5f29bb
DG		 2448}
2449
5013c547 2450static void spapr_machine_2_2_class_options(MachineClass *mc)
4aee7362 2451{
fc9f38c3 2452 spapr_machine_2_3_class_options(mc);
f949b4e5 2453 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2);
4aee7362 2454}
fccbc785 2455DEFINE_SPAPR_MACHINE(2_2, "2.2", false);
4aee7362 2456
1c5f29bb
DG		 2457/*
2458 * pseries-2.1
2459 */
2460#define SPAPR_COMPAT_2_1 \
1c5f29bb 2461 HW_COMPAT_2_1
3dab0244 2462
5013c547 2463static void spapr_machine_2_1_instance_options(MachineState *machine)
1c5f29bb 2464{
5013c547 2465 spapr_machine_2_2_instance_options(machine);
1c5f29bb 2466}
d25228e7 2467
5013c547 2468static void spapr_machine_2_1_class_options(MachineClass *mc)
d25228e7 2469{
fc9f38c3 2470 spapr_machine_2_2_class_options(mc);
f949b4e5 2471 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1);
d25228e7 2472}
fccbc785 2473DEFINE_SPAPR_MACHINE(2_1, "2.1", false);
fb0fc8f6 2474
29ee3247 2475static void spapr_machine_register_types(void)
9fdf0c29 2476{
29ee3247 2477 type_register_static(&spapr_machine_info);
9fdf0c29
DG		 2478}
2479
29ee3247 2480type_init(spapr_machine_register_types)
Empty description
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