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target-ppc: implement darn instruction
[qemu.git] / hw / ppc / spapr.c
CommitLineData
9fdf0c29
DG		 1/*
2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
3 *
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 *
26 */
0d75590d 27#include "qemu/osdep.h"
da34e65c 28#include "qapi/error.h"
9c17d615 29#include "sysemu/sysemu.h"
e35704ba 30#include "sysemu/numa.h"
83c9f4ca 31#include "hw/hw.h"
03dd024f 32#include "qemu/log.h"
71461b0f 33#include "hw/fw-path-provider.h"
9fdf0c29 34#include "elf.h"
1422e32d 35#include "net/net.h"
ad440b4a 36#include "sysemu/device_tree.h"
fa1d36df 37#include "sysemu/block-backend.h"
9c17d615
PB		 38#include "sysemu/cpus.h"
39#include "sysemu/kvm.h"
c20d332a 40#include "sysemu/device_tree.h"
e97c3636 41#include "kvm_ppc.h"
ff14e817 42#include "migration/migration.h"
4be21d56 43#include "mmu-hash64.h"
3794d548 44#include "qom/cpu.h"
9fdf0c29
DG		 45
46#include "hw/boards.h"
0d09e41a 47#include "hw/ppc/ppc.h"
9fdf0c29
DG		 48#include "hw/loader.h"
49
7804c353 50#include "hw/ppc/fdt.h"
0d09e41a
PB		 51#include "hw/ppc/spapr.h"
52#include "hw/ppc/spapr_vio.h"
53#include "hw/pci-host/spapr.h"
54#include "hw/ppc/xics.h"
a2cb15b0 55#include "hw/pci/msi.h"
9fdf0c29 56
83c9f4ca 57#include "hw/pci/pci.h"
71461b0f
AK		 58#include "hw/scsi/scsi.h"
59#include "hw/virtio/virtio-scsi.h"
f61b4bed 60
022c62cb 61#include "exec/address-spaces.h"
35139a59 62#include "hw/usb.h"
1de7afc9 63#include "qemu/config-file.h"
135a129a 64#include "qemu/error-report.h"
2a6593cb 65#include "trace.h"
34316482 66#include "hw/nmi.h"
890c2b77 67
68a27b20 68#include "hw/compat.h"
f348b6d1 69#include "qemu/cutils.h"
94a94e4c 70#include "hw/ppc/spapr_cpu_core.h"
2474bfd4 71#include "qmp-commands.h"
68a27b20 72
9fdf0c29
DG		 73#include <libfdt.h>
74
4d8d5467
BH		 75/* SLOF memory layout:
76 *
77 * SLOF raw image loaded at 0, copies its romfs right below the flat
78 * device-tree, then position SLOF itself 31M below that
79 *
80 * So we set FW_OVERHEAD to 40MB which should account for all of that
81 * and more
82 *
83 * We load our kernel at 4M, leaving space for SLOF initial image
84 */
38b02bd8 85#define FDT_MAX_SIZE 0x100000
39ac8455 86#define RTAS_MAX_SIZE 0x10000
b7d1f77a 87#define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */
a9f8ad8f
DG		 88#define FW_MAX_SIZE 0x400000
89#define FW_FILE_NAME "slof.bin"
4d8d5467
BH		 90#define FW_OVERHEAD 0x2800000
91#define KERNEL_LOAD_ADDR FW_MAX_SIZE
a9f8ad8f 92
4d8d5467 93#define MIN_RMA_SLOF 128UL
9fdf0c29 94
0c103f8e
DG		 95#define PHANDLE_XICP 0x00001111
96
7f763a5d
DG		 97#define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift))
98
c04d6cfa 99static XICSState *try_create_xics(const char *type, int nr_servers,
34f2af3d 100 int nr_irqs, Error **errp)
c04d6cfa 101{
34f2af3d 102 Error *err = NULL;
c04d6cfa
AL		 103 DeviceState *dev;
104
105 dev = qdev_create(NULL, type);
106 qdev_prop_set_uint32(dev, "nr_servers", nr_servers);
107 qdev_prop_set_uint32(dev, "nr_irqs", nr_irqs);
34f2af3d
MA		 108 object_property_set_bool(OBJECT(dev), true, "realized", &err);
109 if (err) {
110 error_propagate(errp, err);
111 object_unparent(OBJECT(dev));
c04d6cfa
AL		 112 return NULL;
113 }
5a3d7b23 114 return XICS_COMMON(dev);
c04d6cfa
AL		 115}
116
446f16a6 117static XICSState *xics_system_init(MachineState *machine,
1e49182d 118 int nr_servers, int nr_irqs, Error **errp)
c04d6cfa 119{
27f24582 120 XICSState *xics = NULL;
c04d6cfa 121
11ad93f6 122 if (kvm_enabled()) {
34f2af3d
MA		 123 Error *err = NULL;
124
446f16a6 125 if (machine_kernel_irqchip_allowed(machine)) {
27f24582
BH		 126 xics = try_create_xics(TYPE_XICS_SPAPR_KVM, nr_servers, nr_irqs,
127 &err);
11ad93f6 128 }
27f24582 129 if (machine_kernel_irqchip_required(machine) && !xics) {
b83baa60
MA		 130 error_reportf_err(err,
131 "kernel_irqchip requested but unavailable: ");
132 } else {
133 error_free(err);
11ad93f6
DG		 134 }
135 }
136
27f24582
BH		 137 if (!xics) {
138 xics = try_create_xics(TYPE_XICS_SPAPR, nr_servers, nr_irqs, errp);
c04d6cfa
AL		 139 }
140
27f24582 141 return xics;
c04d6cfa
AL		 142}
143
833d4668
AK		 144static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
145 int smt_threads)
146{
147 int i, ret = 0;
148 uint32_t servers_prop[smt_threads];
149 uint32_t gservers_prop[smt_threads * 2];
150 int index = ppc_get_vcpu_dt_id(cpu);
151
6d9412ea 152 if (cpu->cpu_version) {
4bce526e 153 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->cpu_version);
6d9412ea
AK		 154 if (ret < 0) {
155 return ret;
156 }
157 }
158
833d4668
AK		 159 /* Build interrupt servers and gservers properties */
160 for (i = 0; i < smt_threads; i++) {
161 servers_prop[i] = cpu_to_be32(index + i);
162 /* Hack, direct the group queues back to cpu 0 */
163 gservers_prop[i*2] = cpu_to_be32(index + i);
164 gservers_prop[i*2 + 1] = 0;
165 }
166 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
167 servers_prop, sizeof(servers_prop));
168 if (ret < 0) {
169 return ret;
170 }
171 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s",
172 gservers_prop, sizeof(gservers_prop));
173
174 return ret;
175}
176
0da6f3fe
BR		 177static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, CPUState *cs)
178{
179 int ret = 0;
180 PowerPCCPU *cpu = POWERPC_CPU(cs);
181 int index = ppc_get_vcpu_dt_id(cpu);
182 uint32_t associativity[] = {cpu_to_be32(0x5),
183 cpu_to_be32(0x0),
184 cpu_to_be32(0x0),
185 cpu_to_be32(0x0),
186 cpu_to_be32(cs->numa_node),
187 cpu_to_be32(index)};
188
189 /* Advertise NUMA via ibm,associativity */
190 if (nb_numa_nodes > 1) {
191 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity,
192 sizeof(associativity));
193 }
194
195 return ret;
196}
197
28e02042 198static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr)
6e806cc3 199{
82677ed2
AK		 200 int ret = 0, offset, cpus_offset;
201 CPUState *cs;
6e806cc3
BR		 202 char cpu_model[32];
203 int smt = kvmppc_smt_threads();
7f763a5d 204 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
6e806cc3 205
82677ed2
AK		 206 CPU_FOREACH(cs) {
207 PowerPCCPU *cpu = POWERPC_CPU(cs);
208 DeviceClass *dc = DEVICE_GET_CLASS(cs);
209 int index = ppc_get_vcpu_dt_id(cpu);
6e806cc3 210
0f20ba62 211 if ((index % smt) != 0) {
6e806cc3
BR		 212 continue;
213 }
214
82677ed2 215 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index);
6e806cc3 216
82677ed2
AK		 217 cpus_offset = fdt_path_offset(fdt, "/cpus");
218 if (cpus_offset < 0) {
219 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"),
220 "cpus");
221 if (cpus_offset < 0) {
222 return cpus_offset;
223 }
224 }
225 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model);
6e806cc3 226 if (offset < 0) {
82677ed2
AK		 227 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model);
228 if (offset < 0) {
229 return offset;
230 }
6e806cc3
BR		 231 }
232
7f763a5d
DG		 233 ret = fdt_setprop(fdt, offset, "ibm,pft-size",
234 pft_size_prop, sizeof(pft_size_prop));
6e806cc3
BR		 235 if (ret < 0) {
236 return ret;
237 }
833d4668 238
0da6f3fe
BR		 239 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cs);
240 if (ret < 0) {
241 return ret;
242 }
243
82677ed2 244 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu,
2a48d993 245 ppc_get_compat_smt_threads(cpu));
833d4668
AK		 246 if (ret < 0) {
247 return ret;
248 }
6e806cc3
BR		 249 }
250 return ret;
251}
252
b082d65a
AK		 253static hwaddr spapr_node0_size(void)
254{
fb164994
DG		 255 MachineState *machine = MACHINE(qdev_get_machine());
256
b082d65a
AK		 257 if (nb_numa_nodes) {
258 int i;
259 for (i = 0; i < nb_numa_nodes; ++i) {
260 if (numa_info[i].node_mem) {
fb164994
DG		 261 return MIN(pow2floor(numa_info[i].node_mem),
262 machine->ram_size);
b082d65a
AK		 263 }
264 }
265 }
fb164994 266 return machine->ram_size;
b082d65a
AK		 267}
268
a1d59c0f
AK		 269static void add_str(GString *s, const gchar *s1)
270{
271 g_string_append_len(s, s1, strlen(s1) + 1);
272}
7f763a5d 273
3bbf37f2 274static void *spapr_create_fdt_skel(hwaddr initrd_base,
a8170e5e
AK		 275 hwaddr initrd_size,
276 hwaddr kernel_size,
16457e7f 277 bool little_endian,
74d042e5
DG		 278 const char *kernel_cmdline,
279 uint32_t epow_irq)
9fdf0c29
DG		 280{
281 void *fdt;
9fdf0c29
DG		 282 uint32_t start_prop = cpu_to_be32(initrd_base);
283 uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size);
a1d59c0f
AK		 284 GString *hypertas = g_string_sized_new(256);
285 GString *qemu_hypertas = g_string_sized_new(256);
7f763a5d 286 uint32_t refpoints[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)};
9e734e3d 287 uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(max_cpus)};
6e806cc3 288 unsigned char vec5[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80};
ef951443 289 char *buf;
9fdf0c29 290
a1d59c0f
AK		 291 add_str(hypertas, "hcall-pft");
292 add_str(hypertas, "hcall-term");
293 add_str(hypertas, "hcall-dabr");
294 add_str(hypertas, "hcall-interrupt");
295 add_str(hypertas, "hcall-tce");
296 add_str(hypertas, "hcall-vio");
297 add_str(hypertas, "hcall-splpar");
298 add_str(hypertas, "hcall-bulk");
299 add_str(hypertas, "hcall-set-mode");
6cc09e26
TH		 300 add_str(hypertas, "hcall-sprg0");
301 add_str(hypertas, "hcall-copy");
302 add_str(hypertas, "hcall-debug");
a1d59c0f
AK		 303 add_str(qemu_hypertas, "hcall-memop1");
304
7267c094 305 fdt = g_malloc0(FDT_MAX_SIZE);
9fdf0c29
DG		 306 _FDT((fdt_create(fdt, FDT_MAX_SIZE)));
307
4d8d5467
BH		 308 if (kernel_size) {
309 _FDT((fdt_add_reservemap_entry(fdt, KERNEL_LOAD_ADDR, kernel_size)));
310 }
311 if (initrd_size) {
312 _FDT((fdt_add_reservemap_entry(fdt, initrd_base, initrd_size)));
313 }
9fdf0c29
DG		 314 _FDT((fdt_finish_reservemap(fdt)));
315
316 /* Root node */
317 _FDT((fdt_begin_node(fdt, "")));
318 _FDT((fdt_property_string(fdt, "device_type", "chrp")));
5d73dd66 319 _FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)")));
d63919c9 320 _FDT((fdt_property_string(fdt, "compatible", "qemu,pseries")));
9fdf0c29 321
ef951443
ND		 322 /*
323 * Add info to guest to indentify which host is it being run on
324 * and what is the uuid of the guest
325 */
326 if (kvmppc_get_host_model(&buf)) {
327 _FDT((fdt_property_string(fdt, "host-model", buf)));
328 g_free(buf);
329 }
330 if (kvmppc_get_host_serial(&buf)) {
331 _FDT((fdt_property_string(fdt, "host-serial", buf)));
332 g_free(buf);
333 }
334
335 buf = g_strdup_printf(UUID_FMT, qemu_uuid[0], qemu_uuid[1],
336 qemu_uuid[2], qemu_uuid[3], qemu_uuid[4],
337 qemu_uuid[5], qemu_uuid[6], qemu_uuid[7],
338 qemu_uuid[8], qemu_uuid[9], qemu_uuid[10],
339 qemu_uuid[11], qemu_uuid[12], qemu_uuid[13],
340 qemu_uuid[14], qemu_uuid[15]);
341
342 _FDT((fdt_property_string(fdt, "vm,uuid", buf)));
3dc0a66d
AK		 343 if (qemu_uuid_set) {
344 _FDT((fdt_property_string(fdt, "system-id", buf)));
345 }
ef951443
ND		 346 g_free(buf);
347
2c1aaa81
SB		 348 if (qemu_get_vm_name()) {
349 _FDT((fdt_property_string(fdt, "ibm,partition-name",
350 qemu_get_vm_name())));
351 }
352
9fdf0c29
DG		 353 _FDT((fdt_property_cell(fdt, "#address-cells", 0x2)));
354 _FDT((fdt_property_cell(fdt, "#size-cells", 0x2)));
355
356 /* /chosen */
357 _FDT((fdt_begin_node(fdt, "chosen")));
358
6e806cc3
BR		 359 /* Set Form1_affinity */
360 _FDT((fdt_property(fdt, "ibm,architecture-vec-5", vec5, sizeof(vec5))));
361
9fdf0c29
DG		 362 _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline)));
363 _FDT((fdt_property(fdt, "linux,initrd-start",
364 &start_prop, sizeof(start_prop))));
365 _FDT((fdt_property(fdt, "linux,initrd-end",
366 &end_prop, sizeof(end_prop))));
4d8d5467
BH		 367 if (kernel_size) {
368 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR),
369 cpu_to_be64(kernel_size) };
9fdf0c29 370
4d8d5467 371 _FDT((fdt_property(fdt, "qemu,boot-kernel", &kprop, sizeof(kprop))));
16457e7f
BH		 372 if (little_endian) {
373 _FDT((fdt_property(fdt, "qemu,boot-kernel-le", NULL, 0)));
374 }
4d8d5467 375 }
cc84c0f3
AS		 376 if (boot_menu) {
377 _FDT((fdt_property_cell(fdt, "qemu,boot-menu", boot_menu)));
378 }
f28359d8
LZ		 379 _FDT((fdt_property_cell(fdt, "qemu,graphic-width", graphic_width)));
380 _FDT((fdt_property_cell(fdt, "qemu,graphic-height", graphic_height)));
381 _FDT((fdt_property_cell(fdt, "qemu,graphic-depth", graphic_depth)));
3384f95c 382
9fdf0c29
DG		 383 _FDT((fdt_end_node(fdt)));
384
f43e3525
DG		 385 /* RTAS */
386 _FDT((fdt_begin_node(fdt, "rtas")));
387
da95324e
AK		 388 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
389 add_str(hypertas, "hcall-multi-tce");
390 }
a1d59c0f
AK		 391 _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas->str,
392 hypertas->len)));
393 g_string_free(hypertas, TRUE);
394 _FDT((fdt_property(fdt, "qemu,hypertas-functions", qemu_hypertas->str,
395 qemu_hypertas->len)));
396 g_string_free(qemu_hypertas, TRUE);
f43e3525 397
6e806cc3
BR		 398 _FDT((fdt_property(fdt, "ibm,associativity-reference-points",
399 refpoints, sizeof(refpoints))));
400
74d042e5 401 _FDT((fdt_property_cell(fdt, "rtas-error-log-max", RTAS_ERROR_LOG_MAX)));
79853e18
TD		 402 _FDT((fdt_property_cell(fdt, "rtas-event-scan-rate",
403 RTAS_EVENT_SCAN_RATE)));
74d042e5 404
226419d6 405 if (msi_nonbroken) {
a95f9922
SB		 406 _FDT((fdt_property(fdt, "ibm,change-msix-capable", NULL, 0)));
407 }
408
2e14072f 409 /*
9d632f5f 410 * According to PAPR, rtas ibm,os-term does not guarantee a return
2e14072f
ND		 411 * back to the guest cpu.
412 *
413 * While an additional ibm,extended-os-term property indicates that
414 * rtas call return will always occur. Set this property.
415 */
416 _FDT((fdt_property(fdt, "ibm,extended-os-term", NULL, 0)));
417
f43e3525
DG		 418 _FDT((fdt_end_node(fdt)));
419
b5cec4c5 420 /* interrupt controller */
9dfef5aa 421 _FDT((fdt_begin_node(fdt, "interrupt-controller")));
b5cec4c5
DG		 422
423 _FDT((fdt_property_string(fdt, "device_type",
424 "PowerPC-External-Interrupt-Presentation")));
425 _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp")));
b5cec4c5
DG		 426 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));
427 _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges",
428 interrupt_server_ranges_prop,
429 sizeof(interrupt_server_ranges_prop))));
0c103f8e
DG		 430 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 2)));
431 _FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP)));
432 _FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP)));
b5cec4c5
DG		 433
434 _FDT((fdt_end_node(fdt)));
435
4040ab72
DG		 436 /* vdevice */
437 _FDT((fdt_begin_node(fdt, "vdevice")));
438
439 _FDT((fdt_property_string(fdt, "device_type", "vdevice")));
440 _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice")));
441 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1)));
442 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0)));
b5cec4c5
DG		 443 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2)));
444 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));
4040ab72
DG		 445
446 _FDT((fdt_end_node(fdt)));
447
74d042e5
DG		 448 /* event-sources */
449 spapr_events_fdt_skel(fdt, epow_irq);
450
f7d69146
AG		 451 /* /hypervisor node */
452 if (kvm_enabled()) {
453 uint8_t hypercall[16];
454
455 /* indicate KVM hypercall interface */
456 _FDT((fdt_begin_node(fdt, "hypervisor")));
457 _FDT((fdt_property_string(fdt, "compatible", "linux,kvm")));
458 if (kvmppc_has_cap_fixup_hcalls()) {
459 /*
460 * Older KVM versions with older guest kernels were broken with the
461 * magic page, don't allow the guest to map it.
462 */
0ddbd053
AK		 463 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall,
464 sizeof(hypercall))) {
465 _FDT((fdt_property(fdt, "hcall-instructions", hypercall,
466 sizeof(hypercall))));
467 }
f7d69146
AG		 468 }
469 _FDT((fdt_end_node(fdt)));
470 }
471
9fdf0c29
DG		 472 _FDT((fdt_end_node(fdt))); /* close root node */
473 _FDT((fdt_finish(fdt)));
474
a3467baa
DG		 475 return fdt;
476}
477
03d196b7 478static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start,
26a8c353
AK		 479 hwaddr size)
480{
481 uint32_t associativity[] = {
482 cpu_to_be32(0x4), /* length */
483 cpu_to_be32(0x0), cpu_to_be32(0x0),
c3b4f589 484 cpu_to_be32(0x0), cpu_to_be32(nodeid)
26a8c353
AK		 485 };
486 char mem_name[32];
487 uint64_t mem_reg_property[2];
488 int off;
489
490 mem_reg_property[0] = cpu_to_be64(start);
491 mem_reg_property[1] = cpu_to_be64(size);
492
493 sprintf(mem_name, "memory@" TARGET_FMT_lx, start);
494 off = fdt_add_subnode(fdt, 0, mem_name);
495 _FDT(off);
496 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
497 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
498 sizeof(mem_reg_property))));
499 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,
500 sizeof(associativity))));
03d196b7 501 return off;
26a8c353
AK		 502}
503
28e02042 504static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt)
7f763a5d 505{
fb164994 506 MachineState *machine = MACHINE(spapr);
7db8a127
AK		 507 hwaddr mem_start, node_size;
508 int i, nb_nodes = nb_numa_nodes;
509 NodeInfo *nodes = numa_info;
510 NodeInfo ramnode;
511
512 /* No NUMA nodes, assume there is just one node with whole RAM */
513 if (!nb_numa_nodes) {
514 nb_nodes = 1;
fb164994 515 ramnode.node_mem = machine->ram_size;
7db8a127 516 nodes = &ramnode;
5fe269b1 517 }
7f763a5d 518
7db8a127
AK		 519 for (i = 0, mem_start = 0; i < nb_nodes; ++i) {
520 if (!nodes[i].node_mem) {
521 continue;
522 }
fb164994 523 if (mem_start >= machine->ram_size) {
5fe269b1
PM		 524 node_size = 0;
525 } else {
7db8a127 526 node_size = nodes[i].node_mem;
fb164994
DG		 527 if (node_size > machine->ram_size - mem_start) {
528 node_size = machine->ram_size - mem_start;
5fe269b1
PM		 529 }
530 }
7db8a127
AK		 531 if (!mem_start) {
532 /* ppc_spapr_init() checks for rma_size <= node0_size already */
e8f986fc 533 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size);
7db8a127
AK		 534 mem_start += spapr->rma_size;
535 node_size -= spapr->rma_size;
536 }
6010818c
AK		 537 for ( ; node_size; ) {
538 hwaddr sizetmp = pow2floor(node_size);
539
540 /* mem_start != 0 here */
541 if (ctzl(mem_start) < ctzl(sizetmp)) {
542 sizetmp = 1ULL << ctzl(mem_start);
543 }
544
545 spapr_populate_memory_node(fdt, i, mem_start, sizetmp);
546 node_size -= sizetmp;
547 mem_start += sizetmp;
548 }
7f763a5d
DG		 549 }
550
551 return 0;
552}
553
0da6f3fe
BR		 554static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
555 sPAPRMachineState *spapr)
556{
557 PowerPCCPU *cpu = POWERPC_CPU(cs);
558 CPUPPCState *env = &cpu->env;
559 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
560 int index = ppc_get_vcpu_dt_id(cpu);
561 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
562 0xffffffff, 0xffffffff};
afd10a0f
BR		 563 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq()
564 : SPAPR_TIMEBASE_FREQ;
0da6f3fe
BR		 565 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
566 uint32_t page_sizes_prop[64];
567 size_t page_sizes_prop_size;
22419c2a 568 uint32_t vcpus_per_socket = smp_threads * smp_cores;
0da6f3fe 569 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
af81cf32
BR		 570 sPAPRDRConnector *drc;
571 sPAPRDRConnectorClass *drck;
572 int drc_index;
573
574 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index);
575 if (drc) {
576 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
577 drc_index = drck->get_index(drc);
578 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index)));
579 }
0da6f3fe 580
90da0d5a
BH		 581 /* Note: we keep CI large pages off for now because a 64K capable guest
582 * provisioned with large pages might otherwise try to map a qemu
583 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages
584 * even if that qemu runs on a 4k host.
585 *
586 * We can later add this bit back when we are confident this is not
587 * an issue (!HV KVM or 64K host)
588 */
589 uint8_t pa_features_206[] = { 6, 0,
590 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
591 uint8_t pa_features_207[] = { 24, 0,
592 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
593 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
594 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
595 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
596 uint8_t *pa_features;
597 size_t pa_size;
598
0da6f3fe
BR		 599 _FDT((fdt_setprop_cell(fdt, offset, "reg", index)));
600 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
601
602 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
603 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
604 env->dcache_line_size)));
605 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
606 env->dcache_line_size)));
607 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
608 env->icache_line_size)));
609 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
610 env->icache_line_size)));
611
612 if (pcc->l1_dcache_size) {
613 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
614 pcc->l1_dcache_size)));
615 } else {
ce9863b7 616 error_report("Warning: Unknown L1 dcache size for cpu");
0da6f3fe
BR		 617 }
618 if (pcc->l1_icache_size) {
619 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
620 pcc->l1_icache_size)));
621 } else {
ce9863b7 622 error_report("Warning: Unknown L1 icache size for cpu");
0da6f3fe
BR		 623 }
624
625 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
626 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
fd5da5c4 627 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr)));
0da6f3fe
BR		 628 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr)));
629 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
630 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
631
632 if (env->spr_cb[SPR_PURR].oea_read) {
633 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
634 }
635
636 if (env->mmu_model & POWERPC_MMU_1TSEG) {
637 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
638 segs, sizeof(segs))));
639 }
640
641 /* Advertise VMX/VSX (vector extensions) if available
642 * 0 / no property == no vector extensions
643 * 1 == VMX / Altivec available
644 * 2 == VSX available */
645 if (env->insns_flags & PPC_ALTIVEC) {
646 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
647
648 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
649 }
650
651 /* Advertise DFP (Decimal Floating Point) if available
652 * 0 / no property == no DFP
653 * 1 == DFP available */
654 if (env->insns_flags2 & PPC2_DFP) {
655 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
656 }
657
3654fa95 658 page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop,
0da6f3fe
BR		 659 sizeof(page_sizes_prop));
660 if (page_sizes_prop_size) {
661 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
662 page_sizes_prop, page_sizes_prop_size)));
663 }
664
90da0d5a
BH		 665 /* Do the ibm,pa-features property, adjust it for ci-large-pages */
666 if (env->mmu_model == POWERPC_MMU_2_06) {
667 pa_features = pa_features_206;
668 pa_size = sizeof(pa_features_206);
669 } else /* env->mmu_model == POWERPC_MMU_2_07 */ {
670 pa_features = pa_features_207;
671 pa_size = sizeof(pa_features_207);
672 }
673 if (env->ci_large_pages) {
674 pa_features[3] |= 0x20;
675 }
676 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size)));
677
0da6f3fe 678 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id",
22419c2a 679 cs->cpu_index / vcpus_per_socket)));
0da6f3fe
BR		 680
681 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size",
682 pft_size_prop, sizeof(pft_size_prop))));
683
684 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cs));
685
686 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu,
687 ppc_get_compat_smt_threads(cpu)));
688}
689
690static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr)
691{
692 CPUState *cs;
693 int cpus_offset;
694 char *nodename;
695 int smt = kvmppc_smt_threads();
696
697 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
698 _FDT(cpus_offset);
699 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
700 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
701
702 /*
703 * We walk the CPUs in reverse order to ensure that CPU DT nodes
704 * created by fdt_add_subnode() end up in the right order in FDT
705 * for the guest kernel the enumerate the CPUs correctly.
706 */
707 CPU_FOREACH_REVERSE(cs) {
708 PowerPCCPU *cpu = POWERPC_CPU(cs);
709 int index = ppc_get_vcpu_dt_id(cpu);
710 DeviceClass *dc = DEVICE_GET_CLASS(cs);
711 int offset;
712
713 if ((index % smt) != 0) {
714 continue;
715 }
716
717 nodename = g_strdup_printf("%s@%x", dc->fw_name, index);
718 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
719 g_free(nodename);
720 _FDT(offset);
721 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
722 }
723
724}
725
03d196b7
BR		 726/*
727 * Adds ibm,dynamic-reconfiguration-memory node.
728 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation
729 * of this device tree node.
730 */
731static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt)
732{
733 MachineState *machine = MACHINE(spapr);
734 int ret, i, offset;
735 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
736 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)};
d0e5a8f2
BR		 737 uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size;
738 uint32_t nr_lmbs = (spapr->hotplug_memory.base +
739 memory_region_size(&spapr->hotplug_memory.mr)) /
740 lmb_size;
03d196b7 741 uint32_t *int_buf, *cur_index, buf_len;
6663864e 742 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1;
03d196b7 743
16c25aef 744 /*
d0e5a8f2 745 * Don't create the node if there is no hotpluggable memory
16c25aef 746 */
d0e5a8f2 747 if (machine->ram_size == machine->maxram_size) {
16c25aef
BR		 748 return 0;
749 }
750
ef001f06
TH		 751 /*
752 * Allocate enough buffer size to fit in ibm,dynamic-memory
753 * or ibm,associativity-lookup-arrays
754 */
755 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2)
756 * sizeof(uint32_t);
03d196b7
BR		 757 cur_index = int_buf = g_malloc0(buf_len);
758
759 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory");
760
761 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size,
762 sizeof(prop_lmb_size));
763 if (ret < 0) {
764 goto out;
765 }
766
767 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff);
768 if (ret < 0) {
769 goto out;
770 }
771
772 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0);
773 if (ret < 0) {
774 goto out;
775 }
776
777 /* ibm,dynamic-memory */
778 int_buf[0] = cpu_to_be32(nr_lmbs);
779 cur_index++;
780 for (i = 0; i < nr_lmbs; i++) {
d0e5a8f2 781 uint64_t addr = i * lmb_size;
03d196b7
BR		 782 uint32_t *dynamic_memory = cur_index;
783
d0e5a8f2
BR		 784 if (i >= hotplug_lmb_start) {
785 sPAPRDRConnector *drc;
786 sPAPRDRConnectorClass *drck;
787
788 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, i);
789 g_assert(drc);
790 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
791
792 dynamic_memory[0] = cpu_to_be32(addr >> 32);
793 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
794 dynamic_memory[2] = cpu_to_be32(drck->get_index(drc));
795 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
796 dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL));
797 if (memory_region_present(get_system_memory(), addr)) {
798 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED);
799 } else {
800 dynamic_memory[5] = cpu_to_be32(0);
801 }
03d196b7 802 } else {
d0e5a8f2
BR		 803 /*
804 * LMB information for RMA, boot time RAM and gap b/n RAM and
805 * hotplug memory region -- all these are marked as reserved
806 * and as having no valid DRC.
807 */
808 dynamic_memory[0] = cpu_to_be32(addr >> 32);
809 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
810 dynamic_memory[2] = cpu_to_be32(0);
811 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
812 dynamic_memory[4] = cpu_to_be32(-1);
813 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED |
814 SPAPR_LMB_FLAGS_DRC_INVALID);
03d196b7
BR		 815 }
816
817 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE;
818 }
819 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len);
820 if (ret < 0) {
821 goto out;
822 }
823
824 /* ibm,associativity-lookup-arrays */
825 cur_index = int_buf;
6663864e 826 int_buf[0] = cpu_to_be32(nr_nodes);
03d196b7
BR		 827 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */
828 cur_index += 2;
6663864e 829 for (i = 0; i < nr_nodes; i++) {
03d196b7
BR		 830 uint32_t associativity[] = {
831 cpu_to_be32(0x0),
832 cpu_to_be32(0x0),
833 cpu_to_be32(0x0),
834 cpu_to_be32(i)
835 };
836 memcpy(cur_index, associativity, sizeof(associativity));
837 cur_index += 4;
838 }
839 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf,
840 (cur_index - int_buf) * sizeof(uint32_t));
841out:
842 g_free(int_buf);
843 return ret;
844}
845
846int spapr_h_cas_compose_response(sPAPRMachineState *spapr,
847 target_ulong addr, target_ulong size,
848 bool cpu_update, bool memory_update)
849{
850 void *fdt, *fdt_skel;
851 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 };
852 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine());
853
854 size -= sizeof(hdr);
855
856 /* Create sceleton */
857 fdt_skel = g_malloc0(size);
858 _FDT((fdt_create(fdt_skel, size)));
859 _FDT((fdt_begin_node(fdt_skel, "")));
860 _FDT((fdt_end_node(fdt_skel)));
861 _FDT((fdt_finish(fdt_skel)));
862 fdt = g_malloc0(size);
863 _FDT((fdt_open_into(fdt_skel, fdt, size)));
864 g_free(fdt_skel);
865
866 /* Fixup cpu nodes */
867 if (cpu_update) {
868 _FDT((spapr_fixup_cpu_dt(fdt, spapr)));
869 }
870
16c25aef 871 /* Generate ibm,dynamic-reconfiguration-memory node if required */
03d196b7
BR		 872 if (memory_update && smc->dr_lmb_enabled) {
873 _FDT((spapr_populate_drconf_memory(spapr, fdt)));
03d196b7
BR		 874 }
875
876 /* Pack resulting tree */
877 _FDT((fdt_pack(fdt)));
878
879 if (fdt_totalsize(fdt) + sizeof(hdr) > size) {
880 trace_spapr_cas_failed(size);
881 return -1;
882 }
883
884 cpu_physical_memory_write(addr, &hdr, sizeof(hdr));
885 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt));
886 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr));
887 g_free(fdt);
888
889 return 0;
890}
891
28e02042 892static void spapr_finalize_fdt(sPAPRMachineState *spapr,
a8170e5e
AK		 893 hwaddr fdt_addr,
894 hwaddr rtas_addr,
895 hwaddr rtas_size)
a3467baa 896{
5b2128d2 897 MachineState *machine = MACHINE(qdev_get_machine());
3c0c47e3 898 MachineClass *mc = MACHINE_GET_CLASS(machine);
c20d332a 899 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
5b2128d2 900 const char *boot_device = machine->boot_order;
71461b0f
AK		 901 int ret, i;
902 size_t cb = 0;
903 char *bootlist;
a3467baa 904 void *fdt;
3384f95c 905 sPAPRPHBState *phb;
a3467baa 906
7267c094 907 fdt = g_malloc(FDT_MAX_SIZE);
a3467baa
DG		 908
909 /* open out the base tree into a temp buffer for the final tweaks */
910 _FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE)));
4040ab72 911
e8f986fc
BR		 912 ret = spapr_populate_memory(spapr, fdt);
913 if (ret < 0) {
ce9863b7 914 error_report("couldn't setup memory nodes in fdt");
e8f986fc 915 exit(1);
7f763a5d
DG		 916 }
917
4040ab72
DG		 918 ret = spapr_populate_vdevice(spapr->vio_bus, fdt);
919 if (ret < 0) {
ce9863b7 920 error_report("couldn't setup vio devices in fdt");
4040ab72
DG		 921 exit(1);
922 }
923
4d9392be
TH		 924 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) {
925 ret = spapr_rng_populate_dt(fdt);
926 if (ret < 0) {
ce9863b7 927 error_report("could not set up rng device in the fdt");
4d9392be
TH		 928 exit(1);
929 }
930 }
931
3384f95c 932 QLIST_FOREACH(phb, &spapr->phbs, list) {
e0fdbd7c 933 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt);
da34fed7
TH		 934 if (ret < 0) {
935 error_report("couldn't setup PCI devices in fdt");
936 exit(1);
937 }
3384f95c
DG		 938 }
939
39ac8455
DG		 940 /* RTAS */
941 ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size);
942 if (ret < 0) {
ce9863b7 943 error_report("Couldn't set up RTAS device tree properties");
39ac8455
DG		 944 }
945
0da6f3fe
BR		 946 /* cpus */
947 spapr_populate_cpus_dt_node(fdt, spapr);
6e806cc3 948
71461b0f
AK		 949 bootlist = get_boot_devices_list(&cb, true);
950 if (cb && bootlist) {
951 int offset = fdt_path_offset(fdt, "/chosen");
952 if (offset < 0) {
953 exit(1);
954 }
955 for (i = 0; i < cb; i++) {
956 if (bootlist[i] == '\n') {
957 bootlist[i] = ' ';
958 }
959
960 }
961 ret = fdt_setprop_string(fdt, offset, "qemu,boot-list", bootlist);
962 }
963
5b2128d2
AG		 964 if (boot_device && strlen(boot_device)) {
965 int offset = fdt_path_offset(fdt, "/chosen");
966
967 if (offset < 0) {
968 exit(1);
969 }
970 fdt_setprop_string(fdt, offset, "qemu,boot-device", boot_device);
971 }
972
3fc5acde 973 if (!spapr->has_graphics) {
f28359d8
LZ		 974 spapr_populate_chosen_stdout(fdt, spapr->vio_bus);
975 }
68f3a94c 976
c20d332a
BR		 977 if (smc->dr_lmb_enabled) {
978 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB));
979 }
980
3c0c47e3 981 if (mc->query_hotpluggable_cpus) {
af81cf32
BR		 982 int offset = fdt_path_offset(fdt, "/cpus");
983 ret = spapr_drc_populate_dt(fdt, offset, NULL,
984 SPAPR_DR_CONNECTOR_TYPE_CPU);
985 if (ret < 0) {
986 error_report("Couldn't set up CPU DR device tree properties");
987 exit(1);
988 }
989 }
990
4040ab72
DG		 991 _FDT((fdt_pack(fdt)));
992
4d8d5467 993 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) {
730fce59
TH		 994 error_report("FDT too big ! 0x%x bytes (max is 0x%x)",
995 fdt_totalsize(fdt), FDT_MAX_SIZE);
4d8d5467
BH		 996 exit(1);
997 }
998
ad440b4a 999 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
a3467baa 1000 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt));
9fdf0c29 1001
a21a7a70 1002 g_free(bootlist);
7267c094 1003 g_free(fdt);
9fdf0c29
DG		 1004}
1005
1006static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
1007{
1008 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
1009}
1010
1b14670a 1011static void emulate_spapr_hypercall(PowerPCCPU *cpu)
9fdf0c29 1012{
1b14670a
AF		 1013 CPUPPCState *env = &cpu->env;
1014
efcb9383
DG		 1015 if (msr_pr) {
1016 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1017 env->gpr[3] = H_PRIVILEGE;
1018 } else {
aa100fa4 1019 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]);
efcb9383 1020 }
9fdf0c29
DG		 1021}
1022
e6b8fd24
SMJ		 1023#define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1024#define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1025#define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1026#define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1027#define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1028
715c5407
DG		 1029/*
1030 * Get the fd to access the kernel htab, re-opening it if necessary
1031 */
1032static int get_htab_fd(sPAPRMachineState *spapr)
1033{
1034 if (spapr->htab_fd >= 0) {
1035 return spapr->htab_fd;
1036 }
1037
1038 spapr->htab_fd = kvmppc_get_htab_fd(false);
1039 if (spapr->htab_fd < 0) {
1040 error_report("Unable to open fd for reading hash table from KVM: %s",
1041 strerror(errno));
1042 }
1043
1044 return spapr->htab_fd;
1045}
1046
1047static void close_htab_fd(sPAPRMachineState *spapr)
1048{
1049 if (spapr->htab_fd >= 0) {
1050 close(spapr->htab_fd);
1051 }
1052 spapr->htab_fd = -1;
1053}
1054
8dfe8e7f
DG		 1055static int spapr_hpt_shift_for_ramsize(uint64_t ramsize)
1056{
1057 int shift;
1058
1059 /* We aim for a hash table of size 1/128 the size of RAM (rounded
1060 * up). The PAPR recommendation is actually 1/64 of RAM size, but
1061 * that's much more than is needed for Linux guests */
1062 shift = ctz64(pow2ceil(ramsize)) - 7;
1063 shift = MAX(shift, 18); /* Minimum architected size */
1064 shift = MIN(shift, 46); /* Maximum architected size */
1065 return shift;
1066}
1067
c5f54f3e
DG		 1068static void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift,
1069 Error **errp)
7f763a5d 1070{
c5f54f3e
DG		 1071 long rc;
1072
1073 /* Clean up any HPT info from a previous boot */
1074 g_free(spapr->htab);
1075 spapr->htab = NULL;
1076 spapr->htab_shift = 0;
1077 close_htab_fd(spapr);
1078
1079 rc = kvmppc_reset_htab(shift);
1080 if (rc < 0) {
1081 /* kernel-side HPT needed, but couldn't allocate one */
1082 error_setg_errno(errp, errno,
1083 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)",
1084 shift);
1085 /* This is almost certainly fatal, but if the caller really
1086 * wants to carry on with shift == 0, it's welcome to try */
1087 } else if (rc > 0) {
1088 /* kernel-side HPT allocated */
1089 if (rc != shift) {
1090 error_setg(errp,
1091 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)",
1092 shift, rc);
7735feda
BR		 1093 }
1094
7f763a5d 1095 spapr->htab_shift = shift;
c18ad9a5 1096 spapr->htab = NULL;
b817772a 1097 } else {
c5f54f3e
DG		 1098 /* kernel-side HPT not needed, allocate in userspace instead */
1099 size_t size = 1ULL << shift;
1100 int i;
b817772a 1101
c5f54f3e
DG		 1102 spapr->htab = qemu_memalign(size, size);
1103 if (!spapr->htab) {
1104 error_setg_errno(errp, errno,
1105 "Could not allocate HPT of order %d", shift);
1106 return;
7735feda
BR		 1107 }
1108
c5f54f3e
DG		 1109 memset(spapr->htab, 0, size);
1110 spapr->htab_shift = shift;
e6b8fd24 1111
c5f54f3e
DG		 1112 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) {
1113 DIRTY_HPTE(HPTE(spapr->htab, i));
e6b8fd24 1114 }
7f763a5d 1115 }
9fdf0c29
DG		 1116}
1117
9e3f9733
AG		 1118static int find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque)
1119{
1120 bool matched = false;
1121
1122 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
1123 matched = true;
1124 }
1125
1126 if (!matched) {
1127 error_report("Device %s is not supported by this machine yet.",
1128 qdev_fw_name(DEVICE(sbdev)));
1129 exit(1);
1130 }
1131
1132 return 0;
1133}
1134
c8787ad4 1135static void ppc_spapr_reset(void)
a3467baa 1136{
c5f54f3e
DG		 1137 MachineState *machine = MACHINE(qdev_get_machine());
1138 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
182735ef 1139 PowerPCCPU *first_ppc_cpu;
b7d1f77a 1140 uint32_t rtas_limit;
259186a7 1141
9e3f9733
AG		 1142 /* Check for unknown sysbus devices */
1143 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL);
1144
c5f54f3e
DG		 1145 /* Allocate and/or reset the hash page table */
1146 spapr_reallocate_hpt(spapr,
1147 spapr_hpt_shift_for_ramsize(machine->maxram_size),
1148 &error_fatal);
1149
1150 /* Update the RMA size if necessary */
1151 if (spapr->vrma_adjust) {
1152 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(),
1153 spapr->htab_shift);
1154 }
a3467baa 1155
c8787ad4 1156 qemu_devices_reset();
a3467baa 1157
b7d1f77a
BH		 1158 /*
1159 * We place the device tree and RTAS just below either the top of the RMA,
1160 * or just below 2GB, whichever is lowere, so that it can be
1161 * processed with 32-bit real mode code if necessary
1162 */
1163 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR);
1164 spapr->rtas_addr = rtas_limit - RTAS_MAX_SIZE;
1165 spapr->fdt_addr = spapr->rtas_addr - FDT_MAX_SIZE;
1166
a3467baa
DG		 1167 /* Load the fdt */
1168 spapr_finalize_fdt(spapr, spapr->fdt_addr, spapr->rtas_addr,
1169 spapr->rtas_size);
1170
b7d1f77a
BH		 1171 /* Copy RTAS over */
1172 cpu_physical_memory_write(spapr->rtas_addr, spapr->rtas_blob,
1173 spapr->rtas_size);
1174
a3467baa 1175 /* Set up the entry state */
182735ef
AF		 1176 first_ppc_cpu = POWERPC_CPU(first_cpu);
1177 first_ppc_cpu->env.gpr[3] = spapr->fdt_addr;
1178 first_ppc_cpu->env.gpr[5] = 0;
1179 first_cpu->halted = 0;
1b718907 1180 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT;
a3467baa
DG		 1181
1182}
1183
28e02042 1184static void spapr_create_nvram(sPAPRMachineState *spapr)
639e8102 1185{
2ff3de68 1186 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram");
3978b863 1187 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
639e8102 1188
3978b863 1189 if (dinfo) {
6231a6da
MA		 1190 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
1191 &error_fatal);
639e8102
DG		 1192 }
1193
1194 qdev_init_nofail(dev);
1195
1196 spapr->nvram = (struct sPAPRNVRAM *)dev;
1197}
1198
28e02042 1199static void spapr_rtc_create(sPAPRMachineState *spapr)
28df36a1
DG		 1200{
1201 DeviceState *dev = qdev_create(NULL, TYPE_SPAPR_RTC);
1202
1203 qdev_init_nofail(dev);
1204 spapr->rtc = dev;
74e5ae28
DG		 1205
1206 object_property_add_alias(qdev_get_machine(), "rtc-time",
1207 OBJECT(spapr->rtc), "date", NULL);
28df36a1
DG		 1208}
1209
8c57b867 1210/* Returns whether we want to use VGA or not */
14c6a894 1211static bool spapr_vga_init(PCIBus *pci_bus, Error **errp)
f28359d8 1212{
8c57b867 1213 switch (vga_interface_type) {
8c57b867 1214 case VGA_NONE:
7effdaa3
MW		 1215 return false;
1216 case VGA_DEVICE:
1217 return true;
1ddcae82 1218 case VGA_STD:
b798c190 1219 case VGA_VIRTIO:
1ddcae82 1220 return pci_vga_init(pci_bus) != NULL;
8c57b867 1221 default:
14c6a894
DG		 1222 error_setg(errp,
1223 "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1224 return false;
f28359d8 1225 }
f28359d8
LZ		 1226}
1227
880ae7de
DG		 1228static int spapr_post_load(void *opaque, int version_id)
1229{
28e02042 1230 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque;
880ae7de
DG		 1231 int err = 0;
1232
631b22ea 1233 /* In earlier versions, there was no separate qdev for the PAPR
880ae7de
DG		 1234 * RTC, so the RTC offset was stored directly in sPAPREnvironment.
1235 * So when migrating from those versions, poke the incoming offset
1236 * value into the RTC device */
1237 if (version_id < 3) {
1238 err = spapr_rtc_import_offset(spapr->rtc, spapr->rtc_offset);
1239 }
1240
1241 return err;
1242}
1243
1244static bool version_before_3(void *opaque, int version_id)
1245{
1246 return version_id < 3;
1247}
1248
4be21d56
DG		 1249static const VMStateDescription vmstate_spapr = {
1250 .name = "spapr",
880ae7de 1251 .version_id = 3,
4be21d56 1252 .minimum_version_id = 1,
880ae7de 1253 .post_load = spapr_post_load,
3aff6c2f 1254 .fields = (VMStateField[]) {
880ae7de
DG		 1255 /* used to be @next_irq */
1256 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4),
4be21d56
DG		 1257
1258 /* RTC offset */
28e02042 1259 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3),
880ae7de 1260
28e02042 1261 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2),
4be21d56
DG		 1262 VMSTATE_END_OF_LIST()
1263 },
1264};
1265
4be21d56
DG		 1266static int htab_save_setup(QEMUFile *f, void *opaque)
1267{
28e02042 1268 sPAPRMachineState *spapr = opaque;
4be21d56 1269
4be21d56
DG		 1270 /* "Iteration" header */
1271 qemu_put_be32(f, spapr->htab_shift);
1272
e68cb8b4
AK		 1273 if (spapr->htab) {
1274 spapr->htab_save_index = 0;
1275 spapr->htab_first_pass = true;
1276 } else {
1277 assert(kvm_enabled());
e68cb8b4
AK		 1278 }
1279
1280
4be21d56
DG		 1281 return 0;
1282}
1283
28e02042 1284static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr,
4be21d56
DG		 1285 int64_t max_ns)
1286{
378bc217 1287 bool has_timeout = max_ns != -1;
4be21d56
DG		 1288 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1289 int index = spapr->htab_save_index;
bc72ad67 1290 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
4be21d56
DG		 1291
1292 assert(spapr->htab_first_pass);
1293
1294 do {
1295 int chunkstart;
1296
1297 /* Consume invalid HPTEs */
1298 while ((index < htabslots)
1299 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1300 index++;
1301 CLEAN_HPTE(HPTE(spapr->htab, index));
1302 }
1303
1304 /* Consume valid HPTEs */
1305 chunkstart = index;
338c25b6 1306 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
4be21d56
DG		 1307 && HPTE_VALID(HPTE(spapr->htab, index))) {
1308 index++;
1309 CLEAN_HPTE(HPTE(spapr->htab, index));
1310 }
1311
1312 if (index > chunkstart) {
1313 int n_valid = index - chunkstart;
1314
1315 qemu_put_be32(f, chunkstart);
1316 qemu_put_be16(f, n_valid);
1317 qemu_put_be16(f, 0);
1318 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1319 HASH_PTE_SIZE_64 * n_valid);
1320
378bc217
DG		 1321 if (has_timeout &&
1322 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
4be21d56
DG		 1323 break;
1324 }
1325 }
1326 } while ((index < htabslots) && !qemu_file_rate_limit(f));
1327
1328 if (index >= htabslots) {
1329 assert(index == htabslots);
1330 index = 0;
1331 spapr->htab_first_pass = false;
1332 }
1333 spapr->htab_save_index = index;
1334}
1335
28e02042 1336static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr,
e68cb8b4 1337 int64_t max_ns)
4be21d56
DG		 1338{
1339 bool final = max_ns < 0;
1340 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1341 int examined = 0, sent = 0;
1342 int index = spapr->htab_save_index;
bc72ad67 1343 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
4be21d56
DG		 1344
1345 assert(!spapr->htab_first_pass);
1346
1347 do {
1348 int chunkstart, invalidstart;
1349
1350 /* Consume non-dirty HPTEs */
1351 while ((index < htabslots)
1352 && !HPTE_DIRTY(HPTE(spapr->htab, index))) {
1353 index++;
1354 examined++;
1355 }
1356
1357 chunkstart = index;
1358 /* Consume valid dirty HPTEs */
338c25b6 1359 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
4be21d56
DG		 1360 && HPTE_DIRTY(HPTE(spapr->htab, index))
1361 && HPTE_VALID(HPTE(spapr->htab, index))) {
1362 CLEAN_HPTE(HPTE(spapr->htab, index));
1363 index++;
1364 examined++;
1365 }
1366
1367 invalidstart = index;
1368 /* Consume invalid dirty HPTEs */
338c25b6 1369 while ((index < htabslots) && (index - invalidstart < USHRT_MAX)
4be21d56
DG		 1370 && HPTE_DIRTY(HPTE(spapr->htab, index))
1371 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1372 CLEAN_HPTE(HPTE(spapr->htab, index));
1373 index++;
1374 examined++;
1375 }
1376
1377 if (index > chunkstart) {
1378 int n_valid = invalidstart - chunkstart;
1379 int n_invalid = index - invalidstart;
1380
1381 qemu_put_be32(f, chunkstart);
1382 qemu_put_be16(f, n_valid);
1383 qemu_put_be16(f, n_invalid);
1384 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1385 HASH_PTE_SIZE_64 * n_valid);
1386 sent += index - chunkstart;
1387
bc72ad67 1388 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
4be21d56
DG		 1389 break;
1390 }
1391 }
1392
1393 if (examined >= htabslots) {
1394 break;
1395 }
1396
1397 if (index >= htabslots) {
1398 assert(index == htabslots);
1399 index = 0;
1400 }
1401 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final));
1402
1403 if (index >= htabslots) {
1404 assert(index == htabslots);
1405 index = 0;
1406 }
1407
1408 spapr->htab_save_index = index;
1409
e68cb8b4 1410 return (examined >= htabslots) && (sent == 0) ? 1 : 0;
4be21d56
DG		 1411}
1412
e68cb8b4
AK		 1413#define MAX_ITERATION_NS 5000000 /* 5 ms */
1414#define MAX_KVM_BUF_SIZE 2048
1415
4be21d56
DG		 1416static int htab_save_iterate(QEMUFile *f, void *opaque)
1417{
28e02042 1418 sPAPRMachineState *spapr = opaque;
715c5407 1419 int fd;
e68cb8b4 1420 int rc = 0;
4be21d56
DG		 1421
1422 /* Iteration header */
1423 qemu_put_be32(f, 0);
1424
e68cb8b4
AK		 1425 if (!spapr->htab) {
1426 assert(kvm_enabled());
1427
715c5407
DG		 1428 fd = get_htab_fd(spapr);
1429 if (fd < 0) {
1430 return fd;
01a57972
SMJ		 1431 }
1432
715c5407 1433 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS);
e68cb8b4
AK		 1434 if (rc < 0) {
1435 return rc;
1436 }
1437 } else if (spapr->htab_first_pass) {
4be21d56
DG		 1438 htab_save_first_pass(f, spapr, MAX_ITERATION_NS);
1439 } else {
e68cb8b4 1440 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS);
4be21d56
DG		 1441 }
1442
1443 /* End marker */
1444 qemu_put_be32(f, 0);
1445 qemu_put_be16(f, 0);
1446 qemu_put_be16(f, 0);
1447
e68cb8b4 1448 return rc;
4be21d56
DG		 1449}
1450
1451static int htab_save_complete(QEMUFile *f, void *opaque)
1452{
28e02042 1453 sPAPRMachineState *spapr = opaque;
715c5407 1454 int fd;
4be21d56
DG		 1455
1456 /* Iteration header */
1457 qemu_put_be32(f, 0);
1458
e68cb8b4
AK		 1459 if (!spapr->htab) {
1460 int rc;
1461
1462 assert(kvm_enabled());
1463
715c5407
DG		 1464 fd = get_htab_fd(spapr);
1465 if (fd < 0) {
1466 return fd;
01a57972
SMJ		 1467 }
1468
715c5407 1469 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1);
e68cb8b4
AK		 1470 if (rc < 0) {
1471 return rc;
1472 }
e68cb8b4 1473 } else {
378bc217
DG		 1474 if (spapr->htab_first_pass) {
1475 htab_save_first_pass(f, spapr, -1);
1476 }
e68cb8b4
AK		 1477 htab_save_later_pass(f, spapr, -1);
1478 }
4be21d56
DG		 1479
1480 /* End marker */
1481 qemu_put_be32(f, 0);
1482 qemu_put_be16(f, 0);
1483 qemu_put_be16(f, 0);
1484
1485 return 0;
1486}
1487
1488static int htab_load(QEMUFile *f, void *opaque, int version_id)
1489{
28e02042 1490 sPAPRMachineState *spapr = opaque;
4be21d56 1491 uint32_t section_hdr;
e68cb8b4 1492 int fd = -1;
4be21d56
DG		 1493
1494 if (version_id < 1 || version_id > 1) {
98a5d100 1495 error_report("htab_load() bad version");
4be21d56
DG		 1496 return -EINVAL;
1497 }
1498
1499 section_hdr = qemu_get_be32(f);
1500
1501 if (section_hdr) {
9897e462 1502 Error *local_err = NULL;
c5f54f3e
DG		 1503
1504 /* First section gives the htab size */
1505 spapr_reallocate_hpt(spapr, section_hdr, &local_err);
1506 if (local_err) {
1507 error_report_err(local_err);
4be21d56
DG		 1508 return -EINVAL;
1509 }
1510 return 0;
1511 }
1512
e68cb8b4
AK		 1513 if (!spapr->htab) {
1514 assert(kvm_enabled());
1515
1516 fd = kvmppc_get_htab_fd(true);
1517 if (fd < 0) {
98a5d100
DG		 1518 error_report("Unable to open fd to restore KVM hash table: %s",
1519 strerror(errno));
e68cb8b4
AK		 1520 }
1521 }
1522
4be21d56
DG		 1523 while (true) {
1524 uint32_t index;
1525 uint16_t n_valid, n_invalid;
1526
1527 index = qemu_get_be32(f);
1528 n_valid = qemu_get_be16(f);
1529 n_invalid = qemu_get_be16(f);
1530
1531 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) {
1532 /* End of Stream */
1533 break;
1534 }
1535
e68cb8b4 1536 if ((index + n_valid + n_invalid) >
4be21d56
DG		 1537 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) {
1538 /* Bad index in stream */
98a5d100
DG		 1539 error_report(
1540 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
1541 index, n_valid, n_invalid, spapr->htab_shift);
4be21d56
DG		 1542 return -EINVAL;
1543 }
1544
e68cb8b4
AK		 1545 if (spapr->htab) {
1546 if (n_valid) {
1547 qemu_get_buffer(f, HPTE(spapr->htab, index),
1548 HASH_PTE_SIZE_64 * n_valid);
1549 }
1550 if (n_invalid) {
1551 memset(HPTE(spapr->htab, index + n_valid), 0,
1552 HASH_PTE_SIZE_64 * n_invalid);
1553 }
1554 } else {
1555 int rc;
1556
1557 assert(fd >= 0);
1558
1559 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid);
1560 if (rc < 0) {
1561 return rc;
1562 }
4be21d56
DG		 1563 }
1564 }
1565
e68cb8b4
AK		 1566 if (!spapr->htab) {
1567 assert(fd >= 0);
1568 close(fd);
1569 }
1570
4be21d56
DG		 1571 return 0;
1572}
1573
c573fc03
TH		 1574static void htab_cleanup(void *opaque)
1575{
1576 sPAPRMachineState *spapr = opaque;
1577
1578 close_htab_fd(spapr);
1579}
1580
4be21d56
DG		 1581static SaveVMHandlers savevm_htab_handlers = {
1582 .save_live_setup = htab_save_setup,
1583 .save_live_iterate = htab_save_iterate,
a3e06c3d 1584 .save_live_complete_precopy = htab_save_complete,
c573fc03 1585 .cleanup = htab_cleanup,
4be21d56
DG		 1586 .load_state = htab_load,
1587};
1588
5b2128d2
AG		 1589static void spapr_boot_set(void *opaque, const char *boot_device,
1590 Error **errp)
1591{
1592 MachineState *machine = MACHINE(qdev_get_machine());
1593 machine->boot_order = g_strdup(boot_device);
1594}
1595
224245bf
DG		 1596/*
1597 * Reset routine for LMB DR devices.
1598 *
1599 * Unlike PCI DR devices, LMB DR devices explicitly register this reset
1600 * routine. Reset for PCI DR devices will be handled by PHB reset routine
1601 * when it walks all its children devices. LMB devices reset occurs
1602 * as part of spapr_ppc_reset().
1603 */
1604static void spapr_drc_reset(void *opaque)
1605{
1606 sPAPRDRConnector *drc = opaque;
1607 DeviceState *d = DEVICE(drc);
1608
1609 if (d) {
1610 device_reset(d);
1611 }
1612}
1613
1614static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr)
1615{
1616 MachineState *machine = MACHINE(spapr);
1617 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
e8f986fc 1618 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size;
224245bf
DG		 1619 int i;
1620
1621 for (i = 0; i < nr_lmbs; i++) {
1622 sPAPRDRConnector *drc;
1623 uint64_t addr;
1624
e8f986fc 1625 addr = i * lmb_size + spapr->hotplug_memory.base;
224245bf
DG		 1626 drc = spapr_dr_connector_new(OBJECT(spapr), SPAPR_DR_CONNECTOR_TYPE_LMB,
1627 addr/lmb_size);
1628 qemu_register_reset(spapr_drc_reset, drc);
1629 }
1630}
1631
1632/*
1633 * If RAM size, maxmem size and individual node mem sizes aren't aligned
1634 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest
1635 * since we can't support such unaligned sizes with DRCONF_MEMORY.
1636 */
7c150d6f 1637static void spapr_validate_node_memory(MachineState *machine, Error **errp)
224245bf
DG		 1638{
1639 int i;
1640
7c150d6f
DG		 1641 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) {
1642 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT
1643 " is not aligned to %llu MiB",
1644 machine->ram_size,
1645 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1646 return;
1647 }
1648
1649 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) {
1650 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT
1651 " is not aligned to %llu MiB",
1652 machine->ram_size,
1653 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1654 return;
224245bf
DG		 1655 }
1656
1657 for (i = 0; i < nb_numa_nodes; i++) {
1658 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) {
7c150d6f
DG		 1659 error_setg(errp,
1660 "Node %d memory size 0x%" PRIx64
1661 " is not aligned to %llu MiB",
1662 i, numa_info[i].node_mem,
1663 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1664 return;
224245bf
DG		 1665 }
1666 }
1667}
1668
9fdf0c29 1669/* pSeries LPAR / sPAPR hardware init */
3ef96221 1670static void ppc_spapr_init(MachineState *machine)
9fdf0c29 1671{
28e02042 1672 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
3c0c47e3 1673 MachineClass *mc = MACHINE_GET_CLASS(machine);
224245bf 1674 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
3ef96221
MA		 1675 const char *kernel_filename = machine->kernel_filename;
1676 const char *kernel_cmdline = machine->kernel_cmdline;
1677 const char *initrd_filename = machine->initrd_filename;
8c9f64df 1678 PCIHostState *phb;
9fdf0c29 1679 int i;
890c2b77
AK		 1680 MemoryRegion *sysmem = get_system_memory();
1681 MemoryRegion *ram = g_new(MemoryRegion, 1);
658fa66b
AK		 1682 MemoryRegion *rma_region;
1683 void *rma = NULL;
a8170e5e 1684 hwaddr rma_alloc_size;
b082d65a 1685 hwaddr node0_size = spapr_node0_size();
4d8d5467
BH		 1686 uint32_t initrd_base = 0;
1687 long kernel_size = 0, initrd_size = 0;
b7d1f77a 1688 long load_limit, fw_size;
16457e7f 1689 bool kernel_le = false;
39ac8455 1690 char *filename;
94a94e4c
BR		 1691 int smt = kvmppc_smt_threads();
1692 int spapr_cores = smp_cpus / smp_threads;
1693 int spapr_max_cores = max_cpus / smp_threads;
1694
3c0c47e3 1695 if (mc->query_hotpluggable_cpus) {
94a94e4c
BR		 1696 if (smp_cpus % smp_threads) {
1697 error_report("smp_cpus (%u) must be multiple of threads (%u)",
1698 smp_cpus, smp_threads);
1699 exit(1);
1700 }
1701 if (max_cpus % smp_threads) {
1702 error_report("max_cpus (%u) must be multiple of threads (%u)",
1703 max_cpus, smp_threads);
1704 exit(1);
1705 }
1706 }
9fdf0c29 1707
226419d6 1708 msi_nonbroken = true;
0ee2c058 1709
d43b45e2
DG		 1710 QLIST_INIT(&spapr->phbs);
1711
9fdf0c29
DG		 1712 cpu_ppc_hypercall = emulate_spapr_hypercall;
1713
354ac20a 1714 /* Allocate RMA if necessary */
658fa66b 1715 rma_alloc_size = kvmppc_alloc_rma(&rma);
354ac20a
DG		 1716
1717 if (rma_alloc_size == -1) {
730fce59 1718 error_report("Unable to create RMA");
354ac20a
DG		 1719 exit(1);
1720 }
7f763a5d 1721
c4177479 1722 if (rma_alloc_size && (rma_alloc_size < node0_size)) {
7f763a5d 1723 spapr->rma_size = rma_alloc_size;
354ac20a 1724 } else {
c4177479 1725 spapr->rma_size = node0_size;
7f763a5d
DG		 1726
1727 /* With KVM, we don't actually know whether KVM supports an
1728 * unbounded RMA (PR KVM) or is limited by the hash table size
1729 * (HV KVM using VRMA), so we always assume the latter
1730 *
1731 * In that case, we also limit the initial allocations for RTAS
1732 * etc... to 256M since we have no way to know what the VRMA size
1733 * is going to be as it depends on the size of the hash table
1734 * isn't determined yet.
1735 */
1736 if (kvm_enabled()) {
1737 spapr->vrma_adjust = 1;
1738 spapr->rma_size = MIN(spapr->rma_size, 0x10000000);
1739 }
912acdf4
BH		 1740
1741 /* Actually we don't support unbounded RMA anymore since we
1742 * added proper emulation of HV mode. The max we can get is
1743 * 16G which also happens to be what we configure for PAPR
1744 * mode so make sure we don't do anything bigger than that
1745 */
1746 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull);
354ac20a
DG		 1747 }
1748
c4177479 1749 if (spapr->rma_size > node0_size) {
d54e4d76
DG		 1750 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")",
1751 spapr->rma_size);
c4177479
AK		 1752 exit(1);
1753 }
1754
b7d1f77a
BH		 1755 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */
1756 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD;
9fdf0c29 1757
7b565160 1758 /* Set up Interrupt Controller before we create the VCPUs */
27f24582
BH		 1759 spapr->xics = xics_system_init(machine,
1760 DIV_ROUND_UP(max_cpus * smt, smp_threads),
1761 XICS_IRQS_SPAPR, &error_fatal);
7b565160 1762
224245bf 1763 if (smc->dr_lmb_enabled) {
7c150d6f 1764 spapr_validate_node_memory(machine, &error_fatal);
224245bf
DG		 1765 }
1766
9fdf0c29 1767 /* init CPUs */
19fb2c36
BR		 1768 if (machine->cpu_model == NULL) {
1769 machine->cpu_model = kvm_enabled() ? "host" : "POWER7";
9fdf0c29 1770 }
94a94e4c 1771
e703d2f7
GK		 1772 ppc_cpu_parse_features(machine->cpu_model);
1773
3c0c47e3 1774 if (mc->query_hotpluggable_cpus) {
94a94e4c
BR		 1775 char *type = spapr_get_cpu_core_type(machine->cpu_model);
1776
4babfaf0 1777 if (type == NULL) {
caebf378
CLG		 1778 error_report("Unable to find sPAPR CPU Core definition");
1779 exit(1);
1780 }
1781
94a94e4c 1782 spapr->cores = g_new0(Object *, spapr_max_cores);
af81cf32 1783 for (i = 0; i < spapr_max_cores; i++) {
12bf2d33 1784 int core_id = i * smp_threads;
af81cf32
BR		 1785 sPAPRDRConnector *drc =
1786 spapr_dr_connector_new(OBJECT(spapr),
12bf2d33
GK		 1787 SPAPR_DR_CONNECTOR_TYPE_CPU,
1788 (core_id / smp_threads) * smt);
af81cf32
BR		 1789
1790 qemu_register_reset(spapr_drc_reset, drc);
1791
1792 if (i < spapr_cores) {
caebf378 1793 Object *core = object_new(type);
af81cf32
BR		 1794 object_property_set_int(core, smp_threads, "nr-threads",
1795 &error_fatal);
12bf2d33 1796 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID,
af81cf32
BR		 1797 &error_fatal);
1798 object_property_set_bool(core, true, "realized", &error_fatal);
94a94e4c 1799 }
9fdf0c29 1800 }
94a94e4c
BR		 1801 g_free(type);
1802 } else {
1803 for (i = 0; i < smp_cpus; i++) {
1804 PowerPCCPU *cpu = cpu_ppc_init(machine->cpu_model);
1805 if (cpu == NULL) {
1806 error_report("Unable to find PowerPC CPU definition");
1807 exit(1);
1808 }
1809 spapr_cpu_init(spapr, cpu, &error_fatal);
1810 }
9fdf0c29
DG		 1811 }
1812
026bfd89
DG		 1813 if (kvm_enabled()) {
1814 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */
1815 kvmppc_enable_logical_ci_hcalls();
ef9971dd 1816 kvmppc_enable_set_mode_hcall();
026bfd89
DG		 1817 }
1818
9fdf0c29 1819 /* allocate RAM */
f92f5da1 1820 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram",
fb164994 1821 machine->ram_size);
f92f5da1 1822 memory_region_add_subregion(sysmem, 0, ram);
9fdf0c29 1823
658fa66b
AK		 1824 if (rma_alloc_size && rma) {
1825 rma_region = g_new(MemoryRegion, 1);
1826 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma",
1827 rma_alloc_size, rma);
1828 vmstate_register_ram_global(rma_region);
1829 memory_region_add_subregion(sysmem, 0, rma_region);
1830 }
1831
4a1c9cf0
BR		 1832 /* initialize hotplug memory address space */
1833 if (machine->ram_size < machine->maxram_size) {
1834 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size;
71c9a3dd
BR		 1835 /*
1836 * Limit the number of hotpluggable memory slots to half the number
1837 * slots that KVM supports, leaving the other half for PCI and other
1838 * devices. However ensure that number of slots doesn't drop below 32.
1839 */
1840 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 :
1841 SPAPR_MAX_RAM_SLOTS;
4a1c9cf0 1842
71c9a3dd
BR		 1843 if (max_memslots < SPAPR_MAX_RAM_SLOTS) {
1844 max_memslots = SPAPR_MAX_RAM_SLOTS;
1845 }
1846 if (machine->ram_slots > max_memslots) {
d54e4d76
DG		 1847 error_report("Specified number of memory slots %"
1848 PRIu64" exceeds max supported %d",
71c9a3dd 1849 machine->ram_slots, max_memslots);
d54e4d76 1850 exit(1);
4a1c9cf0
BR		 1851 }
1852
1853 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size,
1854 SPAPR_HOTPLUG_MEM_ALIGN);
1855 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr),
1856 "hotplug-memory", hotplug_mem_size);
1857 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base,
1858 &spapr->hotplug_memory.mr);
1859 }
1860
224245bf
DG		 1861 if (smc->dr_lmb_enabled) {
1862 spapr_create_lmb_dr_connectors(spapr);
1863 }
1864
39ac8455 1865 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
4c56440d 1866 if (!filename) {
730fce59 1867 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin");
4c56440d
SW		 1868 exit(1);
1869 }
b7d1f77a 1870 spapr->rtas_size = get_image_size(filename);
8afc22a2
ZJ		 1871 if (spapr->rtas_size < 0) {
1872 error_report("Could not get size of LPAR rtas '%s'", filename);
1873 exit(1);
1874 }
b7d1f77a
BH		 1875 spapr->rtas_blob = g_malloc(spapr->rtas_size);
1876 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) {
730fce59 1877 error_report("Could not load LPAR rtas '%s'", filename);
39ac8455
DG		 1878 exit(1);
1879 }
4d8d5467 1880 if (spapr->rtas_size > RTAS_MAX_SIZE) {
730fce59
TH		 1881 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)",
1882 (size_t)spapr->rtas_size, RTAS_MAX_SIZE);
4d8d5467
BH		 1883 exit(1);
1884 }
7267c094 1885 g_free(filename);
39ac8455 1886
74d042e5
DG		 1887 /* Set up EPOW events infrastructure */
1888 spapr_events_init(spapr);
1889
12f42174 1890 /* Set up the RTC RTAS interfaces */
28df36a1 1891 spapr_rtc_create(spapr);
12f42174 1892
b5cec4c5 1893 /* Set up VIO bus */
4040ab72
DG		 1894 spapr->vio_bus = spapr_vio_bus_init();
1895
277f9acf 1896 for (i = 0; i < MAX_SERIAL_PORTS; i++) {
4040ab72 1897 if (serial_hds[i]) {
d601fac4 1898 spapr_vty_create(spapr->vio_bus, serial_hds[i]);
4040ab72
DG		 1899 }
1900 }
9fdf0c29 1901
639e8102
DG		 1902 /* We always have at least the nvram device on VIO */
1903 spapr_create_nvram(spapr);
1904
3384f95c 1905 /* Set up PCI */
fa28f71b
AK		 1906 spapr_pci_rtas_init();
1907
89dfd6e1 1908 phb = spapr_create_phb(spapr, 0);
3384f95c 1909
277f9acf 1910 for (i = 0; i < nb_nics; i++) {
8d90ad90
DG		 1911 NICInfo *nd = &nd_table[i];
1912
1913 if (!nd->model) {
7267c094 1914 nd->model = g_strdup("ibmveth");
8d90ad90
DG		 1915 }
1916
1917 if (strcmp(nd->model, "ibmveth") == 0) {
d601fac4 1918 spapr_vlan_create(spapr->vio_bus, nd);
8d90ad90 1919 } else {
29b358f9 1920 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL);
8d90ad90
DG		 1921 }
1922 }
1923
6e270446 1924 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) {
d601fac4 1925 spapr_vscsi_create(spapr->vio_bus);
6e270446
BH		 1926 }
1927
f28359d8 1928 /* Graphics */
14c6a894 1929 if (spapr_vga_init(phb->bus, &error_fatal)) {
3fc5acde 1930 spapr->has_graphics = true;
c6e76503 1931 machine->usb |= defaults_enabled() && !machine->usb_disabled;
f28359d8
LZ		 1932 }
1933
4ee9ced9 1934 if (machine->usb) {
57040d45
TH		 1935 if (smc->use_ohci_by_default) {
1936 pci_create_simple(phb->bus, -1, "pci-ohci");
1937 } else {
1938 pci_create_simple(phb->bus, -1, "nec-usb-xhci");
1939 }
c86580b8 1940
35139a59 1941 if (spapr->has_graphics) {
c86580b8
MA		 1942 USBBus *usb_bus = usb_bus_find(-1);
1943
1944 usb_create_simple(usb_bus, "usb-kbd");
1945 usb_create_simple(usb_bus, "usb-mouse");
35139a59
DG		 1946 }
1947 }
1948
7f763a5d 1949 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) {
d54e4d76
DG		 1950 error_report(
1951 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)",
1952 MIN_RMA_SLOF);
4d8d5467
BH		 1953 exit(1);
1954 }
1955
9fdf0c29
DG		 1956 if (kernel_filename) {
1957 uint64_t lowaddr = 0;
1958
9fdf0c29 1959 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
7ef295ea
PC		 1960 NULL, &lowaddr, NULL, 1, PPC_ELF_MACHINE,
1961 0, 0);
3b66da82 1962 if (kernel_size == ELF_LOAD_WRONG_ENDIAN) {
16457e7f
BH		 1963 kernel_size = load_elf(kernel_filename,
1964 translate_kernel_address, NULL,
7ef295ea
PC		 1965 NULL, &lowaddr, NULL, 0, PPC_ELF_MACHINE,
1966 0, 0);
16457e7f
BH		 1967 kernel_le = kernel_size > 0;
1968 }
9fdf0c29 1969 if (kernel_size < 0) {
d54e4d76
DG		 1970 error_report("error loading %s: %s",
1971 kernel_filename, load_elf_strerror(kernel_size));
9fdf0c29
DG		 1972 exit(1);
1973 }
1974
1975 /* load initrd */
1976 if (initrd_filename) {
4d8d5467
BH		 1977 /* Try to locate the initrd in the gap between the kernel
1978 * and the firmware. Add a bit of space just in case
1979 */
1980 initrd_base = (KERNEL_LOAD_ADDR + kernel_size + 0x1ffff) & ~0xffff;
9fdf0c29 1981 initrd_size = load_image_targphys(initrd_filename, initrd_base,
4d8d5467 1982 load_limit - initrd_base);
9fdf0c29 1983 if (initrd_size < 0) {
d54e4d76
DG		 1984 error_report("could not load initial ram disk '%s'",
1985 initrd_filename);
9fdf0c29
DG		 1986 exit(1);
1987 }
1988 } else {
1989 initrd_base = 0;
1990 initrd_size = 0;
1991 }
4d8d5467 1992 }
a3467baa 1993
8e7ea787
AF		 1994 if (bios_name == NULL) {
1995 bios_name = FW_FILE_NAME;
1996 }
1997 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
4c56440d 1998 if (!filename) {
68fea5a0 1999 error_report("Could not find LPAR firmware '%s'", bios_name);
4c56440d
SW		 2000 exit(1);
2001 }
4d8d5467 2002 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
68fea5a0
TH		 2003 if (fw_size <= 0) {
2004 error_report("Could not load LPAR firmware '%s'", filename);
4d8d5467
BH		 2005 exit(1);
2006 }
2007 g_free(filename);
4d8d5467 2008
28e02042
DG		 2009 /* FIXME: Should register things through the MachineState's qdev
2010 * interface, this is a legacy from the sPAPREnvironment structure
2011 * which predated MachineState but had a similar function */
4be21d56
DG		 2012 vmstate_register(NULL, 0, &vmstate_spapr, spapr);
2013 register_savevm_live(NULL, "spapr/htab", -1, 1,
2014 &savevm_htab_handlers, spapr);
2015
9fdf0c29 2016 /* Prepare the device tree */
3bbf37f2 2017 spapr->fdt_skel = spapr_create_fdt_skel(initrd_base, initrd_size,
16457e7f 2018 kernel_size, kernel_le,
31fe14d1
NF		 2019 kernel_cmdline,
2020 spapr->check_exception_irq);
a3467baa 2021 assert(spapr->fdt_skel != NULL);
5b2128d2 2022
46503c2b
MR		 2023 /* used by RTAS */
2024 QTAILQ_INIT(&spapr->ccs_list);
2025 qemu_register_reset(spapr_ccs_reset_hook, spapr);
2026
5b2128d2 2027 qemu_register_boot_set(spapr_boot_set, spapr);
9fdf0c29
DG		 2028}
2029
135a129a
AK		 2030static int spapr_kvm_type(const char *vm_type)
2031{
2032 if (!vm_type) {
2033 return 0;
2034 }
2035
2036 if (!strcmp(vm_type, "HV")) {
2037 return 1;
2038 }
2039
2040 if (!strcmp(vm_type, "PR")) {
2041 return 2;
2042 }
2043
2044 error_report("Unknown kvm-type specified '%s'", vm_type);
2045 exit(1);
2046}
2047
71461b0f 2048/*
627b84f4 2049 * Implementation of an interface to adjust firmware path
71461b0f
AK		 2050 * for the bootindex property handling.
2051 */
2052static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus,
2053 DeviceState *dev)
2054{
2055#define CAST(type, obj, name) \
2056 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
2057 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE);
2058 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE);
2059
2060 if (d) {
2061 void *spapr = CAST(void, bus->parent, "spapr-vscsi");
2062 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI);
2063 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE);
2064
2065 if (spapr) {
2066 /*
2067 * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
2068 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun
2069 * in the top 16 bits of the 64-bit LUN
2070 */
2071 unsigned id = 0x8000 | (d->id << 8) | d->lun;
2072 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2073 (uint64_t)id << 48);
2074 } else if (virtio) {
2075 /*
2076 * We use SRP luns of the form 01000000 | (target << 8) | lun
2077 * in the top 32 bits of the 64-bit LUN
2078 * Note: the quote above is from SLOF and it is wrong,
2079 * the actual binding is:
2080 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
2081 */
2082 unsigned id = 0x1000000 | (d->id << 16) | d->lun;
2083 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2084 (uint64_t)id << 32);
2085 } else if (usb) {
2086 /*
2087 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
2088 * in the top 32 bits of the 64-bit LUN
2089 */
2090 unsigned usb_port = atoi(usb->port->path);
2091 unsigned id = 0x1000000 | (usb_port << 16) | d->lun;
2092 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2093 (uint64_t)id << 32);
2094 }
2095 }
2096
2097 if (phb) {
2098 /* Replace "pci" with "pci@800000020000000" */
2099 return g_strdup_printf("pci@%"PRIX64, phb->buid);
2100 }
2101
2102 return NULL;
2103}
2104
23825581
EH		 2105static char *spapr_get_kvm_type(Object *obj, Error **errp)
2106{
28e02042 2107 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
23825581 2108
28e02042 2109 return g_strdup(spapr->kvm_type);
23825581
EH		 2110}
2111
2112static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp)
2113{
28e02042 2114 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
23825581 2115
28e02042
DG		 2116 g_free(spapr->kvm_type);
2117 spapr->kvm_type = g_strdup(value);
23825581
EH		 2118}
2119
2120static void spapr_machine_initfn(Object *obj)
2121{
715c5407
DG		 2122 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2123
2124 spapr->htab_fd = -1;
23825581
EH		 2125 object_property_add_str(obj, "kvm-type",
2126 spapr_get_kvm_type, spapr_set_kvm_type, NULL);
49d2e648
MA		 2127 object_property_set_description(obj, "kvm-type",
2128 "Specifies the KVM virtualization mode (HV, PR)",
2129 NULL);
23825581
EH		 2130}
2131
87bbdd9c
DG		 2132static void spapr_machine_finalizefn(Object *obj)
2133{
2134 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2135
2136 g_free(spapr->kvm_type);
2137}
2138
34316482
AK		 2139static void ppc_cpu_do_nmi_on_cpu(void *arg)
2140{
2141 CPUState *cs = arg;
2142
2143 cpu_synchronize_state(cs);
2144 ppc_cpu_do_system_reset(cs);
2145}
2146
2147static void spapr_nmi(NMIState *n, int cpu_index, Error **errp)
2148{
2149 CPUState *cs;
2150
2151 CPU_FOREACH(cs) {
2152 async_run_on_cpu(cs, ppc_cpu_do_nmi_on_cpu, cs);
2153 }
2154}
2155
c20d332a
BR		 2156static void spapr_add_lmbs(DeviceState *dev, uint64_t addr, uint64_t size,
2157 uint32_t node, Error **errp)
2158{
2159 sPAPRDRConnector *drc;
2160 sPAPRDRConnectorClass *drck;
2161 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE;
2162 int i, fdt_offset, fdt_size;
2163 void *fdt;
2164
c20d332a
BR		 2165 for (i = 0; i < nr_lmbs; i++) {
2166 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB,
2167 addr/SPAPR_MEMORY_BLOCK_SIZE);
2168 g_assert(drc);
2169
2170 fdt = create_device_tree(&fdt_size);
2171 fdt_offset = spapr_populate_memory_node(fdt, node, addr,
2172 SPAPR_MEMORY_BLOCK_SIZE);
2173
2174 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2175 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, errp);
c20d332a
BR		 2176 addr += SPAPR_MEMORY_BLOCK_SIZE;
2177 }
5dd5238c
JD		 2178 /* send hotplug notification to the
2179 * guest only in case of hotplugged memory
2180 */
2181 if (dev->hotplugged) {
2182 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, nr_lmbs);
2183 }
c20d332a
BR		 2184}
2185
2186static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2187 uint32_t node, Error **errp)
2188{
2189 Error *local_err = NULL;
2190 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev);
2191 PCDIMMDevice *dimm = PC_DIMM(dev);
2192 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
2193 MemoryRegion *mr = ddc->get_memory_region(dimm);
2194 uint64_t align = memory_region_get_alignment(mr);
2195 uint64_t size = memory_region_size(mr);
2196 uint64_t addr;
2197
2198 if (size % SPAPR_MEMORY_BLOCK_SIZE) {
2199 error_setg(&local_err, "Hotplugged memory size must be a multiple of "
2200 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE/M_BYTE);
2201 goto out;
2202 }
2203
d6a9b0b8 2204 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err);
c20d332a
BR		 2205 if (local_err) {
2206 goto out;
2207 }
2208
2209 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err);
2210 if (local_err) {
2211 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr);
2212 goto out;
2213 }
2214
2215 spapr_add_lmbs(dev, addr, size, node, &error_abort);
2216
2217out:
2218 error_propagate(errp, local_err);
2219}
2220
af81cf32
BR		 2221void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset,
2222 sPAPRMachineState *spapr)
2223{
2224 PowerPCCPU *cpu = POWERPC_CPU(cs);
2225 DeviceClass *dc = DEVICE_GET_CLASS(cs);
2226 int id = ppc_get_vcpu_dt_id(cpu);
2227 void *fdt;
2228 int offset, fdt_size;
2229 char *nodename;
2230
2231 fdt = create_device_tree(&fdt_size);
2232 nodename = g_strdup_printf("%s@%x", dc->fw_name, id);
2233 offset = fdt_add_subnode(fdt, 0, nodename);
2234
2235 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
2236 g_free(nodename);
2237
2238 *fdt_offset = offset;
2239 return fdt;
2240}
2241
c20d332a
BR		 2242static void spapr_machine_device_plug(HotplugHandler *hotplug_dev,
2243 DeviceState *dev, Error **errp)
2244{
2245 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine());
2246
2247 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
b556854b 2248 int node;
c20d332a
BR		 2249
2250 if (!smc->dr_lmb_enabled) {
2251 error_setg(errp, "Memory hotplug not supported for this machine");
2252 return;
2253 }
2254 node = object_property_get_int(OBJECT(dev), PC_DIMM_NODE_PROP, errp);
2255 if (*errp) {
2256 return;
2257 }
1a5512bb
GA		 2258 if (node < 0 || node >= MAX_NODES) {
2259 error_setg(errp, "Invaild node %d", node);
2260 return;
2261 }
c20d332a 2262
b556854b
BR		 2263 /*
2264 * Currently PowerPC kernel doesn't allow hot-adding memory to
2265 * memory-less node, but instead will silently add the memory
2266 * to the first node that has some memory. This causes two
2267 * unexpected behaviours for the user.
2268 *
2269 * - Memory gets hotplugged to a different node than what the user
2270 * specified.
2271 * - Since pc-dimm subsystem in QEMU still thinks that memory belongs
2272 * to memory-less node, a reboot will set things accordingly
2273 * and the previously hotplugged memory now ends in the right node.
2274 * This appears as if some memory moved from one node to another.
2275 *
2276 * So until kernel starts supporting memory hotplug to memory-less
2277 * nodes, just prevent such attempts upfront in QEMU.
2278 */
2279 if (nb_numa_nodes && !numa_info[node].node_mem) {
2280 error_setg(errp, "Can't hotplug memory to memory-less node %d",
2281 node);
2282 return;
2283 }
2284
c20d332a 2285 spapr_memory_plug(hotplug_dev, dev, node, errp);
af81cf32
BR		 2286 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
2287 spapr_core_plug(hotplug_dev, dev, errp);
c20d332a
BR		 2288 }
2289}
2290
2291static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev,
2292 DeviceState *dev, Error **errp)
2293{
3c0c47e3 2294 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
6f4b5c3e 2295
c20d332a
BR		 2296 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2297 error_setg(errp, "Memory hot unplug not supported by sPAPR");
6f4b5c3e 2298 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
3c0c47e3 2299 if (!mc->query_hotpluggable_cpus) {
6f4b5c3e
BR		 2300 error_setg(errp, "CPU hot unplug not supported on this machine");
2301 return;
2302 }
2303 spapr_core_unplug(hotplug_dev, dev, errp);
c20d332a
BR		 2304 }
2305}
2306
94a94e4c
BR		 2307static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev,
2308 DeviceState *dev, Error **errp)
2309{
2310 if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
2311 spapr_core_pre_plug(hotplug_dev, dev, errp);
2312 }
2313}
2314
c20d332a
BR		 2315static HotplugHandler *spapr_get_hotpug_handler(MachineState *machine,
2316 DeviceState *dev)
2317{
94a94e4c
BR		 2318 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
2319 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
c20d332a
BR		 2320 return HOTPLUG_HANDLER(machine);
2321 }
2322 return NULL;
2323}
2324
20bb648d
DG		 2325static unsigned spapr_cpu_index_to_socket_id(unsigned cpu_index)
2326{
2327 /* Allocate to NUMA nodes on a "socket" basis (not that concept of
2328 * socket means much for the paravirtualized PAPR platform) */
2329 return cpu_index / smp_threads / smp_cores;
2330}
2331
2474bfd4
IM		 2332static HotpluggableCPUList *spapr_query_hotpluggable_cpus(MachineState *machine)
2333{
2334 int i;
2335 HotpluggableCPUList *head = NULL;
2336 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
2337 int spapr_max_cores = max_cpus / smp_threads;
2474bfd4
IM		 2338
2339 for (i = 0; i < spapr_max_cores; i++) {
2340 HotpluggableCPUList *list_item = g_new0(typeof(*list_item), 1);
2341 HotpluggableCPU *cpu_item = g_new0(typeof(*cpu_item), 1);
2342 CpuInstanceProperties *cpu_props = g_new0(typeof(*cpu_props), 1);
2343
2344 cpu_item->type = spapr_get_cpu_core_type(machine->cpu_model);
2345 cpu_item->vcpus_count = smp_threads;
27393c33 2346 cpu_props->has_core_id = true;
12bf2d33 2347 cpu_props->core_id = i * smp_threads;
2474bfd4
IM		 2348 /* TODO: add 'has_node/node' here to describe
2349 to which node core belongs */
2350
2351 cpu_item->props = cpu_props;
2352 if (spapr->cores[i]) {
2353 cpu_item->has_qom_path = true;
2354 cpu_item->qom_path = object_get_canonical_path(spapr->cores[i]);
2355 }
2356 list_item->value = cpu_item;
2357 list_item->next = head;
2358 head = list_item;
2359 }
2360 return head;
2361}
2362
29ee3247
AK		 2363static void spapr_machine_class_init(ObjectClass *oc, void *data)
2364{
2365 MachineClass *mc = MACHINE_CLASS(oc);
224245bf 2366 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc);
71461b0f 2367 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
34316482 2368 NMIClass *nc = NMI_CLASS(oc);
c20d332a 2369 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
958db90c 2370
0eb9054c 2371 mc->desc = "pSeries Logical Partition (PAPR compliant)";
fc9f38c3
DG		 2372
2373 /*
2374 * We set up the default / latest behaviour here. The class_init
2375 * functions for the specific versioned machine types can override
2376 * these details for backwards compatibility
2377 */
958db90c
MA		 2378 mc->init = ppc_spapr_init;
2379 mc->reset = ppc_spapr_reset;
2380 mc->block_default_type = IF_SCSI;
38b02bd8 2381 mc->max_cpus = MAX_CPUMASK_BITS;
958db90c 2382 mc->no_parallel = 1;
5b2128d2 2383 mc->default_boot_order = "";
a34944fe 2384 mc->default_ram_size = 512 * M_BYTE;
958db90c 2385 mc->kvm_type = spapr_kvm_type;
9e3f9733 2386 mc->has_dynamic_sysbus = true;
e4024630 2387 mc->pci_allow_0_address = true;
c20d332a 2388 mc->get_hotplug_handler = spapr_get_hotpug_handler;
94a94e4c 2389 hc->pre_plug = spapr_machine_device_pre_plug;
c20d332a
BR		 2390 hc->plug = spapr_machine_device_plug;
2391 hc->unplug = spapr_machine_device_unplug;
20bb648d 2392 mc->cpu_index_to_socket_id = spapr_cpu_index_to_socket_id;
00b4fbe2 2393
fc9f38c3 2394 smc->dr_lmb_enabled = true;
3c0c47e3 2395 mc->query_hotpluggable_cpus = spapr_query_hotpluggable_cpus;
71461b0f 2396 fwc->get_dev_path = spapr_get_fw_dev_path;
34316482 2397 nc->nmi_monitor_handler = spapr_nmi;
29ee3247
AK		 2398}
2399
2400static const TypeInfo spapr_machine_info = {
2401 .name = TYPE_SPAPR_MACHINE,
2402 .parent = TYPE_MACHINE,
4aee7362 2403 .abstract = true,
6ca1502e 2404 .instance_size = sizeof(sPAPRMachineState),
23825581 2405 .instance_init = spapr_machine_initfn,
87bbdd9c 2406 .instance_finalize = spapr_machine_finalizefn,
183930c0 2407 .class_size = sizeof(sPAPRMachineClass),
29ee3247 2408 .class_init = spapr_machine_class_init,
71461b0f
AK		 2409 .interfaces = (InterfaceInfo[]) {
2410 { TYPE_FW_PATH_PROVIDER },
34316482 2411 { TYPE_NMI },
c20d332a 2412 { TYPE_HOTPLUG_HANDLER },
71461b0f
AK		 2413 { }
2414 },
29ee3247
AK		 2415};
2416
fccbc785 2417#define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \
5013c547
DG		 2418 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \
2419 void *data) \
2420 { \
2421 MachineClass *mc = MACHINE_CLASS(oc); \
2422 spapr_machine_##suffix##_class_options(mc); \
fccbc785
DG		 2423 if (latest) { \
2424 mc->alias = "pseries"; \
2425 mc->is_default = 1; \
2426 } \
5013c547
DG		 2427 } \
2428 static void spapr_machine_##suffix##_instance_init(Object *obj) \
2429 { \
2430 MachineState *machine = MACHINE(obj); \
2431 spapr_machine_##suffix##_instance_options(machine); \
2432 } \
2433 static const TypeInfo spapr_machine_##suffix##_info = { \
2434 .name = MACHINE_TYPE_NAME("pseries-" verstr), \
2435 .parent = TYPE_SPAPR_MACHINE, \
2436 .class_init = spapr_machine_##suffix##_class_init, \
2437 .instance_init = spapr_machine_##suffix##_instance_init, \
2438 }; \
2439 static void spapr_machine_register_##suffix(void) \
2440 { \
2441 type_register(&spapr_machine_##suffix##_info); \
2442 } \
0e6aac87 2443 type_init(spapr_machine_register_##suffix)
5013c547 2444
1ea1eefc
BR		 2445/*
2446 * pseries-2.7
2447 */
2448static void spapr_machine_2_7_instance_options(MachineState *machine)
2449{
2450}
2451
2452static void spapr_machine_2_7_class_options(MachineClass *mc)
2453{
2454 /* Defaults for the latest behaviour inherited from the base class */
2455}
2456
2457DEFINE_SPAPR_MACHINE(2_7, "2.7", true);
2458
4b23699c
DG		 2459/*
2460 * pseries-2.6
2461 */
1ea1eefc 2462#define SPAPR_COMPAT_2_6 \
ae4de14c
AK		 2463 HW_COMPAT_2_6 \
2464 { \
2465 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
2466 .property = "ddw",\
2467 .value = stringify(off),\
2468 },
1ea1eefc 2469
4b23699c
DG		 2470static void spapr_machine_2_6_instance_options(MachineState *machine)
2471{
2472}
2473
2474static void spapr_machine_2_6_class_options(MachineClass *mc)
2475{
1ea1eefc 2476 spapr_machine_2_7_class_options(mc);
3c0c47e3 2477 mc->query_hotpluggable_cpus = NULL;
1ea1eefc 2478 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6);
4b23699c
DG		 2479}
2480
1ea1eefc 2481DEFINE_SPAPR_MACHINE(2_6, "2.6", false);
4b23699c 2482
1c5f29bb
DG		 2483/*
2484 * pseries-2.5
2485 */
4b23699c 2486#define SPAPR_COMPAT_2_5 \
57c522f4
TH		 2487 HW_COMPAT_2_5 \
2488 { \
2489 .driver = "spapr-vlan", \
2490 .property = "use-rx-buffer-pools", \
2491 .value = "off", \
2492 },
4b23699c 2493
5013c547 2494static void spapr_machine_2_5_instance_options(MachineState *machine)
1c5f29bb 2495{
5013c547
DG		 2496}
2497
2498static void spapr_machine_2_5_class_options(MachineClass *mc)
2499{
57040d45
TH		 2500 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
2501
4b23699c 2502 spapr_machine_2_6_class_options(mc);
57040d45 2503 smc->use_ohci_by_default = true;
4b23699c 2504 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5);
1c5f29bb
DG		 2505}
2506
4b23699c 2507DEFINE_SPAPR_MACHINE(2_5, "2.5", false);
1c5f29bb
DG		 2508
2509/*
2510 * pseries-2.4
2511 */
80fd50f9
CH		 2512#define SPAPR_COMPAT_2_4 \
2513 HW_COMPAT_2_4
2514
5013c547 2515static void spapr_machine_2_4_instance_options(MachineState *machine)
1c5f29bb 2516{
5013c547
DG		 2517 spapr_machine_2_5_instance_options(machine);
2518}
1c5f29bb 2519
5013c547
DG		 2520static void spapr_machine_2_4_class_options(MachineClass *mc)
2521{
fc9f38c3
DG		 2522 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
2523
2524 spapr_machine_2_5_class_options(mc);
fc9f38c3 2525 smc->dr_lmb_enabled = false;
f949b4e5 2526 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4);
1c5f29bb
DG		 2527}
2528
fccbc785 2529DEFINE_SPAPR_MACHINE(2_4, "2.4", false);
1c5f29bb
DG		 2530
2531/*
2532 * pseries-2.3
2533 */
38ff32c6 2534#define SPAPR_COMPAT_2_3 \
7619c7b0
MR		 2535 HW_COMPAT_2_3 \
2536 {\
2537 .driver = "spapr-pci-host-bridge",\
2538 .property = "dynamic-reconfiguration",\
2539 .value = "off",\
2540 },
38ff32c6 2541
5013c547 2542static void spapr_machine_2_3_instance_options(MachineState *machine)
d25228e7 2543{
5013c547 2544 spapr_machine_2_4_instance_options(machine);
ff14e817 2545 savevm_skip_section_footers();
13d16814 2546 global_state_set_optional();
09b5e30d 2547 savevm_skip_configuration();
d25228e7
JW		 2548}
2549
5013c547 2550static void spapr_machine_2_3_class_options(MachineClass *mc)
6026db45 2551{
fc9f38c3 2552 spapr_machine_2_4_class_options(mc);
f949b4e5 2553 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3);
6026db45 2554}
fccbc785 2555DEFINE_SPAPR_MACHINE(2_3, "2.3", false);
6026db45 2556
1c5f29bb
DG		 2557/*
2558 * pseries-2.2
2559 */
2560
2561#define SPAPR_COMPAT_2_2 \
1c5f29bb
DG		 2562 HW_COMPAT_2_2 \
2563 {\
2564 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
2565 .property = "mem_win_size",\
2566 .value = "0x20000000",\
2567 },
2568
5013c547 2569static void spapr_machine_2_2_instance_options(MachineState *machine)
1c5f29bb 2570{
5013c547 2571 spapr_machine_2_3_instance_options(machine);
cba0e779 2572 machine->suppress_vmdesc = true;
1c5f29bb
DG		 2573}
2574
5013c547 2575static void spapr_machine_2_2_class_options(MachineClass *mc)
4aee7362 2576{
fc9f38c3 2577 spapr_machine_2_3_class_options(mc);
f949b4e5 2578 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2);
4aee7362 2579}
fccbc785 2580DEFINE_SPAPR_MACHINE(2_2, "2.2", false);
4aee7362 2581
1c5f29bb
DG		 2582/*
2583 * pseries-2.1
2584 */
2585#define SPAPR_COMPAT_2_1 \
1c5f29bb 2586 HW_COMPAT_2_1
3dab0244 2587
5013c547 2588static void spapr_machine_2_1_instance_options(MachineState *machine)
1c5f29bb 2589{
5013c547 2590 spapr_machine_2_2_instance_options(machine);
1c5f29bb 2591}
d25228e7 2592
5013c547 2593static void spapr_machine_2_1_class_options(MachineClass *mc)
d25228e7 2594{
fc9f38c3 2595 spapr_machine_2_2_class_options(mc);
f949b4e5 2596 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1);
d25228e7 2597}
fccbc785 2598DEFINE_SPAPR_MACHINE(2_1, "2.1", false);
fb0fc8f6 2599
29ee3247 2600static void spapr_machine_register_types(void)
9fdf0c29 2601{
29ee3247 2602 type_register_static(&spapr_machine_info);
9fdf0c29
DG		 2603}
2604
29ee3247 2605type_init(spapr_machine_register_types)
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