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target-ppc: convert SPE FP ops to TCG
[qemu.git] / target-ppc / op_helper.c
CommitLineData
9a64fbe4 1/*
3fc6c082 2 * PowerPC emulation helpers for qemu.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
9a64fbe4
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
9a64fbe4 20#include "exec.h"
603fccce 21#include "host-utils.h"
a7812ae4 22#include "helper.h"
9a64fbe4 23
0411a972 24#include "helper_regs.h"
0487d6a8
JM		 25#include "op_helper.h"
26
9a64fbe4 27#define MEMSUFFIX _raw
0487d6a8 28#include "op_helper.h"
9a64fbe4 29#include "op_helper_mem.h"
a541f297 30#if !defined(CONFIG_USER_ONLY)
9a64fbe4 31#define MEMSUFFIX _user
0487d6a8 32#include "op_helper.h"
9a64fbe4
FB		 33#include "op_helper_mem.h"
34#define MEMSUFFIX _kernel
0487d6a8 35#include "op_helper.h"
9a64fbe4 36#include "op_helper_mem.h"
1e42b8f0
JM		 37#define MEMSUFFIX _hypv
38#include "op_helper.h"
39#include "op_helper_mem.h"
40#endif
9a64fbe4 41
fdabc366
FB		 42//#define DEBUG_OP
43//#define DEBUG_EXCEPTIONS
76a66253 44//#define DEBUG_SOFTWARE_TLB
fdabc366 45
9a64fbe4
FB		 46/*****************************************************************************/
47/* Exceptions processing helpers */
9a64fbe4 48
64adab3f 49void helper_raise_exception_err (uint32_t exception, uint32_t error_code)
9a64fbe4 50{
64adab3f 51 raise_exception_err(env, exception, error_code);
76a66253 52}
9fddaa0c 53
64adab3f 54void helper_raise_debug (void)
9fddaa0c 55{
64adab3f 56 raise_exception(env, EXCP_DEBUG);
9a64fbe4
FB		 57}
58
64adab3f 59
76a66253
JM		 60/*****************************************************************************/
61/* Registers load and stores */
a7812ae4 62target_ulong helper_load_cr (void)
76a66253 63{
e1571908
AJ		 64 return (env->crf[0] << 28) |
65 (env->crf[1] << 24) |
66 (env->crf[2] << 20) |
67 (env->crf[3] << 16) |
68 (env->crf[4] << 12) |
69 (env->crf[5] << 8) |
70 (env->crf[6] << 4) |
71 (env->crf[7] << 0);
76a66253
JM		 72}
73
e1571908 74void helper_store_cr (target_ulong val, uint32_t mask)
76a66253
JM		 75{
76 int i, sh;
77
36081602 78 for (i = 0, sh = 7; i < 8; i++, sh--) {
76a66253 79 if (mask & (1 << sh))
e1571908 80 env->crf[i] = (val >> (sh * 4)) & 0xFUL;
76a66253
JM		 81 }
82}
83
c80f84e3
JM		 84#if defined(TARGET_PPC64)
85void do_store_pri (int prio)
86{
87 env->spr[SPR_PPR] &= ~0x001C000000000000ULL;
88 env->spr[SPR_PPR] |= ((uint64_t)prio & 0x7) << 50;
89}
90#endif
91
a496775f
JM		 92target_ulong ppc_load_dump_spr (int sprn)
93{
6b80055d 94 if (loglevel != 0) {
a496775f
JM		 95 fprintf(logfile, "Read SPR %d %03x => " ADDRX "\n",
96 sprn, sprn, env->spr[sprn]);
97 }
98
99 return env->spr[sprn];
100}
101
102void ppc_store_dump_spr (int sprn, target_ulong val)
103{
6b80055d 104 if (loglevel != 0) {
a496775f
JM		 105 fprintf(logfile, "Write SPR %d %03x => " ADDRX " <= " ADDRX "\n",
106 sprn, sprn, env->spr[sprn], val);
107 }
108 env->spr[sprn] = val;
109}
110
9a64fbe4 111/*****************************************************************************/
fdabc366 112/* Fixed point operations helpers */
d9bce9d9 113#if defined(TARGET_PPC64)
d9bce9d9 114
74637406
AJ		 115/* multiply high word */
116uint64_t helper_mulhd (uint64_t arg1, uint64_t arg2)
fdabc366 117{
74637406 118 uint64_t tl, th;
fdabc366 119
74637406
AJ		 120 muls64(&tl, &th, arg1, arg2);
121 return th;
d9bce9d9 122}
d9bce9d9 123
74637406
AJ		 124/* multiply high word unsigned */
125uint64_t helper_mulhdu (uint64_t arg1, uint64_t arg2)
fdabc366 126{
74637406 127 uint64_t tl, th;
fdabc366 128
74637406
AJ		 129 mulu64(&tl, &th, arg1, arg2);
130 return th;
fdabc366
FB		 131}
132
74637406 133uint64_t helper_mulldo (uint64_t arg1, uint64_t arg2)
fdabc366 134{
d9bce9d9
JM		 135 int64_t th;
136 uint64_t tl;
137
74637406 138 muls64(&tl, (uint64_t *)&th, arg1, arg2);
88ad920b 139 /* If th != 0 && th != -1, then we had an overflow */
6f2d8978 140 if (likely((uint64_t)(th + 1) <= 1)) {
3d7b417e 141 env->xer &= ~(1 << XER_OV);
fdabc366 142 } else {
3d7b417e 143 env->xer |= (1 << XER_OV) | (1 << XER_SO);
fdabc366 144 }
74637406 145 return (int64_t)tl;
d9bce9d9
JM		 146}
147#endif
148
26d67362 149target_ulong helper_cntlzw (target_ulong t)
603fccce 150{
26d67362 151 return clz32(t);
603fccce
JM		 152}
153
154#if defined(TARGET_PPC64)
26d67362 155target_ulong helper_cntlzd (target_ulong t)
603fccce 156{
26d67362 157 return clz64(t);
603fccce
JM		 158}
159#endif
160
9a64fbe4 161/* shift right arithmetic helper */
26d67362 162target_ulong helper_sraw (target_ulong value, target_ulong shift)
9a64fbe4
FB		 163{
164 int32_t ret;
165
26d67362
AJ		 166 if (likely(!(shift & 0x20))) {
167 if (likely((uint32_t)shift != 0)) {
168 shift &= 0x1f;
169 ret = (int32_t)value >> shift;
170 if (likely(ret >= 0 || (value & ((1 << shift) - 1)) == 0)) {
3d7b417e 171 env->xer &= ~(1 << XER_CA);
fdabc366 172 } else {
3d7b417e 173 env->xer |= (1 << XER_CA);
fdabc366
FB		 174 }
175 } else {
26d67362 176 ret = (int32_t)value;
3d7b417e 177 env->xer &= ~(1 << XER_CA);
fdabc366
FB		 178 }
179 } else {
26d67362
AJ		 180 ret = (int32_t)value >> 31;
181 if (ret) {
3d7b417e 182 env->xer |= (1 << XER_CA);
26d67362
AJ		 183 } else {
184 env->xer &= ~(1 << XER_CA);
76a66253 185 }
fdabc366 186 }
26d67362 187 return (target_long)ret;
9a64fbe4
FB		 188}
189
d9bce9d9 190#if defined(TARGET_PPC64)
26d67362 191target_ulong helper_srad (target_ulong value, target_ulong shift)
d9bce9d9
JM		 192{
193 int64_t ret;
194
26d67362
AJ		 195 if (likely(!(shift & 0x40))) {
196 if (likely((uint64_t)shift != 0)) {
197 shift &= 0x3f;
198 ret = (int64_t)value >> shift;
199 if (likely(ret >= 0 || (value & ((1 << shift) - 1)) == 0)) {
3d7b417e 200 env->xer &= ~(1 << XER_CA);
d9bce9d9 201 } else {
3d7b417e 202 env->xer |= (1 << XER_CA);
d9bce9d9
JM		 203 }
204 } else {
26d67362 205 ret = (int64_t)value;
3d7b417e 206 env->xer &= ~(1 << XER_CA);
d9bce9d9
JM		 207 }
208 } else {
26d67362
AJ		 209 ret = (int64_t)value >> 63;
210 if (ret) {
3d7b417e 211 env->xer |= (1 << XER_CA);
26d67362
AJ		 212 } else {
213 env->xer &= ~(1 << XER_CA);
d9bce9d9
JM		 214 }
215 }
26d67362 216 return ret;
d9bce9d9
JM		 217}
218#endif
219
26d67362 220target_ulong helper_popcntb (target_ulong val)
d9bce9d9 221{
6176a26d
AJ		 222 val = (val & 0x55555555) + ((val >> 1) & 0x55555555);
223 val = (val & 0x33333333) + ((val >> 2) & 0x33333333);
224 val = (val & 0x0f0f0f0f) + ((val >> 4) & 0x0f0f0f0f);
225 return val;
d9bce9d9
JM		 226}
227
228#if defined(TARGET_PPC64)
26d67362 229target_ulong helper_popcntb_64 (target_ulong val)
d9bce9d9 230{
6176a26d
AJ		 231 val = (val & 0x5555555555555555ULL) + ((val >> 1) & 0x5555555555555555ULL);
232 val = (val & 0x3333333333333333ULL) + ((val >> 2) & 0x3333333333333333ULL);
233 val = (val & 0x0f0f0f0f0f0f0f0fULL) + ((val >> 4) & 0x0f0f0f0f0f0f0f0fULL);
234 return val;
d9bce9d9
JM		 235}
236#endif
237
fdabc366 238/*****************************************************************************/
9a64fbe4 239/* Floating point operations helpers */
0ca9d380 240static always_inline int fpisneg (float64 d)
7c58044c 241{
0ca9d380 242 CPU_DoubleU u;
7c58044c 243
0ca9d380 244 u.d = d;
7c58044c 245
0ca9d380 246 return u.ll >> 63 != 0;
7c58044c
JM		 247}
248
0ca9d380 249static always_inline int isden (float64 d)
7c58044c 250{
0ca9d380 251 CPU_DoubleU u;
7c58044c 252
0ca9d380 253 u.d = d;
7c58044c 254
0ca9d380 255 return ((u.ll >> 52) & 0x7FF) == 0;
7c58044c
JM		 256}
257
0ca9d380 258static always_inline int iszero (float64 d)
7c58044c 259{
0ca9d380 260 CPU_DoubleU u;
7c58044c 261
0ca9d380 262 u.d = d;
7c58044c 263
0ca9d380 264 return (u.ll & ~0x8000000000000000ULL) == 0;
7c58044c
JM		 265}
266
0ca9d380 267static always_inline int isinfinity (float64 d)
7c58044c 268{
0ca9d380 269 CPU_DoubleU u;
7c58044c 270
0ca9d380 271 u.d = d;
7c58044c 272
0ca9d380
AJ		 273 return ((u.ll >> 52) & 0x7FF) == 0x7FF &&
274 (u.ll & 0x000FFFFFFFFFFFFFULL) == 0;
7c58044c
JM		 275}
276
80621676
AJ		 277#ifdef CONFIG_SOFTFLOAT
278static always_inline int isfinite (float64 d)
279{
280 CPU_DoubleU u;
281
282 u.d = d;
283
284 return (((u.ll >> 52) & 0x7FF) != 0x7FF);
285}
286
287static always_inline int isnormal (float64 d)
288{
289 CPU_DoubleU u;
290
291 u.d = d;
292
293 uint32_t exp = (u.ll >> 52) & 0x7FF;
294 return ((0 < exp) && (exp < 0x7FF));
295}
296#endif
297
af12906f 298uint32_t helper_compute_fprf (uint64_t arg, uint32_t set_fprf)
7c58044c 299{
af12906f 300 CPU_DoubleU farg;
7c58044c 301 int isneg;
af12906f
AJ		 302 int ret;
303 farg.ll = arg;
304 isneg = fpisneg(farg.d);
305 if (unlikely(float64_is_nan(farg.d))) {
306 if (float64_is_signaling_nan(farg.d)) {
7c58044c 307 /* Signaling NaN: flags are undefined */
af12906f 308 ret = 0x00;
7c58044c
JM		 309 } else {
310 /* Quiet NaN */
af12906f 311 ret = 0x11;
7c58044c 312 }
af12906f 313 } else if (unlikely(isinfinity(farg.d))) {
7c58044c
JM		 314 /* +/- infinity */
315 if (isneg)
af12906f 316 ret = 0x09;
7c58044c 317 else
af12906f 318 ret = 0x05;
7c58044c 319 } else {
af12906f 320 if (iszero(farg.d)) {
7c58044c
JM		 321 /* +/- zero */
322 if (isneg)
af12906f 323 ret = 0x12;
7c58044c 324 else
af12906f 325 ret = 0x02;
7c58044c 326 } else {
af12906f 327 if (isden(farg.d)) {
7c58044c 328 /* Denormalized numbers */
af12906f 329 ret = 0x10;
7c58044c
JM		 330 } else {
331 /* Normalized numbers */
af12906f 332 ret = 0x00;
7c58044c
JM		 333 }
334 if (isneg) {
af12906f 335 ret |= 0x08;
7c58044c 336 } else {
af12906f 337 ret |= 0x04;
7c58044c
JM		 338 }
339 }
340 }
341 if (set_fprf) {
342 /* We update FPSCR_FPRF */
343 env->fpscr &= ~(0x1F << FPSCR_FPRF);
af12906f 344 env->fpscr |= ret << FPSCR_FPRF;
7c58044c
JM		 345 }
346 /* We just need fpcc to update Rc1 */
af12906f 347 return ret & 0xF;
7c58044c
JM		 348}
349
350/* Floating-point invalid operations exception */
af12906f 351static always_inline uint64_t fload_invalid_op_excp (int op)
7c58044c 352{
af12906f 353 uint64_t ret = 0;
7c58044c
JM		 354 int ve;
355
356 ve = fpscr_ve;
357 if (op & POWERPC_EXCP_FP_VXSNAN) {
358 /* Operation on signaling NaN */
359 env->fpscr |= 1 << FPSCR_VXSNAN;
360 }
361 if (op & POWERPC_EXCP_FP_VXSOFT) {
362 /* Software-defined condition */
363 env->fpscr |= 1 << FPSCR_VXSOFT;
364 }
365 switch (op & ~(POWERPC_EXCP_FP_VXSOFT | POWERPC_EXCP_FP_VXSNAN)) {
366 case POWERPC_EXCP_FP_VXISI:
367 /* Magnitude subtraction of infinities */
368 env->fpscr |= 1 << FPSCR_VXISI;
369 goto update_arith;
370 case POWERPC_EXCP_FP_VXIDI:
371 /* Division of infinity by infinity */
372 env->fpscr |= 1 << FPSCR_VXIDI;
373 goto update_arith;
374 case POWERPC_EXCP_FP_VXZDZ:
375 /* Division of zero by zero */
376 env->fpscr |= 1 << FPSCR_VXZDZ;
377 goto update_arith;
378 case POWERPC_EXCP_FP_VXIMZ:
379 /* Multiplication of zero by infinity */
380 env->fpscr |= 1 << FPSCR_VXIMZ;
381 goto update_arith;
382 case POWERPC_EXCP_FP_VXVC:
383 /* Ordered comparison of NaN */
384 env->fpscr |= 1 << FPSCR_VXVC;
385 env->fpscr &= ~(0xF << FPSCR_FPCC);
386 env->fpscr |= 0x11 << FPSCR_FPCC;
387 /* We must update the target FPR before raising the exception */
388 if (ve != 0) {
389 env->exception_index = POWERPC_EXCP_PROGRAM;
390 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC;
391 /* Update the floating-point enabled exception summary */
392 env->fpscr |= 1 << FPSCR_FEX;
393 /* Exception is differed */
394 ve = 0;
395 }
396 break;
397 case POWERPC_EXCP_FP_VXSQRT:
398 /* Square root of a negative number */
399 env->fpscr |= 1 << FPSCR_VXSQRT;
400 update_arith:
401 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
402 if (ve == 0) {
403 /* Set the result to quiet NaN */
af12906f 404 ret = UINT64_MAX;
7c58044c
JM		 405 env->fpscr &= ~(0xF << FPSCR_FPCC);
406 env->fpscr |= 0x11 << FPSCR_FPCC;
407 }
408 break;
409 case POWERPC_EXCP_FP_VXCVI:
410 /* Invalid conversion */
411 env->fpscr |= 1 << FPSCR_VXCVI;
412 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
413 if (ve == 0) {
414 /* Set the result to quiet NaN */
af12906f 415 ret = UINT64_MAX;
7c58044c
JM		 416 env->fpscr &= ~(0xF << FPSCR_FPCC);
417 env->fpscr |= 0x11 << FPSCR_FPCC;
418 }
419 break;
420 }
421 /* Update the floating-point invalid operation summary */
422 env->fpscr |= 1 << FPSCR_VX;
423 /* Update the floating-point exception summary */
424 env->fpscr |= 1 << FPSCR_FX;
425 if (ve != 0) {
426 /* Update the floating-point enabled exception summary */
427 env->fpscr |= 1 << FPSCR_FEX;
428 if (msr_fe0 != 0 || msr_fe1 != 0)
64adab3f 429 raise_exception_err(env, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_FP | op);
7c58044c 430 }
af12906f 431 return ret;
7c58044c
JM		 432}
433
af12906f 434static always_inline uint64_t float_zero_divide_excp (uint64_t arg1, uint64_t arg2)
7c58044c 435{
7c58044c
JM		 436 env->fpscr |= 1 << FPSCR_ZX;
437 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
438 /* Update the floating-point exception summary */
439 env->fpscr |= 1 << FPSCR_FX;
440 if (fpscr_ze != 0) {
441 /* Update the floating-point enabled exception summary */
442 env->fpscr |= 1 << FPSCR_FEX;
443 if (msr_fe0 != 0 || msr_fe1 != 0) {
64adab3f
AJ		 444 raise_exception_err(env, POWERPC_EXCP_PROGRAM,
445 POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX);
7c58044c
JM		 446 }
447 } else {
448 /* Set the result to infinity */
af12906f
AJ		 449 arg1 = ((arg1 ^ arg2) & 0x8000000000000000ULL);
450 arg1 |= 0x7FFULL << 52;
7c58044c 451 }
af12906f 452 return arg1;
7c58044c
JM		 453}
454
455static always_inline void float_overflow_excp (void)
456{
457 env->fpscr |= 1 << FPSCR_OX;
458 /* Update the floating-point exception summary */
459 env->fpscr |= 1 << FPSCR_FX;
460 if (fpscr_oe != 0) {
461 /* XXX: should adjust the result */
462 /* Update the floating-point enabled exception summary */
463 env->fpscr |= 1 << FPSCR_FEX;
464 /* We must update the target FPR before raising the exception */
465 env->exception_index = POWERPC_EXCP_PROGRAM;
466 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
467 } else {
468 env->fpscr |= 1 << FPSCR_XX;
469 env->fpscr |= 1 << FPSCR_FI;
470 }
471}
472
473static always_inline void float_underflow_excp (void)
474{
475 env->fpscr |= 1 << FPSCR_UX;
476 /* Update the floating-point exception summary */
477 env->fpscr |= 1 << FPSCR_FX;
478 if (fpscr_ue != 0) {
479 /* XXX: should adjust the result */
480 /* Update the floating-point enabled exception summary */
481 env->fpscr |= 1 << FPSCR_FEX;
482 /* We must update the target FPR before raising the exception */
483 env->exception_index = POWERPC_EXCP_PROGRAM;
484 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
485 }
486}
487
488static always_inline void float_inexact_excp (void)
489{
490 env->fpscr |= 1 << FPSCR_XX;
491 /* Update the floating-point exception summary */
492 env->fpscr |= 1 << FPSCR_FX;
493 if (fpscr_xe != 0) {
494 /* Update the floating-point enabled exception summary */
495 env->fpscr |= 1 << FPSCR_FEX;
496 /* We must update the target FPR before raising the exception */
497 env->exception_index = POWERPC_EXCP_PROGRAM;
498 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
499 }
500}
501
502static always_inline void fpscr_set_rounding_mode (void)
503{
504 int rnd_type;
505
506 /* Set rounding mode */
507 switch (fpscr_rn) {
508 case 0:
509 /* Best approximation (round to nearest) */
510 rnd_type = float_round_nearest_even;
511 break;
512 case 1:
513 /* Smaller magnitude (round toward zero) */
514 rnd_type = float_round_to_zero;
515 break;
516 case 2:
517 /* Round toward +infinite */
518 rnd_type = float_round_up;
519 break;
520 default:
521 case 3:
522 /* Round toward -infinite */
523 rnd_type = float_round_down;
524 break;
525 }
526 set_float_rounding_mode(rnd_type, &env->fp_status);
527}
528
af12906f 529void helper_fpscr_setbit (uint32_t bit)
7c58044c
JM		 530{
531 int prev;
532
533 prev = (env->fpscr >> bit) & 1;
534 env->fpscr |= 1 << bit;
535 if (prev == 0) {
536 switch (bit) {
537 case FPSCR_VX:
538 env->fpscr |= 1 << FPSCR_FX;
539 if (fpscr_ve)
540 goto raise_ve;
541 case FPSCR_OX:
542 env->fpscr |= 1 << FPSCR_FX;
543 if (fpscr_oe)
544 goto raise_oe;
545 break;
546 case FPSCR_UX:
547 env->fpscr |= 1 << FPSCR_FX;
548 if (fpscr_ue)
549 goto raise_ue;
550 break;
551 case FPSCR_ZX:
552 env->fpscr |= 1 << FPSCR_FX;
553 if (fpscr_ze)
554 goto raise_ze;
555 break;
556 case FPSCR_XX:
557 env->fpscr |= 1 << FPSCR_FX;
558 if (fpscr_xe)
559 goto raise_xe;
560 break;
561 case FPSCR_VXSNAN:
562 case FPSCR_VXISI:
563 case FPSCR_VXIDI:
564 case FPSCR_VXZDZ:
565 case FPSCR_VXIMZ:
566 case FPSCR_VXVC:
567 case FPSCR_VXSOFT:
568 case FPSCR_VXSQRT:
569 case FPSCR_VXCVI:
570 env->fpscr |= 1 << FPSCR_VX;
571 env->fpscr |= 1 << FPSCR_FX;
572 if (fpscr_ve != 0)
573 goto raise_ve;
574 break;
575 case FPSCR_VE:
576 if (fpscr_vx != 0) {
577 raise_ve:
578 env->error_code = POWERPC_EXCP_FP;
579 if (fpscr_vxsnan)
580 env->error_code |= POWERPC_EXCP_FP_VXSNAN;
581 if (fpscr_vxisi)
582 env->error_code |= POWERPC_EXCP_FP_VXISI;
583 if (fpscr_vxidi)
584 env->error_code |= POWERPC_EXCP_FP_VXIDI;
585 if (fpscr_vxzdz)
586 env->error_code |= POWERPC_EXCP_FP_VXZDZ;
587 if (fpscr_vximz)
588 env->error_code |= POWERPC_EXCP_FP_VXIMZ;
589 if (fpscr_vxvc)
590 env->error_code |= POWERPC_EXCP_FP_VXVC;
591 if (fpscr_vxsoft)
592 env->error_code |= POWERPC_EXCP_FP_VXSOFT;
593 if (fpscr_vxsqrt)
594 env->error_code |= POWERPC_EXCP_FP_VXSQRT;
595 if (fpscr_vxcvi)
596 env->error_code |= POWERPC_EXCP_FP_VXCVI;
597 goto raise_excp;
598 }
599 break;
600 case FPSCR_OE:
601 if (fpscr_ox != 0) {
602 raise_oe:
603 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
604 goto raise_excp;
605 }
606 break;
607 case FPSCR_UE:
608 if (fpscr_ux != 0) {
609 raise_ue:
610 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
611 goto raise_excp;
612 }
613 break;
614 case FPSCR_ZE:
615 if (fpscr_zx != 0) {
616 raise_ze:
617 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX;
618 goto raise_excp;
619 }
620 break;
621 case FPSCR_XE:
622 if (fpscr_xx != 0) {
623 raise_xe:
624 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
625 goto raise_excp;
626 }
627 break;
628 case FPSCR_RN1:
629 case FPSCR_RN:
630 fpscr_set_rounding_mode();
631 break;
632 default:
633 break;
634 raise_excp:
635 /* Update the floating-point enabled exception summary */
636 env->fpscr |= 1 << FPSCR_FEX;
637 /* We have to update Rc1 before raising the exception */
638 env->exception_index = POWERPC_EXCP_PROGRAM;
639 break;
640 }
641 }
642}
643
af12906f 644void helper_store_fpscr (uint64_t arg, uint32_t mask)
7c58044c
JM		 645{
646 /*
647 * We use only the 32 LSB of the incoming fpr
648 */
7c58044c
JM		 649 uint32_t prev, new;
650 int i;
651
7c58044c 652 prev = env->fpscr;
af12906f 653 new = (uint32_t)arg;
7c58044c
JM		 654 new &= ~0x90000000;
655 new |= prev & 0x90000000;
656 for (i = 0; i < 7; i++) {
657 if (mask & (1 << i)) {
658 env->fpscr &= ~(0xF << (4 * i));
659 env->fpscr |= new & (0xF << (4 * i));
660 }
661 }
662 /* Update VX and FEX */
663 if (fpscr_ix != 0)
664 env->fpscr |= 1 << FPSCR_VX;
5567025f
AJ		 665 else
666 env->fpscr &= ~(1 << FPSCR_VX);
7c58044c
JM		 667 if ((fpscr_ex & fpscr_eex) != 0) {
668 env->fpscr |= 1 << FPSCR_FEX;
669 env->exception_index = POWERPC_EXCP_PROGRAM;
670 /* XXX: we should compute it properly */
671 env->error_code = POWERPC_EXCP_FP;
672 }
5567025f
AJ		 673 else
674 env->fpscr &= ~(1 << FPSCR_FEX);
7c58044c
JM		 675 fpscr_set_rounding_mode();
676}
7c58044c 677
af12906f 678void helper_float_check_status (void)
7c58044c 679{
af12906f 680#ifdef CONFIG_SOFTFLOAT
7c58044c
JM		 681 if (env->exception_index == POWERPC_EXCP_PROGRAM &&
682 (env->error_code & POWERPC_EXCP_FP)) {
683 /* Differred floating-point exception after target FPR update */
684 if (msr_fe0 != 0 || msr_fe1 != 0)
64adab3f 685 raise_exception_err(env, env->exception_index, env->error_code);
7c58044c
JM		 686 } else if (env->fp_status.float_exception_flags & float_flag_overflow) {
687 float_overflow_excp();
688 } else if (env->fp_status.float_exception_flags & float_flag_underflow) {
689 float_underflow_excp();
690 } else if (env->fp_status.float_exception_flags & float_flag_inexact) {
691 float_inexact_excp();
692 }
af12906f
AJ		 693#else
694 if (env->exception_index == POWERPC_EXCP_PROGRAM &&
695 (env->error_code & POWERPC_EXCP_FP)) {
696 /* Differred floating-point exception after target FPR update */
697 if (msr_fe0 != 0 || msr_fe1 != 0)
64adab3f 698 raise_exception_err(env, env->exception_index, env->error_code);
af12906f
AJ		 699 }
700 RETURN();
701#endif
702}
703
704#ifdef CONFIG_SOFTFLOAT
705void helper_reset_fpstatus (void)
706{
707 env->fp_status.float_exception_flags = 0;
7c58044c
JM		 708}
709#endif
710
af12906f
AJ		 711/* fadd - fadd. */
712uint64_t helper_fadd (uint64_t arg1, uint64_t arg2)
7c58044c 713{
af12906f
AJ		 714 CPU_DoubleU farg1, farg2;
715
716 farg1.ll = arg1;
717 farg2.ll = arg2;
718#if USE_PRECISE_EMULATION
719 if (unlikely(float64_is_signaling_nan(farg1.d) ||
720 float64_is_signaling_nan(farg2.d))) {
7c58044c 721 /* sNaN addition */
af12906f
AJ		 722 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
723 } else if (likely(isfinite(farg1.d) || isfinite(farg2.d) ||
724 fpisneg(farg1.d) == fpisneg(farg2.d))) {
725 farg1.d = float64_add(farg1.d, farg2.d, &env->fp_status);
7c58044c
JM		 726 } else {
727 /* Magnitude subtraction of infinities */
af12906f 728 farg1.ll == fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
7c58044c 729 }
af12906f
AJ		 730#else
731 farg1.d = float64_add(farg1.d, farg2.d, &env->fp_status);
732#endif
733 return farg1.ll;
7c58044c
JM		 734}
735
af12906f
AJ		 736/* fsub - fsub. */
737uint64_t helper_fsub (uint64_t arg1, uint64_t arg2)
738{
739 CPU_DoubleU farg1, farg2;
740
741 farg1.ll = arg1;
742 farg2.ll = arg2;
743#if USE_PRECISE_EMULATION
7c58044c 744{
af12906f
AJ		 745 if (unlikely(float64_is_signaling_nan(farg1.d) ||
746 float64_is_signaling_nan(farg2.d))) {
7c58044c 747 /* sNaN subtraction */
af12906f
AJ		 748 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
749 } else if (likely(isfinite(farg1.d) || isfinite(farg2.d) ||
750 fpisneg(farg1.d) != fpisneg(farg2.d))) {
751 farg1.d = float64_sub(farg1.d, farg2.d, &env->fp_status);
7c58044c
JM		 752 } else {
753 /* Magnitude subtraction of infinities */
af12906f 754 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
7c58044c
JM		 755 }
756}
af12906f
AJ		 757#else
758 farg1.d = float64_sub(farg1.d, farg2.d, &env->fp_status);
759#endif
760 return farg1.ll;
761}
7c58044c 762
af12906f
AJ		 763/* fmul - fmul. */
764uint64_t helper_fmul (uint64_t arg1, uint64_t arg2)
7c58044c 765{
af12906f
AJ		 766 CPU_DoubleU farg1, farg2;
767
768 farg1.ll = arg1;
769 farg2.ll = arg2;
770#if USE_PRECISE_EMULATION
771 if (unlikely(float64_is_signaling_nan(farg1.d) ||
772 float64_is_signaling_nan(farg2.d))) {
7c58044c 773 /* sNaN multiplication */
af12906f
AJ		 774 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
775 } else if (unlikely((isinfinity(farg1.d) && iszero(farg2.d)) ||
776 (iszero(farg1.d) && isinfinity(farg2.d)))) {
7c58044c 777 /* Multiplication of zero by infinity */
af12906f 778 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
7c58044c 779 } else {
af12906f 780 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
7c58044c
JM		 781 }
782}
af12906f
AJ		 783#else
784 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
785#endif
786 return farg1.ll;
787}
7c58044c 788
af12906f
AJ		 789/* fdiv - fdiv. */
790uint64_t helper_fdiv (uint64_t arg1, uint64_t arg2)
7c58044c 791{
af12906f
AJ		 792 CPU_DoubleU farg1, farg2;
793
794 farg1.ll = arg1;
795 farg2.ll = arg2;
796#if USE_PRECISE_EMULATION
797 if (unlikely(float64_is_signaling_nan(farg1.d) ||
798 float64_is_signaling_nan(farg2.d))) {
7c58044c 799 /* sNaN division */
af12906f
AJ		 800 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
801 } else if (unlikely(isinfinity(farg1.d) && isinfinity(farg2.d))) {
7c58044c 802 /* Division of infinity by infinity */
af12906f
AJ		 803 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIDI);
804 } else if (unlikely(iszero(farg2.d))) {
805 if (iszero(farg1.d)) {
7c58044c 806 /* Division of zero by zero */
af12906f 807 farg1.ll fload_invalid_op_excp(POWERPC_EXCP_FP_VXZDZ);
7c58044c
JM		 808 } else {
809 /* Division by zero */
af12906f 810 farg1.ll = float_zero_divide_excp(farg1.d, farg2.d);
7c58044c
JM		 811 }
812 } else {
af12906f 813 farg1.d = float64_div(farg1.d, farg2.d, &env->fp_status);
7c58044c 814 }
af12906f
AJ		 815#else
816 farg1.d = float64_div(farg1.d, farg2.d, &env->fp_status);
817#endif
818 return farg1.ll;
7c58044c 819}
7c58044c 820
af12906f
AJ		 821/* fabs */
822uint64_t helper_fabs (uint64_t arg)
9a64fbe4 823{
af12906f 824 CPU_DoubleU farg;
9a64fbe4 825
af12906f
AJ		 826 farg.ll = arg;
827 farg.d = float64_abs(farg.d);
828 return farg.ll;
829}
830
831/* fnabs */
832uint64_t helper_fnabs (uint64_t arg)
833{
834 CPU_DoubleU farg;
835
836 farg.ll = arg;
837 farg.d = float64_abs(farg.d);
838 farg.d = float64_chs(farg.d);
839 return farg.ll;
840}
841
842/* fneg */
843uint64_t helper_fneg (uint64_t arg)
844{
845 CPU_DoubleU farg;
846
847 farg.ll = arg;
848 farg.d = float64_chs(farg.d);
849 return farg.ll;
850}
851
852/* fctiw - fctiw. */
853uint64_t helper_fctiw (uint64_t arg)
854{
855 CPU_DoubleU farg;
856 farg.ll = arg;
857
858 if (unlikely(float64_is_signaling_nan(farg.d))) {
7c58044c 859 /* sNaN conversion */
af12906f
AJ		 860 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
861 } else if (unlikely(float64_is_nan(farg.d) || isinfinity(farg.d))) {
7c58044c 862 /* qNan / infinity conversion */
af12906f 863 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
7c58044c 864 } else {
af12906f 865 farg.ll = float64_to_int32(farg.d, &env->fp_status);
1cdb9c3d 866#if USE_PRECISE_EMULATION
7c58044c
JM		 867 /* XXX: higher bits are not supposed to be significant.
868 * to make tests easier, return the same as a real PowerPC 750
869 */
af12906f 870 farg.ll |= 0xFFF80000ULL << 32;
e864cabd 871#endif
7c58044c 872 }
af12906f 873 return farg.ll;
9a64fbe4
FB		 874}
875
af12906f
AJ		 876/* fctiwz - fctiwz. */
877uint64_t helper_fctiwz (uint64_t arg)
9a64fbe4 878{
af12906f
AJ		 879 CPU_DoubleU farg;
880 farg.ll = arg;
4ecc3190 881
af12906f 882 if (unlikely(float64_is_signaling_nan(farg.d))) {
7c58044c 883 /* sNaN conversion */
af12906f
AJ		 884 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
885 } else if (unlikely(float64_is_nan(farg.d) || isinfinity(farg.d))) {
7c58044c 886 /* qNan / infinity conversion */
af12906f 887 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
7c58044c 888 } else {
af12906f 889 farg.ll = float64_to_int32_round_to_zero(farg.d, &env->fp_status);
1cdb9c3d 890#if USE_PRECISE_EMULATION
7c58044c
JM		 891 /* XXX: higher bits are not supposed to be significant.
892 * to make tests easier, return the same as a real PowerPC 750
893 */
af12906f 894 farg.ll |= 0xFFF80000ULL << 32;
e864cabd 895#endif
7c58044c 896 }
af12906f 897 return farg.ll;
9a64fbe4
FB		 898}
899
426613db 900#if defined(TARGET_PPC64)
af12906f
AJ		 901/* fcfid - fcfid. */
902uint64_t helper_fcfid (uint64_t arg)
426613db 903{
af12906f
AJ		 904 CPU_DoubleU farg;
905 farg.d = int64_to_float64(arg, &env->fp_status);
906 return farg.ll;
426613db
JM		 907}
908
af12906f
AJ		 909/* fctid - fctid. */
910uint64_t helper_fctid (uint64_t arg)
426613db 911{
af12906f
AJ		 912 CPU_DoubleU farg;
913 farg.ll = arg;
426613db 914
af12906f 915 if (unlikely(float64_is_signaling_nan(farg.d))) {
7c58044c 916 /* sNaN conversion */
af12906f
AJ		 917 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
918 } else if (unlikely(float64_is_nan(farg.d) || isinfinity(farg.d))) {
7c58044c 919 /* qNan / infinity conversion */
af12906f 920 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
7c58044c 921 } else {
af12906f 922 farg.ll = float64_to_int64(farg.d, &env->fp_status);
7c58044c 923 }
af12906f 924 return farg.ll;
426613db
JM		 925}
926
af12906f
AJ		 927/* fctidz - fctidz. */
928uint64_t helper_fctidz (uint64_t arg)
426613db 929{
af12906f
AJ		 930 CPU_DoubleU farg;
931 farg.ll = arg;
426613db 932
af12906f 933 if (unlikely(float64_is_signaling_nan(farg.d))) {
7c58044c 934 /* sNaN conversion */
af12906f
AJ		 935 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
936 } else if (unlikely(float64_is_nan(farg.d) || isinfinity(farg.d))) {
7c58044c 937 /* qNan / infinity conversion */
af12906f 938 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
7c58044c 939 } else {
af12906f 940 farg.ll = float64_to_int64_round_to_zero(farg.d, &env->fp_status);
7c58044c 941 }
af12906f 942 return farg.ll;
426613db
JM		 943}
944
945#endif
946
af12906f 947static always_inline uint64_t do_fri (uint64_t arg, int rounding_mode)
d7e4b87e 948{
af12906f
AJ		 949 CPU_DoubleU farg;
950 farg.ll = arg;
951
952 if (unlikely(float64_is_signaling_nan(farg.d))) {
7c58044c 953 /* sNaN round */
af12906f
AJ		 954 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
955 } else if (unlikely(float64_is_nan(farg.d) || isinfinity(farg.d))) {
7c58044c 956 /* qNan / infinity round */
af12906f 957 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
7c58044c
JM		 958 } else {
959 set_float_rounding_mode(rounding_mode, &env->fp_status);
af12906f 960 farg.ll = float64_round_to_int(farg.d, &env->fp_status);
7c58044c
JM		 961 /* Restore rounding mode from FPSCR */
962 fpscr_set_rounding_mode();
963 }
af12906f 964 return farg.ll;
d7e4b87e
JM		 965}
966
af12906f 967uint64_t helper_frin (uint64_t arg)
d7e4b87e 968{
af12906f 969 return do_fri(arg, float_round_nearest_even);
d7e4b87e
JM		 970}
971
af12906f 972uint64_t helper_friz (uint64_t arg)
d7e4b87e 973{
af12906f 974 return do_fri(arg, float_round_to_zero);
d7e4b87e
JM		 975}
976
af12906f 977uint64_t helper_frip (uint64_t arg)
d7e4b87e 978{
af12906f 979 return do_fri(arg, float_round_up);
d7e4b87e
JM		 980}
981
af12906f 982uint64_t helper_frim (uint64_t arg)
d7e4b87e 983{
af12906f 984 return do_fri(arg, float_round_down);
d7e4b87e
JM		 985}
986
af12906f
AJ		 987/* fmadd - fmadd. */
988uint64_t helper_fmadd (uint64_t arg1, uint64_t arg2, uint64_t arg3)
e864cabd 989{
af12906f
AJ		 990 CPU_DoubleU farg1, farg2, farg3;
991
992 farg1.ll = arg1;
993 farg2.ll = arg2;
994 farg3.ll = arg3;
995#if USE_PRECISE_EMULATION
996 if (unlikely(float64_is_signaling_nan(farg1.d) ||
997 float64_is_signaling_nan(farg2.d) ||
998 float64_is_signaling_nan(farg3.d))) {
7c58044c 999 /* sNaN operation */
af12906f 1000 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
7c58044c 1001 } else {
e864cabd 1002#ifdef FLOAT128
7c58044c
JM		 1003 /* This is the way the PowerPC specification defines it */
1004 float128 ft0_128, ft1_128;
1005
af12906f
AJ		 1006 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1007 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
7c58044c 1008 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
af12906f 1009 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
7c58044c 1010 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
af12906f 1011 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
e864cabd 1012#else
7c58044c 1013 /* This is OK on x86 hosts */
af12906f 1014 farg1.d = (farg1.d * farg2.d) + farg3.d;
e864cabd 1015#endif
7c58044c 1016 }
af12906f
AJ		 1017#else
1018 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1019 farg1.d = float64_add(farg1.d, farg3.d, &env->fp_status);
1020#endif
1021 return farg1.ll;
e864cabd
JM		 1022}
1023
af12906f
AJ		 1024/* fmsub - fmsub. */
1025uint64_t helper_fmsub (uint64_t arg1, uint64_t arg2, uint64_t arg3)
e864cabd 1026{
af12906f
AJ		 1027 CPU_DoubleU farg1, farg2, farg3;
1028
1029 farg1.ll = arg1;
1030 farg2.ll = arg2;
1031 farg3.ll = arg3;
1032#if USE_PRECISE_EMULATION
1033 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1034 float64_is_signaling_nan(farg2.d) ||
1035 float64_is_signaling_nan(farg3.d))) {
7c58044c 1036 /* sNaN operation */
af12906f 1037 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
7c58044c 1038 } else {
e864cabd 1039#ifdef FLOAT128
7c58044c
JM		 1040 /* This is the way the PowerPC specification defines it */
1041 float128 ft0_128, ft1_128;
1042
af12906f
AJ		 1043 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1044 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
7c58044c 1045 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
af12906f 1046 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
7c58044c 1047 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
af12906f 1048 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
e864cabd 1049#else
7c58044c 1050 /* This is OK on x86 hosts */
af12906f 1051 farg1.d = (farg1.d * farg2.d) - farg3.d;
e864cabd 1052#endif
7c58044c 1053 }
af12906f
AJ		 1054#else
1055 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1056 farg1.d = float64_sub(farg1.d, farg3.d, &env->fp_status);
1057#endif
1058 return farg1.ll;
e864cabd 1059}
e864cabd 1060
af12906f
AJ		 1061/* fnmadd - fnmadd. */
1062uint64_t helper_fnmadd (uint64_t arg1, uint64_t arg2, uint64_t arg3)
4b3686fa 1063{
af12906f
AJ		 1064 CPU_DoubleU farg1, farg2, farg3;
1065
1066 farg1.ll = arg1;
1067 farg2.ll = arg2;
1068 farg3.ll = arg3;
1069
1070 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1071 float64_is_signaling_nan(farg2.d) ||
1072 float64_is_signaling_nan(farg3.d))) {
7c58044c 1073 /* sNaN operation */
af12906f 1074 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
7c58044c 1075 } else {
1cdb9c3d 1076#if USE_PRECISE_EMULATION
e864cabd 1077#ifdef FLOAT128
7c58044c
JM		 1078 /* This is the way the PowerPC specification defines it */
1079 float128 ft0_128, ft1_128;
1080
af12906f
AJ		 1081 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1082 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
7c58044c 1083 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
af12906f 1084 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
7c58044c 1085 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
af12906f 1086 farg1.d= float128_to_float64(ft0_128, &env->fp_status);
e864cabd 1087#else
7c58044c 1088 /* This is OK on x86 hosts */
af12906f 1089 farg1.d = (farg1.d * farg2.d) + farg3.d;
e864cabd
JM		 1090#endif
1091#else
af12906f
AJ		 1092 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1093 farg1.d = float64_add(farg1.d, farg3.d, &env->fp_status);
e864cabd 1094#endif
af12906f
AJ		 1095 if (likely(!isnan(farg1.d)))
1096 farg1.d = float64_chs(farg1.d);
7c58044c 1097 }
af12906f 1098 return farg1.ll;
4b3686fa
FB		 1099}
1100
af12906f
AJ		 1101/* fnmsub - fnmsub. */
1102uint64_t helper_fnmsub (uint64_t arg1, uint64_t arg2, uint64_t arg3)
4b3686fa 1103{
af12906f
AJ		 1104 CPU_DoubleU farg1, farg2, farg3;
1105
1106 farg1.ll = arg1;
1107 farg2.ll = arg2;
1108 farg3.ll = arg3;
1109
1110 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1111 float64_is_signaling_nan(farg2.d) ||
1112 float64_is_signaling_nan(farg3.d))) {
7c58044c 1113 /* sNaN operation */
af12906f 1114 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
7c58044c 1115 } else {
1cdb9c3d 1116#if USE_PRECISE_EMULATION
e864cabd 1117#ifdef FLOAT128
7c58044c
JM		 1118 /* This is the way the PowerPC specification defines it */
1119 float128 ft0_128, ft1_128;
1120
af12906f
AJ		 1121 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1122 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
7c58044c 1123 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
af12906f 1124 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
7c58044c 1125 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
af12906f 1126 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
e864cabd 1127#else
7c58044c 1128 /* This is OK on x86 hosts */
af12906f 1129 farg1.d = (farg1.d * farg2.d) - farg3.d;
e864cabd
JM		 1130#endif
1131#else
af12906f
AJ		 1132 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1133 farg1.d = float64_sub(farg1.d, farg3.d, &env->fp_status);
e864cabd 1134#endif
af12906f
AJ		 1135 if (likely(!isnan(farg1.d)))
1136 farg1.d = float64_chs(farg1.d);
7c58044c 1137 }
af12906f 1138 return farg1.ll;
1ef59d0a
FB		 1139}
1140
af12906f
AJ		 1141
1142/* frsp - frsp. */
1143uint64_t helper_frsp (uint64_t arg)
7c58044c 1144{
af12906f
AJ		 1145 CPU_DoubleU farg;
1146 farg.ll = arg;
1147
1148#if USE_PRECISE_EMULATION
1149 if (unlikely(float64_is_signaling_nan(farg.d))) {
7c58044c 1150 /* sNaN square root */
af12906f 1151 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
7c58044c 1152 } else {
af12906f 1153 fard.d = float64_to_float32(farg.d, &env->fp_status);
7c58044c 1154 }
af12906f
AJ		 1155#else
1156 farg.d = float64_to_float32(farg.d, &env->fp_status);
1157#endif
1158 return farg.ll;
7c58044c 1159}
7c58044c 1160
af12906f
AJ		 1161/* fsqrt - fsqrt. */
1162uint64_t helper_fsqrt (uint64_t arg)
9a64fbe4 1163{
af12906f
AJ		 1164 CPU_DoubleU farg;
1165 farg.ll = arg;
1166
1167 if (unlikely(float64_is_signaling_nan(farg.d))) {
7c58044c 1168 /* sNaN square root */
af12906f
AJ		 1169 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1170 } else if (unlikely(fpisneg(farg.d) && !iszero(farg.d))) {
7c58044c 1171 /* Square root of a negative nonzero number */
af12906f 1172 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
7c58044c 1173 } else {
af12906f 1174 farg.d = float64_sqrt(farg.d, &env->fp_status);
7c58044c 1175 }
af12906f 1176 return farg.ll;
9a64fbe4
FB		 1177}
1178
af12906f
AJ		 1179/* fre - fre. */
1180uint64_t helper_fre (uint64_t arg)
d7e4b87e 1181{
af12906f
AJ		 1182 CPU_DoubleU farg;
1183 farg.ll = arg;
d7e4b87e 1184
af12906f 1185 if (unlikely(float64_is_signaling_nan(farg.d))) {
7c58044c 1186 /* sNaN reciprocal */
af12906f
AJ		 1187 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1188 } else if (unlikely(iszero(farg.d))) {
7c58044c 1189 /* Zero reciprocal */
af12906f
AJ		 1190 farg.ll = float_zero_divide_excp(1.0, farg.d);
1191 } else if (likely(isnormal(farg.d))) {
1192 farg.d = float64_div(1.0, farg.d, &env->fp_status);
d7e4b87e 1193 } else {
af12906f
AJ		 1194 if (farg.ll == 0x8000000000000000ULL) {
1195 farg.ll = 0xFFF0000000000000ULL;
1196 } else if (farg.ll == 0x0000000000000000ULL) {
1197 farg.ll = 0x7FF0000000000000ULL;
1198 } else if (isnan(farg.d)) {
1199 farg.ll = 0x7FF8000000000000ULL;
1200 } else if (fpisneg(farg.d)) {
1201 farg.ll = 0x8000000000000000ULL;
d7e4b87e 1202 } else {
af12906f 1203 farg.ll = 0x0000000000000000ULL;
d7e4b87e 1204 }
d7e4b87e 1205 }
af12906f 1206 return farg.d;
d7e4b87e
JM		 1207}
1208
af12906f
AJ		 1209/* fres - fres. */
1210uint64_t helper_fres (uint64_t arg)
9a64fbe4 1211{
af12906f
AJ		 1212 CPU_DoubleU farg;
1213 farg.ll = arg;
4ecc3190 1214
af12906f 1215 if (unlikely(float64_is_signaling_nan(farg.d))) {
7c58044c 1216 /* sNaN reciprocal */
af12906f
AJ		 1217 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1218 } else if (unlikely(iszero(farg.d))) {
7c58044c 1219 /* Zero reciprocal */
af12906f
AJ		 1220 farg.ll = float_zero_divide_excp(1.0, farg.d);
1221 } else if (likely(isnormal(farg.d))) {
1cdb9c3d 1222#if USE_PRECISE_EMULATION
af12906f
AJ		 1223 farg.d = float64_div(1.0, farg.d, &env->fp_status);
1224 farg.d = float64_to_float32(farg.d, &env->fp_status);
e864cabd 1225#else
af12906f 1226 farg.d = float32_div(1.0, farg.d, &env->fp_status);
e864cabd 1227#endif
4ecc3190 1228 } else {
af12906f
AJ		 1229 if (farg.ll == 0x8000000000000000ULL) {
1230 farg.ll = 0xFFF0000000000000ULL;
1231 } else if (farg.ll == 0x0000000000000000ULL) {
1232 farg.ll = 0x7FF0000000000000ULL;
1233 } else if (isnan(farg.d)) {
1234 farg.ll = 0x7FF8000000000000ULL;
1235 } else if (fpisneg(farg.d)) {
1236 farg.ll = 0x8000000000000000ULL;
4ecc3190 1237 } else {
af12906f 1238 farg.ll = 0x0000000000000000ULL;
4ecc3190 1239 }
4ecc3190 1240 }
af12906f 1241 return farg.ll;
9a64fbe4
FB		 1242}
1243
af12906f
AJ		 1244/* frsqrte - frsqrte. */
1245uint64_t helper_frsqrte (uint64_t arg)
9a64fbe4 1246{
af12906f
AJ		 1247 CPU_DoubleU farg;
1248 farg.ll = arg;
4ecc3190 1249
af12906f 1250 if (unlikely(float64_is_signaling_nan(farg.d))) {
7c58044c 1251 /* sNaN reciprocal square root */
af12906f
AJ		 1252 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1253 } else if (unlikely(fpisneg(farg.d) && !iszero(farg.d))) {
7c58044c 1254 /* Reciprocal square root of a negative nonzero number */
af12906f
AJ		 1255 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
1256 } else if (likely(isnormal(farg.d))) {
1257 farg.d = float64_sqrt(farg.d, &env->fp_status);
1258 farg.d = float32_div(1.0, farg.d, &env->fp_status);
4ecc3190 1259 } else {
af12906f
AJ		 1260 if (farg.ll == 0x8000000000000000ULL) {
1261 farg.ll = 0xFFF0000000000000ULL;
1262 } else if (farg.ll == 0x0000000000000000ULL) {
1263 farg.ll = 0x7FF0000000000000ULL;
1264 } else if (isnan(farg.d)) {
1265 farg.ll |= 0x000FFFFFFFFFFFFFULL;
1266 } else if (fpisneg(farg.d)) {
1267 farg.ll = 0x7FF8000000000000ULL;
4ecc3190 1268 } else {
af12906f 1269 farg.ll = 0x0000000000000000ULL;
4ecc3190 1270 }
4ecc3190 1271 }
af12906f 1272 return farg.ll;
9a64fbe4
FB		 1273}
1274
af12906f
AJ		 1275/* fsel - fsel. */
1276uint64_t helper_fsel (uint64_t arg1, uint64_t arg2, uint64_t arg3)
9a64fbe4 1277{
af12906f
AJ		 1278 CPU_DoubleU farg1, farg2, farg3;
1279
1280 farg1.ll = arg1;
1281 farg2.ll = arg2;
1282 farg3.ll = arg3;
1283
1284 if (!fpisneg(farg1.d) || iszero(farg1.d))
1285 return farg2.ll;
4ecc3190 1286 else
af12906f 1287 return farg2.ll;
9a64fbe4
FB		 1288}
1289
af12906f 1290uint32_t helper_fcmpu (uint64_t arg1, uint64_t arg2)
9a64fbe4 1291{
af12906f 1292 CPU_DoubleU farg1, farg2;
e1571908 1293 uint32_t ret = 0;
af12906f
AJ		 1294 farg1.ll = arg1;
1295 farg2.ll = arg2;
e1571908 1296
af12906f
AJ		 1297 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1298 float64_is_signaling_nan(farg2.d))) {
7c58044c
JM		 1299 /* sNaN comparison */
1300 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1301 } else {
af12906f 1302 if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
e1571908 1303 ret = 0x08UL;
af12906f 1304 } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
e1571908 1305 ret = 0x04UL;
fdabc366 1306 } else {
e1571908 1307 ret = 0x02UL;
fdabc366 1308 }
9a64fbe4 1309 }
7c58044c 1310 env->fpscr &= ~(0x0F << FPSCR_FPRF);
e1571908
AJ		 1311 env->fpscr |= ret << FPSCR_FPRF;
1312 return ret;
9a64fbe4
FB		 1313}
1314
af12906f 1315uint32_t helper_fcmpo (uint64_t arg1, uint64_t arg2)
9a64fbe4 1316{
af12906f 1317 CPU_DoubleU farg1, farg2;
e1571908 1318 uint32_t ret = 0;
af12906f
AJ		 1319 farg1.ll = arg1;
1320 farg2.ll = arg2;
e1571908 1321
af12906f
AJ		 1322 if (unlikely(float64_is_nan(farg1.d) ||
1323 float64_is_nan(farg2.d))) {
1324 if (float64_is_signaling_nan(farg1.d) ||
1325 float64_is_signaling_nan(farg2.d)) {
7c58044c
JM		 1326 /* sNaN comparison */
1327 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN |
1328 POWERPC_EXCP_FP_VXVC);
1329 } else {
1330 /* qNaN comparison */
1331 fload_invalid_op_excp(POWERPC_EXCP_FP_VXVC);
1332 }
1333 } else {
af12906f 1334 if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
e1571908 1335 ret = 0x08UL;
af12906f 1336 } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
e1571908 1337 ret = 0x04UL;
fdabc366 1338 } else {
e1571908 1339 ret = 0x02UL;
fdabc366 1340 }
9a64fbe4 1341 }
7c58044c 1342 env->fpscr &= ~(0x0F << FPSCR_FPRF);
e1571908
AJ		 1343 env->fpscr |= ret << FPSCR_FPRF;
1344 return ret;
9a64fbe4
FB		 1345}
1346
76a66253 1347#if !defined (CONFIG_USER_ONLY)
6b80055d 1348void cpu_dump_rfi (target_ulong RA, target_ulong msr);
0411a972 1349
6676f424 1350void do_store_msr (void)
0411a972 1351{
6676f424
AJ		 1352 T0 = hreg_store_msr(env, T0, 0);
1353 if (T0 != 0) {
0411a972 1354 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
64adab3f 1355 raise_exception(env, T0);
0411a972
JM		 1356 }
1357}
1358
1359static always_inline void __do_rfi (target_ulong nip, target_ulong msr,
1360 target_ulong msrm, int keep_msrh)
9a64fbe4 1361{
426613db 1362#if defined(TARGET_PPC64)
0411a972
JM		 1363 if (msr & (1ULL << MSR_SF)) {
1364 nip = (uint64_t)nip;
1365 msr &= (uint64_t)msrm;
a42bd6cc 1366 } else {
0411a972
JM		 1367 nip = (uint32_t)nip;
1368 msr = (uint32_t)(msr & msrm);
1369 if (keep_msrh)
1370 msr |= env->msr & ~((uint64_t)0xFFFFFFFF);
a42bd6cc 1371 }
426613db 1372#else
0411a972
JM		 1373 nip = (uint32_t)nip;
1374 msr &= (uint32_t)msrm;
426613db 1375#endif
0411a972
JM		 1376 /* XXX: beware: this is false if VLE is supported */
1377 env->nip = nip & ~((target_ulong)0x00000003);
a4f30719 1378 hreg_store_msr(env, msr, 1);
fdabc366 1379#if defined (DEBUG_OP)
0411a972 1380 cpu_dump_rfi(env->nip, env->msr);
fdabc366 1381#endif
0411a972
JM		 1382 /* No need to raise an exception here,
1383 * as rfi is always the last insn of a TB
1384 */
fdabc366 1385 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
9a64fbe4 1386}
d9bce9d9 1387
0411a972
JM		 1388void do_rfi (void)
1389{
1390 __do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
1391 ~((target_ulong)0xFFFF0000), 1);
1392}
1393
d9bce9d9 1394#if defined(TARGET_PPC64)
426613db
JM		 1395void do_rfid (void)
1396{
0411a972
JM		 1397 __do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
1398 ~((target_ulong)0xFFFF0000), 0);
d9bce9d9 1399}
7863667f 1400
be147d08
JM		 1401void do_hrfid (void)
1402{
0411a972
JM		 1403 __do_rfi(env->spr[SPR_HSRR0], env->spr[SPR_HSRR1],
1404 ~((target_ulong)0xFFFF0000), 0);
be147d08
JM		 1405}
1406#endif
76a66253 1407#endif
9a64fbe4 1408
76a66253 1409void do_tw (int flags)
9a64fbe4 1410{
d9bce9d9
JM		 1411 if (!likely(!(((int32_t)T0 < (int32_t)T1 && (flags & 0x10)) ||
1412 ((int32_t)T0 > (int32_t)T1 && (flags & 0x08)) ||
1413 ((int32_t)T0 == (int32_t)T1 && (flags & 0x04)) ||
1414 ((uint32_t)T0 < (uint32_t)T1 && (flags & 0x02)) ||
a42bd6cc 1415 ((uint32_t)T0 > (uint32_t)T1 && (flags & 0x01))))) {
64adab3f 1416 raise_exception_err(env, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
a42bd6cc 1417 }
9a64fbe4
FB		 1418}
1419
d9bce9d9
JM		 1420#if defined(TARGET_PPC64)
1421void do_td (int flags)
1422{
1423 if (!likely(!(((int64_t)T0 < (int64_t)T1 && (flags & 0x10)) ||
1424 ((int64_t)T0 > (int64_t)T1 && (flags & 0x08)) ||
1425 ((int64_t)T0 == (int64_t)T1 && (flags & 0x04)) ||
1426 ((uint64_t)T0 < (uint64_t)T1 && (flags & 0x02)) ||
1427 ((uint64_t)T0 > (uint64_t)T1 && (flags & 0x01)))))
64adab3f 1428 raise_exception_err(env, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
d9bce9d9
JM		 1429}
1430#endif
1431
fdabc366 1432/*****************************************************************************/
76a66253
JM		 1433/* PowerPC 601 specific instructions (POWER bridge) */
1434void do_POWER_abso (void)
9a64fbe4 1435{
9c7e37e7 1436 if ((int32_t)T0 == INT32_MIN) {
76a66253 1437 T0 = INT32_MAX;
3d7b417e 1438 env->xer |= (1 << XER_OV) | (1 << XER_SO);
9c7e37e7 1439 } else if ((int32_t)T0 < 0) {
76a66253 1440 T0 = -T0;
3d7b417e 1441 env->xer &= ~(1 << XER_OV);
9c7e37e7 1442 } else {
3d7b417e 1443 env->xer &= ~(1 << XER_OV);
76a66253 1444 }
9a64fbe4
FB		 1445}
1446
76a66253 1447void do_POWER_clcs (void)
9a64fbe4 1448{
76a66253
JM		 1449 switch (T0) {
1450 case 0x0CUL:
1451 /* Instruction cache line size */
d63001d1 1452 T0 = env->icache_line_size;
76a66253
JM		 1453 break;
1454 case 0x0DUL:
1455 /* Data cache line size */
d63001d1 1456 T0 = env->dcache_line_size;
76a66253
JM		 1457 break;
1458 case 0x0EUL:
1459 /* Minimum cache line size */
d63001d1
JM		 1460 T0 = env->icache_line_size < env->dcache_line_size ?
1461 env->icache_line_size : env->dcache_line_size;
76a66253
JM		 1462 break;
1463 case 0x0FUL:
1464 /* Maximum cache line size */
d63001d1
JM		 1465 T0 = env->icache_line_size > env->dcache_line_size ?
1466 env->icache_line_size : env->dcache_line_size;
76a66253
JM		 1467 break;
1468 default:
1469 /* Undefined */
1470 break;
1471 }
1472}
1473
1474void do_POWER_div (void)
1475{
1476 uint64_t tmp;
1477
6f2d8978
JM		 1478 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) ||
1479 (int32_t)T1 == 0) {
1480 T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
76a66253
JM		 1481 env->spr[SPR_MQ] = 0;
1482 } else {
1483 tmp = ((uint64_t)T0 << 32) | env->spr[SPR_MQ];
1484 env->spr[SPR_MQ] = tmp % T1;
d9bce9d9 1485 T0 = tmp / (int32_t)T1;
76a66253
JM		 1486 }
1487}
1488
1489void do_POWER_divo (void)
1490{
1491 int64_t tmp;
1492
6f2d8978
JM		 1493 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) ||
1494 (int32_t)T1 == 0) {
1495 T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
76a66253 1496 env->spr[SPR_MQ] = 0;
3d7b417e 1497 env->xer |= (1 << XER_OV) | (1 << XER_SO);
76a66253
JM		 1498 } else {
1499 tmp = ((uint64_t)T0 << 32) | env->spr[SPR_MQ];
1500 env->spr[SPR_MQ] = tmp % T1;
d9bce9d9 1501 tmp /= (int32_t)T1;
76a66253 1502 if (tmp > (int64_t)INT32_MAX || tmp < (int64_t)INT32_MIN) {
3d7b417e 1503 env->xer |= (1 << XER_OV) | (1 << XER_SO);
76a66253 1504 } else {
3d7b417e 1505 env->xer &= ~(1 << XER_OV);
76a66253
JM		 1506 }
1507 T0 = tmp;
1508 }
1509}
1510
1511void do_POWER_divs (void)
1512{
6f2d8978
JM		 1513 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) ||
1514 (int32_t)T1 == 0) {
1515 T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
76a66253
JM		 1516 env->spr[SPR_MQ] = 0;
1517 } else {
1518 env->spr[SPR_MQ] = T0 % T1;
d9bce9d9 1519 T0 = (int32_t)T0 / (int32_t)T1;
76a66253
JM		 1520 }
1521}
1522
1523void do_POWER_divso (void)
1524{
6f2d8978
JM		 1525 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) ||
1526 (int32_t)T1 == 0) {
1527 T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
76a66253 1528 env->spr[SPR_MQ] = 0;
3d7b417e 1529 env->xer |= (1 << XER_OV) | (1 << XER_SO);
76a66253 1530 } else {
d9bce9d9
JM		 1531 T0 = (int32_t)T0 / (int32_t)T1;
1532 env->spr[SPR_MQ] = (int32_t)T0 % (int32_t)T1;
3d7b417e 1533 env->xer &= ~(1 << XER_OV);
76a66253
JM		 1534 }
1535}
1536
1537void do_POWER_dozo (void)
1538{
d9bce9d9 1539 if ((int32_t)T1 > (int32_t)T0) {
76a66253
JM		 1540 T2 = T0;
1541 T0 = T1 - T0;
d9bce9d9
JM		 1542 if (((uint32_t)(~T2) ^ (uint32_t)T1 ^ UINT32_MAX) &
1543 ((uint32_t)(~T2) ^ (uint32_t)T0) & (1UL << 31)) {
3d7b417e 1544 env->xer |= (1 << XER_OV) | (1 << XER_SO);
76a66253 1545 } else {
3d7b417e 1546 env->xer &= ~(1 << XER_OV);
76a66253
JM		 1547 }
1548 } else {
1549 T0 = 0;
3d7b417e 1550 env->xer &= ~(1 << XER_OV);
76a66253
JM		 1551 }
1552}
1553
1554void do_POWER_maskg (void)
1555{
1556 uint32_t ret;
1557
d9bce9d9 1558 if ((uint32_t)T0 == (uint32_t)(T1 + 1)) {
6f2d8978 1559 ret = UINT32_MAX;
76a66253 1560 } else {
6f2d8978
JM		 1561 ret = (UINT32_MAX >> ((uint32_t)T0)) ^
1562 ((UINT32_MAX >> ((uint32_t)T1)) >> 1);
d9bce9d9 1563 if ((uint32_t)T0 > (uint32_t)T1)
76a66253
JM		 1564 ret = ~ret;
1565 }
1566 T0 = ret;
1567}
1568
1569void do_POWER_mulo (void)
1570{
1571 uint64_t tmp;
1572
1573 tmp = (uint64_t)T0 * (uint64_t)T1;
1574 env->spr[SPR_MQ] = tmp >> 32;
1575 T0 = tmp;
1576 if (tmp >> 32 != ((uint64_t)T0 >> 16) * ((uint64_t)T1 >> 16)) {
3d7b417e 1577 env->xer |= (1 << XER_OV) | (1 << XER_SO);
76a66253 1578 } else {
3d7b417e 1579 env->xer &= ~(1 << XER_OV);
76a66253
JM		 1580 }
1581}
1582
1583#if !defined (CONFIG_USER_ONLY)
1584void do_POWER_rac (void)
1585{
76a66253 1586 mmu_ctx_t ctx;
faadf50e 1587 int nb_BATs;
76a66253
JM		 1588
1589 /* We don't have to generate many instances of this instruction,
1590 * as rac is supervisor only.
1591 */
faadf50e
JM		 1592 /* XXX: FIX THIS: Pretend we have no BAT */
1593 nb_BATs = env->nb_BATs;
1594 env->nb_BATs = 0;
1595 if (get_physical_address(env, &ctx, T0, 0, ACCESS_INT) == 0)
76a66253 1596 T0 = ctx.raddr;
faadf50e 1597 env->nb_BATs = nb_BATs;
76a66253
JM		 1598}
1599
1600void do_POWER_rfsvc (void)
1601{
0411a972 1602 __do_rfi(env->lr, env->ctr, 0x0000FFFF, 0);
76a66253
JM		 1603}
1604
056401ea
JM		 1605void do_store_hid0_601 (void)
1606{
1607 uint32_t hid0;
1608
1609 hid0 = env->spr[SPR_HID0];
1610 if ((T0 ^ hid0) & 0x00000008) {
1611 /* Change current endianness */
1612 env->hflags &= ~(1 << MSR_LE);
1613 env->hflags_nmsr &= ~(1 << MSR_LE);
1614 env->hflags_nmsr |= (1 << MSR_LE) & (((T0 >> 3) & 1) << MSR_LE);
1615 env->hflags |= env->hflags_nmsr;
1616 if (loglevel != 0) {
1617 fprintf(logfile, "%s: set endianness to %c => " ADDRX "\n",
1618 __func__, T0 & 0x8 ? 'l' : 'b', env->hflags);
1619 }
1620 }
1621 env->spr[SPR_HID0] = T0;
76a66253
JM		 1622}
1623#endif
1624
1625/*****************************************************************************/
1626/* 602 specific instructions */
1627/* mfrom is the most crazy instruction ever seen, imho ! */
1628/* Real implementation uses a ROM table. Do the same */
1629#define USE_MFROM_ROM_TABLE
1630void do_op_602_mfrom (void)
1631{
1632 if (likely(T0 < 602)) {
d9bce9d9 1633#if defined(USE_MFROM_ROM_TABLE)
76a66253
JM		 1634#include "mfrom_table.c"
1635 T0 = mfrom_ROM_table[T0];
fdabc366 1636#else
76a66253
JM		 1637 double d;
1638 /* Extremly decomposed:
1639 * -T0 / 256
1640 * T0 = 256 * log10(10 + 1.0) + 0.5
1641 */
1642 d = T0;
1643 d = float64_div(d, 256, &env->fp_status);
1644 d = float64_chs(d);
1645 d = exp10(d); // XXX: use float emulation function
1646 d = float64_add(d, 1.0, &env->fp_status);
1647 d = log10(d); // XXX: use float emulation function
1648 d = float64_mul(d, 256, &env->fp_status);
1649 d = float64_add(d, 0.5, &env->fp_status);
1650 T0 = float64_round_to_int(d, &env->fp_status);
fdabc366 1651#endif
76a66253
JM		 1652 } else {
1653 T0 = 0;
1654 }
1655}
1656
1657/*****************************************************************************/
1658/* Embedded PowerPC specific helpers */
76a66253 1659
a750fc0b
JM		 1660/* XXX: to be improved to check access rights when in user-mode */
1661void do_load_dcr (void)
1662{
1663 target_ulong val;
1664
1665 if (unlikely(env->dcr_env == NULL)) {
1666 if (loglevel != 0) {
1667 fprintf(logfile, "No DCR environment\n");
1668 }
64adab3f
AJ		 1669 raise_exception_err(env, POWERPC_EXCP_PROGRAM,
1670 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
a750fc0b
JM		 1671 } else if (unlikely(ppc_dcr_read(env->dcr_env, T0, &val) != 0)) {
1672 if (loglevel != 0) {
1673 fprintf(logfile, "DCR read error %d %03x\n", (int)T0, (int)T0);
1674 }
64adab3f
AJ		 1675 raise_exception_err(env, POWERPC_EXCP_PROGRAM,
1676 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
a750fc0b
JM		 1677 } else {
1678 T0 = val;
1679 }
1680}
1681
1682void do_store_dcr (void)
1683{
1684 if (unlikely(env->dcr_env == NULL)) {
1685 if (loglevel != 0) {
1686 fprintf(logfile, "No DCR environment\n");
1687 }
64adab3f
AJ		 1688 raise_exception_err(env, POWERPC_EXCP_PROGRAM,
1689 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
a750fc0b
JM		 1690 } else if (unlikely(ppc_dcr_write(env->dcr_env, T0, T1) != 0)) {
1691 if (loglevel != 0) {
1692 fprintf(logfile, "DCR write error %d %03x\n", (int)T0, (int)T0);
1693 }
64adab3f
AJ		 1694 raise_exception_err(env, POWERPC_EXCP_PROGRAM,
1695 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
a750fc0b
JM		 1696 }
1697}
1698
76a66253 1699#if !defined(CONFIG_USER_ONLY)
a42bd6cc 1700void do_40x_rfci (void)
76a66253 1701{
0411a972
JM		 1702 __do_rfi(env->spr[SPR_40x_SRR2], env->spr[SPR_40x_SRR3],
1703 ~((target_ulong)0xFFFF0000), 0);
a42bd6cc
JM		 1704}
1705
1706void do_rfci (void)
1707{
0411a972
JM		 1708 __do_rfi(env->spr[SPR_BOOKE_CSRR0], SPR_BOOKE_CSRR1,
1709 ~((target_ulong)0x3FFF0000), 0);
a42bd6cc
JM		 1710}
1711
1712void do_rfdi (void)
1713{
0411a972
JM		 1714 __do_rfi(env->spr[SPR_BOOKE_DSRR0], SPR_BOOKE_DSRR1,
1715 ~((target_ulong)0x3FFF0000), 0);
a42bd6cc
JM		 1716}
1717
1718void do_rfmci (void)
1719{
0411a972
JM		 1720 __do_rfi(env->spr[SPR_BOOKE_MCSRR0], SPR_BOOKE_MCSRR1,
1721 ~((target_ulong)0x3FFF0000), 0);
76a66253
JM		 1722}
1723
76a66253
JM		 1724void do_load_403_pb (int num)
1725{
1726 T0 = env->pb[num];
1727}
1728
1729void do_store_403_pb (int num)
1730{
1731 if (likely(env->pb[num] != T0)) {
1732 env->pb[num] = T0;
1733 /* Should be optimized */
1734 tlb_flush(env, 1);
1735 }
1736}
1737#endif
1738
1739/* 440 specific */
1740void do_440_dlmzb (void)
1741{
1742 target_ulong mask;
1743 int i;
1744
1745 i = 1;
1746 for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
1747 if ((T0 & mask) == 0)
1748 goto done;
1749 i++;
1750 }
1751 for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
1752 if ((T1 & mask) == 0)
1753 break;
1754 i++;
1755 }
1756 done:
1757 T0 = i;
fdabc366
FB		 1758}
1759
1c97856d 1760/*****************************************************************************/
0487d6a8
JM		 1761/* SPE extension helpers */
1762/* Use a table to make this quicker */
1763static uint8_t hbrev[16] = {
1764 0x0, 0x8, 0x4, 0xC, 0x2, 0xA, 0x6, 0xE,
1765 0x1, 0x9, 0x5, 0xD, 0x3, 0xB, 0x7, 0xF,
1766};
1767
b068d6a7 1768static always_inline uint8_t byte_reverse (uint8_t val)
0487d6a8
JM		 1769{
1770 return hbrev[val >> 4] | (hbrev[val & 0xF] << 4);
1771}
1772
b068d6a7 1773static always_inline uint32_t word_reverse (uint32_t val)
0487d6a8
JM		 1774{
1775 return byte_reverse(val >> 24) | (byte_reverse(val >> 16) << 8) |
1776 (byte_reverse(val >> 8) << 16) | (byte_reverse(val) << 24);
1777}
1778
3cd7d1dd 1779#define MASKBITS 16 // Random value - to be fixed (implementation dependant)
57951c27 1780target_ulong helper_brinc (target_ulong arg1, target_ulong arg2)
0487d6a8
JM		 1781{
1782 uint32_t a, b, d, mask;
1783
3cd7d1dd 1784 mask = UINT32_MAX >> (32 - MASKBITS);
57951c27
AJ		 1785 a = arg1 & mask;
1786 b = arg2 & mask;
3cd7d1dd 1787 d = word_reverse(1 + word_reverse(a | ~b));
57951c27 1788 return (arg1 & ~mask) | (d & b);
0487d6a8
JM		 1789}
1790
57951c27 1791uint32_t helper_cntlsw32 (uint32_t val)
0487d6a8
JM		 1792{
1793 if (val & 0x80000000)
603fccce 1794 return clz32(~val);
0487d6a8 1795 else
603fccce 1796 return clz32(val);
0487d6a8
JM		 1797}
1798
57951c27 1799uint32_t helper_cntlzw32 (uint32_t val)
0487d6a8 1800{
603fccce 1801 return clz32(val);
0487d6a8
JM		 1802}
1803
1c97856d
AJ		 1804/* Single-precision floating-point conversions */
1805static always_inline uint32_t efscfsi (uint32_t val)
0487d6a8 1806{
0ca9d380 1807 CPU_FloatU u;
0487d6a8
JM		 1808
1809 u.f = int32_to_float32(val, &env->spe_status);
1810
0ca9d380 1811 return u.l;
0487d6a8
JM		 1812}
1813
1c97856d 1814static always_inline uint32_t efscfui (uint32_t val)
0487d6a8 1815{
0ca9d380 1816 CPU_FloatU u;
0487d6a8
JM		 1817
1818 u.f = uint32_to_float32(val, &env->spe_status);
1819
0ca9d380 1820 return u.l;
0487d6a8
JM		 1821}
1822
1c97856d 1823static always_inline int32_t efsctsi (uint32_t val)
0487d6a8 1824{
0ca9d380 1825 CPU_FloatU u;
0487d6a8 1826
0ca9d380 1827 u.l = val;
0487d6a8
JM		 1828 /* NaN are not treated the same way IEEE 754 does */
1829 if (unlikely(isnan(u.f)))
1830 return 0;
1831
1832 return float32_to_int32(u.f, &env->spe_status);
1833}
1834
1c97856d 1835static always_inline uint32_t efsctui (uint32_t val)
0487d6a8 1836{
0ca9d380 1837 CPU_FloatU u;
0487d6a8 1838
0ca9d380 1839 u.l = val;
0487d6a8
JM		 1840 /* NaN are not treated the same way IEEE 754 does */
1841 if (unlikely(isnan(u.f)))
1842 return 0;
1843
1844 return float32_to_uint32(u.f, &env->spe_status);
1845}
1846
1c97856d 1847static always_inline uint32_t efsctsiz (uint32_t val)
0487d6a8 1848{
0ca9d380 1849 CPU_FloatU u;
0487d6a8 1850
0ca9d380 1851 u.l = val;
0487d6a8
JM		 1852 /* NaN are not treated the same way IEEE 754 does */
1853 if (unlikely(isnan(u.f)))
1854 return 0;
1855
1856 return float32_to_int32_round_to_zero(u.f, &env->spe_status);
1857}
1858
1c97856d 1859static always_inline uint32_t efsctuiz (uint32_t val)
0487d6a8 1860{
0ca9d380 1861 CPU_FloatU u;
0487d6a8 1862
0ca9d380 1863 u.l = val;
0487d6a8
JM		 1864 /* NaN are not treated the same way IEEE 754 does */
1865 if (unlikely(isnan(u.f)))
1866 return 0;
1867
1868 return float32_to_uint32_round_to_zero(u.f, &env->spe_status);
1869}
1870
1c97856d 1871static always_inline uint32_t efscfsf (uint32_t val)
0487d6a8 1872{
0ca9d380 1873 CPU_FloatU u;
0487d6a8
JM		 1874 float32 tmp;
1875
1876 u.f = int32_to_float32(val, &env->spe_status);
1877 tmp = int64_to_float32(1ULL << 32, &env->spe_status);
1878 u.f = float32_div(u.f, tmp, &env->spe_status);
1879
0ca9d380 1880 return u.l;
0487d6a8
JM		 1881}
1882
1c97856d 1883static always_inline uint32_t efscfuf (uint32_t val)
0487d6a8 1884{
0ca9d380 1885 CPU_FloatU u;
0487d6a8
JM		 1886 float32 tmp;
1887
1888 u.f = uint32_to_float32(val, &env->spe_status);
1889 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
1890 u.f = float32_div(u.f, tmp, &env->spe_status);
1891
0ca9d380 1892 return u.l;
0487d6a8
JM		 1893}
1894
1c97856d 1895static always_inline uint32_t efsctsf (uint32_t val)
0487d6a8 1896{
0ca9d380 1897 CPU_FloatU u;
0487d6a8
JM		 1898 float32 tmp;
1899
0ca9d380 1900 u.l = val;
0487d6a8
JM		 1901 /* NaN are not treated the same way IEEE 754 does */
1902 if (unlikely(isnan(u.f)))
1903 return 0;
1904 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
1905 u.f = float32_mul(u.f, tmp, &env->spe_status);
1906
1907 return float32_to_int32(u.f, &env->spe_status);
1908}
1909
1c97856d 1910static always_inline uint32_t efsctuf (uint32_t val)
0487d6a8 1911{
0ca9d380 1912 CPU_FloatU u;
0487d6a8
JM		 1913 float32 tmp;
1914
0ca9d380 1915 u.l = val;
0487d6a8
JM		 1916 /* NaN are not treated the same way IEEE 754 does */
1917 if (unlikely(isnan(u.f)))
1918 return 0;
1919 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
1920 u.f = float32_mul(u.f, tmp, &env->spe_status);
1921
1922 return float32_to_uint32(u.f, &env->spe_status);
1923}
1924
1c97856d
AJ		 1925#define HELPER_SPE_SINGLE_CONV(name) \
1926uint32_t helper_e##name (uint32_t val) \
1927{ \
1928 return e##name(val); \
1929}
1930/* efscfsi */
1931HELPER_SPE_SINGLE_CONV(fscfsi);
1932/* efscfui */
1933HELPER_SPE_SINGLE_CONV(fscfui);
1934/* efscfuf */
1935HELPER_SPE_SINGLE_CONV(fscfuf);
1936/* efscfsf */
1937HELPER_SPE_SINGLE_CONV(fscfsf);
1938/* efsctsi */
1939HELPER_SPE_SINGLE_CONV(fsctsi);
1940/* efsctui */
1941HELPER_SPE_SINGLE_CONV(fsctui);
1942/* efsctsiz */
1943HELPER_SPE_SINGLE_CONV(fsctsiz);
1944/* efsctuiz */
1945HELPER_SPE_SINGLE_CONV(fsctuiz);
1946/* efsctsf */
1947HELPER_SPE_SINGLE_CONV(fsctsf);
1948/* efsctuf */
1949HELPER_SPE_SINGLE_CONV(fsctuf);
1950
1951#define HELPER_SPE_VECTOR_CONV(name) \
1952uint64_t helper_ev##name (uint64_t val) \
1953{ \
1954 return ((uint64_t)e##name(val >> 32) << 32) | \
1955 (uint64_t)e##name(val); \
0487d6a8 1956}
1c97856d
AJ		 1957/* evfscfsi */
1958HELPER_SPE_VECTOR_CONV(fscfsi);
1959/* evfscfui */
1960HELPER_SPE_VECTOR_CONV(fscfui);
1961/* evfscfuf */
1962HELPER_SPE_VECTOR_CONV(fscfuf);
1963/* evfscfsf */
1964HELPER_SPE_VECTOR_CONV(fscfsf);
1965/* evfsctsi */
1966HELPER_SPE_VECTOR_CONV(fsctsi);
1967/* evfsctui */
1968HELPER_SPE_VECTOR_CONV(fsctui);
1969/* evfsctsiz */
1970HELPER_SPE_VECTOR_CONV(fsctsiz);
1971/* evfsctuiz */
1972HELPER_SPE_VECTOR_CONV(fsctuiz);
1973/* evfsctsf */
1974HELPER_SPE_VECTOR_CONV(fsctsf);
1975/* evfsctuf */
1976HELPER_SPE_VECTOR_CONV(fsctuf);
0487d6a8 1977
1c97856d
AJ		 1978/* Single-precision floating-point arithmetic */
1979static always_inline uint32_t efsadd (uint32_t op1, uint32_t op2)
0487d6a8 1980{
1c97856d
AJ		 1981 CPU_FloatU u1, u2;
1982 u1.l = op1;
1983 u2.l = op2;
1984 u1.f = float32_add(u1.f, u2.f, &env->spe_status);
1985 return u1.l;
0487d6a8
JM		 1986}
1987
1c97856d 1988static always_inline uint32_t efssub (uint32_t op1, uint32_t op2)
0487d6a8 1989{
1c97856d
AJ		 1990 CPU_FloatU u1, u2;
1991 u1.l = op1;
1992 u2.l = op2;
1993 u1.f = float32_sub(u1.f, u2.f, &env->spe_status);
1994 return u1.l;
0487d6a8
JM		 1995}
1996
1c97856d 1997static always_inline uint32_t efsmul (uint32_t op1, uint32_t op2)
0487d6a8 1998{
1c97856d
AJ		 1999 CPU_FloatU u1, u2;
2000 u1.l = op1;
2001 u2.l = op2;
2002 u1.f = float32_mul(u1.f, u2.f, &env->spe_status);
2003 return u1.l;
0487d6a8
JM		 2004}
2005
1c97856d 2006static always_inline uint32_t efsdiv (uint32_t op1, uint32_t op2)
0487d6a8 2007{
1c97856d
AJ		 2008 CPU_FloatU u1, u2;
2009 u1.l = op1;
2010 u2.l = op2;
2011 u1.f = float32_div(u1.f, u2.f, &env->spe_status);
2012 return u1.l;
0487d6a8
JM		 2013}
2014
1c97856d
AJ		 2015#define HELPER_SPE_SINGLE_ARITH(name) \
2016uint32_t helper_e##name (uint32_t op1, uint32_t op2) \
2017{ \
2018 return e##name(op1, op2); \
2019}
2020/* efsadd */
2021HELPER_SPE_SINGLE_ARITH(fsadd);
2022/* efssub */
2023HELPER_SPE_SINGLE_ARITH(fssub);
2024/* efsmul */
2025HELPER_SPE_SINGLE_ARITH(fsmul);
2026/* efsdiv */
2027HELPER_SPE_SINGLE_ARITH(fsdiv);
2028
2029#define HELPER_SPE_VECTOR_ARITH(name) \
2030uint64_t helper_ev##name (uint64_t op1, uint64_t op2) \
2031{ \
2032 return ((uint64_t)e##name(op1 >> 32, op2 >> 32) << 32) | \
2033 (uint64_t)e##name(op1, op2); \
2034}
2035/* evfsadd */
2036HELPER_SPE_VECTOR_ARITH(fsadd);
2037/* evfssub */
2038HELPER_SPE_VECTOR_ARITH(fssub);
2039/* evfsmul */
2040HELPER_SPE_VECTOR_ARITH(fsmul);
2041/* evfsdiv */
2042HELPER_SPE_VECTOR_ARITH(fsdiv);
2043
2044/* Single-precision floating-point comparisons */
2045static always_inline uint32_t efststlt (uint32_t op1, uint32_t op2)
0487d6a8 2046{
1c97856d
AJ		 2047 CPU_FloatU u1, u2;
2048 u1.l = op1;
2049 u2.l = op2;
2050 return float32_lt(u1.f, u2.f, &env->spe_status) ? 4 : 0;
0487d6a8
JM		 2051}
2052
1c97856d 2053static always_inline uint32_t efststgt (uint32_t op1, uint32_t op2)
0487d6a8 2054{
1c97856d
AJ		 2055 CPU_FloatU u1, u2;
2056 u1.l = op1;
2057 u2.l = op2;
2058 return float32_le(u1.f, u2.f, &env->spe_status) ? 0 : 4;
0487d6a8
JM		 2059}
2060
1c97856d 2061static always_inline uint32_t efststeq (uint32_t op1, uint32_t op2)
0487d6a8 2062{
1c97856d
AJ		 2063 CPU_FloatU u1, u2;
2064 u1.l = op1;
2065 u2.l = op2;
2066 return float32_eq(u1.f, u2.f, &env->spe_status) ? 4 : 0;
0487d6a8
JM		 2067}
2068
1c97856d 2069static always_inline uint32_t efscmplt (uint32_t op1, uint32_t op2)
0487d6a8
JM		 2070{
2071 /* XXX: TODO: test special values (NaN, infinites, ...) */
1c97856d 2072 return efststlt(op1, op2);
0487d6a8
JM		 2073}
2074
1c97856d 2075static always_inline uint32_t efscmpgt (uint32_t op1, uint32_t op2)
0487d6a8
JM		 2076{
2077 /* XXX: TODO: test special values (NaN, infinites, ...) */
1c97856d 2078 return efststgt(op1, op2);
0487d6a8
JM		 2079}
2080
1c97856d 2081static always_inline uint32_t efscmpeq (uint32_t op1, uint32_t op2)
0487d6a8
JM		 2082{
2083 /* XXX: TODO: test special values (NaN, infinites, ...) */
1c97856d 2084 return efststeq(op1, op2);
0487d6a8
JM		 2085}
2086
1c97856d
AJ		 2087#define HELPER_SINGLE_SPE_CMP(name) \
2088uint32_t helper_e##name (uint32_t op1, uint32_t op2) \
2089{ \
2090 return e##name(op1, op2) << 2; \
2091}
2092/* efststlt */
2093HELPER_SINGLE_SPE_CMP(fststlt);
2094/* efststgt */
2095HELPER_SINGLE_SPE_CMP(fststgt);
2096/* efststeq */
2097HELPER_SINGLE_SPE_CMP(fststeq);
2098/* efscmplt */
2099HELPER_SINGLE_SPE_CMP(fscmplt);
2100/* efscmpgt */
2101HELPER_SINGLE_SPE_CMP(fscmpgt);
2102/* efscmpeq */
2103HELPER_SINGLE_SPE_CMP(fscmpeq);
2104
2105static always_inline uint32_t evcmp_merge (int t0, int t1)
0487d6a8 2106{
1c97856d 2107 return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1);
0487d6a8
JM		 2108}
2109
1c97856d
AJ		 2110#define HELPER_VECTOR_SPE_CMP(name) \
2111uint32_t helper_ev##name (uint64_t op1, uint64_t op2) \
2112{ \
2113 return evcmp_merge(e##name(op1 >> 32, op2 >> 32), e##name(op1, op2)); \
0487d6a8 2114}
1c97856d
AJ		 2115/* evfststlt */
2116HELPER_VECTOR_SPE_CMP(fststlt);
2117/* evfststgt */
2118HELPER_VECTOR_SPE_CMP(fststgt);
2119/* evfststeq */
2120HELPER_VECTOR_SPE_CMP(fststeq);
2121/* evfscmplt */
2122HELPER_VECTOR_SPE_CMP(fscmplt);
2123/* evfscmpgt */
2124HELPER_VECTOR_SPE_CMP(fscmpgt);
2125/* evfscmpeq */
2126HELPER_VECTOR_SPE_CMP(fscmpeq);
0487d6a8 2127
1c97856d
AJ		 2128/* Double-precision floating-point conversion */
2129uint64_t helper_efdcfsi (uint32_t val)
0487d6a8 2130{
1c97856d
AJ		 2131 CPU_DoubleU u;
2132
2133 u.d = int32_to_float64(val, &env->spe_status);
2134
2135 return u.ll;
0487d6a8
JM		 2136}
2137
1c97856d 2138uint64_t helper_efdcfsid (uint64_t val)
0487d6a8 2139{
0ca9d380 2140 CPU_DoubleU u;
0487d6a8 2141
0ca9d380 2142 u.d = int64_to_float64(val, &env->spe_status);
0487d6a8 2143
0ca9d380 2144 return u.ll;
0487d6a8
JM		 2145}
2146
1c97856d
AJ		 2147uint64_t helper_efdcfui (uint32_t val)
2148{
2149 CPU_DoubleU u;
2150
2151 u.d = uint32_to_float64(val, &env->spe_status);
2152
2153 return u.ll;
2154}
2155
2156uint64_t helper_efdcfuid (uint64_t val)
0487d6a8 2157{
0ca9d380 2158 CPU_DoubleU u;
0487d6a8 2159
0ca9d380 2160 u.d = uint64_to_float64(val, &env->spe_status);
0487d6a8 2161
0ca9d380 2162 return u.ll;
0487d6a8
JM		 2163}
2164
1c97856d 2165uint32_t helper_efdctsi (uint64_t val)
0487d6a8 2166{
0ca9d380 2167 CPU_DoubleU u;
0487d6a8 2168
0ca9d380 2169 u.ll = val;
0487d6a8 2170 /* NaN are not treated the same way IEEE 754 does */
0ca9d380 2171 if (unlikely(isnan(u.d)))
0487d6a8
JM		 2172 return 0;
2173
1c97856d 2174 return float64_to_int32(u.d, &env->spe_status);
0487d6a8
JM		 2175}
2176
1c97856d 2177uint32_t helper_efdctui (uint64_t val)
0487d6a8 2178{
0ca9d380 2179 CPU_DoubleU u;
0487d6a8 2180
0ca9d380 2181 u.ll = val;
0487d6a8 2182 /* NaN are not treated the same way IEEE 754 does */
0ca9d380 2183 if (unlikely(isnan(u.d)))
0487d6a8
JM		 2184 return 0;
2185
1c97856d 2186 return float64_to_uint32(u.d, &env->spe_status);
0487d6a8
JM		 2187}
2188
1c97856d 2189uint32_t helper_efdctsiz (uint64_t val)
0487d6a8 2190{
0ca9d380 2191 CPU_DoubleU u;
0487d6a8 2192
0ca9d380 2193 u.ll = val;
0487d6a8 2194 /* NaN are not treated the same way IEEE 754 does */
0ca9d380 2195 if (unlikely(isnan(u.d)))
0487d6a8
JM		 2196 return 0;
2197
1c97856d 2198 return float64_to_int32_round_to_zero(u.d, &env->spe_status);
0487d6a8
JM		 2199}
2200
1c97856d 2201uint64_t helper_efdctsidz (uint64_t val)
0487d6a8 2202{
0ca9d380 2203 CPU_DoubleU u;
0487d6a8 2204
0ca9d380 2205 u.ll = val;
0487d6a8 2206 /* NaN are not treated the same way IEEE 754 does */
0ca9d380 2207 if (unlikely(isnan(u.d)))
0487d6a8
JM		 2208 return 0;
2209
1c97856d 2210 return float64_to_int64_round_to_zero(u.d, &env->spe_status);
0487d6a8
JM		 2211}
2212
1c97856d 2213uint32_t helper_efdctuiz (uint64_t val)
0487d6a8 2214{
1c97856d 2215 CPU_DoubleU u;
0487d6a8 2216
1c97856d
AJ		 2217 u.ll = val;
2218 /* NaN are not treated the same way IEEE 754 does */
2219 if (unlikely(isnan(u.d)))
2220 return 0;
0487d6a8 2221
1c97856d 2222 return float64_to_uint32_round_to_zero(u.d, &env->spe_status);
0487d6a8
JM		 2223}
2224
1c97856d 2225uint64_t helper_efdctuidz (uint64_t val)
0487d6a8 2226{
1c97856d 2227 CPU_DoubleU u;
0487d6a8 2228
1c97856d
AJ		 2229 u.ll = val;
2230 /* NaN are not treated the same way IEEE 754 does */
2231 if (unlikely(isnan(u.d)))
2232 return 0;
0487d6a8 2233
1c97856d 2234 return float64_to_uint64_round_to_zero(u.d, &env->spe_status);
0487d6a8
JM		 2235}
2236
1c97856d 2237uint64_t helper_efdcfsf (uint32_t val)
0487d6a8 2238{
0ca9d380 2239 CPU_DoubleU u;
0487d6a8
JM		 2240 float64 tmp;
2241
0ca9d380 2242 u.d = int32_to_float64(val, &env->spe_status);
0487d6a8 2243 tmp = int64_to_float64(1ULL << 32, &env->spe_status);
0ca9d380 2244 u.d = float64_div(u.d, tmp, &env->spe_status);
0487d6a8 2245
0ca9d380 2246 return u.ll;
0487d6a8
JM		 2247}
2248
1c97856d 2249uint64_t helper_efdcfuf (uint32_t val)
0487d6a8 2250{
0ca9d380 2251 CPU_DoubleU u;
0487d6a8
JM		 2252 float64 tmp;
2253
0ca9d380 2254 u.d = uint32_to_float64(val, &env->spe_status);
0487d6a8 2255 tmp = int64_to_float64(1ULL << 32, &env->spe_status);
0ca9d380 2256 u.d = float64_div(u.d, tmp, &env->spe_status);
0487d6a8 2257
0ca9d380 2258 return u.ll;
0487d6a8
JM		 2259}
2260
1c97856d 2261uint32_t helper_efdctsf (uint64_t val)
0487d6a8 2262{
0ca9d380 2263 CPU_DoubleU u;
0487d6a8
JM		 2264 float64 tmp;
2265
0ca9d380 2266 u.ll = val;
0487d6a8 2267 /* NaN are not treated the same way IEEE 754 does */
0ca9d380 2268 if (unlikely(isnan(u.d)))
0487d6a8
JM		 2269 return 0;
2270 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
0ca9d380 2271 u.d = float64_mul(u.d, tmp, &env->spe_status);
0487d6a8 2272
0ca9d380 2273 return float64_to_int32(u.d, &env->spe_status);
0487d6a8
JM		 2274}
2275
1c97856d 2276uint32_t helper_efdctuf (uint64_t val)
0487d6a8 2277{
0ca9d380 2278 CPU_DoubleU u;
0487d6a8
JM		 2279 float64 tmp;
2280
0ca9d380 2281 u.ll = val;
0487d6a8 2282 /* NaN are not treated the same way IEEE 754 does */
0ca9d380 2283 if (unlikely(isnan(u.d)))
0487d6a8
JM		 2284 return 0;
2285 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
0ca9d380 2286 u.d = float64_mul(u.d, tmp, &env->spe_status);
0487d6a8 2287
0ca9d380 2288 return float64_to_uint32(u.d, &env->spe_status);
0487d6a8
JM		 2289}
2290
1c97856d 2291uint32_t helper_efscfd (uint64_t val)
0487d6a8 2292{
0ca9d380
AJ		 2293 CPU_DoubleU u1;
2294 CPU_FloatU u2;
0487d6a8 2295
0ca9d380
AJ		 2296 u1.ll = val;
2297 u2.f = float64_to_float32(u1.d, &env->spe_status);
0487d6a8 2298
0ca9d380 2299 return u2.l;
0487d6a8
JM		 2300}
2301
1c97856d 2302uint64_t helper_efdcfs (uint32_t val)
0487d6a8 2303{
0ca9d380
AJ		 2304 CPU_DoubleU u2;
2305 CPU_FloatU u1;
0487d6a8 2306
0ca9d380
AJ		 2307 u1.l = val;
2308 u2.d = float32_to_float64(u1.f, &env->spe_status);
0487d6a8 2309
0ca9d380 2310 return u2.ll;
0487d6a8
JM		 2311}
2312
1c97856d
AJ		 2313/* Double precision fixed-point arithmetic */
2314uint64_t helper_efdadd (uint64_t op1, uint64_t op2)
0487d6a8 2315{
1c97856d
AJ		 2316 CPU_DoubleU u1, u2;
2317 u1.ll = op1;
2318 u2.ll = op2;
2319 u1.d = float64_add(u1.d, u2.d, &env->spe_status);
2320 return u1.ll;
0487d6a8
JM		 2321}
2322
1c97856d 2323uint64_t helper_efdsub (uint64_t op1, uint64_t op2)
0487d6a8 2324{
1c97856d
AJ		 2325 CPU_DoubleU u1, u2;
2326 u1.ll = op1;
2327 u2.ll = op2;
2328 u1.d = float64_sub(u1.d, u2.d, &env->spe_status);
2329 return u1.ll;
0487d6a8
JM		 2330}
2331
1c97856d 2332uint64_t helper_efdmul (uint64_t op1, uint64_t op2)
0487d6a8 2333{
1c97856d
AJ		 2334 CPU_DoubleU u1, u2;
2335 u1.ll = op1;
2336 u2.ll = op2;
2337 u1.d = float64_mul(u1.d, u2.d, &env->spe_status);
2338 return u1.ll;
0487d6a8
JM		 2339}
2340
1c97856d 2341uint64_t helper_efddiv (uint64_t op1, uint64_t op2)
0487d6a8 2342{
1c97856d
AJ		 2343 CPU_DoubleU u1, u2;
2344 u1.ll = op1;
2345 u2.ll = op2;
2346 u1.d = float64_div(u1.d, u2.d, &env->spe_status);
2347 return u1.ll;
0487d6a8
JM		 2348}
2349
1c97856d
AJ		 2350/* Double precision floating point helpers */
2351uint32_t helper_efdtstlt (uint64_t op1, uint64_t op2)
0487d6a8 2352{
1c97856d
AJ		 2353 CPU_DoubleU u1, u2;
2354 u1.ll = op1;
2355 u2.ll = op2;
2356 return float64_lt(u1.d, u2.d, &env->spe_status) ? 4 : 0;
0487d6a8
JM		 2357}
2358
1c97856d 2359uint32_t helper_efdtstgt (uint64_t op1, uint64_t op2)
0487d6a8 2360{
1c97856d
AJ		 2361 CPU_DoubleU u1, u2;
2362 u1.ll = op1;
2363 u2.ll = op2;
2364 return float64_le(u1.d, u2.d, &env->spe_status) ? 0 : 4;
0487d6a8
JM		 2365}
2366
1c97856d 2367uint32_t helper_efdtsteq (uint64_t op1, uint64_t op2)
0487d6a8 2368{
1c97856d
AJ		 2369 CPU_DoubleU u1, u2;
2370 u1.ll = op1;
2371 u2.ll = op2;
2372 return float64_eq(u1.d, u2.d, &env->spe_status) ? 4 : 0;
0487d6a8
JM		 2373}
2374
1c97856d 2375uint32_t helper_efdcmplt (uint64_t op1, uint64_t op2)
0487d6a8 2376{
1c97856d
AJ		 2377 /* XXX: TODO: test special values (NaN, infinites, ...) */
2378 return helper_efdtstlt(op1, op2);
0487d6a8
JM		 2379}
2380
1c97856d
AJ		 2381uint32_t helper_efdcmpgt (uint64_t op1, uint64_t op2)
2382{
2383 /* XXX: TODO: test special values (NaN, infinites, ...) */
2384 return helper_efdtstgt(op1, op2);
2385}
0487d6a8 2386
1c97856d
AJ		 2387uint32_t helper_efdcmpeq (uint64_t op1, uint64_t op2)
2388{
2389 /* XXX: TODO: test special values (NaN, infinites, ...) */
2390 return helper_efdtsteq(op1, op2);
2391}
0487d6a8 2392
fdabc366
FB		 2393/*****************************************************************************/
2394/* Softmmu support */
2395#if !defined (CONFIG_USER_ONLY)
2396
2397#define MMUSUFFIX _mmu
fdabc366
FB		 2398
2399#define SHIFT 0
2400#include "softmmu_template.h"
2401
2402#define SHIFT 1
2403#include "softmmu_template.h"
2404
2405#define SHIFT 2
2406#include "softmmu_template.h"
2407
2408#define SHIFT 3
2409#include "softmmu_template.h"
2410
2411/* try to fill the TLB and return an exception if error. If retaddr is
2412 NULL, it means that the function was called in C code (i.e. not
2413 from generated code or from helper.c) */
2414/* XXX: fix it to restore all registers */
6ebbf390 2415void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
fdabc366
FB		 2416{
2417 TranslationBlock *tb;
2418 CPUState *saved_env;
44f8625d 2419 unsigned long pc;
fdabc366
FB		 2420 int ret;
2421
2422 /* XXX: hack to restore env in all cases, even if not called from
2423 generated code */
2424 saved_env = env;
2425 env = cpu_single_env;
6ebbf390 2426 ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
76a66253 2427 if (unlikely(ret != 0)) {
fdabc366
FB		 2428 if (likely(retaddr)) {
2429 /* now we have a real cpu fault */
44f8625d 2430 pc = (unsigned long)retaddr;
fdabc366
FB		 2431 tb = tb_find_pc(pc);
2432 if (likely(tb)) {
2433 /* the PC is inside the translated code. It means that we have
2434 a virtual CPU fault */
2435 cpu_restore_state(tb, env, pc, NULL);
76a66253 2436 }
fdabc366 2437 }
64adab3f 2438 raise_exception_err(env, env->exception_index, env->error_code);
fdabc366
FB		 2439 }
2440 env = saved_env;
9a64fbe4
FB		 2441}
2442
76a66253
JM		 2443/* Software driven TLBs management */
2444/* PowerPC 602/603 software TLB load instructions helpers */
2445void do_load_6xx_tlb (int is_code)
2446{
2447 target_ulong RPN, CMP, EPN;
2448 int way;
d9bce9d9 2449
76a66253
JM		 2450 RPN = env->spr[SPR_RPA];
2451 if (is_code) {
2452 CMP = env->spr[SPR_ICMP];
2453 EPN = env->spr[SPR_IMISS];
2454 } else {
2455 CMP = env->spr[SPR_DCMP];
2456 EPN = env->spr[SPR_DMISS];
2457 }
2458 way = (env->spr[SPR_SRR1] >> 17) & 1;
2459#if defined (DEBUG_SOFTWARE_TLB)
2460 if (loglevel != 0) {
6b542af7
JM		 2461 fprintf(logfile, "%s: EPN " TDX " " ADDRX " PTE0 " ADDRX
2462 " PTE1 " ADDRX " way %d\n",
2463 __func__, T0, EPN, CMP, RPN, way);
76a66253
JM		 2464 }
2465#endif
2466 /* Store this TLB */
d9bce9d9
JM		 2467 ppc6xx_tlb_store(env, (uint32_t)(T0 & TARGET_PAGE_MASK),
2468 way, is_code, CMP, RPN);
76a66253
JM		 2469}
2470
7dbe11ac
JM		 2471void do_load_74xx_tlb (int is_code)
2472{
2473 target_ulong RPN, CMP, EPN;
2474 int way;
2475
2476 RPN = env->spr[SPR_PTELO];
2477 CMP = env->spr[SPR_PTEHI];
2478 EPN = env->spr[SPR_TLBMISS] & ~0x3;
2479 way = env->spr[SPR_TLBMISS] & 0x3;
2480#if defined (DEBUG_SOFTWARE_TLB)
2481 if (loglevel != 0) {
6b542af7
JM		 2482 fprintf(logfile, "%s: EPN " TDX " " ADDRX " PTE0 " ADDRX
2483 " PTE1 " ADDRX " way %d\n",
2484 __func__, T0, EPN, CMP, RPN, way);
7dbe11ac
JM		 2485 }
2486#endif
2487 /* Store this TLB */
2488 ppc6xx_tlb_store(env, (uint32_t)(T0 & TARGET_PAGE_MASK),
2489 way, is_code, CMP, RPN);
2490}
2491
a11b8151 2492static always_inline target_ulong booke_tlb_to_page_size (int size)
a8dea12f
JM		 2493{
2494 return 1024 << (2 * size);
2495}
2496
a11b8151 2497static always_inline int booke_page_size_to_tlb (target_ulong page_size)
a8dea12f
JM		 2498{
2499 int size;
2500
2501 switch (page_size) {
2502 case 0x00000400UL:
2503 size = 0x0;
2504 break;
2505 case 0x00001000UL:
2506 size = 0x1;
2507 break;
2508 case 0x00004000UL:
2509 size = 0x2;
2510 break;
2511 case 0x00010000UL:
2512 size = 0x3;
2513 break;
2514 case 0x00040000UL:
2515 size = 0x4;
2516 break;
2517 case 0x00100000UL:
2518 size = 0x5;
2519 break;
2520 case 0x00400000UL:
2521 size = 0x6;
2522 break;
2523 case 0x01000000UL:
2524 size = 0x7;
2525 break;
2526 case 0x04000000UL:
2527 size = 0x8;
2528 break;
2529 case 0x10000000UL:
2530 size = 0x9;
2531 break;
2532 case 0x40000000UL:
2533 size = 0xA;
2534 break;
2535#if defined (TARGET_PPC64)
2536 case 0x000100000000ULL:
2537 size = 0xB;
2538 break;
2539 case 0x000400000000ULL:
2540 size = 0xC;
2541 break;
2542 case 0x001000000000ULL:
2543 size = 0xD;
2544 break;
2545 case 0x004000000000ULL:
2546 size = 0xE;
2547 break;
2548 case 0x010000000000ULL:
2549 size = 0xF;
2550 break;
2551#endif
2552 default:
2553 size = -1;
2554 break;
2555 }
2556
2557 return size;
2558}
2559
76a66253 2560/* Helpers for 4xx TLB management */
76a66253
JM		 2561void do_4xx_tlbre_lo (void)
2562{
a8dea12f
JM		 2563 ppcemb_tlb_t *tlb;
2564 int size;
76a66253
JM		 2565
2566 T0 &= 0x3F;
a8dea12f
JM		 2567 tlb = &env->tlb[T0].tlbe;
2568 T0 = tlb->EPN;
2569 if (tlb->prot & PAGE_VALID)
2570 T0 |= 0x400;
2571 size = booke_page_size_to_tlb(tlb->size);
2572 if (size < 0 || size > 0x7)
2573 size = 1;
2574 T0 |= size << 7;
2575 env->spr[SPR_40x_PID] = tlb->PID;
76a66253
JM		 2576}
2577
2578void do_4xx_tlbre_hi (void)
2579{
a8dea12f 2580 ppcemb_tlb_t *tlb;
76a66253
JM		 2581
2582 T0 &= 0x3F;
a8dea12f
JM		 2583 tlb = &env->tlb[T0].tlbe;
2584 T0 = tlb->RPN;
2585 if (tlb->prot & PAGE_EXEC)
2586 T0 |= 0x200;
2587 if (tlb->prot & PAGE_WRITE)
2588 T0 |= 0x100;
76a66253
JM		 2589}
2590
c55e9aef 2591void do_4xx_tlbwe_hi (void)
76a66253 2592{
a8dea12f 2593 ppcemb_tlb_t *tlb;
76a66253
JM		 2594 target_ulong page, end;
2595
c55e9aef 2596#if defined (DEBUG_SOFTWARE_TLB)
6b80055d 2597 if (loglevel != 0) {
6b542af7 2598 fprintf(logfile, "%s T0 " TDX " T1 " TDX "\n", __func__, T0, T1);
c55e9aef
JM		 2599 }
2600#endif
76a66253 2601 T0 &= 0x3F;
a8dea12f 2602 tlb = &env->tlb[T0].tlbe;
76a66253
JM		 2603 /* Invalidate previous TLB (if it's valid) */
2604 if (tlb->prot & PAGE_VALID) {
2605 end = tlb->EPN + tlb->size;
c55e9aef 2606#if defined (DEBUG_SOFTWARE_TLB)
6b80055d 2607 if (loglevel != 0) {
c55e9aef
JM		 2608 fprintf(logfile, "%s: invalidate old TLB %d start " ADDRX
2609 " end " ADDRX "\n", __func__, (int)T0, tlb->EPN, end);
2610 }
2611#endif
76a66253
JM		 2612 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2613 tlb_flush_page(env, page);
2614 }
a8dea12f 2615 tlb->size = booke_tlb_to_page_size((T1 >> 7) & 0x7);
c294fc58
JM		 2616 /* We cannot handle TLB size < TARGET_PAGE_SIZE.
2617 * If this ever occurs, one should use the ppcemb target instead
2618 * of the ppc or ppc64 one
2619 */
2620 if ((T1 & 0x40) && tlb->size < TARGET_PAGE_SIZE) {
71c8b8fd
JM		 2621 cpu_abort(env, "TLB size " TARGET_FMT_lu " < %u "
2622 "are not supported (%d)\n",
c294fc58
JM		 2623 tlb->size, TARGET_PAGE_SIZE, (int)((T1 >> 7) & 0x7));
2624 }
a750fc0b 2625 tlb->EPN = T1 & ~(tlb->size - 1);
c55e9aef 2626 if (T1 & 0x40)
76a66253
JM		 2627 tlb->prot |= PAGE_VALID;
2628 else
2629 tlb->prot &= ~PAGE_VALID;
c294fc58
JM		 2630 if (T1 & 0x20) {
2631 /* XXX: TO BE FIXED */
2632 cpu_abort(env, "Little-endian TLB entries are not supported by now\n");
2633 }
c55e9aef 2634 tlb->PID = env->spr[SPR_40x_PID]; /* PID */
a8dea12f 2635 tlb->attr = T1 & 0xFF;
c55e9aef 2636#if defined (DEBUG_SOFTWARE_TLB)
c294fc58
JM		 2637 if (loglevel != 0) {
2638 fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
c55e9aef 2639 " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
5fafdf24 2640 (int)T0, tlb->RPN, tlb->EPN, tlb->size,
c55e9aef
JM		 2641 tlb->prot & PAGE_READ ? 'r' : '-',
2642 tlb->prot & PAGE_WRITE ? 'w' : '-',
2643 tlb->prot & PAGE_EXEC ? 'x' : '-',
2644 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
2645 }
2646#endif
76a66253
JM		 2647 /* Invalidate new TLB (if valid) */
2648 if (tlb->prot & PAGE_VALID) {
2649 end = tlb->EPN + tlb->size;
c55e9aef 2650#if defined (DEBUG_SOFTWARE_TLB)
6b80055d 2651 if (loglevel != 0) {
c55e9aef
JM		 2652 fprintf(logfile, "%s: invalidate TLB %d start " ADDRX
2653 " end " ADDRX "\n", __func__, (int)T0, tlb->EPN, end);
2654 }
2655#endif
76a66253
JM		 2656 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2657 tlb_flush_page(env, page);
2658 }
76a66253
JM		 2659}
2660
c55e9aef 2661void do_4xx_tlbwe_lo (void)
76a66253 2662{
a8dea12f 2663 ppcemb_tlb_t *tlb;
76a66253 2664
c55e9aef 2665#if defined (DEBUG_SOFTWARE_TLB)
6b80055d 2666 if (loglevel != 0) {
6b542af7 2667 fprintf(logfile, "%s T0 " TDX " T1 " TDX "\n", __func__, T0, T1);
c55e9aef
JM		 2668 }
2669#endif
76a66253 2670 T0 &= 0x3F;
a8dea12f 2671 tlb = &env->tlb[T0].tlbe;
76a66253
JM		 2672 tlb->RPN = T1 & 0xFFFFFC00;
2673 tlb->prot = PAGE_READ;
2674 if (T1 & 0x200)
2675 tlb->prot |= PAGE_EXEC;
2676 if (T1 & 0x100)
2677 tlb->prot |= PAGE_WRITE;
c55e9aef 2678#if defined (DEBUG_SOFTWARE_TLB)
6b80055d
JM		 2679 if (loglevel != 0) {
2680 fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
c55e9aef 2681 " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
5fafdf24 2682 (int)T0, tlb->RPN, tlb->EPN, tlb->size,
c55e9aef
JM		 2683 tlb->prot & PAGE_READ ? 'r' : '-',
2684 tlb->prot & PAGE_WRITE ? 'w' : '-',
2685 tlb->prot & PAGE_EXEC ? 'x' : '-',
2686 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
2687 }
2688#endif
76a66253 2689}
5eb7995e 2690
a4bb6c3e
JM		 2691/* PowerPC 440 TLB management */
2692void do_440_tlbwe (int word)
5eb7995e
JM		 2693{
2694 ppcemb_tlb_t *tlb;
a4bb6c3e 2695 target_ulong EPN, RPN, size;
5eb7995e
JM		 2696 int do_flush_tlbs;
2697
2698#if defined (DEBUG_SOFTWARE_TLB)
2699 if (loglevel != 0) {
6b542af7 2700 fprintf(logfile, "%s word %d T0 " TDX " T1 " TDX "\n",
69facb78 2701 __func__, word, T0, T1);
5eb7995e
JM		 2702 }
2703#endif
2704 do_flush_tlbs = 0;
2705 T0 &= 0x3F;
2706 tlb = &env->tlb[T0].tlbe;
a4bb6c3e
JM		 2707 switch (word) {
2708 default:
2709 /* Just here to please gcc */
2710 case 0:
2711 EPN = T1 & 0xFFFFFC00;
2712 if ((tlb->prot & PAGE_VALID) && EPN != tlb->EPN)
5eb7995e 2713 do_flush_tlbs = 1;
a4bb6c3e
JM		 2714 tlb->EPN = EPN;
2715 size = booke_tlb_to_page_size((T1 >> 4) & 0xF);
2716 if ((tlb->prot & PAGE_VALID) && tlb->size < size)
2717 do_flush_tlbs = 1;
2718 tlb->size = size;
2719 tlb->attr &= ~0x1;
2720 tlb->attr |= (T1 >> 8) & 1;
2721 if (T1 & 0x200) {
2722 tlb->prot |= PAGE_VALID;
2723 } else {
2724 if (tlb->prot & PAGE_VALID) {
2725 tlb->prot &= ~PAGE_VALID;
2726 do_flush_tlbs = 1;
2727 }
5eb7995e 2728 }
a4bb6c3e
JM		 2729 tlb->PID = env->spr[SPR_440_MMUCR] & 0x000000FF;
2730 if (do_flush_tlbs)
2731 tlb_flush(env, 1);
2732 break;
2733 case 1:
2734 RPN = T1 & 0xFFFFFC0F;
2735 if ((tlb->prot & PAGE_VALID) && tlb->RPN != RPN)
2736 tlb_flush(env, 1);
2737 tlb->RPN = RPN;
2738 break;
2739 case 2:
2740 tlb->attr = (tlb->attr & 0x1) | (T1 & 0x0000FF00);
2741 tlb->prot = tlb->prot & PAGE_VALID;
2742 if (T1 & 0x1)
2743 tlb->prot |= PAGE_READ << 4;
2744 if (T1 & 0x2)
2745 tlb->prot |= PAGE_WRITE << 4;
2746 if (T1 & 0x4)
2747 tlb->prot |= PAGE_EXEC << 4;
2748 if (T1 & 0x8)
2749 tlb->prot |= PAGE_READ;
2750 if (T1 & 0x10)
2751 tlb->prot |= PAGE_WRITE;
2752 if (T1 & 0x20)
2753 tlb->prot |= PAGE_EXEC;
2754 break;
5eb7995e 2755 }
5eb7995e
JM		 2756}
2757
a4bb6c3e 2758void do_440_tlbre (int word)
5eb7995e
JM		 2759{
2760 ppcemb_tlb_t *tlb;
2761 int size;
2762
2763 T0 &= 0x3F;
2764 tlb = &env->tlb[T0].tlbe;
a4bb6c3e
JM		 2765 switch (word) {
2766 default:
2767 /* Just here to please gcc */
2768 case 0:
2769 T0 = tlb->EPN;
2770 size = booke_page_size_to_tlb(tlb->size);
2771 if (size < 0 || size > 0xF)
2772 size = 1;
2773 T0 |= size << 4;
2774 if (tlb->attr & 0x1)
2775 T0 |= 0x100;
2776 if (tlb->prot & PAGE_VALID)
2777 T0 |= 0x200;
2778 env->spr[SPR_440_MMUCR] &= ~0x000000FF;
2779 env->spr[SPR_440_MMUCR] |= tlb->PID;
2780 break;
2781 case 1:
2782 T0 = tlb->RPN;
2783 break;
2784 case 2:
2785 T0 = tlb->attr & ~0x1;
2786 if (tlb->prot & (PAGE_READ << 4))
2787 T0 |= 0x1;
2788 if (tlb->prot & (PAGE_WRITE << 4))
2789 T0 |= 0x2;
2790 if (tlb->prot & (PAGE_EXEC << 4))
2791 T0 |= 0x4;
2792 if (tlb->prot & PAGE_READ)
2793 T0 |= 0x8;
2794 if (tlb->prot & PAGE_WRITE)
2795 T0 |= 0x10;
2796 if (tlb->prot & PAGE_EXEC)
2797 T0 |= 0x20;
2798 break;
2799 }
5eb7995e 2800}
76a66253 2801#endif /* !CONFIG_USER_ONLY */
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