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Use float32/64 instead of float/double
[qemu.git] / target-ppc / op_helper.c
CommitLineData
9a64fbe4 1/*
3fc6c082 2 * PowerPC emulation helpers for qemu.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
9a64fbe4
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
9a64fbe4 20#include "exec.h"
603fccce 21#include "host-utils.h"
9a64fbe4 22
0411a972 23#include "helper_regs.h"
0487d6a8
JM		 24#include "op_helper.h"
25
9a64fbe4 26#define MEMSUFFIX _raw
0487d6a8 27#include "op_helper.h"
9a64fbe4 28#include "op_helper_mem.h"
a541f297 29#if !defined(CONFIG_USER_ONLY)
9a64fbe4 30#define MEMSUFFIX _user
0487d6a8 31#include "op_helper.h"
9a64fbe4
FB		 32#include "op_helper_mem.h"
33#define MEMSUFFIX _kernel
0487d6a8 34#include "op_helper.h"
9a64fbe4 35#include "op_helper_mem.h"
1e42b8f0
JM		 36#define MEMSUFFIX _hypv
37#include "op_helper.h"
38#include "op_helper_mem.h"
39#endif
9a64fbe4 40
fdabc366
FB		 41//#define DEBUG_OP
42//#define DEBUG_EXCEPTIONS
76a66253 43//#define DEBUG_SOFTWARE_TLB
fdabc366 44
9a64fbe4
FB		 45/*****************************************************************************/
46/* Exceptions processing helpers */
9a64fbe4 47
9fddaa0c 48void do_raise_exception_err (uint32_t exception, int error_code)
9a64fbe4 49{
9fddaa0c
FB		 50#if 0
51 printf("Raise exception %3x code : %d\n", exception, error_code);
52#endif
9fddaa0c
FB		 53 env->exception_index = exception;
54 env->error_code = error_code;
76a66253
JM		 55 cpu_loop_exit();
56}
9fddaa0c
FB		 57
58void do_raise_exception (uint32_t exception)
59{
60 do_raise_exception_err(exception, 0);
9a64fbe4
FB		 61}
62
a496775f
JM		 63void cpu_dump_EA (target_ulong EA);
64void do_print_mem_EA (target_ulong EA)
65{
66 cpu_dump_EA(EA);
67}
68
76a66253
JM		 69/*****************************************************************************/
70/* Registers load and stores */
71void do_load_cr (void)
72{
73 T0 = (env->crf[0] << 28) |
74 (env->crf[1] << 24) |
75 (env->crf[2] << 20) |
76 (env->crf[3] << 16) |
77 (env->crf[4] << 12) |
78 (env->crf[5] << 8) |
79 (env->crf[6] << 4) |
80 (env->crf[7] << 0);
81}
82
83void do_store_cr (uint32_t mask)
84{
85 int i, sh;
86
36081602 87 for (i = 0, sh = 7; i < 8; i++, sh--) {
76a66253
JM		 88 if (mask & (1 << sh))
89 env->crf[i] = (T0 >> (sh * 4)) & 0xFUL;
90 }
91}
92
c80f84e3
JM		 93#if defined(TARGET_PPC64)
94void do_store_pri (int prio)
95{
96 env->spr[SPR_PPR] &= ~0x001C000000000000ULL;
97 env->spr[SPR_PPR] |= ((uint64_t)prio & 0x7) << 50;
98}
99#endif
100
a496775f
JM		 101target_ulong ppc_load_dump_spr (int sprn)
102{
6b80055d 103 if (loglevel != 0) {
a496775f
JM		 104 fprintf(logfile, "Read SPR %d %03x => " ADDRX "\n",
105 sprn, sprn, env->spr[sprn]);
106 }
107
108 return env->spr[sprn];
109}
110
111void ppc_store_dump_spr (int sprn, target_ulong val)
112{
6b80055d 113 if (loglevel != 0) {
a496775f
JM		 114 fprintf(logfile, "Write SPR %d %03x => " ADDRX " <= " ADDRX "\n",
115 sprn, sprn, env->spr[sprn], val);
116 }
117 env->spr[sprn] = val;
118}
119
9a64fbe4 120/*****************************************************************************/
fdabc366 121/* Fixed point operations helpers */
fdabc366
FB		 122void do_adde (void)
123{
124 T2 = T0;
125 T0 += T1 + xer_ca;
d9bce9d9
JM		 126 if (likely(!((uint32_t)T0 < (uint32_t)T2 ||
127 (xer_ca == 1 && (uint32_t)T0 == (uint32_t)T2)))) {
fdabc366
FB		 128 xer_ca = 0;
129 } else {
130 xer_ca = 1;
131 }
132}
133
d9bce9d9
JM		 134#if defined(TARGET_PPC64)
135void do_adde_64 (void)
fdabc366
FB		 136{
137 T2 = T0;
138 T0 += T1 + xer_ca;
d9bce9d9
JM		 139 if (likely(!((uint64_t)T0 < (uint64_t)T2 ||
140 (xer_ca == 1 && (uint64_t)T0 == (uint64_t)T2)))) {
fdabc366
FB		 141 xer_ca = 0;
142 } else {
143 xer_ca = 1;
144 }
fdabc366 145}
d9bce9d9 146#endif
fdabc366
FB		 147
148void do_addmeo (void)
149{
150 T1 = T0;
151 T0 += xer_ca + (-1);
c3e10c7b
JM		 152 xer_ov = ((uint32_t)T1 & ((uint32_t)T1 ^ (uint32_t)T0)) >> 31;
153 xer_so |= xer_ov;
fdabc366
FB		 154 if (likely(T1 != 0))
155 xer_ca = 1;
c3e10c7b
JM		 156 else
157 xer_ca = 0;
fdabc366
FB		 158}
159
d9bce9d9
JM		 160#if defined(TARGET_PPC64)
161void do_addmeo_64 (void)
fdabc366
FB		 162{
163 T1 = T0;
d9bce9d9 164 T0 += xer_ca + (-1);
c3e10c7b
JM		 165 xer_ov = ((uint64_t)T1 & ((uint64_t)T1 ^ (uint64_t)T0)) >> 63;
166 xer_so |= xer_ov;
d9bce9d9 167 if (likely(T1 != 0))
fdabc366 168 xer_ca = 1;
c3e10c7b
JM		 169 else
170 xer_ca = 0;
fdabc366 171}
d9bce9d9 172#endif
fdabc366
FB		 173
174void do_divwo (void)
175{
6f2d8978 176 if (likely(!(((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) ||
d9bce9d9 177 (int32_t)T1 == 0))) {
fdabc366 178 xer_ov = 0;
d9bce9d9 179 T0 = (int32_t)T0 / (int32_t)T1;
fdabc366 180 } else {
fdabc366 181 xer_ov = 1;
6f2d8978 182 T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
fdabc366 183 }
6f2d8978 184 xer_so |= xer_ov;
fdabc366
FB		 185}
186
d9bce9d9
JM		 187#if defined(TARGET_PPC64)
188void do_divdo (void)
189{
6f2d8978 190 if (likely(!(((int64_t)T0 == INT64_MIN && (int64_t)T1 == (int64_t)-1LL) ||
d9bce9d9
JM		 191 (int64_t)T1 == 0))) {
192 xer_ov = 0;
193 T0 = (int64_t)T0 / (int64_t)T1;
194 } else {
d9bce9d9 195 xer_ov = 1;
6f2d8978 196 T0 = UINT64_MAX * ((uint64_t)T0 >> 63);
d9bce9d9 197 }
6f2d8978 198 xer_so |= xer_ov;
d9bce9d9
JM		 199}
200#endif
201
fdabc366
FB		 202void do_divwuo (void)
203{
204 if (likely((uint32_t)T1 != 0)) {
205 xer_ov = 0;
206 T0 = (uint32_t)T0 / (uint32_t)T1;
207 } else {
fdabc366 208 xer_ov = 1;
966439a6 209 xer_so = 1;
fdabc366
FB		 210 T0 = 0;
211 }
212}
213
d9bce9d9
JM		 214#if defined(TARGET_PPC64)
215void do_divduo (void)
216{
217 if (likely((uint64_t)T1 != 0)) {
218 xer_ov = 0;
219 T0 = (uint64_t)T0 / (uint64_t)T1;
220 } else {
d9bce9d9 221 xer_ov = 1;
966439a6 222 xer_so = 1;
d9bce9d9
JM		 223 T0 = 0;
224 }
225}
226#endif
227
fdabc366
FB		 228void do_mullwo (void)
229{
d9bce9d9 230 int64_t res = (int64_t)T0 * (int64_t)T1;
fdabc366
FB		 231
232 if (likely((int32_t)res == res)) {
233 xer_ov = 0;
234 } else {
235 xer_ov = 1;
236 xer_so = 1;
237 }
238 T0 = (int32_t)res;
239}
240
d9bce9d9
JM		 241#if defined(TARGET_PPC64)
242void do_mulldo (void)
fdabc366 243{
d9bce9d9
JM		 244 int64_t th;
245 uint64_t tl;
246
9d901a20 247 muls64(&tl, &th, T0, T1);
6f2d8978 248 T0 = (int64_t)tl;
88ad920b 249 /* If th != 0 && th != -1, then we had an overflow */
6f2d8978 250 if (likely((uint64_t)(th + 1) <= 1)) {
fdabc366 251 xer_ov = 0;
fdabc366
FB		 252 } else {
253 xer_ov = 1;
fdabc366 254 }
6f2d8978 255 xer_so |= xer_ov;
fdabc366 256}
d9bce9d9 257#endif
fdabc366 258
d9bce9d9 259void do_nego (void)
fdabc366 260{
d9bce9d9 261 if (likely((int32_t)T0 != INT32_MIN)) {
fdabc366 262 xer_ov = 0;
d9bce9d9 263 T0 = -(int32_t)T0;
fdabc366 264 } else {
fdabc366 265 xer_ov = 1;
d9bce9d9 266 xer_so = 1;
fdabc366 267 }
fdabc366
FB		 268}
269
d9bce9d9
JM		 270#if defined(TARGET_PPC64)
271void do_nego_64 (void)
fdabc366 272{
d9bce9d9 273 if (likely((int64_t)T0 != INT64_MIN)) {
fdabc366 274 xer_ov = 0;
d9bce9d9 275 T0 = -(int64_t)T0;
fdabc366 276 } else {
fdabc366 277 xer_ov = 1;
d9bce9d9 278 xer_so = 1;
fdabc366
FB		 279 }
280}
d9bce9d9 281#endif
fdabc366
FB		 282
283void do_subfe (void)
284{
285 T0 = T1 + ~T0 + xer_ca;
d9bce9d9
JM		 286 if (likely((uint32_t)T0 >= (uint32_t)T1 &&
287 (xer_ca == 0 || (uint32_t)T0 != (uint32_t)T1))) {
fdabc366
FB		 288 xer_ca = 0;
289 } else {
290 xer_ca = 1;
291 }
292}
293
d9bce9d9
JM		 294#if defined(TARGET_PPC64)
295void do_subfe_64 (void)
fdabc366 296{
fdabc366 297 T0 = T1 + ~T0 + xer_ca;
d9bce9d9
JM		 298 if (likely((uint64_t)T0 >= (uint64_t)T1 &&
299 (xer_ca == 0 || (uint64_t)T0 != (uint64_t)T1))) {
300 xer_ca = 0;
301 } else {
302 xer_ca = 1;
303 }
304}
305#endif
306
307void do_subfmeo (void)
308{
309 T1 = T0;
310 T0 = ~T0 + xer_ca - 1;
c3e10c7b
JM		 311 xer_ov = ((uint32_t)~T1 & ((uint32_t)~T1 ^ (uint32_t)T0)) >> 31;
312 xer_so |= xer_ov;
d9bce9d9 313 if (likely((uint32_t)T1 != UINT32_MAX))
fdabc366 314 xer_ca = 1;
c3e10c7b
JM		 315 else
316 xer_ca = 0;
fdabc366
FB		 317}
318
d9bce9d9
JM		 319#if defined(TARGET_PPC64)
320void do_subfmeo_64 (void)
fdabc366
FB		 321{
322 T1 = T0;
323 T0 = ~T0 + xer_ca - 1;
c3e10c7b
JM		 324 xer_ov = ((uint64_t)~T1 & ((uint64_t)~T1 ^ (uint64_t)T0)) >> 63;
325 xer_so |= xer_ov;
d9bce9d9 326 if (likely((uint64_t)T1 != UINT64_MAX))
fdabc366 327 xer_ca = 1;
c3e10c7b
JM		 328 else
329 xer_ca = 0;
fdabc366 330}
d9bce9d9 331#endif
fdabc366
FB		 332
333void do_subfzeo (void)
334{
335 T1 = T0;
336 T0 = ~T0 + xer_ca;
c3e10c7b
JM		 337 xer_ov = (((uint32_t)~T1 ^ UINT32_MAX) &
338 ((uint32_t)(~T1) ^ (uint32_t)T0)) >> 31;
339 xer_so |= xer_ov;
d9bce9d9 340 if (likely((uint32_t)T0 >= (uint32_t)~T1)) {
fdabc366
FB		 341 xer_ca = 0;
342 } else {
343 xer_ca = 1;
344 }
345}
346
d9bce9d9
JM		 347#if defined(TARGET_PPC64)
348void do_subfzeo_64 (void)
349{
350 T1 = T0;
351 T0 = ~T0 + xer_ca;
c3e10c7b
JM		 352 xer_ov = (((uint64_t)~T1 ^ UINT64_MAX) &
353 ((uint64_t)(~T1) ^ (uint64_t)T0)) >> 63;
354 xer_so |= xer_ov;
d9bce9d9
JM		 355 if (likely((uint64_t)T0 >= (uint64_t)~T1)) {
356 xer_ca = 0;
357 } else {
358 xer_ca = 1;
359 }
360}
361#endif
362
603fccce
JM		 363void do_cntlzw (void)
364{
365 T0 = clz32(T0);
366}
367
368#if defined(TARGET_PPC64)
369void do_cntlzd (void)
370{
371 T0 = clz64(T0);
372}
373#endif
374
9a64fbe4
FB		 375/* shift right arithmetic helper */
376void do_sraw (void)
377{
378 int32_t ret;
379
fdabc366 380 if (likely(!(T1 & 0x20UL))) {
d9bce9d9 381 if (likely((uint32_t)T1 != 0)) {
fdabc366
FB		 382 ret = (int32_t)T0 >> (T1 & 0x1fUL);
383 if (likely(ret >= 0 || ((int32_t)T0 & ((1 << T1) - 1)) == 0)) {
76a66253 384 xer_ca = 0;
fdabc366 385 } else {
76a66253 386 xer_ca = 1;
fdabc366
FB		 387 }
388 } else {
76a66253 389 ret = T0;
fdabc366
FB		 390 xer_ca = 0;
391 }
392 } else {
6f2d8978 393 ret = UINT32_MAX * ((uint32_t)T0 >> 31);
fdabc366
FB		 394 if (likely(ret >= 0 || ((uint32_t)T0 & ~0x80000000UL) == 0)) {
395 xer_ca = 0;
76a66253 396 } else {
9a64fbe4 397 xer_ca = 1;
76a66253 398 }
fdabc366 399 }
4b3686fa 400 T0 = ret;
9a64fbe4
FB		 401}
402
d9bce9d9
JM		 403#if defined(TARGET_PPC64)
404void do_srad (void)
405{
406 int64_t ret;
407
408 if (likely(!(T1 & 0x40UL))) {
409 if (likely((uint64_t)T1 != 0)) {
410 ret = (int64_t)T0 >> (T1 & 0x3FUL);
411 if (likely(ret >= 0 || ((int64_t)T0 & ((1 << T1) - 1)) == 0)) {
412 xer_ca = 0;
413 } else {
414 xer_ca = 1;
415 }
416 } else {
417 ret = T0;
418 xer_ca = 0;
419 }
420 } else {
6f2d8978 421 ret = UINT64_MAX * ((uint64_t)T0 >> 63);
d9bce9d9
JM		 422 if (likely(ret >= 0 || ((uint64_t)T0 & ~0x8000000000000000ULL) == 0)) {
423 xer_ca = 0;
424 } else {
425 xer_ca = 1;
426 }
427 }
428 T0 = ret;
429}
430#endif
431
d9bce9d9
JM		 432void do_popcntb (void)
433{
434 uint32_t ret;
435 int i;
436
437 ret = 0;
438 for (i = 0; i < 32; i += 8)
603fccce 439 ret |= ctpop8((T0 >> i) & 0xFF) << i;
d9bce9d9
JM		 440 T0 = ret;
441}
442
443#if defined(TARGET_PPC64)
444void do_popcntb_64 (void)
445{
446 uint64_t ret;
447 int i;
448
449 ret = 0;
450 for (i = 0; i < 64; i += 8)
603fccce 451 ret |= ctpop8((T0 >> i) & 0xFF) << i;
d9bce9d9
JM		 452 T0 = ret;
453}
454#endif
455
fdabc366 456/*****************************************************************************/
9a64fbe4 457/* Floating point operations helpers */
0ca9d380 458static always_inline int fpisneg (float64 d)
7c58044c 459{
0ca9d380 460 CPU_DoubleU u;
7c58044c 461
0ca9d380 462 u.d = d;
7c58044c 463
0ca9d380 464 return u.ll >> 63 != 0;
7c58044c
JM		 465}
466
0ca9d380 467static always_inline int isden (float64 d)
7c58044c 468{
0ca9d380 469 CPU_DoubleU u;
7c58044c 470
0ca9d380 471 u.d = d;
7c58044c 472
0ca9d380 473 return ((u.ll >> 52) & 0x7FF) == 0;
7c58044c
JM		 474}
475
0ca9d380 476static always_inline int iszero (float64 d)
7c58044c 477{
0ca9d380 478 CPU_DoubleU u;
7c58044c 479
0ca9d380 480 u.d = d;
7c58044c 481
0ca9d380 482 return (u.ll & ~0x8000000000000000ULL) == 0;
7c58044c
JM		 483}
484
0ca9d380 485static always_inline int isinfinity (float64 d)
7c58044c 486{
0ca9d380 487 CPU_DoubleU u;
7c58044c 488
0ca9d380 489 u.d = d;
7c58044c 490
0ca9d380
AJ		 491 return ((u.ll >> 52) & 0x7FF) == 0x7FF &&
492 (u.ll & 0x000FFFFFFFFFFFFFULL) == 0;
7c58044c
JM		 493}
494
495void do_compute_fprf (int set_fprf)
496{
497 int isneg;
498
499 isneg = fpisneg(FT0);
500 if (unlikely(float64_is_nan(FT0))) {
501 if (float64_is_signaling_nan(FT0)) {
502 /* Signaling NaN: flags are undefined */
503 T0 = 0x00;
504 } else {
505 /* Quiet NaN */
506 T0 = 0x11;
507 }
508 } else if (unlikely(isinfinity(FT0))) {
509 /* +/- infinity */
510 if (isneg)
511 T0 = 0x09;
512 else
513 T0 = 0x05;
514 } else {
515 if (iszero(FT0)) {
516 /* +/- zero */
517 if (isneg)
518 T0 = 0x12;
519 else
520 T0 = 0x02;
521 } else {
522 if (isden(FT0)) {
523 /* Denormalized numbers */
524 T0 = 0x10;
525 } else {
526 /* Normalized numbers */
527 T0 = 0x00;
528 }
529 if (isneg) {
530 T0 |= 0x08;
531 } else {
532 T0 |= 0x04;
533 }
534 }
535 }
536 if (set_fprf) {
537 /* We update FPSCR_FPRF */
538 env->fpscr &= ~(0x1F << FPSCR_FPRF);
539 env->fpscr |= T0 << FPSCR_FPRF;
540 }
541 /* We just need fpcc to update Rc1 */
542 T0 &= 0xF;
543}
544
545/* Floating-point invalid operations exception */
546static always_inline void fload_invalid_op_excp (int op)
547{
548 int ve;
549
550 ve = fpscr_ve;
551 if (op & POWERPC_EXCP_FP_VXSNAN) {
552 /* Operation on signaling NaN */
553 env->fpscr |= 1 << FPSCR_VXSNAN;
554 }
555 if (op & POWERPC_EXCP_FP_VXSOFT) {
556 /* Software-defined condition */
557 env->fpscr |= 1 << FPSCR_VXSOFT;
558 }
559 switch (op & ~(POWERPC_EXCP_FP_VXSOFT | POWERPC_EXCP_FP_VXSNAN)) {
560 case POWERPC_EXCP_FP_VXISI:
561 /* Magnitude subtraction of infinities */
562 env->fpscr |= 1 << FPSCR_VXISI;
563 goto update_arith;
564 case POWERPC_EXCP_FP_VXIDI:
565 /* Division of infinity by infinity */
566 env->fpscr |= 1 << FPSCR_VXIDI;
567 goto update_arith;
568 case POWERPC_EXCP_FP_VXZDZ:
569 /* Division of zero by zero */
570 env->fpscr |= 1 << FPSCR_VXZDZ;
571 goto update_arith;
572 case POWERPC_EXCP_FP_VXIMZ:
573 /* Multiplication of zero by infinity */
574 env->fpscr |= 1 << FPSCR_VXIMZ;
575 goto update_arith;
576 case POWERPC_EXCP_FP_VXVC:
577 /* Ordered comparison of NaN */
578 env->fpscr |= 1 << FPSCR_VXVC;
579 env->fpscr &= ~(0xF << FPSCR_FPCC);
580 env->fpscr |= 0x11 << FPSCR_FPCC;
581 /* We must update the target FPR before raising the exception */
582 if (ve != 0) {
583 env->exception_index = POWERPC_EXCP_PROGRAM;
584 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC;
585 /* Update the floating-point enabled exception summary */
586 env->fpscr |= 1 << FPSCR_FEX;
587 /* Exception is differed */
588 ve = 0;
589 }
590 break;
591 case POWERPC_EXCP_FP_VXSQRT:
592 /* Square root of a negative number */
593 env->fpscr |= 1 << FPSCR_VXSQRT;
594 update_arith:
595 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
596 if (ve == 0) {
597 /* Set the result to quiet NaN */
6f2d8978 598 FT0 = UINT64_MAX;
7c58044c
JM		 599 env->fpscr &= ~(0xF << FPSCR_FPCC);
600 env->fpscr |= 0x11 << FPSCR_FPCC;
601 }
602 break;
603 case POWERPC_EXCP_FP_VXCVI:
604 /* Invalid conversion */
605 env->fpscr |= 1 << FPSCR_VXCVI;
606 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
607 if (ve == 0) {
608 /* Set the result to quiet NaN */
6f2d8978 609 FT0 = UINT64_MAX;
7c58044c
JM		 610 env->fpscr &= ~(0xF << FPSCR_FPCC);
611 env->fpscr |= 0x11 << FPSCR_FPCC;
612 }
613 break;
614 }
615 /* Update the floating-point invalid operation summary */
616 env->fpscr |= 1 << FPSCR_VX;
617 /* Update the floating-point exception summary */
618 env->fpscr |= 1 << FPSCR_FX;
619 if (ve != 0) {
620 /* Update the floating-point enabled exception summary */
621 env->fpscr |= 1 << FPSCR_FEX;
622 if (msr_fe0 != 0 || msr_fe1 != 0)
623 do_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_FP | op);
624 }
625}
626
627static always_inline void float_zero_divide_excp (void)
628{
0ca9d380 629 CPU_DoubleU u0, u1;
7c58044c
JM		 630
631 env->fpscr |= 1 << FPSCR_ZX;
632 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
633 /* Update the floating-point exception summary */
634 env->fpscr |= 1 << FPSCR_FX;
635 if (fpscr_ze != 0) {
636 /* Update the floating-point enabled exception summary */
637 env->fpscr |= 1 << FPSCR_FEX;
638 if (msr_fe0 != 0 || msr_fe1 != 0) {
639 do_raise_exception_err(POWERPC_EXCP_PROGRAM,
640 POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX);
641 }
642 } else {
643 /* Set the result to infinity */
0ca9d380
AJ		 644 u0.d = FT0;
645 u1.d = FT1;
646 u0.ll = ((u0.ll ^ u1.ll) & 0x8000000000000000ULL);
647 u0.ll |= 0x7FFULL << 52;
648 FT0 = u0.d;
7c58044c
JM		 649 }
650}
651
652static always_inline void float_overflow_excp (void)
653{
654 env->fpscr |= 1 << FPSCR_OX;
655 /* Update the floating-point exception summary */
656 env->fpscr |= 1 << FPSCR_FX;
657 if (fpscr_oe != 0) {
658 /* XXX: should adjust the result */
659 /* Update the floating-point enabled exception summary */
660 env->fpscr |= 1 << FPSCR_FEX;
661 /* We must update the target FPR before raising the exception */
662 env->exception_index = POWERPC_EXCP_PROGRAM;
663 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
664 } else {
665 env->fpscr |= 1 << FPSCR_XX;
666 env->fpscr |= 1 << FPSCR_FI;
667 }
668}
669
670static always_inline void float_underflow_excp (void)
671{
672 env->fpscr |= 1 << FPSCR_UX;
673 /* Update the floating-point exception summary */
674 env->fpscr |= 1 << FPSCR_FX;
675 if (fpscr_ue != 0) {
676 /* XXX: should adjust the result */
677 /* Update the floating-point enabled exception summary */
678 env->fpscr |= 1 << FPSCR_FEX;
679 /* We must update the target FPR before raising the exception */
680 env->exception_index = POWERPC_EXCP_PROGRAM;
681 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
682 }
683}
684
685static always_inline void float_inexact_excp (void)
686{
687 env->fpscr |= 1 << FPSCR_XX;
688 /* Update the floating-point exception summary */
689 env->fpscr |= 1 << FPSCR_FX;
690 if (fpscr_xe != 0) {
691 /* Update the floating-point enabled exception summary */
692 env->fpscr |= 1 << FPSCR_FEX;
693 /* We must update the target FPR before raising the exception */
694 env->exception_index = POWERPC_EXCP_PROGRAM;
695 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
696 }
697}
698
699static always_inline void fpscr_set_rounding_mode (void)
700{
701 int rnd_type;
702
703 /* Set rounding mode */
704 switch (fpscr_rn) {
705 case 0:
706 /* Best approximation (round to nearest) */
707 rnd_type = float_round_nearest_even;
708 break;
709 case 1:
710 /* Smaller magnitude (round toward zero) */
711 rnd_type = float_round_to_zero;
712 break;
713 case 2:
714 /* Round toward +infinite */
715 rnd_type = float_round_up;
716 break;
717 default:
718 case 3:
719 /* Round toward -infinite */
720 rnd_type = float_round_down;
721 break;
722 }
723 set_float_rounding_mode(rnd_type, &env->fp_status);
724}
725
726void do_fpscr_setbit (int bit)
727{
728 int prev;
729
730 prev = (env->fpscr >> bit) & 1;
731 env->fpscr |= 1 << bit;
732 if (prev == 0) {
733 switch (bit) {
734 case FPSCR_VX:
735 env->fpscr |= 1 << FPSCR_FX;
736 if (fpscr_ve)
737 goto raise_ve;
738 case FPSCR_OX:
739 env->fpscr |= 1 << FPSCR_FX;
740 if (fpscr_oe)
741 goto raise_oe;
742 break;
743 case FPSCR_UX:
744 env->fpscr |= 1 << FPSCR_FX;
745 if (fpscr_ue)
746 goto raise_ue;
747 break;
748 case FPSCR_ZX:
749 env->fpscr |= 1 << FPSCR_FX;
750 if (fpscr_ze)
751 goto raise_ze;
752 break;
753 case FPSCR_XX:
754 env->fpscr |= 1 << FPSCR_FX;
755 if (fpscr_xe)
756 goto raise_xe;
757 break;
758 case FPSCR_VXSNAN:
759 case FPSCR_VXISI:
760 case FPSCR_VXIDI:
761 case FPSCR_VXZDZ:
762 case FPSCR_VXIMZ:
763 case FPSCR_VXVC:
764 case FPSCR_VXSOFT:
765 case FPSCR_VXSQRT:
766 case FPSCR_VXCVI:
767 env->fpscr |= 1 << FPSCR_VX;
768 env->fpscr |= 1 << FPSCR_FX;
769 if (fpscr_ve != 0)
770 goto raise_ve;
771 break;
772 case FPSCR_VE:
773 if (fpscr_vx != 0) {
774 raise_ve:
775 env->error_code = POWERPC_EXCP_FP;
776 if (fpscr_vxsnan)
777 env->error_code |= POWERPC_EXCP_FP_VXSNAN;
778 if (fpscr_vxisi)
779 env->error_code |= POWERPC_EXCP_FP_VXISI;
780 if (fpscr_vxidi)
781 env->error_code |= POWERPC_EXCP_FP_VXIDI;
782 if (fpscr_vxzdz)
783 env->error_code |= POWERPC_EXCP_FP_VXZDZ;
784 if (fpscr_vximz)
785 env->error_code |= POWERPC_EXCP_FP_VXIMZ;
786 if (fpscr_vxvc)
787 env->error_code |= POWERPC_EXCP_FP_VXVC;
788 if (fpscr_vxsoft)
789 env->error_code |= POWERPC_EXCP_FP_VXSOFT;
790 if (fpscr_vxsqrt)
791 env->error_code |= POWERPC_EXCP_FP_VXSQRT;
792 if (fpscr_vxcvi)
793 env->error_code |= POWERPC_EXCP_FP_VXCVI;
794 goto raise_excp;
795 }
796 break;
797 case FPSCR_OE:
798 if (fpscr_ox != 0) {
799 raise_oe:
800 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
801 goto raise_excp;
802 }
803 break;
804 case FPSCR_UE:
805 if (fpscr_ux != 0) {
806 raise_ue:
807 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
808 goto raise_excp;
809 }
810 break;
811 case FPSCR_ZE:
812 if (fpscr_zx != 0) {
813 raise_ze:
814 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX;
815 goto raise_excp;
816 }
817 break;
818 case FPSCR_XE:
819 if (fpscr_xx != 0) {
820 raise_xe:
821 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
822 goto raise_excp;
823 }
824 break;
825 case FPSCR_RN1:
826 case FPSCR_RN:
827 fpscr_set_rounding_mode();
828 break;
829 default:
830 break;
831 raise_excp:
832 /* Update the floating-point enabled exception summary */
833 env->fpscr |= 1 << FPSCR_FEX;
834 /* We have to update Rc1 before raising the exception */
835 env->exception_index = POWERPC_EXCP_PROGRAM;
836 break;
837 }
838 }
839}
840
841#if defined(WORDS_BIGENDIAN)
842#define WORD0 0
843#define WORD1 1
844#else
845#define WORD0 1
846#define WORD1 0
847#endif
848void do_store_fpscr (uint32_t mask)
849{
850 /*
851 * We use only the 32 LSB of the incoming fpr
852 */
0ca9d380 853 CPU_DoubleU u;
7c58044c
JM		 854 uint32_t prev, new;
855 int i;
856
857 u.d = FT0;
858 prev = env->fpscr;
0ca9d380 859 new = u.l.lower;
7c58044c
JM		 860 new &= ~0x90000000;
861 new |= prev & 0x90000000;
862 for (i = 0; i < 7; i++) {
863 if (mask & (1 << i)) {
864 env->fpscr &= ~(0xF << (4 * i));
865 env->fpscr |= new & (0xF << (4 * i));
866 }
867 }
868 /* Update VX and FEX */
869 if (fpscr_ix != 0)
870 env->fpscr |= 1 << FPSCR_VX;
5567025f
AJ		 871 else
872 env->fpscr &= ~(1 << FPSCR_VX);
7c58044c
JM		 873 if ((fpscr_ex & fpscr_eex) != 0) {
874 env->fpscr |= 1 << FPSCR_FEX;
875 env->exception_index = POWERPC_EXCP_PROGRAM;
876 /* XXX: we should compute it properly */
877 env->error_code = POWERPC_EXCP_FP;
878 }
5567025f
AJ		 879 else
880 env->fpscr &= ~(1 << FPSCR_FEX);
7c58044c
JM		 881 fpscr_set_rounding_mode();
882}
883#undef WORD0
884#undef WORD1
885
886#ifdef CONFIG_SOFTFLOAT
887void do_float_check_status (void)
888{
889 if (env->exception_index == POWERPC_EXCP_PROGRAM &&
890 (env->error_code & POWERPC_EXCP_FP)) {
891 /* Differred floating-point exception after target FPR update */
892 if (msr_fe0 != 0 || msr_fe1 != 0)
893 do_raise_exception_err(env->exception_index, env->error_code);
894 } else if (env->fp_status.float_exception_flags & float_flag_overflow) {
895 float_overflow_excp();
896 } else if (env->fp_status.float_exception_flags & float_flag_underflow) {
897 float_underflow_excp();
898 } else if (env->fp_status.float_exception_flags & float_flag_inexact) {
899 float_inexact_excp();
900 }
901}
902#endif
903
904#if USE_PRECISE_EMULATION
905void do_fadd (void)
906{
907 if (unlikely(float64_is_signaling_nan(FT0) ||
908 float64_is_signaling_nan(FT1))) {
909 /* sNaN addition */
910 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
911 } else if (likely(isfinite(FT0) || isfinite(FT1) ||
912 fpisneg(FT0) == fpisneg(FT1))) {
913 FT0 = float64_add(FT0, FT1, &env->fp_status);
914 } else {
915 /* Magnitude subtraction of infinities */
916 fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
917 }
918}
919
920void do_fsub (void)
921{
922 if (unlikely(float64_is_signaling_nan(FT0) ||
923 float64_is_signaling_nan(FT1))) {
924 /* sNaN subtraction */
925 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
926 } else if (likely(isfinite(FT0) || isfinite(FT1) ||
927 fpisneg(FT0) != fpisneg(FT1))) {
928 FT0 = float64_sub(FT0, FT1, &env->fp_status);
929 } else {
930 /* Magnitude subtraction of infinities */
931 fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
932 }
933}
934
935void do_fmul (void)
936{
937 if (unlikely(float64_is_signaling_nan(FT0) ||
938 float64_is_signaling_nan(FT1))) {
939 /* sNaN multiplication */
940 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
5bda2843
JM		 941 } else if (unlikely((isinfinity(FT0) && iszero(FT1)) ||
942 (iszero(FT0) && isinfinity(FT1)))) {
7c58044c
JM		 943 /* Multiplication of zero by infinity */
944 fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
945 } else {
946 FT0 = float64_mul(FT0, FT1, &env->fp_status);
947 }
948}
949
950void do_fdiv (void)
951{
952 if (unlikely(float64_is_signaling_nan(FT0) ||
953 float64_is_signaling_nan(FT1))) {
954 /* sNaN division */
955 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
956 } else if (unlikely(isinfinity(FT0) && isinfinity(FT1))) {
957 /* Division of infinity by infinity */
958 fload_invalid_op_excp(POWERPC_EXCP_FP_VXIDI);
959 } else if (unlikely(iszero(FT1))) {
960 if (iszero(FT0)) {
961 /* Division of zero by zero */
962 fload_invalid_op_excp(POWERPC_EXCP_FP_VXZDZ);
963 } else {
964 /* Division by zero */
965 float_zero_divide_excp();
966 }
967 } else {
968 FT0 = float64_div(FT0, FT1, &env->fp_status);
969 }
970}
971#endif /* USE_PRECISE_EMULATION */
972
9a64fbe4
FB		 973void do_fctiw (void)
974{
0ca9d380 975 CPU_DoubleU p;
9a64fbe4 976
7c58044c
JM		 977 if (unlikely(float64_is_signaling_nan(FT0))) {
978 /* sNaN conversion */
979 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
980 } else if (unlikely(float64_is_nan(FT0) || isinfinity(FT0))) {
981 /* qNan / infinity conversion */
982 fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
983 } else {
0ca9d380 984 p.ll = float64_to_int32(FT0, &env->fp_status);
e864cabd 985#if USE_PRECISE_EMULATION
7c58044c
JM		 986 /* XXX: higher bits are not supposed to be significant.
987 * to make tests easier, return the same as a real PowerPC 750
988 */
0ca9d380 989 p.ll |= 0xFFF80000ULL << 32;
e864cabd 990#endif
7c58044c
JM		 991 FT0 = p.d;
992 }
9a64fbe4
FB		 993}
994
995void do_fctiwz (void)
996{
0ca9d380 997 CPU_DoubleU p;
4ecc3190 998
7c58044c
JM		 999 if (unlikely(float64_is_signaling_nan(FT0))) {
1000 /* sNaN conversion */
1001 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1002 } else if (unlikely(float64_is_nan(FT0) || isinfinity(FT0))) {
1003 /* qNan / infinity conversion */
1004 fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1005 } else {
0ca9d380 1006 p.ll = float64_to_int32_round_to_zero(FT0, &env->fp_status);
e864cabd 1007#if USE_PRECISE_EMULATION
7c58044c
JM		 1008 /* XXX: higher bits are not supposed to be significant.
1009 * to make tests easier, return the same as a real PowerPC 750
1010 */
0ca9d380 1011 p.ll |= 0xFFF80000ULL << 32;
e864cabd 1012#endif
7c58044c
JM		 1013 FT0 = p.d;
1014 }
9a64fbe4
FB		 1015}
1016
426613db
JM		 1017#if defined(TARGET_PPC64)
1018void do_fcfid (void)
1019{
0ca9d380 1020 CPU_DoubleU p;
426613db
JM		 1021
1022 p.d = FT0;
0ca9d380 1023 FT0 = int64_to_float64(p.ll, &env->fp_status);
426613db
JM		 1024}
1025
1026void do_fctid (void)
1027{
0ca9d380 1028 CPU_DoubleU p;
426613db 1029
7c58044c
JM		 1030 if (unlikely(float64_is_signaling_nan(FT0))) {
1031 /* sNaN conversion */
1032 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1033 } else if (unlikely(float64_is_nan(FT0) || isinfinity(FT0))) {
1034 /* qNan / infinity conversion */
1035 fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1036 } else {
0ca9d380 1037 p.ll = float64_to_int64(FT0, &env->fp_status);
7c58044c
JM		 1038 FT0 = p.d;
1039 }
426613db
JM		 1040}
1041
1042void do_fctidz (void)
1043{
0ca9d380 1044 CPU_DoubleU p;
426613db 1045
7c58044c
JM		 1046 if (unlikely(float64_is_signaling_nan(FT0))) {
1047 /* sNaN conversion */
1048 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1049 } else if (unlikely(float64_is_nan(FT0) || isinfinity(FT0))) {
1050 /* qNan / infinity conversion */
1051 fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1052 } else {
0ca9d380 1053 p.ll = float64_to_int64_round_to_zero(FT0, &env->fp_status);
7c58044c
JM		 1054 FT0 = p.d;
1055 }
426613db
JM		 1056}
1057
1058#endif
1059
b068d6a7 1060static always_inline void do_fri (int rounding_mode)
d7e4b87e 1061{
7c58044c
JM		 1062 if (unlikely(float64_is_signaling_nan(FT0))) {
1063 /* sNaN round */
1064 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1065 } else if (unlikely(float64_is_nan(FT0) || isinfinity(FT0))) {
1066 /* qNan / infinity round */
1067 fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1068 } else {
1069 set_float_rounding_mode(rounding_mode, &env->fp_status);
1070 FT0 = float64_round_to_int(FT0, &env->fp_status);
1071 /* Restore rounding mode from FPSCR */
1072 fpscr_set_rounding_mode();
1073 }
d7e4b87e
JM		 1074}
1075
1076void do_frin (void)
1077{
1078 do_fri(float_round_nearest_even);
1079}
1080
1081void do_friz (void)
1082{
1083 do_fri(float_round_to_zero);
1084}
1085
1086void do_frip (void)
1087{
1088 do_fri(float_round_up);
1089}
1090
1091void do_frim (void)
1092{
1093 do_fri(float_round_down);
1094}
1095
e864cabd
JM		 1096#if USE_PRECISE_EMULATION
1097void do_fmadd (void)
1098{
7c58044c
JM		 1099 if (unlikely(float64_is_signaling_nan(FT0) ||
1100 float64_is_signaling_nan(FT1) ||
1101 float64_is_signaling_nan(FT2))) {
1102 /* sNaN operation */
1103 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1104 } else {
e864cabd 1105#ifdef FLOAT128
7c58044c
JM		 1106 /* This is the way the PowerPC specification defines it */
1107 float128 ft0_128, ft1_128;
1108
1109 ft0_128 = float64_to_float128(FT0, &env->fp_status);
1110 ft1_128 = float64_to_float128(FT1, &env->fp_status);
1111 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1112 ft1_128 = float64_to_float128(FT2, &env->fp_status);
1113 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
1114 FT0 = float128_to_float64(ft0_128, &env->fp_status);
e864cabd 1115#else
7c58044c
JM		 1116 /* This is OK on x86 hosts */
1117 FT0 = (FT0 * FT1) + FT2;
e864cabd 1118#endif
7c58044c 1119 }
e864cabd
JM		 1120}
1121
1122void do_fmsub (void)
1123{
7c58044c
JM		 1124 if (unlikely(float64_is_signaling_nan(FT0) ||
1125 float64_is_signaling_nan(FT1) ||
1126 float64_is_signaling_nan(FT2))) {
1127 /* sNaN operation */
1128 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1129 } else {
e864cabd 1130#ifdef FLOAT128
7c58044c
JM		 1131 /* This is the way the PowerPC specification defines it */
1132 float128 ft0_128, ft1_128;
1133
1134 ft0_128 = float64_to_float128(FT0, &env->fp_status);
1135 ft1_128 = float64_to_float128(FT1, &env->fp_status);
1136 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1137 ft1_128 = float64_to_float128(FT2, &env->fp_status);
1138 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
1139 FT0 = float128_to_float64(ft0_128, &env->fp_status);
e864cabd 1140#else
7c58044c
JM		 1141 /* This is OK on x86 hosts */
1142 FT0 = (FT0 * FT1) - FT2;
e864cabd 1143#endif
7c58044c 1144 }
e864cabd
JM		 1145}
1146#endif /* USE_PRECISE_EMULATION */
1147
4b3686fa
FB		 1148void do_fnmadd (void)
1149{
7c58044c
JM		 1150 if (unlikely(float64_is_signaling_nan(FT0) ||
1151 float64_is_signaling_nan(FT1) ||
1152 float64_is_signaling_nan(FT2))) {
1153 /* sNaN operation */
1154 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1155 } else {
e864cabd
JM		 1156#if USE_PRECISE_EMULATION
1157#ifdef FLOAT128
7c58044c
JM		 1158 /* This is the way the PowerPC specification defines it */
1159 float128 ft0_128, ft1_128;
1160
1161 ft0_128 = float64_to_float128(FT0, &env->fp_status);
1162 ft1_128 = float64_to_float128(FT1, &env->fp_status);
1163 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1164 ft1_128 = float64_to_float128(FT2, &env->fp_status);
1165 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
1166 FT0 = float128_to_float64(ft0_128, &env->fp_status);
e864cabd 1167#else
7c58044c
JM		 1168 /* This is OK on x86 hosts */
1169 FT0 = (FT0 * FT1) + FT2;
e864cabd
JM		 1170#endif
1171#else
7c58044c
JM		 1172 FT0 = float64_mul(FT0, FT1, &env->fp_status);
1173 FT0 = float64_add(FT0, FT2, &env->fp_status);
e864cabd 1174#endif
7c58044c
JM		 1175 if (likely(!isnan(FT0)))
1176 FT0 = float64_chs(FT0);
1177 }
4b3686fa
FB		 1178}
1179
1180void do_fnmsub (void)
1181{
7c58044c
JM		 1182 if (unlikely(float64_is_signaling_nan(FT0) ||
1183 float64_is_signaling_nan(FT1) ||
1184 float64_is_signaling_nan(FT2))) {
1185 /* sNaN operation */
1186 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1187 } else {
e864cabd
JM		 1188#if USE_PRECISE_EMULATION
1189#ifdef FLOAT128
7c58044c
JM		 1190 /* This is the way the PowerPC specification defines it */
1191 float128 ft0_128, ft1_128;
1192
1193 ft0_128 = float64_to_float128(FT0, &env->fp_status);
1194 ft1_128 = float64_to_float128(FT1, &env->fp_status);
1195 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1196 ft1_128 = float64_to_float128(FT2, &env->fp_status);
1197 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
1198 FT0 = float128_to_float64(ft0_128, &env->fp_status);
e864cabd 1199#else
7c58044c
JM		 1200 /* This is OK on x86 hosts */
1201 FT0 = (FT0 * FT1) - FT2;
e864cabd
JM		 1202#endif
1203#else
7c58044c
JM		 1204 FT0 = float64_mul(FT0, FT1, &env->fp_status);
1205 FT0 = float64_sub(FT0, FT2, &env->fp_status);
e864cabd 1206#endif
7c58044c
JM		 1207 if (likely(!isnan(FT0)))
1208 FT0 = float64_chs(FT0);
1209 }
1ef59d0a
FB		 1210}
1211
7c58044c
JM		 1212#if USE_PRECISE_EMULATION
1213void do_frsp (void)
1214{
1215 if (unlikely(float64_is_signaling_nan(FT0))) {
1216 /* sNaN square root */
1217 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1218 } else {
1219 FT0 = float64_to_float32(FT0, &env->fp_status);
1220 }
1221}
1222#endif /* USE_PRECISE_EMULATION */
1223
9a64fbe4
FB		 1224void do_fsqrt (void)
1225{
7c58044c
JM		 1226 if (unlikely(float64_is_signaling_nan(FT0))) {
1227 /* sNaN square root */
1228 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1229 } else if (unlikely(fpisneg(FT0) && !iszero(FT0))) {
1230 /* Square root of a negative nonzero number */
1231 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
1232 } else {
1233 FT0 = float64_sqrt(FT0, &env->fp_status);
1234 }
9a64fbe4
FB		 1235}
1236
d7e4b87e
JM		 1237void do_fre (void)
1238{
0ca9d380 1239 CPU_DoubleU p;
d7e4b87e 1240
7c58044c
JM		 1241 if (unlikely(float64_is_signaling_nan(FT0))) {
1242 /* sNaN reciprocal */
1243 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1244 } else if (unlikely(iszero(FT0))) {
1245 /* Zero reciprocal */
1246 float_zero_divide_excp();
1247 } else if (likely(isnormal(FT0))) {
d7e4b87e
JM		 1248 FT0 = float64_div(1.0, FT0, &env->fp_status);
1249 } else {
1250 p.d = FT0;
0ca9d380
AJ		 1251 if (p.ll == 0x8000000000000000ULL) {
1252 p.ll = 0xFFF0000000000000ULL;
1253 } else if (p.ll == 0x0000000000000000ULL) {
1254 p.ll = 0x7FF0000000000000ULL;
d7e4b87e 1255 } else if (isnan(FT0)) {
0ca9d380 1256 p.ll = 0x7FF8000000000000ULL;
7c58044c 1257 } else if (fpisneg(FT0)) {
0ca9d380 1258 p.ll = 0x8000000000000000ULL;
d7e4b87e 1259 } else {
0ca9d380 1260 p.ll = 0x0000000000000000ULL;
d7e4b87e
JM		 1261 }
1262 FT0 = p.d;
1263 }
1264}
1265
9a64fbe4
FB		 1266void do_fres (void)
1267{
0ca9d380 1268 CPU_DoubleU p;
4ecc3190 1269
7c58044c
JM		 1270 if (unlikely(float64_is_signaling_nan(FT0))) {
1271 /* sNaN reciprocal */
1272 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1273 } else if (unlikely(iszero(FT0))) {
1274 /* Zero reciprocal */
1275 float_zero_divide_excp();
1276 } else if (likely(isnormal(FT0))) {
e864cabd
JM		 1277#if USE_PRECISE_EMULATION
1278 FT0 = float64_div(1.0, FT0, &env->fp_status);
1279 FT0 = float64_to_float32(FT0, &env->fp_status);
1280#else
76a66253 1281 FT0 = float32_div(1.0, FT0, &env->fp_status);
e864cabd 1282#endif
4ecc3190
FB		 1283 } else {
1284 p.d = FT0;
0ca9d380
AJ		 1285 if (p.ll == 0x8000000000000000ULL) {
1286 p.ll = 0xFFF0000000000000ULL;
1287 } else if (p.ll == 0x0000000000000000ULL) {
1288 p.ll = 0x7FF0000000000000ULL;
4ecc3190 1289 } else if (isnan(FT0)) {
0ca9d380 1290 p.ll = 0x7FF8000000000000ULL;
7c58044c 1291 } else if (fpisneg(FT0)) {
0ca9d380 1292 p.ll = 0x8000000000000000ULL;
4ecc3190 1293 } else {
0ca9d380 1294 p.ll = 0x0000000000000000ULL;
4ecc3190
FB		 1295 }
1296 FT0 = p.d;
1297 }
9a64fbe4
FB		 1298}
1299
4ecc3190 1300void do_frsqrte (void)
9a64fbe4 1301{
0ca9d380 1302 CPU_DoubleU p;
4ecc3190 1303
7c58044c
JM		 1304 if (unlikely(float64_is_signaling_nan(FT0))) {
1305 /* sNaN reciprocal square root */
1306 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1307 } else if (unlikely(fpisneg(FT0) && !iszero(FT0))) {
1308 /* Reciprocal square root of a negative nonzero number */
1309 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
1310 } else if (likely(isnormal(FT0))) {
fdabc366
FB		 1311 FT0 = float64_sqrt(FT0, &env->fp_status);
1312 FT0 = float32_div(1.0, FT0, &env->fp_status);
4ecc3190
FB		 1313 } else {
1314 p.d = FT0;
0ca9d380
AJ		 1315 if (p.ll == 0x8000000000000000ULL) {
1316 p.ll = 0xFFF0000000000000ULL;
1317 } else if (p.ll == 0x0000000000000000ULL) {
1318 p.ll = 0x7FF0000000000000ULL;
4ecc3190 1319 } else if (isnan(FT0)) {
0ca9d380 1320 p.ll |= 0x000FFFFFFFFFFFFFULL;
7c58044c 1321 } else if (fpisneg(FT0)) {
0ca9d380 1322 p.ll = 0x7FF8000000000000ULL;
4ecc3190 1323 } else {
0ca9d380 1324 p.ll = 0x0000000000000000ULL;
4ecc3190
FB		 1325 }
1326 FT0 = p.d;
1327 }
9a64fbe4
FB		 1328}
1329
1330void do_fsel (void)
1331{
7c58044c 1332 if (!fpisneg(FT0) || iszero(FT0))
9a64fbe4 1333 FT0 = FT1;
4ecc3190
FB		 1334 else
1335 FT0 = FT2;
9a64fbe4
FB		 1336}
1337
1338void do_fcmpu (void)
1339{
7c58044c
JM		 1340 if (unlikely(float64_is_signaling_nan(FT0) ||
1341 float64_is_signaling_nan(FT1))) {
1342 /* sNaN comparison */
1343 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1344 } else {
fdabc366
FB		 1345 if (float64_lt(FT0, FT1, &env->fp_status)) {
1346 T0 = 0x08UL;
1347 } else if (!float64_le(FT0, FT1, &env->fp_status)) {
1348 T0 = 0x04UL;
1349 } else {
1350 T0 = 0x02UL;
1351 }
9a64fbe4 1352 }
7c58044c
JM		 1353 env->fpscr &= ~(0x0F << FPSCR_FPRF);
1354 env->fpscr |= T0 << FPSCR_FPRF;
9a64fbe4
FB		 1355}
1356
1357void do_fcmpo (void)
1358{
7c58044c
JM		 1359 if (unlikely(float64_is_nan(FT0) ||
1360 float64_is_nan(FT1))) {
1361 if (float64_is_signaling_nan(FT0) ||
1362 float64_is_signaling_nan(FT1)) {
1363 /* sNaN comparison */
1364 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN |
1365 POWERPC_EXCP_FP_VXVC);
1366 } else {
1367 /* qNaN comparison */
1368 fload_invalid_op_excp(POWERPC_EXCP_FP_VXVC);
1369 }
1370 } else {
fdabc366
FB		 1371 if (float64_lt(FT0, FT1, &env->fp_status)) {
1372 T0 = 0x08UL;
1373 } else if (!float64_le(FT0, FT1, &env->fp_status)) {
1374 T0 = 0x04UL;
1375 } else {
1376 T0 = 0x02UL;
1377 }
9a64fbe4 1378 }
7c58044c
JM		 1379 env->fpscr &= ~(0x0F << FPSCR_FPRF);
1380 env->fpscr |= T0 << FPSCR_FPRF;
9a64fbe4
FB		 1381}
1382
76a66253 1383#if !defined (CONFIG_USER_ONLY)
6b80055d 1384void cpu_dump_rfi (target_ulong RA, target_ulong msr);
0411a972
JM		 1385
1386void do_store_msr (void)
1387{
a4f30719 1388 T0 = hreg_store_msr(env, T0, 0);
0411a972
JM		 1389 if (T0 != 0) {
1390 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1391 do_raise_exception(T0);
1392 }
1393}
1394
1395static always_inline void __do_rfi (target_ulong nip, target_ulong msr,
1396 target_ulong msrm, int keep_msrh)
9a64fbe4 1397{
426613db 1398#if defined(TARGET_PPC64)
0411a972
JM		 1399 if (msr & (1ULL << MSR_SF)) {
1400 nip = (uint64_t)nip;
1401 msr &= (uint64_t)msrm;
a42bd6cc 1402 } else {
0411a972
JM		 1403 nip = (uint32_t)nip;
1404 msr = (uint32_t)(msr & msrm);
1405 if (keep_msrh)
1406 msr |= env->msr & ~((uint64_t)0xFFFFFFFF);
a42bd6cc 1407 }
426613db 1408#else
0411a972
JM		 1409 nip = (uint32_t)nip;
1410 msr &= (uint32_t)msrm;
426613db 1411#endif
0411a972
JM		 1412 /* XXX: beware: this is false if VLE is supported */
1413 env->nip = nip & ~((target_ulong)0x00000003);
a4f30719 1414 hreg_store_msr(env, msr, 1);
fdabc366 1415#if defined (DEBUG_OP)
0411a972 1416 cpu_dump_rfi(env->nip, env->msr);
fdabc366 1417#endif
0411a972
JM		 1418 /* No need to raise an exception here,
1419 * as rfi is always the last insn of a TB
1420 */
fdabc366 1421 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
9a64fbe4 1422}
d9bce9d9 1423
0411a972
JM		 1424void do_rfi (void)
1425{
1426 __do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
1427 ~((target_ulong)0xFFFF0000), 1);
1428}
1429
d9bce9d9 1430#if defined(TARGET_PPC64)
426613db
JM		 1431void do_rfid (void)
1432{
0411a972
JM		 1433 __do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
1434 ~((target_ulong)0xFFFF0000), 0);
d9bce9d9 1435}
7863667f 1436
be147d08
JM		 1437void do_hrfid (void)
1438{
0411a972
JM		 1439 __do_rfi(env->spr[SPR_HSRR0], env->spr[SPR_HSRR1],
1440 ~((target_ulong)0xFFFF0000), 0);
be147d08
JM		 1441}
1442#endif
76a66253 1443#endif
9a64fbe4 1444
76a66253 1445void do_tw (int flags)
9a64fbe4 1446{
d9bce9d9
JM		 1447 if (!likely(!(((int32_t)T0 < (int32_t)T1 && (flags & 0x10)) ||
1448 ((int32_t)T0 > (int32_t)T1 && (flags & 0x08)) ||
1449 ((int32_t)T0 == (int32_t)T1 && (flags & 0x04)) ||
1450 ((uint32_t)T0 < (uint32_t)T1 && (flags & 0x02)) ||
a42bd6cc 1451 ((uint32_t)T0 > (uint32_t)T1 && (flags & 0x01))))) {
e1833e1f 1452 do_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
a42bd6cc 1453 }
9a64fbe4
FB		 1454}
1455
d9bce9d9
JM		 1456#if defined(TARGET_PPC64)
1457void do_td (int flags)
1458{
1459 if (!likely(!(((int64_t)T0 < (int64_t)T1 && (flags & 0x10)) ||
1460 ((int64_t)T0 > (int64_t)T1 && (flags & 0x08)) ||
1461 ((int64_t)T0 == (int64_t)T1 && (flags & 0x04)) ||
1462 ((uint64_t)T0 < (uint64_t)T1 && (flags & 0x02)) ||
1463 ((uint64_t)T0 > (uint64_t)T1 && (flags & 0x01)))))
e1833e1f 1464 do_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
d9bce9d9
JM		 1465}
1466#endif
1467
fdabc366 1468/*****************************************************************************/
76a66253
JM		 1469/* PowerPC 601 specific instructions (POWER bridge) */
1470void do_POWER_abso (void)
9a64fbe4 1471{
9c7e37e7 1472 if ((int32_t)T0 == INT32_MIN) {
76a66253
JM		 1473 T0 = INT32_MAX;
1474 xer_ov = 1;
9c7e37e7 1475 } else if ((int32_t)T0 < 0) {
76a66253
JM		 1476 T0 = -T0;
1477 xer_ov = 0;
9c7e37e7
JM		 1478 } else {
1479 xer_ov = 0;
76a66253 1480 }
9c7e37e7 1481 xer_so |= xer_ov;
9a64fbe4
FB		 1482}
1483
76a66253 1484void do_POWER_clcs (void)
9a64fbe4 1485{
76a66253
JM		 1486 switch (T0) {
1487 case 0x0CUL:
1488 /* Instruction cache line size */
d63001d1 1489 T0 = env->icache_line_size;
76a66253
JM		 1490 break;
1491 case 0x0DUL:
1492 /* Data cache line size */
d63001d1 1493 T0 = env->dcache_line_size;
76a66253
JM		 1494 break;
1495 case 0x0EUL:
1496 /* Minimum cache line size */
d63001d1
JM		 1497 T0 = env->icache_line_size < env->dcache_line_size ?
1498 env->icache_line_size : env->dcache_line_size;
76a66253
JM		 1499 break;
1500 case 0x0FUL:
1501 /* Maximum cache line size */
d63001d1
JM		 1502 T0 = env->icache_line_size > env->dcache_line_size ?
1503 env->icache_line_size : env->dcache_line_size;
76a66253
JM		 1504 break;
1505 default:
1506 /* Undefined */
1507 break;
1508 }
1509}
1510
1511void do_POWER_div (void)
1512{
1513 uint64_t tmp;
1514
6f2d8978
JM		 1515 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) ||
1516 (int32_t)T1 == 0) {
1517 T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
76a66253
JM		 1518 env->spr[SPR_MQ] = 0;
1519 } else {
1520 tmp = ((uint64_t)T0 << 32) | env->spr[SPR_MQ];
1521 env->spr[SPR_MQ] = tmp % T1;
d9bce9d9 1522 T0 = tmp / (int32_t)T1;
76a66253
JM		 1523 }
1524}
1525
1526void do_POWER_divo (void)
1527{
1528 int64_t tmp;
1529
6f2d8978
JM		 1530 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) ||
1531 (int32_t)T1 == 0) {
1532 T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
76a66253
JM		 1533 env->spr[SPR_MQ] = 0;
1534 xer_ov = 1;
76a66253
JM		 1535 } else {
1536 tmp = ((uint64_t)T0 << 32) | env->spr[SPR_MQ];
1537 env->spr[SPR_MQ] = tmp % T1;
d9bce9d9 1538 tmp /= (int32_t)T1;
76a66253
JM		 1539 if (tmp > (int64_t)INT32_MAX || tmp < (int64_t)INT32_MIN) {
1540 xer_ov = 1;
76a66253
JM		 1541 } else {
1542 xer_ov = 0;
1543 }
1544 T0 = tmp;
1545 }
6f2d8978 1546 xer_so |= xer_ov;
76a66253
JM		 1547}
1548
1549void do_POWER_divs (void)
1550{
6f2d8978
JM		 1551 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) ||
1552 (int32_t)T1 == 0) {
1553 T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
76a66253
JM		 1554 env->spr[SPR_MQ] = 0;
1555 } else {
1556 env->spr[SPR_MQ] = T0 % T1;
d9bce9d9 1557 T0 = (int32_t)T0 / (int32_t)T1;
76a66253
JM		 1558 }
1559}
1560
1561void do_POWER_divso (void)
1562{
6f2d8978
JM		 1563 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) ||
1564 (int32_t)T1 == 0) {
1565 T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
76a66253
JM		 1566 env->spr[SPR_MQ] = 0;
1567 xer_ov = 1;
76a66253 1568 } else {
d9bce9d9
JM		 1569 T0 = (int32_t)T0 / (int32_t)T1;
1570 env->spr[SPR_MQ] = (int32_t)T0 % (int32_t)T1;
76a66253
JM		 1571 xer_ov = 0;
1572 }
6f2d8978 1573 xer_so |= xer_ov;
76a66253
JM		 1574}
1575
1576void do_POWER_dozo (void)
1577{
d9bce9d9 1578 if ((int32_t)T1 > (int32_t)T0) {
76a66253
JM		 1579 T2 = T0;
1580 T0 = T1 - T0;
d9bce9d9
JM		 1581 if (((uint32_t)(~T2) ^ (uint32_t)T1 ^ UINT32_MAX) &
1582 ((uint32_t)(~T2) ^ (uint32_t)T0) & (1UL << 31)) {
76a66253 1583 xer_ov = 1;
966439a6 1584 xer_so = 1;
76a66253
JM		 1585 } else {
1586 xer_ov = 0;
1587 }
1588 } else {
1589 T0 = 0;
1590 xer_ov = 0;
1591 }
1592}
1593
1594void do_POWER_maskg (void)
1595{
1596 uint32_t ret;
1597
d9bce9d9 1598 if ((uint32_t)T0 == (uint32_t)(T1 + 1)) {
6f2d8978 1599 ret = UINT32_MAX;
76a66253 1600 } else {
6f2d8978
JM		 1601 ret = (UINT32_MAX >> ((uint32_t)T0)) ^
1602 ((UINT32_MAX >> ((uint32_t)T1)) >> 1);
d9bce9d9 1603 if ((uint32_t)T0 > (uint32_t)T1)
76a66253
JM		 1604 ret = ~ret;
1605 }
1606 T0 = ret;
1607}
1608
1609void do_POWER_mulo (void)
1610{
1611 uint64_t tmp;
1612
1613 tmp = (uint64_t)T0 * (uint64_t)T1;
1614 env->spr[SPR_MQ] = tmp >> 32;
1615 T0 = tmp;
1616 if (tmp >> 32 != ((uint64_t)T0 >> 16) * ((uint64_t)T1 >> 16)) {
1617 xer_ov = 1;
1618 xer_so = 1;
1619 } else {
1620 xer_ov = 0;
1621 }
1622}
1623
1624#if !defined (CONFIG_USER_ONLY)
1625void do_POWER_rac (void)
1626{
76a66253 1627 mmu_ctx_t ctx;
faadf50e 1628 int nb_BATs;
76a66253
JM		 1629
1630 /* We don't have to generate many instances of this instruction,
1631 * as rac is supervisor only.
1632 */
faadf50e
JM		 1633 /* XXX: FIX THIS: Pretend we have no BAT */
1634 nb_BATs = env->nb_BATs;
1635 env->nb_BATs = 0;
1636 if (get_physical_address(env, &ctx, T0, 0, ACCESS_INT) == 0)
76a66253 1637 T0 = ctx.raddr;
faadf50e 1638 env->nb_BATs = nb_BATs;
76a66253
JM		 1639}
1640
1641void do_POWER_rfsvc (void)
1642{
0411a972 1643 __do_rfi(env->lr, env->ctr, 0x0000FFFF, 0);
76a66253
JM		 1644}
1645
056401ea
JM		 1646void do_store_hid0_601 (void)
1647{
1648 uint32_t hid0;
1649
1650 hid0 = env->spr[SPR_HID0];
1651 if ((T0 ^ hid0) & 0x00000008) {
1652 /* Change current endianness */
1653 env->hflags &= ~(1 << MSR_LE);
1654 env->hflags_nmsr &= ~(1 << MSR_LE);
1655 env->hflags_nmsr |= (1 << MSR_LE) & (((T0 >> 3) & 1) << MSR_LE);
1656 env->hflags |= env->hflags_nmsr;
1657 if (loglevel != 0) {
1658 fprintf(logfile, "%s: set endianness to %c => " ADDRX "\n",
1659 __func__, T0 & 0x8 ? 'l' : 'b', env->hflags);
1660 }
1661 }
1662 env->spr[SPR_HID0] = T0;
76a66253
JM		 1663}
1664#endif
1665
1666/*****************************************************************************/
1667/* 602 specific instructions */
1668/* mfrom is the most crazy instruction ever seen, imho ! */
1669/* Real implementation uses a ROM table. Do the same */
1670#define USE_MFROM_ROM_TABLE
1671void do_op_602_mfrom (void)
1672{
1673 if (likely(T0 < 602)) {
d9bce9d9 1674#if defined(USE_MFROM_ROM_TABLE)
76a66253
JM		 1675#include "mfrom_table.c"
1676 T0 = mfrom_ROM_table[T0];
fdabc366 1677#else
76a66253
JM		 1678 double d;
1679 /* Extremly decomposed:
1680 * -T0 / 256
1681 * T0 = 256 * log10(10 + 1.0) + 0.5
1682 */
1683 d = T0;
1684 d = float64_div(d, 256, &env->fp_status);
1685 d = float64_chs(d);
1686 d = exp10(d); // XXX: use float emulation function
1687 d = float64_add(d, 1.0, &env->fp_status);
1688 d = log10(d); // XXX: use float emulation function
1689 d = float64_mul(d, 256, &env->fp_status);
1690 d = float64_add(d, 0.5, &env->fp_status);
1691 T0 = float64_round_to_int(d, &env->fp_status);
fdabc366 1692#endif
76a66253
JM		 1693 } else {
1694 T0 = 0;
1695 }
1696}
1697
1698/*****************************************************************************/
1699/* Embedded PowerPC specific helpers */
76a66253
JM		 1700void do_405_check_sat (void)
1701{
d9bce9d9
JM		 1702 if (!likely((((uint32_t)T1 ^ (uint32_t)T2) >> 31) ||
1703 !(((uint32_t)T0 ^ (uint32_t)T2) >> 31))) {
76a66253
JM		 1704 /* Saturate result */
1705 if (T2 >> 31) {
1706 T0 = INT32_MIN;
1707 } else {
1708 T0 = INT32_MAX;
1709 }
1710 }
1711}
1712
a750fc0b
JM		 1713/* XXX: to be improved to check access rights when in user-mode */
1714void do_load_dcr (void)
1715{
1716 target_ulong val;
1717
1718 if (unlikely(env->dcr_env == NULL)) {
1719 if (loglevel != 0) {
1720 fprintf(logfile, "No DCR environment\n");
1721 }
e1833e1f
JM		 1722 do_raise_exception_err(POWERPC_EXCP_PROGRAM,
1723 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
a750fc0b
JM		 1724 } else if (unlikely(ppc_dcr_read(env->dcr_env, T0, &val) != 0)) {
1725 if (loglevel != 0) {
1726 fprintf(logfile, "DCR read error %d %03x\n", (int)T0, (int)T0);
1727 }
e1833e1f
JM		 1728 do_raise_exception_err(POWERPC_EXCP_PROGRAM,
1729 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
a750fc0b
JM		 1730 } else {
1731 T0 = val;
1732 }
1733}
1734
1735void do_store_dcr (void)
1736{
1737 if (unlikely(env->dcr_env == NULL)) {
1738 if (loglevel != 0) {
1739 fprintf(logfile, "No DCR environment\n");
1740 }
e1833e1f
JM		 1741 do_raise_exception_err(POWERPC_EXCP_PROGRAM,
1742 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
a750fc0b
JM		 1743 } else if (unlikely(ppc_dcr_write(env->dcr_env, T0, T1) != 0)) {
1744 if (loglevel != 0) {
1745 fprintf(logfile, "DCR write error %d %03x\n", (int)T0, (int)T0);
1746 }
e1833e1f
JM		 1747 do_raise_exception_err(POWERPC_EXCP_PROGRAM,
1748 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
a750fc0b
JM		 1749 }
1750}
1751
76a66253 1752#if !defined(CONFIG_USER_ONLY)
a42bd6cc 1753void do_40x_rfci (void)
76a66253 1754{
0411a972
JM		 1755 __do_rfi(env->spr[SPR_40x_SRR2], env->spr[SPR_40x_SRR3],
1756 ~((target_ulong)0xFFFF0000), 0);
a42bd6cc
JM		 1757}
1758
1759void do_rfci (void)
1760{
0411a972
JM		 1761 __do_rfi(env->spr[SPR_BOOKE_CSRR0], SPR_BOOKE_CSRR1,
1762 ~((target_ulong)0x3FFF0000), 0);
a42bd6cc
JM		 1763}
1764
1765void do_rfdi (void)
1766{
0411a972
JM		 1767 __do_rfi(env->spr[SPR_BOOKE_DSRR0], SPR_BOOKE_DSRR1,
1768 ~((target_ulong)0x3FFF0000), 0);
a42bd6cc
JM		 1769}
1770
1771void do_rfmci (void)
1772{
0411a972
JM		 1773 __do_rfi(env->spr[SPR_BOOKE_MCSRR0], SPR_BOOKE_MCSRR1,
1774 ~((target_ulong)0x3FFF0000), 0);
76a66253
JM		 1775}
1776
76a66253
JM		 1777void do_load_403_pb (int num)
1778{
1779 T0 = env->pb[num];
1780}
1781
1782void do_store_403_pb (int num)
1783{
1784 if (likely(env->pb[num] != T0)) {
1785 env->pb[num] = T0;
1786 /* Should be optimized */
1787 tlb_flush(env, 1);
1788 }
1789}
1790#endif
1791
1792/* 440 specific */
1793void do_440_dlmzb (void)
1794{
1795 target_ulong mask;
1796 int i;
1797
1798 i = 1;
1799 for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
1800 if ((T0 & mask) == 0)
1801 goto done;
1802 i++;
1803 }
1804 for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
1805 if ((T1 & mask) == 0)
1806 break;
1807 i++;
1808 }
1809 done:
1810 T0 = i;
fdabc366
FB		 1811}
1812
0487d6a8
JM		 1813/* SPE extension helpers */
1814/* Use a table to make this quicker */
1815static uint8_t hbrev[16] = {
1816 0x0, 0x8, 0x4, 0xC, 0x2, 0xA, 0x6, 0xE,
1817 0x1, 0x9, 0x5, 0xD, 0x3, 0xB, 0x7, 0xF,
1818};
1819
b068d6a7 1820static always_inline uint8_t byte_reverse (uint8_t val)
0487d6a8
JM		 1821{
1822 return hbrev[val >> 4] | (hbrev[val & 0xF] << 4);
1823}
1824
b068d6a7 1825static always_inline uint32_t word_reverse (uint32_t val)
0487d6a8
JM		 1826{
1827 return byte_reverse(val >> 24) | (byte_reverse(val >> 16) << 8) |
1828 (byte_reverse(val >> 8) << 16) | (byte_reverse(val) << 24);
1829}
1830
3cd7d1dd 1831#define MASKBITS 16 // Random value - to be fixed (implementation dependant)
0487d6a8
JM		 1832void do_brinc (void)
1833{
1834 uint32_t a, b, d, mask;
1835
3cd7d1dd
JM		 1836 mask = UINT32_MAX >> (32 - MASKBITS);
1837 a = T0 & mask;
1838 b = T1 & mask;
1839 d = word_reverse(1 + word_reverse(a | ~b));
1840 T0 = (T0 & ~mask) | (d & b);
0487d6a8
JM		 1841}
1842
1843#define DO_SPE_OP2(name) \
1844void do_ev##name (void) \
1845{ \
1846 T0_64 = ((uint64_t)_do_e##name(T0_64 >> 32, T1_64 >> 32) << 32) | \
1847 (uint64_t)_do_e##name(T0_64, T1_64); \
1848}
1849
1850#define DO_SPE_OP1(name) \
1851void do_ev##name (void) \
1852{ \
1853 T0_64 = ((uint64_t)_do_e##name(T0_64 >> 32) << 32) | \
1854 (uint64_t)_do_e##name(T0_64); \
1855}
1856
1857/* Fixed-point vector arithmetic */
b068d6a7 1858static always_inline uint32_t _do_eabs (uint32_t val)
0487d6a8 1859{
9c7e37e7
JM		 1860 if ((val & 0x80000000) && val != 0x80000000)
1861 val -= val;
0487d6a8
JM		 1862
1863 return val;
1864}
1865
b068d6a7 1866static always_inline uint32_t _do_eaddw (uint32_t op1, uint32_t op2)
0487d6a8
JM		 1867{
1868 return op1 + op2;
1869}
1870
b068d6a7 1871static always_inline int _do_ecntlsw (uint32_t val)
0487d6a8
JM		 1872{
1873 if (val & 0x80000000)
603fccce 1874 return clz32(~val);
0487d6a8 1875 else
603fccce 1876 return clz32(val);
0487d6a8
JM		 1877}
1878
b068d6a7 1879static always_inline int _do_ecntlzw (uint32_t val)
0487d6a8 1880{
603fccce 1881 return clz32(val);
0487d6a8
JM		 1882}
1883
b068d6a7 1884static always_inline uint32_t _do_eneg (uint32_t val)
0487d6a8
JM		 1885{
1886 if (val != 0x80000000)
9c7e37e7 1887 val -= val;
0487d6a8
JM		 1888
1889 return val;
1890}
1891
b068d6a7 1892static always_inline uint32_t _do_erlw (uint32_t op1, uint32_t op2)
0487d6a8
JM		 1893{
1894 return rotl32(op1, op2);
1895}
1896
b068d6a7 1897static always_inline uint32_t _do_erndw (uint32_t val)
0487d6a8
JM		 1898{
1899 return (val + 0x000080000000) & 0xFFFF0000;
1900}
1901
b068d6a7 1902static always_inline uint32_t _do_eslw (uint32_t op1, uint32_t op2)
0487d6a8
JM		 1903{
1904 /* No error here: 6 bits are used */
1905 return op1 << (op2 & 0x3F);
1906}
1907
b068d6a7 1908static always_inline int32_t _do_esrws (int32_t op1, uint32_t op2)
0487d6a8
JM		 1909{
1910 /* No error here: 6 bits are used */
1911 return op1 >> (op2 & 0x3F);
1912}
1913
b068d6a7 1914static always_inline uint32_t _do_esrwu (uint32_t op1, uint32_t op2)
0487d6a8
JM		 1915{
1916 /* No error here: 6 bits are used */
1917 return op1 >> (op2 & 0x3F);
1918}
1919
b068d6a7 1920static always_inline uint32_t _do_esubfw (uint32_t op1, uint32_t op2)
0487d6a8
JM		 1921{
1922 return op2 - op1;
1923}
1924
1925/* evabs */
1926DO_SPE_OP1(abs);
1927/* evaddw */
1928DO_SPE_OP2(addw);
1929/* evcntlsw */
1930DO_SPE_OP1(cntlsw);
1931/* evcntlzw */
1932DO_SPE_OP1(cntlzw);
1933/* evneg */
1934DO_SPE_OP1(neg);
1935/* evrlw */
1936DO_SPE_OP2(rlw);
1937/* evrnd */
1938DO_SPE_OP1(rndw);
1939/* evslw */
1940DO_SPE_OP2(slw);
1941/* evsrws */
1942DO_SPE_OP2(srws);
1943/* evsrwu */
1944DO_SPE_OP2(srwu);
1945/* evsubfw */
1946DO_SPE_OP2(subfw);
1947
1948/* evsel is a little bit more complicated... */
b068d6a7 1949static always_inline uint32_t _do_esel (uint32_t op1, uint32_t op2, int n)
0487d6a8
JM		 1950{
1951 if (n)
1952 return op1;
1953 else
1954 return op2;
1955}
1956
1957void do_evsel (void)
1958{
1959 T0_64 = ((uint64_t)_do_esel(T0_64 >> 32, T1_64 >> 32, T0 >> 3) << 32) |
1960 (uint64_t)_do_esel(T0_64, T1_64, (T0 >> 2) & 1);
1961}
1962
1963/* Fixed-point vector comparisons */
1964#define DO_SPE_CMP(name) \
1965void do_ev##name (void) \
1966{ \
1967 T0 = _do_evcmp_merge((uint64_t)_do_e##name(T0_64 >> 32, \
1968 T1_64 >> 32) << 32, \
1969 _do_e##name(T0_64, T1_64)); \
1970}
1971
b068d6a7 1972static always_inline uint32_t _do_evcmp_merge (int t0, int t1)
0487d6a8
JM		 1973{
1974 return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1);
1975}
b068d6a7 1976static always_inline int _do_ecmpeq (uint32_t op1, uint32_t op2)
0487d6a8
JM		 1977{
1978 return op1 == op2 ? 1 : 0;
1979}
1980
b068d6a7 1981static always_inline int _do_ecmpgts (int32_t op1, int32_t op2)
0487d6a8
JM		 1982{
1983 return op1 > op2 ? 1 : 0;
1984}
1985
b068d6a7 1986static always_inline int _do_ecmpgtu (uint32_t op1, uint32_t op2)
0487d6a8
JM		 1987{
1988 return op1 > op2 ? 1 : 0;
1989}
1990
b068d6a7 1991static always_inline int _do_ecmplts (int32_t op1, int32_t op2)
0487d6a8
JM		 1992{
1993 return op1 < op2 ? 1 : 0;
1994}
1995
b068d6a7 1996static always_inline int _do_ecmpltu (uint32_t op1, uint32_t op2)
0487d6a8
JM		 1997{
1998 return op1 < op2 ? 1 : 0;
1999}
2000
2001/* evcmpeq */
2002DO_SPE_CMP(cmpeq);
2003/* evcmpgts */
2004DO_SPE_CMP(cmpgts);
2005/* evcmpgtu */
2006DO_SPE_CMP(cmpgtu);
2007/* evcmplts */
2008DO_SPE_CMP(cmplts);
2009/* evcmpltu */
2010DO_SPE_CMP(cmpltu);
2011
2012/* Single precision floating-point conversions from/to integer */
b068d6a7 2013static always_inline uint32_t _do_efscfsi (int32_t val)
0487d6a8 2014{
0ca9d380 2015 CPU_FloatU u;
0487d6a8
JM		 2016
2017 u.f = int32_to_float32(val, &env->spe_status);
2018
0ca9d380 2019 return u.l;
0487d6a8
JM		 2020}
2021
b068d6a7 2022static always_inline uint32_t _do_efscfui (uint32_t val)
0487d6a8 2023{
0ca9d380 2024 CPU_FloatU u;
0487d6a8
JM		 2025
2026 u.f = uint32_to_float32(val, &env->spe_status);
2027
0ca9d380 2028 return u.l;
0487d6a8
JM		 2029}
2030
b068d6a7 2031static always_inline int32_t _do_efsctsi (uint32_t val)
0487d6a8 2032{
0ca9d380 2033 CPU_FloatU u;
0487d6a8 2034
0ca9d380 2035 u.l = val;
0487d6a8
JM		 2036 /* NaN are not treated the same way IEEE 754 does */
2037 if (unlikely(isnan(u.f)))
2038 return 0;
2039
2040 return float32_to_int32(u.f, &env->spe_status);
2041}
2042
b068d6a7 2043static always_inline uint32_t _do_efsctui (uint32_t val)
0487d6a8 2044{
0ca9d380 2045 CPU_FloatU u;
0487d6a8 2046
0ca9d380 2047 u.l = val;
0487d6a8
JM		 2048 /* NaN are not treated the same way IEEE 754 does */
2049 if (unlikely(isnan(u.f)))
2050 return 0;
2051
2052 return float32_to_uint32(u.f, &env->spe_status);
2053}
2054
b068d6a7 2055static always_inline int32_t _do_efsctsiz (uint32_t val)
0487d6a8 2056{
0ca9d380 2057 CPU_FloatU u;
0487d6a8 2058
0ca9d380 2059 u.l = val;
0487d6a8
JM		 2060 /* NaN are not treated the same way IEEE 754 does */
2061 if (unlikely(isnan(u.f)))
2062 return 0;
2063
2064 return float32_to_int32_round_to_zero(u.f, &env->spe_status);
2065}
2066
b068d6a7 2067static always_inline uint32_t _do_efsctuiz (uint32_t val)
0487d6a8 2068{
0ca9d380 2069 CPU_FloatU u;
0487d6a8 2070
0ca9d380 2071 u.l = val;
0487d6a8
JM		 2072 /* NaN are not treated the same way IEEE 754 does */
2073 if (unlikely(isnan(u.f)))
2074 return 0;
2075
2076 return float32_to_uint32_round_to_zero(u.f, &env->spe_status);
2077}
2078
2079void do_efscfsi (void)
2080{
2081 T0_64 = _do_efscfsi(T0_64);
2082}
2083
2084void do_efscfui (void)
2085{
2086 T0_64 = _do_efscfui(T0_64);
2087}
2088
2089void do_efsctsi (void)
2090{
2091 T0_64 = _do_efsctsi(T0_64);
2092}
2093
2094void do_efsctui (void)
2095{
2096 T0_64 = _do_efsctui(T0_64);
2097}
2098
2099void do_efsctsiz (void)
2100{
2101 T0_64 = _do_efsctsiz(T0_64);
2102}
2103
2104void do_efsctuiz (void)
2105{
2106 T0_64 = _do_efsctuiz(T0_64);
2107}
2108
2109/* Single precision floating-point conversion to/from fractional */
b068d6a7 2110static always_inline uint32_t _do_efscfsf (uint32_t val)
0487d6a8 2111{
0ca9d380 2112 CPU_FloatU u;
0487d6a8
JM		 2113 float32 tmp;
2114
2115 u.f = int32_to_float32(val, &env->spe_status);
2116 tmp = int64_to_float32(1ULL << 32, &env->spe_status);
2117 u.f = float32_div(u.f, tmp, &env->spe_status);
2118
0ca9d380 2119 return u.l;
0487d6a8
JM		 2120}
2121
b068d6a7 2122static always_inline uint32_t _do_efscfuf (uint32_t val)
0487d6a8 2123{
0ca9d380 2124 CPU_FloatU u;
0487d6a8
JM		 2125 float32 tmp;
2126
2127 u.f = uint32_to_float32(val, &env->spe_status);
2128 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2129 u.f = float32_div(u.f, tmp, &env->spe_status);
2130
0ca9d380 2131 return u.l;
0487d6a8
JM		 2132}
2133
b068d6a7 2134static always_inline int32_t _do_efsctsf (uint32_t val)
0487d6a8 2135{
0ca9d380 2136 CPU_FloatU u;
0487d6a8
JM		 2137 float32 tmp;
2138
0ca9d380 2139 u.l = val;
0487d6a8
JM		 2140 /* NaN are not treated the same way IEEE 754 does */
2141 if (unlikely(isnan(u.f)))
2142 return 0;
2143 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2144 u.f = float32_mul(u.f, tmp, &env->spe_status);
2145
2146 return float32_to_int32(u.f, &env->spe_status);
2147}
2148
b068d6a7 2149static always_inline uint32_t _do_efsctuf (uint32_t val)
0487d6a8 2150{
0ca9d380 2151 CPU_FloatU u;
0487d6a8
JM		 2152 float32 tmp;
2153
0ca9d380 2154 u.l = val;
0487d6a8
JM		 2155 /* NaN are not treated the same way IEEE 754 does */
2156 if (unlikely(isnan(u.f)))
2157 return 0;
2158 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2159 u.f = float32_mul(u.f, tmp, &env->spe_status);
2160
2161 return float32_to_uint32(u.f, &env->spe_status);
2162}
2163
b068d6a7 2164static always_inline int32_t _do_efsctsfz (uint32_t val)
0487d6a8 2165{
0ca9d380 2166 CPU_FloatU u;
0487d6a8
JM		 2167 float32 tmp;
2168
0ca9d380 2169 u.l = val;
0487d6a8
JM		 2170 /* NaN are not treated the same way IEEE 754 does */
2171 if (unlikely(isnan(u.f)))
2172 return 0;
2173 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2174 u.f = float32_mul(u.f, tmp, &env->spe_status);
2175
2176 return float32_to_int32_round_to_zero(u.f, &env->spe_status);
2177}
2178
b068d6a7 2179static always_inline uint32_t _do_efsctufz (uint32_t val)
0487d6a8 2180{
0ca9d380 2181 CPU_FloatU u;
0487d6a8
JM		 2182 float32 tmp;
2183
0ca9d380 2184 u.l = val;
0487d6a8
JM		 2185 /* NaN are not treated the same way IEEE 754 does */
2186 if (unlikely(isnan(u.f)))
2187 return 0;
2188 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2189 u.f = float32_mul(u.f, tmp, &env->spe_status);
2190
2191 return float32_to_uint32_round_to_zero(u.f, &env->spe_status);
2192}
2193
2194void do_efscfsf (void)
2195{
2196 T0_64 = _do_efscfsf(T0_64);
2197}
2198
2199void do_efscfuf (void)
2200{
2201 T0_64 = _do_efscfuf(T0_64);
2202}
2203
2204void do_efsctsf (void)
2205{
2206 T0_64 = _do_efsctsf(T0_64);
2207}
2208
2209void do_efsctuf (void)
2210{
2211 T0_64 = _do_efsctuf(T0_64);
2212}
2213
2214void do_efsctsfz (void)
2215{
2216 T0_64 = _do_efsctsfz(T0_64);
2217}
2218
2219void do_efsctufz (void)
2220{
2221 T0_64 = _do_efsctufz(T0_64);
2222}
2223
2224/* Double precision floating point helpers */
b068d6a7 2225static always_inline int _do_efdcmplt (uint64_t op1, uint64_t op2)
0487d6a8
JM		 2226{
2227 /* XXX: TODO: test special values (NaN, infinites, ...) */
2228 return _do_efdtstlt(op1, op2);
2229}
2230
b068d6a7 2231static always_inline int _do_efdcmpgt (uint64_t op1, uint64_t op2)
0487d6a8
JM		 2232{
2233 /* XXX: TODO: test special values (NaN, infinites, ...) */
2234 return _do_efdtstgt(op1, op2);
2235}
2236
b068d6a7 2237static always_inline int _do_efdcmpeq (uint64_t op1, uint64_t op2)
0487d6a8
JM		 2238{
2239 /* XXX: TODO: test special values (NaN, infinites, ...) */
2240 return _do_efdtsteq(op1, op2);
2241}
2242
2243void do_efdcmplt (void)
2244{
2245 T0 = _do_efdcmplt(T0_64, T1_64);
2246}
2247
2248void do_efdcmpgt (void)
2249{
2250 T0 = _do_efdcmpgt(T0_64, T1_64);
2251}
2252
2253void do_efdcmpeq (void)
2254{
2255 T0 = _do_efdcmpeq(T0_64, T1_64);
2256}
2257
2258/* Double precision floating-point conversion to/from integer */
b068d6a7 2259static always_inline uint64_t _do_efdcfsi (int64_t val)
0487d6a8 2260{
0ca9d380 2261 CPU_DoubleU u;
0487d6a8 2262
0ca9d380 2263 u.d = int64_to_float64(val, &env->spe_status);
0487d6a8 2264
0ca9d380 2265 return u.ll;
0487d6a8
JM		 2266}
2267
b068d6a7 2268static always_inline uint64_t _do_efdcfui (uint64_t val)
0487d6a8 2269{
0ca9d380 2270 CPU_DoubleU u;
0487d6a8 2271
0ca9d380 2272 u.d = uint64_to_float64(val, &env->spe_status);
0487d6a8 2273
0ca9d380 2274 return u.ll;
0487d6a8
JM		 2275}
2276
b068d6a7 2277static always_inline int64_t _do_efdctsi (uint64_t val)
0487d6a8 2278{
0ca9d380 2279 CPU_DoubleU u;
0487d6a8 2280
0ca9d380 2281 u.ll = val;
0487d6a8 2282 /* NaN are not treated the same way IEEE 754 does */
0ca9d380 2283 if (unlikely(isnan(u.d)))
0487d6a8
JM		 2284 return 0;
2285
0ca9d380 2286 return float64_to_int64(u.d, &env->spe_status);
0487d6a8
JM		 2287}
2288
b068d6a7 2289static always_inline uint64_t _do_efdctui (uint64_t val)
0487d6a8 2290{
0ca9d380 2291 CPU_DoubleU u;
0487d6a8 2292
0ca9d380 2293 u.ll = val;
0487d6a8 2294 /* NaN are not treated the same way IEEE 754 does */
0ca9d380 2295 if (unlikely(isnan(u.d)))
0487d6a8
JM		 2296 return 0;
2297
0ca9d380 2298 return float64_to_uint64(u.d, &env->spe_status);
0487d6a8
JM		 2299}
2300
b068d6a7 2301static always_inline int64_t _do_efdctsiz (uint64_t val)
0487d6a8 2302{
0ca9d380 2303 CPU_DoubleU u;
0487d6a8 2304
0ca9d380 2305 u.ll = val;
0487d6a8 2306 /* NaN are not treated the same way IEEE 754 does */
0ca9d380 2307 if (unlikely(isnan(u.d)))
0487d6a8
JM		 2308 return 0;
2309
0ca9d380 2310 return float64_to_int64_round_to_zero(u.d, &env->spe_status);
0487d6a8
JM		 2311}
2312
b068d6a7 2313static always_inline uint64_t _do_efdctuiz (uint64_t val)
0487d6a8 2314{
0ca9d380 2315 CPU_DoubleU u;
0487d6a8 2316
0ca9d380 2317 u.ll = val;
0487d6a8 2318 /* NaN are not treated the same way IEEE 754 does */
0ca9d380 2319 if (unlikely(isnan(u.d)))
0487d6a8
JM		 2320 return 0;
2321
0ca9d380 2322 return float64_to_uint64_round_to_zero(u.d, &env->spe_status);
0487d6a8
JM		 2323}
2324
2325void do_efdcfsi (void)
2326{
2327 T0_64 = _do_efdcfsi(T0_64);
2328}
2329
2330void do_efdcfui (void)
2331{
2332 T0_64 = _do_efdcfui(T0_64);
2333}
2334
2335void do_efdctsi (void)
2336{
2337 T0_64 = _do_efdctsi(T0_64);
2338}
2339
2340void do_efdctui (void)
2341{
2342 T0_64 = _do_efdctui(T0_64);
2343}
2344
2345void do_efdctsiz (void)
2346{
2347 T0_64 = _do_efdctsiz(T0_64);
2348}
2349
2350void do_efdctuiz (void)
2351{
2352 T0_64 = _do_efdctuiz(T0_64);
2353}
2354
2355/* Double precision floating-point conversion to/from fractional */
b068d6a7 2356static always_inline uint64_t _do_efdcfsf (int64_t val)
0487d6a8 2357{
0ca9d380 2358 CPU_DoubleU u;
0487d6a8
JM		 2359 float64 tmp;
2360
0ca9d380 2361 u.d = int32_to_float64(val, &env->spe_status);
0487d6a8 2362 tmp = int64_to_float64(1ULL << 32, &env->spe_status);
0ca9d380 2363 u.d = float64_div(u.d, tmp, &env->spe_status);
0487d6a8 2364
0ca9d380 2365 return u.ll;
0487d6a8
JM		 2366}
2367
b068d6a7 2368static always_inline uint64_t _do_efdcfuf (uint64_t val)
0487d6a8 2369{
0ca9d380 2370 CPU_DoubleU u;
0487d6a8
JM		 2371 float64 tmp;
2372
0ca9d380 2373 u.d = uint32_to_float64(val, &env->spe_status);
0487d6a8 2374 tmp = int64_to_float64(1ULL << 32, &env->spe_status);
0ca9d380 2375 u.d = float64_div(u.d, tmp, &env->spe_status);
0487d6a8 2376
0ca9d380 2377 return u.ll;
0487d6a8
JM		 2378}
2379
b068d6a7 2380static always_inline int64_t _do_efdctsf (uint64_t val)
0487d6a8 2381{
0ca9d380 2382 CPU_DoubleU u;
0487d6a8
JM		 2383 float64 tmp;
2384
0ca9d380 2385 u.ll = val;
0487d6a8 2386 /* NaN are not treated the same way IEEE 754 does */
0ca9d380 2387 if (unlikely(isnan(u.d)))
0487d6a8
JM		 2388 return 0;
2389 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
0ca9d380 2390 u.d = float64_mul(u.d, tmp, &env->spe_status);
0487d6a8 2391
0ca9d380 2392 return float64_to_int32(u.d, &env->spe_status);
0487d6a8
JM		 2393}
2394
b068d6a7 2395static always_inline uint64_t _do_efdctuf (uint64_t val)
0487d6a8 2396{
0ca9d380 2397 CPU_DoubleU u;
0487d6a8
JM		 2398 float64 tmp;
2399
0ca9d380 2400 u.ll = val;
0487d6a8 2401 /* NaN are not treated the same way IEEE 754 does */
0ca9d380 2402 if (unlikely(isnan(u.d)))
0487d6a8
JM		 2403 return 0;
2404 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
0ca9d380 2405 u.d = float64_mul(u.d, tmp, &env->spe_status);
0487d6a8 2406
0ca9d380 2407 return float64_to_uint32(u.d, &env->spe_status);
0487d6a8
JM		 2408}
2409
b068d6a7 2410static always_inline int64_t _do_efdctsfz (uint64_t val)
0487d6a8 2411{
0ca9d380 2412 CPU_DoubleU u;
0487d6a8
JM		 2413 float64 tmp;
2414
0ca9d380 2415 u.ll = val;
0487d6a8 2416 /* NaN are not treated the same way IEEE 754 does */
0ca9d380 2417 if (unlikely(isnan(u.d)))
0487d6a8
JM		 2418 return 0;
2419 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
0ca9d380 2420 u.d = float64_mul(u.d, tmp, &env->spe_status);
0487d6a8 2421
0ca9d380 2422 return float64_to_int32_round_to_zero(u.d, &env->spe_status);
0487d6a8
JM		 2423}
2424
b068d6a7 2425static always_inline uint64_t _do_efdctufz (uint64_t val)
0487d6a8 2426{
0ca9d380 2427 CPU_DoubleU u;
0487d6a8
JM		 2428 float64 tmp;
2429
0ca9d380 2430 u.ll = val;
0487d6a8 2431 /* NaN are not treated the same way IEEE 754 does */
0ca9d380 2432 if (unlikely(isnan(u.d)))
0487d6a8
JM		 2433 return 0;
2434 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
0ca9d380 2435 u.d = float64_mul(u.d, tmp, &env->spe_status);
0487d6a8 2436
0ca9d380 2437 return float64_to_uint32_round_to_zero(u.d, &env->spe_status);
0487d6a8
JM		 2438}
2439
2440void do_efdcfsf (void)
2441{
2442 T0_64 = _do_efdcfsf(T0_64);
2443}
2444
2445void do_efdcfuf (void)
2446{
2447 T0_64 = _do_efdcfuf(T0_64);
2448}
2449
2450void do_efdctsf (void)
2451{
2452 T0_64 = _do_efdctsf(T0_64);
2453}
2454
2455void do_efdctuf (void)
2456{
2457 T0_64 = _do_efdctuf(T0_64);
2458}
2459
2460void do_efdctsfz (void)
2461{
2462 T0_64 = _do_efdctsfz(T0_64);
2463}
2464
2465void do_efdctufz (void)
2466{
2467 T0_64 = _do_efdctufz(T0_64);
2468}
2469
2470/* Floating point conversion between single and double precision */
b068d6a7 2471static always_inline uint32_t _do_efscfd (uint64_t val)
0487d6a8 2472{
0ca9d380
AJ		 2473 CPU_DoubleU u1;
2474 CPU_FloatU u2;
0487d6a8 2475
0ca9d380
AJ		 2476 u1.ll = val;
2477 u2.f = float64_to_float32(u1.d, &env->spe_status);
0487d6a8 2478
0ca9d380 2479 return u2.l;
0487d6a8
JM		 2480}
2481
b068d6a7 2482static always_inline uint64_t _do_efdcfs (uint32_t val)
0487d6a8 2483{
0ca9d380
AJ		 2484 CPU_DoubleU u2;
2485 CPU_FloatU u1;
0487d6a8 2486
0ca9d380
AJ		 2487 u1.l = val;
2488 u2.d = float32_to_float64(u1.f, &env->spe_status);
0487d6a8 2489
0ca9d380 2490 return u2.ll;
0487d6a8
JM		 2491}
2492
2493void do_efscfd (void)
2494{
2495 T0_64 = _do_efscfd(T0_64);
2496}
2497
2498void do_efdcfs (void)
2499{
2500 T0_64 = _do_efdcfs(T0_64);
2501}
2502
2503/* Single precision fixed-point vector arithmetic */
2504/* evfsabs */
2505DO_SPE_OP1(fsabs);
2506/* evfsnabs */
2507DO_SPE_OP1(fsnabs);
2508/* evfsneg */
2509DO_SPE_OP1(fsneg);
2510/* evfsadd */
2511DO_SPE_OP2(fsadd);
2512/* evfssub */
2513DO_SPE_OP2(fssub);
2514/* evfsmul */
2515DO_SPE_OP2(fsmul);
2516/* evfsdiv */
2517DO_SPE_OP2(fsdiv);
2518
2519/* Single-precision floating-point comparisons */
b068d6a7 2520static always_inline int _do_efscmplt (uint32_t op1, uint32_t op2)
0487d6a8
JM		 2521{
2522 /* XXX: TODO: test special values (NaN, infinites, ...) */
2523 return _do_efststlt(op1, op2);
2524}
2525
b068d6a7 2526static always_inline int _do_efscmpgt (uint32_t op1, uint32_t op2)
0487d6a8
JM		 2527{
2528 /* XXX: TODO: test special values (NaN, infinites, ...) */
2529 return _do_efststgt(op1, op2);
2530}
2531
b068d6a7 2532static always_inline int _do_efscmpeq (uint32_t op1, uint32_t op2)
0487d6a8
JM		 2533{
2534 /* XXX: TODO: test special values (NaN, infinites, ...) */
2535 return _do_efststeq(op1, op2);
2536}
2537
2538void do_efscmplt (void)
2539{
2540 T0 = _do_efscmplt(T0_64, T1_64);
2541}
2542
2543void do_efscmpgt (void)
2544{
2545 T0 = _do_efscmpgt(T0_64, T1_64);
2546}
2547
2548void do_efscmpeq (void)
2549{
2550 T0 = _do_efscmpeq(T0_64, T1_64);
2551}
2552
2553/* Single-precision floating-point vector comparisons */
2554/* evfscmplt */
2555DO_SPE_CMP(fscmplt);
2556/* evfscmpgt */
2557DO_SPE_CMP(fscmpgt);
2558/* evfscmpeq */
2559DO_SPE_CMP(fscmpeq);
2560/* evfststlt */
2561DO_SPE_CMP(fststlt);
2562/* evfststgt */
2563DO_SPE_CMP(fststgt);
2564/* evfststeq */
2565DO_SPE_CMP(fststeq);
2566
2567/* Single-precision floating-point vector conversions */
2568/* evfscfsi */
2569DO_SPE_OP1(fscfsi);
2570/* evfscfui */
2571DO_SPE_OP1(fscfui);
2572/* evfscfuf */
2573DO_SPE_OP1(fscfuf);
2574/* evfscfsf */
2575DO_SPE_OP1(fscfsf);
2576/* evfsctsi */
2577DO_SPE_OP1(fsctsi);
2578/* evfsctui */
2579DO_SPE_OP1(fsctui);
2580/* evfsctsiz */
2581DO_SPE_OP1(fsctsiz);
2582/* evfsctuiz */
2583DO_SPE_OP1(fsctuiz);
2584/* evfsctsf */
2585DO_SPE_OP1(fsctsf);
2586/* evfsctuf */
2587DO_SPE_OP1(fsctuf);
0487d6a8 2588
fdabc366
FB		 2589/*****************************************************************************/
2590/* Softmmu support */
2591#if !defined (CONFIG_USER_ONLY)
2592
2593#define MMUSUFFIX _mmu
273af660
TS		 2594#ifdef __s390__
2595# define GETPC() ((void*)((unsigned long)__builtin_return_address(0) & 0x7fffffffUL))
2596#else
2597# define GETPC() (__builtin_return_address(0))
2598#endif
fdabc366
FB		 2599
2600#define SHIFT 0
2601#include "softmmu_template.h"
2602
2603#define SHIFT 1
2604#include "softmmu_template.h"
2605
2606#define SHIFT 2
2607#include "softmmu_template.h"
2608
2609#define SHIFT 3
2610#include "softmmu_template.h"
2611
2612/* try to fill the TLB and return an exception if error. If retaddr is
2613 NULL, it means that the function was called in C code (i.e. not
2614 from generated code or from helper.c) */
2615/* XXX: fix it to restore all registers */
6ebbf390 2616void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
fdabc366
FB		 2617{
2618 TranslationBlock *tb;
2619 CPUState *saved_env;
44f8625d 2620 unsigned long pc;
fdabc366
FB		 2621 int ret;
2622
2623 /* XXX: hack to restore env in all cases, even if not called from
2624 generated code */
2625 saved_env = env;
2626 env = cpu_single_env;
6ebbf390 2627 ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
76a66253 2628 if (unlikely(ret != 0)) {
fdabc366
FB		 2629 if (likely(retaddr)) {
2630 /* now we have a real cpu fault */
44f8625d 2631 pc = (unsigned long)retaddr;
fdabc366
FB		 2632 tb = tb_find_pc(pc);
2633 if (likely(tb)) {
2634 /* the PC is inside the translated code. It means that we have
2635 a virtual CPU fault */
2636 cpu_restore_state(tb, env, pc, NULL);
76a66253 2637 }
fdabc366
FB		 2638 }
2639 do_raise_exception_err(env->exception_index, env->error_code);
2640 }
2641 env = saved_env;
9a64fbe4
FB		 2642}
2643
76a66253
JM		 2644/* Software driven TLBs management */
2645/* PowerPC 602/603 software TLB load instructions helpers */
2646void do_load_6xx_tlb (int is_code)
2647{
2648 target_ulong RPN, CMP, EPN;
2649 int way;
d9bce9d9 2650
76a66253
JM		 2651 RPN = env->spr[SPR_RPA];
2652 if (is_code) {
2653 CMP = env->spr[SPR_ICMP];
2654 EPN = env->spr[SPR_IMISS];
2655 } else {
2656 CMP = env->spr[SPR_DCMP];
2657 EPN = env->spr[SPR_DMISS];
2658 }
2659 way = (env->spr[SPR_SRR1] >> 17) & 1;
2660#if defined (DEBUG_SOFTWARE_TLB)
2661 if (loglevel != 0) {
6b542af7
JM		 2662 fprintf(logfile, "%s: EPN " TDX " " ADDRX " PTE0 " ADDRX
2663 " PTE1 " ADDRX " way %d\n",
2664 __func__, T0, EPN, CMP, RPN, way);
76a66253
JM		 2665 }
2666#endif
2667 /* Store this TLB */
d9bce9d9
JM		 2668 ppc6xx_tlb_store(env, (uint32_t)(T0 & TARGET_PAGE_MASK),
2669 way, is_code, CMP, RPN);
76a66253
JM		 2670}
2671
7dbe11ac
JM		 2672void do_load_74xx_tlb (int is_code)
2673{
2674 target_ulong RPN, CMP, EPN;
2675 int way;
2676
2677 RPN = env->spr[SPR_PTELO];
2678 CMP = env->spr[SPR_PTEHI];
2679 EPN = env->spr[SPR_TLBMISS] & ~0x3;
2680 way = env->spr[SPR_TLBMISS] & 0x3;
2681#if defined (DEBUG_SOFTWARE_TLB)
2682 if (loglevel != 0) {
6b542af7
JM		 2683 fprintf(logfile, "%s: EPN " TDX " " ADDRX " PTE0 " ADDRX
2684 " PTE1 " ADDRX " way %d\n",
2685 __func__, T0, EPN, CMP, RPN, way);
7dbe11ac
JM		 2686 }
2687#endif
2688 /* Store this TLB */
2689 ppc6xx_tlb_store(env, (uint32_t)(T0 & TARGET_PAGE_MASK),
2690 way, is_code, CMP, RPN);
2691}
2692
a11b8151 2693static always_inline target_ulong booke_tlb_to_page_size (int size)
a8dea12f
JM		 2694{
2695 return 1024 << (2 * size);
2696}
2697
a11b8151 2698static always_inline int booke_page_size_to_tlb (target_ulong page_size)
a8dea12f
JM		 2699{
2700 int size;
2701
2702 switch (page_size) {
2703 case 0x00000400UL:
2704 size = 0x0;
2705 break;
2706 case 0x00001000UL:
2707 size = 0x1;
2708 break;
2709 case 0x00004000UL:
2710 size = 0x2;
2711 break;
2712 case 0x00010000UL:
2713 size = 0x3;
2714 break;
2715 case 0x00040000UL:
2716 size = 0x4;
2717 break;
2718 case 0x00100000UL:
2719 size = 0x5;
2720 break;
2721 case 0x00400000UL:
2722 size = 0x6;
2723 break;
2724 case 0x01000000UL:
2725 size = 0x7;
2726 break;
2727 case 0x04000000UL:
2728 size = 0x8;
2729 break;
2730 case 0x10000000UL:
2731 size = 0x9;
2732 break;
2733 case 0x40000000UL:
2734 size = 0xA;
2735 break;
2736#if defined (TARGET_PPC64)
2737 case 0x000100000000ULL:
2738 size = 0xB;
2739 break;
2740 case 0x000400000000ULL:
2741 size = 0xC;
2742 break;
2743 case 0x001000000000ULL:
2744 size = 0xD;
2745 break;
2746 case 0x004000000000ULL:
2747 size = 0xE;
2748 break;
2749 case 0x010000000000ULL:
2750 size = 0xF;
2751 break;
2752#endif
2753 default:
2754 size = -1;
2755 break;
2756 }
2757
2758 return size;
2759}
2760
76a66253 2761/* Helpers for 4xx TLB management */
76a66253
JM		 2762void do_4xx_tlbre_lo (void)
2763{
a8dea12f
JM		 2764 ppcemb_tlb_t *tlb;
2765 int size;
76a66253
JM		 2766
2767 T0 &= 0x3F;
a8dea12f
JM		 2768 tlb = &env->tlb[T0].tlbe;
2769 T0 = tlb->EPN;
2770 if (tlb->prot & PAGE_VALID)
2771 T0 |= 0x400;
2772 size = booke_page_size_to_tlb(tlb->size);
2773 if (size < 0 || size > 0x7)
2774 size = 1;
2775 T0 |= size << 7;
2776 env->spr[SPR_40x_PID] = tlb->PID;
76a66253
JM		 2777}
2778
2779void do_4xx_tlbre_hi (void)
2780{
a8dea12f 2781 ppcemb_tlb_t *tlb;
76a66253
JM		 2782
2783 T0 &= 0x3F;
a8dea12f
JM		 2784 tlb = &env->tlb[T0].tlbe;
2785 T0 = tlb->RPN;
2786 if (tlb->prot & PAGE_EXEC)
2787 T0 |= 0x200;
2788 if (tlb->prot & PAGE_WRITE)
2789 T0 |= 0x100;
76a66253
JM		 2790}
2791
c55e9aef 2792void do_4xx_tlbwe_hi (void)
76a66253 2793{
a8dea12f 2794 ppcemb_tlb_t *tlb;
76a66253
JM		 2795 target_ulong page, end;
2796
c55e9aef 2797#if defined (DEBUG_SOFTWARE_TLB)
6b80055d 2798 if (loglevel != 0) {
6b542af7 2799 fprintf(logfile, "%s T0 " TDX " T1 " TDX "\n", __func__, T0, T1);
c55e9aef
JM		 2800 }
2801#endif
76a66253 2802 T0 &= 0x3F;
a8dea12f 2803 tlb = &env->tlb[T0].tlbe;
76a66253
JM		 2804 /* Invalidate previous TLB (if it's valid) */
2805 if (tlb->prot & PAGE_VALID) {
2806 end = tlb->EPN + tlb->size;
c55e9aef 2807#if defined (DEBUG_SOFTWARE_TLB)
6b80055d 2808 if (loglevel != 0) {
c55e9aef
JM		 2809 fprintf(logfile, "%s: invalidate old TLB %d start " ADDRX
2810 " end " ADDRX "\n", __func__, (int)T0, tlb->EPN, end);
2811 }
2812#endif
76a66253
JM		 2813 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2814 tlb_flush_page(env, page);
2815 }
a8dea12f 2816 tlb->size = booke_tlb_to_page_size((T1 >> 7) & 0x7);
c294fc58
JM		 2817 /* We cannot handle TLB size < TARGET_PAGE_SIZE.
2818 * If this ever occurs, one should use the ppcemb target instead
2819 * of the ppc or ppc64 one
2820 */
2821 if ((T1 & 0x40) && tlb->size < TARGET_PAGE_SIZE) {
71c8b8fd
JM		 2822 cpu_abort(env, "TLB size " TARGET_FMT_lu " < %u "
2823 "are not supported (%d)\n",
c294fc58
JM		 2824 tlb->size, TARGET_PAGE_SIZE, (int)((T1 >> 7) & 0x7));
2825 }
a750fc0b 2826 tlb->EPN = T1 & ~(tlb->size - 1);
c55e9aef 2827 if (T1 & 0x40)
76a66253
JM		 2828 tlb->prot |= PAGE_VALID;
2829 else
2830 tlb->prot &= ~PAGE_VALID;
c294fc58
JM		 2831 if (T1 & 0x20) {
2832 /* XXX: TO BE FIXED */
2833 cpu_abort(env, "Little-endian TLB entries are not supported by now\n");
2834 }
c55e9aef 2835 tlb->PID = env->spr[SPR_40x_PID]; /* PID */
a8dea12f 2836 tlb->attr = T1 & 0xFF;
c55e9aef 2837#if defined (DEBUG_SOFTWARE_TLB)
c294fc58
JM		 2838 if (loglevel != 0) {
2839 fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
c55e9aef 2840 " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
5fafdf24 2841 (int)T0, tlb->RPN, tlb->EPN, tlb->size,
c55e9aef
JM		 2842 tlb->prot & PAGE_READ ? 'r' : '-',
2843 tlb->prot & PAGE_WRITE ? 'w' : '-',
2844 tlb->prot & PAGE_EXEC ? 'x' : '-',
2845 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
2846 }
2847#endif
76a66253
JM		 2848 /* Invalidate new TLB (if valid) */
2849 if (tlb->prot & PAGE_VALID) {
2850 end = tlb->EPN + tlb->size;
c55e9aef 2851#if defined (DEBUG_SOFTWARE_TLB)
6b80055d 2852 if (loglevel != 0) {
c55e9aef
JM		 2853 fprintf(logfile, "%s: invalidate TLB %d start " ADDRX
2854 " end " ADDRX "\n", __func__, (int)T0, tlb->EPN, end);
2855 }
2856#endif
76a66253
JM		 2857 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2858 tlb_flush_page(env, page);
2859 }
76a66253
JM		 2860}
2861
c55e9aef 2862void do_4xx_tlbwe_lo (void)
76a66253 2863{
a8dea12f 2864 ppcemb_tlb_t *tlb;
76a66253 2865
c55e9aef 2866#if defined (DEBUG_SOFTWARE_TLB)
6b80055d 2867 if (loglevel != 0) {
6b542af7 2868 fprintf(logfile, "%s T0 " TDX " T1 " TDX "\n", __func__, T0, T1);
c55e9aef
JM		 2869 }
2870#endif
76a66253 2871 T0 &= 0x3F;
a8dea12f 2872 tlb = &env->tlb[T0].tlbe;
76a66253
JM		 2873 tlb->RPN = T1 & 0xFFFFFC00;
2874 tlb->prot = PAGE_READ;
2875 if (T1 & 0x200)
2876 tlb->prot |= PAGE_EXEC;
2877 if (T1 & 0x100)
2878 tlb->prot |= PAGE_WRITE;
c55e9aef 2879#if defined (DEBUG_SOFTWARE_TLB)
6b80055d
JM		 2880 if (loglevel != 0) {
2881 fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
c55e9aef 2882 " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
5fafdf24 2883 (int)T0, tlb->RPN, tlb->EPN, tlb->size,
c55e9aef
JM		 2884 tlb->prot & PAGE_READ ? 'r' : '-',
2885 tlb->prot & PAGE_WRITE ? 'w' : '-',
2886 tlb->prot & PAGE_EXEC ? 'x' : '-',
2887 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
2888 }
2889#endif
76a66253 2890}
5eb7995e 2891
a4bb6c3e
JM		 2892/* PowerPC 440 TLB management */
2893void do_440_tlbwe (int word)
5eb7995e
JM		 2894{
2895 ppcemb_tlb_t *tlb;
a4bb6c3e 2896 target_ulong EPN, RPN, size;
5eb7995e
JM		 2897 int do_flush_tlbs;
2898
2899#if defined (DEBUG_SOFTWARE_TLB)
2900 if (loglevel != 0) {
6b542af7 2901 fprintf(logfile, "%s word %d T0 " TDX " T1 " TDX "\n",
69facb78 2902 __func__, word, T0, T1);
5eb7995e
JM		 2903 }
2904#endif
2905 do_flush_tlbs = 0;
2906 T0 &= 0x3F;
2907 tlb = &env->tlb[T0].tlbe;
a4bb6c3e
JM		 2908 switch (word) {
2909 default:
2910 /* Just here to please gcc */
2911 case 0:
2912 EPN = T1 & 0xFFFFFC00;
2913 if ((tlb->prot & PAGE_VALID) && EPN != tlb->EPN)
5eb7995e 2914 do_flush_tlbs = 1;
a4bb6c3e
JM		 2915 tlb->EPN = EPN;
2916 size = booke_tlb_to_page_size((T1 >> 4) & 0xF);
2917 if ((tlb->prot & PAGE_VALID) && tlb->size < size)
2918 do_flush_tlbs = 1;
2919 tlb->size = size;
2920 tlb->attr &= ~0x1;
2921 tlb->attr |= (T1 >> 8) & 1;
2922 if (T1 & 0x200) {
2923 tlb->prot |= PAGE_VALID;
2924 } else {
2925 if (tlb->prot & PAGE_VALID) {
2926 tlb->prot &= ~PAGE_VALID;
2927 do_flush_tlbs = 1;
2928 }
5eb7995e 2929 }
a4bb6c3e
JM		 2930 tlb->PID = env->spr[SPR_440_MMUCR] & 0x000000FF;
2931 if (do_flush_tlbs)
2932 tlb_flush(env, 1);
2933 break;
2934 case 1:
2935 RPN = T1 & 0xFFFFFC0F;
2936 if ((tlb->prot & PAGE_VALID) && tlb->RPN != RPN)
2937 tlb_flush(env, 1);
2938 tlb->RPN = RPN;
2939 break;
2940 case 2:
2941 tlb->attr = (tlb->attr & 0x1) | (T1 & 0x0000FF00);
2942 tlb->prot = tlb->prot & PAGE_VALID;
2943 if (T1 & 0x1)
2944 tlb->prot |= PAGE_READ << 4;
2945 if (T1 & 0x2)
2946 tlb->prot |= PAGE_WRITE << 4;
2947 if (T1 & 0x4)
2948 tlb->prot |= PAGE_EXEC << 4;
2949 if (T1 & 0x8)
2950 tlb->prot |= PAGE_READ;
2951 if (T1 & 0x10)
2952 tlb->prot |= PAGE_WRITE;
2953 if (T1 & 0x20)
2954 tlb->prot |= PAGE_EXEC;
2955 break;
5eb7995e 2956 }
5eb7995e
JM		 2957}
2958
a4bb6c3e 2959void do_440_tlbre (int word)
5eb7995e
JM		 2960{
2961 ppcemb_tlb_t *tlb;
2962 int size;
2963
2964 T0 &= 0x3F;
2965 tlb = &env->tlb[T0].tlbe;
a4bb6c3e
JM		 2966 switch (word) {
2967 default:
2968 /* Just here to please gcc */
2969 case 0:
2970 T0 = tlb->EPN;
2971 size = booke_page_size_to_tlb(tlb->size);
2972 if (size < 0 || size > 0xF)
2973 size = 1;
2974 T0 |= size << 4;
2975 if (tlb->attr & 0x1)
2976 T0 |= 0x100;
2977 if (tlb->prot & PAGE_VALID)
2978 T0 |= 0x200;
2979 env->spr[SPR_440_MMUCR] &= ~0x000000FF;
2980 env->spr[SPR_440_MMUCR] |= tlb->PID;
2981 break;
2982 case 1:
2983 T0 = tlb->RPN;
2984 break;
2985 case 2:
2986 T0 = tlb->attr & ~0x1;
2987 if (tlb->prot & (PAGE_READ << 4))
2988 T0 |= 0x1;
2989 if (tlb->prot & (PAGE_WRITE << 4))
2990 T0 |= 0x2;
2991 if (tlb->prot & (PAGE_EXEC << 4))
2992 T0 |= 0x4;
2993 if (tlb->prot & PAGE_READ)
2994 T0 |= 0x8;
2995 if (tlb->prot & PAGE_WRITE)
2996 T0 |= 0x10;
2997 if (tlb->prot & PAGE_EXEC)
2998 T0 |= 0x20;
2999 break;
3000 }
5eb7995e 3001}
76a66253 3002#endif /* !CONFIG_USER_ONLY */
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