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Optimize PowerPC overflow flag computation in most useful cases.
[qemu.git] / target-ppc / op_helper.c
CommitLineData
9a64fbe4 1/*
3fc6c082 2 * PowerPC emulation helpers for qemu.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
9a64fbe4
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
9a64fbe4 20#include "exec.h"
603fccce 21#include "host-utils.h"
9a64fbe4 22
0411a972 23#include "helper_regs.h"
0487d6a8
JM		 24#include "op_helper.h"
25
9a64fbe4 26#define MEMSUFFIX _raw
0487d6a8 27#include "op_helper.h"
9a64fbe4 28#include "op_helper_mem.h"
a541f297 29#if !defined(CONFIG_USER_ONLY)
9a64fbe4 30#define MEMSUFFIX _user
0487d6a8 31#include "op_helper.h"
9a64fbe4
FB		 32#include "op_helper_mem.h"
33#define MEMSUFFIX _kernel
0487d6a8 34#include "op_helper.h"
9a64fbe4 35#include "op_helper_mem.h"
1e42b8f0
JM		 36#if defined(TARGET_PPC64H)
37#define MEMSUFFIX _hypv
38#include "op_helper.h"
39#include "op_helper_mem.h"
40#endif
9a64fbe4
FB		 41#endif
42
fdabc366
FB		 43//#define DEBUG_OP
44//#define DEBUG_EXCEPTIONS
76a66253 45//#define DEBUG_SOFTWARE_TLB
fdabc366 46
9a64fbe4
FB		 47/*****************************************************************************/
48/* Exceptions processing helpers */
9a64fbe4 49
9fddaa0c 50void do_raise_exception_err (uint32_t exception, int error_code)
9a64fbe4 51{
9fddaa0c
FB		 52#if 0
53 printf("Raise exception %3x code : %d\n", exception, error_code);
54#endif
9fddaa0c
FB		 55 env->exception_index = exception;
56 env->error_code = error_code;
76a66253
JM		 57 cpu_loop_exit();
58}
9fddaa0c
FB		 59
60void do_raise_exception (uint32_t exception)
61{
62 do_raise_exception_err(exception, 0);
9a64fbe4
FB		 63}
64
a496775f
JM		 65void cpu_dump_EA (target_ulong EA);
66void do_print_mem_EA (target_ulong EA)
67{
68 cpu_dump_EA(EA);
69}
70
76a66253
JM		 71/*****************************************************************************/
72/* Registers load and stores */
73void do_load_cr (void)
74{
75 T0 = (env->crf[0] << 28) |
76 (env->crf[1] << 24) |
77 (env->crf[2] << 20) |
78 (env->crf[3] << 16) |
79 (env->crf[4] << 12) |
80 (env->crf[5] << 8) |
81 (env->crf[6] << 4) |
82 (env->crf[7] << 0);
83}
84
85void do_store_cr (uint32_t mask)
86{
87 int i, sh;
88
36081602 89 for (i = 0, sh = 7; i < 8; i++, sh--) {
76a66253
JM		 90 if (mask & (1 << sh))
91 env->crf[i] = (T0 >> (sh * 4)) & 0xFUL;
92 }
93}
94
c80f84e3
JM		 95#if defined(TARGET_PPC64)
96void do_store_pri (int prio)
97{
98 env->spr[SPR_PPR] &= ~0x001C000000000000ULL;
99 env->spr[SPR_PPR] |= ((uint64_t)prio & 0x7) << 50;
100}
101#endif
102
a496775f
JM		 103target_ulong ppc_load_dump_spr (int sprn)
104{
6b80055d 105 if (loglevel != 0) {
a496775f
JM		 106 fprintf(logfile, "Read SPR %d %03x => " ADDRX "\n",
107 sprn, sprn, env->spr[sprn]);
108 }
109
110 return env->spr[sprn];
111}
112
113void ppc_store_dump_spr (int sprn, target_ulong val)
114{
6b80055d 115 if (loglevel != 0) {
a496775f
JM		 116 fprintf(logfile, "Write SPR %d %03x => " ADDRX " <= " ADDRX "\n",
117 sprn, sprn, env->spr[sprn], val);
118 }
119 env->spr[sprn] = val;
120}
121
9a64fbe4 122/*****************************************************************************/
fdabc366 123/* Fixed point operations helpers */
fdabc366
FB		 124void do_adde (void)
125{
126 T2 = T0;
127 T0 += T1 + xer_ca;
d9bce9d9
JM		 128 if (likely(!((uint32_t)T0 < (uint32_t)T2 ||
129 (xer_ca == 1 && (uint32_t)T0 == (uint32_t)T2)))) {
fdabc366
FB		 130 xer_ca = 0;
131 } else {
132 xer_ca = 1;
133 }
134}
135
d9bce9d9
JM		 136#if defined(TARGET_PPC64)
137void do_adde_64 (void)
fdabc366
FB		 138{
139 T2 = T0;
140 T0 += T1 + xer_ca;
d9bce9d9
JM		 141 if (likely(!((uint64_t)T0 < (uint64_t)T2 ||
142 (xer_ca == 1 && (uint64_t)T0 == (uint64_t)T2)))) {
fdabc366
FB		 143 xer_ca = 0;
144 } else {
145 xer_ca = 1;
146 }
fdabc366 147}
d9bce9d9 148#endif
fdabc366
FB		 149
150void do_addmeo (void)
151{
152 T1 = T0;
153 T0 += xer_ca + (-1);
c3e10c7b
JM		 154 xer_ov = ((uint32_t)T1 & ((uint32_t)T1 ^ (uint32_t)T0)) >> 31;
155 xer_so |= xer_ov;
fdabc366
FB		 156 if (likely(T1 != 0))
157 xer_ca = 1;
c3e10c7b
JM		 158 else
159 xer_ca = 0;
fdabc366
FB		 160}
161
d9bce9d9
JM		 162#if defined(TARGET_PPC64)
163void do_addmeo_64 (void)
fdabc366
FB		 164{
165 T1 = T0;
d9bce9d9 166 T0 += xer_ca + (-1);
c3e10c7b
JM		 167 xer_ov = ((uint64_t)T1 & ((uint64_t)T1 ^ (uint64_t)T0)) >> 63;
168 xer_so |= xer_ov;
d9bce9d9 169 if (likely(T1 != 0))
fdabc366 170 xer_ca = 1;
c3e10c7b
JM		 171 else
172 xer_ca = 0;
fdabc366 173}
d9bce9d9 174#endif
fdabc366
FB		 175
176void do_divwo (void)
177{
d9bce9d9
JM		 178 if (likely(!(((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) ||
179 (int32_t)T1 == 0))) {
fdabc366 180 xer_ov = 0;
d9bce9d9 181 T0 = (int32_t)T0 / (int32_t)T1;
fdabc366 182 } else {
fdabc366 183 xer_ov = 1;
966439a6 184 xer_so = 1;
fdabc366
FB		 185 T0 = (-1) * ((uint32_t)T0 >> 31);
186 }
187}
188
d9bce9d9
JM		 189#if defined(TARGET_PPC64)
190void do_divdo (void)
191{
192 if (likely(!(((int64_t)T0 == INT64_MIN && (int64_t)T1 == -1ULL) ||
193 (int64_t)T1 == 0))) {
194 xer_ov = 0;
195 T0 = (int64_t)T0 / (int64_t)T1;
196 } else {
d9bce9d9 197 xer_ov = 1;
966439a6 198 xer_so = 1;
d9bce9d9
JM		 199 T0 = (-1ULL) * ((uint64_t)T0 >> 63);
200 }
201}
202#endif
203
fdabc366
FB		 204void do_divwuo (void)
205{
206 if (likely((uint32_t)T1 != 0)) {
207 xer_ov = 0;
208 T0 = (uint32_t)T0 / (uint32_t)T1;
209 } else {
fdabc366 210 xer_ov = 1;
966439a6 211 xer_so = 1;
fdabc366
FB		 212 T0 = 0;
213 }
214}
215
d9bce9d9
JM		 216#if defined(TARGET_PPC64)
217void do_divduo (void)
218{
219 if (likely((uint64_t)T1 != 0)) {
220 xer_ov = 0;
221 T0 = (uint64_t)T0 / (uint64_t)T1;
222 } else {
d9bce9d9 223 xer_ov = 1;
966439a6 224 xer_so = 1;
d9bce9d9
JM		 225 T0 = 0;
226 }
227}
228#endif
229
fdabc366
FB		 230void do_mullwo (void)
231{
d9bce9d9 232 int64_t res = (int64_t)T0 * (int64_t)T1;
fdabc366
FB		 233
234 if (likely((int32_t)res == res)) {
235 xer_ov = 0;
236 } else {
237 xer_ov = 1;
238 xer_so = 1;
239 }
240 T0 = (int32_t)res;
241}
242
d9bce9d9
JM		 243#if defined(TARGET_PPC64)
244void do_mulldo (void)
fdabc366 245{
d9bce9d9
JM		 246 int64_t th;
247 uint64_t tl;
248
9d901a20 249 muls64(&tl, &th, T0, T1);
88ad920b
JM		 250 /* If th != 0 && th != -1, then we had an overflow */
251 if (likely((th + 1) <= 1)) {
fdabc366 252 xer_ov = 0;
fdabc366
FB		 253 } else {
254 xer_ov = 1;
255 xer_so = 1;
256 }
d9bce9d9 257 T0 = (int64_t)tl;
fdabc366 258}
d9bce9d9 259#endif
fdabc366 260
d9bce9d9 261void do_nego (void)
fdabc366 262{
d9bce9d9 263 if (likely((int32_t)T0 != INT32_MIN)) {
fdabc366 264 xer_ov = 0;
d9bce9d9 265 T0 = -(int32_t)T0;
fdabc366 266 } else {
fdabc366 267 xer_ov = 1;
d9bce9d9 268 xer_so = 1;
fdabc366 269 }
fdabc366
FB		 270}
271
d9bce9d9
JM		 272#if defined(TARGET_PPC64)
273void do_nego_64 (void)
fdabc366 274{
d9bce9d9 275 if (likely((int64_t)T0 != INT64_MIN)) {
fdabc366 276 xer_ov = 0;
d9bce9d9 277 T0 = -(int64_t)T0;
fdabc366 278 } else {
fdabc366 279 xer_ov = 1;
d9bce9d9 280 xer_so = 1;
fdabc366
FB		 281 }
282}
d9bce9d9 283#endif
fdabc366
FB		 284
285void do_subfe (void)
286{
287 T0 = T1 + ~T0 + xer_ca;
d9bce9d9
JM		 288 if (likely((uint32_t)T0 >= (uint32_t)T1 &&
289 (xer_ca == 0 || (uint32_t)T0 != (uint32_t)T1))) {
fdabc366
FB		 290 xer_ca = 0;
291 } else {
292 xer_ca = 1;
293 }
294}
295
d9bce9d9
JM		 296#if defined(TARGET_PPC64)
297void do_subfe_64 (void)
fdabc366 298{
fdabc366 299 T0 = T1 + ~T0 + xer_ca;
d9bce9d9
JM		 300 if (likely((uint64_t)T0 >= (uint64_t)T1 &&
301 (xer_ca == 0 || (uint64_t)T0 != (uint64_t)T1))) {
302 xer_ca = 0;
303 } else {
304 xer_ca = 1;
305 }
306}
307#endif
308
309void do_subfmeo (void)
310{
311 T1 = T0;
312 T0 = ~T0 + xer_ca - 1;
c3e10c7b
JM		 313 xer_ov = ((uint32_t)~T1 & ((uint32_t)~T1 ^ (uint32_t)T0)) >> 31;
314 xer_so |= xer_ov;
d9bce9d9 315 if (likely((uint32_t)T1 != UINT32_MAX))
fdabc366 316 xer_ca = 1;
c3e10c7b
JM		 317 else
318 xer_ca = 0;
fdabc366
FB		 319}
320
d9bce9d9
JM		 321#if defined(TARGET_PPC64)
322void do_subfmeo_64 (void)
fdabc366
FB		 323{
324 T1 = T0;
325 T0 = ~T0 + xer_ca - 1;
c3e10c7b
JM		 326 xer_ov = ((uint64_t)~T1 & ((uint64_t)~T1 ^ (uint64_t)T0)) >> 63;
327 xer_so |= xer_ov;
d9bce9d9 328 if (likely((uint64_t)T1 != UINT64_MAX))
fdabc366 329 xer_ca = 1;
c3e10c7b
JM		 330 else
331 xer_ca = 0;
fdabc366 332}
d9bce9d9 333#endif
fdabc366
FB		 334
335void do_subfzeo (void)
336{
337 T1 = T0;
338 T0 = ~T0 + xer_ca;
c3e10c7b
JM		 339 xer_ov = (((uint32_t)~T1 ^ UINT32_MAX) &
340 ((uint32_t)(~T1) ^ (uint32_t)T0)) >> 31;
341 xer_so |= xer_ov;
d9bce9d9 342 if (likely((uint32_t)T0 >= (uint32_t)~T1)) {
fdabc366
FB		 343 xer_ca = 0;
344 } else {
345 xer_ca = 1;
346 }
347}
348
d9bce9d9
JM		 349#if defined(TARGET_PPC64)
350void do_subfzeo_64 (void)
351{
352 T1 = T0;
353 T0 = ~T0 + xer_ca;
c3e10c7b
JM		 354 xer_ov = (((uint64_t)~T1 ^ UINT64_MAX) &
355 ((uint64_t)(~T1) ^ (uint64_t)T0)) >> 63;
356 xer_so |= xer_ov;
d9bce9d9
JM		 357 if (likely((uint64_t)T0 >= (uint64_t)~T1)) {
358 xer_ca = 0;
359 } else {
360 xer_ca = 1;
361 }
362}
363#endif
364
603fccce
JM		 365void do_cntlzw (void)
366{
367 T0 = clz32(T0);
368}
369
370#if defined(TARGET_PPC64)
371void do_cntlzd (void)
372{
373 T0 = clz64(T0);
374}
375#endif
376
9a64fbe4
FB		 377/* shift right arithmetic helper */
378void do_sraw (void)
379{
380 int32_t ret;
381
fdabc366 382 if (likely(!(T1 & 0x20UL))) {
d9bce9d9 383 if (likely((uint32_t)T1 != 0)) {
fdabc366
FB		 384 ret = (int32_t)T0 >> (T1 & 0x1fUL);
385 if (likely(ret >= 0 || ((int32_t)T0 & ((1 << T1) - 1)) == 0)) {
76a66253 386 xer_ca = 0;
fdabc366 387 } else {
76a66253 388 xer_ca = 1;
fdabc366
FB		 389 }
390 } else {
76a66253 391 ret = T0;
fdabc366
FB		 392 xer_ca = 0;
393 }
394 } else {
395 ret = (-1) * ((uint32_t)T0 >> 31);
396 if (likely(ret >= 0 || ((uint32_t)T0 & ~0x80000000UL) == 0)) {
397 xer_ca = 0;
76a66253 398 } else {
9a64fbe4 399 xer_ca = 1;
76a66253 400 }
fdabc366 401 }
4b3686fa 402 T0 = ret;
9a64fbe4
FB		 403}
404
d9bce9d9
JM		 405#if defined(TARGET_PPC64)
406void do_srad (void)
407{
408 int64_t ret;
409
410 if (likely(!(T1 & 0x40UL))) {
411 if (likely((uint64_t)T1 != 0)) {
412 ret = (int64_t)T0 >> (T1 & 0x3FUL);
413 if (likely(ret >= 0 || ((int64_t)T0 & ((1 << T1) - 1)) == 0)) {
414 xer_ca = 0;
415 } else {
416 xer_ca = 1;
417 }
418 } else {
419 ret = T0;
420 xer_ca = 0;
421 }
422 } else {
423 ret = (-1) * ((uint64_t)T0 >> 63);
424 if (likely(ret >= 0 || ((uint64_t)T0 & ~0x8000000000000000ULL) == 0)) {
425 xer_ca = 0;
426 } else {
427 xer_ca = 1;
428 }
429 }
430 T0 = ret;
431}
432#endif
433
d9bce9d9
JM		 434void do_popcntb (void)
435{
436 uint32_t ret;
437 int i;
438
439 ret = 0;
440 for (i = 0; i < 32; i += 8)
603fccce 441 ret |= ctpop8((T0 >> i) & 0xFF) << i;
d9bce9d9
JM		 442 T0 = ret;
443}
444
445#if defined(TARGET_PPC64)
446void do_popcntb_64 (void)
447{
448 uint64_t ret;
449 int i;
450
451 ret = 0;
452 for (i = 0; i < 64; i += 8)
603fccce 453 ret |= ctpop8((T0 >> i) & 0xFF) << i;
d9bce9d9
JM		 454 T0 = ret;
455}
456#endif
457
fdabc366 458/*****************************************************************************/
9a64fbe4 459/* Floating point operations helpers */
a11b8151 460static always_inline int fpisneg (float64 f)
7c58044c
JM		 461{
462 union {
463 float64 f;
464 uint64_t u;
465 } u;
466
467 u.f = f;
468
469 return u.u >> 63 != 0;
470}
471
a11b8151 472static always_inline int isden (float f)
7c58044c
JM		 473{
474 union {
475 float64 f;
476 uint64_t u;
477 } u;
478
479 u.f = f;
480
481 return ((u.u >> 52) & 0x7FF) == 0;
482}
483
a11b8151 484static always_inline int iszero (float64 f)
7c58044c
JM		 485{
486 union {
487 float64 f;
488 uint64_t u;
489 } u;
490
491 u.f = f;
492
493 return (u.u & ~0x8000000000000000ULL) == 0;
494}
495
a11b8151 496static always_inline int isinfinity (float64 f)
7c58044c
JM		 497{
498 union {
499 float64 f;
500 uint64_t u;
501 } u;
502
503 u.f = f;
504
86c4a9f5 505 return ((u.u >> 52) & 0x7FF) == 0x7FF &&
7c58044c
JM		 506 (u.u & 0x000FFFFFFFFFFFFFULL) == 0;
507}
508
509void do_compute_fprf (int set_fprf)
510{
511 int isneg;
512
513 isneg = fpisneg(FT0);
514 if (unlikely(float64_is_nan(FT0))) {
515 if (float64_is_signaling_nan(FT0)) {
516 /* Signaling NaN: flags are undefined */
517 T0 = 0x00;
518 } else {
519 /* Quiet NaN */
520 T0 = 0x11;
521 }
522 } else if (unlikely(isinfinity(FT0))) {
523 /* +/- infinity */
524 if (isneg)
525 T0 = 0x09;
526 else
527 T0 = 0x05;
528 } else {
529 if (iszero(FT0)) {
530 /* +/- zero */
531 if (isneg)
532 T0 = 0x12;
533 else
534 T0 = 0x02;
535 } else {
536 if (isden(FT0)) {
537 /* Denormalized numbers */
538 T0 = 0x10;
539 } else {
540 /* Normalized numbers */
541 T0 = 0x00;
542 }
543 if (isneg) {
544 T0 |= 0x08;
545 } else {
546 T0 |= 0x04;
547 }
548 }
549 }
550 if (set_fprf) {
551 /* We update FPSCR_FPRF */
552 env->fpscr &= ~(0x1F << FPSCR_FPRF);
553 env->fpscr |= T0 << FPSCR_FPRF;
554 }
555 /* We just need fpcc to update Rc1 */
556 T0 &= 0xF;
557}
558
559/* Floating-point invalid operations exception */
560static always_inline void fload_invalid_op_excp (int op)
561{
562 int ve;
563
564 ve = fpscr_ve;
565 if (op & POWERPC_EXCP_FP_VXSNAN) {
566 /* Operation on signaling NaN */
567 env->fpscr |= 1 << FPSCR_VXSNAN;
568 }
569 if (op & POWERPC_EXCP_FP_VXSOFT) {
570 /* Software-defined condition */
571 env->fpscr |= 1 << FPSCR_VXSOFT;
572 }
573 switch (op & ~(POWERPC_EXCP_FP_VXSOFT | POWERPC_EXCP_FP_VXSNAN)) {
574 case POWERPC_EXCP_FP_VXISI:
575 /* Magnitude subtraction of infinities */
576 env->fpscr |= 1 << FPSCR_VXISI;
577 goto update_arith;
578 case POWERPC_EXCP_FP_VXIDI:
579 /* Division of infinity by infinity */
580 env->fpscr |= 1 << FPSCR_VXIDI;
581 goto update_arith;
582 case POWERPC_EXCP_FP_VXZDZ:
583 /* Division of zero by zero */
584 env->fpscr |= 1 << FPSCR_VXZDZ;
585 goto update_arith;
586 case POWERPC_EXCP_FP_VXIMZ:
587 /* Multiplication of zero by infinity */
588 env->fpscr |= 1 << FPSCR_VXIMZ;
589 goto update_arith;
590 case POWERPC_EXCP_FP_VXVC:
591 /* Ordered comparison of NaN */
592 env->fpscr |= 1 << FPSCR_VXVC;
593 env->fpscr &= ~(0xF << FPSCR_FPCC);
594 env->fpscr |= 0x11 << FPSCR_FPCC;
595 /* We must update the target FPR before raising the exception */
596 if (ve != 0) {
597 env->exception_index = POWERPC_EXCP_PROGRAM;
598 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC;
599 /* Update the floating-point enabled exception summary */
600 env->fpscr |= 1 << FPSCR_FEX;
601 /* Exception is differed */
602 ve = 0;
603 }
604 break;
605 case POWERPC_EXCP_FP_VXSQRT:
606 /* Square root of a negative number */
607 env->fpscr |= 1 << FPSCR_VXSQRT;
608 update_arith:
609 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
610 if (ve == 0) {
611 /* Set the result to quiet NaN */
612 FT0 = (uint64_t)-1;
613 env->fpscr &= ~(0xF << FPSCR_FPCC);
614 env->fpscr |= 0x11 << FPSCR_FPCC;
615 }
616 break;
617 case POWERPC_EXCP_FP_VXCVI:
618 /* Invalid conversion */
619 env->fpscr |= 1 << FPSCR_VXCVI;
620 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
621 if (ve == 0) {
622 /* Set the result to quiet NaN */
623 FT0 = (uint64_t)-1;
624 env->fpscr &= ~(0xF << FPSCR_FPCC);
625 env->fpscr |= 0x11 << FPSCR_FPCC;
626 }
627 break;
628 }
629 /* Update the floating-point invalid operation summary */
630 env->fpscr |= 1 << FPSCR_VX;
631 /* Update the floating-point exception summary */
632 env->fpscr |= 1 << FPSCR_FX;
633 if (ve != 0) {
634 /* Update the floating-point enabled exception summary */
635 env->fpscr |= 1 << FPSCR_FEX;
636 if (msr_fe0 != 0 || msr_fe1 != 0)
637 do_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_FP | op);
638 }
639}
640
641static always_inline void float_zero_divide_excp (void)
642{
643 union {
644 float64 f;
645 uint64_t u;
646 } u0, u1;
7c58044c
JM		 647
648 env->fpscr |= 1 << FPSCR_ZX;
649 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
650 /* Update the floating-point exception summary */
651 env->fpscr |= 1 << FPSCR_FX;
652 if (fpscr_ze != 0) {
653 /* Update the floating-point enabled exception summary */
654 env->fpscr |= 1 << FPSCR_FEX;
655 if (msr_fe0 != 0 || msr_fe1 != 0) {
656 do_raise_exception_err(POWERPC_EXCP_PROGRAM,
657 POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX);
658 }
659 } else {
660 /* Set the result to infinity */
661 u0.f = FT0;
662 u1.f = FT1;
663 u0.u = ((u0.u ^ u1.u) & 0x8000000000000000ULL);
86c4a9f5 664 u0.u |= 0x7FFULL << 52;
7c58044c
JM		 665 FT0 = u0.f;
666 }
667}
668
669static always_inline void float_overflow_excp (void)
670{
671 env->fpscr |= 1 << FPSCR_OX;
672 /* Update the floating-point exception summary */
673 env->fpscr |= 1 << FPSCR_FX;
674 if (fpscr_oe != 0) {
675 /* XXX: should adjust the result */
676 /* Update the floating-point enabled exception summary */
677 env->fpscr |= 1 << FPSCR_FEX;
678 /* We must update the target FPR before raising the exception */
679 env->exception_index = POWERPC_EXCP_PROGRAM;
680 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
681 } else {
682 env->fpscr |= 1 << FPSCR_XX;
683 env->fpscr |= 1 << FPSCR_FI;
684 }
685}
686
687static always_inline void float_underflow_excp (void)
688{
689 env->fpscr |= 1 << FPSCR_UX;
690 /* Update the floating-point exception summary */
691 env->fpscr |= 1 << FPSCR_FX;
692 if (fpscr_ue != 0) {
693 /* XXX: should adjust the result */
694 /* Update the floating-point enabled exception summary */
695 env->fpscr |= 1 << FPSCR_FEX;
696 /* We must update the target FPR before raising the exception */
697 env->exception_index = POWERPC_EXCP_PROGRAM;
698 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
699 }
700}
701
702static always_inline void float_inexact_excp (void)
703{
704 env->fpscr |= 1 << FPSCR_XX;
705 /* Update the floating-point exception summary */
706 env->fpscr |= 1 << FPSCR_FX;
707 if (fpscr_xe != 0) {
708 /* Update the floating-point enabled exception summary */
709 env->fpscr |= 1 << FPSCR_FEX;
710 /* We must update the target FPR before raising the exception */
711 env->exception_index = POWERPC_EXCP_PROGRAM;
712 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
713 }
714}
715
716static always_inline void fpscr_set_rounding_mode (void)
717{
718 int rnd_type;
719
720 /* Set rounding mode */
721 switch (fpscr_rn) {
722 case 0:
723 /* Best approximation (round to nearest) */
724 rnd_type = float_round_nearest_even;
725 break;
726 case 1:
727 /* Smaller magnitude (round toward zero) */
728 rnd_type = float_round_to_zero;
729 break;
730 case 2:
731 /* Round toward +infinite */
732 rnd_type = float_round_up;
733 break;
734 default:
735 case 3:
736 /* Round toward -infinite */
737 rnd_type = float_round_down;
738 break;
739 }
740 set_float_rounding_mode(rnd_type, &env->fp_status);
741}
742
743void do_fpscr_setbit (int bit)
744{
745 int prev;
746
747 prev = (env->fpscr >> bit) & 1;
748 env->fpscr |= 1 << bit;
749 if (prev == 0) {
750 switch (bit) {
751 case FPSCR_VX:
752 env->fpscr |= 1 << FPSCR_FX;
753 if (fpscr_ve)
754 goto raise_ve;
755 case FPSCR_OX:
756 env->fpscr |= 1 << FPSCR_FX;
757 if (fpscr_oe)
758 goto raise_oe;
759 break;
760 case FPSCR_UX:
761 env->fpscr |= 1 << FPSCR_FX;
762 if (fpscr_ue)
763 goto raise_ue;
764 break;
765 case FPSCR_ZX:
766 env->fpscr |= 1 << FPSCR_FX;
767 if (fpscr_ze)
768 goto raise_ze;
769 break;
770 case FPSCR_XX:
771 env->fpscr |= 1 << FPSCR_FX;
772 if (fpscr_xe)
773 goto raise_xe;
774 break;
775 case FPSCR_VXSNAN:
776 case FPSCR_VXISI:
777 case FPSCR_VXIDI:
778 case FPSCR_VXZDZ:
779 case FPSCR_VXIMZ:
780 case FPSCR_VXVC:
781 case FPSCR_VXSOFT:
782 case FPSCR_VXSQRT:
783 case FPSCR_VXCVI:
784 env->fpscr |= 1 << FPSCR_VX;
785 env->fpscr |= 1 << FPSCR_FX;
786 if (fpscr_ve != 0)
787 goto raise_ve;
788 break;
789 case FPSCR_VE:
790 if (fpscr_vx != 0) {
791 raise_ve:
792 env->error_code = POWERPC_EXCP_FP;
793 if (fpscr_vxsnan)
794 env->error_code |= POWERPC_EXCP_FP_VXSNAN;
795 if (fpscr_vxisi)
796 env->error_code |= POWERPC_EXCP_FP_VXISI;
797 if (fpscr_vxidi)
798 env->error_code |= POWERPC_EXCP_FP_VXIDI;
799 if (fpscr_vxzdz)
800 env->error_code |= POWERPC_EXCP_FP_VXZDZ;
801 if (fpscr_vximz)
802 env->error_code |= POWERPC_EXCP_FP_VXIMZ;
803 if (fpscr_vxvc)
804 env->error_code |= POWERPC_EXCP_FP_VXVC;
805 if (fpscr_vxsoft)
806 env->error_code |= POWERPC_EXCP_FP_VXSOFT;
807 if (fpscr_vxsqrt)
808 env->error_code |= POWERPC_EXCP_FP_VXSQRT;
809 if (fpscr_vxcvi)
810 env->error_code |= POWERPC_EXCP_FP_VXCVI;
811 goto raise_excp;
812 }
813 break;
814 case FPSCR_OE:
815 if (fpscr_ox != 0) {
816 raise_oe:
817 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
818 goto raise_excp;
819 }
820 break;
821 case FPSCR_UE:
822 if (fpscr_ux != 0) {
823 raise_ue:
824 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
825 goto raise_excp;
826 }
827 break;
828 case FPSCR_ZE:
829 if (fpscr_zx != 0) {
830 raise_ze:
831 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX;
832 goto raise_excp;
833 }
834 break;
835 case FPSCR_XE:
836 if (fpscr_xx != 0) {
837 raise_xe:
838 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
839 goto raise_excp;
840 }
841 break;
842 case FPSCR_RN1:
843 case FPSCR_RN:
844 fpscr_set_rounding_mode();
845 break;
846 default:
847 break;
848 raise_excp:
849 /* Update the floating-point enabled exception summary */
850 env->fpscr |= 1 << FPSCR_FEX;
851 /* We have to update Rc1 before raising the exception */
852 env->exception_index = POWERPC_EXCP_PROGRAM;
853 break;
854 }
855 }
856}
857
858#if defined(WORDS_BIGENDIAN)
859#define WORD0 0
860#define WORD1 1
861#else
862#define WORD0 1
863#define WORD1 0
864#endif
865void do_store_fpscr (uint32_t mask)
866{
867 /*
868 * We use only the 32 LSB of the incoming fpr
869 */
870 union {
871 double d;
872 struct {
873 uint32_t u[2];
874 } s;
875 } u;
876 uint32_t prev, new;
877 int i;
878
879 u.d = FT0;
880 prev = env->fpscr;
881 new = u.s.u[WORD1];
882 new &= ~0x90000000;
883 new |= prev & 0x90000000;
884 for (i = 0; i < 7; i++) {
885 if (mask & (1 << i)) {
886 env->fpscr &= ~(0xF << (4 * i));
887 env->fpscr |= new & (0xF << (4 * i));
888 }
889 }
890 /* Update VX and FEX */
891 if (fpscr_ix != 0)
892 env->fpscr |= 1 << FPSCR_VX;
893 if ((fpscr_ex & fpscr_eex) != 0) {
894 env->fpscr |= 1 << FPSCR_FEX;
895 env->exception_index = POWERPC_EXCP_PROGRAM;
896 /* XXX: we should compute it properly */
897 env->error_code = POWERPC_EXCP_FP;
898 }
899 fpscr_set_rounding_mode();
900}
901#undef WORD0
902#undef WORD1
903
904#ifdef CONFIG_SOFTFLOAT
905void do_float_check_status (void)
906{
907 if (env->exception_index == POWERPC_EXCP_PROGRAM &&
908 (env->error_code & POWERPC_EXCP_FP)) {
909 /* Differred floating-point exception after target FPR update */
910 if (msr_fe0 != 0 || msr_fe1 != 0)
911 do_raise_exception_err(env->exception_index, env->error_code);
912 } else if (env->fp_status.float_exception_flags & float_flag_overflow) {
913 float_overflow_excp();
914 } else if (env->fp_status.float_exception_flags & float_flag_underflow) {
915 float_underflow_excp();
916 } else if (env->fp_status.float_exception_flags & float_flag_inexact) {
917 float_inexact_excp();
918 }
919}
920#endif
921
922#if USE_PRECISE_EMULATION
923void do_fadd (void)
924{
925 if (unlikely(float64_is_signaling_nan(FT0) ||
926 float64_is_signaling_nan(FT1))) {
927 /* sNaN addition */
928 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
929 } else if (likely(isfinite(FT0) || isfinite(FT1) ||
930 fpisneg(FT0) == fpisneg(FT1))) {
931 FT0 = float64_add(FT0, FT1, &env->fp_status);
932 } else {
933 /* Magnitude subtraction of infinities */
934 fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
935 }
936}
937
938void do_fsub (void)
939{
940 if (unlikely(float64_is_signaling_nan(FT0) ||
941 float64_is_signaling_nan(FT1))) {
942 /* sNaN subtraction */
943 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
944 } else if (likely(isfinite(FT0) || isfinite(FT1) ||
945 fpisneg(FT0) != fpisneg(FT1))) {
946 FT0 = float64_sub(FT0, FT1, &env->fp_status);
947 } else {
948 /* Magnitude subtraction of infinities */
949 fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
950 }
951}
952
953void do_fmul (void)
954{
955 if (unlikely(float64_is_signaling_nan(FT0) ||
956 float64_is_signaling_nan(FT1))) {
957 /* sNaN multiplication */
958 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
5bda2843
JM		 959 } else if (unlikely((isinfinity(FT0) && iszero(FT1)) ||
960 (iszero(FT0) && isinfinity(FT1)))) {
7c58044c
JM		 961 /* Multiplication of zero by infinity */
962 fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
963 } else {
964 FT0 = float64_mul(FT0, FT1, &env->fp_status);
965 }
966}
967
968void do_fdiv (void)
969{
970 if (unlikely(float64_is_signaling_nan(FT0) ||
971 float64_is_signaling_nan(FT1))) {
972 /* sNaN division */
973 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
974 } else if (unlikely(isinfinity(FT0) && isinfinity(FT1))) {
975 /* Division of infinity by infinity */
976 fload_invalid_op_excp(POWERPC_EXCP_FP_VXIDI);
977 } else if (unlikely(iszero(FT1))) {
978 if (iszero(FT0)) {
979 /* Division of zero by zero */
980 fload_invalid_op_excp(POWERPC_EXCP_FP_VXZDZ);
981 } else {
982 /* Division by zero */
983 float_zero_divide_excp();
984 }
985 } else {
986 FT0 = float64_div(FT0, FT1, &env->fp_status);
987 }
988}
989#endif /* USE_PRECISE_EMULATION */
990
9a64fbe4
FB		 991void do_fctiw (void)
992{
993 union {
994 double d;
995 uint64_t i;
4ecc3190 996 } p;
9a64fbe4 997
7c58044c
JM		 998 if (unlikely(float64_is_signaling_nan(FT0))) {
999 /* sNaN conversion */
1000 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1001 } else if (unlikely(float64_is_nan(FT0) || isinfinity(FT0))) {
1002 /* qNan / infinity conversion */
1003 fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1004 } else {
1005 p.i = float64_to_int32(FT0, &env->fp_status);
e864cabd 1006#if USE_PRECISE_EMULATION
7c58044c
JM		 1007 /* XXX: higher bits are not supposed to be significant.
1008 * to make tests easier, return the same as a real PowerPC 750
1009 */
1010 p.i |= 0xFFF80000ULL << 32;
e864cabd 1011#endif
7c58044c
JM		 1012 FT0 = p.d;
1013 }
9a64fbe4
FB		 1014}
1015
1016void do_fctiwz (void)
1017{
1018 union {
1019 double d;
1020 uint64_t i;
4ecc3190
FB		 1021 } p;
1022
7c58044c
JM		 1023 if (unlikely(float64_is_signaling_nan(FT0))) {
1024 /* sNaN conversion */
1025 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1026 } else if (unlikely(float64_is_nan(FT0) || isinfinity(FT0))) {
1027 /* qNan / infinity conversion */
1028 fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1029 } else {
1030 p.i = float64_to_int32_round_to_zero(FT0, &env->fp_status);
e864cabd 1031#if USE_PRECISE_EMULATION
7c58044c
JM		 1032 /* XXX: higher bits are not supposed to be significant.
1033 * to make tests easier, return the same as a real PowerPC 750
1034 */
1035 p.i |= 0xFFF80000ULL << 32;
e864cabd 1036#endif
7c58044c
JM		 1037 FT0 = p.d;
1038 }
9a64fbe4
FB		 1039}
1040
426613db
JM		 1041#if defined(TARGET_PPC64)
1042void do_fcfid (void)
1043{
1044 union {
1045 double d;
1046 uint64_t i;
1047 } p;
1048
1049 p.d = FT0;
1050 FT0 = int64_to_float64(p.i, &env->fp_status);
1051}
1052
1053void do_fctid (void)
1054{
1055 union {
1056 double d;
1057 uint64_t i;
1058 } p;
1059
7c58044c
JM		 1060 if (unlikely(float64_is_signaling_nan(FT0))) {
1061 /* sNaN conversion */
1062 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1063 } else if (unlikely(float64_is_nan(FT0) || isinfinity(FT0))) {
1064 /* qNan / infinity conversion */
1065 fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1066 } else {
1067 p.i = float64_to_int64(FT0, &env->fp_status);
1068 FT0 = p.d;
1069 }
426613db
JM		 1070}
1071
1072void do_fctidz (void)
1073{
1074 union {
1075 double d;
1076 uint64_t i;
1077 } p;
1078
7c58044c
JM		 1079 if (unlikely(float64_is_signaling_nan(FT0))) {
1080 /* sNaN conversion */
1081 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1082 } else if (unlikely(float64_is_nan(FT0) || isinfinity(FT0))) {
1083 /* qNan / infinity conversion */
1084 fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1085 } else {
1086 p.i = float64_to_int64_round_to_zero(FT0, &env->fp_status);
1087 FT0 = p.d;
1088 }
426613db
JM		 1089}
1090
1091#endif
1092
b068d6a7 1093static always_inline void do_fri (int rounding_mode)
d7e4b87e 1094{
7c58044c
JM		 1095 if (unlikely(float64_is_signaling_nan(FT0))) {
1096 /* sNaN round */
1097 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1098 } else if (unlikely(float64_is_nan(FT0) || isinfinity(FT0))) {
1099 /* qNan / infinity round */
1100 fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1101 } else {
1102 set_float_rounding_mode(rounding_mode, &env->fp_status);
1103 FT0 = float64_round_to_int(FT0, &env->fp_status);
1104 /* Restore rounding mode from FPSCR */
1105 fpscr_set_rounding_mode();
1106 }
d7e4b87e
JM		 1107}
1108
1109void do_frin (void)
1110{
1111 do_fri(float_round_nearest_even);
1112}
1113
1114void do_friz (void)
1115{
1116 do_fri(float_round_to_zero);
1117}
1118
1119void do_frip (void)
1120{
1121 do_fri(float_round_up);
1122}
1123
1124void do_frim (void)
1125{
1126 do_fri(float_round_down);
1127}
1128
e864cabd
JM		 1129#if USE_PRECISE_EMULATION
1130void do_fmadd (void)
1131{
7c58044c
JM		 1132 if (unlikely(float64_is_signaling_nan(FT0) ||
1133 float64_is_signaling_nan(FT1) ||
1134 float64_is_signaling_nan(FT2))) {
1135 /* sNaN operation */
1136 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1137 } else {
e864cabd 1138#ifdef FLOAT128
7c58044c
JM		 1139 /* This is the way the PowerPC specification defines it */
1140 float128 ft0_128, ft1_128;
1141
1142 ft0_128 = float64_to_float128(FT0, &env->fp_status);
1143 ft1_128 = float64_to_float128(FT1, &env->fp_status);
1144 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1145 ft1_128 = float64_to_float128(FT2, &env->fp_status);
1146 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
1147 FT0 = float128_to_float64(ft0_128, &env->fp_status);
e864cabd 1148#else
7c58044c
JM		 1149 /* This is OK on x86 hosts */
1150 FT0 = (FT0 * FT1) + FT2;
e864cabd 1151#endif
7c58044c 1152 }
e864cabd
JM		 1153}
1154
1155void do_fmsub (void)
1156{
7c58044c
JM		 1157 if (unlikely(float64_is_signaling_nan(FT0) ||
1158 float64_is_signaling_nan(FT1) ||
1159 float64_is_signaling_nan(FT2))) {
1160 /* sNaN operation */
1161 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1162 } else {
e864cabd 1163#ifdef FLOAT128
7c58044c
JM		 1164 /* This is the way the PowerPC specification defines it */
1165 float128 ft0_128, ft1_128;
1166
1167 ft0_128 = float64_to_float128(FT0, &env->fp_status);
1168 ft1_128 = float64_to_float128(FT1, &env->fp_status);
1169 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1170 ft1_128 = float64_to_float128(FT2, &env->fp_status);
1171 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
1172 FT0 = float128_to_float64(ft0_128, &env->fp_status);
e864cabd 1173#else
7c58044c
JM		 1174 /* This is OK on x86 hosts */
1175 FT0 = (FT0 * FT1) - FT2;
e864cabd 1176#endif
7c58044c 1177 }
e864cabd
JM		 1178}
1179#endif /* USE_PRECISE_EMULATION */
1180
4b3686fa
FB		 1181void do_fnmadd (void)
1182{
7c58044c
JM		 1183 if (unlikely(float64_is_signaling_nan(FT0) ||
1184 float64_is_signaling_nan(FT1) ||
1185 float64_is_signaling_nan(FT2))) {
1186 /* sNaN operation */
1187 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1188 } else {
e864cabd
JM		 1189#if USE_PRECISE_EMULATION
1190#ifdef FLOAT128
7c58044c
JM		 1191 /* This is the way the PowerPC specification defines it */
1192 float128 ft0_128, ft1_128;
1193
1194 ft0_128 = float64_to_float128(FT0, &env->fp_status);
1195 ft1_128 = float64_to_float128(FT1, &env->fp_status);
1196 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1197 ft1_128 = float64_to_float128(FT2, &env->fp_status);
1198 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
1199 FT0 = float128_to_float64(ft0_128, &env->fp_status);
e864cabd 1200#else
7c58044c
JM		 1201 /* This is OK on x86 hosts */
1202 FT0 = (FT0 * FT1) + FT2;
e864cabd
JM		 1203#endif
1204#else
7c58044c
JM		 1205 FT0 = float64_mul(FT0, FT1, &env->fp_status);
1206 FT0 = float64_add(FT0, FT2, &env->fp_status);
e864cabd 1207#endif
7c58044c
JM		 1208 if (likely(!isnan(FT0)))
1209 FT0 = float64_chs(FT0);
1210 }
4b3686fa
FB		 1211}
1212
1213void do_fnmsub (void)
1214{
7c58044c
JM		 1215 if (unlikely(float64_is_signaling_nan(FT0) ||
1216 float64_is_signaling_nan(FT1) ||
1217 float64_is_signaling_nan(FT2))) {
1218 /* sNaN operation */
1219 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1220 } else {
e864cabd
JM		 1221#if USE_PRECISE_EMULATION
1222#ifdef FLOAT128
7c58044c
JM		 1223 /* This is the way the PowerPC specification defines it */
1224 float128 ft0_128, ft1_128;
1225
1226 ft0_128 = float64_to_float128(FT0, &env->fp_status);
1227 ft1_128 = float64_to_float128(FT1, &env->fp_status);
1228 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1229 ft1_128 = float64_to_float128(FT2, &env->fp_status);
1230 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
1231 FT0 = float128_to_float64(ft0_128, &env->fp_status);
e864cabd 1232#else
7c58044c
JM		 1233 /* This is OK on x86 hosts */
1234 FT0 = (FT0 * FT1) - FT2;
e864cabd
JM		 1235#endif
1236#else
7c58044c
JM		 1237 FT0 = float64_mul(FT0, FT1, &env->fp_status);
1238 FT0 = float64_sub(FT0, FT2, &env->fp_status);
e864cabd 1239#endif
7c58044c
JM		 1240 if (likely(!isnan(FT0)))
1241 FT0 = float64_chs(FT0);
1242 }
1ef59d0a
FB		 1243}
1244
7c58044c
JM		 1245#if USE_PRECISE_EMULATION
1246void do_frsp (void)
1247{
1248 if (unlikely(float64_is_signaling_nan(FT0))) {
1249 /* sNaN square root */
1250 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1251 } else {
1252 FT0 = float64_to_float32(FT0, &env->fp_status);
1253 }
1254}
1255#endif /* USE_PRECISE_EMULATION */
1256
9a64fbe4
FB		 1257void do_fsqrt (void)
1258{
7c58044c
JM		 1259 if (unlikely(float64_is_signaling_nan(FT0))) {
1260 /* sNaN square root */
1261 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1262 } else if (unlikely(fpisneg(FT0) && !iszero(FT0))) {
1263 /* Square root of a negative nonzero number */
1264 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
1265 } else {
1266 FT0 = float64_sqrt(FT0, &env->fp_status);
1267 }
9a64fbe4
FB		 1268}
1269
d7e4b87e
JM		 1270void do_fre (void)
1271{
1272 union {
1273 double d;
1274 uint64_t i;
1275 } p;
1276
7c58044c
JM		 1277 if (unlikely(float64_is_signaling_nan(FT0))) {
1278 /* sNaN reciprocal */
1279 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1280 } else if (unlikely(iszero(FT0))) {
1281 /* Zero reciprocal */
1282 float_zero_divide_excp();
1283 } else if (likely(isnormal(FT0))) {
d7e4b87e
JM		 1284 FT0 = float64_div(1.0, FT0, &env->fp_status);
1285 } else {
1286 p.d = FT0;
1287 if (p.i == 0x8000000000000000ULL) {
1288 p.i = 0xFFF0000000000000ULL;
1289 } else if (p.i == 0x0000000000000000ULL) {
1290 p.i = 0x7FF0000000000000ULL;
1291 } else if (isnan(FT0)) {
1292 p.i = 0x7FF8000000000000ULL;
7c58044c 1293 } else if (fpisneg(FT0)) {
d7e4b87e
JM		 1294 p.i = 0x8000000000000000ULL;
1295 } else {
1296 p.i = 0x0000000000000000ULL;
1297 }
1298 FT0 = p.d;
1299 }
1300}
1301
9a64fbe4
FB		 1302void do_fres (void)
1303{
4ecc3190
FB		 1304 union {
1305 double d;
1306 uint64_t i;
1307 } p;
1308
7c58044c
JM		 1309 if (unlikely(float64_is_signaling_nan(FT0))) {
1310 /* sNaN reciprocal */
1311 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1312 } else if (unlikely(iszero(FT0))) {
1313 /* Zero reciprocal */
1314 float_zero_divide_excp();
1315 } else if (likely(isnormal(FT0))) {
e864cabd
JM		 1316#if USE_PRECISE_EMULATION
1317 FT0 = float64_div(1.0, FT0, &env->fp_status);
1318 FT0 = float64_to_float32(FT0, &env->fp_status);
1319#else
76a66253 1320 FT0 = float32_div(1.0, FT0, &env->fp_status);
e864cabd 1321#endif
4ecc3190
FB		 1322 } else {
1323 p.d = FT0;
1324 if (p.i == 0x8000000000000000ULL) {
1325 p.i = 0xFFF0000000000000ULL;
1326 } else if (p.i == 0x0000000000000000ULL) {
1327 p.i = 0x7FF0000000000000ULL;
1328 } else if (isnan(FT0)) {
1329 p.i = 0x7FF8000000000000ULL;
7c58044c 1330 } else if (fpisneg(FT0)) {
4ecc3190
FB		 1331 p.i = 0x8000000000000000ULL;
1332 } else {
1333 p.i = 0x0000000000000000ULL;
1334 }
1335 FT0 = p.d;
1336 }
9a64fbe4
FB		 1337}
1338
4ecc3190 1339void do_frsqrte (void)
9a64fbe4 1340{
4ecc3190
FB		 1341 union {
1342 double d;
1343 uint64_t i;
1344 } p;
1345
7c58044c
JM		 1346 if (unlikely(float64_is_signaling_nan(FT0))) {
1347 /* sNaN reciprocal square root */
1348 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1349 } else if (unlikely(fpisneg(FT0) && !iszero(FT0))) {
1350 /* Reciprocal square root of a negative nonzero number */
1351 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
1352 } else if (likely(isnormal(FT0))) {
fdabc366
FB		 1353 FT0 = float64_sqrt(FT0, &env->fp_status);
1354 FT0 = float32_div(1.0, FT0, &env->fp_status);
4ecc3190
FB		 1355 } else {
1356 p.d = FT0;
1357 if (p.i == 0x8000000000000000ULL) {
1358 p.i = 0xFFF0000000000000ULL;
1359 } else if (p.i == 0x0000000000000000ULL) {
1360 p.i = 0x7FF0000000000000ULL;
1361 } else if (isnan(FT0)) {
7c58044c
JM		 1362 p.i |= 0x000FFFFFFFFFFFFFULL;
1363 } else if (fpisneg(FT0)) {
4ecc3190
FB		 1364 p.i = 0x7FF8000000000000ULL;
1365 } else {
1366 p.i = 0x0000000000000000ULL;
1367 }
1368 FT0 = p.d;
1369 }
9a64fbe4
FB		 1370}
1371
1372void do_fsel (void)
1373{
7c58044c 1374 if (!fpisneg(FT0) || iszero(FT0))
9a64fbe4 1375 FT0 = FT1;
4ecc3190
FB		 1376 else
1377 FT0 = FT2;
9a64fbe4
FB		 1378}
1379
1380void do_fcmpu (void)
1381{
7c58044c
JM		 1382 if (unlikely(float64_is_signaling_nan(FT0) ||
1383 float64_is_signaling_nan(FT1))) {
1384 /* sNaN comparison */
1385 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1386 } else {
fdabc366
FB		 1387 if (float64_lt(FT0, FT1, &env->fp_status)) {
1388 T0 = 0x08UL;
1389 } else if (!float64_le(FT0, FT1, &env->fp_status)) {
1390 T0 = 0x04UL;
1391 } else {
1392 T0 = 0x02UL;
1393 }
9a64fbe4 1394 }
7c58044c
JM		 1395 env->fpscr &= ~(0x0F << FPSCR_FPRF);
1396 env->fpscr |= T0 << FPSCR_FPRF;
9a64fbe4
FB		 1397}
1398
1399void do_fcmpo (void)
1400{
7c58044c
JM		 1401 if (unlikely(float64_is_nan(FT0) ||
1402 float64_is_nan(FT1))) {
1403 if (float64_is_signaling_nan(FT0) ||
1404 float64_is_signaling_nan(FT1)) {
1405 /* sNaN comparison */
1406 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN |
1407 POWERPC_EXCP_FP_VXVC);
1408 } else {
1409 /* qNaN comparison */
1410 fload_invalid_op_excp(POWERPC_EXCP_FP_VXVC);
1411 }
1412 } else {
fdabc366
FB		 1413 if (float64_lt(FT0, FT1, &env->fp_status)) {
1414 T0 = 0x08UL;
1415 } else if (!float64_le(FT0, FT1, &env->fp_status)) {
1416 T0 = 0x04UL;
1417 } else {
1418 T0 = 0x02UL;
1419 }
9a64fbe4 1420 }
7c58044c
JM		 1421 env->fpscr &= ~(0x0F << FPSCR_FPRF);
1422 env->fpscr |= T0 << FPSCR_FPRF;
9a64fbe4
FB		 1423}
1424
76a66253 1425#if !defined (CONFIG_USER_ONLY)
6b80055d 1426void cpu_dump_rfi (target_ulong RA, target_ulong msr);
0411a972
JM		 1427
1428void do_store_msr (void)
1429{
1430 T0 = hreg_store_msr(env, T0);
1431 if (T0 != 0) {
1432 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1433 do_raise_exception(T0);
1434 }
1435}
1436
1437static always_inline void __do_rfi (target_ulong nip, target_ulong msr,
1438 target_ulong msrm, int keep_msrh)
9a64fbe4 1439{
426613db 1440#if defined(TARGET_PPC64)
0411a972
JM		 1441 if (msr & (1ULL << MSR_SF)) {
1442 nip = (uint64_t)nip;
1443 msr &= (uint64_t)msrm;
a42bd6cc 1444 } else {
0411a972
JM		 1445 nip = (uint32_t)nip;
1446 msr = (uint32_t)(msr & msrm);
1447 if (keep_msrh)
1448 msr |= env->msr & ~((uint64_t)0xFFFFFFFF);
a42bd6cc 1449 }
426613db 1450#else
0411a972
JM		 1451 nip = (uint32_t)nip;
1452 msr &= (uint32_t)msrm;
426613db 1453#endif
0411a972
JM		 1454 /* XXX: beware: this is false if VLE is supported */
1455 env->nip = nip & ~((target_ulong)0x00000003);
1456 hreg_store_msr(env, msr);
fdabc366 1457#if defined (DEBUG_OP)
0411a972 1458 cpu_dump_rfi(env->nip, env->msr);
fdabc366 1459#endif
0411a972
JM		 1460 /* No need to raise an exception here,
1461 * as rfi is always the last insn of a TB
1462 */
fdabc366 1463 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
9a64fbe4 1464}
d9bce9d9 1465
0411a972
JM		 1466void do_rfi (void)
1467{
1468 __do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
1469 ~((target_ulong)0xFFFF0000), 1);
1470}
1471
d9bce9d9 1472#if defined(TARGET_PPC64)
426613db
JM		 1473void do_rfid (void)
1474{
0411a972
JM		 1475 __do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
1476 ~((target_ulong)0xFFFF0000), 0);
d9bce9d9
JM		 1477}
1478#endif
be147d08
JM		 1479#if defined(TARGET_PPC64H)
1480void do_hrfid (void)
1481{
0411a972
JM		 1482 __do_rfi(env->spr[SPR_HSRR0], env->spr[SPR_HSRR1],
1483 ~((target_ulong)0xFFFF0000), 0);
be147d08
JM		 1484}
1485#endif
76a66253 1486#endif
9a64fbe4 1487
76a66253 1488void do_tw (int flags)
9a64fbe4 1489{
d9bce9d9
JM		 1490 if (!likely(!(((int32_t)T0 < (int32_t)T1 && (flags & 0x10)) ||
1491 ((int32_t)T0 > (int32_t)T1 && (flags & 0x08)) ||
1492 ((int32_t)T0 == (int32_t)T1 && (flags & 0x04)) ||
1493 ((uint32_t)T0 < (uint32_t)T1 && (flags & 0x02)) ||
a42bd6cc 1494 ((uint32_t)T0 > (uint32_t)T1 && (flags & 0x01))))) {
e1833e1f 1495 do_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
a42bd6cc 1496 }
9a64fbe4
FB		 1497}
1498
d9bce9d9
JM		 1499#if defined(TARGET_PPC64)
1500void do_td (int flags)
1501{
1502 if (!likely(!(((int64_t)T0 < (int64_t)T1 && (flags & 0x10)) ||
1503 ((int64_t)T0 > (int64_t)T1 && (flags & 0x08)) ||
1504 ((int64_t)T0 == (int64_t)T1 && (flags & 0x04)) ||
1505 ((uint64_t)T0 < (uint64_t)T1 && (flags & 0x02)) ||
1506 ((uint64_t)T0 > (uint64_t)T1 && (flags & 0x01)))))
e1833e1f 1507 do_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
d9bce9d9
JM		 1508}
1509#endif
1510
fdabc366 1511/*****************************************************************************/
76a66253
JM		 1512/* PowerPC 601 specific instructions (POWER bridge) */
1513void do_POWER_abso (void)
9a64fbe4 1514{
d9bce9d9 1515 if ((uint32_t)T0 == INT32_MIN) {
76a66253
JM		 1516 T0 = INT32_MAX;
1517 xer_ov = 1;
1518 xer_so = 1;
1519 } else {
1520 T0 = -T0;
1521 xer_ov = 0;
1522 }
9a64fbe4
FB		 1523}
1524
76a66253 1525void do_POWER_clcs (void)
9a64fbe4 1526{
76a66253
JM		 1527 switch (T0) {
1528 case 0x0CUL:
1529 /* Instruction cache line size */
d63001d1 1530 T0 = env->icache_line_size;
76a66253
JM		 1531 break;
1532 case 0x0DUL:
1533 /* Data cache line size */
d63001d1 1534 T0 = env->dcache_line_size;
76a66253
JM		 1535 break;
1536 case 0x0EUL:
1537 /* Minimum cache line size */
d63001d1
JM		 1538 T0 = env->icache_line_size < env->dcache_line_size ?
1539 env->icache_line_size : env->dcache_line_size;
76a66253
JM		 1540 break;
1541 case 0x0FUL:
1542 /* Maximum cache line size */
d63001d1
JM		 1543 T0 = env->icache_line_size > env->dcache_line_size ?
1544 env->icache_line_size : env->dcache_line_size;
76a66253
JM		 1545 break;
1546 default:
1547 /* Undefined */
1548 break;
1549 }
1550}
1551
1552void do_POWER_div (void)
1553{
1554 uint64_t tmp;
1555
d9bce9d9 1556 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) || (int32_t)T1 == 0) {
76a66253
JM		 1557 T0 = (long)((-1) * (T0 >> 31));
1558 env->spr[SPR_MQ] = 0;
1559 } else {
1560 tmp = ((uint64_t)T0 << 32) | env->spr[SPR_MQ];
1561 env->spr[SPR_MQ] = tmp % T1;
d9bce9d9 1562 T0 = tmp / (int32_t)T1;
76a66253
JM		 1563 }
1564}
1565
1566void do_POWER_divo (void)
1567{
1568 int64_t tmp;
1569
d9bce9d9 1570 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) || (int32_t)T1 == 0) {
76a66253
JM		 1571 T0 = (long)((-1) * (T0 >> 31));
1572 env->spr[SPR_MQ] = 0;
1573 xer_ov = 1;
1574 xer_so = 1;
1575 } else {
1576 tmp = ((uint64_t)T0 << 32) | env->spr[SPR_MQ];
1577 env->spr[SPR_MQ] = tmp % T1;
d9bce9d9 1578 tmp /= (int32_t)T1;
76a66253
JM		 1579 if (tmp > (int64_t)INT32_MAX || tmp < (int64_t)INT32_MIN) {
1580 xer_ov = 1;
1581 xer_so = 1;
1582 } else {
1583 xer_ov = 0;
1584 }
1585 T0 = tmp;
1586 }
1587}
1588
1589void do_POWER_divs (void)
1590{
d9bce9d9 1591 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) || (int32_t)T1 == 0) {
76a66253
JM		 1592 T0 = (long)((-1) * (T0 >> 31));
1593 env->spr[SPR_MQ] = 0;
1594 } else {
1595 env->spr[SPR_MQ] = T0 % T1;
d9bce9d9 1596 T0 = (int32_t)T0 / (int32_t)T1;
76a66253
JM		 1597 }
1598}
1599
1600void do_POWER_divso (void)
1601{
d9bce9d9 1602 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) || (int32_t)T1 == 0) {
76a66253
JM		 1603 T0 = (long)((-1) * (T0 >> 31));
1604 env->spr[SPR_MQ] = 0;
1605 xer_ov = 1;
1606 xer_so = 1;
1607 } else {
d9bce9d9
JM		 1608 T0 = (int32_t)T0 / (int32_t)T1;
1609 env->spr[SPR_MQ] = (int32_t)T0 % (int32_t)T1;
76a66253
JM		 1610 xer_ov = 0;
1611 }
1612}
1613
1614void do_POWER_dozo (void)
1615{
d9bce9d9 1616 if ((int32_t)T1 > (int32_t)T0) {
76a66253
JM		 1617 T2 = T0;
1618 T0 = T1 - T0;
d9bce9d9
JM		 1619 if (((uint32_t)(~T2) ^ (uint32_t)T1 ^ UINT32_MAX) &
1620 ((uint32_t)(~T2) ^ (uint32_t)T0) & (1UL << 31)) {
76a66253 1621 xer_ov = 1;
966439a6 1622 xer_so = 1;
76a66253
JM		 1623 } else {
1624 xer_ov = 0;
1625 }
1626 } else {
1627 T0 = 0;
1628 xer_ov = 0;
1629 }
1630}
1631
1632void do_POWER_maskg (void)
1633{
1634 uint32_t ret;
1635
d9bce9d9 1636 if ((uint32_t)T0 == (uint32_t)(T1 + 1)) {
76a66253
JM		 1637 ret = -1;
1638 } else {
d9bce9d9
JM		 1639 ret = (((uint32_t)(-1)) >> ((uint32_t)T0)) ^
1640 (((uint32_t)(-1) >> ((uint32_t)T1)) >> 1);
1641 if ((uint32_t)T0 > (uint32_t)T1)
76a66253
JM		 1642 ret = ~ret;
1643 }
1644 T0 = ret;
1645}
1646
1647void do_POWER_mulo (void)
1648{
1649 uint64_t tmp;
1650
1651 tmp = (uint64_t)T0 * (uint64_t)T1;
1652 env->spr[SPR_MQ] = tmp >> 32;
1653 T0 = tmp;
1654 if (tmp >> 32 != ((uint64_t)T0 >> 16) * ((uint64_t)T1 >> 16)) {
1655 xer_ov = 1;
1656 xer_so = 1;
1657 } else {
1658 xer_ov = 0;
1659 }
1660}
1661
1662#if !defined (CONFIG_USER_ONLY)
1663void do_POWER_rac (void)
1664{
76a66253 1665 mmu_ctx_t ctx;
faadf50e 1666 int nb_BATs;
76a66253
JM		 1667
1668 /* We don't have to generate many instances of this instruction,
1669 * as rac is supervisor only.
1670 */
faadf50e
JM		 1671 /* XXX: FIX THIS: Pretend we have no BAT */
1672 nb_BATs = env->nb_BATs;
1673 env->nb_BATs = 0;
1674 if (get_physical_address(env, &ctx, T0, 0, ACCESS_INT) == 0)
76a66253 1675 T0 = ctx.raddr;
faadf50e 1676 env->nb_BATs = nb_BATs;
76a66253
JM		 1677}
1678
1679void do_POWER_rfsvc (void)
1680{
0411a972 1681 __do_rfi(env->lr, env->ctr, 0x0000FFFF, 0);
76a66253
JM		 1682}
1683
056401ea
JM		 1684void do_store_hid0_601 (void)
1685{
1686 uint32_t hid0;
1687
1688 hid0 = env->spr[SPR_HID0];
1689 if ((T0 ^ hid0) & 0x00000008) {
1690 /* Change current endianness */
1691 env->hflags &= ~(1 << MSR_LE);
1692 env->hflags_nmsr &= ~(1 << MSR_LE);
1693 env->hflags_nmsr |= (1 << MSR_LE) & (((T0 >> 3) & 1) << MSR_LE);
1694 env->hflags |= env->hflags_nmsr;
1695 if (loglevel != 0) {
1696 fprintf(logfile, "%s: set endianness to %c => " ADDRX "\n",
1697 __func__, T0 & 0x8 ? 'l' : 'b', env->hflags);
1698 }
1699 }
1700 env->spr[SPR_HID0] = T0;
76a66253
JM		 1701}
1702#endif
1703
1704/*****************************************************************************/
1705/* 602 specific instructions */
1706/* mfrom is the most crazy instruction ever seen, imho ! */
1707/* Real implementation uses a ROM table. Do the same */
1708#define USE_MFROM_ROM_TABLE
1709void do_op_602_mfrom (void)
1710{
1711 if (likely(T0 < 602)) {
d9bce9d9 1712#if defined(USE_MFROM_ROM_TABLE)
76a66253
JM		 1713#include "mfrom_table.c"
1714 T0 = mfrom_ROM_table[T0];
fdabc366 1715#else
76a66253
JM		 1716 double d;
1717 /* Extremly decomposed:
1718 * -T0 / 256
1719 * T0 = 256 * log10(10 + 1.0) + 0.5
1720 */
1721 d = T0;
1722 d = float64_div(d, 256, &env->fp_status);
1723 d = float64_chs(d);
1724 d = exp10(d); // XXX: use float emulation function
1725 d = float64_add(d, 1.0, &env->fp_status);
1726 d = log10(d); // XXX: use float emulation function
1727 d = float64_mul(d, 256, &env->fp_status);
1728 d = float64_add(d, 0.5, &env->fp_status);
1729 T0 = float64_round_to_int(d, &env->fp_status);
fdabc366 1730#endif
76a66253
JM		 1731 } else {
1732 T0 = 0;
1733 }
1734}
1735
1736/*****************************************************************************/
1737/* Embedded PowerPC specific helpers */
76a66253
JM		 1738void do_405_check_sat (void)
1739{
d9bce9d9
JM		 1740 if (!likely((((uint32_t)T1 ^ (uint32_t)T2) >> 31) ||
1741 !(((uint32_t)T0 ^ (uint32_t)T2) >> 31))) {
76a66253
JM		 1742 /* Saturate result */
1743 if (T2 >> 31) {
1744 T0 = INT32_MIN;
1745 } else {
1746 T0 = INT32_MAX;
1747 }
1748 }
1749}
1750
a750fc0b
JM		 1751/* XXX: to be improved to check access rights when in user-mode */
1752void do_load_dcr (void)
1753{
1754 target_ulong val;
1755
1756 if (unlikely(env->dcr_env == NULL)) {
1757 if (loglevel != 0) {
1758 fprintf(logfile, "No DCR environment\n");
1759 }
e1833e1f
JM		 1760 do_raise_exception_err(POWERPC_EXCP_PROGRAM,
1761 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
a750fc0b
JM		 1762 } else if (unlikely(ppc_dcr_read(env->dcr_env, T0, &val) != 0)) {
1763 if (loglevel != 0) {
1764 fprintf(logfile, "DCR read error %d %03x\n", (int)T0, (int)T0);
1765 }
e1833e1f
JM		 1766 do_raise_exception_err(POWERPC_EXCP_PROGRAM,
1767 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
a750fc0b
JM		 1768 } else {
1769 T0 = val;
1770 }
1771}
1772
1773void do_store_dcr (void)
1774{
1775 if (unlikely(env->dcr_env == NULL)) {
1776 if (loglevel != 0) {
1777 fprintf(logfile, "No DCR environment\n");
1778 }
e1833e1f
JM		 1779 do_raise_exception_err(POWERPC_EXCP_PROGRAM,
1780 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
a750fc0b
JM		 1781 } else if (unlikely(ppc_dcr_write(env->dcr_env, T0, T1) != 0)) {
1782 if (loglevel != 0) {
1783 fprintf(logfile, "DCR write error %d %03x\n", (int)T0, (int)T0);
1784 }
e1833e1f
JM		 1785 do_raise_exception_err(POWERPC_EXCP_PROGRAM,
1786 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
a750fc0b
JM		 1787 }
1788}
1789
76a66253 1790#if !defined(CONFIG_USER_ONLY)
a42bd6cc 1791void do_40x_rfci (void)
76a66253 1792{
0411a972
JM		 1793 __do_rfi(env->spr[SPR_40x_SRR2], env->spr[SPR_40x_SRR3],
1794 ~((target_ulong)0xFFFF0000), 0);
a42bd6cc
JM		 1795}
1796
1797void do_rfci (void)
1798{
0411a972
JM		 1799 __do_rfi(env->spr[SPR_BOOKE_CSRR0], SPR_BOOKE_CSRR1,
1800 ~((target_ulong)0x3FFF0000), 0);
a42bd6cc
JM		 1801}
1802
1803void do_rfdi (void)
1804{
0411a972
JM		 1805 __do_rfi(env->spr[SPR_BOOKE_DSRR0], SPR_BOOKE_DSRR1,
1806 ~((target_ulong)0x3FFF0000), 0);
a42bd6cc
JM		 1807}
1808
1809void do_rfmci (void)
1810{
0411a972
JM		 1811 __do_rfi(env->spr[SPR_BOOKE_MCSRR0], SPR_BOOKE_MCSRR1,
1812 ~((target_ulong)0x3FFF0000), 0);
76a66253
JM		 1813}
1814
76a66253
JM		 1815void do_load_403_pb (int num)
1816{
1817 T0 = env->pb[num];
1818}
1819
1820void do_store_403_pb (int num)
1821{
1822 if (likely(env->pb[num] != T0)) {
1823 env->pb[num] = T0;
1824 /* Should be optimized */
1825 tlb_flush(env, 1);
1826 }
1827}
1828#endif
1829
1830/* 440 specific */
1831void do_440_dlmzb (void)
1832{
1833 target_ulong mask;
1834 int i;
1835
1836 i = 1;
1837 for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
1838 if ((T0 & mask) == 0)
1839 goto done;
1840 i++;
1841 }
1842 for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
1843 if ((T1 & mask) == 0)
1844 break;
1845 i++;
1846 }
1847 done:
1848 T0 = i;
fdabc366
FB		 1849}
1850
35cdaad6 1851#if defined(TARGET_PPCEMB)
0487d6a8
JM		 1852/* SPE extension helpers */
1853/* Use a table to make this quicker */
1854static uint8_t hbrev[16] = {
1855 0x0, 0x8, 0x4, 0xC, 0x2, 0xA, 0x6, 0xE,
1856 0x1, 0x9, 0x5, 0xD, 0x3, 0xB, 0x7, 0xF,
1857};
1858
b068d6a7 1859static always_inline uint8_t byte_reverse (uint8_t val)
0487d6a8
JM		 1860{
1861 return hbrev[val >> 4] | (hbrev[val & 0xF] << 4);
1862}
1863
b068d6a7 1864static always_inline uint32_t word_reverse (uint32_t val)
0487d6a8
JM		 1865{
1866 return byte_reverse(val >> 24) | (byte_reverse(val >> 16) << 8) |
1867 (byte_reverse(val >> 8) << 16) | (byte_reverse(val) << 24);
1868}
1869
1870#define MASKBITS 16 // Random value - to be fixed
1871void do_brinc (void)
1872{
1873 uint32_t a, b, d, mask;
1874
1875 mask = (uint32_t)(-1UL) >> MASKBITS;
1876 b = T1_64 & mask;
1877 a = T0_64 & mask;
1878 d = word_reverse(1 + word_reverse(a | ~mask));
1879 T0_64 = (T0_64 & ~mask) | (d & mask);
1880}
1881
1882#define DO_SPE_OP2(name) \
1883void do_ev##name (void) \
1884{ \
1885 T0_64 = ((uint64_t)_do_e##name(T0_64 >> 32, T1_64 >> 32) << 32) | \
1886 (uint64_t)_do_e##name(T0_64, T1_64); \
1887}
1888
1889#define DO_SPE_OP1(name) \
1890void do_ev##name (void) \
1891{ \
1892 T0_64 = ((uint64_t)_do_e##name(T0_64 >> 32) << 32) | \
1893 (uint64_t)_do_e##name(T0_64); \
1894}
1895
1896/* Fixed-point vector arithmetic */
b068d6a7 1897static always_inline uint32_t _do_eabs (uint32_t val)
0487d6a8
JM		 1898{
1899 if (val != 0x80000000)
1900 val &= ~0x80000000;
1901
1902 return val;
1903}
1904
b068d6a7 1905static always_inline uint32_t _do_eaddw (uint32_t op1, uint32_t op2)
0487d6a8
JM		 1906{
1907 return op1 + op2;
1908}
1909
b068d6a7 1910static always_inline int _do_ecntlsw (uint32_t val)
0487d6a8
JM		 1911{
1912 if (val & 0x80000000)
603fccce 1913 return clz32(~val);
0487d6a8 1914 else
603fccce 1915 return clz32(val);
0487d6a8
JM		 1916}
1917
b068d6a7 1918static always_inline int _do_ecntlzw (uint32_t val)
0487d6a8 1919{
603fccce 1920 return clz32(val);
0487d6a8
JM		 1921}
1922
b068d6a7 1923static always_inline uint32_t _do_eneg (uint32_t val)
0487d6a8
JM		 1924{
1925 if (val != 0x80000000)
1926 val ^= 0x80000000;
1927
1928 return val;
1929}
1930
b068d6a7 1931static always_inline uint32_t _do_erlw (uint32_t op1, uint32_t op2)
0487d6a8
JM		 1932{
1933 return rotl32(op1, op2);
1934}
1935
b068d6a7 1936static always_inline uint32_t _do_erndw (uint32_t val)
0487d6a8
JM		 1937{
1938 return (val + 0x000080000000) & 0xFFFF0000;
1939}
1940
b068d6a7 1941static always_inline uint32_t _do_eslw (uint32_t op1, uint32_t op2)
0487d6a8
JM		 1942{
1943 /* No error here: 6 bits are used */
1944 return op1 << (op2 & 0x3F);
1945}
1946
b068d6a7 1947static always_inline int32_t _do_esrws (int32_t op1, uint32_t op2)
0487d6a8
JM		 1948{
1949 /* No error here: 6 bits are used */
1950 return op1 >> (op2 & 0x3F);
1951}
1952
b068d6a7 1953static always_inline uint32_t _do_esrwu (uint32_t op1, uint32_t op2)
0487d6a8
JM		 1954{
1955 /* No error here: 6 bits are used */
1956 return op1 >> (op2 & 0x3F);
1957}
1958
b068d6a7 1959static always_inline uint32_t _do_esubfw (uint32_t op1, uint32_t op2)
0487d6a8
JM		 1960{
1961 return op2 - op1;
1962}
1963
1964/* evabs */
1965DO_SPE_OP1(abs);
1966/* evaddw */
1967DO_SPE_OP2(addw);
1968/* evcntlsw */
1969DO_SPE_OP1(cntlsw);
1970/* evcntlzw */
1971DO_SPE_OP1(cntlzw);
1972/* evneg */
1973DO_SPE_OP1(neg);
1974/* evrlw */
1975DO_SPE_OP2(rlw);
1976/* evrnd */
1977DO_SPE_OP1(rndw);
1978/* evslw */
1979DO_SPE_OP2(slw);
1980/* evsrws */
1981DO_SPE_OP2(srws);
1982/* evsrwu */
1983DO_SPE_OP2(srwu);
1984/* evsubfw */
1985DO_SPE_OP2(subfw);
1986
1987/* evsel is a little bit more complicated... */
b068d6a7 1988static always_inline uint32_t _do_esel (uint32_t op1, uint32_t op2, int n)
0487d6a8
JM		 1989{
1990 if (n)
1991 return op1;
1992 else
1993 return op2;
1994}
1995
1996void do_evsel (void)
1997{
1998 T0_64 = ((uint64_t)_do_esel(T0_64 >> 32, T1_64 >> 32, T0 >> 3) << 32) |
1999 (uint64_t)_do_esel(T0_64, T1_64, (T0 >> 2) & 1);
2000}
2001
2002/* Fixed-point vector comparisons */
2003#define DO_SPE_CMP(name) \
2004void do_ev##name (void) \
2005{ \
2006 T0 = _do_evcmp_merge((uint64_t)_do_e##name(T0_64 >> 32, \
2007 T1_64 >> 32) << 32, \
2008 _do_e##name(T0_64, T1_64)); \
2009}
2010
b068d6a7 2011static always_inline uint32_t _do_evcmp_merge (int t0, int t1)
0487d6a8
JM		 2012{
2013 return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1);
2014}
b068d6a7 2015static always_inline int _do_ecmpeq (uint32_t op1, uint32_t op2)
0487d6a8
JM		 2016{
2017 return op1 == op2 ? 1 : 0;
2018}
2019
b068d6a7 2020static always_inline int _do_ecmpgts (int32_t op1, int32_t op2)
0487d6a8
JM		 2021{
2022 return op1 > op2 ? 1 : 0;
2023}
2024
b068d6a7 2025static always_inline int _do_ecmpgtu (uint32_t op1, uint32_t op2)
0487d6a8
JM		 2026{
2027 return op1 > op2 ? 1 : 0;
2028}
2029
b068d6a7 2030static always_inline int _do_ecmplts (int32_t op1, int32_t op2)
0487d6a8
JM		 2031{
2032 return op1 < op2 ? 1 : 0;
2033}
2034
b068d6a7 2035static always_inline int _do_ecmpltu (uint32_t op1, uint32_t op2)
0487d6a8
JM		 2036{
2037 return op1 < op2 ? 1 : 0;
2038}
2039
2040/* evcmpeq */
2041DO_SPE_CMP(cmpeq);
2042/* evcmpgts */
2043DO_SPE_CMP(cmpgts);
2044/* evcmpgtu */
2045DO_SPE_CMP(cmpgtu);
2046/* evcmplts */
2047DO_SPE_CMP(cmplts);
2048/* evcmpltu */
2049DO_SPE_CMP(cmpltu);
2050
2051/* Single precision floating-point conversions from/to integer */
b068d6a7 2052static always_inline uint32_t _do_efscfsi (int32_t val)
0487d6a8
JM		 2053{
2054 union {
2055 uint32_t u;
2056 float32 f;
2057 } u;
2058
2059 u.f = int32_to_float32(val, &env->spe_status);
2060
2061 return u.u;
2062}
2063
b068d6a7 2064static always_inline uint32_t _do_efscfui (uint32_t val)
0487d6a8
JM		 2065{
2066 union {
2067 uint32_t u;
2068 float32 f;
2069 } u;
2070
2071 u.f = uint32_to_float32(val, &env->spe_status);
2072
2073 return u.u;
2074}
2075
b068d6a7 2076static always_inline int32_t _do_efsctsi (uint32_t val)
0487d6a8
JM		 2077{
2078 union {
2079 int32_t u;
2080 float32 f;
2081 } u;
2082
2083 u.u = val;
2084 /* NaN are not treated the same way IEEE 754 does */
2085 if (unlikely(isnan(u.f)))
2086 return 0;
2087
2088 return float32_to_int32(u.f, &env->spe_status);
2089}
2090
b068d6a7 2091static always_inline uint32_t _do_efsctui (uint32_t val)
0487d6a8
JM		 2092{
2093 union {
2094 int32_t u;
2095 float32 f;
2096 } u;
2097
2098 u.u = val;
2099 /* NaN are not treated the same way IEEE 754 does */
2100 if (unlikely(isnan(u.f)))
2101 return 0;
2102
2103 return float32_to_uint32(u.f, &env->spe_status);
2104}
2105
b068d6a7 2106static always_inline int32_t _do_efsctsiz (uint32_t val)
0487d6a8
JM		 2107{
2108 union {
2109 int32_t u;
2110 float32 f;
2111 } u;
2112
2113 u.u = val;
2114 /* NaN are not treated the same way IEEE 754 does */
2115 if (unlikely(isnan(u.f)))
2116 return 0;
2117
2118 return float32_to_int32_round_to_zero(u.f, &env->spe_status);
2119}
2120
b068d6a7 2121static always_inline uint32_t _do_efsctuiz (uint32_t val)
0487d6a8
JM		 2122{
2123 union {
2124 int32_t u;
2125 float32 f;
2126 } u;
2127
2128 u.u = val;
2129 /* NaN are not treated the same way IEEE 754 does */
2130 if (unlikely(isnan(u.f)))
2131 return 0;
2132
2133 return float32_to_uint32_round_to_zero(u.f, &env->spe_status);
2134}
2135
2136void do_efscfsi (void)
2137{
2138 T0_64 = _do_efscfsi(T0_64);
2139}
2140
2141void do_efscfui (void)
2142{
2143 T0_64 = _do_efscfui(T0_64);
2144}
2145
2146void do_efsctsi (void)
2147{
2148 T0_64 = _do_efsctsi(T0_64);
2149}
2150
2151void do_efsctui (void)
2152{
2153 T0_64 = _do_efsctui(T0_64);
2154}
2155
2156void do_efsctsiz (void)
2157{
2158 T0_64 = _do_efsctsiz(T0_64);
2159}
2160
2161void do_efsctuiz (void)
2162{
2163 T0_64 = _do_efsctuiz(T0_64);
2164}
2165
2166/* Single precision floating-point conversion to/from fractional */
b068d6a7 2167static always_inline uint32_t _do_efscfsf (uint32_t val)
0487d6a8
JM		 2168{
2169 union {
2170 uint32_t u;
2171 float32 f;
2172 } u;
2173 float32 tmp;
2174
2175 u.f = int32_to_float32(val, &env->spe_status);
2176 tmp = int64_to_float32(1ULL << 32, &env->spe_status);
2177 u.f = float32_div(u.f, tmp, &env->spe_status);
2178
2179 return u.u;
2180}
2181
b068d6a7 2182static always_inline uint32_t _do_efscfuf (uint32_t val)
0487d6a8
JM		 2183{
2184 union {
2185 uint32_t u;
2186 float32 f;
2187 } u;
2188 float32 tmp;
2189
2190 u.f = uint32_to_float32(val, &env->spe_status);
2191 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2192 u.f = float32_div(u.f, tmp, &env->spe_status);
2193
2194 return u.u;
2195}
2196
b068d6a7 2197static always_inline int32_t _do_efsctsf (uint32_t val)
0487d6a8
JM		 2198{
2199 union {
2200 int32_t u;
2201 float32 f;
2202 } u;
2203 float32 tmp;
2204
2205 u.u = val;
2206 /* NaN are not treated the same way IEEE 754 does */
2207 if (unlikely(isnan(u.f)))
2208 return 0;
2209 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2210 u.f = float32_mul(u.f, tmp, &env->spe_status);
2211
2212 return float32_to_int32(u.f, &env->spe_status);
2213}
2214
b068d6a7 2215static always_inline uint32_t _do_efsctuf (uint32_t val)
0487d6a8
JM		 2216{
2217 union {
2218 int32_t u;
2219 float32 f;
2220 } u;
2221 float32 tmp;
2222
2223 u.u = val;
2224 /* NaN are not treated the same way IEEE 754 does */
2225 if (unlikely(isnan(u.f)))
2226 return 0;
2227 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2228 u.f = float32_mul(u.f, tmp, &env->spe_status);
2229
2230 return float32_to_uint32(u.f, &env->spe_status);
2231}
2232
b068d6a7 2233static always_inline int32_t _do_efsctsfz (uint32_t val)
0487d6a8
JM		 2234{
2235 union {
2236 int32_t u;
2237 float32 f;
2238 } u;
2239 float32 tmp;
2240
2241 u.u = val;
2242 /* NaN are not treated the same way IEEE 754 does */
2243 if (unlikely(isnan(u.f)))
2244 return 0;
2245 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2246 u.f = float32_mul(u.f, tmp, &env->spe_status);
2247
2248 return float32_to_int32_round_to_zero(u.f, &env->spe_status);
2249}
2250
b068d6a7 2251static always_inline uint32_t _do_efsctufz (uint32_t val)
0487d6a8
JM		 2252{
2253 union {
2254 int32_t u;
2255 float32 f;
2256 } u;
2257 float32 tmp;
2258
2259 u.u = val;
2260 /* NaN are not treated the same way IEEE 754 does */
2261 if (unlikely(isnan(u.f)))
2262 return 0;
2263 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2264 u.f = float32_mul(u.f, tmp, &env->spe_status);
2265
2266 return float32_to_uint32_round_to_zero(u.f, &env->spe_status);
2267}
2268
2269void do_efscfsf (void)
2270{
2271 T0_64 = _do_efscfsf(T0_64);
2272}
2273
2274void do_efscfuf (void)
2275{
2276 T0_64 = _do_efscfuf(T0_64);
2277}
2278
2279void do_efsctsf (void)
2280{
2281 T0_64 = _do_efsctsf(T0_64);
2282}
2283
2284void do_efsctuf (void)
2285{
2286 T0_64 = _do_efsctuf(T0_64);
2287}
2288
2289void do_efsctsfz (void)
2290{
2291 T0_64 = _do_efsctsfz(T0_64);
2292}
2293
2294void do_efsctufz (void)
2295{
2296 T0_64 = _do_efsctufz(T0_64);
2297}
2298
2299/* Double precision floating point helpers */
b068d6a7 2300static always_inline int _do_efdcmplt (uint64_t op1, uint64_t op2)
0487d6a8
JM		 2301{
2302 /* XXX: TODO: test special values (NaN, infinites, ...) */
2303 return _do_efdtstlt(op1, op2);
2304}
2305
b068d6a7 2306static always_inline int _do_efdcmpgt (uint64_t op1, uint64_t op2)
0487d6a8
JM		 2307{
2308 /* XXX: TODO: test special values (NaN, infinites, ...) */
2309 return _do_efdtstgt(op1, op2);
2310}
2311
b068d6a7 2312static always_inline int _do_efdcmpeq (uint64_t op1, uint64_t op2)
0487d6a8
JM		 2313{
2314 /* XXX: TODO: test special values (NaN, infinites, ...) */
2315 return _do_efdtsteq(op1, op2);
2316}
2317
2318void do_efdcmplt (void)
2319{
2320 T0 = _do_efdcmplt(T0_64, T1_64);
2321}
2322
2323void do_efdcmpgt (void)
2324{
2325 T0 = _do_efdcmpgt(T0_64, T1_64);
2326}
2327
2328void do_efdcmpeq (void)
2329{
2330 T0 = _do_efdcmpeq(T0_64, T1_64);
2331}
2332
2333/* Double precision floating-point conversion to/from integer */
b068d6a7 2334static always_inline uint64_t _do_efdcfsi (int64_t val)
0487d6a8
JM		 2335{
2336 union {
2337 uint64_t u;
2338 float64 f;
2339 } u;
2340
2341 u.f = int64_to_float64(val, &env->spe_status);
2342
2343 return u.u;
2344}
2345
b068d6a7 2346static always_inline uint64_t _do_efdcfui (uint64_t val)
0487d6a8
JM		 2347{
2348 union {
2349 uint64_t u;
2350 float64 f;
2351 } u;
2352
2353 u.f = uint64_to_float64(val, &env->spe_status);
2354
2355 return u.u;
2356}
2357
b068d6a7 2358static always_inline int64_t _do_efdctsi (uint64_t val)
0487d6a8
JM		 2359{
2360 union {
2361 int64_t u;
2362 float64 f;
2363 } u;
2364
2365 u.u = val;
2366 /* NaN are not treated the same way IEEE 754 does */
2367 if (unlikely(isnan(u.f)))
2368 return 0;
2369
2370 return float64_to_int64(u.f, &env->spe_status);
2371}
2372
b068d6a7 2373static always_inline uint64_t _do_efdctui (uint64_t val)
0487d6a8
JM		 2374{
2375 union {
2376 int64_t u;
2377 float64 f;
2378 } u;
2379
2380 u.u = val;
2381 /* NaN are not treated the same way IEEE 754 does */
2382 if (unlikely(isnan(u.f)))
2383 return 0;
2384
2385 return float64_to_uint64(u.f, &env->spe_status);
2386}
2387
b068d6a7 2388static always_inline int64_t _do_efdctsiz (uint64_t val)
0487d6a8
JM		 2389{
2390 union {
2391 int64_t u;
2392 float64 f;
2393 } u;
2394
2395 u.u = val;
2396 /* NaN are not treated the same way IEEE 754 does */
2397 if (unlikely(isnan(u.f)))
2398 return 0;
2399
2400 return float64_to_int64_round_to_zero(u.f, &env->spe_status);
2401}
2402
b068d6a7 2403static always_inline uint64_t _do_efdctuiz (uint64_t val)
0487d6a8
JM		 2404{
2405 union {
2406 int64_t u;
2407 float64 f;
2408 } u;
2409
2410 u.u = val;
2411 /* NaN are not treated the same way IEEE 754 does */
2412 if (unlikely(isnan(u.f)))
2413 return 0;
2414
2415 return float64_to_uint64_round_to_zero(u.f, &env->spe_status);
2416}
2417
2418void do_efdcfsi (void)
2419{
2420 T0_64 = _do_efdcfsi(T0_64);
2421}
2422
2423void do_efdcfui (void)
2424{
2425 T0_64 = _do_efdcfui(T0_64);
2426}
2427
2428void do_efdctsi (void)
2429{
2430 T0_64 = _do_efdctsi(T0_64);
2431}
2432
2433void do_efdctui (void)
2434{
2435 T0_64 = _do_efdctui(T0_64);
2436}
2437
2438void do_efdctsiz (void)
2439{
2440 T0_64 = _do_efdctsiz(T0_64);
2441}
2442
2443void do_efdctuiz (void)
2444{
2445 T0_64 = _do_efdctuiz(T0_64);
2446}
2447
2448/* Double precision floating-point conversion to/from fractional */
b068d6a7 2449static always_inline uint64_t _do_efdcfsf (int64_t val)
0487d6a8
JM		 2450{
2451 union {
2452 uint64_t u;
2453 float64 f;
2454 } u;
2455 float64 tmp;
2456
2457 u.f = int32_to_float64(val, &env->spe_status);
2458 tmp = int64_to_float64(1ULL << 32, &env->spe_status);
2459 u.f = float64_div(u.f, tmp, &env->spe_status);
2460
2461 return u.u;
2462}
2463
b068d6a7 2464static always_inline uint64_t _do_efdcfuf (uint64_t val)
0487d6a8
JM		 2465{
2466 union {
2467 uint64_t u;
2468 float64 f;
2469 } u;
2470 float64 tmp;
2471
2472 u.f = uint32_to_float64(val, &env->spe_status);
2473 tmp = int64_to_float64(1ULL << 32, &env->spe_status);
2474 u.f = float64_div(u.f, tmp, &env->spe_status);
2475
2476 return u.u;
2477}
2478
b068d6a7 2479static always_inline int64_t _do_efdctsf (uint64_t val)
0487d6a8
JM		 2480{
2481 union {
2482 int64_t u;
2483 float64 f;
2484 } u;
2485 float64 tmp;
2486
2487 u.u = val;
2488 /* NaN are not treated the same way IEEE 754 does */
2489 if (unlikely(isnan(u.f)))
2490 return 0;
2491 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2492 u.f = float64_mul(u.f, tmp, &env->spe_status);
2493
2494 return float64_to_int32(u.f, &env->spe_status);
2495}
2496
b068d6a7 2497static always_inline uint64_t _do_efdctuf (uint64_t val)
0487d6a8
JM		 2498{
2499 union {
2500 int64_t u;
2501 float64 f;
2502 } u;
2503 float64 tmp;
2504
2505 u.u = val;
2506 /* NaN are not treated the same way IEEE 754 does */
2507 if (unlikely(isnan(u.f)))
2508 return 0;
2509 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2510 u.f = float64_mul(u.f, tmp, &env->spe_status);
2511
2512 return float64_to_uint32(u.f, &env->spe_status);
2513}
2514
b068d6a7 2515static always_inline int64_t _do_efdctsfz (uint64_t val)
0487d6a8
JM		 2516{
2517 union {
2518 int64_t u;
2519 float64 f;
2520 } u;
2521 float64 tmp;
2522
2523 u.u = val;
2524 /* NaN are not treated the same way IEEE 754 does */
2525 if (unlikely(isnan(u.f)))
2526 return 0;
2527 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2528 u.f = float64_mul(u.f, tmp, &env->spe_status);
2529
2530 return float64_to_int32_round_to_zero(u.f, &env->spe_status);
2531}
2532
b068d6a7 2533static always_inline uint64_t _do_efdctufz (uint64_t val)
0487d6a8
JM		 2534{
2535 union {
2536 int64_t u;
2537 float64 f;
2538 } u;
2539 float64 tmp;
2540
2541 u.u = val;
2542 /* NaN are not treated the same way IEEE 754 does */
2543 if (unlikely(isnan(u.f)))
2544 return 0;
2545 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2546 u.f = float64_mul(u.f, tmp, &env->spe_status);
2547
2548 return float64_to_uint32_round_to_zero(u.f, &env->spe_status);
2549}
2550
2551void do_efdcfsf (void)
2552{
2553 T0_64 = _do_efdcfsf(T0_64);
2554}
2555
2556void do_efdcfuf (void)
2557{
2558 T0_64 = _do_efdcfuf(T0_64);
2559}
2560
2561void do_efdctsf (void)
2562{
2563 T0_64 = _do_efdctsf(T0_64);
2564}
2565
2566void do_efdctuf (void)
2567{
2568 T0_64 = _do_efdctuf(T0_64);
2569}
2570
2571void do_efdctsfz (void)
2572{
2573 T0_64 = _do_efdctsfz(T0_64);
2574}
2575
2576void do_efdctufz (void)
2577{
2578 T0_64 = _do_efdctufz(T0_64);
2579}
2580
2581/* Floating point conversion between single and double precision */
b068d6a7 2582static always_inline uint32_t _do_efscfd (uint64_t val)
0487d6a8
JM		 2583{
2584 union {
2585 uint64_t u;
2586 float64 f;
2587 } u1;
2588 union {
2589 uint32_t u;
2590 float32 f;
2591 } u2;
2592
2593 u1.u = val;
2594 u2.f = float64_to_float32(u1.f, &env->spe_status);
2595
2596 return u2.u;
2597}
2598
b068d6a7 2599static always_inline uint64_t _do_efdcfs (uint32_t val)
0487d6a8
JM		 2600{
2601 union {
2602 uint64_t u;
2603 float64 f;
2604 } u2;
2605 union {
2606 uint32_t u;
2607 float32 f;
2608 } u1;
2609
2610 u1.u = val;
2611 u2.f = float32_to_float64(u1.f, &env->spe_status);
2612
2613 return u2.u;
2614}
2615
2616void do_efscfd (void)
2617{
2618 T0_64 = _do_efscfd(T0_64);
2619}
2620
2621void do_efdcfs (void)
2622{
2623 T0_64 = _do_efdcfs(T0_64);
2624}
2625
2626/* Single precision fixed-point vector arithmetic */
2627/* evfsabs */
2628DO_SPE_OP1(fsabs);
2629/* evfsnabs */
2630DO_SPE_OP1(fsnabs);
2631/* evfsneg */
2632DO_SPE_OP1(fsneg);
2633/* evfsadd */
2634DO_SPE_OP2(fsadd);
2635/* evfssub */
2636DO_SPE_OP2(fssub);
2637/* evfsmul */
2638DO_SPE_OP2(fsmul);
2639/* evfsdiv */
2640DO_SPE_OP2(fsdiv);
2641
2642/* Single-precision floating-point comparisons */
b068d6a7 2643static always_inline int _do_efscmplt (uint32_t op1, uint32_t op2)
0487d6a8
JM		 2644{
2645 /* XXX: TODO: test special values (NaN, infinites, ...) */
2646 return _do_efststlt(op1, op2);
2647}
2648
b068d6a7 2649static always_inline int _do_efscmpgt (uint32_t op1, uint32_t op2)
0487d6a8
JM		 2650{
2651 /* XXX: TODO: test special values (NaN, infinites, ...) */
2652 return _do_efststgt(op1, op2);
2653}
2654
b068d6a7 2655static always_inline int _do_efscmpeq (uint32_t op1, uint32_t op2)
0487d6a8
JM		 2656{
2657 /* XXX: TODO: test special values (NaN, infinites, ...) */
2658 return _do_efststeq(op1, op2);
2659}
2660
2661void do_efscmplt (void)
2662{
2663 T0 = _do_efscmplt(T0_64, T1_64);
2664}
2665
2666void do_efscmpgt (void)
2667{
2668 T0 = _do_efscmpgt(T0_64, T1_64);
2669}
2670
2671void do_efscmpeq (void)
2672{
2673 T0 = _do_efscmpeq(T0_64, T1_64);
2674}
2675
2676/* Single-precision floating-point vector comparisons */
2677/* evfscmplt */
2678DO_SPE_CMP(fscmplt);
2679/* evfscmpgt */
2680DO_SPE_CMP(fscmpgt);
2681/* evfscmpeq */
2682DO_SPE_CMP(fscmpeq);
2683/* evfststlt */
2684DO_SPE_CMP(fststlt);
2685/* evfststgt */
2686DO_SPE_CMP(fststgt);
2687/* evfststeq */
2688DO_SPE_CMP(fststeq);
2689
2690/* Single-precision floating-point vector conversions */
2691/* evfscfsi */
2692DO_SPE_OP1(fscfsi);
2693/* evfscfui */
2694DO_SPE_OP1(fscfui);
2695/* evfscfuf */
2696DO_SPE_OP1(fscfuf);
2697/* evfscfsf */
2698DO_SPE_OP1(fscfsf);
2699/* evfsctsi */
2700DO_SPE_OP1(fsctsi);
2701/* evfsctui */
2702DO_SPE_OP1(fsctui);
2703/* evfsctsiz */
2704DO_SPE_OP1(fsctsiz);
2705/* evfsctuiz */
2706DO_SPE_OP1(fsctuiz);
2707/* evfsctsf */
2708DO_SPE_OP1(fsctsf);
2709/* evfsctuf */
2710DO_SPE_OP1(fsctuf);
35cdaad6 2711#endif /* defined(TARGET_PPCEMB) */
0487d6a8 2712
fdabc366
FB		 2713/*****************************************************************************/
2714/* Softmmu support */
2715#if !defined (CONFIG_USER_ONLY)
2716
2717#define MMUSUFFIX _mmu
273af660
TS		 2718#ifdef __s390__
2719# define GETPC() ((void*)((unsigned long)__builtin_return_address(0) & 0x7fffffffUL))
2720#else
2721# define GETPC() (__builtin_return_address(0))
2722#endif
fdabc366
FB		 2723
2724#define SHIFT 0
2725#include "softmmu_template.h"
2726
2727#define SHIFT 1
2728#include "softmmu_template.h"
2729
2730#define SHIFT 2
2731#include "softmmu_template.h"
2732
2733#define SHIFT 3
2734#include "softmmu_template.h"
2735
2736/* try to fill the TLB and return an exception if error. If retaddr is
2737 NULL, it means that the function was called in C code (i.e. not
2738 from generated code or from helper.c) */
2739/* XXX: fix it to restore all registers */
6ebbf390 2740void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
fdabc366
FB		 2741{
2742 TranslationBlock *tb;
2743 CPUState *saved_env;
2744 target_phys_addr_t pc;
2745 int ret;
2746
2747 /* XXX: hack to restore env in all cases, even if not called from
2748 generated code */
2749 saved_env = env;
2750 env = cpu_single_env;
6ebbf390 2751 ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
76a66253 2752 if (unlikely(ret != 0)) {
fdabc366
FB		 2753 if (likely(retaddr)) {
2754 /* now we have a real cpu fault */
a750fc0b 2755 pc = (target_phys_addr_t)(unsigned long)retaddr;
fdabc366
FB		 2756 tb = tb_find_pc(pc);
2757 if (likely(tb)) {
2758 /* the PC is inside the translated code. It means that we have
2759 a virtual CPU fault */
2760 cpu_restore_state(tb, env, pc, NULL);
76a66253 2761 }
fdabc366
FB		 2762 }
2763 do_raise_exception_err(env->exception_index, env->error_code);
2764 }
2765 env = saved_env;
9a64fbe4
FB		 2766}
2767
76a66253
JM		 2768/* Software driven TLBs management */
2769/* PowerPC 602/603 software TLB load instructions helpers */
2770void do_load_6xx_tlb (int is_code)
2771{
2772 target_ulong RPN, CMP, EPN;
2773 int way;
d9bce9d9 2774
76a66253
JM		 2775 RPN = env->spr[SPR_RPA];
2776 if (is_code) {
2777 CMP = env->spr[SPR_ICMP];
2778 EPN = env->spr[SPR_IMISS];
2779 } else {
2780 CMP = env->spr[SPR_DCMP];
2781 EPN = env->spr[SPR_DMISS];
2782 }
2783 way = (env->spr[SPR_SRR1] >> 17) & 1;
2784#if defined (DEBUG_SOFTWARE_TLB)
2785 if (loglevel != 0) {
2786 fprintf(logfile, "%s: EPN %08lx %08lx PTE0 %08lx PTE1 %08lx way %d\n",
2787 __func__, (unsigned long)T0, (unsigned long)EPN,
2788 (unsigned long)CMP, (unsigned long)RPN, way);
2789 }
2790#endif
2791 /* Store this TLB */
d9bce9d9
JM		 2792 ppc6xx_tlb_store(env, (uint32_t)(T0 & TARGET_PAGE_MASK),
2793 way, is_code, CMP, RPN);
76a66253
JM		 2794}
2795
7dbe11ac
JM		 2796void do_load_74xx_tlb (int is_code)
2797{
2798 target_ulong RPN, CMP, EPN;
2799 int way;
2800
2801 RPN = env->spr[SPR_PTELO];
2802 CMP = env->spr[SPR_PTEHI];
2803 EPN = env->spr[SPR_TLBMISS] & ~0x3;
2804 way = env->spr[SPR_TLBMISS] & 0x3;
2805#if defined (DEBUG_SOFTWARE_TLB)
2806 if (loglevel != 0) {
2807 fprintf(logfile, "%s: EPN %08lx %08lx PTE0 %08lx PTE1 %08lx way %d\n",
2808 __func__, (unsigned long)T0, (unsigned long)EPN,
2809 (unsigned long)CMP, (unsigned long)RPN, way);
2810 }
2811#endif
2812 /* Store this TLB */
2813 ppc6xx_tlb_store(env, (uint32_t)(T0 & TARGET_PAGE_MASK),
2814 way, is_code, CMP, RPN);
2815}
2816
a11b8151 2817static always_inline target_ulong booke_tlb_to_page_size (int size)
a8dea12f
JM		 2818{
2819 return 1024 << (2 * size);
2820}
2821
a11b8151 2822static always_inline int booke_page_size_to_tlb (target_ulong page_size)
a8dea12f
JM		 2823{
2824 int size;
2825
2826 switch (page_size) {
2827 case 0x00000400UL:
2828 size = 0x0;
2829 break;
2830 case 0x00001000UL:
2831 size = 0x1;
2832 break;
2833 case 0x00004000UL:
2834 size = 0x2;
2835 break;
2836 case 0x00010000UL:
2837 size = 0x3;
2838 break;
2839 case 0x00040000UL:
2840 size = 0x4;
2841 break;
2842 case 0x00100000UL:
2843 size = 0x5;
2844 break;
2845 case 0x00400000UL:
2846 size = 0x6;
2847 break;
2848 case 0x01000000UL:
2849 size = 0x7;
2850 break;
2851 case 0x04000000UL:
2852 size = 0x8;
2853 break;
2854 case 0x10000000UL:
2855 size = 0x9;
2856 break;
2857 case 0x40000000UL:
2858 size = 0xA;
2859 break;
2860#if defined (TARGET_PPC64)
2861 case 0x000100000000ULL:
2862 size = 0xB;
2863 break;
2864 case 0x000400000000ULL:
2865 size = 0xC;
2866 break;
2867 case 0x001000000000ULL:
2868 size = 0xD;
2869 break;
2870 case 0x004000000000ULL:
2871 size = 0xE;
2872 break;
2873 case 0x010000000000ULL:
2874 size = 0xF;
2875 break;
2876#endif
2877 default:
2878 size = -1;
2879 break;
2880 }
2881
2882 return size;
2883}
2884
76a66253 2885/* Helpers for 4xx TLB management */
76a66253
JM		 2886void do_4xx_tlbre_lo (void)
2887{
a8dea12f
JM		 2888 ppcemb_tlb_t *tlb;
2889 int size;
76a66253
JM		 2890
2891 T0 &= 0x3F;
a8dea12f
JM		 2892 tlb = &env->tlb[T0].tlbe;
2893 T0 = tlb->EPN;
2894 if (tlb->prot & PAGE_VALID)
2895 T0 |= 0x400;
2896 size = booke_page_size_to_tlb(tlb->size);
2897 if (size < 0 || size > 0x7)
2898 size = 1;
2899 T0 |= size << 7;
2900 env->spr[SPR_40x_PID] = tlb->PID;
76a66253
JM		 2901}
2902
2903void do_4xx_tlbre_hi (void)
2904{
a8dea12f 2905 ppcemb_tlb_t *tlb;
76a66253
JM		 2906
2907 T0 &= 0x3F;
a8dea12f
JM		 2908 tlb = &env->tlb[T0].tlbe;
2909 T0 = tlb->RPN;
2910 if (tlb->prot & PAGE_EXEC)
2911 T0 |= 0x200;
2912 if (tlb->prot & PAGE_WRITE)
2913 T0 |= 0x100;
76a66253
JM		 2914}
2915
c55e9aef 2916void do_4xx_tlbwe_hi (void)
76a66253 2917{
a8dea12f 2918 ppcemb_tlb_t *tlb;
76a66253
JM		 2919 target_ulong page, end;
2920
c55e9aef 2921#if defined (DEBUG_SOFTWARE_TLB)
6b80055d 2922 if (loglevel != 0) {
c55e9aef
JM		 2923 fprintf(logfile, "%s T0 " REGX " T1 " REGX "\n", __func__, T0, T1);
2924 }
2925#endif
76a66253 2926 T0 &= 0x3F;
a8dea12f 2927 tlb = &env->tlb[T0].tlbe;
76a66253
JM		 2928 /* Invalidate previous TLB (if it's valid) */
2929 if (tlb->prot & PAGE_VALID) {
2930 end = tlb->EPN + tlb->size;
c55e9aef 2931#if defined (DEBUG_SOFTWARE_TLB)
6b80055d 2932 if (loglevel != 0) {
c55e9aef
JM		 2933 fprintf(logfile, "%s: invalidate old TLB %d start " ADDRX
2934 " end " ADDRX "\n", __func__, (int)T0, tlb->EPN, end);
2935 }
2936#endif
76a66253
JM		 2937 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2938 tlb_flush_page(env, page);
2939 }
a8dea12f 2940 tlb->size = booke_tlb_to_page_size((T1 >> 7) & 0x7);
c294fc58
JM		 2941 /* We cannot handle TLB size < TARGET_PAGE_SIZE.
2942 * If this ever occurs, one should use the ppcemb target instead
2943 * of the ppc or ppc64 one
2944 */
2945 if ((T1 & 0x40) && tlb->size < TARGET_PAGE_SIZE) {
71c8b8fd
JM		 2946 cpu_abort(env, "TLB size " TARGET_FMT_lu " < %u "
2947 "are not supported (%d)\n",
c294fc58
JM		 2948 tlb->size, TARGET_PAGE_SIZE, (int)((T1 >> 7) & 0x7));
2949 }
a750fc0b 2950 tlb->EPN = T1 & ~(tlb->size - 1);
c55e9aef 2951 if (T1 & 0x40)
76a66253
JM		 2952 tlb->prot |= PAGE_VALID;
2953 else
2954 tlb->prot &= ~PAGE_VALID;
c294fc58
JM		 2955 if (T1 & 0x20) {
2956 /* XXX: TO BE FIXED */
2957 cpu_abort(env, "Little-endian TLB entries are not supported by now\n");
2958 }
c55e9aef 2959 tlb->PID = env->spr[SPR_40x_PID]; /* PID */
a8dea12f 2960 tlb->attr = T1 & 0xFF;
c55e9aef 2961#if defined (DEBUG_SOFTWARE_TLB)
c294fc58
JM		 2962 if (loglevel != 0) {
2963 fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
c55e9aef 2964 " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
5fafdf24 2965 (int)T0, tlb->RPN, tlb->EPN, tlb->size,
c55e9aef
JM		 2966 tlb->prot & PAGE_READ ? 'r' : '-',
2967 tlb->prot & PAGE_WRITE ? 'w' : '-',
2968 tlb->prot & PAGE_EXEC ? 'x' : '-',
2969 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
2970 }
2971#endif
76a66253
JM		 2972 /* Invalidate new TLB (if valid) */
2973 if (tlb->prot & PAGE_VALID) {
2974 end = tlb->EPN + tlb->size;
c55e9aef 2975#if defined (DEBUG_SOFTWARE_TLB)
6b80055d 2976 if (loglevel != 0) {
c55e9aef
JM		 2977 fprintf(logfile, "%s: invalidate TLB %d start " ADDRX
2978 " end " ADDRX "\n", __func__, (int)T0, tlb->EPN, end);
2979 }
2980#endif
76a66253
JM		 2981 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2982 tlb_flush_page(env, page);
2983 }
76a66253
JM		 2984}
2985
c55e9aef 2986void do_4xx_tlbwe_lo (void)
76a66253 2987{
a8dea12f 2988 ppcemb_tlb_t *tlb;
76a66253 2989
c55e9aef 2990#if defined (DEBUG_SOFTWARE_TLB)
6b80055d 2991 if (loglevel != 0) {
c55e9aef
JM		 2992 fprintf(logfile, "%s T0 " REGX " T1 " REGX "\n", __func__, T0, T1);
2993 }
2994#endif
76a66253 2995 T0 &= 0x3F;
a8dea12f 2996 tlb = &env->tlb[T0].tlbe;
76a66253
JM		 2997 tlb->RPN = T1 & 0xFFFFFC00;
2998 tlb->prot = PAGE_READ;
2999 if (T1 & 0x200)
3000 tlb->prot |= PAGE_EXEC;
3001 if (T1 & 0x100)
3002 tlb->prot |= PAGE_WRITE;
c55e9aef 3003#if defined (DEBUG_SOFTWARE_TLB)
6b80055d
JM		 3004 if (loglevel != 0) {
3005 fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
c55e9aef 3006 " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
5fafdf24 3007 (int)T0, tlb->RPN, tlb->EPN, tlb->size,
c55e9aef
JM		 3008 tlb->prot & PAGE_READ ? 'r' : '-',
3009 tlb->prot & PAGE_WRITE ? 'w' : '-',
3010 tlb->prot & PAGE_EXEC ? 'x' : '-',
3011 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
3012 }
3013#endif
76a66253 3014}
5eb7995e 3015
a4bb6c3e
JM		 3016/* PowerPC 440 TLB management */
3017void do_440_tlbwe (int word)
5eb7995e
JM		 3018{
3019 ppcemb_tlb_t *tlb;
a4bb6c3e 3020 target_ulong EPN, RPN, size;
5eb7995e
JM		 3021 int do_flush_tlbs;
3022
3023#if defined (DEBUG_SOFTWARE_TLB)
3024 if (loglevel != 0) {
a4bb6c3e
JM		 3025 fprintf(logfile, "%s word %d T0 " REGX " T1 " REGX "\n",
3026 __func__, word, T0, T1);
5eb7995e
JM		 3027 }
3028#endif
3029 do_flush_tlbs = 0;
3030 T0 &= 0x3F;
3031 tlb = &env->tlb[T0].tlbe;
a4bb6c3e
JM		 3032 switch (word) {
3033 default:
3034 /* Just here to please gcc */
3035 case 0:
3036 EPN = T1 & 0xFFFFFC00;
3037 if ((tlb->prot & PAGE_VALID) && EPN != tlb->EPN)
5eb7995e 3038 do_flush_tlbs = 1;
a4bb6c3e
JM		 3039 tlb->EPN = EPN;
3040 size = booke_tlb_to_page_size((T1 >> 4) & 0xF);
3041 if ((tlb->prot & PAGE_VALID) && tlb->size < size)
3042 do_flush_tlbs = 1;
3043 tlb->size = size;
3044 tlb->attr &= ~0x1;
3045 tlb->attr |= (T1 >> 8) & 1;
3046 if (T1 & 0x200) {
3047 tlb->prot |= PAGE_VALID;
3048 } else {
3049 if (tlb->prot & PAGE_VALID) {
3050 tlb->prot &= ~PAGE_VALID;
3051 do_flush_tlbs = 1;
3052 }
5eb7995e 3053 }
a4bb6c3e
JM		 3054 tlb->PID = env->spr[SPR_440_MMUCR] & 0x000000FF;
3055 if (do_flush_tlbs)
3056 tlb_flush(env, 1);
3057 break;
3058 case 1:
3059 RPN = T1 & 0xFFFFFC0F;
3060 if ((tlb->prot & PAGE_VALID) && tlb->RPN != RPN)
3061 tlb_flush(env, 1);
3062 tlb->RPN = RPN;
3063 break;
3064 case 2:
3065 tlb->attr = (tlb->attr & 0x1) | (T1 & 0x0000FF00);
3066 tlb->prot = tlb->prot & PAGE_VALID;
3067 if (T1 & 0x1)
3068 tlb->prot |= PAGE_READ << 4;
3069 if (T1 & 0x2)
3070 tlb->prot |= PAGE_WRITE << 4;
3071 if (T1 & 0x4)
3072 tlb->prot |= PAGE_EXEC << 4;
3073 if (T1 & 0x8)
3074 tlb->prot |= PAGE_READ;
3075 if (T1 & 0x10)
3076 tlb->prot |= PAGE_WRITE;
3077 if (T1 & 0x20)
3078 tlb->prot |= PAGE_EXEC;
3079 break;
5eb7995e 3080 }
5eb7995e
JM		 3081}
3082
a4bb6c3e 3083void do_440_tlbre (int word)
5eb7995e
JM		 3084{
3085 ppcemb_tlb_t *tlb;
3086 int size;
3087
3088 T0 &= 0x3F;
3089 tlb = &env->tlb[T0].tlbe;
a4bb6c3e
JM		 3090 switch (word) {
3091 default:
3092 /* Just here to please gcc */
3093 case 0:
3094 T0 = tlb->EPN;
3095 size = booke_page_size_to_tlb(tlb->size);
3096 if (size < 0 || size > 0xF)
3097 size = 1;
3098 T0 |= size << 4;
3099 if (tlb->attr & 0x1)
3100 T0 |= 0x100;
3101 if (tlb->prot & PAGE_VALID)
3102 T0 |= 0x200;
3103 env->spr[SPR_440_MMUCR] &= ~0x000000FF;
3104 env->spr[SPR_440_MMUCR] |= tlb->PID;
3105 break;
3106 case 1:
3107 T0 = tlb->RPN;
3108 break;
3109 case 2:
3110 T0 = tlb->attr & ~0x1;
3111 if (tlb->prot & (PAGE_READ << 4))
3112 T0 |= 0x1;
3113 if (tlb->prot & (PAGE_WRITE << 4))
3114 T0 |= 0x2;
3115 if (tlb->prot & (PAGE_EXEC << 4))
3116 T0 |= 0x4;
3117 if (tlb->prot & PAGE_READ)
3118 T0 |= 0x8;
3119 if (tlb->prot & PAGE_WRITE)
3120 T0 |= 0x10;
3121 if (tlb->prot & PAGE_EXEC)
3122 T0 |= 0x20;
3123 break;
3124 }
5eb7995e 3125}
76a66253 3126#endif /* !CONFIG_USER_ONLY */
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