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5391d806 1/*
38cdea7c 2 * QEMU IDE disk and CD/DVD-ROM Emulator
5fafdf24 3 *
5391d806 4 * Copyright (c) 2003 Fabrice Bellard
201a51fc 5 * Copyright (c) 2006 Openedhand Ltd.
5fafdf24 6 *
5391d806
FB		 7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
e688df6b 25
53239262 26#include "qemu/osdep.h"
a9c94277 27#include "hw/isa/isa.h"
d6454270 28#include "migration/vmstate.h"
1de7afc9 29#include "qemu/error-report.h"
db725815 30#include "qemu/main-loop.h"
1de7afc9 31#include "qemu/timer.h"
9c17d615 32#include "sysemu/sysemu.h"
78631611 33#include "sysemu/blockdev.h"
9c17d615 34#include "sysemu/dma.h"
0d09e41a 35#include "hw/block/block.h"
4be74634 36#include "sysemu/block-backend.h"
e688df6b 37#include "qapi/error.h"
f348b6d1 38#include "qemu/cutils.h"
b255df7e 39#include "sysemu/replay.h"
59f2a787 40
a9c94277 41#include "hw/ide/internal.h"
3eee2611 42#include "trace.h"
e8b54394 43
b93af93d
BW		 44/* These values were based on a Seagate ST3500418AS but have been modified
45 to make more sense in QEMU */
46static const int smart_attributes[][12] = {
47 /* id, flags, hflags, val, wrst, raw (6 bytes), threshold */
48 /* raw read error rate*/
49 { 0x01, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06},
50 /* spin up */
51 { 0x03, 0x03, 0x00, 0x64, 0x64, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
52 /* start stop count */
53 { 0x04, 0x02, 0x00, 0x64, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14},
54 /* remapped sectors */
55 { 0x05, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x24},
56 /* power on hours */
57 { 0x09, 0x03, 0x00, 0x64, 0x64, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
58 /* power cycle count */
59 { 0x0c, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
60 /* airflow-temperature-celsius */
61 { 190, 0x03, 0x00, 0x45, 0x45, 0x1f, 0x00, 0x1f, 0x1f, 0x00, 0x00, 0x32},
e8b54394
BW		 62};
63
0e168d35
JS		 64const char *IDE_DMA_CMD_lookup[IDE_DMA__COUNT] = {
65 [IDE_DMA_READ] = "DMA READ",
66 [IDE_DMA_WRITE] = "DMA WRITE",
67 [IDE_DMA_TRIM] = "DMA TRIM",
68 [IDE_DMA_ATAPI] = "DMA ATAPI"
69};
70
71static const char *IDE_DMA_CMD_str(enum ide_dma_cmd enval)
72{
159a9df0 73 if ((unsigned)enval < IDE_DMA__COUNT) {
0e168d35
JS		 74 return IDE_DMA_CMD_lookup[enval];
75 }
76 return "DMA UNKNOWN CMD";
77}
78
40c4ed3f 79static void ide_dummy_transfer_stop(IDEState *s);
98087450 80
5391d806
FB		 81static void padstr(char *str, const char *src, int len)
82{
83 int i, v;
84 for(i = 0; i < len; i++) {
85 if (*src)
86 v = *src++;
87 else
88 v = ' ';
69b34976 89 str[i^1] = v;
5391d806
FB		 90 }
91}
92
67b915a5
FB		 93static void put_le16(uint16_t *p, unsigned int v)
94{
0c4ad8dc 95 *p = cpu_to_le16(v);
67b915a5
FB		 96}
97
01ce352e
JS		 98static void ide_identify_size(IDEState *s)
99{
100 uint16_t *p = (uint16_t *)s->identify_data;
101 put_le16(p + 60, s->nb_sectors);
102 put_le16(p + 61, s->nb_sectors >> 16);
103 put_le16(p + 100, s->nb_sectors);
104 put_le16(p + 101, s->nb_sectors >> 16);
105 put_le16(p + 102, s->nb_sectors >> 32);
106 put_le16(p + 103, s->nb_sectors >> 48);
107}
108
5391d806
FB		 109static void ide_identify(IDEState *s)
110{
111 uint16_t *p;
112 unsigned int oldsize;
d353fb72 113 IDEDevice *dev = s->unit ? s->bus->slave : s->bus->master;
5391d806 114
4bf6637d 115 p = (uint16_t *)s->identify_data;
94458802 116 if (s->identify_set) {
4bf6637d 117 goto fill_buffer;
94458802 118 }
4bf6637d 119 memset(p, 0, sizeof(s->identify_data));
94458802 120
67b915a5 121 put_le16(p + 0, 0x0040);
5fafdf24 122 put_le16(p + 1, s->cylinders);
67b915a5
FB		 123 put_le16(p + 3, s->heads);
124 put_le16(p + 4, 512 * s->sectors); /* XXX: retired, remove ? */
125 put_le16(p + 5, 512); /* XXX: retired, remove ? */
5fafdf24 126 put_le16(p + 6, s->sectors);
fa879c64 127 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
67b915a5
FB		 128 put_le16(p + 20, 3); /* XXX: retired, remove ? */
129 put_le16(p + 21, 512); /* cache size in sectors */
130 put_le16(p + 22, 4); /* ecc bytes */
47c06340 131 padstr((char *)(p + 23), s->version, 8); /* firmware version */
27e0c9a1 132 padstr((char *)(p + 27), s->drive_model_str, 40); /* model */
3b46e624 133#if MAX_MULT_SECTORS > 1
67b915a5 134 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
5391d806 135#endif
67b915a5 136 put_le16(p + 48, 1); /* dword I/O */
94458802 137 put_le16(p + 49, (1 << 11) | (1 << 9) | (1 << 8)); /* DMA and LBA supported */
67b915a5
FB		 138 put_le16(p + 51, 0x200); /* PIO transfer cycle */
139 put_le16(p + 52, 0x200); /* DMA transfer cycle */
94458802 140 put_le16(p + 53, 1 | (1 << 1) | (1 << 2)); /* words 54-58,64-70,88 are valid */
67b915a5
FB		 141 put_le16(p + 54, s->cylinders);
142 put_le16(p + 55, s->heads);
143 put_le16(p + 56, s->sectors);
5391d806 144 oldsize = s->cylinders * s->heads * s->sectors;
67b915a5
FB		 145 put_le16(p + 57, oldsize);
146 put_le16(p + 58, oldsize >> 16);
5391d806 147 if (s->mult_sectors)
67b915a5 148 put_le16(p + 59, 0x100 | s->mult_sectors);
01ce352e
JS		 149 /* *(p + 60) := nb_sectors -- see ide_identify_size */
150 /* *(p + 61) := nb_sectors >> 16 -- see ide_identify_size */
d1b5c20d 151 put_le16(p + 62, 0x07); /* single word dma0-2 supported */
94458802 152 put_le16(p + 63, 0x07); /* mdma0-2 supported */
79d1d331 153 put_le16(p + 64, 0x03); /* pio3-4 supported */
94458802
FB		 154 put_le16(p + 65, 120);
155 put_le16(p + 66, 120);
156 put_le16(p + 67, 120);
157 put_le16(p + 68, 120);
d353fb72
CH		 158 if (dev && dev->conf.discard_granularity) {
159 put_le16(p + 69, (1 << 14)); /* determinate TRIM behavior */
160 }
ccf0fd8b
RE		 161
162 if (s->ncq_queues) {
163 put_le16(p + 75, s->ncq_queues - 1);
164 /* NCQ supported */
165 put_le16(p + 76, (1 << 8));
166 }
167
94458802
FB		 168 put_le16(p + 80, 0xf0); /* ata3 -> ata6 supported */
169 put_le16(p + 81, 0x16); /* conforms to ata5 */
a58b8d54
CH		 170 /* 14=NOP supported, 5=WCACHE supported, 0=SMART supported */
171 put_le16(p + 82, (1 << 14) | (1 << 5) | 1);
c2ff060f
FB		 172 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
173 put_le16(p + 83, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10));
95ebda85
FB		 174 /* 14=set to 1, 8=has WWN, 1=SMART self test, 0=SMART error logging */
175 if (s->wwn) {
176 put_le16(p + 84, (1 << 14) | (1 << 8) | 0);
177 } else {
178 put_le16(p + 84, (1 << 14) | 0);
179 }
e900a7b7 180 /* 14 = NOP supported, 5=WCACHE enabled, 0=SMART feature set enabled */
4be74634
MA		 181 if (blk_enable_write_cache(s->blk)) {
182 put_le16(p + 85, (1 << 14) | (1 << 5) | 1);
183 } else {
184 put_le16(p + 85, (1 << 14) | 1);
185 }
c2ff060f 186 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
2844bdd9 187 put_le16(p + 86, (1 << 13) | (1 <<12) | (1 << 10));
95ebda85
FB		 188 /* 14=set to 1, 8=has WWN, 1=SMART self test, 0=SMART error logging */
189 if (s->wwn) {
190 put_le16(p + 87, (1 << 14) | (1 << 8) | 0);
191 } else {
192 put_le16(p + 87, (1 << 14) | 0);
193 }
94458802
FB		 194 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
195 put_le16(p + 93, 1 | (1 << 14) | 0x2000);
01ce352e
JS		 196 /* *(p + 100) := nb_sectors -- see ide_identify_size */
197 /* *(p + 101) := nb_sectors >> 16 -- see ide_identify_size */
198 /* *(p + 102) := nb_sectors >> 32 -- see ide_identify_size */
199 /* *(p + 103) := nb_sectors >> 48 -- see ide_identify_size */
d353fb72 200
57dac7ef
MA		 201 if (dev && dev->conf.physical_block_size)
202 put_le16(p + 106, 0x6000 | get_physical_block_exp(&dev->conf));
95ebda85
FB		 203 if (s->wwn) {
204 /* LE 16-bit words 111-108 contain 64-bit World Wide Name */
205 put_le16(p + 108, s->wwn >> 48);
206 put_le16(p + 109, s->wwn >> 32);
207 put_le16(p + 110, s->wwn >> 16);
208 put_le16(p + 111, s->wwn);
209 }
d353fb72
CH		 210 if (dev && dev->conf.discard_granularity) {
211 put_le16(p + 169, 1); /* TRIM support */
212 }
96f43c2b
DB		 213 if (dev) {
214 put_le16(p + 217, dev->rotation_rate); /* Nominal media rotation rate */
215 }
94458802 216
01ce352e 217 ide_identify_size(s);
94458802 218 s->identify_set = 1;
4bf6637d
JS		 219
220fill_buffer:
221 memcpy(s->io_buffer, p, sizeof(s->identify_data));
5391d806
FB		 222}
223
224static void ide_atapi_identify(IDEState *s)
225{
226 uint16_t *p;
227
4bf6637d 228 p = (uint16_t *)s->identify_data;
94458802 229 if (s->identify_set) {
4bf6637d 230 goto fill_buffer;
94458802 231 }
4bf6637d 232 memset(p, 0, sizeof(s->identify_data));
94458802 233
5391d806 234 /* Removable CDROM, 50us response, 12 byte packets */
67b915a5 235 put_le16(p + 0, (2 << 14) | (5 << 8) | (1 << 7) | (2 << 5) | (0 << 0));
fa879c64 236 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
67b915a5
FB		 237 put_le16(p + 20, 3); /* buffer type */
238 put_le16(p + 21, 512); /* cache size in sectors */
239 put_le16(p + 22, 4); /* ecc bytes */
47c06340 240 padstr((char *)(p + 23), s->version, 8); /* firmware version */
27e0c9a1 241 padstr((char *)(p + 27), s->drive_model_str, 40); /* model */
67b915a5 242 put_le16(p + 48, 1); /* dword I/O (XXX: should not be set on CDROM) */
8ccad811
FB		 243#ifdef USE_DMA_CDROM
244 put_le16(p + 49, 1 << 9 | 1 << 8); /* DMA and LBA supported */
245 put_le16(p + 53, 7); /* words 64-70, 54-58, 88 valid */
d1b5c20d 246 put_le16(p + 62, 7); /* single word dma0-2 supported */
8ccad811 247 put_le16(p + 63, 7); /* mdma0-2 supported */
8ccad811 248#else
67b915a5
FB		 249 put_le16(p + 49, 1 << 9); /* LBA supported, no DMA */
250 put_le16(p + 53, 3); /* words 64-70, 54-58 valid */
251 put_le16(p + 63, 0x103); /* DMA modes XXX: may be incorrect */
8ccad811 252#endif
79d1d331 253 put_le16(p + 64, 3); /* pio3-4 supported */
67b915a5
FB		 254 put_le16(p + 65, 0xb4); /* minimum DMA multiword tx cycle time */
255 put_le16(p + 66, 0xb4); /* recommended DMA multiword tx cycle time */
256 put_le16(p + 67, 0x12c); /* minimum PIO cycle time without flow control */
257 put_le16(p + 68, 0xb4); /* minimum PIO cycle time with IORDY flow control */
94458802 258
67b915a5
FB		 259 put_le16(p + 71, 30); /* in ns */
260 put_le16(p + 72, 30); /* in ns */
5391d806 261
1bdaa28d
AG		 262 if (s->ncq_queues) {
263 put_le16(p + 75, s->ncq_queues - 1);
264 /* NCQ supported */
265 put_le16(p + 76, (1 << 8));
266 }
267
67b915a5 268 put_le16(p + 80, 0x1e); /* support up to ATA/ATAPI-4 */
c5fe97e3
JS		 269 if (s->wwn) {
270 put_le16(p + 84, (1 << 8)); /* supports WWN for words 108-111 */
271 put_le16(p + 87, (1 << 8)); /* WWN enabled */
272 }
273
8ccad811
FB		 274#ifdef USE_DMA_CDROM
275 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
276#endif
c5fe97e3
JS		 277
278 if (s->wwn) {
279 /* LE 16-bit words 111-108 contain 64-bit World Wide Name */
280 put_le16(p + 108, s->wwn >> 48);
281 put_le16(p + 109, s->wwn >> 32);
282 put_le16(p + 110, s->wwn >> 16);
283 put_le16(p + 111, s->wwn);
284 }
285
94458802 286 s->identify_set = 1;
4bf6637d
JS		 287
288fill_buffer:
289 memcpy(s->io_buffer, p, sizeof(s->identify_data));
5391d806
FB		 290}
291
01ce352e
JS		 292static void ide_cfata_identify_size(IDEState *s)
293{
294 uint16_t *p = (uint16_t *)s->identify_data;
295 put_le16(p + 7, s->nb_sectors >> 16); /* Sectors per card */
296 put_le16(p + 8, s->nb_sectors); /* Sectors per card */
297 put_le16(p + 60, s->nb_sectors); /* Total LBA sectors */
298 put_le16(p + 61, s->nb_sectors >> 16); /* Total LBA sectors */
299}
300
201a51fc
AZ		 301static void ide_cfata_identify(IDEState *s)
302{
303 uint16_t *p;
304 uint32_t cur_sec;
201a51fc 305
4bf6637d
JS		 306 p = (uint16_t *)s->identify_data;
307 if (s->identify_set) {
201a51fc 308 goto fill_buffer;
4bf6637d 309 }
201a51fc
AZ		 310 memset(p, 0, sizeof(s->identify_data));
311
312 cur_sec = s->cylinders * s->heads * s->sectors;
313
314 put_le16(p + 0, 0x848a); /* CF Storage Card signature */
315 put_le16(p + 1, s->cylinders); /* Default cylinders */
316 put_le16(p + 3, s->heads); /* Default heads */
317 put_le16(p + 6, s->sectors); /* Default sectors per track */
01ce352e
JS		 318 /* *(p + 7) := nb_sectors >> 16 -- see ide_cfata_identify_size */
319 /* *(p + 8) := nb_sectors -- see ide_cfata_identify_size */
fa879c64 320 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
201a51fc 321 put_le16(p + 22, 0x0004); /* ECC bytes */
47c06340 322 padstr((char *) (p + 23), s->version, 8); /* Firmware Revision */
27e0c9a1 323 padstr((char *) (p + 27), s->drive_model_str, 40);/* Model number */
201a51fc
AZ		 324#if MAX_MULT_SECTORS > 1
325 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
326#else
327 put_le16(p + 47, 0x0000);
328#endif
329 put_le16(p + 49, 0x0f00); /* Capabilities */
330 put_le16(p + 51, 0x0002); /* PIO cycle timing mode */
331 put_le16(p + 52, 0x0001); /* DMA cycle timing mode */
332 put_le16(p + 53, 0x0003); /* Translation params valid */
333 put_le16(p + 54, s->cylinders); /* Current cylinders */
334 put_le16(p + 55, s->heads); /* Current heads */
335 put_le16(p + 56, s->sectors); /* Current sectors */
336 put_le16(p + 57, cur_sec); /* Current capacity */
337 put_le16(p + 58, cur_sec >> 16); /* Current capacity */
338 if (s->mult_sectors) /* Multiple sector setting */
339 put_le16(p + 59, 0x100 | s->mult_sectors);
01ce352e
JS		 340 /* *(p + 60) := nb_sectors -- see ide_cfata_identify_size */
341 /* *(p + 61) := nb_sectors >> 16 -- see ide_cfata_identify_size */
201a51fc
AZ		 342 put_le16(p + 63, 0x0203); /* Multiword DMA capability */
343 put_le16(p + 64, 0x0001); /* Flow Control PIO support */
344 put_le16(p + 65, 0x0096); /* Min. Multiword DMA cycle */
345 put_le16(p + 66, 0x0096); /* Rec. Multiword DMA cycle */
346 put_le16(p + 68, 0x00b4); /* Min. PIO cycle time */
347 put_le16(p + 82, 0x400c); /* Command Set supported */
348 put_le16(p + 83, 0x7068); /* Command Set supported */
349 put_le16(p + 84, 0x4000); /* Features supported */
350 put_le16(p + 85, 0x000c); /* Command Set enabled */
351 put_le16(p + 86, 0x7044); /* Command Set enabled */
352 put_le16(p + 87, 0x4000); /* Features enabled */
353 put_le16(p + 91, 0x4060); /* Current APM level */
354 put_le16(p + 129, 0x0002); /* Current features option */
355 put_le16(p + 130, 0x0005); /* Reassigned sectors */
356 put_le16(p + 131, 0x0001); /* Initial power mode */
357 put_le16(p + 132, 0x0000); /* User signature */
358 put_le16(p + 160, 0x8100); /* Power requirement */
359 put_le16(p + 161, 0x8001); /* CF command set */
360
01ce352e 361 ide_cfata_identify_size(s);
201a51fc
AZ		 362 s->identify_set = 1;
363
364fill_buffer:
365 memcpy(s->io_buffer, p, sizeof(s->identify_data));
366}
367
5391d806
FB		 368static void ide_set_signature(IDEState *s)
369{
370 s->select &= 0xf0; /* clear head */
371 /* put signature */
372 s->nsector = 1;
373 s->sector = 1;
cd8722bb 374 if (s->drive_kind == IDE_CD) {
5391d806
FB		 375 s->lcyl = 0x14;
376 s->hcyl = 0xeb;
4be74634 377 } else if (s->blk) {
5391d806
FB		 378 s->lcyl = 0;
379 s->hcyl = 0;
380 } else {
381 s->lcyl = 0xff;
382 s->hcyl = 0xff;
383 }
384}
385
d8b070fe
AN		 386static bool ide_sect_range_ok(IDEState *s,
387 uint64_t sector, uint64_t nb_sectors)
388{
389 uint64_t total_sectors;
390
391 blk_get_geometry(s->blk, &total_sectors);
392 if (sector > total_sectors || nb_sectors > total_sectors - sector) {
393 return false;
394 }
395 return true;
396}
397
d353fb72 398typedef struct TrimAIOCB {
7c84b1b8 399 BlockAIOCB common;
ef0e64a9 400 IDEState *s;
d353fb72
CH		 401 QEMUBH *bh;
402 int ret;
501378c3 403 QEMUIOVector *qiov;
7c84b1b8 404 BlockAIOCB *aiocb;
501378c3 405 int i, j;
d353fb72
CH		 406} TrimAIOCB;
407
7c84b1b8 408static void trim_aio_cancel(BlockAIOCB *acb)
d353fb72
CH		 409{
410 TrimAIOCB *iocb = container_of(acb, TrimAIOCB, common);
411
e551c999 412 /* Exit the loop so ide_issue_trim_cb will not continue */
501378c3
PB		 413 iocb->j = iocb->qiov->niov - 1;
414 iocb->i = (iocb->qiov->iov[iocb->j].iov_len / 8) - 1;
415
e551c999 416 iocb->ret = -ECANCELED;
501378c3
PB		 417
418 if (iocb->aiocb) {
4be74634 419 blk_aio_cancel_async(iocb->aiocb);
e551c999 420 iocb->aiocb = NULL;
501378c3 421 }
d353fb72
CH		 422}
423
d7331bed 424static const AIOCBInfo trim_aiocb_info = {
d353fb72 425 .aiocb_size = sizeof(TrimAIOCB),
e551c999 426 .cancel_async = trim_aio_cancel,
d353fb72
CH		 427};
428
429static void ide_trim_bh_cb(void *opaque)
430{
431 TrimAIOCB *iocb = opaque;
432
caeadbc8
AN		 433 iocb->common.cb(iocb->common.opaque, iocb->ret);
434
d353fb72
CH		 435 qemu_bh_delete(iocb->bh);
436 iocb->bh = NULL;
8007429a 437 qemu_aio_unref(iocb);
d353fb72
CH		 438}
439
501378c3
PB		 440static void ide_issue_trim_cb(void *opaque, int ret)
441{
442 TrimAIOCB *iocb = opaque;
ef0e64a9
AN		 443 IDEState *s = iocb->s;
444
501378c3
PB		 445 if (ret >= 0) {
446 while (iocb->j < iocb->qiov->niov) {
447 int j = iocb->j;
448 while (++iocb->i < iocb->qiov->iov[j].iov_len / 8) {
449 int i = iocb->i;
450 uint64_t *buffer = iocb->qiov->iov[j].iov_base;
451
452 /* 6-byte LBA + 2-byte range per entry */
453 uint64_t entry = le64_to_cpu(buffer[i]);
454 uint64_t sector = entry & 0x0000ffffffffffffULL;
455 uint16_t count = entry >> 48;
456
457 if (count == 0) {
458 continue;
459 }
460
947858b0 461 if (!ide_sect_range_ok(s, sector, count)) {
caeadbc8 462 iocb->ret = -EINVAL;
947858b0
AN		 463 goto done;
464 }
465
501378c3 466 /* Got an entry! Submit and exit. */
ef0e64a9 467 iocb->aiocb = blk_aio_pdiscard(s->blk,
1c6c4bb7
EB		 468 sector << BDRV_SECTOR_BITS,
469 count << BDRV_SECTOR_BITS,
470 ide_issue_trim_cb, opaque);
501378c3
PB		 471 return;
472 }
473
474 iocb->j++;
475 iocb->i = -1;
476 }
477 } else {
478 iocb->ret = ret;
479 }
480
947858b0 481done:
501378c3
PB		 482 iocb->aiocb = NULL;
483 if (iocb->bh) {
b255df7e 484 replay_bh_schedule_event(iocb->bh);
501378c3
PB		 485 }
486}
487
8a8e63eb
PB		 488BlockAIOCB *ide_issue_trim(
489 int64_t offset, QEMUIOVector *qiov,
490 BlockCompletionFunc *cb, void *cb_opaque, void *opaque)
d353fb72 491{
ef0e64a9 492 IDEState *s = opaque;
d353fb72 493 TrimAIOCB *iocb;
d353fb72 494
ef0e64a9
AN		 495 iocb = blk_aio_get(&trim_aiocb_info, s->blk, cb, cb_opaque);
496 iocb->s = s;
d353fb72
CH		 497 iocb->bh = qemu_bh_new(ide_trim_bh_cb, iocb);
498 iocb->ret = 0;
501378c3
PB		 499 iocb->qiov = qiov;
500 iocb->i = -1;
501 iocb->j = 0;
502 ide_issue_trim_cb(iocb, 0);
d353fb72
CH		 503 return &iocb->common;
504}
505
9ef2e93f 506void ide_abort_command(IDEState *s)
5391d806 507{
08ee9e33 508 ide_transfer_stop(s);
5391d806
FB		 509 s->status = READY_STAT | ERR_STAT;
510 s->error = ABRT_ERR;
511}
512
0eeee07e
EY		 513static void ide_set_retry(IDEState *s)
514{
515 s->bus->retry_unit = s->unit;
516 s->bus->retry_sector_num = ide_get_sector(s);
517 s->bus->retry_nsector = s->nsector;
518}
519
520static void ide_clear_retry(IDEState *s)
521{
522 s->bus->retry_unit = -1;
523 s->bus->retry_sector_num = 0;
524 s->bus->retry_nsector = 0;
525}
526
5391d806 527/* prepare data transfer and tell what to do after */
c173723f
PB		 528bool ide_transfer_start_norecurse(IDEState *s, uint8_t *buf, int size,
529 EndTransferFunc *end_transfer_func)
5391d806 530{
5391d806
FB		 531 s->data_ptr = buf;
532 s->data_end = buf + size;
35f78ab4 533 ide_set_retry(s);
40a6238a 534 if (!(s->status & ERR_STAT)) {
7603d156 535 s->status |= DRQ_STAT;
40a6238a 536 }
bed9bcfa
PB		 537 if (!s->bus->dma->ops->pio_transfer) {
538 s->end_transfer_func = end_transfer_func;
c173723f 539 return false;
44635123 540 }
bed9bcfa 541 s->bus->dma->ops->pio_transfer(s->bus->dma);
c173723f
PB		 542 return true;
543}
544
545void ide_transfer_start(IDEState *s, uint8_t *buf, int size,
546 EndTransferFunc *end_transfer_func)
547{
548 if (ide_transfer_start_norecurse(s, buf, size, end_transfer_func)) {
549 end_transfer_func(s);
550 }
5391d806
FB		 551}
552
c7e73adb
PB		 553static void ide_cmd_done(IDEState *s)
554{
555 if (s->bus->dma->ops->cmd_done) {
556 s->bus->dma->ops->cmd_done(s->bus->dma);
557 }
558}
559
882941a5 560static void ide_transfer_halt(IDEState *s)
5391d806 561{
882941a5 562 s->end_transfer_func = ide_transfer_stop;
5391d806
FB		 563 s->data_ptr = s->io_buffer;
564 s->data_end = s->io_buffer;
565 s->status &= ~DRQ_STAT;
e3044e23
JS		 566}
567
568void ide_transfer_stop(IDEState *s)
569{
882941a5 570 ide_transfer_halt(s);
ee4cd662 571 ide_cmd_done(s);
e3044e23
JS		 572}
573
356721ae 574int64_t ide_get_sector(IDEState *s)
5391d806
FB		 575{
576 int64_t sector_num;
577 if (s->select & 0x40) {
578 /* lba */
7d37435b
PB		 579 if (!s->lba48) {
580 sector_num = ((s->select & 0x0f) << 24) | (s->hcyl << 16) |
581 (s->lcyl << 8) | s->sector;
582 } else {
583 sector_num = ((int64_t)s->hob_hcyl << 40) |
584 ((int64_t) s->hob_lcyl << 32) |
585 ((int64_t) s->hob_sector << 24) |
586 ((int64_t) s->hcyl << 16) |
587 ((int64_t) s->lcyl << 8) | s->sector;
588 }
5391d806
FB		 589 } else {
590 sector_num = ((s->hcyl << 8) | s->lcyl) * s->heads * s->sectors +
c2ff060f 591 (s->select & 0x0f) * s->sectors + (s->sector - 1);
5391d806
FB		 592 }
593 return sector_num;
594}
595
356721ae 596void ide_set_sector(IDEState *s, int64_t sector_num)
5391d806
FB		 597{
598 unsigned int cyl, r;
599 if (s->select & 0x40) {
7d37435b 600 if (!s->lba48) {
c2ff060f
FB		 601 s->select = (s->select & 0xf0) | (sector_num >> 24);
602 s->hcyl = (sector_num >> 16);
603 s->lcyl = (sector_num >> 8);
604 s->sector = (sector_num);
7d37435b
PB		 605 } else {
606 s->sector = sector_num;
607 s->lcyl = sector_num >> 8;
608 s->hcyl = sector_num >> 16;
609 s->hob_sector = sector_num >> 24;
610 s->hob_lcyl = sector_num >> 32;
611 s->hob_hcyl = sector_num >> 40;
612 }
5391d806
FB		 613 } else {
614 cyl = sector_num / (s->heads * s->sectors);
615 r = sector_num % (s->heads * s->sectors);
616 s->hcyl = cyl >> 8;
617 s->lcyl = cyl;
1b8eb456 618 s->select = (s->select & 0xf0) | ((r / s->sectors) & 0x0f);
5391d806
FB		 619 s->sector = (r % s->sectors) + 1;
620 }
621}
622
e162cfb0
AZ		 623static void ide_rw_error(IDEState *s) {
624 ide_abort_command(s);
9cdd03a7 625 ide_set_irq(s->bus);
e162cfb0
AZ		 626}
627
1d8c11d6
PL		 628static void ide_buffered_readv_cb(void *opaque, int ret)
629{
630 IDEBufferedRequest *req = opaque;
631 if (!req->orphaned) {
632 if (!ret) {
5bbe9325
VSO		 633 assert(req->qiov.size == req->original_qiov->size);
634 qemu_iovec_from_buf(req->original_qiov, 0,
635 req->qiov.local_iov.iov_base,
1d8c11d6
PL		 636 req->original_qiov->size);
637 }
638 req->original_cb(req->original_opaque, ret);
639 }
640 QLIST_REMOVE(req, list);
5bbe9325 641 qemu_vfree(qemu_iovec_buf(&req->qiov));
1d8c11d6
PL		 642 g_free(req);
643}
644
645#define MAX_BUFFERED_REQS 16
646
647BlockAIOCB *ide_buffered_readv(IDEState *s, int64_t sector_num,
648 QEMUIOVector *iov, int nb_sectors,
649 BlockCompletionFunc *cb, void *opaque)
650{
651 BlockAIOCB *aioreq;
652 IDEBufferedRequest *req;
653 int c = 0;
654
655 QLIST_FOREACH(req, &s->buffered_requests, list) {
656 c++;
657 }
658 if (c > MAX_BUFFERED_REQS) {
659 return blk_abort_aio_request(s->blk, cb, opaque, -EIO);
660 }
661
662 req = g_new0(IDEBufferedRequest, 1);
663 req->original_qiov = iov;
664 req->original_cb = cb;
665 req->original_opaque = opaque;
5bbe9325
VSO		 666 qemu_iovec_init_buf(&req->qiov, blk_blockalign(s->blk, iov->size),
667 iov->size);
1d8c11d6 668
d4f510eb
EB		 669 aioreq = blk_aio_preadv(s->blk, sector_num << BDRV_SECTOR_BITS,
670 &req->qiov, 0, ide_buffered_readv_cb, req);
1d8c11d6
PL		 671
672 QLIST_INSERT_HEAD(&s->buffered_requests, req, list);
673 return aioreq;
674}
675
86698a12
JS		 676/**
677 * Cancel all pending DMA requests.
678 * Any buffered DMA requests are instantly canceled,
679 * but any pending unbuffered DMA requests must be waited on.
680 */
681void ide_cancel_dma_sync(IDEState *s)
682{
683 IDEBufferedRequest *req;
684
685 /* First invoke the callbacks of all buffered requests
686 * and flag those requests as orphaned. Ideally there
687 * are no unbuffered (Scatter Gather DMA Requests or
688 * write requests) pending and we can avoid to drain. */
689 QLIST_FOREACH(req, &s->buffered_requests, list) {
690 if (!req->orphaned) {
3eee2611 691 trace_ide_cancel_dma_sync_buffered(req->original_cb, req);
86698a12
JS		 692 req->original_cb(req->original_opaque, -ECANCELED);
693 }
694 req->orphaned = true;
695 }
696
697 /*
698 * We can't cancel Scatter Gather DMA in the middle of the
699 * operation or a partial (not full) DMA transfer would reach
700 * the storage so we wait for completion instead (we beahve
701 * like if the DMA was completed by the time the guest trying
702 * to cancel dma with bmdma_cmd_writeb with BM_CMD_START not
703 * set).
704 *
705 * In the future we'll be able to safely cancel the I/O if the
706 * whole DMA operation will be submitted to disk with a single
707 * aio operation with preadv/pwritev.
708 */
709 if (s->bus->dma->aiocb) {
3eee2611 710 trace_ide_cancel_dma_sync_remaining();
51f7b5b8 711 blk_drain(s->blk);
86698a12
JS		 712 assert(s->bus->dma->aiocb == NULL);
713 }
714}
715
4e2b8b4a
PB		 716static void ide_sector_read(IDEState *s);
717
bef0fd59
SH		 718static void ide_sector_read_cb(void *opaque, int ret)
719{
720 IDEState *s = opaque;
721 int n;
722
723 s->pio_aiocb = NULL;
724 s->status &= ~BUSY_STAT;
725
0d910cfe
FZ		 726 if (ret == -ECANCELED) {
727 return;
728 }
bef0fd59 729 if (ret != 0) {
fd648f10
PB		 730 if (ide_handle_rw_error(s, -ret, IDE_RETRY_PIO |
731 IDE_RETRY_READ)) {
bef0fd59
SH		 732 return;
733 }
734 }
735
ecca3b39
AG		 736 block_acct_done(blk_get_stats(s->blk), &s->acct);
737
bef0fd59
SH		 738 n = s->nsector;
739 if (n > s->req_nb_sectors) {
740 n = s->req_nb_sectors;
741 }
742
bef0fd59
SH		 743 ide_set_sector(s, ide_get_sector(s) + n);
744 s->nsector -= n;
dd0bf7ba
JS		 745 /* Allow the guest to read the io_buffer */
746 ide_transfer_start(s, s->io_buffer, n * BDRV_SECTOR_SIZE, ide_sector_read);
dd0bf7ba 747 ide_set_irq(s->bus);
bef0fd59
SH		 748}
749
4e2b8b4a 750static void ide_sector_read(IDEState *s)
5391d806
FB		 751{
752 int64_t sector_num;
bef0fd59 753 int n;
5391d806
FB		 754
755 s->status = READY_STAT | SEEK_STAT;
a136e5a8 756 s->error = 0; /* not needed by IDE spec, but needed by Windows */
5391d806
FB		 757 sector_num = ide_get_sector(s);
758 n = s->nsector;
bef0fd59 759
5391d806 760 if (n == 0) {
5391d806 761 ide_transfer_stop(s);
bef0fd59
SH		 762 return;
763 }
764
765 s->status |= BUSY_STAT;
766
767 if (n > s->req_nb_sectors) {
768 n = s->req_nb_sectors;
769 }
770
3eee2611 771 trace_ide_sector_read(sector_num, n);
a597e79c 772
58ac3211
MA		 773 if (!ide_sect_range_ok(s, sector_num, n)) {
774 ide_rw_error(s);
ecca3b39 775 block_acct_invalid(blk_get_stats(s->blk), BLOCK_ACCT_READ);
58ac3211
MA		 776 return;
777 }
778
e5863d49 779 qemu_iovec_init_buf(&s->qiov, s->io_buffer, n * BDRV_SECTOR_SIZE);
bef0fd59 780
4be74634 781 block_acct_start(blk_get_stats(s->blk), &s->acct,
5366d0c8 782 n * BDRV_SECTOR_SIZE, BLOCK_ACCT_READ);
d66a8fa8
PL		 783 s->pio_aiocb = ide_buffered_readv(s, sector_num, &s->qiov, n,
784 ide_sector_read_cb, s);
5391d806
FB		 785}
786
aaeda4a3 787void dma_buf_commit(IDEState *s, uint32_t tx_bytes)
7aea4412 788{
659142ec
JS		 789 if (s->bus->dma->ops->commit_buf) {
790 s->bus->dma->ops->commit_buf(s->bus->dma, tx_bytes);
791 }
aaeda4a3 792 s->io_buffer_offset += tx_bytes;
1fb8648d 793 qemu_sglist_destroy(&s->sg);
7aea4412
AL		 794}
795
0e7ce54c 796void ide_set_inactive(IDEState *s, bool more)
8337606d 797{
40a6238a 798 s->bus->dma->aiocb = NULL;
0eeee07e 799 ide_clear_retry(s);
829b933b 800 if (s->bus->dma->ops->set_inactive) {
0e7ce54c 801 s->bus->dma->ops->set_inactive(s->bus->dma, more);
829b933b 802 }
c7e73adb 803 ide_cmd_done(s);
8337606d
KW		 804}
805
356721ae 806void ide_dma_error(IDEState *s)
e162cfb0 807{
659142ec 808 dma_buf_commit(s, 0);
08ee9e33 809 ide_abort_command(s);
0e7ce54c 810 ide_set_inactive(s, false);
9cdd03a7 811 ide_set_irq(s->bus);
e162cfb0
AZ		 812}
813
502356ee 814int ide_handle_rw_error(IDEState *s, int error, int op)
428c5705 815{
fd648f10 816 bool is_read = (op & IDE_RETRY_READ) != 0;
4be74634 817 BlockErrorAction action = blk_get_error_action(s->blk, is_read, error);
428c5705 818
a589569f 819 if (action == BLOCK_ERROR_ACTION_STOP) {
a96cb236 820 assert(s->bus->retry_unit == s->unit);
def93791 821 s->bus->error_status = op;
a589569f 822 } else if (action == BLOCK_ERROR_ACTION_REPORT) {
ecca3b39 823 block_acct_failed(blk_get_stats(s->blk), &s->acct);
502356ee 824 if (IS_IDE_RETRY_DMA(op)) {
428c5705 825 ide_dma_error(s);
502356ee
PB		 826 } else if (IS_IDE_RETRY_ATAPI(op)) {
827 ide_atapi_io_error(s, -error);
7aea4412 828 } else {
428c5705 829 ide_rw_error(s);
7aea4412 830 }
428c5705 831 }
4be74634 832 blk_error_action(s->blk, action, is_read, error);
a589569f 833 return action != BLOCK_ERROR_ACTION_IGNORE;
428c5705
AL		 834}
835
4e2b8b4a 836static void ide_dma_cb(void *opaque, int ret)
98087450 837{
40a6238a 838 IDEState *s = opaque;
8ccad811
FB		 839 int n;
840 int64_t sector_num;
cbe0ed62 841 uint64_t offset;
038268e2 842 bool stay_active = false;
8ccad811 843
0d910cfe
FZ		 844 if (ret == -ECANCELED) {
845 return;
846 }
caeadbc8
AN		 847
848 if (ret == -EINVAL) {
849 ide_dma_error(s);
850 return;
851 }
852
e162cfb0 853 if (ret < 0) {
218fd37c 854 if (ide_handle_rw_error(s, -ret, ide_dma_cmd_to_retry(s->dma_cmd))) {
87ac25fd 855 s->bus->dma->aiocb = NULL;
5839df7b 856 dma_buf_commit(s, 0);
ce4b6522
KW		 857 return;
858 }
e162cfb0
AZ		 859 }
860
8ccad811 861 n = s->io_buffer_size >> 9;
038268e2
KW		 862 if (n > s->nsector) {
863 /* The PRDs were longer than needed for this request. Shorten them so
864 * we don't get a negative remainder. The Active bit must remain set
865 * after the request completes. */
866 n = s->nsector;
867 stay_active = true;
868 }
869
8ccad811
FB		 870 sector_num = ide_get_sector(s);
871 if (n > 0) {
a718978e
JS		 872 assert(n * 512 == s->sg.size);
873 dma_buf_commit(s, s->sg.size);
8ccad811
FB		 874 sector_num += n;
875 ide_set_sector(s, sector_num);
876 s->nsector -= n;
8ccad811
FB		 877 }
878
879 /* end of transfer ? */
880 if (s->nsector == 0) {
98087450 881 s->status = READY_STAT | SEEK_STAT;
9cdd03a7 882 ide_set_irq(s->bus);
cd369c46 883 goto eot;
98087450 884 }
8ccad811
FB		 885
886 /* launch next transfer */
887 n = s->nsector;
596bb44d 888 s->io_buffer_index = 0;
8ccad811 889 s->io_buffer_size = n * 512;
a718978e 890 if (s->bus->dma->ops->prepare_buf(s->bus->dma, s->io_buffer_size) < 512) {
69c38b8f
KW		 891 /* The PRDs were too short. Reset the Active bit, but don't raise an
892 * interrupt. */
72bcca73 893 s->status = READY_STAT | SEEK_STAT;
3251bdcf 894 dma_buf_commit(s, 0);
7aea4412 895 goto eot;
69c38b8f 896 }
cd369c46 897
0e168d35 898 trace_ide_dma_cb(s, sector_num, n, IDE_DMA_CMD_str(s->dma_cmd));
cd369c46 899
d66168ed
MT		 900 if ((s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) &&
901 !ide_sect_range_ok(s, sector_num, n)) {
58ac3211 902 ide_dma_error(s);
ecca3b39 903 block_acct_invalid(blk_get_stats(s->blk), s->acct.type);
58ac3211
MA		 904 return;
905 }
906
cbe0ed62 907 offset = sector_num << BDRV_SECTOR_BITS;
4e1e0051
CH		 908 switch (s->dma_cmd) {
909 case IDE_DMA_READ:
cbe0ed62 910 s->bus->dma->aiocb = dma_blk_read(s->blk, &s->sg, offset,
99868af3 911 BDRV_SECTOR_SIZE, ide_dma_cb, s);
4e1e0051
CH		 912 break;
913 case IDE_DMA_WRITE:
cbe0ed62 914 s->bus->dma->aiocb = dma_blk_write(s->blk, &s->sg, offset,
99868af3 915 BDRV_SECTOR_SIZE, ide_dma_cb, s);
4e1e0051 916 break;
d353fb72 917 case IDE_DMA_TRIM:
8a8e63eb 918 s->bus->dma->aiocb = dma_blk_io(blk_get_aio_context(s->blk),
99868af3 919 &s->sg, offset, BDRV_SECTOR_SIZE,
ef0e64a9 920 ide_issue_trim, s, ide_dma_cb, s,
4be74634 921 DMA_DIRECTION_TO_DEVICE);
d353fb72 922 break;
502356ee
PB		 923 default:
924 abort();
cd369c46 925 }
cd369c46
CH		 926 return;
927
928eot:
a597e79c 929 if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) {
4be74634 930 block_acct_done(blk_get_stats(s->blk), &s->acct);
a597e79c 931 }
0e7ce54c 932 ide_set_inactive(s, stay_active);
98087450
FB		 933}
934
4e1e0051 935static void ide_sector_start_dma(IDEState *s, enum ide_dma_cmd dma_cmd)
98087450 936{
9da82227 937 s->status = READY_STAT | SEEK_STAT | DRQ_STAT;
98087450 938 s->io_buffer_size = 0;
4e1e0051 939 s->dma_cmd = dma_cmd;
a597e79c
CH		 940
941 switch (dma_cmd) {
942 case IDE_DMA_READ:
4be74634 943 block_acct_start(blk_get_stats(s->blk), &s->acct,
5366d0c8 944 s->nsector * BDRV_SECTOR_SIZE, BLOCK_ACCT_READ);
a597e79c
CH		 945 break;
946 case IDE_DMA_WRITE:
4be74634 947 block_acct_start(blk_get_stats(s->blk), &s->acct,
5366d0c8 948 s->nsector * BDRV_SECTOR_SIZE, BLOCK_ACCT_WRITE);
a597e79c
CH		 949 break;
950 default:
951 break;
952 }
953
4855b576
PB		 954 ide_start_dma(s, ide_dma_cb);
955}
956
097310b5 957void ide_start_dma(IDEState *s, BlockCompletionFunc *cb)
4855b576 958{
c71c06d4 959 s->io_buffer_index = 0;
0eeee07e 960 ide_set_retry(s);
4855b576
PB		 961 if (s->bus->dma->ops->start_dma) {
962 s->bus->dma->ops->start_dma(s->bus->dma, s, cb);
963 }
98087450
FB		 964}
965
4e2b8b4a
PB		 966static void ide_sector_write(IDEState *s);
967
a09db21f
FB		 968static void ide_sector_write_timer_cb(void *opaque)
969{
970 IDEState *s = opaque;
9cdd03a7 971 ide_set_irq(s->bus);
a09db21f
FB		 972}
973
e82dabd8 974static void ide_sector_write_cb(void *opaque, int ret)
5391d806 975{
e82dabd8
SH		 976 IDEState *s = opaque;
977 int n;
a597e79c 978
0d910cfe
FZ		 979 if (ret == -ECANCELED) {
980 return;
981 }
428c5705 982
e82dabd8
SH		 983 s->pio_aiocb = NULL;
984 s->status &= ~BUSY_STAT;
985
e162cfb0 986 if (ret != 0) {
fd648f10 987 if (ide_handle_rw_error(s, -ret, IDE_RETRY_PIO)) {
428c5705 988 return;
e82dabd8 989 }
e162cfb0
AZ		 990 }
991
ecca3b39
AG		 992 block_acct_done(blk_get_stats(s->blk), &s->acct);
993
e82dabd8
SH		 994 n = s->nsector;
995 if (n > s->req_nb_sectors) {
996 n = s->req_nb_sectors;
997 }
5391d806 998 s->nsector -= n;
36334faf 999
6aff22c0 1000 ide_set_sector(s, ide_get_sector(s) + n);
5391d806 1001 if (s->nsector == 0) {
292eef5a 1002 /* no more sectors to write */
5391d806
FB		 1003 ide_transfer_stop(s);
1004 } else {
e82dabd8
SH		 1005 int n1 = s->nsector;
1006 if (n1 > s->req_nb_sectors) {
5391d806 1007 n1 = s->req_nb_sectors;
e82dabd8
SH		 1008 }
1009 ide_transfer_start(s, s->io_buffer, n1 * BDRV_SECTOR_SIZE,
1010 ide_sector_write);
5391d806 1011 }
3b46e624 1012
31c2a146
TS		 1013 if (win2k_install_hack && ((++s->irq_count % 16) == 0)) {
1014 /* It seems there is a bug in the Windows 2000 installer HDD
1015 IDE driver which fills the disk with empty logs when the
1016 IDE write IRQ comes too early. This hack tries to correct
1017 that at the expense of slower write performances. Use this
1018 option _only_ to install Windows 2000. You must disable it
1019 for normal use. */
73bcb24d
RS		 1020 timer_mod(s->sector_write_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
1021 (NANOSECONDS_PER_SECOND / 1000));
f7736b91 1022 } else {
9cdd03a7 1023 ide_set_irq(s->bus);
31c2a146 1024 }
5391d806
FB		 1025}
1026
4e2b8b4a 1027static void ide_sector_write(IDEState *s)
e82dabd8
SH		 1028{
1029 int64_t sector_num;
1030 int n;
1031
1032 s->status = READY_STAT | SEEK_STAT | BUSY_STAT;
1033 sector_num = ide_get_sector(s);
3eee2611 1034
e82dabd8
SH		 1035 n = s->nsector;
1036 if (n > s->req_nb_sectors) {
1037 n = s->req_nb_sectors;
1038 }
1039
3eee2611
JS		 1040 trace_ide_sector_write(sector_num, n);
1041
58ac3211
MA		 1042 if (!ide_sect_range_ok(s, sector_num, n)) {
1043 ide_rw_error(s);
ecca3b39 1044 block_acct_invalid(blk_get_stats(s->blk), BLOCK_ACCT_WRITE);
58ac3211
MA		 1045 return;
1046 }
1047
e5863d49 1048 qemu_iovec_init_buf(&s->qiov, s->io_buffer, n * BDRV_SECTOR_SIZE);
e82dabd8 1049
4be74634 1050 block_acct_start(blk_get_stats(s->blk), &s->acct,
c618f331 1051 n * BDRV_SECTOR_SIZE, BLOCK_ACCT_WRITE);
d4f510eb
EB		 1052 s->pio_aiocb = blk_aio_pwritev(s->blk, sector_num << BDRV_SECTOR_BITS,
1053 &s->qiov, 0, ide_sector_write_cb, s);
e82dabd8
SH		 1054}
1055
b0484ae4
CH		 1056static void ide_flush_cb(void *opaque, int ret)
1057{
1058 IDEState *s = opaque;
1059
69f72a22
PB		 1060 s->pio_aiocb = NULL;
1061
0d910cfe
FZ		 1062 if (ret == -ECANCELED) {
1063 return;
1064 }
e2bcadad
KW		 1065 if (ret < 0) {
1066 /* XXX: What sector number to set here? */
fd648f10 1067 if (ide_handle_rw_error(s, -ret, IDE_RETRY_FLUSH)) {
e2bcadad
KW		 1068 return;
1069 }
1070 }
b0484ae4 1071
4be74634
MA		 1072 if (s->blk) {
1073 block_acct_done(blk_get_stats(s->blk), &s->acct);
f7f3ff1d 1074 }
b0484ae4 1075 s->status = READY_STAT | SEEK_STAT;
c7e73adb 1076 ide_cmd_done(s);
b0484ae4
CH		 1077 ide_set_irq(s->bus);
1078}
1079
4e2b8b4a 1080static void ide_flush_cache(IDEState *s)
6bcb1a79 1081{
4be74634 1082 if (s->blk == NULL) {
6bcb1a79 1083 ide_flush_cb(s, 0);
b2df7531
KW		 1084 return;
1085 }
1086
f68ec837 1087 s->status |= BUSY_STAT;
35f78ab4 1088 ide_set_retry(s);
4be74634 1089 block_acct_start(blk_get_stats(s->blk), &s->acct, 0, BLOCK_ACCT_FLUSH);
13471a40 1090 s->pio_aiocb = blk_aio_flush(s->blk, ide_flush_cb, s);
6bcb1a79
KW		 1091}
1092
201a51fc
AZ		 1093static void ide_cfata_metadata_inquiry(IDEState *s)
1094{
1095 uint16_t *p;
1096 uint32_t spd;
1097
1098 p = (uint16_t *) s->io_buffer;
1099 memset(p, 0, 0x200);
1100 spd = ((s->mdata_size - 1) >> 9) + 1;
1101
1102 put_le16(p + 0, 0x0001); /* Data format revision */
1103 put_le16(p + 1, 0x0000); /* Media property: silicon */
1104 put_le16(p + 2, s->media_changed); /* Media status */
1105 put_le16(p + 3, s->mdata_size & 0xffff); /* Capacity in bytes (low) */
1106 put_le16(p + 4, s->mdata_size >> 16); /* Capacity in bytes (high) */
1107 put_le16(p + 5, spd & 0xffff); /* Sectors per device (low) */
1108 put_le16(p + 6, spd >> 16); /* Sectors per device (high) */
1109}
1110
1111static void ide_cfata_metadata_read(IDEState *s)
1112{
1113 uint16_t *p;
1114
1115 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
1116 s->status = ERR_STAT;
1117 s->error = ABRT_ERR;
1118 return;
1119 }
1120
1121 p = (uint16_t *) s->io_buffer;
1122 memset(p, 0, 0x200);
1123
1124 put_le16(p + 0, s->media_changed); /* Media status */
1125 memcpy(p + 1, s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
1126 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
1127 s->nsector << 9), 0x200 - 2));
1128}
1129
1130static void ide_cfata_metadata_write(IDEState *s)
1131{
1132 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
1133 s->status = ERR_STAT;
1134 s->error = ABRT_ERR;
1135 return;
1136 }
1137
1138 s->media_changed = 0;
1139
1140 memcpy(s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
1141 s->io_buffer + 2,
1142 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
1143 s->nsector << 9), 0x200 - 2));
1144}
1145
bd491d6a 1146/* called when the inserted state of the media has changed */
39829a01 1147static void ide_cd_change_cb(void *opaque, bool load, Error **errp)
bd491d6a
TS		 1148{
1149 IDEState *s = opaque;
96b8f136 1150 uint64_t nb_sectors;
bd491d6a 1151
25ad22bc 1152 s->tray_open = !load;
4be74634 1153 blk_get_geometry(s->blk, &nb_sectors);
bd491d6a 1154 s->nb_sectors = nb_sectors;
9118e7f0 1155
4b9b7092
AS		 1156 /*
1157 * First indicate to the guest that a CD has been removed. That's
1158 * done on the next command the guest sends us.
1159 *
67cc61e4 1160 * Then we set UNIT_ATTENTION, by which the guest will
4b9b7092
AS		 1161 * detect a new CD in the drive. See ide_atapi_cmd() for details.
1162 */
93c8cfd9 1163 s->cdrom_changed = 1;
996faf1a 1164 s->events.new_media = true;
2df0a3a3
PB		 1165 s->events.eject_request = false;
1166 ide_set_irq(s->bus);
1167}
1168
1169static void ide_cd_eject_request_cb(void *opaque, bool force)
1170{
1171 IDEState *s = opaque;
1172
1173 s->events.eject_request = true;
1174 if (force) {
1175 s->tray_locked = false;
1176 }
9cdd03a7 1177 ide_set_irq(s->bus);
bd491d6a
TS		 1178}
1179
c2ff060f
FB		 1180static void ide_cmd_lba48_transform(IDEState *s, int lba48)
1181{
1182 s->lba48 = lba48;
1183
1184 /* handle the 'magic' 0 nsector count conversion here. to avoid
1185 * fiddling with the rest of the read logic, we just store the
1186 * full sector count in ->nsector and ignore ->hob_nsector from now
1187 */
1188 if (!s->lba48) {
7d37435b
PB		 1189 if (!s->nsector)
1190 s->nsector = 256;
c2ff060f 1191 } else {
7d37435b
PB		 1192 if (!s->nsector && !s->hob_nsector)
1193 s->nsector = 65536;
1194 else {
1195 int lo = s->nsector;
1196 int hi = s->hob_nsector;
c2ff060f 1197
7d37435b
PB		 1198 s->nsector = (hi << 8) | lo;
1199 }
c2ff060f
FB		 1200 }
1201}
1202
bcbdc4d3 1203static void ide_clear_hob(IDEBus *bus)
c2ff060f
FB		 1204{
1205 /* any write clears HOB high bit of device control register */
bcbdc4d3
GH		 1206 bus->ifs[0].select &= ~(1 << 7);
1207 bus->ifs[1].select &= ~(1 << 7);
c2ff060f
FB		 1208}
1209
335ca2f2
JS		 1210/* IOport [W]rite [R]egisters */
1211enum ATA_IOPORT_WR {
1212 ATA_IOPORT_WR_DATA = 0,
1213 ATA_IOPORT_WR_FEATURES = 1,
1214 ATA_IOPORT_WR_SECTOR_COUNT = 2,
1215 ATA_IOPORT_WR_SECTOR_NUMBER = 3,
1216 ATA_IOPORT_WR_CYLINDER_LOW = 4,
1217 ATA_IOPORT_WR_CYLINDER_HIGH = 5,
1218 ATA_IOPORT_WR_DEVICE_HEAD = 6,
1219 ATA_IOPORT_WR_COMMAND = 7,
1220 ATA_IOPORT_WR_NUM_REGISTERS,
1221};
1222
1223const char *ATA_IOPORT_WR_lookup[ATA_IOPORT_WR_NUM_REGISTERS] = {
1224 [ATA_IOPORT_WR_DATA] = "Data",
1225 [ATA_IOPORT_WR_FEATURES] = "Features",
1226 [ATA_IOPORT_WR_SECTOR_COUNT] = "Sector Count",
1227 [ATA_IOPORT_WR_SECTOR_NUMBER] = "Sector Number",
1228 [ATA_IOPORT_WR_CYLINDER_LOW] = "Cylinder Low",
1229 [ATA_IOPORT_WR_CYLINDER_HIGH] = "Cylinder High",
1230 [ATA_IOPORT_WR_DEVICE_HEAD] = "Device/Head",
1231 [ATA_IOPORT_WR_COMMAND] = "Command"
1232};
1233
356721ae 1234void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
caed8802 1235{
bcbdc4d3 1236 IDEBus *bus = opaque;
3eee2611
JS		 1237 IDEState *s = idebus_active_if(bus);
1238 int reg_num = addr & 7;
5391d806 1239
335ca2f2 1240 trace_ide_ioport_write(addr, ATA_IOPORT_WR_lookup[reg_num], val, bus, s);
fcdd25ab
AL		 1241
1242 /* ignore writes to command block while busy with previous command */
3eee2611 1243 if (reg_num != 7 && (s->status & (BUSY_STAT|DRQ_STAT))) {
fcdd25ab 1244 return;
3eee2611 1245 }
fcdd25ab 1246
3eee2611 1247 switch (reg_num) {
5391d806
FB		 1248 case 0:
1249 break;
335ca2f2
JS		 1250 case ATA_IOPORT_WR_FEATURES:
1251 ide_clear_hob(bus);
c45c3d00 1252 /* NOTE: data is written to the two drives */
335ca2f2
JS		 1253 bus->ifs[0].hob_feature = bus->ifs[0].feature;
1254 bus->ifs[1].hob_feature = bus->ifs[1].feature;
bcbdc4d3
GH		 1255 bus->ifs[0].feature = val;
1256 bus->ifs[1].feature = val;
5391d806 1257 break;
335ca2f2 1258 case ATA_IOPORT_WR_SECTOR_COUNT:
7d37435b
PB		 1259 ide_clear_hob(bus);
1260 bus->ifs[0].hob_nsector = bus->ifs[0].nsector;
1261 bus->ifs[1].hob_nsector = bus->ifs[1].nsector;
bcbdc4d3
GH		 1262 bus->ifs[0].nsector = val;
1263 bus->ifs[1].nsector = val;
5391d806 1264 break;
335ca2f2 1265 case ATA_IOPORT_WR_SECTOR_NUMBER:
7d37435b
PB		 1266 ide_clear_hob(bus);
1267 bus->ifs[0].hob_sector = bus->ifs[0].sector;
1268 bus->ifs[1].hob_sector = bus->ifs[1].sector;
bcbdc4d3
GH		 1269 bus->ifs[0].sector = val;
1270 bus->ifs[1].sector = val;
5391d806 1271 break;
335ca2f2 1272 case ATA_IOPORT_WR_CYLINDER_LOW:
7d37435b
PB		 1273 ide_clear_hob(bus);
1274 bus->ifs[0].hob_lcyl = bus->ifs[0].lcyl;
1275 bus->ifs[1].hob_lcyl = bus->ifs[1].lcyl;
bcbdc4d3
GH		 1276 bus->ifs[0].lcyl = val;
1277 bus->ifs[1].lcyl = val;
5391d806 1278 break;
335ca2f2 1279 case ATA_IOPORT_WR_CYLINDER_HIGH:
7d37435b
PB		 1280 ide_clear_hob(bus);
1281 bus->ifs[0].hob_hcyl = bus->ifs[0].hcyl;
1282 bus->ifs[1].hob_hcyl = bus->ifs[1].hcyl;
bcbdc4d3
GH		 1283 bus->ifs[0].hcyl = val;
1284 bus->ifs[1].hcyl = val;
5391d806 1285 break;
335ca2f2 1286 case ATA_IOPORT_WR_DEVICE_HEAD:
7d37435b 1287 /* FIXME: HOB readback uses bit 7 */
bcbdc4d3
GH		 1288 bus->ifs[0].select = (val & ~0x10) | 0xa0;
1289 bus->ifs[1].select = (val | 0x10) | 0xa0;
5391d806 1290 /* select drive */
bcbdc4d3 1291 bus->unit = (val >> 4) & 1;
5391d806
FB		 1292 break;
1293 default:
335ca2f2 1294 case ATA_IOPORT_WR_COMMAND:
5391d806 1295 /* command */
7cff87ff
AG		 1296 ide_exec_cmd(bus, val);
1297 break;
1298 }
1299}
1300
4590355b
JS		 1301static void ide_reset(IDEState *s)
1302{
3eee2611 1303 trace_ide_reset(s);
4590355b
JS		 1304
1305 if (s->pio_aiocb) {
1306 blk_aio_cancel(s->pio_aiocb);
1307 s->pio_aiocb = NULL;
1308 }
1309
1310 if (s->drive_kind == IDE_CFATA)
1311 s->mult_sectors = 0;
1312 else
1313 s->mult_sectors = MAX_MULT_SECTORS;
1314 /* ide regs */
1315 s->feature = 0;
1316 s->error = 0;
1317 s->nsector = 0;
1318 s->sector = 0;
1319 s->lcyl = 0;
1320 s->hcyl = 0;
1321
1322 /* lba48 */
1323 s->hob_feature = 0;
1324 s->hob_sector = 0;
1325 s->hob_nsector = 0;
1326 s->hob_lcyl = 0;
1327 s->hob_hcyl = 0;
1328
1329 s->select = 0xa0;
1330 s->status = READY_STAT | SEEK_STAT;
1331
1332 s->lba48 = 0;
1333
1334 /* ATAPI specific */
1335 s->sense_key = 0;
1336 s->asc = 0;
1337 s->cdrom_changed = 0;
1338 s->packet_transfer_size = 0;
1339 s->elementary_transfer_size = 0;
1340 s->io_buffer_index = 0;
1341 s->cd_sector_size = 0;
1342 s->atapi_dma = 0;
1343 s->tray_locked = 0;
1344 s->tray_open = 0;
1345 /* ATA DMA state */
1346 s->io_buffer_size = 0;
1347 s->req_nb_sectors = 0;
1348
1349 ide_set_signature(s);
1350 /* init the transfer handler so that 0xffff is returned on data
1351 accesses */
1352 s->end_transfer_func = ide_dummy_transfer_stop;
1353 ide_dummy_transfer_stop(s);
1354 s->media_changed = 0;
1355}
1356
b300337e
KW		 1357static bool cmd_nop(IDEState *s, uint8_t cmd)
1358{
1359 return true;
1360}
1361
f34ae00d
JS		 1362static bool cmd_device_reset(IDEState *s, uint8_t cmd)
1363{
1364 /* Halt PIO (in the DRQ phase), then DMA */
882941a5 1365 ide_transfer_halt(s);
f34ae00d
JS		 1366 ide_cancel_dma_sync(s);
1367
1368 /* Reset any PIO commands, reset signature, etc */
1369 ide_reset(s);
1370
1371 /* RESET: ATA8-ACS3 7.10.4 "Normal Outputs";
1372 * ATA8-ACS3 Table 184 "Device Signatures for Normal Output" */
1373 s->status = 0x00;
1374
1375 /* Do not overwrite status register */
1376 return false;
1377}
1378
4286434c
KW		 1379static bool cmd_data_set_management(IDEState *s, uint8_t cmd)
1380{
1381 switch (s->feature) {
1382 case DSM_TRIM:
4be74634 1383 if (s->blk) {
4286434c
KW		 1384 ide_sector_start_dma(s, IDE_DMA_TRIM);
1385 return false;
1386 }
1387 break;
1388 }
1389
1390 ide_abort_command(s);
1391 return true;
1392}
1393
1c66869a
KW		 1394static bool cmd_identify(IDEState *s, uint8_t cmd)
1395{
4be74634 1396 if (s->blk && s->drive_kind != IDE_CD) {
1c66869a
KW		 1397 if (s->drive_kind != IDE_CFATA) {
1398 ide_identify(s);
1399 } else {
1400 ide_cfata_identify(s);
1401 }
1402 s->status = READY_STAT | SEEK_STAT;
1403 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
1404 ide_set_irq(s->bus);
1405 return false;
1406 } else {
1407 if (s->drive_kind == IDE_CD) {
1408 ide_set_signature(s);
1409 }
1410 ide_abort_command(s);
1411 }
1412
1413 return true;
1414}
1415
413860cf
KW		 1416static bool cmd_verify(IDEState *s, uint8_t cmd)
1417{
1418 bool lba48 = (cmd == WIN_VERIFY_EXT);
1419
1420 /* do sector number check ? */
1421 ide_cmd_lba48_transform(s, lba48);
1422
1423 return true;
1424}
1425
adf3a2c4
KW		 1426static bool cmd_set_multiple_mode(IDEState *s, uint8_t cmd)
1427{
1428 if (s->drive_kind == IDE_CFATA && s->nsector == 0) {
1429 /* Disable Read and Write Multiple */
1430 s->mult_sectors = 0;
1431 } else if ((s->nsector & 0xff) != 0 &&
1432 ((s->nsector & 0xff) > MAX_MULT_SECTORS ||
1433 (s->nsector & (s->nsector - 1)) != 0)) {
1434 ide_abort_command(s);
1435 } else {
1436 s->mult_sectors = s->nsector & 0xff;
1437 }
1438
1439 return true;
1440}
1441
1442static bool cmd_read_multiple(IDEState *s, uint8_t cmd)
1443{
1444 bool lba48 = (cmd == WIN_MULTREAD_EXT);
1445
4be74634 1446 if (!s->blk || !s->mult_sectors) {
adf3a2c4
KW		 1447 ide_abort_command(s);
1448 return true;
1449 }
1450
1451 ide_cmd_lba48_transform(s, lba48);
1452 s->req_nb_sectors = s->mult_sectors;
1453 ide_sector_read(s);
1454 return false;
1455}
1456
1457static bool cmd_write_multiple(IDEState *s, uint8_t cmd)
1458{
1459 bool lba48 = (cmd == WIN_MULTWRITE_EXT);
1460 int n;
1461
4be74634 1462 if (!s->blk || !s->mult_sectors) {
adf3a2c4
KW		 1463 ide_abort_command(s);
1464 return true;
1465 }
1466
1467 ide_cmd_lba48_transform(s, lba48);
1468
1469 s->req_nb_sectors = s->mult_sectors;
1470 n = MIN(s->nsector, s->req_nb_sectors);
1471
1472 s->status = SEEK_STAT | READY_STAT;
1473 ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_write);
1474
1475 s->media_changed = 1;
1476
1477 return false;
1478}
1479
0e6498ed
KW		 1480static bool cmd_read_pio(IDEState *s, uint8_t cmd)
1481{
1482 bool lba48 = (cmd == WIN_READ_EXT);
1483
1484 if (s->drive_kind == IDE_CD) {
1485 ide_set_signature(s); /* odd, but ATA4 8.27.5.2 requires it */
1486 ide_abort_command(s);
1487 return true;
1488 }
1489
4be74634 1490 if (!s->blk) {
0e6498ed
KW		 1491 ide_abort_command(s);
1492 return true;
1493 }
1494
1495 ide_cmd_lba48_transform(s, lba48);
1496 s->req_nb_sectors = 1;
1497 ide_sector_read(s);
1498
1499 return false;
1500}
1501
1502static bool cmd_write_pio(IDEState *s, uint8_t cmd)
1503{
1504 bool lba48 = (cmd == WIN_WRITE_EXT);
1505
4be74634 1506 if (!s->blk) {
0e6498ed
KW		 1507 ide_abort_command(s);
1508 return true;
1509 }
1510
1511 ide_cmd_lba48_transform(s, lba48);
1512
1513 s->req_nb_sectors = 1;
1514 s->status = SEEK_STAT | READY_STAT;
1515 ide_transfer_start(s, s->io_buffer, 512, ide_sector_write);
1516
1517 s->media_changed = 1;
1518
1519 return false;
1520}
1521
92a6a6f6
KW		 1522static bool cmd_read_dma(IDEState *s, uint8_t cmd)
1523{
1524 bool lba48 = (cmd == WIN_READDMA_EXT);
1525
4be74634 1526 if (!s->blk) {
92a6a6f6
KW		 1527 ide_abort_command(s);
1528 return true;
1529 }
1530
1531 ide_cmd_lba48_transform(s, lba48);
1532 ide_sector_start_dma(s, IDE_DMA_READ);
1533
1534 return false;
1535}
1536
1537static bool cmd_write_dma(IDEState *s, uint8_t cmd)
1538{
1539 bool lba48 = (cmd == WIN_WRITEDMA_EXT);
1540
4be74634 1541 if (!s->blk) {
92a6a6f6
KW		 1542 ide_abort_command(s);
1543 return true;
1544 }
1545
1546 ide_cmd_lba48_transform(s, lba48);
1547 ide_sector_start_dma(s, IDE_DMA_WRITE);
1548
1549 s->media_changed = 1;
1550
1551 return false;
1552}
1553
9afce429
KW		 1554static bool cmd_flush_cache(IDEState *s, uint8_t cmd)
1555{
1556 ide_flush_cache(s);
1557 return false;
1558}
1559
61fdda37
KW		 1560static bool cmd_seek(IDEState *s, uint8_t cmd)
1561{
1562 /* XXX: Check that seek is within bounds */
1563 return true;
1564}
1565
63a82e6a
KW		 1566static bool cmd_read_native_max(IDEState *s, uint8_t cmd)
1567{
1568 bool lba48 = (cmd == WIN_READ_NATIVE_MAX_EXT);
1569
1570 /* Refuse if no sectors are addressable (e.g. medium not inserted) */
1571 if (s->nb_sectors == 0) {
1572 ide_abort_command(s);
1573 return true;
1574 }
1575
1576 ide_cmd_lba48_transform(s, lba48);
1577 ide_set_sector(s, s->nb_sectors - 1);
1578
1579 return true;
1580}
1581
785f6320
KW		 1582static bool cmd_check_power_mode(IDEState *s, uint8_t cmd)
1583{
1584 s->nsector = 0xff; /* device active or idle */
1585 return true;
1586}
1587
ee03398c
KW		 1588static bool cmd_set_features(IDEState *s, uint8_t cmd)
1589{
1590 uint16_t *identify_data;
1591
4be74634 1592 if (!s->blk) {
ee03398c
KW		 1593 ide_abort_command(s);
1594 return true;
1595 }
1596
1597 /* XXX: valid for CDROM ? */
1598 switch (s->feature) {
1599 case 0x02: /* write cache enable */
4be74634 1600 blk_set_enable_write_cache(s->blk, true);
ee03398c
KW		 1601 identify_data = (uint16_t *)s->identify_data;
1602 put_le16(identify_data + 85, (1 << 14) | (1 << 5) | 1);
1603 return true;
1604 case 0x82: /* write cache disable */
4be74634 1605 blk_set_enable_write_cache(s->blk, false);
ee03398c
KW		 1606 identify_data = (uint16_t *)s->identify_data;
1607 put_le16(identify_data + 85, (1 << 14) | 1);
1608 ide_flush_cache(s);
1609 return false;
1610 case 0xcc: /* reverting to power-on defaults enable */
1611 case 0x66: /* reverting to power-on defaults disable */
1612 case 0xaa: /* read look-ahead enable */
1613 case 0x55: /* read look-ahead disable */
1614 case 0x05: /* set advanced power management mode */
1615 case 0x85: /* disable advanced power management mode */
1616 case 0x69: /* NOP */
1617 case 0x67: /* NOP */
1618 case 0x96: /* NOP */
1619 case 0x9a: /* NOP */
1620 case 0x42: /* enable Automatic Acoustic Mode */
1621 case 0xc2: /* disable Automatic Acoustic Mode */
1622 return true;
1623 case 0x03: /* set transfer mode */
1624 {
1625 uint8_t val = s->nsector & 0x07;
1626 identify_data = (uint16_t *)s->identify_data;
1627
1628 switch (s->nsector >> 3) {
1629 case 0x00: /* pio default */
1630 case 0x01: /* pio mode */
1631 put_le16(identify_data + 62, 0x07);
1632 put_le16(identify_data + 63, 0x07);
1633 put_le16(identify_data + 88, 0x3f);
1634 break;
1635 case 0x02: /* sigle word dma mode*/
1636 put_le16(identify_data + 62, 0x07 | (1 << (val + 8)));
1637 put_le16(identify_data + 63, 0x07);
1638 put_le16(identify_data + 88, 0x3f);
1639 break;
1640 case 0x04: /* mdma mode */
1641 put_le16(identify_data + 62, 0x07);
1642 put_le16(identify_data + 63, 0x07 | (1 << (val + 8)));
1643 put_le16(identify_data + 88, 0x3f);
1644 break;
1645 case 0x08: /* udma mode */
1646 put_le16(identify_data + 62, 0x07);
1647 put_le16(identify_data + 63, 0x07);
1648 put_le16(identify_data + 88, 0x3f | (1 << (val + 8)));
1649 break;
1650 default:
1651 goto abort_cmd;
1652 }
1653 return true;
1654 }
1655 }
1656
1657abort_cmd:
1658 ide_abort_command(s);
1659 return true;
1660}
1661
ee425c78
KW		 1662
1663/*** ATAPI commands ***/
1664
1665static bool cmd_identify_packet(IDEState *s, uint8_t cmd)
1666{
1667 ide_atapi_identify(s);
1668 s->status = READY_STAT | SEEK_STAT;
1669 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
1670 ide_set_irq(s->bus);
1671 return false;
1672}
1673
1674static bool cmd_exec_dev_diagnostic(IDEState *s, uint8_t cmd)
1675{
1676 ide_set_signature(s);
1677
1678 if (s->drive_kind == IDE_CD) {
1679 s->status = 0; /* ATAPI spec (v6) section 9.10 defines packet
1680 * devices to return a clear status register
1681 * with READY_STAT *not* set. */
850484a2 1682 s->error = 0x01;
ee425c78
KW		 1683 } else {
1684 s->status = READY_STAT | SEEK_STAT;
1685 /* The bits of the error register are not as usual for this command!
1686 * They are part of the regular output (this is why ERR_STAT isn't set)
1687 * Device 0 passed, Device 1 passed or not present. */
1688 s->error = 0x01;
1689 ide_set_irq(s->bus);
1690 }
1691
1692 return false;
1693}
1694
ee425c78
KW		 1695static bool cmd_packet(IDEState *s, uint8_t cmd)
1696{
1697 /* overlapping commands not supported */
1698 if (s->feature & 0x02) {
1699 ide_abort_command(s);
1700 return true;
1701 }
1702
1703 s->status = READY_STAT | SEEK_STAT;
1704 s->atapi_dma = s->feature & 1;
502356ee
PB		 1705 if (s->atapi_dma) {
1706 s->dma_cmd = IDE_DMA_ATAPI;
1707 }
ee425c78
KW		 1708 s->nsector = 1;
1709 ide_transfer_start(s, s->io_buffer, ATAPI_PACKET_SIZE,
1710 ide_atapi_cmd);
1711 return false;
1712}
1713
6b1dd744
KW		 1714
1715/*** CF-ATA commands ***/
1716
1717static bool cmd_cfa_req_ext_error_code(IDEState *s, uint8_t cmd)
1718{
1719 s->error = 0x09; /* miscellaneous error */
1720 s->status = READY_STAT | SEEK_STAT;
1721 ide_set_irq(s->bus);
1722
1723 return false;
1724}
1725
1726static bool cmd_cfa_erase_sectors(IDEState *s, uint8_t cmd)
1727{
1728 /* WIN_SECURITY_FREEZE_LOCK has the same ID as CFA_WEAR_LEVEL and is
1729 * required for Windows 8 to work with AHCI */
1730
1731 if (cmd == CFA_WEAR_LEVEL) {
1732 s->nsector = 0;
1733 }
1734
1735 if (cmd == CFA_ERASE_SECTORS) {
1736 s->media_changed = 1;
1737 }
1738
1739 return true;
1740}
1741
1742static bool cmd_cfa_translate_sector(IDEState *s, uint8_t cmd)
1743{
1744 s->status = READY_STAT | SEEK_STAT;
1745
1746 memset(s->io_buffer, 0, 0x200);
1747 s->io_buffer[0x00] = s->hcyl; /* Cyl MSB */
1748 s->io_buffer[0x01] = s->lcyl; /* Cyl LSB */
1749 s->io_buffer[0x02] = s->select; /* Head */
1750 s->io_buffer[0x03] = s->sector; /* Sector */
1751 s->io_buffer[0x04] = ide_get_sector(s) >> 16; /* LBA MSB */
1752 s->io_buffer[0x05] = ide_get_sector(s) >> 8; /* LBA */
1753 s->io_buffer[0x06] = ide_get_sector(s) >> 0; /* LBA LSB */
1754 s->io_buffer[0x13] = 0x00; /* Erase flag */
1755 s->io_buffer[0x18] = 0x00; /* Hot count */
1756 s->io_buffer[0x19] = 0x00; /* Hot count */
1757 s->io_buffer[0x1a] = 0x01; /* Hot count */
1758
1759 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1760 ide_set_irq(s->bus);
1761
1762 return false;
1763}
1764
1765static bool cmd_cfa_access_metadata_storage(IDEState *s, uint8_t cmd)
1766{
1767 switch (s->feature) {
1768 case 0x02: /* Inquiry Metadata Storage */
1769 ide_cfata_metadata_inquiry(s);
1770 break;
1771 case 0x03: /* Read Metadata Storage */
1772 ide_cfata_metadata_read(s);
1773 break;
1774 case 0x04: /* Write Metadata Storage */
1775 ide_cfata_metadata_write(s);
1776 break;
1777 default:
1778 ide_abort_command(s);
1779 return true;
1780 }
1781
1782 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1783 s->status = 0x00; /* NOTE: READY is _not_ set */
1784 ide_set_irq(s->bus);
1785
1786 return false;
1787}
1788
1789static bool cmd_ibm_sense_condition(IDEState *s, uint8_t cmd)
1790{
1791 switch (s->feature) {
1792 case 0x01: /* sense temperature in device */
1793 s->nsector = 0x50; /* +20 C */
1794 break;
1795 default:
1796 ide_abort_command(s);
1797 return true;
1798 }
1799
1800 return true;
1801}
1802
ff352677
KW		 1803
1804/*** SMART commands ***/
1805
1806static bool cmd_smart(IDEState *s, uint8_t cmd)
1807{
1808 int n;
1809
1810 if (s->hcyl != 0xc2 || s->lcyl != 0x4f) {
1811 goto abort_cmd;
1812 }
1813
1814 if (!s->smart_enabled && s->feature != SMART_ENABLE) {
1815 goto abort_cmd;
1816 }
1817
1818 switch (s->feature) {
1819 case SMART_DISABLE:
1820 s->smart_enabled = 0;
1821 return true;
1822
1823 case SMART_ENABLE:
1824 s->smart_enabled = 1;
1825 return true;
1826
1827 case SMART_ATTR_AUTOSAVE:
1828 switch (s->sector) {
1829 case 0x00:
1830 s->smart_autosave = 0;
1831 break;
1832 case 0xf1:
1833 s->smart_autosave = 1;
1834 break;
1835 default:
1836 goto abort_cmd;
1837 }
1838 return true;
1839
1840 case SMART_STATUS:
1841 if (!s->smart_errors) {
1842 s->hcyl = 0xc2;
1843 s->lcyl = 0x4f;
1844 } else {
1845 s->hcyl = 0x2c;
1846 s->lcyl = 0xf4;
1847 }
1848 return true;
1849
1850 case SMART_READ_THRESH:
1851 memset(s->io_buffer, 0, 0x200);
1852 s->io_buffer[0] = 0x01; /* smart struct version */
1853
1854 for (n = 0; n < ARRAY_SIZE(smart_attributes); n++) {
1855 s->io_buffer[2 + 0 + (n * 12)] = smart_attributes[n][0];
1856 s->io_buffer[2 + 1 + (n * 12)] = smart_attributes[n][11];
1857 }
1858
1859 /* checksum */
1860 for (n = 0; n < 511; n++) {
1861 s->io_buffer[511] += s->io_buffer[n];
1862 }
1863 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1864
1865 s->status = READY_STAT | SEEK_STAT;
1866 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1867 ide_set_irq(s->bus);
1868 return false;
1869
1870 case SMART_READ_DATA:
1871 memset(s->io_buffer, 0, 0x200);
1872 s->io_buffer[0] = 0x01; /* smart struct version */
1873
1874 for (n = 0; n < ARRAY_SIZE(smart_attributes); n++) {
1875 int i;
1876 for (i = 0; i < 11; i++) {
1877 s->io_buffer[2 + i + (n * 12)] = smart_attributes[n][i];
1878 }
1879 }
1880
1881 s->io_buffer[362] = 0x02 | (s->smart_autosave ? 0x80 : 0x00);
1882 if (s->smart_selftest_count == 0) {
1883 s->io_buffer[363] = 0;
1884 } else {
1885 s->io_buffer[363] =
1886 s->smart_selftest_data[3 +
1887 (s->smart_selftest_count - 1) *
1888 24];
1889 }
1890 s->io_buffer[364] = 0x20;
1891 s->io_buffer[365] = 0x01;
1892 /* offline data collection capacity: execute + self-test*/
1893 s->io_buffer[367] = (1 << 4 | 1 << 3 | 1);
1894 s->io_buffer[368] = 0x03; /* smart capability (1) */
1895 s->io_buffer[369] = 0x00; /* smart capability (2) */
1896 s->io_buffer[370] = 0x01; /* error logging supported */
1897 s->io_buffer[372] = 0x02; /* minutes for poll short test */
1898 s->io_buffer[373] = 0x36; /* minutes for poll ext test */
1899 s->io_buffer[374] = 0x01; /* minutes for poll conveyance */
1900
1901 for (n = 0; n < 511; n++) {
1902 s->io_buffer[511] += s->io_buffer[n];
1903 }
1904 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1905
1906 s->status = READY_STAT | SEEK_STAT;
1907 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1908 ide_set_irq(s->bus);
1909 return false;
1910
1911 case SMART_READ_LOG:
1912 switch (s->sector) {
1913 case 0x01: /* summary smart error log */
1914 memset(s->io_buffer, 0, 0x200);
1915 s->io_buffer[0] = 0x01;
1916 s->io_buffer[1] = 0x00; /* no error entries */
1917 s->io_buffer[452] = s->smart_errors & 0xff;
1918 s->io_buffer[453] = (s->smart_errors & 0xff00) >> 8;
1919
1920 for (n = 0; n < 511; n++) {
1921 s->io_buffer[511] += s->io_buffer[n];
1922 }
1923 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1924 break;
1925 case 0x06: /* smart self test log */
1926 memset(s->io_buffer, 0, 0x200);
1927 s->io_buffer[0] = 0x01;
1928 if (s->smart_selftest_count == 0) {
1929 s->io_buffer[508] = 0;
1930 } else {
1931 s->io_buffer[508] = s->smart_selftest_count;
1932 for (n = 2; n < 506; n++) {
1933 s->io_buffer[n] = s->smart_selftest_data[n];
1934 }
1935 }
1936
1937 for (n = 0; n < 511; n++) {
1938 s->io_buffer[511] += s->io_buffer[n];
1939 }
1940 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1941 break;
1942 default:
1943 goto abort_cmd;
1944 }
1945 s->status = READY_STAT | SEEK_STAT;
1946 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1947 ide_set_irq(s->bus);
1948 return false;
1949
1950 case SMART_EXECUTE_OFFLINE:
1951 switch (s->sector) {
1952 case 0: /* off-line routine */
1953 case 1: /* short self test */
1954 case 2: /* extended self test */
1955 s->smart_selftest_count++;
1956 if (s->smart_selftest_count > 21) {
940973ae 1957 s->smart_selftest_count = 1;
ff352677
KW		 1958 }
1959 n = 2 + (s->smart_selftest_count - 1) * 24;
1960 s->smart_selftest_data[n] = s->sector;
1961 s->smart_selftest_data[n + 1] = 0x00; /* OK and finished */
1962 s->smart_selftest_data[n + 2] = 0x34; /* hour count lsb */
1963 s->smart_selftest_data[n + 3] = 0x12; /* hour count msb */
1964 break;
1965 default:
1966 goto abort_cmd;
1967 }
1968 return true;
1969 }
1970
1971abort_cmd:
1972 ide_abort_command(s);
1973 return true;
1974}
1975
844505b1
MA		 1976#define HD_OK (1u << IDE_HD)
1977#define CD_OK (1u << IDE_CD)
1978#define CFA_OK (1u << IDE_CFATA)
1979#define HD_CFA_OK (HD_OK | CFA_OK)
1980#define ALL_OK (HD_OK | CD_OK | CFA_OK)
1981
a0436e92
KW		 1982/* Set the Disk Seek Completed status bit during completion */
1983#define SET_DSC (1u << 8)
1984
844505b1 1985/* See ACS-2 T13/2015-D Table B.2 Command codes */
a0436e92
KW		 1986static const struct {
1987 /* Returns true if the completion code should be run */
1988 bool (*handler)(IDEState *s, uint8_t cmd);
1989 int flags;
1990} ide_cmd_table[0x100] = {
844505b1 1991 /* NOP not implemented, mandatory for CD */
6b1dd744 1992 [CFA_REQ_EXT_ERROR_CODE] = { cmd_cfa_req_ext_error_code, CFA_OK },
d9033e1d 1993 [WIN_DSM] = { cmd_data_set_management, HD_CFA_OK },
ee425c78 1994 [WIN_DEVICE_RESET] = { cmd_device_reset, CD_OK },
b300337e 1995 [WIN_RECAL] = { cmd_nop, HD_CFA_OK | SET_DSC},
0e6498ed 1996 [WIN_READ] = { cmd_read_pio, ALL_OK },
d9033e1d 1997 [WIN_READ_ONCE] = { cmd_read_pio, HD_CFA_OK },
0e6498ed 1998 [WIN_READ_EXT] = { cmd_read_pio, HD_CFA_OK },
92a6a6f6 1999 [WIN_READDMA_EXT] = { cmd_read_dma, HD_CFA_OK },
63a82e6a 2000 [WIN_READ_NATIVE_MAX_EXT] = { cmd_read_native_max, HD_CFA_OK | SET_DSC },
adf3a2c4 2001 [WIN_MULTREAD_EXT] = { cmd_read_multiple, HD_CFA_OK },
0e6498ed
KW		 2002 [WIN_WRITE] = { cmd_write_pio, HD_CFA_OK },
2003 [WIN_WRITE_ONCE] = { cmd_write_pio, HD_CFA_OK },
2004 [WIN_WRITE_EXT] = { cmd_write_pio, HD_CFA_OK },
92a6a6f6 2005 [WIN_WRITEDMA_EXT] = { cmd_write_dma, HD_CFA_OK },
0e6498ed 2006 [CFA_WRITE_SECT_WO_ERASE] = { cmd_write_pio, CFA_OK },
adf3a2c4 2007 [WIN_MULTWRITE_EXT] = { cmd_write_multiple, HD_CFA_OK },
0e6498ed 2008 [WIN_WRITE_VERIFY] = { cmd_write_pio, HD_CFA_OK },
413860cf
KW		 2009 [WIN_VERIFY] = { cmd_verify, HD_CFA_OK | SET_DSC },
2010 [WIN_VERIFY_ONCE] = { cmd_verify, HD_CFA_OK | SET_DSC },
2011 [WIN_VERIFY_EXT] = { cmd_verify, HD_CFA_OK | SET_DSC },
61fdda37 2012 [WIN_SEEK] = { cmd_seek, HD_CFA_OK | SET_DSC },
6b1dd744 2013 [CFA_TRANSLATE_SECTOR] = { cmd_cfa_translate_sector, CFA_OK },
ee425c78 2014 [WIN_DIAGNOSE] = { cmd_exec_dev_diagnostic, ALL_OK },
b300337e 2015 [WIN_SPECIFY] = { cmd_nop, HD_CFA_OK | SET_DSC },
d9033e1d
JS		 2016 [WIN_STANDBYNOW2] = { cmd_nop, HD_CFA_OK },
2017 [WIN_IDLEIMMEDIATE2] = { cmd_nop, HD_CFA_OK },
2018 [WIN_STANDBY2] = { cmd_nop, HD_CFA_OK },
2019 [WIN_SETIDLE2] = { cmd_nop, HD_CFA_OK },
2020 [WIN_CHECKPOWERMODE2] = { cmd_check_power_mode, HD_CFA_OK | SET_DSC },
2021 [WIN_SLEEPNOW2] = { cmd_nop, HD_CFA_OK },
ee425c78
KW		 2022 [WIN_PACKETCMD] = { cmd_packet, CD_OK },
2023 [WIN_PIDENTIFY] = { cmd_identify_packet, CD_OK },
ff352677 2024 [WIN_SMART] = { cmd_smart, HD_CFA_OK | SET_DSC },
6b1dd744
KW		 2025 [CFA_ACCESS_METADATA_STORAGE] = { cmd_cfa_access_metadata_storage, CFA_OK },
2026 [CFA_ERASE_SECTORS] = { cmd_cfa_erase_sectors, CFA_OK | SET_DSC },
adf3a2c4
KW		 2027 [WIN_MULTREAD] = { cmd_read_multiple, HD_CFA_OK },
2028 [WIN_MULTWRITE] = { cmd_write_multiple, HD_CFA_OK },
2029 [WIN_SETMULT] = { cmd_set_multiple_mode, HD_CFA_OK | SET_DSC },
92a6a6f6
KW		 2030 [WIN_READDMA] = { cmd_read_dma, HD_CFA_OK },
2031 [WIN_READDMA_ONCE] = { cmd_read_dma, HD_CFA_OK },
2032 [WIN_WRITEDMA] = { cmd_write_dma, HD_CFA_OK },
2033 [WIN_WRITEDMA_ONCE] = { cmd_write_dma, HD_CFA_OK },
adf3a2c4 2034 [CFA_WRITE_MULTI_WO_ERASE] = { cmd_write_multiple, CFA_OK },
d9033e1d
JS		 2035 [WIN_STANDBYNOW1] = { cmd_nop, HD_CFA_OK },
2036 [WIN_IDLEIMMEDIATE] = { cmd_nop, HD_CFA_OK },
2037 [WIN_STANDBY] = { cmd_nop, HD_CFA_OK },
2038 [WIN_SETIDLE1] = { cmd_nop, HD_CFA_OK },
2039 [WIN_CHECKPOWERMODE1] = { cmd_check_power_mode, HD_CFA_OK | SET_DSC },
2040 [WIN_SLEEPNOW1] = { cmd_nop, HD_CFA_OK },
9afce429
KW		 2041 [WIN_FLUSH_CACHE] = { cmd_flush_cache, ALL_OK },
2042 [WIN_FLUSH_CACHE_EXT] = { cmd_flush_cache, HD_CFA_OK },
1c66869a 2043 [WIN_IDENTIFY] = { cmd_identify, ALL_OK },
ee03398c 2044 [WIN_SETFEATURES] = { cmd_set_features, ALL_OK | SET_DSC },
6b1dd744
KW		 2045 [IBM_SENSE_CONDITION] = { cmd_ibm_sense_condition, CFA_OK | SET_DSC },
2046 [CFA_WEAR_LEVEL] = { cmd_cfa_erase_sectors, HD_CFA_OK | SET_DSC },
d9033e1d 2047 [WIN_READ_NATIVE_MAX] = { cmd_read_native_max, HD_CFA_OK | SET_DSC },
844505b1
MA		 2048};
2049
2050static bool ide_cmd_permitted(IDEState *s, uint32_t cmd)
2051{
2052 return cmd < ARRAY_SIZE(ide_cmd_table)
a0436e92 2053 && (ide_cmd_table[cmd].flags & (1u << s->drive_kind));
844505b1 2054}
7cff87ff
AG		 2055
2056void ide_exec_cmd(IDEBus *bus, uint32_t val)
2057{
2058 IDEState *s;
dfe1ea8f 2059 bool complete;
7cff87ff 2060
6ef2ba5e 2061 s = idebus_active_if(bus);
3eee2611
JS		 2062 trace_ide_exec_cmd(bus, s, val);
2063
66a0a2cb 2064 /* ignore commands to non existent slave */
4be74634 2065 if (s != bus->ifs && !s->blk) {
6ef2ba5e 2066 return;
4be74634 2067 }
c2ff060f 2068
266e7781
JS		 2069 /* Only RESET is allowed while BSY and/or DRQ are set,
2070 * and only to ATAPI devices. */
2071 if (s->status & (BUSY_STAT|DRQ_STAT)) {
2072 if (val != WIN_DEVICE_RESET || s->drive_kind != IDE_CD) {
2073 return;
2074 }
2075 }
fcdd25ab 2076
844505b1 2077 if (!ide_cmd_permitted(s, val)) {
dfe1ea8f
KW		 2078 ide_abort_command(s);
2079 ide_set_irq(s->bus);
2080 return;
844505b1
MA		 2081 }
2082
dfe1ea8f
KW		 2083 s->status = READY_STAT | BUSY_STAT;
2084 s->error = 0;
36334faf 2085 s->io_buffer_offset = 0;
a0436e92 2086
dfe1ea8f
KW		 2087 complete = ide_cmd_table[val].handler(s, val);
2088 if (complete) {
2089 s->status &= ~BUSY_STAT;
2090 assert(!!s->error == !!(s->status & ERR_STAT));
a0436e92 2091
dfe1ea8f
KW		 2092 if ((ide_cmd_table[val].flags & SET_DSC) && !s->error) {
2093 s->status |= SEEK_STAT;
a0436e92
KW		 2094 }
2095
c7e73adb 2096 ide_cmd_done(s);
6ef2ba5e 2097 ide_set_irq(s->bus);
6ef2ba5e 2098 }
5391d806
FB		 2099}
2100
335ca2f2
JS		 2101/* IOport [R]ead [R]egisters */
2102enum ATA_IOPORT_RR {
2103 ATA_IOPORT_RR_DATA = 0,
2104 ATA_IOPORT_RR_ERROR = 1,
2105 ATA_IOPORT_RR_SECTOR_COUNT = 2,
2106 ATA_IOPORT_RR_SECTOR_NUMBER = 3,
2107 ATA_IOPORT_RR_CYLINDER_LOW = 4,
2108 ATA_IOPORT_RR_CYLINDER_HIGH = 5,
2109 ATA_IOPORT_RR_DEVICE_HEAD = 6,
2110 ATA_IOPORT_RR_STATUS = 7,
2111 ATA_IOPORT_RR_NUM_REGISTERS,
2112};
2113
2114const char *ATA_IOPORT_RR_lookup[ATA_IOPORT_RR_NUM_REGISTERS] = {
2115 [ATA_IOPORT_RR_DATA] = "Data",
2116 [ATA_IOPORT_RR_ERROR] = "Error",
2117 [ATA_IOPORT_RR_SECTOR_COUNT] = "Sector Count",
2118 [ATA_IOPORT_RR_SECTOR_NUMBER] = "Sector Number",
2119 [ATA_IOPORT_RR_CYLINDER_LOW] = "Cylinder Low",
2120 [ATA_IOPORT_RR_CYLINDER_HIGH] = "Cylinder High",
2121 [ATA_IOPORT_RR_DEVICE_HEAD] = "Device/Head",
2122 [ATA_IOPORT_RR_STATUS] = "Status"
2123};
2124
3eee2611 2125uint32_t ide_ioport_read(void *opaque, uint32_t addr)
5391d806 2126{
bcbdc4d3
GH		 2127 IDEBus *bus = opaque;
2128 IDEState *s = idebus_active_if(bus);
3eee2611 2129 uint32_t reg_num;
c2ff060f 2130 int ret, hob;
5391d806 2131
3eee2611 2132 reg_num = addr & 7;
c2ff060f
FB		 2133 /* FIXME: HOB readback uses bit 7, but it's always set right now */
2134 //hob = s->select & (1 << 7);
2135 hob = 0;
3eee2611 2136 switch (reg_num) {
335ca2f2 2137 case ATA_IOPORT_RR_DATA:
5391d806
FB		 2138 ret = 0xff;
2139 break;
335ca2f2 2140 case ATA_IOPORT_RR_ERROR:
4be74634
MA		 2141 if ((!bus->ifs[0].blk && !bus->ifs[1].blk) ||
2142 (s != bus->ifs && !s->blk)) {
c45c3d00 2143 ret = 0;
4be74634 2144 } else if (!hob) {
c45c3d00 2145 ret = s->error;
4be74634 2146 } else {
7d37435b 2147 ret = s->hob_feature;
4be74634 2148 }
5391d806 2149 break;
335ca2f2 2150 case ATA_IOPORT_RR_SECTOR_COUNT:
4be74634 2151 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
c45c3d00 2152 ret = 0;
4be74634 2153 } else if (!hob) {
c45c3d00 2154 ret = s->nsector & 0xff;
4be74634 2155 } else {
7d37435b 2156 ret = s->hob_nsector;
4be74634 2157 }
5391d806 2158 break;
335ca2f2 2159 case ATA_IOPORT_RR_SECTOR_NUMBER:
4be74634 2160 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
c45c3d00 2161 ret = 0;
4be74634 2162 } else if (!hob) {
c45c3d00 2163 ret = s->sector;
4be74634 2164 } else {
7d37435b 2165 ret = s->hob_sector;
4be74634 2166 }
5391d806 2167 break;
335ca2f2 2168 case ATA_IOPORT_RR_CYLINDER_LOW:
4be74634 2169 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
c45c3d00 2170 ret = 0;
4be74634 2171 } else if (!hob) {
c45c3d00 2172 ret = s->lcyl;
4be74634 2173 } else {
7d37435b 2174 ret = s->hob_lcyl;
4be74634 2175 }
5391d806 2176 break;
335ca2f2 2177 case ATA_IOPORT_RR_CYLINDER_HIGH:
4be74634 2178 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
c45c3d00 2179 ret = 0;
4be74634 2180 } else if (!hob) {
c45c3d00 2181 ret = s->hcyl;
4be74634 2182 } else {
7d37435b 2183 ret = s->hob_hcyl;
4be74634 2184 }
5391d806 2185 break;
335ca2f2 2186 case ATA_IOPORT_RR_DEVICE_HEAD:
4be74634 2187 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
c45c3d00 2188 ret = 0;
4be74634 2189 } else {
7ae98627 2190 ret = s->select;
4be74634 2191 }
5391d806
FB		 2192 break;
2193 default:
335ca2f2 2194 case ATA_IOPORT_RR_STATUS:
4be74634
MA		 2195 if ((!bus->ifs[0].blk && !bus->ifs[1].blk) ||
2196 (s != bus->ifs && !s->blk)) {
c45c3d00 2197 ret = 0;
4be74634 2198 } else {
c45c3d00 2199 ret = s->status;
4be74634 2200 }
9cdd03a7 2201 qemu_irq_lower(bus->irq);
5391d806
FB		 2202 break;
2203 }
3eee2611 2204
335ca2f2 2205 trace_ide_ioport_read(addr, ATA_IOPORT_RR_lookup[reg_num], ret, bus, s);
5391d806
FB		 2206 return ret;
2207}
2208
356721ae 2209uint32_t ide_status_read(void *opaque, uint32_t addr)
5391d806 2210{
bcbdc4d3
GH		 2211 IDEBus *bus = opaque;
2212 IDEState *s = idebus_active_if(bus);
5391d806 2213 int ret;
7ae98627 2214
4be74634
MA		 2215 if ((!bus->ifs[0].blk && !bus->ifs[1].blk) ||
2216 (s != bus->ifs && !s->blk)) {
7ae98627 2217 ret = 0;
4be74634 2218 } else {
7ae98627 2219 ret = s->status;
4be74634 2220 }
3eee2611
JS		 2221
2222 trace_ide_status_read(addr, ret, bus, s);
5391d806
FB		 2223 return ret;
2224}
2225
356721ae 2226void ide_cmd_write(void *opaque, uint32_t addr, uint32_t val)
5391d806 2227{
bcbdc4d3 2228 IDEBus *bus = opaque;
5391d806
FB		 2229 IDEState *s;
2230 int i;
2231
3eee2611
JS		 2232 trace_ide_cmd_write(addr, val, bus);
2233
5391d806 2234 /* common for both drives */
9cdd03a7 2235 if (!(bus->cmd & IDE_CMD_RESET) &&
5391d806
FB		 2236 (val & IDE_CMD_RESET)) {
2237 /* reset low to high */
2238 for(i = 0;i < 2; i++) {
bcbdc4d3 2239 s = &bus->ifs[i];
5391d806
FB		 2240 s->status = BUSY_STAT | SEEK_STAT;
2241 s->error = 0x01;
2242 }
9cdd03a7 2243 } else if ((bus->cmd & IDE_CMD_RESET) &&
5391d806
FB		 2244 !(val & IDE_CMD_RESET)) {
2245 /* high to low */
2246 for(i = 0;i < 2; i++) {
bcbdc4d3 2247 s = &bus->ifs[i];
cd8722bb 2248 if (s->drive_kind == IDE_CD)
6b136f9e
FB		 2249 s->status = 0x00; /* NOTE: READY is _not_ set */
2250 else
56bf1d37 2251 s->status = READY_STAT | SEEK_STAT;
5391d806
FB		 2252 ide_set_signature(s);
2253 }
2254 }
2255
9cdd03a7 2256 bus->cmd = val;
5391d806
FB		 2257}
2258
40c4ed3f
KW		 2259/*
2260 * Returns true if the running PIO transfer is a PIO out (i.e. data is
2261 * transferred from the device to the guest), false if it's a PIO in
2262 */
2263static bool ide_is_pio_out(IDEState *s)
2264{
2265 if (s->end_transfer_func == ide_sector_write ||
2266 s->end_transfer_func == ide_atapi_cmd) {
2267 return false;
2268 } else if (s->end_transfer_func == ide_sector_read ||
2269 s->end_transfer_func == ide_transfer_stop ||
2270 s->end_transfer_func == ide_atapi_cmd_reply_end ||
2271 s->end_transfer_func == ide_dummy_transfer_stop) {
2272 return true;
2273 }
2274
2275 abort();
2276}
2277
356721ae 2278void ide_data_writew(void *opaque, uint32_t addr, uint32_t val)
5391d806 2279{
bcbdc4d3
GH		 2280 IDEBus *bus = opaque;
2281 IDEState *s = idebus_active_if(bus);
5391d806
FB		 2282 uint8_t *p;
2283
1787efc3
JS		 2284 trace_ide_data_writew(addr, val, bus, s);
2285
40c4ed3f
KW		 2286 /* PIO data access allowed only when DRQ bit is set. The result of a write
2287 * during PIO out is indeterminate, just ignore it. */
2288 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
fcdd25ab 2289 return;
40c4ed3f 2290 }
fcdd25ab 2291
5391d806 2292 p = s->data_ptr;
d2ff8585
KW		 2293 if (p + 2 > s->data_end) {
2294 return;
2295 }
2296
0c4ad8dc 2297 *(uint16_t *)p = le16_to_cpu(val);
5391d806
FB		 2298 p += 2;
2299 s->data_ptr = p;
cb72cba8
KW		 2300 if (p >= s->data_end) {
2301 s->status &= ~DRQ_STAT;
5391d806 2302 s->end_transfer_func(s);
cb72cba8 2303 }
5391d806
FB		 2304}
2305
356721ae 2306uint32_t ide_data_readw(void *opaque, uint32_t addr)
5391d806 2307{
bcbdc4d3
GH		 2308 IDEBus *bus = opaque;
2309 IDEState *s = idebus_active_if(bus);
5391d806
FB		 2310 uint8_t *p;
2311 int ret;
fcdd25ab 2312
40c4ed3f
KW		 2313 /* PIO data access allowed only when DRQ bit is set. The result of a read
2314 * during PIO in is indeterminate, return 0 and don't move forward. */
2315 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
fcdd25ab 2316 return 0;
40c4ed3f 2317 }
fcdd25ab 2318
5391d806 2319 p = s->data_ptr;
d2ff8585
KW		 2320 if (p + 2 > s->data_end) {
2321 return 0;
2322 }
2323
0c4ad8dc 2324 ret = cpu_to_le16(*(uint16_t *)p);
5391d806
FB		 2325 p += 2;
2326 s->data_ptr = p;
cb72cba8
KW		 2327 if (p >= s->data_end) {
2328 s->status &= ~DRQ_STAT;
5391d806 2329 s->end_transfer_func(s);
cb72cba8 2330 }
1787efc3
JS		 2331
2332 trace_ide_data_readw(addr, ret, bus, s);
5391d806
FB		 2333 return ret;
2334}
2335
356721ae 2336void ide_data_writel(void *opaque, uint32_t addr, uint32_t val)
5391d806 2337{
bcbdc4d3
GH		 2338 IDEBus *bus = opaque;
2339 IDEState *s = idebus_active_if(bus);
5391d806
FB		 2340 uint8_t *p;
2341
1787efc3
JS		 2342 trace_ide_data_writel(addr, val, bus, s);
2343
40c4ed3f
KW		 2344 /* PIO data access allowed only when DRQ bit is set. The result of a write
2345 * during PIO out is indeterminate, just ignore it. */
2346 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
fcdd25ab 2347 return;
40c4ed3f 2348 }
fcdd25ab 2349
5391d806 2350 p = s->data_ptr;
d2ff8585
KW		 2351 if (p + 4 > s->data_end) {
2352 return;
2353 }
2354
0c4ad8dc 2355 *(uint32_t *)p = le32_to_cpu(val);
5391d806
FB		 2356 p += 4;
2357 s->data_ptr = p;
cb72cba8
KW		 2358 if (p >= s->data_end) {
2359 s->status &= ~DRQ_STAT;
5391d806 2360 s->end_transfer_func(s);
cb72cba8 2361 }
5391d806
FB		 2362}
2363
356721ae 2364uint32_t ide_data_readl(void *opaque, uint32_t addr)
5391d806 2365{
bcbdc4d3
GH		 2366 IDEBus *bus = opaque;
2367 IDEState *s = idebus_active_if(bus);
5391d806
FB		 2368 uint8_t *p;
2369 int ret;
3b46e624 2370
40c4ed3f
KW		 2371 /* PIO data access allowed only when DRQ bit is set. The result of a read
2372 * during PIO in is indeterminate, return 0 and don't move forward. */
2373 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
1787efc3
JS		 2374 ret = 0;
2375 goto out;
40c4ed3f 2376 }
fcdd25ab 2377
5391d806 2378 p = s->data_ptr;
d2ff8585
KW		 2379 if (p + 4 > s->data_end) {
2380 return 0;
2381 }
2382
0c4ad8dc 2383 ret = cpu_to_le32(*(uint32_t *)p);
5391d806
FB		 2384 p += 4;
2385 s->data_ptr = p;
cb72cba8
KW		 2386 if (p >= s->data_end) {
2387 s->status &= ~DRQ_STAT;
5391d806 2388 s->end_transfer_func(s);
cb72cba8 2389 }
1787efc3
JS		 2390
2391out:
2392 trace_ide_data_readl(addr, ret, bus, s);
5391d806
FB		 2393 return ret;
2394}
2395
a7dfe172
FB		 2396static void ide_dummy_transfer_stop(IDEState *s)
2397{
2398 s->data_ptr = s->io_buffer;
2399 s->data_end = s->io_buffer;
2400 s->io_buffer[0] = 0xff;
2401 s->io_buffer[1] = 0xff;
2402 s->io_buffer[2] = 0xff;
2403 s->io_buffer[3] = 0xff;
2404}
2405
4a643563
BS		 2406void ide_bus_reset(IDEBus *bus)
2407{
2408 bus->unit = 0;
2409 bus->cmd = 0;
2410 ide_reset(&bus->ifs[0]);
2411 ide_reset(&bus->ifs[1]);
2412 ide_clear_hob(bus);
40a6238a
AG		 2413
2414 /* pending async DMA */
2415 if (bus->dma->aiocb) {
0e168d35 2416 trace_ide_bus_reset_aio();
4be74634 2417 blk_aio_cancel(bus->dma->aiocb);
40a6238a
AG		 2418 bus->dma->aiocb = NULL;
2419 }
2420
2421 /* reset dma provider too */
1374bec0
PB		 2422 if (bus->dma->ops->reset) {
2423 bus->dma->ops->reset(bus->dma);
2424 }
4a643563
BS		 2425}
2426
e4def80b
MA		 2427static bool ide_cd_is_tray_open(void *opaque)
2428{
2429 return ((IDEState *)opaque)->tray_open;
2430}
2431
f107639a
MA		 2432static bool ide_cd_is_medium_locked(void *opaque)
2433{
2434 return ((IDEState *)opaque)->tray_locked;
2435}
2436
01ce352e
JS		 2437static void ide_resize_cb(void *opaque)
2438{
2439 IDEState *s = opaque;
2440 uint64_t nb_sectors;
2441
2442 if (!s->identify_set) {
2443 return;
2444 }
2445
4be74634 2446 blk_get_geometry(s->blk, &nb_sectors);
01ce352e
JS		 2447 s->nb_sectors = nb_sectors;
2448
2449 /* Update the identify data buffer. */
2450 if (s->drive_kind == IDE_CFATA) {
2451 ide_cfata_identify_size(s);
2452 } else {
2453 /* IDE_CD uses a different set of callbacks entirely. */
2454 assert(s->drive_kind != IDE_CD);
2455 ide_identify_size(s);
2456 }
2457}
2458
0e49de52 2459static const BlockDevOps ide_cd_block_ops = {
145feb17 2460 .change_media_cb = ide_cd_change_cb,
2df0a3a3 2461 .eject_request_cb = ide_cd_eject_request_cb,
e4def80b 2462 .is_tray_open = ide_cd_is_tray_open,
f107639a 2463 .is_medium_locked = ide_cd_is_medium_locked,
0e49de52
MA		 2464};
2465
01ce352e
JS		 2466static const BlockDevOps ide_hd_block_ops = {
2467 .resize_cb = ide_resize_cb,
2468};
2469
4be74634 2470int ide_init_drive(IDEState *s, BlockBackend *blk, IDEDriveKind kind,
95ebda85 2471 const char *version, const char *serial, const char *model,
ba801960
MA		 2472 uint64_t wwn,
2473 uint32_t cylinders, uint32_t heads, uint32_t secs,
794939e8 2474 int chs_trans, Error **errp)
88804180 2475{
88804180
GH		 2476 uint64_t nb_sectors;
2477
4be74634 2478 s->blk = blk;
1f56e32a
MA		 2479 s->drive_kind = kind;
2480
4be74634 2481 blk_get_geometry(blk, &nb_sectors);
870111c8
MA		 2482 s->cylinders = cylinders;
2483 s->heads = heads;
2484 s->sectors = secs;
ba801960 2485 s->chs_trans = chs_trans;
870111c8 2486 s->nb_sectors = nb_sectors;
95ebda85 2487 s->wwn = wwn;
870111c8
MA		 2488 /* The SMART values should be preserved across power cycles
2489 but they aren't. */
2490 s->smart_enabled = 1;
2491 s->smart_autosave = 1;
2492 s->smart_errors = 0;
2493 s->smart_selftest_count = 0;
1f56e32a 2494 if (kind == IDE_CD) {
4be74634
MA		 2495 blk_set_dev_ops(blk, &ide_cd_block_ops, s);
2496 blk_set_guest_block_size(blk, 2048);
7aa9c811 2497 } else {
4be74634 2498 if (!blk_is_inserted(s->blk)) {
794939e8 2499 error_setg(errp, "Device needs media, but drive is empty");
98f28ad7
MA		 2500 return -1;
2501 }
4be74634 2502 if (blk_is_read_only(blk)) {
794939e8 2503 error_setg(errp, "Can't use a read-only drive");
7aa9c811
MA		 2504 return -1;
2505 }
4be74634 2506 blk_set_dev_ops(blk, &ide_hd_block_ops, s);
88804180 2507 }
f8b6cc00 2508 if (serial) {
aa2c91bd 2509 pstrcpy(s->drive_serial_str, sizeof(s->drive_serial_str), serial);
6ced55a5 2510 } else {
88804180
GH		 2511 snprintf(s->drive_serial_str, sizeof(s->drive_serial_str),
2512 "QM%05d", s->drive_serial);
870111c8 2513 }
27e0c9a1
FB		 2514 if (model) {
2515 pstrcpy(s->drive_model_str, sizeof(s->drive_model_str), model);
2516 } else {
2517 switch (kind) {
2518 case IDE_CD:
2519 strcpy(s->drive_model_str, "QEMU DVD-ROM");
2520 break;
2521 case IDE_CFATA:
2522 strcpy(s->drive_model_str, "QEMU MICRODRIVE");
2523 break;
2524 default:
2525 strcpy(s->drive_model_str, "QEMU HARDDISK");
2526 break;
2527 }
2528 }
2529
47c06340
GH		 2530 if (version) {
2531 pstrcpy(s->version, sizeof(s->version), version);
2532 } else {
35c2c8dc 2533 pstrcpy(s->version, sizeof(s->version), qemu_hw_version());
47c06340 2534 }
40a6238a 2535
88804180 2536 ide_reset(s);
4be74634 2537 blk_iostatus_enable(blk);
c4d74df7 2538 return 0;
88804180
GH		 2539}
2540
57234ee4 2541static void ide_init1(IDEBus *bus, int unit)
d459da0e
MA		 2542{
2543 static int drive_serial = 1;
2544 IDEState *s = &bus->ifs[unit];
2545
2546 s->bus = bus;
2547 s->unit = unit;
2548 s->drive_serial = drive_serial++;
1b2adf28 2549 /* we need at least 2k alignment for accessing CDROMs using O_DIRECT */
50641c5c 2550 s->io_buffer_total_len = IDE_DMA_BUF_SECTORS*512 + 4;
c925400b
KW		 2551 s->io_buffer = qemu_memalign(2048, s->io_buffer_total_len);
2552 memset(s->io_buffer, 0, s->io_buffer_total_len);
2553
4be74634 2554 s->smart_selftest_data = blk_blockalign(s->blk, 512);
c925400b
KW		 2555 memset(s->smart_selftest_data, 0, 512);
2556
bc72ad67 2557 s->sector_write_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
d459da0e 2558 ide_sector_write_timer_cb, s);
57234ee4
MA		 2559}
2560
40a6238a
AG		 2561static int ide_nop_int(IDEDMA *dma, int x)
2562{
2563 return 0;
2564}
2565
9898586d
PB		 2566static void ide_nop(IDEDMA *dma)
2567{
2568}
2569
a718978e 2570static int32_t ide_nop_int32(IDEDMA *dma, int32_t l)
3251bdcf
JS		 2571{
2572 return 0;
2573}
2574
40a6238a 2575static const IDEDMAOps ide_dma_nop_ops = {
3251bdcf 2576 .prepare_buf = ide_nop_int32,
9898586d 2577 .restart_dma = ide_nop,
40a6238a 2578 .rw_buf = ide_nop_int,
40a6238a
AG		 2579};
2580
9898586d
PB		 2581static void ide_restart_dma(IDEState *s, enum ide_dma_cmd dma_cmd)
2582{
a96cb236 2583 s->unit = s->bus->retry_unit;
dc5d0af4
PB		 2584 ide_set_sector(s, s->bus->retry_sector_num);
2585 s->nsector = s->bus->retry_nsector;
9898586d 2586 s->bus->dma->ops->restart_dma(s->bus->dma);
9898586d
PB		 2587 s->io_buffer_size = 0;
2588 s->dma_cmd = dma_cmd;
2589 ide_start_dma(s, ide_dma_cb);
2590}
2591
2592static void ide_restart_bh(void *opaque)
2593{
2594 IDEBus *bus = opaque;
2595 IDEState *s;
2596 bool is_read;
2597 int error_status;
2598
2599 qemu_bh_delete(bus->bh);
2600 bus->bh = NULL;
2601
2602 error_status = bus->error_status;
2603 if (bus->error_status == 0) {
2604 return;
2605 }
2606
2607 s = idebus_active_if(bus);
2608 is_read = (bus->error_status & IDE_RETRY_READ) != 0;
2609
2610 /* The error status must be cleared before resubmitting the request: The
2611 * request may fail again, and this case can only be distinguished if the
2612 * called function can set a new error status. */
2613 bus->error_status = 0;
2614
7c03a691
JS		 2615 /* The HBA has generically asked to be kicked on retry */
2616 if (error_status & IDE_RETRY_HBA) {
2617 if (s->bus->dma->ops->restart) {
2618 s->bus->dma->ops->restart(s->bus->dma);
2619 }
502356ee 2620 } else if (IS_IDE_RETRY_DMA(error_status)) {
9898586d
PB		 2621 if (error_status & IDE_RETRY_TRIM) {
2622 ide_restart_dma(s, IDE_DMA_TRIM);
2623 } else {
2624 ide_restart_dma(s, is_read ? IDE_DMA_READ : IDE_DMA_WRITE);
2625 }
502356ee 2626 } else if (IS_IDE_RETRY_PIO(error_status)) {
9898586d
PB		 2627 if (is_read) {
2628 ide_sector_read(s);
2629 } else {
2630 ide_sector_write(s);
2631 }
2632 } else if (error_status & IDE_RETRY_FLUSH) {
2633 ide_flush_cache(s);
502356ee
PB		 2634 } else if (IS_IDE_RETRY_ATAPI(error_status)) {
2635 assert(s->end_transfer_func == ide_atapi_cmd);
2636 ide_atapi_dma_restart(s);
9898586d 2637 } else {
502356ee 2638 abort();
9898586d
PB		 2639 }
2640}
2641
2642static void ide_restart_cb(void *opaque, int running, RunState state)
2643{
2644 IDEBus *bus = opaque;
2645
2646 if (!running)
2647 return;
2648
2649 if (!bus->bh) {
2650 bus->bh = qemu_bh_new(ide_restart_bh, bus);
2651 qemu_bh_schedule(bus->bh);
2652 }
2653}
2654
f878c916
PB		 2655void ide_register_restart_cb(IDEBus *bus)
2656{
9898586d 2657 if (bus->dma->ops->restart_dma) {
ca44141d 2658 bus->vmstate = qemu_add_vm_change_state_handler(ide_restart_cb, bus);
9898586d 2659 }
f878c916
PB		 2660}
2661
40a6238a
AG		 2662static IDEDMA ide_dma_nop = {
2663 .ops = &ide_dma_nop_ops,
2664 .aiocb = NULL,
2665};
2666
57234ee4
MA		 2667void ide_init2(IDEBus *bus, qemu_irq irq)
2668{
2669 int i;
2670
2671 for(i = 0; i < 2; i++) {
2672 ide_init1(bus, i);
2673 ide_reset(&bus->ifs[i]);
870111c8 2674 }
57234ee4 2675 bus->irq = irq;
40a6238a 2676 bus->dma = &ide_dma_nop;
d459da0e
MA		 2677}
2678
c9f08641
LQ		 2679void ide_exit(IDEState *s)
2680{
2681 timer_del(s->sector_write_timer);
2682 timer_free(s->sector_write_timer);
2683 qemu_vfree(s->smart_selftest_data);
2684 qemu_vfree(s->io_buffer);
2685}
2686
37159f13 2687static bool is_identify_set(void *opaque, int version_id)
aa941b94 2688{
37159f13
JQ		 2689 IDEState *s = opaque;
2690
2691 return s->identify_set != 0;
2692}
2693
50641c5c
JQ		 2694static EndTransferFunc* transfer_end_table[] = {
2695 ide_sector_read,
2696 ide_sector_write,
2697 ide_transfer_stop,
2698 ide_atapi_cmd_reply_end,
2699 ide_atapi_cmd,
2700 ide_dummy_transfer_stop,
2701};
2702
2703static int transfer_end_table_idx(EndTransferFunc *fn)
2704{
2705 int i;
2706
2707 for (i = 0; i < ARRAY_SIZE(transfer_end_table); i++)
2708 if (transfer_end_table[i] == fn)
2709 return i;
2710
2711 return -1;
2712}
2713
37159f13 2714static int ide_drive_post_load(void *opaque, int version_id)
aa941b94 2715{
37159f13
JQ		 2716 IDEState *s = opaque;
2717
6b896ab2 2718 if (s->blk && s->identify_set) {
4be74634 2719 blk_set_enable_write_cache(s->blk, !!(s->identify_data[85] & (1 << 5)));
7cdd481c 2720 }
37159f13 2721 return 0;
aa941b94
AZ		 2722}
2723
50641c5c
JQ		 2724static int ide_drive_pio_post_load(void *opaque, int version_id)
2725{
2726 IDEState *s = opaque;
2727
fb60105d 2728 if (s->end_transfer_fn_idx >= ARRAY_SIZE(transfer_end_table)) {
50641c5c
JQ		 2729 return -EINVAL;
2730 }
2731 s->end_transfer_func = transfer_end_table[s->end_transfer_fn_idx];
2732 s->data_ptr = s->io_buffer + s->cur_io_buffer_offset;
2733 s->data_end = s->data_ptr + s->cur_io_buffer_len;
819fa276 2734 s->atapi_dma = s->feature & 1; /* as per cmd_packet */
50641c5c
JQ		 2735
2736 return 0;
2737}
2738
44b1ff31 2739static int ide_drive_pio_pre_save(void *opaque)
50641c5c
JQ		 2740{
2741 IDEState *s = opaque;
2742 int idx;
2743
2744 s->cur_io_buffer_offset = s->data_ptr - s->io_buffer;
2745 s->cur_io_buffer_len = s->data_end - s->data_ptr;
2746
2747 idx = transfer_end_table_idx(s->end_transfer_func);
2748 if (idx == -1) {
2749 fprintf(stderr, "%s: invalid end_transfer_func for DRQ_STAT\n",
2750 __func__);
2751 s->end_transfer_fn_idx = 2;
2752 } else {
2753 s->end_transfer_fn_idx = idx;
2754 }
44b1ff31
DDAG		 2755
2756 return 0;
50641c5c
JQ		 2757}
2758
2759static bool ide_drive_pio_state_needed(void *opaque)
2760{
2761 IDEState *s = opaque;
2762
fdc650d7 2763 return ((s->status & DRQ_STAT) != 0)
fd648f10 2764 || (s->bus->error_status & IDE_RETRY_PIO);
50641c5c
JQ		 2765}
2766
db118fe7
MA		 2767static bool ide_tray_state_needed(void *opaque)
2768{
2769 IDEState *s = opaque;
2770
2771 return s->tray_open || s->tray_locked;
2772}
2773
996faf1a
AS		 2774static bool ide_atapi_gesn_needed(void *opaque)
2775{
2776 IDEState *s = opaque;
2777
2778 return s->events.new_media || s->events.eject_request;
2779}
2780
def93791
KW		 2781static bool ide_error_needed(void *opaque)
2782{
2783 IDEBus *bus = opaque;
2784
2785 return (bus->error_status != 0);
2786}
2787
996faf1a 2788/* Fields for GET_EVENT_STATUS_NOTIFICATION ATAPI command */
656fbeff 2789static const VMStateDescription vmstate_ide_atapi_gesn_state = {
996faf1a
AS		 2790 .name ="ide_drive/atapi/gesn_state",
2791 .version_id = 1,
2792 .minimum_version_id = 1,
5cd8cada 2793 .needed = ide_atapi_gesn_needed,
35d08458 2794 .fields = (VMStateField[]) {
996faf1a
AS		 2795 VMSTATE_BOOL(events.new_media, IDEState),
2796 VMSTATE_BOOL(events.eject_request, IDEState),
0754f9ec 2797 VMSTATE_END_OF_LIST()
996faf1a
AS		 2798 }
2799};
2800
db118fe7
MA		 2801static const VMStateDescription vmstate_ide_tray_state = {
2802 .name = "ide_drive/tray_state",
2803 .version_id = 1,
2804 .minimum_version_id = 1,
5cd8cada 2805 .needed = ide_tray_state_needed,
db118fe7
MA		 2806 .fields = (VMStateField[]) {
2807 VMSTATE_BOOL(tray_open, IDEState),
2808 VMSTATE_BOOL(tray_locked, IDEState),
2809 VMSTATE_END_OF_LIST()
2810 }
2811};
2812
656fbeff 2813static const VMStateDescription vmstate_ide_drive_pio_state = {
50641c5c
JQ		 2814 .name = "ide_drive/pio_state",
2815 .version_id = 1,
2816 .minimum_version_id = 1,
50641c5c
JQ		 2817 .pre_save = ide_drive_pio_pre_save,
2818 .post_load = ide_drive_pio_post_load,
5cd8cada 2819 .needed = ide_drive_pio_state_needed,
35d08458 2820 .fields = (VMStateField[]) {
50641c5c
JQ		 2821 VMSTATE_INT32(req_nb_sectors, IDEState),
2822 VMSTATE_VARRAY_INT32(io_buffer, IDEState, io_buffer_total_len, 1,
7d37435b 2823 vmstate_info_uint8, uint8_t),
50641c5c
JQ		 2824 VMSTATE_INT32(cur_io_buffer_offset, IDEState),
2825 VMSTATE_INT32(cur_io_buffer_len, IDEState),
2826 VMSTATE_UINT8(end_transfer_fn_idx, IDEState),
2827 VMSTATE_INT32(elementary_transfer_size, IDEState),
2828 VMSTATE_INT32(packet_transfer_size, IDEState),
2829 VMSTATE_END_OF_LIST()
2830 }
2831};
2832
37159f13
JQ		 2833const VMStateDescription vmstate_ide_drive = {
2834 .name = "ide_drive",
3abb6260 2835 .version_id = 3,
37159f13 2836 .minimum_version_id = 0,
37159f13 2837 .post_load = ide_drive_post_load,
35d08458 2838 .fields = (VMStateField[]) {
37159f13
JQ		 2839 VMSTATE_INT32(mult_sectors, IDEState),
2840 VMSTATE_INT32(identify_set, IDEState),
2841 VMSTATE_BUFFER_TEST(identify_data, IDEState, is_identify_set),
2842 VMSTATE_UINT8(feature, IDEState),
2843 VMSTATE_UINT8(error, IDEState),
2844 VMSTATE_UINT32(nsector, IDEState),
2845 VMSTATE_UINT8(sector, IDEState),
2846 VMSTATE_UINT8(lcyl, IDEState),
2847 VMSTATE_UINT8(hcyl, IDEState),
2848 VMSTATE_UINT8(hob_feature, IDEState),
2849 VMSTATE_UINT8(hob_sector, IDEState),
2850 VMSTATE_UINT8(hob_nsector, IDEState),
2851 VMSTATE_UINT8(hob_lcyl, IDEState),
2852 VMSTATE_UINT8(hob_hcyl, IDEState),
2853 VMSTATE_UINT8(select, IDEState),
2854 VMSTATE_UINT8(status, IDEState),
2855 VMSTATE_UINT8(lba48, IDEState),
2856 VMSTATE_UINT8(sense_key, IDEState),
2857 VMSTATE_UINT8(asc, IDEState),
2858 VMSTATE_UINT8_V(cdrom_changed, IDEState, 3),
37159f13 2859 VMSTATE_END_OF_LIST()
50641c5c 2860 },
5cd8cada
JQ		 2861 .subsections = (const VMStateDescription*[]) {
2862 &vmstate_ide_drive_pio_state,
2863 &vmstate_ide_tray_state,
2864 &vmstate_ide_atapi_gesn_state,
2865 NULL
37159f13
JQ		 2866 }
2867};
2868
656fbeff 2869static const VMStateDescription vmstate_ide_error_status = {
def93791 2870 .name ="ide_bus/error",
d12b9ff2 2871 .version_id = 2,
def93791 2872 .minimum_version_id = 1,
5cd8cada 2873 .needed = ide_error_needed,
35d08458 2874 .fields = (VMStateField[]) {
def93791 2875 VMSTATE_INT32(error_status, IDEBus),
d12b9ff2
PB		 2876 VMSTATE_INT64_V(retry_sector_num, IDEBus, 2),
2877 VMSTATE_UINT32_V(retry_nsector, IDEBus, 2),
2878 VMSTATE_UINT8_V(retry_unit, IDEBus, 2),
def93791
KW		 2879 VMSTATE_END_OF_LIST()
2880 }
2881};
2882
6521dc62
JQ		 2883const VMStateDescription vmstate_ide_bus = {
2884 .name = "ide_bus",
2885 .version_id = 1,
2886 .minimum_version_id = 1,
35d08458 2887 .fields = (VMStateField[]) {
6521dc62
JQ		 2888 VMSTATE_UINT8(cmd, IDEBus),
2889 VMSTATE_UINT8(unit, IDEBus),
2890 VMSTATE_END_OF_LIST()
def93791 2891 },
5cd8cada
JQ		 2892 .subsections = (const VMStateDescription*[]) {
2893 &vmstate_ide_error_status,
2894 NULL
6521dc62
JQ		 2895 }
2896};
75717903 2897
d8f94e1b 2898void ide_drive_get(DriveInfo **hd, int n)
75717903
IY		 2899{
2900 int i;
75717903 2901
d8f94e1b
JS		 2902 for (i = 0; i < n; i++) {
2903 hd[i] = drive_get_by_index(IF_IDE, i);
75717903
IY		 2904 }
2905}
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