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ahci: move PIO Setup FIS before transfer, fix it for ATAPI commands
[qemu.git] / hw / ide / core.c
CommitLineData
5391d806 1/*
38cdea7c 2 * QEMU IDE disk and CD/DVD-ROM Emulator
5fafdf24 3 *
5391d806 4 * Copyright (c) 2003 Fabrice Bellard
201a51fc 5 * Copyright (c) 2006 Openedhand Ltd.
5fafdf24 6 *
5391d806
FB		 7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
e688df6b 25
53239262 26#include "qemu/osdep.h"
a9c94277 27#include "hw/hw.h"
a9c94277 28#include "hw/isa/isa.h"
1de7afc9
PB		 29#include "qemu/error-report.h"
30#include "qemu/timer.h"
9c17d615 31#include "sysemu/sysemu.h"
78631611 32#include "sysemu/blockdev.h"
9c17d615 33#include "sysemu/dma.h"
0d09e41a 34#include "hw/block/block.h"
4be74634 35#include "sysemu/block-backend.h"
e688df6b 36#include "qapi/error.h"
f348b6d1 37#include "qemu/cutils.h"
59f2a787 38
a9c94277 39#include "hw/ide/internal.h"
3eee2611 40#include "trace.h"
e8b54394 41
b93af93d
BW		 42/* These values were based on a Seagate ST3500418AS but have been modified
43 to make more sense in QEMU */
44static const int smart_attributes[][12] = {
45 /* id, flags, hflags, val, wrst, raw (6 bytes), threshold */
46 /* raw read error rate*/
47 { 0x01, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06},
48 /* spin up */
49 { 0x03, 0x03, 0x00, 0x64, 0x64, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
50 /* start stop count */
51 { 0x04, 0x02, 0x00, 0x64, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14},
52 /* remapped sectors */
53 { 0x05, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x24},
54 /* power on hours */
55 { 0x09, 0x03, 0x00, 0x64, 0x64, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
56 /* power cycle count */
57 { 0x0c, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
58 /* airflow-temperature-celsius */
59 { 190, 0x03, 0x00, 0x45, 0x45, 0x1f, 0x00, 0x1f, 0x1f, 0x00, 0x00, 0x32},
e8b54394
BW		 60};
61
0e168d35
JS		 62const char *IDE_DMA_CMD_lookup[IDE_DMA__COUNT] = {
63 [IDE_DMA_READ] = "DMA READ",
64 [IDE_DMA_WRITE] = "DMA WRITE",
65 [IDE_DMA_TRIM] = "DMA TRIM",
66 [IDE_DMA_ATAPI] = "DMA ATAPI"
67};
68
69static const char *IDE_DMA_CMD_str(enum ide_dma_cmd enval)
70{
159a9df0 71 if ((unsigned)enval < IDE_DMA__COUNT) {
0e168d35
JS		 72 return IDE_DMA_CMD_lookup[enval];
73 }
74 return "DMA UNKNOWN CMD";
75}
76
40c4ed3f 77static void ide_dummy_transfer_stop(IDEState *s);
98087450 78
5391d806
FB		 79static void padstr(char *str, const char *src, int len)
80{
81 int i, v;
82 for(i = 0; i < len; i++) {
83 if (*src)
84 v = *src++;
85 else
86 v = ' ';
69b34976 87 str[i^1] = v;
5391d806
FB		 88 }
89}
90
67b915a5
FB		 91static void put_le16(uint16_t *p, unsigned int v)
92{
0c4ad8dc 93 *p = cpu_to_le16(v);
67b915a5
FB		 94}
95
01ce352e
JS		 96static void ide_identify_size(IDEState *s)
97{
98 uint16_t *p = (uint16_t *)s->identify_data;
99 put_le16(p + 60, s->nb_sectors);
100 put_le16(p + 61, s->nb_sectors >> 16);
101 put_le16(p + 100, s->nb_sectors);
102 put_le16(p + 101, s->nb_sectors >> 16);
103 put_le16(p + 102, s->nb_sectors >> 32);
104 put_le16(p + 103, s->nb_sectors >> 48);
105}
106
5391d806
FB		 107static void ide_identify(IDEState *s)
108{
109 uint16_t *p;
110 unsigned int oldsize;
d353fb72 111 IDEDevice *dev = s->unit ? s->bus->slave : s->bus->master;
5391d806 112
4bf6637d 113 p = (uint16_t *)s->identify_data;
94458802 114 if (s->identify_set) {
4bf6637d 115 goto fill_buffer;
94458802 116 }
4bf6637d 117 memset(p, 0, sizeof(s->identify_data));
94458802 118
67b915a5 119 put_le16(p + 0, 0x0040);
5fafdf24 120 put_le16(p + 1, s->cylinders);
67b915a5
FB		 121 put_le16(p + 3, s->heads);
122 put_le16(p + 4, 512 * s->sectors); /* XXX: retired, remove ? */
123 put_le16(p + 5, 512); /* XXX: retired, remove ? */
5fafdf24 124 put_le16(p + 6, s->sectors);
fa879c64 125 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
67b915a5
FB		 126 put_le16(p + 20, 3); /* XXX: retired, remove ? */
127 put_le16(p + 21, 512); /* cache size in sectors */
128 put_le16(p + 22, 4); /* ecc bytes */
47c06340 129 padstr((char *)(p + 23), s->version, 8); /* firmware version */
27e0c9a1 130 padstr((char *)(p + 27), s->drive_model_str, 40); /* model */
3b46e624 131#if MAX_MULT_SECTORS > 1
67b915a5 132 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
5391d806 133#endif
67b915a5 134 put_le16(p + 48, 1); /* dword I/O */
94458802 135 put_le16(p + 49, (1 << 11) | (1 << 9) | (1 << 8)); /* DMA and LBA supported */
67b915a5
FB		 136 put_le16(p + 51, 0x200); /* PIO transfer cycle */
137 put_le16(p + 52, 0x200); /* DMA transfer cycle */
94458802 138 put_le16(p + 53, 1 | (1 << 1) | (1 << 2)); /* words 54-58,64-70,88 are valid */
67b915a5
FB		 139 put_le16(p + 54, s->cylinders);
140 put_le16(p + 55, s->heads);
141 put_le16(p + 56, s->sectors);
5391d806 142 oldsize = s->cylinders * s->heads * s->sectors;
67b915a5
FB		 143 put_le16(p + 57, oldsize);
144 put_le16(p + 58, oldsize >> 16);
5391d806 145 if (s->mult_sectors)
67b915a5 146 put_le16(p + 59, 0x100 | s->mult_sectors);
01ce352e
JS		 147 /* *(p + 60) := nb_sectors -- see ide_identify_size */
148 /* *(p + 61) := nb_sectors >> 16 -- see ide_identify_size */
d1b5c20d 149 put_le16(p + 62, 0x07); /* single word dma0-2 supported */
94458802 150 put_le16(p + 63, 0x07); /* mdma0-2 supported */
79d1d331 151 put_le16(p + 64, 0x03); /* pio3-4 supported */
94458802
FB		 152 put_le16(p + 65, 120);
153 put_le16(p + 66, 120);
154 put_le16(p + 67, 120);
155 put_le16(p + 68, 120);
d353fb72
CH		 156 if (dev && dev->conf.discard_granularity) {
157 put_le16(p + 69, (1 << 14)); /* determinate TRIM behavior */
158 }
ccf0fd8b
RE		 159
160 if (s->ncq_queues) {
161 put_le16(p + 75, s->ncq_queues - 1);
162 /* NCQ supported */
163 put_le16(p + 76, (1 << 8));
164 }
165
94458802
FB		 166 put_le16(p + 80, 0xf0); /* ata3 -> ata6 supported */
167 put_le16(p + 81, 0x16); /* conforms to ata5 */
a58b8d54
CH		 168 /* 14=NOP supported, 5=WCACHE supported, 0=SMART supported */
169 put_le16(p + 82, (1 << 14) | (1 << 5) | 1);
c2ff060f
FB		 170 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
171 put_le16(p + 83, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10));
95ebda85
FB		 172 /* 14=set to 1, 8=has WWN, 1=SMART self test, 0=SMART error logging */
173 if (s->wwn) {
174 put_le16(p + 84, (1 << 14) | (1 << 8) | 0);
175 } else {
176 put_le16(p + 84, (1 << 14) | 0);
177 }
e900a7b7 178 /* 14 = NOP supported, 5=WCACHE enabled, 0=SMART feature set enabled */
4be74634
MA		 179 if (blk_enable_write_cache(s->blk)) {
180 put_le16(p + 85, (1 << 14) | (1 << 5) | 1);
181 } else {
182 put_le16(p + 85, (1 << 14) | 1);
183 }
c2ff060f 184 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
2844bdd9 185 put_le16(p + 86, (1 << 13) | (1 <<12) | (1 << 10));
95ebda85
FB		 186 /* 14=set to 1, 8=has WWN, 1=SMART self test, 0=SMART error logging */
187 if (s->wwn) {
188 put_le16(p + 87, (1 << 14) | (1 << 8) | 0);
189 } else {
190 put_le16(p + 87, (1 << 14) | 0);
191 }
94458802
FB		 192 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
193 put_le16(p + 93, 1 | (1 << 14) | 0x2000);
01ce352e
JS		 194 /* *(p + 100) := nb_sectors -- see ide_identify_size */
195 /* *(p + 101) := nb_sectors >> 16 -- see ide_identify_size */
196 /* *(p + 102) := nb_sectors >> 32 -- see ide_identify_size */
197 /* *(p + 103) := nb_sectors >> 48 -- see ide_identify_size */
d353fb72 198
57dac7ef
MA		 199 if (dev && dev->conf.physical_block_size)
200 put_le16(p + 106, 0x6000 | get_physical_block_exp(&dev->conf));
95ebda85
FB		 201 if (s->wwn) {
202 /* LE 16-bit words 111-108 contain 64-bit World Wide Name */
203 put_le16(p + 108, s->wwn >> 48);
204 put_le16(p + 109, s->wwn >> 32);
205 put_le16(p + 110, s->wwn >> 16);
206 put_le16(p + 111, s->wwn);
207 }
d353fb72
CH		 208 if (dev && dev->conf.discard_granularity) {
209 put_le16(p + 169, 1); /* TRIM support */
210 }
96f43c2b
DB		 211 if (dev) {
212 put_le16(p + 217, dev->rotation_rate); /* Nominal media rotation rate */
213 }
94458802 214
01ce352e 215 ide_identify_size(s);
94458802 216 s->identify_set = 1;
4bf6637d
JS		 217
218fill_buffer:
219 memcpy(s->io_buffer, p, sizeof(s->identify_data));
5391d806
FB		 220}
221
222static void ide_atapi_identify(IDEState *s)
223{
224 uint16_t *p;
225
4bf6637d 226 p = (uint16_t *)s->identify_data;
94458802 227 if (s->identify_set) {
4bf6637d 228 goto fill_buffer;
94458802 229 }
4bf6637d 230 memset(p, 0, sizeof(s->identify_data));
94458802 231
5391d806 232 /* Removable CDROM, 50us response, 12 byte packets */
67b915a5 233 put_le16(p + 0, (2 << 14) | (5 << 8) | (1 << 7) | (2 << 5) | (0 << 0));
fa879c64 234 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
67b915a5
FB		 235 put_le16(p + 20, 3); /* buffer type */
236 put_le16(p + 21, 512); /* cache size in sectors */
237 put_le16(p + 22, 4); /* ecc bytes */
47c06340 238 padstr((char *)(p + 23), s->version, 8); /* firmware version */
27e0c9a1 239 padstr((char *)(p + 27), s->drive_model_str, 40); /* model */
67b915a5 240 put_le16(p + 48, 1); /* dword I/O (XXX: should not be set on CDROM) */
8ccad811
FB		 241#ifdef USE_DMA_CDROM
242 put_le16(p + 49, 1 << 9 | 1 << 8); /* DMA and LBA supported */
243 put_le16(p + 53, 7); /* words 64-70, 54-58, 88 valid */
d1b5c20d 244 put_le16(p + 62, 7); /* single word dma0-2 supported */
8ccad811 245 put_le16(p + 63, 7); /* mdma0-2 supported */
8ccad811 246#else
67b915a5
FB		 247 put_le16(p + 49, 1 << 9); /* LBA supported, no DMA */
248 put_le16(p + 53, 3); /* words 64-70, 54-58 valid */
249 put_le16(p + 63, 0x103); /* DMA modes XXX: may be incorrect */
8ccad811 250#endif
79d1d331 251 put_le16(p + 64, 3); /* pio3-4 supported */
67b915a5
FB		 252 put_le16(p + 65, 0xb4); /* minimum DMA multiword tx cycle time */
253 put_le16(p + 66, 0xb4); /* recommended DMA multiword tx cycle time */
254 put_le16(p + 67, 0x12c); /* minimum PIO cycle time without flow control */
255 put_le16(p + 68, 0xb4); /* minimum PIO cycle time with IORDY flow control */
94458802 256
67b915a5
FB		 257 put_le16(p + 71, 30); /* in ns */
258 put_le16(p + 72, 30); /* in ns */
5391d806 259
1bdaa28d
AG		 260 if (s->ncq_queues) {
261 put_le16(p + 75, s->ncq_queues - 1);
262 /* NCQ supported */
263 put_le16(p + 76, (1 << 8));
264 }
265
67b915a5 266 put_le16(p + 80, 0x1e); /* support up to ATA/ATAPI-4 */
c5fe97e3
JS		 267 if (s->wwn) {
268 put_le16(p + 84, (1 << 8)); /* supports WWN for words 108-111 */
269 put_le16(p + 87, (1 << 8)); /* WWN enabled */
270 }
271
8ccad811
FB		 272#ifdef USE_DMA_CDROM
273 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
274#endif
c5fe97e3
JS		 275
276 if (s->wwn) {
277 /* LE 16-bit words 111-108 contain 64-bit World Wide Name */
278 put_le16(p + 108, s->wwn >> 48);
279 put_le16(p + 109, s->wwn >> 32);
280 put_le16(p + 110, s->wwn >> 16);
281 put_le16(p + 111, s->wwn);
282 }
283
94458802 284 s->identify_set = 1;
4bf6637d
JS		 285
286fill_buffer:
287 memcpy(s->io_buffer, p, sizeof(s->identify_data));
5391d806
FB		 288}
289
01ce352e
JS		 290static void ide_cfata_identify_size(IDEState *s)
291{
292 uint16_t *p = (uint16_t *)s->identify_data;
293 put_le16(p + 7, s->nb_sectors >> 16); /* Sectors per card */
294 put_le16(p + 8, s->nb_sectors); /* Sectors per card */
295 put_le16(p + 60, s->nb_sectors); /* Total LBA sectors */
296 put_le16(p + 61, s->nb_sectors >> 16); /* Total LBA sectors */
297}
298
201a51fc
AZ		 299static void ide_cfata_identify(IDEState *s)
300{
301 uint16_t *p;
302 uint32_t cur_sec;
201a51fc 303
4bf6637d
JS		 304 p = (uint16_t *)s->identify_data;
305 if (s->identify_set) {
201a51fc 306 goto fill_buffer;
4bf6637d 307 }
201a51fc
AZ		 308 memset(p, 0, sizeof(s->identify_data));
309
310 cur_sec = s->cylinders * s->heads * s->sectors;
311
312 put_le16(p + 0, 0x848a); /* CF Storage Card signature */
313 put_le16(p + 1, s->cylinders); /* Default cylinders */
314 put_le16(p + 3, s->heads); /* Default heads */
315 put_le16(p + 6, s->sectors); /* Default sectors per track */
01ce352e
JS		 316 /* *(p + 7) := nb_sectors >> 16 -- see ide_cfata_identify_size */
317 /* *(p + 8) := nb_sectors -- see ide_cfata_identify_size */
fa879c64 318 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
201a51fc 319 put_le16(p + 22, 0x0004); /* ECC bytes */
47c06340 320 padstr((char *) (p + 23), s->version, 8); /* Firmware Revision */
27e0c9a1 321 padstr((char *) (p + 27), s->drive_model_str, 40);/* Model number */
201a51fc
AZ		 322#if MAX_MULT_SECTORS > 1
323 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
324#else
325 put_le16(p + 47, 0x0000);
326#endif
327 put_le16(p + 49, 0x0f00); /* Capabilities */
328 put_le16(p + 51, 0x0002); /* PIO cycle timing mode */
329 put_le16(p + 52, 0x0001); /* DMA cycle timing mode */
330 put_le16(p + 53, 0x0003); /* Translation params valid */
331 put_le16(p + 54, s->cylinders); /* Current cylinders */
332 put_le16(p + 55, s->heads); /* Current heads */
333 put_le16(p + 56, s->sectors); /* Current sectors */
334 put_le16(p + 57, cur_sec); /* Current capacity */
335 put_le16(p + 58, cur_sec >> 16); /* Current capacity */
336 if (s->mult_sectors) /* Multiple sector setting */
337 put_le16(p + 59, 0x100 | s->mult_sectors);
01ce352e
JS		 338 /* *(p + 60) := nb_sectors -- see ide_cfata_identify_size */
339 /* *(p + 61) := nb_sectors >> 16 -- see ide_cfata_identify_size */
201a51fc
AZ		 340 put_le16(p + 63, 0x0203); /* Multiword DMA capability */
341 put_le16(p + 64, 0x0001); /* Flow Control PIO support */
342 put_le16(p + 65, 0x0096); /* Min. Multiword DMA cycle */
343 put_le16(p + 66, 0x0096); /* Rec. Multiword DMA cycle */
344 put_le16(p + 68, 0x00b4); /* Min. PIO cycle time */
345 put_le16(p + 82, 0x400c); /* Command Set supported */
346 put_le16(p + 83, 0x7068); /* Command Set supported */
347 put_le16(p + 84, 0x4000); /* Features supported */
348 put_le16(p + 85, 0x000c); /* Command Set enabled */
349 put_le16(p + 86, 0x7044); /* Command Set enabled */
350 put_le16(p + 87, 0x4000); /* Features enabled */
351 put_le16(p + 91, 0x4060); /* Current APM level */
352 put_le16(p + 129, 0x0002); /* Current features option */
353 put_le16(p + 130, 0x0005); /* Reassigned sectors */
354 put_le16(p + 131, 0x0001); /* Initial power mode */
355 put_le16(p + 132, 0x0000); /* User signature */
356 put_le16(p + 160, 0x8100); /* Power requirement */
357 put_le16(p + 161, 0x8001); /* CF command set */
358
01ce352e 359 ide_cfata_identify_size(s);
201a51fc
AZ		 360 s->identify_set = 1;
361
362fill_buffer:
363 memcpy(s->io_buffer, p, sizeof(s->identify_data));
364}
365
5391d806
FB		 366static void ide_set_signature(IDEState *s)
367{
368 s->select &= 0xf0; /* clear head */
369 /* put signature */
370 s->nsector = 1;
371 s->sector = 1;
cd8722bb 372 if (s->drive_kind == IDE_CD) {
5391d806
FB		 373 s->lcyl = 0x14;
374 s->hcyl = 0xeb;
4be74634 375 } else if (s->blk) {
5391d806
FB		 376 s->lcyl = 0;
377 s->hcyl = 0;
378 } else {
379 s->lcyl = 0xff;
380 s->hcyl = 0xff;
381 }
382}
383
d8b070fe
AN		 384static bool ide_sect_range_ok(IDEState *s,
385 uint64_t sector, uint64_t nb_sectors)
386{
387 uint64_t total_sectors;
388
389 blk_get_geometry(s->blk, &total_sectors);
390 if (sector > total_sectors || nb_sectors > total_sectors - sector) {
391 return false;
392 }
393 return true;
394}
395
d353fb72 396typedef struct TrimAIOCB {
7c84b1b8 397 BlockAIOCB common;
ef0e64a9 398 IDEState *s;
d353fb72
CH		 399 QEMUBH *bh;
400 int ret;
501378c3 401 QEMUIOVector *qiov;
7c84b1b8 402 BlockAIOCB *aiocb;
501378c3 403 int i, j;
d353fb72
CH		 404} TrimAIOCB;
405
7c84b1b8 406static void trim_aio_cancel(BlockAIOCB *acb)
d353fb72
CH		 407{
408 TrimAIOCB *iocb = container_of(acb, TrimAIOCB, common);
409
e551c999 410 /* Exit the loop so ide_issue_trim_cb will not continue */
501378c3
PB		 411 iocb->j = iocb->qiov->niov - 1;
412 iocb->i = (iocb->qiov->iov[iocb->j].iov_len / 8) - 1;
413
e551c999 414 iocb->ret = -ECANCELED;
501378c3
PB		 415
416 if (iocb->aiocb) {
4be74634 417 blk_aio_cancel_async(iocb->aiocb);
e551c999 418 iocb->aiocb = NULL;
501378c3 419 }
d353fb72
CH		 420}
421
d7331bed 422static const AIOCBInfo trim_aiocb_info = {
d353fb72 423 .aiocb_size = sizeof(TrimAIOCB),
e551c999 424 .cancel_async = trim_aio_cancel,
d353fb72
CH		 425};
426
427static void ide_trim_bh_cb(void *opaque)
428{
429 TrimAIOCB *iocb = opaque;
430
caeadbc8
AN		 431 iocb->common.cb(iocb->common.opaque, iocb->ret);
432
d353fb72
CH		 433 qemu_bh_delete(iocb->bh);
434 iocb->bh = NULL;
8007429a 435 qemu_aio_unref(iocb);
d353fb72
CH		 436}
437
501378c3
PB		 438static void ide_issue_trim_cb(void *opaque, int ret)
439{
440 TrimAIOCB *iocb = opaque;
ef0e64a9
AN		 441 IDEState *s = iocb->s;
442
501378c3
PB		 443 if (ret >= 0) {
444 while (iocb->j < iocb->qiov->niov) {
445 int j = iocb->j;
446 while (++iocb->i < iocb->qiov->iov[j].iov_len / 8) {
447 int i = iocb->i;
448 uint64_t *buffer = iocb->qiov->iov[j].iov_base;
449
450 /* 6-byte LBA + 2-byte range per entry */
451 uint64_t entry = le64_to_cpu(buffer[i]);
452 uint64_t sector = entry & 0x0000ffffffffffffULL;
453 uint16_t count = entry >> 48;
454
455 if (count == 0) {
456 continue;
457 }
458
947858b0 459 if (!ide_sect_range_ok(s, sector, count)) {
caeadbc8 460 iocb->ret = -EINVAL;
947858b0
AN		 461 goto done;
462 }
463
501378c3 464 /* Got an entry! Submit and exit. */
ef0e64a9 465 iocb->aiocb = blk_aio_pdiscard(s->blk,
1c6c4bb7
EB		 466 sector << BDRV_SECTOR_BITS,
467 count << BDRV_SECTOR_BITS,
468 ide_issue_trim_cb, opaque);
501378c3
PB		 469 return;
470 }
471
472 iocb->j++;
473 iocb->i = -1;
474 }
475 } else {
476 iocb->ret = ret;
477 }
478
947858b0 479done:
501378c3
PB		 480 iocb->aiocb = NULL;
481 if (iocb->bh) {
482 qemu_bh_schedule(iocb->bh);
483 }
484}
485
8a8e63eb
PB		 486BlockAIOCB *ide_issue_trim(
487 int64_t offset, QEMUIOVector *qiov,
488 BlockCompletionFunc *cb, void *cb_opaque, void *opaque)
d353fb72 489{
ef0e64a9 490 IDEState *s = opaque;
d353fb72 491 TrimAIOCB *iocb;
d353fb72 492
ef0e64a9
AN		 493 iocb = blk_aio_get(&trim_aiocb_info, s->blk, cb, cb_opaque);
494 iocb->s = s;
d353fb72
CH		 495 iocb->bh = qemu_bh_new(ide_trim_bh_cb, iocb);
496 iocb->ret = 0;
501378c3
PB		 497 iocb->qiov = qiov;
498 iocb->i = -1;
499 iocb->j = 0;
500 ide_issue_trim_cb(iocb, 0);
d353fb72
CH		 501 return &iocb->common;
502}
503
9ef2e93f 504void ide_abort_command(IDEState *s)
5391d806 505{
08ee9e33 506 ide_transfer_stop(s);
5391d806
FB		 507 s->status = READY_STAT | ERR_STAT;
508 s->error = ABRT_ERR;
509}
510
0eeee07e
EY		 511static void ide_set_retry(IDEState *s)
512{
513 s->bus->retry_unit = s->unit;
514 s->bus->retry_sector_num = ide_get_sector(s);
515 s->bus->retry_nsector = s->nsector;
516}
517
518static void ide_clear_retry(IDEState *s)
519{
520 s->bus->retry_unit = -1;
521 s->bus->retry_sector_num = 0;
522 s->bus->retry_nsector = 0;
523}
524
5391d806 525/* prepare data transfer and tell what to do after */
33231e0e
KW		 526void ide_transfer_start(IDEState *s, uint8_t *buf, int size,
527 EndTransferFunc *end_transfer_func)
5391d806
FB		 528{
529 s->end_transfer_func = end_transfer_func;
530 s->data_ptr = buf;
531 s->data_end = buf + size;
35f78ab4 532 ide_set_retry(s);
40a6238a 533 if (!(s->status & ERR_STAT)) {
7603d156 534 s->status |= DRQ_STAT;
40a6238a 535 }
44635123
PB		 536 if (s->bus->dma->ops->start_transfer) {
537 s->bus->dma->ops->start_transfer(s->bus->dma);
538 }
5391d806
FB		 539}
540
c7e73adb
PB		 541static void ide_cmd_done(IDEState *s)
542{
543 if (s->bus->dma->ops->cmd_done) {
544 s->bus->dma->ops->cmd_done(s->bus->dma);
545 }
546}
547
e3044e23
JS		 548static void ide_transfer_halt(IDEState *s,
549 void(*end_transfer_func)(IDEState *),
550 bool notify)
5391d806 551{
e3044e23 552 s->end_transfer_func = end_transfer_func;
5391d806
FB		 553 s->data_ptr = s->io_buffer;
554 s->data_end = s->io_buffer;
555 s->status &= ~DRQ_STAT;
e3044e23
JS		 556 if (notify) {
557 ide_cmd_done(s);
558 }
559}
560
561void ide_transfer_stop(IDEState *s)
562{
563 ide_transfer_halt(s, ide_transfer_stop, true);
564}
565
e3044e23
JS		 566static void ide_transfer_cancel(IDEState *s)
567{
568 ide_transfer_halt(s, ide_transfer_cancel, false);
5391d806
FB		 569}
570
356721ae 571int64_t ide_get_sector(IDEState *s)
5391d806
FB		 572{
573 int64_t sector_num;
574 if (s->select & 0x40) {
575 /* lba */
c2ff060f
FB		 576 if (!s->lba48) {
577 sector_num = ((s->select & 0x0f) << 24) | (s->hcyl << 16) |
578 (s->lcyl << 8) | s->sector;
579 } else {
580 sector_num = ((int64_t)s->hob_hcyl << 40) |
581 ((int64_t) s->hob_lcyl << 32) |
582 ((int64_t) s->hob_sector << 24) |
583 ((int64_t) s->hcyl << 16) |
584 ((int64_t) s->lcyl << 8) | s->sector;
585 }
5391d806
FB		 586 } else {
587 sector_num = ((s->hcyl << 8) | s->lcyl) * s->heads * s->sectors +
c2ff060f 588 (s->select & 0x0f) * s->sectors + (s->sector - 1);
5391d806
FB		 589 }
590 return sector_num;
591}
592
356721ae 593void ide_set_sector(IDEState *s, int64_t sector_num)
5391d806
FB		 594{
595 unsigned int cyl, r;
596 if (s->select & 0x40) {
c2ff060f
FB		 597 if (!s->lba48) {
598 s->select = (s->select & 0xf0) | (sector_num >> 24);
599 s->hcyl = (sector_num >> 16);
600 s->lcyl = (sector_num >> 8);
601 s->sector = (sector_num);
602 } else {
603 s->sector = sector_num;
604 s->lcyl = sector_num >> 8;
605 s->hcyl = sector_num >> 16;
606 s->hob_sector = sector_num >> 24;
607 s->hob_lcyl = sector_num >> 32;
608 s->hob_hcyl = sector_num >> 40;
609 }
5391d806
FB		 610 } else {
611 cyl = sector_num / (s->heads * s->sectors);
612 r = sector_num % (s->heads * s->sectors);
613 s->hcyl = cyl >> 8;
614 s->lcyl = cyl;
1b8eb456 615 s->select = (s->select & 0xf0) | ((r / s->sectors) & 0x0f);
5391d806
FB		 616 s->sector = (r % s->sectors) + 1;
617 }
618}
619
e162cfb0
AZ		 620static void ide_rw_error(IDEState *s) {
621 ide_abort_command(s);
9cdd03a7 622 ide_set_irq(s->bus);
e162cfb0
AZ		 623}
624
1d8c11d6
PL		 625static void ide_buffered_readv_cb(void *opaque, int ret)
626{
627 IDEBufferedRequest *req = opaque;
628 if (!req->orphaned) {
629 if (!ret) {
630 qemu_iovec_from_buf(req->original_qiov, 0, req->iov.iov_base,
631 req->original_qiov->size);
632 }
633 req->original_cb(req->original_opaque, ret);
634 }
635 QLIST_REMOVE(req, list);
636 qemu_vfree(req->iov.iov_base);
637 g_free(req);
638}
639
640#define MAX_BUFFERED_REQS 16
641
642BlockAIOCB *ide_buffered_readv(IDEState *s, int64_t sector_num,
643 QEMUIOVector *iov, int nb_sectors,
644 BlockCompletionFunc *cb, void *opaque)
645{
646 BlockAIOCB *aioreq;
647 IDEBufferedRequest *req;
648 int c = 0;
649
650 QLIST_FOREACH(req, &s->buffered_requests, list) {
651 c++;
652 }
653 if (c > MAX_BUFFERED_REQS) {
654 return blk_abort_aio_request(s->blk, cb, opaque, -EIO);
655 }
656
657 req = g_new0(IDEBufferedRequest, 1);
658 req->original_qiov = iov;
659 req->original_cb = cb;
660 req->original_opaque = opaque;
661 req->iov.iov_base = qemu_blockalign(blk_bs(s->blk), iov->size);
662 req->iov.iov_len = iov->size;
663 qemu_iovec_init_external(&req->qiov, &req->iov, 1);
664
d4f510eb
EB		 665 aioreq = blk_aio_preadv(s->blk, sector_num << BDRV_SECTOR_BITS,
666 &req->qiov, 0, ide_buffered_readv_cb, req);
1d8c11d6
PL		 667
668 QLIST_INSERT_HEAD(&s->buffered_requests, req, list);
669 return aioreq;
670}
671
86698a12
JS		 672/**
673 * Cancel all pending DMA requests.
674 * Any buffered DMA requests are instantly canceled,
675 * but any pending unbuffered DMA requests must be waited on.
676 */
677void ide_cancel_dma_sync(IDEState *s)
678{
679 IDEBufferedRequest *req;
680
681 /* First invoke the callbacks of all buffered requests
682 * and flag those requests as orphaned. Ideally there
683 * are no unbuffered (Scatter Gather DMA Requests or
684 * write requests) pending and we can avoid to drain. */
685 QLIST_FOREACH(req, &s->buffered_requests, list) {
686 if (!req->orphaned) {
3eee2611 687 trace_ide_cancel_dma_sync_buffered(req->original_cb, req);
86698a12
JS		 688 req->original_cb(req->original_opaque, -ECANCELED);
689 }
690 req->orphaned = true;
691 }
692
693 /*
694 * We can't cancel Scatter Gather DMA in the middle of the
695 * operation or a partial (not full) DMA transfer would reach
696 * the storage so we wait for completion instead (we beahve
697 * like if the DMA was completed by the time the guest trying
698 * to cancel dma with bmdma_cmd_writeb with BM_CMD_START not
699 * set).
700 *
701 * In the future we'll be able to safely cancel the I/O if the
702 * whole DMA operation will be submitted to disk with a single
703 * aio operation with preadv/pwritev.
704 */
705 if (s->bus->dma->aiocb) {
3eee2611 706 trace_ide_cancel_dma_sync_remaining();
51f7b5b8 707 blk_drain(s->blk);
86698a12
JS		 708 assert(s->bus->dma->aiocb == NULL);
709 }
710}
711
4e2b8b4a
PB		 712static void ide_sector_read(IDEState *s);
713
bef0fd59
SH		 714static void ide_sector_read_cb(void *opaque, int ret)
715{
716 IDEState *s = opaque;
717 int n;
718
719 s->pio_aiocb = NULL;
720 s->status &= ~BUSY_STAT;
721
0d910cfe
FZ		 722 if (ret == -ECANCELED) {
723 return;
724 }
bef0fd59 725 if (ret != 0) {
fd648f10
PB		 726 if (ide_handle_rw_error(s, -ret, IDE_RETRY_PIO |
727 IDE_RETRY_READ)) {
bef0fd59
SH		 728 return;
729 }
730 }
731
ecca3b39
AG		 732 block_acct_done(blk_get_stats(s->blk), &s->acct);
733
bef0fd59
SH		 734 n = s->nsector;
735 if (n > s->req_nb_sectors) {
736 n = s->req_nb_sectors;
737 }
738
bef0fd59
SH		 739 ide_set_sector(s, ide_get_sector(s) + n);
740 s->nsector -= n;
dd0bf7ba
JS		 741 /* Allow the guest to read the io_buffer */
742 ide_transfer_start(s, s->io_buffer, n * BDRV_SECTOR_SIZE, ide_sector_read);
dd0bf7ba 743 ide_set_irq(s->bus);
bef0fd59
SH		 744}
745
4e2b8b4a 746static void ide_sector_read(IDEState *s)
5391d806
FB		 747{
748 int64_t sector_num;
bef0fd59 749 int n;
5391d806
FB		 750
751 s->status = READY_STAT | SEEK_STAT;
a136e5a8 752 s->error = 0; /* not needed by IDE spec, but needed by Windows */
5391d806
FB		 753 sector_num = ide_get_sector(s);
754 n = s->nsector;
bef0fd59 755
5391d806 756 if (n == 0) {
5391d806 757 ide_transfer_stop(s);
bef0fd59
SH		 758 return;
759 }
760
761 s->status |= BUSY_STAT;
762
763 if (n > s->req_nb_sectors) {
764 n = s->req_nb_sectors;
765 }
766
3eee2611 767 trace_ide_sector_read(sector_num, n);
a597e79c 768
58ac3211
MA		 769 if (!ide_sect_range_ok(s, sector_num, n)) {
770 ide_rw_error(s);
ecca3b39 771 block_acct_invalid(blk_get_stats(s->blk), BLOCK_ACCT_READ);
58ac3211
MA		 772 return;
773 }
774
bef0fd59
SH		 775 s->iov.iov_base = s->io_buffer;
776 s->iov.iov_len = n * BDRV_SECTOR_SIZE;
777 qemu_iovec_init_external(&s->qiov, &s->iov, 1);
778
4be74634 779 block_acct_start(blk_get_stats(s->blk), &s->acct,
5366d0c8 780 n * BDRV_SECTOR_SIZE, BLOCK_ACCT_READ);
d66a8fa8
PL		 781 s->pio_aiocb = ide_buffered_readv(s, sector_num, &s->qiov, n,
782 ide_sector_read_cb, s);
5391d806
FB		 783}
784
aaeda4a3 785void dma_buf_commit(IDEState *s, uint32_t tx_bytes)
7aea4412 786{
659142ec
JS		 787 if (s->bus->dma->ops->commit_buf) {
788 s->bus->dma->ops->commit_buf(s->bus->dma, tx_bytes);
789 }
aaeda4a3 790 s->io_buffer_offset += tx_bytes;
1fb8648d 791 qemu_sglist_destroy(&s->sg);
7aea4412
AL		 792}
793
0e7ce54c 794void ide_set_inactive(IDEState *s, bool more)
8337606d 795{
40a6238a 796 s->bus->dma->aiocb = NULL;
0eeee07e 797 ide_clear_retry(s);
829b933b 798 if (s->bus->dma->ops->set_inactive) {
0e7ce54c 799 s->bus->dma->ops->set_inactive(s->bus->dma, more);
829b933b 800 }
c7e73adb 801 ide_cmd_done(s);
8337606d
KW		 802}
803
356721ae 804void ide_dma_error(IDEState *s)
e162cfb0 805{
659142ec 806 dma_buf_commit(s, 0);
08ee9e33 807 ide_abort_command(s);
0e7ce54c 808 ide_set_inactive(s, false);
9cdd03a7 809 ide_set_irq(s->bus);
e162cfb0
AZ		 810}
811
502356ee 812int ide_handle_rw_error(IDEState *s, int error, int op)
428c5705 813{
fd648f10 814 bool is_read = (op & IDE_RETRY_READ) != 0;
4be74634 815 BlockErrorAction action = blk_get_error_action(s->blk, is_read, error);
428c5705 816
a589569f 817 if (action == BLOCK_ERROR_ACTION_STOP) {
a96cb236 818 assert(s->bus->retry_unit == s->unit);
def93791 819 s->bus->error_status = op;
a589569f 820 } else if (action == BLOCK_ERROR_ACTION_REPORT) {
ecca3b39 821 block_acct_failed(blk_get_stats(s->blk), &s->acct);
502356ee 822 if (IS_IDE_RETRY_DMA(op)) {
428c5705 823 ide_dma_error(s);
502356ee
PB		 824 } else if (IS_IDE_RETRY_ATAPI(op)) {
825 ide_atapi_io_error(s, -error);
7aea4412 826 } else {
428c5705 827 ide_rw_error(s);
7aea4412 828 }
428c5705 829 }
4be74634 830 blk_error_action(s->blk, action, is_read, error);
a589569f 831 return action != BLOCK_ERROR_ACTION_IGNORE;
428c5705
AL		 832}
833
4e2b8b4a 834static void ide_dma_cb(void *opaque, int ret)
98087450 835{
40a6238a 836 IDEState *s = opaque;
8ccad811
FB		 837 int n;
838 int64_t sector_num;
cbe0ed62 839 uint64_t offset;
038268e2 840 bool stay_active = false;
8ccad811 841
0d910cfe
FZ		 842 if (ret == -ECANCELED) {
843 return;
844 }
caeadbc8
AN		 845
846 if (ret == -EINVAL) {
847 ide_dma_error(s);
848 return;
849 }
850
e162cfb0 851 if (ret < 0) {
218fd37c 852 if (ide_handle_rw_error(s, -ret, ide_dma_cmd_to_retry(s->dma_cmd))) {
87ac25fd 853 s->bus->dma->aiocb = NULL;
5839df7b 854 dma_buf_commit(s, 0);
ce4b6522
KW		 855 return;
856 }
e162cfb0
AZ		 857 }
858
8ccad811 859 n = s->io_buffer_size >> 9;
038268e2
KW		 860 if (n > s->nsector) {
861 /* The PRDs were longer than needed for this request. Shorten them so
862 * we don't get a negative remainder. The Active bit must remain set
863 * after the request completes. */
864 n = s->nsector;
865 stay_active = true;
866 }
867
8ccad811
FB		 868 sector_num = ide_get_sector(s);
869 if (n > 0) {
a718978e
JS		 870 assert(n * 512 == s->sg.size);
871 dma_buf_commit(s, s->sg.size);
8ccad811
FB		 872 sector_num += n;
873 ide_set_sector(s, sector_num);
874 s->nsector -= n;
8ccad811
FB		 875 }
876
877 /* end of transfer ? */
878 if (s->nsector == 0) {
98087450 879 s->status = READY_STAT | SEEK_STAT;
9cdd03a7 880 ide_set_irq(s->bus);
cd369c46 881 goto eot;
98087450 882 }
8ccad811
FB		 883
884 /* launch next transfer */
885 n = s->nsector;
596bb44d 886 s->io_buffer_index = 0;
8ccad811 887 s->io_buffer_size = n * 512;
a718978e 888 if (s->bus->dma->ops->prepare_buf(s->bus->dma, s->io_buffer_size) < 512) {
69c38b8f
KW		 889 /* The PRDs were too short. Reset the Active bit, but don't raise an
890 * interrupt. */
72bcca73 891 s->status = READY_STAT | SEEK_STAT;
3251bdcf 892 dma_buf_commit(s, 0);
7aea4412 893 goto eot;
69c38b8f 894 }
cd369c46 895
0e168d35 896 trace_ide_dma_cb(s, sector_num, n, IDE_DMA_CMD_str(s->dma_cmd));
cd369c46 897
d66168ed
MT		 898 if ((s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) &&
899 !ide_sect_range_ok(s, sector_num, n)) {
58ac3211 900 ide_dma_error(s);
ecca3b39 901 block_acct_invalid(blk_get_stats(s->blk), s->acct.type);
58ac3211
MA		 902 return;
903 }
904
cbe0ed62 905 offset = sector_num << BDRV_SECTOR_BITS;
4e1e0051
CH		 906 switch (s->dma_cmd) {
907 case IDE_DMA_READ:
cbe0ed62 908 s->bus->dma->aiocb = dma_blk_read(s->blk, &s->sg, offset,
99868af3 909 BDRV_SECTOR_SIZE, ide_dma_cb, s);
4e1e0051
CH		 910 break;
911 case IDE_DMA_WRITE:
cbe0ed62 912 s->bus->dma->aiocb = dma_blk_write(s->blk, &s->sg, offset,
99868af3 913 BDRV_SECTOR_SIZE, ide_dma_cb, s);
4e1e0051 914 break;
d353fb72 915 case IDE_DMA_TRIM:
8a8e63eb 916 s->bus->dma->aiocb = dma_blk_io(blk_get_aio_context(s->blk),
99868af3 917 &s->sg, offset, BDRV_SECTOR_SIZE,
ef0e64a9 918 ide_issue_trim, s, ide_dma_cb, s,
4be74634 919 DMA_DIRECTION_TO_DEVICE);
d353fb72 920 break;
502356ee
PB		 921 default:
922 abort();
cd369c46 923 }
cd369c46
CH		 924 return;
925
926eot:
a597e79c 927 if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) {
4be74634 928 block_acct_done(blk_get_stats(s->blk), &s->acct);
a597e79c 929 }
0e7ce54c 930 ide_set_inactive(s, stay_active);
98087450
FB		 931}
932
4e1e0051 933static void ide_sector_start_dma(IDEState *s, enum ide_dma_cmd dma_cmd)
98087450 934{
9da82227 935 s->status = READY_STAT | SEEK_STAT | DRQ_STAT;
98087450 936 s->io_buffer_size = 0;
4e1e0051 937 s->dma_cmd = dma_cmd;
a597e79c
CH		 938
939 switch (dma_cmd) {
940 case IDE_DMA_READ:
4be74634 941 block_acct_start(blk_get_stats(s->blk), &s->acct,
5366d0c8 942 s->nsector * BDRV_SECTOR_SIZE, BLOCK_ACCT_READ);
a597e79c
CH		 943 break;
944 case IDE_DMA_WRITE:
4be74634 945 block_acct_start(blk_get_stats(s->blk), &s->acct,
5366d0c8 946 s->nsector * BDRV_SECTOR_SIZE, BLOCK_ACCT_WRITE);
a597e79c
CH		 947 break;
948 default:
949 break;
950 }
951
4855b576
PB		 952 ide_start_dma(s, ide_dma_cb);
953}
954
097310b5 955void ide_start_dma(IDEState *s, BlockCompletionFunc *cb)
4855b576 956{
c71c06d4 957 s->io_buffer_index = 0;
0eeee07e 958 ide_set_retry(s);
4855b576
PB		 959 if (s->bus->dma->ops->start_dma) {
960 s->bus->dma->ops->start_dma(s->bus->dma, s, cb);
961 }
98087450
FB		 962}
963
4e2b8b4a
PB		 964static void ide_sector_write(IDEState *s);
965
a09db21f
FB		 966static void ide_sector_write_timer_cb(void *opaque)
967{
968 IDEState *s = opaque;
9cdd03a7 969 ide_set_irq(s->bus);
a09db21f
FB		 970}
971
e82dabd8 972static void ide_sector_write_cb(void *opaque, int ret)
5391d806 973{
e82dabd8
SH		 974 IDEState *s = opaque;
975 int n;
a597e79c 976
0d910cfe
FZ		 977 if (ret == -ECANCELED) {
978 return;
979 }
428c5705 980
e82dabd8
SH		 981 s->pio_aiocb = NULL;
982 s->status &= ~BUSY_STAT;
983
e162cfb0 984 if (ret != 0) {
fd648f10 985 if (ide_handle_rw_error(s, -ret, IDE_RETRY_PIO)) {
428c5705 986 return;
e82dabd8 987 }
e162cfb0
AZ		 988 }
989
ecca3b39
AG		 990 block_acct_done(blk_get_stats(s->blk), &s->acct);
991
e82dabd8
SH		 992 n = s->nsector;
993 if (n > s->req_nb_sectors) {
994 n = s->req_nb_sectors;
995 }
5391d806 996 s->nsector -= n;
36334faf 997
6aff22c0 998 ide_set_sector(s, ide_get_sector(s) + n);
5391d806 999 if (s->nsector == 0) {
292eef5a 1000 /* no more sectors to write */
5391d806
FB		 1001 ide_transfer_stop(s);
1002 } else {
e82dabd8
SH		 1003 int n1 = s->nsector;
1004 if (n1 > s->req_nb_sectors) {
5391d806 1005 n1 = s->req_nb_sectors;
e82dabd8
SH		 1006 }
1007 ide_transfer_start(s, s->io_buffer, n1 * BDRV_SECTOR_SIZE,
1008 ide_sector_write);
5391d806 1009 }
3b46e624 1010
31c2a146
TS		 1011 if (win2k_install_hack && ((++s->irq_count % 16) == 0)) {
1012 /* It seems there is a bug in the Windows 2000 installer HDD
1013 IDE driver which fills the disk with empty logs when the
1014 IDE write IRQ comes too early. This hack tries to correct
1015 that at the expense of slower write performances. Use this
1016 option _only_ to install Windows 2000. You must disable it
1017 for normal use. */
73bcb24d
RS		 1018 timer_mod(s->sector_write_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
1019 (NANOSECONDS_PER_SECOND / 1000));
f7736b91 1020 } else {
9cdd03a7 1021 ide_set_irq(s->bus);
31c2a146 1022 }
5391d806
FB		 1023}
1024
4e2b8b4a 1025static void ide_sector_write(IDEState *s)
e82dabd8
SH		 1026{
1027 int64_t sector_num;
1028 int n;
1029
1030 s->status = READY_STAT | SEEK_STAT | BUSY_STAT;
1031 sector_num = ide_get_sector(s);
3eee2611 1032
e82dabd8
SH		 1033 n = s->nsector;
1034 if (n > s->req_nb_sectors) {
1035 n = s->req_nb_sectors;
1036 }
1037
3eee2611
JS		 1038 trace_ide_sector_write(sector_num, n);
1039
58ac3211
MA		 1040 if (!ide_sect_range_ok(s, sector_num, n)) {
1041 ide_rw_error(s);
ecca3b39 1042 block_acct_invalid(blk_get_stats(s->blk), BLOCK_ACCT_WRITE);
58ac3211
MA		 1043 return;
1044 }
1045
e82dabd8
SH		 1046 s->iov.iov_base = s->io_buffer;
1047 s->iov.iov_len = n * BDRV_SECTOR_SIZE;
1048 qemu_iovec_init_external(&s->qiov, &s->iov, 1);
1049
4be74634 1050 block_acct_start(blk_get_stats(s->blk), &s->acct,
c618f331 1051 n * BDRV_SECTOR_SIZE, BLOCK_ACCT_WRITE);
d4f510eb
EB		 1052 s->pio_aiocb = blk_aio_pwritev(s->blk, sector_num << BDRV_SECTOR_BITS,
1053 &s->qiov, 0, ide_sector_write_cb, s);
e82dabd8
SH		 1054}
1055
b0484ae4
CH		 1056static void ide_flush_cb(void *opaque, int ret)
1057{
1058 IDEState *s = opaque;
1059
69f72a22
PB		 1060 s->pio_aiocb = NULL;
1061
0d910cfe
FZ		 1062 if (ret == -ECANCELED) {
1063 return;
1064 }
e2bcadad
KW		 1065 if (ret < 0) {
1066 /* XXX: What sector number to set here? */
fd648f10 1067 if (ide_handle_rw_error(s, -ret, IDE_RETRY_FLUSH)) {
e2bcadad
KW		 1068 return;
1069 }
1070 }
b0484ae4 1071
4be74634
MA		 1072 if (s->blk) {
1073 block_acct_done(blk_get_stats(s->blk), &s->acct);
f7f3ff1d 1074 }
b0484ae4 1075 s->status = READY_STAT | SEEK_STAT;
c7e73adb 1076 ide_cmd_done(s);
b0484ae4
CH		 1077 ide_set_irq(s->bus);
1078}
1079
4e2b8b4a 1080static void ide_flush_cache(IDEState *s)
6bcb1a79 1081{
4be74634 1082 if (s->blk == NULL) {
6bcb1a79 1083 ide_flush_cb(s, 0);
b2df7531
KW		 1084 return;
1085 }
1086
f68ec837 1087 s->status |= BUSY_STAT;
35f78ab4 1088 ide_set_retry(s);
4be74634 1089 block_acct_start(blk_get_stats(s->blk), &s->acct, 0, BLOCK_ACCT_FLUSH);
13471a40 1090 s->pio_aiocb = blk_aio_flush(s->blk, ide_flush_cb, s);
6bcb1a79
KW		 1091}
1092
201a51fc
AZ		 1093static void ide_cfata_metadata_inquiry(IDEState *s)
1094{
1095 uint16_t *p;
1096 uint32_t spd;
1097
1098 p = (uint16_t *) s->io_buffer;
1099 memset(p, 0, 0x200);
1100 spd = ((s->mdata_size - 1) >> 9) + 1;
1101
1102 put_le16(p + 0, 0x0001); /* Data format revision */
1103 put_le16(p + 1, 0x0000); /* Media property: silicon */
1104 put_le16(p + 2, s->media_changed); /* Media status */
1105 put_le16(p + 3, s->mdata_size & 0xffff); /* Capacity in bytes (low) */
1106 put_le16(p + 4, s->mdata_size >> 16); /* Capacity in bytes (high) */
1107 put_le16(p + 5, spd & 0xffff); /* Sectors per device (low) */
1108 put_le16(p + 6, spd >> 16); /* Sectors per device (high) */
1109}
1110
1111static void ide_cfata_metadata_read(IDEState *s)
1112{
1113 uint16_t *p;
1114
1115 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
1116 s->status = ERR_STAT;
1117 s->error = ABRT_ERR;
1118 return;
1119 }
1120
1121 p = (uint16_t *) s->io_buffer;
1122 memset(p, 0, 0x200);
1123
1124 put_le16(p + 0, s->media_changed); /* Media status */
1125 memcpy(p + 1, s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
1126 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
1127 s->nsector << 9), 0x200 - 2));
1128}
1129
1130static void ide_cfata_metadata_write(IDEState *s)
1131{
1132 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
1133 s->status = ERR_STAT;
1134 s->error = ABRT_ERR;
1135 return;
1136 }
1137
1138 s->media_changed = 0;
1139
1140 memcpy(s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
1141 s->io_buffer + 2,
1142 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
1143 s->nsector << 9), 0x200 - 2));
1144}
1145
bd491d6a 1146/* called when the inserted state of the media has changed */
39829a01 1147static void ide_cd_change_cb(void *opaque, bool load, Error **errp)
bd491d6a
TS		 1148{
1149 IDEState *s = opaque;
96b8f136 1150 uint64_t nb_sectors;
bd491d6a 1151
25ad22bc 1152 s->tray_open = !load;
4be74634 1153 blk_get_geometry(s->blk, &nb_sectors);
bd491d6a 1154 s->nb_sectors = nb_sectors;
9118e7f0 1155
4b9b7092
AS		 1156 /*
1157 * First indicate to the guest that a CD has been removed. That's
1158 * done on the next command the guest sends us.
1159 *
67cc61e4 1160 * Then we set UNIT_ATTENTION, by which the guest will
4b9b7092
AS		 1161 * detect a new CD in the drive. See ide_atapi_cmd() for details.
1162 */
93c8cfd9 1163 s->cdrom_changed = 1;
996faf1a 1164 s->events.new_media = true;
2df0a3a3
PB		 1165 s->events.eject_request = false;
1166 ide_set_irq(s->bus);
1167}
1168
1169static void ide_cd_eject_request_cb(void *opaque, bool force)
1170{
1171 IDEState *s = opaque;
1172
1173 s->events.eject_request = true;
1174 if (force) {
1175 s->tray_locked = false;
1176 }
9cdd03a7 1177 ide_set_irq(s->bus);
bd491d6a
TS		 1178}
1179
c2ff060f
FB		 1180static void ide_cmd_lba48_transform(IDEState *s, int lba48)
1181{
1182 s->lba48 = lba48;
1183
1184 /* handle the 'magic' 0 nsector count conversion here. to avoid
1185 * fiddling with the rest of the read logic, we just store the
1186 * full sector count in ->nsector and ignore ->hob_nsector from now
1187 */
1188 if (!s->lba48) {
1189 if (!s->nsector)
1190 s->nsector = 256;
1191 } else {
1192 if (!s->nsector && !s->hob_nsector)
1193 s->nsector = 65536;
1194 else {
1195 int lo = s->nsector;
1196 int hi = s->hob_nsector;
1197
1198 s->nsector = (hi << 8) | lo;
1199 }
1200 }
1201}
1202
bcbdc4d3 1203static void ide_clear_hob(IDEBus *bus)
c2ff060f
FB		 1204{
1205 /* any write clears HOB high bit of device control register */
bcbdc4d3
GH		 1206 bus->ifs[0].select &= ~(1 << 7);
1207 bus->ifs[1].select &= ~(1 << 7);
c2ff060f
FB		 1208}
1209
335ca2f2
JS		 1210/* IOport [W]rite [R]egisters */
1211enum ATA_IOPORT_WR {
1212 ATA_IOPORT_WR_DATA = 0,
1213 ATA_IOPORT_WR_FEATURES = 1,
1214 ATA_IOPORT_WR_SECTOR_COUNT = 2,
1215 ATA_IOPORT_WR_SECTOR_NUMBER = 3,
1216 ATA_IOPORT_WR_CYLINDER_LOW = 4,
1217 ATA_IOPORT_WR_CYLINDER_HIGH = 5,
1218 ATA_IOPORT_WR_DEVICE_HEAD = 6,
1219 ATA_IOPORT_WR_COMMAND = 7,
1220 ATA_IOPORT_WR_NUM_REGISTERS,
1221};
1222
1223const char *ATA_IOPORT_WR_lookup[ATA_IOPORT_WR_NUM_REGISTERS] = {
1224 [ATA_IOPORT_WR_DATA] = "Data",
1225 [ATA_IOPORT_WR_FEATURES] = "Features",
1226 [ATA_IOPORT_WR_SECTOR_COUNT] = "Sector Count",
1227 [ATA_IOPORT_WR_SECTOR_NUMBER] = "Sector Number",
1228 [ATA_IOPORT_WR_CYLINDER_LOW] = "Cylinder Low",
1229 [ATA_IOPORT_WR_CYLINDER_HIGH] = "Cylinder High",
1230 [ATA_IOPORT_WR_DEVICE_HEAD] = "Device/Head",
1231 [ATA_IOPORT_WR_COMMAND] = "Command"
1232};
1233
356721ae 1234void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
caed8802 1235{
bcbdc4d3 1236 IDEBus *bus = opaque;
3eee2611
JS		 1237 IDEState *s = idebus_active_if(bus);
1238 int reg_num = addr & 7;
5391d806 1239
335ca2f2 1240 trace_ide_ioport_write(addr, ATA_IOPORT_WR_lookup[reg_num], val, bus, s);
fcdd25ab
AL		 1241
1242 /* ignore writes to command block while busy with previous command */
3eee2611 1243 if (reg_num != 7 && (s->status & (BUSY_STAT|DRQ_STAT))) {
fcdd25ab 1244 return;
3eee2611 1245 }
fcdd25ab 1246
3eee2611 1247 switch (reg_num) {
5391d806
FB		 1248 case 0:
1249 break;
335ca2f2
JS		 1250 case ATA_IOPORT_WR_FEATURES:
1251 ide_clear_hob(bus);
c45c3d00 1252 /* NOTE: data is written to the two drives */
335ca2f2
JS		 1253 bus->ifs[0].hob_feature = bus->ifs[0].feature;
1254 bus->ifs[1].hob_feature = bus->ifs[1].feature;
bcbdc4d3
GH		 1255 bus->ifs[0].feature = val;
1256 bus->ifs[1].feature = val;
5391d806 1257 break;
335ca2f2 1258 case ATA_IOPORT_WR_SECTOR_COUNT:
bcbdc4d3
GH		 1259 ide_clear_hob(bus);
1260 bus->ifs[0].hob_nsector = bus->ifs[0].nsector;
1261 bus->ifs[1].hob_nsector = bus->ifs[1].nsector;
1262 bus->ifs[0].nsector = val;
1263 bus->ifs[1].nsector = val;
5391d806 1264 break;
335ca2f2 1265 case ATA_IOPORT_WR_SECTOR_NUMBER:
bcbdc4d3
GH		 1266 ide_clear_hob(bus);
1267 bus->ifs[0].hob_sector = bus->ifs[0].sector;
1268 bus->ifs[1].hob_sector = bus->ifs[1].sector;
1269 bus->ifs[0].sector = val;
1270 bus->ifs[1].sector = val;
5391d806 1271 break;
335ca2f2 1272 case ATA_IOPORT_WR_CYLINDER_LOW:
bcbdc4d3
GH		 1273 ide_clear_hob(bus);
1274 bus->ifs[0].hob_lcyl = bus->ifs[0].lcyl;
1275 bus->ifs[1].hob_lcyl = bus->ifs[1].lcyl;
1276 bus->ifs[0].lcyl = val;
1277 bus->ifs[1].lcyl = val;
5391d806 1278 break;
335ca2f2 1279 case ATA_IOPORT_WR_CYLINDER_HIGH:
bcbdc4d3
GH		 1280 ide_clear_hob(bus);
1281 bus->ifs[0].hob_hcyl = bus->ifs[0].hcyl;
1282 bus->ifs[1].hob_hcyl = bus->ifs[1].hcyl;
1283 bus->ifs[0].hcyl = val;
1284 bus->ifs[1].hcyl = val;
5391d806 1285 break;
335ca2f2 1286 case ATA_IOPORT_WR_DEVICE_HEAD:
c2ff060f 1287 /* FIXME: HOB readback uses bit 7 */
bcbdc4d3
GH		 1288 bus->ifs[0].select = (val & ~0x10) | 0xa0;
1289 bus->ifs[1].select = (val | 0x10) | 0xa0;
5391d806 1290 /* select drive */
bcbdc4d3 1291 bus->unit = (val >> 4) & 1;
5391d806
FB		 1292 break;
1293 default:
335ca2f2 1294 case ATA_IOPORT_WR_COMMAND:
5391d806 1295 /* command */
7cff87ff
AG		 1296 ide_exec_cmd(bus, val);
1297 break;
1298 }
1299}
1300
4590355b
JS		 1301static void ide_reset(IDEState *s)
1302{
3eee2611 1303 trace_ide_reset(s);
4590355b
JS		 1304
1305 if (s->pio_aiocb) {
1306 blk_aio_cancel(s->pio_aiocb);
1307 s->pio_aiocb = NULL;
1308 }
1309
1310 if (s->drive_kind == IDE_CFATA)
1311 s->mult_sectors = 0;
1312 else
1313 s->mult_sectors = MAX_MULT_SECTORS;
1314 /* ide regs */
1315 s->feature = 0;
1316 s->error = 0;
1317 s->nsector = 0;
1318 s->sector = 0;
1319 s->lcyl = 0;
1320 s->hcyl = 0;
1321
1322 /* lba48 */
1323 s->hob_feature = 0;
1324 s->hob_sector = 0;
1325 s->hob_nsector = 0;
1326 s->hob_lcyl = 0;
1327 s->hob_hcyl = 0;
1328
1329 s->select = 0xa0;
1330 s->status = READY_STAT | SEEK_STAT;
1331
1332 s->lba48 = 0;
1333
1334 /* ATAPI specific */
1335 s->sense_key = 0;
1336 s->asc = 0;
1337 s->cdrom_changed = 0;
1338 s->packet_transfer_size = 0;
1339 s->elementary_transfer_size = 0;
1340 s->io_buffer_index = 0;
1341 s->cd_sector_size = 0;
1342 s->atapi_dma = 0;
1343 s->tray_locked = 0;
1344 s->tray_open = 0;
1345 /* ATA DMA state */
1346 s->io_buffer_size = 0;
1347 s->req_nb_sectors = 0;
1348
1349 ide_set_signature(s);
1350 /* init the transfer handler so that 0xffff is returned on data
1351 accesses */
1352 s->end_transfer_func = ide_dummy_transfer_stop;
1353 ide_dummy_transfer_stop(s);
1354 s->media_changed = 0;
1355}
1356
b300337e
KW		 1357static bool cmd_nop(IDEState *s, uint8_t cmd)
1358{
1359 return true;
1360}
1361
f34ae00d
JS		 1362static bool cmd_device_reset(IDEState *s, uint8_t cmd)
1363{
1364 /* Halt PIO (in the DRQ phase), then DMA */
1365 ide_transfer_cancel(s);
1366 ide_cancel_dma_sync(s);
1367
1368 /* Reset any PIO commands, reset signature, etc */
1369 ide_reset(s);
1370
1371 /* RESET: ATA8-ACS3 7.10.4 "Normal Outputs";
1372 * ATA8-ACS3 Table 184 "Device Signatures for Normal Output" */
1373 s->status = 0x00;
1374
1375 /* Do not overwrite status register */
1376 return false;
1377}
1378
4286434c
KW		 1379static bool cmd_data_set_management(IDEState *s, uint8_t cmd)
1380{
1381 switch (s->feature) {
1382 case DSM_TRIM:
4be74634 1383 if (s->blk) {
4286434c
KW		 1384 ide_sector_start_dma(s, IDE_DMA_TRIM);
1385 return false;
1386 }
1387 break;
1388 }
1389
1390 ide_abort_command(s);
1391 return true;
1392}
1393
1c66869a
KW		 1394static bool cmd_identify(IDEState *s, uint8_t cmd)
1395{
4be74634 1396 if (s->blk && s->drive_kind != IDE_CD) {
1c66869a
KW		 1397 if (s->drive_kind != IDE_CFATA) {
1398 ide_identify(s);
1399 } else {
1400 ide_cfata_identify(s);
1401 }
1402 s->status = READY_STAT | SEEK_STAT;
1403 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
1404 ide_set_irq(s->bus);
1405 return false;
1406 } else {
1407 if (s->drive_kind == IDE_CD) {
1408 ide_set_signature(s);
1409 }
1410 ide_abort_command(s);
1411 }
1412
1413 return true;
1414}
1415
413860cf
KW		 1416static bool cmd_verify(IDEState *s, uint8_t cmd)
1417{
1418 bool lba48 = (cmd == WIN_VERIFY_EXT);
1419
1420 /* do sector number check ? */
1421 ide_cmd_lba48_transform(s, lba48);
1422
1423 return true;
1424}
1425
adf3a2c4
KW		 1426static bool cmd_set_multiple_mode(IDEState *s, uint8_t cmd)
1427{
1428 if (s->drive_kind == IDE_CFATA && s->nsector == 0) {
1429 /* Disable Read and Write Multiple */
1430 s->mult_sectors = 0;
1431 } else if ((s->nsector & 0xff) != 0 &&
1432 ((s->nsector & 0xff) > MAX_MULT_SECTORS ||
1433 (s->nsector & (s->nsector - 1)) != 0)) {
1434 ide_abort_command(s);
1435 } else {
1436 s->mult_sectors = s->nsector & 0xff;
1437 }
1438
1439 return true;
1440}
1441
1442static bool cmd_read_multiple(IDEState *s, uint8_t cmd)
1443{
1444 bool lba48 = (cmd == WIN_MULTREAD_EXT);
1445
4be74634 1446 if (!s->blk || !s->mult_sectors) {
adf3a2c4
KW		 1447 ide_abort_command(s);
1448 return true;
1449 }
1450
1451 ide_cmd_lba48_transform(s, lba48);
1452 s->req_nb_sectors = s->mult_sectors;
1453 ide_sector_read(s);
1454 return false;
1455}
1456
1457static bool cmd_write_multiple(IDEState *s, uint8_t cmd)
1458{
1459 bool lba48 = (cmd == WIN_MULTWRITE_EXT);
1460 int n;
1461
4be74634 1462 if (!s->blk || !s->mult_sectors) {
adf3a2c4
KW		 1463 ide_abort_command(s);
1464 return true;
1465 }
1466
1467 ide_cmd_lba48_transform(s, lba48);
1468
1469 s->req_nb_sectors = s->mult_sectors;
1470 n = MIN(s->nsector, s->req_nb_sectors);
1471
1472 s->status = SEEK_STAT | READY_STAT;
1473 ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_write);
1474
1475 s->media_changed = 1;
1476
1477 return false;
1478}
1479
0e6498ed
KW		 1480static bool cmd_read_pio(IDEState *s, uint8_t cmd)
1481{
1482 bool lba48 = (cmd == WIN_READ_EXT);
1483
1484 if (s->drive_kind == IDE_CD) {
1485 ide_set_signature(s); /* odd, but ATA4 8.27.5.2 requires it */
1486 ide_abort_command(s);
1487 return true;
1488 }
1489
4be74634 1490 if (!s->blk) {
0e6498ed
KW		 1491 ide_abort_command(s);
1492 return true;
1493 }
1494
1495 ide_cmd_lba48_transform(s, lba48);
1496 s->req_nb_sectors = 1;
1497 ide_sector_read(s);
1498
1499 return false;
1500}
1501
1502static bool cmd_write_pio(IDEState *s, uint8_t cmd)
1503{
1504 bool lba48 = (cmd == WIN_WRITE_EXT);
1505
4be74634 1506 if (!s->blk) {
0e6498ed
KW		 1507 ide_abort_command(s);
1508 return true;
1509 }
1510
1511 ide_cmd_lba48_transform(s, lba48);
1512
1513 s->req_nb_sectors = 1;
1514 s->status = SEEK_STAT | READY_STAT;
1515 ide_transfer_start(s, s->io_buffer, 512, ide_sector_write);
1516
1517 s->media_changed = 1;
1518
1519 return false;
1520}
1521
92a6a6f6
KW		 1522static bool cmd_read_dma(IDEState *s, uint8_t cmd)
1523{
1524 bool lba48 = (cmd == WIN_READDMA_EXT);
1525
4be74634 1526 if (!s->blk) {
92a6a6f6
KW		 1527 ide_abort_command(s);
1528 return true;
1529 }
1530
1531 ide_cmd_lba48_transform(s, lba48);
1532 ide_sector_start_dma(s, IDE_DMA_READ);
1533
1534 return false;
1535}
1536
1537static bool cmd_write_dma(IDEState *s, uint8_t cmd)
1538{
1539 bool lba48 = (cmd == WIN_WRITEDMA_EXT);
1540
4be74634 1541 if (!s->blk) {
92a6a6f6
KW		 1542 ide_abort_command(s);
1543 return true;
1544 }
1545
1546 ide_cmd_lba48_transform(s, lba48);
1547 ide_sector_start_dma(s, IDE_DMA_WRITE);
1548
1549 s->media_changed = 1;
1550
1551 return false;
1552}
1553
9afce429
KW		 1554static bool cmd_flush_cache(IDEState *s, uint8_t cmd)
1555{
1556 ide_flush_cache(s);
1557 return false;
1558}
1559
61fdda37
KW		 1560static bool cmd_seek(IDEState *s, uint8_t cmd)
1561{
1562 /* XXX: Check that seek is within bounds */
1563 return true;
1564}
1565
63a82e6a
KW		 1566static bool cmd_read_native_max(IDEState *s, uint8_t cmd)
1567{
1568 bool lba48 = (cmd == WIN_READ_NATIVE_MAX_EXT);
1569
1570 /* Refuse if no sectors are addressable (e.g. medium not inserted) */
1571 if (s->nb_sectors == 0) {
1572 ide_abort_command(s);
1573 return true;
1574 }
1575
1576 ide_cmd_lba48_transform(s, lba48);
1577 ide_set_sector(s, s->nb_sectors - 1);
1578
1579 return true;
1580}
1581
785f6320
KW		 1582static bool cmd_check_power_mode(IDEState *s, uint8_t cmd)
1583{
1584 s->nsector = 0xff; /* device active or idle */
1585 return true;
1586}
1587
ee03398c
KW		 1588static bool cmd_set_features(IDEState *s, uint8_t cmd)
1589{
1590 uint16_t *identify_data;
1591
4be74634 1592 if (!s->blk) {
ee03398c
KW		 1593 ide_abort_command(s);
1594 return true;
1595 }
1596
1597 /* XXX: valid for CDROM ? */
1598 switch (s->feature) {
1599 case 0x02: /* write cache enable */
4be74634 1600 blk_set_enable_write_cache(s->blk, true);
ee03398c
KW		 1601 identify_data = (uint16_t *)s->identify_data;
1602 put_le16(identify_data + 85, (1 << 14) | (1 << 5) | 1);
1603 return true;
1604 case 0x82: /* write cache disable */
4be74634 1605 blk_set_enable_write_cache(s->blk, false);
ee03398c
KW		 1606 identify_data = (uint16_t *)s->identify_data;
1607 put_le16(identify_data + 85, (1 << 14) | 1);
1608 ide_flush_cache(s);
1609 return false;
1610 case 0xcc: /* reverting to power-on defaults enable */
1611 case 0x66: /* reverting to power-on defaults disable */
1612 case 0xaa: /* read look-ahead enable */
1613 case 0x55: /* read look-ahead disable */
1614 case 0x05: /* set advanced power management mode */
1615 case 0x85: /* disable advanced power management mode */
1616 case 0x69: /* NOP */
1617 case 0x67: /* NOP */
1618 case 0x96: /* NOP */
1619 case 0x9a: /* NOP */
1620 case 0x42: /* enable Automatic Acoustic Mode */
1621 case 0xc2: /* disable Automatic Acoustic Mode */
1622 return true;
1623 case 0x03: /* set transfer mode */
1624 {
1625 uint8_t val = s->nsector & 0x07;
1626 identify_data = (uint16_t *)s->identify_data;
1627
1628 switch (s->nsector >> 3) {
1629 case 0x00: /* pio default */
1630 case 0x01: /* pio mode */
1631 put_le16(identify_data + 62, 0x07);
1632 put_le16(identify_data + 63, 0x07);
1633 put_le16(identify_data + 88, 0x3f);
1634 break;
1635 case 0x02: /* sigle word dma mode*/
1636 put_le16(identify_data + 62, 0x07 | (1 << (val + 8)));
1637 put_le16(identify_data + 63, 0x07);
1638 put_le16(identify_data + 88, 0x3f);
1639 break;
1640 case 0x04: /* mdma mode */
1641 put_le16(identify_data + 62, 0x07);
1642 put_le16(identify_data + 63, 0x07 | (1 << (val + 8)));
1643 put_le16(identify_data + 88, 0x3f);
1644 break;
1645 case 0x08: /* udma mode */
1646 put_le16(identify_data + 62, 0x07);
1647 put_le16(identify_data + 63, 0x07);
1648 put_le16(identify_data + 88, 0x3f | (1 << (val + 8)));
1649 break;
1650 default:
1651 goto abort_cmd;
1652 }
1653 return true;
1654 }
1655 }
1656
1657abort_cmd:
1658 ide_abort_command(s);
1659 return true;
1660}
1661
ee425c78
KW		 1662
1663/*** ATAPI commands ***/
1664
1665static bool cmd_identify_packet(IDEState *s, uint8_t cmd)
1666{
1667 ide_atapi_identify(s);
1668 s->status = READY_STAT | SEEK_STAT;
1669 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
1670 ide_set_irq(s->bus);
1671 return false;
1672}
1673
1674static bool cmd_exec_dev_diagnostic(IDEState *s, uint8_t cmd)
1675{
1676 ide_set_signature(s);
1677
1678 if (s->drive_kind == IDE_CD) {
1679 s->status = 0; /* ATAPI spec (v6) section 9.10 defines packet
1680 * devices to return a clear status register
1681 * with READY_STAT *not* set. */
850484a2 1682 s->error = 0x01;
ee425c78
KW		 1683 } else {
1684 s->status = READY_STAT | SEEK_STAT;
1685 /* The bits of the error register are not as usual for this command!
1686 * They are part of the regular output (this is why ERR_STAT isn't set)
1687 * Device 0 passed, Device 1 passed or not present. */
1688 s->error = 0x01;
1689 ide_set_irq(s->bus);
1690 }
1691
1692 return false;
1693}
1694
ee425c78
KW		 1695static bool cmd_packet(IDEState *s, uint8_t cmd)
1696{
1697 /* overlapping commands not supported */
1698 if (s->feature & 0x02) {
1699 ide_abort_command(s);
1700 return true;
1701 }
1702
1703 s->status = READY_STAT | SEEK_STAT;
1704 s->atapi_dma = s->feature & 1;
502356ee
PB		 1705 if (s->atapi_dma) {
1706 s->dma_cmd = IDE_DMA_ATAPI;
1707 }
ee425c78
KW		 1708 s->nsector = 1;
1709 ide_transfer_start(s, s->io_buffer, ATAPI_PACKET_SIZE,
1710 ide_atapi_cmd);
1711 return false;
1712}
1713
6b1dd744
KW		 1714
1715/*** CF-ATA commands ***/
1716
1717static bool cmd_cfa_req_ext_error_code(IDEState *s, uint8_t cmd)
1718{
1719 s->error = 0x09; /* miscellaneous error */
1720 s->status = READY_STAT | SEEK_STAT;
1721 ide_set_irq(s->bus);
1722
1723 return false;
1724}
1725
1726static bool cmd_cfa_erase_sectors(IDEState *s, uint8_t cmd)
1727{
1728 /* WIN_SECURITY_FREEZE_LOCK has the same ID as CFA_WEAR_LEVEL and is
1729 * required for Windows 8 to work with AHCI */
1730
1731 if (cmd == CFA_WEAR_LEVEL) {
1732 s->nsector = 0;
1733 }
1734
1735 if (cmd == CFA_ERASE_SECTORS) {
1736 s->media_changed = 1;
1737 }
1738
1739 return true;
1740}
1741
1742static bool cmd_cfa_translate_sector(IDEState *s, uint8_t cmd)
1743{
1744 s->status = READY_STAT | SEEK_STAT;
1745
1746 memset(s->io_buffer, 0, 0x200);
1747 s->io_buffer[0x00] = s->hcyl; /* Cyl MSB */
1748 s->io_buffer[0x01] = s->lcyl; /* Cyl LSB */
1749 s->io_buffer[0x02] = s->select; /* Head */
1750 s->io_buffer[0x03] = s->sector; /* Sector */
1751 s->io_buffer[0x04] = ide_get_sector(s) >> 16; /* LBA MSB */
1752 s->io_buffer[0x05] = ide_get_sector(s) >> 8; /* LBA */
1753 s->io_buffer[0x06] = ide_get_sector(s) >> 0; /* LBA LSB */
1754 s->io_buffer[0x13] = 0x00; /* Erase flag */
1755 s->io_buffer[0x18] = 0x00; /* Hot count */
1756 s->io_buffer[0x19] = 0x00; /* Hot count */
1757 s->io_buffer[0x1a] = 0x01; /* Hot count */
1758
1759 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1760 ide_set_irq(s->bus);
1761
1762 return false;
1763}
1764
1765static bool cmd_cfa_access_metadata_storage(IDEState *s, uint8_t cmd)
1766{
1767 switch (s->feature) {
1768 case 0x02: /* Inquiry Metadata Storage */
1769 ide_cfata_metadata_inquiry(s);
1770 break;
1771 case 0x03: /* Read Metadata Storage */
1772 ide_cfata_metadata_read(s);
1773 break;
1774 case 0x04: /* Write Metadata Storage */
1775 ide_cfata_metadata_write(s);
1776 break;
1777 default:
1778 ide_abort_command(s);
1779 return true;
1780 }
1781
1782 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1783 s->status = 0x00; /* NOTE: READY is _not_ set */
1784 ide_set_irq(s->bus);
1785
1786 return false;
1787}
1788
1789static bool cmd_ibm_sense_condition(IDEState *s, uint8_t cmd)
1790{
1791 switch (s->feature) {
1792 case 0x01: /* sense temperature in device */
1793 s->nsector = 0x50; /* +20 C */
1794 break;
1795 default:
1796 ide_abort_command(s);
1797 return true;
1798 }
1799
1800 return true;
1801}
1802
ff352677
KW		 1803
1804/*** SMART commands ***/
1805
1806static bool cmd_smart(IDEState *s, uint8_t cmd)
1807{
1808 int n;
1809
1810 if (s->hcyl != 0xc2 || s->lcyl != 0x4f) {
1811 goto abort_cmd;
1812 }
1813
1814 if (!s->smart_enabled && s->feature != SMART_ENABLE) {
1815 goto abort_cmd;
1816 }
1817
1818 switch (s->feature) {
1819 case SMART_DISABLE:
1820 s->smart_enabled = 0;
1821 return true;
1822
1823 case SMART_ENABLE:
1824 s->smart_enabled = 1;
1825 return true;
1826
1827 case SMART_ATTR_AUTOSAVE:
1828 switch (s->sector) {
1829 case 0x00:
1830 s->smart_autosave = 0;
1831 break;
1832 case 0xf1:
1833 s->smart_autosave = 1;
1834 break;
1835 default:
1836 goto abort_cmd;
1837 }
1838 return true;
1839
1840 case SMART_STATUS:
1841 if (!s->smart_errors) {
1842 s->hcyl = 0xc2;
1843 s->lcyl = 0x4f;
1844 } else {
1845 s->hcyl = 0x2c;
1846 s->lcyl = 0xf4;
1847 }
1848 return true;
1849
1850 case SMART_READ_THRESH:
1851 memset(s->io_buffer, 0, 0x200);
1852 s->io_buffer[0] = 0x01; /* smart struct version */
1853
1854 for (n = 0; n < ARRAY_SIZE(smart_attributes); n++) {
1855 s->io_buffer[2 + 0 + (n * 12)] = smart_attributes[n][0];
1856 s->io_buffer[2 + 1 + (n * 12)] = smart_attributes[n][11];
1857 }
1858
1859 /* checksum */
1860 for (n = 0; n < 511; n++) {
1861 s->io_buffer[511] += s->io_buffer[n];
1862 }
1863 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1864
1865 s->status = READY_STAT | SEEK_STAT;
1866 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1867 ide_set_irq(s->bus);
1868 return false;
1869
1870 case SMART_READ_DATA:
1871 memset(s->io_buffer, 0, 0x200);
1872 s->io_buffer[0] = 0x01; /* smart struct version */
1873
1874 for (n = 0; n < ARRAY_SIZE(smart_attributes); n++) {
1875 int i;
1876 for (i = 0; i < 11; i++) {
1877 s->io_buffer[2 + i + (n * 12)] = smart_attributes[n][i];
1878 }
1879 }
1880
1881 s->io_buffer[362] = 0x02 | (s->smart_autosave ? 0x80 : 0x00);
1882 if (s->smart_selftest_count == 0) {
1883 s->io_buffer[363] = 0;
1884 } else {
1885 s->io_buffer[363] =
1886 s->smart_selftest_data[3 +
1887 (s->smart_selftest_count - 1) *
1888 24];
1889 }
1890 s->io_buffer[364] = 0x20;
1891 s->io_buffer[365] = 0x01;
1892 /* offline data collection capacity: execute + self-test*/
1893 s->io_buffer[367] = (1 << 4 | 1 << 3 | 1);
1894 s->io_buffer[368] = 0x03; /* smart capability (1) */
1895 s->io_buffer[369] = 0x00; /* smart capability (2) */
1896 s->io_buffer[370] = 0x01; /* error logging supported */
1897 s->io_buffer[372] = 0x02; /* minutes for poll short test */
1898 s->io_buffer[373] = 0x36; /* minutes for poll ext test */
1899 s->io_buffer[374] = 0x01; /* minutes for poll conveyance */
1900
1901 for (n = 0; n < 511; n++) {
1902 s->io_buffer[511] += s->io_buffer[n];
1903 }
1904 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1905
1906 s->status = READY_STAT | SEEK_STAT;
1907 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1908 ide_set_irq(s->bus);
1909 return false;
1910
1911 case SMART_READ_LOG:
1912 switch (s->sector) {
1913 case 0x01: /* summary smart error log */
1914 memset(s->io_buffer, 0, 0x200);
1915 s->io_buffer[0] = 0x01;
1916 s->io_buffer[1] = 0x00; /* no error entries */
1917 s->io_buffer[452] = s->smart_errors & 0xff;
1918 s->io_buffer[453] = (s->smart_errors & 0xff00) >> 8;
1919
1920 for (n = 0; n < 511; n++) {
1921 s->io_buffer[511] += s->io_buffer[n];
1922 }
1923 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1924 break;
1925 case 0x06: /* smart self test log */
1926 memset(s->io_buffer, 0, 0x200);
1927 s->io_buffer[0] = 0x01;
1928 if (s->smart_selftest_count == 0) {
1929 s->io_buffer[508] = 0;
1930 } else {
1931 s->io_buffer[508] = s->smart_selftest_count;
1932 for (n = 2; n < 506; n++) {
1933 s->io_buffer[n] = s->smart_selftest_data[n];
1934 }
1935 }
1936
1937 for (n = 0; n < 511; n++) {
1938 s->io_buffer[511] += s->io_buffer[n];
1939 }
1940 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1941 break;
1942 default:
1943 goto abort_cmd;
1944 }
1945 s->status = READY_STAT | SEEK_STAT;
1946 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1947 ide_set_irq(s->bus);
1948 return false;
1949
1950 case SMART_EXECUTE_OFFLINE:
1951 switch (s->sector) {
1952 case 0: /* off-line routine */
1953 case 1: /* short self test */
1954 case 2: /* extended self test */
1955 s->smart_selftest_count++;
1956 if (s->smart_selftest_count > 21) {
940973ae 1957 s->smart_selftest_count = 1;
ff352677
KW		 1958 }
1959 n = 2 + (s->smart_selftest_count - 1) * 24;
1960 s->smart_selftest_data[n] = s->sector;
1961 s->smart_selftest_data[n + 1] = 0x00; /* OK and finished */
1962 s->smart_selftest_data[n + 2] = 0x34; /* hour count lsb */
1963 s->smart_selftest_data[n + 3] = 0x12; /* hour count msb */
1964 break;
1965 default:
1966 goto abort_cmd;
1967 }
1968 return true;
1969 }
1970
1971abort_cmd:
1972 ide_abort_command(s);
1973 return true;
1974}
1975
844505b1
MA		 1976#define HD_OK (1u << IDE_HD)
1977#define CD_OK (1u << IDE_CD)
1978#define CFA_OK (1u << IDE_CFATA)
1979#define HD_CFA_OK (HD_OK | CFA_OK)
1980#define ALL_OK (HD_OK | CD_OK | CFA_OK)
1981
a0436e92
KW		 1982/* Set the Disk Seek Completed status bit during completion */
1983#define SET_DSC (1u << 8)
1984
844505b1 1985/* See ACS-2 T13/2015-D Table B.2 Command codes */
a0436e92
KW		 1986static const struct {
1987 /* Returns true if the completion code should be run */
1988 bool (*handler)(IDEState *s, uint8_t cmd);
1989 int flags;
1990} ide_cmd_table[0x100] = {
844505b1 1991 /* NOP not implemented, mandatory for CD */
6b1dd744 1992 [CFA_REQ_EXT_ERROR_CODE] = { cmd_cfa_req_ext_error_code, CFA_OK },
d9033e1d 1993 [WIN_DSM] = { cmd_data_set_management, HD_CFA_OK },
ee425c78 1994 [WIN_DEVICE_RESET] = { cmd_device_reset, CD_OK },
b300337e 1995 [WIN_RECAL] = { cmd_nop, HD_CFA_OK | SET_DSC},
0e6498ed 1996 [WIN_READ] = { cmd_read_pio, ALL_OK },
d9033e1d 1997 [WIN_READ_ONCE] = { cmd_read_pio, HD_CFA_OK },
0e6498ed 1998 [WIN_READ_EXT] = { cmd_read_pio, HD_CFA_OK },
92a6a6f6 1999 [WIN_READDMA_EXT] = { cmd_read_dma, HD_CFA_OK },
63a82e6a 2000 [WIN_READ_NATIVE_MAX_EXT] = { cmd_read_native_max, HD_CFA_OK | SET_DSC },
adf3a2c4 2001 [WIN_MULTREAD_EXT] = { cmd_read_multiple, HD_CFA_OK },
0e6498ed
KW		 2002 [WIN_WRITE] = { cmd_write_pio, HD_CFA_OK },
2003 [WIN_WRITE_ONCE] = { cmd_write_pio, HD_CFA_OK },
2004 [WIN_WRITE_EXT] = { cmd_write_pio, HD_CFA_OK },
92a6a6f6 2005 [WIN_WRITEDMA_EXT] = { cmd_write_dma, HD_CFA_OK },
0e6498ed 2006 [CFA_WRITE_SECT_WO_ERASE] = { cmd_write_pio, CFA_OK },
adf3a2c4 2007 [WIN_MULTWRITE_EXT] = { cmd_write_multiple, HD_CFA_OK },
0e6498ed 2008 [WIN_WRITE_VERIFY] = { cmd_write_pio, HD_CFA_OK },
413860cf
KW		 2009 [WIN_VERIFY] = { cmd_verify, HD_CFA_OK | SET_DSC },
2010 [WIN_VERIFY_ONCE] = { cmd_verify, HD_CFA_OK | SET_DSC },
2011 [WIN_VERIFY_EXT] = { cmd_verify, HD_CFA_OK | SET_DSC },
61fdda37 2012 [WIN_SEEK] = { cmd_seek, HD_CFA_OK | SET_DSC },
6b1dd744 2013 [CFA_TRANSLATE_SECTOR] = { cmd_cfa_translate_sector, CFA_OK },
ee425c78 2014 [WIN_DIAGNOSE] = { cmd_exec_dev_diagnostic, ALL_OK },
b300337e 2015 [WIN_SPECIFY] = { cmd_nop, HD_CFA_OK | SET_DSC },
d9033e1d
JS		 2016 [WIN_STANDBYNOW2] = { cmd_nop, HD_CFA_OK },
2017 [WIN_IDLEIMMEDIATE2] = { cmd_nop, HD_CFA_OK },
2018 [WIN_STANDBY2] = { cmd_nop, HD_CFA_OK },
2019 [WIN_SETIDLE2] = { cmd_nop, HD_CFA_OK },
2020 [WIN_CHECKPOWERMODE2] = { cmd_check_power_mode, HD_CFA_OK | SET_DSC },
2021 [WIN_SLEEPNOW2] = { cmd_nop, HD_CFA_OK },
ee425c78
KW		 2022 [WIN_PACKETCMD] = { cmd_packet, CD_OK },
2023 [WIN_PIDENTIFY] = { cmd_identify_packet, CD_OK },
ff352677 2024 [WIN_SMART] = { cmd_smart, HD_CFA_OK | SET_DSC },
6b1dd744
KW		 2025 [CFA_ACCESS_METADATA_STORAGE] = { cmd_cfa_access_metadata_storage, CFA_OK },
2026 [CFA_ERASE_SECTORS] = { cmd_cfa_erase_sectors, CFA_OK | SET_DSC },
adf3a2c4
KW		 2027 [WIN_MULTREAD] = { cmd_read_multiple, HD_CFA_OK },
2028 [WIN_MULTWRITE] = { cmd_write_multiple, HD_CFA_OK },
2029 [WIN_SETMULT] = { cmd_set_multiple_mode, HD_CFA_OK | SET_DSC },
92a6a6f6
KW		 2030 [WIN_READDMA] = { cmd_read_dma, HD_CFA_OK },
2031 [WIN_READDMA_ONCE] = { cmd_read_dma, HD_CFA_OK },
2032 [WIN_WRITEDMA] = { cmd_write_dma, HD_CFA_OK },
2033 [WIN_WRITEDMA_ONCE] = { cmd_write_dma, HD_CFA_OK },
adf3a2c4 2034 [CFA_WRITE_MULTI_WO_ERASE] = { cmd_write_multiple, CFA_OK },
d9033e1d
JS		 2035 [WIN_STANDBYNOW1] = { cmd_nop, HD_CFA_OK },
2036 [WIN_IDLEIMMEDIATE] = { cmd_nop, HD_CFA_OK },
2037 [WIN_STANDBY] = { cmd_nop, HD_CFA_OK },
2038 [WIN_SETIDLE1] = { cmd_nop, HD_CFA_OK },
2039 [WIN_CHECKPOWERMODE1] = { cmd_check_power_mode, HD_CFA_OK | SET_DSC },
2040 [WIN_SLEEPNOW1] = { cmd_nop, HD_CFA_OK },
9afce429
KW		 2041 [WIN_FLUSH_CACHE] = { cmd_flush_cache, ALL_OK },
2042 [WIN_FLUSH_CACHE_EXT] = { cmd_flush_cache, HD_CFA_OK },
1c66869a 2043 [WIN_IDENTIFY] = { cmd_identify, ALL_OK },
ee03398c 2044 [WIN_SETFEATURES] = { cmd_set_features, ALL_OK | SET_DSC },
6b1dd744
KW		 2045 [IBM_SENSE_CONDITION] = { cmd_ibm_sense_condition, CFA_OK | SET_DSC },
2046 [CFA_WEAR_LEVEL] = { cmd_cfa_erase_sectors, HD_CFA_OK | SET_DSC },
d9033e1d 2047 [WIN_READ_NATIVE_MAX] = { cmd_read_native_max, HD_CFA_OK | SET_DSC },
844505b1
MA		 2048};
2049
2050static bool ide_cmd_permitted(IDEState *s, uint32_t cmd)
2051{
2052 return cmd < ARRAY_SIZE(ide_cmd_table)
a0436e92 2053 && (ide_cmd_table[cmd].flags & (1u << s->drive_kind));
844505b1 2054}
7cff87ff
AG		 2055
2056void ide_exec_cmd(IDEBus *bus, uint32_t val)
2057{
2058 IDEState *s;
dfe1ea8f 2059 bool complete;
7cff87ff 2060
6ef2ba5e 2061 s = idebus_active_if(bus);
3eee2611
JS		 2062 trace_ide_exec_cmd(bus, s, val);
2063
66a0a2cb 2064 /* ignore commands to non existent slave */
4be74634 2065 if (s != bus->ifs && !s->blk) {
6ef2ba5e 2066 return;
4be74634 2067 }
c2ff060f 2068
266e7781
JS		 2069 /* Only RESET is allowed while BSY and/or DRQ are set,
2070 * and only to ATAPI devices. */
2071 if (s->status & (BUSY_STAT|DRQ_STAT)) {
2072 if (val != WIN_DEVICE_RESET || s->drive_kind != IDE_CD) {
2073 return;
2074 }
2075 }
fcdd25ab 2076
844505b1 2077 if (!ide_cmd_permitted(s, val)) {
dfe1ea8f
KW		 2078 ide_abort_command(s);
2079 ide_set_irq(s->bus);
2080 return;
844505b1
MA		 2081 }
2082
dfe1ea8f
KW		 2083 s->status = READY_STAT | BUSY_STAT;
2084 s->error = 0;
36334faf 2085 s->io_buffer_offset = 0;
a0436e92 2086
dfe1ea8f
KW		 2087 complete = ide_cmd_table[val].handler(s, val);
2088 if (complete) {
2089 s->status &= ~BUSY_STAT;
2090 assert(!!s->error == !!(s->status & ERR_STAT));
a0436e92 2091
dfe1ea8f
KW		 2092 if ((ide_cmd_table[val].flags & SET_DSC) && !s->error) {
2093 s->status |= SEEK_STAT;
a0436e92
KW		 2094 }
2095
c7e73adb 2096 ide_cmd_done(s);
6ef2ba5e 2097 ide_set_irq(s->bus);
6ef2ba5e 2098 }
5391d806
FB		 2099}
2100
335ca2f2
JS		 2101/* IOport [R]ead [R]egisters */
2102enum ATA_IOPORT_RR {
2103 ATA_IOPORT_RR_DATA = 0,
2104 ATA_IOPORT_RR_ERROR = 1,
2105 ATA_IOPORT_RR_SECTOR_COUNT = 2,
2106 ATA_IOPORT_RR_SECTOR_NUMBER = 3,
2107 ATA_IOPORT_RR_CYLINDER_LOW = 4,
2108 ATA_IOPORT_RR_CYLINDER_HIGH = 5,
2109 ATA_IOPORT_RR_DEVICE_HEAD = 6,
2110 ATA_IOPORT_RR_STATUS = 7,
2111 ATA_IOPORT_RR_NUM_REGISTERS,
2112};
2113
2114const char *ATA_IOPORT_RR_lookup[ATA_IOPORT_RR_NUM_REGISTERS] = {
2115 [ATA_IOPORT_RR_DATA] = "Data",
2116 [ATA_IOPORT_RR_ERROR] = "Error",
2117 [ATA_IOPORT_RR_SECTOR_COUNT] = "Sector Count",
2118 [ATA_IOPORT_RR_SECTOR_NUMBER] = "Sector Number",
2119 [ATA_IOPORT_RR_CYLINDER_LOW] = "Cylinder Low",
2120 [ATA_IOPORT_RR_CYLINDER_HIGH] = "Cylinder High",
2121 [ATA_IOPORT_RR_DEVICE_HEAD] = "Device/Head",
2122 [ATA_IOPORT_RR_STATUS] = "Status"
2123};
2124
3eee2611 2125uint32_t ide_ioport_read(void *opaque, uint32_t addr)
5391d806 2126{
bcbdc4d3
GH		 2127 IDEBus *bus = opaque;
2128 IDEState *s = idebus_active_if(bus);
3eee2611 2129 uint32_t reg_num;
c2ff060f 2130 int ret, hob;
5391d806 2131
3eee2611 2132 reg_num = addr & 7;
c2ff060f
FB		 2133 /* FIXME: HOB readback uses bit 7, but it's always set right now */
2134 //hob = s->select & (1 << 7);
2135 hob = 0;
3eee2611 2136 switch (reg_num) {
335ca2f2 2137 case ATA_IOPORT_RR_DATA:
5391d806
FB		 2138 ret = 0xff;
2139 break;
335ca2f2 2140 case ATA_IOPORT_RR_ERROR:
4be74634
MA		 2141 if ((!bus->ifs[0].blk && !bus->ifs[1].blk) ||
2142 (s != bus->ifs && !s->blk)) {
c45c3d00 2143 ret = 0;
4be74634 2144 } else if (!hob) {
c45c3d00 2145 ret = s->error;
4be74634 2146 } else {
c2ff060f 2147 ret = s->hob_feature;
4be74634 2148 }
5391d806 2149 break;
335ca2f2 2150 case ATA_IOPORT_RR_SECTOR_COUNT:
4be74634 2151 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
c45c3d00 2152 ret = 0;
4be74634 2153 } else if (!hob) {
c45c3d00 2154 ret = s->nsector & 0xff;
4be74634 2155 } else {
c2ff060f 2156 ret = s->hob_nsector;
4be74634 2157 }
5391d806 2158 break;
335ca2f2 2159 case ATA_IOPORT_RR_SECTOR_NUMBER:
4be74634 2160 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
c45c3d00 2161 ret = 0;
4be74634 2162 } else if (!hob) {
c45c3d00 2163 ret = s->sector;
4be74634 2164 } else {
c2ff060f 2165 ret = s->hob_sector;
4be74634 2166 }
5391d806 2167 break;
335ca2f2 2168 case ATA_IOPORT_RR_CYLINDER_LOW:
4be74634 2169 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
c45c3d00 2170 ret = 0;
4be74634 2171 } else if (!hob) {
c45c3d00 2172 ret = s->lcyl;
4be74634 2173 } else {
c2ff060f 2174 ret = s->hob_lcyl;
4be74634 2175 }
5391d806 2176 break;
335ca2f2 2177 case ATA_IOPORT_RR_CYLINDER_HIGH:
4be74634 2178 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
c45c3d00 2179 ret = 0;
4be74634 2180 } else if (!hob) {
c45c3d00 2181 ret = s->hcyl;
4be74634 2182 } else {
c2ff060f 2183 ret = s->hob_hcyl;
4be74634 2184 }
5391d806 2185 break;
335ca2f2 2186 case ATA_IOPORT_RR_DEVICE_HEAD:
4be74634 2187 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
c45c3d00 2188 ret = 0;
4be74634 2189 } else {
7ae98627 2190 ret = s->select;
4be74634 2191 }
5391d806
FB		 2192 break;
2193 default:
335ca2f2 2194 case ATA_IOPORT_RR_STATUS:
4be74634
MA		 2195 if ((!bus->ifs[0].blk && !bus->ifs[1].blk) ||
2196 (s != bus->ifs && !s->blk)) {
c45c3d00 2197 ret = 0;
4be74634 2198 } else {
c45c3d00 2199 ret = s->status;
4be74634 2200 }
9cdd03a7 2201 qemu_irq_lower(bus->irq);
5391d806
FB		 2202 break;
2203 }
3eee2611 2204
335ca2f2 2205 trace_ide_ioport_read(addr, ATA_IOPORT_RR_lookup[reg_num], ret, bus, s);
5391d806
FB		 2206 return ret;
2207}
2208
356721ae 2209uint32_t ide_status_read(void *opaque, uint32_t addr)
5391d806 2210{
bcbdc4d3
GH		 2211 IDEBus *bus = opaque;
2212 IDEState *s = idebus_active_if(bus);
5391d806 2213 int ret;
7ae98627 2214
4be74634
MA		 2215 if ((!bus->ifs[0].blk && !bus->ifs[1].blk) ||
2216 (s != bus->ifs && !s->blk)) {
7ae98627 2217 ret = 0;
4be74634 2218 } else {
7ae98627 2219 ret = s->status;
4be74634 2220 }
3eee2611
JS		 2221
2222 trace_ide_status_read(addr, ret, bus, s);
5391d806
FB		 2223 return ret;
2224}
2225
356721ae 2226void ide_cmd_write(void *opaque, uint32_t addr, uint32_t val)
5391d806 2227{
bcbdc4d3 2228 IDEBus *bus = opaque;
5391d806
FB		 2229 IDEState *s;
2230 int i;
2231
3eee2611
JS		 2232 trace_ide_cmd_write(addr, val, bus);
2233
5391d806 2234 /* common for both drives */
9cdd03a7 2235 if (!(bus->cmd & IDE_CMD_RESET) &&
5391d806
FB		 2236 (val & IDE_CMD_RESET)) {
2237 /* reset low to high */
2238 for(i = 0;i < 2; i++) {
bcbdc4d3 2239 s = &bus->ifs[i];
5391d806
FB		 2240 s->status = BUSY_STAT | SEEK_STAT;
2241 s->error = 0x01;
2242 }
9cdd03a7 2243 } else if ((bus->cmd & IDE_CMD_RESET) &&
5391d806
FB		 2244 !(val & IDE_CMD_RESET)) {
2245 /* high to low */
2246 for(i = 0;i < 2; i++) {
bcbdc4d3 2247 s = &bus->ifs[i];
cd8722bb 2248 if (s->drive_kind == IDE_CD)
6b136f9e
FB		 2249 s->status = 0x00; /* NOTE: READY is _not_ set */
2250 else
56bf1d37 2251 s->status = READY_STAT | SEEK_STAT;
5391d806
FB		 2252 ide_set_signature(s);
2253 }
2254 }
2255
9cdd03a7 2256 bus->cmd = val;
5391d806
FB		 2257}
2258
40c4ed3f
KW		 2259/*
2260 * Returns true if the running PIO transfer is a PIO out (i.e. data is
2261 * transferred from the device to the guest), false if it's a PIO in
2262 */
2263static bool ide_is_pio_out(IDEState *s)
2264{
2265 if (s->end_transfer_func == ide_sector_write ||
2266 s->end_transfer_func == ide_atapi_cmd) {
2267 return false;
2268 } else if (s->end_transfer_func == ide_sector_read ||
2269 s->end_transfer_func == ide_transfer_stop ||
2270 s->end_transfer_func == ide_atapi_cmd_reply_end ||
2271 s->end_transfer_func == ide_dummy_transfer_stop) {
2272 return true;
2273 }
2274
2275 abort();
2276}
2277
356721ae 2278void ide_data_writew(void *opaque, uint32_t addr, uint32_t val)
5391d806 2279{
bcbdc4d3
GH		 2280 IDEBus *bus = opaque;
2281 IDEState *s = idebus_active_if(bus);
5391d806
FB		 2282 uint8_t *p;
2283
1787efc3
JS		 2284 trace_ide_data_writew(addr, val, bus, s);
2285
40c4ed3f
KW		 2286 /* PIO data access allowed only when DRQ bit is set. The result of a write
2287 * during PIO out is indeterminate, just ignore it. */
2288 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
fcdd25ab 2289 return;
40c4ed3f 2290 }
fcdd25ab 2291
5391d806 2292 p = s->data_ptr;
d2ff8585
KW		 2293 if (p + 2 > s->data_end) {
2294 return;
2295 }
2296
0c4ad8dc 2297 *(uint16_t *)p = le16_to_cpu(val);
5391d806
FB		 2298 p += 2;
2299 s->data_ptr = p;
cb72cba8
KW		 2300 if (p >= s->data_end) {
2301 s->status &= ~DRQ_STAT;
5391d806 2302 s->end_transfer_func(s);
cb72cba8 2303 }
5391d806
FB		 2304}
2305
356721ae 2306uint32_t ide_data_readw(void *opaque, uint32_t addr)
5391d806 2307{
bcbdc4d3
GH		 2308 IDEBus *bus = opaque;
2309 IDEState *s = idebus_active_if(bus);
5391d806
FB		 2310 uint8_t *p;
2311 int ret;
fcdd25ab 2312
40c4ed3f
KW		 2313 /* PIO data access allowed only when DRQ bit is set. The result of a read
2314 * during PIO in is indeterminate, return 0 and don't move forward. */
2315 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
fcdd25ab 2316 return 0;
40c4ed3f 2317 }
fcdd25ab 2318
5391d806 2319 p = s->data_ptr;
d2ff8585
KW		 2320 if (p + 2 > s->data_end) {
2321 return 0;
2322 }
2323
0c4ad8dc 2324 ret = cpu_to_le16(*(uint16_t *)p);
5391d806
FB		 2325 p += 2;
2326 s->data_ptr = p;
cb72cba8
KW		 2327 if (p >= s->data_end) {
2328 s->status &= ~DRQ_STAT;
5391d806 2329 s->end_transfer_func(s);
cb72cba8 2330 }
1787efc3
JS		 2331
2332 trace_ide_data_readw(addr, ret, bus, s);
5391d806
FB		 2333 return ret;
2334}
2335
356721ae 2336void ide_data_writel(void *opaque, uint32_t addr, uint32_t val)
5391d806 2337{
bcbdc4d3
GH		 2338 IDEBus *bus = opaque;
2339 IDEState *s = idebus_active_if(bus);
5391d806
FB		 2340 uint8_t *p;
2341
1787efc3
JS		 2342 trace_ide_data_writel(addr, val, bus, s);
2343
40c4ed3f
KW		 2344 /* PIO data access allowed only when DRQ bit is set. The result of a write
2345 * during PIO out is indeterminate, just ignore it. */
2346 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
fcdd25ab 2347 return;
40c4ed3f 2348 }
fcdd25ab 2349
5391d806 2350 p = s->data_ptr;
d2ff8585
KW		 2351 if (p + 4 > s->data_end) {
2352 return;
2353 }
2354
0c4ad8dc 2355 *(uint32_t *)p = le32_to_cpu(val);
5391d806
FB		 2356 p += 4;
2357 s->data_ptr = p;
cb72cba8
KW		 2358 if (p >= s->data_end) {
2359 s->status &= ~DRQ_STAT;
5391d806 2360 s->end_transfer_func(s);
cb72cba8 2361 }
5391d806
FB		 2362}
2363
356721ae 2364uint32_t ide_data_readl(void *opaque, uint32_t addr)
5391d806 2365{
bcbdc4d3
GH		 2366 IDEBus *bus = opaque;
2367 IDEState *s = idebus_active_if(bus);
5391d806
FB		 2368 uint8_t *p;
2369 int ret;
3b46e624 2370
40c4ed3f
KW		 2371 /* PIO data access allowed only when DRQ bit is set. The result of a read
2372 * during PIO in is indeterminate, return 0 and don't move forward. */
2373 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
1787efc3
JS		 2374 ret = 0;
2375 goto out;
40c4ed3f 2376 }
fcdd25ab 2377
5391d806 2378 p = s->data_ptr;
d2ff8585
KW		 2379 if (p + 4 > s->data_end) {
2380 return 0;
2381 }
2382
0c4ad8dc 2383 ret = cpu_to_le32(*(uint32_t *)p);
5391d806
FB		 2384 p += 4;
2385 s->data_ptr = p;
cb72cba8
KW		 2386 if (p >= s->data_end) {
2387 s->status &= ~DRQ_STAT;
5391d806 2388 s->end_transfer_func(s);
cb72cba8 2389 }
1787efc3
JS		 2390
2391out:
2392 trace_ide_data_readl(addr, ret, bus, s);
5391d806
FB		 2393 return ret;
2394}
2395
a7dfe172
FB		 2396static void ide_dummy_transfer_stop(IDEState *s)
2397{
2398 s->data_ptr = s->io_buffer;
2399 s->data_end = s->io_buffer;
2400 s->io_buffer[0] = 0xff;
2401 s->io_buffer[1] = 0xff;
2402 s->io_buffer[2] = 0xff;
2403 s->io_buffer[3] = 0xff;
2404}
2405
4a643563
BS		 2406void ide_bus_reset(IDEBus *bus)
2407{
2408 bus->unit = 0;
2409 bus->cmd = 0;
2410 ide_reset(&bus->ifs[0]);
2411 ide_reset(&bus->ifs[1]);
2412 ide_clear_hob(bus);
40a6238a
AG		 2413
2414 /* pending async DMA */
2415 if (bus->dma->aiocb) {
0e168d35 2416 trace_ide_bus_reset_aio();
4be74634 2417 blk_aio_cancel(bus->dma->aiocb);
40a6238a
AG		 2418 bus->dma->aiocb = NULL;
2419 }
2420
2421 /* reset dma provider too */
1374bec0
PB		 2422 if (bus->dma->ops->reset) {
2423 bus->dma->ops->reset(bus->dma);
2424 }
4a643563
BS		 2425}
2426
e4def80b
MA		 2427static bool ide_cd_is_tray_open(void *opaque)
2428{
2429 return ((IDEState *)opaque)->tray_open;
2430}
2431
f107639a
MA		 2432static bool ide_cd_is_medium_locked(void *opaque)
2433{
2434 return ((IDEState *)opaque)->tray_locked;
2435}
2436
01ce352e
JS		 2437static void ide_resize_cb(void *opaque)
2438{
2439 IDEState *s = opaque;
2440 uint64_t nb_sectors;
2441
2442 if (!s->identify_set) {
2443 return;
2444 }
2445
4be74634 2446 blk_get_geometry(s->blk, &nb_sectors);
01ce352e
JS		 2447 s->nb_sectors = nb_sectors;
2448
2449 /* Update the identify data buffer. */
2450 if (s->drive_kind == IDE_CFATA) {
2451 ide_cfata_identify_size(s);
2452 } else {
2453 /* IDE_CD uses a different set of callbacks entirely. */
2454 assert(s->drive_kind != IDE_CD);
2455 ide_identify_size(s);
2456 }
2457}
2458
0e49de52 2459static const BlockDevOps ide_cd_block_ops = {
145feb17 2460 .change_media_cb = ide_cd_change_cb,
2df0a3a3 2461 .eject_request_cb = ide_cd_eject_request_cb,
e4def80b 2462 .is_tray_open = ide_cd_is_tray_open,
f107639a 2463 .is_medium_locked = ide_cd_is_medium_locked,
0e49de52
MA		 2464};
2465
01ce352e
JS		 2466static const BlockDevOps ide_hd_block_ops = {
2467 .resize_cb = ide_resize_cb,
2468};
2469
4be74634 2470int ide_init_drive(IDEState *s, BlockBackend *blk, IDEDriveKind kind,
95ebda85 2471 const char *version, const char *serial, const char *model,
ba801960
MA		 2472 uint64_t wwn,
2473 uint32_t cylinders, uint32_t heads, uint32_t secs,
794939e8 2474 int chs_trans, Error **errp)
88804180 2475{
88804180
GH		 2476 uint64_t nb_sectors;
2477
4be74634 2478 s->blk = blk;
1f56e32a
MA		 2479 s->drive_kind = kind;
2480
4be74634 2481 blk_get_geometry(blk, &nb_sectors);
870111c8
MA		 2482 s->cylinders = cylinders;
2483 s->heads = heads;
2484 s->sectors = secs;
ba801960 2485 s->chs_trans = chs_trans;
870111c8 2486 s->nb_sectors = nb_sectors;
95ebda85 2487 s->wwn = wwn;
870111c8
MA		 2488 /* The SMART values should be preserved across power cycles
2489 but they aren't. */
2490 s->smart_enabled = 1;
2491 s->smart_autosave = 1;
2492 s->smart_errors = 0;
2493 s->smart_selftest_count = 0;
1f56e32a 2494 if (kind == IDE_CD) {
4be74634
MA		 2495 blk_set_dev_ops(blk, &ide_cd_block_ops, s);
2496 blk_set_guest_block_size(blk, 2048);
7aa9c811 2497 } else {
4be74634 2498 if (!blk_is_inserted(s->blk)) {
794939e8 2499 error_setg(errp, "Device needs media, but drive is empty");
98f28ad7
MA		 2500 return -1;
2501 }
4be74634 2502 if (blk_is_read_only(blk)) {
794939e8 2503 error_setg(errp, "Can't use a read-only drive");
7aa9c811
MA		 2504 return -1;
2505 }
4be74634 2506 blk_set_dev_ops(blk, &ide_hd_block_ops, s);
88804180 2507 }
f8b6cc00 2508 if (serial) {
aa2c91bd 2509 pstrcpy(s->drive_serial_str, sizeof(s->drive_serial_str), serial);
6ced55a5 2510 } else {
88804180
GH		 2511 snprintf(s->drive_serial_str, sizeof(s->drive_serial_str),
2512 "QM%05d", s->drive_serial);
870111c8 2513 }
27e0c9a1
FB		 2514 if (model) {
2515 pstrcpy(s->drive_model_str, sizeof(s->drive_model_str), model);
2516 } else {
2517 switch (kind) {
2518 case IDE_CD:
2519 strcpy(s->drive_model_str, "QEMU DVD-ROM");
2520 break;
2521 case IDE_CFATA:
2522 strcpy(s->drive_model_str, "QEMU MICRODRIVE");
2523 break;
2524 default:
2525 strcpy(s->drive_model_str, "QEMU HARDDISK");
2526 break;
2527 }
2528 }
2529
47c06340
GH		 2530 if (version) {
2531 pstrcpy(s->version, sizeof(s->version), version);
2532 } else {
35c2c8dc 2533 pstrcpy(s->version, sizeof(s->version), qemu_hw_version());
47c06340 2534 }
40a6238a 2535
88804180 2536 ide_reset(s);
4be74634 2537 blk_iostatus_enable(blk);
c4d74df7 2538 return 0;
88804180
GH		 2539}
2540
57234ee4 2541static void ide_init1(IDEBus *bus, int unit)
d459da0e
MA		 2542{
2543 static int drive_serial = 1;
2544 IDEState *s = &bus->ifs[unit];
2545
2546 s->bus = bus;
2547 s->unit = unit;
2548 s->drive_serial = drive_serial++;
1b2adf28 2549 /* we need at least 2k alignment for accessing CDROMs using O_DIRECT */
50641c5c 2550 s->io_buffer_total_len = IDE_DMA_BUF_SECTORS*512 + 4;
c925400b
KW		 2551 s->io_buffer = qemu_memalign(2048, s->io_buffer_total_len);
2552 memset(s->io_buffer, 0, s->io_buffer_total_len);
2553
4be74634 2554 s->smart_selftest_data = blk_blockalign(s->blk, 512);
c925400b
KW		 2555 memset(s->smart_selftest_data, 0, 512);
2556
bc72ad67 2557 s->sector_write_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
d459da0e 2558 ide_sector_write_timer_cb, s);
57234ee4
MA		 2559}
2560
40a6238a
AG		 2561static int ide_nop_int(IDEDMA *dma, int x)
2562{
2563 return 0;
2564}
2565
9898586d
PB		 2566static void ide_nop(IDEDMA *dma)
2567{
2568}
2569
a718978e 2570static int32_t ide_nop_int32(IDEDMA *dma, int32_t l)
3251bdcf
JS		 2571{
2572 return 0;
2573}
2574
40a6238a 2575static const IDEDMAOps ide_dma_nop_ops = {
3251bdcf 2576 .prepare_buf = ide_nop_int32,
9898586d 2577 .restart_dma = ide_nop,
40a6238a 2578 .rw_buf = ide_nop_int,
40a6238a
AG		 2579};
2580
9898586d
PB		 2581static void ide_restart_dma(IDEState *s, enum ide_dma_cmd dma_cmd)
2582{
a96cb236 2583 s->unit = s->bus->retry_unit;
dc5d0af4
PB		 2584 ide_set_sector(s, s->bus->retry_sector_num);
2585 s->nsector = s->bus->retry_nsector;
9898586d 2586 s->bus->dma->ops->restart_dma(s->bus->dma);
9898586d
PB		 2587 s->io_buffer_size = 0;
2588 s->dma_cmd = dma_cmd;
2589 ide_start_dma(s, ide_dma_cb);
2590}
2591
2592static void ide_restart_bh(void *opaque)
2593{
2594 IDEBus *bus = opaque;
2595 IDEState *s;
2596 bool is_read;
2597 int error_status;
2598
2599 qemu_bh_delete(bus->bh);
2600 bus->bh = NULL;
2601
2602 error_status = bus->error_status;
2603 if (bus->error_status == 0) {
2604 return;
2605 }
2606
2607 s = idebus_active_if(bus);
2608 is_read = (bus->error_status & IDE_RETRY_READ) != 0;
2609
2610 /* The error status must be cleared before resubmitting the request: The
2611 * request may fail again, and this case can only be distinguished if the
2612 * called function can set a new error status. */
2613 bus->error_status = 0;
2614
7c03a691
JS		 2615 /* The HBA has generically asked to be kicked on retry */
2616 if (error_status & IDE_RETRY_HBA) {
2617 if (s->bus->dma->ops->restart) {
2618 s->bus->dma->ops->restart(s->bus->dma);
2619 }
502356ee 2620 } else if (IS_IDE_RETRY_DMA(error_status)) {
9898586d
PB		 2621 if (error_status & IDE_RETRY_TRIM) {
2622 ide_restart_dma(s, IDE_DMA_TRIM);
2623 } else {
2624 ide_restart_dma(s, is_read ? IDE_DMA_READ : IDE_DMA_WRITE);
2625 }
502356ee 2626 } else if (IS_IDE_RETRY_PIO(error_status)) {
9898586d
PB		 2627 if (is_read) {
2628 ide_sector_read(s);
2629 } else {
2630 ide_sector_write(s);
2631 }
2632 } else if (error_status & IDE_RETRY_FLUSH) {
2633 ide_flush_cache(s);
502356ee
PB		 2634 } else if (IS_IDE_RETRY_ATAPI(error_status)) {
2635 assert(s->end_transfer_func == ide_atapi_cmd);
2636 ide_atapi_dma_restart(s);
9898586d 2637 } else {
502356ee 2638 abort();
9898586d
PB		 2639 }
2640}
2641
2642static void ide_restart_cb(void *opaque, int running, RunState state)
2643{
2644 IDEBus *bus = opaque;
2645
2646 if (!running)
2647 return;
2648
2649 if (!bus->bh) {
2650 bus->bh = qemu_bh_new(ide_restart_bh, bus);
2651 qemu_bh_schedule(bus->bh);
2652 }
2653}
2654
f878c916
PB		 2655void ide_register_restart_cb(IDEBus *bus)
2656{
9898586d 2657 if (bus->dma->ops->restart_dma) {
ca44141d 2658 bus->vmstate = qemu_add_vm_change_state_handler(ide_restart_cb, bus);
9898586d 2659 }
f878c916
PB		 2660}
2661
40a6238a
AG		 2662static IDEDMA ide_dma_nop = {
2663 .ops = &ide_dma_nop_ops,
2664 .aiocb = NULL,
2665};
2666
57234ee4
MA		 2667void ide_init2(IDEBus *bus, qemu_irq irq)
2668{
2669 int i;
2670
2671 for(i = 0; i < 2; i++) {
2672 ide_init1(bus, i);
2673 ide_reset(&bus->ifs[i]);
870111c8 2674 }
57234ee4 2675 bus->irq = irq;
40a6238a 2676 bus->dma = &ide_dma_nop;
d459da0e
MA		 2677}
2678
c9f08641
LQ		 2679void ide_exit(IDEState *s)
2680{
2681 timer_del(s->sector_write_timer);
2682 timer_free(s->sector_write_timer);
2683 qemu_vfree(s->smart_selftest_data);
2684 qemu_vfree(s->io_buffer);
2685}
2686
4a91d3b3
RH		 2687static const MemoryRegionPortio ide_portio_list[] = {
2688 { 0, 8, 1, .read = ide_ioport_read, .write = ide_ioport_write },
e477317c
PB		 2689 { 0, 1, 2, .read = ide_data_readw, .write = ide_data_writew },
2690 { 0, 1, 4, .read = ide_data_readl, .write = ide_data_writel },
4a91d3b3
RH		 2691 PORTIO_END_OF_LIST(),
2692};
2693
2694static const MemoryRegionPortio ide_portio2_list[] = {
2695 { 0, 1, 1, .read = ide_status_read, .write = ide_cmd_write },
2696 PORTIO_END_OF_LIST(),
2697};
2698
2699void ide_init_ioport(IDEBus *bus, ISADevice *dev, int iobase, int iobase2)
69b91039 2700{
4a91d3b3
RH		 2701 /* ??? Assume only ISA and PCI configurations, and that the PCI-ISA
2702 bridge has been setup properly to always register with ISA. */
e305a165
MAL		 2703 isa_register_portio_list(dev, &bus->portio_list,
2704 iobase, ide_portio_list, bus, "ide");
4a91d3b3 2705
caed8802 2706 if (iobase2) {
e305a165
MAL		 2707 isa_register_portio_list(dev, &bus->portio2_list,
2708 iobase2, ide_portio2_list, bus, "ide");
5391d806 2709 }
5391d806 2710}
69b91039 2711
37159f13 2712static bool is_identify_set(void *opaque, int version_id)
aa941b94 2713{
37159f13
JQ		 2714 IDEState *s = opaque;
2715
2716 return s->identify_set != 0;
2717}
2718
50641c5c
JQ		 2719static EndTransferFunc* transfer_end_table[] = {
2720 ide_sector_read,
2721 ide_sector_write,
2722 ide_transfer_stop,
2723 ide_atapi_cmd_reply_end,
2724 ide_atapi_cmd,
2725 ide_dummy_transfer_stop,
2726};
2727
2728static int transfer_end_table_idx(EndTransferFunc *fn)
2729{
2730 int i;
2731
2732 for (i = 0; i < ARRAY_SIZE(transfer_end_table); i++)
2733 if (transfer_end_table[i] == fn)
2734 return i;
2735
2736 return -1;
2737}
2738
37159f13 2739static int ide_drive_post_load(void *opaque, int version_id)
aa941b94 2740{
37159f13
JQ		 2741 IDEState *s = opaque;
2742
6b896ab2 2743 if (s->blk && s->identify_set) {
4be74634 2744 blk_set_enable_write_cache(s->blk, !!(s->identify_data[85] & (1 << 5)));
7cdd481c 2745 }
37159f13 2746 return 0;
aa941b94
AZ		 2747}
2748
50641c5c
JQ		 2749static int ide_drive_pio_post_load(void *opaque, int version_id)
2750{
2751 IDEState *s = opaque;
2752
fb60105d 2753 if (s->end_transfer_fn_idx >= ARRAY_SIZE(transfer_end_table)) {
50641c5c
JQ		 2754 return -EINVAL;
2755 }
2756 s->end_transfer_func = transfer_end_table[s->end_transfer_fn_idx];
2757 s->data_ptr = s->io_buffer + s->cur_io_buffer_offset;
2758 s->data_end = s->data_ptr + s->cur_io_buffer_len;
819fa276 2759 s->atapi_dma = s->feature & 1; /* as per cmd_packet */
50641c5c
JQ		 2760
2761 return 0;
2762}
2763
44b1ff31 2764static int ide_drive_pio_pre_save(void *opaque)
50641c5c
JQ		 2765{
2766 IDEState *s = opaque;
2767 int idx;
2768
2769 s->cur_io_buffer_offset = s->data_ptr - s->io_buffer;
2770 s->cur_io_buffer_len = s->data_end - s->data_ptr;
2771
2772 idx = transfer_end_table_idx(s->end_transfer_func);
2773 if (idx == -1) {
2774 fprintf(stderr, "%s: invalid end_transfer_func for DRQ_STAT\n",
2775 __func__);
2776 s->end_transfer_fn_idx = 2;
2777 } else {
2778 s->end_transfer_fn_idx = idx;
2779 }
44b1ff31
DDAG		 2780
2781 return 0;
50641c5c
JQ		 2782}
2783
2784static bool ide_drive_pio_state_needed(void *opaque)
2785{
2786 IDEState *s = opaque;
2787
fdc650d7 2788 return ((s->status & DRQ_STAT) != 0)
fd648f10 2789 || (s->bus->error_status & IDE_RETRY_PIO);
50641c5c
JQ		 2790}
2791
db118fe7
MA		 2792static bool ide_tray_state_needed(void *opaque)
2793{
2794 IDEState *s = opaque;
2795
2796 return s->tray_open || s->tray_locked;
2797}
2798
996faf1a
AS		 2799static bool ide_atapi_gesn_needed(void *opaque)
2800{
2801 IDEState *s = opaque;
2802
2803 return s->events.new_media || s->events.eject_request;
2804}
2805
def93791
KW		 2806static bool ide_error_needed(void *opaque)
2807{
2808 IDEBus *bus = opaque;
2809
2810 return (bus->error_status != 0);
2811}
2812
996faf1a 2813/* Fields for GET_EVENT_STATUS_NOTIFICATION ATAPI command */
656fbeff 2814static const VMStateDescription vmstate_ide_atapi_gesn_state = {
996faf1a
AS		 2815 .name ="ide_drive/atapi/gesn_state",
2816 .version_id = 1,
2817 .minimum_version_id = 1,
5cd8cada 2818 .needed = ide_atapi_gesn_needed,
35d08458 2819 .fields = (VMStateField[]) {
996faf1a
AS		 2820 VMSTATE_BOOL(events.new_media, IDEState),
2821 VMSTATE_BOOL(events.eject_request, IDEState),
0754f9ec 2822 VMSTATE_END_OF_LIST()
996faf1a
AS		 2823 }
2824};
2825
db118fe7
MA		 2826static const VMStateDescription vmstate_ide_tray_state = {
2827 .name = "ide_drive/tray_state",
2828 .version_id = 1,
2829 .minimum_version_id = 1,
5cd8cada 2830 .needed = ide_tray_state_needed,
db118fe7
MA		 2831 .fields = (VMStateField[]) {
2832 VMSTATE_BOOL(tray_open, IDEState),
2833 VMSTATE_BOOL(tray_locked, IDEState),
2834 VMSTATE_END_OF_LIST()
2835 }
2836};
2837
656fbeff 2838static const VMStateDescription vmstate_ide_drive_pio_state = {
50641c5c
JQ		 2839 .name = "ide_drive/pio_state",
2840 .version_id = 1,
2841 .minimum_version_id = 1,
50641c5c
JQ		 2842 .pre_save = ide_drive_pio_pre_save,
2843 .post_load = ide_drive_pio_post_load,
5cd8cada 2844 .needed = ide_drive_pio_state_needed,
35d08458 2845 .fields = (VMStateField[]) {
50641c5c
JQ		 2846 VMSTATE_INT32(req_nb_sectors, IDEState),
2847 VMSTATE_VARRAY_INT32(io_buffer, IDEState, io_buffer_total_len, 1,
2848 vmstate_info_uint8, uint8_t),
2849 VMSTATE_INT32(cur_io_buffer_offset, IDEState),
2850 VMSTATE_INT32(cur_io_buffer_len, IDEState),
2851 VMSTATE_UINT8(end_transfer_fn_idx, IDEState),
2852 VMSTATE_INT32(elementary_transfer_size, IDEState),
2853 VMSTATE_INT32(packet_transfer_size, IDEState),
2854 VMSTATE_END_OF_LIST()
2855 }
2856};
2857
37159f13
JQ		 2858const VMStateDescription vmstate_ide_drive = {
2859 .name = "ide_drive",
3abb6260 2860 .version_id = 3,
37159f13 2861 .minimum_version_id = 0,
37159f13 2862 .post_load = ide_drive_post_load,
35d08458 2863 .fields = (VMStateField[]) {
37159f13
JQ		 2864 VMSTATE_INT32(mult_sectors, IDEState),
2865 VMSTATE_INT32(identify_set, IDEState),
2866 VMSTATE_BUFFER_TEST(identify_data, IDEState, is_identify_set),
2867 VMSTATE_UINT8(feature, IDEState),
2868 VMSTATE_UINT8(error, IDEState),
2869 VMSTATE_UINT32(nsector, IDEState),
2870 VMSTATE_UINT8(sector, IDEState),
2871 VMSTATE_UINT8(lcyl, IDEState),
2872 VMSTATE_UINT8(hcyl, IDEState),
2873 VMSTATE_UINT8(hob_feature, IDEState),
2874 VMSTATE_UINT8(hob_sector, IDEState),
2875 VMSTATE_UINT8(hob_nsector, IDEState),
2876 VMSTATE_UINT8(hob_lcyl, IDEState),
2877 VMSTATE_UINT8(hob_hcyl, IDEState),
2878 VMSTATE_UINT8(select, IDEState),
2879 VMSTATE_UINT8(status, IDEState),
2880 VMSTATE_UINT8(lba48, IDEState),
2881 VMSTATE_UINT8(sense_key, IDEState),
2882 VMSTATE_UINT8(asc, IDEState),
2883 VMSTATE_UINT8_V(cdrom_changed, IDEState, 3),
37159f13 2884 VMSTATE_END_OF_LIST()
50641c5c 2885 },
5cd8cada
JQ		 2886 .subsections = (const VMStateDescription*[]) {
2887 &vmstate_ide_drive_pio_state,
2888 &vmstate_ide_tray_state,
2889 &vmstate_ide_atapi_gesn_state,
2890 NULL
37159f13
JQ		 2891 }
2892};
2893
656fbeff 2894static const VMStateDescription vmstate_ide_error_status = {
def93791 2895 .name ="ide_bus/error",
d12b9ff2 2896 .version_id = 2,
def93791 2897 .minimum_version_id = 1,
5cd8cada 2898 .needed = ide_error_needed,
35d08458 2899 .fields = (VMStateField[]) {
def93791 2900 VMSTATE_INT32(error_status, IDEBus),
d12b9ff2
PB		 2901 VMSTATE_INT64_V(retry_sector_num, IDEBus, 2),
2902 VMSTATE_UINT32_V(retry_nsector, IDEBus, 2),
2903 VMSTATE_UINT8_V(retry_unit, IDEBus, 2),
def93791
KW		 2904 VMSTATE_END_OF_LIST()
2905 }
2906};
2907
6521dc62
JQ		 2908const VMStateDescription vmstate_ide_bus = {
2909 .name = "ide_bus",
2910 .version_id = 1,
2911 .minimum_version_id = 1,
35d08458 2912 .fields = (VMStateField[]) {
6521dc62
JQ		 2913 VMSTATE_UINT8(cmd, IDEBus),
2914 VMSTATE_UINT8(unit, IDEBus),
2915 VMSTATE_END_OF_LIST()
def93791 2916 },
5cd8cada
JQ		 2917 .subsections = (const VMStateDescription*[]) {
2918 &vmstate_ide_error_status,
2919 NULL
6521dc62
JQ		 2920 }
2921};
75717903 2922
d8f94e1b 2923void ide_drive_get(DriveInfo **hd, int n)
75717903
IY		 2924{
2925 int i;
75717903 2926
d8f94e1b
JS		 2927 for (i = 0; i < n; i++) {
2928 hd[i] = drive_get_by_index(IF_IDE, i);
75717903
IY		 2929 }
2930}
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