]> Git Repo - qemu.git/blame - hw/ide/core.c
projects / qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ide: simplify start_transfer callbacks
[qemu.git] / hw / ide / core.c
CommitLineData
5391d806 1/*
38cdea7c 2 * QEMU IDE disk and CD/DVD-ROM Emulator
5fafdf24 3 *
5391d806 4 * Copyright (c) 2003 Fabrice Bellard
201a51fc 5 * Copyright (c) 2006 Openedhand Ltd.
5fafdf24 6 *
5391d806
FB		 7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
59f2a787 25#include <hw/hw.h>
0d09e41a 26#include <hw/i386/pc.h>
a2cb15b0 27#include <hw/pci/pci.h>
0d09e41a 28#include <hw/isa/isa.h>
1de7afc9
PB		 29#include "qemu/error-report.h"
30#include "qemu/timer.h"
9c17d615
PB		 31#include "sysemu/sysemu.h"
32#include "sysemu/dma.h"
0d09e41a 33#include "hw/block/block.h"
9c17d615 34#include "sysemu/blockdev.h"
59f2a787
GH		 35
36#include <hw/ide/internal.h>
e8b54394 37
b93af93d
BW		 38/* These values were based on a Seagate ST3500418AS but have been modified
39 to make more sense in QEMU */
40static const int smart_attributes[][12] = {
41 /* id, flags, hflags, val, wrst, raw (6 bytes), threshold */
42 /* raw read error rate*/
43 { 0x01, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06},
44 /* spin up */
45 { 0x03, 0x03, 0x00, 0x64, 0x64, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
46 /* start stop count */
47 { 0x04, 0x02, 0x00, 0x64, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14},
48 /* remapped sectors */
49 { 0x05, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x24},
50 /* power on hours */
51 { 0x09, 0x03, 0x00, 0x64, 0x64, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
52 /* power cycle count */
53 { 0x0c, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
54 /* airflow-temperature-celsius */
55 { 190, 0x03, 0x00, 0x45, 0x45, 0x1f, 0x00, 0x1f, 0x1f, 0x00, 0x00, 0x32},
e8b54394
BW		 56};
57
ce4b6522 58static int ide_handle_rw_error(IDEState *s, int error, int op);
40c4ed3f 59static void ide_dummy_transfer_stop(IDEState *s);
98087450 60
5391d806
FB		 61static void padstr(char *str, const char *src, int len)
62{
63 int i, v;
64 for(i = 0; i < len; i++) {
65 if (*src)
66 v = *src++;
67 else
68 v = ' ';
69b34976 69 str[i^1] = v;
5391d806
FB		 70 }
71}
72
67b915a5
FB		 73static void put_le16(uint16_t *p, unsigned int v)
74{
0c4ad8dc 75 *p = cpu_to_le16(v);
67b915a5
FB		 76}
77
5391d806
FB		 78static void ide_identify(IDEState *s)
79{
80 uint16_t *p;
81 unsigned int oldsize;
d353fb72 82 IDEDevice *dev = s->unit ? s->bus->slave : s->bus->master;
5391d806 83
94458802
FB		 84 if (s->identify_set) {
85 memcpy(s->io_buffer, s->identify_data, sizeof(s->identify_data));
86 return;
87 }
88
5391d806
FB		 89 memset(s->io_buffer, 0, 512);
90 p = (uint16_t *)s->io_buffer;
67b915a5 91 put_le16(p + 0, 0x0040);
5fafdf24 92 put_le16(p + 1, s->cylinders);
67b915a5
FB		 93 put_le16(p + 3, s->heads);
94 put_le16(p + 4, 512 * s->sectors); /* XXX: retired, remove ? */
95 put_le16(p + 5, 512); /* XXX: retired, remove ? */
5fafdf24 96 put_le16(p + 6, s->sectors);
fa879c64 97 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
67b915a5
FB		 98 put_le16(p + 20, 3); /* XXX: retired, remove ? */
99 put_le16(p + 21, 512); /* cache size in sectors */
100 put_le16(p + 22, 4); /* ecc bytes */
47c06340 101 padstr((char *)(p + 23), s->version, 8); /* firmware version */
27e0c9a1 102 padstr((char *)(p + 27), s->drive_model_str, 40); /* model */
3b46e624 103#if MAX_MULT_SECTORS > 1
67b915a5 104 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
5391d806 105#endif
67b915a5 106 put_le16(p + 48, 1); /* dword I/O */
94458802 107 put_le16(p + 49, (1 << 11) | (1 << 9) | (1 << 8)); /* DMA and LBA supported */
67b915a5
FB		 108 put_le16(p + 51, 0x200); /* PIO transfer cycle */
109 put_le16(p + 52, 0x200); /* DMA transfer cycle */
94458802 110 put_le16(p + 53, 1 | (1 << 1) | (1 << 2)); /* words 54-58,64-70,88 are valid */
67b915a5
FB		 111 put_le16(p + 54, s->cylinders);
112 put_le16(p + 55, s->heads);
113 put_le16(p + 56, s->sectors);
5391d806 114 oldsize = s->cylinders * s->heads * s->sectors;
67b915a5
FB		 115 put_le16(p + 57, oldsize);
116 put_le16(p + 58, oldsize >> 16);
5391d806 117 if (s->mult_sectors)
67b915a5
FB		 118 put_le16(p + 59, 0x100 | s->mult_sectors);
119 put_le16(p + 60, s->nb_sectors);
120 put_le16(p + 61, s->nb_sectors >> 16);
d1b5c20d 121 put_le16(p + 62, 0x07); /* single word dma0-2 supported */
94458802 122 put_le16(p + 63, 0x07); /* mdma0-2 supported */
79d1d331 123 put_le16(p + 64, 0x03); /* pio3-4 supported */
94458802
FB		 124 put_le16(p + 65, 120);
125 put_le16(p + 66, 120);
126 put_le16(p + 67, 120);
127 put_le16(p + 68, 120);
d353fb72
CH		 128 if (dev && dev->conf.discard_granularity) {
129 put_le16(p + 69, (1 << 14)); /* determinate TRIM behavior */
130 }
ccf0fd8b
RE		 131
132 if (s->ncq_queues) {
133 put_le16(p + 75, s->ncq_queues - 1);
134 /* NCQ supported */
135 put_le16(p + 76, (1 << 8));
136 }
137
94458802
FB		 138 put_le16(p + 80, 0xf0); /* ata3 -> ata6 supported */
139 put_le16(p + 81, 0x16); /* conforms to ata5 */
a58b8d54
CH		 140 /* 14=NOP supported, 5=WCACHE supported, 0=SMART supported */
141 put_le16(p + 82, (1 << 14) | (1 << 5) | 1);
c2ff060f
FB		 142 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
143 put_le16(p + 83, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10));
95ebda85
FB		 144 /* 14=set to 1, 8=has WWN, 1=SMART self test, 0=SMART error logging */
145 if (s->wwn) {
146 put_le16(p + 84, (1 << 14) | (1 << 8) | 0);
147 } else {
148 put_le16(p + 84, (1 << 14) | 0);
149 }
e900a7b7
CH		 150 /* 14 = NOP supported, 5=WCACHE enabled, 0=SMART feature set enabled */
151 if (bdrv_enable_write_cache(s->bs))
152 put_le16(p + 85, (1 << 14) | (1 << 5) | 1);
153 else
154 put_le16(p + 85, (1 << 14) | 1);
c2ff060f 155 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
2844bdd9 156 put_le16(p + 86, (1 << 13) | (1 <<12) | (1 << 10));
95ebda85
FB		 157 /* 14=set to 1, 8=has WWN, 1=SMART self test, 0=SMART error logging */
158 if (s->wwn) {
159 put_le16(p + 87, (1 << 14) | (1 << 8) | 0);
160 } else {
161 put_le16(p + 87, (1 << 14) | 0);
162 }
94458802
FB		 163 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
164 put_le16(p + 93, 1 | (1 << 14) | 0x2000);
c2ff060f
FB		 165 put_le16(p + 100, s->nb_sectors);
166 put_le16(p + 101, s->nb_sectors >> 16);
167 put_le16(p + 102, s->nb_sectors >> 32);
168 put_le16(p + 103, s->nb_sectors >> 48);
d353fb72 169
57dac7ef
MA		 170 if (dev && dev->conf.physical_block_size)
171 put_le16(p + 106, 0x6000 | get_physical_block_exp(&dev->conf));
95ebda85
FB		 172 if (s->wwn) {
173 /* LE 16-bit words 111-108 contain 64-bit World Wide Name */
174 put_le16(p + 108, s->wwn >> 48);
175 put_le16(p + 109, s->wwn >> 32);
176 put_le16(p + 110, s->wwn >> 16);
177 put_le16(p + 111, s->wwn);
178 }
d353fb72
CH		 179 if (dev && dev->conf.discard_granularity) {
180 put_le16(p + 169, 1); /* TRIM support */
181 }
94458802
FB		 182
183 memcpy(s->identify_data, p, sizeof(s->identify_data));
184 s->identify_set = 1;
5391d806
FB		 185}
186
187static void ide_atapi_identify(IDEState *s)
188{
189 uint16_t *p;
190
94458802
FB		 191 if (s->identify_set) {
192 memcpy(s->io_buffer, s->identify_data, sizeof(s->identify_data));
193 return;
194 }
195
5391d806
FB		 196 memset(s->io_buffer, 0, 512);
197 p = (uint16_t *)s->io_buffer;
198 /* Removable CDROM, 50us response, 12 byte packets */
67b915a5 199 put_le16(p + 0, (2 << 14) | (5 << 8) | (1 << 7) | (2 << 5) | (0 << 0));
fa879c64 200 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
67b915a5
FB		 201 put_le16(p + 20, 3); /* buffer type */
202 put_le16(p + 21, 512); /* cache size in sectors */
203 put_le16(p + 22, 4); /* ecc bytes */
47c06340 204 padstr((char *)(p + 23), s->version, 8); /* firmware version */
27e0c9a1 205 padstr((char *)(p + 27), s->drive_model_str, 40); /* model */
67b915a5 206 put_le16(p + 48, 1); /* dword I/O (XXX: should not be set on CDROM) */
8ccad811
FB		 207#ifdef USE_DMA_CDROM
208 put_le16(p + 49, 1 << 9 | 1 << 8); /* DMA and LBA supported */
209 put_le16(p + 53, 7); /* words 64-70, 54-58, 88 valid */
d1b5c20d 210 put_le16(p + 62, 7); /* single word dma0-2 supported */
8ccad811 211 put_le16(p + 63, 7); /* mdma0-2 supported */
8ccad811 212#else
67b915a5
FB		 213 put_le16(p + 49, 1 << 9); /* LBA supported, no DMA */
214 put_le16(p + 53, 3); /* words 64-70, 54-58 valid */
215 put_le16(p + 63, 0x103); /* DMA modes XXX: may be incorrect */
8ccad811 216#endif
79d1d331 217 put_le16(p + 64, 3); /* pio3-4 supported */
67b915a5
FB		 218 put_le16(p + 65, 0xb4); /* minimum DMA multiword tx cycle time */
219 put_le16(p + 66, 0xb4); /* recommended DMA multiword tx cycle time */
220 put_le16(p + 67, 0x12c); /* minimum PIO cycle time without flow control */
221 put_le16(p + 68, 0xb4); /* minimum PIO cycle time with IORDY flow control */
94458802 222
67b915a5
FB		 223 put_le16(p + 71, 30); /* in ns */
224 put_le16(p + 72, 30); /* in ns */
5391d806 225
1bdaa28d
AG		 226 if (s->ncq_queues) {
227 put_le16(p + 75, s->ncq_queues - 1);
228 /* NCQ supported */
229 put_le16(p + 76, (1 << 8));
230 }
231
67b915a5 232 put_le16(p + 80, 0x1e); /* support up to ATA/ATAPI-4 */
8ccad811
FB		 233#ifdef USE_DMA_CDROM
234 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
235#endif
94458802
FB		 236 memcpy(s->identify_data, p, sizeof(s->identify_data));
237 s->identify_set = 1;
5391d806
FB		 238}
239
201a51fc
AZ		 240static void ide_cfata_identify(IDEState *s)
241{
242 uint16_t *p;
243 uint32_t cur_sec;
201a51fc
AZ		 244
245 p = (uint16_t *) s->identify_data;
246 if (s->identify_set)
247 goto fill_buffer;
248
249 memset(p, 0, sizeof(s->identify_data));
250
251 cur_sec = s->cylinders * s->heads * s->sectors;
252
253 put_le16(p + 0, 0x848a); /* CF Storage Card signature */
254 put_le16(p + 1, s->cylinders); /* Default cylinders */
255 put_le16(p + 3, s->heads); /* Default heads */
256 put_le16(p + 6, s->sectors); /* Default sectors per track */
257 put_le16(p + 7, s->nb_sectors >> 16); /* Sectors per card */
258 put_le16(p + 8, s->nb_sectors); /* Sectors per card */
fa879c64 259 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
201a51fc 260 put_le16(p + 22, 0x0004); /* ECC bytes */
47c06340 261 padstr((char *) (p + 23), s->version, 8); /* Firmware Revision */
27e0c9a1 262 padstr((char *) (p + 27), s->drive_model_str, 40);/* Model number */
201a51fc
AZ		 263#if MAX_MULT_SECTORS > 1
264 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
265#else
266 put_le16(p + 47, 0x0000);
267#endif
268 put_le16(p + 49, 0x0f00); /* Capabilities */
269 put_le16(p + 51, 0x0002); /* PIO cycle timing mode */
270 put_le16(p + 52, 0x0001); /* DMA cycle timing mode */
271 put_le16(p + 53, 0x0003); /* Translation params valid */
272 put_le16(p + 54, s->cylinders); /* Current cylinders */
273 put_le16(p + 55, s->heads); /* Current heads */
274 put_le16(p + 56, s->sectors); /* Current sectors */
275 put_le16(p + 57, cur_sec); /* Current capacity */
276 put_le16(p + 58, cur_sec >> 16); /* Current capacity */
277 if (s->mult_sectors) /* Multiple sector setting */
278 put_le16(p + 59, 0x100 | s->mult_sectors);
279 put_le16(p + 60, s->nb_sectors); /* Total LBA sectors */
280 put_le16(p + 61, s->nb_sectors >> 16); /* Total LBA sectors */
281 put_le16(p + 63, 0x0203); /* Multiword DMA capability */
282 put_le16(p + 64, 0x0001); /* Flow Control PIO support */
283 put_le16(p + 65, 0x0096); /* Min. Multiword DMA cycle */
284 put_le16(p + 66, 0x0096); /* Rec. Multiword DMA cycle */
285 put_le16(p + 68, 0x00b4); /* Min. PIO cycle time */
286 put_le16(p + 82, 0x400c); /* Command Set supported */
287 put_le16(p + 83, 0x7068); /* Command Set supported */
288 put_le16(p + 84, 0x4000); /* Features supported */
289 put_le16(p + 85, 0x000c); /* Command Set enabled */
290 put_le16(p + 86, 0x7044); /* Command Set enabled */
291 put_le16(p + 87, 0x4000); /* Features enabled */
292 put_le16(p + 91, 0x4060); /* Current APM level */
293 put_le16(p + 129, 0x0002); /* Current features option */
294 put_le16(p + 130, 0x0005); /* Reassigned sectors */
295 put_le16(p + 131, 0x0001); /* Initial power mode */
296 put_le16(p + 132, 0x0000); /* User signature */
297 put_le16(p + 160, 0x8100); /* Power requirement */
298 put_le16(p + 161, 0x8001); /* CF command set */
299
300 s->identify_set = 1;
301
302fill_buffer:
303 memcpy(s->io_buffer, p, sizeof(s->identify_data));
304}
305
5391d806
FB		 306static void ide_set_signature(IDEState *s)
307{
308 s->select &= 0xf0; /* clear head */
309 /* put signature */
310 s->nsector = 1;
311 s->sector = 1;
cd8722bb 312 if (s->drive_kind == IDE_CD) {
5391d806
FB		 313 s->lcyl = 0x14;
314 s->hcyl = 0xeb;
315 } else if (s->bs) {
316 s->lcyl = 0;
317 s->hcyl = 0;
318 } else {
319 s->lcyl = 0xff;
320 s->hcyl = 0xff;
321 }
322}
323
d353fb72
CH		 324typedef struct TrimAIOCB {
325 BlockDriverAIOCB common;
326 QEMUBH *bh;
327 int ret;
501378c3
PB		 328 QEMUIOVector *qiov;
329 BlockDriverAIOCB *aiocb;
330 int i, j;
d353fb72
CH		 331} TrimAIOCB;
332
333static void trim_aio_cancel(BlockDriverAIOCB *acb)
334{
335 TrimAIOCB *iocb = container_of(acb, TrimAIOCB, common);
336
501378c3
PB		 337 /* Exit the loop in case bdrv_aio_cancel calls ide_issue_trim_cb again. */
338 iocb->j = iocb->qiov->niov - 1;
339 iocb->i = (iocb->qiov->iov[iocb->j].iov_len / 8) - 1;
340
341 /* Tell ide_issue_trim_cb not to trigger the completion, too. */
d353fb72
CH		 342 qemu_bh_delete(iocb->bh);
343 iocb->bh = NULL;
501378c3
PB		 344
345 if (iocb->aiocb) {
346 bdrv_aio_cancel(iocb->aiocb);
347 }
d353fb72
CH		 348 qemu_aio_release(iocb);
349}
350
d7331bed 351static const AIOCBInfo trim_aiocb_info = {
d353fb72
CH		 352 .aiocb_size = sizeof(TrimAIOCB),
353 .cancel = trim_aio_cancel,
354};
355
356static void ide_trim_bh_cb(void *opaque)
357{
358 TrimAIOCB *iocb = opaque;
359
360 iocb->common.cb(iocb->common.opaque, iocb->ret);
361
362 qemu_bh_delete(iocb->bh);
363 iocb->bh = NULL;
d353fb72
CH		 364 qemu_aio_release(iocb);
365}
366
501378c3
PB		 367static void ide_issue_trim_cb(void *opaque, int ret)
368{
369 TrimAIOCB *iocb = opaque;
370 if (ret >= 0) {
371 while (iocb->j < iocb->qiov->niov) {
372 int j = iocb->j;
373 while (++iocb->i < iocb->qiov->iov[j].iov_len / 8) {
374 int i = iocb->i;
375 uint64_t *buffer = iocb->qiov->iov[j].iov_base;
376
377 /* 6-byte LBA + 2-byte range per entry */
378 uint64_t entry = le64_to_cpu(buffer[i]);
379 uint64_t sector = entry & 0x0000ffffffffffffULL;
380 uint16_t count = entry >> 48;
381
382 if (count == 0) {
383 continue;
384 }
385
386 /* Got an entry! Submit and exit. */
387 iocb->aiocb = bdrv_aio_discard(iocb->common.bs, sector, count,
388 ide_issue_trim_cb, opaque);
389 return;
390 }
391
392 iocb->j++;
393 iocb->i = -1;
394 }
395 } else {
396 iocb->ret = ret;
397 }
398
399 iocb->aiocb = NULL;
400 if (iocb->bh) {
401 qemu_bh_schedule(iocb->bh);
402 }
403}
404
d353fb72
CH		 405BlockDriverAIOCB *ide_issue_trim(BlockDriverState *bs,
406 int64_t sector_num, QEMUIOVector *qiov, int nb_sectors,
407 BlockDriverCompletionFunc *cb, void *opaque)
408{
409 TrimAIOCB *iocb;
d353fb72 410
d7331bed 411 iocb = qemu_aio_get(&trim_aiocb_info, bs, cb, opaque);
d353fb72
CH		 412 iocb->bh = qemu_bh_new(ide_trim_bh_cb, iocb);
413 iocb->ret = 0;
501378c3
PB		 414 iocb->qiov = qiov;
415 iocb->i = -1;
416 iocb->j = 0;
417 ide_issue_trim_cb(iocb, 0);
d353fb72
CH		 418 return &iocb->common;
419}
420
5391d806
FB		 421static inline void ide_abort_command(IDEState *s)
422{
423 s->status = READY_STAT | ERR_STAT;
424 s->error = ABRT_ERR;
425}
426
5391d806 427/* prepare data transfer and tell what to do after */
33231e0e
KW		 428void ide_transfer_start(IDEState *s, uint8_t *buf, int size,
429 EndTransferFunc *end_transfer_func)
5391d806
FB		 430{
431 s->end_transfer_func = end_transfer_func;
432 s->data_ptr = buf;
433 s->data_end = buf + size;
40a6238a 434 if (!(s->status & ERR_STAT)) {
7603d156 435 s->status |= DRQ_STAT;
40a6238a 436 }
44635123
PB		 437 if (s->bus->dma->ops->start_transfer) {
438 s->bus->dma->ops->start_transfer(s->bus->dma);
439 }
5391d806
FB		 440}
441
33231e0e 442void ide_transfer_stop(IDEState *s)
5391d806
FB		 443{
444 s->end_transfer_func = ide_transfer_stop;
445 s->data_ptr = s->io_buffer;
446 s->data_end = s->io_buffer;
447 s->status &= ~DRQ_STAT;
448}
449
356721ae 450int64_t ide_get_sector(IDEState *s)
5391d806
FB		 451{
452 int64_t sector_num;
453 if (s->select & 0x40) {
454 /* lba */
c2ff060f
FB		 455 if (!s->lba48) {
456 sector_num = ((s->select & 0x0f) << 24) | (s->hcyl << 16) |
457 (s->lcyl << 8) | s->sector;
458 } else {
459 sector_num = ((int64_t)s->hob_hcyl << 40) |
460 ((int64_t) s->hob_lcyl << 32) |
461 ((int64_t) s->hob_sector << 24) |
462 ((int64_t) s->hcyl << 16) |
463 ((int64_t) s->lcyl << 8) | s->sector;
464 }
5391d806
FB		 465 } else {
466 sector_num = ((s->hcyl << 8) | s->lcyl) * s->heads * s->sectors +
c2ff060f 467 (s->select & 0x0f) * s->sectors + (s->sector - 1);
5391d806
FB		 468 }
469 return sector_num;
470}
471
356721ae 472void ide_set_sector(IDEState *s, int64_t sector_num)
5391d806
FB		 473{
474 unsigned int cyl, r;
475 if (s->select & 0x40) {
c2ff060f
FB		 476 if (!s->lba48) {
477 s->select = (s->select & 0xf0) | (sector_num >> 24);
478 s->hcyl = (sector_num >> 16);
479 s->lcyl = (sector_num >> 8);
480 s->sector = (sector_num);
481 } else {
482 s->sector = sector_num;
483 s->lcyl = sector_num >> 8;
484 s->hcyl = sector_num >> 16;
485 s->hob_sector = sector_num >> 24;
486 s->hob_lcyl = sector_num >> 32;
487 s->hob_hcyl = sector_num >> 40;
488 }
5391d806
FB		 489 } else {
490 cyl = sector_num / (s->heads * s->sectors);
491 r = sector_num % (s->heads * s->sectors);
492 s->hcyl = cyl >> 8;
493 s->lcyl = cyl;
1b8eb456 494 s->select = (s->select & 0xf0) | ((r / s->sectors) & 0x0f);
5391d806
FB		 495 s->sector = (r % s->sectors) + 1;
496 }
497}
498
e162cfb0
AZ		 499static void ide_rw_error(IDEState *s) {
500 ide_abort_command(s);
9cdd03a7 501 ide_set_irq(s->bus);
e162cfb0
AZ		 502}
503
58ac3211
MA		 504static bool ide_sect_range_ok(IDEState *s,
505 uint64_t sector, uint64_t nb_sectors)
506{
507 uint64_t total_sectors;
508
509 bdrv_get_geometry(s->bs, &total_sectors);
510 if (sector > total_sectors || nb_sectors > total_sectors - sector) {
511 return false;
512 }
513 return true;
514}
515
bef0fd59
SH		 516static void ide_sector_read_cb(void *opaque, int ret)
517{
518 IDEState *s = opaque;
519 int n;
520
521 s->pio_aiocb = NULL;
522 s->status &= ~BUSY_STAT;
523
524 bdrv_acct_done(s->bs, &s->acct);
525 if (ret != 0) {
526 if (ide_handle_rw_error(s, -ret, BM_STATUS_PIO_RETRY |
527 BM_STATUS_RETRY_READ)) {
528 return;
529 }
530 }
531
532 n = s->nsector;
533 if (n > s->req_nb_sectors) {
534 n = s->req_nb_sectors;
535 }
536
537 /* Allow the guest to read the io_buffer */
538 ide_transfer_start(s, s->io_buffer, n * BDRV_SECTOR_SIZE, ide_sector_read);
539
540 ide_set_irq(s->bus);
541
542 ide_set_sector(s, ide_get_sector(s) + n);
543 s->nsector -= n;
544}
545
40a6238a 546void ide_sector_read(IDEState *s)
5391d806
FB		 547{
548 int64_t sector_num;
bef0fd59 549 int n;
5391d806
FB		 550
551 s->status = READY_STAT | SEEK_STAT;
a136e5a8 552 s->error = 0; /* not needed by IDE spec, but needed by Windows */
5391d806
FB		 553 sector_num = ide_get_sector(s);
554 n = s->nsector;
bef0fd59 555
5391d806 556 if (n == 0) {
5391d806 557 ide_transfer_stop(s);
bef0fd59
SH		 558 return;
559 }
560
561 s->status |= BUSY_STAT;
562
563 if (n > s->req_nb_sectors) {
564 n = s->req_nb_sectors;
565 }
566
5391d806 567#if defined(DEBUG_IDE)
bef0fd59 568 printf("sector=%" PRId64 "\n", sector_num);
5391d806 569#endif
a597e79c 570
58ac3211
MA		 571 if (!ide_sect_range_ok(s, sector_num, n)) {
572 ide_rw_error(s);
573 return;
574 }
575
bef0fd59
SH		 576 s->iov.iov_base = s->io_buffer;
577 s->iov.iov_len = n * BDRV_SECTOR_SIZE;
578 qemu_iovec_init_external(&s->qiov, &s->iov, 1);
579
580 bdrv_acct_start(s->bs, &s->acct, n * BDRV_SECTOR_SIZE, BDRV_ACCT_READ);
581 s->pio_aiocb = bdrv_aio_readv(s->bs, sector_num, &s->qiov, n,
582 ide_sector_read_cb, s);
5391d806
FB		 583}
584
b61744b3 585static void dma_buf_commit(IDEState *s)
7aea4412 586{
1fb8648d 587 qemu_sglist_destroy(&s->sg);
7aea4412
AL		 588}
589
a62eaa26
KW		 590static void ide_async_cmd_done(IDEState *s)
591{
592 if (s->bus->dma->ops->async_cmd_done) {
593 s->bus->dma->ops->async_cmd_done(s->bus->dma);
594 }
595}
596
33231e0e 597void ide_set_inactive(IDEState *s)
8337606d 598{
40a6238a 599 s->bus->dma->aiocb = NULL;
829b933b
PB		 600 if (s->bus->dma->ops->set_inactive) {
601 s->bus->dma->ops->set_inactive(s->bus->dma);
602 }
a62eaa26 603 ide_async_cmd_done(s);
8337606d
KW		 604}
605
356721ae 606void ide_dma_error(IDEState *s)
e162cfb0
AZ		 607{
608 ide_transfer_stop(s);
609 s->error = ABRT_ERR;
610 s->status = READY_STAT | ERR_STAT;
40a6238a 611 ide_set_inactive(s);
9cdd03a7 612 ide_set_irq(s->bus);
e162cfb0
AZ		 613}
614
ce4b6522 615static int ide_handle_rw_error(IDEState *s, int error, int op)
428c5705 616{
1ceee0d5 617 bool is_read = (op & BM_STATUS_RETRY_READ) != 0;
3e1caa5f 618 BlockErrorAction action = bdrv_get_error_action(s->bs, is_read, error);
428c5705 619
a589569f 620 if (action == BLOCK_ERROR_ACTION_STOP) {
40a6238a 621 s->bus->dma->ops->set_unit(s->bus->dma, s->unit);
def93791 622 s->bus->error_status = op;
a589569f 623 } else if (action == BLOCK_ERROR_ACTION_REPORT) {
ce4b6522 624 if (op & BM_STATUS_DMA_RETRY) {
b61744b3 625 dma_buf_commit(s);
428c5705 626 ide_dma_error(s);
7aea4412 627 } else {
428c5705 628 ide_rw_error(s);
7aea4412 629 }
428c5705 630 }
3e1caa5f 631 bdrv_error_action(s->bs, action, is_read, error);
a589569f 632 return action != BLOCK_ERROR_ACTION_IGNORE;
428c5705
AL		 633}
634
cd369c46 635void ide_dma_cb(void *opaque, int ret)
98087450 636{
40a6238a 637 IDEState *s = opaque;
8ccad811
FB		 638 int n;
639 int64_t sector_num;
038268e2 640 bool stay_active = false;
8ccad811 641
e162cfb0 642 if (ret < 0) {
cd369c46
CH		 643 int op = BM_STATUS_DMA_RETRY;
644
4e1e0051 645 if (s->dma_cmd == IDE_DMA_READ)
cd369c46 646 op |= BM_STATUS_RETRY_READ;
d353fb72
CH		 647 else if (s->dma_cmd == IDE_DMA_TRIM)
648 op |= BM_STATUS_RETRY_TRIM;
649
cd369c46 650 if (ide_handle_rw_error(s, -ret, op)) {
ce4b6522
KW		 651 return;
652 }
e162cfb0
AZ		 653 }
654
8ccad811 655 n = s->io_buffer_size >> 9;
038268e2
KW		 656 if (n > s->nsector) {
657 /* The PRDs were longer than needed for this request. Shorten them so
658 * we don't get a negative remainder. The Active bit must remain set
659 * after the request completes. */
660 n = s->nsector;
661 stay_active = true;
662 }
663
8ccad811
FB		 664 sector_num = ide_get_sector(s);
665 if (n > 0) {
b61744b3 666 dma_buf_commit(s);
8ccad811
FB		 667 sector_num += n;
668 ide_set_sector(s, sector_num);
669 s->nsector -= n;
8ccad811
FB		 670 }
671
672 /* end of transfer ? */
673 if (s->nsector == 0) {
98087450 674 s->status = READY_STAT | SEEK_STAT;
9cdd03a7 675 ide_set_irq(s->bus);
cd369c46 676 goto eot;
98087450 677 }
8ccad811
FB		 678
679 /* launch next transfer */
680 n = s->nsector;
596bb44d 681 s->io_buffer_index = 0;
8ccad811 682 s->io_buffer_size = n * 512;
4e1e0051 683 if (s->bus->dma->ops->prepare_buf(s->bus->dma, ide_cmd_is_read(s)) == 0) {
69c38b8f
KW		 684 /* The PRDs were too short. Reset the Active bit, but don't raise an
685 * interrupt. */
72bcca73 686 s->status = READY_STAT | SEEK_STAT;
7aea4412 687 goto eot;
69c38b8f 688 }
cd369c46 689
8ccad811 690#ifdef DEBUG_AIO
4e1e0051
CH		 691 printf("ide_dma_cb: sector_num=%" PRId64 " n=%d, cmd_cmd=%d\n",
692 sector_num, n, s->dma_cmd);
8ccad811 693#endif
cd369c46 694
58ac3211
MA		 695 if (!ide_sect_range_ok(s, sector_num, n)) {
696 dma_buf_commit(s);
697 ide_dma_error(s);
698 return;
699 }
700
4e1e0051
CH		 701 switch (s->dma_cmd) {
702 case IDE_DMA_READ:
cd369c46
CH		 703 s->bus->dma->aiocb = dma_bdrv_read(s->bs, &s->sg, sector_num,
704 ide_dma_cb, s);
4e1e0051
CH		 705 break;
706 case IDE_DMA_WRITE:
cd369c46
CH		 707 s->bus->dma->aiocb = dma_bdrv_write(s->bs, &s->sg, sector_num,
708 ide_dma_cb, s);
4e1e0051 709 break;
d353fb72
CH		 710 case IDE_DMA_TRIM:
711 s->bus->dma->aiocb = dma_bdrv_io(s->bs, &s->sg, sector_num,
43cf8ae6
DG		 712 ide_issue_trim, ide_dma_cb, s,
713 DMA_DIRECTION_TO_DEVICE);
d353fb72 714 break;
cd369c46 715 }
cd369c46
CH		 716 return;
717
718eot:
a597e79c
CH		 719 if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) {
720 bdrv_acct_done(s->bs, &s->acct);
721 }
722 ide_set_inactive(s);
038268e2
KW		 723 if (stay_active) {
724 s->bus->dma->ops->add_status(s->bus->dma, BM_STATUS_DMAING);
725 }
98087450
FB		 726}
727
4e1e0051 728static void ide_sector_start_dma(IDEState *s, enum ide_dma_cmd dma_cmd)
98087450 729{
8ccad811 730 s->status = READY_STAT | SEEK_STAT | DRQ_STAT | BUSY_STAT;
98087450
FB		 731 s->io_buffer_index = 0;
732 s->io_buffer_size = 0;
4e1e0051 733 s->dma_cmd = dma_cmd;
a597e79c
CH		 734
735 switch (dma_cmd) {
736 case IDE_DMA_READ:
737 bdrv_acct_start(s->bs, &s->acct, s->nsector * BDRV_SECTOR_SIZE,
738 BDRV_ACCT_READ);
739 break;
740 case IDE_DMA_WRITE:
741 bdrv_acct_start(s->bs, &s->acct, s->nsector * BDRV_SECTOR_SIZE,
742 BDRV_ACCT_WRITE);
743 break;
744 default:
745 break;
746 }
747
cd369c46 748 s->bus->dma->ops->start_dma(s->bus->dma, s, ide_dma_cb);
98087450
FB		 749}
750
a09db21f
FB		 751static void ide_sector_write_timer_cb(void *opaque)
752{
753 IDEState *s = opaque;
9cdd03a7 754 ide_set_irq(s->bus);
a09db21f
FB		 755}
756
e82dabd8 757static void ide_sector_write_cb(void *opaque, int ret)
5391d806 758{
e82dabd8
SH		 759 IDEState *s = opaque;
760 int n;
a597e79c 761
a597e79c 762 bdrv_acct_done(s->bs, &s->acct);
428c5705 763
e82dabd8
SH		 764 s->pio_aiocb = NULL;
765 s->status &= ~BUSY_STAT;
766
e162cfb0 767 if (ret != 0) {
e82dabd8 768 if (ide_handle_rw_error(s, -ret, BM_STATUS_PIO_RETRY)) {
428c5705 769 return;
e82dabd8 770 }
e162cfb0
AZ		 771 }
772
e82dabd8
SH		 773 n = s->nsector;
774 if (n > s->req_nb_sectors) {
775 n = s->req_nb_sectors;
776 }
5391d806
FB		 777 s->nsector -= n;
778 if (s->nsector == 0) {
292eef5a 779 /* no more sectors to write */
5391d806
FB		 780 ide_transfer_stop(s);
781 } else {
e82dabd8
SH		 782 int n1 = s->nsector;
783 if (n1 > s->req_nb_sectors) {
5391d806 784 n1 = s->req_nb_sectors;
e82dabd8
SH		 785 }
786 ide_transfer_start(s, s->io_buffer, n1 * BDRV_SECTOR_SIZE,
787 ide_sector_write);
5391d806 788 }
e82dabd8 789 ide_set_sector(s, ide_get_sector(s) + n);
3b46e624 790
31c2a146
TS		 791 if (win2k_install_hack && ((++s->irq_count % 16) == 0)) {
792 /* It seems there is a bug in the Windows 2000 installer HDD
793 IDE driver which fills the disk with empty logs when the
794 IDE write IRQ comes too early. This hack tries to correct
795 that at the expense of slower write performances. Use this
796 option _only_ to install Windows 2000. You must disable it
797 for normal use. */
bc72ad67
AB		 798 timer_mod(s->sector_write_timer,
799 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + (get_ticks_per_sec() / 1000));
f7736b91 800 } else {
9cdd03a7 801 ide_set_irq(s->bus);
31c2a146 802 }
5391d806
FB		 803}
804
e82dabd8
SH		 805void ide_sector_write(IDEState *s)
806{
807 int64_t sector_num;
808 int n;
809
810 s->status = READY_STAT | SEEK_STAT | BUSY_STAT;
811 sector_num = ide_get_sector(s);
812#if defined(DEBUG_IDE)
813 printf("sector=%" PRId64 "\n", sector_num);
814#endif
815 n = s->nsector;
816 if (n > s->req_nb_sectors) {
817 n = s->req_nb_sectors;
818 }
819
58ac3211
MA		 820 if (!ide_sect_range_ok(s, sector_num, n)) {
821 ide_rw_error(s);
822 return;
823 }
824
e82dabd8
SH		 825 s->iov.iov_base = s->io_buffer;
826 s->iov.iov_len = n * BDRV_SECTOR_SIZE;
827 qemu_iovec_init_external(&s->qiov, &s->iov, 1);
828
829 bdrv_acct_start(s->bs, &s->acct, n * BDRV_SECTOR_SIZE, BDRV_ACCT_READ);
830 s->pio_aiocb = bdrv_aio_writev(s->bs, sector_num, &s->qiov, n,
831 ide_sector_write_cb, s);
832}
833
b0484ae4
CH		 834static void ide_flush_cb(void *opaque, int ret)
835{
836 IDEState *s = opaque;
837
69f72a22
PB		 838 s->pio_aiocb = NULL;
839
e2bcadad
KW		 840 if (ret < 0) {
841 /* XXX: What sector number to set here? */
842 if (ide_handle_rw_error(s, -ret, BM_STATUS_RETRY_FLUSH)) {
843 return;
844 }
845 }
b0484ae4 846
a597e79c 847 bdrv_acct_done(s->bs, &s->acct);
b0484ae4 848 s->status = READY_STAT | SEEK_STAT;
a62eaa26 849 ide_async_cmd_done(s);
b0484ae4
CH		 850 ide_set_irq(s->bus);
851}
852
40a6238a 853void ide_flush_cache(IDEState *s)
6bcb1a79 854{
b2df7531 855 if (s->bs == NULL) {
6bcb1a79 856 ide_flush_cb(s, 0);
b2df7531
KW		 857 return;
858 }
859
f68ec837 860 s->status |= BUSY_STAT;
a597e79c 861 bdrv_acct_start(s->bs, &s->acct, 0, BDRV_ACCT_FLUSH);
69f72a22 862 s->pio_aiocb = bdrv_aio_flush(s->bs, ide_flush_cb, s);
6bcb1a79
KW		 863}
864
201a51fc
AZ		 865static void ide_cfata_metadata_inquiry(IDEState *s)
866{
867 uint16_t *p;
868 uint32_t spd;
869
870 p = (uint16_t *) s->io_buffer;
871 memset(p, 0, 0x200);
872 spd = ((s->mdata_size - 1) >> 9) + 1;
873
874 put_le16(p + 0, 0x0001); /* Data format revision */
875 put_le16(p + 1, 0x0000); /* Media property: silicon */
876 put_le16(p + 2, s->media_changed); /* Media status */
877 put_le16(p + 3, s->mdata_size & 0xffff); /* Capacity in bytes (low) */
878 put_le16(p + 4, s->mdata_size >> 16); /* Capacity in bytes (high) */
879 put_le16(p + 5, spd & 0xffff); /* Sectors per device (low) */
880 put_le16(p + 6, spd >> 16); /* Sectors per device (high) */
881}
882
883static void ide_cfata_metadata_read(IDEState *s)
884{
885 uint16_t *p;
886
887 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
888 s->status = ERR_STAT;
889 s->error = ABRT_ERR;
890 return;
891 }
892
893 p = (uint16_t *) s->io_buffer;
894 memset(p, 0, 0x200);
895
896 put_le16(p + 0, s->media_changed); /* Media status */
897 memcpy(p + 1, s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
898 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
899 s->nsector << 9), 0x200 - 2));
900}
901
902static void ide_cfata_metadata_write(IDEState *s)
903{
904 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
905 s->status = ERR_STAT;
906 s->error = ABRT_ERR;
907 return;
908 }
909
910 s->media_changed = 0;
911
912 memcpy(s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
913 s->io_buffer + 2,
914 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
915 s->nsector << 9), 0x200 - 2));
916}
917
bd491d6a 918/* called when the inserted state of the media has changed */
7d4b4ba5 919static void ide_cd_change_cb(void *opaque, bool load)
bd491d6a
TS		 920{
921 IDEState *s = opaque;
96b8f136 922 uint64_t nb_sectors;
bd491d6a 923
25ad22bc 924 s->tray_open = !load;
bd491d6a
TS		 925 bdrv_get_geometry(s->bs, &nb_sectors);
926 s->nb_sectors = nb_sectors;
9118e7f0 927
4b9b7092
AS		 928 /*
929 * First indicate to the guest that a CD has been removed. That's
930 * done on the next command the guest sends us.
931 *
67cc61e4 932 * Then we set UNIT_ATTENTION, by which the guest will
4b9b7092
AS		 933 * detect a new CD in the drive. See ide_atapi_cmd() for details.
934 */
93c8cfd9 935 s->cdrom_changed = 1;
996faf1a 936 s->events.new_media = true;
2df0a3a3
PB		 937 s->events.eject_request = false;
938 ide_set_irq(s->bus);
939}
940
941static void ide_cd_eject_request_cb(void *opaque, bool force)
942{
943 IDEState *s = opaque;
944
945 s->events.eject_request = true;
946 if (force) {
947 s->tray_locked = false;
948 }
9cdd03a7 949 ide_set_irq(s->bus);
bd491d6a
TS		 950}
951
c2ff060f
FB		 952static void ide_cmd_lba48_transform(IDEState *s, int lba48)
953{
954 s->lba48 = lba48;
955
956 /* handle the 'magic' 0 nsector count conversion here. to avoid
957 * fiddling with the rest of the read logic, we just store the
958 * full sector count in ->nsector and ignore ->hob_nsector from now
959 */
960 if (!s->lba48) {
961 if (!s->nsector)
962 s->nsector = 256;
963 } else {
964 if (!s->nsector && !s->hob_nsector)
965 s->nsector = 65536;
966 else {
967 int lo = s->nsector;
968 int hi = s->hob_nsector;
969
970 s->nsector = (hi << 8) | lo;
971 }
972 }
973}
974
bcbdc4d3 975static void ide_clear_hob(IDEBus *bus)
c2ff060f
FB		 976{
977 /* any write clears HOB high bit of device control register */
bcbdc4d3
GH		 978 bus->ifs[0].select &= ~(1 << 7);
979 bus->ifs[1].select &= ~(1 << 7);
c2ff060f
FB		 980}
981
356721ae 982void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
caed8802 983{
bcbdc4d3 984 IDEBus *bus = opaque;
5391d806
FB		 985
986#ifdef DEBUG_IDE
987 printf("IDE: write addr=0x%x val=0x%02x\n", addr, val);
988#endif
c2ff060f 989
5391d806 990 addr &= 7;
fcdd25ab
AL		 991
992 /* ignore writes to command block while busy with previous command */
bcbdc4d3 993 if (addr != 7 && (idebus_active_if(bus)->status & (BUSY_STAT|DRQ_STAT)))
fcdd25ab
AL		 994 return;
995
5391d806
FB		 996 switch(addr) {
997 case 0:
998 break;
999 case 1:
bcbdc4d3 1000 ide_clear_hob(bus);
c45c3d00 1001 /* NOTE: data is written to the two drives */
bcbdc4d3
GH		 1002 bus->ifs[0].hob_feature = bus->ifs[0].feature;
1003 bus->ifs[1].hob_feature = bus->ifs[1].feature;
1004 bus->ifs[0].feature = val;
1005 bus->ifs[1].feature = val;
5391d806
FB		 1006 break;
1007 case 2:
bcbdc4d3
GH		 1008 ide_clear_hob(bus);
1009 bus->ifs[0].hob_nsector = bus->ifs[0].nsector;
1010 bus->ifs[1].hob_nsector = bus->ifs[1].nsector;
1011 bus->ifs[0].nsector = val;
1012 bus->ifs[1].nsector = val;
5391d806
FB		 1013 break;
1014 case 3:
bcbdc4d3
GH		 1015 ide_clear_hob(bus);
1016 bus->ifs[0].hob_sector = bus->ifs[0].sector;
1017 bus->ifs[1].hob_sector = bus->ifs[1].sector;
1018 bus->ifs[0].sector = val;
1019 bus->ifs[1].sector = val;
5391d806
FB		 1020 break;
1021 case 4:
bcbdc4d3
GH		 1022 ide_clear_hob(bus);
1023 bus->ifs[0].hob_lcyl = bus->ifs[0].lcyl;
1024 bus->ifs[1].hob_lcyl = bus->ifs[1].lcyl;
1025 bus->ifs[0].lcyl = val;
1026 bus->ifs[1].lcyl = val;
5391d806
FB		 1027 break;
1028 case 5:
bcbdc4d3
GH		 1029 ide_clear_hob(bus);
1030 bus->ifs[0].hob_hcyl = bus->ifs[0].hcyl;
1031 bus->ifs[1].hob_hcyl = bus->ifs[1].hcyl;
1032 bus->ifs[0].hcyl = val;
1033 bus->ifs[1].hcyl = val;
5391d806
FB		 1034 break;
1035 case 6:
c2ff060f 1036 /* FIXME: HOB readback uses bit 7 */
bcbdc4d3
GH		 1037 bus->ifs[0].select = (val & ~0x10) | 0xa0;
1038 bus->ifs[1].select = (val | 0x10) | 0xa0;
5391d806 1039 /* select drive */
bcbdc4d3 1040 bus->unit = (val >> 4) & 1;
5391d806
FB		 1041 break;
1042 default:
1043 case 7:
1044 /* command */
7cff87ff
AG		 1045 ide_exec_cmd(bus, val);
1046 break;
1047 }
1048}
1049
b300337e
KW		 1050static bool cmd_nop(IDEState *s, uint8_t cmd)
1051{
1052 return true;
1053}
1054
4286434c
KW		 1055static bool cmd_data_set_management(IDEState *s, uint8_t cmd)
1056{
1057 switch (s->feature) {
1058 case DSM_TRIM:
1059 if (s->bs) {
1060 ide_sector_start_dma(s, IDE_DMA_TRIM);
1061 return false;
1062 }
1063 break;
1064 }
1065
1066 ide_abort_command(s);
1067 return true;
1068}
1069
1c66869a
KW		 1070static bool cmd_identify(IDEState *s, uint8_t cmd)
1071{
1072 if (s->bs && s->drive_kind != IDE_CD) {
1073 if (s->drive_kind != IDE_CFATA) {
1074 ide_identify(s);
1075 } else {
1076 ide_cfata_identify(s);
1077 }
1078 s->status = READY_STAT | SEEK_STAT;
1079 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
1080 ide_set_irq(s->bus);
1081 return false;
1082 } else {
1083 if (s->drive_kind == IDE_CD) {
1084 ide_set_signature(s);
1085 }
1086 ide_abort_command(s);
1087 }
1088
1089 return true;
1090}
1091
413860cf
KW		 1092static bool cmd_verify(IDEState *s, uint8_t cmd)
1093{
1094 bool lba48 = (cmd == WIN_VERIFY_EXT);
1095
1096 /* do sector number check ? */
1097 ide_cmd_lba48_transform(s, lba48);
1098
1099 return true;
1100}
1101
adf3a2c4
KW		 1102static bool cmd_set_multiple_mode(IDEState *s, uint8_t cmd)
1103{
1104 if (s->drive_kind == IDE_CFATA && s->nsector == 0) {
1105 /* Disable Read and Write Multiple */
1106 s->mult_sectors = 0;
1107 } else if ((s->nsector & 0xff) != 0 &&
1108 ((s->nsector & 0xff) > MAX_MULT_SECTORS ||
1109 (s->nsector & (s->nsector - 1)) != 0)) {
1110 ide_abort_command(s);
1111 } else {
1112 s->mult_sectors = s->nsector & 0xff;
1113 }
1114
1115 return true;
1116}
1117
1118static bool cmd_read_multiple(IDEState *s, uint8_t cmd)
1119{
1120 bool lba48 = (cmd == WIN_MULTREAD_EXT);
1121
1122 if (!s->bs || !s->mult_sectors) {
1123 ide_abort_command(s);
1124 return true;
1125 }
1126
1127 ide_cmd_lba48_transform(s, lba48);
1128 s->req_nb_sectors = s->mult_sectors;
1129 ide_sector_read(s);
1130 return false;
1131}
1132
1133static bool cmd_write_multiple(IDEState *s, uint8_t cmd)
1134{
1135 bool lba48 = (cmd == WIN_MULTWRITE_EXT);
1136 int n;
1137
1138 if (!s->bs || !s->mult_sectors) {
1139 ide_abort_command(s);
1140 return true;
1141 }
1142
1143 ide_cmd_lba48_transform(s, lba48);
1144
1145 s->req_nb_sectors = s->mult_sectors;
1146 n = MIN(s->nsector, s->req_nb_sectors);
1147
1148 s->status = SEEK_STAT | READY_STAT;
1149 ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_write);
1150
1151 s->media_changed = 1;
1152
1153 return false;
1154}
1155
0e6498ed
KW		 1156static bool cmd_read_pio(IDEState *s, uint8_t cmd)
1157{
1158 bool lba48 = (cmd == WIN_READ_EXT);
1159
1160 if (s->drive_kind == IDE_CD) {
1161 ide_set_signature(s); /* odd, but ATA4 8.27.5.2 requires it */
1162 ide_abort_command(s);
1163 return true;
1164 }
1165
1166 if (!s->bs) {
1167 ide_abort_command(s);
1168 return true;
1169 }
1170
1171 ide_cmd_lba48_transform(s, lba48);
1172 s->req_nb_sectors = 1;
1173 ide_sector_read(s);
1174
1175 return false;
1176}
1177
1178static bool cmd_write_pio(IDEState *s, uint8_t cmd)
1179{
1180 bool lba48 = (cmd == WIN_WRITE_EXT);
1181
1182 if (!s->bs) {
1183 ide_abort_command(s);
1184 return true;
1185 }
1186
1187 ide_cmd_lba48_transform(s, lba48);
1188
1189 s->req_nb_sectors = 1;
1190 s->status = SEEK_STAT | READY_STAT;
1191 ide_transfer_start(s, s->io_buffer, 512, ide_sector_write);
1192
1193 s->media_changed = 1;
1194
1195 return false;
1196}
1197
92a6a6f6
KW		 1198static bool cmd_read_dma(IDEState *s, uint8_t cmd)
1199{
1200 bool lba48 = (cmd == WIN_READDMA_EXT);
1201
1202 if (!s->bs) {
1203 ide_abort_command(s);
1204 return true;
1205 }
1206
1207 ide_cmd_lba48_transform(s, lba48);
1208 ide_sector_start_dma(s, IDE_DMA_READ);
1209
1210 return false;
1211}
1212
1213static bool cmd_write_dma(IDEState *s, uint8_t cmd)
1214{
1215 bool lba48 = (cmd == WIN_WRITEDMA_EXT);
1216
1217 if (!s->bs) {
1218 ide_abort_command(s);
1219 return true;
1220 }
1221
1222 ide_cmd_lba48_transform(s, lba48);
1223 ide_sector_start_dma(s, IDE_DMA_WRITE);
1224
1225 s->media_changed = 1;
1226
1227 return false;
1228}
1229
9afce429
KW		 1230static bool cmd_flush_cache(IDEState *s, uint8_t cmd)
1231{
1232 ide_flush_cache(s);
1233 return false;
1234}
1235
61fdda37
KW		 1236static bool cmd_seek(IDEState *s, uint8_t cmd)
1237{
1238 /* XXX: Check that seek is within bounds */
1239 return true;
1240}
1241
63a82e6a
KW		 1242static bool cmd_read_native_max(IDEState *s, uint8_t cmd)
1243{
1244 bool lba48 = (cmd == WIN_READ_NATIVE_MAX_EXT);
1245
1246 /* Refuse if no sectors are addressable (e.g. medium not inserted) */
1247 if (s->nb_sectors == 0) {
1248 ide_abort_command(s);
1249 return true;
1250 }
1251
1252 ide_cmd_lba48_transform(s, lba48);
1253 ide_set_sector(s, s->nb_sectors - 1);
1254
1255 return true;
1256}
1257
785f6320
KW		 1258static bool cmd_check_power_mode(IDEState *s, uint8_t cmd)
1259{
1260 s->nsector = 0xff; /* device active or idle */
1261 return true;
1262}
1263
ee03398c
KW		 1264static bool cmd_set_features(IDEState *s, uint8_t cmd)
1265{
1266 uint16_t *identify_data;
1267
1268 if (!s->bs) {
1269 ide_abort_command(s);
1270 return true;
1271 }
1272
1273 /* XXX: valid for CDROM ? */
1274 switch (s->feature) {
1275 case 0x02: /* write cache enable */
1276 bdrv_set_enable_write_cache(s->bs, true);
1277 identify_data = (uint16_t *)s->identify_data;
1278 put_le16(identify_data + 85, (1 << 14) | (1 << 5) | 1);
1279 return true;
1280 case 0x82: /* write cache disable */
1281 bdrv_set_enable_write_cache(s->bs, false);
1282 identify_data = (uint16_t *)s->identify_data;
1283 put_le16(identify_data + 85, (1 << 14) | 1);
1284 ide_flush_cache(s);
1285 return false;
1286 case 0xcc: /* reverting to power-on defaults enable */
1287 case 0x66: /* reverting to power-on defaults disable */
1288 case 0xaa: /* read look-ahead enable */
1289 case 0x55: /* read look-ahead disable */
1290 case 0x05: /* set advanced power management mode */
1291 case 0x85: /* disable advanced power management mode */
1292 case 0x69: /* NOP */
1293 case 0x67: /* NOP */
1294 case 0x96: /* NOP */
1295 case 0x9a: /* NOP */
1296 case 0x42: /* enable Automatic Acoustic Mode */
1297 case 0xc2: /* disable Automatic Acoustic Mode */
1298 return true;
1299 case 0x03: /* set transfer mode */
1300 {
1301 uint8_t val = s->nsector & 0x07;
1302 identify_data = (uint16_t *)s->identify_data;
1303
1304 switch (s->nsector >> 3) {
1305 case 0x00: /* pio default */
1306 case 0x01: /* pio mode */
1307 put_le16(identify_data + 62, 0x07);
1308 put_le16(identify_data + 63, 0x07);
1309 put_le16(identify_data + 88, 0x3f);
1310 break;
1311 case 0x02: /* sigle word dma mode*/
1312 put_le16(identify_data + 62, 0x07 | (1 << (val + 8)));
1313 put_le16(identify_data + 63, 0x07);
1314 put_le16(identify_data + 88, 0x3f);
1315 break;
1316 case 0x04: /* mdma mode */
1317 put_le16(identify_data + 62, 0x07);
1318 put_le16(identify_data + 63, 0x07 | (1 << (val + 8)));
1319 put_le16(identify_data + 88, 0x3f);
1320 break;
1321 case 0x08: /* udma mode */
1322 put_le16(identify_data + 62, 0x07);
1323 put_le16(identify_data + 63, 0x07);
1324 put_le16(identify_data + 88, 0x3f | (1 << (val + 8)));
1325 break;
1326 default:
1327 goto abort_cmd;
1328 }
1329 return true;
1330 }
1331 }
1332
1333abort_cmd:
1334 ide_abort_command(s);
1335 return true;
1336}
1337
ee425c78
KW		 1338
1339/*** ATAPI commands ***/
1340
1341static bool cmd_identify_packet(IDEState *s, uint8_t cmd)
1342{
1343 ide_atapi_identify(s);
1344 s->status = READY_STAT | SEEK_STAT;
1345 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
1346 ide_set_irq(s->bus);
1347 return false;
1348}
1349
1350static bool cmd_exec_dev_diagnostic(IDEState *s, uint8_t cmd)
1351{
1352 ide_set_signature(s);
1353
1354 if (s->drive_kind == IDE_CD) {
1355 s->status = 0; /* ATAPI spec (v6) section 9.10 defines packet
1356 * devices to return a clear status register
1357 * with READY_STAT *not* set. */
850484a2 1358 s->error = 0x01;
ee425c78
KW		 1359 } else {
1360 s->status = READY_STAT | SEEK_STAT;
1361 /* The bits of the error register are not as usual for this command!
1362 * They are part of the regular output (this is why ERR_STAT isn't set)
1363 * Device 0 passed, Device 1 passed or not present. */
1364 s->error = 0x01;
1365 ide_set_irq(s->bus);
1366 }
1367
1368 return false;
1369}
1370
1371static bool cmd_device_reset(IDEState *s, uint8_t cmd)
1372{
1373 ide_set_signature(s);
1374 s->status = 0x00; /* NOTE: READY is _not_ set */
1375 s->error = 0x01;
1376
1377 return false;
1378}
1379
1380static bool cmd_packet(IDEState *s, uint8_t cmd)
1381{
1382 /* overlapping commands not supported */
1383 if (s->feature & 0x02) {
1384 ide_abort_command(s);
1385 return true;
1386 }
1387
1388 s->status = READY_STAT | SEEK_STAT;
1389 s->atapi_dma = s->feature & 1;
1390 s->nsector = 1;
1391 ide_transfer_start(s, s->io_buffer, ATAPI_PACKET_SIZE,
1392 ide_atapi_cmd);
1393 return false;
1394}
1395
6b1dd744
KW		 1396
1397/*** CF-ATA commands ***/
1398
1399static bool cmd_cfa_req_ext_error_code(IDEState *s, uint8_t cmd)
1400{
1401 s->error = 0x09; /* miscellaneous error */
1402 s->status = READY_STAT | SEEK_STAT;
1403 ide_set_irq(s->bus);
1404
1405 return false;
1406}
1407
1408static bool cmd_cfa_erase_sectors(IDEState *s, uint8_t cmd)
1409{
1410 /* WIN_SECURITY_FREEZE_LOCK has the same ID as CFA_WEAR_LEVEL and is
1411 * required for Windows 8 to work with AHCI */
1412
1413 if (cmd == CFA_WEAR_LEVEL) {
1414 s->nsector = 0;
1415 }
1416
1417 if (cmd == CFA_ERASE_SECTORS) {
1418 s->media_changed = 1;
1419 }
1420
1421 return true;
1422}
1423
1424static bool cmd_cfa_translate_sector(IDEState *s, uint8_t cmd)
1425{
1426 s->status = READY_STAT | SEEK_STAT;
1427
1428 memset(s->io_buffer, 0, 0x200);
1429 s->io_buffer[0x00] = s->hcyl; /* Cyl MSB */
1430 s->io_buffer[0x01] = s->lcyl; /* Cyl LSB */
1431 s->io_buffer[0x02] = s->select; /* Head */
1432 s->io_buffer[0x03] = s->sector; /* Sector */
1433 s->io_buffer[0x04] = ide_get_sector(s) >> 16; /* LBA MSB */
1434 s->io_buffer[0x05] = ide_get_sector(s) >> 8; /* LBA */
1435 s->io_buffer[0x06] = ide_get_sector(s) >> 0; /* LBA LSB */
1436 s->io_buffer[0x13] = 0x00; /* Erase flag */
1437 s->io_buffer[0x18] = 0x00; /* Hot count */
1438 s->io_buffer[0x19] = 0x00; /* Hot count */
1439 s->io_buffer[0x1a] = 0x01; /* Hot count */
1440
1441 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1442 ide_set_irq(s->bus);
1443
1444 return false;
1445}
1446
1447static bool cmd_cfa_access_metadata_storage(IDEState *s, uint8_t cmd)
1448{
1449 switch (s->feature) {
1450 case 0x02: /* Inquiry Metadata Storage */
1451 ide_cfata_metadata_inquiry(s);
1452 break;
1453 case 0x03: /* Read Metadata Storage */
1454 ide_cfata_metadata_read(s);
1455 break;
1456 case 0x04: /* Write Metadata Storage */
1457 ide_cfata_metadata_write(s);
1458 break;
1459 default:
1460 ide_abort_command(s);
1461 return true;
1462 }
1463
1464 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1465 s->status = 0x00; /* NOTE: READY is _not_ set */
1466 ide_set_irq(s->bus);
1467
1468 return false;
1469}
1470
1471static bool cmd_ibm_sense_condition(IDEState *s, uint8_t cmd)
1472{
1473 switch (s->feature) {
1474 case 0x01: /* sense temperature in device */
1475 s->nsector = 0x50; /* +20 C */
1476 break;
1477 default:
1478 ide_abort_command(s);
1479 return true;
1480 }
1481
1482 return true;
1483}
1484
ff352677
KW		 1485
1486/*** SMART commands ***/
1487
1488static bool cmd_smart(IDEState *s, uint8_t cmd)
1489{
1490 int n;
1491
1492 if (s->hcyl != 0xc2 || s->lcyl != 0x4f) {
1493 goto abort_cmd;
1494 }
1495
1496 if (!s->smart_enabled && s->feature != SMART_ENABLE) {
1497 goto abort_cmd;
1498 }
1499
1500 switch (s->feature) {
1501 case SMART_DISABLE:
1502 s->smart_enabled = 0;
1503 return true;
1504
1505 case SMART_ENABLE:
1506 s->smart_enabled = 1;
1507 return true;
1508
1509 case SMART_ATTR_AUTOSAVE:
1510 switch (s->sector) {
1511 case 0x00:
1512 s->smart_autosave = 0;
1513 break;
1514 case 0xf1:
1515 s->smart_autosave = 1;
1516 break;
1517 default:
1518 goto abort_cmd;
1519 }
1520 return true;
1521
1522 case SMART_STATUS:
1523 if (!s->smart_errors) {
1524 s->hcyl = 0xc2;
1525 s->lcyl = 0x4f;
1526 } else {
1527 s->hcyl = 0x2c;
1528 s->lcyl = 0xf4;
1529 }
1530 return true;
1531
1532 case SMART_READ_THRESH:
1533 memset(s->io_buffer, 0, 0x200);
1534 s->io_buffer[0] = 0x01; /* smart struct version */
1535
1536 for (n = 0; n < ARRAY_SIZE(smart_attributes); n++) {
1537 s->io_buffer[2 + 0 + (n * 12)] = smart_attributes[n][0];
1538 s->io_buffer[2 + 1 + (n * 12)] = smart_attributes[n][11];
1539 }
1540
1541 /* checksum */
1542 for (n = 0; n < 511; n++) {
1543 s->io_buffer[511] += s->io_buffer[n];
1544 }
1545 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1546
1547 s->status = READY_STAT | SEEK_STAT;
1548 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1549 ide_set_irq(s->bus);
1550 return false;
1551
1552 case SMART_READ_DATA:
1553 memset(s->io_buffer, 0, 0x200);
1554 s->io_buffer[0] = 0x01; /* smart struct version */
1555
1556 for (n = 0; n < ARRAY_SIZE(smart_attributes); n++) {
1557 int i;
1558 for (i = 0; i < 11; i++) {
1559 s->io_buffer[2 + i + (n * 12)] = smart_attributes[n][i];
1560 }
1561 }
1562
1563 s->io_buffer[362] = 0x02 | (s->smart_autosave ? 0x80 : 0x00);
1564 if (s->smart_selftest_count == 0) {
1565 s->io_buffer[363] = 0;
1566 } else {
1567 s->io_buffer[363] =
1568 s->smart_selftest_data[3 +
1569 (s->smart_selftest_count - 1) *
1570 24];
1571 }
1572 s->io_buffer[364] = 0x20;
1573 s->io_buffer[365] = 0x01;
1574 /* offline data collection capacity: execute + self-test*/
1575 s->io_buffer[367] = (1 << 4 | 1 << 3 | 1);
1576 s->io_buffer[368] = 0x03; /* smart capability (1) */
1577 s->io_buffer[369] = 0x00; /* smart capability (2) */
1578 s->io_buffer[370] = 0x01; /* error logging supported */
1579 s->io_buffer[372] = 0x02; /* minutes for poll short test */
1580 s->io_buffer[373] = 0x36; /* minutes for poll ext test */
1581 s->io_buffer[374] = 0x01; /* minutes for poll conveyance */
1582
1583 for (n = 0; n < 511; n++) {
1584 s->io_buffer[511] += s->io_buffer[n];
1585 }
1586 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1587
1588 s->status = READY_STAT | SEEK_STAT;
1589 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1590 ide_set_irq(s->bus);
1591 return false;
1592
1593 case SMART_READ_LOG:
1594 switch (s->sector) {
1595 case 0x01: /* summary smart error log */
1596 memset(s->io_buffer, 0, 0x200);
1597 s->io_buffer[0] = 0x01;
1598 s->io_buffer[1] = 0x00; /* no error entries */
1599 s->io_buffer[452] = s->smart_errors & 0xff;
1600 s->io_buffer[453] = (s->smart_errors & 0xff00) >> 8;
1601
1602 for (n = 0; n < 511; n++) {
1603 s->io_buffer[511] += s->io_buffer[n];
1604 }
1605 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1606 break;
1607 case 0x06: /* smart self test log */
1608 memset(s->io_buffer, 0, 0x200);
1609 s->io_buffer[0] = 0x01;
1610 if (s->smart_selftest_count == 0) {
1611 s->io_buffer[508] = 0;
1612 } else {
1613 s->io_buffer[508] = s->smart_selftest_count;
1614 for (n = 2; n < 506; n++) {
1615 s->io_buffer[n] = s->smart_selftest_data[n];
1616 }
1617 }
1618
1619 for (n = 0; n < 511; n++) {
1620 s->io_buffer[511] += s->io_buffer[n];
1621 }
1622 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1623 break;
1624 default:
1625 goto abort_cmd;
1626 }
1627 s->status = READY_STAT | SEEK_STAT;
1628 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1629 ide_set_irq(s->bus);
1630 return false;
1631
1632 case SMART_EXECUTE_OFFLINE:
1633 switch (s->sector) {
1634 case 0: /* off-line routine */
1635 case 1: /* short self test */
1636 case 2: /* extended self test */
1637 s->smart_selftest_count++;
1638 if (s->smart_selftest_count > 21) {
940973ae 1639 s->smart_selftest_count = 1;
ff352677
KW		 1640 }
1641 n = 2 + (s->smart_selftest_count - 1) * 24;
1642 s->smart_selftest_data[n] = s->sector;
1643 s->smart_selftest_data[n + 1] = 0x00; /* OK and finished */
1644 s->smart_selftest_data[n + 2] = 0x34; /* hour count lsb */
1645 s->smart_selftest_data[n + 3] = 0x12; /* hour count msb */
1646 break;
1647 default:
1648 goto abort_cmd;
1649 }
1650 return true;
1651 }
1652
1653abort_cmd:
1654 ide_abort_command(s);
1655 return true;
1656}
1657
844505b1
MA		 1658#define HD_OK (1u << IDE_HD)
1659#define CD_OK (1u << IDE_CD)
1660#define CFA_OK (1u << IDE_CFATA)
1661#define HD_CFA_OK (HD_OK | CFA_OK)
1662#define ALL_OK (HD_OK | CD_OK | CFA_OK)
1663
a0436e92
KW		 1664/* Set the Disk Seek Completed status bit during completion */
1665#define SET_DSC (1u << 8)
1666
844505b1 1667/* See ACS-2 T13/2015-D Table B.2 Command codes */
a0436e92
KW		 1668static const struct {
1669 /* Returns true if the completion code should be run */
1670 bool (*handler)(IDEState *s, uint8_t cmd);
1671 int flags;
1672} ide_cmd_table[0x100] = {
844505b1 1673 /* NOP not implemented, mandatory for CD */
6b1dd744 1674 [CFA_REQ_EXT_ERROR_CODE] = { cmd_cfa_req_ext_error_code, CFA_OK },
4286434c 1675 [WIN_DSM] = { cmd_data_set_management, ALL_OK },
ee425c78 1676 [WIN_DEVICE_RESET] = { cmd_device_reset, CD_OK },
b300337e 1677 [WIN_RECAL] = { cmd_nop, HD_CFA_OK | SET_DSC},
0e6498ed
KW		 1678 [WIN_READ] = { cmd_read_pio, ALL_OK },
1679 [WIN_READ_ONCE] = { cmd_read_pio, ALL_OK },
1680 [WIN_READ_EXT] = { cmd_read_pio, HD_CFA_OK },
92a6a6f6 1681 [WIN_READDMA_EXT] = { cmd_read_dma, HD_CFA_OK },
63a82e6a 1682 [WIN_READ_NATIVE_MAX_EXT] = { cmd_read_native_max, HD_CFA_OK | SET_DSC },
adf3a2c4 1683 [WIN_MULTREAD_EXT] = { cmd_read_multiple, HD_CFA_OK },
0e6498ed
KW		 1684 [WIN_WRITE] = { cmd_write_pio, HD_CFA_OK },
1685 [WIN_WRITE_ONCE] = { cmd_write_pio, HD_CFA_OK },
1686 [WIN_WRITE_EXT] = { cmd_write_pio, HD_CFA_OK },
92a6a6f6 1687 [WIN_WRITEDMA_EXT] = { cmd_write_dma, HD_CFA_OK },
0e6498ed 1688 [CFA_WRITE_SECT_WO_ERASE] = { cmd_write_pio, CFA_OK },
adf3a2c4 1689 [WIN_MULTWRITE_EXT] = { cmd_write_multiple, HD_CFA_OK },
0e6498ed 1690 [WIN_WRITE_VERIFY] = { cmd_write_pio, HD_CFA_OK },
413860cf
KW		 1691 [WIN_VERIFY] = { cmd_verify, HD_CFA_OK | SET_DSC },
1692 [WIN_VERIFY_ONCE] = { cmd_verify, HD_CFA_OK | SET_DSC },
1693 [WIN_VERIFY_EXT] = { cmd_verify, HD_CFA_OK | SET_DSC },
61fdda37 1694 [WIN_SEEK] = { cmd_seek, HD_CFA_OK | SET_DSC },
6b1dd744 1695 [CFA_TRANSLATE_SECTOR] = { cmd_cfa_translate_sector, CFA_OK },
ee425c78 1696 [WIN_DIAGNOSE] = { cmd_exec_dev_diagnostic, ALL_OK },
b300337e
KW		 1697 [WIN_SPECIFY] = { cmd_nop, HD_CFA_OK | SET_DSC },
1698 [WIN_STANDBYNOW2] = { cmd_nop, ALL_OK },
1699 [WIN_IDLEIMMEDIATE2] = { cmd_nop, ALL_OK },
1700 [WIN_STANDBY2] = { cmd_nop, ALL_OK },
1701 [WIN_SETIDLE2] = { cmd_nop, ALL_OK },
785f6320 1702 [WIN_CHECKPOWERMODE2] = { cmd_check_power_mode, ALL_OK | SET_DSC },
b300337e 1703 [WIN_SLEEPNOW2] = { cmd_nop, ALL_OK },
ee425c78
KW		 1704 [WIN_PACKETCMD] = { cmd_packet, CD_OK },
1705 [WIN_PIDENTIFY] = { cmd_identify_packet, CD_OK },
ff352677 1706 [WIN_SMART] = { cmd_smart, HD_CFA_OK | SET_DSC },
6b1dd744
KW		 1707 [CFA_ACCESS_METADATA_STORAGE] = { cmd_cfa_access_metadata_storage, CFA_OK },
1708 [CFA_ERASE_SECTORS] = { cmd_cfa_erase_sectors, CFA_OK | SET_DSC },
adf3a2c4
KW		 1709 [WIN_MULTREAD] = { cmd_read_multiple, HD_CFA_OK },
1710 [WIN_MULTWRITE] = { cmd_write_multiple, HD_CFA_OK },
1711 [WIN_SETMULT] = { cmd_set_multiple_mode, HD_CFA_OK | SET_DSC },
92a6a6f6
KW		 1712 [WIN_READDMA] = { cmd_read_dma, HD_CFA_OK },
1713 [WIN_READDMA_ONCE] = { cmd_read_dma, HD_CFA_OK },
1714 [WIN_WRITEDMA] = { cmd_write_dma, HD_CFA_OK },
1715 [WIN_WRITEDMA_ONCE] = { cmd_write_dma, HD_CFA_OK },
adf3a2c4 1716 [CFA_WRITE_MULTI_WO_ERASE] = { cmd_write_multiple, CFA_OK },
b300337e
KW		 1717 [WIN_STANDBYNOW1] = { cmd_nop, ALL_OK },
1718 [WIN_IDLEIMMEDIATE] = { cmd_nop, ALL_OK },
1719 [WIN_STANDBY] = { cmd_nop, ALL_OK },
1720 [WIN_SETIDLE1] = { cmd_nop, ALL_OK },
785f6320 1721 [WIN_CHECKPOWERMODE1] = { cmd_check_power_mode, ALL_OK | SET_DSC },
b300337e 1722 [WIN_SLEEPNOW1] = { cmd_nop, ALL_OK },
9afce429
KW		 1723 [WIN_FLUSH_CACHE] = { cmd_flush_cache, ALL_OK },
1724 [WIN_FLUSH_CACHE_EXT] = { cmd_flush_cache, HD_CFA_OK },
1c66869a 1725 [WIN_IDENTIFY] = { cmd_identify, ALL_OK },
ee03398c 1726 [WIN_SETFEATURES] = { cmd_set_features, ALL_OK | SET_DSC },
6b1dd744
KW		 1727 [IBM_SENSE_CONDITION] = { cmd_ibm_sense_condition, CFA_OK | SET_DSC },
1728 [CFA_WEAR_LEVEL] = { cmd_cfa_erase_sectors, HD_CFA_OK | SET_DSC },
63a82e6a 1729 [WIN_READ_NATIVE_MAX] = { cmd_read_native_max, ALL_OK | SET_DSC },
844505b1
MA		 1730};
1731
1732static bool ide_cmd_permitted(IDEState *s, uint32_t cmd)
1733{
1734 return cmd < ARRAY_SIZE(ide_cmd_table)
a0436e92 1735 && (ide_cmd_table[cmd].flags & (1u << s->drive_kind));
844505b1 1736}
7cff87ff
AG		 1737
1738void ide_exec_cmd(IDEBus *bus, uint32_t val)
1739{
1740 IDEState *s;
dfe1ea8f 1741 bool complete;
7cff87ff 1742
5391d806 1743#if defined(DEBUG_IDE)
6ef2ba5e 1744 printf("ide: CMD=%02x\n", val);
5391d806 1745#endif
6ef2ba5e 1746 s = idebus_active_if(bus);
66a0a2cb 1747 /* ignore commands to non existent slave */
6ef2ba5e
AG		 1748 if (s != bus->ifs && !s->bs)
1749 return;
c2ff060f 1750
6ef2ba5e
AG		 1751 /* Only DEVICE RESET is allowed while BSY or/and DRQ are set */
1752 if ((s->status & (BUSY_STAT|DRQ_STAT)) && val != WIN_DEVICE_RESET)
1753 return;
fcdd25ab 1754
844505b1 1755 if (!ide_cmd_permitted(s, val)) {
dfe1ea8f
KW		 1756 ide_abort_command(s);
1757 ide_set_irq(s->bus);
1758 return;
844505b1
MA		 1759 }
1760
dfe1ea8f
KW		 1761 s->status = READY_STAT | BUSY_STAT;
1762 s->error = 0;
a0436e92 1763
dfe1ea8f
KW		 1764 complete = ide_cmd_table[val].handler(s, val);
1765 if (complete) {
1766 s->status &= ~BUSY_STAT;
1767 assert(!!s->error == !!(s->status & ERR_STAT));
a0436e92 1768
dfe1ea8f
KW		 1769 if ((ide_cmd_table[val].flags & SET_DSC) && !s->error) {
1770 s->status |= SEEK_STAT;
a0436e92
KW		 1771 }
1772
6ef2ba5e 1773 ide_set_irq(s->bus);
6ef2ba5e 1774 }
5391d806
FB		 1775}
1776
356721ae 1777uint32_t ide_ioport_read(void *opaque, uint32_t addr1)
5391d806 1778{
bcbdc4d3
GH		 1779 IDEBus *bus = opaque;
1780 IDEState *s = idebus_active_if(bus);
5391d806 1781 uint32_t addr;
c2ff060f 1782 int ret, hob;
5391d806
FB		 1783
1784 addr = addr1 & 7;
c2ff060f
FB		 1785 /* FIXME: HOB readback uses bit 7, but it's always set right now */
1786 //hob = s->select & (1 << 7);
1787 hob = 0;
5391d806
FB		 1788 switch(addr) {
1789 case 0:
1790 ret = 0xff;
1791 break;
1792 case 1:
bcbdc4d3
GH		 1793 if ((!bus->ifs[0].bs && !bus->ifs[1].bs) ||
1794 (s != bus->ifs && !s->bs))
c45c3d00 1795 ret = 0;
c2ff060f 1796 else if (!hob)
c45c3d00 1797 ret = s->error;
c2ff060f
FB		 1798 else
1799 ret = s->hob_feature;
5391d806
FB		 1800 break;
1801 case 2:
bcbdc4d3 1802 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
c45c3d00 1803 ret = 0;
c2ff060f 1804 else if (!hob)
c45c3d00 1805 ret = s->nsector & 0xff;
c2ff060f
FB		 1806 else
1807 ret = s->hob_nsector;
5391d806
FB		 1808 break;
1809 case 3:
bcbdc4d3 1810 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
c45c3d00 1811 ret = 0;
c2ff060f 1812 else if (!hob)
c45c3d00 1813 ret = s->sector;
c2ff060f
FB		 1814 else
1815 ret = s->hob_sector;
5391d806
FB		 1816 break;
1817 case 4:
bcbdc4d3 1818 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
c45c3d00 1819 ret = 0;
c2ff060f 1820 else if (!hob)
c45c3d00 1821 ret = s->lcyl;
c2ff060f
FB		 1822 else
1823 ret = s->hob_lcyl;
5391d806
FB		 1824 break;
1825 case 5:
bcbdc4d3 1826 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
c45c3d00 1827 ret = 0;
c2ff060f 1828 else if (!hob)
c45c3d00 1829 ret = s->hcyl;
c2ff060f
FB		 1830 else
1831 ret = s->hob_hcyl;
5391d806
FB		 1832 break;
1833 case 6:
bcbdc4d3 1834 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
c45c3d00
FB		 1835 ret = 0;
1836 else
7ae98627 1837 ret = s->select;
5391d806
FB		 1838 break;
1839 default:
1840 case 7:
bcbdc4d3
GH		 1841 if ((!bus->ifs[0].bs && !bus->ifs[1].bs) ||
1842 (s != bus->ifs && !s->bs))
c45c3d00
FB		 1843 ret = 0;
1844 else
1845 ret = s->status;
9cdd03a7 1846 qemu_irq_lower(bus->irq);
5391d806
FB		 1847 break;
1848 }
1849#ifdef DEBUG_IDE
1850 printf("ide: read addr=0x%x val=%02x\n", addr1, ret);
1851#endif
1852 return ret;
1853}
1854
356721ae 1855uint32_t ide_status_read(void *opaque, uint32_t addr)
5391d806 1856{
bcbdc4d3
GH		 1857 IDEBus *bus = opaque;
1858 IDEState *s = idebus_active_if(bus);
5391d806 1859 int ret;
7ae98627 1860
bcbdc4d3
GH		 1861 if ((!bus->ifs[0].bs && !bus->ifs[1].bs) ||
1862 (s != bus->ifs && !s->bs))
7ae98627
FB		 1863 ret = 0;
1864 else
1865 ret = s->status;
5391d806
FB		 1866#ifdef DEBUG_IDE
1867 printf("ide: read status addr=0x%x val=%02x\n", addr, ret);
1868#endif
1869 return ret;
1870}
1871
356721ae 1872void ide_cmd_write(void *opaque, uint32_t addr, uint32_t val)
5391d806 1873{
bcbdc4d3 1874 IDEBus *bus = opaque;
5391d806
FB		 1875 IDEState *s;
1876 int i;
1877
1878#ifdef DEBUG_IDE
1879 printf("ide: write control addr=0x%x val=%02x\n", addr, val);
1880#endif
1881 /* common for both drives */
9cdd03a7 1882 if (!(bus->cmd & IDE_CMD_RESET) &&
5391d806
FB		 1883 (val & IDE_CMD_RESET)) {
1884 /* reset low to high */
1885 for(i = 0;i < 2; i++) {
bcbdc4d3 1886 s = &bus->ifs[i];
5391d806
FB		 1887 s->status = BUSY_STAT | SEEK_STAT;
1888 s->error = 0x01;
1889 }
9cdd03a7 1890 } else if ((bus->cmd & IDE_CMD_RESET) &&
5391d806
FB		 1891 !(val & IDE_CMD_RESET)) {
1892 /* high to low */
1893 for(i = 0;i < 2; i++) {
bcbdc4d3 1894 s = &bus->ifs[i];
cd8722bb 1895 if (s->drive_kind == IDE_CD)
6b136f9e
FB		 1896 s->status = 0x00; /* NOTE: READY is _not_ set */
1897 else
56bf1d37 1898 s->status = READY_STAT | SEEK_STAT;
5391d806
FB		 1899 ide_set_signature(s);
1900 }
1901 }
1902
9cdd03a7 1903 bus->cmd = val;
5391d806
FB		 1904}
1905
40c4ed3f
KW		 1906/*
1907 * Returns true if the running PIO transfer is a PIO out (i.e. data is
1908 * transferred from the device to the guest), false if it's a PIO in
1909 */
1910static bool ide_is_pio_out(IDEState *s)
1911{
1912 if (s->end_transfer_func == ide_sector_write ||
1913 s->end_transfer_func == ide_atapi_cmd) {
1914 return false;
1915 } else if (s->end_transfer_func == ide_sector_read ||
1916 s->end_transfer_func == ide_transfer_stop ||
1917 s->end_transfer_func == ide_atapi_cmd_reply_end ||
1918 s->end_transfer_func == ide_dummy_transfer_stop) {
1919 return true;
1920 }
1921
1922 abort();
1923}
1924
356721ae 1925void ide_data_writew(void *opaque, uint32_t addr, uint32_t val)
5391d806 1926{
bcbdc4d3
GH		 1927 IDEBus *bus = opaque;
1928 IDEState *s = idebus_active_if(bus);
5391d806
FB		 1929 uint8_t *p;
1930
40c4ed3f
KW		 1931 /* PIO data access allowed only when DRQ bit is set. The result of a write
1932 * during PIO out is indeterminate, just ignore it. */
1933 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
fcdd25ab 1934 return;
40c4ed3f 1935 }
fcdd25ab 1936
5391d806 1937 p = s->data_ptr;
0c4ad8dc 1938 *(uint16_t *)p = le16_to_cpu(val);
5391d806
FB		 1939 p += 2;
1940 s->data_ptr = p;
1941 if (p >= s->data_end)
1942 s->end_transfer_func(s);
1943}
1944
356721ae 1945uint32_t ide_data_readw(void *opaque, uint32_t addr)
5391d806 1946{
bcbdc4d3
GH		 1947 IDEBus *bus = opaque;
1948 IDEState *s = idebus_active_if(bus);
5391d806
FB		 1949 uint8_t *p;
1950 int ret;
fcdd25ab 1951
40c4ed3f
KW		 1952 /* PIO data access allowed only when DRQ bit is set. The result of a read
1953 * during PIO in is indeterminate, return 0 and don't move forward. */
1954 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
fcdd25ab 1955 return 0;
40c4ed3f 1956 }
fcdd25ab 1957
5391d806 1958 p = s->data_ptr;
0c4ad8dc 1959 ret = cpu_to_le16(*(uint16_t *)p);
5391d806
FB		 1960 p += 2;
1961 s->data_ptr = p;
1962 if (p >= s->data_end)
1963 s->end_transfer_func(s);
1964 return ret;
1965}
1966
356721ae 1967void ide_data_writel(void *opaque, uint32_t addr, uint32_t val)
5391d806 1968{
bcbdc4d3
GH		 1969 IDEBus *bus = opaque;
1970 IDEState *s = idebus_active_if(bus);
5391d806
FB		 1971 uint8_t *p;
1972
40c4ed3f
KW		 1973 /* PIO data access allowed only when DRQ bit is set. The result of a write
1974 * during PIO out is indeterminate, just ignore it. */
1975 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
fcdd25ab 1976 return;
40c4ed3f 1977 }
fcdd25ab 1978
5391d806 1979 p = s->data_ptr;
0c4ad8dc 1980 *(uint32_t *)p = le32_to_cpu(val);
5391d806
FB		 1981 p += 4;
1982 s->data_ptr = p;
1983 if (p >= s->data_end)
1984 s->end_transfer_func(s);
1985}
1986
356721ae 1987uint32_t ide_data_readl(void *opaque, uint32_t addr)
5391d806 1988{
bcbdc4d3
GH		 1989 IDEBus *bus = opaque;
1990 IDEState *s = idebus_active_if(bus);
5391d806
FB		 1991 uint8_t *p;
1992 int ret;
3b46e624 1993
40c4ed3f
KW		 1994 /* PIO data access allowed only when DRQ bit is set. The result of a read
1995 * during PIO in is indeterminate, return 0 and don't move forward. */
1996 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
fcdd25ab 1997 return 0;
40c4ed3f 1998 }
fcdd25ab 1999
5391d806 2000 p = s->data_ptr;
0c4ad8dc 2001 ret = cpu_to_le32(*(uint32_t *)p);
5391d806
FB		 2002 p += 4;
2003 s->data_ptr = p;
2004 if (p >= s->data_end)
2005 s->end_transfer_func(s);
2006 return ret;
2007}
2008
a7dfe172
FB		 2009static void ide_dummy_transfer_stop(IDEState *s)
2010{
2011 s->data_ptr = s->io_buffer;
2012 s->data_end = s->io_buffer;
2013 s->io_buffer[0] = 0xff;
2014 s->io_buffer[1] = 0xff;
2015 s->io_buffer[2] = 0xff;
2016 s->io_buffer[3] = 0xff;
2017}
2018
4a643563 2019static void ide_reset(IDEState *s)
5391d806 2020{
4a643563
BS		 2021#ifdef DEBUG_IDE
2022 printf("ide: reset\n");
2023#endif
bef0fd59
SH		 2024
2025 if (s->pio_aiocb) {
2026 bdrv_aio_cancel(s->pio_aiocb);
2027 s->pio_aiocb = NULL;
2028 }
2029
cd8722bb 2030 if (s->drive_kind == IDE_CFATA)
201a51fc
AZ		 2031 s->mult_sectors = 0;
2032 else
2033 s->mult_sectors = MAX_MULT_SECTORS;
4a643563
BS		 2034 /* ide regs */
2035 s->feature = 0;
2036 s->error = 0;
2037 s->nsector = 0;
2038 s->sector = 0;
2039 s->lcyl = 0;
2040 s->hcyl = 0;
2041
2042 /* lba48 */
2043 s->hob_feature = 0;
2044 s->hob_sector = 0;
2045 s->hob_nsector = 0;
2046 s->hob_lcyl = 0;
2047 s->hob_hcyl = 0;
2048
5391d806 2049 s->select = 0xa0;
41a2b959 2050 s->status = READY_STAT | SEEK_STAT;
4a643563
BS		 2051
2052 s->lba48 = 0;
2053
2054 /* ATAPI specific */
2055 s->sense_key = 0;
2056 s->asc = 0;
2057 s->cdrom_changed = 0;
2058 s->packet_transfer_size = 0;
2059 s->elementary_transfer_size = 0;
2060 s->io_buffer_index = 0;
2061 s->cd_sector_size = 0;
2062 s->atapi_dma = 0;
a7f3d65b
PH		 2063 s->tray_locked = 0;
2064 s->tray_open = 0;
4a643563
BS		 2065 /* ATA DMA state */
2066 s->io_buffer_size = 0;
2067 s->req_nb_sectors = 0;
2068
5391d806 2069 ide_set_signature(s);
a7dfe172
FB		 2070 /* init the transfer handler so that 0xffff is returned on data
2071 accesses */
2072 s->end_transfer_func = ide_dummy_transfer_stop;
2073 ide_dummy_transfer_stop(s);
201a51fc 2074 s->media_changed = 0;
5391d806
FB		 2075}
2076
4a643563
BS		 2077void ide_bus_reset(IDEBus *bus)
2078{
2079 bus->unit = 0;
2080 bus->cmd = 0;
2081 ide_reset(&bus->ifs[0]);
2082 ide_reset(&bus->ifs[1]);
2083 ide_clear_hob(bus);
40a6238a
AG		 2084
2085 /* pending async DMA */
2086 if (bus->dma->aiocb) {
2087#ifdef DEBUG_AIO
2088 printf("aio_cancel\n");
2089#endif
2090 bdrv_aio_cancel(bus->dma->aiocb);
2091 bus->dma->aiocb = NULL;
2092 }
2093
2094 /* reset dma provider too */
1374bec0
PB		 2095 if (bus->dma->ops->reset) {
2096 bus->dma->ops->reset(bus->dma);
2097 }
4a643563
BS		 2098}
2099
e4def80b
MA		 2100static bool ide_cd_is_tray_open(void *opaque)
2101{
2102 return ((IDEState *)opaque)->tray_open;
2103}
2104
f107639a
MA		 2105static bool ide_cd_is_medium_locked(void *opaque)
2106{
2107 return ((IDEState *)opaque)->tray_locked;
2108}
2109
0e49de52 2110static const BlockDevOps ide_cd_block_ops = {
145feb17 2111 .change_media_cb = ide_cd_change_cb,
2df0a3a3 2112 .eject_request_cb = ide_cd_eject_request_cb,
e4def80b 2113 .is_tray_open = ide_cd_is_tray_open,
f107639a 2114 .is_medium_locked = ide_cd_is_medium_locked,
0e49de52
MA		 2115};
2116
1f56e32a 2117int ide_init_drive(IDEState *s, BlockDriverState *bs, IDEDriveKind kind,
95ebda85 2118 const char *version, const char *serial, const char *model,
ba801960
MA		 2119 uint64_t wwn,
2120 uint32_t cylinders, uint32_t heads, uint32_t secs,
2121 int chs_trans)
88804180 2122{
88804180
GH		 2123 uint64_t nb_sectors;
2124
f8b6cc00 2125 s->bs = bs;
1f56e32a
MA		 2126 s->drive_kind = kind;
2127
f8b6cc00 2128 bdrv_get_geometry(bs, &nb_sectors);
870111c8
MA		 2129 s->cylinders = cylinders;
2130 s->heads = heads;
2131 s->sectors = secs;
ba801960 2132 s->chs_trans = chs_trans;
870111c8 2133 s->nb_sectors = nb_sectors;
95ebda85 2134 s->wwn = wwn;
870111c8
MA		 2135 /* The SMART values should be preserved across power cycles
2136 but they aren't. */
2137 s->smart_enabled = 1;
2138 s->smart_autosave = 1;
2139 s->smart_errors = 0;
2140 s->smart_selftest_count = 0;
1f56e32a 2141 if (kind == IDE_CD) {
0e49de52 2142 bdrv_set_dev_ops(bs, &ide_cd_block_ops, s);
1b7fd729 2143 bdrv_set_guest_block_size(bs, 2048);
7aa9c811 2144 } else {
98f28ad7
MA		 2145 if (!bdrv_is_inserted(s->bs)) {
2146 error_report("Device needs media, but drive is empty");
2147 return -1;
2148 }
7aa9c811
MA		 2149 if (bdrv_is_read_only(bs)) {
2150 error_report("Can't use a read-only drive");
2151 return -1;
2152 }
88804180 2153 }
f8b6cc00 2154 if (serial) {
aa2c91bd 2155 pstrcpy(s->drive_serial_str, sizeof(s->drive_serial_str), serial);
6ced55a5 2156 } else {
88804180
GH		 2157 snprintf(s->drive_serial_str, sizeof(s->drive_serial_str),
2158 "QM%05d", s->drive_serial);
870111c8 2159 }
27e0c9a1
FB		 2160 if (model) {
2161 pstrcpy(s->drive_model_str, sizeof(s->drive_model_str), model);
2162 } else {
2163 switch (kind) {
2164 case IDE_CD:
2165 strcpy(s->drive_model_str, "QEMU DVD-ROM");
2166 break;
2167 case IDE_CFATA:
2168 strcpy(s->drive_model_str, "QEMU MICRODRIVE");
2169 break;
2170 default:
2171 strcpy(s->drive_model_str, "QEMU HARDDISK");
2172 break;
2173 }
2174 }
2175
47c06340
GH		 2176 if (version) {
2177 pstrcpy(s->version, sizeof(s->version), version);
2178 } else {
93bfef4c 2179 pstrcpy(s->version, sizeof(s->version), qemu_get_version());
47c06340 2180 }
40a6238a 2181
88804180 2182 ide_reset(s);
50fb1900 2183 bdrv_iostatus_enable(bs);
c4d74df7 2184 return 0;
88804180
GH		 2185}
2186
57234ee4 2187static void ide_init1(IDEBus *bus, int unit)
d459da0e
MA		 2188{
2189 static int drive_serial = 1;
2190 IDEState *s = &bus->ifs[unit];
2191
2192 s->bus = bus;
2193 s->unit = unit;
2194 s->drive_serial = drive_serial++;
1b2adf28 2195 /* we need at least 2k alignment for accessing CDROMs using O_DIRECT */
50641c5c 2196 s->io_buffer_total_len = IDE_DMA_BUF_SECTORS*512 + 4;
c925400b
KW		 2197 s->io_buffer = qemu_memalign(2048, s->io_buffer_total_len);
2198 memset(s->io_buffer, 0, s->io_buffer_total_len);
2199
d459da0e 2200 s->smart_selftest_data = qemu_blockalign(s->bs, 512);
c925400b
KW		 2201 memset(s->smart_selftest_data, 0, 512);
2202
bc72ad67 2203 s->sector_write_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
d459da0e 2204 ide_sector_write_timer_cb, s);
57234ee4
MA		 2205}
2206
40a6238a
AG		 2207static void ide_nop_start(IDEDMA *dma, IDEState *s,
2208 BlockDriverCompletionFunc *cb)
2209{
2210}
2211
40a6238a
AG		 2212static int ide_nop_int(IDEDMA *dma, int x)
2213{
2214 return 0;
2215}
2216
1dfb4dd9 2217static void ide_nop_restart(void *opaque, int x, RunState y)
40a6238a
AG		 2218{
2219}
2220
2221static const IDEDMAOps ide_dma_nop_ops = {
2222 .start_dma = ide_nop_start,
40a6238a
AG		 2223 .prepare_buf = ide_nop_int,
2224 .rw_buf = ide_nop_int,
2225 .set_unit = ide_nop_int,
2226 .add_status = ide_nop_int,
40a6238a 2227 .restart_cb = ide_nop_restart,
40a6238a
AG		 2228};
2229
2230static IDEDMA ide_dma_nop = {
2231 .ops = &ide_dma_nop_ops,
2232 .aiocb = NULL,
2233};
2234
57234ee4
MA		 2235void ide_init2(IDEBus *bus, qemu_irq irq)
2236{
2237 int i;
2238
2239 for(i = 0; i < 2; i++) {
2240 ide_init1(bus, i);
2241 ide_reset(&bus->ifs[i]);
870111c8 2242 }
57234ee4 2243 bus->irq = irq;
40a6238a 2244 bus->dma = &ide_dma_nop;
d459da0e
MA		 2245}
2246
4a91d3b3
RH		 2247static const MemoryRegionPortio ide_portio_list[] = {
2248 { 0, 8, 1, .read = ide_ioport_read, .write = ide_ioport_write },
2249 { 0, 2, 2, .read = ide_data_readw, .write = ide_data_writew },
2250 { 0, 4, 4, .read = ide_data_readl, .write = ide_data_writel },
2251 PORTIO_END_OF_LIST(),
2252};
2253
2254static const MemoryRegionPortio ide_portio2_list[] = {
2255 { 0, 1, 1, .read = ide_status_read, .write = ide_cmd_write },
2256 PORTIO_END_OF_LIST(),
2257};
2258
2259void ide_init_ioport(IDEBus *bus, ISADevice *dev, int iobase, int iobase2)
69b91039 2260{
4a91d3b3
RH		 2261 /* ??? Assume only ISA and PCI configurations, and that the PCI-ISA
2262 bridge has been setup properly to always register with ISA. */
2263 isa_register_portio_list(dev, iobase, ide_portio_list, bus, "ide");
2264
caed8802 2265 if (iobase2) {
4a91d3b3 2266 isa_register_portio_list(dev, iobase2, ide_portio2_list, bus, "ide");
5391d806 2267 }
5391d806 2268}
69b91039 2269
37159f13 2270static bool is_identify_set(void *opaque, int version_id)
aa941b94 2271{
37159f13
JQ		 2272 IDEState *s = opaque;
2273
2274 return s->identify_set != 0;
2275}
2276
50641c5c
JQ		 2277static EndTransferFunc* transfer_end_table[] = {
2278 ide_sector_read,
2279 ide_sector_write,
2280 ide_transfer_stop,
2281 ide_atapi_cmd_reply_end,
2282 ide_atapi_cmd,
2283 ide_dummy_transfer_stop,
2284};
2285
2286static int transfer_end_table_idx(EndTransferFunc *fn)
2287{
2288 int i;
2289
2290 for (i = 0; i < ARRAY_SIZE(transfer_end_table); i++)
2291 if (transfer_end_table[i] == fn)
2292 return i;
2293
2294 return -1;
2295}
2296
37159f13 2297static int ide_drive_post_load(void *opaque, int version_id)
aa941b94 2298{
37159f13
JQ		 2299 IDEState *s = opaque;
2300
7cdd481c
PB		 2301 if (s->identify_set) {
2302 bdrv_set_enable_write_cache(s->bs, !!(s->identify_data[85] & (1 << 5)));
2303 }
37159f13 2304 return 0;
aa941b94
AZ		 2305}
2306
50641c5c
JQ		 2307static int ide_drive_pio_post_load(void *opaque, int version_id)
2308{
2309 IDEState *s = opaque;
2310
fb60105d 2311 if (s->end_transfer_fn_idx >= ARRAY_SIZE(transfer_end_table)) {
50641c5c
JQ		 2312 return -EINVAL;
2313 }
2314 s->end_transfer_func = transfer_end_table[s->end_transfer_fn_idx];
2315 s->data_ptr = s->io_buffer + s->cur_io_buffer_offset;
2316 s->data_end = s->data_ptr + s->cur_io_buffer_len;
2317
2318 return 0;
2319}
2320
2321static void ide_drive_pio_pre_save(void *opaque)
2322{
2323 IDEState *s = opaque;
2324 int idx;
2325
2326 s->cur_io_buffer_offset = s->data_ptr - s->io_buffer;
2327 s->cur_io_buffer_len = s->data_end - s->data_ptr;
2328
2329 idx = transfer_end_table_idx(s->end_transfer_func);
2330 if (idx == -1) {
2331 fprintf(stderr, "%s: invalid end_transfer_func for DRQ_STAT\n",
2332 __func__);
2333 s->end_transfer_fn_idx = 2;
2334 } else {
2335 s->end_transfer_fn_idx = idx;
2336 }
2337}
2338
2339static bool ide_drive_pio_state_needed(void *opaque)
2340{
2341 IDEState *s = opaque;
2342
fdc650d7
KW		 2343 return ((s->status & DRQ_STAT) != 0)
2344 || (s->bus->error_status & BM_STATUS_PIO_RETRY);
50641c5c
JQ		 2345}
2346
db118fe7
MA		 2347static bool ide_tray_state_needed(void *opaque)
2348{
2349 IDEState *s = opaque;
2350
2351 return s->tray_open || s->tray_locked;
2352}
2353
996faf1a
AS		 2354static bool ide_atapi_gesn_needed(void *opaque)
2355{
2356 IDEState *s = opaque;
2357
2358 return s->events.new_media || s->events.eject_request;
2359}
2360
def93791
KW		 2361static bool ide_error_needed(void *opaque)
2362{
2363 IDEBus *bus = opaque;
2364
2365 return (bus->error_status != 0);
2366}
2367
996faf1a 2368/* Fields for GET_EVENT_STATUS_NOTIFICATION ATAPI command */
656fbeff 2369static const VMStateDescription vmstate_ide_atapi_gesn_state = {
996faf1a
AS		 2370 .name ="ide_drive/atapi/gesn_state",
2371 .version_id = 1,
2372 .minimum_version_id = 1,
35d08458 2373 .fields = (VMStateField[]) {
996faf1a
AS		 2374 VMSTATE_BOOL(events.new_media, IDEState),
2375 VMSTATE_BOOL(events.eject_request, IDEState),
0754f9ec 2376 VMSTATE_END_OF_LIST()
996faf1a
AS		 2377 }
2378};
2379
db118fe7
MA		 2380static const VMStateDescription vmstate_ide_tray_state = {
2381 .name = "ide_drive/tray_state",
2382 .version_id = 1,
2383 .minimum_version_id = 1,
db118fe7
MA		 2384 .fields = (VMStateField[]) {
2385 VMSTATE_BOOL(tray_open, IDEState),
2386 VMSTATE_BOOL(tray_locked, IDEState),
2387 VMSTATE_END_OF_LIST()
2388 }
2389};
2390
656fbeff 2391static const VMStateDescription vmstate_ide_drive_pio_state = {
50641c5c
JQ		 2392 .name = "ide_drive/pio_state",
2393 .version_id = 1,
2394 .minimum_version_id = 1,
50641c5c
JQ		 2395 .pre_save = ide_drive_pio_pre_save,
2396 .post_load = ide_drive_pio_post_load,
35d08458 2397 .fields = (VMStateField[]) {
50641c5c
JQ		 2398 VMSTATE_INT32(req_nb_sectors, IDEState),
2399 VMSTATE_VARRAY_INT32(io_buffer, IDEState, io_buffer_total_len, 1,
2400 vmstate_info_uint8, uint8_t),
2401 VMSTATE_INT32(cur_io_buffer_offset, IDEState),
2402 VMSTATE_INT32(cur_io_buffer_len, IDEState),
2403 VMSTATE_UINT8(end_transfer_fn_idx, IDEState),
2404 VMSTATE_INT32(elementary_transfer_size, IDEState),
2405 VMSTATE_INT32(packet_transfer_size, IDEState),
2406 VMSTATE_END_OF_LIST()
2407 }
2408};
2409
37159f13
JQ		 2410const VMStateDescription vmstate_ide_drive = {
2411 .name = "ide_drive",
3abb6260 2412 .version_id = 3,
37159f13 2413 .minimum_version_id = 0,
37159f13 2414 .post_load = ide_drive_post_load,
35d08458 2415 .fields = (VMStateField[]) {
37159f13
JQ		 2416 VMSTATE_INT32(mult_sectors, IDEState),
2417 VMSTATE_INT32(identify_set, IDEState),
2418 VMSTATE_BUFFER_TEST(identify_data, IDEState, is_identify_set),
2419 VMSTATE_UINT8(feature, IDEState),
2420 VMSTATE_UINT8(error, IDEState),
2421 VMSTATE_UINT32(nsector, IDEState),
2422 VMSTATE_UINT8(sector, IDEState),
2423 VMSTATE_UINT8(lcyl, IDEState),
2424 VMSTATE_UINT8(hcyl, IDEState),
2425 VMSTATE_UINT8(hob_feature, IDEState),
2426 VMSTATE_UINT8(hob_sector, IDEState),
2427 VMSTATE_UINT8(hob_nsector, IDEState),
2428 VMSTATE_UINT8(hob_lcyl, IDEState),
2429 VMSTATE_UINT8(hob_hcyl, IDEState),
2430 VMSTATE_UINT8(select, IDEState),
2431 VMSTATE_UINT8(status, IDEState),
2432 VMSTATE_UINT8(lba48, IDEState),
2433 VMSTATE_UINT8(sense_key, IDEState),
2434 VMSTATE_UINT8(asc, IDEState),
2435 VMSTATE_UINT8_V(cdrom_changed, IDEState, 3),
37159f13 2436 VMSTATE_END_OF_LIST()
50641c5c
JQ		 2437 },
2438 .subsections = (VMStateSubsection []) {
2439 {
2440 .vmsd = &vmstate_ide_drive_pio_state,
2441 .needed = ide_drive_pio_state_needed,
db118fe7
MA		 2442 }, {
2443 .vmsd = &vmstate_ide_tray_state,
2444 .needed = ide_tray_state_needed,
996faf1a
AS		 2445 }, {
2446 .vmsd = &vmstate_ide_atapi_gesn_state,
2447 .needed = ide_atapi_gesn_needed,
50641c5c
JQ		 2448 }, {
2449 /* empty */
2450 }
37159f13
JQ		 2451 }
2452};
2453
656fbeff 2454static const VMStateDescription vmstate_ide_error_status = {
def93791
KW		 2455 .name ="ide_bus/error",
2456 .version_id = 1,
2457 .minimum_version_id = 1,
35d08458 2458 .fields = (VMStateField[]) {
def93791
KW		 2459 VMSTATE_INT32(error_status, IDEBus),
2460 VMSTATE_END_OF_LIST()
2461 }
2462};
2463
6521dc62
JQ		 2464const VMStateDescription vmstate_ide_bus = {
2465 .name = "ide_bus",
2466 .version_id = 1,
2467 .minimum_version_id = 1,
35d08458 2468 .fields = (VMStateField[]) {
6521dc62
JQ		 2469 VMSTATE_UINT8(cmd, IDEBus),
2470 VMSTATE_UINT8(unit, IDEBus),
2471 VMSTATE_END_OF_LIST()
def93791
KW		 2472 },
2473 .subsections = (VMStateSubsection []) {
2474 {
2475 .vmsd = &vmstate_ide_error_status,
2476 .needed = ide_error_needed,
2477 }, {
2478 /* empty */
2479 }
6521dc62
JQ		 2480 }
2481};
75717903
IY		 2482
2483void ide_drive_get(DriveInfo **hd, int max_bus)
2484{
2485 int i;
2486
2487 if (drive_get_max_bus(IF_IDE) >= max_bus) {
2488 fprintf(stderr, "qemu: too many IDE bus: %d\n", max_bus);
2489 exit(1);
2490 }
2491
2492 for(i = 0; i < max_bus * MAX_IDE_DEVS; i++) {
2493 hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
2494 }
2495}
Empty description
This page took 1.19323 seconds and 4 git commands to generate.