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ide: restart atapi dma by re-evaluating command packet
[qemu.git] / hw / ide / core.c
CommitLineData
5391d806 1/*
38cdea7c 2 * QEMU IDE disk and CD/DVD-ROM Emulator
5fafdf24 3 *
5391d806 4 * Copyright (c) 2003 Fabrice Bellard
201a51fc 5 * Copyright (c) 2006 Openedhand Ltd.
5fafdf24 6 *
5391d806
FB		 7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
53239262 25#include "qemu/osdep.h"
59f2a787 26#include <hw/hw.h>
0d09e41a 27#include <hw/i386/pc.h>
a2cb15b0 28#include <hw/pci/pci.h>
0d09e41a 29#include <hw/isa/isa.h>
1de7afc9
PB		 30#include "qemu/error-report.h"
31#include "qemu/timer.h"
9c17d615
PB		 32#include "sysemu/sysemu.h"
33#include "sysemu/dma.h"
0d09e41a 34#include "hw/block/block.h"
4be74634 35#include "sysemu/block-backend.h"
f348b6d1 36#include "qemu/cutils.h"
59f2a787
GH		 37
38#include <hw/ide/internal.h>
e8b54394 39
b93af93d
BW		 40/* These values were based on a Seagate ST3500418AS but have been modified
41 to make more sense in QEMU */
42static const int smart_attributes[][12] = {
43 /* id, flags, hflags, val, wrst, raw (6 bytes), threshold */
44 /* raw read error rate*/
45 { 0x01, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06},
46 /* spin up */
47 { 0x03, 0x03, 0x00, 0x64, 0x64, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
48 /* start stop count */
49 { 0x04, 0x02, 0x00, 0x64, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14},
50 /* remapped sectors */
51 { 0x05, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x24},
52 /* power on hours */
53 { 0x09, 0x03, 0x00, 0x64, 0x64, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
54 /* power cycle count */
55 { 0x0c, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
56 /* airflow-temperature-celsius */
57 { 190, 0x03, 0x00, 0x45, 0x45, 0x1f, 0x00, 0x1f, 0x1f, 0x00, 0x00, 0x32},
e8b54394
BW		 58};
59
ce4b6522 60static int ide_handle_rw_error(IDEState *s, int error, int op);
40c4ed3f 61static void ide_dummy_transfer_stop(IDEState *s);
98087450 62
5391d806
FB		 63static void padstr(char *str, const char *src, int len)
64{
65 int i, v;
66 for(i = 0; i < len; i++) {
67 if (*src)
68 v = *src++;
69 else
70 v = ' ';
69b34976 71 str[i^1] = v;
5391d806
FB		 72 }
73}
74
67b915a5
FB		 75static void put_le16(uint16_t *p, unsigned int v)
76{
0c4ad8dc 77 *p = cpu_to_le16(v);
67b915a5
FB		 78}
79
01ce352e
JS		 80static void ide_identify_size(IDEState *s)
81{
82 uint16_t *p = (uint16_t *)s->identify_data;
83 put_le16(p + 60, s->nb_sectors);
84 put_le16(p + 61, s->nb_sectors >> 16);
85 put_le16(p + 100, s->nb_sectors);
86 put_le16(p + 101, s->nb_sectors >> 16);
87 put_le16(p + 102, s->nb_sectors >> 32);
88 put_le16(p + 103, s->nb_sectors >> 48);
89}
90
5391d806
FB		 91static void ide_identify(IDEState *s)
92{
93 uint16_t *p;
94 unsigned int oldsize;
d353fb72 95 IDEDevice *dev = s->unit ? s->bus->slave : s->bus->master;
5391d806 96
4bf6637d 97 p = (uint16_t *)s->identify_data;
94458802 98 if (s->identify_set) {
4bf6637d 99 goto fill_buffer;
94458802 100 }
4bf6637d 101 memset(p, 0, sizeof(s->identify_data));
94458802 102
67b915a5 103 put_le16(p + 0, 0x0040);
5fafdf24 104 put_le16(p + 1, s->cylinders);
67b915a5
FB		 105 put_le16(p + 3, s->heads);
106 put_le16(p + 4, 512 * s->sectors); /* XXX: retired, remove ? */
107 put_le16(p + 5, 512); /* XXX: retired, remove ? */
5fafdf24 108 put_le16(p + 6, s->sectors);
fa879c64 109 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
67b915a5
FB		 110 put_le16(p + 20, 3); /* XXX: retired, remove ? */
111 put_le16(p + 21, 512); /* cache size in sectors */
112 put_le16(p + 22, 4); /* ecc bytes */
47c06340 113 padstr((char *)(p + 23), s->version, 8); /* firmware version */
27e0c9a1 114 padstr((char *)(p + 27), s->drive_model_str, 40); /* model */
3b46e624 115#if MAX_MULT_SECTORS > 1
67b915a5 116 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
5391d806 117#endif
67b915a5 118 put_le16(p + 48, 1); /* dword I/O */
94458802 119 put_le16(p + 49, (1 << 11) | (1 << 9) | (1 << 8)); /* DMA and LBA supported */
67b915a5
FB		 120 put_le16(p + 51, 0x200); /* PIO transfer cycle */
121 put_le16(p + 52, 0x200); /* DMA transfer cycle */
94458802 122 put_le16(p + 53, 1 | (1 << 1) | (1 << 2)); /* words 54-58,64-70,88 are valid */
67b915a5
FB		 123 put_le16(p + 54, s->cylinders);
124 put_le16(p + 55, s->heads);
125 put_le16(p + 56, s->sectors);
5391d806 126 oldsize = s->cylinders * s->heads * s->sectors;
67b915a5
FB		 127 put_le16(p + 57, oldsize);
128 put_le16(p + 58, oldsize >> 16);
5391d806 129 if (s->mult_sectors)
67b915a5 130 put_le16(p + 59, 0x100 | s->mult_sectors);
01ce352e
JS		 131 /* *(p + 60) := nb_sectors -- see ide_identify_size */
132 /* *(p + 61) := nb_sectors >> 16 -- see ide_identify_size */
d1b5c20d 133 put_le16(p + 62, 0x07); /* single word dma0-2 supported */
94458802 134 put_le16(p + 63, 0x07); /* mdma0-2 supported */
79d1d331 135 put_le16(p + 64, 0x03); /* pio3-4 supported */
94458802
FB		 136 put_le16(p + 65, 120);
137 put_le16(p + 66, 120);
138 put_le16(p + 67, 120);
139 put_le16(p + 68, 120);
d353fb72
CH		 140 if (dev && dev->conf.discard_granularity) {
141 put_le16(p + 69, (1 << 14)); /* determinate TRIM behavior */
142 }
ccf0fd8b
RE		 143
144 if (s->ncq_queues) {
145 put_le16(p + 75, s->ncq_queues - 1);
146 /* NCQ supported */
147 put_le16(p + 76, (1 << 8));
148 }
149
94458802
FB		 150 put_le16(p + 80, 0xf0); /* ata3 -> ata6 supported */
151 put_le16(p + 81, 0x16); /* conforms to ata5 */
a58b8d54
CH		 152 /* 14=NOP supported, 5=WCACHE supported, 0=SMART supported */
153 put_le16(p + 82, (1 << 14) | (1 << 5) | 1);
c2ff060f
FB		 154 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
155 put_le16(p + 83, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10));
95ebda85
FB		 156 /* 14=set to 1, 8=has WWN, 1=SMART self test, 0=SMART error logging */
157 if (s->wwn) {
158 put_le16(p + 84, (1 << 14) | (1 << 8) | 0);
159 } else {
160 put_le16(p + 84, (1 << 14) | 0);
161 }
e900a7b7 162 /* 14 = NOP supported, 5=WCACHE enabled, 0=SMART feature set enabled */
4be74634
MA		 163 if (blk_enable_write_cache(s->blk)) {
164 put_le16(p + 85, (1 << 14) | (1 << 5) | 1);
165 } else {
166 put_le16(p + 85, (1 << 14) | 1);
167 }
c2ff060f 168 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
2844bdd9 169 put_le16(p + 86, (1 << 13) | (1 <<12) | (1 << 10));
95ebda85
FB		 170 /* 14=set to 1, 8=has WWN, 1=SMART self test, 0=SMART error logging */
171 if (s->wwn) {
172 put_le16(p + 87, (1 << 14) | (1 << 8) | 0);
173 } else {
174 put_le16(p + 87, (1 << 14) | 0);
175 }
94458802
FB		 176 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
177 put_le16(p + 93, 1 | (1 << 14) | 0x2000);
01ce352e
JS		 178 /* *(p + 100) := nb_sectors -- see ide_identify_size */
179 /* *(p + 101) := nb_sectors >> 16 -- see ide_identify_size */
180 /* *(p + 102) := nb_sectors >> 32 -- see ide_identify_size */
181 /* *(p + 103) := nb_sectors >> 48 -- see ide_identify_size */
d353fb72 182
57dac7ef
MA		 183 if (dev && dev->conf.physical_block_size)
184 put_le16(p + 106, 0x6000 | get_physical_block_exp(&dev->conf));
95ebda85
FB		 185 if (s->wwn) {
186 /* LE 16-bit words 111-108 contain 64-bit World Wide Name */
187 put_le16(p + 108, s->wwn >> 48);
188 put_le16(p + 109, s->wwn >> 32);
189 put_le16(p + 110, s->wwn >> 16);
190 put_le16(p + 111, s->wwn);
191 }
d353fb72
CH		 192 if (dev && dev->conf.discard_granularity) {
193 put_le16(p + 169, 1); /* TRIM support */
194 }
94458802 195
01ce352e 196 ide_identify_size(s);
94458802 197 s->identify_set = 1;
4bf6637d
JS		 198
199fill_buffer:
200 memcpy(s->io_buffer, p, sizeof(s->identify_data));
5391d806
FB		 201}
202
203static void ide_atapi_identify(IDEState *s)
204{
205 uint16_t *p;
206
4bf6637d 207 p = (uint16_t *)s->identify_data;
94458802 208 if (s->identify_set) {
4bf6637d 209 goto fill_buffer;
94458802 210 }
4bf6637d 211 memset(p, 0, sizeof(s->identify_data));
94458802 212
5391d806 213 /* Removable CDROM, 50us response, 12 byte packets */
67b915a5 214 put_le16(p + 0, (2 << 14) | (5 << 8) | (1 << 7) | (2 << 5) | (0 << 0));
fa879c64 215 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
67b915a5
FB		 216 put_le16(p + 20, 3); /* buffer type */
217 put_le16(p + 21, 512); /* cache size in sectors */
218 put_le16(p + 22, 4); /* ecc bytes */
47c06340 219 padstr((char *)(p + 23), s->version, 8); /* firmware version */
27e0c9a1 220 padstr((char *)(p + 27), s->drive_model_str, 40); /* model */
67b915a5 221 put_le16(p + 48, 1); /* dword I/O (XXX: should not be set on CDROM) */
8ccad811
FB		 222#ifdef USE_DMA_CDROM
223 put_le16(p + 49, 1 << 9 | 1 << 8); /* DMA and LBA supported */
224 put_le16(p + 53, 7); /* words 64-70, 54-58, 88 valid */
d1b5c20d 225 put_le16(p + 62, 7); /* single word dma0-2 supported */
8ccad811 226 put_le16(p + 63, 7); /* mdma0-2 supported */
8ccad811 227#else
67b915a5
FB		 228 put_le16(p + 49, 1 << 9); /* LBA supported, no DMA */
229 put_le16(p + 53, 3); /* words 64-70, 54-58 valid */
230 put_le16(p + 63, 0x103); /* DMA modes XXX: may be incorrect */
8ccad811 231#endif
79d1d331 232 put_le16(p + 64, 3); /* pio3-4 supported */
67b915a5
FB		 233 put_le16(p + 65, 0xb4); /* minimum DMA multiword tx cycle time */
234 put_le16(p + 66, 0xb4); /* recommended DMA multiword tx cycle time */
235 put_le16(p + 67, 0x12c); /* minimum PIO cycle time without flow control */
236 put_le16(p + 68, 0xb4); /* minimum PIO cycle time with IORDY flow control */
94458802 237
67b915a5
FB		 238 put_le16(p + 71, 30); /* in ns */
239 put_le16(p + 72, 30); /* in ns */
5391d806 240
1bdaa28d
AG		 241 if (s->ncq_queues) {
242 put_le16(p + 75, s->ncq_queues - 1);
243 /* NCQ supported */
244 put_le16(p + 76, (1 << 8));
245 }
246
67b915a5 247 put_le16(p + 80, 0x1e); /* support up to ATA/ATAPI-4 */
c5fe97e3
JS		 248 if (s->wwn) {
249 put_le16(p + 84, (1 << 8)); /* supports WWN for words 108-111 */
250 put_le16(p + 87, (1 << 8)); /* WWN enabled */
251 }
252
8ccad811
FB		 253#ifdef USE_DMA_CDROM
254 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
255#endif
c5fe97e3
JS		 256
257 if (s->wwn) {
258 /* LE 16-bit words 111-108 contain 64-bit World Wide Name */
259 put_le16(p + 108, s->wwn >> 48);
260 put_le16(p + 109, s->wwn >> 32);
261 put_le16(p + 110, s->wwn >> 16);
262 put_le16(p + 111, s->wwn);
263 }
264
94458802 265 s->identify_set = 1;
4bf6637d
JS		 266
267fill_buffer:
268 memcpy(s->io_buffer, p, sizeof(s->identify_data));
5391d806
FB		 269}
270
01ce352e
JS		 271static void ide_cfata_identify_size(IDEState *s)
272{
273 uint16_t *p = (uint16_t *)s->identify_data;
274 put_le16(p + 7, s->nb_sectors >> 16); /* Sectors per card */
275 put_le16(p + 8, s->nb_sectors); /* Sectors per card */
276 put_le16(p + 60, s->nb_sectors); /* Total LBA sectors */
277 put_le16(p + 61, s->nb_sectors >> 16); /* Total LBA sectors */
278}
279
201a51fc
AZ		 280static void ide_cfata_identify(IDEState *s)
281{
282 uint16_t *p;
283 uint32_t cur_sec;
201a51fc 284
4bf6637d
JS		 285 p = (uint16_t *)s->identify_data;
286 if (s->identify_set) {
201a51fc 287 goto fill_buffer;
4bf6637d 288 }
201a51fc
AZ		 289 memset(p, 0, sizeof(s->identify_data));
290
291 cur_sec = s->cylinders * s->heads * s->sectors;
292
293 put_le16(p + 0, 0x848a); /* CF Storage Card signature */
294 put_le16(p + 1, s->cylinders); /* Default cylinders */
295 put_le16(p + 3, s->heads); /* Default heads */
296 put_le16(p + 6, s->sectors); /* Default sectors per track */
01ce352e
JS		 297 /* *(p + 7) := nb_sectors >> 16 -- see ide_cfata_identify_size */
298 /* *(p + 8) := nb_sectors -- see ide_cfata_identify_size */
fa879c64 299 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
201a51fc 300 put_le16(p + 22, 0x0004); /* ECC bytes */
47c06340 301 padstr((char *) (p + 23), s->version, 8); /* Firmware Revision */
27e0c9a1 302 padstr((char *) (p + 27), s->drive_model_str, 40);/* Model number */
201a51fc
AZ		 303#if MAX_MULT_SECTORS > 1
304 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
305#else
306 put_le16(p + 47, 0x0000);
307#endif
308 put_le16(p + 49, 0x0f00); /* Capabilities */
309 put_le16(p + 51, 0x0002); /* PIO cycle timing mode */
310 put_le16(p + 52, 0x0001); /* DMA cycle timing mode */
311 put_le16(p + 53, 0x0003); /* Translation params valid */
312 put_le16(p + 54, s->cylinders); /* Current cylinders */
313 put_le16(p + 55, s->heads); /* Current heads */
314 put_le16(p + 56, s->sectors); /* Current sectors */
315 put_le16(p + 57, cur_sec); /* Current capacity */
316 put_le16(p + 58, cur_sec >> 16); /* Current capacity */
317 if (s->mult_sectors) /* Multiple sector setting */
318 put_le16(p + 59, 0x100 | s->mult_sectors);
01ce352e
JS		 319 /* *(p + 60) := nb_sectors -- see ide_cfata_identify_size */
320 /* *(p + 61) := nb_sectors >> 16 -- see ide_cfata_identify_size */
201a51fc
AZ		 321 put_le16(p + 63, 0x0203); /* Multiword DMA capability */
322 put_le16(p + 64, 0x0001); /* Flow Control PIO support */
323 put_le16(p + 65, 0x0096); /* Min. Multiword DMA cycle */
324 put_le16(p + 66, 0x0096); /* Rec. Multiword DMA cycle */
325 put_le16(p + 68, 0x00b4); /* Min. PIO cycle time */
326 put_le16(p + 82, 0x400c); /* Command Set supported */
327 put_le16(p + 83, 0x7068); /* Command Set supported */
328 put_le16(p + 84, 0x4000); /* Features supported */
329 put_le16(p + 85, 0x000c); /* Command Set enabled */
330 put_le16(p + 86, 0x7044); /* Command Set enabled */
331 put_le16(p + 87, 0x4000); /* Features enabled */
332 put_le16(p + 91, 0x4060); /* Current APM level */
333 put_le16(p + 129, 0x0002); /* Current features option */
334 put_le16(p + 130, 0x0005); /* Reassigned sectors */
335 put_le16(p + 131, 0x0001); /* Initial power mode */
336 put_le16(p + 132, 0x0000); /* User signature */
337 put_le16(p + 160, 0x8100); /* Power requirement */
338 put_le16(p + 161, 0x8001); /* CF command set */
339
01ce352e 340 ide_cfata_identify_size(s);
201a51fc
AZ		 341 s->identify_set = 1;
342
343fill_buffer:
344 memcpy(s->io_buffer, p, sizeof(s->identify_data));
345}
346
5391d806
FB		 347static void ide_set_signature(IDEState *s)
348{
349 s->select &= 0xf0; /* clear head */
350 /* put signature */
351 s->nsector = 1;
352 s->sector = 1;
cd8722bb 353 if (s->drive_kind == IDE_CD) {
5391d806
FB		 354 s->lcyl = 0x14;
355 s->hcyl = 0xeb;
4be74634 356 } else if (s->blk) {
5391d806
FB		 357 s->lcyl = 0;
358 s->hcyl = 0;
359 } else {
360 s->lcyl = 0xff;
361 s->hcyl = 0xff;
362 }
363}
364
d353fb72 365typedef struct TrimAIOCB {
7c84b1b8 366 BlockAIOCB common;
a987ee1f 367 BlockBackend *blk;
d353fb72
CH		 368 QEMUBH *bh;
369 int ret;
501378c3 370 QEMUIOVector *qiov;
7c84b1b8 371 BlockAIOCB *aiocb;
501378c3 372 int i, j;
d353fb72
CH		 373} TrimAIOCB;
374
7c84b1b8 375static void trim_aio_cancel(BlockAIOCB *acb)
d353fb72
CH		 376{
377 TrimAIOCB *iocb = container_of(acb, TrimAIOCB, common);
378
e551c999 379 /* Exit the loop so ide_issue_trim_cb will not continue */
501378c3
PB		 380 iocb->j = iocb->qiov->niov - 1;
381 iocb->i = (iocb->qiov->iov[iocb->j].iov_len / 8) - 1;
382
e551c999 383 iocb->ret = -ECANCELED;
501378c3
PB		 384
385 if (iocb->aiocb) {
4be74634 386 blk_aio_cancel_async(iocb->aiocb);
e551c999 387 iocb->aiocb = NULL;
501378c3 388 }
d353fb72
CH		 389}
390
d7331bed 391static const AIOCBInfo trim_aiocb_info = {
d353fb72 392 .aiocb_size = sizeof(TrimAIOCB),
e551c999 393 .cancel_async = trim_aio_cancel,
d353fb72
CH		 394};
395
396static void ide_trim_bh_cb(void *opaque)
397{
398 TrimAIOCB *iocb = opaque;
399
400 iocb->common.cb(iocb->common.opaque, iocb->ret);
401
402 qemu_bh_delete(iocb->bh);
403 iocb->bh = NULL;
8007429a 404 qemu_aio_unref(iocb);
d353fb72
CH		 405}
406
501378c3
PB		 407static void ide_issue_trim_cb(void *opaque, int ret)
408{
409 TrimAIOCB *iocb = opaque;
410 if (ret >= 0) {
411 while (iocb->j < iocb->qiov->niov) {
412 int j = iocb->j;
413 while (++iocb->i < iocb->qiov->iov[j].iov_len / 8) {
414 int i = iocb->i;
415 uint64_t *buffer = iocb->qiov->iov[j].iov_base;
416
417 /* 6-byte LBA + 2-byte range per entry */
418 uint64_t entry = le64_to_cpu(buffer[i]);
419 uint64_t sector = entry & 0x0000ffffffffffffULL;
420 uint16_t count = entry >> 48;
421
422 if (count == 0) {
423 continue;
424 }
425
426 /* Got an entry! Submit and exit. */
a987ee1f
MA		 427 iocb->aiocb = blk_aio_discard(iocb->blk, sector, count,
428 ide_issue_trim_cb, opaque);
501378c3
PB		 429 return;
430 }
431
432 iocb->j++;
433 iocb->i = -1;
434 }
435 } else {
436 iocb->ret = ret;
437 }
438
439 iocb->aiocb = NULL;
440 if (iocb->bh) {
441 qemu_bh_schedule(iocb->bh);
442 }
443}
444
4be74634 445BlockAIOCB *ide_issue_trim(BlockBackend *blk,
d353fb72 446 int64_t sector_num, QEMUIOVector *qiov, int nb_sectors,
097310b5 447 BlockCompletionFunc *cb, void *opaque)
d353fb72
CH		 448{
449 TrimAIOCB *iocb;
d353fb72 450
4be74634 451 iocb = blk_aio_get(&trim_aiocb_info, blk, cb, opaque);
a987ee1f 452 iocb->blk = blk;
d353fb72
CH		 453 iocb->bh = qemu_bh_new(ide_trim_bh_cb, iocb);
454 iocb->ret = 0;
501378c3
PB		 455 iocb->qiov = qiov;
456 iocb->i = -1;
457 iocb->j = 0;
458 ide_issue_trim_cb(iocb, 0);
d353fb72
CH		 459 return &iocb->common;
460}
461
9ef2e93f 462void ide_abort_command(IDEState *s)
5391d806 463{
08ee9e33 464 ide_transfer_stop(s);
5391d806
FB		 465 s->status = READY_STAT | ERR_STAT;
466 s->error = ABRT_ERR;
467}
468
5391d806 469/* prepare data transfer and tell what to do after */
33231e0e
KW		 470void ide_transfer_start(IDEState *s, uint8_t *buf, int size,
471 EndTransferFunc *end_transfer_func)
5391d806
FB		 472{
473 s->end_transfer_func = end_transfer_func;
474 s->data_ptr = buf;
475 s->data_end = buf + size;
40a6238a 476 if (!(s->status & ERR_STAT)) {
7603d156 477 s->status |= DRQ_STAT;
40a6238a 478 }
44635123
PB		 479 if (s->bus->dma->ops->start_transfer) {
480 s->bus->dma->ops->start_transfer(s->bus->dma);
481 }
5391d806
FB		 482}
483
c7e73adb
PB		 484static void ide_cmd_done(IDEState *s)
485{
486 if (s->bus->dma->ops->cmd_done) {
487 s->bus->dma->ops->cmd_done(s->bus->dma);
488 }
489}
490
e3044e23
JS		 491static void ide_transfer_halt(IDEState *s,
492 void(*end_transfer_func)(IDEState *),
493 bool notify)
5391d806 494{
e3044e23 495 s->end_transfer_func = end_transfer_func;
5391d806
FB		 496 s->data_ptr = s->io_buffer;
497 s->data_end = s->io_buffer;
498 s->status &= ~DRQ_STAT;
e3044e23
JS		 499 if (notify) {
500 ide_cmd_done(s);
501 }
502}
503
504void ide_transfer_stop(IDEState *s)
505{
506 ide_transfer_halt(s, ide_transfer_stop, true);
507}
508
e3044e23
JS		 509static void ide_transfer_cancel(IDEState *s)
510{
511 ide_transfer_halt(s, ide_transfer_cancel, false);
5391d806
FB		 512}
513
356721ae 514int64_t ide_get_sector(IDEState *s)
5391d806
FB		 515{
516 int64_t sector_num;
517 if (s->select & 0x40) {
518 /* lba */
c2ff060f
FB		 519 if (!s->lba48) {
520 sector_num = ((s->select & 0x0f) << 24) | (s->hcyl << 16) |
521 (s->lcyl << 8) | s->sector;
522 } else {
523 sector_num = ((int64_t)s->hob_hcyl << 40) |
524 ((int64_t) s->hob_lcyl << 32) |
525 ((int64_t) s->hob_sector << 24) |
526 ((int64_t) s->hcyl << 16) |
527 ((int64_t) s->lcyl << 8) | s->sector;
528 }
5391d806
FB		 529 } else {
530 sector_num = ((s->hcyl << 8) | s->lcyl) * s->heads * s->sectors +
c2ff060f 531 (s->select & 0x0f) * s->sectors + (s->sector - 1);
5391d806
FB		 532 }
533 return sector_num;
534}
535
356721ae 536void ide_set_sector(IDEState *s, int64_t sector_num)
5391d806
FB		 537{
538 unsigned int cyl, r;
539 if (s->select & 0x40) {
c2ff060f
FB		 540 if (!s->lba48) {
541 s->select = (s->select & 0xf0) | (sector_num >> 24);
542 s->hcyl = (sector_num >> 16);
543 s->lcyl = (sector_num >> 8);
544 s->sector = (sector_num);
545 } else {
546 s->sector = sector_num;
547 s->lcyl = sector_num >> 8;
548 s->hcyl = sector_num >> 16;
549 s->hob_sector = sector_num >> 24;
550 s->hob_lcyl = sector_num >> 32;
551 s->hob_hcyl = sector_num >> 40;
552 }
5391d806
FB		 553 } else {
554 cyl = sector_num / (s->heads * s->sectors);
555 r = sector_num % (s->heads * s->sectors);
556 s->hcyl = cyl >> 8;
557 s->lcyl = cyl;
1b8eb456 558 s->select = (s->select & 0xf0) | ((r / s->sectors) & 0x0f);
5391d806
FB		 559 s->sector = (r % s->sectors) + 1;
560 }
561}
562
e162cfb0
AZ		 563static void ide_rw_error(IDEState *s) {
564 ide_abort_command(s);
9cdd03a7 565 ide_set_irq(s->bus);
e162cfb0
AZ		 566}
567
58ac3211
MA		 568static bool ide_sect_range_ok(IDEState *s,
569 uint64_t sector, uint64_t nb_sectors)
570{
571 uint64_t total_sectors;
572
4be74634 573 blk_get_geometry(s->blk, &total_sectors);
58ac3211
MA		 574 if (sector > total_sectors || nb_sectors > total_sectors - sector) {
575 return false;
576 }
577 return true;
578}
579
1d8c11d6
PL		 580static void ide_buffered_readv_cb(void *opaque, int ret)
581{
582 IDEBufferedRequest *req = opaque;
583 if (!req->orphaned) {
584 if (!ret) {
585 qemu_iovec_from_buf(req->original_qiov, 0, req->iov.iov_base,
586 req->original_qiov->size);
587 }
588 req->original_cb(req->original_opaque, ret);
589 }
590 QLIST_REMOVE(req, list);
591 qemu_vfree(req->iov.iov_base);
592 g_free(req);
593}
594
595#define MAX_BUFFERED_REQS 16
596
597BlockAIOCB *ide_buffered_readv(IDEState *s, int64_t sector_num,
598 QEMUIOVector *iov, int nb_sectors,
599 BlockCompletionFunc *cb, void *opaque)
600{
601 BlockAIOCB *aioreq;
602 IDEBufferedRequest *req;
603 int c = 0;
604
605 QLIST_FOREACH(req, &s->buffered_requests, list) {
606 c++;
607 }
608 if (c > MAX_BUFFERED_REQS) {
609 return blk_abort_aio_request(s->blk, cb, opaque, -EIO);
610 }
611
612 req = g_new0(IDEBufferedRequest, 1);
613 req->original_qiov = iov;
614 req->original_cb = cb;
615 req->original_opaque = opaque;
616 req->iov.iov_base = qemu_blockalign(blk_bs(s->blk), iov->size);
617 req->iov.iov_len = iov->size;
618 qemu_iovec_init_external(&req->qiov, &req->iov, 1);
619
620 aioreq = blk_aio_readv(s->blk, sector_num, &req->qiov, nb_sectors,
621 ide_buffered_readv_cb, req);
622
623 QLIST_INSERT_HEAD(&s->buffered_requests, req, list);
624 return aioreq;
625}
626
86698a12
JS		 627/**
628 * Cancel all pending DMA requests.
629 * Any buffered DMA requests are instantly canceled,
630 * but any pending unbuffered DMA requests must be waited on.
631 */
632void ide_cancel_dma_sync(IDEState *s)
633{
634 IDEBufferedRequest *req;
635
636 /* First invoke the callbacks of all buffered requests
637 * and flag those requests as orphaned. Ideally there
638 * are no unbuffered (Scatter Gather DMA Requests or
639 * write requests) pending and we can avoid to drain. */
640 QLIST_FOREACH(req, &s->buffered_requests, list) {
641 if (!req->orphaned) {
642#ifdef DEBUG_IDE
643 printf("%s: invoking cb %p of buffered request %p with"
644 " -ECANCELED\n", __func__, req->original_cb, req);
645#endif
646 req->original_cb(req->original_opaque, -ECANCELED);
647 }
648 req->orphaned = true;
649 }
650
651 /*
652 * We can't cancel Scatter Gather DMA in the middle of the
653 * operation or a partial (not full) DMA transfer would reach
654 * the storage so we wait for completion instead (we beahve
655 * like if the DMA was completed by the time the guest trying
656 * to cancel dma with bmdma_cmd_writeb with BM_CMD_START not
657 * set).
658 *
659 * In the future we'll be able to safely cancel the I/O if the
660 * whole DMA operation will be submitted to disk with a single
661 * aio operation with preadv/pwritev.
662 */
663 if (s->bus->dma->aiocb) {
664#ifdef DEBUG_IDE
665 printf("%s: draining all remaining requests", __func__);
666#endif
51f7b5b8 667 blk_drain(s->blk);
86698a12
JS		 668 assert(s->bus->dma->aiocb == NULL);
669 }
670}
671
4e2b8b4a
PB		 672static void ide_sector_read(IDEState *s);
673
bef0fd59
SH		 674static void ide_sector_read_cb(void *opaque, int ret)
675{
676 IDEState *s = opaque;
677 int n;
678
679 s->pio_aiocb = NULL;
680 s->status &= ~BUSY_STAT;
681
0d910cfe
FZ		 682 if (ret == -ECANCELED) {
683 return;
684 }
bef0fd59 685 if (ret != 0) {
fd648f10
PB		 686 if (ide_handle_rw_error(s, -ret, IDE_RETRY_PIO |
687 IDE_RETRY_READ)) {
bef0fd59
SH		 688 return;
689 }
690 }
691
ecca3b39
AG		 692 block_acct_done(blk_get_stats(s->blk), &s->acct);
693
bef0fd59
SH		 694 n = s->nsector;
695 if (n > s->req_nb_sectors) {
696 n = s->req_nb_sectors;
697 }
698
bef0fd59
SH		 699 ide_set_sector(s, ide_get_sector(s) + n);
700 s->nsector -= n;
dd0bf7ba
JS		 701 /* Allow the guest to read the io_buffer */
702 ide_transfer_start(s, s->io_buffer, n * BDRV_SECTOR_SIZE, ide_sector_read);
dd0bf7ba 703 ide_set_irq(s->bus);
bef0fd59
SH		 704}
705
4e2b8b4a 706static void ide_sector_read(IDEState *s)
5391d806
FB		 707{
708 int64_t sector_num;
bef0fd59 709 int n;
5391d806
FB		 710
711 s->status = READY_STAT | SEEK_STAT;
a136e5a8 712 s->error = 0; /* not needed by IDE spec, but needed by Windows */
5391d806
FB		 713 sector_num = ide_get_sector(s);
714 n = s->nsector;
bef0fd59 715
5391d806 716 if (n == 0) {
5391d806 717 ide_transfer_stop(s);
bef0fd59
SH		 718 return;
719 }
720
721 s->status |= BUSY_STAT;
722
723 if (n > s->req_nb_sectors) {
724 n = s->req_nb_sectors;
725 }
726
5391d806 727#if defined(DEBUG_IDE)
bef0fd59 728 printf("sector=%" PRId64 "\n", sector_num);
5391d806 729#endif
a597e79c 730
58ac3211
MA		 731 if (!ide_sect_range_ok(s, sector_num, n)) {
732 ide_rw_error(s);
ecca3b39 733 block_acct_invalid(blk_get_stats(s->blk), BLOCK_ACCT_READ);
58ac3211
MA		 734 return;
735 }
736
bef0fd59
SH		 737 s->iov.iov_base = s->io_buffer;
738 s->iov.iov_len = n * BDRV_SECTOR_SIZE;
739 qemu_iovec_init_external(&s->qiov, &s->iov, 1);
740
4be74634 741 block_acct_start(blk_get_stats(s->blk), &s->acct,
5366d0c8 742 n * BDRV_SECTOR_SIZE, BLOCK_ACCT_READ);
d66a8fa8
PL		 743 s->pio_aiocb = ide_buffered_readv(s, sector_num, &s->qiov, n,
744 ide_sector_read_cb, s);
5391d806
FB		 745}
746
aaeda4a3 747void dma_buf_commit(IDEState *s, uint32_t tx_bytes)
7aea4412 748{
659142ec
JS		 749 if (s->bus->dma->ops->commit_buf) {
750 s->bus->dma->ops->commit_buf(s->bus->dma, tx_bytes);
751 }
aaeda4a3 752 s->io_buffer_offset += tx_bytes;
1fb8648d 753 qemu_sglist_destroy(&s->sg);
7aea4412
AL		 754}
755
0e7ce54c 756void ide_set_inactive(IDEState *s, bool more)
8337606d 757{
40a6238a 758 s->bus->dma->aiocb = NULL;
a96cb236 759 s->bus->retry_unit = -1;
dc5d0af4
PB		 760 s->bus->retry_sector_num = 0;
761 s->bus->retry_nsector = 0;
829b933b 762 if (s->bus->dma->ops->set_inactive) {
0e7ce54c 763 s->bus->dma->ops->set_inactive(s->bus->dma, more);
829b933b 764 }
c7e73adb 765 ide_cmd_done(s);
8337606d
KW		 766}
767
356721ae 768void ide_dma_error(IDEState *s)
e162cfb0 769{
659142ec 770 dma_buf_commit(s, 0);
08ee9e33 771 ide_abort_command(s);
0e7ce54c 772 ide_set_inactive(s, false);
9cdd03a7 773 ide_set_irq(s->bus);
e162cfb0
AZ		 774}
775
ce4b6522 776static int ide_handle_rw_error(IDEState *s, int error, int op)
428c5705 777{
fd648f10 778 bool is_read = (op & IDE_RETRY_READ) != 0;
4be74634 779 BlockErrorAction action = blk_get_error_action(s->blk, is_read, error);
428c5705 780
a589569f 781 if (action == BLOCK_ERROR_ACTION_STOP) {
a96cb236 782 assert(s->bus->retry_unit == s->unit);
def93791 783 s->bus->error_status = op;
a589569f 784 } else if (action == BLOCK_ERROR_ACTION_REPORT) {
ecca3b39 785 block_acct_failed(blk_get_stats(s->blk), &s->acct);
fd648f10 786 if (op & IDE_RETRY_DMA) {
428c5705 787 ide_dma_error(s);
7aea4412 788 } else {
428c5705 789 ide_rw_error(s);
7aea4412 790 }
428c5705 791 }
4be74634 792 blk_error_action(s->blk, action, is_read, error);
a589569f 793 return action != BLOCK_ERROR_ACTION_IGNORE;
428c5705
AL		 794}
795
4e2b8b4a 796static void ide_dma_cb(void *opaque, int ret)
98087450 797{
40a6238a 798 IDEState *s = opaque;
8ccad811
FB		 799 int n;
800 int64_t sector_num;
038268e2 801 bool stay_active = false;
8ccad811 802
0d910cfe
FZ		 803 if (ret == -ECANCELED) {
804 return;
805 }
e162cfb0 806 if (ret < 0) {
218fd37c 807 if (ide_handle_rw_error(s, -ret, ide_dma_cmd_to_retry(s->dma_cmd))) {
ce4b6522
KW		 808 return;
809 }
e162cfb0
AZ		 810 }
811
8ccad811 812 n = s->io_buffer_size >> 9;
038268e2
KW		 813 if (n > s->nsector) {
814 /* The PRDs were longer than needed for this request. Shorten them so
815 * we don't get a negative remainder. The Active bit must remain set
816 * after the request completes. */
817 n = s->nsector;
818 stay_active = true;
819 }
820
8ccad811
FB		 821 sector_num = ide_get_sector(s);
822 if (n > 0) {
a718978e
JS		 823 assert(n * 512 == s->sg.size);
824 dma_buf_commit(s, s->sg.size);
8ccad811
FB		 825 sector_num += n;
826 ide_set_sector(s, sector_num);
827 s->nsector -= n;
8ccad811
FB		 828 }
829
830 /* end of transfer ? */
831 if (s->nsector == 0) {
98087450 832 s->status = READY_STAT | SEEK_STAT;
9cdd03a7 833 ide_set_irq(s->bus);
cd369c46 834 goto eot;
98087450 835 }
8ccad811
FB		 836
837 /* launch next transfer */
838 n = s->nsector;
596bb44d 839 s->io_buffer_index = 0;
8ccad811 840 s->io_buffer_size = n * 512;
a718978e 841 if (s->bus->dma->ops->prepare_buf(s->bus->dma, s->io_buffer_size) < 512) {
69c38b8f
KW		 842 /* The PRDs were too short. Reset the Active bit, but don't raise an
843 * interrupt. */
72bcca73 844 s->status = READY_STAT | SEEK_STAT;
3251bdcf 845 dma_buf_commit(s, 0);
7aea4412 846 goto eot;
69c38b8f 847 }
cd369c46 848
8ccad811 849#ifdef DEBUG_AIO
4e1e0051
CH		 850 printf("ide_dma_cb: sector_num=%" PRId64 " n=%d, cmd_cmd=%d\n",
851 sector_num, n, s->dma_cmd);
8ccad811 852#endif
cd369c46 853
d66168ed
MT		 854 if ((s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) &&
855 !ide_sect_range_ok(s, sector_num, n)) {
58ac3211 856 ide_dma_error(s);
ecca3b39 857 block_acct_invalid(blk_get_stats(s->blk), s->acct.type);
58ac3211
MA		 858 return;
859 }
860
4e1e0051
CH		 861 switch (s->dma_cmd) {
862 case IDE_DMA_READ:
4be74634
MA		 863 s->bus->dma->aiocb = dma_blk_read(s->blk, &s->sg, sector_num,
864 ide_dma_cb, s);
4e1e0051
CH		 865 break;
866 case IDE_DMA_WRITE:
4be74634
MA		 867 s->bus->dma->aiocb = dma_blk_write(s->blk, &s->sg, sector_num,
868 ide_dma_cb, s);
4e1e0051 869 break;
d353fb72 870 case IDE_DMA_TRIM:
4be74634
MA		 871 s->bus->dma->aiocb = dma_blk_io(s->blk, &s->sg, sector_num,
872 ide_issue_trim, ide_dma_cb, s,
873 DMA_DIRECTION_TO_DEVICE);
d353fb72 874 break;
cd369c46 875 }
cd369c46
CH		 876 return;
877
878eot:
a597e79c 879 if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) {
4be74634 880 block_acct_done(blk_get_stats(s->blk), &s->acct);
a597e79c 881 }
0e7ce54c 882 ide_set_inactive(s, stay_active);
98087450
FB		 883}
884
4e1e0051 885static void ide_sector_start_dma(IDEState *s, enum ide_dma_cmd dma_cmd)
98087450 886{
8ccad811 887 s->status = READY_STAT | SEEK_STAT | DRQ_STAT | BUSY_STAT;
98087450 888 s->io_buffer_size = 0;
4e1e0051 889 s->dma_cmd = dma_cmd;
a597e79c
CH		 890
891 switch (dma_cmd) {
892 case IDE_DMA_READ:
4be74634 893 block_acct_start(blk_get_stats(s->blk), &s->acct,
5366d0c8 894 s->nsector * BDRV_SECTOR_SIZE, BLOCK_ACCT_READ);
a597e79c
CH		 895 break;
896 case IDE_DMA_WRITE:
4be74634 897 block_acct_start(blk_get_stats(s->blk), &s->acct,
5366d0c8 898 s->nsector * BDRV_SECTOR_SIZE, BLOCK_ACCT_WRITE);
a597e79c
CH		 899 break;
900 default:
901 break;
902 }
903
4855b576
PB		 904 ide_start_dma(s, ide_dma_cb);
905}
906
097310b5 907void ide_start_dma(IDEState *s, BlockCompletionFunc *cb)
4855b576 908{
c71c06d4 909 s->io_buffer_index = 0;
a96cb236 910 s->bus->retry_unit = s->unit;
dc5d0af4
PB		 911 s->bus->retry_sector_num = ide_get_sector(s);
912 s->bus->retry_nsector = s->nsector;
4855b576
PB		 913 if (s->bus->dma->ops->start_dma) {
914 s->bus->dma->ops->start_dma(s->bus->dma, s, cb);
915 }
98087450
FB		 916}
917
4e2b8b4a
PB		 918static void ide_sector_write(IDEState *s);
919
a09db21f
FB		 920static void ide_sector_write_timer_cb(void *opaque)
921{
922 IDEState *s = opaque;
9cdd03a7 923 ide_set_irq(s->bus);
a09db21f
FB		 924}
925
e82dabd8 926static void ide_sector_write_cb(void *opaque, int ret)
5391d806 927{
e82dabd8
SH		 928 IDEState *s = opaque;
929 int n;
a597e79c 930
0d910cfe
FZ		 931 if (ret == -ECANCELED) {
932 return;
933 }
428c5705 934
e82dabd8
SH		 935 s->pio_aiocb = NULL;
936 s->status &= ~BUSY_STAT;
937
e162cfb0 938 if (ret != 0) {
fd648f10 939 if (ide_handle_rw_error(s, -ret, IDE_RETRY_PIO)) {
428c5705 940 return;
e82dabd8 941 }
e162cfb0
AZ		 942 }
943
ecca3b39
AG		 944 block_acct_done(blk_get_stats(s->blk), &s->acct);
945
e82dabd8
SH		 946 n = s->nsector;
947 if (n > s->req_nb_sectors) {
948 n = s->req_nb_sectors;
949 }
5391d806 950 s->nsector -= n;
36334faf 951
6aff22c0 952 ide_set_sector(s, ide_get_sector(s) + n);
5391d806 953 if (s->nsector == 0) {
292eef5a 954 /* no more sectors to write */
5391d806
FB		 955 ide_transfer_stop(s);
956 } else {
e82dabd8
SH		 957 int n1 = s->nsector;
958 if (n1 > s->req_nb_sectors) {
5391d806 959 n1 = s->req_nb_sectors;
e82dabd8
SH		 960 }
961 ide_transfer_start(s, s->io_buffer, n1 * BDRV_SECTOR_SIZE,
962 ide_sector_write);
5391d806 963 }
3b46e624 964
31c2a146
TS		 965 if (win2k_install_hack && ((++s->irq_count % 16) == 0)) {
966 /* It seems there is a bug in the Windows 2000 installer HDD
967 IDE driver which fills the disk with empty logs when the
968 IDE write IRQ comes too early. This hack tries to correct
969 that at the expense of slower write performances. Use this
970 option _only_ to install Windows 2000. You must disable it
971 for normal use. */
73bcb24d
RS		 972 timer_mod(s->sector_write_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
973 (NANOSECONDS_PER_SECOND / 1000));
f7736b91 974 } else {
9cdd03a7 975 ide_set_irq(s->bus);
31c2a146 976 }
5391d806
FB		 977}
978
4e2b8b4a 979static void ide_sector_write(IDEState *s)
e82dabd8
SH		 980{
981 int64_t sector_num;
982 int n;
983
984 s->status = READY_STAT | SEEK_STAT | BUSY_STAT;
985 sector_num = ide_get_sector(s);
986#if defined(DEBUG_IDE)
987 printf("sector=%" PRId64 "\n", sector_num);
988#endif
989 n = s->nsector;
990 if (n > s->req_nb_sectors) {
991 n = s->req_nb_sectors;
992 }
993
58ac3211
MA		 994 if (!ide_sect_range_ok(s, sector_num, n)) {
995 ide_rw_error(s);
ecca3b39 996 block_acct_invalid(blk_get_stats(s->blk), BLOCK_ACCT_WRITE);
58ac3211
MA		 997 return;
998 }
999
e82dabd8
SH		 1000 s->iov.iov_base = s->io_buffer;
1001 s->iov.iov_len = n * BDRV_SECTOR_SIZE;
1002 qemu_iovec_init_external(&s->qiov, &s->iov, 1);
1003
4be74634 1004 block_acct_start(blk_get_stats(s->blk), &s->acct,
c618f331 1005 n * BDRV_SECTOR_SIZE, BLOCK_ACCT_WRITE);
4be74634
MA		 1006 s->pio_aiocb = blk_aio_writev(s->blk, sector_num, &s->qiov, n,
1007 ide_sector_write_cb, s);
e82dabd8
SH		 1008}
1009
b0484ae4
CH		 1010static void ide_flush_cb(void *opaque, int ret)
1011{
1012 IDEState *s = opaque;
1013
69f72a22
PB		 1014 s->pio_aiocb = NULL;
1015
0d910cfe
FZ		 1016 if (ret == -ECANCELED) {
1017 return;
1018 }
e2bcadad
KW		 1019 if (ret < 0) {
1020 /* XXX: What sector number to set here? */
fd648f10 1021 if (ide_handle_rw_error(s, -ret, IDE_RETRY_FLUSH)) {
e2bcadad
KW		 1022 return;
1023 }
1024 }
b0484ae4 1025
4be74634
MA		 1026 if (s->blk) {
1027 block_acct_done(blk_get_stats(s->blk), &s->acct);
f7f3ff1d 1028 }
b0484ae4 1029 s->status = READY_STAT | SEEK_STAT;
c7e73adb 1030 ide_cmd_done(s);
b0484ae4
CH		 1031 ide_set_irq(s->bus);
1032}
1033
4e2b8b4a 1034static void ide_flush_cache(IDEState *s)
6bcb1a79 1035{
4be74634 1036 if (s->blk == NULL) {
6bcb1a79 1037 ide_flush_cb(s, 0);
b2df7531
KW		 1038 return;
1039 }
1040
f68ec837 1041 s->status |= BUSY_STAT;
4be74634
MA		 1042 block_acct_start(blk_get_stats(s->blk), &s->acct, 0, BLOCK_ACCT_FLUSH);
1043 s->pio_aiocb = blk_aio_flush(s->blk, ide_flush_cb, s);
6bcb1a79
KW		 1044}
1045
201a51fc
AZ		 1046static void ide_cfata_metadata_inquiry(IDEState *s)
1047{
1048 uint16_t *p;
1049 uint32_t spd;
1050
1051 p = (uint16_t *) s->io_buffer;
1052 memset(p, 0, 0x200);
1053 spd = ((s->mdata_size - 1) >> 9) + 1;
1054
1055 put_le16(p + 0, 0x0001); /* Data format revision */
1056 put_le16(p + 1, 0x0000); /* Media property: silicon */
1057 put_le16(p + 2, s->media_changed); /* Media status */
1058 put_le16(p + 3, s->mdata_size & 0xffff); /* Capacity in bytes (low) */
1059 put_le16(p + 4, s->mdata_size >> 16); /* Capacity in bytes (high) */
1060 put_le16(p + 5, spd & 0xffff); /* Sectors per device (low) */
1061 put_le16(p + 6, spd >> 16); /* Sectors per device (high) */
1062}
1063
1064static void ide_cfata_metadata_read(IDEState *s)
1065{
1066 uint16_t *p;
1067
1068 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
1069 s->status = ERR_STAT;
1070 s->error = ABRT_ERR;
1071 return;
1072 }
1073
1074 p = (uint16_t *) s->io_buffer;
1075 memset(p, 0, 0x200);
1076
1077 put_le16(p + 0, s->media_changed); /* Media status */
1078 memcpy(p + 1, s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
1079 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
1080 s->nsector << 9), 0x200 - 2));
1081}
1082
1083static void ide_cfata_metadata_write(IDEState *s)
1084{
1085 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
1086 s->status = ERR_STAT;
1087 s->error = ABRT_ERR;
1088 return;
1089 }
1090
1091 s->media_changed = 0;
1092
1093 memcpy(s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
1094 s->io_buffer + 2,
1095 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
1096 s->nsector << 9), 0x200 - 2));
1097}
1098
bd491d6a 1099/* called when the inserted state of the media has changed */
7d4b4ba5 1100static void ide_cd_change_cb(void *opaque, bool load)
bd491d6a
TS		 1101{
1102 IDEState *s = opaque;
96b8f136 1103 uint64_t nb_sectors;
bd491d6a 1104
25ad22bc 1105 s->tray_open = !load;
4be74634 1106 blk_get_geometry(s->blk, &nb_sectors);
bd491d6a 1107 s->nb_sectors = nb_sectors;
9118e7f0 1108
4b9b7092
AS		 1109 /*
1110 * First indicate to the guest that a CD has been removed. That's
1111 * done on the next command the guest sends us.
1112 *
67cc61e4 1113 * Then we set UNIT_ATTENTION, by which the guest will
4b9b7092
AS		 1114 * detect a new CD in the drive. See ide_atapi_cmd() for details.
1115 */
93c8cfd9 1116 s->cdrom_changed = 1;
996faf1a 1117 s->events.new_media = true;
2df0a3a3
PB		 1118 s->events.eject_request = false;
1119 ide_set_irq(s->bus);
1120}
1121
1122static void ide_cd_eject_request_cb(void *opaque, bool force)
1123{
1124 IDEState *s = opaque;
1125
1126 s->events.eject_request = true;
1127 if (force) {
1128 s->tray_locked = false;
1129 }
9cdd03a7 1130 ide_set_irq(s->bus);
bd491d6a
TS		 1131}
1132
c2ff060f
FB		 1133static void ide_cmd_lba48_transform(IDEState *s, int lba48)
1134{
1135 s->lba48 = lba48;
1136
1137 /* handle the 'magic' 0 nsector count conversion here. to avoid
1138 * fiddling with the rest of the read logic, we just store the
1139 * full sector count in ->nsector and ignore ->hob_nsector from now
1140 */
1141 if (!s->lba48) {
1142 if (!s->nsector)
1143 s->nsector = 256;
1144 } else {
1145 if (!s->nsector && !s->hob_nsector)
1146 s->nsector = 65536;
1147 else {
1148 int lo = s->nsector;
1149 int hi = s->hob_nsector;
1150
1151 s->nsector = (hi << 8) | lo;
1152 }
1153 }
1154}
1155
bcbdc4d3 1156static void ide_clear_hob(IDEBus *bus)
c2ff060f
FB		 1157{
1158 /* any write clears HOB high bit of device control register */
bcbdc4d3
GH		 1159 bus->ifs[0].select &= ~(1 << 7);
1160 bus->ifs[1].select &= ~(1 << 7);
c2ff060f
FB		 1161}
1162
356721ae 1163void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
caed8802 1164{
bcbdc4d3 1165 IDEBus *bus = opaque;
5391d806
FB		 1166
1167#ifdef DEBUG_IDE
1168 printf("IDE: write addr=0x%x val=0x%02x\n", addr, val);
1169#endif
c2ff060f 1170
5391d806 1171 addr &= 7;
fcdd25ab
AL		 1172
1173 /* ignore writes to command block while busy with previous command */
bcbdc4d3 1174 if (addr != 7 && (idebus_active_if(bus)->status & (BUSY_STAT|DRQ_STAT)))
fcdd25ab
AL		 1175 return;
1176
5391d806
FB		 1177 switch(addr) {
1178 case 0:
1179 break;
1180 case 1:
bcbdc4d3 1181 ide_clear_hob(bus);
c45c3d00 1182 /* NOTE: data is written to the two drives */
bcbdc4d3
GH		 1183 bus->ifs[0].hob_feature = bus->ifs[0].feature;
1184 bus->ifs[1].hob_feature = bus->ifs[1].feature;
1185 bus->ifs[0].feature = val;
1186 bus->ifs[1].feature = val;
5391d806
FB		 1187 break;
1188 case 2:
bcbdc4d3
GH		 1189 ide_clear_hob(bus);
1190 bus->ifs[0].hob_nsector = bus->ifs[0].nsector;
1191 bus->ifs[1].hob_nsector = bus->ifs[1].nsector;
1192 bus->ifs[0].nsector = val;
1193 bus->ifs[1].nsector = val;
5391d806
FB		 1194 break;
1195 case 3:
bcbdc4d3
GH		 1196 ide_clear_hob(bus);
1197 bus->ifs[0].hob_sector = bus->ifs[0].sector;
1198 bus->ifs[1].hob_sector = bus->ifs[1].sector;
1199 bus->ifs[0].sector = val;
1200 bus->ifs[1].sector = val;
5391d806
FB		 1201 break;
1202 case 4:
bcbdc4d3
GH		 1203 ide_clear_hob(bus);
1204 bus->ifs[0].hob_lcyl = bus->ifs[0].lcyl;
1205 bus->ifs[1].hob_lcyl = bus->ifs[1].lcyl;
1206 bus->ifs[0].lcyl = val;
1207 bus->ifs[1].lcyl = val;
5391d806
FB		 1208 break;
1209 case 5:
bcbdc4d3
GH		 1210 ide_clear_hob(bus);
1211 bus->ifs[0].hob_hcyl = bus->ifs[0].hcyl;
1212 bus->ifs[1].hob_hcyl = bus->ifs[1].hcyl;
1213 bus->ifs[0].hcyl = val;
1214 bus->ifs[1].hcyl = val;
5391d806
FB		 1215 break;
1216 case 6:
c2ff060f 1217 /* FIXME: HOB readback uses bit 7 */
bcbdc4d3
GH		 1218 bus->ifs[0].select = (val & ~0x10) | 0xa0;
1219 bus->ifs[1].select = (val | 0x10) | 0xa0;
5391d806 1220 /* select drive */
bcbdc4d3 1221 bus->unit = (val >> 4) & 1;
5391d806
FB		 1222 break;
1223 default:
1224 case 7:
1225 /* command */
7cff87ff
AG		 1226 ide_exec_cmd(bus, val);
1227 break;
1228 }
1229}
1230
4590355b
JS		 1231static void ide_reset(IDEState *s)
1232{
1233#ifdef DEBUG_IDE
1234 printf("ide: reset\n");
1235#endif
1236
1237 if (s->pio_aiocb) {
1238 blk_aio_cancel(s->pio_aiocb);
1239 s->pio_aiocb = NULL;
1240 }
1241
1242 if (s->drive_kind == IDE_CFATA)
1243 s->mult_sectors = 0;
1244 else
1245 s->mult_sectors = MAX_MULT_SECTORS;
1246 /* ide regs */
1247 s->feature = 0;
1248 s->error = 0;
1249 s->nsector = 0;
1250 s->sector = 0;
1251 s->lcyl = 0;
1252 s->hcyl = 0;
1253
1254 /* lba48 */
1255 s->hob_feature = 0;
1256 s->hob_sector = 0;
1257 s->hob_nsector = 0;
1258 s->hob_lcyl = 0;
1259 s->hob_hcyl = 0;
1260
1261 s->select = 0xa0;
1262 s->status = READY_STAT | SEEK_STAT;
1263
1264 s->lba48 = 0;
1265
1266 /* ATAPI specific */
1267 s->sense_key = 0;
1268 s->asc = 0;
1269 s->cdrom_changed = 0;
1270 s->packet_transfer_size = 0;
1271 s->elementary_transfer_size = 0;
1272 s->io_buffer_index = 0;
1273 s->cd_sector_size = 0;
1274 s->atapi_dma = 0;
1275 s->tray_locked = 0;
1276 s->tray_open = 0;
1277 /* ATA DMA state */
1278 s->io_buffer_size = 0;
1279 s->req_nb_sectors = 0;
1280
1281 ide_set_signature(s);
1282 /* init the transfer handler so that 0xffff is returned on data
1283 accesses */
1284 s->end_transfer_func = ide_dummy_transfer_stop;
1285 ide_dummy_transfer_stop(s);
1286 s->media_changed = 0;
1287}
1288
b300337e
KW		 1289static bool cmd_nop(IDEState *s, uint8_t cmd)
1290{
1291 return true;
1292}
1293
f34ae00d
JS		 1294static bool cmd_device_reset(IDEState *s, uint8_t cmd)
1295{
1296 /* Halt PIO (in the DRQ phase), then DMA */
1297 ide_transfer_cancel(s);
1298 ide_cancel_dma_sync(s);
1299
1300 /* Reset any PIO commands, reset signature, etc */
1301 ide_reset(s);
1302
1303 /* RESET: ATA8-ACS3 7.10.4 "Normal Outputs";
1304 * ATA8-ACS3 Table 184 "Device Signatures for Normal Output" */
1305 s->status = 0x00;
1306
1307 /* Do not overwrite status register */
1308 return false;
1309}
1310
4286434c
KW		 1311static bool cmd_data_set_management(IDEState *s, uint8_t cmd)
1312{
1313 switch (s->feature) {
1314 case DSM_TRIM:
4be74634 1315 if (s->blk) {
4286434c
KW		 1316 ide_sector_start_dma(s, IDE_DMA_TRIM);
1317 return false;
1318 }
1319 break;
1320 }
1321
1322 ide_abort_command(s);
1323 return true;
1324}
1325
1c66869a
KW		 1326static bool cmd_identify(IDEState *s, uint8_t cmd)
1327{
4be74634 1328 if (s->blk && s->drive_kind != IDE_CD) {
1c66869a
KW		 1329 if (s->drive_kind != IDE_CFATA) {
1330 ide_identify(s);
1331 } else {
1332 ide_cfata_identify(s);
1333 }
1334 s->status = READY_STAT | SEEK_STAT;
1335 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
1336 ide_set_irq(s->bus);
1337 return false;
1338 } else {
1339 if (s->drive_kind == IDE_CD) {
1340 ide_set_signature(s);
1341 }
1342 ide_abort_command(s);
1343 }
1344
1345 return true;
1346}
1347
413860cf
KW		 1348static bool cmd_verify(IDEState *s, uint8_t cmd)
1349{
1350 bool lba48 = (cmd == WIN_VERIFY_EXT);
1351
1352 /* do sector number check ? */
1353 ide_cmd_lba48_transform(s, lba48);
1354
1355 return true;
1356}
1357
adf3a2c4
KW		 1358static bool cmd_set_multiple_mode(IDEState *s, uint8_t cmd)
1359{
1360 if (s->drive_kind == IDE_CFATA && s->nsector == 0) {
1361 /* Disable Read and Write Multiple */
1362 s->mult_sectors = 0;
1363 } else if ((s->nsector & 0xff) != 0 &&
1364 ((s->nsector & 0xff) > MAX_MULT_SECTORS ||
1365 (s->nsector & (s->nsector - 1)) != 0)) {
1366 ide_abort_command(s);
1367 } else {
1368 s->mult_sectors = s->nsector & 0xff;
1369 }
1370
1371 return true;
1372}
1373
1374static bool cmd_read_multiple(IDEState *s, uint8_t cmd)
1375{
1376 bool lba48 = (cmd == WIN_MULTREAD_EXT);
1377
4be74634 1378 if (!s->blk || !s->mult_sectors) {
adf3a2c4
KW		 1379 ide_abort_command(s);
1380 return true;
1381 }
1382
1383 ide_cmd_lba48_transform(s, lba48);
1384 s->req_nb_sectors = s->mult_sectors;
1385 ide_sector_read(s);
1386 return false;
1387}
1388
1389static bool cmd_write_multiple(IDEState *s, uint8_t cmd)
1390{
1391 bool lba48 = (cmd == WIN_MULTWRITE_EXT);
1392 int n;
1393
4be74634 1394 if (!s->blk || !s->mult_sectors) {
adf3a2c4
KW		 1395 ide_abort_command(s);
1396 return true;
1397 }
1398
1399 ide_cmd_lba48_transform(s, lba48);
1400
1401 s->req_nb_sectors = s->mult_sectors;
1402 n = MIN(s->nsector, s->req_nb_sectors);
1403
1404 s->status = SEEK_STAT | READY_STAT;
1405 ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_write);
1406
1407 s->media_changed = 1;
1408
1409 return false;
1410}
1411
0e6498ed
KW		 1412static bool cmd_read_pio(IDEState *s, uint8_t cmd)
1413{
1414 bool lba48 = (cmd == WIN_READ_EXT);
1415
1416 if (s->drive_kind == IDE_CD) {
1417 ide_set_signature(s); /* odd, but ATA4 8.27.5.2 requires it */
1418 ide_abort_command(s);
1419 return true;
1420 }
1421
4be74634 1422 if (!s->blk) {
0e6498ed
KW		 1423 ide_abort_command(s);
1424 return true;
1425 }
1426
1427 ide_cmd_lba48_transform(s, lba48);
1428 s->req_nb_sectors = 1;
1429 ide_sector_read(s);
1430
1431 return false;
1432}
1433
1434static bool cmd_write_pio(IDEState *s, uint8_t cmd)
1435{
1436 bool lba48 = (cmd == WIN_WRITE_EXT);
1437
4be74634 1438 if (!s->blk) {
0e6498ed
KW		 1439 ide_abort_command(s);
1440 return true;
1441 }
1442
1443 ide_cmd_lba48_transform(s, lba48);
1444
1445 s->req_nb_sectors = 1;
1446 s->status = SEEK_STAT | READY_STAT;
1447 ide_transfer_start(s, s->io_buffer, 512, ide_sector_write);
1448
1449 s->media_changed = 1;
1450
1451 return false;
1452}
1453
92a6a6f6
KW		 1454static bool cmd_read_dma(IDEState *s, uint8_t cmd)
1455{
1456 bool lba48 = (cmd == WIN_READDMA_EXT);
1457
4be74634 1458 if (!s->blk) {
92a6a6f6
KW		 1459 ide_abort_command(s);
1460 return true;
1461 }
1462
1463 ide_cmd_lba48_transform(s, lba48);
1464 ide_sector_start_dma(s, IDE_DMA_READ);
1465
1466 return false;
1467}
1468
1469static bool cmd_write_dma(IDEState *s, uint8_t cmd)
1470{
1471 bool lba48 = (cmd == WIN_WRITEDMA_EXT);
1472
4be74634 1473 if (!s->blk) {
92a6a6f6
KW		 1474 ide_abort_command(s);
1475 return true;
1476 }
1477
1478 ide_cmd_lba48_transform(s, lba48);
1479 ide_sector_start_dma(s, IDE_DMA_WRITE);
1480
1481 s->media_changed = 1;
1482
1483 return false;
1484}
1485
9afce429
KW		 1486static bool cmd_flush_cache(IDEState *s, uint8_t cmd)
1487{
1488 ide_flush_cache(s);
1489 return false;
1490}
1491
61fdda37
KW		 1492static bool cmd_seek(IDEState *s, uint8_t cmd)
1493{
1494 /* XXX: Check that seek is within bounds */
1495 return true;
1496}
1497
63a82e6a
KW		 1498static bool cmd_read_native_max(IDEState *s, uint8_t cmd)
1499{
1500 bool lba48 = (cmd == WIN_READ_NATIVE_MAX_EXT);
1501
1502 /* Refuse if no sectors are addressable (e.g. medium not inserted) */
1503 if (s->nb_sectors == 0) {
1504 ide_abort_command(s);
1505 return true;
1506 }
1507
1508 ide_cmd_lba48_transform(s, lba48);
1509 ide_set_sector(s, s->nb_sectors - 1);
1510
1511 return true;
1512}
1513
785f6320
KW		 1514static bool cmd_check_power_mode(IDEState *s, uint8_t cmd)
1515{
1516 s->nsector = 0xff; /* device active or idle */
1517 return true;
1518}
1519
ee03398c
KW		 1520static bool cmd_set_features(IDEState *s, uint8_t cmd)
1521{
1522 uint16_t *identify_data;
1523
4be74634 1524 if (!s->blk) {
ee03398c
KW		 1525 ide_abort_command(s);
1526 return true;
1527 }
1528
1529 /* XXX: valid for CDROM ? */
1530 switch (s->feature) {
1531 case 0x02: /* write cache enable */
4be74634 1532 blk_set_enable_write_cache(s->blk, true);
ee03398c
KW		 1533 identify_data = (uint16_t *)s->identify_data;
1534 put_le16(identify_data + 85, (1 << 14) | (1 << 5) | 1);
1535 return true;
1536 case 0x82: /* write cache disable */
4be74634 1537 blk_set_enable_write_cache(s->blk, false);
ee03398c
KW		 1538 identify_data = (uint16_t *)s->identify_data;
1539 put_le16(identify_data + 85, (1 << 14) | 1);
1540 ide_flush_cache(s);
1541 return false;
1542 case 0xcc: /* reverting to power-on defaults enable */
1543 case 0x66: /* reverting to power-on defaults disable */
1544 case 0xaa: /* read look-ahead enable */
1545 case 0x55: /* read look-ahead disable */
1546 case 0x05: /* set advanced power management mode */
1547 case 0x85: /* disable advanced power management mode */
1548 case 0x69: /* NOP */
1549 case 0x67: /* NOP */
1550 case 0x96: /* NOP */
1551 case 0x9a: /* NOP */
1552 case 0x42: /* enable Automatic Acoustic Mode */
1553 case 0xc2: /* disable Automatic Acoustic Mode */
1554 return true;
1555 case 0x03: /* set transfer mode */
1556 {
1557 uint8_t val = s->nsector & 0x07;
1558 identify_data = (uint16_t *)s->identify_data;
1559
1560 switch (s->nsector >> 3) {
1561 case 0x00: /* pio default */
1562 case 0x01: /* pio mode */
1563 put_le16(identify_data + 62, 0x07);
1564 put_le16(identify_data + 63, 0x07);
1565 put_le16(identify_data + 88, 0x3f);
1566 break;
1567 case 0x02: /* sigle word dma mode*/
1568 put_le16(identify_data + 62, 0x07 | (1 << (val + 8)));
1569 put_le16(identify_data + 63, 0x07);
1570 put_le16(identify_data + 88, 0x3f);
1571 break;
1572 case 0x04: /* mdma mode */
1573 put_le16(identify_data + 62, 0x07);
1574 put_le16(identify_data + 63, 0x07 | (1 << (val + 8)));
1575 put_le16(identify_data + 88, 0x3f);
1576 break;
1577 case 0x08: /* udma mode */
1578 put_le16(identify_data + 62, 0x07);
1579 put_le16(identify_data + 63, 0x07);
1580 put_le16(identify_data + 88, 0x3f | (1 << (val + 8)));
1581 break;
1582 default:
1583 goto abort_cmd;
1584 }
1585 return true;
1586 }
1587 }
1588
1589abort_cmd:
1590 ide_abort_command(s);
1591 return true;
1592}
1593
ee425c78
KW		 1594
1595/*** ATAPI commands ***/
1596
1597static bool cmd_identify_packet(IDEState *s, uint8_t cmd)
1598{
1599 ide_atapi_identify(s);
1600 s->status = READY_STAT | SEEK_STAT;
1601 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
1602 ide_set_irq(s->bus);
1603 return false;
1604}
1605
1606static bool cmd_exec_dev_diagnostic(IDEState *s, uint8_t cmd)
1607{
1608 ide_set_signature(s);
1609
1610 if (s->drive_kind == IDE_CD) {
1611 s->status = 0; /* ATAPI spec (v6) section 9.10 defines packet
1612 * devices to return a clear status register
1613 * with READY_STAT *not* set. */
850484a2 1614 s->error = 0x01;
ee425c78
KW		 1615 } else {
1616 s->status = READY_STAT | SEEK_STAT;
1617 /* The bits of the error register are not as usual for this command!
1618 * They are part of the regular output (this is why ERR_STAT isn't set)
1619 * Device 0 passed, Device 1 passed or not present. */
1620 s->error = 0x01;
1621 ide_set_irq(s->bus);
1622 }
1623
1624 return false;
1625}
1626
ee425c78
KW		 1627static bool cmd_packet(IDEState *s, uint8_t cmd)
1628{
1629 /* overlapping commands not supported */
1630 if (s->feature & 0x02) {
1631 ide_abort_command(s);
1632 return true;
1633 }
1634
1635 s->status = READY_STAT | SEEK_STAT;
1636 s->atapi_dma = s->feature & 1;
1637 s->nsector = 1;
1638 ide_transfer_start(s, s->io_buffer, ATAPI_PACKET_SIZE,
1639 ide_atapi_cmd);
1640 return false;
1641}
1642
6b1dd744
KW		 1643
1644/*** CF-ATA commands ***/
1645
1646static bool cmd_cfa_req_ext_error_code(IDEState *s, uint8_t cmd)
1647{
1648 s->error = 0x09; /* miscellaneous error */
1649 s->status = READY_STAT | SEEK_STAT;
1650 ide_set_irq(s->bus);
1651
1652 return false;
1653}
1654
1655static bool cmd_cfa_erase_sectors(IDEState *s, uint8_t cmd)
1656{
1657 /* WIN_SECURITY_FREEZE_LOCK has the same ID as CFA_WEAR_LEVEL and is
1658 * required for Windows 8 to work with AHCI */
1659
1660 if (cmd == CFA_WEAR_LEVEL) {
1661 s->nsector = 0;
1662 }
1663
1664 if (cmd == CFA_ERASE_SECTORS) {
1665 s->media_changed = 1;
1666 }
1667
1668 return true;
1669}
1670
1671static bool cmd_cfa_translate_sector(IDEState *s, uint8_t cmd)
1672{
1673 s->status = READY_STAT | SEEK_STAT;
1674
1675 memset(s->io_buffer, 0, 0x200);
1676 s->io_buffer[0x00] = s->hcyl; /* Cyl MSB */
1677 s->io_buffer[0x01] = s->lcyl; /* Cyl LSB */
1678 s->io_buffer[0x02] = s->select; /* Head */
1679 s->io_buffer[0x03] = s->sector; /* Sector */
1680 s->io_buffer[0x04] = ide_get_sector(s) >> 16; /* LBA MSB */
1681 s->io_buffer[0x05] = ide_get_sector(s) >> 8; /* LBA */
1682 s->io_buffer[0x06] = ide_get_sector(s) >> 0; /* LBA LSB */
1683 s->io_buffer[0x13] = 0x00; /* Erase flag */
1684 s->io_buffer[0x18] = 0x00; /* Hot count */
1685 s->io_buffer[0x19] = 0x00; /* Hot count */
1686 s->io_buffer[0x1a] = 0x01; /* Hot count */
1687
1688 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1689 ide_set_irq(s->bus);
1690
1691 return false;
1692}
1693
1694static bool cmd_cfa_access_metadata_storage(IDEState *s, uint8_t cmd)
1695{
1696 switch (s->feature) {
1697 case 0x02: /* Inquiry Metadata Storage */
1698 ide_cfata_metadata_inquiry(s);
1699 break;
1700 case 0x03: /* Read Metadata Storage */
1701 ide_cfata_metadata_read(s);
1702 break;
1703 case 0x04: /* Write Metadata Storage */
1704 ide_cfata_metadata_write(s);
1705 break;
1706 default:
1707 ide_abort_command(s);
1708 return true;
1709 }
1710
1711 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1712 s->status = 0x00; /* NOTE: READY is _not_ set */
1713 ide_set_irq(s->bus);
1714
1715 return false;
1716}
1717
1718static bool cmd_ibm_sense_condition(IDEState *s, uint8_t cmd)
1719{
1720 switch (s->feature) {
1721 case 0x01: /* sense temperature in device */
1722 s->nsector = 0x50; /* +20 C */
1723 break;
1724 default:
1725 ide_abort_command(s);
1726 return true;
1727 }
1728
1729 return true;
1730}
1731
ff352677
KW		 1732
1733/*** SMART commands ***/
1734
1735static bool cmd_smart(IDEState *s, uint8_t cmd)
1736{
1737 int n;
1738
1739 if (s->hcyl != 0xc2 || s->lcyl != 0x4f) {
1740 goto abort_cmd;
1741 }
1742
1743 if (!s->smart_enabled && s->feature != SMART_ENABLE) {
1744 goto abort_cmd;
1745 }
1746
1747 switch (s->feature) {
1748 case SMART_DISABLE:
1749 s->smart_enabled = 0;
1750 return true;
1751
1752 case SMART_ENABLE:
1753 s->smart_enabled = 1;
1754 return true;
1755
1756 case SMART_ATTR_AUTOSAVE:
1757 switch (s->sector) {
1758 case 0x00:
1759 s->smart_autosave = 0;
1760 break;
1761 case 0xf1:
1762 s->smart_autosave = 1;
1763 break;
1764 default:
1765 goto abort_cmd;
1766 }
1767 return true;
1768
1769 case SMART_STATUS:
1770 if (!s->smart_errors) {
1771 s->hcyl = 0xc2;
1772 s->lcyl = 0x4f;
1773 } else {
1774 s->hcyl = 0x2c;
1775 s->lcyl = 0xf4;
1776 }
1777 return true;
1778
1779 case SMART_READ_THRESH:
1780 memset(s->io_buffer, 0, 0x200);
1781 s->io_buffer[0] = 0x01; /* smart struct version */
1782
1783 for (n = 0; n < ARRAY_SIZE(smart_attributes); n++) {
1784 s->io_buffer[2 + 0 + (n * 12)] = smart_attributes[n][0];
1785 s->io_buffer[2 + 1 + (n * 12)] = smart_attributes[n][11];
1786 }
1787
1788 /* checksum */
1789 for (n = 0; n < 511; n++) {
1790 s->io_buffer[511] += s->io_buffer[n];
1791 }
1792 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1793
1794 s->status = READY_STAT | SEEK_STAT;
1795 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1796 ide_set_irq(s->bus);
1797 return false;
1798
1799 case SMART_READ_DATA:
1800 memset(s->io_buffer, 0, 0x200);
1801 s->io_buffer[0] = 0x01; /* smart struct version */
1802
1803 for (n = 0; n < ARRAY_SIZE(smart_attributes); n++) {
1804 int i;
1805 for (i = 0; i < 11; i++) {
1806 s->io_buffer[2 + i + (n * 12)] = smart_attributes[n][i];
1807 }
1808 }
1809
1810 s->io_buffer[362] = 0x02 | (s->smart_autosave ? 0x80 : 0x00);
1811 if (s->smart_selftest_count == 0) {
1812 s->io_buffer[363] = 0;
1813 } else {
1814 s->io_buffer[363] =
1815 s->smart_selftest_data[3 +
1816 (s->smart_selftest_count - 1) *
1817 24];
1818 }
1819 s->io_buffer[364] = 0x20;
1820 s->io_buffer[365] = 0x01;
1821 /* offline data collection capacity: execute + self-test*/
1822 s->io_buffer[367] = (1 << 4 | 1 << 3 | 1);
1823 s->io_buffer[368] = 0x03; /* smart capability (1) */
1824 s->io_buffer[369] = 0x00; /* smart capability (2) */
1825 s->io_buffer[370] = 0x01; /* error logging supported */
1826 s->io_buffer[372] = 0x02; /* minutes for poll short test */
1827 s->io_buffer[373] = 0x36; /* minutes for poll ext test */
1828 s->io_buffer[374] = 0x01; /* minutes for poll conveyance */
1829
1830 for (n = 0; n < 511; n++) {
1831 s->io_buffer[511] += s->io_buffer[n];
1832 }
1833 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1834
1835 s->status = READY_STAT | SEEK_STAT;
1836 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1837 ide_set_irq(s->bus);
1838 return false;
1839
1840 case SMART_READ_LOG:
1841 switch (s->sector) {
1842 case 0x01: /* summary smart error log */
1843 memset(s->io_buffer, 0, 0x200);
1844 s->io_buffer[0] = 0x01;
1845 s->io_buffer[1] = 0x00; /* no error entries */
1846 s->io_buffer[452] = s->smart_errors & 0xff;
1847 s->io_buffer[453] = (s->smart_errors & 0xff00) >> 8;
1848
1849 for (n = 0; n < 511; n++) {
1850 s->io_buffer[511] += s->io_buffer[n];
1851 }
1852 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1853 break;
1854 case 0x06: /* smart self test log */
1855 memset(s->io_buffer, 0, 0x200);
1856 s->io_buffer[0] = 0x01;
1857 if (s->smart_selftest_count == 0) {
1858 s->io_buffer[508] = 0;
1859 } else {
1860 s->io_buffer[508] = s->smart_selftest_count;
1861 for (n = 2; n < 506; n++) {
1862 s->io_buffer[n] = s->smart_selftest_data[n];
1863 }
1864 }
1865
1866 for (n = 0; n < 511; n++) {
1867 s->io_buffer[511] += s->io_buffer[n];
1868 }
1869 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1870 break;
1871 default:
1872 goto abort_cmd;
1873 }
1874 s->status = READY_STAT | SEEK_STAT;
1875 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1876 ide_set_irq(s->bus);
1877 return false;
1878
1879 case SMART_EXECUTE_OFFLINE:
1880 switch (s->sector) {
1881 case 0: /* off-line routine */
1882 case 1: /* short self test */
1883 case 2: /* extended self test */
1884 s->smart_selftest_count++;
1885 if (s->smart_selftest_count > 21) {
940973ae 1886 s->smart_selftest_count = 1;
ff352677
KW		 1887 }
1888 n = 2 + (s->smart_selftest_count - 1) * 24;
1889 s->smart_selftest_data[n] = s->sector;
1890 s->smart_selftest_data[n + 1] = 0x00; /* OK and finished */
1891 s->smart_selftest_data[n + 2] = 0x34; /* hour count lsb */
1892 s->smart_selftest_data[n + 3] = 0x12; /* hour count msb */
1893 break;
1894 default:
1895 goto abort_cmd;
1896 }
1897 return true;
1898 }
1899
1900abort_cmd:
1901 ide_abort_command(s);
1902 return true;
1903}
1904
844505b1
MA		 1905#define HD_OK (1u << IDE_HD)
1906#define CD_OK (1u << IDE_CD)
1907#define CFA_OK (1u << IDE_CFATA)
1908#define HD_CFA_OK (HD_OK | CFA_OK)
1909#define ALL_OK (HD_OK | CD_OK | CFA_OK)
1910
a0436e92
KW		 1911/* Set the Disk Seek Completed status bit during completion */
1912#define SET_DSC (1u << 8)
1913
844505b1 1914/* See ACS-2 T13/2015-D Table B.2 Command codes */
a0436e92
KW		 1915static const struct {
1916 /* Returns true if the completion code should be run */
1917 bool (*handler)(IDEState *s, uint8_t cmd);
1918 int flags;
1919} ide_cmd_table[0x100] = {
844505b1 1920 /* NOP not implemented, mandatory for CD */
6b1dd744 1921 [CFA_REQ_EXT_ERROR_CODE] = { cmd_cfa_req_ext_error_code, CFA_OK },
d9033e1d 1922 [WIN_DSM] = { cmd_data_set_management, HD_CFA_OK },
ee425c78 1923 [WIN_DEVICE_RESET] = { cmd_device_reset, CD_OK },
b300337e 1924 [WIN_RECAL] = { cmd_nop, HD_CFA_OK | SET_DSC},
0e6498ed 1925 [WIN_READ] = { cmd_read_pio, ALL_OK },
d9033e1d 1926 [WIN_READ_ONCE] = { cmd_read_pio, HD_CFA_OK },
0e6498ed 1927 [WIN_READ_EXT] = { cmd_read_pio, HD_CFA_OK },
92a6a6f6 1928 [WIN_READDMA_EXT] = { cmd_read_dma, HD_CFA_OK },
63a82e6a 1929 [WIN_READ_NATIVE_MAX_EXT] = { cmd_read_native_max, HD_CFA_OK | SET_DSC },
adf3a2c4 1930 [WIN_MULTREAD_EXT] = { cmd_read_multiple, HD_CFA_OK },
0e6498ed
KW		 1931 [WIN_WRITE] = { cmd_write_pio, HD_CFA_OK },
1932 [WIN_WRITE_ONCE] = { cmd_write_pio, HD_CFA_OK },
1933 [WIN_WRITE_EXT] = { cmd_write_pio, HD_CFA_OK },
92a6a6f6 1934 [WIN_WRITEDMA_EXT] = { cmd_write_dma, HD_CFA_OK },
0e6498ed 1935 [CFA_WRITE_SECT_WO_ERASE] = { cmd_write_pio, CFA_OK },
adf3a2c4 1936 [WIN_MULTWRITE_EXT] = { cmd_write_multiple, HD_CFA_OK },
0e6498ed 1937 [WIN_WRITE_VERIFY] = { cmd_write_pio, HD_CFA_OK },
413860cf
KW		 1938 [WIN_VERIFY] = { cmd_verify, HD_CFA_OK | SET_DSC },
1939 [WIN_VERIFY_ONCE] = { cmd_verify, HD_CFA_OK | SET_DSC },
1940 [WIN_VERIFY_EXT] = { cmd_verify, HD_CFA_OK | SET_DSC },
61fdda37 1941 [WIN_SEEK] = { cmd_seek, HD_CFA_OK | SET_DSC },
6b1dd744 1942 [CFA_TRANSLATE_SECTOR] = { cmd_cfa_translate_sector, CFA_OK },
ee425c78 1943 [WIN_DIAGNOSE] = { cmd_exec_dev_diagnostic, ALL_OK },
b300337e 1944 [WIN_SPECIFY] = { cmd_nop, HD_CFA_OK | SET_DSC },
d9033e1d
JS		 1945 [WIN_STANDBYNOW2] = { cmd_nop, HD_CFA_OK },
1946 [WIN_IDLEIMMEDIATE2] = { cmd_nop, HD_CFA_OK },
1947 [WIN_STANDBY2] = { cmd_nop, HD_CFA_OK },
1948 [WIN_SETIDLE2] = { cmd_nop, HD_CFA_OK },
1949 [WIN_CHECKPOWERMODE2] = { cmd_check_power_mode, HD_CFA_OK | SET_DSC },
1950 [WIN_SLEEPNOW2] = { cmd_nop, HD_CFA_OK },
ee425c78
KW		 1951 [WIN_PACKETCMD] = { cmd_packet, CD_OK },
1952 [WIN_PIDENTIFY] = { cmd_identify_packet, CD_OK },
ff352677 1953 [WIN_SMART] = { cmd_smart, HD_CFA_OK | SET_DSC },
6b1dd744
KW		 1954 [CFA_ACCESS_METADATA_STORAGE] = { cmd_cfa_access_metadata_storage, CFA_OK },
1955 [CFA_ERASE_SECTORS] = { cmd_cfa_erase_sectors, CFA_OK | SET_DSC },
adf3a2c4
KW		 1956 [WIN_MULTREAD] = { cmd_read_multiple, HD_CFA_OK },
1957 [WIN_MULTWRITE] = { cmd_write_multiple, HD_CFA_OK },
1958 [WIN_SETMULT] = { cmd_set_multiple_mode, HD_CFA_OK | SET_DSC },
92a6a6f6
KW		 1959 [WIN_READDMA] = { cmd_read_dma, HD_CFA_OK },
1960 [WIN_READDMA_ONCE] = { cmd_read_dma, HD_CFA_OK },
1961 [WIN_WRITEDMA] = { cmd_write_dma, HD_CFA_OK },
1962 [WIN_WRITEDMA_ONCE] = { cmd_write_dma, HD_CFA_OK },
adf3a2c4 1963 [CFA_WRITE_MULTI_WO_ERASE] = { cmd_write_multiple, CFA_OK },
d9033e1d
JS		 1964 [WIN_STANDBYNOW1] = { cmd_nop, HD_CFA_OK },
1965 [WIN_IDLEIMMEDIATE] = { cmd_nop, HD_CFA_OK },
1966 [WIN_STANDBY] = { cmd_nop, HD_CFA_OK },
1967 [WIN_SETIDLE1] = { cmd_nop, HD_CFA_OK },
1968 [WIN_CHECKPOWERMODE1] = { cmd_check_power_mode, HD_CFA_OK | SET_DSC },
1969 [WIN_SLEEPNOW1] = { cmd_nop, HD_CFA_OK },
9afce429
KW		 1970 [WIN_FLUSH_CACHE] = { cmd_flush_cache, ALL_OK },
1971 [WIN_FLUSH_CACHE_EXT] = { cmd_flush_cache, HD_CFA_OK },
1c66869a 1972 [WIN_IDENTIFY] = { cmd_identify, ALL_OK },
ee03398c 1973 [WIN_SETFEATURES] = { cmd_set_features, ALL_OK | SET_DSC },
6b1dd744
KW		 1974 [IBM_SENSE_CONDITION] = { cmd_ibm_sense_condition, CFA_OK | SET_DSC },
1975 [CFA_WEAR_LEVEL] = { cmd_cfa_erase_sectors, HD_CFA_OK | SET_DSC },
d9033e1d 1976 [WIN_READ_NATIVE_MAX] = { cmd_read_native_max, HD_CFA_OK | SET_DSC },
844505b1
MA		 1977};
1978
1979static bool ide_cmd_permitted(IDEState *s, uint32_t cmd)
1980{
1981 return cmd < ARRAY_SIZE(ide_cmd_table)
a0436e92 1982 && (ide_cmd_table[cmd].flags & (1u << s->drive_kind));
844505b1 1983}
7cff87ff
AG		 1984
1985void ide_exec_cmd(IDEBus *bus, uint32_t val)
1986{
1987 IDEState *s;
dfe1ea8f 1988 bool complete;
7cff87ff 1989
5391d806 1990#if defined(DEBUG_IDE)
6ef2ba5e 1991 printf("ide: CMD=%02x\n", val);
5391d806 1992#endif
6ef2ba5e 1993 s = idebus_active_if(bus);
66a0a2cb 1994 /* ignore commands to non existent slave */
4be74634 1995 if (s != bus->ifs && !s->blk) {
6ef2ba5e 1996 return;
4be74634 1997 }
c2ff060f 1998
266e7781
JS		 1999 /* Only RESET is allowed while BSY and/or DRQ are set,
2000 * and only to ATAPI devices. */
2001 if (s->status & (BUSY_STAT|DRQ_STAT)) {
2002 if (val != WIN_DEVICE_RESET || s->drive_kind != IDE_CD) {
2003 return;
2004 }
2005 }
fcdd25ab 2006
844505b1 2007 if (!ide_cmd_permitted(s, val)) {
dfe1ea8f
KW		 2008 ide_abort_command(s);
2009 ide_set_irq(s->bus);
2010 return;
844505b1
MA		 2011 }
2012
dfe1ea8f
KW		 2013 s->status = READY_STAT | BUSY_STAT;
2014 s->error = 0;
36334faf 2015 s->io_buffer_offset = 0;
a0436e92 2016
dfe1ea8f
KW		 2017 complete = ide_cmd_table[val].handler(s, val);
2018 if (complete) {
2019 s->status &= ~BUSY_STAT;
2020 assert(!!s->error == !!(s->status & ERR_STAT));
a0436e92 2021
dfe1ea8f
KW		 2022 if ((ide_cmd_table[val].flags & SET_DSC) && !s->error) {
2023 s->status |= SEEK_STAT;
a0436e92
KW		 2024 }
2025
c7e73adb 2026 ide_cmd_done(s);
6ef2ba5e 2027 ide_set_irq(s->bus);
6ef2ba5e 2028 }
5391d806
FB		 2029}
2030
356721ae 2031uint32_t ide_ioport_read(void *opaque, uint32_t addr1)
5391d806 2032{
bcbdc4d3
GH		 2033 IDEBus *bus = opaque;
2034 IDEState *s = idebus_active_if(bus);
5391d806 2035 uint32_t addr;
c2ff060f 2036 int ret, hob;
5391d806
FB		 2037
2038 addr = addr1 & 7;
c2ff060f
FB		 2039 /* FIXME: HOB readback uses bit 7, but it's always set right now */
2040 //hob = s->select & (1 << 7);
2041 hob = 0;
5391d806
FB		 2042 switch(addr) {
2043 case 0:
2044 ret = 0xff;
2045 break;
2046 case 1:
4be74634
MA		 2047 if ((!bus->ifs[0].blk && !bus->ifs[1].blk) ||
2048 (s != bus->ifs && !s->blk)) {
c45c3d00 2049 ret = 0;
4be74634 2050 } else if (!hob) {
c45c3d00 2051 ret = s->error;
4be74634 2052 } else {
c2ff060f 2053 ret = s->hob_feature;
4be74634 2054 }
5391d806
FB		 2055 break;
2056 case 2:
4be74634 2057 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
c45c3d00 2058 ret = 0;
4be74634 2059 } else if (!hob) {
c45c3d00 2060 ret = s->nsector & 0xff;
4be74634 2061 } else {
c2ff060f 2062 ret = s->hob_nsector;
4be74634 2063 }
5391d806
FB		 2064 break;
2065 case 3:
4be74634 2066 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
c45c3d00 2067 ret = 0;
4be74634 2068 } else if (!hob) {
c45c3d00 2069 ret = s->sector;
4be74634 2070 } else {
c2ff060f 2071 ret = s->hob_sector;
4be74634 2072 }
5391d806
FB		 2073 break;
2074 case 4:
4be74634 2075 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
c45c3d00 2076 ret = 0;
4be74634 2077 } else if (!hob) {
c45c3d00 2078 ret = s->lcyl;
4be74634 2079 } else {
c2ff060f 2080 ret = s->hob_lcyl;
4be74634 2081 }
5391d806
FB		 2082 break;
2083 case 5:
4be74634 2084 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
c45c3d00 2085 ret = 0;
4be74634 2086 } else if (!hob) {
c45c3d00 2087 ret = s->hcyl;
4be74634 2088 } else {
c2ff060f 2089 ret = s->hob_hcyl;
4be74634 2090 }
5391d806
FB		 2091 break;
2092 case 6:
4be74634 2093 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
c45c3d00 2094 ret = 0;
4be74634 2095 } else {
7ae98627 2096 ret = s->select;
4be74634 2097 }
5391d806
FB		 2098 break;
2099 default:
2100 case 7:
4be74634
MA		 2101 if ((!bus->ifs[0].blk && !bus->ifs[1].blk) ||
2102 (s != bus->ifs && !s->blk)) {
c45c3d00 2103 ret = 0;
4be74634 2104 } else {
c45c3d00 2105 ret = s->status;
4be74634 2106 }
9cdd03a7 2107 qemu_irq_lower(bus->irq);
5391d806
FB		 2108 break;
2109 }
2110#ifdef DEBUG_IDE
2111 printf("ide: read addr=0x%x val=%02x\n", addr1, ret);
2112#endif
2113 return ret;
2114}
2115
356721ae 2116uint32_t ide_status_read(void *opaque, uint32_t addr)
5391d806 2117{
bcbdc4d3
GH		 2118 IDEBus *bus = opaque;
2119 IDEState *s = idebus_active_if(bus);
5391d806 2120 int ret;
7ae98627 2121
4be74634
MA		 2122 if ((!bus->ifs[0].blk && !bus->ifs[1].blk) ||
2123 (s != bus->ifs && !s->blk)) {
7ae98627 2124 ret = 0;
4be74634 2125 } else {
7ae98627 2126 ret = s->status;
4be74634 2127 }
5391d806
FB		 2128#ifdef DEBUG_IDE
2129 printf("ide: read status addr=0x%x val=%02x\n", addr, ret);
2130#endif
2131 return ret;
2132}
2133
356721ae 2134void ide_cmd_write(void *opaque, uint32_t addr, uint32_t val)
5391d806 2135{
bcbdc4d3 2136 IDEBus *bus = opaque;
5391d806
FB		 2137 IDEState *s;
2138 int i;
2139
2140#ifdef DEBUG_IDE
2141 printf("ide: write control addr=0x%x val=%02x\n", addr, val);
2142#endif
2143 /* common for both drives */
9cdd03a7 2144 if (!(bus->cmd & IDE_CMD_RESET) &&
5391d806
FB		 2145 (val & IDE_CMD_RESET)) {
2146 /* reset low to high */
2147 for(i = 0;i < 2; i++) {
bcbdc4d3 2148 s = &bus->ifs[i];
5391d806
FB		 2149 s->status = BUSY_STAT | SEEK_STAT;
2150 s->error = 0x01;
2151 }
9cdd03a7 2152 } else if ((bus->cmd & IDE_CMD_RESET) &&
5391d806
FB		 2153 !(val & IDE_CMD_RESET)) {
2154 /* high to low */
2155 for(i = 0;i < 2; i++) {
bcbdc4d3 2156 s = &bus->ifs[i];
cd8722bb 2157 if (s->drive_kind == IDE_CD)
6b136f9e
FB		 2158 s->status = 0x00; /* NOTE: READY is _not_ set */
2159 else
56bf1d37 2160 s->status = READY_STAT | SEEK_STAT;
5391d806
FB		 2161 ide_set_signature(s);
2162 }
2163 }
2164
9cdd03a7 2165 bus->cmd = val;
5391d806
FB		 2166}
2167
40c4ed3f
KW		 2168/*
2169 * Returns true if the running PIO transfer is a PIO out (i.e. data is
2170 * transferred from the device to the guest), false if it's a PIO in
2171 */
2172static bool ide_is_pio_out(IDEState *s)
2173{
2174 if (s->end_transfer_func == ide_sector_write ||
2175 s->end_transfer_func == ide_atapi_cmd) {
2176 return false;
2177 } else if (s->end_transfer_func == ide_sector_read ||
2178 s->end_transfer_func == ide_transfer_stop ||
2179 s->end_transfer_func == ide_atapi_cmd_reply_end ||
2180 s->end_transfer_func == ide_dummy_transfer_stop) {
2181 return true;
2182 }
2183
2184 abort();
2185}
2186
356721ae 2187void ide_data_writew(void *opaque, uint32_t addr, uint32_t val)
5391d806 2188{
bcbdc4d3
GH		 2189 IDEBus *bus = opaque;
2190 IDEState *s = idebus_active_if(bus);
5391d806
FB		 2191 uint8_t *p;
2192
40c4ed3f
KW		 2193 /* PIO data access allowed only when DRQ bit is set. The result of a write
2194 * during PIO out is indeterminate, just ignore it. */
2195 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
fcdd25ab 2196 return;
40c4ed3f 2197 }
fcdd25ab 2198
5391d806 2199 p = s->data_ptr;
d2ff8585
KW		 2200 if (p + 2 > s->data_end) {
2201 return;
2202 }
2203
0c4ad8dc 2204 *(uint16_t *)p = le16_to_cpu(val);
5391d806
FB		 2205 p += 2;
2206 s->data_ptr = p;
cb72cba8
KW		 2207 if (p >= s->data_end) {
2208 s->status &= ~DRQ_STAT;
5391d806 2209 s->end_transfer_func(s);
cb72cba8 2210 }
5391d806
FB		 2211}
2212
356721ae 2213uint32_t ide_data_readw(void *opaque, uint32_t addr)
5391d806 2214{
bcbdc4d3
GH		 2215 IDEBus *bus = opaque;
2216 IDEState *s = idebus_active_if(bus);
5391d806
FB		 2217 uint8_t *p;
2218 int ret;
fcdd25ab 2219
40c4ed3f
KW		 2220 /* PIO data access allowed only when DRQ bit is set. The result of a read
2221 * during PIO in is indeterminate, return 0 and don't move forward. */
2222 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
fcdd25ab 2223 return 0;
40c4ed3f 2224 }
fcdd25ab 2225
5391d806 2226 p = s->data_ptr;
d2ff8585
KW		 2227 if (p + 2 > s->data_end) {
2228 return 0;
2229 }
2230
0c4ad8dc 2231 ret = cpu_to_le16(*(uint16_t *)p);
5391d806
FB		 2232 p += 2;
2233 s->data_ptr = p;
cb72cba8
KW		 2234 if (p >= s->data_end) {
2235 s->status &= ~DRQ_STAT;
5391d806 2236 s->end_transfer_func(s);
cb72cba8 2237 }
5391d806
FB		 2238 return ret;
2239}
2240
356721ae 2241void ide_data_writel(void *opaque, uint32_t addr, uint32_t val)
5391d806 2242{
bcbdc4d3
GH		 2243 IDEBus *bus = opaque;
2244 IDEState *s = idebus_active_if(bus);
5391d806
FB		 2245 uint8_t *p;
2246
40c4ed3f
KW		 2247 /* PIO data access allowed only when DRQ bit is set. The result of a write
2248 * during PIO out is indeterminate, just ignore it. */
2249 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
fcdd25ab 2250 return;
40c4ed3f 2251 }
fcdd25ab 2252
5391d806 2253 p = s->data_ptr;
d2ff8585
KW		 2254 if (p + 4 > s->data_end) {
2255 return;
2256 }
2257
0c4ad8dc 2258 *(uint32_t *)p = le32_to_cpu(val);
5391d806
FB		 2259 p += 4;
2260 s->data_ptr = p;
cb72cba8
KW		 2261 if (p >= s->data_end) {
2262 s->status &= ~DRQ_STAT;
5391d806 2263 s->end_transfer_func(s);
cb72cba8 2264 }
5391d806
FB		 2265}
2266
356721ae 2267uint32_t ide_data_readl(void *opaque, uint32_t addr)
5391d806 2268{
bcbdc4d3
GH		 2269 IDEBus *bus = opaque;
2270 IDEState *s = idebus_active_if(bus);
5391d806
FB		 2271 uint8_t *p;
2272 int ret;
3b46e624 2273
40c4ed3f
KW		 2274 /* PIO data access allowed only when DRQ bit is set. The result of a read
2275 * during PIO in is indeterminate, return 0 and don't move forward. */
2276 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
fcdd25ab 2277 return 0;
40c4ed3f 2278 }
fcdd25ab 2279
5391d806 2280 p = s->data_ptr;
d2ff8585
KW		 2281 if (p + 4 > s->data_end) {
2282 return 0;
2283 }
2284
0c4ad8dc 2285 ret = cpu_to_le32(*(uint32_t *)p);
5391d806
FB		 2286 p += 4;
2287 s->data_ptr = p;
cb72cba8
KW		 2288 if (p >= s->data_end) {
2289 s->status &= ~DRQ_STAT;
5391d806 2290 s->end_transfer_func(s);
cb72cba8 2291 }
5391d806
FB		 2292 return ret;
2293}
2294
a7dfe172
FB		 2295static void ide_dummy_transfer_stop(IDEState *s)
2296{
2297 s->data_ptr = s->io_buffer;
2298 s->data_end = s->io_buffer;
2299 s->io_buffer[0] = 0xff;
2300 s->io_buffer[1] = 0xff;
2301 s->io_buffer[2] = 0xff;
2302 s->io_buffer[3] = 0xff;
2303}
2304
4a643563
BS		 2305void ide_bus_reset(IDEBus *bus)
2306{
2307 bus->unit = 0;
2308 bus->cmd = 0;
2309 ide_reset(&bus->ifs[0]);
2310 ide_reset(&bus->ifs[1]);
2311 ide_clear_hob(bus);
40a6238a
AG		 2312
2313 /* pending async DMA */
2314 if (bus->dma->aiocb) {
2315#ifdef DEBUG_AIO
2316 printf("aio_cancel\n");
2317#endif
4be74634 2318 blk_aio_cancel(bus->dma->aiocb);
40a6238a
AG		 2319 bus->dma->aiocb = NULL;
2320 }
2321
2322 /* reset dma provider too */
1374bec0
PB		 2323 if (bus->dma->ops->reset) {
2324 bus->dma->ops->reset(bus->dma);
2325 }
4a643563
BS		 2326}
2327
e4def80b
MA		 2328static bool ide_cd_is_tray_open(void *opaque)
2329{
2330 return ((IDEState *)opaque)->tray_open;
2331}
2332
f107639a
MA		 2333static bool ide_cd_is_medium_locked(void *opaque)
2334{
2335 return ((IDEState *)opaque)->tray_locked;
2336}
2337
01ce352e
JS		 2338static void ide_resize_cb(void *opaque)
2339{
2340 IDEState *s = opaque;
2341 uint64_t nb_sectors;
2342
2343 if (!s->identify_set) {
2344 return;
2345 }
2346
4be74634 2347 blk_get_geometry(s->blk, &nb_sectors);
01ce352e
JS		 2348 s->nb_sectors = nb_sectors;
2349
2350 /* Update the identify data buffer. */
2351 if (s->drive_kind == IDE_CFATA) {
2352 ide_cfata_identify_size(s);
2353 } else {
2354 /* IDE_CD uses a different set of callbacks entirely. */
2355 assert(s->drive_kind != IDE_CD);
2356 ide_identify_size(s);
2357 }
2358}
2359
0e49de52 2360static const BlockDevOps ide_cd_block_ops = {
145feb17 2361 .change_media_cb = ide_cd_change_cb,
2df0a3a3 2362 .eject_request_cb = ide_cd_eject_request_cb,
e4def80b 2363 .is_tray_open = ide_cd_is_tray_open,
f107639a 2364 .is_medium_locked = ide_cd_is_medium_locked,
0e49de52
MA		 2365};
2366
01ce352e
JS		 2367static const BlockDevOps ide_hd_block_ops = {
2368 .resize_cb = ide_resize_cb,
2369};
2370
4be74634 2371int ide_init_drive(IDEState *s, BlockBackend *blk, IDEDriveKind kind,
95ebda85 2372 const char *version, const char *serial, const char *model,
ba801960
MA		 2373 uint64_t wwn,
2374 uint32_t cylinders, uint32_t heads, uint32_t secs,
2375 int chs_trans)
88804180 2376{
88804180
GH		 2377 uint64_t nb_sectors;
2378
4be74634 2379 s->blk = blk;
1f56e32a
MA		 2380 s->drive_kind = kind;
2381
4be74634 2382 blk_get_geometry(blk, &nb_sectors);
870111c8
MA		 2383 s->cylinders = cylinders;
2384 s->heads = heads;
2385 s->sectors = secs;
ba801960 2386 s->chs_trans = chs_trans;
870111c8 2387 s->nb_sectors = nb_sectors;
95ebda85 2388 s->wwn = wwn;
870111c8
MA		 2389 /* The SMART values should be preserved across power cycles
2390 but they aren't. */
2391 s->smart_enabled = 1;
2392 s->smart_autosave = 1;
2393 s->smart_errors = 0;
2394 s->smart_selftest_count = 0;
1f56e32a 2395 if (kind == IDE_CD) {
4be74634
MA		 2396 blk_set_dev_ops(blk, &ide_cd_block_ops, s);
2397 blk_set_guest_block_size(blk, 2048);
7aa9c811 2398 } else {
4be74634 2399 if (!blk_is_inserted(s->blk)) {
98f28ad7
MA		 2400 error_report("Device needs media, but drive is empty");
2401 return -1;
2402 }
4be74634 2403 if (blk_is_read_only(blk)) {
7aa9c811
MA		 2404 error_report("Can't use a read-only drive");
2405 return -1;
2406 }
4be74634 2407 blk_set_dev_ops(blk, &ide_hd_block_ops, s);
88804180 2408 }
f8b6cc00 2409 if (serial) {
aa2c91bd 2410 pstrcpy(s->drive_serial_str, sizeof(s->drive_serial_str), serial);
6ced55a5 2411 } else {
88804180
GH		 2412 snprintf(s->drive_serial_str, sizeof(s->drive_serial_str),
2413 "QM%05d", s->drive_serial);
870111c8 2414 }
27e0c9a1
FB		 2415 if (model) {
2416 pstrcpy(s->drive_model_str, sizeof(s->drive_model_str), model);
2417 } else {
2418 switch (kind) {
2419 case IDE_CD:
2420 strcpy(s->drive_model_str, "QEMU DVD-ROM");
2421 break;
2422 case IDE_CFATA:
2423 strcpy(s->drive_model_str, "QEMU MICRODRIVE");
2424 break;
2425 default:
2426 strcpy(s->drive_model_str, "QEMU HARDDISK");
2427 break;
2428 }
2429 }
2430
47c06340
GH		 2431 if (version) {
2432 pstrcpy(s->version, sizeof(s->version), version);
2433 } else {
35c2c8dc 2434 pstrcpy(s->version, sizeof(s->version), qemu_hw_version());
47c06340 2435 }
40a6238a 2436
88804180 2437 ide_reset(s);
4be74634 2438 blk_iostatus_enable(blk);
c4d74df7 2439 return 0;
88804180
GH		 2440}
2441
57234ee4 2442static void ide_init1(IDEBus *bus, int unit)
d459da0e
MA		 2443{
2444 static int drive_serial = 1;
2445 IDEState *s = &bus->ifs[unit];
2446
2447 s->bus = bus;
2448 s->unit = unit;
2449 s->drive_serial = drive_serial++;
1b2adf28 2450 /* we need at least 2k alignment for accessing CDROMs using O_DIRECT */
50641c5c 2451 s->io_buffer_total_len = IDE_DMA_BUF_SECTORS*512 + 4;
c925400b
KW		 2452 s->io_buffer = qemu_memalign(2048, s->io_buffer_total_len);
2453 memset(s->io_buffer, 0, s->io_buffer_total_len);
2454
4be74634 2455 s->smart_selftest_data = blk_blockalign(s->blk, 512);
c925400b
KW		 2456 memset(s->smart_selftest_data, 0, 512);
2457
bc72ad67 2458 s->sector_write_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
d459da0e 2459 ide_sector_write_timer_cb, s);
57234ee4
MA		 2460}
2461
40a6238a
AG		 2462static int ide_nop_int(IDEDMA *dma, int x)
2463{
2464 return 0;
2465}
2466
9898586d
PB		 2467static void ide_nop(IDEDMA *dma)
2468{
2469}
2470
a718978e 2471static int32_t ide_nop_int32(IDEDMA *dma, int32_t l)
3251bdcf
JS		 2472{
2473 return 0;
2474}
2475
40a6238a 2476static const IDEDMAOps ide_dma_nop_ops = {
3251bdcf 2477 .prepare_buf = ide_nop_int32,
9898586d 2478 .restart_dma = ide_nop,
40a6238a 2479 .rw_buf = ide_nop_int,
40a6238a
AG		 2480};
2481
9898586d
PB		 2482static void ide_restart_dma(IDEState *s, enum ide_dma_cmd dma_cmd)
2483{
a96cb236 2484 s->unit = s->bus->retry_unit;
dc5d0af4
PB		 2485 ide_set_sector(s, s->bus->retry_sector_num);
2486 s->nsector = s->bus->retry_nsector;
9898586d 2487 s->bus->dma->ops->restart_dma(s->bus->dma);
9898586d
PB		 2488 s->io_buffer_size = 0;
2489 s->dma_cmd = dma_cmd;
2490 ide_start_dma(s, ide_dma_cb);
2491}
2492
2493static void ide_restart_bh(void *opaque)
2494{
2495 IDEBus *bus = opaque;
2496 IDEState *s;
2497 bool is_read;
2498 int error_status;
2499
2500 qemu_bh_delete(bus->bh);
2501 bus->bh = NULL;
2502
2503 error_status = bus->error_status;
2504 if (bus->error_status == 0) {
2505 return;
2506 }
2507
2508 s = idebus_active_if(bus);
2509 is_read = (bus->error_status & IDE_RETRY_READ) != 0;
2510
2511 /* The error status must be cleared before resubmitting the request: The
2512 * request may fail again, and this case can only be distinguished if the
2513 * called function can set a new error status. */
2514 bus->error_status = 0;
2515
7c03a691
JS		 2516 /* The HBA has generically asked to be kicked on retry */
2517 if (error_status & IDE_RETRY_HBA) {
2518 if (s->bus->dma->ops->restart) {
2519 s->bus->dma->ops->restart(s->bus->dma);
2520 }
2521 }
2522
9898586d
PB		 2523 if (error_status & IDE_RETRY_DMA) {
2524 if (error_status & IDE_RETRY_TRIM) {
2525 ide_restart_dma(s, IDE_DMA_TRIM);
2526 } else {
2527 ide_restart_dma(s, is_read ? IDE_DMA_READ : IDE_DMA_WRITE);
2528 }
2529 } else if (error_status & IDE_RETRY_PIO) {
2530 if (is_read) {
2531 ide_sector_read(s);
2532 } else {
2533 ide_sector_write(s);
2534 }
2535 } else if (error_status & IDE_RETRY_FLUSH) {
2536 ide_flush_cache(s);
2537 } else {
2538 /*
2539 * We've not got any bits to tell us about ATAPI - but
2540 * we do have the end_transfer_func that tells us what
2541 * we're trying to do.
2542 */
2543 if (s->end_transfer_func == ide_atapi_cmd) {
2544 ide_atapi_dma_restart(s);
2545 }
2546 }
2547}
2548
2549static void ide_restart_cb(void *opaque, int running, RunState state)
2550{
2551 IDEBus *bus = opaque;
2552
2553 if (!running)
2554 return;
2555
2556 if (!bus->bh) {
2557 bus->bh = qemu_bh_new(ide_restart_bh, bus);
2558 qemu_bh_schedule(bus->bh);
2559 }
2560}
2561
f878c916
PB		 2562void ide_register_restart_cb(IDEBus *bus)
2563{
9898586d
PB		 2564 if (bus->dma->ops->restart_dma) {
2565 qemu_add_vm_change_state_handler(ide_restart_cb, bus);
2566 }
f878c916
PB		 2567}
2568
40a6238a
AG		 2569static IDEDMA ide_dma_nop = {
2570 .ops = &ide_dma_nop_ops,
2571 .aiocb = NULL,
2572};
2573
57234ee4
MA		 2574void ide_init2(IDEBus *bus, qemu_irq irq)
2575{
2576 int i;
2577
2578 for(i = 0; i < 2; i++) {
2579 ide_init1(bus, i);
2580 ide_reset(&bus->ifs[i]);
870111c8 2581 }
57234ee4 2582 bus->irq = irq;
40a6238a 2583 bus->dma = &ide_dma_nop;
d459da0e
MA		 2584}
2585
4a91d3b3
RH		 2586static const MemoryRegionPortio ide_portio_list[] = {
2587 { 0, 8, 1, .read = ide_ioport_read, .write = ide_ioport_write },
e477317c
PB		 2588 { 0, 1, 2, .read = ide_data_readw, .write = ide_data_writew },
2589 { 0, 1, 4, .read = ide_data_readl, .write = ide_data_writel },
4a91d3b3
RH		 2590 PORTIO_END_OF_LIST(),
2591};
2592
2593static const MemoryRegionPortio ide_portio2_list[] = {
2594 { 0, 1, 1, .read = ide_status_read, .write = ide_cmd_write },
2595 PORTIO_END_OF_LIST(),
2596};
2597
2598void ide_init_ioport(IDEBus *bus, ISADevice *dev, int iobase, int iobase2)
69b91039 2599{
4a91d3b3
RH		 2600 /* ??? Assume only ISA and PCI configurations, and that the PCI-ISA
2601 bridge has been setup properly to always register with ISA. */
2602 isa_register_portio_list(dev, iobase, ide_portio_list, bus, "ide");
2603
caed8802 2604 if (iobase2) {
4a91d3b3 2605 isa_register_portio_list(dev, iobase2, ide_portio2_list, bus, "ide");
5391d806 2606 }
5391d806 2607}
69b91039 2608
37159f13 2609static bool is_identify_set(void *opaque, int version_id)
aa941b94 2610{
37159f13
JQ		 2611 IDEState *s = opaque;
2612
2613 return s->identify_set != 0;
2614}
2615
50641c5c
JQ		 2616static EndTransferFunc* transfer_end_table[] = {
2617 ide_sector_read,
2618 ide_sector_write,
2619 ide_transfer_stop,
2620 ide_atapi_cmd_reply_end,
2621 ide_atapi_cmd,
2622 ide_dummy_transfer_stop,
2623};
2624
2625static int transfer_end_table_idx(EndTransferFunc *fn)
2626{
2627 int i;
2628
2629 for (i = 0; i < ARRAY_SIZE(transfer_end_table); i++)
2630 if (transfer_end_table[i] == fn)
2631 return i;
2632
2633 return -1;
2634}
2635
37159f13 2636static int ide_drive_post_load(void *opaque, int version_id)
aa941b94 2637{
37159f13
JQ		 2638 IDEState *s = opaque;
2639
6b896ab2 2640 if (s->blk && s->identify_set) {
4be74634 2641 blk_set_enable_write_cache(s->blk, !!(s->identify_data[85] & (1 << 5)));
7cdd481c 2642 }
37159f13 2643 return 0;
aa941b94
AZ		 2644}
2645
50641c5c
JQ		 2646static int ide_drive_pio_post_load(void *opaque, int version_id)
2647{
2648 IDEState *s = opaque;
2649
fb60105d 2650 if (s->end_transfer_fn_idx >= ARRAY_SIZE(transfer_end_table)) {
50641c5c
JQ		 2651 return -EINVAL;
2652 }
2653 s->end_transfer_func = transfer_end_table[s->end_transfer_fn_idx];
2654 s->data_ptr = s->io_buffer + s->cur_io_buffer_offset;
2655 s->data_end = s->data_ptr + s->cur_io_buffer_len;
819fa276 2656 s->atapi_dma = s->feature & 1; /* as per cmd_packet */
50641c5c
JQ		 2657
2658 return 0;
2659}
2660
2661static void ide_drive_pio_pre_save(void *opaque)
2662{
2663 IDEState *s = opaque;
2664 int idx;
2665
2666 s->cur_io_buffer_offset = s->data_ptr - s->io_buffer;
2667 s->cur_io_buffer_len = s->data_end - s->data_ptr;
2668
2669 idx = transfer_end_table_idx(s->end_transfer_func);
2670 if (idx == -1) {
2671 fprintf(stderr, "%s: invalid end_transfer_func for DRQ_STAT\n",
2672 __func__);
2673 s->end_transfer_fn_idx = 2;
2674 } else {
2675 s->end_transfer_fn_idx = idx;
2676 }
2677}
2678
2679static bool ide_drive_pio_state_needed(void *opaque)
2680{
2681 IDEState *s = opaque;
2682
fdc650d7 2683 return ((s->status & DRQ_STAT) != 0)
fd648f10 2684 || (s->bus->error_status & IDE_RETRY_PIO);
50641c5c
JQ		 2685}
2686
db118fe7
MA		 2687static bool ide_tray_state_needed(void *opaque)
2688{
2689 IDEState *s = opaque;
2690
2691 return s->tray_open || s->tray_locked;
2692}
2693
996faf1a
AS		 2694static bool ide_atapi_gesn_needed(void *opaque)
2695{
2696 IDEState *s = opaque;
2697
2698 return s->events.new_media || s->events.eject_request;
2699}
2700
def93791
KW		 2701static bool ide_error_needed(void *opaque)
2702{
2703 IDEBus *bus = opaque;
2704
2705 return (bus->error_status != 0);
2706}
2707
996faf1a 2708/* Fields for GET_EVENT_STATUS_NOTIFICATION ATAPI command */
656fbeff 2709static const VMStateDescription vmstate_ide_atapi_gesn_state = {
996faf1a
AS		 2710 .name ="ide_drive/atapi/gesn_state",
2711 .version_id = 1,
2712 .minimum_version_id = 1,
5cd8cada 2713 .needed = ide_atapi_gesn_needed,
35d08458 2714 .fields = (VMStateField[]) {
996faf1a
AS		 2715 VMSTATE_BOOL(events.new_media, IDEState),
2716 VMSTATE_BOOL(events.eject_request, IDEState),
0754f9ec 2717 VMSTATE_END_OF_LIST()
996faf1a
AS		 2718 }
2719};
2720
db118fe7
MA		 2721static const VMStateDescription vmstate_ide_tray_state = {
2722 .name = "ide_drive/tray_state",
2723 .version_id = 1,
2724 .minimum_version_id = 1,
5cd8cada 2725 .needed = ide_tray_state_needed,
db118fe7
MA		 2726 .fields = (VMStateField[]) {
2727 VMSTATE_BOOL(tray_open, IDEState),
2728 VMSTATE_BOOL(tray_locked, IDEState),
2729 VMSTATE_END_OF_LIST()
2730 }
2731};
2732
656fbeff 2733static const VMStateDescription vmstate_ide_drive_pio_state = {
50641c5c
JQ		 2734 .name = "ide_drive/pio_state",
2735 .version_id = 1,
2736 .minimum_version_id = 1,
50641c5c
JQ		 2737 .pre_save = ide_drive_pio_pre_save,
2738 .post_load = ide_drive_pio_post_load,
5cd8cada 2739 .needed = ide_drive_pio_state_needed,
35d08458 2740 .fields = (VMStateField[]) {
50641c5c
JQ		 2741 VMSTATE_INT32(req_nb_sectors, IDEState),
2742 VMSTATE_VARRAY_INT32(io_buffer, IDEState, io_buffer_total_len, 1,
2743 vmstate_info_uint8, uint8_t),
2744 VMSTATE_INT32(cur_io_buffer_offset, IDEState),
2745 VMSTATE_INT32(cur_io_buffer_len, IDEState),
2746 VMSTATE_UINT8(end_transfer_fn_idx, IDEState),
2747 VMSTATE_INT32(elementary_transfer_size, IDEState),
2748 VMSTATE_INT32(packet_transfer_size, IDEState),
2749 VMSTATE_END_OF_LIST()
2750 }
2751};
2752
37159f13
JQ		 2753const VMStateDescription vmstate_ide_drive = {
2754 .name = "ide_drive",
3abb6260 2755 .version_id = 3,
37159f13 2756 .minimum_version_id = 0,
37159f13 2757 .post_load = ide_drive_post_load,
35d08458 2758 .fields = (VMStateField[]) {
37159f13
JQ		 2759 VMSTATE_INT32(mult_sectors, IDEState),
2760 VMSTATE_INT32(identify_set, IDEState),
2761 VMSTATE_BUFFER_TEST(identify_data, IDEState, is_identify_set),
2762 VMSTATE_UINT8(feature, IDEState),
2763 VMSTATE_UINT8(error, IDEState),
2764 VMSTATE_UINT32(nsector, IDEState),
2765 VMSTATE_UINT8(sector, IDEState),
2766 VMSTATE_UINT8(lcyl, IDEState),
2767 VMSTATE_UINT8(hcyl, IDEState),
2768 VMSTATE_UINT8(hob_feature, IDEState),
2769 VMSTATE_UINT8(hob_sector, IDEState),
2770 VMSTATE_UINT8(hob_nsector, IDEState),
2771 VMSTATE_UINT8(hob_lcyl, IDEState),
2772 VMSTATE_UINT8(hob_hcyl, IDEState),
2773 VMSTATE_UINT8(select, IDEState),
2774 VMSTATE_UINT8(status, IDEState),
2775 VMSTATE_UINT8(lba48, IDEState),
2776 VMSTATE_UINT8(sense_key, IDEState),
2777 VMSTATE_UINT8(asc, IDEState),
2778 VMSTATE_UINT8_V(cdrom_changed, IDEState, 3),
37159f13 2779 VMSTATE_END_OF_LIST()
50641c5c 2780 },
5cd8cada
JQ		 2781 .subsections = (const VMStateDescription*[]) {
2782 &vmstate_ide_drive_pio_state,
2783 &vmstate_ide_tray_state,
2784 &vmstate_ide_atapi_gesn_state,
2785 NULL
37159f13
JQ		 2786 }
2787};
2788
656fbeff 2789static const VMStateDescription vmstate_ide_error_status = {
def93791 2790 .name ="ide_bus/error",
d12b9ff2 2791 .version_id = 2,
def93791 2792 .minimum_version_id = 1,
5cd8cada 2793 .needed = ide_error_needed,
35d08458 2794 .fields = (VMStateField[]) {
def93791 2795 VMSTATE_INT32(error_status, IDEBus),
d12b9ff2
PB		 2796 VMSTATE_INT64_V(retry_sector_num, IDEBus, 2),
2797 VMSTATE_UINT32_V(retry_nsector, IDEBus, 2),
2798 VMSTATE_UINT8_V(retry_unit, IDEBus, 2),
def93791
KW		 2799 VMSTATE_END_OF_LIST()
2800 }
2801};
2802
6521dc62
JQ		 2803const VMStateDescription vmstate_ide_bus = {
2804 .name = "ide_bus",
2805 .version_id = 1,
2806 .minimum_version_id = 1,
35d08458 2807 .fields = (VMStateField[]) {
6521dc62
JQ		 2808 VMSTATE_UINT8(cmd, IDEBus),
2809 VMSTATE_UINT8(unit, IDEBus),
2810 VMSTATE_END_OF_LIST()
def93791 2811 },
5cd8cada
JQ		 2812 .subsections = (const VMStateDescription*[]) {
2813 &vmstate_ide_error_status,
2814 NULL
6521dc62
JQ		 2815 }
2816};
75717903 2817
d8f94e1b 2818void ide_drive_get(DriveInfo **hd, int n)
75717903
IY		 2819{
2820 int i;
d8f94e1b
JS		 2821 int highest_bus = drive_get_max_bus(IF_IDE) + 1;
2822 int max_devs = drive_get_max_devs(IF_IDE);
2823 int n_buses = max_devs ? (n / max_devs) : n;
75717903 2824
d8f94e1b
JS		 2825 /*
2826 * Note: The number of actual buses available is not known.
2827 * We compute this based on the size of the DriveInfo* array, n.
2828 * If it is less than max_devs * <num_real_buses>,
2829 * We will stop looking for drives prematurely instead of overfilling
2830 * the array.
2831 */
2832
2833 if (highest_bus > n_buses) {
2834 error_report("Too many IDE buses defined (%d > %d)",
2835 highest_bus, n_buses);
75717903
IY		 2836 exit(1);
2837 }
2838
d8f94e1b
JS		 2839 for (i = 0; i < n; i++) {
2840 hd[i] = drive_get_by_index(IF_IDE, i);
75717903
IY		 2841 }
2842}
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