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ide: migrate initial request state via IDEBus
[qemu.git] / hw / ide / core.c
CommitLineData
5391d806 1/*
38cdea7c 2 * QEMU IDE disk and CD/DVD-ROM Emulator
5fafdf24 3 *
5391d806 4 * Copyright (c) 2003 Fabrice Bellard
201a51fc 5 * Copyright (c) 2006 Openedhand Ltd.
5fafdf24 6 *
5391d806
FB		 7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
59f2a787 25#include <hw/hw.h>
0d09e41a 26#include <hw/i386/pc.h>
a2cb15b0 27#include <hw/pci/pci.h>
0d09e41a 28#include <hw/isa/isa.h>
1de7afc9
PB		 29#include "qemu/error-report.h"
30#include "qemu/timer.h"
9c17d615
PB		 31#include "sysemu/sysemu.h"
32#include "sysemu/dma.h"
0d09e41a 33#include "hw/block/block.h"
4be74634 34#include "sysemu/block-backend.h"
59f2a787
GH		 35
36#include <hw/ide/internal.h>
e8b54394 37
b93af93d
BW		 38/* These values were based on a Seagate ST3500418AS but have been modified
39 to make more sense in QEMU */
40static const int smart_attributes[][12] = {
41 /* id, flags, hflags, val, wrst, raw (6 bytes), threshold */
42 /* raw read error rate*/
43 { 0x01, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06},
44 /* spin up */
45 { 0x03, 0x03, 0x00, 0x64, 0x64, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
46 /* start stop count */
47 { 0x04, 0x02, 0x00, 0x64, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14},
48 /* remapped sectors */
49 { 0x05, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x24},
50 /* power on hours */
51 { 0x09, 0x03, 0x00, 0x64, 0x64, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
52 /* power cycle count */
53 { 0x0c, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
54 /* airflow-temperature-celsius */
55 { 190, 0x03, 0x00, 0x45, 0x45, 0x1f, 0x00, 0x1f, 0x1f, 0x00, 0x00, 0x32},
e8b54394
BW		 56};
57
ce4b6522 58static int ide_handle_rw_error(IDEState *s, int error, int op);
40c4ed3f 59static void ide_dummy_transfer_stop(IDEState *s);
98087450 60
5391d806
FB		 61static void padstr(char *str, const char *src, int len)
62{
63 int i, v;
64 for(i = 0; i < len; i++) {
65 if (*src)
66 v = *src++;
67 else
68 v = ' ';
69b34976 69 str[i^1] = v;
5391d806
FB		 70 }
71}
72
67b915a5
FB		 73static void put_le16(uint16_t *p, unsigned int v)
74{
0c4ad8dc 75 *p = cpu_to_le16(v);
67b915a5
FB		 76}
77
01ce352e
JS		 78static void ide_identify_size(IDEState *s)
79{
80 uint16_t *p = (uint16_t *)s->identify_data;
81 put_le16(p + 60, s->nb_sectors);
82 put_le16(p + 61, s->nb_sectors >> 16);
83 put_le16(p + 100, s->nb_sectors);
84 put_le16(p + 101, s->nb_sectors >> 16);
85 put_le16(p + 102, s->nb_sectors >> 32);
86 put_le16(p + 103, s->nb_sectors >> 48);
87}
88
5391d806
FB		 89static void ide_identify(IDEState *s)
90{
91 uint16_t *p;
92 unsigned int oldsize;
d353fb72 93 IDEDevice *dev = s->unit ? s->bus->slave : s->bus->master;
5391d806 94
4bf6637d 95 p = (uint16_t *)s->identify_data;
94458802 96 if (s->identify_set) {
4bf6637d 97 goto fill_buffer;
94458802 98 }
4bf6637d 99 memset(p, 0, sizeof(s->identify_data));
94458802 100
67b915a5 101 put_le16(p + 0, 0x0040);
5fafdf24 102 put_le16(p + 1, s->cylinders);
67b915a5
FB		 103 put_le16(p + 3, s->heads);
104 put_le16(p + 4, 512 * s->sectors); /* XXX: retired, remove ? */
105 put_le16(p + 5, 512); /* XXX: retired, remove ? */
5fafdf24 106 put_le16(p + 6, s->sectors);
fa879c64 107 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
67b915a5
FB		 108 put_le16(p + 20, 3); /* XXX: retired, remove ? */
109 put_le16(p + 21, 512); /* cache size in sectors */
110 put_le16(p + 22, 4); /* ecc bytes */
47c06340 111 padstr((char *)(p + 23), s->version, 8); /* firmware version */
27e0c9a1 112 padstr((char *)(p + 27), s->drive_model_str, 40); /* model */
3b46e624 113#if MAX_MULT_SECTORS > 1
67b915a5 114 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
5391d806 115#endif
67b915a5 116 put_le16(p + 48, 1); /* dword I/O */
94458802 117 put_le16(p + 49, (1 << 11) | (1 << 9) | (1 << 8)); /* DMA and LBA supported */
67b915a5
FB		 118 put_le16(p + 51, 0x200); /* PIO transfer cycle */
119 put_le16(p + 52, 0x200); /* DMA transfer cycle */
94458802 120 put_le16(p + 53, 1 | (1 << 1) | (1 << 2)); /* words 54-58,64-70,88 are valid */
67b915a5
FB		 121 put_le16(p + 54, s->cylinders);
122 put_le16(p + 55, s->heads);
123 put_le16(p + 56, s->sectors);
5391d806 124 oldsize = s->cylinders * s->heads * s->sectors;
67b915a5
FB		 125 put_le16(p + 57, oldsize);
126 put_le16(p + 58, oldsize >> 16);
5391d806 127 if (s->mult_sectors)
67b915a5 128 put_le16(p + 59, 0x100 | s->mult_sectors);
01ce352e
JS		 129 /* *(p + 60) := nb_sectors -- see ide_identify_size */
130 /* *(p + 61) := nb_sectors >> 16 -- see ide_identify_size */
d1b5c20d 131 put_le16(p + 62, 0x07); /* single word dma0-2 supported */
94458802 132 put_le16(p + 63, 0x07); /* mdma0-2 supported */
79d1d331 133 put_le16(p + 64, 0x03); /* pio3-4 supported */
94458802
FB		 134 put_le16(p + 65, 120);
135 put_le16(p + 66, 120);
136 put_le16(p + 67, 120);
137 put_le16(p + 68, 120);
d353fb72
CH		 138 if (dev && dev->conf.discard_granularity) {
139 put_le16(p + 69, (1 << 14)); /* determinate TRIM behavior */
140 }
ccf0fd8b
RE		 141
142 if (s->ncq_queues) {
143 put_le16(p + 75, s->ncq_queues - 1);
144 /* NCQ supported */
145 put_le16(p + 76, (1 << 8));
146 }
147
94458802
FB		 148 put_le16(p + 80, 0xf0); /* ata3 -> ata6 supported */
149 put_le16(p + 81, 0x16); /* conforms to ata5 */
a58b8d54
CH		 150 /* 14=NOP supported, 5=WCACHE supported, 0=SMART supported */
151 put_le16(p + 82, (1 << 14) | (1 << 5) | 1);
c2ff060f
FB		 152 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
153 put_le16(p + 83, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10));
95ebda85
FB		 154 /* 14=set to 1, 8=has WWN, 1=SMART self test, 0=SMART error logging */
155 if (s->wwn) {
156 put_le16(p + 84, (1 << 14) | (1 << 8) | 0);
157 } else {
158 put_le16(p + 84, (1 << 14) | 0);
159 }
e900a7b7 160 /* 14 = NOP supported, 5=WCACHE enabled, 0=SMART feature set enabled */
4be74634
MA		 161 if (blk_enable_write_cache(s->blk)) {
162 put_le16(p + 85, (1 << 14) | (1 << 5) | 1);
163 } else {
164 put_le16(p + 85, (1 << 14) | 1);
165 }
c2ff060f 166 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
2844bdd9 167 put_le16(p + 86, (1 << 13) | (1 <<12) | (1 << 10));
95ebda85
FB		 168 /* 14=set to 1, 8=has WWN, 1=SMART self test, 0=SMART error logging */
169 if (s->wwn) {
170 put_le16(p + 87, (1 << 14) | (1 << 8) | 0);
171 } else {
172 put_le16(p + 87, (1 << 14) | 0);
173 }
94458802
FB		 174 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
175 put_le16(p + 93, 1 | (1 << 14) | 0x2000);
01ce352e
JS		 176 /* *(p + 100) := nb_sectors -- see ide_identify_size */
177 /* *(p + 101) := nb_sectors >> 16 -- see ide_identify_size */
178 /* *(p + 102) := nb_sectors >> 32 -- see ide_identify_size */
179 /* *(p + 103) := nb_sectors >> 48 -- see ide_identify_size */
d353fb72 180
57dac7ef
MA		 181 if (dev && dev->conf.physical_block_size)
182 put_le16(p + 106, 0x6000 | get_physical_block_exp(&dev->conf));
95ebda85
FB		 183 if (s->wwn) {
184 /* LE 16-bit words 111-108 contain 64-bit World Wide Name */
185 put_le16(p + 108, s->wwn >> 48);
186 put_le16(p + 109, s->wwn >> 32);
187 put_le16(p + 110, s->wwn >> 16);
188 put_le16(p + 111, s->wwn);
189 }
d353fb72
CH		 190 if (dev && dev->conf.discard_granularity) {
191 put_le16(p + 169, 1); /* TRIM support */
192 }
94458802 193
01ce352e 194 ide_identify_size(s);
94458802 195 s->identify_set = 1;
4bf6637d
JS		 196
197fill_buffer:
198 memcpy(s->io_buffer, p, sizeof(s->identify_data));
5391d806
FB		 199}
200
201static void ide_atapi_identify(IDEState *s)
202{
203 uint16_t *p;
204
4bf6637d 205 p = (uint16_t *)s->identify_data;
94458802 206 if (s->identify_set) {
4bf6637d 207 goto fill_buffer;
94458802 208 }
4bf6637d 209 memset(p, 0, sizeof(s->identify_data));
94458802 210
5391d806 211 /* Removable CDROM, 50us response, 12 byte packets */
67b915a5 212 put_le16(p + 0, (2 << 14) | (5 << 8) | (1 << 7) | (2 << 5) | (0 << 0));
fa879c64 213 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
67b915a5
FB		 214 put_le16(p + 20, 3); /* buffer type */
215 put_le16(p + 21, 512); /* cache size in sectors */
216 put_le16(p + 22, 4); /* ecc bytes */
47c06340 217 padstr((char *)(p + 23), s->version, 8); /* firmware version */
27e0c9a1 218 padstr((char *)(p + 27), s->drive_model_str, 40); /* model */
67b915a5 219 put_le16(p + 48, 1); /* dword I/O (XXX: should not be set on CDROM) */
8ccad811
FB		 220#ifdef USE_DMA_CDROM
221 put_le16(p + 49, 1 << 9 | 1 << 8); /* DMA and LBA supported */
222 put_le16(p + 53, 7); /* words 64-70, 54-58, 88 valid */
d1b5c20d 223 put_le16(p + 62, 7); /* single word dma0-2 supported */
8ccad811 224 put_le16(p + 63, 7); /* mdma0-2 supported */
8ccad811 225#else
67b915a5
FB		 226 put_le16(p + 49, 1 << 9); /* LBA supported, no DMA */
227 put_le16(p + 53, 3); /* words 64-70, 54-58 valid */
228 put_le16(p + 63, 0x103); /* DMA modes XXX: may be incorrect */
8ccad811 229#endif
79d1d331 230 put_le16(p + 64, 3); /* pio3-4 supported */
67b915a5
FB		 231 put_le16(p + 65, 0xb4); /* minimum DMA multiword tx cycle time */
232 put_le16(p + 66, 0xb4); /* recommended DMA multiword tx cycle time */
233 put_le16(p + 67, 0x12c); /* minimum PIO cycle time without flow control */
234 put_le16(p + 68, 0xb4); /* minimum PIO cycle time with IORDY flow control */
94458802 235
67b915a5
FB		 236 put_le16(p + 71, 30); /* in ns */
237 put_le16(p + 72, 30); /* in ns */
5391d806 238
1bdaa28d
AG		 239 if (s->ncq_queues) {
240 put_le16(p + 75, s->ncq_queues - 1);
241 /* NCQ supported */
242 put_le16(p + 76, (1 << 8));
243 }
244
67b915a5 245 put_le16(p + 80, 0x1e); /* support up to ATA/ATAPI-4 */
c5fe97e3
JS		 246 if (s->wwn) {
247 put_le16(p + 84, (1 << 8)); /* supports WWN for words 108-111 */
248 put_le16(p + 87, (1 << 8)); /* WWN enabled */
249 }
250
8ccad811
FB		 251#ifdef USE_DMA_CDROM
252 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
253#endif
c5fe97e3
JS		 254
255 if (s->wwn) {
256 /* LE 16-bit words 111-108 contain 64-bit World Wide Name */
257 put_le16(p + 108, s->wwn >> 48);
258 put_le16(p + 109, s->wwn >> 32);
259 put_le16(p + 110, s->wwn >> 16);
260 put_le16(p + 111, s->wwn);
261 }
262
94458802 263 s->identify_set = 1;
4bf6637d
JS		 264
265fill_buffer:
266 memcpy(s->io_buffer, p, sizeof(s->identify_data));
5391d806
FB		 267}
268
01ce352e
JS		 269static void ide_cfata_identify_size(IDEState *s)
270{
271 uint16_t *p = (uint16_t *)s->identify_data;
272 put_le16(p + 7, s->nb_sectors >> 16); /* Sectors per card */
273 put_le16(p + 8, s->nb_sectors); /* Sectors per card */
274 put_le16(p + 60, s->nb_sectors); /* Total LBA sectors */
275 put_le16(p + 61, s->nb_sectors >> 16); /* Total LBA sectors */
276}
277
201a51fc
AZ		 278static void ide_cfata_identify(IDEState *s)
279{
280 uint16_t *p;
281 uint32_t cur_sec;
201a51fc 282
4bf6637d
JS		 283 p = (uint16_t *)s->identify_data;
284 if (s->identify_set) {
201a51fc 285 goto fill_buffer;
4bf6637d 286 }
201a51fc
AZ		 287 memset(p, 0, sizeof(s->identify_data));
288
289 cur_sec = s->cylinders * s->heads * s->sectors;
290
291 put_le16(p + 0, 0x848a); /* CF Storage Card signature */
292 put_le16(p + 1, s->cylinders); /* Default cylinders */
293 put_le16(p + 3, s->heads); /* Default heads */
294 put_le16(p + 6, s->sectors); /* Default sectors per track */
01ce352e
JS		 295 /* *(p + 7) := nb_sectors >> 16 -- see ide_cfata_identify_size */
296 /* *(p + 8) := nb_sectors -- see ide_cfata_identify_size */
fa879c64 297 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
201a51fc 298 put_le16(p + 22, 0x0004); /* ECC bytes */
47c06340 299 padstr((char *) (p + 23), s->version, 8); /* Firmware Revision */
27e0c9a1 300 padstr((char *) (p + 27), s->drive_model_str, 40);/* Model number */
201a51fc
AZ		 301#if MAX_MULT_SECTORS > 1
302 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
303#else
304 put_le16(p + 47, 0x0000);
305#endif
306 put_le16(p + 49, 0x0f00); /* Capabilities */
307 put_le16(p + 51, 0x0002); /* PIO cycle timing mode */
308 put_le16(p + 52, 0x0001); /* DMA cycle timing mode */
309 put_le16(p + 53, 0x0003); /* Translation params valid */
310 put_le16(p + 54, s->cylinders); /* Current cylinders */
311 put_le16(p + 55, s->heads); /* Current heads */
312 put_le16(p + 56, s->sectors); /* Current sectors */
313 put_le16(p + 57, cur_sec); /* Current capacity */
314 put_le16(p + 58, cur_sec >> 16); /* Current capacity */
315 if (s->mult_sectors) /* Multiple sector setting */
316 put_le16(p + 59, 0x100 | s->mult_sectors);
01ce352e
JS		 317 /* *(p + 60) := nb_sectors -- see ide_cfata_identify_size */
318 /* *(p + 61) := nb_sectors >> 16 -- see ide_cfata_identify_size */
201a51fc
AZ		 319 put_le16(p + 63, 0x0203); /* Multiword DMA capability */
320 put_le16(p + 64, 0x0001); /* Flow Control PIO support */
321 put_le16(p + 65, 0x0096); /* Min. Multiword DMA cycle */
322 put_le16(p + 66, 0x0096); /* Rec. Multiword DMA cycle */
323 put_le16(p + 68, 0x00b4); /* Min. PIO cycle time */
324 put_le16(p + 82, 0x400c); /* Command Set supported */
325 put_le16(p + 83, 0x7068); /* Command Set supported */
326 put_le16(p + 84, 0x4000); /* Features supported */
327 put_le16(p + 85, 0x000c); /* Command Set enabled */
328 put_le16(p + 86, 0x7044); /* Command Set enabled */
329 put_le16(p + 87, 0x4000); /* Features enabled */
330 put_le16(p + 91, 0x4060); /* Current APM level */
331 put_le16(p + 129, 0x0002); /* Current features option */
332 put_le16(p + 130, 0x0005); /* Reassigned sectors */
333 put_le16(p + 131, 0x0001); /* Initial power mode */
334 put_le16(p + 132, 0x0000); /* User signature */
335 put_le16(p + 160, 0x8100); /* Power requirement */
336 put_le16(p + 161, 0x8001); /* CF command set */
337
01ce352e 338 ide_cfata_identify_size(s);
201a51fc
AZ		 339 s->identify_set = 1;
340
341fill_buffer:
342 memcpy(s->io_buffer, p, sizeof(s->identify_data));
343}
344
5391d806
FB		 345static void ide_set_signature(IDEState *s)
346{
347 s->select &= 0xf0; /* clear head */
348 /* put signature */
349 s->nsector = 1;
350 s->sector = 1;
cd8722bb 351 if (s->drive_kind == IDE_CD) {
5391d806
FB		 352 s->lcyl = 0x14;
353 s->hcyl = 0xeb;
4be74634 354 } else if (s->blk) {
5391d806
FB		 355 s->lcyl = 0;
356 s->hcyl = 0;
357 } else {
358 s->lcyl = 0xff;
359 s->hcyl = 0xff;
360 }
361}
362
d353fb72 363typedef struct TrimAIOCB {
7c84b1b8 364 BlockAIOCB common;
a987ee1f 365 BlockBackend *blk;
d353fb72
CH		 366 QEMUBH *bh;
367 int ret;
501378c3 368 QEMUIOVector *qiov;
7c84b1b8 369 BlockAIOCB *aiocb;
501378c3 370 int i, j;
d353fb72
CH		 371} TrimAIOCB;
372
7c84b1b8 373static void trim_aio_cancel(BlockAIOCB *acb)
d353fb72
CH		 374{
375 TrimAIOCB *iocb = container_of(acb, TrimAIOCB, common);
376
e551c999 377 /* Exit the loop so ide_issue_trim_cb will not continue */
501378c3
PB		 378 iocb->j = iocb->qiov->niov - 1;
379 iocb->i = (iocb->qiov->iov[iocb->j].iov_len / 8) - 1;
380
e551c999 381 iocb->ret = -ECANCELED;
501378c3
PB		 382
383 if (iocb->aiocb) {
4be74634 384 blk_aio_cancel_async(iocb->aiocb);
e551c999 385 iocb->aiocb = NULL;
501378c3 386 }
d353fb72
CH		 387}
388
d7331bed 389static const AIOCBInfo trim_aiocb_info = {
d353fb72 390 .aiocb_size = sizeof(TrimAIOCB),
e551c999 391 .cancel_async = trim_aio_cancel,
d353fb72
CH		 392};
393
394static void ide_trim_bh_cb(void *opaque)
395{
396 TrimAIOCB *iocb = opaque;
397
398 iocb->common.cb(iocb->common.opaque, iocb->ret);
399
400 qemu_bh_delete(iocb->bh);
401 iocb->bh = NULL;
8007429a 402 qemu_aio_unref(iocb);
d353fb72
CH		 403}
404
501378c3
PB		 405static void ide_issue_trim_cb(void *opaque, int ret)
406{
407 TrimAIOCB *iocb = opaque;
408 if (ret >= 0) {
409 while (iocb->j < iocb->qiov->niov) {
410 int j = iocb->j;
411 while (++iocb->i < iocb->qiov->iov[j].iov_len / 8) {
412 int i = iocb->i;
413 uint64_t *buffer = iocb->qiov->iov[j].iov_base;
414
415 /* 6-byte LBA + 2-byte range per entry */
416 uint64_t entry = le64_to_cpu(buffer[i]);
417 uint64_t sector = entry & 0x0000ffffffffffffULL;
418 uint16_t count = entry >> 48;
419
420 if (count == 0) {
421 continue;
422 }
423
424 /* Got an entry! Submit and exit. */
a987ee1f
MA		 425 iocb->aiocb = blk_aio_discard(iocb->blk, sector, count,
426 ide_issue_trim_cb, opaque);
501378c3
PB		 427 return;
428 }
429
430 iocb->j++;
431 iocb->i = -1;
432 }
433 } else {
434 iocb->ret = ret;
435 }
436
437 iocb->aiocb = NULL;
438 if (iocb->bh) {
439 qemu_bh_schedule(iocb->bh);
440 }
441}
442
4be74634 443BlockAIOCB *ide_issue_trim(BlockBackend *blk,
d353fb72 444 int64_t sector_num, QEMUIOVector *qiov, int nb_sectors,
097310b5 445 BlockCompletionFunc *cb, void *opaque)
d353fb72
CH		 446{
447 TrimAIOCB *iocb;
d353fb72 448
4be74634 449 iocb = blk_aio_get(&trim_aiocb_info, blk, cb, opaque);
a987ee1f 450 iocb->blk = blk;
d353fb72
CH		 451 iocb->bh = qemu_bh_new(ide_trim_bh_cb, iocb);
452 iocb->ret = 0;
501378c3
PB		 453 iocb->qiov = qiov;
454 iocb->i = -1;
455 iocb->j = 0;
456 ide_issue_trim_cb(iocb, 0);
d353fb72
CH		 457 return &iocb->common;
458}
459
5391d806
FB		 460static inline void ide_abort_command(IDEState *s)
461{
08ee9e33 462 ide_transfer_stop(s);
5391d806
FB		 463 s->status = READY_STAT | ERR_STAT;
464 s->error = ABRT_ERR;
465}
466
5391d806 467/* prepare data transfer and tell what to do after */
33231e0e
KW		 468void ide_transfer_start(IDEState *s, uint8_t *buf, int size,
469 EndTransferFunc *end_transfer_func)
5391d806
FB		 470{
471 s->end_transfer_func = end_transfer_func;
472 s->data_ptr = buf;
473 s->data_end = buf + size;
40a6238a 474 if (!(s->status & ERR_STAT)) {
7603d156 475 s->status |= DRQ_STAT;
40a6238a 476 }
44635123
PB		 477 if (s->bus->dma->ops->start_transfer) {
478 s->bus->dma->ops->start_transfer(s->bus->dma);
479 }
5391d806
FB		 480}
481
c7e73adb
PB		 482static void ide_cmd_done(IDEState *s)
483{
484 if (s->bus->dma->ops->cmd_done) {
485 s->bus->dma->ops->cmd_done(s->bus->dma);
486 }
487}
488
33231e0e 489void ide_transfer_stop(IDEState *s)
5391d806
FB		 490{
491 s->end_transfer_func = ide_transfer_stop;
492 s->data_ptr = s->io_buffer;
493 s->data_end = s->io_buffer;
494 s->status &= ~DRQ_STAT;
c7e73adb 495 ide_cmd_done(s);
5391d806
FB		 496}
497
356721ae 498int64_t ide_get_sector(IDEState *s)
5391d806
FB		 499{
500 int64_t sector_num;
501 if (s->select & 0x40) {
502 /* lba */
c2ff060f
FB		 503 if (!s->lba48) {
504 sector_num = ((s->select & 0x0f) << 24) | (s->hcyl << 16) |
505 (s->lcyl << 8) | s->sector;
506 } else {
507 sector_num = ((int64_t)s->hob_hcyl << 40) |
508 ((int64_t) s->hob_lcyl << 32) |
509 ((int64_t) s->hob_sector << 24) |
510 ((int64_t) s->hcyl << 16) |
511 ((int64_t) s->lcyl << 8) | s->sector;
512 }
5391d806
FB		 513 } else {
514 sector_num = ((s->hcyl << 8) | s->lcyl) * s->heads * s->sectors +
c2ff060f 515 (s->select & 0x0f) * s->sectors + (s->sector - 1);
5391d806
FB		 516 }
517 return sector_num;
518}
519
356721ae 520void ide_set_sector(IDEState *s, int64_t sector_num)
5391d806
FB		 521{
522 unsigned int cyl, r;
523 if (s->select & 0x40) {
c2ff060f
FB		 524 if (!s->lba48) {
525 s->select = (s->select & 0xf0) | (sector_num >> 24);
526 s->hcyl = (sector_num >> 16);
527 s->lcyl = (sector_num >> 8);
528 s->sector = (sector_num);
529 } else {
530 s->sector = sector_num;
531 s->lcyl = sector_num >> 8;
532 s->hcyl = sector_num >> 16;
533 s->hob_sector = sector_num >> 24;
534 s->hob_lcyl = sector_num >> 32;
535 s->hob_hcyl = sector_num >> 40;
536 }
5391d806
FB		 537 } else {
538 cyl = sector_num / (s->heads * s->sectors);
539 r = sector_num % (s->heads * s->sectors);
540 s->hcyl = cyl >> 8;
541 s->lcyl = cyl;
1b8eb456 542 s->select = (s->select & 0xf0) | ((r / s->sectors) & 0x0f);
5391d806
FB		 543 s->sector = (r % s->sectors) + 1;
544 }
545}
546
e162cfb0
AZ		 547static void ide_rw_error(IDEState *s) {
548 ide_abort_command(s);
9cdd03a7 549 ide_set_irq(s->bus);
e162cfb0
AZ		 550}
551
58ac3211
MA		 552static bool ide_sect_range_ok(IDEState *s,
553 uint64_t sector, uint64_t nb_sectors)
554{
555 uint64_t total_sectors;
556
4be74634 557 blk_get_geometry(s->blk, &total_sectors);
58ac3211
MA		 558 if (sector > total_sectors || nb_sectors > total_sectors - sector) {
559 return false;
560 }
561 return true;
562}
563
bef0fd59
SH		 564static void ide_sector_read_cb(void *opaque, int ret)
565{
566 IDEState *s = opaque;
567 int n;
568
569 s->pio_aiocb = NULL;
570 s->status &= ~BUSY_STAT;
571
0d910cfe
FZ		 572 if (ret == -ECANCELED) {
573 return;
574 }
4be74634 575 block_acct_done(blk_get_stats(s->blk), &s->acct);
bef0fd59 576 if (ret != 0) {
fd648f10
PB		 577 if (ide_handle_rw_error(s, -ret, IDE_RETRY_PIO |
578 IDE_RETRY_READ)) {
bef0fd59
SH		 579 return;
580 }
581 }
582
583 n = s->nsector;
584 if (n > s->req_nb_sectors) {
585 n = s->req_nb_sectors;
586 }
587
588 /* Allow the guest to read the io_buffer */
589 ide_transfer_start(s, s->io_buffer, n * BDRV_SECTOR_SIZE, ide_sector_read);
590
591 ide_set_irq(s->bus);
592
593 ide_set_sector(s, ide_get_sector(s) + n);
594 s->nsector -= n;
36334faf 595 s->io_buffer_offset += 512 * n;
bef0fd59
SH		 596}
597
40a6238a 598void ide_sector_read(IDEState *s)
5391d806
FB		 599{
600 int64_t sector_num;
bef0fd59 601 int n;
5391d806
FB		 602
603 s->status = READY_STAT | SEEK_STAT;
a136e5a8 604 s->error = 0; /* not needed by IDE spec, but needed by Windows */
5391d806
FB		 605 sector_num = ide_get_sector(s);
606 n = s->nsector;
bef0fd59 607
5391d806 608 if (n == 0) {
5391d806 609 ide_transfer_stop(s);
bef0fd59
SH		 610 return;
611 }
612
613 s->status |= BUSY_STAT;
614
615 if (n > s->req_nb_sectors) {
616 n = s->req_nb_sectors;
617 }
618
5391d806 619#if defined(DEBUG_IDE)
bef0fd59 620 printf("sector=%" PRId64 "\n", sector_num);
5391d806 621#endif
a597e79c 622
58ac3211
MA		 623 if (!ide_sect_range_ok(s, sector_num, n)) {
624 ide_rw_error(s);
625 return;
626 }
627
bef0fd59
SH		 628 s->iov.iov_base = s->io_buffer;
629 s->iov.iov_len = n * BDRV_SECTOR_SIZE;
630 qemu_iovec_init_external(&s->qiov, &s->iov, 1);
631
4be74634 632 block_acct_start(blk_get_stats(s->blk), &s->acct,
5366d0c8 633 n * BDRV_SECTOR_SIZE, BLOCK_ACCT_READ);
4be74634
MA		 634 s->pio_aiocb = blk_aio_readv(s->blk, sector_num, &s->qiov, n,
635 ide_sector_read_cb, s);
5391d806
FB		 636}
637
659142ec 638static void dma_buf_commit(IDEState *s, uint32_t tx_bytes)
7aea4412 639{
659142ec
JS		 640 if (s->bus->dma->ops->commit_buf) {
641 s->bus->dma->ops->commit_buf(s->bus->dma, tx_bytes);
642 }
1fb8648d 643 qemu_sglist_destroy(&s->sg);
7aea4412
AL		 644}
645
0e7ce54c 646void ide_set_inactive(IDEState *s, bool more)
8337606d 647{
40a6238a 648 s->bus->dma->aiocb = NULL;
a96cb236 649 s->bus->retry_unit = -1;
dc5d0af4
PB		 650 s->bus->retry_sector_num = 0;
651 s->bus->retry_nsector = 0;
829b933b 652 if (s->bus->dma->ops->set_inactive) {
0e7ce54c 653 s->bus->dma->ops->set_inactive(s->bus->dma, more);
829b933b 654 }
c7e73adb 655 ide_cmd_done(s);
8337606d
KW		 656}
657
356721ae 658void ide_dma_error(IDEState *s)
e162cfb0 659{
659142ec 660 dma_buf_commit(s, 0);
08ee9e33 661 ide_abort_command(s);
0e7ce54c 662 ide_set_inactive(s, false);
9cdd03a7 663 ide_set_irq(s->bus);
e162cfb0
AZ		 664}
665
ce4b6522 666static int ide_handle_rw_error(IDEState *s, int error, int op)
428c5705 667{
fd648f10 668 bool is_read = (op & IDE_RETRY_READ) != 0;
4be74634 669 BlockErrorAction action = blk_get_error_action(s->blk, is_read, error);
428c5705 670
a589569f 671 if (action == BLOCK_ERROR_ACTION_STOP) {
a96cb236 672 assert(s->bus->retry_unit == s->unit);
def93791 673 s->bus->error_status = op;
a589569f 674 } else if (action == BLOCK_ERROR_ACTION_REPORT) {
fd648f10 675 if (op & IDE_RETRY_DMA) {
428c5705 676 ide_dma_error(s);
7aea4412 677 } else {
428c5705 678 ide_rw_error(s);
7aea4412 679 }
428c5705 680 }
4be74634 681 blk_error_action(s->blk, action, is_read, error);
a589569f 682 return action != BLOCK_ERROR_ACTION_IGNORE;
428c5705
AL		 683}
684
cd369c46 685void ide_dma_cb(void *opaque, int ret)
98087450 686{
40a6238a 687 IDEState *s = opaque;
8ccad811
FB		 688 int n;
689 int64_t sector_num;
038268e2 690 bool stay_active = false;
8ccad811 691
0d910cfe
FZ		 692 if (ret == -ECANCELED) {
693 return;
694 }
e162cfb0 695 if (ret < 0) {
fd648f10 696 int op = IDE_RETRY_DMA;
cd369c46 697
4e1e0051 698 if (s->dma_cmd == IDE_DMA_READ)
fd648f10 699 op |= IDE_RETRY_READ;
d353fb72 700 else if (s->dma_cmd == IDE_DMA_TRIM)
fd648f10 701 op |= IDE_RETRY_TRIM;
d353fb72 702
cd369c46 703 if (ide_handle_rw_error(s, -ret, op)) {
ce4b6522
KW		 704 return;
705 }
e162cfb0
AZ		 706 }
707
8ccad811 708 n = s->io_buffer_size >> 9;
038268e2
KW		 709 if (n > s->nsector) {
710 /* The PRDs were longer than needed for this request. Shorten them so
711 * we don't get a negative remainder. The Active bit must remain set
712 * after the request completes. */
713 n = s->nsector;
714 stay_active = true;
715 }
716
8ccad811
FB		 717 sector_num = ide_get_sector(s);
718 if (n > 0) {
659142ec
JS		 719 assert(s->io_buffer_size == s->sg.size);
720 dma_buf_commit(s, s->io_buffer_size);
8ccad811
FB		 721 sector_num += n;
722 ide_set_sector(s, sector_num);
723 s->nsector -= n;
8ccad811
FB		 724 }
725
726 /* end of transfer ? */
727 if (s->nsector == 0) {
98087450 728 s->status = READY_STAT | SEEK_STAT;
9cdd03a7 729 ide_set_irq(s->bus);
cd369c46 730 goto eot;
98087450 731 }
8ccad811
FB		 732
733 /* launch next transfer */
734 n = s->nsector;
596bb44d 735 s->io_buffer_index = 0;
8ccad811 736 s->io_buffer_size = n * 512;
3251bdcf 737 if (s->bus->dma->ops->prepare_buf(s->bus->dma, ide_cmd_is_read(s)) < 512) {
69c38b8f
KW		 738 /* The PRDs were too short. Reset the Active bit, but don't raise an
739 * interrupt. */
72bcca73 740 s->status = READY_STAT | SEEK_STAT;
3251bdcf 741 dma_buf_commit(s, 0);
7aea4412 742 goto eot;
69c38b8f 743 }
cd369c46 744
8ccad811 745#ifdef DEBUG_AIO
4e1e0051
CH		 746 printf("ide_dma_cb: sector_num=%" PRId64 " n=%d, cmd_cmd=%d\n",
747 sector_num, n, s->dma_cmd);
8ccad811 748#endif
cd369c46 749
d66168ed
MT		 750 if ((s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) &&
751 !ide_sect_range_ok(s, sector_num, n)) {
58ac3211
MA		 752 ide_dma_error(s);
753 return;
754 }
755
4e1e0051
CH		 756 switch (s->dma_cmd) {
757 case IDE_DMA_READ:
4be74634
MA		 758 s->bus->dma->aiocb = dma_blk_read(s->blk, &s->sg, sector_num,
759 ide_dma_cb, s);
4e1e0051
CH		 760 break;
761 case IDE_DMA_WRITE:
4be74634
MA		 762 s->bus->dma->aiocb = dma_blk_write(s->blk, &s->sg, sector_num,
763 ide_dma_cb, s);
4e1e0051 764 break;
d353fb72 765 case IDE_DMA_TRIM:
4be74634
MA		 766 s->bus->dma->aiocb = dma_blk_io(s->blk, &s->sg, sector_num,
767 ide_issue_trim, ide_dma_cb, s,
768 DMA_DIRECTION_TO_DEVICE);
d353fb72 769 break;
cd369c46 770 }
cd369c46
CH		 771 return;
772
773eot:
a597e79c 774 if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) {
4be74634 775 block_acct_done(blk_get_stats(s->blk), &s->acct);
a597e79c 776 }
0e7ce54c 777 ide_set_inactive(s, stay_active);
98087450
FB		 778}
779
4e1e0051 780static void ide_sector_start_dma(IDEState *s, enum ide_dma_cmd dma_cmd)
98087450 781{
8ccad811 782 s->status = READY_STAT | SEEK_STAT | DRQ_STAT | BUSY_STAT;
98087450
FB		 783 s->io_buffer_index = 0;
784 s->io_buffer_size = 0;
4e1e0051 785 s->dma_cmd = dma_cmd;
a597e79c
CH		 786
787 switch (dma_cmd) {
788 case IDE_DMA_READ:
4be74634 789 block_acct_start(blk_get_stats(s->blk), &s->acct,
5366d0c8 790 s->nsector * BDRV_SECTOR_SIZE, BLOCK_ACCT_READ);
a597e79c
CH		 791 break;
792 case IDE_DMA_WRITE:
4be74634 793 block_acct_start(blk_get_stats(s->blk), &s->acct,
5366d0c8 794 s->nsector * BDRV_SECTOR_SIZE, BLOCK_ACCT_WRITE);
a597e79c
CH		 795 break;
796 default:
797 break;
798 }
799
4855b576
PB		 800 ide_start_dma(s, ide_dma_cb);
801}
802
097310b5 803void ide_start_dma(IDEState *s, BlockCompletionFunc *cb)
4855b576 804{
a96cb236 805 s->bus->retry_unit = s->unit;
dc5d0af4
PB		 806 s->bus->retry_sector_num = ide_get_sector(s);
807 s->bus->retry_nsector = s->nsector;
4855b576
PB		 808 if (s->bus->dma->ops->start_dma) {
809 s->bus->dma->ops->start_dma(s->bus->dma, s, cb);
810 }
98087450
FB		 811}
812
a09db21f
FB		 813static void ide_sector_write_timer_cb(void *opaque)
814{
815 IDEState *s = opaque;
9cdd03a7 816 ide_set_irq(s->bus);
a09db21f
FB		 817}
818
e82dabd8 819static void ide_sector_write_cb(void *opaque, int ret)
5391d806 820{
e82dabd8
SH		 821 IDEState *s = opaque;
822 int n;
a597e79c 823
0d910cfe
FZ		 824 if (ret == -ECANCELED) {
825 return;
826 }
4be74634 827 block_acct_done(blk_get_stats(s->blk), &s->acct);
428c5705 828
e82dabd8
SH		 829 s->pio_aiocb = NULL;
830 s->status &= ~BUSY_STAT;
831
e162cfb0 832 if (ret != 0) {
fd648f10 833 if (ide_handle_rw_error(s, -ret, IDE_RETRY_PIO)) {
428c5705 834 return;
e82dabd8 835 }
e162cfb0
AZ		 836 }
837
e82dabd8
SH		 838 n = s->nsector;
839 if (n > s->req_nb_sectors) {
840 n = s->req_nb_sectors;
841 }
5391d806 842 s->nsector -= n;
36334faf
JS		 843 s->io_buffer_offset += 512 * n;
844
5391d806 845 if (s->nsector == 0) {
292eef5a 846 /* no more sectors to write */
5391d806
FB		 847 ide_transfer_stop(s);
848 } else {
e82dabd8
SH		 849 int n1 = s->nsector;
850 if (n1 > s->req_nb_sectors) {
5391d806 851 n1 = s->req_nb_sectors;
e82dabd8
SH		 852 }
853 ide_transfer_start(s, s->io_buffer, n1 * BDRV_SECTOR_SIZE,
854 ide_sector_write);
5391d806 855 }
e82dabd8 856 ide_set_sector(s, ide_get_sector(s) + n);
3b46e624 857
31c2a146
TS		 858 if (win2k_install_hack && ((++s->irq_count % 16) == 0)) {
859 /* It seems there is a bug in the Windows 2000 installer HDD
860 IDE driver which fills the disk with empty logs when the
861 IDE write IRQ comes too early. This hack tries to correct
862 that at the expense of slower write performances. Use this
863 option _only_ to install Windows 2000. You must disable it
864 for normal use. */
bc72ad67
AB		 865 timer_mod(s->sector_write_timer,
866 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + (get_ticks_per_sec() / 1000));
f7736b91 867 } else {
9cdd03a7 868 ide_set_irq(s->bus);
31c2a146 869 }
5391d806
FB		 870}
871
e82dabd8
SH		 872void ide_sector_write(IDEState *s)
873{
874 int64_t sector_num;
875 int n;
876
877 s->status = READY_STAT | SEEK_STAT | BUSY_STAT;
878 sector_num = ide_get_sector(s);
879#if defined(DEBUG_IDE)
880 printf("sector=%" PRId64 "\n", sector_num);
881#endif
882 n = s->nsector;
883 if (n > s->req_nb_sectors) {
884 n = s->req_nb_sectors;
885 }
886
58ac3211
MA		 887 if (!ide_sect_range_ok(s, sector_num, n)) {
888 ide_rw_error(s);
889 return;
890 }
891
e82dabd8
SH		 892 s->iov.iov_base = s->io_buffer;
893 s->iov.iov_len = n * BDRV_SECTOR_SIZE;
894 qemu_iovec_init_external(&s->qiov, &s->iov, 1);
895
4be74634 896 block_acct_start(blk_get_stats(s->blk), &s->acct,
5366d0c8 897 n * BDRV_SECTOR_SIZE, BLOCK_ACCT_READ);
4be74634
MA		 898 s->pio_aiocb = blk_aio_writev(s->blk, sector_num, &s->qiov, n,
899 ide_sector_write_cb, s);
e82dabd8
SH		 900}
901
b0484ae4
CH		 902static void ide_flush_cb(void *opaque, int ret)
903{
904 IDEState *s = opaque;
905
69f72a22
PB		 906 s->pio_aiocb = NULL;
907
0d910cfe
FZ		 908 if (ret == -ECANCELED) {
909 return;
910 }
e2bcadad
KW		 911 if (ret < 0) {
912 /* XXX: What sector number to set here? */
fd648f10 913 if (ide_handle_rw_error(s, -ret, IDE_RETRY_FLUSH)) {
e2bcadad
KW		 914 return;
915 }
916 }
b0484ae4 917
4be74634
MA		 918 if (s->blk) {
919 block_acct_done(blk_get_stats(s->blk), &s->acct);
f7f3ff1d 920 }
b0484ae4 921 s->status = READY_STAT | SEEK_STAT;
c7e73adb 922 ide_cmd_done(s);
b0484ae4
CH		 923 ide_set_irq(s->bus);
924}
925
40a6238a 926void ide_flush_cache(IDEState *s)
6bcb1a79 927{
4be74634 928 if (s->blk == NULL) {
6bcb1a79 929 ide_flush_cb(s, 0);
b2df7531
KW		 930 return;
931 }
932
f68ec837 933 s->status |= BUSY_STAT;
4be74634
MA		 934 block_acct_start(blk_get_stats(s->blk), &s->acct, 0, BLOCK_ACCT_FLUSH);
935 s->pio_aiocb = blk_aio_flush(s->blk, ide_flush_cb, s);
6bcb1a79
KW		 936}
937
201a51fc
AZ		 938static void ide_cfata_metadata_inquiry(IDEState *s)
939{
940 uint16_t *p;
941 uint32_t spd;
942
943 p = (uint16_t *) s->io_buffer;
944 memset(p, 0, 0x200);
945 spd = ((s->mdata_size - 1) >> 9) + 1;
946
947 put_le16(p + 0, 0x0001); /* Data format revision */
948 put_le16(p + 1, 0x0000); /* Media property: silicon */
949 put_le16(p + 2, s->media_changed); /* Media status */
950 put_le16(p + 3, s->mdata_size & 0xffff); /* Capacity in bytes (low) */
951 put_le16(p + 4, s->mdata_size >> 16); /* Capacity in bytes (high) */
952 put_le16(p + 5, spd & 0xffff); /* Sectors per device (low) */
953 put_le16(p + 6, spd >> 16); /* Sectors per device (high) */
954}
955
956static void ide_cfata_metadata_read(IDEState *s)
957{
958 uint16_t *p;
959
960 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
961 s->status = ERR_STAT;
962 s->error = ABRT_ERR;
963 return;
964 }
965
966 p = (uint16_t *) s->io_buffer;
967 memset(p, 0, 0x200);
968
969 put_le16(p + 0, s->media_changed); /* Media status */
970 memcpy(p + 1, s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
971 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
972 s->nsector << 9), 0x200 - 2));
973}
974
975static void ide_cfata_metadata_write(IDEState *s)
976{
977 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
978 s->status = ERR_STAT;
979 s->error = ABRT_ERR;
980 return;
981 }
982
983 s->media_changed = 0;
984
985 memcpy(s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
986 s->io_buffer + 2,
987 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
988 s->nsector << 9), 0x200 - 2));
989}
990
bd491d6a 991/* called when the inserted state of the media has changed */
7d4b4ba5 992static void ide_cd_change_cb(void *opaque, bool load)
bd491d6a
TS		 993{
994 IDEState *s = opaque;
96b8f136 995 uint64_t nb_sectors;
bd491d6a 996
25ad22bc 997 s->tray_open = !load;
4be74634 998 blk_get_geometry(s->blk, &nb_sectors);
bd491d6a 999 s->nb_sectors = nb_sectors;
9118e7f0 1000
4b9b7092
AS		 1001 /*
1002 * First indicate to the guest that a CD has been removed. That's
1003 * done on the next command the guest sends us.
1004 *
67cc61e4 1005 * Then we set UNIT_ATTENTION, by which the guest will
4b9b7092
AS		 1006 * detect a new CD in the drive. See ide_atapi_cmd() for details.
1007 */
93c8cfd9 1008 s->cdrom_changed = 1;
996faf1a 1009 s->events.new_media = true;
2df0a3a3
PB		 1010 s->events.eject_request = false;
1011 ide_set_irq(s->bus);
1012}
1013
1014static void ide_cd_eject_request_cb(void *opaque, bool force)
1015{
1016 IDEState *s = opaque;
1017
1018 s->events.eject_request = true;
1019 if (force) {
1020 s->tray_locked = false;
1021 }
9cdd03a7 1022 ide_set_irq(s->bus);
bd491d6a
TS		 1023}
1024
c2ff060f
FB		 1025static void ide_cmd_lba48_transform(IDEState *s, int lba48)
1026{
1027 s->lba48 = lba48;
1028
1029 /* handle the 'magic' 0 nsector count conversion here. to avoid
1030 * fiddling with the rest of the read logic, we just store the
1031 * full sector count in ->nsector and ignore ->hob_nsector from now
1032 */
1033 if (!s->lba48) {
1034 if (!s->nsector)
1035 s->nsector = 256;
1036 } else {
1037 if (!s->nsector && !s->hob_nsector)
1038 s->nsector = 65536;
1039 else {
1040 int lo = s->nsector;
1041 int hi = s->hob_nsector;
1042
1043 s->nsector = (hi << 8) | lo;
1044 }
1045 }
1046}
1047
bcbdc4d3 1048static void ide_clear_hob(IDEBus *bus)
c2ff060f
FB		 1049{
1050 /* any write clears HOB high bit of device control register */
bcbdc4d3
GH		 1051 bus->ifs[0].select &= ~(1 << 7);
1052 bus->ifs[1].select &= ~(1 << 7);
c2ff060f
FB		 1053}
1054
356721ae 1055void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
caed8802 1056{
bcbdc4d3 1057 IDEBus *bus = opaque;
5391d806
FB		 1058
1059#ifdef DEBUG_IDE
1060 printf("IDE: write addr=0x%x val=0x%02x\n", addr, val);
1061#endif
c2ff060f 1062
5391d806 1063 addr &= 7;
fcdd25ab
AL		 1064
1065 /* ignore writes to command block while busy with previous command */
bcbdc4d3 1066 if (addr != 7 && (idebus_active_if(bus)->status & (BUSY_STAT|DRQ_STAT)))
fcdd25ab
AL		 1067 return;
1068
5391d806
FB		 1069 switch(addr) {
1070 case 0:
1071 break;
1072 case 1:
bcbdc4d3 1073 ide_clear_hob(bus);
c45c3d00 1074 /* NOTE: data is written to the two drives */
bcbdc4d3
GH		 1075 bus->ifs[0].hob_feature = bus->ifs[0].feature;
1076 bus->ifs[1].hob_feature = bus->ifs[1].feature;
1077 bus->ifs[0].feature = val;
1078 bus->ifs[1].feature = val;
5391d806
FB		 1079 break;
1080 case 2:
bcbdc4d3
GH		 1081 ide_clear_hob(bus);
1082 bus->ifs[0].hob_nsector = bus->ifs[0].nsector;
1083 bus->ifs[1].hob_nsector = bus->ifs[1].nsector;
1084 bus->ifs[0].nsector = val;
1085 bus->ifs[1].nsector = val;
5391d806
FB		 1086 break;
1087 case 3:
bcbdc4d3
GH		 1088 ide_clear_hob(bus);
1089 bus->ifs[0].hob_sector = bus->ifs[0].sector;
1090 bus->ifs[1].hob_sector = bus->ifs[1].sector;
1091 bus->ifs[0].sector = val;
1092 bus->ifs[1].sector = val;
5391d806
FB		 1093 break;
1094 case 4:
bcbdc4d3
GH		 1095 ide_clear_hob(bus);
1096 bus->ifs[0].hob_lcyl = bus->ifs[0].lcyl;
1097 bus->ifs[1].hob_lcyl = bus->ifs[1].lcyl;
1098 bus->ifs[0].lcyl = val;
1099 bus->ifs[1].lcyl = val;
5391d806
FB		 1100 break;
1101 case 5:
bcbdc4d3
GH		 1102 ide_clear_hob(bus);
1103 bus->ifs[0].hob_hcyl = bus->ifs[0].hcyl;
1104 bus->ifs[1].hob_hcyl = bus->ifs[1].hcyl;
1105 bus->ifs[0].hcyl = val;
1106 bus->ifs[1].hcyl = val;
5391d806
FB		 1107 break;
1108 case 6:
c2ff060f 1109 /* FIXME: HOB readback uses bit 7 */
bcbdc4d3
GH		 1110 bus->ifs[0].select = (val & ~0x10) | 0xa0;
1111 bus->ifs[1].select = (val | 0x10) | 0xa0;
5391d806 1112 /* select drive */
bcbdc4d3 1113 bus->unit = (val >> 4) & 1;
5391d806
FB		 1114 break;
1115 default:
1116 case 7:
1117 /* command */
7cff87ff
AG		 1118 ide_exec_cmd(bus, val);
1119 break;
1120 }
1121}
1122
b300337e
KW		 1123static bool cmd_nop(IDEState *s, uint8_t cmd)
1124{
1125 return true;
1126}
1127
4286434c
KW		 1128static bool cmd_data_set_management(IDEState *s, uint8_t cmd)
1129{
1130 switch (s->feature) {
1131 case DSM_TRIM:
4be74634 1132 if (s->blk) {
4286434c
KW		 1133 ide_sector_start_dma(s, IDE_DMA_TRIM);
1134 return false;
1135 }
1136 break;
1137 }
1138
1139 ide_abort_command(s);
1140 return true;
1141}
1142
1c66869a
KW		 1143static bool cmd_identify(IDEState *s, uint8_t cmd)
1144{
4be74634 1145 if (s->blk && s->drive_kind != IDE_CD) {
1c66869a
KW		 1146 if (s->drive_kind != IDE_CFATA) {
1147 ide_identify(s);
1148 } else {
1149 ide_cfata_identify(s);
1150 }
1151 s->status = READY_STAT | SEEK_STAT;
1152 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
1153 ide_set_irq(s->bus);
1154 return false;
1155 } else {
1156 if (s->drive_kind == IDE_CD) {
1157 ide_set_signature(s);
1158 }
1159 ide_abort_command(s);
1160 }
1161
1162 return true;
1163}
1164
413860cf
KW		 1165static bool cmd_verify(IDEState *s, uint8_t cmd)
1166{
1167 bool lba48 = (cmd == WIN_VERIFY_EXT);
1168
1169 /* do sector number check ? */
1170 ide_cmd_lba48_transform(s, lba48);
1171
1172 return true;
1173}
1174
adf3a2c4
KW		 1175static bool cmd_set_multiple_mode(IDEState *s, uint8_t cmd)
1176{
1177 if (s->drive_kind == IDE_CFATA && s->nsector == 0) {
1178 /* Disable Read and Write Multiple */
1179 s->mult_sectors = 0;
1180 } else if ((s->nsector & 0xff) != 0 &&
1181 ((s->nsector & 0xff) > MAX_MULT_SECTORS ||
1182 (s->nsector & (s->nsector - 1)) != 0)) {
1183 ide_abort_command(s);
1184 } else {
1185 s->mult_sectors = s->nsector & 0xff;
1186 }
1187
1188 return true;
1189}
1190
1191static bool cmd_read_multiple(IDEState *s, uint8_t cmd)
1192{
1193 bool lba48 = (cmd == WIN_MULTREAD_EXT);
1194
4be74634 1195 if (!s->blk || !s->mult_sectors) {
adf3a2c4
KW		 1196 ide_abort_command(s);
1197 return true;
1198 }
1199
1200 ide_cmd_lba48_transform(s, lba48);
1201 s->req_nb_sectors = s->mult_sectors;
1202 ide_sector_read(s);
1203 return false;
1204}
1205
1206static bool cmd_write_multiple(IDEState *s, uint8_t cmd)
1207{
1208 bool lba48 = (cmd == WIN_MULTWRITE_EXT);
1209 int n;
1210
4be74634 1211 if (!s->blk || !s->mult_sectors) {
adf3a2c4
KW		 1212 ide_abort_command(s);
1213 return true;
1214 }
1215
1216 ide_cmd_lba48_transform(s, lba48);
1217
1218 s->req_nb_sectors = s->mult_sectors;
1219 n = MIN(s->nsector, s->req_nb_sectors);
1220
1221 s->status = SEEK_STAT | READY_STAT;
1222 ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_write);
1223
1224 s->media_changed = 1;
1225
1226 return false;
1227}
1228
0e6498ed
KW		 1229static bool cmd_read_pio(IDEState *s, uint8_t cmd)
1230{
1231 bool lba48 = (cmd == WIN_READ_EXT);
1232
1233 if (s->drive_kind == IDE_CD) {
1234 ide_set_signature(s); /* odd, but ATA4 8.27.5.2 requires it */
1235 ide_abort_command(s);
1236 return true;
1237 }
1238
4be74634 1239 if (!s->blk) {
0e6498ed
KW		 1240 ide_abort_command(s);
1241 return true;
1242 }
1243
1244 ide_cmd_lba48_transform(s, lba48);
1245 s->req_nb_sectors = 1;
1246 ide_sector_read(s);
1247
1248 return false;
1249}
1250
1251static bool cmd_write_pio(IDEState *s, uint8_t cmd)
1252{
1253 bool lba48 = (cmd == WIN_WRITE_EXT);
1254
4be74634 1255 if (!s->blk) {
0e6498ed
KW		 1256 ide_abort_command(s);
1257 return true;
1258 }
1259
1260 ide_cmd_lba48_transform(s, lba48);
1261
1262 s->req_nb_sectors = 1;
1263 s->status = SEEK_STAT | READY_STAT;
1264 ide_transfer_start(s, s->io_buffer, 512, ide_sector_write);
1265
1266 s->media_changed = 1;
1267
1268 return false;
1269}
1270
92a6a6f6
KW		 1271static bool cmd_read_dma(IDEState *s, uint8_t cmd)
1272{
1273 bool lba48 = (cmd == WIN_READDMA_EXT);
1274
4be74634 1275 if (!s->blk) {
92a6a6f6
KW		 1276 ide_abort_command(s);
1277 return true;
1278 }
1279
1280 ide_cmd_lba48_transform(s, lba48);
1281 ide_sector_start_dma(s, IDE_DMA_READ);
1282
1283 return false;
1284}
1285
1286static bool cmd_write_dma(IDEState *s, uint8_t cmd)
1287{
1288 bool lba48 = (cmd == WIN_WRITEDMA_EXT);
1289
4be74634 1290 if (!s->blk) {
92a6a6f6
KW		 1291 ide_abort_command(s);
1292 return true;
1293 }
1294
1295 ide_cmd_lba48_transform(s, lba48);
1296 ide_sector_start_dma(s, IDE_DMA_WRITE);
1297
1298 s->media_changed = 1;
1299
1300 return false;
1301}
1302
9afce429
KW		 1303static bool cmd_flush_cache(IDEState *s, uint8_t cmd)
1304{
1305 ide_flush_cache(s);
1306 return false;
1307}
1308
61fdda37
KW		 1309static bool cmd_seek(IDEState *s, uint8_t cmd)
1310{
1311 /* XXX: Check that seek is within bounds */
1312 return true;
1313}
1314
63a82e6a
KW		 1315static bool cmd_read_native_max(IDEState *s, uint8_t cmd)
1316{
1317 bool lba48 = (cmd == WIN_READ_NATIVE_MAX_EXT);
1318
1319 /* Refuse if no sectors are addressable (e.g. medium not inserted) */
1320 if (s->nb_sectors == 0) {
1321 ide_abort_command(s);
1322 return true;
1323 }
1324
1325 ide_cmd_lba48_transform(s, lba48);
1326 ide_set_sector(s, s->nb_sectors - 1);
1327
1328 return true;
1329}
1330
785f6320
KW		 1331static bool cmd_check_power_mode(IDEState *s, uint8_t cmd)
1332{
1333 s->nsector = 0xff; /* device active or idle */
1334 return true;
1335}
1336
ee03398c
KW		 1337static bool cmd_set_features(IDEState *s, uint8_t cmd)
1338{
1339 uint16_t *identify_data;
1340
4be74634 1341 if (!s->blk) {
ee03398c
KW		 1342 ide_abort_command(s);
1343 return true;
1344 }
1345
1346 /* XXX: valid for CDROM ? */
1347 switch (s->feature) {
1348 case 0x02: /* write cache enable */
4be74634 1349 blk_set_enable_write_cache(s->blk, true);
ee03398c
KW		 1350 identify_data = (uint16_t *)s->identify_data;
1351 put_le16(identify_data + 85, (1 << 14) | (1 << 5) | 1);
1352 return true;
1353 case 0x82: /* write cache disable */
4be74634 1354 blk_set_enable_write_cache(s->blk, false);
ee03398c
KW		 1355 identify_data = (uint16_t *)s->identify_data;
1356 put_le16(identify_data + 85, (1 << 14) | 1);
1357 ide_flush_cache(s);
1358 return false;
1359 case 0xcc: /* reverting to power-on defaults enable */
1360 case 0x66: /* reverting to power-on defaults disable */
1361 case 0xaa: /* read look-ahead enable */
1362 case 0x55: /* read look-ahead disable */
1363 case 0x05: /* set advanced power management mode */
1364 case 0x85: /* disable advanced power management mode */
1365 case 0x69: /* NOP */
1366 case 0x67: /* NOP */
1367 case 0x96: /* NOP */
1368 case 0x9a: /* NOP */
1369 case 0x42: /* enable Automatic Acoustic Mode */
1370 case 0xc2: /* disable Automatic Acoustic Mode */
1371 return true;
1372 case 0x03: /* set transfer mode */
1373 {
1374 uint8_t val = s->nsector & 0x07;
1375 identify_data = (uint16_t *)s->identify_data;
1376
1377 switch (s->nsector >> 3) {
1378 case 0x00: /* pio default */
1379 case 0x01: /* pio mode */
1380 put_le16(identify_data + 62, 0x07);
1381 put_le16(identify_data + 63, 0x07);
1382 put_le16(identify_data + 88, 0x3f);
1383 break;
1384 case 0x02: /* sigle word dma mode*/
1385 put_le16(identify_data + 62, 0x07 | (1 << (val + 8)));
1386 put_le16(identify_data + 63, 0x07);
1387 put_le16(identify_data + 88, 0x3f);
1388 break;
1389 case 0x04: /* mdma mode */
1390 put_le16(identify_data + 62, 0x07);
1391 put_le16(identify_data + 63, 0x07 | (1 << (val + 8)));
1392 put_le16(identify_data + 88, 0x3f);
1393 break;
1394 case 0x08: /* udma mode */
1395 put_le16(identify_data + 62, 0x07);
1396 put_le16(identify_data + 63, 0x07);
1397 put_le16(identify_data + 88, 0x3f | (1 << (val + 8)));
1398 break;
1399 default:
1400 goto abort_cmd;
1401 }
1402 return true;
1403 }
1404 }
1405
1406abort_cmd:
1407 ide_abort_command(s);
1408 return true;
1409}
1410
ee425c78
KW		 1411
1412/*** ATAPI commands ***/
1413
1414static bool cmd_identify_packet(IDEState *s, uint8_t cmd)
1415{
1416 ide_atapi_identify(s);
1417 s->status = READY_STAT | SEEK_STAT;
1418 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
1419 ide_set_irq(s->bus);
1420 return false;
1421}
1422
1423static bool cmd_exec_dev_diagnostic(IDEState *s, uint8_t cmd)
1424{
1425 ide_set_signature(s);
1426
1427 if (s->drive_kind == IDE_CD) {
1428 s->status = 0; /* ATAPI spec (v6) section 9.10 defines packet
1429 * devices to return a clear status register
1430 * with READY_STAT *not* set. */
850484a2 1431 s->error = 0x01;
ee425c78
KW		 1432 } else {
1433 s->status = READY_STAT | SEEK_STAT;
1434 /* The bits of the error register are not as usual for this command!
1435 * They are part of the regular output (this is why ERR_STAT isn't set)
1436 * Device 0 passed, Device 1 passed or not present. */
1437 s->error = 0x01;
1438 ide_set_irq(s->bus);
1439 }
1440
1441 return false;
1442}
1443
1444static bool cmd_device_reset(IDEState *s, uint8_t cmd)
1445{
1446 ide_set_signature(s);
1447 s->status = 0x00; /* NOTE: READY is _not_ set */
1448 s->error = 0x01;
1449
1450 return false;
1451}
1452
1453static bool cmd_packet(IDEState *s, uint8_t cmd)
1454{
1455 /* overlapping commands not supported */
1456 if (s->feature & 0x02) {
1457 ide_abort_command(s);
1458 return true;
1459 }
1460
1461 s->status = READY_STAT | SEEK_STAT;
1462 s->atapi_dma = s->feature & 1;
1463 s->nsector = 1;
1464 ide_transfer_start(s, s->io_buffer, ATAPI_PACKET_SIZE,
1465 ide_atapi_cmd);
1466 return false;
1467}
1468
6b1dd744
KW		 1469
1470/*** CF-ATA commands ***/
1471
1472static bool cmd_cfa_req_ext_error_code(IDEState *s, uint8_t cmd)
1473{
1474 s->error = 0x09; /* miscellaneous error */
1475 s->status = READY_STAT | SEEK_STAT;
1476 ide_set_irq(s->bus);
1477
1478 return false;
1479}
1480
1481static bool cmd_cfa_erase_sectors(IDEState *s, uint8_t cmd)
1482{
1483 /* WIN_SECURITY_FREEZE_LOCK has the same ID as CFA_WEAR_LEVEL and is
1484 * required for Windows 8 to work with AHCI */
1485
1486 if (cmd == CFA_WEAR_LEVEL) {
1487 s->nsector = 0;
1488 }
1489
1490 if (cmd == CFA_ERASE_SECTORS) {
1491 s->media_changed = 1;
1492 }
1493
1494 return true;
1495}
1496
1497static bool cmd_cfa_translate_sector(IDEState *s, uint8_t cmd)
1498{
1499 s->status = READY_STAT | SEEK_STAT;
1500
1501 memset(s->io_buffer, 0, 0x200);
1502 s->io_buffer[0x00] = s->hcyl; /* Cyl MSB */
1503 s->io_buffer[0x01] = s->lcyl; /* Cyl LSB */
1504 s->io_buffer[0x02] = s->select; /* Head */
1505 s->io_buffer[0x03] = s->sector; /* Sector */
1506 s->io_buffer[0x04] = ide_get_sector(s) >> 16; /* LBA MSB */
1507 s->io_buffer[0x05] = ide_get_sector(s) >> 8; /* LBA */
1508 s->io_buffer[0x06] = ide_get_sector(s) >> 0; /* LBA LSB */
1509 s->io_buffer[0x13] = 0x00; /* Erase flag */
1510 s->io_buffer[0x18] = 0x00; /* Hot count */
1511 s->io_buffer[0x19] = 0x00; /* Hot count */
1512 s->io_buffer[0x1a] = 0x01; /* Hot count */
1513
1514 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1515 ide_set_irq(s->bus);
1516
1517 return false;
1518}
1519
1520static bool cmd_cfa_access_metadata_storage(IDEState *s, uint8_t cmd)
1521{
1522 switch (s->feature) {
1523 case 0x02: /* Inquiry Metadata Storage */
1524 ide_cfata_metadata_inquiry(s);
1525 break;
1526 case 0x03: /* Read Metadata Storage */
1527 ide_cfata_metadata_read(s);
1528 break;
1529 case 0x04: /* Write Metadata Storage */
1530 ide_cfata_metadata_write(s);
1531 break;
1532 default:
1533 ide_abort_command(s);
1534 return true;
1535 }
1536
1537 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1538 s->status = 0x00; /* NOTE: READY is _not_ set */
1539 ide_set_irq(s->bus);
1540
1541 return false;
1542}
1543
1544static bool cmd_ibm_sense_condition(IDEState *s, uint8_t cmd)
1545{
1546 switch (s->feature) {
1547 case 0x01: /* sense temperature in device */
1548 s->nsector = 0x50; /* +20 C */
1549 break;
1550 default:
1551 ide_abort_command(s);
1552 return true;
1553 }
1554
1555 return true;
1556}
1557
ff352677
KW		 1558
1559/*** SMART commands ***/
1560
1561static bool cmd_smart(IDEState *s, uint8_t cmd)
1562{
1563 int n;
1564
1565 if (s->hcyl != 0xc2 || s->lcyl != 0x4f) {
1566 goto abort_cmd;
1567 }
1568
1569 if (!s->smart_enabled && s->feature != SMART_ENABLE) {
1570 goto abort_cmd;
1571 }
1572
1573 switch (s->feature) {
1574 case SMART_DISABLE:
1575 s->smart_enabled = 0;
1576 return true;
1577
1578 case SMART_ENABLE:
1579 s->smart_enabled = 1;
1580 return true;
1581
1582 case SMART_ATTR_AUTOSAVE:
1583 switch (s->sector) {
1584 case 0x00:
1585 s->smart_autosave = 0;
1586 break;
1587 case 0xf1:
1588 s->smart_autosave = 1;
1589 break;
1590 default:
1591 goto abort_cmd;
1592 }
1593 return true;
1594
1595 case SMART_STATUS:
1596 if (!s->smart_errors) {
1597 s->hcyl = 0xc2;
1598 s->lcyl = 0x4f;
1599 } else {
1600 s->hcyl = 0x2c;
1601 s->lcyl = 0xf4;
1602 }
1603 return true;
1604
1605 case SMART_READ_THRESH:
1606 memset(s->io_buffer, 0, 0x200);
1607 s->io_buffer[0] = 0x01; /* smart struct version */
1608
1609 for (n = 0; n < ARRAY_SIZE(smart_attributes); n++) {
1610 s->io_buffer[2 + 0 + (n * 12)] = smart_attributes[n][0];
1611 s->io_buffer[2 + 1 + (n * 12)] = smart_attributes[n][11];
1612 }
1613
1614 /* checksum */
1615 for (n = 0; n < 511; n++) {
1616 s->io_buffer[511] += s->io_buffer[n];
1617 }
1618 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1619
1620 s->status = READY_STAT | SEEK_STAT;
1621 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1622 ide_set_irq(s->bus);
1623 return false;
1624
1625 case SMART_READ_DATA:
1626 memset(s->io_buffer, 0, 0x200);
1627 s->io_buffer[0] = 0x01; /* smart struct version */
1628
1629 for (n = 0; n < ARRAY_SIZE(smart_attributes); n++) {
1630 int i;
1631 for (i = 0; i < 11; i++) {
1632 s->io_buffer[2 + i + (n * 12)] = smart_attributes[n][i];
1633 }
1634 }
1635
1636 s->io_buffer[362] = 0x02 | (s->smart_autosave ? 0x80 : 0x00);
1637 if (s->smart_selftest_count == 0) {
1638 s->io_buffer[363] = 0;
1639 } else {
1640 s->io_buffer[363] =
1641 s->smart_selftest_data[3 +
1642 (s->smart_selftest_count - 1) *
1643 24];
1644 }
1645 s->io_buffer[364] = 0x20;
1646 s->io_buffer[365] = 0x01;
1647 /* offline data collection capacity: execute + self-test*/
1648 s->io_buffer[367] = (1 << 4 | 1 << 3 | 1);
1649 s->io_buffer[368] = 0x03; /* smart capability (1) */
1650 s->io_buffer[369] = 0x00; /* smart capability (2) */
1651 s->io_buffer[370] = 0x01; /* error logging supported */
1652 s->io_buffer[372] = 0x02; /* minutes for poll short test */
1653 s->io_buffer[373] = 0x36; /* minutes for poll ext test */
1654 s->io_buffer[374] = 0x01; /* minutes for poll conveyance */
1655
1656 for (n = 0; n < 511; n++) {
1657 s->io_buffer[511] += s->io_buffer[n];
1658 }
1659 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1660
1661 s->status = READY_STAT | SEEK_STAT;
1662 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1663 ide_set_irq(s->bus);
1664 return false;
1665
1666 case SMART_READ_LOG:
1667 switch (s->sector) {
1668 case 0x01: /* summary smart error log */
1669 memset(s->io_buffer, 0, 0x200);
1670 s->io_buffer[0] = 0x01;
1671 s->io_buffer[1] = 0x00; /* no error entries */
1672 s->io_buffer[452] = s->smart_errors & 0xff;
1673 s->io_buffer[453] = (s->smart_errors & 0xff00) >> 8;
1674
1675 for (n = 0; n < 511; n++) {
1676 s->io_buffer[511] += s->io_buffer[n];
1677 }
1678 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1679 break;
1680 case 0x06: /* smart self test log */
1681 memset(s->io_buffer, 0, 0x200);
1682 s->io_buffer[0] = 0x01;
1683 if (s->smart_selftest_count == 0) {
1684 s->io_buffer[508] = 0;
1685 } else {
1686 s->io_buffer[508] = s->smart_selftest_count;
1687 for (n = 2; n < 506; n++) {
1688 s->io_buffer[n] = s->smart_selftest_data[n];
1689 }
1690 }
1691
1692 for (n = 0; n < 511; n++) {
1693 s->io_buffer[511] += s->io_buffer[n];
1694 }
1695 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1696 break;
1697 default:
1698 goto abort_cmd;
1699 }
1700 s->status = READY_STAT | SEEK_STAT;
1701 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1702 ide_set_irq(s->bus);
1703 return false;
1704
1705 case SMART_EXECUTE_OFFLINE:
1706 switch (s->sector) {
1707 case 0: /* off-line routine */
1708 case 1: /* short self test */
1709 case 2: /* extended self test */
1710 s->smart_selftest_count++;
1711 if (s->smart_selftest_count > 21) {
940973ae 1712 s->smart_selftest_count = 1;
ff352677
KW		 1713 }
1714 n = 2 + (s->smart_selftest_count - 1) * 24;
1715 s->smart_selftest_data[n] = s->sector;
1716 s->smart_selftest_data[n + 1] = 0x00; /* OK and finished */
1717 s->smart_selftest_data[n + 2] = 0x34; /* hour count lsb */
1718 s->smart_selftest_data[n + 3] = 0x12; /* hour count msb */
1719 break;
1720 default:
1721 goto abort_cmd;
1722 }
1723 return true;
1724 }
1725
1726abort_cmd:
1727 ide_abort_command(s);
1728 return true;
1729}
1730
844505b1
MA		 1731#define HD_OK (1u << IDE_HD)
1732#define CD_OK (1u << IDE_CD)
1733#define CFA_OK (1u << IDE_CFATA)
1734#define HD_CFA_OK (HD_OK | CFA_OK)
1735#define ALL_OK (HD_OK | CD_OK | CFA_OK)
1736
a0436e92
KW		 1737/* Set the Disk Seek Completed status bit during completion */
1738#define SET_DSC (1u << 8)
1739
844505b1 1740/* See ACS-2 T13/2015-D Table B.2 Command codes */
a0436e92
KW		 1741static const struct {
1742 /* Returns true if the completion code should be run */
1743 bool (*handler)(IDEState *s, uint8_t cmd);
1744 int flags;
1745} ide_cmd_table[0x100] = {
844505b1 1746 /* NOP not implemented, mandatory for CD */
6b1dd744 1747 [CFA_REQ_EXT_ERROR_CODE] = { cmd_cfa_req_ext_error_code, CFA_OK },
4286434c 1748 [WIN_DSM] = { cmd_data_set_management, ALL_OK },
ee425c78 1749 [WIN_DEVICE_RESET] = { cmd_device_reset, CD_OK },
b300337e 1750 [WIN_RECAL] = { cmd_nop, HD_CFA_OK | SET_DSC},
0e6498ed
KW		 1751 [WIN_READ] = { cmd_read_pio, ALL_OK },
1752 [WIN_READ_ONCE] = { cmd_read_pio, ALL_OK },
1753 [WIN_READ_EXT] = { cmd_read_pio, HD_CFA_OK },
92a6a6f6 1754 [WIN_READDMA_EXT] = { cmd_read_dma, HD_CFA_OK },
63a82e6a 1755 [WIN_READ_NATIVE_MAX_EXT] = { cmd_read_native_max, HD_CFA_OK | SET_DSC },
adf3a2c4 1756 [WIN_MULTREAD_EXT] = { cmd_read_multiple, HD_CFA_OK },
0e6498ed
KW		 1757 [WIN_WRITE] = { cmd_write_pio, HD_CFA_OK },
1758 [WIN_WRITE_ONCE] = { cmd_write_pio, HD_CFA_OK },
1759 [WIN_WRITE_EXT] = { cmd_write_pio, HD_CFA_OK },
92a6a6f6 1760 [WIN_WRITEDMA_EXT] = { cmd_write_dma, HD_CFA_OK },
0e6498ed 1761 [CFA_WRITE_SECT_WO_ERASE] = { cmd_write_pio, CFA_OK },
adf3a2c4 1762 [WIN_MULTWRITE_EXT] = { cmd_write_multiple, HD_CFA_OK },
0e6498ed 1763 [WIN_WRITE_VERIFY] = { cmd_write_pio, HD_CFA_OK },
413860cf
KW		 1764 [WIN_VERIFY] = { cmd_verify, HD_CFA_OK | SET_DSC },
1765 [WIN_VERIFY_ONCE] = { cmd_verify, HD_CFA_OK | SET_DSC },
1766 [WIN_VERIFY_EXT] = { cmd_verify, HD_CFA_OK | SET_DSC },
61fdda37 1767 [WIN_SEEK] = { cmd_seek, HD_CFA_OK | SET_DSC },
6b1dd744 1768 [CFA_TRANSLATE_SECTOR] = { cmd_cfa_translate_sector, CFA_OK },
ee425c78 1769 [WIN_DIAGNOSE] = { cmd_exec_dev_diagnostic, ALL_OK },
b300337e
KW		 1770 [WIN_SPECIFY] = { cmd_nop, HD_CFA_OK | SET_DSC },
1771 [WIN_STANDBYNOW2] = { cmd_nop, ALL_OK },
1772 [WIN_IDLEIMMEDIATE2] = { cmd_nop, ALL_OK },
1773 [WIN_STANDBY2] = { cmd_nop, ALL_OK },
1774 [WIN_SETIDLE2] = { cmd_nop, ALL_OK },
785f6320 1775 [WIN_CHECKPOWERMODE2] = { cmd_check_power_mode, ALL_OK | SET_DSC },
b300337e 1776 [WIN_SLEEPNOW2] = { cmd_nop, ALL_OK },
ee425c78
KW		 1777 [WIN_PACKETCMD] = { cmd_packet, CD_OK },
1778 [WIN_PIDENTIFY] = { cmd_identify_packet, CD_OK },
ff352677 1779 [WIN_SMART] = { cmd_smart, HD_CFA_OK | SET_DSC },
6b1dd744
KW		 1780 [CFA_ACCESS_METADATA_STORAGE] = { cmd_cfa_access_metadata_storage, CFA_OK },
1781 [CFA_ERASE_SECTORS] = { cmd_cfa_erase_sectors, CFA_OK | SET_DSC },
adf3a2c4
KW		 1782 [WIN_MULTREAD] = { cmd_read_multiple, HD_CFA_OK },
1783 [WIN_MULTWRITE] = { cmd_write_multiple, HD_CFA_OK },
1784 [WIN_SETMULT] = { cmd_set_multiple_mode, HD_CFA_OK | SET_DSC },
92a6a6f6
KW		 1785 [WIN_READDMA] = { cmd_read_dma, HD_CFA_OK },
1786 [WIN_READDMA_ONCE] = { cmd_read_dma, HD_CFA_OK },
1787 [WIN_WRITEDMA] = { cmd_write_dma, HD_CFA_OK },
1788 [WIN_WRITEDMA_ONCE] = { cmd_write_dma, HD_CFA_OK },
adf3a2c4 1789 [CFA_WRITE_MULTI_WO_ERASE] = { cmd_write_multiple, CFA_OK },
b300337e
KW		 1790 [WIN_STANDBYNOW1] = { cmd_nop, ALL_OK },
1791 [WIN_IDLEIMMEDIATE] = { cmd_nop, ALL_OK },
1792 [WIN_STANDBY] = { cmd_nop, ALL_OK },
1793 [WIN_SETIDLE1] = { cmd_nop, ALL_OK },
785f6320 1794 [WIN_CHECKPOWERMODE1] = { cmd_check_power_mode, ALL_OK | SET_DSC },
b300337e 1795 [WIN_SLEEPNOW1] = { cmd_nop, ALL_OK },
9afce429
KW		 1796 [WIN_FLUSH_CACHE] = { cmd_flush_cache, ALL_OK },
1797 [WIN_FLUSH_CACHE_EXT] = { cmd_flush_cache, HD_CFA_OK },
1c66869a 1798 [WIN_IDENTIFY] = { cmd_identify, ALL_OK },
ee03398c 1799 [WIN_SETFEATURES] = { cmd_set_features, ALL_OK | SET_DSC },
6b1dd744
KW		 1800 [IBM_SENSE_CONDITION] = { cmd_ibm_sense_condition, CFA_OK | SET_DSC },
1801 [CFA_WEAR_LEVEL] = { cmd_cfa_erase_sectors, HD_CFA_OK | SET_DSC },
63a82e6a 1802 [WIN_READ_NATIVE_MAX] = { cmd_read_native_max, ALL_OK | SET_DSC },
844505b1
MA		 1803};
1804
1805static bool ide_cmd_permitted(IDEState *s, uint32_t cmd)
1806{
1807 return cmd < ARRAY_SIZE(ide_cmd_table)
a0436e92 1808 && (ide_cmd_table[cmd].flags & (1u << s->drive_kind));
844505b1 1809}
7cff87ff
AG		 1810
1811void ide_exec_cmd(IDEBus *bus, uint32_t val)
1812{
1813 IDEState *s;
dfe1ea8f 1814 bool complete;
7cff87ff 1815
5391d806 1816#if defined(DEBUG_IDE)
6ef2ba5e 1817 printf("ide: CMD=%02x\n", val);
5391d806 1818#endif
6ef2ba5e 1819 s = idebus_active_if(bus);
66a0a2cb 1820 /* ignore commands to non existent slave */
4be74634 1821 if (s != bus->ifs && !s->blk) {
6ef2ba5e 1822 return;
4be74634 1823 }
c2ff060f 1824
6ef2ba5e
AG		 1825 /* Only DEVICE RESET is allowed while BSY or/and DRQ are set */
1826 if ((s->status & (BUSY_STAT|DRQ_STAT)) && val != WIN_DEVICE_RESET)
1827 return;
fcdd25ab 1828
844505b1 1829 if (!ide_cmd_permitted(s, val)) {
dfe1ea8f
KW		 1830 ide_abort_command(s);
1831 ide_set_irq(s->bus);
1832 return;
844505b1
MA		 1833 }
1834
dfe1ea8f
KW		 1835 s->status = READY_STAT | BUSY_STAT;
1836 s->error = 0;
36334faf 1837 s->io_buffer_offset = 0;
a0436e92 1838
dfe1ea8f
KW		 1839 complete = ide_cmd_table[val].handler(s, val);
1840 if (complete) {
1841 s->status &= ~BUSY_STAT;
1842 assert(!!s->error == !!(s->status & ERR_STAT));
a0436e92 1843
dfe1ea8f
KW		 1844 if ((ide_cmd_table[val].flags & SET_DSC) && !s->error) {
1845 s->status |= SEEK_STAT;
a0436e92
KW		 1846 }
1847
c7e73adb 1848 ide_cmd_done(s);
6ef2ba5e 1849 ide_set_irq(s->bus);
6ef2ba5e 1850 }
5391d806
FB		 1851}
1852
356721ae 1853uint32_t ide_ioport_read(void *opaque, uint32_t addr1)
5391d806 1854{
bcbdc4d3
GH		 1855 IDEBus *bus = opaque;
1856 IDEState *s = idebus_active_if(bus);
5391d806 1857 uint32_t addr;
c2ff060f 1858 int ret, hob;
5391d806
FB		 1859
1860 addr = addr1 & 7;
c2ff060f
FB		 1861 /* FIXME: HOB readback uses bit 7, but it's always set right now */
1862 //hob = s->select & (1 << 7);
1863 hob = 0;
5391d806
FB		 1864 switch(addr) {
1865 case 0:
1866 ret = 0xff;
1867 break;
1868 case 1:
4be74634
MA		 1869 if ((!bus->ifs[0].blk && !bus->ifs[1].blk) ||
1870 (s != bus->ifs && !s->blk)) {
c45c3d00 1871 ret = 0;
4be74634 1872 } else if (!hob) {
c45c3d00 1873 ret = s->error;
4be74634 1874 } else {
c2ff060f 1875 ret = s->hob_feature;
4be74634 1876 }
5391d806
FB		 1877 break;
1878 case 2:
4be74634 1879 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
c45c3d00 1880 ret = 0;
4be74634 1881 } else if (!hob) {
c45c3d00 1882 ret = s->nsector & 0xff;
4be74634 1883 } else {
c2ff060f 1884 ret = s->hob_nsector;
4be74634 1885 }
5391d806
FB		 1886 break;
1887 case 3:
4be74634 1888 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
c45c3d00 1889 ret = 0;
4be74634 1890 } else if (!hob) {
c45c3d00 1891 ret = s->sector;
4be74634 1892 } else {
c2ff060f 1893 ret = s->hob_sector;
4be74634 1894 }
5391d806
FB		 1895 break;
1896 case 4:
4be74634 1897 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
c45c3d00 1898 ret = 0;
4be74634 1899 } else if (!hob) {
c45c3d00 1900 ret = s->lcyl;
4be74634 1901 } else {
c2ff060f 1902 ret = s->hob_lcyl;
4be74634 1903 }
5391d806
FB		 1904 break;
1905 case 5:
4be74634 1906 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
c45c3d00 1907 ret = 0;
4be74634 1908 } else if (!hob) {
c45c3d00 1909 ret = s->hcyl;
4be74634 1910 } else {
c2ff060f 1911 ret = s->hob_hcyl;
4be74634 1912 }
5391d806
FB		 1913 break;
1914 case 6:
4be74634 1915 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
c45c3d00 1916 ret = 0;
4be74634 1917 } else {
7ae98627 1918 ret = s->select;
4be74634 1919 }
5391d806
FB		 1920 break;
1921 default:
1922 case 7:
4be74634
MA		 1923 if ((!bus->ifs[0].blk && !bus->ifs[1].blk) ||
1924 (s != bus->ifs && !s->blk)) {
c45c3d00 1925 ret = 0;
4be74634 1926 } else {
c45c3d00 1927 ret = s->status;
4be74634 1928 }
9cdd03a7 1929 qemu_irq_lower(bus->irq);
5391d806
FB		 1930 break;
1931 }
1932#ifdef DEBUG_IDE
1933 printf("ide: read addr=0x%x val=%02x\n", addr1, ret);
1934#endif
1935 return ret;
1936}
1937
356721ae 1938uint32_t ide_status_read(void *opaque, uint32_t addr)
5391d806 1939{
bcbdc4d3
GH		 1940 IDEBus *bus = opaque;
1941 IDEState *s = idebus_active_if(bus);
5391d806 1942 int ret;
7ae98627 1943
4be74634
MA		 1944 if ((!bus->ifs[0].blk && !bus->ifs[1].blk) ||
1945 (s != bus->ifs && !s->blk)) {
7ae98627 1946 ret = 0;
4be74634 1947 } else {
7ae98627 1948 ret = s->status;
4be74634 1949 }
5391d806
FB		 1950#ifdef DEBUG_IDE
1951 printf("ide: read status addr=0x%x val=%02x\n", addr, ret);
1952#endif
1953 return ret;
1954}
1955
356721ae 1956void ide_cmd_write(void *opaque, uint32_t addr, uint32_t val)
5391d806 1957{
bcbdc4d3 1958 IDEBus *bus = opaque;
5391d806
FB		 1959 IDEState *s;
1960 int i;
1961
1962#ifdef DEBUG_IDE
1963 printf("ide: write control addr=0x%x val=%02x\n", addr, val);
1964#endif
1965 /* common for both drives */
9cdd03a7 1966 if (!(bus->cmd & IDE_CMD_RESET) &&
5391d806
FB		 1967 (val & IDE_CMD_RESET)) {
1968 /* reset low to high */
1969 for(i = 0;i < 2; i++) {
bcbdc4d3 1970 s = &bus->ifs[i];
5391d806
FB		 1971 s->status = BUSY_STAT | SEEK_STAT;
1972 s->error = 0x01;
1973 }
9cdd03a7 1974 } else if ((bus->cmd & IDE_CMD_RESET) &&
5391d806
FB		 1975 !(val & IDE_CMD_RESET)) {
1976 /* high to low */
1977 for(i = 0;i < 2; i++) {
bcbdc4d3 1978 s = &bus->ifs[i];
cd8722bb 1979 if (s->drive_kind == IDE_CD)
6b136f9e
FB		 1980 s->status = 0x00; /* NOTE: READY is _not_ set */
1981 else
56bf1d37 1982 s->status = READY_STAT | SEEK_STAT;
5391d806
FB		 1983 ide_set_signature(s);
1984 }
1985 }
1986
9cdd03a7 1987 bus->cmd = val;
5391d806
FB		 1988}
1989
40c4ed3f
KW		 1990/*
1991 * Returns true if the running PIO transfer is a PIO out (i.e. data is
1992 * transferred from the device to the guest), false if it's a PIO in
1993 */
1994static bool ide_is_pio_out(IDEState *s)
1995{
1996 if (s->end_transfer_func == ide_sector_write ||
1997 s->end_transfer_func == ide_atapi_cmd) {
1998 return false;
1999 } else if (s->end_transfer_func == ide_sector_read ||
2000 s->end_transfer_func == ide_transfer_stop ||
2001 s->end_transfer_func == ide_atapi_cmd_reply_end ||
2002 s->end_transfer_func == ide_dummy_transfer_stop) {
2003 return true;
2004 }
2005
2006 abort();
2007}
2008
356721ae 2009void ide_data_writew(void *opaque, uint32_t addr, uint32_t val)
5391d806 2010{
bcbdc4d3
GH		 2011 IDEBus *bus = opaque;
2012 IDEState *s = idebus_active_if(bus);
5391d806
FB		 2013 uint8_t *p;
2014
40c4ed3f
KW		 2015 /* PIO data access allowed only when DRQ bit is set. The result of a write
2016 * during PIO out is indeterminate, just ignore it. */
2017 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
fcdd25ab 2018 return;
40c4ed3f 2019 }
fcdd25ab 2020
5391d806 2021 p = s->data_ptr;
0c4ad8dc 2022 *(uint16_t *)p = le16_to_cpu(val);
5391d806
FB		 2023 p += 2;
2024 s->data_ptr = p;
2025 if (p >= s->data_end)
2026 s->end_transfer_func(s);
2027}
2028
356721ae 2029uint32_t ide_data_readw(void *opaque, uint32_t addr)
5391d806 2030{
bcbdc4d3
GH		 2031 IDEBus *bus = opaque;
2032 IDEState *s = idebus_active_if(bus);
5391d806
FB		 2033 uint8_t *p;
2034 int ret;
fcdd25ab 2035
40c4ed3f
KW		 2036 /* PIO data access allowed only when DRQ bit is set. The result of a read
2037 * during PIO in is indeterminate, return 0 and don't move forward. */
2038 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
fcdd25ab 2039 return 0;
40c4ed3f 2040 }
fcdd25ab 2041
5391d806 2042 p = s->data_ptr;
0c4ad8dc 2043 ret = cpu_to_le16(*(uint16_t *)p);
5391d806
FB		 2044 p += 2;
2045 s->data_ptr = p;
2046 if (p >= s->data_end)
2047 s->end_transfer_func(s);
2048 return ret;
2049}
2050
356721ae 2051void ide_data_writel(void *opaque, uint32_t addr, uint32_t val)
5391d806 2052{
bcbdc4d3
GH		 2053 IDEBus *bus = opaque;
2054 IDEState *s = idebus_active_if(bus);
5391d806
FB		 2055 uint8_t *p;
2056
40c4ed3f
KW		 2057 /* PIO data access allowed only when DRQ bit is set. The result of a write
2058 * during PIO out is indeterminate, just ignore it. */
2059 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
fcdd25ab 2060 return;
40c4ed3f 2061 }
fcdd25ab 2062
5391d806 2063 p = s->data_ptr;
0c4ad8dc 2064 *(uint32_t *)p = le32_to_cpu(val);
5391d806
FB		 2065 p += 4;
2066 s->data_ptr = p;
2067 if (p >= s->data_end)
2068 s->end_transfer_func(s);
2069}
2070
356721ae 2071uint32_t ide_data_readl(void *opaque, uint32_t addr)
5391d806 2072{
bcbdc4d3
GH		 2073 IDEBus *bus = opaque;
2074 IDEState *s = idebus_active_if(bus);
5391d806
FB		 2075 uint8_t *p;
2076 int ret;
3b46e624 2077
40c4ed3f
KW		 2078 /* PIO data access allowed only when DRQ bit is set. The result of a read
2079 * during PIO in is indeterminate, return 0 and don't move forward. */
2080 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
fcdd25ab 2081 return 0;
40c4ed3f 2082 }
fcdd25ab 2083
5391d806 2084 p = s->data_ptr;
0c4ad8dc 2085 ret = cpu_to_le32(*(uint32_t *)p);
5391d806
FB		 2086 p += 4;
2087 s->data_ptr = p;
2088 if (p >= s->data_end)
2089 s->end_transfer_func(s);
2090 return ret;
2091}
2092
a7dfe172
FB		 2093static void ide_dummy_transfer_stop(IDEState *s)
2094{
2095 s->data_ptr = s->io_buffer;
2096 s->data_end = s->io_buffer;
2097 s->io_buffer[0] = 0xff;
2098 s->io_buffer[1] = 0xff;
2099 s->io_buffer[2] = 0xff;
2100 s->io_buffer[3] = 0xff;
2101}
2102
4a643563 2103static void ide_reset(IDEState *s)
5391d806 2104{
4a643563
BS		 2105#ifdef DEBUG_IDE
2106 printf("ide: reset\n");
2107#endif
bef0fd59
SH		 2108
2109 if (s->pio_aiocb) {
4be74634 2110 blk_aio_cancel(s->pio_aiocb);
bef0fd59
SH		 2111 s->pio_aiocb = NULL;
2112 }
2113
cd8722bb 2114 if (s->drive_kind == IDE_CFATA)
201a51fc
AZ		 2115 s->mult_sectors = 0;
2116 else
2117 s->mult_sectors = MAX_MULT_SECTORS;
4a643563
BS		 2118 /* ide regs */
2119 s->feature = 0;
2120 s->error = 0;
2121 s->nsector = 0;
2122 s->sector = 0;
2123 s->lcyl = 0;
2124 s->hcyl = 0;
2125
2126 /* lba48 */
2127 s->hob_feature = 0;
2128 s->hob_sector = 0;
2129 s->hob_nsector = 0;
2130 s->hob_lcyl = 0;
2131 s->hob_hcyl = 0;
2132
5391d806 2133 s->select = 0xa0;
41a2b959 2134 s->status = READY_STAT | SEEK_STAT;
4a643563
BS		 2135
2136 s->lba48 = 0;
2137
2138 /* ATAPI specific */
2139 s->sense_key = 0;
2140 s->asc = 0;
2141 s->cdrom_changed = 0;
2142 s->packet_transfer_size = 0;
2143 s->elementary_transfer_size = 0;
2144 s->io_buffer_index = 0;
2145 s->cd_sector_size = 0;
2146 s->atapi_dma = 0;
a7f3d65b
PH		 2147 s->tray_locked = 0;
2148 s->tray_open = 0;
4a643563
BS		 2149 /* ATA DMA state */
2150 s->io_buffer_size = 0;
2151 s->req_nb_sectors = 0;
2152
5391d806 2153 ide_set_signature(s);
a7dfe172
FB		 2154 /* init the transfer handler so that 0xffff is returned on data
2155 accesses */
2156 s->end_transfer_func = ide_dummy_transfer_stop;
2157 ide_dummy_transfer_stop(s);
201a51fc 2158 s->media_changed = 0;
5391d806
FB		 2159}
2160
4a643563
BS		 2161void ide_bus_reset(IDEBus *bus)
2162{
2163 bus->unit = 0;
2164 bus->cmd = 0;
2165 ide_reset(&bus->ifs[0]);
2166 ide_reset(&bus->ifs[1]);
2167 ide_clear_hob(bus);
40a6238a
AG		 2168
2169 /* pending async DMA */
2170 if (bus->dma->aiocb) {
2171#ifdef DEBUG_AIO
2172 printf("aio_cancel\n");
2173#endif
4be74634 2174 blk_aio_cancel(bus->dma->aiocb);
40a6238a
AG		 2175 bus->dma->aiocb = NULL;
2176 }
2177
2178 /* reset dma provider too */
1374bec0
PB		 2179 if (bus->dma->ops->reset) {
2180 bus->dma->ops->reset(bus->dma);
2181 }
4a643563
BS		 2182}
2183
e4def80b
MA		 2184static bool ide_cd_is_tray_open(void *opaque)
2185{
2186 return ((IDEState *)opaque)->tray_open;
2187}
2188
f107639a
MA		 2189static bool ide_cd_is_medium_locked(void *opaque)
2190{
2191 return ((IDEState *)opaque)->tray_locked;
2192}
2193
01ce352e
JS		 2194static void ide_resize_cb(void *opaque)
2195{
2196 IDEState *s = opaque;
2197 uint64_t nb_sectors;
2198
2199 if (!s->identify_set) {
2200 return;
2201 }
2202
4be74634 2203 blk_get_geometry(s->blk, &nb_sectors);
01ce352e
JS		 2204 s->nb_sectors = nb_sectors;
2205
2206 /* Update the identify data buffer. */
2207 if (s->drive_kind == IDE_CFATA) {
2208 ide_cfata_identify_size(s);
2209 } else {
2210 /* IDE_CD uses a different set of callbacks entirely. */
2211 assert(s->drive_kind != IDE_CD);
2212 ide_identify_size(s);
2213 }
2214}
2215
0e49de52 2216static const BlockDevOps ide_cd_block_ops = {
145feb17 2217 .change_media_cb = ide_cd_change_cb,
2df0a3a3 2218 .eject_request_cb = ide_cd_eject_request_cb,
e4def80b 2219 .is_tray_open = ide_cd_is_tray_open,
f107639a 2220 .is_medium_locked = ide_cd_is_medium_locked,
0e49de52
MA		 2221};
2222
01ce352e
JS		 2223static const BlockDevOps ide_hd_block_ops = {
2224 .resize_cb = ide_resize_cb,
2225};
2226
4be74634 2227int ide_init_drive(IDEState *s, BlockBackend *blk, IDEDriveKind kind,
95ebda85 2228 const char *version, const char *serial, const char *model,
ba801960
MA		 2229 uint64_t wwn,
2230 uint32_t cylinders, uint32_t heads, uint32_t secs,
2231 int chs_trans)
88804180 2232{
88804180
GH		 2233 uint64_t nb_sectors;
2234
4be74634 2235 s->blk = blk;
1f56e32a
MA		 2236 s->drive_kind = kind;
2237
4be74634 2238 blk_get_geometry(blk, &nb_sectors);
870111c8
MA		 2239 s->cylinders = cylinders;
2240 s->heads = heads;
2241 s->sectors = secs;
ba801960 2242 s->chs_trans = chs_trans;
870111c8 2243 s->nb_sectors = nb_sectors;
95ebda85 2244 s->wwn = wwn;
870111c8
MA		 2245 /* The SMART values should be preserved across power cycles
2246 but they aren't. */
2247 s->smart_enabled = 1;
2248 s->smart_autosave = 1;
2249 s->smart_errors = 0;
2250 s->smart_selftest_count = 0;
1f56e32a 2251 if (kind == IDE_CD) {
4be74634
MA		 2252 blk_set_dev_ops(blk, &ide_cd_block_ops, s);
2253 blk_set_guest_block_size(blk, 2048);
7aa9c811 2254 } else {
4be74634 2255 if (!blk_is_inserted(s->blk)) {
98f28ad7
MA		 2256 error_report("Device needs media, but drive is empty");
2257 return -1;
2258 }
4be74634 2259 if (blk_is_read_only(blk)) {
7aa9c811
MA		 2260 error_report("Can't use a read-only drive");
2261 return -1;
2262 }
4be74634 2263 blk_set_dev_ops(blk, &ide_hd_block_ops, s);
88804180 2264 }
f8b6cc00 2265 if (serial) {
aa2c91bd 2266 pstrcpy(s->drive_serial_str, sizeof(s->drive_serial_str), serial);
6ced55a5 2267 } else {
88804180
GH		 2268 snprintf(s->drive_serial_str, sizeof(s->drive_serial_str),
2269 "QM%05d", s->drive_serial);
870111c8 2270 }
27e0c9a1
FB		 2271 if (model) {
2272 pstrcpy(s->drive_model_str, sizeof(s->drive_model_str), model);
2273 } else {
2274 switch (kind) {
2275 case IDE_CD:
2276 strcpy(s->drive_model_str, "QEMU DVD-ROM");
2277 break;
2278 case IDE_CFATA:
2279 strcpy(s->drive_model_str, "QEMU MICRODRIVE");
2280 break;
2281 default:
2282 strcpy(s->drive_model_str, "QEMU HARDDISK");
2283 break;
2284 }
2285 }
2286
47c06340
GH		 2287 if (version) {
2288 pstrcpy(s->version, sizeof(s->version), version);
2289 } else {
93bfef4c 2290 pstrcpy(s->version, sizeof(s->version), qemu_get_version());
47c06340 2291 }
40a6238a 2292
88804180 2293 ide_reset(s);
4be74634 2294 blk_iostatus_enable(blk);
c4d74df7 2295 return 0;
88804180
GH		 2296}
2297
57234ee4 2298static void ide_init1(IDEBus *bus, int unit)
d459da0e
MA		 2299{
2300 static int drive_serial = 1;
2301 IDEState *s = &bus->ifs[unit];
2302
2303 s->bus = bus;
2304 s->unit = unit;
2305 s->drive_serial = drive_serial++;
1b2adf28 2306 /* we need at least 2k alignment for accessing CDROMs using O_DIRECT */
50641c5c 2307 s->io_buffer_total_len = IDE_DMA_BUF_SECTORS*512 + 4;
c925400b
KW		 2308 s->io_buffer = qemu_memalign(2048, s->io_buffer_total_len);
2309 memset(s->io_buffer, 0, s->io_buffer_total_len);
2310
4be74634 2311 s->smart_selftest_data = blk_blockalign(s->blk, 512);
c925400b
KW		 2312 memset(s->smart_selftest_data, 0, 512);
2313
bc72ad67 2314 s->sector_write_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
d459da0e 2315 ide_sector_write_timer_cb, s);
57234ee4
MA		 2316}
2317
40a6238a
AG		 2318static int ide_nop_int(IDEDMA *dma, int x)
2319{
2320 return 0;
2321}
2322
9898586d
PB		 2323static void ide_nop(IDEDMA *dma)
2324{
2325}
2326
3251bdcf
JS		 2327static int32_t ide_nop_int32(IDEDMA *dma, int x)
2328{
2329 return 0;
2330}
2331
40a6238a 2332static const IDEDMAOps ide_dma_nop_ops = {
3251bdcf 2333 .prepare_buf = ide_nop_int32,
9898586d 2334 .restart_dma = ide_nop,
40a6238a 2335 .rw_buf = ide_nop_int,
40a6238a
AG		 2336};
2337
9898586d
PB		 2338static void ide_restart_dma(IDEState *s, enum ide_dma_cmd dma_cmd)
2339{
a96cb236 2340 s->unit = s->bus->retry_unit;
dc5d0af4
PB		 2341 ide_set_sector(s, s->bus->retry_sector_num);
2342 s->nsector = s->bus->retry_nsector;
9898586d
PB		 2343 s->bus->dma->ops->restart_dma(s->bus->dma);
2344 s->io_buffer_index = 0;
2345 s->io_buffer_size = 0;
2346 s->dma_cmd = dma_cmd;
2347 ide_start_dma(s, ide_dma_cb);
2348}
2349
2350static void ide_restart_bh(void *opaque)
2351{
2352 IDEBus *bus = opaque;
2353 IDEState *s;
2354 bool is_read;
2355 int error_status;
2356
2357 qemu_bh_delete(bus->bh);
2358 bus->bh = NULL;
2359
2360 error_status = bus->error_status;
2361 if (bus->error_status == 0) {
2362 return;
2363 }
2364
2365 s = idebus_active_if(bus);
2366 is_read = (bus->error_status & IDE_RETRY_READ) != 0;
2367
2368 /* The error status must be cleared before resubmitting the request: The
2369 * request may fail again, and this case can only be distinguished if the
2370 * called function can set a new error status. */
2371 bus->error_status = 0;
2372
2373 if (error_status & IDE_RETRY_DMA) {
2374 if (error_status & IDE_RETRY_TRIM) {
2375 ide_restart_dma(s, IDE_DMA_TRIM);
2376 } else {
2377 ide_restart_dma(s, is_read ? IDE_DMA_READ : IDE_DMA_WRITE);
2378 }
2379 } else if (error_status & IDE_RETRY_PIO) {
2380 if (is_read) {
2381 ide_sector_read(s);
2382 } else {
2383 ide_sector_write(s);
2384 }
2385 } else if (error_status & IDE_RETRY_FLUSH) {
2386 ide_flush_cache(s);
2387 } else {
2388 /*
2389 * We've not got any bits to tell us about ATAPI - but
2390 * we do have the end_transfer_func that tells us what
2391 * we're trying to do.
2392 */
2393 if (s->end_transfer_func == ide_atapi_cmd) {
2394 ide_atapi_dma_restart(s);
2395 }
2396 }
2397}
2398
2399static void ide_restart_cb(void *opaque, int running, RunState state)
2400{
2401 IDEBus *bus = opaque;
2402
2403 if (!running)
2404 return;
2405
2406 if (!bus->bh) {
2407 bus->bh = qemu_bh_new(ide_restart_bh, bus);
2408 qemu_bh_schedule(bus->bh);
2409 }
2410}
2411
f878c916
PB		 2412void ide_register_restart_cb(IDEBus *bus)
2413{
9898586d
PB		 2414 if (bus->dma->ops->restart_dma) {
2415 qemu_add_vm_change_state_handler(ide_restart_cb, bus);
2416 }
f878c916
PB		 2417}
2418
40a6238a
AG		 2419static IDEDMA ide_dma_nop = {
2420 .ops = &ide_dma_nop_ops,
2421 .aiocb = NULL,
2422};
2423
57234ee4
MA		 2424void ide_init2(IDEBus *bus, qemu_irq irq)
2425{
2426 int i;
2427
2428 for(i = 0; i < 2; i++) {
2429 ide_init1(bus, i);
2430 ide_reset(&bus->ifs[i]);
870111c8 2431 }
57234ee4 2432 bus->irq = irq;
40a6238a 2433 bus->dma = &ide_dma_nop;
d459da0e
MA		 2434}
2435
4a91d3b3
RH		 2436static const MemoryRegionPortio ide_portio_list[] = {
2437 { 0, 8, 1, .read = ide_ioport_read, .write = ide_ioport_write },
2438 { 0, 2, 2, .read = ide_data_readw, .write = ide_data_writew },
2439 { 0, 4, 4, .read = ide_data_readl, .write = ide_data_writel },
2440 PORTIO_END_OF_LIST(),
2441};
2442
2443static const MemoryRegionPortio ide_portio2_list[] = {
2444 { 0, 1, 1, .read = ide_status_read, .write = ide_cmd_write },
2445 PORTIO_END_OF_LIST(),
2446};
2447
2448void ide_init_ioport(IDEBus *bus, ISADevice *dev, int iobase, int iobase2)
69b91039 2449{
4a91d3b3
RH		 2450 /* ??? Assume only ISA and PCI configurations, and that the PCI-ISA
2451 bridge has been setup properly to always register with ISA. */
2452 isa_register_portio_list(dev, iobase, ide_portio_list, bus, "ide");
2453
caed8802 2454 if (iobase2) {
4a91d3b3 2455 isa_register_portio_list(dev, iobase2, ide_portio2_list, bus, "ide");
5391d806 2456 }
5391d806 2457}
69b91039 2458
37159f13 2459static bool is_identify_set(void *opaque, int version_id)
aa941b94 2460{
37159f13
JQ		 2461 IDEState *s = opaque;
2462
2463 return s->identify_set != 0;
2464}
2465
50641c5c
JQ		 2466static EndTransferFunc* transfer_end_table[] = {
2467 ide_sector_read,
2468 ide_sector_write,
2469 ide_transfer_stop,
2470 ide_atapi_cmd_reply_end,
2471 ide_atapi_cmd,
2472 ide_dummy_transfer_stop,
2473};
2474
2475static int transfer_end_table_idx(EndTransferFunc *fn)
2476{
2477 int i;
2478
2479 for (i = 0; i < ARRAY_SIZE(transfer_end_table); i++)
2480 if (transfer_end_table[i] == fn)
2481 return i;
2482
2483 return -1;
2484}
2485
37159f13 2486static int ide_drive_post_load(void *opaque, int version_id)
aa941b94 2487{
37159f13
JQ		 2488 IDEState *s = opaque;
2489
6b896ab2 2490 if (s->blk && s->identify_set) {
4be74634 2491 blk_set_enable_write_cache(s->blk, !!(s->identify_data[85] & (1 << 5)));
7cdd481c 2492 }
37159f13 2493 return 0;
aa941b94
AZ		 2494}
2495
50641c5c
JQ		 2496static int ide_drive_pio_post_load(void *opaque, int version_id)
2497{
2498 IDEState *s = opaque;
2499
fb60105d 2500 if (s->end_transfer_fn_idx >= ARRAY_SIZE(transfer_end_table)) {
50641c5c
JQ		 2501 return -EINVAL;
2502 }
2503 s->end_transfer_func = transfer_end_table[s->end_transfer_fn_idx];
2504 s->data_ptr = s->io_buffer + s->cur_io_buffer_offset;
2505 s->data_end = s->data_ptr + s->cur_io_buffer_len;
819fa276 2506 s->atapi_dma = s->feature & 1; /* as per cmd_packet */
50641c5c
JQ		 2507
2508 return 0;
2509}
2510
2511static void ide_drive_pio_pre_save(void *opaque)
2512{
2513 IDEState *s = opaque;
2514 int idx;
2515
2516 s->cur_io_buffer_offset = s->data_ptr - s->io_buffer;
2517 s->cur_io_buffer_len = s->data_end - s->data_ptr;
2518
2519 idx = transfer_end_table_idx(s->end_transfer_func);
2520 if (idx == -1) {
2521 fprintf(stderr, "%s: invalid end_transfer_func for DRQ_STAT\n",
2522 __func__);
2523 s->end_transfer_fn_idx = 2;
2524 } else {
2525 s->end_transfer_fn_idx = idx;
2526 }
2527}
2528
2529static bool ide_drive_pio_state_needed(void *opaque)
2530{
2531 IDEState *s = opaque;
2532
fdc650d7 2533 return ((s->status & DRQ_STAT) != 0)
fd648f10 2534 || (s->bus->error_status & IDE_RETRY_PIO);
50641c5c
JQ		 2535}
2536
db118fe7
MA		 2537static bool ide_tray_state_needed(void *opaque)
2538{
2539 IDEState *s = opaque;
2540
2541 return s->tray_open || s->tray_locked;
2542}
2543
996faf1a
AS		 2544static bool ide_atapi_gesn_needed(void *opaque)
2545{
2546 IDEState *s = opaque;
2547
2548 return s->events.new_media || s->events.eject_request;
2549}
2550
def93791
KW		 2551static bool ide_error_needed(void *opaque)
2552{
2553 IDEBus *bus = opaque;
2554
2555 return (bus->error_status != 0);
2556}
2557
996faf1a 2558/* Fields for GET_EVENT_STATUS_NOTIFICATION ATAPI command */
656fbeff 2559static const VMStateDescription vmstate_ide_atapi_gesn_state = {
996faf1a
AS		 2560 .name ="ide_drive/atapi/gesn_state",
2561 .version_id = 1,
2562 .minimum_version_id = 1,
35d08458 2563 .fields = (VMStateField[]) {
996faf1a
AS		 2564 VMSTATE_BOOL(events.new_media, IDEState),
2565 VMSTATE_BOOL(events.eject_request, IDEState),
0754f9ec 2566 VMSTATE_END_OF_LIST()
996faf1a
AS		 2567 }
2568};
2569
db118fe7
MA		 2570static const VMStateDescription vmstate_ide_tray_state = {
2571 .name = "ide_drive/tray_state",
2572 .version_id = 1,
2573 .minimum_version_id = 1,
db118fe7
MA		 2574 .fields = (VMStateField[]) {
2575 VMSTATE_BOOL(tray_open, IDEState),
2576 VMSTATE_BOOL(tray_locked, IDEState),
2577 VMSTATE_END_OF_LIST()
2578 }
2579};
2580
656fbeff 2581static const VMStateDescription vmstate_ide_drive_pio_state = {
50641c5c
JQ		 2582 .name = "ide_drive/pio_state",
2583 .version_id = 1,
2584 .minimum_version_id = 1,
50641c5c
JQ		 2585 .pre_save = ide_drive_pio_pre_save,
2586 .post_load = ide_drive_pio_post_load,
35d08458 2587 .fields = (VMStateField[]) {
50641c5c
JQ		 2588 VMSTATE_INT32(req_nb_sectors, IDEState),
2589 VMSTATE_VARRAY_INT32(io_buffer, IDEState, io_buffer_total_len, 1,
2590 vmstate_info_uint8, uint8_t),
2591 VMSTATE_INT32(cur_io_buffer_offset, IDEState),
2592 VMSTATE_INT32(cur_io_buffer_len, IDEState),
2593 VMSTATE_UINT8(end_transfer_fn_idx, IDEState),
2594 VMSTATE_INT32(elementary_transfer_size, IDEState),
2595 VMSTATE_INT32(packet_transfer_size, IDEState),
2596 VMSTATE_END_OF_LIST()
2597 }
2598};
2599
37159f13
JQ		 2600const VMStateDescription vmstate_ide_drive = {
2601 .name = "ide_drive",
3abb6260 2602 .version_id = 3,
37159f13 2603 .minimum_version_id = 0,
37159f13 2604 .post_load = ide_drive_post_load,
35d08458 2605 .fields = (VMStateField[]) {
37159f13
JQ		 2606 VMSTATE_INT32(mult_sectors, IDEState),
2607 VMSTATE_INT32(identify_set, IDEState),
2608 VMSTATE_BUFFER_TEST(identify_data, IDEState, is_identify_set),
2609 VMSTATE_UINT8(feature, IDEState),
2610 VMSTATE_UINT8(error, IDEState),
2611 VMSTATE_UINT32(nsector, IDEState),
2612 VMSTATE_UINT8(sector, IDEState),
2613 VMSTATE_UINT8(lcyl, IDEState),
2614 VMSTATE_UINT8(hcyl, IDEState),
2615 VMSTATE_UINT8(hob_feature, IDEState),
2616 VMSTATE_UINT8(hob_sector, IDEState),
2617 VMSTATE_UINT8(hob_nsector, IDEState),
2618 VMSTATE_UINT8(hob_lcyl, IDEState),
2619 VMSTATE_UINT8(hob_hcyl, IDEState),
2620 VMSTATE_UINT8(select, IDEState),
2621 VMSTATE_UINT8(status, IDEState),
2622 VMSTATE_UINT8(lba48, IDEState),
2623 VMSTATE_UINT8(sense_key, IDEState),
2624 VMSTATE_UINT8(asc, IDEState),
2625 VMSTATE_UINT8_V(cdrom_changed, IDEState, 3),
37159f13 2626 VMSTATE_END_OF_LIST()
50641c5c
JQ		 2627 },
2628 .subsections = (VMStateSubsection []) {
2629 {
2630 .vmsd = &vmstate_ide_drive_pio_state,
2631 .needed = ide_drive_pio_state_needed,
db118fe7
MA		 2632 }, {
2633 .vmsd = &vmstate_ide_tray_state,
2634 .needed = ide_tray_state_needed,
996faf1a
AS		 2635 }, {
2636 .vmsd = &vmstate_ide_atapi_gesn_state,
2637 .needed = ide_atapi_gesn_needed,
50641c5c
JQ		 2638 }, {
2639 /* empty */
2640 }
37159f13
JQ		 2641 }
2642};
2643
656fbeff 2644static const VMStateDescription vmstate_ide_error_status = {
def93791 2645 .name ="ide_bus/error",
d12b9ff2 2646 .version_id = 2,
def93791 2647 .minimum_version_id = 1,
35d08458 2648 .fields = (VMStateField[]) {
def93791 2649 VMSTATE_INT32(error_status, IDEBus),
d12b9ff2
PB		 2650 VMSTATE_INT64_V(retry_sector_num, IDEBus, 2),
2651 VMSTATE_UINT32_V(retry_nsector, IDEBus, 2),
2652 VMSTATE_UINT8_V(retry_unit, IDEBus, 2),
def93791
KW		 2653 VMSTATE_END_OF_LIST()
2654 }
2655};
2656
6521dc62
JQ		 2657const VMStateDescription vmstate_ide_bus = {
2658 .name = "ide_bus",
2659 .version_id = 1,
2660 .minimum_version_id = 1,
35d08458 2661 .fields = (VMStateField[]) {
6521dc62
JQ		 2662 VMSTATE_UINT8(cmd, IDEBus),
2663 VMSTATE_UINT8(unit, IDEBus),
2664 VMSTATE_END_OF_LIST()
def93791
KW		 2665 },
2666 .subsections = (VMStateSubsection []) {
2667 {
2668 .vmsd = &vmstate_ide_error_status,
2669 .needed = ide_error_needed,
2670 }, {
2671 /* empty */
2672 }
6521dc62
JQ		 2673 }
2674};
75717903 2675
d8f94e1b 2676void ide_drive_get(DriveInfo **hd, int n)
75717903
IY		 2677{
2678 int i;
d8f94e1b
JS		 2679 int highest_bus = drive_get_max_bus(IF_IDE) + 1;
2680 int max_devs = drive_get_max_devs(IF_IDE);
2681 int n_buses = max_devs ? (n / max_devs) : n;
75717903 2682
d8f94e1b
JS		 2683 /*
2684 * Note: The number of actual buses available is not known.
2685 * We compute this based on the size of the DriveInfo* array, n.
2686 * If it is less than max_devs * <num_real_buses>,
2687 * We will stop looking for drives prematurely instead of overfilling
2688 * the array.
2689 */
2690
2691 if (highest_bus > n_buses) {
2692 error_report("Too many IDE buses defined (%d > %d)",
2693 highest_bus, n_buses);
75717903
IY		 2694 exit(1);
2695 }
2696
d8f94e1b
JS		 2697 for (i = 0; i < n; i++) {
2698 hd[i] = drive_get_by_index(IF_IDE, i);
75717903
IY		 2699 }
2700}
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