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hw/block/nvme: Align I/O BAR to 4 KiB
[qemu.git] / hw / ide / core.c
CommitLineData
5391d806 1/*
38cdea7c 2 * QEMU IDE disk and CD/DVD-ROM Emulator
5fafdf24 3 *
5391d806 4 * Copyright (c) 2003 Fabrice Bellard
201a51fc 5 * Copyright (c) 2006 Openedhand Ltd.
5fafdf24 6 *
5391d806
FB		 7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
e688df6b 25
53239262 26#include "qemu/osdep.h"
a9c94277 27#include "hw/isa/isa.h"
d6454270 28#include "migration/vmstate.h"
1de7afc9 29#include "qemu/error-report.h"
db725815 30#include "qemu/main-loop.h"
1de7afc9 31#include "qemu/timer.h"
9c17d615 32#include "sysemu/sysemu.h"
78631611 33#include "sysemu/blockdev.h"
9c17d615 34#include "sysemu/dma.h"
0d09e41a 35#include "hw/block/block.h"
4be74634 36#include "sysemu/block-backend.h"
e688df6b 37#include "qapi/error.h"
f348b6d1 38#include "qemu/cutils.h"
b255df7e 39#include "sysemu/replay.h"
54d31236 40#include "sysemu/runstate.h"
a9c94277 41#include "hw/ide/internal.h"
3eee2611 42#include "trace.h"
e8b54394 43
b93af93d
BW		 44/* These values were based on a Seagate ST3500418AS but have been modified
45 to make more sense in QEMU */
46static const int smart_attributes[][12] = {
47 /* id, flags, hflags, val, wrst, raw (6 bytes), threshold */
48 /* raw read error rate*/
49 { 0x01, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06},
50 /* spin up */
51 { 0x03, 0x03, 0x00, 0x64, 0x64, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
52 /* start stop count */
53 { 0x04, 0x02, 0x00, 0x64, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14},
54 /* remapped sectors */
55 { 0x05, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x24},
56 /* power on hours */
57 { 0x09, 0x03, 0x00, 0x64, 0x64, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
58 /* power cycle count */
59 { 0x0c, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
60 /* airflow-temperature-celsius */
61 { 190, 0x03, 0x00, 0x45, 0x45, 0x1f, 0x00, 0x1f, 0x1f, 0x00, 0x00, 0x32},
e8b54394
BW		 62};
63
0e168d35
JS		 64const char *IDE_DMA_CMD_lookup[IDE_DMA__COUNT] = {
65 [IDE_DMA_READ] = "DMA READ",
66 [IDE_DMA_WRITE] = "DMA WRITE",
67 [IDE_DMA_TRIM] = "DMA TRIM",
68 [IDE_DMA_ATAPI] = "DMA ATAPI"
69};
70
71static const char *IDE_DMA_CMD_str(enum ide_dma_cmd enval)
72{
159a9df0 73 if ((unsigned)enval < IDE_DMA__COUNT) {
0e168d35
JS		 74 return IDE_DMA_CMD_lookup[enval];
75 }
76 return "DMA UNKNOWN CMD";
77}
78
40c4ed3f 79static void ide_dummy_transfer_stop(IDEState *s);
98087450 80
5391d806
FB		 81static void padstr(char *str, const char *src, int len)
82{
83 int i, v;
84 for(i = 0; i < len; i++) {
85 if (*src)
86 v = *src++;
87 else
88 v = ' ';
69b34976 89 str[i^1] = v;
5391d806
FB		 90 }
91}
92
67b915a5
FB		 93static void put_le16(uint16_t *p, unsigned int v)
94{
0c4ad8dc 95 *p = cpu_to_le16(v);
67b915a5
FB		 96}
97
01ce352e
JS		 98static void ide_identify_size(IDEState *s)
99{
100 uint16_t *p = (uint16_t *)s->identify_data;
101 put_le16(p + 60, s->nb_sectors);
102 put_le16(p + 61, s->nb_sectors >> 16);
103 put_le16(p + 100, s->nb_sectors);
104 put_le16(p + 101, s->nb_sectors >> 16);
105 put_le16(p + 102, s->nb_sectors >> 32);
106 put_le16(p + 103, s->nb_sectors >> 48);
107}
108
5391d806
FB		 109static void ide_identify(IDEState *s)
110{
111 uint16_t *p;
112 unsigned int oldsize;
d353fb72 113 IDEDevice *dev = s->unit ? s->bus->slave : s->bus->master;
5391d806 114
4bf6637d 115 p = (uint16_t *)s->identify_data;
94458802 116 if (s->identify_set) {
4bf6637d 117 goto fill_buffer;
94458802 118 }
4bf6637d 119 memset(p, 0, sizeof(s->identify_data));
94458802 120
67b915a5 121 put_le16(p + 0, 0x0040);
5fafdf24 122 put_le16(p + 1, s->cylinders);
67b915a5
FB		 123 put_le16(p + 3, s->heads);
124 put_le16(p + 4, 512 * s->sectors); /* XXX: retired, remove ? */
125 put_le16(p + 5, 512); /* XXX: retired, remove ? */
5fafdf24 126 put_le16(p + 6, s->sectors);
fa879c64 127 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
67b915a5
FB		 128 put_le16(p + 20, 3); /* XXX: retired, remove ? */
129 put_le16(p + 21, 512); /* cache size in sectors */
130 put_le16(p + 22, 4); /* ecc bytes */
47c06340 131 padstr((char *)(p + 23), s->version, 8); /* firmware version */
27e0c9a1 132 padstr((char *)(p + 27), s->drive_model_str, 40); /* model */
3b46e624 133#if MAX_MULT_SECTORS > 1
67b915a5 134 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
5391d806 135#endif
67b915a5 136 put_le16(p + 48, 1); /* dword I/O */
94458802 137 put_le16(p + 49, (1 << 11) | (1 << 9) | (1 << 8)); /* DMA and LBA supported */
67b915a5
FB		 138 put_le16(p + 51, 0x200); /* PIO transfer cycle */
139 put_le16(p + 52, 0x200); /* DMA transfer cycle */
94458802 140 put_le16(p + 53, 1 | (1 << 1) | (1 << 2)); /* words 54-58,64-70,88 are valid */
67b915a5
FB		 141 put_le16(p + 54, s->cylinders);
142 put_le16(p + 55, s->heads);
143 put_le16(p + 56, s->sectors);
5391d806 144 oldsize = s->cylinders * s->heads * s->sectors;
67b915a5
FB		 145 put_le16(p + 57, oldsize);
146 put_le16(p + 58, oldsize >> 16);
5391d806 147 if (s->mult_sectors)
67b915a5 148 put_le16(p + 59, 0x100 | s->mult_sectors);
01ce352e
JS		 149 /* *(p + 60) := nb_sectors -- see ide_identify_size */
150 /* *(p + 61) := nb_sectors >> 16 -- see ide_identify_size */
d1b5c20d 151 put_le16(p + 62, 0x07); /* single word dma0-2 supported */
94458802 152 put_le16(p + 63, 0x07); /* mdma0-2 supported */
79d1d331 153 put_le16(p + 64, 0x03); /* pio3-4 supported */
94458802
FB		 154 put_le16(p + 65, 120);
155 put_le16(p + 66, 120);
156 put_le16(p + 67, 120);
157 put_le16(p + 68, 120);
d353fb72
CH		 158 if (dev && dev->conf.discard_granularity) {
159 put_le16(p + 69, (1 << 14)); /* determinate TRIM behavior */
160 }
ccf0fd8b
RE		 161
162 if (s->ncq_queues) {
163 put_le16(p + 75, s->ncq_queues - 1);
164 /* NCQ supported */
165 put_le16(p + 76, (1 << 8));
166 }
167
94458802
FB		 168 put_le16(p + 80, 0xf0); /* ata3 -> ata6 supported */
169 put_le16(p + 81, 0x16); /* conforms to ata5 */
a58b8d54
CH		 170 /* 14=NOP supported, 5=WCACHE supported, 0=SMART supported */
171 put_le16(p + 82, (1 << 14) | (1 << 5) | 1);
c2ff060f
FB		 172 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
173 put_le16(p + 83, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10));
95ebda85
FB		 174 /* 14=set to 1, 8=has WWN, 1=SMART self test, 0=SMART error logging */
175 if (s->wwn) {
176 put_le16(p + 84, (1 << 14) | (1 << 8) | 0);
177 } else {
178 put_le16(p + 84, (1 << 14) | 0);
179 }
e900a7b7 180 /* 14 = NOP supported, 5=WCACHE enabled, 0=SMART feature set enabled */
4be74634
MA		 181 if (blk_enable_write_cache(s->blk)) {
182 put_le16(p + 85, (1 << 14) | (1 << 5) | 1);
183 } else {
184 put_le16(p + 85, (1 << 14) | 1);
185 }
c2ff060f 186 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
2844bdd9 187 put_le16(p + 86, (1 << 13) | (1 <<12) | (1 << 10));
95ebda85
FB		 188 /* 14=set to 1, 8=has WWN, 1=SMART self test, 0=SMART error logging */
189 if (s->wwn) {
190 put_le16(p + 87, (1 << 14) | (1 << 8) | 0);
191 } else {
192 put_le16(p + 87, (1 << 14) | 0);
193 }
94458802
FB		 194 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
195 put_le16(p + 93, 1 | (1 << 14) | 0x2000);
01ce352e
JS		 196 /* *(p + 100) := nb_sectors -- see ide_identify_size */
197 /* *(p + 101) := nb_sectors >> 16 -- see ide_identify_size */
198 /* *(p + 102) := nb_sectors >> 32 -- see ide_identify_size */
199 /* *(p + 103) := nb_sectors >> 48 -- see ide_identify_size */
d353fb72 200
57dac7ef
MA		 201 if (dev && dev->conf.physical_block_size)
202 put_le16(p + 106, 0x6000 | get_physical_block_exp(&dev->conf));
95ebda85
FB		 203 if (s->wwn) {
204 /* LE 16-bit words 111-108 contain 64-bit World Wide Name */
205 put_le16(p + 108, s->wwn >> 48);
206 put_le16(p + 109, s->wwn >> 32);
207 put_le16(p + 110, s->wwn >> 16);
208 put_le16(p + 111, s->wwn);
209 }
d353fb72
CH		 210 if (dev && dev->conf.discard_granularity) {
211 put_le16(p + 169, 1); /* TRIM support */
212 }
96f43c2b
DB		 213 if (dev) {
214 put_le16(p + 217, dev->rotation_rate); /* Nominal media rotation rate */
215 }
94458802 216
01ce352e 217 ide_identify_size(s);
94458802 218 s->identify_set = 1;
4bf6637d
JS		 219
220fill_buffer:
221 memcpy(s->io_buffer, p, sizeof(s->identify_data));
5391d806
FB		 222}
223
224static void ide_atapi_identify(IDEState *s)
225{
226 uint16_t *p;
227
4bf6637d 228 p = (uint16_t *)s->identify_data;
94458802 229 if (s->identify_set) {
4bf6637d 230 goto fill_buffer;
94458802 231 }
4bf6637d 232 memset(p, 0, sizeof(s->identify_data));
94458802 233
5391d806 234 /* Removable CDROM, 50us response, 12 byte packets */
67b915a5 235 put_le16(p + 0, (2 << 14) | (5 << 8) | (1 << 7) | (2 << 5) | (0 << 0));
fa879c64 236 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
67b915a5
FB		 237 put_le16(p + 20, 3); /* buffer type */
238 put_le16(p + 21, 512); /* cache size in sectors */
239 put_le16(p + 22, 4); /* ecc bytes */
47c06340 240 padstr((char *)(p + 23), s->version, 8); /* firmware version */
27e0c9a1 241 padstr((char *)(p + 27), s->drive_model_str, 40); /* model */
67b915a5 242 put_le16(p + 48, 1); /* dword I/O (XXX: should not be set on CDROM) */
8ccad811
FB		 243#ifdef USE_DMA_CDROM
244 put_le16(p + 49, 1 << 9 | 1 << 8); /* DMA and LBA supported */
245 put_le16(p + 53, 7); /* words 64-70, 54-58, 88 valid */
d1b5c20d 246 put_le16(p + 62, 7); /* single word dma0-2 supported */
8ccad811 247 put_le16(p + 63, 7); /* mdma0-2 supported */
8ccad811 248#else
67b915a5
FB		 249 put_le16(p + 49, 1 << 9); /* LBA supported, no DMA */
250 put_le16(p + 53, 3); /* words 64-70, 54-58 valid */
251 put_le16(p + 63, 0x103); /* DMA modes XXX: may be incorrect */
8ccad811 252#endif
79d1d331 253 put_le16(p + 64, 3); /* pio3-4 supported */
67b915a5
FB		 254 put_le16(p + 65, 0xb4); /* minimum DMA multiword tx cycle time */
255 put_le16(p + 66, 0xb4); /* recommended DMA multiword tx cycle time */
256 put_le16(p + 67, 0x12c); /* minimum PIO cycle time without flow control */
257 put_le16(p + 68, 0xb4); /* minimum PIO cycle time with IORDY flow control */
94458802 258
67b915a5
FB		 259 put_le16(p + 71, 30); /* in ns */
260 put_le16(p + 72, 30); /* in ns */
5391d806 261
1bdaa28d
AG		 262 if (s->ncq_queues) {
263 put_le16(p + 75, s->ncq_queues - 1);
264 /* NCQ supported */
265 put_le16(p + 76, (1 << 8));
266 }
267
67b915a5 268 put_le16(p + 80, 0x1e); /* support up to ATA/ATAPI-4 */
c5fe97e3
JS		 269 if (s->wwn) {
270 put_le16(p + 84, (1 << 8)); /* supports WWN for words 108-111 */
271 put_le16(p + 87, (1 << 8)); /* WWN enabled */
272 }
273
8ccad811
FB		 274#ifdef USE_DMA_CDROM
275 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
276#endif
c5fe97e3
JS		 277
278 if (s->wwn) {
279 /* LE 16-bit words 111-108 contain 64-bit World Wide Name */
280 put_le16(p + 108, s->wwn >> 48);
281 put_le16(p + 109, s->wwn >> 32);
282 put_le16(p + 110, s->wwn >> 16);
283 put_le16(p + 111, s->wwn);
284 }
285
94458802 286 s->identify_set = 1;
4bf6637d
JS		 287
288fill_buffer:
289 memcpy(s->io_buffer, p, sizeof(s->identify_data));
5391d806
FB		 290}
291
01ce352e
JS		 292static void ide_cfata_identify_size(IDEState *s)
293{
294 uint16_t *p = (uint16_t *)s->identify_data;
295 put_le16(p + 7, s->nb_sectors >> 16); /* Sectors per card */
296 put_le16(p + 8, s->nb_sectors); /* Sectors per card */
297 put_le16(p + 60, s->nb_sectors); /* Total LBA sectors */
298 put_le16(p + 61, s->nb_sectors >> 16); /* Total LBA sectors */
299}
300
201a51fc
AZ		 301static void ide_cfata_identify(IDEState *s)
302{
303 uint16_t *p;
304 uint32_t cur_sec;
201a51fc 305
4bf6637d
JS		 306 p = (uint16_t *)s->identify_data;
307 if (s->identify_set) {
201a51fc 308 goto fill_buffer;
4bf6637d 309 }
201a51fc
AZ		 310 memset(p, 0, sizeof(s->identify_data));
311
312 cur_sec = s->cylinders * s->heads * s->sectors;
313
314 put_le16(p + 0, 0x848a); /* CF Storage Card signature */
315 put_le16(p + 1, s->cylinders); /* Default cylinders */
316 put_le16(p + 3, s->heads); /* Default heads */
317 put_le16(p + 6, s->sectors); /* Default sectors per track */
01ce352e
JS		 318 /* *(p + 7) := nb_sectors >> 16 -- see ide_cfata_identify_size */
319 /* *(p + 8) := nb_sectors -- see ide_cfata_identify_size */
fa879c64 320 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
201a51fc 321 put_le16(p + 22, 0x0004); /* ECC bytes */
47c06340 322 padstr((char *) (p + 23), s->version, 8); /* Firmware Revision */
27e0c9a1 323 padstr((char *) (p + 27), s->drive_model_str, 40);/* Model number */
201a51fc
AZ		 324#if MAX_MULT_SECTORS > 1
325 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
326#else
327 put_le16(p + 47, 0x0000);
328#endif
329 put_le16(p + 49, 0x0f00); /* Capabilities */
330 put_le16(p + 51, 0x0002); /* PIO cycle timing mode */
331 put_le16(p + 52, 0x0001); /* DMA cycle timing mode */
332 put_le16(p + 53, 0x0003); /* Translation params valid */
333 put_le16(p + 54, s->cylinders); /* Current cylinders */
334 put_le16(p + 55, s->heads); /* Current heads */
335 put_le16(p + 56, s->sectors); /* Current sectors */
336 put_le16(p + 57, cur_sec); /* Current capacity */
337 put_le16(p + 58, cur_sec >> 16); /* Current capacity */
338 if (s->mult_sectors) /* Multiple sector setting */
339 put_le16(p + 59, 0x100 | s->mult_sectors);
01ce352e
JS		 340 /* *(p + 60) := nb_sectors -- see ide_cfata_identify_size */
341 /* *(p + 61) := nb_sectors >> 16 -- see ide_cfata_identify_size */
201a51fc
AZ		 342 put_le16(p + 63, 0x0203); /* Multiword DMA capability */
343 put_le16(p + 64, 0x0001); /* Flow Control PIO support */
344 put_le16(p + 65, 0x0096); /* Min. Multiword DMA cycle */
345 put_le16(p + 66, 0x0096); /* Rec. Multiword DMA cycle */
346 put_le16(p + 68, 0x00b4); /* Min. PIO cycle time */
347 put_le16(p + 82, 0x400c); /* Command Set supported */
348 put_le16(p + 83, 0x7068); /* Command Set supported */
349 put_le16(p + 84, 0x4000); /* Features supported */
350 put_le16(p + 85, 0x000c); /* Command Set enabled */
351 put_le16(p + 86, 0x7044); /* Command Set enabled */
352 put_le16(p + 87, 0x4000); /* Features enabled */
353 put_le16(p + 91, 0x4060); /* Current APM level */
354 put_le16(p + 129, 0x0002); /* Current features option */
355 put_le16(p + 130, 0x0005); /* Reassigned sectors */
356 put_le16(p + 131, 0x0001); /* Initial power mode */
357 put_le16(p + 132, 0x0000); /* User signature */
358 put_le16(p + 160, 0x8100); /* Power requirement */
359 put_le16(p + 161, 0x8001); /* CF command set */
360
01ce352e 361 ide_cfata_identify_size(s);
201a51fc
AZ		 362 s->identify_set = 1;
363
364fill_buffer:
365 memcpy(s->io_buffer, p, sizeof(s->identify_data));
366}
367
5391d806
FB		 368static void ide_set_signature(IDEState *s)
369{
370 s->select &= 0xf0; /* clear head */
371 /* put signature */
372 s->nsector = 1;
373 s->sector = 1;
cd8722bb 374 if (s->drive_kind == IDE_CD) {
5391d806
FB		 375 s->lcyl = 0x14;
376 s->hcyl = 0xeb;
4be74634 377 } else if (s->blk) {
5391d806
FB		 378 s->lcyl = 0;
379 s->hcyl = 0;
380 } else {
381 s->lcyl = 0xff;
382 s->hcyl = 0xff;
383 }
384}
385
d8b070fe
AN		 386static bool ide_sect_range_ok(IDEState *s,
387 uint64_t sector, uint64_t nb_sectors)
388{
389 uint64_t total_sectors;
390
391 blk_get_geometry(s->blk, &total_sectors);
392 if (sector > total_sectors || nb_sectors > total_sectors - sector) {
393 return false;
394 }
395 return true;
396}
397
d353fb72 398typedef struct TrimAIOCB {
7c84b1b8 399 BlockAIOCB common;
ef0e64a9 400 IDEState *s;
d353fb72
CH		 401 QEMUBH *bh;
402 int ret;
501378c3 403 QEMUIOVector *qiov;
7c84b1b8 404 BlockAIOCB *aiocb;
501378c3 405 int i, j;
d353fb72
CH		 406} TrimAIOCB;
407
7c84b1b8 408static void trim_aio_cancel(BlockAIOCB *acb)
d353fb72
CH		 409{
410 TrimAIOCB *iocb = container_of(acb, TrimAIOCB, common);
411
e551c999 412 /* Exit the loop so ide_issue_trim_cb will not continue */
501378c3
PB		 413 iocb->j = iocb->qiov->niov - 1;
414 iocb->i = (iocb->qiov->iov[iocb->j].iov_len / 8) - 1;
415
e551c999 416 iocb->ret = -ECANCELED;
501378c3
PB		 417
418 if (iocb->aiocb) {
4be74634 419 blk_aio_cancel_async(iocb->aiocb);
e551c999 420 iocb->aiocb = NULL;
501378c3 421 }
d353fb72
CH		 422}
423
d7331bed 424static const AIOCBInfo trim_aiocb_info = {
d353fb72 425 .aiocb_size = sizeof(TrimAIOCB),
e551c999 426 .cancel_async = trim_aio_cancel,
d353fb72
CH		 427};
428
429static void ide_trim_bh_cb(void *opaque)
430{
431 TrimAIOCB *iocb = opaque;
432
caeadbc8
AN		 433 iocb->common.cb(iocb->common.opaque, iocb->ret);
434
d353fb72
CH		 435 qemu_bh_delete(iocb->bh);
436 iocb->bh = NULL;
8007429a 437 qemu_aio_unref(iocb);
d353fb72
CH		 438}
439
501378c3
PB		 440static void ide_issue_trim_cb(void *opaque, int ret)
441{
442 TrimAIOCB *iocb = opaque;
ef0e64a9
AN		 443 IDEState *s = iocb->s;
444
99f18035
AN		 445 if (iocb->i >= 0) {
446 if (ret >= 0) {
447 block_acct_done(blk_get_stats(s->blk), &s->acct);
448 } else {
449 block_acct_failed(blk_get_stats(s->blk), &s->acct);
450 }
451 }
452
501378c3
PB		 453 if (ret >= 0) {
454 while (iocb->j < iocb->qiov->niov) {
455 int j = iocb->j;
456 while (++iocb->i < iocb->qiov->iov[j].iov_len / 8) {
457 int i = iocb->i;
458 uint64_t *buffer = iocb->qiov->iov[j].iov_base;
459
460 /* 6-byte LBA + 2-byte range per entry */
461 uint64_t entry = le64_to_cpu(buffer[i]);
462 uint64_t sector = entry & 0x0000ffffffffffffULL;
463 uint16_t count = entry >> 48;
464
465 if (count == 0) {
466 continue;
467 }
468
947858b0 469 if (!ide_sect_range_ok(s, sector, count)) {
99f18035 470 block_acct_invalid(blk_get_stats(s->blk), BLOCK_ACCT_UNMAP);
caeadbc8 471 iocb->ret = -EINVAL;
947858b0
AN		 472 goto done;
473 }
474
99f18035
AN		 475 block_acct_start(blk_get_stats(s->blk), &s->acct,
476 count << BDRV_SECTOR_BITS, BLOCK_ACCT_UNMAP);
477
501378c3 478 /* Got an entry! Submit and exit. */
ef0e64a9 479 iocb->aiocb = blk_aio_pdiscard(s->blk,
1c6c4bb7
EB		 480 sector << BDRV_SECTOR_BITS,
481 count << BDRV_SECTOR_BITS,
482 ide_issue_trim_cb, opaque);
501378c3
PB		 483 return;
484 }
485
486 iocb->j++;
487 iocb->i = -1;
488 }
489 } else {
490 iocb->ret = ret;
491 }
492
947858b0 493done:
501378c3
PB		 494 iocb->aiocb = NULL;
495 if (iocb->bh) {
b255df7e 496 replay_bh_schedule_event(iocb->bh);
501378c3
PB		 497 }
498}
499
8a8e63eb
PB		 500BlockAIOCB *ide_issue_trim(
501 int64_t offset, QEMUIOVector *qiov,
502 BlockCompletionFunc *cb, void *cb_opaque, void *opaque)
d353fb72 503{
ef0e64a9 504 IDEState *s = opaque;
d353fb72 505 TrimAIOCB *iocb;
d353fb72 506
ef0e64a9
AN		 507 iocb = blk_aio_get(&trim_aiocb_info, s->blk, cb, cb_opaque);
508 iocb->s = s;
d353fb72
CH		 509 iocb->bh = qemu_bh_new(ide_trim_bh_cb, iocb);
510 iocb->ret = 0;
501378c3
PB		 511 iocb->qiov = qiov;
512 iocb->i = -1;
513 iocb->j = 0;
514 ide_issue_trim_cb(iocb, 0);
d353fb72
CH		 515 return &iocb->common;
516}
517
9ef2e93f 518void ide_abort_command(IDEState *s)
5391d806 519{
08ee9e33 520 ide_transfer_stop(s);
5391d806
FB		 521 s->status = READY_STAT | ERR_STAT;
522 s->error = ABRT_ERR;
523}
524
0eeee07e
EY		 525static void ide_set_retry(IDEState *s)
526{
527 s->bus->retry_unit = s->unit;
528 s->bus->retry_sector_num = ide_get_sector(s);
529 s->bus->retry_nsector = s->nsector;
530}
531
532static void ide_clear_retry(IDEState *s)
533{
534 s->bus->retry_unit = -1;
535 s->bus->retry_sector_num = 0;
536 s->bus->retry_nsector = 0;
537}
538
5391d806 539/* prepare data transfer and tell what to do after */
c173723f
PB		 540bool ide_transfer_start_norecurse(IDEState *s, uint8_t *buf, int size,
541 EndTransferFunc *end_transfer_func)
5391d806 542{
5391d806
FB		 543 s->data_ptr = buf;
544 s->data_end = buf + size;
35f78ab4 545 ide_set_retry(s);
40a6238a 546 if (!(s->status & ERR_STAT)) {
7603d156 547 s->status |= DRQ_STAT;
40a6238a 548 }
bed9bcfa
PB		 549 if (!s->bus->dma->ops->pio_transfer) {
550 s->end_transfer_func = end_transfer_func;
c173723f 551 return false;
44635123 552 }
bed9bcfa 553 s->bus->dma->ops->pio_transfer(s->bus->dma);
c173723f
PB		 554 return true;
555}
556
557void ide_transfer_start(IDEState *s, uint8_t *buf, int size,
558 EndTransferFunc *end_transfer_func)
559{
560 if (ide_transfer_start_norecurse(s, buf, size, end_transfer_func)) {
561 end_transfer_func(s);
562 }
5391d806
FB		 563}
564
c7e73adb
PB		 565static void ide_cmd_done(IDEState *s)
566{
567 if (s->bus->dma->ops->cmd_done) {
568 s->bus->dma->ops->cmd_done(s->bus->dma);
569 }
570}
571
882941a5 572static void ide_transfer_halt(IDEState *s)
5391d806 573{
882941a5 574 s->end_transfer_func = ide_transfer_stop;
5391d806
FB		 575 s->data_ptr = s->io_buffer;
576 s->data_end = s->io_buffer;
577 s->status &= ~DRQ_STAT;
e3044e23
JS		 578}
579
580void ide_transfer_stop(IDEState *s)
581{
882941a5 582 ide_transfer_halt(s);
ee4cd662 583 ide_cmd_done(s);
e3044e23
JS		 584}
585
356721ae 586int64_t ide_get_sector(IDEState *s)
5391d806
FB		 587{
588 int64_t sector_num;
589 if (s->select & 0x40) {
590 /* lba */
7d37435b
PB		 591 if (!s->lba48) {
592 sector_num = ((s->select & 0x0f) << 24) | (s->hcyl << 16) |
593 (s->lcyl << 8) | s->sector;
594 } else {
595 sector_num = ((int64_t)s->hob_hcyl << 40) |
596 ((int64_t) s->hob_lcyl << 32) |
597 ((int64_t) s->hob_sector << 24) |
598 ((int64_t) s->hcyl << 16) |
599 ((int64_t) s->lcyl << 8) | s->sector;
600 }
5391d806
FB		 601 } else {
602 sector_num = ((s->hcyl << 8) | s->lcyl) * s->heads * s->sectors +
c2ff060f 603 (s->select & 0x0f) * s->sectors + (s->sector - 1);
5391d806
FB		 604 }
605 return sector_num;
606}
607
356721ae 608void ide_set_sector(IDEState *s, int64_t sector_num)
5391d806
FB		 609{
610 unsigned int cyl, r;
611 if (s->select & 0x40) {
7d37435b 612 if (!s->lba48) {
c2ff060f
FB		 613 s->select = (s->select & 0xf0) | (sector_num >> 24);
614 s->hcyl = (sector_num >> 16);
615 s->lcyl = (sector_num >> 8);
616 s->sector = (sector_num);
7d37435b
PB		 617 } else {
618 s->sector = sector_num;
619 s->lcyl = sector_num >> 8;
620 s->hcyl = sector_num >> 16;
621 s->hob_sector = sector_num >> 24;
622 s->hob_lcyl = sector_num >> 32;
623 s->hob_hcyl = sector_num >> 40;
624 }
5391d806
FB		 625 } else {
626 cyl = sector_num / (s->heads * s->sectors);
627 r = sector_num % (s->heads * s->sectors);
628 s->hcyl = cyl >> 8;
629 s->lcyl = cyl;
1b8eb456 630 s->select = (s->select & 0xf0) | ((r / s->sectors) & 0x0f);
5391d806
FB		 631 s->sector = (r % s->sectors) + 1;
632 }
633}
634
e162cfb0
AZ		 635static void ide_rw_error(IDEState *s) {
636 ide_abort_command(s);
9cdd03a7 637 ide_set_irq(s->bus);
e162cfb0
AZ		 638}
639
1d8c11d6
PL		 640static void ide_buffered_readv_cb(void *opaque, int ret)
641{
642 IDEBufferedRequest *req = opaque;
643 if (!req->orphaned) {
644 if (!ret) {
5bbe9325
VSO		 645 assert(req->qiov.size == req->original_qiov->size);
646 qemu_iovec_from_buf(req->original_qiov, 0,
647 req->qiov.local_iov.iov_base,
1d8c11d6
PL		 648 req->original_qiov->size);
649 }
650 req->original_cb(req->original_opaque, ret);
651 }
652 QLIST_REMOVE(req, list);
5bbe9325 653 qemu_vfree(qemu_iovec_buf(&req->qiov));
1d8c11d6
PL		 654 g_free(req);
655}
656
657#define MAX_BUFFERED_REQS 16
658
659BlockAIOCB *ide_buffered_readv(IDEState *s, int64_t sector_num,
660 QEMUIOVector *iov, int nb_sectors,
661 BlockCompletionFunc *cb, void *opaque)
662{
663 BlockAIOCB *aioreq;
664 IDEBufferedRequest *req;
665 int c = 0;
666
667 QLIST_FOREACH(req, &s->buffered_requests, list) {
668 c++;
669 }
670 if (c > MAX_BUFFERED_REQS) {
671 return blk_abort_aio_request(s->blk, cb, opaque, -EIO);
672 }
673
674 req = g_new0(IDEBufferedRequest, 1);
675 req->original_qiov = iov;
676 req->original_cb = cb;
677 req->original_opaque = opaque;
5bbe9325
VSO		 678 qemu_iovec_init_buf(&req->qiov, blk_blockalign(s->blk, iov->size),
679 iov->size);
1d8c11d6 680
d4f510eb
EB		 681 aioreq = blk_aio_preadv(s->blk, sector_num << BDRV_SECTOR_BITS,
682 &req->qiov, 0, ide_buffered_readv_cb, req);
1d8c11d6
PL		 683
684 QLIST_INSERT_HEAD(&s->buffered_requests, req, list);
685 return aioreq;
686}
687
86698a12
JS		 688/**
689 * Cancel all pending DMA requests.
690 * Any buffered DMA requests are instantly canceled,
691 * but any pending unbuffered DMA requests must be waited on.
692 */
693void ide_cancel_dma_sync(IDEState *s)
694{
695 IDEBufferedRequest *req;
696
697 /* First invoke the callbacks of all buffered requests
698 * and flag those requests as orphaned. Ideally there
699 * are no unbuffered (Scatter Gather DMA Requests or
700 * write requests) pending and we can avoid to drain. */
701 QLIST_FOREACH(req, &s->buffered_requests, list) {
702 if (!req->orphaned) {
3eee2611 703 trace_ide_cancel_dma_sync_buffered(req->original_cb, req);
86698a12
JS		 704 req->original_cb(req->original_opaque, -ECANCELED);
705 }
706 req->orphaned = true;
707 }
708
709 /*
710 * We can't cancel Scatter Gather DMA in the middle of the
711 * operation or a partial (not full) DMA transfer would reach
68b57b0d 712 * the storage so we wait for completion instead (we behave
86698a12
JS		 713 * like if the DMA was completed by the time the guest trying
714 * to cancel dma with bmdma_cmd_writeb with BM_CMD_START not
715 * set).
716 *
717 * In the future we'll be able to safely cancel the I/O if the
718 * whole DMA operation will be submitted to disk with a single
719 * aio operation with preadv/pwritev.
720 */
721 if (s->bus->dma->aiocb) {
3eee2611 722 trace_ide_cancel_dma_sync_remaining();
51f7b5b8 723 blk_drain(s->blk);
86698a12
JS		 724 assert(s->bus->dma->aiocb == NULL);
725 }
726}
727
4e2b8b4a
PB		 728static void ide_sector_read(IDEState *s);
729
bef0fd59
SH		 730static void ide_sector_read_cb(void *opaque, int ret)
731{
732 IDEState *s = opaque;
733 int n;
734
735 s->pio_aiocb = NULL;
736 s->status &= ~BUSY_STAT;
737
bef0fd59 738 if (ret != 0) {
fd648f10
PB		 739 if (ide_handle_rw_error(s, -ret, IDE_RETRY_PIO |
740 IDE_RETRY_READ)) {
bef0fd59
SH		 741 return;
742 }
743 }
744
ecca3b39
AG		 745 block_acct_done(blk_get_stats(s->blk), &s->acct);
746
bef0fd59
SH		 747 n = s->nsector;
748 if (n > s->req_nb_sectors) {
749 n = s->req_nb_sectors;
750 }
751
bef0fd59
SH		 752 ide_set_sector(s, ide_get_sector(s) + n);
753 s->nsector -= n;
dd0bf7ba
JS		 754 /* Allow the guest to read the io_buffer */
755 ide_transfer_start(s, s->io_buffer, n * BDRV_SECTOR_SIZE, ide_sector_read);
dd0bf7ba 756 ide_set_irq(s->bus);
bef0fd59
SH		 757}
758
4e2b8b4a 759static void ide_sector_read(IDEState *s)
5391d806
FB		 760{
761 int64_t sector_num;
bef0fd59 762 int n;
5391d806
FB		 763
764 s->status = READY_STAT | SEEK_STAT;
a136e5a8 765 s->error = 0; /* not needed by IDE spec, but needed by Windows */
5391d806
FB		 766 sector_num = ide_get_sector(s);
767 n = s->nsector;
bef0fd59 768
5391d806 769 if (n == 0) {
5391d806 770 ide_transfer_stop(s);
bef0fd59
SH		 771 return;
772 }
773
774 s->status |= BUSY_STAT;
775
776 if (n > s->req_nb_sectors) {
777 n = s->req_nb_sectors;
778 }
779
3eee2611 780 trace_ide_sector_read(sector_num, n);
a597e79c 781
58ac3211
MA		 782 if (!ide_sect_range_ok(s, sector_num, n)) {
783 ide_rw_error(s);
ecca3b39 784 block_acct_invalid(blk_get_stats(s->blk), BLOCK_ACCT_READ);
58ac3211
MA		 785 return;
786 }
787
e5863d49 788 qemu_iovec_init_buf(&s->qiov, s->io_buffer, n * BDRV_SECTOR_SIZE);
bef0fd59 789
4be74634 790 block_acct_start(blk_get_stats(s->blk), &s->acct,
5366d0c8 791 n * BDRV_SECTOR_SIZE, BLOCK_ACCT_READ);
d66a8fa8
PL		 792 s->pio_aiocb = ide_buffered_readv(s, sector_num, &s->qiov, n,
793 ide_sector_read_cb, s);
5391d806
FB		 794}
795
aaeda4a3 796void dma_buf_commit(IDEState *s, uint32_t tx_bytes)
7aea4412 797{
659142ec
JS		 798 if (s->bus->dma->ops->commit_buf) {
799 s->bus->dma->ops->commit_buf(s->bus->dma, tx_bytes);
800 }
aaeda4a3 801 s->io_buffer_offset += tx_bytes;
1fb8648d 802 qemu_sglist_destroy(&s->sg);
7aea4412
AL		 803}
804
0e7ce54c 805void ide_set_inactive(IDEState *s, bool more)
8337606d 806{
40a6238a 807 s->bus->dma->aiocb = NULL;
0eeee07e 808 ide_clear_retry(s);
829b933b 809 if (s->bus->dma->ops->set_inactive) {
0e7ce54c 810 s->bus->dma->ops->set_inactive(s->bus->dma, more);
829b933b 811 }
c7e73adb 812 ide_cmd_done(s);
8337606d
KW		 813}
814
356721ae 815void ide_dma_error(IDEState *s)
e162cfb0 816{
659142ec 817 dma_buf_commit(s, 0);
08ee9e33 818 ide_abort_command(s);
0e7ce54c 819 ide_set_inactive(s, false);
9cdd03a7 820 ide_set_irq(s->bus);
e162cfb0
AZ		 821}
822
502356ee 823int ide_handle_rw_error(IDEState *s, int error, int op)
428c5705 824{
fd648f10 825 bool is_read = (op & IDE_RETRY_READ) != 0;
4be74634 826 BlockErrorAction action = blk_get_error_action(s->blk, is_read, error);
428c5705 827
a589569f 828 if (action == BLOCK_ERROR_ACTION_STOP) {
a96cb236 829 assert(s->bus->retry_unit == s->unit);
def93791 830 s->bus->error_status = op;
a589569f 831 } else if (action == BLOCK_ERROR_ACTION_REPORT) {
ecca3b39 832 block_acct_failed(blk_get_stats(s->blk), &s->acct);
502356ee 833 if (IS_IDE_RETRY_DMA(op)) {
428c5705 834 ide_dma_error(s);
502356ee
PB		 835 } else if (IS_IDE_RETRY_ATAPI(op)) {
836 ide_atapi_io_error(s, -error);
7aea4412 837 } else {
428c5705 838 ide_rw_error(s);
7aea4412 839 }
428c5705 840 }
4be74634 841 blk_error_action(s->blk, action, is_read, error);
a589569f 842 return action != BLOCK_ERROR_ACTION_IGNORE;
428c5705
AL		 843}
844
4e2b8b4a 845static void ide_dma_cb(void *opaque, int ret)
98087450 846{
40a6238a 847 IDEState *s = opaque;
8ccad811
FB		 848 int n;
849 int64_t sector_num;
cbe0ed62 850 uint64_t offset;
038268e2 851 bool stay_active = false;
ed78352a 852 int32_t prep_size = 0;
8ccad811 853
caeadbc8
AN		 854 if (ret == -EINVAL) {
855 ide_dma_error(s);
856 return;
857 }
858
e162cfb0 859 if (ret < 0) {
218fd37c 860 if (ide_handle_rw_error(s, -ret, ide_dma_cmd_to_retry(s->dma_cmd))) {
87ac25fd 861 s->bus->dma->aiocb = NULL;
5839df7b 862 dma_buf_commit(s, 0);
ce4b6522
KW		 863 return;
864 }
e162cfb0
AZ		 865 }
866
ed78352a
AP		 867 if (s->io_buffer_size > s->nsector * 512) {
868 /*
869 * The PRDs were longer than needed for this request.
870 * The Active bit must remain set after the request completes.
871 */
038268e2
KW		 872 n = s->nsector;
873 stay_active = true;
ed78352a
AP		 874 } else {
875 n = s->io_buffer_size >> 9;
038268e2
KW		 876 }
877
8ccad811
FB		 878 sector_num = ide_get_sector(s);
879 if (n > 0) {
a718978e
JS		 880 assert(n * 512 == s->sg.size);
881 dma_buf_commit(s, s->sg.size);
8ccad811
FB		 882 sector_num += n;
883 ide_set_sector(s, sector_num);
884 s->nsector -= n;
8ccad811
FB		 885 }
886
887 /* end of transfer ? */
888 if (s->nsector == 0) {
98087450 889 s->status = READY_STAT | SEEK_STAT;
9cdd03a7 890 ide_set_irq(s->bus);
cd369c46 891 goto eot;
98087450 892 }
8ccad811
FB		 893
894 /* launch next transfer */
895 n = s->nsector;
596bb44d 896 s->io_buffer_index = 0;
8ccad811 897 s->io_buffer_size = n * 512;
ed78352a
AP		 898 prep_size = s->bus->dma->ops->prepare_buf(s->bus->dma, s->io_buffer_size);
899 /* prepare_buf() must succeed and respect the limit */
900 assert(prep_size >= 0 && prep_size <= n * 512);
901
902 /*
903 * Now prep_size stores the number of bytes in the sglist, and
904 * s->io_buffer_size stores the number of bytes described by the PRDs.
905 */
906
907 if (prep_size < n * 512) {
908 /*
909 * The PRDs are too short for this request. Error condition!
910 * Reset the Active bit and don't raise the interrupt.
911 */
72bcca73 912 s->status = READY_STAT | SEEK_STAT;
3251bdcf 913 dma_buf_commit(s, 0);
7aea4412 914 goto eot;
69c38b8f 915 }
cd369c46 916
0e168d35 917 trace_ide_dma_cb(s, sector_num, n, IDE_DMA_CMD_str(s->dma_cmd));
cd369c46 918
d66168ed
MT		 919 if ((s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) &&
920 !ide_sect_range_ok(s, sector_num, n)) {
58ac3211 921 ide_dma_error(s);
ecca3b39 922 block_acct_invalid(blk_get_stats(s->blk), s->acct.type);
58ac3211
MA		 923 return;
924 }
925
cbe0ed62 926 offset = sector_num << BDRV_SECTOR_BITS;
4e1e0051
CH		 927 switch (s->dma_cmd) {
928 case IDE_DMA_READ:
cbe0ed62 929 s->bus->dma->aiocb = dma_blk_read(s->blk, &s->sg, offset,
99868af3 930 BDRV_SECTOR_SIZE, ide_dma_cb, s);
4e1e0051
CH		 931 break;
932 case IDE_DMA_WRITE:
cbe0ed62 933 s->bus->dma->aiocb = dma_blk_write(s->blk, &s->sg, offset,
99868af3 934 BDRV_SECTOR_SIZE, ide_dma_cb, s);
4e1e0051 935 break;
d353fb72 936 case IDE_DMA_TRIM:
8a8e63eb 937 s->bus->dma->aiocb = dma_blk_io(blk_get_aio_context(s->blk),
99868af3 938 &s->sg, offset, BDRV_SECTOR_SIZE,
ef0e64a9 939 ide_issue_trim, s, ide_dma_cb, s,
4be74634 940 DMA_DIRECTION_TO_DEVICE);
d353fb72 941 break;
502356ee
PB		 942 default:
943 abort();
cd369c46 944 }
cd369c46
CH		 945 return;
946
947eot:
a597e79c 948 if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) {
4be74634 949 block_acct_done(blk_get_stats(s->blk), &s->acct);
a597e79c 950 }
0e7ce54c 951 ide_set_inactive(s, stay_active);
98087450
FB		 952}
953
4e1e0051 954static void ide_sector_start_dma(IDEState *s, enum ide_dma_cmd dma_cmd)
98087450 955{
9da82227 956 s->status = READY_STAT | SEEK_STAT | DRQ_STAT;
98087450 957 s->io_buffer_size = 0;
4e1e0051 958 s->dma_cmd = dma_cmd;
a597e79c
CH		 959
960 switch (dma_cmd) {
961 case IDE_DMA_READ:
4be74634 962 block_acct_start(blk_get_stats(s->blk), &s->acct,
5366d0c8 963 s->nsector * BDRV_SECTOR_SIZE, BLOCK_ACCT_READ);
a597e79c
CH		 964 break;
965 case IDE_DMA_WRITE:
4be74634 966 block_acct_start(blk_get_stats(s->blk), &s->acct,
5366d0c8 967 s->nsector * BDRV_SECTOR_SIZE, BLOCK_ACCT_WRITE);
a597e79c
CH		 968 break;
969 default:
970 break;
971 }
972
4855b576
PB		 973 ide_start_dma(s, ide_dma_cb);
974}
975
097310b5 976void ide_start_dma(IDEState *s, BlockCompletionFunc *cb)
4855b576 977{
c71c06d4 978 s->io_buffer_index = 0;
0eeee07e 979 ide_set_retry(s);
4855b576
PB		 980 if (s->bus->dma->ops->start_dma) {
981 s->bus->dma->ops->start_dma(s->bus->dma, s, cb);
982 }
98087450
FB		 983}
984
4e2b8b4a
PB		 985static void ide_sector_write(IDEState *s);
986
a09db21f
FB		 987static void ide_sector_write_timer_cb(void *opaque)
988{
989 IDEState *s = opaque;
9cdd03a7 990 ide_set_irq(s->bus);
a09db21f
FB		 991}
992
e82dabd8 993static void ide_sector_write_cb(void *opaque, int ret)
5391d806 994{
e82dabd8
SH		 995 IDEState *s = opaque;
996 int n;
a597e79c 997
e82dabd8
SH		 998 s->pio_aiocb = NULL;
999 s->status &= ~BUSY_STAT;
1000
e162cfb0 1001 if (ret != 0) {
fd648f10 1002 if (ide_handle_rw_error(s, -ret, IDE_RETRY_PIO)) {
428c5705 1003 return;
e82dabd8 1004 }
e162cfb0
AZ		 1005 }
1006
ecca3b39
AG		 1007 block_acct_done(blk_get_stats(s->blk), &s->acct);
1008
e82dabd8
SH		 1009 n = s->nsector;
1010 if (n > s->req_nb_sectors) {
1011 n = s->req_nb_sectors;
1012 }
5391d806 1013 s->nsector -= n;
36334faf 1014
6aff22c0 1015 ide_set_sector(s, ide_get_sector(s) + n);
5391d806 1016 if (s->nsector == 0) {
292eef5a 1017 /* no more sectors to write */
5391d806
FB		 1018 ide_transfer_stop(s);
1019 } else {
e82dabd8
SH		 1020 int n1 = s->nsector;
1021 if (n1 > s->req_nb_sectors) {
5391d806 1022 n1 = s->req_nb_sectors;
e82dabd8
SH		 1023 }
1024 ide_transfer_start(s, s->io_buffer, n1 * BDRV_SECTOR_SIZE,
1025 ide_sector_write);
5391d806 1026 }
3b46e624 1027
31c2a146
TS		 1028 if (win2k_install_hack && ((++s->irq_count % 16) == 0)) {
1029 /* It seems there is a bug in the Windows 2000 installer HDD
1030 IDE driver which fills the disk with empty logs when the
1031 IDE write IRQ comes too early. This hack tries to correct
1032 that at the expense of slower write performances. Use this
1033 option _only_ to install Windows 2000. You must disable it
1034 for normal use. */
73bcb24d
RS		 1035 timer_mod(s->sector_write_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
1036 (NANOSECONDS_PER_SECOND / 1000));
f7736b91 1037 } else {
9cdd03a7 1038 ide_set_irq(s->bus);
31c2a146 1039 }
5391d806
FB		 1040}
1041
4e2b8b4a 1042static void ide_sector_write(IDEState *s)
e82dabd8
SH		 1043{
1044 int64_t sector_num;
1045 int n;
1046
1047 s->status = READY_STAT | SEEK_STAT | BUSY_STAT;
1048 sector_num = ide_get_sector(s);
3eee2611 1049
e82dabd8
SH		 1050 n = s->nsector;
1051 if (n > s->req_nb_sectors) {
1052 n = s->req_nb_sectors;
1053 }
1054
3eee2611
JS		 1055 trace_ide_sector_write(sector_num, n);
1056
58ac3211
MA		 1057 if (!ide_sect_range_ok(s, sector_num, n)) {
1058 ide_rw_error(s);
ecca3b39 1059 block_acct_invalid(blk_get_stats(s->blk), BLOCK_ACCT_WRITE);
58ac3211
MA		 1060 return;
1061 }
1062
e5863d49 1063 qemu_iovec_init_buf(&s->qiov, s->io_buffer, n * BDRV_SECTOR_SIZE);
e82dabd8 1064
4be74634 1065 block_acct_start(blk_get_stats(s->blk), &s->acct,
c618f331 1066 n * BDRV_SECTOR_SIZE, BLOCK_ACCT_WRITE);
d4f510eb
EB		 1067 s->pio_aiocb = blk_aio_pwritev(s->blk, sector_num << BDRV_SECTOR_BITS,
1068 &s->qiov, 0, ide_sector_write_cb, s);
e82dabd8
SH		 1069}
1070
b0484ae4
CH		 1071static void ide_flush_cb(void *opaque, int ret)
1072{
1073 IDEState *s = opaque;
1074
69f72a22
PB		 1075 s->pio_aiocb = NULL;
1076
e2bcadad
KW		 1077 if (ret < 0) {
1078 /* XXX: What sector number to set here? */
fd648f10 1079 if (ide_handle_rw_error(s, -ret, IDE_RETRY_FLUSH)) {
e2bcadad
KW		 1080 return;
1081 }
1082 }
b0484ae4 1083
4be74634
MA		 1084 if (s->blk) {
1085 block_acct_done(blk_get_stats(s->blk), &s->acct);
f7f3ff1d 1086 }
b0484ae4 1087 s->status = READY_STAT | SEEK_STAT;
c7e73adb 1088 ide_cmd_done(s);
b0484ae4
CH		 1089 ide_set_irq(s->bus);
1090}
1091
4e2b8b4a 1092static void ide_flush_cache(IDEState *s)
6bcb1a79 1093{
4be74634 1094 if (s->blk == NULL) {
6bcb1a79 1095 ide_flush_cb(s, 0);
b2df7531
KW		 1096 return;
1097 }
1098
f68ec837 1099 s->status |= BUSY_STAT;
35f78ab4 1100 ide_set_retry(s);
4be74634 1101 block_acct_start(blk_get_stats(s->blk), &s->acct, 0, BLOCK_ACCT_FLUSH);
13471a40 1102 s->pio_aiocb = blk_aio_flush(s->blk, ide_flush_cb, s);
6bcb1a79
KW		 1103}
1104
201a51fc
AZ		 1105static void ide_cfata_metadata_inquiry(IDEState *s)
1106{
1107 uint16_t *p;
1108 uint32_t spd;
1109
1110 p = (uint16_t *) s->io_buffer;
1111 memset(p, 0, 0x200);
1112 spd = ((s->mdata_size - 1) >> 9) + 1;
1113
1114 put_le16(p + 0, 0x0001); /* Data format revision */
1115 put_le16(p + 1, 0x0000); /* Media property: silicon */
1116 put_le16(p + 2, s->media_changed); /* Media status */
1117 put_le16(p + 3, s->mdata_size & 0xffff); /* Capacity in bytes (low) */
1118 put_le16(p + 4, s->mdata_size >> 16); /* Capacity in bytes (high) */
1119 put_le16(p + 5, spd & 0xffff); /* Sectors per device (low) */
1120 put_le16(p + 6, spd >> 16); /* Sectors per device (high) */
1121}
1122
1123static void ide_cfata_metadata_read(IDEState *s)
1124{
1125 uint16_t *p;
1126
1127 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
1128 s->status = ERR_STAT;
1129 s->error = ABRT_ERR;
1130 return;
1131 }
1132
1133 p = (uint16_t *) s->io_buffer;
1134 memset(p, 0, 0x200);
1135
1136 put_le16(p + 0, s->media_changed); /* Media status */
1137 memcpy(p + 1, s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
1138 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
1139 s->nsector << 9), 0x200 - 2));
1140}
1141
1142static void ide_cfata_metadata_write(IDEState *s)
1143{
1144 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
1145 s->status = ERR_STAT;
1146 s->error = ABRT_ERR;
1147 return;
1148 }
1149
1150 s->media_changed = 0;
1151
1152 memcpy(s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
1153 s->io_buffer + 2,
1154 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
1155 s->nsector << 9), 0x200 - 2));
1156}
1157
bd491d6a 1158/* called when the inserted state of the media has changed */
39829a01 1159static void ide_cd_change_cb(void *opaque, bool load, Error **errp)
bd491d6a
TS		 1160{
1161 IDEState *s = opaque;
96b8f136 1162 uint64_t nb_sectors;
bd491d6a 1163
25ad22bc 1164 s->tray_open = !load;
4be74634 1165 blk_get_geometry(s->blk, &nb_sectors);
bd491d6a 1166 s->nb_sectors = nb_sectors;
9118e7f0 1167
4b9b7092
AS		 1168 /*
1169 * First indicate to the guest that a CD has been removed. That's
1170 * done on the next command the guest sends us.
1171 *
67cc61e4 1172 * Then we set UNIT_ATTENTION, by which the guest will
4b9b7092
AS		 1173 * detect a new CD in the drive. See ide_atapi_cmd() for details.
1174 */
93c8cfd9 1175 s->cdrom_changed = 1;
996faf1a 1176 s->events.new_media = true;
2df0a3a3
PB		 1177 s->events.eject_request = false;
1178 ide_set_irq(s->bus);
1179}
1180
1181static void ide_cd_eject_request_cb(void *opaque, bool force)
1182{
1183 IDEState *s = opaque;
1184
1185 s->events.eject_request = true;
1186 if (force) {
1187 s->tray_locked = false;
1188 }
9cdd03a7 1189 ide_set_irq(s->bus);
bd491d6a
TS		 1190}
1191
c2ff060f
FB		 1192static void ide_cmd_lba48_transform(IDEState *s, int lba48)
1193{
1194 s->lba48 = lba48;
1195
1196 /* handle the 'magic' 0 nsector count conversion here. to avoid
1197 * fiddling with the rest of the read logic, we just store the
1198 * full sector count in ->nsector and ignore ->hob_nsector from now
1199 */
1200 if (!s->lba48) {
7d37435b
PB		 1201 if (!s->nsector)
1202 s->nsector = 256;
c2ff060f 1203 } else {
7d37435b
PB		 1204 if (!s->nsector && !s->hob_nsector)
1205 s->nsector = 65536;
1206 else {
1207 int lo = s->nsector;
1208 int hi = s->hob_nsector;
c2ff060f 1209
7d37435b
PB		 1210 s->nsector = (hi << 8) | lo;
1211 }
c2ff060f
FB		 1212 }
1213}
1214
bcbdc4d3 1215static void ide_clear_hob(IDEBus *bus)
c2ff060f
FB		 1216{
1217 /* any write clears HOB high bit of device control register */
bcbdc4d3
GH		 1218 bus->ifs[0].select &= ~(1 << 7);
1219 bus->ifs[1].select &= ~(1 << 7);
c2ff060f
FB		 1220}
1221
335ca2f2
JS		 1222/* IOport [W]rite [R]egisters */
1223enum ATA_IOPORT_WR {
1224 ATA_IOPORT_WR_DATA = 0,
1225 ATA_IOPORT_WR_FEATURES = 1,
1226 ATA_IOPORT_WR_SECTOR_COUNT = 2,
1227 ATA_IOPORT_WR_SECTOR_NUMBER = 3,
1228 ATA_IOPORT_WR_CYLINDER_LOW = 4,
1229 ATA_IOPORT_WR_CYLINDER_HIGH = 5,
1230 ATA_IOPORT_WR_DEVICE_HEAD = 6,
1231 ATA_IOPORT_WR_COMMAND = 7,
1232 ATA_IOPORT_WR_NUM_REGISTERS,
1233};
1234
1235const char *ATA_IOPORT_WR_lookup[ATA_IOPORT_WR_NUM_REGISTERS] = {
1236 [ATA_IOPORT_WR_DATA] = "Data",
1237 [ATA_IOPORT_WR_FEATURES] = "Features",
1238 [ATA_IOPORT_WR_SECTOR_COUNT] = "Sector Count",
1239 [ATA_IOPORT_WR_SECTOR_NUMBER] = "Sector Number",
1240 [ATA_IOPORT_WR_CYLINDER_LOW] = "Cylinder Low",
1241 [ATA_IOPORT_WR_CYLINDER_HIGH] = "Cylinder High",
1242 [ATA_IOPORT_WR_DEVICE_HEAD] = "Device/Head",
1243 [ATA_IOPORT_WR_COMMAND] = "Command"
1244};
1245
356721ae 1246void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
caed8802 1247{
bcbdc4d3 1248 IDEBus *bus = opaque;
3eee2611
JS		 1249 IDEState *s = idebus_active_if(bus);
1250 int reg_num = addr & 7;
5391d806 1251
335ca2f2 1252 trace_ide_ioport_write(addr, ATA_IOPORT_WR_lookup[reg_num], val, bus, s);
fcdd25ab
AL		 1253
1254 /* ignore writes to command block while busy with previous command */
3eee2611 1255 if (reg_num != 7 && (s->status & (BUSY_STAT|DRQ_STAT))) {
fcdd25ab 1256 return;
3eee2611 1257 }
fcdd25ab 1258
3eee2611 1259 switch (reg_num) {
5391d806
FB		 1260 case 0:
1261 break;
335ca2f2
JS		 1262 case ATA_IOPORT_WR_FEATURES:
1263 ide_clear_hob(bus);
c45c3d00 1264 /* NOTE: data is written to the two drives */
335ca2f2
JS		 1265 bus->ifs[0].hob_feature = bus->ifs[0].feature;
1266 bus->ifs[1].hob_feature = bus->ifs[1].feature;
bcbdc4d3
GH		 1267 bus->ifs[0].feature = val;
1268 bus->ifs[1].feature = val;
5391d806 1269 break;
335ca2f2 1270 case ATA_IOPORT_WR_SECTOR_COUNT:
7d37435b
PB		 1271 ide_clear_hob(bus);
1272 bus->ifs[0].hob_nsector = bus->ifs[0].nsector;
1273 bus->ifs[1].hob_nsector = bus->ifs[1].nsector;
bcbdc4d3
GH		 1274 bus->ifs[0].nsector = val;
1275 bus->ifs[1].nsector = val;
5391d806 1276 break;
335ca2f2 1277 case ATA_IOPORT_WR_SECTOR_NUMBER:
7d37435b
PB		 1278 ide_clear_hob(bus);
1279 bus->ifs[0].hob_sector = bus->ifs[0].sector;
1280 bus->ifs[1].hob_sector = bus->ifs[1].sector;
bcbdc4d3
GH		 1281 bus->ifs[0].sector = val;
1282 bus->ifs[1].sector = val;
5391d806 1283 break;
335ca2f2 1284 case ATA_IOPORT_WR_CYLINDER_LOW:
7d37435b
PB		 1285 ide_clear_hob(bus);
1286 bus->ifs[0].hob_lcyl = bus->ifs[0].lcyl;
1287 bus->ifs[1].hob_lcyl = bus->ifs[1].lcyl;
bcbdc4d3
GH		 1288 bus->ifs[0].lcyl = val;
1289 bus->ifs[1].lcyl = val;
5391d806 1290 break;
335ca2f2 1291 case ATA_IOPORT_WR_CYLINDER_HIGH:
7d37435b
PB		 1292 ide_clear_hob(bus);
1293 bus->ifs[0].hob_hcyl = bus->ifs[0].hcyl;
1294 bus->ifs[1].hob_hcyl = bus->ifs[1].hcyl;
bcbdc4d3
GH		 1295 bus->ifs[0].hcyl = val;
1296 bus->ifs[1].hcyl = val;
5391d806 1297 break;
335ca2f2 1298 case ATA_IOPORT_WR_DEVICE_HEAD:
7d37435b 1299 /* FIXME: HOB readback uses bit 7 */
bcbdc4d3
GH		 1300 bus->ifs[0].select = (val & ~0x10) | 0xa0;
1301 bus->ifs[1].select = (val | 0x10) | 0xa0;
5391d806 1302 /* select drive */
bcbdc4d3 1303 bus->unit = (val >> 4) & 1;
5391d806
FB		 1304 break;
1305 default:
335ca2f2 1306 case ATA_IOPORT_WR_COMMAND:
5391d806 1307 /* command */
7cff87ff
AG		 1308 ide_exec_cmd(bus, val);
1309 break;
1310 }
1311}
1312
4590355b
JS		 1313static void ide_reset(IDEState *s)
1314{
3eee2611 1315 trace_ide_reset(s);
4590355b
JS		 1316
1317 if (s->pio_aiocb) {
1318 blk_aio_cancel(s->pio_aiocb);
1319 s->pio_aiocb = NULL;
1320 }
1321
1322 if (s->drive_kind == IDE_CFATA)
1323 s->mult_sectors = 0;
1324 else
1325 s->mult_sectors = MAX_MULT_SECTORS;
1326 /* ide regs */
1327 s->feature = 0;
1328 s->error = 0;
1329 s->nsector = 0;
1330 s->sector = 0;
1331 s->lcyl = 0;
1332 s->hcyl = 0;
1333
1334 /* lba48 */
1335 s->hob_feature = 0;
1336 s->hob_sector = 0;
1337 s->hob_nsector = 0;
1338 s->hob_lcyl = 0;
1339 s->hob_hcyl = 0;
1340
1341 s->select = 0xa0;
1342 s->status = READY_STAT | SEEK_STAT;
1343
1344 s->lba48 = 0;
1345
1346 /* ATAPI specific */
1347 s->sense_key = 0;
1348 s->asc = 0;
1349 s->cdrom_changed = 0;
1350 s->packet_transfer_size = 0;
1351 s->elementary_transfer_size = 0;
1352 s->io_buffer_index = 0;
1353 s->cd_sector_size = 0;
1354 s->atapi_dma = 0;
1355 s->tray_locked = 0;
1356 s->tray_open = 0;
1357 /* ATA DMA state */
1358 s->io_buffer_size = 0;
1359 s->req_nb_sectors = 0;
1360
1361 ide_set_signature(s);
1362 /* init the transfer handler so that 0xffff is returned on data
1363 accesses */
1364 s->end_transfer_func = ide_dummy_transfer_stop;
1365 ide_dummy_transfer_stop(s);
1366 s->media_changed = 0;
1367}
1368
b300337e
KW		 1369static bool cmd_nop(IDEState *s, uint8_t cmd)
1370{
1371 return true;
1372}
1373
f34ae00d
JS		 1374static bool cmd_device_reset(IDEState *s, uint8_t cmd)
1375{
1376 /* Halt PIO (in the DRQ phase), then DMA */
882941a5 1377 ide_transfer_halt(s);
f34ae00d
JS		 1378 ide_cancel_dma_sync(s);
1379
1380 /* Reset any PIO commands, reset signature, etc */
1381 ide_reset(s);
1382
1383 /* RESET: ATA8-ACS3 7.10.4 "Normal Outputs";
1384 * ATA8-ACS3 Table 184 "Device Signatures for Normal Output" */
1385 s->status = 0x00;
1386
1387 /* Do not overwrite status register */
1388 return false;
1389}
1390
4286434c
KW		 1391static bool cmd_data_set_management(IDEState *s, uint8_t cmd)
1392{
1393 switch (s->feature) {
1394 case DSM_TRIM:
4be74634 1395 if (s->blk) {
4286434c
KW		 1396 ide_sector_start_dma(s, IDE_DMA_TRIM);
1397 return false;
1398 }
1399 break;
1400 }
1401
1402 ide_abort_command(s);
1403 return true;
1404}
1405
1c66869a
KW		 1406static bool cmd_identify(IDEState *s, uint8_t cmd)
1407{
4be74634 1408 if (s->blk && s->drive_kind != IDE_CD) {
1c66869a
KW		 1409 if (s->drive_kind != IDE_CFATA) {
1410 ide_identify(s);
1411 } else {
1412 ide_cfata_identify(s);
1413 }
1414 s->status = READY_STAT | SEEK_STAT;
1415 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
1416 ide_set_irq(s->bus);
1417 return false;
1418 } else {
1419 if (s->drive_kind == IDE_CD) {
1420 ide_set_signature(s);
1421 }
1422 ide_abort_command(s);
1423 }
1424
1425 return true;
1426}
1427
413860cf
KW		 1428static bool cmd_verify(IDEState *s, uint8_t cmd)
1429{
1430 bool lba48 = (cmd == WIN_VERIFY_EXT);
1431
1432 /* do sector number check ? */
1433 ide_cmd_lba48_transform(s, lba48);
1434
1435 return true;
1436}
1437
adf3a2c4
KW		 1438static bool cmd_set_multiple_mode(IDEState *s, uint8_t cmd)
1439{
1440 if (s->drive_kind == IDE_CFATA && s->nsector == 0) {
1441 /* Disable Read and Write Multiple */
1442 s->mult_sectors = 0;
1443 } else if ((s->nsector & 0xff) != 0 &&
1444 ((s->nsector & 0xff) > MAX_MULT_SECTORS ||
1445 (s->nsector & (s->nsector - 1)) != 0)) {
1446 ide_abort_command(s);
1447 } else {
1448 s->mult_sectors = s->nsector & 0xff;
1449 }
1450
1451 return true;
1452}
1453
1454static bool cmd_read_multiple(IDEState *s, uint8_t cmd)
1455{
1456 bool lba48 = (cmd == WIN_MULTREAD_EXT);
1457
4be74634 1458 if (!s->blk || !s->mult_sectors) {
adf3a2c4
KW		 1459 ide_abort_command(s);
1460 return true;
1461 }
1462
1463 ide_cmd_lba48_transform(s, lba48);
1464 s->req_nb_sectors = s->mult_sectors;
1465 ide_sector_read(s);
1466 return false;
1467}
1468
1469static bool cmd_write_multiple(IDEState *s, uint8_t cmd)
1470{
1471 bool lba48 = (cmd == WIN_MULTWRITE_EXT);
1472 int n;
1473
4be74634 1474 if (!s->blk || !s->mult_sectors) {
adf3a2c4
KW		 1475 ide_abort_command(s);
1476 return true;
1477 }
1478
1479 ide_cmd_lba48_transform(s, lba48);
1480
1481 s->req_nb_sectors = s->mult_sectors;
1482 n = MIN(s->nsector, s->req_nb_sectors);
1483
1484 s->status = SEEK_STAT | READY_STAT;
1485 ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_write);
1486
1487 s->media_changed = 1;
1488
1489 return false;
1490}
1491
0e6498ed
KW		 1492static bool cmd_read_pio(IDEState *s, uint8_t cmd)
1493{
1494 bool lba48 = (cmd == WIN_READ_EXT);
1495
1496 if (s->drive_kind == IDE_CD) {
1497 ide_set_signature(s); /* odd, but ATA4 8.27.5.2 requires it */
1498 ide_abort_command(s);
1499 return true;
1500 }
1501
4be74634 1502 if (!s->blk) {
0e6498ed
KW		 1503 ide_abort_command(s);
1504 return true;
1505 }
1506
1507 ide_cmd_lba48_transform(s, lba48);
1508 s->req_nb_sectors = 1;
1509 ide_sector_read(s);
1510
1511 return false;
1512}
1513
1514static bool cmd_write_pio(IDEState *s, uint8_t cmd)
1515{
1516 bool lba48 = (cmd == WIN_WRITE_EXT);
1517
4be74634 1518 if (!s->blk) {
0e6498ed
KW		 1519 ide_abort_command(s);
1520 return true;
1521 }
1522
1523 ide_cmd_lba48_transform(s, lba48);
1524
1525 s->req_nb_sectors = 1;
1526 s->status = SEEK_STAT | READY_STAT;
1527 ide_transfer_start(s, s->io_buffer, 512, ide_sector_write);
1528
1529 s->media_changed = 1;
1530
1531 return false;
1532}
1533
92a6a6f6
KW		 1534static bool cmd_read_dma(IDEState *s, uint8_t cmd)
1535{
1536 bool lba48 = (cmd == WIN_READDMA_EXT);
1537
4be74634 1538 if (!s->blk) {
92a6a6f6
KW		 1539 ide_abort_command(s);
1540 return true;
1541 }
1542
1543 ide_cmd_lba48_transform(s, lba48);
1544 ide_sector_start_dma(s, IDE_DMA_READ);
1545
1546 return false;
1547}
1548
1549static bool cmd_write_dma(IDEState *s, uint8_t cmd)
1550{
1551 bool lba48 = (cmd == WIN_WRITEDMA_EXT);
1552
4be74634 1553 if (!s->blk) {
92a6a6f6
KW		 1554 ide_abort_command(s);
1555 return true;
1556 }
1557
1558 ide_cmd_lba48_transform(s, lba48);
1559 ide_sector_start_dma(s, IDE_DMA_WRITE);
1560
1561 s->media_changed = 1;
1562
1563 return false;
1564}
1565
9afce429
KW		 1566static bool cmd_flush_cache(IDEState *s, uint8_t cmd)
1567{
1568 ide_flush_cache(s);
1569 return false;
1570}
1571
61fdda37
KW		 1572static bool cmd_seek(IDEState *s, uint8_t cmd)
1573{
1574 /* XXX: Check that seek is within bounds */
1575 return true;
1576}
1577
63a82e6a
KW		 1578static bool cmd_read_native_max(IDEState *s, uint8_t cmd)
1579{
1580 bool lba48 = (cmd == WIN_READ_NATIVE_MAX_EXT);
1581
1582 /* Refuse if no sectors are addressable (e.g. medium not inserted) */
1583 if (s->nb_sectors == 0) {
1584 ide_abort_command(s);
1585 return true;
1586 }
1587
1588 ide_cmd_lba48_transform(s, lba48);
1589 ide_set_sector(s, s->nb_sectors - 1);
1590
1591 return true;
1592}
1593
785f6320
KW		 1594static bool cmd_check_power_mode(IDEState *s, uint8_t cmd)
1595{
1596 s->nsector = 0xff; /* device active or idle */
1597 return true;
1598}
1599
ee03398c
KW		 1600static bool cmd_set_features(IDEState *s, uint8_t cmd)
1601{
1602 uint16_t *identify_data;
1603
4be74634 1604 if (!s->blk) {
ee03398c
KW		 1605 ide_abort_command(s);
1606 return true;
1607 }
1608
1609 /* XXX: valid for CDROM ? */
1610 switch (s->feature) {
1611 case 0x02: /* write cache enable */
4be74634 1612 blk_set_enable_write_cache(s->blk, true);
ee03398c
KW		 1613 identify_data = (uint16_t *)s->identify_data;
1614 put_le16(identify_data + 85, (1 << 14) | (1 << 5) | 1);
1615 return true;
1616 case 0x82: /* write cache disable */
4be74634 1617 blk_set_enable_write_cache(s->blk, false);
ee03398c
KW		 1618 identify_data = (uint16_t *)s->identify_data;
1619 put_le16(identify_data + 85, (1 << 14) | 1);
1620 ide_flush_cache(s);
1621 return false;
1622 case 0xcc: /* reverting to power-on defaults enable */
1623 case 0x66: /* reverting to power-on defaults disable */
1624 case 0xaa: /* read look-ahead enable */
1625 case 0x55: /* read look-ahead disable */
1626 case 0x05: /* set advanced power management mode */
1627 case 0x85: /* disable advanced power management mode */
1628 case 0x69: /* NOP */
1629 case 0x67: /* NOP */
1630 case 0x96: /* NOP */
1631 case 0x9a: /* NOP */
1632 case 0x42: /* enable Automatic Acoustic Mode */
1633 case 0xc2: /* disable Automatic Acoustic Mode */
1634 return true;
1635 case 0x03: /* set transfer mode */
1636 {
1637 uint8_t val = s->nsector & 0x07;
1638 identify_data = (uint16_t *)s->identify_data;
1639
1640 switch (s->nsector >> 3) {
1641 case 0x00: /* pio default */
1642 case 0x01: /* pio mode */
1643 put_le16(identify_data + 62, 0x07);
1644 put_le16(identify_data + 63, 0x07);
1645 put_le16(identify_data + 88, 0x3f);
1646 break;
1647 case 0x02: /* sigle word dma mode*/
1648 put_le16(identify_data + 62, 0x07 | (1 << (val + 8)));
1649 put_le16(identify_data + 63, 0x07);
1650 put_le16(identify_data + 88, 0x3f);
1651 break;
1652 case 0x04: /* mdma mode */
1653 put_le16(identify_data + 62, 0x07);
1654 put_le16(identify_data + 63, 0x07 | (1 << (val + 8)));
1655 put_le16(identify_data + 88, 0x3f);
1656 break;
1657 case 0x08: /* udma mode */
1658 put_le16(identify_data + 62, 0x07);
1659 put_le16(identify_data + 63, 0x07);
1660 put_le16(identify_data + 88, 0x3f | (1 << (val + 8)));
1661 break;
1662 default:
1663 goto abort_cmd;
1664 }
1665 return true;
1666 }
1667 }
1668
1669abort_cmd:
1670 ide_abort_command(s);
1671 return true;
1672}
1673
ee425c78
KW		 1674
1675/*** ATAPI commands ***/
1676
1677static bool cmd_identify_packet(IDEState *s, uint8_t cmd)
1678{
1679 ide_atapi_identify(s);
1680 s->status = READY_STAT | SEEK_STAT;
1681 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
1682 ide_set_irq(s->bus);
1683 return false;
1684}
1685
1686static bool cmd_exec_dev_diagnostic(IDEState *s, uint8_t cmd)
1687{
1688 ide_set_signature(s);
1689
1690 if (s->drive_kind == IDE_CD) {
1691 s->status = 0; /* ATAPI spec (v6) section 9.10 defines packet
1692 * devices to return a clear status register
1693 * with READY_STAT *not* set. */
850484a2 1694 s->error = 0x01;
ee425c78
KW		 1695 } else {
1696 s->status = READY_STAT | SEEK_STAT;
1697 /* The bits of the error register are not as usual for this command!
1698 * They are part of the regular output (this is why ERR_STAT isn't set)
1699 * Device 0 passed, Device 1 passed or not present. */
1700 s->error = 0x01;
1701 ide_set_irq(s->bus);
1702 }
1703
1704 return false;
1705}
1706
ee425c78
KW		 1707static bool cmd_packet(IDEState *s, uint8_t cmd)
1708{
1709 /* overlapping commands not supported */
1710 if (s->feature & 0x02) {
1711 ide_abort_command(s);
1712 return true;
1713 }
1714
1715 s->status = READY_STAT | SEEK_STAT;
1716 s->atapi_dma = s->feature & 1;
502356ee
PB		 1717 if (s->atapi_dma) {
1718 s->dma_cmd = IDE_DMA_ATAPI;
1719 }
ee425c78
KW		 1720 s->nsector = 1;
1721 ide_transfer_start(s, s->io_buffer, ATAPI_PACKET_SIZE,
1722 ide_atapi_cmd);
1723 return false;
1724}
1725
6b1dd744
KW		 1726
1727/*** CF-ATA commands ***/
1728
1729static bool cmd_cfa_req_ext_error_code(IDEState *s, uint8_t cmd)
1730{
1731 s->error = 0x09; /* miscellaneous error */
1732 s->status = READY_STAT | SEEK_STAT;
1733 ide_set_irq(s->bus);
1734
1735 return false;
1736}
1737
1738static bool cmd_cfa_erase_sectors(IDEState *s, uint8_t cmd)
1739{
1740 /* WIN_SECURITY_FREEZE_LOCK has the same ID as CFA_WEAR_LEVEL and is
1741 * required for Windows 8 to work with AHCI */
1742
1743 if (cmd == CFA_WEAR_LEVEL) {
1744 s->nsector = 0;
1745 }
1746
1747 if (cmd == CFA_ERASE_SECTORS) {
1748 s->media_changed = 1;
1749 }
1750
1751 return true;
1752}
1753
1754static bool cmd_cfa_translate_sector(IDEState *s, uint8_t cmd)
1755{
1756 s->status = READY_STAT | SEEK_STAT;
1757
1758 memset(s->io_buffer, 0, 0x200);
1759 s->io_buffer[0x00] = s->hcyl; /* Cyl MSB */
1760 s->io_buffer[0x01] = s->lcyl; /* Cyl LSB */
1761 s->io_buffer[0x02] = s->select; /* Head */
1762 s->io_buffer[0x03] = s->sector; /* Sector */
1763 s->io_buffer[0x04] = ide_get_sector(s) >> 16; /* LBA MSB */
1764 s->io_buffer[0x05] = ide_get_sector(s) >> 8; /* LBA */
1765 s->io_buffer[0x06] = ide_get_sector(s) >> 0; /* LBA LSB */
1766 s->io_buffer[0x13] = 0x00; /* Erase flag */
1767 s->io_buffer[0x18] = 0x00; /* Hot count */
1768 s->io_buffer[0x19] = 0x00; /* Hot count */
1769 s->io_buffer[0x1a] = 0x01; /* Hot count */
1770
1771 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1772 ide_set_irq(s->bus);
1773
1774 return false;
1775}
1776
1777static bool cmd_cfa_access_metadata_storage(IDEState *s, uint8_t cmd)
1778{
1779 switch (s->feature) {
1780 case 0x02: /* Inquiry Metadata Storage */
1781 ide_cfata_metadata_inquiry(s);
1782 break;
1783 case 0x03: /* Read Metadata Storage */
1784 ide_cfata_metadata_read(s);
1785 break;
1786 case 0x04: /* Write Metadata Storage */
1787 ide_cfata_metadata_write(s);
1788 break;
1789 default:
1790 ide_abort_command(s);
1791 return true;
1792 }
1793
1794 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1795 s->status = 0x00; /* NOTE: READY is _not_ set */
1796 ide_set_irq(s->bus);
1797
1798 return false;
1799}
1800
1801static bool cmd_ibm_sense_condition(IDEState *s, uint8_t cmd)
1802{
1803 switch (s->feature) {
1804 case 0x01: /* sense temperature in device */
1805 s->nsector = 0x50; /* +20 C */
1806 break;
1807 default:
1808 ide_abort_command(s);
1809 return true;
1810 }
1811
1812 return true;
1813}
1814
ff352677
KW		 1815
1816/*** SMART commands ***/
1817
1818static bool cmd_smart(IDEState *s, uint8_t cmd)
1819{
1820 int n;
1821
1822 if (s->hcyl != 0xc2 || s->lcyl != 0x4f) {
1823 goto abort_cmd;
1824 }
1825
1826 if (!s->smart_enabled && s->feature != SMART_ENABLE) {
1827 goto abort_cmd;
1828 }
1829
1830 switch (s->feature) {
1831 case SMART_DISABLE:
1832 s->smart_enabled = 0;
1833 return true;
1834
1835 case SMART_ENABLE:
1836 s->smart_enabled = 1;
1837 return true;
1838
1839 case SMART_ATTR_AUTOSAVE:
1840 switch (s->sector) {
1841 case 0x00:
1842 s->smart_autosave = 0;
1843 break;
1844 case 0xf1:
1845 s->smart_autosave = 1;
1846 break;
1847 default:
1848 goto abort_cmd;
1849 }
1850 return true;
1851
1852 case SMART_STATUS:
1853 if (!s->smart_errors) {
1854 s->hcyl = 0xc2;
1855 s->lcyl = 0x4f;
1856 } else {
1857 s->hcyl = 0x2c;
1858 s->lcyl = 0xf4;
1859 }
1860 return true;
1861
1862 case SMART_READ_THRESH:
1863 memset(s->io_buffer, 0, 0x200);
1864 s->io_buffer[0] = 0x01; /* smart struct version */
1865
1866 for (n = 0; n < ARRAY_SIZE(smart_attributes); n++) {
1867 s->io_buffer[2 + 0 + (n * 12)] = smart_attributes[n][0];
1868 s->io_buffer[2 + 1 + (n * 12)] = smart_attributes[n][11];
1869 }
1870
1871 /* checksum */
1872 for (n = 0; n < 511; n++) {
1873 s->io_buffer[511] += s->io_buffer[n];
1874 }
1875 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1876
1877 s->status = READY_STAT | SEEK_STAT;
1878 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1879 ide_set_irq(s->bus);
1880 return false;
1881
1882 case SMART_READ_DATA:
1883 memset(s->io_buffer, 0, 0x200);
1884 s->io_buffer[0] = 0x01; /* smart struct version */
1885
1886 for (n = 0; n < ARRAY_SIZE(smart_attributes); n++) {
1887 int i;
1888 for (i = 0; i < 11; i++) {
1889 s->io_buffer[2 + i + (n * 12)] = smart_attributes[n][i];
1890 }
1891 }
1892
1893 s->io_buffer[362] = 0x02 | (s->smart_autosave ? 0x80 : 0x00);
1894 if (s->smart_selftest_count == 0) {
1895 s->io_buffer[363] = 0;
1896 } else {
1897 s->io_buffer[363] =
1898 s->smart_selftest_data[3 +
1899 (s->smart_selftest_count - 1) *
1900 24];
1901 }
1902 s->io_buffer[364] = 0x20;
1903 s->io_buffer[365] = 0x01;
1904 /* offline data collection capacity: execute + self-test*/
1905 s->io_buffer[367] = (1 << 4 | 1 << 3 | 1);
1906 s->io_buffer[368] = 0x03; /* smart capability (1) */
1907 s->io_buffer[369] = 0x00; /* smart capability (2) */
1908 s->io_buffer[370] = 0x01; /* error logging supported */
1909 s->io_buffer[372] = 0x02; /* minutes for poll short test */
1910 s->io_buffer[373] = 0x36; /* minutes for poll ext test */
1911 s->io_buffer[374] = 0x01; /* minutes for poll conveyance */
1912
1913 for (n = 0; n < 511; n++) {
1914 s->io_buffer[511] += s->io_buffer[n];
1915 }
1916 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1917
1918 s->status = READY_STAT | SEEK_STAT;
1919 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1920 ide_set_irq(s->bus);
1921 return false;
1922
1923 case SMART_READ_LOG:
1924 switch (s->sector) {
1925 case 0x01: /* summary smart error log */
1926 memset(s->io_buffer, 0, 0x200);
1927 s->io_buffer[0] = 0x01;
1928 s->io_buffer[1] = 0x00; /* no error entries */
1929 s->io_buffer[452] = s->smart_errors & 0xff;
1930 s->io_buffer[453] = (s->smart_errors & 0xff00) >> 8;
1931
1932 for (n = 0; n < 511; n++) {
1933 s->io_buffer[511] += s->io_buffer[n];
1934 }
1935 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1936 break;
1937 case 0x06: /* smart self test log */
1938 memset(s->io_buffer, 0, 0x200);
1939 s->io_buffer[0] = 0x01;
1940 if (s->smart_selftest_count == 0) {
1941 s->io_buffer[508] = 0;
1942 } else {
1943 s->io_buffer[508] = s->smart_selftest_count;
1944 for (n = 2; n < 506; n++) {
1945 s->io_buffer[n] = s->smart_selftest_data[n];
1946 }
1947 }
1948
1949 for (n = 0; n < 511; n++) {
1950 s->io_buffer[511] += s->io_buffer[n];
1951 }
1952 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1953 break;
1954 default:
1955 goto abort_cmd;
1956 }
1957 s->status = READY_STAT | SEEK_STAT;
1958 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1959 ide_set_irq(s->bus);
1960 return false;
1961
1962 case SMART_EXECUTE_OFFLINE:
1963 switch (s->sector) {
1964 case 0: /* off-line routine */
1965 case 1: /* short self test */
1966 case 2: /* extended self test */
1967 s->smart_selftest_count++;
1968 if (s->smart_selftest_count > 21) {
940973ae 1969 s->smart_selftest_count = 1;
ff352677
KW		 1970 }
1971 n = 2 + (s->smart_selftest_count - 1) * 24;
1972 s->smart_selftest_data[n] = s->sector;
1973 s->smart_selftest_data[n + 1] = 0x00; /* OK and finished */
1974 s->smart_selftest_data[n + 2] = 0x34; /* hour count lsb */
1975 s->smart_selftest_data[n + 3] = 0x12; /* hour count msb */
1976 break;
1977 default:
1978 goto abort_cmd;
1979 }
1980 return true;
1981 }
1982
1983abort_cmd:
1984 ide_abort_command(s);
1985 return true;
1986}
1987
844505b1
MA		 1988#define HD_OK (1u << IDE_HD)
1989#define CD_OK (1u << IDE_CD)
1990#define CFA_OK (1u << IDE_CFATA)
1991#define HD_CFA_OK (HD_OK | CFA_OK)
1992#define ALL_OK (HD_OK | CD_OK | CFA_OK)
1993
a0436e92
KW		 1994/* Set the Disk Seek Completed status bit during completion */
1995#define SET_DSC (1u << 8)
1996
844505b1 1997/* See ACS-2 T13/2015-D Table B.2 Command codes */
a0436e92
KW		 1998static const struct {
1999 /* Returns true if the completion code should be run */
2000 bool (*handler)(IDEState *s, uint8_t cmd);
2001 int flags;
2002} ide_cmd_table[0x100] = {
844505b1 2003 /* NOP not implemented, mandatory for CD */
6b1dd744 2004 [CFA_REQ_EXT_ERROR_CODE] = { cmd_cfa_req_ext_error_code, CFA_OK },
d9033e1d 2005 [WIN_DSM] = { cmd_data_set_management, HD_CFA_OK },
ee425c78 2006 [WIN_DEVICE_RESET] = { cmd_device_reset, CD_OK },
b300337e 2007 [WIN_RECAL] = { cmd_nop, HD_CFA_OK | SET_DSC},
0e6498ed 2008 [WIN_READ] = { cmd_read_pio, ALL_OK },
d9033e1d 2009 [WIN_READ_ONCE] = { cmd_read_pio, HD_CFA_OK },
0e6498ed 2010 [WIN_READ_EXT] = { cmd_read_pio, HD_CFA_OK },
92a6a6f6 2011 [WIN_READDMA_EXT] = { cmd_read_dma, HD_CFA_OK },
63a82e6a 2012 [WIN_READ_NATIVE_MAX_EXT] = { cmd_read_native_max, HD_CFA_OK | SET_DSC },
adf3a2c4 2013 [WIN_MULTREAD_EXT] = { cmd_read_multiple, HD_CFA_OK },
0e6498ed
KW		 2014 [WIN_WRITE] = { cmd_write_pio, HD_CFA_OK },
2015 [WIN_WRITE_ONCE] = { cmd_write_pio, HD_CFA_OK },
2016 [WIN_WRITE_EXT] = { cmd_write_pio, HD_CFA_OK },
92a6a6f6 2017 [WIN_WRITEDMA_EXT] = { cmd_write_dma, HD_CFA_OK },
0e6498ed 2018 [CFA_WRITE_SECT_WO_ERASE] = { cmd_write_pio, CFA_OK },
adf3a2c4 2019 [WIN_MULTWRITE_EXT] = { cmd_write_multiple, HD_CFA_OK },
0e6498ed 2020 [WIN_WRITE_VERIFY] = { cmd_write_pio, HD_CFA_OK },
413860cf
KW		 2021 [WIN_VERIFY] = { cmd_verify, HD_CFA_OK | SET_DSC },
2022 [WIN_VERIFY_ONCE] = { cmd_verify, HD_CFA_OK | SET_DSC },
2023 [WIN_VERIFY_EXT] = { cmd_verify, HD_CFA_OK | SET_DSC },
61fdda37 2024 [WIN_SEEK] = { cmd_seek, HD_CFA_OK | SET_DSC },
6b1dd744 2025 [CFA_TRANSLATE_SECTOR] = { cmd_cfa_translate_sector, CFA_OK },
ee425c78 2026 [WIN_DIAGNOSE] = { cmd_exec_dev_diagnostic, ALL_OK },
b300337e 2027 [WIN_SPECIFY] = { cmd_nop, HD_CFA_OK | SET_DSC },
d9033e1d
JS		 2028 [WIN_STANDBYNOW2] = { cmd_nop, HD_CFA_OK },
2029 [WIN_IDLEIMMEDIATE2] = { cmd_nop, HD_CFA_OK },
2030 [WIN_STANDBY2] = { cmd_nop, HD_CFA_OK },
2031 [WIN_SETIDLE2] = { cmd_nop, HD_CFA_OK },
2032 [WIN_CHECKPOWERMODE2] = { cmd_check_power_mode, HD_CFA_OK | SET_DSC },
2033 [WIN_SLEEPNOW2] = { cmd_nop, HD_CFA_OK },
ee425c78
KW		 2034 [WIN_PACKETCMD] = { cmd_packet, CD_OK },
2035 [WIN_PIDENTIFY] = { cmd_identify_packet, CD_OK },
ff352677 2036 [WIN_SMART] = { cmd_smart, HD_CFA_OK | SET_DSC },
6b1dd744
KW		 2037 [CFA_ACCESS_METADATA_STORAGE] = { cmd_cfa_access_metadata_storage, CFA_OK },
2038 [CFA_ERASE_SECTORS] = { cmd_cfa_erase_sectors, CFA_OK | SET_DSC },
adf3a2c4
KW		 2039 [WIN_MULTREAD] = { cmd_read_multiple, HD_CFA_OK },
2040 [WIN_MULTWRITE] = { cmd_write_multiple, HD_CFA_OK },
2041 [WIN_SETMULT] = { cmd_set_multiple_mode, HD_CFA_OK | SET_DSC },
92a6a6f6
KW		 2042 [WIN_READDMA] = { cmd_read_dma, HD_CFA_OK },
2043 [WIN_READDMA_ONCE] = { cmd_read_dma, HD_CFA_OK },
2044 [WIN_WRITEDMA] = { cmd_write_dma, HD_CFA_OK },
2045 [WIN_WRITEDMA_ONCE] = { cmd_write_dma, HD_CFA_OK },
adf3a2c4 2046 [CFA_WRITE_MULTI_WO_ERASE] = { cmd_write_multiple, CFA_OK },
d9033e1d
JS		 2047 [WIN_STANDBYNOW1] = { cmd_nop, HD_CFA_OK },
2048 [WIN_IDLEIMMEDIATE] = { cmd_nop, HD_CFA_OK },
2049 [WIN_STANDBY] = { cmd_nop, HD_CFA_OK },
2050 [WIN_SETIDLE1] = { cmd_nop, HD_CFA_OK },
2051 [WIN_CHECKPOWERMODE1] = { cmd_check_power_mode, HD_CFA_OK | SET_DSC },
2052 [WIN_SLEEPNOW1] = { cmd_nop, HD_CFA_OK },
9afce429
KW		 2053 [WIN_FLUSH_CACHE] = { cmd_flush_cache, ALL_OK },
2054 [WIN_FLUSH_CACHE_EXT] = { cmd_flush_cache, HD_CFA_OK },
1c66869a 2055 [WIN_IDENTIFY] = { cmd_identify, ALL_OK },
ee03398c 2056 [WIN_SETFEATURES] = { cmd_set_features, ALL_OK | SET_DSC },
6b1dd744
KW		 2057 [IBM_SENSE_CONDITION] = { cmd_ibm_sense_condition, CFA_OK | SET_DSC },
2058 [CFA_WEAR_LEVEL] = { cmd_cfa_erase_sectors, HD_CFA_OK | SET_DSC },
d9033e1d 2059 [WIN_READ_NATIVE_MAX] = { cmd_read_native_max, HD_CFA_OK | SET_DSC },
844505b1
MA		 2060};
2061
2062static bool ide_cmd_permitted(IDEState *s, uint32_t cmd)
2063{
2064 return cmd < ARRAY_SIZE(ide_cmd_table)
a0436e92 2065 && (ide_cmd_table[cmd].flags & (1u << s->drive_kind));
844505b1 2066}
7cff87ff
AG		 2067
2068void ide_exec_cmd(IDEBus *bus, uint32_t val)
2069{
2070 IDEState *s;
dfe1ea8f 2071 bool complete;
7cff87ff 2072
6ef2ba5e 2073 s = idebus_active_if(bus);
3eee2611
JS		 2074 trace_ide_exec_cmd(bus, s, val);
2075
66a0a2cb 2076 /* ignore commands to non existent slave */
4be74634 2077 if (s != bus->ifs && !s->blk) {
6ef2ba5e 2078 return;
4be74634 2079 }
c2ff060f 2080
266e7781
JS		 2081 /* Only RESET is allowed while BSY and/or DRQ are set,
2082 * and only to ATAPI devices. */
2083 if (s->status & (BUSY_STAT|DRQ_STAT)) {
2084 if (val != WIN_DEVICE_RESET || s->drive_kind != IDE_CD) {
2085 return;
2086 }
2087 }
fcdd25ab 2088
844505b1 2089 if (!ide_cmd_permitted(s, val)) {
dfe1ea8f
KW		 2090 ide_abort_command(s);
2091 ide_set_irq(s->bus);
2092 return;
844505b1
MA		 2093 }
2094
dfe1ea8f
KW		 2095 s->status = READY_STAT | BUSY_STAT;
2096 s->error = 0;
36334faf 2097 s->io_buffer_offset = 0;
a0436e92 2098
dfe1ea8f
KW		 2099 complete = ide_cmd_table[val].handler(s, val);
2100 if (complete) {
2101 s->status &= ~BUSY_STAT;
2102 assert(!!s->error == !!(s->status & ERR_STAT));
a0436e92 2103
dfe1ea8f
KW		 2104 if ((ide_cmd_table[val].flags & SET_DSC) && !s->error) {
2105 s->status |= SEEK_STAT;
a0436e92
KW		 2106 }
2107
c7e73adb 2108 ide_cmd_done(s);
6ef2ba5e 2109 ide_set_irq(s->bus);
6ef2ba5e 2110 }
5391d806
FB		 2111}
2112
335ca2f2
JS		 2113/* IOport [R]ead [R]egisters */
2114enum ATA_IOPORT_RR {
2115 ATA_IOPORT_RR_DATA = 0,
2116 ATA_IOPORT_RR_ERROR = 1,
2117 ATA_IOPORT_RR_SECTOR_COUNT = 2,
2118 ATA_IOPORT_RR_SECTOR_NUMBER = 3,
2119 ATA_IOPORT_RR_CYLINDER_LOW = 4,
2120 ATA_IOPORT_RR_CYLINDER_HIGH = 5,
2121 ATA_IOPORT_RR_DEVICE_HEAD = 6,
2122 ATA_IOPORT_RR_STATUS = 7,
2123 ATA_IOPORT_RR_NUM_REGISTERS,
2124};
2125
2126const char *ATA_IOPORT_RR_lookup[ATA_IOPORT_RR_NUM_REGISTERS] = {
2127 [ATA_IOPORT_RR_DATA] = "Data",
2128 [ATA_IOPORT_RR_ERROR] = "Error",
2129 [ATA_IOPORT_RR_SECTOR_COUNT] = "Sector Count",
2130 [ATA_IOPORT_RR_SECTOR_NUMBER] = "Sector Number",
2131 [ATA_IOPORT_RR_CYLINDER_LOW] = "Cylinder Low",
2132 [ATA_IOPORT_RR_CYLINDER_HIGH] = "Cylinder High",
2133 [ATA_IOPORT_RR_DEVICE_HEAD] = "Device/Head",
2134 [ATA_IOPORT_RR_STATUS] = "Status"
2135};
2136
3eee2611 2137uint32_t ide_ioport_read(void *opaque, uint32_t addr)
5391d806 2138{
bcbdc4d3
GH		 2139 IDEBus *bus = opaque;
2140 IDEState *s = idebus_active_if(bus);
3eee2611 2141 uint32_t reg_num;
c2ff060f 2142 int ret, hob;
5391d806 2143
3eee2611 2144 reg_num = addr & 7;
c2ff060f
FB		 2145 /* FIXME: HOB readback uses bit 7, but it's always set right now */
2146 //hob = s->select & (1 << 7);
2147 hob = 0;
3eee2611 2148 switch (reg_num) {
335ca2f2 2149 case ATA_IOPORT_RR_DATA:
5391d806
FB		 2150 ret = 0xff;
2151 break;
335ca2f2 2152 case ATA_IOPORT_RR_ERROR:
4be74634
MA		 2153 if ((!bus->ifs[0].blk && !bus->ifs[1].blk) ||
2154 (s != bus->ifs && !s->blk)) {
c45c3d00 2155 ret = 0;
4be74634 2156 } else if (!hob) {
c45c3d00 2157 ret = s->error;
4be74634 2158 } else {
7d37435b 2159 ret = s->hob_feature;
4be74634 2160 }
5391d806 2161 break;
335ca2f2 2162 case ATA_IOPORT_RR_SECTOR_COUNT:
4be74634 2163 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
c45c3d00 2164 ret = 0;
4be74634 2165 } else if (!hob) {
c45c3d00 2166 ret = s->nsector & 0xff;
4be74634 2167 } else {
7d37435b 2168 ret = s->hob_nsector;
4be74634 2169 }
5391d806 2170 break;
335ca2f2 2171 case ATA_IOPORT_RR_SECTOR_NUMBER:
4be74634 2172 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
c45c3d00 2173 ret = 0;
4be74634 2174 } else if (!hob) {
c45c3d00 2175 ret = s->sector;
4be74634 2176 } else {
7d37435b 2177 ret = s->hob_sector;
4be74634 2178 }
5391d806 2179 break;
335ca2f2 2180 case ATA_IOPORT_RR_CYLINDER_LOW:
4be74634 2181 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
c45c3d00 2182 ret = 0;
4be74634 2183 } else if (!hob) {
c45c3d00 2184 ret = s->lcyl;
4be74634 2185 } else {
7d37435b 2186 ret = s->hob_lcyl;
4be74634 2187 }
5391d806 2188 break;
335ca2f2 2189 case ATA_IOPORT_RR_CYLINDER_HIGH:
4be74634 2190 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
c45c3d00 2191 ret = 0;
4be74634 2192 } else if (!hob) {
c45c3d00 2193 ret = s->hcyl;
4be74634 2194 } else {
7d37435b 2195 ret = s->hob_hcyl;
4be74634 2196 }
5391d806 2197 break;
335ca2f2 2198 case ATA_IOPORT_RR_DEVICE_HEAD:
4be74634 2199 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
c45c3d00 2200 ret = 0;
4be74634 2201 } else {
7ae98627 2202 ret = s->select;
4be74634 2203 }
5391d806
FB		 2204 break;
2205 default:
335ca2f2 2206 case ATA_IOPORT_RR_STATUS:
4be74634
MA		 2207 if ((!bus->ifs[0].blk && !bus->ifs[1].blk) ||
2208 (s != bus->ifs && !s->blk)) {
c45c3d00 2209 ret = 0;
4be74634 2210 } else {
c45c3d00 2211 ret = s->status;
4be74634 2212 }
9cdd03a7 2213 qemu_irq_lower(bus->irq);
5391d806
FB		 2214 break;
2215 }
3eee2611 2216
335ca2f2 2217 trace_ide_ioport_read(addr, ATA_IOPORT_RR_lookup[reg_num], ret, bus, s);
5391d806
FB		 2218 return ret;
2219}
2220
356721ae 2221uint32_t ide_status_read(void *opaque, uint32_t addr)
5391d806 2222{
bcbdc4d3
GH		 2223 IDEBus *bus = opaque;
2224 IDEState *s = idebus_active_if(bus);
5391d806 2225 int ret;
7ae98627 2226
4be74634
MA		 2227 if ((!bus->ifs[0].blk && !bus->ifs[1].blk) ||
2228 (s != bus->ifs && !s->blk)) {
7ae98627 2229 ret = 0;
4be74634 2230 } else {
7ae98627 2231 ret = s->status;
4be74634 2232 }
3eee2611
JS		 2233
2234 trace_ide_status_read(addr, ret, bus, s);
5391d806
FB		 2235 return ret;
2236}
2237
356721ae 2238void ide_cmd_write(void *opaque, uint32_t addr, uint32_t val)
5391d806 2239{
bcbdc4d3 2240 IDEBus *bus = opaque;
5391d806
FB		 2241 IDEState *s;
2242 int i;
2243
3eee2611
JS		 2244 trace_ide_cmd_write(addr, val, bus);
2245
5391d806 2246 /* common for both drives */
9cdd03a7 2247 if (!(bus->cmd & IDE_CMD_RESET) &&
5391d806
FB		 2248 (val & IDE_CMD_RESET)) {
2249 /* reset low to high */
2250 for(i = 0;i < 2; i++) {
bcbdc4d3 2251 s = &bus->ifs[i];
5391d806
FB		 2252 s->status = BUSY_STAT | SEEK_STAT;
2253 s->error = 0x01;
2254 }
9cdd03a7 2255 } else if ((bus->cmd & IDE_CMD_RESET) &&
5391d806
FB		 2256 !(val & IDE_CMD_RESET)) {
2257 /* high to low */
2258 for(i = 0;i < 2; i++) {
bcbdc4d3 2259 s = &bus->ifs[i];
cd8722bb 2260 if (s->drive_kind == IDE_CD)
6b136f9e
FB		 2261 s->status = 0x00; /* NOTE: READY is _not_ set */
2262 else
56bf1d37 2263 s->status = READY_STAT | SEEK_STAT;
5391d806
FB		 2264 ide_set_signature(s);
2265 }
2266 }
2267
9cdd03a7 2268 bus->cmd = val;
5391d806
FB		 2269}
2270
40c4ed3f
KW		 2271/*
2272 * Returns true if the running PIO transfer is a PIO out (i.e. data is
2273 * transferred from the device to the guest), false if it's a PIO in
2274 */
2275static bool ide_is_pio_out(IDEState *s)
2276{
2277 if (s->end_transfer_func == ide_sector_write ||
2278 s->end_transfer_func == ide_atapi_cmd) {
2279 return false;
2280 } else if (s->end_transfer_func == ide_sector_read ||
2281 s->end_transfer_func == ide_transfer_stop ||
2282 s->end_transfer_func == ide_atapi_cmd_reply_end ||
2283 s->end_transfer_func == ide_dummy_transfer_stop) {
2284 return true;
2285 }
2286
2287 abort();
2288}
2289
356721ae 2290void ide_data_writew(void *opaque, uint32_t addr, uint32_t val)
5391d806 2291{
bcbdc4d3
GH		 2292 IDEBus *bus = opaque;
2293 IDEState *s = idebus_active_if(bus);
5391d806
FB		 2294 uint8_t *p;
2295
1787efc3
JS		 2296 trace_ide_data_writew(addr, val, bus, s);
2297
40c4ed3f
KW		 2298 /* PIO data access allowed only when DRQ bit is set. The result of a write
2299 * during PIO out is indeterminate, just ignore it. */
2300 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
fcdd25ab 2301 return;
40c4ed3f 2302 }
fcdd25ab 2303
5391d806 2304 p = s->data_ptr;
d2ff8585
KW		 2305 if (p + 2 > s->data_end) {
2306 return;
2307 }
2308
0c4ad8dc 2309 *(uint16_t *)p = le16_to_cpu(val);
5391d806
FB		 2310 p += 2;
2311 s->data_ptr = p;
cb72cba8
KW		 2312 if (p >= s->data_end) {
2313 s->status &= ~DRQ_STAT;
5391d806 2314 s->end_transfer_func(s);
cb72cba8 2315 }
5391d806
FB		 2316}
2317
356721ae 2318uint32_t ide_data_readw(void *opaque, uint32_t addr)
5391d806 2319{
bcbdc4d3
GH		 2320 IDEBus *bus = opaque;
2321 IDEState *s = idebus_active_if(bus);
5391d806
FB		 2322 uint8_t *p;
2323 int ret;
fcdd25ab 2324
40c4ed3f
KW		 2325 /* PIO data access allowed only when DRQ bit is set. The result of a read
2326 * during PIO in is indeterminate, return 0 and don't move forward. */
2327 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
fcdd25ab 2328 return 0;
40c4ed3f 2329 }
fcdd25ab 2330
5391d806 2331 p = s->data_ptr;
d2ff8585
KW		 2332 if (p + 2 > s->data_end) {
2333 return 0;
2334 }
2335
0c4ad8dc 2336 ret = cpu_to_le16(*(uint16_t *)p);
5391d806
FB		 2337 p += 2;
2338 s->data_ptr = p;
cb72cba8
KW		 2339 if (p >= s->data_end) {
2340 s->status &= ~DRQ_STAT;
5391d806 2341 s->end_transfer_func(s);
cb72cba8 2342 }
1787efc3
JS		 2343
2344 trace_ide_data_readw(addr, ret, bus, s);
5391d806
FB		 2345 return ret;
2346}
2347
356721ae 2348void ide_data_writel(void *opaque, uint32_t addr, uint32_t val)
5391d806 2349{
bcbdc4d3
GH		 2350 IDEBus *bus = opaque;
2351 IDEState *s = idebus_active_if(bus);
5391d806
FB		 2352 uint8_t *p;
2353
1787efc3
JS		 2354 trace_ide_data_writel(addr, val, bus, s);
2355
40c4ed3f
KW		 2356 /* PIO data access allowed only when DRQ bit is set. The result of a write
2357 * during PIO out is indeterminate, just ignore it. */
2358 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
fcdd25ab 2359 return;
40c4ed3f 2360 }
fcdd25ab 2361
5391d806 2362 p = s->data_ptr;
d2ff8585
KW		 2363 if (p + 4 > s->data_end) {
2364 return;
2365 }
2366
0c4ad8dc 2367 *(uint32_t *)p = le32_to_cpu(val);
5391d806
FB		 2368 p += 4;
2369 s->data_ptr = p;
cb72cba8
KW		 2370 if (p >= s->data_end) {
2371 s->status &= ~DRQ_STAT;
5391d806 2372 s->end_transfer_func(s);
cb72cba8 2373 }
5391d806
FB		 2374}
2375
356721ae 2376uint32_t ide_data_readl(void *opaque, uint32_t addr)
5391d806 2377{
bcbdc4d3
GH		 2378 IDEBus *bus = opaque;
2379 IDEState *s = idebus_active_if(bus);
5391d806
FB		 2380 uint8_t *p;
2381 int ret;
3b46e624 2382
40c4ed3f
KW		 2383 /* PIO data access allowed only when DRQ bit is set. The result of a read
2384 * during PIO in is indeterminate, return 0 and don't move forward. */
2385 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
1787efc3
JS		 2386 ret = 0;
2387 goto out;
40c4ed3f 2388 }
fcdd25ab 2389
5391d806 2390 p = s->data_ptr;
d2ff8585
KW		 2391 if (p + 4 > s->data_end) {
2392 return 0;
2393 }
2394
0c4ad8dc 2395 ret = cpu_to_le32(*(uint32_t *)p);
5391d806
FB		 2396 p += 4;
2397 s->data_ptr = p;
cb72cba8
KW		 2398 if (p >= s->data_end) {
2399 s->status &= ~DRQ_STAT;
5391d806 2400 s->end_transfer_func(s);
cb72cba8 2401 }
1787efc3
JS		 2402
2403out:
2404 trace_ide_data_readl(addr, ret, bus, s);
5391d806
FB		 2405 return ret;
2406}
2407
a7dfe172
FB		 2408static void ide_dummy_transfer_stop(IDEState *s)
2409{
2410 s->data_ptr = s->io_buffer;
2411 s->data_end = s->io_buffer;
2412 s->io_buffer[0] = 0xff;
2413 s->io_buffer[1] = 0xff;
2414 s->io_buffer[2] = 0xff;
2415 s->io_buffer[3] = 0xff;
2416}
2417
4a643563
BS		 2418void ide_bus_reset(IDEBus *bus)
2419{
2420 bus->unit = 0;
2421 bus->cmd = 0;
2422 ide_reset(&bus->ifs[0]);
2423 ide_reset(&bus->ifs[1]);
2424 ide_clear_hob(bus);
40a6238a
AG		 2425
2426 /* pending async DMA */
2427 if (bus->dma->aiocb) {
0e168d35 2428 trace_ide_bus_reset_aio();
4be74634 2429 blk_aio_cancel(bus->dma->aiocb);
40a6238a
AG		 2430 bus->dma->aiocb = NULL;
2431 }
2432
2433 /* reset dma provider too */
1374bec0
PB		 2434 if (bus->dma->ops->reset) {
2435 bus->dma->ops->reset(bus->dma);
2436 }
4a643563
BS		 2437}
2438
e4def80b
MA		 2439static bool ide_cd_is_tray_open(void *opaque)
2440{
2441 return ((IDEState *)opaque)->tray_open;
2442}
2443
f107639a
MA		 2444static bool ide_cd_is_medium_locked(void *opaque)
2445{
2446 return ((IDEState *)opaque)->tray_locked;
2447}
2448
01ce352e
JS		 2449static void ide_resize_cb(void *opaque)
2450{
2451 IDEState *s = opaque;
2452 uint64_t nb_sectors;
2453
2454 if (!s->identify_set) {
2455 return;
2456 }
2457
4be74634 2458 blk_get_geometry(s->blk, &nb_sectors);
01ce352e
JS		 2459 s->nb_sectors = nb_sectors;
2460
2461 /* Update the identify data buffer. */
2462 if (s->drive_kind == IDE_CFATA) {
2463 ide_cfata_identify_size(s);
2464 } else {
2465 /* IDE_CD uses a different set of callbacks entirely. */
2466 assert(s->drive_kind != IDE_CD);
2467 ide_identify_size(s);
2468 }
2469}
2470
0e49de52 2471static const BlockDevOps ide_cd_block_ops = {
145feb17 2472 .change_media_cb = ide_cd_change_cb,
2df0a3a3 2473 .eject_request_cb = ide_cd_eject_request_cb,
e4def80b 2474 .is_tray_open = ide_cd_is_tray_open,
f107639a 2475 .is_medium_locked = ide_cd_is_medium_locked,
0e49de52
MA		 2476};
2477
01ce352e
JS		 2478static const BlockDevOps ide_hd_block_ops = {
2479 .resize_cb = ide_resize_cb,
2480};
2481
4be74634 2482int ide_init_drive(IDEState *s, BlockBackend *blk, IDEDriveKind kind,
95ebda85 2483 const char *version, const char *serial, const char *model,
ba801960
MA		 2484 uint64_t wwn,
2485 uint32_t cylinders, uint32_t heads, uint32_t secs,
794939e8 2486 int chs_trans, Error **errp)
88804180 2487{
88804180
GH		 2488 uint64_t nb_sectors;
2489
4be74634 2490 s->blk = blk;
1f56e32a
MA		 2491 s->drive_kind = kind;
2492
4be74634 2493 blk_get_geometry(blk, &nb_sectors);
870111c8
MA		 2494 s->cylinders = cylinders;
2495 s->heads = heads;
2496 s->sectors = secs;
ba801960 2497 s->chs_trans = chs_trans;
870111c8 2498 s->nb_sectors = nb_sectors;
95ebda85 2499 s->wwn = wwn;
870111c8
MA		 2500 /* The SMART values should be preserved across power cycles
2501 but they aren't. */
2502 s->smart_enabled = 1;
2503 s->smart_autosave = 1;
2504 s->smart_errors = 0;
2505 s->smart_selftest_count = 0;
1f56e32a 2506 if (kind == IDE_CD) {
4be74634
MA		 2507 blk_set_dev_ops(blk, &ide_cd_block_ops, s);
2508 blk_set_guest_block_size(blk, 2048);
7aa9c811 2509 } else {
4be74634 2510 if (!blk_is_inserted(s->blk)) {
794939e8 2511 error_setg(errp, "Device needs media, but drive is empty");
98f28ad7
MA		 2512 return -1;
2513 }
4be74634 2514 if (blk_is_read_only(blk)) {
794939e8 2515 error_setg(errp, "Can't use a read-only drive");
7aa9c811
MA		 2516 return -1;
2517 }
4be74634 2518 blk_set_dev_ops(blk, &ide_hd_block_ops, s);
88804180 2519 }
f8b6cc00 2520 if (serial) {
aa2c91bd 2521 pstrcpy(s->drive_serial_str, sizeof(s->drive_serial_str), serial);
6ced55a5 2522 } else {
88804180
GH		 2523 snprintf(s->drive_serial_str, sizeof(s->drive_serial_str),
2524 "QM%05d", s->drive_serial);
870111c8 2525 }
27e0c9a1
FB		 2526 if (model) {
2527 pstrcpy(s->drive_model_str, sizeof(s->drive_model_str), model);
2528 } else {
2529 switch (kind) {
2530 case IDE_CD:
2531 strcpy(s->drive_model_str, "QEMU DVD-ROM");
2532 break;
2533 case IDE_CFATA:
2534 strcpy(s->drive_model_str, "QEMU MICRODRIVE");
2535 break;
2536 default:
2537 strcpy(s->drive_model_str, "QEMU HARDDISK");
2538 break;
2539 }
2540 }
2541
47c06340
GH		 2542 if (version) {
2543 pstrcpy(s->version, sizeof(s->version), version);
2544 } else {
35c2c8dc 2545 pstrcpy(s->version, sizeof(s->version), qemu_hw_version());
47c06340 2546 }
40a6238a 2547
88804180 2548 ide_reset(s);
4be74634 2549 blk_iostatus_enable(blk);
c4d74df7 2550 return 0;
88804180
GH		 2551}
2552
57234ee4 2553static void ide_init1(IDEBus *bus, int unit)
d459da0e
MA		 2554{
2555 static int drive_serial = 1;
2556 IDEState *s = &bus->ifs[unit];
2557
2558 s->bus = bus;
2559 s->unit = unit;
2560 s->drive_serial = drive_serial++;
1b2adf28 2561 /* we need at least 2k alignment for accessing CDROMs using O_DIRECT */
50641c5c 2562 s->io_buffer_total_len = IDE_DMA_BUF_SECTORS*512 + 4;
c925400b
KW		 2563 s->io_buffer = qemu_memalign(2048, s->io_buffer_total_len);
2564 memset(s->io_buffer, 0, s->io_buffer_total_len);
2565
4be74634 2566 s->smart_selftest_data = blk_blockalign(s->blk, 512);
c925400b
KW		 2567 memset(s->smart_selftest_data, 0, 512);
2568
bc72ad67 2569 s->sector_write_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
d459da0e 2570 ide_sector_write_timer_cb, s);
57234ee4
MA		 2571}
2572
ae0cebd7 2573static int ide_nop_int(const IDEDMA *dma, bool is_write)
40a6238a
AG		 2574{
2575 return 0;
2576}
2577
ae0cebd7 2578static void ide_nop(const IDEDMA *dma)
9898586d
PB		 2579{
2580}
2581
ae0cebd7 2582static int32_t ide_nop_int32(const IDEDMA *dma, int32_t l)
3251bdcf
JS		 2583{
2584 return 0;
2585}
2586
40a6238a 2587static const IDEDMAOps ide_dma_nop_ops = {
3251bdcf 2588 .prepare_buf = ide_nop_int32,
9898586d 2589 .restart_dma = ide_nop,
40a6238a 2590 .rw_buf = ide_nop_int,
40a6238a
AG		 2591};
2592
9898586d
PB		 2593static void ide_restart_dma(IDEState *s, enum ide_dma_cmd dma_cmd)
2594{
a96cb236 2595 s->unit = s->bus->retry_unit;
dc5d0af4
PB		 2596 ide_set_sector(s, s->bus->retry_sector_num);
2597 s->nsector = s->bus->retry_nsector;
9898586d 2598 s->bus->dma->ops->restart_dma(s->bus->dma);
9898586d
PB		 2599 s->io_buffer_size = 0;
2600 s->dma_cmd = dma_cmd;
2601 ide_start_dma(s, ide_dma_cb);
2602}
2603
2604static void ide_restart_bh(void *opaque)
2605{
2606 IDEBus *bus = opaque;
2607 IDEState *s;
2608 bool is_read;
2609 int error_status;
2610
2611 qemu_bh_delete(bus->bh);
2612 bus->bh = NULL;
2613
2614 error_status = bus->error_status;
2615 if (bus->error_status == 0) {
2616 return;
2617 }
2618
2619 s = idebus_active_if(bus);
2620 is_read = (bus->error_status & IDE_RETRY_READ) != 0;
2621
2622 /* The error status must be cleared before resubmitting the request: The
2623 * request may fail again, and this case can only be distinguished if the
2624 * called function can set a new error status. */
2625 bus->error_status = 0;
2626
7c03a691
JS		 2627 /* The HBA has generically asked to be kicked on retry */
2628 if (error_status & IDE_RETRY_HBA) {
2629 if (s->bus->dma->ops->restart) {
2630 s->bus->dma->ops->restart(s->bus->dma);
2631 }
502356ee 2632 } else if (IS_IDE_RETRY_DMA(error_status)) {
9898586d
PB		 2633 if (error_status & IDE_RETRY_TRIM) {
2634 ide_restart_dma(s, IDE_DMA_TRIM);
2635 } else {
2636 ide_restart_dma(s, is_read ? IDE_DMA_READ : IDE_DMA_WRITE);
2637 }
502356ee 2638 } else if (IS_IDE_RETRY_PIO(error_status)) {
9898586d
PB		 2639 if (is_read) {
2640 ide_sector_read(s);
2641 } else {
2642 ide_sector_write(s);
2643 }
2644 } else if (error_status & IDE_RETRY_FLUSH) {
2645 ide_flush_cache(s);
502356ee
PB		 2646 } else if (IS_IDE_RETRY_ATAPI(error_status)) {
2647 assert(s->end_transfer_func == ide_atapi_cmd);
2648 ide_atapi_dma_restart(s);
9898586d 2649 } else {
502356ee 2650 abort();
9898586d
PB		 2651 }
2652}
2653
2654static void ide_restart_cb(void *opaque, int running, RunState state)
2655{
2656 IDEBus *bus = opaque;
2657
2658 if (!running)
2659 return;
2660
2661 if (!bus->bh) {
2662 bus->bh = qemu_bh_new(ide_restart_bh, bus);
2663 qemu_bh_schedule(bus->bh);
2664 }
2665}
2666
f878c916
PB		 2667void ide_register_restart_cb(IDEBus *bus)
2668{
9898586d 2669 if (bus->dma->ops->restart_dma) {
ca44141d 2670 bus->vmstate = qemu_add_vm_change_state_handler(ide_restart_cb, bus);
9898586d 2671 }
f878c916
PB		 2672}
2673
40a6238a
AG		 2674static IDEDMA ide_dma_nop = {
2675 .ops = &ide_dma_nop_ops,
2676 .aiocb = NULL,
2677};
2678
57234ee4
MA		 2679void ide_init2(IDEBus *bus, qemu_irq irq)
2680{
2681 int i;
2682
2683 for(i = 0; i < 2; i++) {
2684 ide_init1(bus, i);
2685 ide_reset(&bus->ifs[i]);
870111c8 2686 }
57234ee4 2687 bus->irq = irq;
40a6238a 2688 bus->dma = &ide_dma_nop;
d459da0e
MA		 2689}
2690
c9f08641
LQ		 2691void ide_exit(IDEState *s)
2692{
2693 timer_del(s->sector_write_timer);
2694 timer_free(s->sector_write_timer);
2695 qemu_vfree(s->smart_selftest_data);
2696 qemu_vfree(s->io_buffer);
2697}
2698
37159f13 2699static bool is_identify_set(void *opaque, int version_id)
aa941b94 2700{
37159f13
JQ		 2701 IDEState *s = opaque;
2702
2703 return s->identify_set != 0;
2704}
2705
50641c5c
JQ		 2706static EndTransferFunc* transfer_end_table[] = {
2707 ide_sector_read,
2708 ide_sector_write,
2709 ide_transfer_stop,
2710 ide_atapi_cmd_reply_end,
2711 ide_atapi_cmd,
2712 ide_dummy_transfer_stop,
2713};
2714
2715static int transfer_end_table_idx(EndTransferFunc *fn)
2716{
2717 int i;
2718
2719 for (i = 0; i < ARRAY_SIZE(transfer_end_table); i++)
2720 if (transfer_end_table[i] == fn)
2721 return i;
2722
2723 return -1;
2724}
2725
37159f13 2726static int ide_drive_post_load(void *opaque, int version_id)
aa941b94 2727{
37159f13
JQ		 2728 IDEState *s = opaque;
2729
6b896ab2 2730 if (s->blk && s->identify_set) {
4be74634 2731 blk_set_enable_write_cache(s->blk, !!(s->identify_data[85] & (1 << 5)));
7cdd481c 2732 }
37159f13 2733 return 0;
aa941b94
AZ		 2734}
2735
50641c5c
JQ		 2736static int ide_drive_pio_post_load(void *opaque, int version_id)
2737{
2738 IDEState *s = opaque;
2739
fb60105d 2740 if (s->end_transfer_fn_idx >= ARRAY_SIZE(transfer_end_table)) {
50641c5c
JQ		 2741 return -EINVAL;
2742 }
2743 s->end_transfer_func = transfer_end_table[s->end_transfer_fn_idx];
2744 s->data_ptr = s->io_buffer + s->cur_io_buffer_offset;
2745 s->data_end = s->data_ptr + s->cur_io_buffer_len;
819fa276 2746 s->atapi_dma = s->feature & 1; /* as per cmd_packet */
50641c5c
JQ		 2747
2748 return 0;
2749}
2750
44b1ff31 2751static int ide_drive_pio_pre_save(void *opaque)
50641c5c
JQ		 2752{
2753 IDEState *s = opaque;
2754 int idx;
2755
2756 s->cur_io_buffer_offset = s->data_ptr - s->io_buffer;
2757 s->cur_io_buffer_len = s->data_end - s->data_ptr;
2758
2759 idx = transfer_end_table_idx(s->end_transfer_func);
2760 if (idx == -1) {
2761 fprintf(stderr, "%s: invalid end_transfer_func for DRQ_STAT\n",
2762 __func__);
2763 s->end_transfer_fn_idx = 2;
2764 } else {
2765 s->end_transfer_fn_idx = idx;
2766 }
44b1ff31
DDAG		 2767
2768 return 0;
50641c5c
JQ		 2769}
2770
2771static bool ide_drive_pio_state_needed(void *opaque)
2772{
2773 IDEState *s = opaque;
2774
fdc650d7 2775 return ((s->status & DRQ_STAT) != 0)
fd648f10 2776 || (s->bus->error_status & IDE_RETRY_PIO);
50641c5c
JQ		 2777}
2778
db118fe7
MA		 2779static bool ide_tray_state_needed(void *opaque)
2780{
2781 IDEState *s = opaque;
2782
2783 return s->tray_open || s->tray_locked;
2784}
2785
996faf1a
AS		 2786static bool ide_atapi_gesn_needed(void *opaque)
2787{
2788 IDEState *s = opaque;
2789
2790 return s->events.new_media || s->events.eject_request;
2791}
2792
def93791
KW		 2793static bool ide_error_needed(void *opaque)
2794{
2795 IDEBus *bus = opaque;
2796
2797 return (bus->error_status != 0);
2798}
2799
996faf1a 2800/* Fields for GET_EVENT_STATUS_NOTIFICATION ATAPI command */
656fbeff 2801static const VMStateDescription vmstate_ide_atapi_gesn_state = {
996faf1a
AS		 2802 .name ="ide_drive/atapi/gesn_state",
2803 .version_id = 1,
2804 .minimum_version_id = 1,
5cd8cada 2805 .needed = ide_atapi_gesn_needed,
35d08458 2806 .fields = (VMStateField[]) {
996faf1a
AS		 2807 VMSTATE_BOOL(events.new_media, IDEState),
2808 VMSTATE_BOOL(events.eject_request, IDEState),
0754f9ec 2809 VMSTATE_END_OF_LIST()
996faf1a
AS		 2810 }
2811};
2812
db118fe7
MA		 2813static const VMStateDescription vmstate_ide_tray_state = {
2814 .name = "ide_drive/tray_state",
2815 .version_id = 1,
2816 .minimum_version_id = 1,
5cd8cada 2817 .needed = ide_tray_state_needed,
db118fe7
MA		 2818 .fields = (VMStateField[]) {
2819 VMSTATE_BOOL(tray_open, IDEState),
2820 VMSTATE_BOOL(tray_locked, IDEState),
2821 VMSTATE_END_OF_LIST()
2822 }
2823};
2824
656fbeff 2825static const VMStateDescription vmstate_ide_drive_pio_state = {
50641c5c
JQ		 2826 .name = "ide_drive/pio_state",
2827 .version_id = 1,
2828 .minimum_version_id = 1,
50641c5c
JQ		 2829 .pre_save = ide_drive_pio_pre_save,
2830 .post_load = ide_drive_pio_post_load,
5cd8cada 2831 .needed = ide_drive_pio_state_needed,
35d08458 2832 .fields = (VMStateField[]) {
50641c5c
JQ		 2833 VMSTATE_INT32(req_nb_sectors, IDEState),
2834 VMSTATE_VARRAY_INT32(io_buffer, IDEState, io_buffer_total_len, 1,
7d37435b 2835 vmstate_info_uint8, uint8_t),
50641c5c
JQ		 2836 VMSTATE_INT32(cur_io_buffer_offset, IDEState),
2837 VMSTATE_INT32(cur_io_buffer_len, IDEState),
2838 VMSTATE_UINT8(end_transfer_fn_idx, IDEState),
2839 VMSTATE_INT32(elementary_transfer_size, IDEState),
2840 VMSTATE_INT32(packet_transfer_size, IDEState),
2841 VMSTATE_END_OF_LIST()
2842 }
2843};
2844
37159f13
JQ		 2845const VMStateDescription vmstate_ide_drive = {
2846 .name = "ide_drive",
3abb6260 2847 .version_id = 3,
37159f13 2848 .minimum_version_id = 0,
37159f13 2849 .post_load = ide_drive_post_load,
35d08458 2850 .fields = (VMStateField[]) {
37159f13
JQ		 2851 VMSTATE_INT32(mult_sectors, IDEState),
2852 VMSTATE_INT32(identify_set, IDEState),
2853 VMSTATE_BUFFER_TEST(identify_data, IDEState, is_identify_set),
2854 VMSTATE_UINT8(feature, IDEState),
2855 VMSTATE_UINT8(error, IDEState),
2856 VMSTATE_UINT32(nsector, IDEState),
2857 VMSTATE_UINT8(sector, IDEState),
2858 VMSTATE_UINT8(lcyl, IDEState),
2859 VMSTATE_UINT8(hcyl, IDEState),
2860 VMSTATE_UINT8(hob_feature, IDEState),
2861 VMSTATE_UINT8(hob_sector, IDEState),
2862 VMSTATE_UINT8(hob_nsector, IDEState),
2863 VMSTATE_UINT8(hob_lcyl, IDEState),
2864 VMSTATE_UINT8(hob_hcyl, IDEState),
2865 VMSTATE_UINT8(select, IDEState),
2866 VMSTATE_UINT8(status, IDEState),
2867 VMSTATE_UINT8(lba48, IDEState),
2868 VMSTATE_UINT8(sense_key, IDEState),
2869 VMSTATE_UINT8(asc, IDEState),
2870 VMSTATE_UINT8_V(cdrom_changed, IDEState, 3),
37159f13 2871 VMSTATE_END_OF_LIST()
50641c5c 2872 },
5cd8cada
JQ		 2873 .subsections = (const VMStateDescription*[]) {
2874 &vmstate_ide_drive_pio_state,
2875 &vmstate_ide_tray_state,
2876 &vmstate_ide_atapi_gesn_state,
2877 NULL
37159f13
JQ		 2878 }
2879};
2880
656fbeff 2881static const VMStateDescription vmstate_ide_error_status = {
def93791 2882 .name ="ide_bus/error",
d12b9ff2 2883 .version_id = 2,
def93791 2884 .minimum_version_id = 1,
5cd8cada 2885 .needed = ide_error_needed,
35d08458 2886 .fields = (VMStateField[]) {
def93791 2887 VMSTATE_INT32(error_status, IDEBus),
d12b9ff2
PB		 2888 VMSTATE_INT64_V(retry_sector_num, IDEBus, 2),
2889 VMSTATE_UINT32_V(retry_nsector, IDEBus, 2),
2890 VMSTATE_UINT8_V(retry_unit, IDEBus, 2),
def93791
KW		 2891 VMSTATE_END_OF_LIST()
2892 }
2893};
2894
6521dc62
JQ		 2895const VMStateDescription vmstate_ide_bus = {
2896 .name = "ide_bus",
2897 .version_id = 1,
2898 .minimum_version_id = 1,
35d08458 2899 .fields = (VMStateField[]) {
6521dc62
JQ		 2900 VMSTATE_UINT8(cmd, IDEBus),
2901 VMSTATE_UINT8(unit, IDEBus),
2902 VMSTATE_END_OF_LIST()
def93791 2903 },
5cd8cada
JQ		 2904 .subsections = (const VMStateDescription*[]) {
2905 &vmstate_ide_error_status,
2906 NULL
6521dc62
JQ		 2907 }
2908};
75717903 2909
d8f94e1b 2910void ide_drive_get(DriveInfo **hd, int n)
75717903
IY		 2911{
2912 int i;
75717903 2913
d8f94e1b
JS		 2914 for (i = 0; i < n; i++) {
2915 hd[i] = drive_get_by_index(IF_IDE, i);
75717903
IY		 2916 }
2917}
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