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accel/tcg: Restrict cpu_io_recompile() from other accelerators
[qemu.git] / accel / tcg / cpu-exec.c
CommitLineData
7d13299d 1/*
e965fc38 2 * emulator main execution loop
5fafdf24 3 *
66321a11 4 * Copyright (c) 2003-2005 Fabrice Bellard
7d13299d 5 *
3ef693a0
FB
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
fb0343d5 9 * version 2.1 of the License, or (at your option) any later version.
7d13299d 10 *
3ef693a0
FB
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
7d13299d 15 *
3ef693a0 16 * You should have received a copy of the GNU Lesser General Public
8167ee88 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
7d13299d 18 */
a8d25326 19
7b31bbc2 20#include "qemu/osdep.h"
a8d25326 21#include "qemu-common.h"
740b1759 22#include "qemu/qemu-print.h"
cea5f9a2 23#include "cpu.h"
d9bb58e5 24#include "trace.h"
76cad711 25#include "disas/disas.h"
63c91552 26#include "exec/exec-all.h"
dcb32f1d 27#include "tcg/tcg.h"
1de7afc9 28#include "qemu/atomic.h"
c905a368 29#include "qemu/compiler.h"
9c17d615 30#include "sysemu/qtest.h"
c2aa5f81 31#include "qemu/timer.h"
79e2b9ae 32#include "qemu/rcu.h"
e1b89321 33#include "exec/tb-hash.h"
f6bb84d5 34#include "exec/tb-lookup.h"
508127e2 35#include "exec/log.h"
8d04fb55 36#include "qemu/main-loop.h"
6220e900
PD
37#if defined(TARGET_I386) && !defined(CONFIG_USER_ONLY)
38#include "hw/i386/apic.h"
39#endif
d2528bdc 40#include "sysemu/cpus.h"
740b1759
CF
41#include "exec/cpu-all.h"
42#include "sysemu/cpu-timers.h"
6f060969 43#include "sysemu/replay.h"
c03f041f 44#include "internal.h"
c2aa5f81
ST
45
46/* -icount align implementation. */
47
48typedef struct SyncClocks {
49 int64_t diff_clk;
50 int64_t last_cpu_icount;
7f7bc144 51 int64_t realtime_clock;
c2aa5f81
ST
52} SyncClocks;
53
54#if !defined(CONFIG_USER_ONLY)
55/* Allow the guest to have a max 3ms advance.
56 * The difference between the 2 clocks could therefore
57 * oscillate around 0.
58 */
59#define VM_CLOCK_ADVANCE 3000000
7f7bc144
ST
60#define THRESHOLD_REDUCE 1.5
61#define MAX_DELAY_PRINT_RATE 2000000000LL
62#define MAX_NB_PRINTS 100
c2aa5f81 63
740b1759
CF
64static int64_t max_delay;
65static int64_t max_advance;
66
5e140196 67static void align_clocks(SyncClocks *sc, CPUState *cpu)
c2aa5f81
ST
68{
69 int64_t cpu_icount;
70
71 if (!icount_align_option) {
72 return;
73 }
74
5e140196 75 cpu_icount = cpu->icount_extra + cpu_neg(cpu)->icount_decr.u16.low;
8191d368 76 sc->diff_clk += icount_to_ns(sc->last_cpu_icount - cpu_icount);
c2aa5f81
ST
77 sc->last_cpu_icount = cpu_icount;
78
79 if (sc->diff_clk > VM_CLOCK_ADVANCE) {
80#ifndef _WIN32
81 struct timespec sleep_delay, rem_delay;
82 sleep_delay.tv_sec = sc->diff_clk / 1000000000LL;
83 sleep_delay.tv_nsec = sc->diff_clk % 1000000000LL;
84 if (nanosleep(&sleep_delay, &rem_delay) < 0) {
a498d0ef 85 sc->diff_clk = rem_delay.tv_sec * 1000000000LL + rem_delay.tv_nsec;
c2aa5f81
ST
86 } else {
87 sc->diff_clk = 0;
88 }
89#else
90 Sleep(sc->diff_clk / SCALE_MS);
91 sc->diff_clk = 0;
92#endif
93 }
94}
95
7f7bc144
ST
96static void print_delay(const SyncClocks *sc)
97{
98 static float threshold_delay;
99 static int64_t last_realtime_clock;
100 static int nb_prints;
101
102 if (icount_align_option &&
103 sc->realtime_clock - last_realtime_clock >= MAX_DELAY_PRINT_RATE &&
104 nb_prints < MAX_NB_PRINTS) {
105 if ((-sc->diff_clk / (float)1000000000LL > threshold_delay) ||
106 (-sc->diff_clk / (float)1000000000LL <
107 (threshold_delay - THRESHOLD_REDUCE))) {
108 threshold_delay = (-sc->diff_clk / 1000000000LL) + 1;
740b1759
CF
109 qemu_printf("Warning: The guest is now late by %.1f to %.1f seconds\n",
110 threshold_delay - 1,
111 threshold_delay);
7f7bc144
ST
112 nb_prints++;
113 last_realtime_clock = sc->realtime_clock;
114 }
115 }
116}
117
5e140196 118static void init_delay_params(SyncClocks *sc, CPUState *cpu)
c2aa5f81
ST
119{
120 if (!icount_align_option) {
121 return;
122 }
2e91cc62
PB
123 sc->realtime_clock = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL_RT);
124 sc->diff_clk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - sc->realtime_clock;
5e140196
RH
125 sc->last_cpu_icount
126 = cpu->icount_extra + cpu_neg(cpu)->icount_decr.u16.low;
27498bef
ST
127 if (sc->diff_clk < max_delay) {
128 max_delay = sc->diff_clk;
129 }
130 if (sc->diff_clk > max_advance) {
131 max_advance = sc->diff_clk;
132 }
7f7bc144
ST
133
134 /* Print every 2s max if the guest is late. We limit the number
135 of printed messages to NB_PRINT_MAX(currently 100) */
136 print_delay(sc);
c2aa5f81
ST
137}
138#else
139static void align_clocks(SyncClocks *sc, const CPUState *cpu)
140{
141}
142
143static void init_delay_params(SyncClocks *sc, const CPUState *cpu)
144{
145}
146#endif /* CONFIG USER ONLY */
7d13299d 147
77211379 148/* Execute a TB, and fix up the CPU state afterwards if necessary */
c905a368
DB
149/*
150 * Disable CFI checks.
151 * TCG creates binary blobs at runtime, with the transformed code.
152 * A TB is a blob of binary code, created at runtime and called with an
153 * indirect function call. Since such function did not exist at compile time,
154 * the CFI runtime has no way to verify its signature and would fail.
155 * TCG is not considered a security-sensitive part of QEMU so this does not
156 * affect the impact of CFI in environment with high security requirements
157 */
eba40358
RH
158static inline TranslationBlock * QEMU_DISABLE_CFI
159cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit)
77211379
PM
160{
161 CPUArchState *env = cpu->env_ptr;
819af24b
SF
162 uintptr_t ret;
163 TranslationBlock *last_tb;
db0c51a3 164 const void *tb_ptr = itb->tc.ptr;
1a830635 165
d977e1c2 166 qemu_log_mask_and_addr(CPU_LOG_EXEC, itb->pc,
4fad446b
PB
167 "Trace %d: %p ["
168 TARGET_FMT_lx "/" TARGET_FMT_lx "/%#x] %s\n",
169 cpu->cpu_index, itb->tc.ptr,
170 itb->cs_base, itb->pc, itb->flags,
4426f83a 171 lookup_symbol(itb->pc));
03afa5f8
RH
172
173#if defined(DEBUG_DISAS)
be2208e2
RH
174 if (qemu_loglevel_mask(CPU_LOG_TB_CPU)
175 && qemu_log_in_addr_range(itb->pc)) {
fc59d2d8 176 FILE *logfile = qemu_log_lock();
ae765180
PM
177 int flags = 0;
178 if (qemu_loglevel_mask(CPU_LOG_TB_FPU)) {
179 flags |= CPU_DUMP_FPU;
180 }
03afa5f8 181#if defined(TARGET_I386)
ae765180 182 flags |= CPU_DUMP_CCOP;
03afa5f8 183#endif
ae765180 184 log_cpu_state(cpu, flags);
fc59d2d8 185 qemu_log_unlock(logfile);
03afa5f8
RH
186 }
187#endif /* DEBUG_DISAS */
188
819af24b 189 ret = tcg_qemu_tb_exec(env, tb_ptr);
626cf8f4 190 cpu->can_do_io = 1;
eba40358
RH
191 /*
192 * TODO: Delay swapping back to the read-write region of the TB
193 * until we actually need to modify the TB. The read-only copy,
194 * coming from the rx region, shares the same host TLB entry as
195 * the code that executed the exit_tb opcode that arrived here.
196 * If we insist on touching both the RX and the RW pages, we
197 * double the host TLB pressure.
198 */
199 last_tb = tcg_splitwx_to_rw((void *)(ret & ~TB_EXIT_MASK));
200 *tb_exit = ret & TB_EXIT_MASK;
201
202 trace_exec_tb_exit(last_tb, *tb_exit);
6db8b538 203
eba40358 204 if (*tb_exit > TB_EXIT_IDX1) {
77211379
PM
205 /* We didn't start executing this TB (eg because the instruction
206 * counter hit zero); we must restore the guest PC to the address
207 * of the start of the TB.
208 */
bdf7ae5b 209 CPUClass *cc = CPU_GET_CLASS(cpu);
819af24b 210 qemu_log_mask_and_addr(CPU_LOG_EXEC, last_tb->pc,
d977e1c2
AB
211 "Stopped execution of TB chain before %p ["
212 TARGET_FMT_lx "] %s\n",
e7e168f4 213 last_tb->tc.ptr, last_tb->pc,
819af24b 214 lookup_symbol(last_tb->pc));
bdf7ae5b 215 if (cc->synchronize_from_tb) {
819af24b 216 cc->synchronize_from_tb(cpu, last_tb);
bdf7ae5b
AF
217 } else {
218 assert(cc->set_pc);
819af24b 219 cc->set_pc(cpu, last_tb->pc);
bdf7ae5b 220 }
77211379 221 }
eba40358 222 return last_tb;
77211379
PM
223}
224
7687bf52 225#ifndef CONFIG_USER_ONLY
2e70f6ef
PB
226/* Execute the code without caching the generated code. An interpreter
227 could be used if available. */
ea3e9847 228static void cpu_exec_nocache(CPUState *cpu, int max_cycles,
56c0269a 229 TranslationBlock *orig_tb, bool ignore_icount)
2e70f6ef 230{
2e70f6ef 231 TranslationBlock *tb;
416986d3 232 uint32_t cflags = curr_cflags() | CF_NOCACHE;
eba40358 233 int tb_exit;
416986d3
RH
234
235 if (ignore_icount) {
236 cflags &= ~CF_USE_ICOUNT;
237 }
2e70f6ef
PB
238
239 /* Should never happen.
240 We only end up here when an existing TB is too long. */
416986d3 241 cflags |= MIN(max_cycles, CF_COUNT_MASK);
2e70f6ef 242
0ac20318 243 mmap_lock();
416986d3
RH
244 tb = tb_gen_code(cpu, orig_tb->pc, orig_tb->cs_base,
245 orig_tb->flags, cflags);
3359baad 246 tb->orig_tb = orig_tb;
0ac20318 247 mmap_unlock();
a5e99826 248
2e70f6ef 249 /* execute the generated code */
6db8b538 250 trace_exec_tb_nocache(tb, tb->pc);
eba40358 251 cpu_tb_exec(cpu, tb, &tb_exit);
a5e99826 252
0ac20318 253 mmap_lock();
2e70f6ef 254 tb_phys_invalidate(tb, -1);
0ac20318 255 mmap_unlock();
be2cdc5e 256 tcg_tb_remove(tb);
2e70f6ef 257}
7687bf52 258#endif
2e70f6ef 259
035ba06c
EH
260static void cpu_exec_enter(CPUState *cpu)
261{
262 CPUClass *cc = CPU_GET_CLASS(cpu);
263
80c4750b
EH
264 if (cc->cpu_exec_enter) {
265 cc->cpu_exec_enter(cpu);
266 }
035ba06c
EH
267}
268
269static void cpu_exec_exit(CPUState *cpu)
fdbc2b57 270{
08e73c48 271 CPUClass *cc = CPU_GET_CLASS(cpu);
035ba06c 272
80c4750b
EH
273 if (cc->cpu_exec_exit) {
274 cc->cpu_exec_exit(cpu);
275 }
035ba06c
EH
276}
277
278void cpu_exec_step_atomic(CPUState *cpu)
279{
fdbc2b57
RH
280 TranslationBlock *tb;
281 target_ulong cs_base, pc;
282 uint32_t flags;
416986d3 283 uint32_t cflags = 1;
ac03ee53 284 uint32_t cf_mask = cflags & CF_HASH_MASK;
eba40358 285 int tb_exit;
fdbc2b57 286
08e73c48 287 if (sigsetjmp(cpu->jmp_env, 0) == 0) {
886cc689 288 start_exclusive();
bfff072c
DC
289 g_assert(cpu == current_cpu);
290 g_assert(!cpu->running);
291 cpu->running = true;
886cc689 292
ac03ee53 293 tb = tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags, cf_mask);
4e2ca83e
EC
294 if (tb == NULL) {
295 mmap_lock();
95590e24 296 tb = tb_gen_code(cpu, pc, cs_base, flags, cflags);
4e2ca83e
EC
297 mmap_unlock();
298 }
08e73c48 299
ac03ee53
EC
300 /* Since we got here, we know that parallel_cpus must be true. */
301 parallel_cpus = false;
035ba06c 302 cpu_exec_enter(cpu);
08e73c48 303 /* execute the generated code */
4e2ca83e 304 trace_exec_tb(tb, pc);
eba40358 305 cpu_tb_exec(cpu, tb, &tb_exit);
035ba06c 306 cpu_exec_exit(cpu);
08e73c48 307 } else {
0ac20318 308 /*
08e73c48
PK
309 * The mmap_lock is dropped by tb_gen_code if it runs out of
310 * memory.
311 */
312#ifndef CONFIG_SOFTMMU
313 tcg_debug_assert(!have_mmap_lock());
314#endif
6aaa24f9
EC
315 if (qemu_mutex_iothread_locked()) {
316 qemu_mutex_unlock_iothread();
317 }
faa9372c 318 assert_no_pages_locked();
e6d86bed 319 qemu_plugin_disable_mem_helpers(cpu);
08e73c48 320 }
426eeecd 321
886cc689
AB
322
323 /*
324 * As we start the exclusive region before codegen we must still
325 * be in the region if we longjump out of either the codegen or
326 * the execution.
327 */
328 g_assert(cpu_in_exclusive_context(cpu));
329 parallel_cpus = true;
bfff072c 330 cpu->running = false;
886cc689 331 end_exclusive();
fdbc2b57
RH
332}
333
909eaac9
EC
334struct tb_desc {
335 target_ulong pc;
336 target_ulong cs_base;
337 CPUArchState *env;
338 tb_page_addr_t phys_page1;
339 uint32_t flags;
4e2ca83e 340 uint32_t cf_mask;
61a67f71 341 uint32_t trace_vcpu_dstate;
909eaac9
EC
342};
343
61b8cef1 344static bool tb_lookup_cmp(const void *p, const void *d)
909eaac9
EC
345{
346 const TranslationBlock *tb = p;
347 const struct tb_desc *desc = d;
348
349 if (tb->pc == desc->pc &&
350 tb->page_addr[0] == desc->phys_page1 &&
351 tb->cs_base == desc->cs_base &&
6d21e420 352 tb->flags == desc->flags &&
61a67f71 353 tb->trace_vcpu_dstate == desc->trace_vcpu_dstate &&
4e2ca83e 354 (tb_cflags(tb) & (CF_HASH_MASK | CF_INVALID)) == desc->cf_mask) {
909eaac9
EC
355 /* check next page if needed */
356 if (tb->page_addr[1] == -1) {
357 return true;
358 } else {
359 tb_page_addr_t phys_page2;
360 target_ulong virt_page2;
361
362 virt_page2 = (desc->pc & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
363 phys_page2 = get_page_addr_code(desc->env, virt_page2);
364 if (tb->page_addr[1] == phys_page2) {
365 return true;
366 }
367 }
368 }
369 return false;
370}
371
cedbcb01 372TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc,
4e2ca83e
EC
373 target_ulong cs_base, uint32_t flags,
374 uint32_t cf_mask)
8a40a180 375{
909eaac9
EC
376 tb_page_addr_t phys_pc;
377 struct tb_desc desc;
42bd3228 378 uint32_t h;
3b46e624 379
909eaac9
EC
380 desc.env = (CPUArchState *)cpu->env_ptr;
381 desc.cs_base = cs_base;
382 desc.flags = flags;
4e2ca83e 383 desc.cf_mask = cf_mask;
61a67f71 384 desc.trace_vcpu_dstate = *cpu->trace_dstate;
909eaac9
EC
385 desc.pc = pc;
386 phys_pc = get_page_addr_code(desc.env, pc);
7252f2de
PM
387 if (phys_pc == -1) {
388 return NULL;
389 }
909eaac9 390 desc.phys_page1 = phys_pc & TARGET_PAGE_MASK;
4e2ca83e 391 h = tb_hash_func(phys_pc, pc, flags, cf_mask, *cpu->trace_dstate);
61b8cef1 392 return qht_lookup_custom(&tb_ctx.htable, &desc, h, tb_lookup_cmp);
9fd1a948
PB
393}
394
a8583393
RH
395void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr)
396{
397 if (TCG_TARGET_HAS_direct_jump) {
398 uintptr_t offset = tb->jmp_target_arg[n];
e7e168f4 399 uintptr_t tc_ptr = (uintptr_t)tb->tc.ptr;
1acbad0f
RH
400 uintptr_t jmp_rx = tc_ptr + offset;
401 uintptr_t jmp_rw = jmp_rx - tcg_splitwx_diff;
402 tb_target_set_jmp_target(tc_ptr, jmp_rx, jmp_rw, addr);
a8583393
RH
403 } else {
404 tb->jmp_target_arg[n] = addr;
405 }
406}
407
a8583393
RH
408static inline void tb_add_jump(TranslationBlock *tb, int n,
409 TranslationBlock *tb_next)
410{
194125e3
EC
411 uintptr_t old;
412
a8583393 413 assert(n < ARRAY_SIZE(tb->jmp_list_next));
194125e3
EC
414 qemu_spin_lock(&tb_next->jmp_lock);
415
416 /* make sure the destination TB is valid */
417 if (tb_next->cflags & CF_INVALID) {
418 goto out_unlock_next;
419 }
420 /* Atomically claim the jump destination slot only if it was NULL */
d73415a3
SH
421 old = qatomic_cmpxchg(&tb->jmp_dest[n], (uintptr_t)NULL,
422 (uintptr_t)tb_next);
194125e3
EC
423 if (old) {
424 goto out_unlock_next;
a8583393 425 }
194125e3
EC
426
427 /* patch the native jump address */
428 tb_set_jmp_target(tb, n, (uintptr_t)tb_next->tc.ptr);
429
430 /* add in TB jmp list */
431 tb->jmp_list_next[n] = tb_next->jmp_list_head;
432 tb_next->jmp_list_head = (uintptr_t)tb | n;
433
434 qemu_spin_unlock(&tb_next->jmp_lock);
435
a8583393
RH
436 qemu_log_mask_and_addr(CPU_LOG_EXEC, tb->pc,
437 "Linking TBs %p [" TARGET_FMT_lx
438 "] index %d -> %p [" TARGET_FMT_lx "]\n",
e7e168f4
EC
439 tb->tc.ptr, tb->pc, n,
440 tb_next->tc.ptr, tb_next->pc);
194125e3 441 return;
a8583393 442
194125e3
EC
443 out_unlock_next:
444 qemu_spin_unlock(&tb_next->jmp_lock);
445 return;
a8583393
RH
446}
447
bd2710d5
SF
448static inline TranslationBlock *tb_find(CPUState *cpu,
449 TranslationBlock *last_tb,
9b990ee5 450 int tb_exit, uint32_t cf_mask)
8a40a180
FB
451{
452 TranslationBlock *tb;
453 target_ulong cs_base, pc;
89fee74a 454 uint32_t flags;
8a40a180 455
4e2ca83e 456 tb = tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags, cf_mask);
f6bb84d5 457 if (tb == NULL) {
f6bb84d5 458 mmap_lock();
95590e24 459 tb = tb_gen_code(cpu, pc, cs_base, flags, cf_mask);
f6bb84d5 460 mmap_unlock();
bd2710d5 461 /* We add the TB in the virtual pc hash table for the fast lookup */
d73415a3 462 qatomic_set(&cpu->tb_jmp_cache[tb_jmp_cache_hash_func(pc)], tb);
8a40a180 463 }
c88c67e5
SF
464#ifndef CONFIG_USER_ONLY
465 /* We don't take care of direct jumps when address mapping changes in
466 * system emulation. So it's not safe to make a direct jump to a TB
467 * spanning two pages because the mapping for the second page can change.
468 */
469 if (tb->page_addr[1] != -1) {
4b7e6950 470 last_tb = NULL;
c88c67e5
SF
471 }
472#endif
a0522c7a 473 /* See if we can patch the calling TB. */
d7f425fd 474 if (last_tb) {
194125e3 475 tb_add_jump(last_tb, tb_exit, tb);
74d356dd 476 }
8a40a180
FB
477 return tb;
478}
479
8b2d34e9
SF
480static inline bool cpu_handle_halt(CPUState *cpu)
481{
482 if (cpu->halted) {
483#if defined(TARGET_I386) && !defined(CONFIG_USER_ONLY)
4084893d 484 if (cpu->interrupt_request & CPU_INTERRUPT_POLL) {
8b2d34e9 485 X86CPU *x86_cpu = X86_CPU(cpu);
8d04fb55 486 qemu_mutex_lock_iothread();
8b2d34e9
SF
487 apic_poll_irq(x86_cpu->apic_state);
488 cpu_reset_interrupt(cpu, CPU_INTERRUPT_POLL);
8d04fb55 489 qemu_mutex_unlock_iothread();
8b2d34e9
SF
490 }
491#endif
492 if (!cpu_has_work(cpu)) {
8b2d34e9
SF
493 return true;
494 }
495
496 cpu->halted = 0;
497 }
498
499 return false;
500}
501
ea284766 502static inline void cpu_handle_debug_exception(CPUState *cpu)
1009d2ed 503{
86025ee4 504 CPUClass *cc = CPU_GET_CLASS(cpu);
1009d2ed
JK
505 CPUWatchpoint *wp;
506
ff4700b0
AF
507 if (!cpu->watchpoint_hit) {
508 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
1009d2ed
JK
509 wp->flags &= ~BP_WATCHPOINT_HIT;
510 }
511 }
86025ee4 512
710384d0
EH
513 if (cc->debug_excp_handler) {
514 cc->debug_excp_handler(cpu);
515 }
1009d2ed
JK
516}
517
ea284766
SF
518static inline bool cpu_handle_exception(CPUState *cpu, int *ret)
519{
17b50b0c
PD
520 if (cpu->exception_index < 0) {
521#ifndef CONFIG_USER_ONLY
522 if (replay_has_exception()
5e140196 523 && cpu_neg(cpu)->icount_decr.u16.low + cpu->icount_extra == 0) {
17b50b0c
PD
524 /* try to cause an exception pending in the log */
525 cpu_exec_nocache(cpu, 1, tb_find(cpu, NULL, 0, curr_cflags()), true);
526 }
527#endif
528 if (cpu->exception_index < 0) {
529 return false;
530 }
531 }
532
533 if (cpu->exception_index >= EXCP_INTERRUPT) {
534 /* exit request from the cpu execution loop */
535 *ret = cpu->exception_index;
536 if (*ret == EXCP_DEBUG) {
537 cpu_handle_debug_exception(cpu);
538 }
539 cpu->exception_index = -1;
540 return true;
541 } else {
ea284766 542#if defined(CONFIG_USER_ONLY)
17b50b0c
PD
543 /* if user mode only, we simulate a fake exception
544 which will be handled outside the cpu execution
545 loop */
ea284766 546#if defined(TARGET_I386)
17b50b0c
PD
547 CPUClass *cc = CPU_GET_CLASS(cpu);
548 cc->do_interrupt(cpu);
549#endif
550 *ret = cpu->exception_index;
551 cpu->exception_index = -1;
552 return true;
553#else
554 if (replay_exception()) {
ea284766 555 CPUClass *cc = CPU_GET_CLASS(cpu);
17b50b0c 556 qemu_mutex_lock_iothread();
ea284766 557 cc->do_interrupt(cpu);
17b50b0c 558 qemu_mutex_unlock_iothread();
ea284766 559 cpu->exception_index = -1;
a7ba744f
LM
560
561 if (unlikely(cpu->singlestep_enabled)) {
562 /*
563 * After processing the exception, ensure an EXCP_DEBUG is
564 * raised when single-stepping so that GDB doesn't miss the
565 * next instruction.
566 */
567 *ret = EXCP_DEBUG;
568 cpu_handle_debug_exception(cpu);
569 return true;
570 }
17b50b0c
PD
571 } else if (!replay_has_interrupt()) {
572 /* give a chance to iothread in replay mode */
573 *ret = EXCP_INTERRUPT;
ea284766 574 return true;
ea284766 575 }
ea284766
SF
576#endif
577 }
578
579 return false;
580}
581
4084893d
PD
582/*
583 * CPU_INTERRUPT_POLL is a virtual event which gets converted into a
584 * "real" interrupt event later. It does not need to be recorded for
585 * replay purposes.
586 */
587static inline bool need_replay_interrupt(int interrupt_request)
588{
589#if defined(TARGET_I386)
590 return !(interrupt_request & CPU_INTERRUPT_POLL);
591#else
592 return true;
593#endif
594}
595
209b71b6 596static inline bool cpu_handle_interrupt(CPUState *cpu,
c385e6e4
SF
597 TranslationBlock **last_tb)
598{
599 CPUClass *cc = CPU_GET_CLASS(cpu);
17b50b0c
PD
600
601 /* Clear the interrupt flag now since we're processing
602 * cpu->interrupt_request and cpu->exit_request.
d84be02d
DH
603 * Ensure zeroing happens before reading cpu->exit_request or
604 * cpu->interrupt_request (see also smp_wmb in cpu_exit())
17b50b0c 605 */
d73415a3 606 qatomic_mb_set(&cpu_neg(cpu)->icount_decr.u16.high, 0);
c385e6e4 607
d73415a3 608 if (unlikely(qatomic_read(&cpu->interrupt_request))) {
8d04fb55
JK
609 int interrupt_request;
610 qemu_mutex_lock_iothread();
611 interrupt_request = cpu->interrupt_request;
c385e6e4
SF
612 if (unlikely(cpu->singlestep_enabled & SSTEP_NOIRQ)) {
613 /* Mask out external interrupts for this step. */
614 interrupt_request &= ~CPU_INTERRUPT_SSTEP_MASK;
615 }
616 if (interrupt_request & CPU_INTERRUPT_DEBUG) {
617 cpu->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
618 cpu->exception_index = EXCP_DEBUG;
8d04fb55 619 qemu_mutex_unlock_iothread();
209b71b6 620 return true;
c385e6e4
SF
621 }
622 if (replay_mode == REPLAY_MODE_PLAY && !replay_has_interrupt()) {
623 /* Do nothing */
624 } else if (interrupt_request & CPU_INTERRUPT_HALT) {
625 replay_interrupt();
626 cpu->interrupt_request &= ~CPU_INTERRUPT_HALT;
627 cpu->halted = 1;
628 cpu->exception_index = EXCP_HLT;
8d04fb55 629 qemu_mutex_unlock_iothread();
209b71b6 630 return true;
c385e6e4
SF
631 }
632#if defined(TARGET_I386)
633 else if (interrupt_request & CPU_INTERRUPT_INIT) {
634 X86CPU *x86_cpu = X86_CPU(cpu);
635 CPUArchState *env = &x86_cpu->env;
636 replay_interrupt();
65c9d60a 637 cpu_svm_check_intercept_param(env, SVM_EXIT_INIT, 0, 0);
c385e6e4
SF
638 do_cpu_init(x86_cpu);
639 cpu->exception_index = EXCP_HALTED;
8d04fb55 640 qemu_mutex_unlock_iothread();
209b71b6 641 return true;
c385e6e4
SF
642 }
643#else
644 else if (interrupt_request & CPU_INTERRUPT_RESET) {
645 replay_interrupt();
646 cpu_reset(cpu);
8d04fb55 647 qemu_mutex_unlock_iothread();
209b71b6 648 return true;
c385e6e4
SF
649 }
650#endif
651 /* The target hook has 3 exit conditions:
652 False when the interrupt isn't processed,
653 True when it is, and we should restart on a new TB,
654 and via longjmp via cpu_loop_exit. */
655 else {
80c4750b
EH
656 if (cc->cpu_exec_interrupt &&
657 cc->cpu_exec_interrupt(cpu, interrupt_request)) {
4084893d
PD
658 if (need_replay_interrupt(interrupt_request)) {
659 replay_interrupt();
660 }
ba3c35d9
RH
661 /*
662 * After processing the interrupt, ensure an EXCP_DEBUG is
663 * raised when single-stepping so that GDB doesn't miss the
664 * next instruction.
665 */
666 cpu->exception_index =
667 (cpu->singlestep_enabled ? EXCP_DEBUG : -1);
c385e6e4
SF
668 *last_tb = NULL;
669 }
8b1fe3f4
SF
670 /* The target hook may have updated the 'cpu->interrupt_request';
671 * reload the 'interrupt_request' value */
672 interrupt_request = cpu->interrupt_request;
c385e6e4 673 }
8b1fe3f4 674 if (interrupt_request & CPU_INTERRUPT_EXITTB) {
c385e6e4
SF
675 cpu->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
676 /* ensure that no TB jump will be modified as
677 the program flow was changed */
678 *last_tb = NULL;
679 }
8d04fb55
JK
680
681 /* If we exit via cpu_loop_exit/longjmp it is reset in cpu_exec */
682 qemu_mutex_unlock_iothread();
c385e6e4 683 }
8d04fb55 684
cfb2d02b 685 /* Finally, check if we need to exit to the main loop. */
d73415a3 686 if (unlikely(qatomic_read(&cpu->exit_request))
740b1759 687 || (icount_enabled()
5e140196 688 && cpu_neg(cpu)->icount_decr.u16.low + cpu->icount_extra == 0)) {
d73415a3 689 qatomic_set(&cpu->exit_request, 0);
5f3bdfd4
PD
690 if (cpu->exception_index == -1) {
691 cpu->exception_index = EXCP_INTERRUPT;
692 }
209b71b6 693 return true;
c385e6e4 694 }
209b71b6
PB
695
696 return false;
c385e6e4
SF
697}
698
928de9ee 699static inline void cpu_loop_exec_tb(CPUState *cpu, TranslationBlock *tb,
cfb2d02b 700 TranslationBlock **last_tb, int *tb_exit)
928de9ee 701{
1aab16c2 702 int32_t insns_left;
928de9ee
SF
703
704 trace_exec_tb(tb, tb->pc);
eba40358 705 tb = cpu_tb_exec(cpu, tb, tb_exit);
1aab16c2
PB
706 if (*tb_exit != TB_EXIT_REQUESTED) {
707 *last_tb = tb;
708 return;
709 }
710
711 *last_tb = NULL;
d73415a3 712 insns_left = qatomic_read(&cpu_neg(cpu)->icount_decr.u32);
1aab16c2 713 if (insns_left < 0) {
e5143e30
AB
714 /* Something asked us to stop executing chained TBs; just
715 * continue round the main loop. Whatever requested the exit
30f3dda2 716 * will also have set something else (eg exit_request or
17b50b0c
PD
717 * interrupt_request) which will be handled by
718 * cpu_handle_interrupt. cpu_handle_interrupt will also
719 * clear cpu->icount_decr.u16.high.
928de9ee 720 */
1aab16c2 721 return;
928de9ee 722 }
1aab16c2
PB
723
724 /* Instruction counter expired. */
740b1759 725 assert(icount_enabled());
1aab16c2 726#ifndef CONFIG_USER_ONLY
eda5f7c6 727 /* Ensure global icount has gone forward */
8191d368 728 icount_update(cpu);
eda5f7c6
AB
729 /* Refill decrementer and continue execution. */
730 insns_left = MIN(0xffff, cpu->icount_budget);
5e140196 731 cpu_neg(cpu)->icount_decr.u16.low = insns_left;
eda5f7c6 732 cpu->icount_extra = cpu->icount_budget - insns_left;
835cbd8d 733 if (!cpu->icount_extra && insns_left < tb->icount) {
1aab16c2
PB
734 /* Execute any remaining instructions, then let the main loop
735 * handle the next event.
736 */
737 if (insns_left > 0) {
738 cpu_exec_nocache(cpu, insns_left, tb, false);
1aab16c2 739 }
928de9ee 740 }
1aab16c2 741#endif
928de9ee
SF
742}
743
7d13299d
FB
744/* main execution loop */
745
ea3e9847 746int cpu_exec(CPUState *cpu)
7d13299d 747{
97a8ea5a 748 CPUClass *cc = CPU_GET_CLASS(cpu);
c385e6e4 749 int ret;
cfb2d02b 750 SyncClocks sc = { 0 };
c2aa5f81 751
6f060969
PD
752 /* replay_interrupt may need current_cpu */
753 current_cpu = cpu;
754
8b2d34e9
SF
755 if (cpu_handle_halt(cpu)) {
756 return EXCP_HALTED;
eda48c34 757 }
5a1e3cfc 758
79e2b9ae
PB
759 rcu_read_lock();
760
035ba06c 761 cpu_exec_enter(cpu);
9d27abd9 762
c2aa5f81
ST
763 /* Calculate difference between guest clock and host clock.
764 * This delay includes the delay of the last cycle, so
765 * what we have to do is sleep until it is 0. As for the
766 * advance/delay we gain here, we try to fix it next time.
767 */
768 init_delay_params(&sc, cpu);
769
4515e58d
PB
770 /* prepare setjmp context for exception handling */
771 if (sigsetjmp(cpu->jmp_env, 0) != 0) {
19a84318 772#if defined(__clang__)
4515e58d
PB
773 /* Some compilers wrongly smash all local variables after
774 * siglongjmp. There were bug reports for gcc 4.5.0 and clang.
775 * Reload essential local variables here for those compilers.
776 * Newer versions of gcc would complain about this code (-Wclobbered). */
777 cpu = current_cpu;
778 cc = CPU_GET_CLASS(cpu);
0448f5f8 779#else /* buggy compiler */
4515e58d
PB
780 /* Assert that the compiler does not smash local variables. */
781 g_assert(cpu == current_cpu);
782 g_assert(cc == CPU_GET_CLASS(cpu));
0448f5f8 783#endif /* buggy compiler */
0ac20318
EC
784#ifndef CONFIG_SOFTMMU
785 tcg_debug_assert(!have_mmap_lock());
786#endif
8d04fb55
JK
787 if (qemu_mutex_iothread_locked()) {
788 qemu_mutex_unlock_iothread();
789 }
e6d86bed
EC
790 qemu_plugin_disable_mem_helpers(cpu);
791
8fd3a9b8 792 assert_no_pages_locked();
4515e58d
PB
793 }
794
795 /* if an exception is pending, we execute it here */
796 while (!cpu_handle_exception(cpu, &ret)) {
797 TranslationBlock *last_tb = NULL;
798 int tb_exit = 0;
799
800 while (!cpu_handle_interrupt(cpu, &last_tb)) {
9b990ee5
RH
801 uint32_t cflags = cpu->cflags_next_tb;
802 TranslationBlock *tb;
803
804 /* When requested, use an exact setting for cflags for the next
805 execution. This is used for icount, precise smc, and stop-
806 after-access watchpoints. Since this request should never
807 have CF_INVALID set, -1 is a convenient invalid value that
808 does not require tcg headers for cpu_common_reset. */
809 if (cflags == -1) {
810 cflags = curr_cflags();
811 } else {
812 cpu->cflags_next_tb = -1;
813 }
814
815 tb = tb_find(cpu, last_tb, tb_exit, cflags);
cfb2d02b 816 cpu_loop_exec_tb(cpu, tb, &last_tb, &tb_exit);
4515e58d
PB
817 /* Try to align the host and virtual clocks
818 if the guest is in advance */
819 align_clocks(&sc, cpu);
7d13299d 820 }
4515e58d 821 }
3fb2ded1 822
035ba06c 823 cpu_exec_exit(cpu);
79e2b9ae 824 rcu_read_unlock();
1057eaa7 825
7d13299d
FB
826 return ret;
827}
740b1759
CF
828
829#ifndef CONFIG_USER_ONLY
830
831void dump_drift_info(void)
832{
833 if (!icount_enabled()) {
834 return;
835 }
836
837 qemu_printf("Host - Guest clock %"PRIi64" ms\n",
8191d368 838 (cpu_get_clock() - icount_get()) / SCALE_MS);
740b1759
CF
839 if (icount_align_option) {
840 qemu_printf("Max guest delay %"PRIi64" ms\n",
841 -max_delay / SCALE_MS);
842 qemu_printf("Max guest advance %"PRIi64" ms\n",
843 max_advance / SCALE_MS);
844 } else {
845 qemu_printf("Max guest delay NA\n");
846 qemu_printf("Max guest advance NA\n");
847 }
848}
849
850#endif /* !CONFIG_USER_ONLY */
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