[J-u-boot.git] / arch / arm / mach-stm32mp / cpu.c

// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
 */

#define LOG_CATEGORY LOGC_ARCH

#include <common.h>
#include <clk.h>
#include <cpu_func.h>
#include <debug_uart.h>
#include <env.h>
#include <init.h>
#include <log.h>
#include <lmb.h>
#include <misc.h>
#include <net.h>
#include <spl.h>
#include <asm/io.h>
#include <asm/arch/stm32.h>
#include <asm/arch/sys_proto.h>
#include <asm/global_data.h>
#include <dm/device.h>
#include <dm/uclass.h>
#include <linux/bitops.h>
#include <linux/printk.h>

/*
 * early TLB into the .data section so that it not get cleared
 * with 16kB allignment (see TTBR0_BASE_ADDR_MASK)
 */
u8 early_tlb[PGTABLE_SIZE] __section(".data") __aligned(0x4000);

struct lmb lmb;

u32 get_bootmode(void)
{
	/* read bootmode from TAMP backup register */
	return (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_MODE_MASK) >>
		    TAMP_BOOT_MODE_SHIFT;
}

/*
 * weak function overidde: set the DDR/SYSRAM executable before to enable the
 * MMU and configure DACR, for early early_enable_caches (SPL or pre-reloc)
 */
void dram_bank_mmu_setup(int bank)
{
	struct bd_info *bd = gd->bd;
	int	i;
	phys_addr_t start;
	phys_size_t size;
	bool use_lmb = false;
	enum dcache_option option;

	if (IS_ENABLED(CONFIG_SPL_BUILD)) {
/* STM32_SYSRAM_BASE exist only when SPL is supported */
#ifdef CONFIG_SPL
		start = ALIGN_DOWN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE);
		size = ALIGN(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE);
#endif
	} else if (gd->flags & GD_FLG_RELOC) {
		/* bd->bi_dram is available only after relocation */
		start = bd->bi_dram[bank].start;
		size =  bd->bi_dram[bank].size;
		use_lmb = true;
	} else {
		/* mark cacheable and executable the beggining of the DDR */
		start = STM32_DDR_BASE;
		size = CONFIG_DDR_CACHEABLE_SIZE;
	}

	for (i = start >> MMU_SECTION_SHIFT;
	     i < (start >> MMU_SECTION_SHIFT) + (size >> MMU_SECTION_SHIFT);
	     i++) {
		option = DCACHE_DEFAULT_OPTION;
		if (use_lmb && lmb_is_reserved_flags(&lmb, i << MMU_SECTION_SHIFT, LMB_NOMAP))
			option = 0; /* INVALID ENTRY in TLB */
		set_section_dcache(i, option);
	}
}
/*
 * initialize the MMU and activate cache in SPL or in U-Boot pre-reloc stage
 * MMU/TLB is updated in enable_caches() for U-Boot after relocation
 * or is deactivated in U-Boot entry function start.S::cpu_init_cp15
 */
static void early_enable_caches(void)
{
	/* I-cache is already enabled in start.S: cpu_init_cp15 */

	if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
		return;

	if (!(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))) {
		gd->arch.tlb_size = PGTABLE_SIZE;
		gd->arch.tlb_addr = (unsigned long)&early_tlb;
	}

	/* enable MMU (default configuration) */
	dcache_enable();
}

/*
 * Early system init
 */
int arch_cpu_init(void)
{
	early_enable_caches();

	/* early armv7 timer init: needed for polling */
	timer_init();

	return 0;
}

/* weak function for SOC specific initialization */
__weak void stm32mp_cpu_init(void)
{
}

int mach_cpu_init(void)
{
	u32 boot_mode;

	stm32mp_cpu_init();

	boot_mode = get_bootmode();

	if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) &&
	    (boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART)
		gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
	else if (IS_ENABLED(CONFIG_DEBUG_UART) && IS_ENABLED(CONFIG_SPL_BUILD))
		debug_uart_init();

	return 0;
}

void enable_caches(void)
{
	/* parse device tree when data cache is still activated */
	lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob);

	/* I-cache is already enabled in start.S: icache_enable() not needed */

	/* deactivate the data cache, early enabled in arch_cpu_init() */
	dcache_disable();
	/*
	 * update MMU after relocation and enable the data cache
	 * warning: the TLB location udpated in board_f.c::reserve_mmu
	 */
	dcache_enable();
}

/* used when CONFIG_DISPLAY_CPUINFO is activated */
int print_cpuinfo(void)
{
	char name[SOC_NAME_SIZE];

	get_soc_name(name);
	printf("CPU: %s\n", name);

	return 0;
}

static void setup_boot_mode(void)
{
	const u32 serial_addr[] = {
		STM32_USART1_BASE,
		STM32_USART2_BASE,
		STM32_USART3_BASE,
		STM32_UART4_BASE,
		STM32_UART5_BASE,
		STM32_USART6_BASE,
		STM32_UART7_BASE,
		STM32_UART8_BASE
	};
	const u32 sdmmc_addr[] = {
		STM32_SDMMC1_BASE,
		STM32_SDMMC2_BASE,
		STM32_SDMMC3_BASE
	};
	char cmd[60];
	u32 boot_ctx = readl(TAMP_BOOT_CONTEXT);
	u32 boot_mode =
		(boot_ctx & TAMP_BOOT_MODE_MASK) >> TAMP_BOOT_MODE_SHIFT;
	unsigned int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1;
	u32 forced_mode = (boot_ctx & TAMP_BOOT_FORCED_MASK);
	struct udevice *dev;

	log_debug("%s: boot_ctx=0x%x => boot_mode=%x, instance=%d forced=%x\n",
		  __func__, boot_ctx, boot_mode, instance, forced_mode);
	switch (boot_mode & TAMP_BOOT_DEVICE_MASK) {
	case BOOT_SERIAL_UART:
		if (instance >= ARRAY_SIZE(serial_addr))
			break;
		/* serial : search associated node in devicetree */
		sprintf(cmd, "serial@%x", serial_addr[instance]);
		if (uclass_get_device_by_name(UCLASS_SERIAL, cmd, &dev)) {
			/* restore console on error */
			if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL))
				gd->flags &= ~(GD_FLG_SILENT |
					       GD_FLG_DISABLE_CONSOLE);
			log_err("uart%d = %s not found in device tree!\n",
				instance + 1, cmd);
			break;
		}
		sprintf(cmd, "%d", dev_seq(dev));
		env_set("boot_device", "serial");
		env_set("boot_instance", cmd);

		/* restore console on uart when not used */
		if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) && gd->cur_serial_dev != dev) {
			gd->flags &= ~(GD_FLG_SILENT |
				       GD_FLG_DISABLE_CONSOLE);
			log_info("serial boot with console enabled!\n");
		}
		break;
	case BOOT_SERIAL_USB:
		env_set("boot_device", "usb");
		env_set("boot_instance", "0");
		break;
	case BOOT_FLASH_SD:
	case BOOT_FLASH_EMMC:
		if (instance >= ARRAY_SIZE(sdmmc_addr))
			break;
		/* search associated sdmmc node in devicetree */
		sprintf(cmd, "mmc@%x", sdmmc_addr[instance]);
		if (uclass_get_device_by_name(UCLASS_MMC, cmd, &dev)) {
			printf("mmc%d = %s not found in device tree!\n",
			       instance, cmd);
			break;
		}
		sprintf(cmd, "%d", dev_seq(dev));
		env_set("boot_device", "mmc");
		env_set("boot_instance", cmd);
		break;
	case BOOT_FLASH_NAND:
		env_set("boot_device", "nand");
		env_set("boot_instance", "0");
		break;
	case BOOT_FLASH_SPINAND:
		env_set("boot_device", "spi-nand");
		env_set("boot_instance", "0");
		break;
	case BOOT_FLASH_NOR:
		env_set("boot_device", "nor");
		env_set("boot_instance", "0");
		break;
	default:
		env_set("boot_device", "invalid");
		env_set("boot_instance", "");
		log_err("unexpected boot mode = %x\n", boot_mode);
		break;
	}

	switch (forced_mode) {
	case BOOT_FASTBOOT:
		log_info("Enter fastboot!\n");
		env_set("preboot", "env set preboot; fastboot 0");
		break;
	case BOOT_STM32PROG:
		env_set("boot_device", "usb");
		env_set("boot_instance", "0");
		break;
	case BOOT_UMS_MMC0:
	case BOOT_UMS_MMC1:
	case BOOT_UMS_MMC2:
		log_info("Enter UMS!\n");
		instance = forced_mode - BOOT_UMS_MMC0;
		sprintf(cmd, "env set preboot; ums 0 mmc %d", instance);
		env_set("preboot", cmd);
		break;
	case BOOT_RECOVERY:
		env_set("preboot", "env set preboot; run altbootcmd");
		break;
	case BOOT_NORMAL:
		break;
	default:
		log_debug("unexpected forced boot mode = %x\n", forced_mode);
		break;
	}

	/* clear TAMP for next reboot */
	clrsetbits_le32(TAMP_BOOT_CONTEXT, TAMP_BOOT_FORCED_MASK, BOOT_NORMAL);
}

/*
 * If there is no MAC address in the environment, then it will be initialized
 * (silently) from the value in the OTP.
 */
__weak int setup_mac_address(void)
{
	int ret;
	int i;
	u32 otp[3];
	uchar enetaddr[6];
	struct udevice *dev;
	int nb_eth, nb_otp, index;

	if (!IS_ENABLED(CONFIG_NET))
		return 0;

	nb_eth = get_eth_nb();

	/* 6 bytes for each MAC addr and 4 bytes for each OTP */
	nb_otp = DIV_ROUND_UP(6 * nb_eth, 4);

	ret = uclass_get_device_by_driver(UCLASS_MISC,
					  DM_DRIVER_GET(stm32mp_bsec),
					  &dev);
	if (ret)
		return ret;

	ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_MAC), otp, 4 * nb_otp);
	if (ret < 0)
		return ret;

	for (index = 0; index < nb_eth; index++) {
		/* MAC already in environment */
		if (eth_env_get_enetaddr_by_index("eth", index, enetaddr))
			continue;

		for (i = 0; i < 6; i++)
			enetaddr[i] = ((uint8_t *)&otp)[i + 6 * index];

		if (!is_valid_ethaddr(enetaddr)) {
			log_err("invalid MAC address %d in OTP %pM\n",
				index, enetaddr);
			return -EINVAL;
		}
		log_debug("OTP MAC address %d = %pM\n", index, enetaddr);
		ret = eth_env_set_enetaddr_by_index("eth", index, enetaddr);
		if (ret) {
			log_err("Failed to set mac address %pM from OTP: %d\n",
				enetaddr, ret);
			return ret;
		}
	}

	return 0;
}

static int setup_serial_number(void)
{
	char serial_string[25];
	u32 otp[3] = {0, 0, 0 };
	struct udevice *dev;
	int ret;

	if (env_get("serial#"))
		return 0;

	ret = uclass_get_device_by_driver(UCLASS_MISC,
					  DM_DRIVER_GET(stm32mp_bsec),
					  &dev);
	if (ret)
		return ret;

	ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_SERIAL),
			otp, sizeof(otp));
	if (ret < 0)
		return ret;

	sprintf(serial_string, "%08X%08X%08X", otp[0], otp[1], otp[2]);
	env_set("serial#", serial_string);

	return 0;
}

__weak void stm32mp_misc_init(void)
{
}

int arch_misc_init(void)
{
	setup_boot_mode();
	setup_mac_address();
	setup_serial_number();
	stm32mp_misc_init();

	return 0;
}

/*
 * Without forcing the ".data" section, this would get saved in ".bss". BSS
 * will be cleared soon after, so it's not suitable.
 */
static uintptr_t rom_api_table __section(".data");
static uintptr_t nt_fw_dtb __section(".data");

/*
 * The ROM gives us the API location in r0 when starting. This is only available
 * during SPL, as there isn't (yet) a mechanism to pass this on to u-boot. Save
 * the FDT address provided by TF-A in r2 at boot time. This function is called
 * from start.S
 */
void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2,
		      unsigned long r3)
{
	if (IS_ENABLED(CONFIG_STM32_ECDSA_VERIFY))
		rom_api_table = r0;

	if (IS_ENABLED(CONFIG_TFABOOT))
		nt_fw_dtb = r2;

	save_boot_params_ret();
}

uintptr_t get_stm32mp_rom_api_table(void)
{
	return rom_api_table;
}

uintptr_t get_stm32mp_bl2_dtb(void)
{
	return nt_fw_dtb;
}

#ifdef CONFIG_SPL_BUILD
void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
{
	typedef void __noreturn (*image_entry_stm32_t)(u32 romapi);
	uintptr_t romapi = get_stm32mp_rom_api_table();

	image_entry_stm32_t image_entry =
		(image_entry_stm32_t)spl_image->entry_point;

	printf("image entry point: 0x%lx\n", spl_image->entry_point);
	image_entry(romapi);
}
#endif
Commit	Line	Data
4549e789	1	// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2514c2d0 PD	2	/*
2514c2d0 PD	3	* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
2514c2d0	4	*/
eb653acd PD	5
	6	#define LOG_CATEGORY LOGC_ARCH
	7
2514c2d0 PD	8	#include <common.h>
2514c2d0 PD	9	#include <clk.h>
9edefc27	10	#include <cpu_func.h>
320d2663	11	#include <debug_uart.h>
9fb625ce	12	#include <env.h>
691d719d	13	#include <init.h>
f7ae49fc	14	#include <log.h>
ade4e042	15	#include <lmb.h>
7f7deb0c	16	#include <misc.h>
90526e9f	17	#include <net.h>
1e94b46f	18	#include <spl.h>
2514c2d0 PD	19	#include <asm/io.h>
2514c2d0 PD	20	#include <asm/arch/stm32.h>
96583cdc	21	#include <asm/arch/sys_proto.h>
401d1c4f	22	#include <asm/global_data.h>
7f7deb0c	23	#include <dm/device.h>
08772f6e	24	#include <dm/uclass.h>
cd93d625	25	#include <linux/bitops.h>
1e94b46f	26	#include <linux/printk.h>
2514c2d0	27
7e8471ca PD	28	/*
	29	* early TLB into the .data section so that it not get cleared
	30	* with 16kB allignment (see TTBR0_BASE_ADDR_MASK)
	31	*/
	32	u8 early_tlb[PGTABLE_SIZE] __section(".data") __aligned(0x4000);
	33
ade4e042 PD	34	struct lmb lmb;
ade4e042 PD	35
7f63c1e6 PD	36	u32 get_bootmode(void)
	37	{
	38	/* read bootmode from TAMP backup register */
	39	return (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_MODE_MASK) >>
	40	TAMP_BOOT_MODE_SHIFT;
08772f6e PD	41	}
08772f6e PD	42
aad84147 PD	43	/*
	44	* weak function overidde: set the DDR/SYSRAM executable before to enable the
	45	* MMU and configure DACR, for early early_enable_caches (SPL or pre-reloc)
	46	*/
	47	void dram_bank_mmu_setup(int bank)
	48	{
	49	struct bd_info *bd = gd->bd;
	50	int i;
	51	phys_addr_t start;
	52	phys_size_t size;
ade4e042 PD	53	bool use_lmb = false;
ade4e042 PD	54	enum dcache_option option;
aad84147 PD	55
aad84147 PD	56	if (IS_ENABLED(CONFIG_SPL_BUILD)) {
960debbe PD	57	/* STM32_SYSRAM_BASE exist only when SPL is supported */
960debbe PD	58	#ifdef CONFIG_SPL
aad84147 PD	59	start = ALIGN_DOWN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE);
aad84147 PD	60	size = ALIGN(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE);
960debbe	61	#endif
aad84147 PD	62	} else if (gd->flags & GD_FLG_RELOC) {
	63	/* bd->bi_dram is available only after relocation */
	64	start = bd->bi_dram[bank].start;
	65	size = bd->bi_dram[bank].size;
ade4e042	66	use_lmb = true;
aad84147 PD	67	} else {
	68	/* mark cacheable and executable the beggining of the DDR */
	69	start = STM32_DDR_BASE;
	70	size = CONFIG_DDR_CACHEABLE_SIZE;
	71	}
	72
	73	for (i = start >> MMU_SECTION_SHIFT;
	74	i < (start >> MMU_SECTION_SHIFT) + (size >> MMU_SECTION_SHIFT);
ade4e042 PD	75	i++) {
	76	option = DCACHE_DEFAULT_OPTION;
	77	if (use_lmb && lmb_is_reserved_flags(&lmb, i << MMU_SECTION_SHIFT, LMB_NOMAP))
	78	option = 0; /* INVALID ENTRY in TLB */
	79	set_section_dcache(i, option);
	80	}
aad84147	81	}
7e8471ca PD	82	/*
	83	* initialize the MMU and activate cache in SPL or in U-Boot pre-reloc stage
	84	* MMU/TLB is updated in enable_caches() for U-Boot after relocation
	85	* or is deactivated in U-Boot entry function start.S::cpu_init_cp15
	86	*/
	87	static void early_enable_caches(void)
	88	{
	89	/* I-cache is already enabled in start.S: cpu_init_cp15 */
	90
	91	if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
	92	return;
	93
23e20b2f PC	94	if (!(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))) {
	95	gd->arch.tlb_size = PGTABLE_SIZE;
	96	gd->arch.tlb_addr = (unsigned long)&early_tlb;
	97	}
7e8471ca	98
aad84147	99	/* enable MMU (default configuration) */
7e8471ca	100	dcache_enable();
7e8471ca PD	101	}
7e8471ca PD	102
08772f6e PD	103	/*
	104	* Early system init
	105	*/
2514c2d0 PD	106	int arch_cpu_init(void)
2514c2d0 PD	107	{
7e8471ca PD	108	early_enable_caches();
7e8471ca PD	109
2514c2d0 PD	110	/* early armv7 timer init: needed for polling */
	111	timer_init();
	112
6df271a7 PD	113	return 0;
	114	}
	115
	116	/* weak function for SOC specific initialization */
	117	__weak void stm32mp_cpu_init(void)
	118	{
	119	}
	120
	121	int mach_cpu_init(void)
	122	{
	123	u32 boot_mode;
	124
	125	stm32mp_cpu_init();
320d2663	126
320d2663 PD	127	boot_mode = get_bootmode();
320d2663 PD	128
5a05af87 PD	129	if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) &&
5a05af87 PD	130	(boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART)
320d2663	131	gd->flags \|= GD_FLG_SILENT \| GD_FLG_DISABLE_CONSOLE;
c8b2eef5	132	else if (IS_ENABLED(CONFIG_DEBUG_UART) && IS_ENABLED(CONFIG_SPL_BUILD))
320d2663	133	debug_uart_init();
2514c2d0 PD	134
	135	return 0;
	136	}
	137
cda3dcb6 PD	138	void enable_caches(void)
cda3dcb6 PD	139	{
ade4e042 PD	140	/* parse device tree when data cache is still activated */
	141	lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob);
	142
7e8471ca PD	143	/* I-cache is already enabled in start.S: icache_enable() not needed */
	144
	145	/* deactivate the data cache, early enabled in arch_cpu_init() */
	146	dcache_disable();
	147	/*
	148	* update MMU after relocation and enable the data cache
	149	* warning: the TLB location udpated in board_f.c::reserve_mmu
	150	*/
cda3dcb6 PD	151	dcache_enable();
	152	}
	153
c8b2eef5	154	/* used when CONFIG_DISPLAY_CPUINFO is activated */
ac5e4d8a PD	155	int print_cpuinfo(void)
	156	{
	157	char name[SOC_NAME_SIZE];
	158
	159	get_soc_name(name);
	160	printf("CPU: %s\n", name);
2514c2d0 PD	161
	162	return 0;
	163	}
2514c2d0	164
08772f6e PD	165	static void setup_boot_mode(void)
08772f6e PD	166	{
7f63c1e6 PD	167	const u32 serial_addr[] = {
	168	STM32_USART1_BASE,
	169	STM32_USART2_BASE,
	170	STM32_USART3_BASE,
	171	STM32_UART4_BASE,
	172	STM32_UART5_BASE,
	173	STM32_USART6_BASE,
	174	STM32_UART7_BASE,
	175	STM32_UART8_BASE
	176	};
3c1057c5 PD	177	const u32 sdmmc_addr[] = {
	178	STM32_SDMMC1_BASE,
	179	STM32_SDMMC2_BASE,
	180	STM32_SDMMC3_BASE
	181	};
08772f6e PD	182	char cmd[60];
	183	u32 boot_ctx = readl(TAMP_BOOT_CONTEXT);
	184	u32 boot_mode =
	185	(boot_ctx & TAMP_BOOT_MODE_MASK) >> TAMP_BOOT_MODE_SHIFT;
e609e131	186	unsigned int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1;
9a2ba283	187	u32 forced_mode = (boot_ctx & TAMP_BOOT_FORCED_MASK);
7f63c1e6	188	struct udevice *dev;
08772f6e	189
eb653acd PD	190	log_debug("%s: boot_ctx=0x%x => boot_mode=%x, instance=%d forced=%x\n",
eb653acd PD	191	__func__, boot_ctx, boot_mode, instance, forced_mode);
08772f6e PD	192	switch (boot_mode & TAMP_BOOT_DEVICE_MASK) {
08772f6e PD	193	case BOOT_SERIAL_UART:
daf07215	194	if (instance >= ARRAY_SIZE(serial_addr))
7f63c1e6	195	break;
f49eb16c	196	/* serial : search associated node in devicetree */
7f63c1e6	197	sprintf(cmd, "serial@%x", serial_addr[instance]);
f49eb16c	198	if (uclass_get_device_by_name(UCLASS_SERIAL, cmd, &dev)) {
b9d5e3aa PD	199	/* restore console on error */
	200	if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL))
	201	gd->flags &= ~(GD_FLG_SILENT \|
	202	GD_FLG_DISABLE_CONSOLE);
cbea7b3e PD	203	log_err("uart%d = %s not found in device tree!\n",
cbea7b3e PD	204	instance + 1, cmd);
7f63c1e6	205	break;
b9d5e3aa	206	}
f49eb16c	207	sprintf(cmd, "%d", dev_seq(dev));
7f63c1e6	208	env_set("boot_device", "serial");
08772f6e	209	env_set("boot_instance", cmd);
7f63c1e6 PD	210
7f63c1e6 PD	211	/* restore console on uart when not used */
5a05af87	212	if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) && gd->cur_serial_dev != dev) {
7f63c1e6 PD	213	gd->flags &= ~(GD_FLG_SILENT \|
7f63c1e6 PD	214	GD_FLG_DISABLE_CONSOLE);
cbea7b3e	215	log_info("serial boot with console enabled!\n");
7f63c1e6	216	}
08772f6e PD	217	break;
	218	case BOOT_SERIAL_USB:
	219	env_set("boot_device", "usb");
	220	env_set("boot_instance", "0");
	221	break;
	222	case BOOT_FLASH_SD:
	223	case BOOT_FLASH_EMMC:
daf07215	224	if (instance >= ARRAY_SIZE(sdmmc_addr))
3c1057c5 PD	225	break;
	226	/* search associated sdmmc node in devicetree */
	227	sprintf(cmd, "mmc@%x", sdmmc_addr[instance]);
	228	if (uclass_get_device_by_name(UCLASS_MMC, cmd, &dev)) {
	229	printf("mmc%d = %s not found in device tree!\n",
	230	instance, cmd);
	231	break;
	232	}
	233	sprintf(cmd, "%d", dev_seq(dev));
08772f6e PD	234	env_set("boot_device", "mmc");
	235	env_set("boot_instance", cmd);
	236	break;
	237	case BOOT_FLASH_NAND:
	238	env_set("boot_device", "nand");
	239	env_set("boot_instance", "0");
	240	break;
b664a745 PD	241	case BOOT_FLASH_SPINAND:
	242	env_set("boot_device", "spi-nand");
	243	env_set("boot_instance", "0");
	244	break;
08772f6e PD	245	case BOOT_FLASH_NOR:
	246	env_set("boot_device", "nor");
	247	env_set("boot_instance", "0");
	248	break;
	249	default:
8b71b20e PD	250	env_set("boot_device", "invalid");
	251	env_set("boot_instance", "");
	252	log_err("unexpected boot mode = %x\n", boot_mode);
08772f6e PD	253	break;
08772f6e PD	254	}
9a2ba283 PD	255
	256	switch (forced_mode) {
	257	case BOOT_FASTBOOT:
cbea7b3e	258	log_info("Enter fastboot!\n");
9a2ba283 PD	259	env_set("preboot", "env set preboot; fastboot 0");
	260	break;
	261	case BOOT_STM32PROG:
	262	env_set("boot_device", "usb");
	263	env_set("boot_instance", "0");
	264	break;
	265	case BOOT_UMS_MMC0:
	266	case BOOT_UMS_MMC1:
	267	case BOOT_UMS_MMC2:
cbea7b3e	268	log_info("Enter UMS!\n");
9a2ba283 PD	269	instance = forced_mode - BOOT_UMS_MMC0;
	270	sprintf(cmd, "env set preboot; ums 0 mmc %d", instance);
	271	env_set("preboot", cmd);
	272	break;
	273	case BOOT_RECOVERY:
	274	env_set("preboot", "env set preboot; run altbootcmd");
	275	break;
	276	case BOOT_NORMAL:
	277	break;
	278	default:
eb653acd	279	log_debug("unexpected forced boot mode = %x\n", forced_mode);
9a2ba283 PD	280	break;
	281	}
	282
	283	/* clear TAMP for next reboot */
	284	clrsetbits_le32(TAMP_BOOT_CONTEXT, TAMP_BOOT_FORCED_MASK, BOOT_NORMAL);
08772f6e PD	285	}
08772f6e PD	286
7f7deb0c PD	287	/*
	288	* If there is no MAC address in the environment, then it will be initialized
	289	* (silently) from the value in the OTP.
	290	*/
e71b9a64	291	__weak int setup_mac_address(void)
7f7deb0c	292	{
7f7deb0c PD	293	int ret;
7f7deb0c PD	294	int i;
46f9eb5d	295	u32 otp[3];
7f7deb0c PD	296	uchar enetaddr[6];
7f7deb0c PD	297	struct udevice *dev;
46f9eb5d	298	int nb_eth, nb_otp, index;
7f7deb0c	299
c8b2eef5 PD	300	if (!IS_ENABLED(CONFIG_NET))
	301	return 0;
	302
46f9eb5d PD	303	nb_eth = get_eth_nb();
	304
	305	/* 6 bytes for each MAC addr and 4 bytes for each OTP */
	306	nb_otp = DIV_ROUND_UP(6 * nb_eth, 4);
7f7deb0c PD	307
7f7deb0c PD	308	ret = uclass_get_device_by_driver(UCLASS_MISC,
65e25bea	309	DM_DRIVER_GET(stm32mp_bsec),
7f7deb0c PD	310	&dev);
	311	if (ret)
	312	return ret;
	313
46f9eb5d	314	ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_MAC), otp, 4 * nb_otp);
8729b1ae	315	if (ret < 0)
7f7deb0c PD	316	return ret;
7f7deb0c PD	317
46f9eb5d PD	318	for (index = 0; index < nb_eth; index++) {
	319	/* MAC already in environment */
	320	if (eth_env_get_enetaddr_by_index("eth", index, enetaddr))
	321	continue;
	322
	323	for (i = 0; i < 6; i++)
	324	enetaddr[i] = ((uint8_t )&otp)[i + 6 index];
7f7deb0c	325
46f9eb5d PD	326	if (!is_valid_ethaddr(enetaddr)) {
	327	log_err("invalid MAC address %d in OTP %pM\n",
	328	index, enetaddr);
	329	return -EINVAL;
	330	}
	331	log_debug("OTP MAC address %d = %pM\n", index, enetaddr);
	332	ret = eth_env_set_enetaddr_by_index("eth", index, enetaddr);
	333	if (ret) {
	334	log_err("Failed to set mac address %pM from OTP: %d\n",
	335	enetaddr, ret);
	336	return ret;
	337	}
7f7deb0c	338	}
7f7deb0c PD	339
	340	return 0;
	341	}
	342
	343	static int setup_serial_number(void)
	344	{
	345	char serial_string[25];
	346	u32 otp[3] = {0, 0, 0 };
	347	struct udevice *dev;
	348	int ret;
	349
	350	if (env_get("serial#"))
	351	return 0;
	352
	353	ret = uclass_get_device_by_driver(UCLASS_MISC,
65e25bea	354	DM_DRIVER_GET(stm32mp_bsec),
7f7deb0c PD	355	&dev);
	356	if (ret)
	357	return ret;
	358
17f1f9b1	359	ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_SERIAL),
7f7deb0c	360	otp, sizeof(otp));
8729b1ae	361	if (ret < 0)
7f7deb0c PD	362	return ret;
7f7deb0c PD	363
8983ba27	364	sprintf(serial_string, "%08X%08X%08X", otp[0], otp[1], otp[2]);
7f7deb0c PD	365	env_set("serial#", serial_string);
	366
	367	return 0;
	368	}
	369
6df271a7	370	__weak void stm32mp_misc_init(void)
2c2d7d6a	371	{
2c2d7d6a MV	372	}
2c2d7d6a MV	373
08772f6e PD	374	int arch_misc_init(void)
	375	{
	376	setup_boot_mode();
7f7deb0c PD	377	setup_mac_address();
7f7deb0c PD	378	setup_serial_number();
6df271a7	379	stm32mp_misc_init();
08772f6e PD	380
	381	return 0;
	382	}
dbeaca79 MV	383
	384	/*
	385	* Without forcing the ".data" section, this would get saved in ".bss". BSS
	386	* will be cleared soon after, so it's not suitable.
	387	*/
	388	static uintptr_t rom_api_table __section(".data");
	389	static uintptr_t nt_fw_dtb __section(".data");
	390
	391	/*
	392	* The ROM gives us the API location in r0 when starting. This is only available
	393	* during SPL, as there isn't (yet) a mechanism to pass this on to u-boot. Save
	394	* the FDT address provided by TF-A in r2 at boot time. This function is called
	395	* from start.S
	396	*/
	397	void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2,
	398	unsigned long r3)
	399	{
	400	if (IS_ENABLED(CONFIG_STM32_ECDSA_VERIFY))
	401	rom_api_table = r0;
	402
	403	if (IS_ENABLED(CONFIG_TFABOOT))
	404	nt_fw_dtb = r2;
	405
	406	save_boot_params_ret();
	407	}
	408
	409	uintptr_t get_stm32mp_rom_api_table(void)
	410	{
	411	return rom_api_table;
	412	}
	413
	414	uintptr_t get_stm32mp_bl2_dtb(void)
	415	{
	416	return nt_fw_dtb;
	417	}
6eea5415 MV	418
	419	#ifdef CONFIG_SPL_BUILD
	420	void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
	421	{
	422	typedef void __noreturn (*image_entry_stm32_t)(u32 romapi);
	423	uintptr_t romapi = get_stm32mp_rom_api_table();
	424
	425	image_entry_stm32_t image_entry =
	426	(image_entry_stm32_t)spl_image->entry_point;
	427
	428	printf("image entry point: 0x%lx\n", spl_image->entry_point);
	429	image_entry(romapi);
	430	}
	431	#endif