[J-u-boot.git] / arch / arm / mach-stm32mp / cpu.c

// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
 */

#define LOG_CATEGORY LOGC_ARCH

#include <common.h>
#include <clk.h>
#include <cpu_func.h>
#include <debug_uart.h>
#include <env.h>
#include <init.h>
#include <log.h>
#include <lmb.h>
#include <misc.h>
#include <net.h>
#include <asm/io.h>
#include <asm/arch/stm32.h>
#include <asm/arch/sys_proto.h>
#include <asm/global_data.h>
#include <dm/device.h>
#include <dm/uclass.h>
#include <linux/bitops.h>

/*
 * early TLB into the .data section so that it not get cleared
 * with 16kB allignment (see TTBR0_BASE_ADDR_MASK)
 */
u8 early_tlb[PGTABLE_SIZE] __section(".data") __aligned(0x4000);

struct lmb lmb;

u32 get_bootmode(void)
{
	/* read bootmode from TAMP backup register */
	return (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_MODE_MASK) >>
		    TAMP_BOOT_MODE_SHIFT;
}

/*
 * weak function overidde: set the DDR/SYSRAM executable before to enable the
 * MMU and configure DACR, for early early_enable_caches (SPL or pre-reloc)
 */
void dram_bank_mmu_setup(int bank)
{
	struct bd_info *bd = gd->bd;
	int	i;
	phys_addr_t start;
	phys_size_t size;
	bool use_lmb = false;
	enum dcache_option option;

	if (IS_ENABLED(CONFIG_SPL_BUILD)) {
/* STM32_SYSRAM_BASE exist only when SPL is supported */
#ifdef CONFIG_SPL
		start = ALIGN_DOWN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE);
		size = ALIGN(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE);
#endif
	} else if (gd->flags & GD_FLG_RELOC) {
		/* bd->bi_dram is available only after relocation */
		start = bd->bi_dram[bank].start;
		size =  bd->bi_dram[bank].size;
		use_lmb = true;
	} else {
		/* mark cacheable and executable the beggining of the DDR */
		start = STM32_DDR_BASE;
		size = CONFIG_DDR_CACHEABLE_SIZE;
	}

	for (i = start >> MMU_SECTION_SHIFT;
	     i < (start >> MMU_SECTION_SHIFT) + (size >> MMU_SECTION_SHIFT);
	     i++) {
		option = DCACHE_DEFAULT_OPTION;
		if (use_lmb && lmb_is_reserved_flags(&lmb, i << MMU_SECTION_SHIFT, LMB_NOMAP))
			option = 0; /* INVALID ENTRY in TLB */
		set_section_dcache(i, option);
	}
}
/*
 * initialize the MMU and activate cache in SPL or in U-Boot pre-reloc stage
 * MMU/TLB is updated in enable_caches() for U-Boot after relocation
 * or is deactivated in U-Boot entry function start.S::cpu_init_cp15
 */
static void early_enable_caches(void)
{
	/* I-cache is already enabled in start.S: cpu_init_cp15 */

	if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
		return;

	if (!(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))) {
		gd->arch.tlb_size = PGTABLE_SIZE;
		gd->arch.tlb_addr = (unsigned long)&early_tlb;
	}

	/* enable MMU (default configuration) */
	dcache_enable();
}

/*
 * Early system init
 */
int arch_cpu_init(void)
{
	early_enable_caches();

	/* early armv7 timer init: needed for polling */
	timer_init();

	return 0;
}

/* weak function for SOC specific initialization */
__weak void stm32mp_cpu_init(void)
{
}

int mach_cpu_init(void)
{
	u32 boot_mode;

	stm32mp_cpu_init();

	boot_mode = get_bootmode();

	if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) &&
	    (boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART)
		gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
	else if (IS_ENABLED(CONFIG_DEBUG_UART) && IS_ENABLED(CONFIG_SPL_BUILD))
		debug_uart_init();

	return 0;
}

void enable_caches(void)
{
	/* parse device tree when data cache is still activated */
	lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob);

	/* I-cache is already enabled in start.S: icache_enable() not needed */

	/* deactivate the data cache, early enabled in arch_cpu_init() */
	dcache_disable();
	/*
	 * update MMU after relocation and enable the data cache
	 * warning: the TLB location udpated in board_f.c::reserve_mmu
	 */
	dcache_enable();
}

/* used when CONFIG_DISPLAY_CPUINFO is activated */
int print_cpuinfo(void)
{
	char name[SOC_NAME_SIZE];

	get_soc_name(name);
	printf("CPU: %s\n", name);

	return 0;
}

static void setup_boot_mode(void)
{
	const u32 serial_addr[] = {
		STM32_USART1_BASE,
		STM32_USART2_BASE,
		STM32_USART3_BASE,
		STM32_UART4_BASE,
		STM32_UART5_BASE,
		STM32_USART6_BASE,
		STM32_UART7_BASE,
		STM32_UART8_BASE
	};
	const u32 sdmmc_addr[] = {
		STM32_SDMMC1_BASE,
		STM32_SDMMC2_BASE,
		STM32_SDMMC3_BASE
	};
	char cmd[60];
	u32 boot_ctx = readl(TAMP_BOOT_CONTEXT);
	u32 boot_mode =
		(boot_ctx & TAMP_BOOT_MODE_MASK) >> TAMP_BOOT_MODE_SHIFT;
	unsigned int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1;
	u32 forced_mode = (boot_ctx & TAMP_BOOT_FORCED_MASK);
	struct udevice *dev;

	log_debug("%s: boot_ctx=0x%x => boot_mode=%x, instance=%d forced=%x\n",
		  __func__, boot_ctx, boot_mode, instance, forced_mode);
	switch (boot_mode & TAMP_BOOT_DEVICE_MASK) {
	case BOOT_SERIAL_UART:
		if (instance > ARRAY_SIZE(serial_addr))
			break;
		/* serial : search associated node in devicetree */
		sprintf(cmd, "serial@%x", serial_addr[instance]);
		if (uclass_get_device_by_name(UCLASS_SERIAL, cmd, &dev)) {
			/* restore console on error */
			if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL))
				gd->flags &= ~(GD_FLG_SILENT |
					       GD_FLG_DISABLE_CONSOLE);
			log_err("uart%d = %s not found in device tree!\n",
				instance + 1, cmd);
			break;
		}
		sprintf(cmd, "%d", dev_seq(dev));
		env_set("boot_device", "serial");
		env_set("boot_instance", cmd);

		/* restore console on uart when not used */
		if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) && gd->cur_serial_dev != dev) {
			gd->flags &= ~(GD_FLG_SILENT |
				       GD_FLG_DISABLE_CONSOLE);
			log_info("serial boot with console enabled!\n");
		}
		break;
	case BOOT_SERIAL_USB:
		env_set("boot_device", "usb");
		env_set("boot_instance", "0");
		break;
	case BOOT_FLASH_SD:
	case BOOT_FLASH_EMMC:
		if (instance > ARRAY_SIZE(sdmmc_addr))
			break;
		/* search associated sdmmc node in devicetree */
		sprintf(cmd, "mmc@%x", sdmmc_addr[instance]);
		if (uclass_get_device_by_name(UCLASS_MMC, cmd, &dev)) {
			printf("mmc%d = %s not found in device tree!\n",
			       instance, cmd);
			break;
		}
		sprintf(cmd, "%d", dev_seq(dev));
		env_set("boot_device", "mmc");
		env_set("boot_instance", cmd);
		break;
	case BOOT_FLASH_NAND:
		env_set("boot_device", "nand");
		env_set("boot_instance", "0");
		break;
	case BOOT_FLASH_SPINAND:
		env_set("boot_device", "spi-nand");
		env_set("boot_instance", "0");
		break;
	case BOOT_FLASH_NOR:
		env_set("boot_device", "nor");
		env_set("boot_instance", "0");
		break;
	default:
		env_set("boot_device", "invalid");
		env_set("boot_instance", "");
		log_err("unexpected boot mode = %x\n", boot_mode);
		break;
	}

	switch (forced_mode) {
	case BOOT_FASTBOOT:
		log_info("Enter fastboot!\n");
		env_set("preboot", "env set preboot; fastboot 0");
		break;
	case BOOT_STM32PROG:
		env_set("boot_device", "usb");
		env_set("boot_instance", "0");
		break;
	case BOOT_UMS_MMC0:
	case BOOT_UMS_MMC1:
	case BOOT_UMS_MMC2:
		log_info("Enter UMS!\n");
		instance = forced_mode - BOOT_UMS_MMC0;
		sprintf(cmd, "env set preboot; ums 0 mmc %d", instance);
		env_set("preboot", cmd);
		break;
	case BOOT_RECOVERY:
		env_set("preboot", "env set preboot; run altbootcmd");
		break;
	case BOOT_NORMAL:
		break;
	default:
		log_debug("unexpected forced boot mode = %x\n", forced_mode);
		break;
	}

	/* clear TAMP for next reboot */
	clrsetbits_le32(TAMP_BOOT_CONTEXT, TAMP_BOOT_FORCED_MASK, BOOT_NORMAL);
}

/*
 * If there is no MAC address in the environment, then it will be initialized
 * (silently) from the value in the OTP.
 */
__weak int setup_mac_address(void)
{
	int ret;
	int i;
	u32 otp[3];
	uchar enetaddr[6];
	struct udevice *dev;
	int nb_eth, nb_otp, index;

	if (!IS_ENABLED(CONFIG_NET))
		return 0;

	nb_eth = get_eth_nb();

	/* 6 bytes for each MAC addr and 4 bytes for each OTP */
	nb_otp = DIV_ROUND_UP(6 * nb_eth, 4);

	ret = uclass_get_device_by_driver(UCLASS_MISC,
					  DM_DRIVER_GET(stm32mp_bsec),
					  &dev);
	if (ret)
		return ret;

	ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_MAC), otp, 4 * nb_otp);
	if (ret < 0)
		return ret;

	for (index = 0; index < nb_eth; index++) {
		/* MAC already in environment */
		if (eth_env_get_enetaddr_by_index("eth", index, enetaddr))
			continue;

		for (i = 0; i < 6; i++)
			enetaddr[i] = ((uint8_t *)&otp)[i + 6 * index];

		if (!is_valid_ethaddr(enetaddr)) {
			log_err("invalid MAC address %d in OTP %pM\n",
				index, enetaddr);
			return -EINVAL;
		}
		log_debug("OTP MAC address %d = %pM\n", index, enetaddr);
		ret = eth_env_set_enetaddr_by_index("eth", index, enetaddr);
		if (ret) {
			log_err("Failed to set mac address %pM from OTP: %d\n",
				enetaddr, ret);
			return ret;
		}
	}

	return 0;
}

static int setup_serial_number(void)
{
	char serial_string[25];
	u32 otp[3] = {0, 0, 0 };
	struct udevice *dev;
	int ret;

	if (env_get("serial#"))
		return 0;

	ret = uclass_get_device_by_driver(UCLASS_MISC,
					  DM_DRIVER_GET(stm32mp_bsec),
					  &dev);
	if (ret)
		return ret;

	ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_SERIAL),
			otp, sizeof(otp));
	if (ret < 0)
		return ret;

	sprintf(serial_string, "%08X%08X%08X", otp[0], otp[1], otp[2]);
	env_set("serial#", serial_string);

	return 0;
}

__weak void stm32mp_misc_init(void)
{
}

int arch_misc_init(void)
{
	setup_boot_mode();
	setup_mac_address();
	setup_serial_number();
	stm32mp_misc_init();

	return 0;
}

/*
 * Without forcing the ".data" section, this would get saved in ".bss". BSS
 * will be cleared soon after, so it's not suitable.
 */
static uintptr_t rom_api_table __section(".data");
static uintptr_t nt_fw_dtb __section(".data");

/*
 * The ROM gives us the API location in r0 when starting. This is only available
 * during SPL, as there isn't (yet) a mechanism to pass this on to u-boot. Save
 * the FDT address provided by TF-A in r2 at boot time. This function is called
 * from start.S
 */
void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2,
		      unsigned long r3)
{
	if (IS_ENABLED(CONFIG_STM32_ECDSA_VERIFY))
		rom_api_table = r0;

	if (IS_ENABLED(CONFIG_TFABOOT))
		nt_fw_dtb = r2;

	save_boot_params_ret();
}

uintptr_t get_stm32mp_rom_api_table(void)
{
	return rom_api_table;
}

uintptr_t get_stm32mp_bl2_dtb(void)
{
	return nt_fw_dtb;
}
Commit	Line	Data
4549e789	1	// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2514c2d0 PD	2	/*
2514c2d0 PD	3	* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
2514c2d0	4	*/
eb653acd PD	5
	6	#define LOG_CATEGORY LOGC_ARCH
	7
2514c2d0 PD	8	#include <common.h>
2514c2d0 PD	9	#include <clk.h>
9edefc27	10	#include <cpu_func.h>
320d2663	11	#include <debug_uart.h>
9fb625ce	12	#include <env.h>
691d719d	13	#include <init.h>
f7ae49fc	14	#include <log.h>
ade4e042	15	#include <lmb.h>
7f7deb0c	16	#include <misc.h>
90526e9f	17	#include <net.h>
2514c2d0 PD	18	#include <asm/io.h>
2514c2d0 PD	19	#include <asm/arch/stm32.h>
96583cdc	20	#include <asm/arch/sys_proto.h>
401d1c4f	21	#include <asm/global_data.h>
7f7deb0c	22	#include <dm/device.h>
08772f6e	23	#include <dm/uclass.h>
cd93d625	24	#include <linux/bitops.h>
2514c2d0	25
7e8471ca PD	26	/*
	27	* early TLB into the .data section so that it not get cleared
	28	* with 16kB allignment (see TTBR0_BASE_ADDR_MASK)
	29	*/
	30	u8 early_tlb[PGTABLE_SIZE] __section(".data") __aligned(0x4000);
	31
ade4e042 PD	32	struct lmb lmb;
ade4e042 PD	33
7f63c1e6 PD	34	u32 get_bootmode(void)
	35	{
	36	/* read bootmode from TAMP backup register */
	37	return (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_MODE_MASK) >>
	38	TAMP_BOOT_MODE_SHIFT;
08772f6e PD	39	}
08772f6e PD	40
aad84147 PD	41	/*
	42	* weak function overidde: set the DDR/SYSRAM executable before to enable the
	43	* MMU and configure DACR, for early early_enable_caches (SPL or pre-reloc)
	44	*/
	45	void dram_bank_mmu_setup(int bank)
	46	{
	47	struct bd_info *bd = gd->bd;
	48	int i;
	49	phys_addr_t start;
	50	phys_size_t size;
ade4e042 PD	51	bool use_lmb = false;
ade4e042 PD	52	enum dcache_option option;
aad84147 PD	53
aad84147 PD	54	if (IS_ENABLED(CONFIG_SPL_BUILD)) {
960debbe PD	55	/* STM32_SYSRAM_BASE exist only when SPL is supported */
960debbe PD	56	#ifdef CONFIG_SPL
aad84147 PD	57	start = ALIGN_DOWN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE);
aad84147 PD	58	size = ALIGN(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE);
960debbe	59	#endif
aad84147 PD	60	} else if (gd->flags & GD_FLG_RELOC) {
	61	/* bd->bi_dram is available only after relocation */
	62	start = bd->bi_dram[bank].start;
	63	size = bd->bi_dram[bank].size;
ade4e042	64	use_lmb = true;
aad84147 PD	65	} else {
	66	/* mark cacheable and executable the beggining of the DDR */
	67	start = STM32_DDR_BASE;
	68	size = CONFIG_DDR_CACHEABLE_SIZE;
	69	}
	70
	71	for (i = start >> MMU_SECTION_SHIFT;
	72	i < (start >> MMU_SECTION_SHIFT) + (size >> MMU_SECTION_SHIFT);
ade4e042 PD	73	i++) {
	74	option = DCACHE_DEFAULT_OPTION;
	75	if (use_lmb && lmb_is_reserved_flags(&lmb, i << MMU_SECTION_SHIFT, LMB_NOMAP))
	76	option = 0; /* INVALID ENTRY in TLB */
	77	set_section_dcache(i, option);
	78	}
aad84147	79	}
7e8471ca PD	80	/*
	81	* initialize the MMU and activate cache in SPL or in U-Boot pre-reloc stage
	82	* MMU/TLB is updated in enable_caches() for U-Boot after relocation
	83	* or is deactivated in U-Boot entry function start.S::cpu_init_cp15
	84	*/
	85	static void early_enable_caches(void)
	86	{
	87	/* I-cache is already enabled in start.S: cpu_init_cp15 */
	88
	89	if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
	90	return;
	91
23e20b2f PC	92	if (!(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))) {
	93	gd->arch.tlb_size = PGTABLE_SIZE;
	94	gd->arch.tlb_addr = (unsigned long)&early_tlb;
	95	}
7e8471ca	96
aad84147	97	/* enable MMU (default configuration) */
7e8471ca	98	dcache_enable();
7e8471ca PD	99	}
7e8471ca PD	100
08772f6e PD	101	/*
	102	* Early system init
	103	*/
2514c2d0 PD	104	int arch_cpu_init(void)
2514c2d0 PD	105	{
7e8471ca PD	106	early_enable_caches();
7e8471ca PD	107
2514c2d0 PD	108	/* early armv7 timer init: needed for polling */
	109	timer_init();
	110
6df271a7 PD	111	return 0;
	112	}
	113
	114	/* weak function for SOC specific initialization */
	115	__weak void stm32mp_cpu_init(void)
	116	{
	117	}
	118
	119	int mach_cpu_init(void)
	120	{
	121	u32 boot_mode;
	122
	123	stm32mp_cpu_init();
320d2663	124
320d2663 PD	125	boot_mode = get_bootmode();
320d2663 PD	126
5a05af87 PD	127	if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) &&
5a05af87 PD	128	(boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART)
320d2663	129	gd->flags \|= GD_FLG_SILENT \| GD_FLG_DISABLE_CONSOLE;
c8b2eef5	130	else if (IS_ENABLED(CONFIG_DEBUG_UART) && IS_ENABLED(CONFIG_SPL_BUILD))
320d2663	131	debug_uart_init();
2514c2d0 PD	132
	133	return 0;
	134	}
	135
cda3dcb6 PD	136	void enable_caches(void)
cda3dcb6 PD	137	{
ade4e042 PD	138	/* parse device tree when data cache is still activated */
	139	lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob);
	140
7e8471ca PD	141	/* I-cache is already enabled in start.S: icache_enable() not needed */
	142
	143	/* deactivate the data cache, early enabled in arch_cpu_init() */
	144	dcache_disable();
	145	/*
	146	* update MMU after relocation and enable the data cache
	147	* warning: the TLB location udpated in board_f.c::reserve_mmu
	148	*/
cda3dcb6 PD	149	dcache_enable();
	150	}
	151
c8b2eef5	152	/* used when CONFIG_DISPLAY_CPUINFO is activated */
ac5e4d8a PD	153	int print_cpuinfo(void)
	154	{
	155	char name[SOC_NAME_SIZE];
	156
	157	get_soc_name(name);
	158	printf("CPU: %s\n", name);
2514c2d0 PD	159
	160	return 0;
	161	}
2514c2d0	162
08772f6e PD	163	static void setup_boot_mode(void)
08772f6e PD	164	{
7f63c1e6 PD	165	const u32 serial_addr[] = {
	166	STM32_USART1_BASE,
	167	STM32_USART2_BASE,
	168	STM32_USART3_BASE,
	169	STM32_UART4_BASE,
	170	STM32_UART5_BASE,
	171	STM32_USART6_BASE,
	172	STM32_UART7_BASE,
	173	STM32_UART8_BASE
	174	};
3c1057c5 PD	175	const u32 sdmmc_addr[] = {
	176	STM32_SDMMC1_BASE,
	177	STM32_SDMMC2_BASE,
	178	STM32_SDMMC3_BASE
	179	};
08772f6e PD	180	char cmd[60];
	181	u32 boot_ctx = readl(TAMP_BOOT_CONTEXT);
	182	u32 boot_mode =
	183	(boot_ctx & TAMP_BOOT_MODE_MASK) >> TAMP_BOOT_MODE_SHIFT;
e609e131	184	unsigned int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1;
9a2ba283	185	u32 forced_mode = (boot_ctx & TAMP_BOOT_FORCED_MASK);
7f63c1e6	186	struct udevice *dev;
08772f6e	187
eb653acd PD	188	log_debug("%s: boot_ctx=0x%x => boot_mode=%x, instance=%d forced=%x\n",
eb653acd PD	189	__func__, boot_ctx, boot_mode, instance, forced_mode);
08772f6e PD	190	switch (boot_mode & TAMP_BOOT_DEVICE_MASK) {
08772f6e PD	191	case BOOT_SERIAL_UART:
7f63c1e6 PD	192	if (instance > ARRAY_SIZE(serial_addr))
7f63c1e6 PD	193	break;
f49eb16c	194	/* serial : search associated node in devicetree */
7f63c1e6	195	sprintf(cmd, "serial@%x", serial_addr[instance]);
f49eb16c	196	if (uclass_get_device_by_name(UCLASS_SERIAL, cmd, &dev)) {
b9d5e3aa PD	197	/* restore console on error */
	198	if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL))
	199	gd->flags &= ~(GD_FLG_SILENT \|
	200	GD_FLG_DISABLE_CONSOLE);
cbea7b3e PD	201	log_err("uart%d = %s not found in device tree!\n",
cbea7b3e PD	202	instance + 1, cmd);
7f63c1e6	203	break;
b9d5e3aa	204	}
f49eb16c	205	sprintf(cmd, "%d", dev_seq(dev));
7f63c1e6	206	env_set("boot_device", "serial");
08772f6e	207	env_set("boot_instance", cmd);
7f63c1e6 PD	208
7f63c1e6 PD	209	/* restore console on uart when not used */
5a05af87	210	if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) && gd->cur_serial_dev != dev) {
7f63c1e6 PD	211	gd->flags &= ~(GD_FLG_SILENT \|
7f63c1e6 PD	212	GD_FLG_DISABLE_CONSOLE);
cbea7b3e	213	log_info("serial boot with console enabled!\n");
7f63c1e6	214	}
08772f6e PD	215	break;
	216	case BOOT_SERIAL_USB:
	217	env_set("boot_device", "usb");
	218	env_set("boot_instance", "0");
	219	break;
	220	case BOOT_FLASH_SD:
	221	case BOOT_FLASH_EMMC:
3c1057c5 PD	222	if (instance > ARRAY_SIZE(sdmmc_addr))
	223	break;
	224	/* search associated sdmmc node in devicetree */
	225	sprintf(cmd, "mmc@%x", sdmmc_addr[instance]);
	226	if (uclass_get_device_by_name(UCLASS_MMC, cmd, &dev)) {
	227	printf("mmc%d = %s not found in device tree!\n",
	228	instance, cmd);
	229	break;
	230	}
	231	sprintf(cmd, "%d", dev_seq(dev));
08772f6e PD	232	env_set("boot_device", "mmc");
	233	env_set("boot_instance", cmd);
	234	break;
	235	case BOOT_FLASH_NAND:
	236	env_set("boot_device", "nand");
	237	env_set("boot_instance", "0");
	238	break;
b664a745 PD	239	case BOOT_FLASH_SPINAND:
	240	env_set("boot_device", "spi-nand");
	241	env_set("boot_instance", "0");
	242	break;
08772f6e PD	243	case BOOT_FLASH_NOR:
	244	env_set("boot_device", "nor");
	245	env_set("boot_instance", "0");
	246	break;
	247	default:
8b71b20e PD	248	env_set("boot_device", "invalid");
	249	env_set("boot_instance", "");
	250	log_err("unexpected boot mode = %x\n", boot_mode);
08772f6e PD	251	break;
08772f6e PD	252	}
9a2ba283 PD	253
	254	switch (forced_mode) {
	255	case BOOT_FASTBOOT:
cbea7b3e	256	log_info("Enter fastboot!\n");
9a2ba283 PD	257	env_set("preboot", "env set preboot; fastboot 0");
	258	break;
	259	case BOOT_STM32PROG:
	260	env_set("boot_device", "usb");
	261	env_set("boot_instance", "0");
	262	break;
	263	case BOOT_UMS_MMC0:
	264	case BOOT_UMS_MMC1:
	265	case BOOT_UMS_MMC2:
cbea7b3e	266	log_info("Enter UMS!\n");
9a2ba283 PD	267	instance = forced_mode - BOOT_UMS_MMC0;
	268	sprintf(cmd, "env set preboot; ums 0 mmc %d", instance);
	269	env_set("preboot", cmd);
	270	break;
	271	case BOOT_RECOVERY:
	272	env_set("preboot", "env set preboot; run altbootcmd");
	273	break;
	274	case BOOT_NORMAL:
	275	break;
	276	default:
eb653acd	277	log_debug("unexpected forced boot mode = %x\n", forced_mode);
9a2ba283 PD	278	break;
	279	}
	280
	281	/* clear TAMP for next reboot */
	282	clrsetbits_le32(TAMP_BOOT_CONTEXT, TAMP_BOOT_FORCED_MASK, BOOT_NORMAL);
08772f6e PD	283	}
08772f6e PD	284
7f7deb0c PD	285	/*
	286	* If there is no MAC address in the environment, then it will be initialized
	287	* (silently) from the value in the OTP.
	288	*/
e71b9a64	289	__weak int setup_mac_address(void)
7f7deb0c	290	{
7f7deb0c PD	291	int ret;
7f7deb0c PD	292	int i;
46f9eb5d	293	u32 otp[3];
7f7deb0c PD	294	uchar enetaddr[6];
7f7deb0c PD	295	struct udevice *dev;
46f9eb5d	296	int nb_eth, nb_otp, index;
7f7deb0c	297
c8b2eef5 PD	298	if (!IS_ENABLED(CONFIG_NET))
	299	return 0;
	300
46f9eb5d PD	301	nb_eth = get_eth_nb();
	302
	303	/* 6 bytes for each MAC addr and 4 bytes for each OTP */
	304	nb_otp = DIV_ROUND_UP(6 * nb_eth, 4);
7f7deb0c PD	305
7f7deb0c PD	306	ret = uclass_get_device_by_driver(UCLASS_MISC,
65e25bea	307	DM_DRIVER_GET(stm32mp_bsec),
7f7deb0c PD	308	&dev);
	309	if (ret)
	310	return ret;
	311
46f9eb5d	312	ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_MAC), otp, 4 * nb_otp);
8729b1ae	313	if (ret < 0)
7f7deb0c PD	314	return ret;
7f7deb0c PD	315
46f9eb5d PD	316	for (index = 0; index < nb_eth; index++) {
	317	/* MAC already in environment */
	318	if (eth_env_get_enetaddr_by_index("eth", index, enetaddr))
	319	continue;
	320
	321	for (i = 0; i < 6; i++)
	322	enetaddr[i] = ((uint8_t )&otp)[i + 6 index];
7f7deb0c	323
46f9eb5d PD	324	if (!is_valid_ethaddr(enetaddr)) {
	325	log_err("invalid MAC address %d in OTP %pM\n",
	326	index, enetaddr);
	327	return -EINVAL;
	328	}
	329	log_debug("OTP MAC address %d = %pM\n", index, enetaddr);
	330	ret = eth_env_set_enetaddr_by_index("eth", index, enetaddr);
	331	if (ret) {
	332	log_err("Failed to set mac address %pM from OTP: %d\n",
	333	enetaddr, ret);
	334	return ret;
	335	}
7f7deb0c	336	}
7f7deb0c PD	337
	338	return 0;
	339	}
	340
	341	static int setup_serial_number(void)
	342	{
	343	char serial_string[25];
	344	u32 otp[3] = {0, 0, 0 };
	345	struct udevice *dev;
	346	int ret;
	347
	348	if (env_get("serial#"))
	349	return 0;
	350
	351	ret = uclass_get_device_by_driver(UCLASS_MISC,
65e25bea	352	DM_DRIVER_GET(stm32mp_bsec),
7f7deb0c PD	353	&dev);
	354	if (ret)
	355	return ret;
	356
17f1f9b1	357	ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_SERIAL),
7f7deb0c	358	otp, sizeof(otp));
8729b1ae	359	if (ret < 0)
7f7deb0c PD	360	return ret;
7f7deb0c PD	361
8983ba27	362	sprintf(serial_string, "%08X%08X%08X", otp[0], otp[1], otp[2]);
7f7deb0c PD	363	env_set("serial#", serial_string);
	364
	365	return 0;
	366	}
	367
6df271a7	368	__weak void stm32mp_misc_init(void)
2c2d7d6a	369	{
2c2d7d6a MV	370	}
2c2d7d6a MV	371
08772f6e PD	372	int arch_misc_init(void)
	373	{
	374	setup_boot_mode();
7f7deb0c PD	375	setup_mac_address();
7f7deb0c PD	376	setup_serial_number();
6df271a7	377	stm32mp_misc_init();
08772f6e PD	378
	379	return 0;
	380	}
dbeaca79 MV	381
	382	/*
	383	* Without forcing the ".data" section, this would get saved in ".bss". BSS
	384	* will be cleared soon after, so it's not suitable.
	385	*/
	386	static uintptr_t rom_api_table __section(".data");
	387	static uintptr_t nt_fw_dtb __section(".data");
	388
	389	/*
	390	* The ROM gives us the API location in r0 when starting. This is only available
	391	* during SPL, as there isn't (yet) a mechanism to pass this on to u-boot. Save
	392	* the FDT address provided by TF-A in r2 at boot time. This function is called
	393	* from start.S
	394	*/
	395	void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2,
	396	unsigned long r3)
	397	{
	398	if (IS_ENABLED(CONFIG_STM32_ECDSA_VERIFY))
	399	rom_api_table = r0;
	400
	401	if (IS_ENABLED(CONFIG_TFABOOT))
	402	nt_fw_dtb = r2;
	403
	404	save_boot_params_ret();
	405	}
	406
	407	uintptr_t get_stm32mp_rom_api_table(void)
	408	{
	409	return rom_api_table;
	410	}
	411
	412	uintptr_t get_stm32mp_bl2_dtb(void)
	413	{
	414	return nt_fw_dtb;
	415	}