Aparna Patra [Wed, 8 Jan 2025 04:49:39 +0000 (10:19 +0530)]
arm: mach-k3: am62p: Set a53 cpu freq based on speed-grade
The maximum frequency of the A53 CPU on the AM62P depends on the speed
grade of the SoC. This value is hardcoded in the DT for all AM62P
variants, potentially causing specifications to be exceeded. Moreover,
setting a common lower frequency for all variants increases boot time.
To prevent these issues, modify the DT at runtime from the R5 core to
adjust the A53 CPU frequency.
Aparna Patra [Wed, 8 Jan 2025 04:49:38 +0000 (10:19 +0530)]
arm: mach-k3: am62p: Fixup a53 max cpu frequency by speed-grade
AM62P SoC has multiple speed grades. Add function to delete
non-relevant CPU frequency nodes, based on the information
retrieved from hardware registers. Fastest grade's maximum
frequency also depends on PMIC voltage, hence to simplify
implementation use the smaller value.
Aparna Patra [Wed, 8 Jan 2025 04:49:37 +0000 (10:19 +0530)]
arm: mach-k3: am62p: Fixup thermal zone critical points
Read the max temperature for the SoC temperature grade from the hardware
and modify the critical trip nodes on each thermal zone of FDT at
runtime so they are correct with the hardware value for its grade.
Aparna Patra [Wed, 8 Jan 2025 04:49:36 +0000 (10:19 +0530)]
arm: mach-k3: am62p: Fixup CPU core, CAN-FD and Video-codec nodes in fdt
AM62P SOC is available in multiple variants:
-CPU cores (Cortex-A) AM62Px1 (1 core),
AM62Px2 (2 cores), AM62Px4 (4 cores)
-With and without CAN-FD & Video-codec support
Remove the relevant FDT nodes by reading the actual configuration
from the SoC registers, with that change it is possible to have a single
dts/dtb file handling the different variant at runtime.
board: ti: Pull redundant DDR functions to a common location and Fixup DDR size when ECC is enabled
As there are few redundant functions in board/ti/*/evm.c files, pull
them to a common location of access to reuse and include the common file
to access the functions.
Call k3-ddrss driver through fixup_ddr_driver_for_ecc() to fixup the
device tree and resize the available amount of DDR, if ECC is enabled.
Otherwise, fixup the device tree using the regular
fdt_fixup_memory_banks().
Also call dram_init_banksize() after every call to
fixup_ddr_driver_for_ecc() is made so that gd->bd is populated
correctly.
Ensure that fixup_ddr_driver_for_ecc() is agnostic to the number of DDR
controllers present.
The functionality of enabling Inline ECC is now controlled by
CONFIG_K3_INLINE_ECC. So, remove the support for 'ti,ecc-enable'
property to avoid redundancy and to ensure the Inline ECC feature is
mananged through build-time config.
Setup the ECC region's start and range using the device private data,
ddrss->ddr_bank_base[0] and ddrss->ddr_ram_size. Also, move start and
range of ECC regions from 32 bits to 64 bits to accommodate for
DDR greater than or equal to 4GB.
ram: k3-ddrss: Add k3_ddrss_ddr_bank_base_size_calc() to solve 'calculations restricted to 32 bits' issue
As R5 is a 32 bit processor, the RAM banks' base and size calculation
is restricted to 32 bits, which results in wrong values if bank's base
is greater than 32 bits or bank's size is greater than or equal to 4GB.
So, add k3_ddrss_ddr_bank_base_size_calc() to get the base address and
size of RAM's banks from the device tree memory node, and store in a
64 bit device private data which can be used for ECC reserved memory
calculation, Setting ECC range and Fixing up bank size in device tree
when ECC is enabled.
Georgi Vlaev [Mon, 6 Jan 2025 09:07:01 +0000 (14:37 +0530)]
ram: k3-ddrss: Use the DDR controller BIST engine for ECC priming
The 1-bit inline ECC support in TI's DDRSS bridge requires
the configured memory regions to be preloaded with a pattern
before use. This is done by the k3-ddrss driver from the
R5 SPL in a 'for' loop. It takes around 10 seconds to fill
2GB of memory, for example. Memset can cut the time in half
and using DMA currently yields a similar result.
The BIST engine of DDR controller provides support for
initializing any memory region with a pattern. This
bypasses the DDRSS bridge, so the required inline ECC
data is not computed and populated in the memory. For
some values like zero, the computed ECC syndrome is also
zero and we can use these values to preload the memory
from the DDR controller, without the assistance of the
bridge.
The registers involved in the process are described in the
'DDR controller registers' topic in [1] AM62 and [2] J721E
reference manuals.
The patch replaces the 'for' loop memory fill function with
the BIST memory initialization procedure. This cuts the time
to preload the 2GB memory from 10 seconds down to 1 second.
The bist preload function uses the lpddr4 APIs in the k3-ddrss,
so this is compatible with devices with both 16-bit LPDDR4 and
32-bit LPDDR4 interfaces (e.g J721E).
The first patch modifies the function documentation style in the
include/fdt_support.h file to comply with kernel-doc requirements.
The second patch modifies the board_fdt_chosen_bootargs() function to
return a const char* type. This change clarifies to the caller that the
returned string should neither be freed nor modified. It aligns with the
existing fdt_setprop() function, which already utilizes a const char*
parameter. This promotes consistency within the codebase and enhances
code safety by preventing unintended modifications to the returned
string.
The third patch addresses the need for flexibility in providing kernel
command line arguments (bootargs) for different kernel images within the
same U-Boot environment. It introduces a read-only (RO) fdt_property
argument to the board_fdt_chosen_bootargs() function, allowing access to
the original chosen/bootargs data. This is crucial for scenarios where
different kernel versions require distinct console setups (e.g., ttyS0
for vendor kernels and ttyAML0 for upstream kernels). By enabling board
developers to either merge or replace the original bootargs, this
patch enhances the configurability of U-Boot for various kernel
images without relying on outdated configurations like CMDLINE_EXTEND.
Dmitry Rokosov [Thu, 19 Dec 2024 21:42:10 +0000 (00:42 +0300)]
common: fdt: hand over original fdt bootargs into board chosen handler
Sometimes, it is necessary to provide an additional bootargs string to
the kernel command line.
We have a real scenario where one U-Boot blob needs to boot several
kernel images: the vendor-patched kernel image and the latest upstream
kernel image. The Amlogic (Meson architecture) tty driver has different
tty suffixes in these kernels: the vendor uses 'ttySx', while the
upstream implementation uses 'ttyAMLx'. The initial console setup is
provided to the kernel using the kernel command line (bootargs). For the
vendor kernel, we should use 'console=ttyS0,115200', while for the
upstream kernel, it must be 'console=ttyAML0,115200'. This means we have
to use different command line strings depending on the kernel version.
To resolve this issue, we cannot use the CMDLINE_EXTEND kernel
configuration because it is considered legacy and is not supported for
the arm64 architecture. CMDLINE_EXTEND is outdated primarily because we
can provide additional command line strings through the
'chosen/bootargs' FDT node. However, U-Boot uses this node to inject the
U-Boot bootargs environment variable content, which results in U-Boot
silently overriding all data in the 'chosen/bootargs' node. While we do
have the board_fdt_chosen_bootargs() board hook to address such issues,
this function lacks any FDT context, such as the original value of the
'chosen/bootargs' node.
This patch introduces a read-only (RO) fdt_property argument to
board_fdt_chosen_bootargs() to share the original 'chosen/bootargs' data
with the board code. Consequently, the board developer can decide how to
handle this information for their board setup: whether to drop it or
merge it with the bootargs environment.
Dmitry Rokosov [Thu, 19 Dec 2024 21:42:09 +0000 (00:42 +0300)]
fdt_support: board_fdt_chosen_bootargs() should return const char*
It should be structured this way to demonstrate to the caller that
freeing the return value is unnecessary and that the caller cannot
modify it.
The function fdt_setprop() includes a parameter with a const char*
prototype, so it is better to use the const qualifier.
Tom Rini [Tue, 17 Dec 2024 16:22:15 +0000 (10:22 -0600)]
chromebook_coral: Move CONFIG_BLOBLIST_ADDR to CAR
Reading doc/board/google/chromebook_coral.rst we can see that at some
point it was intended to put the bloblist in CAR, rather than DRAM, at
some point during development. This is fine for TPL/SPL stages where we
have very minimal information stored in the bloblist and so we can set
the limit there to 4KiB and then expand it to 196KiB in U-Boot proper so
there's room for ACPI tables and so forth. We also update the
documentation to use the same location for CONFIG_BLOBLIST_ADDR in both
references.
Motivations for changes:
Current SMBIOS library and command-line tool is not fully matching with
the requirements:
1. Missing support for other mandatory types (#7, #9, #16, #17, #19).
2. Only a few platforms support SMBIOS node from the device tree.
3. Values of some fields are hardcoded in the library other than fetching
from the device hardware.
4. Embedded data with dynamic length is not supported (E.g. Contained
Object Handles in Type #2 and Contained Elements in Type #3)
Changes:
1. Refactor the SMBIOS library and command-line tool to better align with
the SMBIOS spec.
2. Create an arch-specific driver for all aarch64-based platforms to fetch
SMBIOS private data from the device hardware (processor and cache).
3. Create a sysinfo driver to poppulate platform SMBIOS private data.
4. Add generic SMBIOS DTS file for arm64 platforms for those common strings
and values which cannot be retrieved from the system registers.
Vendors can create their own SMBIOS node using this as an example.
For those boards without SMBIOS nodes, this DTS file can be included to
have a generic SMBIOS information of the system.
5. Add support for Type #7 (Cache Information) and link its handles to
Type #4.
6. To minimize size-growth for those platforms which have not sufficient
ROM spaces or the platforms which don't need detailed SMBIOS
information, new added fields are only being built when kconfig
GENERATE_SMBIOS_TABLE_VERBOSE is selected.
Once this patch is acceptted, subsequent patch sets will add other missing
types (#9, #16, #17, #19).
Tests:
To test this with QEMU arm64, please follow the guide on dt_qemu.rst to
get a merged DT to run with.
```
qemu-system-aarch64 -machine virt -machine dumpdtb=qemu.dtb
cat <(dtc -I dtb qemu.dtb) <(dtc -I dtb ./dts/dt.dtb | grep -v /dts-v1/) \
| dtc - -o merged.dtb
qemu-system-aarch64 -machine virt -nographic -bios u-boot.bin \
-dtb merged.dtb
```
Raymond Mao [Fri, 6 Dec 2024 22:54:26 +0000 (14:54 -0800)]
cmd: update smbios cmd
Update the cmd according to the changes of the smbios library:
1. Refactor smbios cmd print functions to match the content defined
by the specification.
2. Add new print functions for Type 3, 4 and 7.
3. Remove the fallback string "Not specified" from smbios_get_string,
as the spec requires a NULL output for those undefined strings.
4. Update the test_cmd_smbios_sandbox pytest expected result to
align with the smbios library changes and add new pytest
test_cmd_smbios_sysinfo_verbose to test the verbose smbios
output.
Raymond Mao [Fri, 6 Dec 2024 22:54:25 +0000 (14:54 -0800)]
armv8: Add generic smbios information into the device tree
Add common smbios information that can be used by all armv8
platforms and set it as default for qemu-arm64.
>From now smbios library can load values from here for those fields
doesn't exist in the sysinfo driver.
To run this with QEMU arm64, we need to dump the generated DTB
from QEMU first, merge it with the one we build and then re-run
QEMU with the merged DTB.
```
qemu-system-aarch64 -machine virt -machine dumpdtb=qemu.dtb
cat <(dtc -I dtb qemu.dtb) <(dtc -I dtb ./dts/dt.dtb | \
grep -v /dts-v1/) | dtc - -o merged.dtb
qemu-system-aarch64 -machine virt -nographic -bios u-boot.bin \
-dtb merged.dtb
```
For details please take reference on dt_qemu.rst
Raymond Mao [Fri, 6 Dec 2024 22:54:23 +0000 (14:54 -0800)]
smbios: add detailed smbios information
Add detailed SMBIOS information as following:
1. Missing fields in Type #3 and #4
2. Type #7
Add support to dynamic length of contained object handles and
elements.
As SMBIOS is a fundamental feature which is enabled for all
boards, in order to avoid increasing rom size, all detailed SMBIOS
information is under kconfig GENERATE_SMBIOS_TABLE_VERBOSE.
Board maintainers can determine whether to select this feature.
Raymond Mao [Fri, 6 Dec 2024 22:54:22 +0000 (14:54 -0800)]
smbios: Refactor smbios library
Current smbios library does not fully match to the specification.
It hardcodes values instead of exposing values from the device.
It does not reserve the space to support dynamic length for
contained object handles or elements and misses the handling of
a few of fields.
The refactoring of this patch includes:
1. Expose values from device via sysinfo interface.
2. Replace smbios_add_prop with smbios_add_prop_si to allow getting
string values from sysinfo.
3. Add smbios_get_val_si to get values from sysinfo or device tree.
4. Use sysinfo_get_data to get data area.
5. Reserve the space of contained object handles and elements.
6. Miscellaneous fixes in smbios.
Raymond Mao [Fri, 6 Dec 2024 22:54:21 +0000 (14:54 -0800)]
sysinfo: Add sysinfo driver and data structure for smbios
Add sysinfo driver to retrieve smbios information (Type 4 and 7).
So that the smbios library can use it for getting values from the
hardware platform instead of device tree.
Raymond Mao [Fri, 6 Dec 2024 22:54:18 +0000 (14:54 -0800)]
smbios: Refactor the smbios headfile
Move the smbios field definitions to a separated simple headfile,
which is a prerequisite to be included by dts files.
Add new definitions for cache information.
This patch also includes a few of code optimizations in smbios.
Simon Glass [Wed, 20 Nov 2024 15:36:41 +0000 (08:36 -0700)]
common: Move autoprobe out to board init
Rather than doing autoprobe within the driver model code, move it out to
the board-init code. This makes it clear that it is a separate step from
binding devices.
For now this is always done twice, before and after relocation, but we
should discuss whether it might be possible to drop the post-relocation
probe.
For boards with SPL, the autoprobe is still done there as well.
Note that with this change, autoprobe happens after the
EVT_DM_POST_INIT_R/F events are sent, rather than before.
Neal Frager [Wed, 18 Dec 2024 13:01:29 +0000 (13:01 +0000)]
board: zynqmp: zynqmp-sm-k26-revA: release DP from reset
This releases the DP configuration from reset early on during the boot process
for K26 SOM. It will also avoid the boot hang situation should any attempt be
made to configure the DP registers while it is still in reset.
Fixes the same issue as described by the commit 8b81010a2fe3 ("video:
zynqmp: Add support for reset").
Michal Simek [Mon, 16 Dec 2024 07:52:34 +0000 (08:52 +0100)]
xilinx: Sort OF_LIST and add missing vpk120 and zcu670 platforms
Sort OF_LIST entries and also add missing vpk120 and zcu670 platforms.
Compilation is failing when these DTs are exported via DEVICE_TREE because
binman is not able to create a link for default configuration.
Michal Simek [Wed, 18 Dec 2024 11:40:44 +0000 (12:40 +0100)]
zynqmp: Remove usb init initialization for Kria
USB hub initialization is done by driver introduced by commit 09f557e106ef
("usb: onboard-hub: Add i2c initialization for usb5744 hub") that's why
there is no need to do initialization via variables.
Michal Simek [Thu, 12 Dec 2024 09:41:44 +0000 (10:41 +0100)]
arm64: zynqmp: Sync DTs with Linux v6.13-rc1
Sync zynqmp* DTS files with v6.13-rc1 Linux kernel including three patches
from Sean:
arm64: zynqmp: Enable AMS for all boards
arm64: zynqmp: Expose AMS to userspace as HWMON
arm64: zynqmp: Add thermal zones
Michal Simek [Mon, 6 Jan 2025 09:20:40 +0000 (10:20 +0100)]
arm64: versal: RO multi_boot register in non JTAG bootmode
The main reason for this change is that upstream QEMU has no multiboot
register implemented that's why access to it fails which ends up in CI
failure for our target.
That's why in JTAG bootmode returns 0 which is correct behaviour because
multiboot register is not used in this mode and value should be ignored and
as a side effect it is also fixing CI/Qemu issue.
Also move versal_get_bootmode() to avoid function declaration.
Michal Simek [Thu, 5 Dec 2024 10:38:16 +0000 (11:38 +0100)]
arm64: versal: Support operations around multiboot register
Read multiboot register and show it's value by default.
Also extend logic in dfu_alt_info string generation to support capsule
update for different offsets.
Replace magic numbers in buckval2votl() & buckvolt2val() with macros to
help with clarity and correlate what the numbers correspond to in the
TPS65219 datasheet.
Marek Vasut [Wed, 1 Jan 2025 19:19:04 +0000 (20:19 +0100)]
arm64: Convert core type check macros into inline functions
Turn the core type check macros into inline functions to perform
better type checking on them. The inline functions get optimized
out in case they are not used. Indent the MIDR_PARTNUM_CORTEX_An
macros in preparation for addition of future three-digit cores
and use MIDR_PARTNUM_SHIFT in MIDR_PARTNUM_MASK to be consistent.
The commit 7cec3e701940 ("rockchip: rk3588-nanopc-t6: Add support for
NanoPC-T6 LTS") added support for the LTS variant of NanoPC T6. However,
a board specific -u-boot.dtsi file was never added.
Due to the missing -u-boot.dtsi file the LTS fdt included in the FIT is
never tagged with bootph props.
When ENV_IS_IN_SPI_FLASH is enabled, not enabled in defconfig, the env
can successfully load from SPI flash on the non-LTS variant, something
that does not work on the LTS variant due to missing bootph-some-ram
props in the LTS fdt.
Fix this by adding a LTS -u-boot.dtsi file that just include the non-LTS
-u-boot.dtsi file.
Reported-by: Ricardo Pardini <[email protected]> Fixes: 7cec3e701940 ("rockchip: rk3588-nanopc-t6: Add support for NanoPC-T6 LTS") Signed-off-by: Jonas Karlman <[email protected]> Reviewed-by: Kever Yang <[email protected]>
Jonas Karlman [Thu, 12 Dec 2024 23:57:19 +0000 (23:57 +0000)]
rockchip: rk3399: Drop unneeded bob and kevin board specific code
The IO-domain driver will configure io_vsel and always-on/boot-on
regulators will be enabled based on the board device tree now that
required nodes and Kconfig options is enabled for SPL.
Remove the bob and kevin board specific code from the common rk3399.c,
the IO-domain and regulator driver provide similar functionality.
Jonas Karlman [Thu, 12 Dec 2024 23:57:16 +0000 (23:57 +0000)]
rockchip: rk3399-gru: Enable dcache and signature validation in SPL
With TPL being used to init DRAM, SPL being used to load FIT and the
adjusted FIT payload offset it is now possible to increase the size
limit of SPL to 256 KB and enable uses of dcache and FIT signature
validation.
Drop SPL_SYS_DCACHE_OFF=y to enable use of dcache in SPL.
Drop SPL_FIT_SIGNATURE=n to enable signature validation of FIT in SPL.
Change SPL_MAX_SIZE to 256 KB now that payload offset has moved in SPI
and TF-A may be loaded to 0x40000 in DRAM.
Jonas Karlman [Thu, 12 Dec 2024 23:57:10 +0000 (23:57 +0000)]
rockchip: rk3399-gru: Move SPI flash payload offset for bob and kevin
The BootROM on RK3399 only read the first 2 KB of each 4 KB page from
SPI flash. With current FIT payload offset of 0x40000 this limits the
supported TPL+SPL size to only 128 KB.
Change to use 0xE0000 as FIT payload offset, similar to other RK3399
boards, to allow a maximum size for TPL of 192 KB and SPL of 256 KB.
Jonas Karlman [Thu, 12 Dec 2024 23:57:08 +0000 (23:57 +0000)]
rockchip: rk3399: Fix TPL build of bob and kevin
Building chromebook_bob/kevin with TPL=y ends with a linking error:
arch/arm/mach-rockchip/rk3399/rk3399.o: in function `board_debug_uart_init':
arch/arm/mach-rockchip/rk3399/rk3399.c:148:(.text.board_debug_uart_init+0x34):
undefined reference to `spl_gpio_output'
arch/arm/mach-rockchip/rk3399/rk3399.c:148:(.text.board_debug_uart_init+0x34):
relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `spl_gpio_output'
Daniel Semkowicz [Tue, 26 Nov 2024 08:27:15 +0000 (09:27 +0100)]
board: theobroma-systems: Update TF-A setup steps for RK3588 boards
ddrbin_tool interface has been changed. Additional chip_name argument
is now required to modify ddr binary file. Update documentation
to be consistent with the new interface.
Update BL31 and ROCKCHIP_TPL file paths to match current version
of binaries available in the rkbin repository.
Johan Jonker [Mon, 16 Dec 2024 12:44:32 +0000 (13:44 +0100)]
rockchip: use OF_UPSTREAM for rk3066a/rk3188
The device tree for rk3066a/rk3188 combined is now
available in the /dts/upstream directory.
Use imply OF_UPSTREAM to migrate all rk3066a/rk3188 boards.
FUKAUMI Naoki [Sat, 4 Jan 2025 01:57:03 +0000 (01:57 +0000)]
arm64: dts: rockchip: add Radxa ROCK 5C
Radxa ROCK 5C is a 8K computer for everything[1] using the Rockchip
RK3588S2 chip:
- Rockchip RK3588S2
- Quad A76 and Quad A55 CPU
- 6 TOPS NPU
- up to 32GB LPDDR4x RAM
- eMMC / SPI flash connector
- Micro SD Card slot
- Gigabit ethernet port (supports PoE with add-on PoE HAT)
- WiFi6 / BT5.4
- 1x USB 3.0 Type-A HOST port
- 1x USB 3.0 Type-A OTG port
- 2x USB 2.0 Type-A HOST port
- 1x USB Type-C 5V power port
Sam Edwards [Sat, 4 Jan 2025 01:57:01 +0000 (01:57 +0000)]
arm64: dts: rockchip: Split up RK3588's PCIe pinctrls
These pinctrls manage the low-speed PCIe signals:
- CLKREQ#: An output on the RK3588 (both RC or EP modes), used to
request that external clock-generation circuitry provide a clock.
- PERST#: An input on the RK3588 in EP mode, used to detect a reset
signal from the RC. In RC mode, the hardware does not use this signal:
Linux itself generates it by putting the pin in GPIO mode.
- WAKE#: In EP mode, this is an output; in RC mode, this is an input.
Each of these signals serves a distinct purpose, and more importantly,
PERST# should not be muxed when the RK3588 is in the RC role. Bundling
them together in pinctrl groups prevents proper use: indeed, almost none
of the current board-specific .dts files make any use of them.
(Exception: Rock 5A recently had a patch land that misuses _pins; this
patch corrects that.)
However, on some RK3588 boards, the PCIe 3 controller will indefinitely
stall the boot if CLKREQ# is not muxed (details in the next patch).
This patch unbundles the signals to allow them to be used.
Tianling Shen [Thu, 26 Dec 2024 09:20:42 +0000 (17:20 +0800)]
arm64: dts: rockchip: reorder mmc aliases for NanoPi R3S
Typically any non-removable storage (emmc) is listed before removable
storage (sd-card) options. Also U-Boot will try to override and use
mmc0=sdhci and mmc1=sdmmc0 for all rk356x boards.
Jonas Karlman [Thu, 12 Dec 2024 22:09:44 +0000 (22:09 +0000)]
rockchip: rk3288-firefly: Change to use FIT
Change to use FIT and FIT_SIGNATURE when loading U-Boot proper in SPL to
allow checksum validation and fallback loading of FIT from a different
mmc device.
Jonas Karlman [Thu, 12 Dec 2024 22:09:40 +0000 (22:09 +0000)]
rockchip: rk3288-firefly: Drop use of silent console and late boardinfo
Current use of SILENT_CONSOLE hide valuable information when something
goes wrong during boot, drop this Kconfig option to allow user to see
e.g. from what media U-Boot proper is loaded from.
A second Model line is printed on console due to DISPLAY_BOARDINFO_LATE,
drop this Kconfig option to remove the second redundant line.
projects / J-u-boot.git / log