[J-u-boot.git] / arch / arm / mach-stm32mp / cpu.c

// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
 */
#include <common.h>
#include <clk.h>
#include <debug_uart.h>
#include <environment.h>
#include <misc.h>
#include <asm/io.h>
#include <asm/arch/stm32.h>
#include <asm/arch/sys_proto.h>
#include <dm/device.h>
#include <dm/uclass.h>

/* RCC register */
#define RCC_TZCR		(STM32_RCC_BASE + 0x00)
#define RCC_DBGCFGR		(STM32_RCC_BASE + 0x080C)
#define RCC_BDCR		(STM32_RCC_BASE + 0x0140)
#define RCC_MP_APB5ENSETR	(STM32_RCC_BASE + 0x0208)
#define RCC_MP_AHB5ENSETR	(STM32_RCC_BASE + 0x0210)
#define RCC_BDCR_VSWRST		BIT(31)
#define RCC_BDCR_RTCSRC		GENMASK(17, 16)
#define RCC_DBGCFGR_DBGCKEN	BIT(8)

/* Security register */
#define ETZPC_TZMA1_SIZE	(STM32_ETZPC_BASE + 0x04)
#define ETZPC_DECPROT0		(STM32_ETZPC_BASE + 0x10)

#define TZC_GATE_KEEPER		(STM32_TZC_BASE + 0x008)
#define TZC_REGION_ATTRIBUTE0	(STM32_TZC_BASE + 0x110)
#define TZC_REGION_ID_ACCESS0	(STM32_TZC_BASE + 0x114)

#define TAMP_CR1		(STM32_TAMP_BASE + 0x00)

#define PWR_CR1			(STM32_PWR_BASE + 0x00)
#define PWR_CR1_DBP		BIT(8)

/* DBGMCU register */
#define DBGMCU_IDC		(STM32_DBGMCU_BASE + 0x00)
#define DBGMCU_APB4FZ1		(STM32_DBGMCU_BASE + 0x2C)
#define DBGMCU_APB4FZ1_IWDG2	BIT(2)
#define DBGMCU_IDC_DEV_ID_MASK	GENMASK(11, 0)
#define DBGMCU_IDC_DEV_ID_SHIFT	0
#define DBGMCU_IDC_REV_ID_MASK	GENMASK(31, 16)
#define DBGMCU_IDC_REV_ID_SHIFT	16

/* GPIOZ registers */
#define GPIOZ_SECCFGR		0x54004030

/* boot interface from Bootrom
 * - boot instance = bit 31:16
 * - boot device = bit 15:0
 */
#define BOOTROM_PARAM_ADDR	0x2FFC0078
#define BOOTROM_MODE_MASK	GENMASK(15, 0)
#define BOOTROM_MODE_SHIFT	0
#define BOOTROM_INSTANCE_MASK	 GENMASK(31, 16)
#define BOOTROM_INSTANCE_SHIFT	16

/* BSEC OTP index */
#define BSEC_OTP_RPN	1
#define BSEC_OTP_SERIAL	13
#define BSEC_OTP_PKG	16
#define BSEC_OTP_MAC	57

/* Device Part Number (RPN) = OTP_DATA1 lower 8 bits */
#define RPN_SHIFT	0
#define RPN_MASK	GENMASK(7, 0)

/* Package = bit 27:29 of OTP16
 * - 100: LBGA448 (FFI) => AA = LFBGA 18x18mm 448 balls p. 0.8mm
 * - 011: LBGA354 (LCI) => AB = LFBGA 16x16mm 359 balls p. 0.8mm
 * - 010: TFBGA361 (FFC) => AC = TFBGA 12x12mm 361 balls p. 0.5mm
 * - 001: TFBGA257 (LCC) => AD = TFBGA 10x10mm 257 balls p. 0.5mm
 * - others: Reserved
 */
#define PKG_SHIFT	27
#define PKG_MASK	GENMASK(2, 0)

#define PKG_AA_LBGA448	4
#define PKG_AB_LBGA354	3
#define PKG_AC_TFBGA361	2
#define PKG_AD_TFBGA257	1

#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
#ifndef CONFIG_STM32MP1_TRUSTED
static void security_init(void)
{
	/* Disable the backup domain write protection */
	/* the protection is enable at each reset by hardware */
	/* And must be disable by software */
	setbits_le32(PWR_CR1, PWR_CR1_DBP);

	while (!(readl(PWR_CR1) & PWR_CR1_DBP))
		;

	/* If RTC clock isn't enable so this is a cold boot then we need
	 * to reset the backup domain
	 */
	if (!(readl(RCC_BDCR) & RCC_BDCR_RTCSRC)) {
		setbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
		while (!(readl(RCC_BDCR) & RCC_BDCR_VSWRST))
			;
		clrbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
	}

	/* allow non secure access in Write/Read for all peripheral */
	writel(GENMASK(25, 0), ETZPC_DECPROT0);

	/* Open SYSRAM for no secure access */
	writel(0x0, ETZPC_TZMA1_SIZE);

	/* enable TZC1 TZC2 clock */
	writel(BIT(11) | BIT(12), RCC_MP_APB5ENSETR);

	/* Region 0 set to no access by default */
	/* bit 0 / 16 => nsaid0 read/write Enable
	 * bit 1 / 17 => nsaid1 read/write Enable
	 * ...
	 * bit 15 / 31 => nsaid15 read/write Enable
	 */
	writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS0);
	/* bit 30 / 31 => Secure Global Enable : write/read */
	/* bit 0 / 1 => Region Enable for filter 0/1 */
	writel(BIT(0) | BIT(1) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE0);

	/* Enable Filter 0 and 1 */
	setbits_le32(TZC_GATE_KEEPER, BIT(0) | BIT(1));

	/* RCC trust zone deactivated */
	writel(0x0, RCC_TZCR);

	/* TAMP: deactivate the internal tamper
	 * Bit 23 ITAMP8E: monotonic counter overflow
	 * Bit 20 ITAMP5E: RTC calendar overflow
	 * Bit 19 ITAMP4E: HSE monitoring
	 * Bit 18 ITAMP3E: LSE monitoring
	 * Bit 16 ITAMP1E: RTC power domain supply monitoring
	 */
	writel(0x0, TAMP_CR1);

	/* GPIOZ: deactivate the security */
	writel(BIT(0), RCC_MP_AHB5ENSETR);
	writel(0x0, GPIOZ_SECCFGR);
}
#endif /* CONFIG_STM32MP1_TRUSTED */

/*
 * Debug init
 */
static void dbgmcu_init(void)
{
	setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);

	/* Freeze IWDG2 if Cortex-A7 is in debug mode */
	setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2);
}
#endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */

#if !defined(CONFIG_STM32MP1_TRUSTED) && \
	(!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
/* get bootmode from ROM code boot context: saved in TAMP register */
static void update_bootmode(void)
{
	u32 boot_mode;
	u32 bootrom_itf = readl(BOOTROM_PARAM_ADDR);
	u32 bootrom_device, bootrom_instance;

	/* enable TAMP clock = RTCAPBEN */
	writel(BIT(8), RCC_MP_APB5ENSETR);

	/* read bootrom context */
	bootrom_device =
		(bootrom_itf & BOOTROM_MODE_MASK) >> BOOTROM_MODE_SHIFT;
	bootrom_instance =
		(bootrom_itf & BOOTROM_INSTANCE_MASK) >> BOOTROM_INSTANCE_SHIFT;
	boot_mode =
		((bootrom_device << BOOT_TYPE_SHIFT) & BOOT_TYPE_MASK) |
		((bootrom_instance << BOOT_INSTANCE_SHIFT) &
		 BOOT_INSTANCE_MASK);

	/* save the boot mode in TAMP backup register */
	clrsetbits_le32(TAMP_BOOT_CONTEXT,
			TAMP_BOOT_MODE_MASK,
			boot_mode << TAMP_BOOT_MODE_SHIFT);
}
#endif

u32 get_bootmode(void)
{
	/* read bootmode from TAMP backup register */
	return (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_MODE_MASK) >>
		    TAMP_BOOT_MODE_SHIFT;
}

/*
 * Early system init
 */
int arch_cpu_init(void)
{
	u32 boot_mode;

	/* early armv7 timer init: needed for polling */
	timer_init();

#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
	dbgmcu_init();
#ifndef CONFIG_STM32MP1_TRUSTED
	security_init();
	update_bootmode();
#endif
#endif

	boot_mode = get_bootmode();

	if ((boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART)
		gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
#if defined(CONFIG_DEBUG_UART) && \
	!defined(CONFIG_STM32MP1_TRUSTED) && \
	(!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
	else
		debug_uart_init();
#endif

	return 0;
}

void enable_caches(void)
{
	/* Enable D-cache. I-cache is already enabled in start.S */
	dcache_enable();
}

static u32 read_idc(void)
{
	setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);

	return readl(DBGMCU_IDC);
}

u32 get_cpu_rev(void)
{
	return (read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT;
}

static u32 get_otp(int index, int shift, int mask)
{
	int ret;
	struct udevice *dev;
	u32 otp = 0;

	ret = uclass_get_device_by_driver(UCLASS_MISC,
					  DM_GET_DRIVER(stm32mp_bsec),
					  &dev);

	if (!ret)
		ret = misc_read(dev, STM32_BSEC_SHADOW(index),
				&otp, sizeof(otp));

	return (otp >> shift) & mask;
}

/* Get Device Part Number (RPN) from OTP */
static u32 get_cpu_rpn(void)
{
	return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK);
}

u32 get_cpu_type(void)
{
	u32 id;

	id = (read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT;

	return (id << 16) | get_cpu_rpn();
}

/* Get Package options from OTP */
static u32 get_cpu_package(void)
{
	return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK);
}

#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void)
{
	char *cpu_s, *cpu_r, *pkg;

	/* MPUs Part Numbers */
	switch (get_cpu_type()) {
	case CPU_STM32MP157Cxx:
		cpu_s = "157C";
		break;
	case CPU_STM32MP157Axx:
		cpu_s = "157A";
		break;
	case CPU_STM32MP153Cxx:
		cpu_s = "153C";
		break;
	case CPU_STM32MP153Axx:
		cpu_s = "153A";
		break;
	case CPU_STM32MP151Cxx:
		cpu_s = "151C";
		break;
	case CPU_STM32MP151Axx:
		cpu_s = "151A";
		break;
	default:
		cpu_s = "????";
		break;
	}

	/* Package */
	switch (get_cpu_package()) {
	case PKG_AA_LBGA448:
		pkg = "AA";
		break;
	case PKG_AB_LBGA354:
		pkg = "AB";
		break;
	case PKG_AC_TFBGA361:
		pkg = "AC";
		break;
	case PKG_AD_TFBGA257:
		pkg = "AD";
		break;
	default:
		pkg = "??";
		break;
	}

	/* REVISION */
	switch (get_cpu_rev()) {
	case CPU_REVA:
		cpu_r = "A";
		break;
	case CPU_REVB:
		cpu_r = "B";
		break;
	default:
		cpu_r = "?";
		break;
	}

	printf("CPU: STM32MP%s%s Rev.%s\n", cpu_s, pkg, cpu_r);

	return 0;
}
#endif /* CONFIG_DISPLAY_CPUINFO */

static void setup_boot_mode(void)
{
	const u32 serial_addr[] = {
		STM32_USART1_BASE,
		STM32_USART2_BASE,
		STM32_USART3_BASE,
		STM32_UART4_BASE,
		STM32_UART5_BASE,
		STM32_USART6_BASE,
		STM32_UART7_BASE,
		STM32_UART8_BASE
	};
	char cmd[60];
	u32 boot_ctx = readl(TAMP_BOOT_CONTEXT);
	u32 boot_mode =
		(boot_ctx & TAMP_BOOT_MODE_MASK) >> TAMP_BOOT_MODE_SHIFT;
	int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1;
	u32 forced_mode = (boot_ctx & TAMP_BOOT_FORCED_MASK);
	struct udevice *dev;
	int alias;

	pr_debug("%s: boot_ctx=0x%x => boot_mode=%x, instance=%d forced=%x\n",
		 __func__, boot_ctx, boot_mode, instance, forced_mode);
	switch (boot_mode & TAMP_BOOT_DEVICE_MASK) {
	case BOOT_SERIAL_UART:
		if (instance > ARRAY_SIZE(serial_addr))
			break;
		/* serial : search associated alias in devicetree */
		sprintf(cmd, "serial@%x", serial_addr[instance]);
		if (uclass_get_device_by_name(UCLASS_SERIAL, cmd, &dev))
			break;
		if (fdtdec_get_alias_seq(gd->fdt_blob, "serial",
					 dev_of_offset(dev), &alias))
			break;
		sprintf(cmd, "%d", alias);
		env_set("boot_device", "serial");
		env_set("boot_instance", cmd);

		/* restore console on uart when not used */
		if (gd->cur_serial_dev != dev) {
			gd->flags &= ~(GD_FLG_SILENT |
				       GD_FLG_DISABLE_CONSOLE);
			printf("serial boot with console enabled!\n");
		}
		break;
	case BOOT_SERIAL_USB:
		env_set("boot_device", "usb");
		env_set("boot_instance", "0");
		break;
	case BOOT_FLASH_SD:
	case BOOT_FLASH_EMMC:
		sprintf(cmd, "%d", instance);
		env_set("boot_device", "mmc");
		env_set("boot_instance", cmd);
		break;
	case BOOT_FLASH_NAND:
		env_set("boot_device", "nand");
		env_set("boot_instance", "0");
		break;
	case BOOT_FLASH_NOR:
		env_set("boot_device", "nor");
		env_set("boot_instance", "0");
		break;
	default:
		pr_debug("unexpected boot mode = %x\n", boot_mode);
		break;
	}

	switch (forced_mode) {
	case BOOT_FASTBOOT:
		printf("Enter fastboot!\n");
		env_set("preboot", "env set preboot; fastboot 0");
		break;
	case BOOT_STM32PROG:
		env_set("boot_device", "usb");
		env_set("boot_instance", "0");
		break;
	case BOOT_UMS_MMC0:
	case BOOT_UMS_MMC1:
	case BOOT_UMS_MMC2:
		printf("Enter UMS!\n");
		instance = forced_mode - BOOT_UMS_MMC0;
		sprintf(cmd, "env set preboot; ums 0 mmc %d", instance);
		env_set("preboot", cmd);
		break;
	case BOOT_RECOVERY:
		env_set("preboot", "env set preboot; run altbootcmd");
		break;
	case BOOT_NORMAL:
		break;
	default:
		pr_debug("unexpected forced boot mode = %x\n", forced_mode);
		break;
	}

	/* clear TAMP for next reboot */
	clrsetbits_le32(TAMP_BOOT_CONTEXT, TAMP_BOOT_FORCED_MASK, BOOT_NORMAL);
}

/*
 * If there is no MAC address in the environment, then it will be initialized
 * (silently) from the value in the OTP.
 */
static int setup_mac_address(void)
{
#if defined(CONFIG_NET)
	int ret;
	int i;
	u32 otp[2];
	uchar enetaddr[6];
	struct udevice *dev;

	/* MAC already in environment */
	if (eth_env_get_enetaddr("ethaddr", enetaddr))
		return 0;

	ret = uclass_get_device_by_driver(UCLASS_MISC,
					  DM_GET_DRIVER(stm32mp_bsec),
					  &dev);
	if (ret)
		return ret;

	ret = misc_read(dev, BSEC_OTP_MAC * 4 + STM32_BSEC_OTP_OFFSET,
			otp, sizeof(otp));
	if (ret < 0)
		return ret;

	for (i = 0; i < 6; i++)
		enetaddr[i] = ((uint8_t *)&otp)[i];

	if (!is_valid_ethaddr(enetaddr)) {
		pr_err("invalid MAC address in OTP %pM", enetaddr);
		return -EINVAL;
	}
	pr_debug("OTP MAC address = %pM\n", enetaddr);
	ret = !eth_env_set_enetaddr("ethaddr", enetaddr);
	if (!ret)
		pr_err("Failed to set mac address %pM from OTP: %d\n",
		       enetaddr, ret);
#endif

	return 0;
}

static int setup_serial_number(void)
{
	char serial_string[25];
	u32 otp[3] = {0, 0, 0 };
	struct udevice *dev;
	int ret;

	if (env_get("serial#"))
		return 0;

	ret = uclass_get_device_by_driver(UCLASS_MISC,
					  DM_GET_DRIVER(stm32mp_bsec),
					  &dev);
	if (ret)
		return ret;

	ret = misc_read(dev, BSEC_OTP_SERIAL * 4 + STM32_BSEC_OTP_OFFSET,
			otp, sizeof(otp));
	if (ret < 0)
		return ret;

	sprintf(serial_string, "%08X%08X%08X", otp[0], otp[1], otp[2]);
	env_set("serial#", serial_string);

	return 0;
}

int arch_misc_init(void)
{
	setup_boot_mode();
	setup_mac_address();
	setup_serial_number();

	return 0;
}
Commit	Line	Data
4549e789	1	// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2514c2d0 PD	2	/*
2514c2d0 PD	3	* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
2514c2d0 PD	4	*/
	5	#include <common.h>
	6	#include <clk.h>
320d2663	7	#include <debug_uart.h>
7f7deb0c PD	8	#include <environment.h>
7f7deb0c PD	9	#include <misc.h>
2514c2d0 PD	10	#include <asm/io.h>
2514c2d0 PD	11	#include <asm/arch/stm32.h>
96583cdc	12	#include <asm/arch/sys_proto.h>
7f7deb0c	13	#include <dm/device.h>
08772f6e	14	#include <dm/uclass.h>
2514c2d0	15
cda3dcb6 PD	16	/* RCC register */
	17	#define RCC_TZCR (STM32_RCC_BASE + 0x00)
	18	#define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C)
	19	#define RCC_BDCR (STM32_RCC_BASE + 0x0140)
	20	#define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x0208)
59a54e37	21	#define RCC_MP_AHB5ENSETR (STM32_RCC_BASE + 0x0210)
cda3dcb6 PD	22	#define RCC_BDCR_VSWRST BIT(31)
	23	#define RCC_BDCR_RTCSRC GENMASK(17, 16)
	24	#define RCC_DBGCFGR_DBGCKEN BIT(8)
2514c2d0	25
cda3dcb6	26	/* Security register */
2514c2d0 PD	27	#define ETZPC_TZMA1_SIZE (STM32_ETZPC_BASE + 0x04)
	28	#define ETZPC_DECPROT0 (STM32_ETZPC_BASE + 0x10)
	29
	30	#define TZC_GATE_KEEPER (STM32_TZC_BASE + 0x008)
	31	#define TZC_REGION_ATTRIBUTE0 (STM32_TZC_BASE + 0x110)
	32	#define TZC_REGION_ID_ACCESS0 (STM32_TZC_BASE + 0x114)
	33
	34	#define TAMP_CR1 (STM32_TAMP_BASE + 0x00)
	35
	36	#define PWR_CR1 (STM32_PWR_BASE + 0x00)
	37	#define PWR_CR1_DBP BIT(8)
	38
cda3dcb6	39	/* DBGMCU register */
96583cdc	40	#define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00)
cda3dcb6 PD	41	#define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C)
cda3dcb6 PD	42	#define DBGMCU_APB4FZ1_IWDG2 BIT(2)
96583cdc PD	43	#define DBGMCU_IDC_DEV_ID_MASK GENMASK(11, 0)
	44	#define DBGMCU_IDC_DEV_ID_SHIFT 0
	45	#define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16)
	46	#define DBGMCU_IDC_REV_ID_SHIFT 16
2514c2d0	47
59a54e37 PD	48	/* GPIOZ registers */
	49	#define GPIOZ_SECCFGR 0x54004030
	50
08772f6e PD	51	/* boot interface from Bootrom
	52	* - boot instance = bit 31:16
	53	* - boot device = bit 15:0
	54	*/
	55	#define BOOTROM_PARAM_ADDR 0x2FFC0078
	56	#define BOOTROM_MODE_MASK GENMASK(15, 0)
	57	#define BOOTROM_MODE_SHIFT 0
	58	#define BOOTROM_INSTANCE_MASK GENMASK(31, 16)
	59	#define BOOTROM_INSTANCE_SHIFT 16
	60
7f7deb0c	61	/* BSEC OTP index */
35d568f0	62	#define BSEC_OTP_RPN 1
7f7deb0c	63	#define BSEC_OTP_SERIAL 13
35d568f0	64	#define BSEC_OTP_PKG 16
7f7deb0c PD	65	#define BSEC_OTP_MAC 57
7f7deb0c PD	66
35d568f0 PD	67	/* Device Part Number (RPN) = OTP_DATA1 lower 8 bits */
	68	#define RPN_SHIFT 0
	69	#define RPN_MASK GENMASK(7, 0)
	70
	71	/* Package = bit 27:29 of OTP16
	72	* - 100: LBGA448 (FFI) => AA = LFBGA 18x18mm 448 balls p. 0.8mm
	73	* - 011: LBGA354 (LCI) => AB = LFBGA 16x16mm 359 balls p. 0.8mm
	74	* - 010: TFBGA361 (FFC) => AC = TFBGA 12x12mm 361 balls p. 0.5mm
	75	* - 001: TFBGA257 (LCC) => AD = TFBGA 10x10mm 257 balls p. 0.5mm
	76	* - others: Reserved
	77	*/
	78	#define PKG_SHIFT 27
	79	#define PKG_MASK GENMASK(2, 0)
	80
	81	#define PKG_AA_LBGA448 4
	82	#define PKG_AB_LBGA354 3
	83	#define PKG_AC_TFBGA361 2
	84	#define PKG_AD_TFBGA257 1
	85
cda3dcb6	86	#if !defined(CONFIG_SPL) \|\| defined(CONFIG_SPL_BUILD)
abf2678f	87	#ifndef CONFIG_STM32MP1_TRUSTED
2514c2d0 PD	88	static void security_init(void)
	89	{
	90	/* Disable the backup domain write protection */
	91	/* the protection is enable at each reset by hardware */
	92	/* And must be disable by software */
	93	setbits_le32(PWR_CR1, PWR_CR1_DBP);
	94
	95	while (!(readl(PWR_CR1) & PWR_CR1_DBP))
	96	;
	97
	98	/* If RTC clock isn't enable so this is a cold boot then we need
	99	* to reset the backup domain
	100	*/
	101	if (!(readl(RCC_BDCR) & RCC_BDCR_RTCSRC)) {
	102	setbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
	103	while (!(readl(RCC_BDCR) & RCC_BDCR_VSWRST))
	104	;
	105	clrbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
	106	}
	107
	108	/* allow non secure access in Write/Read for all peripheral */
	109	writel(GENMASK(25, 0), ETZPC_DECPROT0);
	110
	111	/* Open SYSRAM for no secure access */
	112	writel(0x0, ETZPC_TZMA1_SIZE);
	113
	114	/* enable TZC1 TZC2 clock */
	115	writel(BIT(11) \| BIT(12), RCC_MP_APB5ENSETR);
	116
	117	/* Region 0 set to no access by default */
	118	/* bit 0 / 16 => nsaid0 read/write Enable
	119	* bit 1 / 17 => nsaid1 read/write Enable
	120	* ...
	121	* bit 15 / 31 => nsaid15 read/write Enable
	122	*/
	123	writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS0);
	124	/* bit 30 / 31 => Secure Global Enable : write/read */
	125	/* bit 0 / 1 => Region Enable for filter 0/1 */
	126	writel(BIT(0) \| BIT(1) \| BIT(30) \| BIT(31), TZC_REGION_ATTRIBUTE0);
	127
	128	/* Enable Filter 0 and 1 */
	129	setbits_le32(TZC_GATE_KEEPER, BIT(0) \| BIT(1));
	130
	131	/* RCC trust zone deactivated */
	132	writel(0x0, RCC_TZCR);
	133
	134	/* TAMP: deactivate the internal tamper
	135	* Bit 23 ITAMP8E: monotonic counter overflow
	136	* Bit 20 ITAMP5E: RTC calendar overflow
	137	* Bit 19 ITAMP4E: HSE monitoring
	138	* Bit 18 ITAMP3E: LSE monitoring
	139	* Bit 16 ITAMP1E: RTC power domain supply monitoring
	140	*/
	141	writel(0x0, TAMP_CR1);
59a54e37 PD	142
	143	/* GPIOZ: deactivate the security */
	144	writel(BIT(0), RCC_MP_AHB5ENSETR);
	145	writel(0x0, GPIOZ_SECCFGR);
2514c2d0	146	}
abf2678f	147	#endif /* CONFIG_STM32MP1_TRUSTED */
2514c2d0	148
cda3dcb6	149	/*
2514c2d0	150	* Debug init
cda3dcb6	151	*/
2514c2d0 PD	152	static void dbgmcu_init(void)
	153	{
	154	setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
	155
	156	/* Freeze IWDG2 if Cortex-A7 is in debug mode */
	157	setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2);
	158	}
	159	#endif /* !defined(CONFIG_SPL) \|\| defined(CONFIG_SPL_BUILD) */
	160
abf2678f PD	161	#if !defined(CONFIG_STM32MP1_TRUSTED) && \
abf2678f PD	162	(!defined(CONFIG_SPL) \|\| defined(CONFIG_SPL_BUILD))
7f63c1e6 PD	163	/* get bootmode from ROM code boot context: saved in TAMP register */
	164	static void update_bootmode(void)
	165	{
	166	u32 boot_mode;
08772f6e PD	167	u32 bootrom_itf = readl(BOOTROM_PARAM_ADDR);
	168	u32 bootrom_device, bootrom_instance;
	169
7f63c1e6 PD	170	/* enable TAMP clock = RTCAPBEN */
	171	writel(BIT(8), RCC_MP_APB5ENSETR);
	172
	173	/* read bootrom context */
08772f6e PD	174	bootrom_device =
	175	(bootrom_itf & BOOTROM_MODE_MASK) >> BOOTROM_MODE_SHIFT;
	176	bootrom_instance =
	177	(bootrom_itf & BOOTROM_INSTANCE_MASK) >> BOOTROM_INSTANCE_SHIFT;
	178	boot_mode =
	179	((bootrom_device << BOOT_TYPE_SHIFT) & BOOT_TYPE_MASK) \|
	180	((bootrom_instance << BOOT_INSTANCE_SHIFT) &
	181	BOOT_INSTANCE_MASK);
	182
	183	/* save the boot mode in TAMP backup register */
	184	clrsetbits_le32(TAMP_BOOT_CONTEXT,
	185	TAMP_BOOT_MODE_MASK,
	186	boot_mode << TAMP_BOOT_MODE_SHIFT);
7f63c1e6	187	}
08772f6e	188	#endif
7f63c1e6 PD	189
	190	u32 get_bootmode(void)
	191	{
	192	/* read bootmode from TAMP backup register */
	193	return (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_MODE_MASK) >>
	194	TAMP_BOOT_MODE_SHIFT;
08772f6e PD	195	}
	196
	197	/*
	198	* Early system init
	199	*/
2514c2d0 PD	200	int arch_cpu_init(void)
2514c2d0 PD	201	{
320d2663 PD	202	u32 boot_mode;
320d2663 PD	203
2514c2d0 PD	204	/* early armv7 timer init: needed for polling */
	205	timer_init();
	206
	207	#if !defined(CONFIG_SPL) \|\| defined(CONFIG_SPL_BUILD)
	208	dbgmcu_init();
abf2678f	209	#ifndef CONFIG_STM32MP1_TRUSTED
2514c2d0	210	security_init();
7f63c1e6	211	update_bootmode();
abf2678f	212	#endif
2514c2d0	213	#endif
320d2663	214
320d2663 PD	215	boot_mode = get_bootmode();
	216
	217	if ((boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART)
	218	gd->flags \|= GD_FLG_SILENT \| GD_FLG_DISABLE_CONSOLE;
	219	#if defined(CONFIG_DEBUG_UART) && \
abf2678f	220	!defined(CONFIG_STM32MP1_TRUSTED) && \
320d2663 PD	221	(!defined(CONFIG_SPL) \|\| defined(CONFIG_SPL_BUILD))
	222	else
	223	debug_uart_init();
	224	#endif
2514c2d0 PD	225
	226	return 0;
	227	}
	228
cda3dcb6 PD	229	void enable_caches(void)
	230	{
	231	/* Enable D-cache. I-cache is already enabled in start.S */
	232	dcache_enable();
	233	}
	234
96583cdc PD	235	static u32 read_idc(void)
	236	{
	237	setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
	238
	239	return readl(DBGMCU_IDC);
	240	}
	241
	242	u32 get_cpu_rev(void)
	243	{
	244	return (read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT;
	245	}
	246
35d568f0 PD	247	static u32 get_otp(int index, int shift, int mask)
	248	{
	249	int ret;
	250	struct udevice *dev;
	251	u32 otp = 0;
	252
	253	ret = uclass_get_device_by_driver(UCLASS_MISC,
	254	DM_GET_DRIVER(stm32mp_bsec),
	255	&dev);
	256
	257	if (!ret)
	258	ret = misc_read(dev, STM32_BSEC_SHADOW(index),
	259	&otp, sizeof(otp));
	260
	261	return (otp >> shift) & mask;
	262	}
	263
	264	/* Get Device Part Number (RPN) from OTP */
	265	static u32 get_cpu_rpn(void)
	266	{
	267	return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK);
	268	}
	269
96583cdc PD	270	u32 get_cpu_type(void)
96583cdc PD	271	{
35d568f0 PD	272	u32 id;
	273
	274	id = (read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT;
	275
	276	return (id << 16) \| get_cpu_rpn();
	277	}
	278
	279	/* Get Package options from OTP */
	280	static u32 get_cpu_package(void)
	281	{
	282	return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK);
96583cdc PD	283	}
96583cdc PD	284
2514c2d0 PD	285	#if defined(CONFIG_DISPLAY_CPUINFO)
	286	int print_cpuinfo(void)
	287	{
35d568f0	288	char cpu_s, cpu_r, *pkg;
96583cdc	289
35d568f0	290	/* MPUs Part Numbers */
96583cdc	291	switch (get_cpu_type()) {
35d568f0 PD	292	case CPU_STM32MP157Cxx:
	293	cpu_s = "157C";
	294	break;
	295	case CPU_STM32MP157Axx:
	296	cpu_s = "157A";
	297	break;
	298	case CPU_STM32MP153Cxx:
	299	cpu_s = "153C";
	300	break;
	301	case CPU_STM32MP153Axx:
	302	cpu_s = "153A";
	303	break;
	304	case CPU_STM32MP151Cxx:
	305	cpu_s = "151C";
	306	break;
	307	case CPU_STM32MP151Axx:
	308	cpu_s = "151A";
	309	break;
	310	default:
	311	cpu_s = "????";
	312	break;
	313	}
	314
	315	/* Package */
	316	switch (get_cpu_package()) {
	317	case PKG_AA_LBGA448:
	318	pkg = "AA";
	319	break;
	320	case PKG_AB_LBGA354:
	321	pkg = "AB";
	322	break;
	323	case PKG_AC_TFBGA361:
	324	pkg = "AC";
	325	break;
	326	case PKG_AD_TFBGA257:
	327	pkg = "AD";
96583cdc PD	328	break;
96583cdc PD	329	default:
35d568f0	330	pkg = "??";
96583cdc PD	331	break;
	332	}
	333
35d568f0	334	/* REVISION */
96583cdc PD	335	switch (get_cpu_rev()) {
	336	case CPU_REVA:
	337	cpu_r = "A";
	338	break;
	339	case CPU_REVB:
	340	cpu_r = "B";
	341	break;
	342	default:
	343	cpu_r = "?";
	344	break;
	345	}
	346
35d568f0	347	printf("CPU: STM32MP%s%s Rev.%s\n", cpu_s, pkg, cpu_r);
2514c2d0 PD	348
	349	return 0;
	350	}
	351	#endif /* CONFIG_DISPLAY_CPUINFO */
	352
08772f6e PD	353	static void setup_boot_mode(void)
08772f6e PD	354	{
7f63c1e6 PD	355	const u32 serial_addr[] = {
	356	STM32_USART1_BASE,
	357	STM32_USART2_BASE,
	358	STM32_USART3_BASE,
	359	STM32_UART4_BASE,
	360	STM32_UART5_BASE,
	361	STM32_USART6_BASE,
	362	STM32_UART7_BASE,
	363	STM32_UART8_BASE
	364	};
08772f6e PD	365	char cmd[60];
	366	u32 boot_ctx = readl(TAMP_BOOT_CONTEXT);
	367	u32 boot_mode =
	368	(boot_ctx & TAMP_BOOT_MODE_MASK) >> TAMP_BOOT_MODE_SHIFT;
	369	int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1;
9a2ba283	370	u32 forced_mode = (boot_ctx & TAMP_BOOT_FORCED_MASK);
7f63c1e6 PD	371	struct udevice *dev;
7f63c1e6 PD	372	int alias;
08772f6e	373
9a2ba283 PD	374	pr_debug("%s: boot_ctx=0x%x => boot_mode=%x, instance=%d forced=%x\n",
9a2ba283 PD	375	__func__, boot_ctx, boot_mode, instance, forced_mode);
08772f6e PD	376	switch (boot_mode & TAMP_BOOT_DEVICE_MASK) {
08772f6e PD	377	case BOOT_SERIAL_UART:
7f63c1e6 PD	378	if (instance > ARRAY_SIZE(serial_addr))
	379	break;
	380	/* serial : search associated alias in devicetree */
	381	sprintf(cmd, "serial@%x", serial_addr[instance]);
	382	if (uclass_get_device_by_name(UCLASS_SERIAL, cmd, &dev))
	383	break;
	384	if (fdtdec_get_alias_seq(gd->fdt_blob, "serial",
	385	dev_of_offset(dev), &alias))
	386	break;
	387	sprintf(cmd, "%d", alias);
	388	env_set("boot_device", "serial");
08772f6e	389	env_set("boot_instance", cmd);
7f63c1e6 PD	390
	391	/* restore console on uart when not used */
	392	if (gd->cur_serial_dev != dev) {
	393	gd->flags &= ~(GD_FLG_SILENT \|
	394	GD_FLG_DISABLE_CONSOLE);
	395	printf("serial boot with console enabled!\n");
	396	}
08772f6e PD	397	break;
	398	case BOOT_SERIAL_USB:
	399	env_set("boot_device", "usb");
	400	env_set("boot_instance", "0");
	401	break;
	402	case BOOT_FLASH_SD:
	403	case BOOT_FLASH_EMMC:
	404	sprintf(cmd, "%d", instance);
	405	env_set("boot_device", "mmc");
	406	env_set("boot_instance", cmd);
	407	break;
	408	case BOOT_FLASH_NAND:
	409	env_set("boot_device", "nand");
	410	env_set("boot_instance", "0");
	411	break;
	412	case BOOT_FLASH_NOR:
	413	env_set("boot_device", "nor");
	414	env_set("boot_instance", "0");
	415	break;
	416	default:
	417	pr_debug("unexpected boot mode = %x\n", boot_mode);
	418	break;
	419	}
9a2ba283 PD	420
	421	switch (forced_mode) {
	422	case BOOT_FASTBOOT:
	423	printf("Enter fastboot!\n");
	424	env_set("preboot", "env set preboot; fastboot 0");
	425	break;
	426	case BOOT_STM32PROG:
	427	env_set("boot_device", "usb");
	428	env_set("boot_instance", "0");
	429	break;
	430	case BOOT_UMS_MMC0:
	431	case BOOT_UMS_MMC1:
	432	case BOOT_UMS_MMC2:
	433	printf("Enter UMS!\n");
	434	instance = forced_mode - BOOT_UMS_MMC0;
	435	sprintf(cmd, "env set preboot; ums 0 mmc %d", instance);
	436	env_set("preboot", cmd);
	437	break;
	438	case BOOT_RECOVERY:
	439	env_set("preboot", "env set preboot; run altbootcmd");
	440	break;
	441	case BOOT_NORMAL:
	442	break;
	443	default:
	444	pr_debug("unexpected forced boot mode = %x\n", forced_mode);
	445	break;
	446	}
	447
	448	/* clear TAMP for next reboot */
	449	clrsetbits_le32(TAMP_BOOT_CONTEXT, TAMP_BOOT_FORCED_MASK, BOOT_NORMAL);
08772f6e PD	450	}
08772f6e PD	451
7f7deb0c PD	452	/*
	453	* If there is no MAC address in the environment, then it will be initialized
	454	* (silently) from the value in the OTP.
	455	*/
	456	static int setup_mac_address(void)
	457	{
	458	#if defined(CONFIG_NET)
	459	int ret;
	460	int i;
	461	u32 otp[2];
	462	uchar enetaddr[6];
	463	struct udevice *dev;
	464
	465	/* MAC already in environment */
	466	if (eth_env_get_enetaddr("ethaddr", enetaddr))
	467	return 0;
	468
	469	ret = uclass_get_device_by_driver(UCLASS_MISC,
	470	DM_GET_DRIVER(stm32mp_bsec),
	471	&dev);
	472	if (ret)
	473	return ret;
	474
	475	ret = misc_read(dev, BSEC_OTP_MAC * 4 + STM32_BSEC_OTP_OFFSET,
	476	otp, sizeof(otp));
8729b1ae	477	if (ret < 0)
7f7deb0c PD	478	return ret;
	479
	480	for (i = 0; i < 6; i++)
	481	enetaddr[i] = ((uint8_t *)&otp)[i];
	482
	483	if (!is_valid_ethaddr(enetaddr)) {
	484	pr_err("invalid MAC address in OTP %pM", enetaddr);
	485	return -EINVAL;
	486	}
	487	pr_debug("OTP MAC address = %pM\n", enetaddr);
	488	ret = !eth_env_set_enetaddr("ethaddr", enetaddr);
	489	if (!ret)
	490	pr_err("Failed to set mac address %pM from OTP: %d\n",
	491	enetaddr, ret);
	492	#endif
	493
	494	return 0;
	495	}
	496
	497	static int setup_serial_number(void)
	498	{
	499	char serial_string[25];
	500	u32 otp[3] = {0, 0, 0 };
	501	struct udevice *dev;
	502	int ret;
	503
	504	if (env_get("serial#"))
	505	return 0;
	506
	507	ret = uclass_get_device_by_driver(UCLASS_MISC,
	508	DM_GET_DRIVER(stm32mp_bsec),
	509	&dev);
	510	if (ret)
	511	return ret;
	512
	513	ret = misc_read(dev, BSEC_OTP_SERIAL * 4 + STM32_BSEC_OTP_OFFSET,
	514	otp, sizeof(otp));
8729b1ae	515	if (ret < 0)
7f7deb0c PD	516	return ret;
7f7deb0c PD	517
8983ba27	518	sprintf(serial_string, "%08X%08X%08X", otp[0], otp[1], otp[2]);
7f7deb0c PD	519	env_set("serial#", serial_string);
	520
	521	return 0;
	522	}
	523
08772f6e PD	524	int arch_misc_init(void)
	525	{
	526	setup_boot_mode();
7f7deb0c PD	527	setup_mac_address();
7f7deb0c PD	528	setup_serial_number();
08772f6e PD	529
	530	return 0;
	531	}