[J-u-boot.git] / arch / arm / mach-stm32mp / cpu.c

// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
 */

#define LOG_CATEGORY LOGC_ARCH

#include <common.h>
#include <clk.h>
#include <cpu_func.h>
#include <debug_uart.h>
#include <env.h>
#include <init.h>
#include <log.h>
#include <lmb.h>
#include <misc.h>
#include <net.h>
#include <asm/io.h>
#include <asm/arch/stm32.h>
#include <asm/arch/sys_proto.h>
#include <asm/global_data.h>
#include <dm/device.h>
#include <dm/uclass.h>
#include <linux/bitops.h>
#include <spl.h>

/*
 * early TLB into the .data section so that it not get cleared
 * with 16kB allignment (see TTBR0_BASE_ADDR_MASK)
 */
u8 early_tlb[PGTABLE_SIZE] __section(".data") __aligned(0x4000);

struct lmb lmb;

u32 get_bootmode(void)
{
	/* read bootmode from TAMP backup register */
	return (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_MODE_MASK) >>
		    TAMP_BOOT_MODE_SHIFT;
}

/*
 * weak function overidde: set the DDR/SYSRAM executable before to enable the
 * MMU and configure DACR, for early early_enable_caches (SPL or pre-reloc)
 */
void dram_bank_mmu_setup(int bank)
{
	struct bd_info *bd = gd->bd;
	int	i;
	phys_addr_t start;
	phys_size_t size;
	bool use_lmb = false;
	enum dcache_option option;

	if (IS_ENABLED(CONFIG_SPL_BUILD)) {
/* STM32_SYSRAM_BASE exist only when SPL is supported */
#ifdef CONFIG_SPL
		start = ALIGN_DOWN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE);
		size = ALIGN(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE);
#endif
	} else if (gd->flags & GD_FLG_RELOC) {
		/* bd->bi_dram is available only after relocation */
		start = bd->bi_dram[bank].start;
		size =  bd->bi_dram[bank].size;
		use_lmb = true;
	} else {
		/* mark cacheable and executable the beggining of the DDR */
		start = STM32_DDR_BASE;
		size = CONFIG_DDR_CACHEABLE_SIZE;
	}

	for (i = start >> MMU_SECTION_SHIFT;
	     i < (start >> MMU_SECTION_SHIFT) + (size >> MMU_SECTION_SHIFT);
	     i++) {
		option = DCACHE_DEFAULT_OPTION;
		if (use_lmb && lmb_is_reserved_flags(&lmb, i << MMU_SECTION_SHIFT, LMB_NOMAP))
			option = 0; /* INVALID ENTRY in TLB */
		set_section_dcache(i, option);
	}
}
/*
 * initialize the MMU and activate cache in SPL or in U-Boot pre-reloc stage
 * MMU/TLB is updated in enable_caches() for U-Boot after relocation
 * or is deactivated in U-Boot entry function start.S::cpu_init_cp15
 */
static void early_enable_caches(void)
{
	/* I-cache is already enabled in start.S: cpu_init_cp15 */

	if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
		return;

	if (!(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))) {
		gd->arch.tlb_size = PGTABLE_SIZE;
		gd->arch.tlb_addr = (unsigned long)&early_tlb;
	}

	/* enable MMU (default configuration) */
	dcache_enable();
}

/*
 * Early system init
 */
int arch_cpu_init(void)
{
	early_enable_caches();

	/* early armv7 timer init: needed for polling */
	timer_init();

	return 0;
}

/* weak function for SOC specific initialization */
__weak void stm32mp_cpu_init(void)
{
}

int mach_cpu_init(void)
{
	u32 boot_mode;

	stm32mp_cpu_init();

	boot_mode = get_bootmode();

	if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) &&
	    (boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART)
		gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
	else if (IS_ENABLED(CONFIG_DEBUG_UART) && IS_ENABLED(CONFIG_SPL_BUILD))
		debug_uart_init();

	return 0;
}

void enable_caches(void)
{
	/* parse device tree when data cache is still activated */
	lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob);

	/* I-cache is already enabled in start.S: icache_enable() not needed */

	/* deactivate the data cache, early enabled in arch_cpu_init() */
	dcache_disable();
	/*
	 * update MMU after relocation and enable the data cache
	 * warning: the TLB location udpated in board_f.c::reserve_mmu
	 */
	dcache_enable();
}

/* used when CONFIG_DISPLAY_CPUINFO is activated */
int print_cpuinfo(void)
{
	char name[SOC_NAME_SIZE];

	get_soc_name(name);
	printf("CPU: %s\n", name);

	return 0;
}

static void setup_boot_mode(void)
{
	const u32 serial_addr[] = {
		STM32_USART1_BASE,
		STM32_USART2_BASE,
		STM32_USART3_BASE,
		STM32_UART4_BASE,
		STM32_UART5_BASE,
		STM32_USART6_BASE,
		STM32_UART7_BASE,
		STM32_UART8_BASE
	};
	const u32 sdmmc_addr[] = {
		STM32_SDMMC1_BASE,
		STM32_SDMMC2_BASE,
		STM32_SDMMC3_BASE
	};
	char cmd[60];
	u32 boot_ctx = readl(TAMP_BOOT_CONTEXT);
	u32 boot_mode =
		(boot_ctx & TAMP_BOOT_MODE_MASK) >> TAMP_BOOT_MODE_SHIFT;
	unsigned int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1;
	u32 forced_mode = (boot_ctx & TAMP_BOOT_FORCED_MASK);
	struct udevice *dev;

	log_debug("%s: boot_ctx=0x%x => boot_mode=%x, instance=%d forced=%x\n",
		  __func__, boot_ctx, boot_mode, instance, forced_mode);
	switch (boot_mode & TAMP_BOOT_DEVICE_MASK) {
	case BOOT_SERIAL_UART:
		if (instance > ARRAY_SIZE(serial_addr))
			break;
		/* serial : search associated node in devicetree */
		sprintf(cmd, "serial@%x", serial_addr[instance]);
		if (uclass_get_device_by_name(UCLASS_SERIAL, cmd, &dev)) {
			/* restore console on error */
			if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL))
				gd->flags &= ~(GD_FLG_SILENT |
					       GD_FLG_DISABLE_CONSOLE);
			log_err("uart%d = %s not found in device tree!\n",
				instance + 1, cmd);
			break;
		}
		sprintf(cmd, "%d", dev_seq(dev));
		env_set("boot_device", "serial");
		env_set("boot_instance", cmd);

		/* restore console on uart when not used */
		if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) && gd->cur_serial_dev != dev) {
			gd->flags &= ~(GD_FLG_SILENT |
				       GD_FLG_DISABLE_CONSOLE);
			log_info("serial boot with console enabled!\n");
		}
		break;
	case BOOT_SERIAL_USB:
		env_set("boot_device", "usb");
		env_set("boot_instance", "0");
		break;
	case BOOT_FLASH_SD:
	case BOOT_FLASH_EMMC:
		if (instance > ARRAY_SIZE(sdmmc_addr))
			break;
		/* search associated sdmmc node in devicetree */
		sprintf(cmd, "mmc@%x", sdmmc_addr[instance]);
		if (uclass_get_device_by_name(UCLASS_MMC, cmd, &dev)) {
			printf("mmc%d = %s not found in device tree!\n",
			       instance, cmd);
			break;
		}
		sprintf(cmd, "%d", dev_seq(dev));
		env_set("boot_device", "mmc");
		env_set("boot_instance", cmd);
		break;
	case BOOT_FLASH_NAND:
		env_set("boot_device", "nand");
		env_set("boot_instance", "0");
		break;
	case BOOT_FLASH_SPINAND:
		env_set("boot_device", "spi-nand");
		env_set("boot_instance", "0");
		break;
	case BOOT_FLASH_NOR:
		env_set("boot_device", "nor");
		env_set("boot_instance", "0");
		break;
	default:
		env_set("boot_device", "invalid");
		env_set("boot_instance", "");
		log_err("unexpected boot mode = %x\n", boot_mode);
		break;
	}

	switch (forced_mode) {
	case BOOT_FASTBOOT:
		log_info("Enter fastboot!\n");
		env_set("preboot", "env set preboot; fastboot 0");
		break;
	case BOOT_STM32PROG:
		env_set("boot_device", "usb");
		env_set("boot_instance", "0");
		break;
	case BOOT_UMS_MMC0:
	case BOOT_UMS_MMC1:
	case BOOT_UMS_MMC2:
		log_info("Enter UMS!\n");
		instance = forced_mode - BOOT_UMS_MMC0;
		sprintf(cmd, "env set preboot; ums 0 mmc %d", instance);
		env_set("preboot", cmd);
		break;
	case BOOT_RECOVERY:
		env_set("preboot", "env set preboot; run altbootcmd");
		break;
	case BOOT_NORMAL:
		break;
	default:
		log_debug("unexpected forced boot mode = %x\n", forced_mode);
		break;
	}

	/* clear TAMP for next reboot */
	clrsetbits_le32(TAMP_BOOT_CONTEXT, TAMP_BOOT_FORCED_MASK, BOOT_NORMAL);
}

/*
 * If there is no MAC address in the environment, then it will be initialized
 * (silently) from the value in the OTP.
 */
__weak int setup_mac_address(void)
{
	int ret;
	int i;
	u32 otp[3];
	uchar enetaddr[6];
	struct udevice *dev;
	int nb_eth, nb_otp, index;

	if (!IS_ENABLED(CONFIG_NET))
		return 0;

	nb_eth = get_eth_nb();

	/* 6 bytes for each MAC addr and 4 bytes for each OTP */
	nb_otp = DIV_ROUND_UP(6 * nb_eth, 4);

	ret = uclass_get_device_by_driver(UCLASS_MISC,
					  DM_DRIVER_GET(stm32mp_bsec),
					  &dev);
	if (ret)
		return ret;

	ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_MAC), otp, 4 * nb_otp);
	if (ret < 0)
		return ret;

	for (index = 0; index < nb_eth; index++) {
		/* MAC already in environment */
		if (eth_env_get_enetaddr_by_index("eth", index, enetaddr))
			continue;

		for (i = 0; i < 6; i++)
			enetaddr[i] = ((uint8_t *)&otp)[i + 6 * index];

		if (!is_valid_ethaddr(enetaddr)) {
			log_err("invalid MAC address %d in OTP %pM\n",
				index, enetaddr);
			return -EINVAL;
		}
		log_debug("OTP MAC address %d = %pM\n", index, enetaddr);
		ret = eth_env_set_enetaddr_by_index("eth", index, enetaddr);
		if (ret) {
			log_err("Failed to set mac address %pM from OTP: %d\n",
				enetaddr, ret);
			return ret;
		}
	}

	return 0;
}

static int setup_serial_number(void)
{
	char serial_string[25];
	u32 otp[3] = {0, 0, 0 };
	struct udevice *dev;
	int ret;

	if (env_get("serial#"))
		return 0;

	ret = uclass_get_device_by_driver(UCLASS_MISC,
					  DM_DRIVER_GET(stm32mp_bsec),
					  &dev);
	if (ret)
		return ret;

	ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_SERIAL),
			otp, sizeof(otp));
	if (ret < 0)
		return ret;

	sprintf(serial_string, "%08X%08X%08X", otp[0], otp[1], otp[2]);
	env_set("serial#", serial_string);

	return 0;
}

__weak void stm32mp_misc_init(void)
{
}

int arch_misc_init(void)
{
	setup_boot_mode();
	setup_mac_address();
	setup_serial_number();
	stm32mp_misc_init();

	return 0;
}

/*
 * Without forcing the ".data" section, this would get saved in ".bss". BSS
 * will be cleared soon after, so it's not suitable.
 */
static uintptr_t rom_api_table __section(".data");
static uintptr_t nt_fw_dtb __section(".data");

/*
 * The ROM gives us the API location in r0 when starting. This is only available
 * during SPL, as there isn't (yet) a mechanism to pass this on to u-boot. Save
 * the FDT address provided by TF-A in r2 at boot time. This function is called
 * from start.S
 */
void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2,
		      unsigned long r3)
{
	if (IS_ENABLED(CONFIG_STM32_ECDSA_VERIFY))
		rom_api_table = r0;

	if (IS_ENABLED(CONFIG_TFABOOT))
		nt_fw_dtb = r2;

	save_boot_params_ret();
}

uintptr_t get_stm32mp_rom_api_table(void)
{
	return rom_api_table;
}

uintptr_t get_stm32mp_bl2_dtb(void)
{
	return nt_fw_dtb;
}

#ifdef CONFIG_SPL_BUILD
void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
{
	typedef void __noreturn (*image_entry_stm32_t)(u32 romapi);
	uintptr_t romapi = get_stm32mp_rom_api_table();

	image_entry_stm32_t image_entry =
		(image_entry_stm32_t)spl_image->entry_point;

	printf("image entry point: 0x%lx\n", spl_image->entry_point);
	image_entry(romapi);
}
#endif
Commit	Line	Data
4549e789	1	// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2514c2d0 PD	2	/*
2514c2d0 PD	3	* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
2514c2d0	4	*/
eb653acd PD	5
	6	#define LOG_CATEGORY LOGC_ARCH
	7
2514c2d0 PD	8	#include <common.h>
2514c2d0 PD	9	#include <clk.h>
9edefc27	10	#include <cpu_func.h>
320d2663	11	#include <debug_uart.h>
9fb625ce	12	#include <env.h>
691d719d	13	#include <init.h>
f7ae49fc	14	#include <log.h>
ade4e042	15	#include <lmb.h>
7f7deb0c	16	#include <misc.h>
90526e9f	17	#include <net.h>
2514c2d0 PD	18	#include <asm/io.h>
2514c2d0 PD	19	#include <asm/arch/stm32.h>
96583cdc	20	#include <asm/arch/sys_proto.h>
401d1c4f	21	#include <asm/global_data.h>
7f7deb0c	22	#include <dm/device.h>
08772f6e	23	#include <dm/uclass.h>
cd93d625	24	#include <linux/bitops.h>
6eea5415	25	#include <spl.h>
2514c2d0	26
7e8471ca PD	27	/*
	28	* early TLB into the .data section so that it not get cleared
	29	* with 16kB allignment (see TTBR0_BASE_ADDR_MASK)
	30	*/
	31	u8 early_tlb[PGTABLE_SIZE] __section(".data") __aligned(0x4000);
	32
ade4e042 PD	33	struct lmb lmb;
ade4e042 PD	34
7f63c1e6 PD	35	u32 get_bootmode(void)
	36	{
	37	/* read bootmode from TAMP backup register */
	38	return (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_MODE_MASK) >>
	39	TAMP_BOOT_MODE_SHIFT;
08772f6e PD	40	}
08772f6e PD	41
aad84147 PD	42	/*
	43	* weak function overidde: set the DDR/SYSRAM executable before to enable the
	44	* MMU and configure DACR, for early early_enable_caches (SPL or pre-reloc)
	45	*/
	46	void dram_bank_mmu_setup(int bank)
	47	{
	48	struct bd_info *bd = gd->bd;
	49	int i;
	50	phys_addr_t start;
	51	phys_size_t size;
ade4e042 PD	52	bool use_lmb = false;
ade4e042 PD	53	enum dcache_option option;
aad84147 PD	54
aad84147 PD	55	if (IS_ENABLED(CONFIG_SPL_BUILD)) {
960debbe PD	56	/* STM32_SYSRAM_BASE exist only when SPL is supported */
960debbe PD	57	#ifdef CONFIG_SPL
aad84147 PD	58	start = ALIGN_DOWN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE);
aad84147 PD	59	size = ALIGN(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE);
960debbe	60	#endif
aad84147 PD	61	} else if (gd->flags & GD_FLG_RELOC) {
	62	/* bd->bi_dram is available only after relocation */
	63	start = bd->bi_dram[bank].start;
	64	size = bd->bi_dram[bank].size;
ade4e042	65	use_lmb = true;
aad84147 PD	66	} else {
	67	/* mark cacheable and executable the beggining of the DDR */
	68	start = STM32_DDR_BASE;
	69	size = CONFIG_DDR_CACHEABLE_SIZE;
	70	}
	71
	72	for (i = start >> MMU_SECTION_SHIFT;
	73	i < (start >> MMU_SECTION_SHIFT) + (size >> MMU_SECTION_SHIFT);
ade4e042 PD	74	i++) {
	75	option = DCACHE_DEFAULT_OPTION;
	76	if (use_lmb && lmb_is_reserved_flags(&lmb, i << MMU_SECTION_SHIFT, LMB_NOMAP))
	77	option = 0; /* INVALID ENTRY in TLB */
	78	set_section_dcache(i, option);
	79	}
aad84147	80	}
7e8471ca PD	81	/*
	82	* initialize the MMU and activate cache in SPL or in U-Boot pre-reloc stage
	83	* MMU/TLB is updated in enable_caches() for U-Boot after relocation
	84	* or is deactivated in U-Boot entry function start.S::cpu_init_cp15
	85	*/
	86	static void early_enable_caches(void)
	87	{
	88	/* I-cache is already enabled in start.S: cpu_init_cp15 */
	89
	90	if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
	91	return;
	92
23e20b2f PC	93	if (!(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))) {
	94	gd->arch.tlb_size = PGTABLE_SIZE;
	95	gd->arch.tlb_addr = (unsigned long)&early_tlb;
	96	}
7e8471ca	97
aad84147	98	/* enable MMU (default configuration) */
7e8471ca	99	dcache_enable();
7e8471ca PD	100	}
7e8471ca PD	101
08772f6e PD	102	/*
	103	* Early system init
	104	*/
2514c2d0 PD	105	int arch_cpu_init(void)
2514c2d0 PD	106	{
7e8471ca PD	107	early_enable_caches();
7e8471ca PD	108
2514c2d0 PD	109	/* early armv7 timer init: needed for polling */
	110	timer_init();
	111
6df271a7 PD	112	return 0;
	113	}
	114
	115	/* weak function for SOC specific initialization */
	116	__weak void stm32mp_cpu_init(void)
	117	{
	118	}
	119
	120	int mach_cpu_init(void)
	121	{
	122	u32 boot_mode;
	123
	124	stm32mp_cpu_init();
320d2663	125
320d2663 PD	126	boot_mode = get_bootmode();
320d2663 PD	127
5a05af87 PD	128	if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) &&
5a05af87 PD	129	(boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART)
320d2663	130	gd->flags \|= GD_FLG_SILENT \| GD_FLG_DISABLE_CONSOLE;
c8b2eef5	131	else if (IS_ENABLED(CONFIG_DEBUG_UART) && IS_ENABLED(CONFIG_SPL_BUILD))
320d2663	132	debug_uart_init();
2514c2d0 PD	133
	134	return 0;
	135	}
	136
cda3dcb6 PD	137	void enable_caches(void)
cda3dcb6 PD	138	{
ade4e042 PD	139	/* parse device tree when data cache is still activated */
	140	lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob);
	141
7e8471ca PD	142	/* I-cache is already enabled in start.S: icache_enable() not needed */
	143
	144	/* deactivate the data cache, early enabled in arch_cpu_init() */
	145	dcache_disable();
	146	/*
	147	* update MMU after relocation and enable the data cache
	148	* warning: the TLB location udpated in board_f.c::reserve_mmu
	149	*/
cda3dcb6 PD	150	dcache_enable();
	151	}
	152
c8b2eef5	153	/* used when CONFIG_DISPLAY_CPUINFO is activated */
ac5e4d8a PD	154	int print_cpuinfo(void)
	155	{
	156	char name[SOC_NAME_SIZE];
	157
	158	get_soc_name(name);
	159	printf("CPU: %s\n", name);
2514c2d0 PD	160
	161	return 0;
	162	}
2514c2d0	163
08772f6e PD	164	static void setup_boot_mode(void)
08772f6e PD	165	{
7f63c1e6 PD	166	const u32 serial_addr[] = {
	167	STM32_USART1_BASE,
	168	STM32_USART2_BASE,
	169	STM32_USART3_BASE,
	170	STM32_UART4_BASE,
	171	STM32_UART5_BASE,
	172	STM32_USART6_BASE,
	173	STM32_UART7_BASE,
	174	STM32_UART8_BASE
	175	};
3c1057c5 PD	176	const u32 sdmmc_addr[] = {
	177	STM32_SDMMC1_BASE,
	178	STM32_SDMMC2_BASE,
	179	STM32_SDMMC3_BASE
	180	};
08772f6e PD	181	char cmd[60];
	182	u32 boot_ctx = readl(TAMP_BOOT_CONTEXT);
	183	u32 boot_mode =
	184	(boot_ctx & TAMP_BOOT_MODE_MASK) >> TAMP_BOOT_MODE_SHIFT;
e609e131	185	unsigned int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1;
9a2ba283	186	u32 forced_mode = (boot_ctx & TAMP_BOOT_FORCED_MASK);
7f63c1e6	187	struct udevice *dev;
08772f6e	188
eb653acd PD	189	log_debug("%s: boot_ctx=0x%x => boot_mode=%x, instance=%d forced=%x\n",
eb653acd PD	190	__func__, boot_ctx, boot_mode, instance, forced_mode);
08772f6e PD	191	switch (boot_mode & TAMP_BOOT_DEVICE_MASK) {
08772f6e PD	192	case BOOT_SERIAL_UART:
7f63c1e6 PD	193	if (instance > ARRAY_SIZE(serial_addr))
7f63c1e6 PD	194	break;
f49eb16c	195	/* serial : search associated node in devicetree */
7f63c1e6	196	sprintf(cmd, "serial@%x", serial_addr[instance]);
f49eb16c	197	if (uclass_get_device_by_name(UCLASS_SERIAL, cmd, &dev)) {
b9d5e3aa PD	198	/* restore console on error */
	199	if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL))
	200	gd->flags &= ~(GD_FLG_SILENT \|
	201	GD_FLG_DISABLE_CONSOLE);
cbea7b3e PD	202	log_err("uart%d = %s not found in device tree!\n",
cbea7b3e PD	203	instance + 1, cmd);
7f63c1e6	204	break;
b9d5e3aa	205	}
f49eb16c	206	sprintf(cmd, "%d", dev_seq(dev));
7f63c1e6	207	env_set("boot_device", "serial");
08772f6e	208	env_set("boot_instance", cmd);
7f63c1e6 PD	209
7f63c1e6 PD	210	/* restore console on uart when not used */
5a05af87	211	if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) && gd->cur_serial_dev != dev) {
7f63c1e6 PD	212	gd->flags &= ~(GD_FLG_SILENT \|
7f63c1e6 PD	213	GD_FLG_DISABLE_CONSOLE);
cbea7b3e	214	log_info("serial boot with console enabled!\n");
7f63c1e6	215	}
08772f6e PD	216	break;
	217	case BOOT_SERIAL_USB:
	218	env_set("boot_device", "usb");
	219	env_set("boot_instance", "0");
	220	break;
	221	case BOOT_FLASH_SD:
	222	case BOOT_FLASH_EMMC:
3c1057c5 PD	223	if (instance > ARRAY_SIZE(sdmmc_addr))
	224	break;
	225	/* search associated sdmmc node in devicetree */
	226	sprintf(cmd, "mmc@%x", sdmmc_addr[instance]);
	227	if (uclass_get_device_by_name(UCLASS_MMC, cmd, &dev)) {
	228	printf("mmc%d = %s not found in device tree!\n",
	229	instance, cmd);
	230	break;
	231	}
	232	sprintf(cmd, "%d", dev_seq(dev));
08772f6e PD	233	env_set("boot_device", "mmc");
	234	env_set("boot_instance", cmd);
	235	break;
	236	case BOOT_FLASH_NAND:
	237	env_set("boot_device", "nand");
	238	env_set("boot_instance", "0");
	239	break;
b664a745 PD	240	case BOOT_FLASH_SPINAND:
	241	env_set("boot_device", "spi-nand");
	242	env_set("boot_instance", "0");
	243	break;
08772f6e PD	244	case BOOT_FLASH_NOR:
	245	env_set("boot_device", "nor");
	246	env_set("boot_instance", "0");
	247	break;
	248	default:
8b71b20e PD	249	env_set("boot_device", "invalid");
	250	env_set("boot_instance", "");
	251	log_err("unexpected boot mode = %x\n", boot_mode);
08772f6e PD	252	break;
08772f6e PD	253	}
9a2ba283 PD	254
	255	switch (forced_mode) {
	256	case BOOT_FASTBOOT:
cbea7b3e	257	log_info("Enter fastboot!\n");
9a2ba283 PD	258	env_set("preboot", "env set preboot; fastboot 0");
	259	break;
	260	case BOOT_STM32PROG:
	261	env_set("boot_device", "usb");
	262	env_set("boot_instance", "0");
	263	break;
	264	case BOOT_UMS_MMC0:
	265	case BOOT_UMS_MMC1:
	266	case BOOT_UMS_MMC2:
cbea7b3e	267	log_info("Enter UMS!\n");
9a2ba283 PD	268	instance = forced_mode - BOOT_UMS_MMC0;
	269	sprintf(cmd, "env set preboot; ums 0 mmc %d", instance);
	270	env_set("preboot", cmd);
	271	break;
	272	case BOOT_RECOVERY:
	273	env_set("preboot", "env set preboot; run altbootcmd");
	274	break;
	275	case BOOT_NORMAL:
	276	break;
	277	default:
eb653acd	278	log_debug("unexpected forced boot mode = %x\n", forced_mode);
9a2ba283 PD	279	break;
	280	}
	281
	282	/* clear TAMP for next reboot */
	283	clrsetbits_le32(TAMP_BOOT_CONTEXT, TAMP_BOOT_FORCED_MASK, BOOT_NORMAL);
08772f6e PD	284	}
08772f6e PD	285
7f7deb0c PD	286	/*
	287	* If there is no MAC address in the environment, then it will be initialized
	288	* (silently) from the value in the OTP.
	289	*/
e71b9a64	290	__weak int setup_mac_address(void)
7f7deb0c	291	{
7f7deb0c PD	292	int ret;
7f7deb0c PD	293	int i;
46f9eb5d	294	u32 otp[3];
7f7deb0c PD	295	uchar enetaddr[6];
7f7deb0c PD	296	struct udevice *dev;
46f9eb5d	297	int nb_eth, nb_otp, index;
7f7deb0c	298
c8b2eef5 PD	299	if (!IS_ENABLED(CONFIG_NET))
	300	return 0;
	301
46f9eb5d PD	302	nb_eth = get_eth_nb();
	303
	304	/* 6 bytes for each MAC addr and 4 bytes for each OTP */
	305	nb_otp = DIV_ROUND_UP(6 * nb_eth, 4);
7f7deb0c PD	306
7f7deb0c PD	307	ret = uclass_get_device_by_driver(UCLASS_MISC,
65e25bea	308	DM_DRIVER_GET(stm32mp_bsec),
7f7deb0c PD	309	&dev);
	310	if (ret)
	311	return ret;
	312
46f9eb5d	313	ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_MAC), otp, 4 * nb_otp);
8729b1ae	314	if (ret < 0)
7f7deb0c PD	315	return ret;
7f7deb0c PD	316
46f9eb5d PD	317	for (index = 0; index < nb_eth; index++) {
	318	/* MAC already in environment */
	319	if (eth_env_get_enetaddr_by_index("eth", index, enetaddr))
	320	continue;
	321
	322	for (i = 0; i < 6; i++)
	323	enetaddr[i] = ((uint8_t )&otp)[i + 6 index];
7f7deb0c	324
46f9eb5d PD	325	if (!is_valid_ethaddr(enetaddr)) {
	326	log_err("invalid MAC address %d in OTP %pM\n",
	327	index, enetaddr);
	328	return -EINVAL;
	329	}
	330	log_debug("OTP MAC address %d = %pM\n", index, enetaddr);
	331	ret = eth_env_set_enetaddr_by_index("eth", index, enetaddr);
	332	if (ret) {
	333	log_err("Failed to set mac address %pM from OTP: %d\n",
	334	enetaddr, ret);
	335	return ret;
	336	}
7f7deb0c	337	}
7f7deb0c PD	338
	339	return 0;
	340	}
	341
	342	static int setup_serial_number(void)
	343	{
	344	char serial_string[25];
	345	u32 otp[3] = {0, 0, 0 };
	346	struct udevice *dev;
	347	int ret;
	348
	349	if (env_get("serial#"))
	350	return 0;
	351
	352	ret = uclass_get_device_by_driver(UCLASS_MISC,
65e25bea	353	DM_DRIVER_GET(stm32mp_bsec),
7f7deb0c PD	354	&dev);
	355	if (ret)
	356	return ret;
	357
17f1f9b1	358	ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_SERIAL),
7f7deb0c	359	otp, sizeof(otp));
8729b1ae	360	if (ret < 0)
7f7deb0c PD	361	return ret;
7f7deb0c PD	362
8983ba27	363	sprintf(serial_string, "%08X%08X%08X", otp[0], otp[1], otp[2]);
7f7deb0c PD	364	env_set("serial#", serial_string);
	365
	366	return 0;
	367	}
	368
6df271a7	369	__weak void stm32mp_misc_init(void)
2c2d7d6a	370	{
2c2d7d6a MV	371	}
2c2d7d6a MV	372
08772f6e PD	373	int arch_misc_init(void)
	374	{
	375	setup_boot_mode();
7f7deb0c PD	376	setup_mac_address();
7f7deb0c PD	377	setup_serial_number();
6df271a7	378	stm32mp_misc_init();
08772f6e PD	379
	380	return 0;
	381	}
dbeaca79 MV	382
	383	/*
	384	* Without forcing the ".data" section, this would get saved in ".bss". BSS
	385	* will be cleared soon after, so it's not suitable.
	386	*/
	387	static uintptr_t rom_api_table __section(".data");
	388	static uintptr_t nt_fw_dtb __section(".data");
	389
	390	/*
	391	* The ROM gives us the API location in r0 when starting. This is only available
	392	* during SPL, as there isn't (yet) a mechanism to pass this on to u-boot. Save
	393	* the FDT address provided by TF-A in r2 at boot time. This function is called
	394	* from start.S
	395	*/
	396	void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2,
	397	unsigned long r3)
	398	{
	399	if (IS_ENABLED(CONFIG_STM32_ECDSA_VERIFY))
	400	rom_api_table = r0;
	401
	402	if (IS_ENABLED(CONFIG_TFABOOT))
	403	nt_fw_dtb = r2;
	404
	405	save_boot_params_ret();
	406	}
	407
	408	uintptr_t get_stm32mp_rom_api_table(void)
	409	{
	410	return rom_api_table;
	411	}
	412
	413	uintptr_t get_stm32mp_bl2_dtb(void)
	414	{
	415	return nt_fw_dtb;
	416	}
6eea5415 MV	417
	418	#ifdef CONFIG_SPL_BUILD
	419	void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
	420	{
	421	typedef void __noreturn (*image_entry_stm32_t)(u32 romapi);
	422	uintptr_t romapi = get_stm32mp_rom_api_table();
	423
	424	image_entry_stm32_t image_entry =
	425	(image_entry_stm32_t)spl_image->entry_point;
	426
	427	printf("image entry point: 0x%lx\n", spl_image->entry_point);
	428	image_entry(romapi);
	429	}
	430	#endif