Commit | Line | Data |
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4549e789 | 1 | // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause |
2514c2d0 PD |
2 | /* |
3 | * Copyright (C) 2018, STMicroelectronics - All Rights Reserved | |
2514c2d0 | 4 | */ |
eb653acd PD |
5 | |
6 | #define LOG_CATEGORY LOGC_ARCH | |
7 | ||
2514c2d0 PD |
8 | #include <common.h> |
9 | #include <clk.h> | |
9edefc27 | 10 | #include <cpu_func.h> |
320d2663 | 11 | #include <debug_uart.h> |
9fb625ce | 12 | #include <env.h> |
691d719d | 13 | #include <init.h> |
f7ae49fc | 14 | #include <log.h> |
ade4e042 | 15 | #include <lmb.h> |
7f7deb0c | 16 | #include <misc.h> |
90526e9f | 17 | #include <net.h> |
2514c2d0 | 18 | #include <asm/io.h> |
bd3f60d2 | 19 | #include <asm/arch/bsec.h> |
2514c2d0 | 20 | #include <asm/arch/stm32.h> |
96583cdc | 21 | #include <asm/arch/sys_proto.h> |
401d1c4f | 22 | #include <asm/global_data.h> |
7f7deb0c | 23 | #include <dm/device.h> |
08772f6e | 24 | #include <dm/uclass.h> |
cd93d625 | 25 | #include <linux/bitops.h> |
2514c2d0 | 26 | |
cda3dcb6 PD |
27 | /* RCC register */ |
28 | #define RCC_TZCR (STM32_RCC_BASE + 0x00) | |
29 | #define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C) | |
30 | #define RCC_BDCR (STM32_RCC_BASE + 0x0140) | |
31 | #define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x0208) | |
59a54e37 | 32 | #define RCC_MP_AHB5ENSETR (STM32_RCC_BASE + 0x0210) |
cda3dcb6 PD |
33 | #define RCC_BDCR_VSWRST BIT(31) |
34 | #define RCC_BDCR_RTCSRC GENMASK(17, 16) | |
35 | #define RCC_DBGCFGR_DBGCKEN BIT(8) | |
2514c2d0 | 36 | |
cda3dcb6 | 37 | /* Security register */ |
2514c2d0 PD |
38 | #define ETZPC_TZMA1_SIZE (STM32_ETZPC_BASE + 0x04) |
39 | #define ETZPC_DECPROT0 (STM32_ETZPC_BASE + 0x10) | |
40 | ||
41 | #define TZC_GATE_KEEPER (STM32_TZC_BASE + 0x008) | |
42 | #define TZC_REGION_ATTRIBUTE0 (STM32_TZC_BASE + 0x110) | |
43 | #define TZC_REGION_ID_ACCESS0 (STM32_TZC_BASE + 0x114) | |
44 | ||
45 | #define TAMP_CR1 (STM32_TAMP_BASE + 0x00) | |
46 | ||
47 | #define PWR_CR1 (STM32_PWR_BASE + 0x00) | |
7bff971a | 48 | #define PWR_MCUCR (STM32_PWR_BASE + 0x14) |
2514c2d0 | 49 | #define PWR_CR1_DBP BIT(8) |
7bff971a | 50 | #define PWR_MCUCR_SBF BIT(6) |
2514c2d0 | 51 | |
cda3dcb6 | 52 | /* DBGMCU register */ |
96583cdc | 53 | #define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00) |
cda3dcb6 PD |
54 | #define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C) |
55 | #define DBGMCU_APB4FZ1_IWDG2 BIT(2) | |
96583cdc PD |
56 | #define DBGMCU_IDC_DEV_ID_MASK GENMASK(11, 0) |
57 | #define DBGMCU_IDC_DEV_ID_SHIFT 0 | |
58 | #define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16) | |
59 | #define DBGMCU_IDC_REV_ID_SHIFT 16 | |
2514c2d0 | 60 | |
59a54e37 PD |
61 | /* GPIOZ registers */ |
62 | #define GPIOZ_SECCFGR 0x54004030 | |
63 | ||
08772f6e PD |
64 | /* boot interface from Bootrom |
65 | * - boot instance = bit 31:16 | |
66 | * - boot device = bit 15:0 | |
67 | */ | |
68 | #define BOOTROM_PARAM_ADDR 0x2FFC0078 | |
69 | #define BOOTROM_MODE_MASK GENMASK(15, 0) | |
70 | #define BOOTROM_MODE_SHIFT 0 | |
71 | #define BOOTROM_INSTANCE_MASK GENMASK(31, 16) | |
72 | #define BOOTROM_INSTANCE_SHIFT 16 | |
73 | ||
35d568f0 PD |
74 | /* Device Part Number (RPN) = OTP_DATA1 lower 8 bits */ |
75 | #define RPN_SHIFT 0 | |
76 | #define RPN_MASK GENMASK(7, 0) | |
77 | ||
78 | /* Package = bit 27:29 of OTP16 | |
79 | * - 100: LBGA448 (FFI) => AA = LFBGA 18x18mm 448 balls p. 0.8mm | |
80 | * - 011: LBGA354 (LCI) => AB = LFBGA 16x16mm 359 balls p. 0.8mm | |
81 | * - 010: TFBGA361 (FFC) => AC = TFBGA 12x12mm 361 balls p. 0.5mm | |
82 | * - 001: TFBGA257 (LCC) => AD = TFBGA 10x10mm 257 balls p. 0.5mm | |
83 | * - others: Reserved | |
84 | */ | |
85 | #define PKG_SHIFT 27 | |
86 | #define PKG_MASK GENMASK(2, 0) | |
87 | ||
7e8471ca PD |
88 | /* |
89 | * early TLB into the .data section so that it not get cleared | |
90 | * with 16kB allignment (see TTBR0_BASE_ADDR_MASK) | |
91 | */ | |
92 | u8 early_tlb[PGTABLE_SIZE] __section(".data") __aligned(0x4000); | |
93 | ||
ade4e042 PD |
94 | struct lmb lmb; |
95 | ||
cda3dcb6 | 96 | #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) |
654706be | 97 | #ifndef CONFIG_TFABOOT |
2514c2d0 PD |
98 | static void security_init(void) |
99 | { | |
100 | /* Disable the backup domain write protection */ | |
101 | /* the protection is enable at each reset by hardware */ | |
102 | /* And must be disable by software */ | |
103 | setbits_le32(PWR_CR1, PWR_CR1_DBP); | |
104 | ||
105 | while (!(readl(PWR_CR1) & PWR_CR1_DBP)) | |
106 | ; | |
107 | ||
108 | /* If RTC clock isn't enable so this is a cold boot then we need | |
109 | * to reset the backup domain | |
110 | */ | |
111 | if (!(readl(RCC_BDCR) & RCC_BDCR_RTCSRC)) { | |
112 | setbits_le32(RCC_BDCR, RCC_BDCR_VSWRST); | |
113 | while (!(readl(RCC_BDCR) & RCC_BDCR_VSWRST)) | |
114 | ; | |
115 | clrbits_le32(RCC_BDCR, RCC_BDCR_VSWRST); | |
116 | } | |
117 | ||
118 | /* allow non secure access in Write/Read for all peripheral */ | |
119 | writel(GENMASK(25, 0), ETZPC_DECPROT0); | |
120 | ||
121 | /* Open SYSRAM for no secure access */ | |
122 | writel(0x0, ETZPC_TZMA1_SIZE); | |
123 | ||
124 | /* enable TZC1 TZC2 clock */ | |
125 | writel(BIT(11) | BIT(12), RCC_MP_APB5ENSETR); | |
126 | ||
127 | /* Region 0 set to no access by default */ | |
128 | /* bit 0 / 16 => nsaid0 read/write Enable | |
129 | * bit 1 / 17 => nsaid1 read/write Enable | |
130 | * ... | |
131 | * bit 15 / 31 => nsaid15 read/write Enable | |
132 | */ | |
133 | writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS0); | |
134 | /* bit 30 / 31 => Secure Global Enable : write/read */ | |
135 | /* bit 0 / 1 => Region Enable for filter 0/1 */ | |
136 | writel(BIT(0) | BIT(1) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE0); | |
137 | ||
138 | /* Enable Filter 0 and 1 */ | |
139 | setbits_le32(TZC_GATE_KEEPER, BIT(0) | BIT(1)); | |
140 | ||
141 | /* RCC trust zone deactivated */ | |
142 | writel(0x0, RCC_TZCR); | |
143 | ||
144 | /* TAMP: deactivate the internal tamper | |
145 | * Bit 23 ITAMP8E: monotonic counter overflow | |
146 | * Bit 20 ITAMP5E: RTC calendar overflow | |
147 | * Bit 19 ITAMP4E: HSE monitoring | |
148 | * Bit 18 ITAMP3E: LSE monitoring | |
149 | * Bit 16 ITAMP1E: RTC power domain supply monitoring | |
150 | */ | |
151 | writel(0x0, TAMP_CR1); | |
59a54e37 PD |
152 | |
153 | /* GPIOZ: deactivate the security */ | |
154 | writel(BIT(0), RCC_MP_AHB5ENSETR); | |
155 | writel(0x0, GPIOZ_SECCFGR); | |
2514c2d0 | 156 | } |
654706be | 157 | #endif /* CONFIG_TFABOOT */ |
2514c2d0 | 158 | |
cda3dcb6 | 159 | /* |
2514c2d0 | 160 | * Debug init |
cda3dcb6 | 161 | */ |
2514c2d0 PD |
162 | static void dbgmcu_init(void) |
163 | { | |
bd3f60d2 PD |
164 | /* |
165 | * Freeze IWDG2 if Cortex-A7 is in debug mode | |
166 | * done in TF-A for TRUSTED boot and | |
167 | * DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE | |
168 | */ | |
97f7e39d PD |
169 | if (!IS_ENABLED(CONFIG_TFABOOT) && bsec_dbgswenable()) { |
170 | setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN); | |
bd3f60d2 | 171 | setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2); |
97f7e39d PD |
172 | } |
173 | } | |
174 | ||
175 | void spl_board_init(void) | |
176 | { | |
177 | dbgmcu_init(); | |
2514c2d0 PD |
178 | } |
179 | #endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */ | |
180 | ||
654706be | 181 | #if !defined(CONFIG_TFABOOT) && \ |
abf2678f | 182 | (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)) |
7f63c1e6 PD |
183 | /* get bootmode from ROM code boot context: saved in TAMP register */ |
184 | static void update_bootmode(void) | |
185 | { | |
186 | u32 boot_mode; | |
08772f6e PD |
187 | u32 bootrom_itf = readl(BOOTROM_PARAM_ADDR); |
188 | u32 bootrom_device, bootrom_instance; | |
189 | ||
7f63c1e6 PD |
190 | /* enable TAMP clock = RTCAPBEN */ |
191 | writel(BIT(8), RCC_MP_APB5ENSETR); | |
192 | ||
193 | /* read bootrom context */ | |
08772f6e PD |
194 | bootrom_device = |
195 | (bootrom_itf & BOOTROM_MODE_MASK) >> BOOTROM_MODE_SHIFT; | |
196 | bootrom_instance = | |
197 | (bootrom_itf & BOOTROM_INSTANCE_MASK) >> BOOTROM_INSTANCE_SHIFT; | |
198 | boot_mode = | |
199 | ((bootrom_device << BOOT_TYPE_SHIFT) & BOOT_TYPE_MASK) | | |
200 | ((bootrom_instance << BOOT_INSTANCE_SHIFT) & | |
201 | BOOT_INSTANCE_MASK); | |
202 | ||
203 | /* save the boot mode in TAMP backup register */ | |
204 | clrsetbits_le32(TAMP_BOOT_CONTEXT, | |
205 | TAMP_BOOT_MODE_MASK, | |
206 | boot_mode << TAMP_BOOT_MODE_SHIFT); | |
7f63c1e6 | 207 | } |
08772f6e | 208 | #endif |
7f63c1e6 PD |
209 | |
210 | u32 get_bootmode(void) | |
211 | { | |
212 | /* read bootmode from TAMP backup register */ | |
213 | return (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_MODE_MASK) >> | |
214 | TAMP_BOOT_MODE_SHIFT; | |
08772f6e PD |
215 | } |
216 | ||
aad84147 PD |
217 | /* |
218 | * weak function overidde: set the DDR/SYSRAM executable before to enable the | |
219 | * MMU and configure DACR, for early early_enable_caches (SPL or pre-reloc) | |
220 | */ | |
221 | void dram_bank_mmu_setup(int bank) | |
222 | { | |
223 | struct bd_info *bd = gd->bd; | |
224 | int i; | |
225 | phys_addr_t start; | |
226 | phys_size_t size; | |
ade4e042 PD |
227 | bool use_lmb = false; |
228 | enum dcache_option option; | |
aad84147 PD |
229 | |
230 | if (IS_ENABLED(CONFIG_SPL_BUILD)) { | |
231 | start = ALIGN_DOWN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE); | |
232 | size = ALIGN(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE); | |
233 | } else if (gd->flags & GD_FLG_RELOC) { | |
234 | /* bd->bi_dram is available only after relocation */ | |
235 | start = bd->bi_dram[bank].start; | |
236 | size = bd->bi_dram[bank].size; | |
ade4e042 | 237 | use_lmb = true; |
aad84147 PD |
238 | } else { |
239 | /* mark cacheable and executable the beggining of the DDR */ | |
240 | start = STM32_DDR_BASE; | |
241 | size = CONFIG_DDR_CACHEABLE_SIZE; | |
242 | } | |
243 | ||
244 | for (i = start >> MMU_SECTION_SHIFT; | |
245 | i < (start >> MMU_SECTION_SHIFT) + (size >> MMU_SECTION_SHIFT); | |
ade4e042 PD |
246 | i++) { |
247 | option = DCACHE_DEFAULT_OPTION; | |
248 | if (use_lmb && lmb_is_reserved_flags(&lmb, i << MMU_SECTION_SHIFT, LMB_NOMAP)) | |
249 | option = 0; /* INVALID ENTRY in TLB */ | |
250 | set_section_dcache(i, option); | |
251 | } | |
aad84147 | 252 | } |
7e8471ca PD |
253 | /* |
254 | * initialize the MMU and activate cache in SPL or in U-Boot pre-reloc stage | |
255 | * MMU/TLB is updated in enable_caches() for U-Boot after relocation | |
256 | * or is deactivated in U-Boot entry function start.S::cpu_init_cp15 | |
257 | */ | |
258 | static void early_enable_caches(void) | |
259 | { | |
260 | /* I-cache is already enabled in start.S: cpu_init_cp15 */ | |
261 | ||
262 | if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) | |
263 | return; | |
264 | ||
23e20b2f PC |
265 | if (!(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))) { |
266 | gd->arch.tlb_size = PGTABLE_SIZE; | |
267 | gd->arch.tlb_addr = (unsigned long)&early_tlb; | |
268 | } | |
7e8471ca | 269 | |
aad84147 | 270 | /* enable MMU (default configuration) */ |
7e8471ca | 271 | dcache_enable(); |
7e8471ca PD |
272 | } |
273 | ||
08772f6e PD |
274 | /* |
275 | * Early system init | |
276 | */ | |
2514c2d0 PD |
277 | int arch_cpu_init(void) |
278 | { | |
320d2663 PD |
279 | u32 boot_mode; |
280 | ||
7e8471ca PD |
281 | early_enable_caches(); |
282 | ||
2514c2d0 PD |
283 | /* early armv7 timer init: needed for polling */ |
284 | timer_init(); | |
285 | ||
286 | #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) | |
654706be | 287 | #ifndef CONFIG_TFABOOT |
2514c2d0 | 288 | security_init(); |
7f63c1e6 | 289 | update_bootmode(); |
abf2678f | 290 | #endif |
7bff971a FD |
291 | /* Reset Coprocessor state unless it wakes up from Standby power mode */ |
292 | if (!(readl(PWR_MCUCR) & PWR_MCUCR_SBF)) { | |
293 | writel(TAMP_COPRO_STATE_OFF, TAMP_COPRO_STATE); | |
294 | writel(0, TAMP_COPRO_RSC_TBL_ADDRESS); | |
295 | } | |
2514c2d0 | 296 | #endif |
320d2663 | 297 | |
320d2663 PD |
298 | boot_mode = get_bootmode(); |
299 | ||
5a05af87 PD |
300 | if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) && |
301 | (boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART) | |
320d2663 PD |
302 | gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; |
303 | #if defined(CONFIG_DEBUG_UART) && \ | |
654706be | 304 | !defined(CONFIG_TFABOOT) && \ |
320d2663 PD |
305 | (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)) |
306 | else | |
307 | debug_uart_init(); | |
308 | #endif | |
2514c2d0 PD |
309 | |
310 | return 0; | |
311 | } | |
312 | ||
cda3dcb6 PD |
313 | void enable_caches(void) |
314 | { | |
ade4e042 PD |
315 | /* parse device tree when data cache is still activated */ |
316 | lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob); | |
317 | ||
7e8471ca PD |
318 | /* I-cache is already enabled in start.S: icache_enable() not needed */ |
319 | ||
320 | /* deactivate the data cache, early enabled in arch_cpu_init() */ | |
321 | dcache_disable(); | |
322 | /* | |
323 | * update MMU after relocation and enable the data cache | |
324 | * warning: the TLB location udpated in board_f.c::reserve_mmu | |
325 | */ | |
cda3dcb6 PD |
326 | dcache_enable(); |
327 | } | |
328 | ||
96583cdc PD |
329 | static u32 read_idc(void) |
330 | { | |
bd3f60d2 PD |
331 | /* DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE */ |
332 | if (bsec_dbgswenable()) { | |
333 | setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN); | |
96583cdc | 334 | |
bd3f60d2 PD |
335 | return readl(DBGMCU_IDC); |
336 | } | |
337 | ||
338 | if (CONFIG_IS_ENABLED(STM32MP15x)) | |
339 | return CPU_DEV_STM32MP15; /* STM32MP15x and unknown revision */ | |
340 | else | |
341 | return 0x0; | |
96583cdc PD |
342 | } |
343 | ||
7802a449 PD |
344 | u32 get_cpu_dev(void) |
345 | { | |
346 | return (read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT; | |
347 | } | |
348 | ||
96583cdc PD |
349 | u32 get_cpu_rev(void) |
350 | { | |
351 | return (read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT; | |
352 | } | |
353 | ||
35d568f0 PD |
354 | static u32 get_otp(int index, int shift, int mask) |
355 | { | |
356 | int ret; | |
357 | struct udevice *dev; | |
358 | u32 otp = 0; | |
359 | ||
360 | ret = uclass_get_device_by_driver(UCLASS_MISC, | |
65e25bea | 361 | DM_DRIVER_GET(stm32mp_bsec), |
35d568f0 PD |
362 | &dev); |
363 | ||
364 | if (!ret) | |
365 | ret = misc_read(dev, STM32_BSEC_SHADOW(index), | |
366 | &otp, sizeof(otp)); | |
367 | ||
368 | return (otp >> shift) & mask; | |
369 | } | |
370 | ||
371 | /* Get Device Part Number (RPN) from OTP */ | |
372 | static u32 get_cpu_rpn(void) | |
373 | { | |
374 | return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK); | |
375 | } | |
376 | ||
96583cdc PD |
377 | u32 get_cpu_type(void) |
378 | { | |
7802a449 | 379 | return (get_cpu_dev() << 16) | get_cpu_rpn(); |
35d568f0 PD |
380 | } |
381 | ||
382 | /* Get Package options from OTP */ | |
24cb4587 | 383 | u32 get_cpu_package(void) |
35d568f0 PD |
384 | { |
385 | return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK); | |
96583cdc PD |
386 | } |
387 | ||
2c2d7d6a MV |
388 | static const char * const soc_type[] = { |
389 | "????", | |
390 | "151C", "151A", "151F", "151D", | |
391 | "153C", "153A", "153F", "153D", | |
392 | "157C", "157A", "157F", "157D" | |
393 | }; | |
394 | ||
395 | static const char * const soc_pkg[] = { "??", "AD", "AC", "AB", "AA" }; | |
396 | static const char * const soc_rev[] = { "?", "A", "B", "Z" }; | |
397 | ||
398 | static void get_cpu_string_offsets(unsigned int *type, unsigned int *pkg, | |
399 | unsigned int *rev) | |
2514c2d0 | 400 | { |
2c2d7d6a MV |
401 | u32 cpu_type = get_cpu_type(); |
402 | u32 ct = cpu_type & ~(BIT(7) | BIT(0)); | |
403 | u32 cm = ((cpu_type & BIT(7)) >> 6) | (cpu_type & BIT(0)); | |
404 | u32 cp = get_cpu_package(); | |
96583cdc | 405 | |
2c2d7d6a MV |
406 | /* Bits 0 and 7 are the ACDF, 00:C 01:A 10:F 11:D */ |
407 | switch (ct) { | |
408 | case CPU_STM32MP151Cxx: | |
409 | *type = cm + 1; | |
050fed8a | 410 | break; |
35d568f0 | 411 | case CPU_STM32MP153Cxx: |
2c2d7d6a | 412 | *type = cm + 5; |
050fed8a | 413 | break; |
2c2d7d6a MV |
414 | case CPU_STM32MP157Cxx: |
415 | *type = cm + 9; | |
35d568f0 PD |
416 | break; |
417 | default: | |
2c2d7d6a | 418 | *type = 0; |
35d568f0 PD |
419 | break; |
420 | } | |
421 | ||
422 | /* Package */ | |
2c2d7d6a | 423 | switch (cp) { |
35d568f0 | 424 | case PKG_AA_LBGA448: |
35d568f0 | 425 | case PKG_AB_LBGA354: |
35d568f0 | 426 | case PKG_AC_TFBGA361: |
35d568f0 | 427 | case PKG_AD_TFBGA257: |
2c2d7d6a | 428 | *pkg = cp; |
96583cdc PD |
429 | break; |
430 | default: | |
2c2d7d6a | 431 | *pkg = 0; |
96583cdc PD |
432 | break; |
433 | } | |
434 | ||
2c2d7d6a | 435 | /* Revision */ |
96583cdc PD |
436 | switch (get_cpu_rev()) { |
437 | case CPU_REVA: | |
2c2d7d6a | 438 | *rev = 1; |
96583cdc PD |
439 | break; |
440 | case CPU_REVB: | |
2c2d7d6a | 441 | *rev = 2; |
96583cdc | 442 | break; |
cf0818b4 | 443 | case CPU_REVZ: |
2c2d7d6a | 444 | *rev = 3; |
cf0818b4 | 445 | break; |
96583cdc | 446 | default: |
2c2d7d6a | 447 | *rev = 0; |
96583cdc PD |
448 | break; |
449 | } | |
2c2d7d6a MV |
450 | } |
451 | ||
452 | void get_soc_name(char name[SOC_NAME_SIZE]) | |
453 | { | |
454 | unsigned int type, pkg, rev; | |
96583cdc | 455 | |
2c2d7d6a MV |
456 | get_cpu_string_offsets(&type, &pkg, &rev); |
457 | ||
458 | snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s", | |
459 | soc_type[type], soc_pkg[pkg], soc_rev[rev]); | |
ac5e4d8a PD |
460 | } |
461 | ||
462 | #if defined(CONFIG_DISPLAY_CPUINFO) | |
463 | int print_cpuinfo(void) | |
464 | { | |
465 | char name[SOC_NAME_SIZE]; | |
466 | ||
467 | get_soc_name(name); | |
468 | printf("CPU: %s\n", name); | |
2514c2d0 PD |
469 | |
470 | return 0; | |
471 | } | |
472 | #endif /* CONFIG_DISPLAY_CPUINFO */ | |
473 | ||
08772f6e PD |
474 | static void setup_boot_mode(void) |
475 | { | |
7f63c1e6 PD |
476 | const u32 serial_addr[] = { |
477 | STM32_USART1_BASE, | |
478 | STM32_USART2_BASE, | |
479 | STM32_USART3_BASE, | |
480 | STM32_UART4_BASE, | |
481 | STM32_UART5_BASE, | |
482 | STM32_USART6_BASE, | |
483 | STM32_UART7_BASE, | |
484 | STM32_UART8_BASE | |
485 | }; | |
3c1057c5 PD |
486 | const u32 sdmmc_addr[] = { |
487 | STM32_SDMMC1_BASE, | |
488 | STM32_SDMMC2_BASE, | |
489 | STM32_SDMMC3_BASE | |
490 | }; | |
08772f6e PD |
491 | char cmd[60]; |
492 | u32 boot_ctx = readl(TAMP_BOOT_CONTEXT); | |
493 | u32 boot_mode = | |
494 | (boot_ctx & TAMP_BOOT_MODE_MASK) >> TAMP_BOOT_MODE_SHIFT; | |
e609e131 | 495 | unsigned int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1; |
9a2ba283 | 496 | u32 forced_mode = (boot_ctx & TAMP_BOOT_FORCED_MASK); |
7f63c1e6 | 497 | struct udevice *dev; |
08772f6e | 498 | |
eb653acd PD |
499 | log_debug("%s: boot_ctx=0x%x => boot_mode=%x, instance=%d forced=%x\n", |
500 | __func__, boot_ctx, boot_mode, instance, forced_mode); | |
08772f6e PD |
501 | switch (boot_mode & TAMP_BOOT_DEVICE_MASK) { |
502 | case BOOT_SERIAL_UART: | |
7f63c1e6 PD |
503 | if (instance > ARRAY_SIZE(serial_addr)) |
504 | break; | |
f49eb16c | 505 | /* serial : search associated node in devicetree */ |
7f63c1e6 | 506 | sprintf(cmd, "serial@%x", serial_addr[instance]); |
f49eb16c | 507 | if (uclass_get_device_by_name(UCLASS_SERIAL, cmd, &dev)) { |
b9d5e3aa PD |
508 | /* restore console on error */ |
509 | if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL)) | |
510 | gd->flags &= ~(GD_FLG_SILENT | | |
511 | GD_FLG_DISABLE_CONSOLE); | |
cbea7b3e PD |
512 | log_err("uart%d = %s not found in device tree!\n", |
513 | instance + 1, cmd); | |
7f63c1e6 | 514 | break; |
b9d5e3aa | 515 | } |
f49eb16c | 516 | sprintf(cmd, "%d", dev_seq(dev)); |
7f63c1e6 | 517 | env_set("boot_device", "serial"); |
08772f6e | 518 | env_set("boot_instance", cmd); |
7f63c1e6 PD |
519 | |
520 | /* restore console on uart when not used */ | |
5a05af87 | 521 | if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) && gd->cur_serial_dev != dev) { |
7f63c1e6 PD |
522 | gd->flags &= ~(GD_FLG_SILENT | |
523 | GD_FLG_DISABLE_CONSOLE); | |
cbea7b3e | 524 | log_info("serial boot with console enabled!\n"); |
7f63c1e6 | 525 | } |
08772f6e PD |
526 | break; |
527 | case BOOT_SERIAL_USB: | |
528 | env_set("boot_device", "usb"); | |
529 | env_set("boot_instance", "0"); | |
530 | break; | |
531 | case BOOT_FLASH_SD: | |
532 | case BOOT_FLASH_EMMC: | |
3c1057c5 PD |
533 | if (instance > ARRAY_SIZE(sdmmc_addr)) |
534 | break; | |
535 | /* search associated sdmmc node in devicetree */ | |
536 | sprintf(cmd, "mmc@%x", sdmmc_addr[instance]); | |
537 | if (uclass_get_device_by_name(UCLASS_MMC, cmd, &dev)) { | |
538 | printf("mmc%d = %s not found in device tree!\n", | |
539 | instance, cmd); | |
540 | break; | |
541 | } | |
542 | sprintf(cmd, "%d", dev_seq(dev)); | |
08772f6e PD |
543 | env_set("boot_device", "mmc"); |
544 | env_set("boot_instance", cmd); | |
545 | break; | |
546 | case BOOT_FLASH_NAND: | |
547 | env_set("boot_device", "nand"); | |
548 | env_set("boot_instance", "0"); | |
549 | break; | |
b664a745 PD |
550 | case BOOT_FLASH_SPINAND: |
551 | env_set("boot_device", "spi-nand"); | |
552 | env_set("boot_instance", "0"); | |
553 | break; | |
08772f6e PD |
554 | case BOOT_FLASH_NOR: |
555 | env_set("boot_device", "nor"); | |
556 | env_set("boot_instance", "0"); | |
557 | break; | |
558 | default: | |
eb653acd | 559 | log_debug("unexpected boot mode = %x\n", boot_mode); |
08772f6e PD |
560 | break; |
561 | } | |
9a2ba283 PD |
562 | |
563 | switch (forced_mode) { | |
564 | case BOOT_FASTBOOT: | |
cbea7b3e | 565 | log_info("Enter fastboot!\n"); |
9a2ba283 PD |
566 | env_set("preboot", "env set preboot; fastboot 0"); |
567 | break; | |
568 | case BOOT_STM32PROG: | |
569 | env_set("boot_device", "usb"); | |
570 | env_set("boot_instance", "0"); | |
571 | break; | |
572 | case BOOT_UMS_MMC0: | |
573 | case BOOT_UMS_MMC1: | |
574 | case BOOT_UMS_MMC2: | |
cbea7b3e | 575 | log_info("Enter UMS!\n"); |
9a2ba283 PD |
576 | instance = forced_mode - BOOT_UMS_MMC0; |
577 | sprintf(cmd, "env set preboot; ums 0 mmc %d", instance); | |
578 | env_set("preboot", cmd); | |
579 | break; | |
580 | case BOOT_RECOVERY: | |
581 | env_set("preboot", "env set preboot; run altbootcmd"); | |
582 | break; | |
583 | case BOOT_NORMAL: | |
584 | break; | |
585 | default: | |
eb653acd | 586 | log_debug("unexpected forced boot mode = %x\n", forced_mode); |
9a2ba283 PD |
587 | break; |
588 | } | |
589 | ||
590 | /* clear TAMP for next reboot */ | |
591 | clrsetbits_le32(TAMP_BOOT_CONTEXT, TAMP_BOOT_FORCED_MASK, BOOT_NORMAL); | |
08772f6e PD |
592 | } |
593 | ||
7f7deb0c PD |
594 | /* |
595 | * If there is no MAC address in the environment, then it will be initialized | |
596 | * (silently) from the value in the OTP. | |
597 | */ | |
e71b9a64 | 598 | __weak int setup_mac_address(void) |
7f7deb0c PD |
599 | { |
600 | #if defined(CONFIG_NET) | |
601 | int ret; | |
602 | int i; | |
603 | u32 otp[2]; | |
604 | uchar enetaddr[6]; | |
605 | struct udevice *dev; | |
606 | ||
607 | /* MAC already in environment */ | |
608 | if (eth_env_get_enetaddr("ethaddr", enetaddr)) | |
609 | return 0; | |
610 | ||
611 | ret = uclass_get_device_by_driver(UCLASS_MISC, | |
65e25bea | 612 | DM_DRIVER_GET(stm32mp_bsec), |
7f7deb0c PD |
613 | &dev); |
614 | if (ret) | |
615 | return ret; | |
616 | ||
17f1f9b1 | 617 | ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_MAC), |
7f7deb0c | 618 | otp, sizeof(otp)); |
8729b1ae | 619 | if (ret < 0) |
7f7deb0c PD |
620 | return ret; |
621 | ||
622 | for (i = 0; i < 6; i++) | |
623 | enetaddr[i] = ((uint8_t *)&otp)[i]; | |
624 | ||
625 | if (!is_valid_ethaddr(enetaddr)) { | |
eb653acd | 626 | log_err("invalid MAC address in OTP %pM\n", enetaddr); |
7f7deb0c PD |
627 | return -EINVAL; |
628 | } | |
eb653acd | 629 | log_debug("OTP MAC address = %pM\n", enetaddr); |
cf8df340 PD |
630 | ret = eth_env_set_enetaddr("ethaddr", enetaddr); |
631 | if (ret) | |
eb653acd | 632 | log_err("Failed to set mac address %pM from OTP: %d\n", enetaddr, ret); |
7f7deb0c PD |
633 | #endif |
634 | ||
635 | return 0; | |
636 | } | |
637 | ||
638 | static int setup_serial_number(void) | |
639 | { | |
640 | char serial_string[25]; | |
641 | u32 otp[3] = {0, 0, 0 }; | |
642 | struct udevice *dev; | |
643 | int ret; | |
644 | ||
645 | if (env_get("serial#")) | |
646 | return 0; | |
647 | ||
648 | ret = uclass_get_device_by_driver(UCLASS_MISC, | |
65e25bea | 649 | DM_DRIVER_GET(stm32mp_bsec), |
7f7deb0c PD |
650 | &dev); |
651 | if (ret) | |
652 | return ret; | |
653 | ||
17f1f9b1 | 654 | ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_SERIAL), |
7f7deb0c | 655 | otp, sizeof(otp)); |
8729b1ae | 656 | if (ret < 0) |
7f7deb0c PD |
657 | return ret; |
658 | ||
8983ba27 | 659 | sprintf(serial_string, "%08X%08X%08X", otp[0], otp[1], otp[2]); |
7f7deb0c PD |
660 | env_set("serial#", serial_string); |
661 | ||
662 | return 0; | |
663 | } | |
664 | ||
2c2d7d6a MV |
665 | static void setup_soc_type_pkg_rev(void) |
666 | { | |
667 | unsigned int type, pkg, rev; | |
668 | ||
669 | get_cpu_string_offsets(&type, &pkg, &rev); | |
670 | ||
671 | env_set("soc_type", soc_type[type]); | |
672 | env_set("soc_pkg", soc_pkg[pkg]); | |
673 | env_set("soc_rev", soc_rev[rev]); | |
674 | } | |
675 | ||
08772f6e PD |
676 | int arch_misc_init(void) |
677 | { | |
678 | setup_boot_mode(); | |
7f7deb0c PD |
679 | setup_mac_address(); |
680 | setup_serial_number(); | |
2c2d7d6a | 681 | setup_soc_type_pkg_rev(); |
08772f6e PD |
682 | |
683 | return 0; | |
684 | } |