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hw/ppc: use error_report instead of fprintf
[qemu.git] / hw / ppc / spapr.c
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9fdf0c29
DG		 1/*
2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
3 *
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 *
26 */
0d75590d 27#include "qemu/osdep.h"
da34e65c 28#include "qapi/error.h"
9c17d615 29#include "sysemu/sysemu.h"
e35704ba 30#include "sysemu/numa.h"
83c9f4ca 31#include "hw/hw.h"
03dd024f 32#include "qemu/log.h"
71461b0f 33#include "hw/fw-path-provider.h"
9fdf0c29 34#include "elf.h"
1422e32d 35#include "net/net.h"
ad440b4a 36#include "sysemu/device_tree.h"
fa1d36df 37#include "sysemu/block-backend.h"
9c17d615
PB		 38#include "sysemu/cpus.h"
39#include "sysemu/kvm.h"
c20d332a 40#include "sysemu/device_tree.h"
e97c3636 41#include "kvm_ppc.h"
ff14e817 42#include "migration/migration.h"
4be21d56 43#include "mmu-hash64.h"
3794d548 44#include "qom/cpu.h"
9fdf0c29
DG		 45
46#include "hw/boards.h"
0d09e41a 47#include "hw/ppc/ppc.h"
9fdf0c29
DG		 48#include "hw/loader.h"
49
7804c353 50#include "hw/ppc/fdt.h"
0d09e41a
PB		 51#include "hw/ppc/spapr.h"
52#include "hw/ppc/spapr_vio.h"
53#include "hw/pci-host/spapr.h"
54#include "hw/ppc/xics.h"
a2cb15b0 55#include "hw/pci/msi.h"
9fdf0c29 56
83c9f4ca 57#include "hw/pci/pci.h"
71461b0f
AK		 58#include "hw/scsi/scsi.h"
59#include "hw/virtio/virtio-scsi.h"
f61b4bed 60
022c62cb 61#include "exec/address-spaces.h"
35139a59 62#include "hw/usb.h"
1de7afc9 63#include "qemu/config-file.h"
135a129a 64#include "qemu/error-report.h"
2a6593cb 65#include "trace.h"
34316482 66#include "hw/nmi.h"
890c2b77 67
68a27b20 68#include "hw/compat.h"
f348b6d1 69#include "qemu/cutils.h"
94a94e4c 70#include "hw/ppc/spapr_cpu_core.h"
2474bfd4 71#include "qmp-commands.h"
68a27b20 72
9fdf0c29
DG		 73#include <libfdt.h>
74
4d8d5467
BH		 75/* SLOF memory layout:
76 *
77 * SLOF raw image loaded at 0, copies its romfs right below the flat
78 * device-tree, then position SLOF itself 31M below that
79 *
80 * So we set FW_OVERHEAD to 40MB which should account for all of that
81 * and more
82 *
83 * We load our kernel at 4M, leaving space for SLOF initial image
84 */
38b02bd8 85#define FDT_MAX_SIZE 0x100000
39ac8455 86#define RTAS_MAX_SIZE 0x10000
b7d1f77a 87#define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */
a9f8ad8f
DG		 88#define FW_MAX_SIZE 0x400000
89#define FW_FILE_NAME "slof.bin"
4d8d5467
BH		 90#define FW_OVERHEAD 0x2800000
91#define KERNEL_LOAD_ADDR FW_MAX_SIZE
a9f8ad8f 92
4d8d5467 93#define MIN_RMA_SLOF 128UL
9fdf0c29 94
0c103f8e
DG		 95#define PHANDLE_XICP 0x00001111
96
7f763a5d
DG		 97#define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift))
98
c04d6cfa 99static XICSState *try_create_xics(const char *type, int nr_servers,
34f2af3d 100 int nr_irqs, Error **errp)
c04d6cfa 101{
34f2af3d 102 Error *err = NULL;
c04d6cfa
AL		 103 DeviceState *dev;
104
105 dev = qdev_create(NULL, type);
106 qdev_prop_set_uint32(dev, "nr_servers", nr_servers);
107 qdev_prop_set_uint32(dev, "nr_irqs", nr_irqs);
34f2af3d
MA		 108 object_property_set_bool(OBJECT(dev), true, "realized", &err);
109 if (err) {
110 error_propagate(errp, err);
111 object_unparent(OBJECT(dev));
c04d6cfa
AL		 112 return NULL;
113 }
5a3d7b23 114 return XICS_COMMON(dev);
c04d6cfa
AL		 115}
116
446f16a6 117static XICSState *xics_system_init(MachineState *machine,
1e49182d 118 int nr_servers, int nr_irqs, Error **errp)
c04d6cfa 119{
27f24582 120 XICSState *xics = NULL;
c04d6cfa 121
11ad93f6 122 if (kvm_enabled()) {
34f2af3d
MA		 123 Error *err = NULL;
124
446f16a6 125 if (machine_kernel_irqchip_allowed(machine)) {
27f24582
BH		 126 xics = try_create_xics(TYPE_XICS_SPAPR_KVM, nr_servers, nr_irqs,
127 &err);
11ad93f6 128 }
27f24582 129 if (machine_kernel_irqchip_required(machine) && !xics) {
b83baa60
MA		 130 error_reportf_err(err,
131 "kernel_irqchip requested but unavailable: ");
132 } else {
133 error_free(err);
11ad93f6
DG		 134 }
135 }
136
27f24582
BH		 137 if (!xics) {
138 xics = try_create_xics(TYPE_XICS_SPAPR, nr_servers, nr_irqs, errp);
c04d6cfa
AL		 139 }
140
27f24582 141 return xics;
c04d6cfa
AL		 142}
143
833d4668
AK		 144static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
145 int smt_threads)
146{
147 int i, ret = 0;
148 uint32_t servers_prop[smt_threads];
149 uint32_t gservers_prop[smt_threads * 2];
150 int index = ppc_get_vcpu_dt_id(cpu);
151
6d9412ea 152 if (cpu->cpu_version) {
4bce526e 153 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->cpu_version);
6d9412ea
AK		 154 if (ret < 0) {
155 return ret;
156 }
157 }
158
833d4668
AK		 159 /* Build interrupt servers and gservers properties */
160 for (i = 0; i < smt_threads; i++) {
161 servers_prop[i] = cpu_to_be32(index + i);
162 /* Hack, direct the group queues back to cpu 0 */
163 gservers_prop[i*2] = cpu_to_be32(index + i);
164 gservers_prop[i*2 + 1] = 0;
165 }
166 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
167 servers_prop, sizeof(servers_prop));
168 if (ret < 0) {
169 return ret;
170 }
171 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s",
172 gservers_prop, sizeof(gservers_prop));
173
174 return ret;
175}
176
0da6f3fe
BR		 177static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, CPUState *cs)
178{
179 int ret = 0;
180 PowerPCCPU *cpu = POWERPC_CPU(cs);
181 int index = ppc_get_vcpu_dt_id(cpu);
182 uint32_t associativity[] = {cpu_to_be32(0x5),
183 cpu_to_be32(0x0),
184 cpu_to_be32(0x0),
185 cpu_to_be32(0x0),
186 cpu_to_be32(cs->numa_node),
187 cpu_to_be32(index)};
188
189 /* Advertise NUMA via ibm,associativity */
190 if (nb_numa_nodes > 1) {
191 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity,
192 sizeof(associativity));
193 }
194
195 return ret;
196}
197
28e02042 198static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr)
6e806cc3 199{
82677ed2
AK		 200 int ret = 0, offset, cpus_offset;
201 CPUState *cs;
6e806cc3
BR		 202 char cpu_model[32];
203 int smt = kvmppc_smt_threads();
7f763a5d 204 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
6e806cc3 205
82677ed2
AK		 206 CPU_FOREACH(cs) {
207 PowerPCCPU *cpu = POWERPC_CPU(cs);
208 DeviceClass *dc = DEVICE_GET_CLASS(cs);
209 int index = ppc_get_vcpu_dt_id(cpu);
6e806cc3 210
0f20ba62 211 if ((index % smt) != 0) {
6e806cc3
BR		 212 continue;
213 }
214
82677ed2 215 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index);
6e806cc3 216
82677ed2
AK		 217 cpus_offset = fdt_path_offset(fdt, "/cpus");
218 if (cpus_offset < 0) {
219 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"),
220 "cpus");
221 if (cpus_offset < 0) {
222 return cpus_offset;
223 }
224 }
225 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model);
6e806cc3 226 if (offset < 0) {
82677ed2
AK		 227 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model);
228 if (offset < 0) {
229 return offset;
230 }
6e806cc3
BR		 231 }
232
7f763a5d
DG		 233 ret = fdt_setprop(fdt, offset, "ibm,pft-size",
234 pft_size_prop, sizeof(pft_size_prop));
6e806cc3
BR		 235 if (ret < 0) {
236 return ret;
237 }
833d4668 238
0da6f3fe
BR		 239 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cs);
240 if (ret < 0) {
241 return ret;
242 }
243
82677ed2 244 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu,
2a48d993 245 ppc_get_compat_smt_threads(cpu));
833d4668
AK		 246 if (ret < 0) {
247 return ret;
248 }
6e806cc3
BR		 249 }
250 return ret;
251}
252
5af9873d
BH		 253
254static size_t create_page_sizes_prop(CPUPPCState *env, uint32_t *prop,
255 size_t maxsize)
256{
257 size_t maxcells = maxsize / sizeof(uint32_t);
258 int i, j, count;
259 uint32_t *p = prop;
260
261 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
262 struct ppc_one_seg_page_size *sps = &env->sps.sps[i];
263
264 if (!sps->page_shift) {
265 break;
266 }
267 for (count = 0; count < PPC_PAGE_SIZES_MAX_SZ; count++) {
268 if (sps->enc[count].page_shift == 0) {
269 break;
270 }
271 }
272 if ((p - prop) >= (maxcells - 3 - count * 2)) {
273 break;
274 }
275 *(p++) = cpu_to_be32(sps->page_shift);
276 *(p++) = cpu_to_be32(sps->slb_enc);
277 *(p++) = cpu_to_be32(count);
278 for (j = 0; j < count; j++) {
279 *(p++) = cpu_to_be32(sps->enc[j].page_shift);
280 *(p++) = cpu_to_be32(sps->enc[j].pte_enc);
281 }
282 }
283
284 return (p - prop) * sizeof(uint32_t);
285}
286
b082d65a
AK		 287static hwaddr spapr_node0_size(void)
288{
fb164994
DG		 289 MachineState *machine = MACHINE(qdev_get_machine());
290
b082d65a
AK		 291 if (nb_numa_nodes) {
292 int i;
293 for (i = 0; i < nb_numa_nodes; ++i) {
294 if (numa_info[i].node_mem) {
fb164994
DG		 295 return MIN(pow2floor(numa_info[i].node_mem),
296 machine->ram_size);
b082d65a
AK		 297 }
298 }
299 }
fb164994 300 return machine->ram_size;
b082d65a
AK		 301}
302
a1d59c0f
AK		 303static void add_str(GString *s, const gchar *s1)
304{
305 g_string_append_len(s, s1, strlen(s1) + 1);
306}
7f763a5d 307
3bbf37f2 308static void *spapr_create_fdt_skel(hwaddr initrd_base,
a8170e5e
AK		 309 hwaddr initrd_size,
310 hwaddr kernel_size,
16457e7f 311 bool little_endian,
74d042e5
DG		 312 const char *kernel_cmdline,
313 uint32_t epow_irq)
9fdf0c29
DG		 314{
315 void *fdt;
9fdf0c29
DG		 316 uint32_t start_prop = cpu_to_be32(initrd_base);
317 uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size);
a1d59c0f
AK		 318 GString *hypertas = g_string_sized_new(256);
319 GString *qemu_hypertas = g_string_sized_new(256);
7f763a5d 320 uint32_t refpoints[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)};
9e734e3d 321 uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(max_cpus)};
6e806cc3 322 unsigned char vec5[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80};
ef951443 323 char *buf;
9fdf0c29 324
a1d59c0f
AK		 325 add_str(hypertas, "hcall-pft");
326 add_str(hypertas, "hcall-term");
327 add_str(hypertas, "hcall-dabr");
328 add_str(hypertas, "hcall-interrupt");
329 add_str(hypertas, "hcall-tce");
330 add_str(hypertas, "hcall-vio");
331 add_str(hypertas, "hcall-splpar");
332 add_str(hypertas, "hcall-bulk");
333 add_str(hypertas, "hcall-set-mode");
6cc09e26
TH		 334 add_str(hypertas, "hcall-sprg0");
335 add_str(hypertas, "hcall-copy");
336 add_str(hypertas, "hcall-debug");
a1d59c0f
AK		 337 add_str(qemu_hypertas, "hcall-memop1");
338
7267c094 339 fdt = g_malloc0(FDT_MAX_SIZE);
9fdf0c29
DG		 340 _FDT((fdt_create(fdt, FDT_MAX_SIZE)));
341
4d8d5467
BH		 342 if (kernel_size) {
343 _FDT((fdt_add_reservemap_entry(fdt, KERNEL_LOAD_ADDR, kernel_size)));
344 }
345 if (initrd_size) {
346 _FDT((fdt_add_reservemap_entry(fdt, initrd_base, initrd_size)));
347 }
9fdf0c29
DG		 348 _FDT((fdt_finish_reservemap(fdt)));
349
350 /* Root node */
351 _FDT((fdt_begin_node(fdt, "")));
352 _FDT((fdt_property_string(fdt, "device_type", "chrp")));
5d73dd66 353 _FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)")));
d63919c9 354 _FDT((fdt_property_string(fdt, "compatible", "qemu,pseries")));
9fdf0c29 355
ef951443
ND		 356 /*
357 * Add info to guest to indentify which host is it being run on
358 * and what is the uuid of the guest
359 */
360 if (kvmppc_get_host_model(&buf)) {
361 _FDT((fdt_property_string(fdt, "host-model", buf)));
362 g_free(buf);
363 }
364 if (kvmppc_get_host_serial(&buf)) {
365 _FDT((fdt_property_string(fdt, "host-serial", buf)));
366 g_free(buf);
367 }
368
369 buf = g_strdup_printf(UUID_FMT, qemu_uuid[0], qemu_uuid[1],
370 qemu_uuid[2], qemu_uuid[3], qemu_uuid[4],
371 qemu_uuid[5], qemu_uuid[6], qemu_uuid[7],
372 qemu_uuid[8], qemu_uuid[9], qemu_uuid[10],
373 qemu_uuid[11], qemu_uuid[12], qemu_uuid[13],
374 qemu_uuid[14], qemu_uuid[15]);
375
376 _FDT((fdt_property_string(fdt, "vm,uuid", buf)));
3dc0a66d
AK		 377 if (qemu_uuid_set) {
378 _FDT((fdt_property_string(fdt, "system-id", buf)));
379 }
ef951443
ND		 380 g_free(buf);
381
2c1aaa81
SB		 382 if (qemu_get_vm_name()) {
383 _FDT((fdt_property_string(fdt, "ibm,partition-name",
384 qemu_get_vm_name())));
385 }
386
9fdf0c29
DG		 387 _FDT((fdt_property_cell(fdt, "#address-cells", 0x2)));
388 _FDT((fdt_property_cell(fdt, "#size-cells", 0x2)));
389
390 /* /chosen */
391 _FDT((fdt_begin_node(fdt, "chosen")));
392
6e806cc3
BR		 393 /* Set Form1_affinity */
394 _FDT((fdt_property(fdt, "ibm,architecture-vec-5", vec5, sizeof(vec5))));
395
9fdf0c29
DG		 396 _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline)));
397 _FDT((fdt_property(fdt, "linux,initrd-start",
398 &start_prop, sizeof(start_prop))));
399 _FDT((fdt_property(fdt, "linux,initrd-end",
400 &end_prop, sizeof(end_prop))));
4d8d5467
BH		 401 if (kernel_size) {
402 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR),
403 cpu_to_be64(kernel_size) };
9fdf0c29 404
4d8d5467 405 _FDT((fdt_property(fdt, "qemu,boot-kernel", &kprop, sizeof(kprop))));
16457e7f
BH		 406 if (little_endian) {
407 _FDT((fdt_property(fdt, "qemu,boot-kernel-le", NULL, 0)));
408 }
4d8d5467 409 }
cc84c0f3
AS		 410 if (boot_menu) {
411 _FDT((fdt_property_cell(fdt, "qemu,boot-menu", boot_menu)));
412 }
f28359d8
LZ		 413 _FDT((fdt_property_cell(fdt, "qemu,graphic-width", graphic_width)));
414 _FDT((fdt_property_cell(fdt, "qemu,graphic-height", graphic_height)));
415 _FDT((fdt_property_cell(fdt, "qemu,graphic-depth", graphic_depth)));
3384f95c 416
9fdf0c29
DG		 417 _FDT((fdt_end_node(fdt)));
418
f43e3525
DG		 419 /* RTAS */
420 _FDT((fdt_begin_node(fdt, "rtas")));
421
da95324e
AK		 422 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
423 add_str(hypertas, "hcall-multi-tce");
424 }
a1d59c0f
AK		 425 _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas->str,
426 hypertas->len)));
427 g_string_free(hypertas, TRUE);
428 _FDT((fdt_property(fdt, "qemu,hypertas-functions", qemu_hypertas->str,
429 qemu_hypertas->len)));
430 g_string_free(qemu_hypertas, TRUE);
f43e3525 431
6e806cc3
BR		 432 _FDT((fdt_property(fdt, "ibm,associativity-reference-points",
433 refpoints, sizeof(refpoints))));
434
74d042e5 435 _FDT((fdt_property_cell(fdt, "rtas-error-log-max", RTAS_ERROR_LOG_MAX)));
79853e18
TD		 436 _FDT((fdt_property_cell(fdt, "rtas-event-scan-rate",
437 RTAS_EVENT_SCAN_RATE)));
74d042e5 438
226419d6 439 if (msi_nonbroken) {
a95f9922
SB		 440 _FDT((fdt_property(fdt, "ibm,change-msix-capable", NULL, 0)));
441 }
442
2e14072f 443 /*
9d632f5f 444 * According to PAPR, rtas ibm,os-term does not guarantee a return
2e14072f
ND		 445 * back to the guest cpu.
446 *
447 * While an additional ibm,extended-os-term property indicates that
448 * rtas call return will always occur. Set this property.
449 */
450 _FDT((fdt_property(fdt, "ibm,extended-os-term", NULL, 0)));
451
f43e3525
DG		 452 _FDT((fdt_end_node(fdt)));
453
b5cec4c5 454 /* interrupt controller */
9dfef5aa 455 _FDT((fdt_begin_node(fdt, "interrupt-controller")));
b5cec4c5
DG		 456
457 _FDT((fdt_property_string(fdt, "device_type",
458 "PowerPC-External-Interrupt-Presentation")));
459 _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp")));
b5cec4c5
DG		 460 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));
461 _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges",
462 interrupt_server_ranges_prop,
463 sizeof(interrupt_server_ranges_prop))));
0c103f8e
DG		 464 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 2)));
465 _FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP)));
466 _FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP)));
b5cec4c5
DG		 467
468 _FDT((fdt_end_node(fdt)));
469
4040ab72
DG		 470 /* vdevice */
471 _FDT((fdt_begin_node(fdt, "vdevice")));
472
473 _FDT((fdt_property_string(fdt, "device_type", "vdevice")));
474 _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice")));
475 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1)));
476 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0)));
b5cec4c5
DG		 477 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2)));
478 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));
4040ab72
DG		 479
480 _FDT((fdt_end_node(fdt)));
481
74d042e5
DG		 482 /* event-sources */
483 spapr_events_fdt_skel(fdt, epow_irq);
484
f7d69146
AG		 485 /* /hypervisor node */
486 if (kvm_enabled()) {
487 uint8_t hypercall[16];
488
489 /* indicate KVM hypercall interface */
490 _FDT((fdt_begin_node(fdt, "hypervisor")));
491 _FDT((fdt_property_string(fdt, "compatible", "linux,kvm")));
492 if (kvmppc_has_cap_fixup_hcalls()) {
493 /*
494 * Older KVM versions with older guest kernels were broken with the
495 * magic page, don't allow the guest to map it.
496 */
0ddbd053
AK		 497 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall,
498 sizeof(hypercall))) {
499 _FDT((fdt_property(fdt, "hcall-instructions", hypercall,
500 sizeof(hypercall))));
501 }
f7d69146
AG		 502 }
503 _FDT((fdt_end_node(fdt)));
504 }
505
9fdf0c29
DG		 506 _FDT((fdt_end_node(fdt))); /* close root node */
507 _FDT((fdt_finish(fdt)));
508
a3467baa
DG		 509 return fdt;
510}
511
03d196b7 512static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start,
26a8c353
AK		 513 hwaddr size)
514{
515 uint32_t associativity[] = {
516 cpu_to_be32(0x4), /* length */
517 cpu_to_be32(0x0), cpu_to_be32(0x0),
c3b4f589 518 cpu_to_be32(0x0), cpu_to_be32(nodeid)
26a8c353
AK		 519 };
520 char mem_name[32];
521 uint64_t mem_reg_property[2];
522 int off;
523
524 mem_reg_property[0] = cpu_to_be64(start);
525 mem_reg_property[1] = cpu_to_be64(size);
526
527 sprintf(mem_name, "memory@" TARGET_FMT_lx, start);
528 off = fdt_add_subnode(fdt, 0, mem_name);
529 _FDT(off);
530 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
531 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
532 sizeof(mem_reg_property))));
533 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,
534 sizeof(associativity))));
03d196b7 535 return off;
26a8c353
AK		 536}
537
28e02042 538static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt)
7f763a5d 539{
fb164994 540 MachineState *machine = MACHINE(spapr);
7db8a127
AK		 541 hwaddr mem_start, node_size;
542 int i, nb_nodes = nb_numa_nodes;
543 NodeInfo *nodes = numa_info;
544 NodeInfo ramnode;
545
546 /* No NUMA nodes, assume there is just one node with whole RAM */
547 if (!nb_numa_nodes) {
548 nb_nodes = 1;
fb164994 549 ramnode.node_mem = machine->ram_size;
7db8a127 550 nodes = &ramnode;
5fe269b1 551 }
7f763a5d 552
7db8a127
AK		 553 for (i = 0, mem_start = 0; i < nb_nodes; ++i) {
554 if (!nodes[i].node_mem) {
555 continue;
556 }
fb164994 557 if (mem_start >= machine->ram_size) {
5fe269b1
PM		 558 node_size = 0;
559 } else {
7db8a127 560 node_size = nodes[i].node_mem;
fb164994
DG		 561 if (node_size > machine->ram_size - mem_start) {
562 node_size = machine->ram_size - mem_start;
5fe269b1
PM		 563 }
564 }
7db8a127
AK		 565 if (!mem_start) {
566 /* ppc_spapr_init() checks for rma_size <= node0_size already */
e8f986fc 567 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size);
7db8a127
AK		 568 mem_start += spapr->rma_size;
569 node_size -= spapr->rma_size;
570 }
6010818c
AK		 571 for ( ; node_size; ) {
572 hwaddr sizetmp = pow2floor(node_size);
573
574 /* mem_start != 0 here */
575 if (ctzl(mem_start) < ctzl(sizetmp)) {
576 sizetmp = 1ULL << ctzl(mem_start);
577 }
578
579 spapr_populate_memory_node(fdt, i, mem_start, sizetmp);
580 node_size -= sizetmp;
581 mem_start += sizetmp;
582 }
7f763a5d
DG		 583 }
584
585 return 0;
586}
587
0da6f3fe
BR		 588static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
589 sPAPRMachineState *spapr)
590{
591 PowerPCCPU *cpu = POWERPC_CPU(cs);
592 CPUPPCState *env = &cpu->env;
593 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
594 int index = ppc_get_vcpu_dt_id(cpu);
595 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
596 0xffffffff, 0xffffffff};
afd10a0f
BR		 597 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq()
598 : SPAPR_TIMEBASE_FREQ;
0da6f3fe
BR		 599 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
600 uint32_t page_sizes_prop[64];
601 size_t page_sizes_prop_size;
22419c2a 602 uint32_t vcpus_per_socket = smp_threads * smp_cores;
0da6f3fe 603 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
af81cf32
BR		 604 sPAPRDRConnector *drc;
605 sPAPRDRConnectorClass *drck;
606 int drc_index;
607
608 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index);
609 if (drc) {
610 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
611 drc_index = drck->get_index(drc);
612 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index)));
613 }
0da6f3fe 614
90da0d5a
BH		 615 /* Note: we keep CI large pages off for now because a 64K capable guest
616 * provisioned with large pages might otherwise try to map a qemu
617 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages
618 * even if that qemu runs on a 4k host.
619 *
620 * We can later add this bit back when we are confident this is not
621 * an issue (!HV KVM or 64K host)
622 */
623 uint8_t pa_features_206[] = { 6, 0,
624 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
625 uint8_t pa_features_207[] = { 24, 0,
626 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
627 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
628 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
629 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
630 uint8_t *pa_features;
631 size_t pa_size;
632
0da6f3fe
BR		 633 _FDT((fdt_setprop_cell(fdt, offset, "reg", index)));
634 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
635
636 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
637 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
638 env->dcache_line_size)));
639 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
640 env->dcache_line_size)));
641 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
642 env->icache_line_size)));
643 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
644 env->icache_line_size)));
645
646 if (pcc->l1_dcache_size) {
647 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
648 pcc->l1_dcache_size)));
649 } else {
ce9863b7 650 error_report("Warning: Unknown L1 dcache size for cpu");
0da6f3fe
BR		 651 }
652 if (pcc->l1_icache_size) {
653 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
654 pcc->l1_icache_size)));
655 } else {
ce9863b7 656 error_report("Warning: Unknown L1 icache size for cpu");
0da6f3fe
BR		 657 }
658
659 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
660 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
fd5da5c4 661 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr)));
0da6f3fe
BR		 662 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr)));
663 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
664 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
665
666 if (env->spr_cb[SPR_PURR].oea_read) {
667 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
668 }
669
670 if (env->mmu_model & POWERPC_MMU_1TSEG) {
671 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
672 segs, sizeof(segs))));
673 }
674
675 /* Advertise VMX/VSX (vector extensions) if available
676 * 0 / no property == no vector extensions
677 * 1 == VMX / Altivec available
678 * 2 == VSX available */
679 if (env->insns_flags & PPC_ALTIVEC) {
680 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
681
682 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
683 }
684
685 /* Advertise DFP (Decimal Floating Point) if available
686 * 0 / no property == no DFP
687 * 1 == DFP available */
688 if (env->insns_flags2 & PPC2_DFP) {
689 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
690 }
691
692 page_sizes_prop_size = create_page_sizes_prop(env, page_sizes_prop,
693 sizeof(page_sizes_prop));
694 if (page_sizes_prop_size) {
695 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
696 page_sizes_prop, page_sizes_prop_size)));
697 }
698
90da0d5a
BH		 699 /* Do the ibm,pa-features property, adjust it for ci-large-pages */
700 if (env->mmu_model == POWERPC_MMU_2_06) {
701 pa_features = pa_features_206;
702 pa_size = sizeof(pa_features_206);
703 } else /* env->mmu_model == POWERPC_MMU_2_07 */ {
704 pa_features = pa_features_207;
705 pa_size = sizeof(pa_features_207);
706 }
707 if (env->ci_large_pages) {
708 pa_features[3] |= 0x20;
709 }
710 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size)));
711
0da6f3fe 712 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id",
22419c2a 713 cs->cpu_index / vcpus_per_socket)));
0da6f3fe
BR		 714
715 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size",
716 pft_size_prop, sizeof(pft_size_prop))));
717
718 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cs));
719
720 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu,
721 ppc_get_compat_smt_threads(cpu)));
722}
723
724static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr)
725{
726 CPUState *cs;
727 int cpus_offset;
728 char *nodename;
729 int smt = kvmppc_smt_threads();
730
731 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
732 _FDT(cpus_offset);
733 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
734 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
735
736 /*
737 * We walk the CPUs in reverse order to ensure that CPU DT nodes
738 * created by fdt_add_subnode() end up in the right order in FDT
739 * for the guest kernel the enumerate the CPUs correctly.
740 */
741 CPU_FOREACH_REVERSE(cs) {
742 PowerPCCPU *cpu = POWERPC_CPU(cs);
743 int index = ppc_get_vcpu_dt_id(cpu);
744 DeviceClass *dc = DEVICE_GET_CLASS(cs);
745 int offset;
746
747 if ((index % smt) != 0) {
748 continue;
749 }
750
751 nodename = g_strdup_printf("%s@%x", dc->fw_name, index);
752 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
753 g_free(nodename);
754 _FDT(offset);
755 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
756 }
757
758}
759
03d196b7
BR		 760/*
761 * Adds ibm,dynamic-reconfiguration-memory node.
762 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation
763 * of this device tree node.
764 */
765static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt)
766{
767 MachineState *machine = MACHINE(spapr);
768 int ret, i, offset;
769 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
770 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)};
d0e5a8f2
BR		 771 uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size;
772 uint32_t nr_lmbs = (spapr->hotplug_memory.base +
773 memory_region_size(&spapr->hotplug_memory.mr)) /
774 lmb_size;
03d196b7 775 uint32_t *int_buf, *cur_index, buf_len;
6663864e 776 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1;
03d196b7 777
16c25aef 778 /*
d0e5a8f2 779 * Don't create the node if there is no hotpluggable memory
16c25aef 780 */
d0e5a8f2 781 if (machine->ram_size == machine->maxram_size) {
16c25aef
BR		 782 return 0;
783 }
784
ef001f06
TH		 785 /*
786 * Allocate enough buffer size to fit in ibm,dynamic-memory
787 * or ibm,associativity-lookup-arrays
788 */
789 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2)
790 * sizeof(uint32_t);
03d196b7
BR		 791 cur_index = int_buf = g_malloc0(buf_len);
792
793 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory");
794
795 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size,
796 sizeof(prop_lmb_size));
797 if (ret < 0) {
798 goto out;
799 }
800
801 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff);
802 if (ret < 0) {
803 goto out;
804 }
805
806 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0);
807 if (ret < 0) {
808 goto out;
809 }
810
811 /* ibm,dynamic-memory */
812 int_buf[0] = cpu_to_be32(nr_lmbs);
813 cur_index++;
814 for (i = 0; i < nr_lmbs; i++) {
d0e5a8f2 815 uint64_t addr = i * lmb_size;
03d196b7
BR		 816 uint32_t *dynamic_memory = cur_index;
817
d0e5a8f2
BR		 818 if (i >= hotplug_lmb_start) {
819 sPAPRDRConnector *drc;
820 sPAPRDRConnectorClass *drck;
821
822 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, i);
823 g_assert(drc);
824 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
825
826 dynamic_memory[0] = cpu_to_be32(addr >> 32);
827 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
828 dynamic_memory[2] = cpu_to_be32(drck->get_index(drc));
829 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
830 dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL));
831 if (memory_region_present(get_system_memory(), addr)) {
832 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED);
833 } else {
834 dynamic_memory[5] = cpu_to_be32(0);
835 }
03d196b7 836 } else {
d0e5a8f2
BR		 837 /*
838 * LMB information for RMA, boot time RAM and gap b/n RAM and
839 * hotplug memory region -- all these are marked as reserved
840 * and as having no valid DRC.
841 */
842 dynamic_memory[0] = cpu_to_be32(addr >> 32);
843 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
844 dynamic_memory[2] = cpu_to_be32(0);
845 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
846 dynamic_memory[4] = cpu_to_be32(-1);
847 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED |
848 SPAPR_LMB_FLAGS_DRC_INVALID);
03d196b7
BR		 849 }
850
851 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE;
852 }
853 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len);
854 if (ret < 0) {
855 goto out;
856 }
857
858 /* ibm,associativity-lookup-arrays */
859 cur_index = int_buf;
6663864e 860 int_buf[0] = cpu_to_be32(nr_nodes);
03d196b7
BR		 861 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */
862 cur_index += 2;
6663864e 863 for (i = 0; i < nr_nodes; i++) {
03d196b7
BR		 864 uint32_t associativity[] = {
865 cpu_to_be32(0x0),
866 cpu_to_be32(0x0),
867 cpu_to_be32(0x0),
868 cpu_to_be32(i)
869 };
870 memcpy(cur_index, associativity, sizeof(associativity));
871 cur_index += 4;
872 }
873 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf,
874 (cur_index - int_buf) * sizeof(uint32_t));
875out:
876 g_free(int_buf);
877 return ret;
878}
879
880int spapr_h_cas_compose_response(sPAPRMachineState *spapr,
881 target_ulong addr, target_ulong size,
882 bool cpu_update, bool memory_update)
883{
884 void *fdt, *fdt_skel;
885 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 };
886 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine());
887
888 size -= sizeof(hdr);
889
890 /* Create sceleton */
891 fdt_skel = g_malloc0(size);
892 _FDT((fdt_create(fdt_skel, size)));
893 _FDT((fdt_begin_node(fdt_skel, "")));
894 _FDT((fdt_end_node(fdt_skel)));
895 _FDT((fdt_finish(fdt_skel)));
896 fdt = g_malloc0(size);
897 _FDT((fdt_open_into(fdt_skel, fdt, size)));
898 g_free(fdt_skel);
899
900 /* Fixup cpu nodes */
901 if (cpu_update) {
902 _FDT((spapr_fixup_cpu_dt(fdt, spapr)));
903 }
904
16c25aef 905 /* Generate ibm,dynamic-reconfiguration-memory node if required */
03d196b7
BR		 906 if (memory_update && smc->dr_lmb_enabled) {
907 _FDT((spapr_populate_drconf_memory(spapr, fdt)));
03d196b7
BR		 908 }
909
910 /* Pack resulting tree */
911 _FDT((fdt_pack(fdt)));
912
913 if (fdt_totalsize(fdt) + sizeof(hdr) > size) {
914 trace_spapr_cas_failed(size);
915 return -1;
916 }
917
918 cpu_physical_memory_write(addr, &hdr, sizeof(hdr));
919 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt));
920 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr));
921 g_free(fdt);
922
923 return 0;
924}
925
28e02042 926static void spapr_finalize_fdt(sPAPRMachineState *spapr,
a8170e5e
AK		 927 hwaddr fdt_addr,
928 hwaddr rtas_addr,
929 hwaddr rtas_size)
a3467baa 930{
5b2128d2 931 MachineState *machine = MACHINE(qdev_get_machine());
3c0c47e3 932 MachineClass *mc = MACHINE_GET_CLASS(machine);
c20d332a 933 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
5b2128d2 934 const char *boot_device = machine->boot_order;
71461b0f
AK		 935 int ret, i;
936 size_t cb = 0;
937 char *bootlist;
a3467baa 938 void *fdt;
3384f95c 939 sPAPRPHBState *phb;
a3467baa 940
7267c094 941 fdt = g_malloc(FDT_MAX_SIZE);
a3467baa
DG		 942
943 /* open out the base tree into a temp buffer for the final tweaks */
944 _FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE)));
4040ab72 945
e8f986fc
BR		 946 ret = spapr_populate_memory(spapr, fdt);
947 if (ret < 0) {
ce9863b7 948 error_report("couldn't setup memory nodes in fdt");
e8f986fc 949 exit(1);
7f763a5d
DG		 950 }
951
4040ab72
DG		 952 ret = spapr_populate_vdevice(spapr->vio_bus, fdt);
953 if (ret < 0) {
ce9863b7 954 error_report("couldn't setup vio devices in fdt");
4040ab72
DG		 955 exit(1);
956 }
957
4d9392be
TH		 958 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) {
959 ret = spapr_rng_populate_dt(fdt);
960 if (ret < 0) {
ce9863b7 961 error_report("could not set up rng device in the fdt");
4d9392be
TH		 962 exit(1);
963 }
964 }
965
3384f95c 966 QLIST_FOREACH(phb, &spapr->phbs, list) {
e0fdbd7c 967 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt);
da34fed7
TH		 968 if (ret < 0) {
969 error_report("couldn't setup PCI devices in fdt");
970 exit(1);
971 }
3384f95c
DG		 972 }
973
39ac8455
DG		 974 /* RTAS */
975 ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size);
976 if (ret < 0) {
ce9863b7 977 error_report("Couldn't set up RTAS device tree properties");
39ac8455
DG		 978 }
979
0da6f3fe
BR		 980 /* cpus */
981 spapr_populate_cpus_dt_node(fdt, spapr);
6e806cc3 982
71461b0f
AK		 983 bootlist = get_boot_devices_list(&cb, true);
984 if (cb && bootlist) {
985 int offset = fdt_path_offset(fdt, "/chosen");
986 if (offset < 0) {
987 exit(1);
988 }
989 for (i = 0; i < cb; i++) {
990 if (bootlist[i] == '\n') {
991 bootlist[i] = ' ';
992 }
993
994 }
995 ret = fdt_setprop_string(fdt, offset, "qemu,boot-list", bootlist);
996 }
997
5b2128d2
AG		 998 if (boot_device && strlen(boot_device)) {
999 int offset = fdt_path_offset(fdt, "/chosen");
1000
1001 if (offset < 0) {
1002 exit(1);
1003 }
1004 fdt_setprop_string(fdt, offset, "qemu,boot-device", boot_device);
1005 }
1006
3fc5acde 1007 if (!spapr->has_graphics) {
f28359d8
LZ		 1008 spapr_populate_chosen_stdout(fdt, spapr->vio_bus);
1009 }
68f3a94c 1010
c20d332a
BR		 1011 if (smc->dr_lmb_enabled) {
1012 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB));
1013 }
1014
3c0c47e3 1015 if (mc->query_hotpluggable_cpus) {
af81cf32
BR		 1016 int offset = fdt_path_offset(fdt, "/cpus");
1017 ret = spapr_drc_populate_dt(fdt, offset, NULL,
1018 SPAPR_DR_CONNECTOR_TYPE_CPU);
1019 if (ret < 0) {
1020 error_report("Couldn't set up CPU DR device tree properties");
1021 exit(1);
1022 }
1023 }
1024
4040ab72
DG		 1025 _FDT((fdt_pack(fdt)));
1026
4d8d5467 1027 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) {
730fce59
TH		 1028 error_report("FDT too big ! 0x%x bytes (max is 0x%x)",
1029 fdt_totalsize(fdt), FDT_MAX_SIZE);
4d8d5467
BH		 1030 exit(1);
1031 }
1032
ad440b4a 1033 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
a3467baa 1034 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt));
9fdf0c29 1035
a21a7a70 1036 g_free(bootlist);
7267c094 1037 g_free(fdt);
9fdf0c29
DG		 1038}
1039
1040static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
1041{
1042 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
1043}
1044
1b14670a 1045static void emulate_spapr_hypercall(PowerPCCPU *cpu)
9fdf0c29 1046{
1b14670a
AF		 1047 CPUPPCState *env = &cpu->env;
1048
efcb9383
DG		 1049 if (msr_pr) {
1050 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1051 env->gpr[3] = H_PRIVILEGE;
1052 } else {
aa100fa4 1053 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]);
efcb9383 1054 }
9fdf0c29
DG		 1055}
1056
e6b8fd24
SMJ		 1057#define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1058#define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1059#define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1060#define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1061#define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1062
715c5407
DG		 1063/*
1064 * Get the fd to access the kernel htab, re-opening it if necessary
1065 */
1066static int get_htab_fd(sPAPRMachineState *spapr)
1067{
1068 if (spapr->htab_fd >= 0) {
1069 return spapr->htab_fd;
1070 }
1071
1072 spapr->htab_fd = kvmppc_get_htab_fd(false);
1073 if (spapr->htab_fd < 0) {
1074 error_report("Unable to open fd for reading hash table from KVM: %s",
1075 strerror(errno));
1076 }
1077
1078 return spapr->htab_fd;
1079}
1080
1081static void close_htab_fd(sPAPRMachineState *spapr)
1082{
1083 if (spapr->htab_fd >= 0) {
1084 close(spapr->htab_fd);
1085 }
1086 spapr->htab_fd = -1;
1087}
1088
8dfe8e7f
DG		 1089static int spapr_hpt_shift_for_ramsize(uint64_t ramsize)
1090{
1091 int shift;
1092
1093 /* We aim for a hash table of size 1/128 the size of RAM (rounded
1094 * up). The PAPR recommendation is actually 1/64 of RAM size, but
1095 * that's much more than is needed for Linux guests */
1096 shift = ctz64(pow2ceil(ramsize)) - 7;
1097 shift = MAX(shift, 18); /* Minimum architected size */
1098 shift = MIN(shift, 46); /* Maximum architected size */
1099 return shift;
1100}
1101
c5f54f3e
DG		 1102static void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift,
1103 Error **errp)
7f763a5d 1104{
c5f54f3e
DG		 1105 long rc;
1106
1107 /* Clean up any HPT info from a previous boot */
1108 g_free(spapr->htab);
1109 spapr->htab = NULL;
1110 spapr->htab_shift = 0;
1111 close_htab_fd(spapr);
1112
1113 rc = kvmppc_reset_htab(shift);
1114 if (rc < 0) {
1115 /* kernel-side HPT needed, but couldn't allocate one */
1116 error_setg_errno(errp, errno,
1117 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)",
1118 shift);
1119 /* This is almost certainly fatal, but if the caller really
1120 * wants to carry on with shift == 0, it's welcome to try */
1121 } else if (rc > 0) {
1122 /* kernel-side HPT allocated */
1123 if (rc != shift) {
1124 error_setg(errp,
1125 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)",
1126 shift, rc);
7735feda
BR		 1127 }
1128
7f763a5d 1129 spapr->htab_shift = shift;
c18ad9a5 1130 spapr->htab = NULL;
b817772a 1131 } else {
c5f54f3e
DG		 1132 /* kernel-side HPT not needed, allocate in userspace instead */
1133 size_t size = 1ULL << shift;
1134 int i;
b817772a 1135
c5f54f3e
DG		 1136 spapr->htab = qemu_memalign(size, size);
1137 if (!spapr->htab) {
1138 error_setg_errno(errp, errno,
1139 "Could not allocate HPT of order %d", shift);
1140 return;
7735feda
BR		 1141 }
1142
c5f54f3e
DG		 1143 memset(spapr->htab, 0, size);
1144 spapr->htab_shift = shift;
e6b8fd24 1145
c5f54f3e
DG		 1146 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) {
1147 DIRTY_HPTE(HPTE(spapr->htab, i));
e6b8fd24 1148 }
7f763a5d 1149 }
9fdf0c29
DG		 1150}
1151
9e3f9733
AG		 1152static int find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque)
1153{
1154 bool matched = false;
1155
1156 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
1157 matched = true;
1158 }
1159
1160 if (!matched) {
1161 error_report("Device %s is not supported by this machine yet.",
1162 qdev_fw_name(DEVICE(sbdev)));
1163 exit(1);
1164 }
1165
1166 return 0;
1167}
1168
c8787ad4 1169static void ppc_spapr_reset(void)
a3467baa 1170{
c5f54f3e
DG		 1171 MachineState *machine = MACHINE(qdev_get_machine());
1172 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
182735ef 1173 PowerPCCPU *first_ppc_cpu;
b7d1f77a 1174 uint32_t rtas_limit;
259186a7 1175
9e3f9733
AG		 1176 /* Check for unknown sysbus devices */
1177 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL);
1178
c5f54f3e
DG		 1179 /* Allocate and/or reset the hash page table */
1180 spapr_reallocate_hpt(spapr,
1181 spapr_hpt_shift_for_ramsize(machine->maxram_size),
1182 &error_fatal);
1183
1184 /* Update the RMA size if necessary */
1185 if (spapr->vrma_adjust) {
1186 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(),
1187 spapr->htab_shift);
1188 }
a3467baa 1189
c8787ad4 1190 qemu_devices_reset();
a3467baa 1191
b7d1f77a
BH		 1192 /*
1193 * We place the device tree and RTAS just below either the top of the RMA,
1194 * or just below 2GB, whichever is lowere, so that it can be
1195 * processed with 32-bit real mode code if necessary
1196 */
1197 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR);
1198 spapr->rtas_addr = rtas_limit - RTAS_MAX_SIZE;
1199 spapr->fdt_addr = spapr->rtas_addr - FDT_MAX_SIZE;
1200
a3467baa
DG		 1201 /* Load the fdt */
1202 spapr_finalize_fdt(spapr, spapr->fdt_addr, spapr->rtas_addr,
1203 spapr->rtas_size);
1204
b7d1f77a
BH		 1205 /* Copy RTAS over */
1206 cpu_physical_memory_write(spapr->rtas_addr, spapr->rtas_blob,
1207 spapr->rtas_size);
1208
a3467baa 1209 /* Set up the entry state */
182735ef
AF		 1210 first_ppc_cpu = POWERPC_CPU(first_cpu);
1211 first_ppc_cpu->env.gpr[3] = spapr->fdt_addr;
1212 first_ppc_cpu->env.gpr[5] = 0;
1213 first_cpu->halted = 0;
1b718907 1214 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT;
a3467baa
DG		 1215
1216}
1217
28e02042 1218static void spapr_create_nvram(sPAPRMachineState *spapr)
639e8102 1219{
2ff3de68 1220 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram");
3978b863 1221 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
639e8102 1222
3978b863 1223 if (dinfo) {
6231a6da
MA		 1224 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
1225 &error_fatal);
639e8102
DG		 1226 }
1227
1228 qdev_init_nofail(dev);
1229
1230 spapr->nvram = (struct sPAPRNVRAM *)dev;
1231}
1232
28e02042 1233static void spapr_rtc_create(sPAPRMachineState *spapr)
28df36a1
DG		 1234{
1235 DeviceState *dev = qdev_create(NULL, TYPE_SPAPR_RTC);
1236
1237 qdev_init_nofail(dev);
1238 spapr->rtc = dev;
74e5ae28
DG		 1239
1240 object_property_add_alias(qdev_get_machine(), "rtc-time",
1241 OBJECT(spapr->rtc), "date", NULL);
28df36a1
DG		 1242}
1243
8c57b867 1244/* Returns whether we want to use VGA or not */
14c6a894 1245static bool spapr_vga_init(PCIBus *pci_bus, Error **errp)
f28359d8 1246{
8c57b867 1247 switch (vga_interface_type) {
8c57b867 1248 case VGA_NONE:
7effdaa3
MW		 1249 return false;
1250 case VGA_DEVICE:
1251 return true;
1ddcae82 1252 case VGA_STD:
b798c190 1253 case VGA_VIRTIO:
1ddcae82 1254 return pci_vga_init(pci_bus) != NULL;
8c57b867 1255 default:
14c6a894
DG		 1256 error_setg(errp,
1257 "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1258 return false;
f28359d8 1259 }
f28359d8
LZ		 1260}
1261
880ae7de
DG		 1262static int spapr_post_load(void *opaque, int version_id)
1263{
28e02042 1264 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque;
880ae7de
DG		 1265 int err = 0;
1266
631b22ea 1267 /* In earlier versions, there was no separate qdev for the PAPR
880ae7de
DG		 1268 * RTC, so the RTC offset was stored directly in sPAPREnvironment.
1269 * So when migrating from those versions, poke the incoming offset
1270 * value into the RTC device */
1271 if (version_id < 3) {
1272 err = spapr_rtc_import_offset(spapr->rtc, spapr->rtc_offset);
1273 }
1274
1275 return err;
1276}
1277
1278static bool version_before_3(void *opaque, int version_id)
1279{
1280 return version_id < 3;
1281}
1282
4be21d56
DG		 1283static const VMStateDescription vmstate_spapr = {
1284 .name = "spapr",
880ae7de 1285 .version_id = 3,
4be21d56 1286 .minimum_version_id = 1,
880ae7de 1287 .post_load = spapr_post_load,
3aff6c2f 1288 .fields = (VMStateField[]) {
880ae7de
DG		 1289 /* used to be @next_irq */
1290 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4),
4be21d56
DG		 1291
1292 /* RTC offset */
28e02042 1293 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3),
880ae7de 1294
28e02042 1295 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2),
4be21d56
DG		 1296 VMSTATE_END_OF_LIST()
1297 },
1298};
1299
4be21d56
DG		 1300static int htab_save_setup(QEMUFile *f, void *opaque)
1301{
28e02042 1302 sPAPRMachineState *spapr = opaque;
4be21d56 1303
4be21d56
DG		 1304 /* "Iteration" header */
1305 qemu_put_be32(f, spapr->htab_shift);
1306
e68cb8b4
AK		 1307 if (spapr->htab) {
1308 spapr->htab_save_index = 0;
1309 spapr->htab_first_pass = true;
1310 } else {
1311 assert(kvm_enabled());
e68cb8b4
AK		 1312 }
1313
1314
4be21d56
DG		 1315 return 0;
1316}
1317
28e02042 1318static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr,
4be21d56
DG		 1319 int64_t max_ns)
1320{
378bc217 1321 bool has_timeout = max_ns != -1;
4be21d56
DG		 1322 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1323 int index = spapr->htab_save_index;
bc72ad67 1324 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
4be21d56
DG		 1325
1326 assert(spapr->htab_first_pass);
1327
1328 do {
1329 int chunkstart;
1330
1331 /* Consume invalid HPTEs */
1332 while ((index < htabslots)
1333 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1334 index++;
1335 CLEAN_HPTE(HPTE(spapr->htab, index));
1336 }
1337
1338 /* Consume valid HPTEs */
1339 chunkstart = index;
338c25b6 1340 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
4be21d56
DG		 1341 && HPTE_VALID(HPTE(spapr->htab, index))) {
1342 index++;
1343 CLEAN_HPTE(HPTE(spapr->htab, index));
1344 }
1345
1346 if (index > chunkstart) {
1347 int n_valid = index - chunkstart;
1348
1349 qemu_put_be32(f, chunkstart);
1350 qemu_put_be16(f, n_valid);
1351 qemu_put_be16(f, 0);
1352 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1353 HASH_PTE_SIZE_64 * n_valid);
1354
378bc217
DG		 1355 if (has_timeout &&
1356 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
4be21d56
DG		 1357 break;
1358 }
1359 }
1360 } while ((index < htabslots) && !qemu_file_rate_limit(f));
1361
1362 if (index >= htabslots) {
1363 assert(index == htabslots);
1364 index = 0;
1365 spapr->htab_first_pass = false;
1366 }
1367 spapr->htab_save_index = index;
1368}
1369
28e02042 1370static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr,
e68cb8b4 1371 int64_t max_ns)
4be21d56
DG		 1372{
1373 bool final = max_ns < 0;
1374 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1375 int examined = 0, sent = 0;
1376 int index = spapr->htab_save_index;
bc72ad67 1377 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
4be21d56
DG		 1378
1379 assert(!spapr->htab_first_pass);
1380
1381 do {
1382 int chunkstart, invalidstart;
1383
1384 /* Consume non-dirty HPTEs */
1385 while ((index < htabslots)
1386 && !HPTE_DIRTY(HPTE(spapr->htab, index))) {
1387 index++;
1388 examined++;
1389 }
1390
1391 chunkstart = index;
1392 /* Consume valid dirty HPTEs */
338c25b6 1393 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
4be21d56
DG		 1394 && HPTE_DIRTY(HPTE(spapr->htab, index))
1395 && HPTE_VALID(HPTE(spapr->htab, index))) {
1396 CLEAN_HPTE(HPTE(spapr->htab, index));
1397 index++;
1398 examined++;
1399 }
1400
1401 invalidstart = index;
1402 /* Consume invalid dirty HPTEs */
338c25b6 1403 while ((index < htabslots) && (index - invalidstart < USHRT_MAX)
4be21d56
DG		 1404 && HPTE_DIRTY(HPTE(spapr->htab, index))
1405 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1406 CLEAN_HPTE(HPTE(spapr->htab, index));
1407 index++;
1408 examined++;
1409 }
1410
1411 if (index > chunkstart) {
1412 int n_valid = invalidstart - chunkstart;
1413 int n_invalid = index - invalidstart;
1414
1415 qemu_put_be32(f, chunkstart);
1416 qemu_put_be16(f, n_valid);
1417 qemu_put_be16(f, n_invalid);
1418 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1419 HASH_PTE_SIZE_64 * n_valid);
1420 sent += index - chunkstart;
1421
bc72ad67 1422 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
4be21d56
DG		 1423 break;
1424 }
1425 }
1426
1427 if (examined >= htabslots) {
1428 break;
1429 }
1430
1431 if (index >= htabslots) {
1432 assert(index == htabslots);
1433 index = 0;
1434 }
1435 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final));
1436
1437 if (index >= htabslots) {
1438 assert(index == htabslots);
1439 index = 0;
1440 }
1441
1442 spapr->htab_save_index = index;
1443
e68cb8b4 1444 return (examined >= htabslots) && (sent == 0) ? 1 : 0;
4be21d56
DG		 1445}
1446
e68cb8b4
AK		 1447#define MAX_ITERATION_NS 5000000 /* 5 ms */
1448#define MAX_KVM_BUF_SIZE 2048
1449
4be21d56
DG		 1450static int htab_save_iterate(QEMUFile *f, void *opaque)
1451{
28e02042 1452 sPAPRMachineState *spapr = opaque;
715c5407 1453 int fd;
e68cb8b4 1454 int rc = 0;
4be21d56
DG		 1455
1456 /* Iteration header */
1457 qemu_put_be32(f, 0);
1458
e68cb8b4
AK		 1459 if (!spapr->htab) {
1460 assert(kvm_enabled());
1461
715c5407
DG		 1462 fd = get_htab_fd(spapr);
1463 if (fd < 0) {
1464 return fd;
01a57972
SMJ		 1465 }
1466
715c5407 1467 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS);
e68cb8b4
AK		 1468 if (rc < 0) {
1469 return rc;
1470 }
1471 } else if (spapr->htab_first_pass) {
4be21d56
DG		 1472 htab_save_first_pass(f, spapr, MAX_ITERATION_NS);
1473 } else {
e68cb8b4 1474 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS);
4be21d56
DG		 1475 }
1476
1477 /* End marker */
1478 qemu_put_be32(f, 0);
1479 qemu_put_be16(f, 0);
1480 qemu_put_be16(f, 0);
1481
e68cb8b4 1482 return rc;
4be21d56
DG		 1483}
1484
1485static int htab_save_complete(QEMUFile *f, void *opaque)
1486{
28e02042 1487 sPAPRMachineState *spapr = opaque;
715c5407 1488 int fd;
4be21d56
DG		 1489
1490 /* Iteration header */
1491 qemu_put_be32(f, 0);
1492
e68cb8b4
AK		 1493 if (!spapr->htab) {
1494 int rc;
1495
1496 assert(kvm_enabled());
1497
715c5407
DG		 1498 fd = get_htab_fd(spapr);
1499 if (fd < 0) {
1500 return fd;
01a57972
SMJ		 1501 }
1502
715c5407 1503 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1);
e68cb8b4
AK		 1504 if (rc < 0) {
1505 return rc;
1506 }
e68cb8b4 1507 } else {
378bc217
DG		 1508 if (spapr->htab_first_pass) {
1509 htab_save_first_pass(f, spapr, -1);
1510 }
e68cb8b4
AK		 1511 htab_save_later_pass(f, spapr, -1);
1512 }
4be21d56
DG		 1513
1514 /* End marker */
1515 qemu_put_be32(f, 0);
1516 qemu_put_be16(f, 0);
1517 qemu_put_be16(f, 0);
1518
1519 return 0;
1520}
1521
1522static int htab_load(QEMUFile *f, void *opaque, int version_id)
1523{
28e02042 1524 sPAPRMachineState *spapr = opaque;
4be21d56 1525 uint32_t section_hdr;
e68cb8b4 1526 int fd = -1;
4be21d56
DG		 1527
1528 if (version_id < 1 || version_id > 1) {
98a5d100 1529 error_report("htab_load() bad version");
4be21d56
DG		 1530 return -EINVAL;
1531 }
1532
1533 section_hdr = qemu_get_be32(f);
1534
1535 if (section_hdr) {
9897e462 1536 Error *local_err = NULL;
c5f54f3e
DG		 1537
1538 /* First section gives the htab size */
1539 spapr_reallocate_hpt(spapr, section_hdr, &local_err);
1540 if (local_err) {
1541 error_report_err(local_err);
4be21d56
DG		 1542 return -EINVAL;
1543 }
1544 return 0;
1545 }
1546
e68cb8b4
AK		 1547 if (!spapr->htab) {
1548 assert(kvm_enabled());
1549
1550 fd = kvmppc_get_htab_fd(true);
1551 if (fd < 0) {
98a5d100
DG		 1552 error_report("Unable to open fd to restore KVM hash table: %s",
1553 strerror(errno));
e68cb8b4
AK		 1554 }
1555 }
1556
4be21d56
DG		 1557 while (true) {
1558 uint32_t index;
1559 uint16_t n_valid, n_invalid;
1560
1561 index = qemu_get_be32(f);
1562 n_valid = qemu_get_be16(f);
1563 n_invalid = qemu_get_be16(f);
1564
1565 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) {
1566 /* End of Stream */
1567 break;
1568 }
1569
e68cb8b4 1570 if ((index + n_valid + n_invalid) >
4be21d56
DG		 1571 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) {
1572 /* Bad index in stream */
98a5d100
DG		 1573 error_report(
1574 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
1575 index, n_valid, n_invalid, spapr->htab_shift);
4be21d56
DG		 1576 return -EINVAL;
1577 }
1578
e68cb8b4
AK		 1579 if (spapr->htab) {
1580 if (n_valid) {
1581 qemu_get_buffer(f, HPTE(spapr->htab, index),
1582 HASH_PTE_SIZE_64 * n_valid);
1583 }
1584 if (n_invalid) {
1585 memset(HPTE(spapr->htab, index + n_valid), 0,
1586 HASH_PTE_SIZE_64 * n_invalid);
1587 }
1588 } else {
1589 int rc;
1590
1591 assert(fd >= 0);
1592
1593 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid);
1594 if (rc < 0) {
1595 return rc;
1596 }
4be21d56
DG		 1597 }
1598 }
1599
e68cb8b4
AK		 1600 if (!spapr->htab) {
1601 assert(fd >= 0);
1602 close(fd);
1603 }
1604
4be21d56
DG		 1605 return 0;
1606}
1607
c573fc03
TH		 1608static void htab_cleanup(void *opaque)
1609{
1610 sPAPRMachineState *spapr = opaque;
1611
1612 close_htab_fd(spapr);
1613}
1614
4be21d56
DG		 1615static SaveVMHandlers savevm_htab_handlers = {
1616 .save_live_setup = htab_save_setup,
1617 .save_live_iterate = htab_save_iterate,
a3e06c3d 1618 .save_live_complete_precopy = htab_save_complete,
c573fc03 1619 .cleanup = htab_cleanup,
4be21d56
DG		 1620 .load_state = htab_load,
1621};
1622
5b2128d2
AG		 1623static void spapr_boot_set(void *opaque, const char *boot_device,
1624 Error **errp)
1625{
1626 MachineState *machine = MACHINE(qdev_get_machine());
1627 machine->boot_order = g_strdup(boot_device);
1628}
1629
224245bf
DG		 1630/*
1631 * Reset routine for LMB DR devices.
1632 *
1633 * Unlike PCI DR devices, LMB DR devices explicitly register this reset
1634 * routine. Reset for PCI DR devices will be handled by PHB reset routine
1635 * when it walks all its children devices. LMB devices reset occurs
1636 * as part of spapr_ppc_reset().
1637 */
1638static void spapr_drc_reset(void *opaque)
1639{
1640 sPAPRDRConnector *drc = opaque;
1641 DeviceState *d = DEVICE(drc);
1642
1643 if (d) {
1644 device_reset(d);
1645 }
1646}
1647
1648static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr)
1649{
1650 MachineState *machine = MACHINE(spapr);
1651 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
e8f986fc 1652 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size;
224245bf
DG		 1653 int i;
1654
1655 for (i = 0; i < nr_lmbs; i++) {
1656 sPAPRDRConnector *drc;
1657 uint64_t addr;
1658
e8f986fc 1659 addr = i * lmb_size + spapr->hotplug_memory.base;
224245bf
DG		 1660 drc = spapr_dr_connector_new(OBJECT(spapr), SPAPR_DR_CONNECTOR_TYPE_LMB,
1661 addr/lmb_size);
1662 qemu_register_reset(spapr_drc_reset, drc);
1663 }
1664}
1665
1666/*
1667 * If RAM size, maxmem size and individual node mem sizes aren't aligned
1668 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest
1669 * since we can't support such unaligned sizes with DRCONF_MEMORY.
1670 */
7c150d6f 1671static void spapr_validate_node_memory(MachineState *machine, Error **errp)
224245bf
DG		 1672{
1673 int i;
1674
7c150d6f
DG		 1675 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) {
1676 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT
1677 " is not aligned to %llu MiB",
1678 machine->ram_size,
1679 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1680 return;
1681 }
1682
1683 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) {
1684 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT
1685 " is not aligned to %llu MiB",
1686 machine->ram_size,
1687 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1688 return;
224245bf
DG		 1689 }
1690
1691 for (i = 0; i < nb_numa_nodes; i++) {
1692 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) {
7c150d6f
DG		 1693 error_setg(errp,
1694 "Node %d memory size 0x%" PRIx64
1695 " is not aligned to %llu MiB",
1696 i, numa_info[i].node_mem,
1697 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1698 return;
224245bf
DG		 1699 }
1700 }
1701}
1702
9fdf0c29 1703/* pSeries LPAR / sPAPR hardware init */
3ef96221 1704static void ppc_spapr_init(MachineState *machine)
9fdf0c29 1705{
28e02042 1706 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
3c0c47e3 1707 MachineClass *mc = MACHINE_GET_CLASS(machine);
224245bf 1708 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
3ef96221
MA		 1709 const char *kernel_filename = machine->kernel_filename;
1710 const char *kernel_cmdline = machine->kernel_cmdline;
1711 const char *initrd_filename = machine->initrd_filename;
8c9f64df 1712 PCIHostState *phb;
9fdf0c29 1713 int i;
890c2b77
AK		 1714 MemoryRegion *sysmem = get_system_memory();
1715 MemoryRegion *ram = g_new(MemoryRegion, 1);
658fa66b
AK		 1716 MemoryRegion *rma_region;
1717 void *rma = NULL;
a8170e5e 1718 hwaddr rma_alloc_size;
b082d65a 1719 hwaddr node0_size = spapr_node0_size();
4d8d5467
BH		 1720 uint32_t initrd_base = 0;
1721 long kernel_size = 0, initrd_size = 0;
b7d1f77a 1722 long load_limit, fw_size;
16457e7f 1723 bool kernel_le = false;
39ac8455 1724 char *filename;
94a94e4c
BR		 1725 int smt = kvmppc_smt_threads();
1726 int spapr_cores = smp_cpus / smp_threads;
1727 int spapr_max_cores = max_cpus / smp_threads;
1728
3c0c47e3 1729 if (mc->query_hotpluggable_cpus) {
94a94e4c
BR		 1730 if (smp_cpus % smp_threads) {
1731 error_report("smp_cpus (%u) must be multiple of threads (%u)",
1732 smp_cpus, smp_threads);
1733 exit(1);
1734 }
1735 if (max_cpus % smp_threads) {
1736 error_report("max_cpus (%u) must be multiple of threads (%u)",
1737 max_cpus, smp_threads);
1738 exit(1);
1739 }
1740 }
9fdf0c29 1741
226419d6 1742 msi_nonbroken = true;
0ee2c058 1743
d43b45e2
DG		 1744 QLIST_INIT(&spapr->phbs);
1745
9fdf0c29
DG		 1746 cpu_ppc_hypercall = emulate_spapr_hypercall;
1747
354ac20a 1748 /* Allocate RMA if necessary */
658fa66b 1749 rma_alloc_size = kvmppc_alloc_rma(&rma);
354ac20a
DG		 1750
1751 if (rma_alloc_size == -1) {
730fce59 1752 error_report("Unable to create RMA");
354ac20a
DG		 1753 exit(1);
1754 }
7f763a5d 1755
c4177479 1756 if (rma_alloc_size && (rma_alloc_size < node0_size)) {
7f763a5d 1757 spapr->rma_size = rma_alloc_size;
354ac20a 1758 } else {
c4177479 1759 spapr->rma_size = node0_size;
7f763a5d
DG		 1760
1761 /* With KVM, we don't actually know whether KVM supports an
1762 * unbounded RMA (PR KVM) or is limited by the hash table size
1763 * (HV KVM using VRMA), so we always assume the latter
1764 *
1765 * In that case, we also limit the initial allocations for RTAS
1766 * etc... to 256M since we have no way to know what the VRMA size
1767 * is going to be as it depends on the size of the hash table
1768 * isn't determined yet.
1769 */
1770 if (kvm_enabled()) {
1771 spapr->vrma_adjust = 1;
1772 spapr->rma_size = MIN(spapr->rma_size, 0x10000000);
1773 }
912acdf4
BH		 1774
1775 /* Actually we don't support unbounded RMA anymore since we
1776 * added proper emulation of HV mode. The max we can get is
1777 * 16G which also happens to be what we configure for PAPR
1778 * mode so make sure we don't do anything bigger than that
1779 */
1780 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull);
354ac20a
DG		 1781 }
1782
c4177479 1783 if (spapr->rma_size > node0_size) {
d54e4d76
DG		 1784 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")",
1785 spapr->rma_size);
c4177479
AK		 1786 exit(1);
1787 }
1788
b7d1f77a
BH		 1789 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */
1790 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD;
9fdf0c29 1791
7b565160 1792 /* Set up Interrupt Controller before we create the VCPUs */
27f24582
BH		 1793 spapr->xics = xics_system_init(machine,
1794 DIV_ROUND_UP(max_cpus * smt, smp_threads),
1795 XICS_IRQS_SPAPR, &error_fatal);
7b565160 1796
224245bf 1797 if (smc->dr_lmb_enabled) {
7c150d6f 1798 spapr_validate_node_memory(machine, &error_fatal);
224245bf
DG		 1799 }
1800
9fdf0c29 1801 /* init CPUs */
19fb2c36
BR		 1802 if (machine->cpu_model == NULL) {
1803 machine->cpu_model = kvm_enabled() ? "host" : "POWER7";
9fdf0c29 1804 }
94a94e4c 1805
e703d2f7
GK		 1806 ppc_cpu_parse_features(machine->cpu_model);
1807
3c0c47e3 1808 if (mc->query_hotpluggable_cpus) {
94a94e4c
BR		 1809 char *type = spapr_get_cpu_core_type(machine->cpu_model);
1810
4babfaf0 1811 if (type == NULL) {
caebf378
CLG		 1812 error_report("Unable to find sPAPR CPU Core definition");
1813 exit(1);
1814 }
1815
94a94e4c 1816 spapr->cores = g_new0(Object *, spapr_max_cores);
af81cf32 1817 for (i = 0; i < spapr_max_cores; i++) {
12bf2d33 1818 int core_id = i * smp_threads;
af81cf32
BR		 1819 sPAPRDRConnector *drc =
1820 spapr_dr_connector_new(OBJECT(spapr),
12bf2d33
GK		 1821 SPAPR_DR_CONNECTOR_TYPE_CPU,
1822 (core_id / smp_threads) * smt);
af81cf32
BR		 1823
1824 qemu_register_reset(spapr_drc_reset, drc);
1825
1826 if (i < spapr_cores) {
caebf378 1827 Object *core = object_new(type);
af81cf32
BR		 1828 object_property_set_int(core, smp_threads, "nr-threads",
1829 &error_fatal);
12bf2d33 1830 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID,
af81cf32
BR		 1831 &error_fatal);
1832 object_property_set_bool(core, true, "realized", &error_fatal);
94a94e4c 1833 }
9fdf0c29 1834 }
94a94e4c
BR		 1835 g_free(type);
1836 } else {
1837 for (i = 0; i < smp_cpus; i++) {
1838 PowerPCCPU *cpu = cpu_ppc_init(machine->cpu_model);
1839 if (cpu == NULL) {
1840 error_report("Unable to find PowerPC CPU definition");
1841 exit(1);
1842 }
1843 spapr_cpu_init(spapr, cpu, &error_fatal);
1844 }
9fdf0c29
DG		 1845 }
1846
026bfd89
DG		 1847 if (kvm_enabled()) {
1848 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */
1849 kvmppc_enable_logical_ci_hcalls();
ef9971dd 1850 kvmppc_enable_set_mode_hcall();
026bfd89
DG		 1851 }
1852
9fdf0c29 1853 /* allocate RAM */
f92f5da1 1854 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram",
fb164994 1855 machine->ram_size);
f92f5da1 1856 memory_region_add_subregion(sysmem, 0, ram);
9fdf0c29 1857
658fa66b
AK		 1858 if (rma_alloc_size && rma) {
1859 rma_region = g_new(MemoryRegion, 1);
1860 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma",
1861 rma_alloc_size, rma);
1862 vmstate_register_ram_global(rma_region);
1863 memory_region_add_subregion(sysmem, 0, rma_region);
1864 }
1865
4a1c9cf0
BR		 1866 /* initialize hotplug memory address space */
1867 if (machine->ram_size < machine->maxram_size) {
1868 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size;
71c9a3dd
BR		 1869 /*
1870 * Limit the number of hotpluggable memory slots to half the number
1871 * slots that KVM supports, leaving the other half for PCI and other
1872 * devices. However ensure that number of slots doesn't drop below 32.
1873 */
1874 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 :
1875 SPAPR_MAX_RAM_SLOTS;
4a1c9cf0 1876
71c9a3dd
BR		 1877 if (max_memslots < SPAPR_MAX_RAM_SLOTS) {
1878 max_memslots = SPAPR_MAX_RAM_SLOTS;
1879 }
1880 if (machine->ram_slots > max_memslots) {
d54e4d76
DG		 1881 error_report("Specified number of memory slots %"
1882 PRIu64" exceeds max supported %d",
71c9a3dd 1883 machine->ram_slots, max_memslots);
d54e4d76 1884 exit(1);
4a1c9cf0
BR		 1885 }
1886
1887 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size,
1888 SPAPR_HOTPLUG_MEM_ALIGN);
1889 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr),
1890 "hotplug-memory", hotplug_mem_size);
1891 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base,
1892 &spapr->hotplug_memory.mr);
1893 }
1894
224245bf
DG		 1895 if (smc->dr_lmb_enabled) {
1896 spapr_create_lmb_dr_connectors(spapr);
1897 }
1898
39ac8455 1899 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
4c56440d 1900 if (!filename) {
730fce59 1901 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin");
4c56440d
SW		 1902 exit(1);
1903 }
b7d1f77a 1904 spapr->rtas_size = get_image_size(filename);
8afc22a2
ZJ		 1905 if (spapr->rtas_size < 0) {
1906 error_report("Could not get size of LPAR rtas '%s'", filename);
1907 exit(1);
1908 }
b7d1f77a
BH		 1909 spapr->rtas_blob = g_malloc(spapr->rtas_size);
1910 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) {
730fce59 1911 error_report("Could not load LPAR rtas '%s'", filename);
39ac8455
DG		 1912 exit(1);
1913 }
4d8d5467 1914 if (spapr->rtas_size > RTAS_MAX_SIZE) {
730fce59
TH		 1915 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)",
1916 (size_t)spapr->rtas_size, RTAS_MAX_SIZE);
4d8d5467
BH		 1917 exit(1);
1918 }
7267c094 1919 g_free(filename);
39ac8455 1920
74d042e5
DG		 1921 /* Set up EPOW events infrastructure */
1922 spapr_events_init(spapr);
1923
12f42174 1924 /* Set up the RTC RTAS interfaces */
28df36a1 1925 spapr_rtc_create(spapr);
12f42174 1926
b5cec4c5 1927 /* Set up VIO bus */
4040ab72
DG		 1928 spapr->vio_bus = spapr_vio_bus_init();
1929
277f9acf 1930 for (i = 0; i < MAX_SERIAL_PORTS; i++) {
4040ab72 1931 if (serial_hds[i]) {
d601fac4 1932 spapr_vty_create(spapr->vio_bus, serial_hds[i]);
4040ab72
DG		 1933 }
1934 }
9fdf0c29 1935
639e8102
DG		 1936 /* We always have at least the nvram device on VIO */
1937 spapr_create_nvram(spapr);
1938
3384f95c 1939 /* Set up PCI */
fa28f71b
AK		 1940 spapr_pci_rtas_init();
1941
89dfd6e1 1942 phb = spapr_create_phb(spapr, 0);
3384f95c 1943
277f9acf 1944 for (i = 0; i < nb_nics; i++) {
8d90ad90
DG		 1945 NICInfo *nd = &nd_table[i];
1946
1947 if (!nd->model) {
7267c094 1948 nd->model = g_strdup("ibmveth");
8d90ad90
DG		 1949 }
1950
1951 if (strcmp(nd->model, "ibmveth") == 0) {
d601fac4 1952 spapr_vlan_create(spapr->vio_bus, nd);
8d90ad90 1953 } else {
29b358f9 1954 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL);
8d90ad90
DG		 1955 }
1956 }
1957
6e270446 1958 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) {
d601fac4 1959 spapr_vscsi_create(spapr->vio_bus);
6e270446
BH		 1960 }
1961
f28359d8 1962 /* Graphics */
14c6a894 1963 if (spapr_vga_init(phb->bus, &error_fatal)) {
3fc5acde 1964 spapr->has_graphics = true;
c6e76503 1965 machine->usb |= defaults_enabled() && !machine->usb_disabled;
f28359d8
LZ		 1966 }
1967
4ee9ced9 1968 if (machine->usb) {
57040d45
TH		 1969 if (smc->use_ohci_by_default) {
1970 pci_create_simple(phb->bus, -1, "pci-ohci");
1971 } else {
1972 pci_create_simple(phb->bus, -1, "nec-usb-xhci");
1973 }
c86580b8 1974
35139a59 1975 if (spapr->has_graphics) {
c86580b8
MA		 1976 USBBus *usb_bus = usb_bus_find(-1);
1977
1978 usb_create_simple(usb_bus, "usb-kbd");
1979 usb_create_simple(usb_bus, "usb-mouse");
35139a59
DG		 1980 }
1981 }
1982
7f763a5d 1983 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) {
d54e4d76
DG		 1984 error_report(
1985 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)",
1986 MIN_RMA_SLOF);
4d8d5467
BH		 1987 exit(1);
1988 }
1989
9fdf0c29
DG		 1990 if (kernel_filename) {
1991 uint64_t lowaddr = 0;
1992
9fdf0c29 1993 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
7ef295ea
PC		 1994 NULL, &lowaddr, NULL, 1, PPC_ELF_MACHINE,
1995 0, 0);
3b66da82 1996 if (kernel_size == ELF_LOAD_WRONG_ENDIAN) {
16457e7f
BH		 1997 kernel_size = load_elf(kernel_filename,
1998 translate_kernel_address, NULL,
7ef295ea
PC		 1999 NULL, &lowaddr, NULL, 0, PPC_ELF_MACHINE,
2000 0, 0);
16457e7f
BH		 2001 kernel_le = kernel_size > 0;
2002 }
9fdf0c29 2003 if (kernel_size < 0) {
d54e4d76
DG		 2004 error_report("error loading %s: %s",
2005 kernel_filename, load_elf_strerror(kernel_size));
9fdf0c29
DG		 2006 exit(1);
2007 }
2008
2009 /* load initrd */
2010 if (initrd_filename) {
4d8d5467
BH		 2011 /* Try to locate the initrd in the gap between the kernel
2012 * and the firmware. Add a bit of space just in case
2013 */
2014 initrd_base = (KERNEL_LOAD_ADDR + kernel_size + 0x1ffff) & ~0xffff;
9fdf0c29 2015 initrd_size = load_image_targphys(initrd_filename, initrd_base,
4d8d5467 2016 load_limit - initrd_base);
9fdf0c29 2017 if (initrd_size < 0) {
d54e4d76
DG		 2018 error_report("could not load initial ram disk '%s'",
2019 initrd_filename);
9fdf0c29
DG		 2020 exit(1);
2021 }
2022 } else {
2023 initrd_base = 0;
2024 initrd_size = 0;
2025 }
4d8d5467 2026 }
a3467baa 2027
8e7ea787
AF		 2028 if (bios_name == NULL) {
2029 bios_name = FW_FILE_NAME;
2030 }
2031 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
4c56440d 2032 if (!filename) {
68fea5a0 2033 error_report("Could not find LPAR firmware '%s'", bios_name);
4c56440d
SW		 2034 exit(1);
2035 }
4d8d5467 2036 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
68fea5a0
TH		 2037 if (fw_size <= 0) {
2038 error_report("Could not load LPAR firmware '%s'", filename);
4d8d5467
BH		 2039 exit(1);
2040 }
2041 g_free(filename);
4d8d5467 2042
28e02042
DG		 2043 /* FIXME: Should register things through the MachineState's qdev
2044 * interface, this is a legacy from the sPAPREnvironment structure
2045 * which predated MachineState but had a similar function */
4be21d56
DG		 2046 vmstate_register(NULL, 0, &vmstate_spapr, spapr);
2047 register_savevm_live(NULL, "spapr/htab", -1, 1,
2048 &savevm_htab_handlers, spapr);
2049
9fdf0c29 2050 /* Prepare the device tree */
3bbf37f2 2051 spapr->fdt_skel = spapr_create_fdt_skel(initrd_base, initrd_size,
16457e7f 2052 kernel_size, kernel_le,
31fe14d1
NF		 2053 kernel_cmdline,
2054 spapr->check_exception_irq);
a3467baa 2055 assert(spapr->fdt_skel != NULL);
5b2128d2 2056
46503c2b
MR		 2057 /* used by RTAS */
2058 QTAILQ_INIT(&spapr->ccs_list);
2059 qemu_register_reset(spapr_ccs_reset_hook, spapr);
2060
5b2128d2 2061 qemu_register_boot_set(spapr_boot_set, spapr);
9fdf0c29
DG		 2062}
2063
135a129a
AK		 2064static int spapr_kvm_type(const char *vm_type)
2065{
2066 if (!vm_type) {
2067 return 0;
2068 }
2069
2070 if (!strcmp(vm_type, "HV")) {
2071 return 1;
2072 }
2073
2074 if (!strcmp(vm_type, "PR")) {
2075 return 2;
2076 }
2077
2078 error_report("Unknown kvm-type specified '%s'", vm_type);
2079 exit(1);
2080}
2081
71461b0f 2082/*
627b84f4 2083 * Implementation of an interface to adjust firmware path
71461b0f
AK		 2084 * for the bootindex property handling.
2085 */
2086static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus,
2087 DeviceState *dev)
2088{
2089#define CAST(type, obj, name) \
2090 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
2091 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE);
2092 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE);
2093
2094 if (d) {
2095 void *spapr = CAST(void, bus->parent, "spapr-vscsi");
2096 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI);
2097 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE);
2098
2099 if (spapr) {
2100 /*
2101 * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
2102 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun
2103 * in the top 16 bits of the 64-bit LUN
2104 */
2105 unsigned id = 0x8000 | (d->id << 8) | d->lun;
2106 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2107 (uint64_t)id << 48);
2108 } else if (virtio) {
2109 /*
2110 * We use SRP luns of the form 01000000 | (target << 8) | lun
2111 * in the top 32 bits of the 64-bit LUN
2112 * Note: the quote above is from SLOF and it is wrong,
2113 * the actual binding is:
2114 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
2115 */
2116 unsigned id = 0x1000000 | (d->id << 16) | d->lun;
2117 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2118 (uint64_t)id << 32);
2119 } else if (usb) {
2120 /*
2121 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
2122 * in the top 32 bits of the 64-bit LUN
2123 */
2124 unsigned usb_port = atoi(usb->port->path);
2125 unsigned id = 0x1000000 | (usb_port << 16) | d->lun;
2126 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2127 (uint64_t)id << 32);
2128 }
2129 }
2130
2131 if (phb) {
2132 /* Replace "pci" with "pci@800000020000000" */
2133 return g_strdup_printf("pci@%"PRIX64, phb->buid);
2134 }
2135
2136 return NULL;
2137}
2138
23825581
EH		 2139static char *spapr_get_kvm_type(Object *obj, Error **errp)
2140{
28e02042 2141 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
23825581 2142
28e02042 2143 return g_strdup(spapr->kvm_type);
23825581
EH		 2144}
2145
2146static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp)
2147{
28e02042 2148 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
23825581 2149
28e02042
DG		 2150 g_free(spapr->kvm_type);
2151 spapr->kvm_type = g_strdup(value);
23825581
EH		 2152}
2153
2154static void spapr_machine_initfn(Object *obj)
2155{
715c5407
DG		 2156 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2157
2158 spapr->htab_fd = -1;
23825581
EH		 2159 object_property_add_str(obj, "kvm-type",
2160 spapr_get_kvm_type, spapr_set_kvm_type, NULL);
49d2e648
MA		 2161 object_property_set_description(obj, "kvm-type",
2162 "Specifies the KVM virtualization mode (HV, PR)",
2163 NULL);
23825581
EH		 2164}
2165
87bbdd9c
DG		 2166static void spapr_machine_finalizefn(Object *obj)
2167{
2168 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2169
2170 g_free(spapr->kvm_type);
2171}
2172
34316482
AK		 2173static void ppc_cpu_do_nmi_on_cpu(void *arg)
2174{
2175 CPUState *cs = arg;
2176
2177 cpu_synchronize_state(cs);
2178 ppc_cpu_do_system_reset(cs);
2179}
2180
2181static void spapr_nmi(NMIState *n, int cpu_index, Error **errp)
2182{
2183 CPUState *cs;
2184
2185 CPU_FOREACH(cs) {
2186 async_run_on_cpu(cs, ppc_cpu_do_nmi_on_cpu, cs);
2187 }
2188}
2189
c20d332a
BR		 2190static void spapr_add_lmbs(DeviceState *dev, uint64_t addr, uint64_t size,
2191 uint32_t node, Error **errp)
2192{
2193 sPAPRDRConnector *drc;
2194 sPAPRDRConnectorClass *drck;
2195 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE;
2196 int i, fdt_offset, fdt_size;
2197 void *fdt;
2198
c20d332a
BR		 2199 for (i = 0; i < nr_lmbs; i++) {
2200 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB,
2201 addr/SPAPR_MEMORY_BLOCK_SIZE);
2202 g_assert(drc);
2203
2204 fdt = create_device_tree(&fdt_size);
2205 fdt_offset = spapr_populate_memory_node(fdt, node, addr,
2206 SPAPR_MEMORY_BLOCK_SIZE);
2207
2208 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2209 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, errp);
c20d332a
BR		 2210 addr += SPAPR_MEMORY_BLOCK_SIZE;
2211 }
5dd5238c
JD		 2212 /* send hotplug notification to the
2213 * guest only in case of hotplugged memory
2214 */
2215 if (dev->hotplugged) {
2216 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, nr_lmbs);
2217 }
c20d332a
BR		 2218}
2219
2220static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2221 uint32_t node, Error **errp)
2222{
2223 Error *local_err = NULL;
2224 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev);
2225 PCDIMMDevice *dimm = PC_DIMM(dev);
2226 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
2227 MemoryRegion *mr = ddc->get_memory_region(dimm);
2228 uint64_t align = memory_region_get_alignment(mr);
2229 uint64_t size = memory_region_size(mr);
2230 uint64_t addr;
2231
2232 if (size % SPAPR_MEMORY_BLOCK_SIZE) {
2233 error_setg(&local_err, "Hotplugged memory size must be a multiple of "
2234 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE/M_BYTE);
2235 goto out;
2236 }
2237
d6a9b0b8 2238 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err);
c20d332a
BR		 2239 if (local_err) {
2240 goto out;
2241 }
2242
2243 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err);
2244 if (local_err) {
2245 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr);
2246 goto out;
2247 }
2248
2249 spapr_add_lmbs(dev, addr, size, node, &error_abort);
2250
2251out:
2252 error_propagate(errp, local_err);
2253}
2254
af81cf32
BR		 2255void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset,
2256 sPAPRMachineState *spapr)
2257{
2258 PowerPCCPU *cpu = POWERPC_CPU(cs);
2259 DeviceClass *dc = DEVICE_GET_CLASS(cs);
2260 int id = ppc_get_vcpu_dt_id(cpu);
2261 void *fdt;
2262 int offset, fdt_size;
2263 char *nodename;
2264
2265 fdt = create_device_tree(&fdt_size);
2266 nodename = g_strdup_printf("%s@%x", dc->fw_name, id);
2267 offset = fdt_add_subnode(fdt, 0, nodename);
2268
2269 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
2270 g_free(nodename);
2271
2272 *fdt_offset = offset;
2273 return fdt;
2274}
2275
c20d332a
BR		 2276static void spapr_machine_device_plug(HotplugHandler *hotplug_dev,
2277 DeviceState *dev, Error **errp)
2278{
2279 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine());
2280
2281 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
b556854b 2282 int node;
c20d332a
BR		 2283
2284 if (!smc->dr_lmb_enabled) {
2285 error_setg(errp, "Memory hotplug not supported for this machine");
2286 return;
2287 }
2288 node = object_property_get_int(OBJECT(dev), PC_DIMM_NODE_PROP, errp);
2289 if (*errp) {
2290 return;
2291 }
1a5512bb
GA		 2292 if (node < 0 || node >= MAX_NODES) {
2293 error_setg(errp, "Invaild node %d", node);
2294 return;
2295 }
c20d332a 2296
b556854b
BR		 2297 /*
2298 * Currently PowerPC kernel doesn't allow hot-adding memory to
2299 * memory-less node, but instead will silently add the memory
2300 * to the first node that has some memory. This causes two
2301 * unexpected behaviours for the user.
2302 *
2303 * - Memory gets hotplugged to a different node than what the user
2304 * specified.
2305 * - Since pc-dimm subsystem in QEMU still thinks that memory belongs
2306 * to memory-less node, a reboot will set things accordingly
2307 * and the previously hotplugged memory now ends in the right node.
2308 * This appears as if some memory moved from one node to another.
2309 *
2310 * So until kernel starts supporting memory hotplug to memory-less
2311 * nodes, just prevent such attempts upfront in QEMU.
2312 */
2313 if (nb_numa_nodes && !numa_info[node].node_mem) {
2314 error_setg(errp, "Can't hotplug memory to memory-less node %d",
2315 node);
2316 return;
2317 }
2318
c20d332a 2319 spapr_memory_plug(hotplug_dev, dev, node, errp);
af81cf32
BR		 2320 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
2321 spapr_core_plug(hotplug_dev, dev, errp);
c20d332a
BR		 2322 }
2323}
2324
2325static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev,
2326 DeviceState *dev, Error **errp)
2327{
3c0c47e3 2328 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
6f4b5c3e 2329
c20d332a
BR		 2330 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2331 error_setg(errp, "Memory hot unplug not supported by sPAPR");
6f4b5c3e 2332 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
3c0c47e3 2333 if (!mc->query_hotpluggable_cpus) {
6f4b5c3e
BR		 2334 error_setg(errp, "CPU hot unplug not supported on this machine");
2335 return;
2336 }
2337 spapr_core_unplug(hotplug_dev, dev, errp);
c20d332a
BR		 2338 }
2339}
2340
94a94e4c
BR		 2341static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev,
2342 DeviceState *dev, Error **errp)
2343{
2344 if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
2345 spapr_core_pre_plug(hotplug_dev, dev, errp);
2346 }
2347}
2348
c20d332a
BR		 2349static HotplugHandler *spapr_get_hotpug_handler(MachineState *machine,
2350 DeviceState *dev)
2351{
94a94e4c
BR		 2352 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
2353 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
c20d332a
BR		 2354 return HOTPLUG_HANDLER(machine);
2355 }
2356 return NULL;
2357}
2358
20bb648d
DG		 2359static unsigned spapr_cpu_index_to_socket_id(unsigned cpu_index)
2360{
2361 /* Allocate to NUMA nodes on a "socket" basis (not that concept of
2362 * socket means much for the paravirtualized PAPR platform) */
2363 return cpu_index / smp_threads / smp_cores;
2364}
2365
2474bfd4
IM		 2366static HotpluggableCPUList *spapr_query_hotpluggable_cpus(MachineState *machine)
2367{
2368 int i;
2369 HotpluggableCPUList *head = NULL;
2370 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
2371 int spapr_max_cores = max_cpus / smp_threads;
2474bfd4
IM		 2372
2373 for (i = 0; i < spapr_max_cores; i++) {
2374 HotpluggableCPUList *list_item = g_new0(typeof(*list_item), 1);
2375 HotpluggableCPU *cpu_item = g_new0(typeof(*cpu_item), 1);
2376 CpuInstanceProperties *cpu_props = g_new0(typeof(*cpu_props), 1);
2377
2378 cpu_item->type = spapr_get_cpu_core_type(machine->cpu_model);
2379 cpu_item->vcpus_count = smp_threads;
27393c33 2380 cpu_props->has_core_id = true;
12bf2d33 2381 cpu_props->core_id = i * smp_threads;
2474bfd4
IM		 2382 /* TODO: add 'has_node/node' here to describe
2383 to which node core belongs */
2384
2385 cpu_item->props = cpu_props;
2386 if (spapr->cores[i]) {
2387 cpu_item->has_qom_path = true;
2388 cpu_item->qom_path = object_get_canonical_path(spapr->cores[i]);
2389 }
2390 list_item->value = cpu_item;
2391 list_item->next = head;
2392 head = list_item;
2393 }
2394 return head;
2395}
2396
29ee3247
AK		 2397static void spapr_machine_class_init(ObjectClass *oc, void *data)
2398{
2399 MachineClass *mc = MACHINE_CLASS(oc);
224245bf 2400 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc);
71461b0f 2401 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
34316482 2402 NMIClass *nc = NMI_CLASS(oc);
c20d332a 2403 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
958db90c 2404
0eb9054c 2405 mc->desc = "pSeries Logical Partition (PAPR compliant)";
fc9f38c3
DG		 2406
2407 /*
2408 * We set up the default / latest behaviour here. The class_init
2409 * functions for the specific versioned machine types can override
2410 * these details for backwards compatibility
2411 */
958db90c
MA		 2412 mc->init = ppc_spapr_init;
2413 mc->reset = ppc_spapr_reset;
2414 mc->block_default_type = IF_SCSI;
38b02bd8 2415 mc->max_cpus = MAX_CPUMASK_BITS;
958db90c 2416 mc->no_parallel = 1;
5b2128d2 2417 mc->default_boot_order = "";
a34944fe 2418 mc->default_ram_size = 512 * M_BYTE;
958db90c 2419 mc->kvm_type = spapr_kvm_type;
9e3f9733 2420 mc->has_dynamic_sysbus = true;
e4024630 2421 mc->pci_allow_0_address = true;
c20d332a 2422 mc->get_hotplug_handler = spapr_get_hotpug_handler;
94a94e4c 2423 hc->pre_plug = spapr_machine_device_pre_plug;
c20d332a
BR		 2424 hc->plug = spapr_machine_device_plug;
2425 hc->unplug = spapr_machine_device_unplug;
20bb648d 2426 mc->cpu_index_to_socket_id = spapr_cpu_index_to_socket_id;
00b4fbe2 2427
fc9f38c3 2428 smc->dr_lmb_enabled = true;
3c0c47e3 2429 mc->query_hotpluggable_cpus = spapr_query_hotpluggable_cpus;
71461b0f 2430 fwc->get_dev_path = spapr_get_fw_dev_path;
34316482 2431 nc->nmi_monitor_handler = spapr_nmi;
29ee3247
AK		 2432}
2433
2434static const TypeInfo spapr_machine_info = {
2435 .name = TYPE_SPAPR_MACHINE,
2436 .parent = TYPE_MACHINE,
4aee7362 2437 .abstract = true,
6ca1502e 2438 .instance_size = sizeof(sPAPRMachineState),
23825581 2439 .instance_init = spapr_machine_initfn,
87bbdd9c 2440 .instance_finalize = spapr_machine_finalizefn,
183930c0 2441 .class_size = sizeof(sPAPRMachineClass),
29ee3247 2442 .class_init = spapr_machine_class_init,
71461b0f
AK		 2443 .interfaces = (InterfaceInfo[]) {
2444 { TYPE_FW_PATH_PROVIDER },
34316482 2445 { TYPE_NMI },
c20d332a 2446 { TYPE_HOTPLUG_HANDLER },
71461b0f
AK		 2447 { }
2448 },
29ee3247
AK		 2449};
2450
fccbc785 2451#define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \
5013c547
DG		 2452 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \
2453 void *data) \
2454 { \
2455 MachineClass *mc = MACHINE_CLASS(oc); \
2456 spapr_machine_##suffix##_class_options(mc); \
fccbc785
DG		 2457 if (latest) { \
2458 mc->alias = "pseries"; \
2459 mc->is_default = 1; \
2460 } \
5013c547
DG		 2461 } \
2462 static void spapr_machine_##suffix##_instance_init(Object *obj) \
2463 { \
2464 MachineState *machine = MACHINE(obj); \
2465 spapr_machine_##suffix##_instance_options(machine); \
2466 } \
2467 static const TypeInfo spapr_machine_##suffix##_info = { \
2468 .name = MACHINE_TYPE_NAME("pseries-" verstr), \
2469 .parent = TYPE_SPAPR_MACHINE, \
2470 .class_init = spapr_machine_##suffix##_class_init, \
2471 .instance_init = spapr_machine_##suffix##_instance_init, \
2472 }; \
2473 static void spapr_machine_register_##suffix(void) \
2474 { \
2475 type_register(&spapr_machine_##suffix##_info); \
2476 } \
0e6aac87 2477 type_init(spapr_machine_register_##suffix)
5013c547 2478
1ea1eefc
BR		 2479/*
2480 * pseries-2.7
2481 */
2482static void spapr_machine_2_7_instance_options(MachineState *machine)
2483{
2484}
2485
2486static void spapr_machine_2_7_class_options(MachineClass *mc)
2487{
2488 /* Defaults for the latest behaviour inherited from the base class */
2489}
2490
2491DEFINE_SPAPR_MACHINE(2_7, "2.7", true);
2492
4b23699c
DG		 2493/*
2494 * pseries-2.6
2495 */
1ea1eefc 2496#define SPAPR_COMPAT_2_6 \
ae4de14c
AK		 2497 HW_COMPAT_2_6 \
2498 { \
2499 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
2500 .property = "ddw",\
2501 .value = stringify(off),\
2502 },
1ea1eefc 2503
4b23699c
DG		 2504static void spapr_machine_2_6_instance_options(MachineState *machine)
2505{
2506}
2507
2508static void spapr_machine_2_6_class_options(MachineClass *mc)
2509{
1ea1eefc 2510 spapr_machine_2_7_class_options(mc);
3c0c47e3 2511 mc->query_hotpluggable_cpus = NULL;
1ea1eefc 2512 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6);
4b23699c
DG		 2513}
2514
1ea1eefc 2515DEFINE_SPAPR_MACHINE(2_6, "2.6", false);
4b23699c 2516
1c5f29bb
DG		 2517/*
2518 * pseries-2.5
2519 */
4b23699c 2520#define SPAPR_COMPAT_2_5 \
57c522f4
TH		 2521 HW_COMPAT_2_5 \
2522 { \
2523 .driver = "spapr-vlan", \
2524 .property = "use-rx-buffer-pools", \
2525 .value = "off", \
2526 },
4b23699c 2527
5013c547 2528static void spapr_machine_2_5_instance_options(MachineState *machine)
1c5f29bb 2529{
5013c547
DG		 2530}
2531
2532static void spapr_machine_2_5_class_options(MachineClass *mc)
2533{
57040d45
TH		 2534 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
2535
4b23699c 2536 spapr_machine_2_6_class_options(mc);
57040d45 2537 smc->use_ohci_by_default = true;
4b23699c 2538 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5);
1c5f29bb
DG		 2539}
2540
4b23699c 2541DEFINE_SPAPR_MACHINE(2_5, "2.5", false);
1c5f29bb
DG		 2542
2543/*
2544 * pseries-2.4
2545 */
80fd50f9
CH		 2546#define SPAPR_COMPAT_2_4 \
2547 HW_COMPAT_2_4
2548
5013c547 2549static void spapr_machine_2_4_instance_options(MachineState *machine)
1c5f29bb 2550{
5013c547
DG		 2551 spapr_machine_2_5_instance_options(machine);
2552}
1c5f29bb 2553
5013c547
DG		 2554static void spapr_machine_2_4_class_options(MachineClass *mc)
2555{
fc9f38c3
DG		 2556 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
2557
2558 spapr_machine_2_5_class_options(mc);
fc9f38c3 2559 smc->dr_lmb_enabled = false;
f949b4e5 2560 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4);
1c5f29bb
DG		 2561}
2562
fccbc785 2563DEFINE_SPAPR_MACHINE(2_4, "2.4", false);
1c5f29bb
DG		 2564
2565/*
2566 * pseries-2.3
2567 */
38ff32c6 2568#define SPAPR_COMPAT_2_3 \
7619c7b0
MR		 2569 HW_COMPAT_2_3 \
2570 {\
2571 .driver = "spapr-pci-host-bridge",\
2572 .property = "dynamic-reconfiguration",\
2573 .value = "off",\
2574 },
38ff32c6 2575
5013c547 2576static void spapr_machine_2_3_instance_options(MachineState *machine)
d25228e7 2577{
5013c547 2578 spapr_machine_2_4_instance_options(machine);
ff14e817 2579 savevm_skip_section_footers();
13d16814 2580 global_state_set_optional();
09b5e30d 2581 savevm_skip_configuration();
d25228e7
JW		 2582}
2583
5013c547 2584static void spapr_machine_2_3_class_options(MachineClass *mc)
6026db45 2585{
fc9f38c3 2586 spapr_machine_2_4_class_options(mc);
f949b4e5 2587 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3);
6026db45 2588}
fccbc785 2589DEFINE_SPAPR_MACHINE(2_3, "2.3", false);
6026db45 2590
1c5f29bb
DG		 2591/*
2592 * pseries-2.2
2593 */
2594
2595#define SPAPR_COMPAT_2_2 \
1c5f29bb
DG		 2596 HW_COMPAT_2_2 \
2597 {\
2598 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
2599 .property = "mem_win_size",\
2600 .value = "0x20000000",\
2601 },
2602
5013c547 2603static void spapr_machine_2_2_instance_options(MachineState *machine)
1c5f29bb 2604{
5013c547 2605 spapr_machine_2_3_instance_options(machine);
cba0e779 2606 machine->suppress_vmdesc = true;
1c5f29bb
DG		 2607}
2608
5013c547 2609static void spapr_machine_2_2_class_options(MachineClass *mc)
4aee7362 2610{
fc9f38c3 2611 spapr_machine_2_3_class_options(mc);
f949b4e5 2612 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2);
4aee7362 2613}
fccbc785 2614DEFINE_SPAPR_MACHINE(2_2, "2.2", false);
4aee7362 2615
1c5f29bb
DG		 2616/*
2617 * pseries-2.1
2618 */
2619#define SPAPR_COMPAT_2_1 \
1c5f29bb 2620 HW_COMPAT_2_1
3dab0244 2621
5013c547 2622static void spapr_machine_2_1_instance_options(MachineState *machine)
1c5f29bb 2623{
5013c547 2624 spapr_machine_2_2_instance_options(machine);
1c5f29bb 2625}
d25228e7 2626
5013c547 2627static void spapr_machine_2_1_class_options(MachineClass *mc)
d25228e7 2628{
fc9f38c3 2629 spapr_machine_2_2_class_options(mc);
f949b4e5 2630 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1);
d25228e7 2631}
fccbc785 2632DEFINE_SPAPR_MACHINE(2_1, "2.1", false);
fb0fc8f6 2633
29ee3247 2634static void spapr_machine_register_types(void)
9fdf0c29 2635{
29ee3247 2636 type_register_static(&spapr_machine_info);
9fdf0c29
DG		 2637}
2638
29ee3247 2639type_init(spapr_machine_register_types)
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