]>
Commit | Line | Data |
---|---|---|
093bc2cd AK |
1 | /* |
2 | * Physical memory management | |
3 | * | |
4 | * Copyright 2011 Red Hat, Inc. and/or its affiliates | |
5 | * | |
6 | * Authors: | |
7 | * Avi Kivity <[email protected]> | |
8 | * | |
9 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
10 | * the COPYING file in the top-level directory. | |
11 | * | |
6b620ca3 PB |
12 | * Contributions after 2012-01-13 are licensed under the terms of the |
13 | * GNU GPL, version 2 or (at your option) any later version. | |
093bc2cd AK |
14 | */ |
15 | ||
d38ea87a | 16 | #include "qemu/osdep.h" |
da34e65c | 17 | #include "qapi/error.h" |
33c11879 | 18 | #include "cpu.h" |
022c62cb PB |
19 | #include "exec/memory.h" |
20 | #include "exec/address-spaces.h" | |
409ddd01 | 21 | #include "qapi/visitor.h" |
1de7afc9 | 22 | #include "qemu/bitops.h" |
8c56c1a5 | 23 | #include "qemu/error-report.h" |
db725815 | 24 | #include "qemu/main-loop.h" |
b6b71cb5 | 25 | #include "qemu/qemu-print.h" |
2c9b15ca | 26 | #include "qom/object.h" |
0ab8ed18 | 27 | #include "trace-root.h" |
093bc2cd | 28 | |
022c62cb | 29 | #include "exec/memory-internal.h" |
220c3ebd | 30 | #include "exec/ram_addr.h" |
8c56c1a5 | 31 | #include "sysemu/kvm.h" |
e1c57ab8 | 32 | #include "sysemu/sysemu.h" |
14a48c1d | 33 | #include "sysemu/tcg.h" |
8072aae3 | 34 | #include "sysemu/accel.h" |
c9356746 | 35 | #include "hw/qdev-properties.h" |
8072aae3 | 36 | #include "hw/boards.h" |
b08199c6 | 37 | #include "migration/vmstate.h" |
67d95c15 | 38 | |
d197063f PB |
39 | //#define DEBUG_UNASSIGNED |
40 | ||
22bde714 JK |
41 | static unsigned memory_region_transaction_depth; |
42 | static bool memory_region_update_pending; | |
4dc56152 | 43 | static bool ioeventfd_update_pending; |
ae7a2bca | 44 | bool global_dirty_log; |
7664e80c | 45 | |
eae3eb3e | 46 | static QTAILQ_HEAD(, MemoryListener) memory_listeners |
72e22d2f | 47 | = QTAILQ_HEAD_INITIALIZER(memory_listeners); |
4ef4db86 | 48 | |
0d673e36 AK |
49 | static QTAILQ_HEAD(, AddressSpace) address_spaces |
50 | = QTAILQ_HEAD_INITIALIZER(address_spaces); | |
51 | ||
967dc9b1 AK |
52 | static GHashTable *flat_views; |
53 | ||
093bc2cd AK |
54 | typedef struct AddrRange AddrRange; |
55 | ||
8417cebf | 56 | /* |
c9cdaa3a | 57 | * Note that signed integers are needed for negative offsetting in aliases |
8417cebf AK |
58 | * (large MemoryRegion::alias_offset). |
59 | */ | |
093bc2cd | 60 | struct AddrRange { |
08dafab4 AK |
61 | Int128 start; |
62 | Int128 size; | |
093bc2cd AK |
63 | }; |
64 | ||
08dafab4 | 65 | static AddrRange addrrange_make(Int128 start, Int128 size) |
093bc2cd AK |
66 | { |
67 | return (AddrRange) { start, size }; | |
68 | } | |
69 | ||
70 | static bool addrrange_equal(AddrRange r1, AddrRange r2) | |
71 | { | |
08dafab4 | 72 | return int128_eq(r1.start, r2.start) && int128_eq(r1.size, r2.size); |
093bc2cd AK |
73 | } |
74 | ||
08dafab4 | 75 | static Int128 addrrange_end(AddrRange r) |
093bc2cd | 76 | { |
08dafab4 | 77 | return int128_add(r.start, r.size); |
093bc2cd AK |
78 | } |
79 | ||
08dafab4 | 80 | static AddrRange addrrange_shift(AddrRange range, Int128 delta) |
093bc2cd | 81 | { |
08dafab4 | 82 | int128_addto(&range.start, delta); |
093bc2cd AK |
83 | return range; |
84 | } | |
85 | ||
08dafab4 AK |
86 | static bool addrrange_contains(AddrRange range, Int128 addr) |
87 | { | |
88 | return int128_ge(addr, range.start) | |
89 | && int128_lt(addr, addrrange_end(range)); | |
90 | } | |
91 | ||
093bc2cd AK |
92 | static bool addrrange_intersects(AddrRange r1, AddrRange r2) |
93 | { | |
08dafab4 AK |
94 | return addrrange_contains(r1, r2.start) |
95 | || addrrange_contains(r2, r1.start); | |
093bc2cd AK |
96 | } |
97 | ||
98 | static AddrRange addrrange_intersection(AddrRange r1, AddrRange r2) | |
99 | { | |
08dafab4 AK |
100 | Int128 start = int128_max(r1.start, r2.start); |
101 | Int128 end = int128_min(addrrange_end(r1), addrrange_end(r2)); | |
102 | return addrrange_make(start, int128_sub(end, start)); | |
093bc2cd AK |
103 | } |
104 | ||
0e0d36b4 AK |
105 | enum ListenerDirection { Forward, Reverse }; |
106 | ||
7376e582 | 107 | #define MEMORY_LISTENER_CALL_GLOBAL(_callback, _direction, _args...) \ |
0e0d36b4 AK |
108 | do { \ |
109 | MemoryListener *_listener; \ | |
110 | \ | |
111 | switch (_direction) { \ | |
112 | case Forward: \ | |
113 | QTAILQ_FOREACH(_listener, &memory_listeners, link) { \ | |
975aefe0 AK |
114 | if (_listener->_callback) { \ |
115 | _listener->_callback(_listener, ##_args); \ | |
116 | } \ | |
0e0d36b4 AK |
117 | } \ |
118 | break; \ | |
119 | case Reverse: \ | |
eae3eb3e | 120 | QTAILQ_FOREACH_REVERSE(_listener, &memory_listeners, link) { \ |
975aefe0 AK |
121 | if (_listener->_callback) { \ |
122 | _listener->_callback(_listener, ##_args); \ | |
123 | } \ | |
0e0d36b4 AK |
124 | } \ |
125 | break; \ | |
126 | default: \ | |
127 | abort(); \ | |
128 | } \ | |
129 | } while (0) | |
130 | ||
9a54635d | 131 | #define MEMORY_LISTENER_CALL(_as, _callback, _direction, _section, _args...) \ |
7376e582 AK |
132 | do { \ |
133 | MemoryListener *_listener; \ | |
134 | \ | |
135 | switch (_direction) { \ | |
136 | case Forward: \ | |
eae3eb3e | 137 | QTAILQ_FOREACH(_listener, &(_as)->listeners, link_as) { \ |
9a54635d | 138 | if (_listener->_callback) { \ |
7376e582 AK |
139 | _listener->_callback(_listener, _section, ##_args); \ |
140 | } \ | |
141 | } \ | |
142 | break; \ | |
143 | case Reverse: \ | |
eae3eb3e | 144 | QTAILQ_FOREACH_REVERSE(_listener, &(_as)->listeners, link_as) { \ |
9a54635d | 145 | if (_listener->_callback) { \ |
7376e582 AK |
146 | _listener->_callback(_listener, _section, ##_args); \ |
147 | } \ | |
148 | } \ | |
149 | break; \ | |
150 | default: \ | |
151 | abort(); \ | |
152 | } \ | |
153 | } while (0) | |
154 | ||
dfde4e6e | 155 | /* No need to ref/unref .mr, the FlatRange keeps it alive. */ |
b2dfd71c | 156 | #define MEMORY_LISTENER_UPDATE_REGION(fr, as, dir, callback, _args...) \ |
9c1f8f44 | 157 | do { \ |
16620684 AK |
158 | MemoryRegionSection mrs = section_from_flat_range(fr, \ |
159 | address_space_to_flatview(as)); \ | |
9a54635d | 160 | MEMORY_LISTENER_CALL(as, callback, dir, &mrs, ##_args); \ |
9c1f8f44 | 161 | } while(0) |
0e0d36b4 | 162 | |
093bc2cd AK |
163 | struct CoalescedMemoryRange { |
164 | AddrRange addr; | |
165 | QTAILQ_ENTRY(CoalescedMemoryRange) link; | |
166 | }; | |
167 | ||
3e9d69e7 AK |
168 | struct MemoryRegionIoeventfd { |
169 | AddrRange addr; | |
170 | bool match_data; | |
171 | uint64_t data; | |
753d5e14 | 172 | EventNotifier *e; |
3e9d69e7 AK |
173 | }; |
174 | ||
73bb753d TB |
175 | static bool memory_region_ioeventfd_before(MemoryRegionIoeventfd *a, |
176 | MemoryRegionIoeventfd *b) | |
3e9d69e7 | 177 | { |
73bb753d | 178 | if (int128_lt(a->addr.start, b->addr.start)) { |
3e9d69e7 | 179 | return true; |
73bb753d | 180 | } else if (int128_gt(a->addr.start, b->addr.start)) { |
3e9d69e7 | 181 | return false; |
73bb753d | 182 | } else if (int128_lt(a->addr.size, b->addr.size)) { |
3e9d69e7 | 183 | return true; |
73bb753d | 184 | } else if (int128_gt(a->addr.size, b->addr.size)) { |
3e9d69e7 | 185 | return false; |
73bb753d | 186 | } else if (a->match_data < b->match_data) { |
3e9d69e7 | 187 | return true; |
73bb753d | 188 | } else if (a->match_data > b->match_data) { |
3e9d69e7 | 189 | return false; |
73bb753d TB |
190 | } else if (a->match_data) { |
191 | if (a->data < b->data) { | |
3e9d69e7 | 192 | return true; |
73bb753d | 193 | } else if (a->data > b->data) { |
3e9d69e7 AK |
194 | return false; |
195 | } | |
196 | } | |
73bb753d | 197 | if (a->e < b->e) { |
3e9d69e7 | 198 | return true; |
73bb753d | 199 | } else if (a->e > b->e) { |
3e9d69e7 AK |
200 | return false; |
201 | } | |
202 | return false; | |
203 | } | |
204 | ||
73bb753d TB |
205 | static bool memory_region_ioeventfd_equal(MemoryRegionIoeventfd *a, |
206 | MemoryRegionIoeventfd *b) | |
3e9d69e7 AK |
207 | { |
208 | return !memory_region_ioeventfd_before(a, b) | |
209 | && !memory_region_ioeventfd_before(b, a); | |
210 | } | |
211 | ||
093bc2cd AK |
212 | /* Range of memory in the global map. Addresses are absolute. */ |
213 | struct FlatRange { | |
214 | MemoryRegion *mr; | |
a8170e5e | 215 | hwaddr offset_in_region; |
093bc2cd | 216 | AddrRange addr; |
5a583347 | 217 | uint8_t dirty_log_mask; |
b138e654 | 218 | bool romd_mode; |
fb1cd6f9 | 219 | bool readonly; |
c26763f8 | 220 | bool nonvolatile; |
3ac7d43a | 221 | int has_coalesced_range; |
093bc2cd AK |
222 | }; |
223 | ||
093bc2cd AK |
224 | #define FOR_EACH_FLAT_RANGE(var, view) \ |
225 | for (var = (view)->ranges; var < (view)->ranges + (view)->nr; ++var) | |
226 | ||
9c1f8f44 | 227 | static inline MemoryRegionSection |
16620684 | 228 | section_from_flat_range(FlatRange *fr, FlatView *fv) |
9c1f8f44 PB |
229 | { |
230 | return (MemoryRegionSection) { | |
231 | .mr = fr->mr, | |
16620684 | 232 | .fv = fv, |
9c1f8f44 PB |
233 | .offset_within_region = fr->offset_in_region, |
234 | .size = fr->addr.size, | |
235 | .offset_within_address_space = int128_get64(fr->addr.start), | |
236 | .readonly = fr->readonly, | |
c26763f8 | 237 | .nonvolatile = fr->nonvolatile, |
9c1f8f44 PB |
238 | }; |
239 | } | |
240 | ||
093bc2cd AK |
241 | static bool flatrange_equal(FlatRange *a, FlatRange *b) |
242 | { | |
243 | return a->mr == b->mr | |
244 | && addrrange_equal(a->addr, b->addr) | |
d0a9b5bc | 245 | && a->offset_in_region == b->offset_in_region |
b138e654 | 246 | && a->romd_mode == b->romd_mode |
c26763f8 MAL |
247 | && a->readonly == b->readonly |
248 | && a->nonvolatile == b->nonvolatile; | |
093bc2cd AK |
249 | } |
250 | ||
89c177bb | 251 | static FlatView *flatview_new(MemoryRegion *mr_root) |
093bc2cd | 252 | { |
cc94cd6d AK |
253 | FlatView *view; |
254 | ||
255 | view = g_new0(FlatView, 1); | |
856d7245 | 256 | view->ref = 1; |
89c177bb AK |
257 | view->root = mr_root; |
258 | memory_region_ref(mr_root); | |
02d9651d | 259 | trace_flatview_new(view, mr_root); |
cc94cd6d AK |
260 | |
261 | return view; | |
093bc2cd AK |
262 | } |
263 | ||
264 | /* Insert a range into a given position. Caller is responsible for maintaining | |
265 | * sorting order. | |
266 | */ | |
267 | static void flatview_insert(FlatView *view, unsigned pos, FlatRange *range) | |
268 | { | |
269 | if (view->nr == view->nr_allocated) { | |
270 | view->nr_allocated = MAX(2 * view->nr, 10); | |
7267c094 | 271 | view->ranges = g_realloc(view->ranges, |
093bc2cd AK |
272 | view->nr_allocated * sizeof(*view->ranges)); |
273 | } | |
274 | memmove(view->ranges + pos + 1, view->ranges + pos, | |
275 | (view->nr - pos) * sizeof(FlatRange)); | |
276 | view->ranges[pos] = *range; | |
dfde4e6e | 277 | memory_region_ref(range->mr); |
093bc2cd AK |
278 | ++view->nr; |
279 | } | |
280 | ||
281 | static void flatview_destroy(FlatView *view) | |
282 | { | |
dfde4e6e PB |
283 | int i; |
284 | ||
02d9651d | 285 | trace_flatview_destroy(view, view->root); |
66a6df1d AK |
286 | if (view->dispatch) { |
287 | address_space_dispatch_free(view->dispatch); | |
288 | } | |
dfde4e6e PB |
289 | for (i = 0; i < view->nr; i++) { |
290 | memory_region_unref(view->ranges[i].mr); | |
291 | } | |
7267c094 | 292 | g_free(view->ranges); |
89c177bb | 293 | memory_region_unref(view->root); |
a9a0c06d | 294 | g_free(view); |
093bc2cd AK |
295 | } |
296 | ||
447b0d0b | 297 | static bool flatview_ref(FlatView *view) |
856d7245 | 298 | { |
447b0d0b | 299 | return atomic_fetch_inc_nonzero(&view->ref) > 0; |
856d7245 PB |
300 | } |
301 | ||
48564041 | 302 | void flatview_unref(FlatView *view) |
856d7245 PB |
303 | { |
304 | if (atomic_fetch_dec(&view->ref) == 1) { | |
02d9651d | 305 | trace_flatview_destroy_rcu(view, view->root); |
092aa2fc | 306 | assert(view->root); |
66a6df1d | 307 | call_rcu(view, flatview_destroy, rcu); |
856d7245 PB |
308 | } |
309 | } | |
310 | ||
3d8e6bf9 AK |
311 | static bool can_merge(FlatRange *r1, FlatRange *r2) |
312 | { | |
08dafab4 | 313 | return int128_eq(addrrange_end(r1->addr), r2->addr.start) |
3d8e6bf9 | 314 | && r1->mr == r2->mr |
08dafab4 AK |
315 | && int128_eq(int128_add(int128_make64(r1->offset_in_region), |
316 | r1->addr.size), | |
317 | int128_make64(r2->offset_in_region)) | |
d0a9b5bc | 318 | && r1->dirty_log_mask == r2->dirty_log_mask |
b138e654 | 319 | && r1->romd_mode == r2->romd_mode |
c26763f8 MAL |
320 | && r1->readonly == r2->readonly |
321 | && r1->nonvolatile == r2->nonvolatile; | |
3d8e6bf9 AK |
322 | } |
323 | ||
8508e024 | 324 | /* Attempt to simplify a view by merging adjacent ranges */ |
3d8e6bf9 AK |
325 | static void flatview_simplify(FlatView *view) |
326 | { | |
838ec117 | 327 | unsigned i, j, k; |
3d8e6bf9 AK |
328 | |
329 | i = 0; | |
330 | while (i < view->nr) { | |
331 | j = i + 1; | |
332 | while (j < view->nr | |
333 | && can_merge(&view->ranges[j-1], &view->ranges[j])) { | |
08dafab4 | 334 | int128_addto(&view->ranges[i].addr.size, view->ranges[j].addr.size); |
3d8e6bf9 AK |
335 | ++j; |
336 | } | |
337 | ++i; | |
838ec117 KW |
338 | for (k = i; k < j; k++) { |
339 | memory_region_unref(view->ranges[k].mr); | |
340 | } | |
3d8e6bf9 AK |
341 | memmove(&view->ranges[i], &view->ranges[j], |
342 | (view->nr - j) * sizeof(view->ranges[j])); | |
343 | view->nr -= j - i; | |
344 | } | |
345 | } | |
346 | ||
e7342aa3 PB |
347 | static bool memory_region_big_endian(MemoryRegion *mr) |
348 | { | |
349 | #ifdef TARGET_WORDS_BIGENDIAN | |
350 | return mr->ops->endianness != DEVICE_LITTLE_ENDIAN; | |
351 | #else | |
352 | return mr->ops->endianness == DEVICE_BIG_ENDIAN; | |
353 | #endif | |
354 | } | |
355 | ||
e11ef3d1 PB |
356 | static bool memory_region_wrong_endianness(MemoryRegion *mr) |
357 | { | |
358 | #ifdef TARGET_WORDS_BIGENDIAN | |
359 | return mr->ops->endianness == DEVICE_LITTLE_ENDIAN; | |
360 | #else | |
361 | return mr->ops->endianness == DEVICE_BIG_ENDIAN; | |
362 | #endif | |
363 | } | |
364 | ||
365 | static void adjust_endianness(MemoryRegion *mr, uint64_t *data, unsigned size) | |
366 | { | |
367 | if (memory_region_wrong_endianness(mr)) { | |
368 | switch (size) { | |
369 | case 1: | |
370 | break; | |
371 | case 2: | |
372 | *data = bswap16(*data); | |
373 | break; | |
374 | case 4: | |
375 | *data = bswap32(*data); | |
376 | break; | |
377 | case 8: | |
378 | *data = bswap64(*data); | |
379 | break; | |
380 | default: | |
381 | abort(); | |
382 | } | |
383 | } | |
384 | } | |
385 | ||
3c754a93 | 386 | static inline void memory_region_shift_read_access(uint64_t *value, |
98f52cdb | 387 | signed shift, |
3c754a93 PMD |
388 | uint64_t mask, |
389 | uint64_t tmp) | |
390 | { | |
98f52cdb PMD |
391 | if (shift >= 0) { |
392 | *value |= (tmp & mask) << shift; | |
393 | } else { | |
394 | *value |= (tmp & mask) >> -shift; | |
395 | } | |
3c754a93 PMD |
396 | } |
397 | ||
398 | static inline uint64_t memory_region_shift_write_access(uint64_t *value, | |
98f52cdb | 399 | signed shift, |
3c754a93 PMD |
400 | uint64_t mask) |
401 | { | |
98f52cdb PMD |
402 | uint64_t tmp; |
403 | ||
404 | if (shift >= 0) { | |
405 | tmp = (*value >> shift) & mask; | |
406 | } else { | |
407 | tmp = (*value << -shift) & mask; | |
408 | } | |
409 | ||
410 | return tmp; | |
3c754a93 PMD |
411 | } |
412 | ||
4779dc1d HB |
413 | static hwaddr memory_region_to_absolute_addr(MemoryRegion *mr, hwaddr offset) |
414 | { | |
415 | MemoryRegion *root; | |
416 | hwaddr abs_addr = offset; | |
417 | ||
418 | abs_addr += mr->addr; | |
419 | for (root = mr; root->container; ) { | |
420 | root = root->container; | |
421 | abs_addr += root->addr; | |
422 | } | |
423 | ||
424 | return abs_addr; | |
425 | } | |
426 | ||
5a68be94 HB |
427 | static int get_cpu_index(void) |
428 | { | |
429 | if (current_cpu) { | |
430 | return current_cpu->cpu_index; | |
431 | } | |
432 | return -1; | |
433 | } | |
434 | ||
cc05c43a | 435 | static MemTxResult memory_region_read_accessor(MemoryRegion *mr, |
ce5d2f33 PB |
436 | hwaddr addr, |
437 | uint64_t *value, | |
438 | unsigned size, | |
98f52cdb | 439 | signed shift, |
cc05c43a PM |
440 | uint64_t mask, |
441 | MemTxAttrs attrs) | |
ce5d2f33 | 442 | { |
ce5d2f33 PB |
443 | uint64_t tmp; |
444 | ||
cc05c43a | 445 | tmp = mr->ops->read(mr->opaque, addr, size); |
23d92d68 | 446 | if (mr->subpage) { |
5a68be94 | 447 | trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size); |
f2d08942 HB |
448 | } else if (mr == &io_mem_notdirty) { |
449 | /* Accesses to code which has previously been translated into a TB show | |
450 | * up in the MMIO path, as accesses to the io_mem_notdirty | |
451 | * MemoryRegion. */ | |
452 | trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size); | |
4779dc1d HB |
453 | } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) { |
454 | hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr); | |
5a68be94 | 455 | trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size); |
23d92d68 | 456 | } |
3c754a93 | 457 | memory_region_shift_read_access(value, shift, mask, tmp); |
cc05c43a | 458 | return MEMTX_OK; |
ce5d2f33 PB |
459 | } |
460 | ||
cc05c43a PM |
461 | static MemTxResult memory_region_read_with_attrs_accessor(MemoryRegion *mr, |
462 | hwaddr addr, | |
463 | uint64_t *value, | |
464 | unsigned size, | |
98f52cdb | 465 | signed shift, |
cc05c43a PM |
466 | uint64_t mask, |
467 | MemTxAttrs attrs) | |
164a4dcd | 468 | { |
cc05c43a PM |
469 | uint64_t tmp = 0; |
470 | MemTxResult r; | |
164a4dcd | 471 | |
cc05c43a | 472 | r = mr->ops->read_with_attrs(mr->opaque, addr, &tmp, size, attrs); |
23d92d68 | 473 | if (mr->subpage) { |
5a68be94 | 474 | trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size); |
f2d08942 HB |
475 | } else if (mr == &io_mem_notdirty) { |
476 | /* Accesses to code which has previously been translated into a TB show | |
477 | * up in the MMIO path, as accesses to the io_mem_notdirty | |
478 | * MemoryRegion. */ | |
479 | trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size); | |
4779dc1d HB |
480 | } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) { |
481 | hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr); | |
5a68be94 | 482 | trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size); |
23d92d68 | 483 | } |
3c754a93 | 484 | memory_region_shift_read_access(value, shift, mask, tmp); |
cc05c43a | 485 | return r; |
164a4dcd AK |
486 | } |
487 | ||
cc05c43a PM |
488 | static MemTxResult memory_region_write_accessor(MemoryRegion *mr, |
489 | hwaddr addr, | |
490 | uint64_t *value, | |
491 | unsigned size, | |
98f52cdb | 492 | signed shift, |
cc05c43a PM |
493 | uint64_t mask, |
494 | MemTxAttrs attrs) | |
164a4dcd | 495 | { |
3c754a93 | 496 | uint64_t tmp = memory_region_shift_write_access(value, shift, mask); |
164a4dcd | 497 | |
23d92d68 | 498 | if (mr->subpage) { |
5a68be94 | 499 | trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size); |
f2d08942 HB |
500 | } else if (mr == &io_mem_notdirty) { |
501 | /* Accesses to code which has previously been translated into a TB show | |
502 | * up in the MMIO path, as accesses to the io_mem_notdirty | |
503 | * MemoryRegion. */ | |
504 | trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size); | |
4779dc1d HB |
505 | } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) { |
506 | hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr); | |
5a68be94 | 507 | trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size); |
23d92d68 | 508 | } |
164a4dcd | 509 | mr->ops->write(mr->opaque, addr, tmp, size); |
cc05c43a | 510 | return MEMTX_OK; |
164a4dcd AK |
511 | } |
512 | ||
cc05c43a PM |
513 | static MemTxResult memory_region_write_with_attrs_accessor(MemoryRegion *mr, |
514 | hwaddr addr, | |
515 | uint64_t *value, | |
516 | unsigned size, | |
98f52cdb | 517 | signed shift, |
cc05c43a PM |
518 | uint64_t mask, |
519 | MemTxAttrs attrs) | |
520 | { | |
3c754a93 | 521 | uint64_t tmp = memory_region_shift_write_access(value, shift, mask); |
cc05c43a | 522 | |
23d92d68 | 523 | if (mr->subpage) { |
5a68be94 | 524 | trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size); |
f2d08942 HB |
525 | } else if (mr == &io_mem_notdirty) { |
526 | /* Accesses to code which has previously been translated into a TB show | |
527 | * up in the MMIO path, as accesses to the io_mem_notdirty | |
528 | * MemoryRegion. */ | |
529 | trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size); | |
4779dc1d HB |
530 | } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) { |
531 | hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr); | |
5a68be94 | 532 | trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size); |
23d92d68 | 533 | } |
cc05c43a PM |
534 | return mr->ops->write_with_attrs(mr->opaque, addr, tmp, size, attrs); |
535 | } | |
536 | ||
537 | static MemTxResult access_with_adjusted_size(hwaddr addr, | |
164a4dcd AK |
538 | uint64_t *value, |
539 | unsigned size, | |
540 | unsigned access_size_min, | |
541 | unsigned access_size_max, | |
05e015f7 KF |
542 | MemTxResult (*access_fn) |
543 | (MemoryRegion *mr, | |
544 | hwaddr addr, | |
545 | uint64_t *value, | |
546 | unsigned size, | |
98f52cdb | 547 | signed shift, |
05e015f7 KF |
548 | uint64_t mask, |
549 | MemTxAttrs attrs), | |
cc05c43a PM |
550 | MemoryRegion *mr, |
551 | MemTxAttrs attrs) | |
164a4dcd AK |
552 | { |
553 | uint64_t access_mask; | |
554 | unsigned access_size; | |
555 | unsigned i; | |
cc05c43a | 556 | MemTxResult r = MEMTX_OK; |
164a4dcd AK |
557 | |
558 | if (!access_size_min) { | |
559 | access_size_min = 1; | |
560 | } | |
561 | if (!access_size_max) { | |
562 | access_size_max = 4; | |
563 | } | |
ce5d2f33 PB |
564 | |
565 | /* FIXME: support unaligned access? */ | |
164a4dcd | 566 | access_size = MAX(MIN(size, access_size_max), access_size_min); |
36960b4d | 567 | access_mask = MAKE_64BIT_MASK(0, access_size * 8); |
e7342aa3 PB |
568 | if (memory_region_big_endian(mr)) { |
569 | for (i = 0; i < size; i += access_size) { | |
05e015f7 | 570 | r |= access_fn(mr, addr + i, value, access_size, |
cc05c43a | 571 | (size - access_size - i) * 8, access_mask, attrs); |
e7342aa3 PB |
572 | } |
573 | } else { | |
574 | for (i = 0; i < size; i += access_size) { | |
05e015f7 | 575 | r |= access_fn(mr, addr + i, value, access_size, i * 8, |
cc05c43a | 576 | access_mask, attrs); |
e7342aa3 | 577 | } |
164a4dcd | 578 | } |
cc05c43a | 579 | return r; |
164a4dcd AK |
580 | } |
581 | ||
e2177955 AK |
582 | static AddressSpace *memory_region_to_address_space(MemoryRegion *mr) |
583 | { | |
0d673e36 AK |
584 | AddressSpace *as; |
585 | ||
feca4ac1 PB |
586 | while (mr->container) { |
587 | mr = mr->container; | |
e2177955 | 588 | } |
0d673e36 AK |
589 | QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) { |
590 | if (mr == as->root) { | |
591 | return as; | |
592 | } | |
e2177955 | 593 | } |
eed2bacf | 594 | return NULL; |
e2177955 AK |
595 | } |
596 | ||
093bc2cd AK |
597 | /* Render a memory region into the global view. Ranges in @view obscure |
598 | * ranges in @mr. | |
599 | */ | |
600 | static void render_memory_region(FlatView *view, | |
601 | MemoryRegion *mr, | |
08dafab4 | 602 | Int128 base, |
fb1cd6f9 | 603 | AddrRange clip, |
c26763f8 MAL |
604 | bool readonly, |
605 | bool nonvolatile) | |
093bc2cd AK |
606 | { |
607 | MemoryRegion *subregion; | |
608 | unsigned i; | |
a8170e5e | 609 | hwaddr offset_in_region; |
08dafab4 AK |
610 | Int128 remain; |
611 | Int128 now; | |
093bc2cd AK |
612 | FlatRange fr; |
613 | AddrRange tmp; | |
614 | ||
6bba19ba AK |
615 | if (!mr->enabled) { |
616 | return; | |
617 | } | |
618 | ||
08dafab4 | 619 | int128_addto(&base, int128_make64(mr->addr)); |
fb1cd6f9 | 620 | readonly |= mr->readonly; |
c26763f8 | 621 | nonvolatile |= mr->nonvolatile; |
093bc2cd AK |
622 | |
623 | tmp = addrrange_make(base, mr->size); | |
624 | ||
625 | if (!addrrange_intersects(tmp, clip)) { | |
626 | return; | |
627 | } | |
628 | ||
629 | clip = addrrange_intersection(tmp, clip); | |
630 | ||
631 | if (mr->alias) { | |
08dafab4 AK |
632 | int128_subfrom(&base, int128_make64(mr->alias->addr)); |
633 | int128_subfrom(&base, int128_make64(mr->alias_offset)); | |
c26763f8 MAL |
634 | render_memory_region(view, mr->alias, base, clip, |
635 | readonly, nonvolatile); | |
093bc2cd AK |
636 | return; |
637 | } | |
638 | ||
639 | /* Render subregions in priority order. */ | |
640 | QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) { | |
c26763f8 MAL |
641 | render_memory_region(view, subregion, base, clip, |
642 | readonly, nonvolatile); | |
093bc2cd AK |
643 | } |
644 | ||
14a3c10a | 645 | if (!mr->terminates) { |
093bc2cd AK |
646 | return; |
647 | } | |
648 | ||
08dafab4 | 649 | offset_in_region = int128_get64(int128_sub(clip.start, base)); |
093bc2cd AK |
650 | base = clip.start; |
651 | remain = clip.size; | |
652 | ||
2eb74e1a | 653 | fr.mr = mr; |
6f6a5ef3 | 654 | fr.dirty_log_mask = memory_region_get_dirty_log_mask(mr); |
b138e654 | 655 | fr.romd_mode = mr->romd_mode; |
2eb74e1a | 656 | fr.readonly = readonly; |
c26763f8 | 657 | fr.nonvolatile = nonvolatile; |
3ac7d43a | 658 | fr.has_coalesced_range = 0; |
2eb74e1a | 659 | |
093bc2cd | 660 | /* Render the region itself into any gaps left by the current view. */ |
08dafab4 AK |
661 | for (i = 0; i < view->nr && int128_nz(remain); ++i) { |
662 | if (int128_ge(base, addrrange_end(view->ranges[i].addr))) { | |
093bc2cd AK |
663 | continue; |
664 | } | |
08dafab4 AK |
665 | if (int128_lt(base, view->ranges[i].addr.start)) { |
666 | now = int128_min(remain, | |
667 | int128_sub(view->ranges[i].addr.start, base)); | |
093bc2cd AK |
668 | fr.offset_in_region = offset_in_region; |
669 | fr.addr = addrrange_make(base, now); | |
670 | flatview_insert(view, i, &fr); | |
671 | ++i; | |
08dafab4 AK |
672 | int128_addto(&base, now); |
673 | offset_in_region += int128_get64(now); | |
674 | int128_subfrom(&remain, now); | |
093bc2cd | 675 | } |
d26a8cae AK |
676 | now = int128_sub(int128_min(int128_add(base, remain), |
677 | addrrange_end(view->ranges[i].addr)), | |
678 | base); | |
679 | int128_addto(&base, now); | |
680 | offset_in_region += int128_get64(now); | |
681 | int128_subfrom(&remain, now); | |
093bc2cd | 682 | } |
08dafab4 | 683 | if (int128_nz(remain)) { |
093bc2cd AK |
684 | fr.offset_in_region = offset_in_region; |
685 | fr.addr = addrrange_make(base, remain); | |
686 | flatview_insert(view, i, &fr); | |
687 | } | |
688 | } | |
689 | ||
89c177bb AK |
690 | static MemoryRegion *memory_region_get_flatview_root(MemoryRegion *mr) |
691 | { | |
e673ba9a PB |
692 | while (mr->enabled) { |
693 | if (mr->alias) { | |
694 | if (!mr->alias_offset && int128_ge(mr->size, mr->alias->size)) { | |
695 | /* The alias is included in its entirety. Use it as | |
696 | * the "real" root, so that we can share more FlatViews. | |
697 | */ | |
698 | mr = mr->alias; | |
699 | continue; | |
700 | } | |
701 | } else if (!mr->terminates) { | |
702 | unsigned int found = 0; | |
703 | MemoryRegion *child, *next = NULL; | |
704 | QTAILQ_FOREACH(child, &mr->subregions, subregions_link) { | |
705 | if (child->enabled) { | |
706 | if (++found > 1) { | |
707 | next = NULL; | |
708 | break; | |
709 | } | |
710 | if (!child->addr && int128_ge(mr->size, child->size)) { | |
711 | /* A child is included in its entirety. If it's the only | |
712 | * enabled one, use it in the hope of finding an alias down the | |
713 | * way. This will also let us share FlatViews. | |
714 | */ | |
715 | next = child; | |
716 | } | |
717 | } | |
718 | } | |
092aa2fc AK |
719 | if (found == 0) { |
720 | return NULL; | |
721 | } | |
e673ba9a PB |
722 | if (next) { |
723 | mr = next; | |
724 | continue; | |
725 | } | |
726 | } | |
727 | ||
092aa2fc | 728 | return mr; |
89c177bb AK |
729 | } |
730 | ||
092aa2fc | 731 | return NULL; |
89c177bb AK |
732 | } |
733 | ||
093bc2cd | 734 | /* Render a memory topology into a list of disjoint absolute ranges. */ |
a9a0c06d | 735 | static FlatView *generate_memory_topology(MemoryRegion *mr) |
093bc2cd | 736 | { |
9bf561e3 | 737 | int i; |
a9a0c06d | 738 | FlatView *view; |
093bc2cd | 739 | |
89c177bb | 740 | view = flatview_new(mr); |
093bc2cd | 741 | |
83f3c251 | 742 | if (mr) { |
a9a0c06d | 743 | render_memory_region(view, mr, int128_zero(), |
c26763f8 MAL |
744 | addrrange_make(int128_zero(), int128_2_64()), |
745 | false, false); | |
83f3c251 | 746 | } |
a9a0c06d | 747 | flatview_simplify(view); |
093bc2cd | 748 | |
9bf561e3 AK |
749 | view->dispatch = address_space_dispatch_new(view); |
750 | for (i = 0; i < view->nr; i++) { | |
751 | MemoryRegionSection mrs = | |
752 | section_from_flat_range(&view->ranges[i], view); | |
753 | flatview_add_to_dispatch(view, &mrs); | |
754 | } | |
755 | address_space_dispatch_compact(view->dispatch); | |
967dc9b1 | 756 | g_hash_table_replace(flat_views, mr, view); |
9bf561e3 | 757 | |
093bc2cd AK |
758 | return view; |
759 | } | |
760 | ||
3e9d69e7 AK |
761 | static void address_space_add_del_ioeventfds(AddressSpace *as, |
762 | MemoryRegionIoeventfd *fds_new, | |
763 | unsigned fds_new_nb, | |
764 | MemoryRegionIoeventfd *fds_old, | |
765 | unsigned fds_old_nb) | |
766 | { | |
767 | unsigned iold, inew; | |
80a1ea37 AK |
768 | MemoryRegionIoeventfd *fd; |
769 | MemoryRegionSection section; | |
3e9d69e7 AK |
770 | |
771 | /* Generate a symmetric difference of the old and new fd sets, adding | |
772 | * and deleting as necessary. | |
773 | */ | |
774 | ||
775 | iold = inew = 0; | |
776 | while (iold < fds_old_nb || inew < fds_new_nb) { | |
777 | if (iold < fds_old_nb | |
778 | && (inew == fds_new_nb | |
73bb753d TB |
779 | || memory_region_ioeventfd_before(&fds_old[iold], |
780 | &fds_new[inew]))) { | |
80a1ea37 AK |
781 | fd = &fds_old[iold]; |
782 | section = (MemoryRegionSection) { | |
16620684 | 783 | .fv = address_space_to_flatview(as), |
80a1ea37 | 784 | .offset_within_address_space = int128_get64(fd->addr.start), |
052e87b0 | 785 | .size = fd->addr.size, |
80a1ea37 | 786 | }; |
9a54635d | 787 | MEMORY_LISTENER_CALL(as, eventfd_del, Forward, §ion, |
753d5e14 | 788 | fd->match_data, fd->data, fd->e); |
3e9d69e7 AK |
789 | ++iold; |
790 | } else if (inew < fds_new_nb | |
791 | && (iold == fds_old_nb | |
73bb753d TB |
792 | || memory_region_ioeventfd_before(&fds_new[inew], |
793 | &fds_old[iold]))) { | |
80a1ea37 AK |
794 | fd = &fds_new[inew]; |
795 | section = (MemoryRegionSection) { | |
16620684 | 796 | .fv = address_space_to_flatview(as), |
80a1ea37 | 797 | .offset_within_address_space = int128_get64(fd->addr.start), |
052e87b0 | 798 | .size = fd->addr.size, |
80a1ea37 | 799 | }; |
9a54635d | 800 | MEMORY_LISTENER_CALL(as, eventfd_add, Reverse, §ion, |
753d5e14 | 801 | fd->match_data, fd->data, fd->e); |
3e9d69e7 AK |
802 | ++inew; |
803 | } else { | |
804 | ++iold; | |
805 | ++inew; | |
806 | } | |
807 | } | |
808 | } | |
809 | ||
48564041 | 810 | FlatView *address_space_get_flatview(AddressSpace *as) |
856d7245 PB |
811 | { |
812 | FlatView *view; | |
813 | ||
374f2981 | 814 | rcu_read_lock(); |
447b0d0b | 815 | do { |
16620684 | 816 | view = address_space_to_flatview(as); |
447b0d0b PB |
817 | /* If somebody has replaced as->current_map concurrently, |
818 | * flatview_ref returns false. | |
819 | */ | |
820 | } while (!flatview_ref(view)); | |
374f2981 | 821 | rcu_read_unlock(); |
856d7245 PB |
822 | return view; |
823 | } | |
824 | ||
3e9d69e7 AK |
825 | static void address_space_update_ioeventfds(AddressSpace *as) |
826 | { | |
99e86347 | 827 | FlatView *view; |
3e9d69e7 AK |
828 | FlatRange *fr; |
829 | unsigned ioeventfd_nb = 0; | |
830 | MemoryRegionIoeventfd *ioeventfds = NULL; | |
831 | AddrRange tmp; | |
832 | unsigned i; | |
833 | ||
856d7245 | 834 | view = address_space_get_flatview(as); |
99e86347 | 835 | FOR_EACH_FLAT_RANGE(fr, view) { |
3e9d69e7 AK |
836 | for (i = 0; i < fr->mr->ioeventfd_nb; ++i) { |
837 | tmp = addrrange_shift(fr->mr->ioeventfds[i].addr, | |
08dafab4 AK |
838 | int128_sub(fr->addr.start, |
839 | int128_make64(fr->offset_in_region))); | |
3e9d69e7 AK |
840 | if (addrrange_intersects(fr->addr, tmp)) { |
841 | ++ioeventfd_nb; | |
7267c094 | 842 | ioeventfds = g_realloc(ioeventfds, |
3e9d69e7 AK |
843 | ioeventfd_nb * sizeof(*ioeventfds)); |
844 | ioeventfds[ioeventfd_nb-1] = fr->mr->ioeventfds[i]; | |
845 | ioeventfds[ioeventfd_nb-1].addr = tmp; | |
846 | } | |
847 | } | |
848 | } | |
849 | ||
850 | address_space_add_del_ioeventfds(as, ioeventfds, ioeventfd_nb, | |
851 | as->ioeventfds, as->ioeventfd_nb); | |
852 | ||
7267c094 | 853 | g_free(as->ioeventfds); |
3e9d69e7 AK |
854 | as->ioeventfds = ioeventfds; |
855 | as->ioeventfd_nb = ioeventfd_nb; | |
856d7245 | 856 | flatview_unref(view); |
3e9d69e7 AK |
857 | } |
858 | ||
909bf763 PB |
859 | static void flat_range_coalesced_io_del(FlatRange *fr, AddressSpace *as) |
860 | { | |
1f7af804 PB |
861 | if (!fr->has_coalesced_range) { |
862 | return; | |
863 | } | |
864 | ||
3ac7d43a PB |
865 | if (--fr->has_coalesced_range > 0) { |
866 | return; | |
867 | } | |
868 | ||
909bf763 PB |
869 | MEMORY_LISTENER_UPDATE_REGION(fr, as, Reverse, coalesced_io_del, |
870 | int128_get64(fr->addr.start), | |
871 | int128_get64(fr->addr.size)); | |
872 | } | |
873 | ||
874 | static void flat_range_coalesced_io_add(FlatRange *fr, AddressSpace *as) | |
875 | { | |
876 | MemoryRegion *mr = fr->mr; | |
877 | CoalescedMemoryRange *cmr; | |
878 | AddrRange tmp; | |
879 | ||
1f7af804 PB |
880 | if (QTAILQ_EMPTY(&mr->coalesced)) { |
881 | return; | |
882 | } | |
883 | ||
3ac7d43a PB |
884 | if (fr->has_coalesced_range++) { |
885 | return; | |
886 | } | |
887 | ||
909bf763 PB |
888 | QTAILQ_FOREACH(cmr, &mr->coalesced, link) { |
889 | tmp = addrrange_shift(cmr->addr, | |
890 | int128_sub(fr->addr.start, | |
891 | int128_make64(fr->offset_in_region))); | |
892 | if (!addrrange_intersects(tmp, fr->addr)) { | |
893 | continue; | |
894 | } | |
895 | tmp = addrrange_intersection(tmp, fr->addr); | |
896 | MEMORY_LISTENER_UPDATE_REGION(fr, as, Forward, coalesced_io_add, | |
897 | int128_get64(tmp.start), | |
898 | int128_get64(tmp.size)); | |
899 | } | |
900 | } | |
901 | ||
b8af1afb | 902 | static void address_space_update_topology_pass(AddressSpace *as, |
a9a0c06d PB |
903 | const FlatView *old_view, |
904 | const FlatView *new_view, | |
b8af1afb | 905 | bool adding) |
093bc2cd | 906 | { |
093bc2cd AK |
907 | unsigned iold, inew; |
908 | FlatRange *frold, *frnew; | |
093bc2cd AK |
909 | |
910 | /* Generate a symmetric difference of the old and new memory maps. | |
911 | * Kill ranges in the old map, and instantiate ranges in the new map. | |
912 | */ | |
913 | iold = inew = 0; | |
a9a0c06d PB |
914 | while (iold < old_view->nr || inew < new_view->nr) { |
915 | if (iold < old_view->nr) { | |
916 | frold = &old_view->ranges[iold]; | |
093bc2cd AK |
917 | } else { |
918 | frold = NULL; | |
919 | } | |
a9a0c06d PB |
920 | if (inew < new_view->nr) { |
921 | frnew = &new_view->ranges[inew]; | |
093bc2cd AK |
922 | } else { |
923 | frnew = NULL; | |
924 | } | |
925 | ||
926 | if (frold | |
927 | && (!frnew | |
08dafab4 AK |
928 | || int128_lt(frold->addr.start, frnew->addr.start) |
929 | || (int128_eq(frold->addr.start, frnew->addr.start) | |
093bc2cd | 930 | && !flatrange_equal(frold, frnew)))) { |
41a6e477 | 931 | /* In old but not in new, or in both but attributes changed. */ |
093bc2cd | 932 | |
b8af1afb | 933 | if (!adding) { |
3ac7d43a | 934 | flat_range_coalesced_io_del(frold, as); |
72e22d2f | 935 | MEMORY_LISTENER_UPDATE_REGION(frold, as, Reverse, region_del); |
b8af1afb AK |
936 | } |
937 | ||
093bc2cd AK |
938 | ++iold; |
939 | } else if (frold && frnew && flatrange_equal(frold, frnew)) { | |
41a6e477 | 940 | /* In both and unchanged (except logging may have changed) */ |
093bc2cd | 941 | |
4f826024 | 942 | if (adding) { |
50c1e149 | 943 | MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_nop); |
b2dfd71c PB |
944 | if (frnew->dirty_log_mask & ~frold->dirty_log_mask) { |
945 | MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, log_start, | |
946 | frold->dirty_log_mask, | |
947 | frnew->dirty_log_mask); | |
948 | } | |
949 | if (frold->dirty_log_mask & ~frnew->dirty_log_mask) { | |
950 | MEMORY_LISTENER_UPDATE_REGION(frnew, as, Reverse, log_stop, | |
951 | frold->dirty_log_mask, | |
952 | frnew->dirty_log_mask); | |
b8af1afb | 953 | } |
5a583347 AK |
954 | } |
955 | ||
093bc2cd AK |
956 | ++iold; |
957 | ++inew; | |
093bc2cd AK |
958 | } else { |
959 | /* In new */ | |
960 | ||
b8af1afb | 961 | if (adding) { |
72e22d2f | 962 | MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_add); |
3ac7d43a | 963 | flat_range_coalesced_io_add(frnew, as); |
b8af1afb AK |
964 | } |
965 | ||
093bc2cd AK |
966 | ++inew; |
967 | } | |
968 | } | |
b8af1afb AK |
969 | } |
970 | ||
967dc9b1 AK |
971 | static void flatviews_init(void) |
972 | { | |
092aa2fc AK |
973 | static FlatView *empty_view; |
974 | ||
967dc9b1 AK |
975 | if (flat_views) { |
976 | return; | |
977 | } | |
978 | ||
979 | flat_views = g_hash_table_new_full(g_direct_hash, g_direct_equal, NULL, | |
980 | (GDestroyNotify) flatview_unref); | |
092aa2fc AK |
981 | if (!empty_view) { |
982 | empty_view = generate_memory_topology(NULL); | |
983 | /* We keep it alive forever in the global variable. */ | |
984 | flatview_ref(empty_view); | |
985 | } else { | |
986 | g_hash_table_replace(flat_views, NULL, empty_view); | |
987 | flatview_ref(empty_view); | |
988 | } | |
967dc9b1 AK |
989 | } |
990 | ||
991 | static void flatviews_reset(void) | |
992 | { | |
993 | AddressSpace *as; | |
994 | ||
995 | if (flat_views) { | |
996 | g_hash_table_unref(flat_views); | |
997 | flat_views = NULL; | |
998 | } | |
999 | flatviews_init(); | |
1000 | ||
1001 | /* Render unique FVs */ | |
1002 | QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) { | |
1003 | MemoryRegion *physmr = memory_region_get_flatview_root(as->root); | |
1004 | ||
1005 | if (g_hash_table_lookup(flat_views, physmr)) { | |
1006 | continue; | |
1007 | } | |
1008 | ||
1009 | generate_memory_topology(physmr); | |
1010 | } | |
1011 | } | |
1012 | ||
1013 | static void address_space_set_flatview(AddressSpace *as) | |
b8af1afb | 1014 | { |
67ace39b | 1015 | FlatView *old_view = address_space_to_flatview(as); |
967dc9b1 AK |
1016 | MemoryRegion *physmr = memory_region_get_flatview_root(as->root); |
1017 | FlatView *new_view = g_hash_table_lookup(flat_views, physmr); | |
1018 | ||
1019 | assert(new_view); | |
1020 | ||
67ace39b AK |
1021 | if (old_view == new_view) { |
1022 | return; | |
1023 | } | |
1024 | ||
1025 | if (old_view) { | |
1026 | flatview_ref(old_view); | |
1027 | } | |
1028 | ||
967dc9b1 | 1029 | flatview_ref(new_view); |
9a62e24f AK |
1030 | |
1031 | if (!QTAILQ_EMPTY(&as->listeners)) { | |
67ace39b AK |
1032 | FlatView tmpview = { .nr = 0 }, *old_view2 = old_view; |
1033 | ||
1034 | if (!old_view2) { | |
1035 | old_view2 = &tmpview; | |
1036 | } | |
1037 | address_space_update_topology_pass(as, old_view2, new_view, false); | |
1038 | address_space_update_topology_pass(as, old_view2, new_view, true); | |
9a62e24f | 1039 | } |
b8af1afb | 1040 | |
374f2981 PB |
1041 | /* Writes are protected by the BQL. */ |
1042 | atomic_rcu_set(&as->current_map, new_view); | |
67ace39b AK |
1043 | if (old_view) { |
1044 | flatview_unref(old_view); | |
1045 | } | |
856d7245 PB |
1046 | |
1047 | /* Note that all the old MemoryRegions are still alive up to this | |
1048 | * point. This relieves most MemoryListeners from the need to | |
1049 | * ref/unref the MemoryRegions they get---unless they use them | |
1050 | * outside the iothread mutex, in which case precise reference | |
1051 | * counting is necessary. | |
1052 | */ | |
67ace39b AK |
1053 | if (old_view) { |
1054 | flatview_unref(old_view); | |
1055 | } | |
093bc2cd AK |
1056 | } |
1057 | ||
202fc01b AK |
1058 | static void address_space_update_topology(AddressSpace *as) |
1059 | { | |
1060 | MemoryRegion *physmr = memory_region_get_flatview_root(as->root); | |
1061 | ||
1062 | flatviews_init(); | |
1063 | if (!g_hash_table_lookup(flat_views, physmr)) { | |
1064 | generate_memory_topology(physmr); | |
1065 | } | |
1066 | address_space_set_flatview(as); | |
1067 | } | |
1068 | ||
4ef4db86 AK |
1069 | void memory_region_transaction_begin(void) |
1070 | { | |
bb880ded | 1071 | qemu_flush_coalesced_mmio_buffer(); |
4ef4db86 AK |
1072 | ++memory_region_transaction_depth; |
1073 | } | |
1074 | ||
1075 | void memory_region_transaction_commit(void) | |
1076 | { | |
0d673e36 AK |
1077 | AddressSpace *as; |
1078 | ||
4ef4db86 | 1079 | assert(memory_region_transaction_depth); |
8d04fb55 JK |
1080 | assert(qemu_mutex_iothread_locked()); |
1081 | ||
4ef4db86 | 1082 | --memory_region_transaction_depth; |
4dc56152 GA |
1083 | if (!memory_region_transaction_depth) { |
1084 | if (memory_region_update_pending) { | |
967dc9b1 AK |
1085 | flatviews_reset(); |
1086 | ||
4dc56152 | 1087 | MEMORY_LISTENER_CALL_GLOBAL(begin, Forward); |
02e2b95f | 1088 | |
4dc56152 | 1089 | QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) { |
967dc9b1 | 1090 | address_space_set_flatview(as); |
02218487 | 1091 | address_space_update_ioeventfds(as); |
4dc56152 | 1092 | } |
ade9c1aa | 1093 | memory_region_update_pending = false; |
0b152095 | 1094 | ioeventfd_update_pending = false; |
4dc56152 GA |
1095 | MEMORY_LISTENER_CALL_GLOBAL(commit, Forward); |
1096 | } else if (ioeventfd_update_pending) { | |
1097 | QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) { | |
1098 | address_space_update_ioeventfds(as); | |
1099 | } | |
ade9c1aa | 1100 | ioeventfd_update_pending = false; |
4dc56152 | 1101 | } |
4dc56152 | 1102 | } |
4ef4db86 AK |
1103 | } |
1104 | ||
545e92e0 AK |
1105 | static void memory_region_destructor_none(MemoryRegion *mr) |
1106 | { | |
1107 | } | |
1108 | ||
1109 | static void memory_region_destructor_ram(MemoryRegion *mr) | |
1110 | { | |
f1060c55 | 1111 | qemu_ram_free(mr->ram_block); |
545e92e0 AK |
1112 | } |
1113 | ||
b4fefef9 PC |
1114 | static bool memory_region_need_escape(char c) |
1115 | { | |
1116 | return c == '/' || c == '[' || c == '\\' || c == ']'; | |
1117 | } | |
1118 | ||
1119 | static char *memory_region_escape_name(const char *name) | |
1120 | { | |
1121 | const char *p; | |
1122 | char *escaped, *q; | |
1123 | uint8_t c; | |
1124 | size_t bytes = 0; | |
1125 | ||
1126 | for (p = name; *p; p++) { | |
1127 | bytes += memory_region_need_escape(*p) ? 4 : 1; | |
1128 | } | |
1129 | if (bytes == p - name) { | |
1130 | return g_memdup(name, bytes + 1); | |
1131 | } | |
1132 | ||
1133 | escaped = g_malloc(bytes + 1); | |
1134 | for (p = name, q = escaped; *p; p++) { | |
1135 | c = *p; | |
1136 | if (unlikely(memory_region_need_escape(c))) { | |
1137 | *q++ = '\\'; | |
1138 | *q++ = 'x'; | |
1139 | *q++ = "0123456789abcdef"[c >> 4]; | |
1140 | c = "0123456789abcdef"[c & 15]; | |
1141 | } | |
1142 | *q++ = c; | |
1143 | } | |
1144 | *q = 0; | |
1145 | return escaped; | |
1146 | } | |
1147 | ||
3df9d748 AK |
1148 | static void memory_region_do_init(MemoryRegion *mr, |
1149 | Object *owner, | |
1150 | const char *name, | |
1151 | uint64_t size) | |
093bc2cd | 1152 | { |
08dafab4 AK |
1153 | mr->size = int128_make64(size); |
1154 | if (size == UINT64_MAX) { | |
1155 | mr->size = int128_2_64(); | |
1156 | } | |
302fa283 | 1157 | mr->name = g_strdup(name); |
612263cf | 1158 | mr->owner = owner; |
58eaa217 | 1159 | mr->ram_block = NULL; |
b4fefef9 PC |
1160 | |
1161 | if (name) { | |
843ef73a PC |
1162 | char *escaped_name = memory_region_escape_name(name); |
1163 | char *name_array = g_strdup_printf("%s[*]", escaped_name); | |
612263cf PB |
1164 | |
1165 | if (!owner) { | |
1166 | owner = container_get(qdev_get_machine(), "/unattached"); | |
1167 | } | |
1168 | ||
843ef73a | 1169 | object_property_add_child(owner, name_array, OBJECT(mr), &error_abort); |
b4fefef9 | 1170 | object_unref(OBJECT(mr)); |
843ef73a PC |
1171 | g_free(name_array); |
1172 | g_free(escaped_name); | |
b4fefef9 PC |
1173 | } |
1174 | } | |
1175 | ||
3df9d748 AK |
1176 | void memory_region_init(MemoryRegion *mr, |
1177 | Object *owner, | |
1178 | const char *name, | |
1179 | uint64_t size) | |
1180 | { | |
1181 | object_initialize(mr, sizeof(*mr), TYPE_MEMORY_REGION); | |
1182 | memory_region_do_init(mr, owner, name, size); | |
1183 | } | |
1184 | ||
d7bce999 EB |
1185 | static void memory_region_get_addr(Object *obj, Visitor *v, const char *name, |
1186 | void *opaque, Error **errp) | |
409ddd01 PC |
1187 | { |
1188 | MemoryRegion *mr = MEMORY_REGION(obj); | |
1189 | uint64_t value = mr->addr; | |
1190 | ||
51e72bc1 | 1191 | visit_type_uint64(v, name, &value, errp); |
409ddd01 PC |
1192 | } |
1193 | ||
d7bce999 EB |
1194 | static void memory_region_get_container(Object *obj, Visitor *v, |
1195 | const char *name, void *opaque, | |
1196 | Error **errp) | |
409ddd01 PC |
1197 | { |
1198 | MemoryRegion *mr = MEMORY_REGION(obj); | |
1199 | gchar *path = (gchar *)""; | |
1200 | ||
1201 | if (mr->container) { | |
1202 | path = object_get_canonical_path(OBJECT(mr->container)); | |
1203 | } | |
51e72bc1 | 1204 | visit_type_str(v, name, &path, errp); |
409ddd01 PC |
1205 | if (mr->container) { |
1206 | g_free(path); | |
1207 | } | |
1208 | } | |
1209 | ||
1210 | static Object *memory_region_resolve_container(Object *obj, void *opaque, | |
1211 | const char *part) | |
1212 | { | |
1213 | MemoryRegion *mr = MEMORY_REGION(obj); | |
1214 | ||
1215 | return OBJECT(mr->container); | |
1216 | } | |
1217 | ||
d7bce999 EB |
1218 | static void memory_region_get_priority(Object *obj, Visitor *v, |
1219 | const char *name, void *opaque, | |
1220 | Error **errp) | |
d33382da PC |
1221 | { |
1222 | MemoryRegion *mr = MEMORY_REGION(obj); | |
1223 | int32_t value = mr->priority; | |
1224 | ||
51e72bc1 | 1225 | visit_type_int32(v, name, &value, errp); |
d33382da PC |
1226 | } |
1227 | ||
d7bce999 EB |
1228 | static void memory_region_get_size(Object *obj, Visitor *v, const char *name, |
1229 | void *opaque, Error **errp) | |
52aef7bb PC |
1230 | { |
1231 | MemoryRegion *mr = MEMORY_REGION(obj); | |
1232 | uint64_t value = memory_region_size(mr); | |
1233 | ||
51e72bc1 | 1234 | visit_type_uint64(v, name, &value, errp); |
52aef7bb PC |
1235 | } |
1236 | ||
b4fefef9 PC |
1237 | static void memory_region_initfn(Object *obj) |
1238 | { | |
1239 | MemoryRegion *mr = MEMORY_REGION(obj); | |
409ddd01 | 1240 | ObjectProperty *op; |
b4fefef9 PC |
1241 | |
1242 | mr->ops = &unassigned_mem_ops; | |
6bba19ba | 1243 | mr->enabled = true; |
5f9a5ea1 | 1244 | mr->romd_mode = true; |
196ea131 | 1245 | mr->global_locking = true; |
545e92e0 | 1246 | mr->destructor = memory_region_destructor_none; |
093bc2cd | 1247 | QTAILQ_INIT(&mr->subregions); |
093bc2cd | 1248 | QTAILQ_INIT(&mr->coalesced); |
409ddd01 PC |
1249 | |
1250 | op = object_property_add(OBJECT(mr), "container", | |
1251 | "link<" TYPE_MEMORY_REGION ">", | |
1252 | memory_region_get_container, | |
1253 | NULL, /* memory_region_set_container */ | |
1254 | NULL, NULL, &error_abort); | |
1255 | op->resolve = memory_region_resolve_container; | |
1256 | ||
1257 | object_property_add(OBJECT(mr), "addr", "uint64", | |
1258 | memory_region_get_addr, | |
1259 | NULL, /* memory_region_set_addr */ | |
1260 | NULL, NULL, &error_abort); | |
d33382da PC |
1261 | object_property_add(OBJECT(mr), "priority", "uint32", |
1262 | memory_region_get_priority, | |
1263 | NULL, /* memory_region_set_priority */ | |
1264 | NULL, NULL, &error_abort); | |
52aef7bb PC |
1265 | object_property_add(OBJECT(mr), "size", "uint64", |
1266 | memory_region_get_size, | |
1267 | NULL, /* memory_region_set_size, */ | |
1268 | NULL, NULL, &error_abort); | |
093bc2cd AK |
1269 | } |
1270 | ||
3df9d748 AK |
1271 | static void iommu_memory_region_initfn(Object *obj) |
1272 | { | |
1273 | MemoryRegion *mr = MEMORY_REGION(obj); | |
1274 | ||
1275 | mr->is_iommu = true; | |
1276 | } | |
1277 | ||
b018ddf6 PB |
1278 | static uint64_t unassigned_mem_read(void *opaque, hwaddr addr, |
1279 | unsigned size) | |
1280 | { | |
1281 | #ifdef DEBUG_UNASSIGNED | |
1282 | printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); | |
1283 | #endif | |
4917cf44 | 1284 | if (current_cpu != NULL) { |
dbea78a4 PM |
1285 | bool is_exec = current_cpu->mem_io_access_type == MMU_INST_FETCH; |
1286 | cpu_unassigned_access(current_cpu, addr, false, is_exec, 0, size); | |
c658b94f | 1287 | } |
68a7439a | 1288 | return 0; |
b018ddf6 PB |
1289 | } |
1290 | ||
1291 | static void unassigned_mem_write(void *opaque, hwaddr addr, | |
1292 | uint64_t val, unsigned size) | |
1293 | { | |
1294 | #ifdef DEBUG_UNASSIGNED | |
1295 | printf("Unassigned mem write " TARGET_FMT_plx " = 0x%"PRIx64"\n", addr, val); | |
1296 | #endif | |
4917cf44 AF |
1297 | if (current_cpu != NULL) { |
1298 | cpu_unassigned_access(current_cpu, addr, true, false, 0, size); | |
c658b94f | 1299 | } |
b018ddf6 PB |
1300 | } |
1301 | ||
d197063f | 1302 | static bool unassigned_mem_accepts(void *opaque, hwaddr addr, |
8372d383 PM |
1303 | unsigned size, bool is_write, |
1304 | MemTxAttrs attrs) | |
d197063f PB |
1305 | { |
1306 | return false; | |
1307 | } | |
1308 | ||
1309 | const MemoryRegionOps unassigned_mem_ops = { | |
1310 | .valid.accepts = unassigned_mem_accepts, | |
1311 | .endianness = DEVICE_NATIVE_ENDIAN, | |
1312 | }; | |
1313 | ||
4a2e242b AW |
1314 | static uint64_t memory_region_ram_device_read(void *opaque, |
1315 | hwaddr addr, unsigned size) | |
1316 | { | |
1317 | MemoryRegion *mr = opaque; | |
1318 | uint64_t data = (uint64_t)~0; | |
1319 | ||
1320 | switch (size) { | |
1321 | case 1: | |
1322 | data = *(uint8_t *)(mr->ram_block->host + addr); | |
1323 | break; | |
1324 | case 2: | |
1325 | data = *(uint16_t *)(mr->ram_block->host + addr); | |
1326 | break; | |
1327 | case 4: | |
1328 | data = *(uint32_t *)(mr->ram_block->host + addr); | |
1329 | break; | |
1330 | case 8: | |
1331 | data = *(uint64_t *)(mr->ram_block->host + addr); | |
1332 | break; | |
1333 | } | |
1334 | ||
1335 | trace_memory_region_ram_device_read(get_cpu_index(), mr, addr, data, size); | |
1336 | ||
1337 | return data; | |
1338 | } | |
1339 | ||
1340 | static void memory_region_ram_device_write(void *opaque, hwaddr addr, | |
1341 | uint64_t data, unsigned size) | |
1342 | { | |
1343 | MemoryRegion *mr = opaque; | |
1344 | ||
1345 | trace_memory_region_ram_device_write(get_cpu_index(), mr, addr, data, size); | |
1346 | ||
1347 | switch (size) { | |
1348 | case 1: | |
1349 | *(uint8_t *)(mr->ram_block->host + addr) = (uint8_t)data; | |
1350 | break; | |
1351 | case 2: | |
1352 | *(uint16_t *)(mr->ram_block->host + addr) = (uint16_t)data; | |
1353 | break; | |
1354 | case 4: | |
1355 | *(uint32_t *)(mr->ram_block->host + addr) = (uint32_t)data; | |
1356 | break; | |
1357 | case 8: | |
1358 | *(uint64_t *)(mr->ram_block->host + addr) = data; | |
1359 | break; | |
1360 | } | |
1361 | } | |
1362 | ||
1363 | static const MemoryRegionOps ram_device_mem_ops = { | |
1364 | .read = memory_region_ram_device_read, | |
1365 | .write = memory_region_ram_device_write, | |
c99a29e7 | 1366 | .endianness = DEVICE_HOST_ENDIAN, |
4a2e242b AW |
1367 | .valid = { |
1368 | .min_access_size = 1, | |
1369 | .max_access_size = 8, | |
1370 | .unaligned = true, | |
1371 | }, | |
1372 | .impl = { | |
1373 | .min_access_size = 1, | |
1374 | .max_access_size = 8, | |
1375 | .unaligned = true, | |
1376 | }, | |
1377 | }; | |
1378 | ||
d2702032 PB |
1379 | bool memory_region_access_valid(MemoryRegion *mr, |
1380 | hwaddr addr, | |
1381 | unsigned size, | |
6d7b9a6c PM |
1382 | bool is_write, |
1383 | MemTxAttrs attrs) | |
093bc2cd | 1384 | { |
a014ed07 PB |
1385 | int access_size_min, access_size_max; |
1386 | int access_size, i; | |
897fa7cf | 1387 | |
093bc2cd AK |
1388 | if (!mr->ops->valid.unaligned && (addr & (size - 1))) { |
1389 | return false; | |
1390 | } | |
1391 | ||
a014ed07 | 1392 | if (!mr->ops->valid.accepts) { |
093bc2cd AK |
1393 | return true; |
1394 | } | |
1395 | ||
a014ed07 PB |
1396 | access_size_min = mr->ops->valid.min_access_size; |
1397 | if (!mr->ops->valid.min_access_size) { | |
1398 | access_size_min = 1; | |
1399 | } | |
1400 | ||
1401 | access_size_max = mr->ops->valid.max_access_size; | |
1402 | if (!mr->ops->valid.max_access_size) { | |
1403 | access_size_max = 4; | |
1404 | } | |
1405 | ||
1406 | access_size = MAX(MIN(size, access_size_max), access_size_min); | |
1407 | for (i = 0; i < size; i += access_size) { | |
1408 | if (!mr->ops->valid.accepts(mr->opaque, addr + i, access_size, | |
8372d383 | 1409 | is_write, attrs)) { |
a014ed07 PB |
1410 | return false; |
1411 | } | |
093bc2cd | 1412 | } |
a014ed07 | 1413 | |
093bc2cd AK |
1414 | return true; |
1415 | } | |
1416 | ||
cc05c43a PM |
1417 | static MemTxResult memory_region_dispatch_read1(MemoryRegion *mr, |
1418 | hwaddr addr, | |
1419 | uint64_t *pval, | |
1420 | unsigned size, | |
1421 | MemTxAttrs attrs) | |
093bc2cd | 1422 | { |
cc05c43a | 1423 | *pval = 0; |
093bc2cd | 1424 | |
ce5d2f33 | 1425 | if (mr->ops->read) { |
cc05c43a PM |
1426 | return access_with_adjusted_size(addr, pval, size, |
1427 | mr->ops->impl.min_access_size, | |
1428 | mr->ops->impl.max_access_size, | |
1429 | memory_region_read_accessor, | |
1430 | mr, attrs); | |
62a0db94 | 1431 | } else { |
cc05c43a PM |
1432 | return access_with_adjusted_size(addr, pval, size, |
1433 | mr->ops->impl.min_access_size, | |
1434 | mr->ops->impl.max_access_size, | |
1435 | memory_region_read_with_attrs_accessor, | |
1436 | mr, attrs); | |
74901c3b | 1437 | } |
093bc2cd AK |
1438 | } |
1439 | ||
3b643495 PM |
1440 | MemTxResult memory_region_dispatch_read(MemoryRegion *mr, |
1441 | hwaddr addr, | |
1442 | uint64_t *pval, | |
1443 | unsigned size, | |
1444 | MemTxAttrs attrs) | |
a621f38d | 1445 | { |
cc05c43a PM |
1446 | MemTxResult r; |
1447 | ||
6d7b9a6c | 1448 | if (!memory_region_access_valid(mr, addr, size, false, attrs)) { |
791af8c8 | 1449 | *pval = unassigned_mem_read(mr, addr, size); |
cc05c43a | 1450 | return MEMTX_DECODE_ERROR; |
791af8c8 | 1451 | } |
a621f38d | 1452 | |
cc05c43a | 1453 | r = memory_region_dispatch_read1(mr, addr, pval, size, attrs); |
791af8c8 | 1454 | adjust_endianness(mr, pval, size); |
cc05c43a | 1455 | return r; |
a621f38d | 1456 | } |
093bc2cd | 1457 | |
8c56c1a5 PF |
1458 | /* Return true if an eventfd was signalled */ |
1459 | static bool memory_region_dispatch_write_eventfds(MemoryRegion *mr, | |
1460 | hwaddr addr, | |
1461 | uint64_t data, | |
1462 | unsigned size, | |
1463 | MemTxAttrs attrs) | |
1464 | { | |
1465 | MemoryRegionIoeventfd ioeventfd = { | |
1466 | .addr = addrrange_make(int128_make64(addr), int128_make64(size)), | |
1467 | .data = data, | |
1468 | }; | |
1469 | unsigned i; | |
1470 | ||
1471 | for (i = 0; i < mr->ioeventfd_nb; i++) { | |
1472 | ioeventfd.match_data = mr->ioeventfds[i].match_data; | |
1473 | ioeventfd.e = mr->ioeventfds[i].e; | |
1474 | ||
73bb753d | 1475 | if (memory_region_ioeventfd_equal(&ioeventfd, &mr->ioeventfds[i])) { |
8c56c1a5 PF |
1476 | event_notifier_set(ioeventfd.e); |
1477 | return true; | |
1478 | } | |
1479 | } | |
1480 | ||
1481 | return false; | |
1482 | } | |
1483 | ||
3b643495 PM |
1484 | MemTxResult memory_region_dispatch_write(MemoryRegion *mr, |
1485 | hwaddr addr, | |
1486 | uint64_t data, | |
1487 | unsigned size, | |
1488 | MemTxAttrs attrs) | |
a621f38d | 1489 | { |
6d7b9a6c | 1490 | if (!memory_region_access_valid(mr, addr, size, true, attrs)) { |
b018ddf6 | 1491 | unassigned_mem_write(mr, addr, data, size); |
cc05c43a | 1492 | return MEMTX_DECODE_ERROR; |
093bc2cd AK |
1493 | } |
1494 | ||
a621f38d AK |
1495 | adjust_endianness(mr, &data, size); |
1496 | ||
8c56c1a5 PF |
1497 | if ((!kvm_eventfds_enabled()) && |
1498 | memory_region_dispatch_write_eventfds(mr, addr, data, size, attrs)) { | |
1499 | return MEMTX_OK; | |
1500 | } | |
1501 | ||
ce5d2f33 | 1502 | if (mr->ops->write) { |
cc05c43a PM |
1503 | return access_with_adjusted_size(addr, &data, size, |
1504 | mr->ops->impl.min_access_size, | |
1505 | mr->ops->impl.max_access_size, | |
1506 | memory_region_write_accessor, mr, | |
1507 | attrs); | |
62a0db94 | 1508 | } else { |
cc05c43a PM |
1509 | return |
1510 | access_with_adjusted_size(addr, &data, size, | |
1511 | mr->ops->impl.min_access_size, | |
1512 | mr->ops->impl.max_access_size, | |
1513 | memory_region_write_with_attrs_accessor, | |
1514 | mr, attrs); | |
74901c3b | 1515 | } |
093bc2cd AK |
1516 | } |
1517 | ||
093bc2cd | 1518 | void memory_region_init_io(MemoryRegion *mr, |
2c9b15ca | 1519 | Object *owner, |
093bc2cd AK |
1520 | const MemoryRegionOps *ops, |
1521 | void *opaque, | |
1522 | const char *name, | |
1523 | uint64_t size) | |
1524 | { | |
2c9b15ca | 1525 | memory_region_init(mr, owner, name, size); |
6d6d2abf | 1526 | mr->ops = ops ? ops : &unassigned_mem_ops; |
093bc2cd | 1527 | mr->opaque = opaque; |
14a3c10a | 1528 | mr->terminates = true; |
093bc2cd AK |
1529 | } |
1530 | ||
1cfe48c1 PM |
1531 | void memory_region_init_ram_nomigrate(MemoryRegion *mr, |
1532 | Object *owner, | |
1533 | const char *name, | |
1534 | uint64_t size, | |
1535 | Error **errp) | |
06329cce MA |
1536 | { |
1537 | memory_region_init_ram_shared_nomigrate(mr, owner, name, size, false, errp); | |
1538 | } | |
1539 | ||
1540 | void memory_region_init_ram_shared_nomigrate(MemoryRegion *mr, | |
1541 | Object *owner, | |
1542 | const char *name, | |
1543 | uint64_t size, | |
1544 | bool share, | |
1545 | Error **errp) | |
093bc2cd | 1546 | { |
1cd3d492 | 1547 | Error *err = NULL; |
2c9b15ca | 1548 | memory_region_init(mr, owner, name, size); |
8ea9252a | 1549 | mr->ram = true; |
14a3c10a | 1550 | mr->terminates = true; |
545e92e0 | 1551 | mr->destructor = memory_region_destructor_ram; |
1cd3d492 | 1552 | mr->ram_block = qemu_ram_alloc(size, share, mr, &err); |
677e7805 | 1553 | mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0; |
1cd3d492 IM |
1554 | if (err) { |
1555 | mr->size = int128_zero(); | |
1556 | object_unparent(OBJECT(mr)); | |
1557 | error_propagate(errp, err); | |
1558 | } | |
0b183fc8 PB |
1559 | } |
1560 | ||
60786ef3 MT |
1561 | void memory_region_init_resizeable_ram(MemoryRegion *mr, |
1562 | Object *owner, | |
1563 | const char *name, | |
1564 | uint64_t size, | |
1565 | uint64_t max_size, | |
1566 | void (*resized)(const char*, | |
1567 | uint64_t length, | |
1568 | void *host), | |
1569 | Error **errp) | |
1570 | { | |
1cd3d492 | 1571 | Error *err = NULL; |
60786ef3 MT |
1572 | memory_region_init(mr, owner, name, size); |
1573 | mr->ram = true; | |
1574 | mr->terminates = true; | |
1575 | mr->destructor = memory_region_destructor_ram; | |
8e41fb63 | 1576 | mr->ram_block = qemu_ram_alloc_resizeable(size, max_size, resized, |
1cd3d492 | 1577 | mr, &err); |
677e7805 | 1578 | mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0; |
1cd3d492 IM |
1579 | if (err) { |
1580 | mr->size = int128_zero(); | |
1581 | object_unparent(OBJECT(mr)); | |
1582 | error_propagate(errp, err); | |
1583 | } | |
60786ef3 MT |
1584 | } |
1585 | ||
d5dbde46 | 1586 | #ifdef CONFIG_POSIX |
0b183fc8 PB |
1587 | void memory_region_init_ram_from_file(MemoryRegion *mr, |
1588 | struct Object *owner, | |
1589 | const char *name, | |
1590 | uint64_t size, | |
98376843 | 1591 | uint64_t align, |
cbfc0171 | 1592 | uint32_t ram_flags, |
7f56e740 PB |
1593 | const char *path, |
1594 | Error **errp) | |
0b183fc8 | 1595 | { |
1cd3d492 | 1596 | Error *err = NULL; |
0b183fc8 PB |
1597 | memory_region_init(mr, owner, name, size); |
1598 | mr->ram = true; | |
1599 | mr->terminates = true; | |
1600 | mr->destructor = memory_region_destructor_ram; | |
98376843 | 1601 | mr->align = align; |
1cd3d492 | 1602 | mr->ram_block = qemu_ram_alloc_from_file(size, mr, ram_flags, path, &err); |
677e7805 | 1603 | mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0; |
1cd3d492 IM |
1604 | if (err) { |
1605 | mr->size = int128_zero(); | |
1606 | object_unparent(OBJECT(mr)); | |
1607 | error_propagate(errp, err); | |
1608 | } | |
093bc2cd | 1609 | } |
fea617c5 MAL |
1610 | |
1611 | void memory_region_init_ram_from_fd(MemoryRegion *mr, | |
1612 | struct Object *owner, | |
1613 | const char *name, | |
1614 | uint64_t size, | |
1615 | bool share, | |
1616 | int fd, | |
1617 | Error **errp) | |
1618 | { | |
1cd3d492 | 1619 | Error *err = NULL; |
fea617c5 MAL |
1620 | memory_region_init(mr, owner, name, size); |
1621 | mr->ram = true; | |
1622 | mr->terminates = true; | |
1623 | mr->destructor = memory_region_destructor_ram; | |
cbfc0171 JH |
1624 | mr->ram_block = qemu_ram_alloc_from_fd(size, mr, |
1625 | share ? RAM_SHARED : 0, | |
1cd3d492 | 1626 | fd, &err); |
fea617c5 | 1627 | mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0; |
1cd3d492 IM |
1628 | if (err) { |
1629 | mr->size = int128_zero(); | |
1630 | object_unparent(OBJECT(mr)); | |
1631 | error_propagate(errp, err); | |
1632 | } | |
fea617c5 | 1633 | } |
0b183fc8 | 1634 | #endif |
093bc2cd AK |
1635 | |
1636 | void memory_region_init_ram_ptr(MemoryRegion *mr, | |
2c9b15ca | 1637 | Object *owner, |
093bc2cd AK |
1638 | const char *name, |
1639 | uint64_t size, | |
1640 | void *ptr) | |
1641 | { | |
2c9b15ca | 1642 | memory_region_init(mr, owner, name, size); |
8ea9252a | 1643 | mr->ram = true; |
14a3c10a | 1644 | mr->terminates = true; |
fc3e7665 | 1645 | mr->destructor = memory_region_destructor_ram; |
677e7805 | 1646 | mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0; |
ef701d7b HT |
1647 | |
1648 | /* qemu_ram_alloc_from_ptr cannot fail with ptr != NULL. */ | |
1649 | assert(ptr != NULL); | |
8e41fb63 | 1650 | mr->ram_block = qemu_ram_alloc_from_ptr(size, ptr, mr, &error_fatal); |
093bc2cd AK |
1651 | } |
1652 | ||
21e00fa5 AW |
1653 | void memory_region_init_ram_device_ptr(MemoryRegion *mr, |
1654 | Object *owner, | |
1655 | const char *name, | |
1656 | uint64_t size, | |
1657 | void *ptr) | |
e4dc3f59 | 1658 | { |
2ddb89b0 BS |
1659 | memory_region_init(mr, owner, name, size); |
1660 | mr->ram = true; | |
1661 | mr->terminates = true; | |
21e00fa5 | 1662 | mr->ram_device = true; |
4a2e242b AW |
1663 | mr->ops = &ram_device_mem_ops; |
1664 | mr->opaque = mr; | |
2ddb89b0 BS |
1665 | mr->destructor = memory_region_destructor_ram; |
1666 | mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0; | |
1667 | /* qemu_ram_alloc_from_ptr cannot fail with ptr != NULL. */ | |
1668 | assert(ptr != NULL); | |
1669 | mr->ram_block = qemu_ram_alloc_from_ptr(size, ptr, mr, &error_fatal); | |
e4dc3f59 ND |
1670 | } |
1671 | ||
093bc2cd | 1672 | void memory_region_init_alias(MemoryRegion *mr, |
2c9b15ca | 1673 | Object *owner, |
093bc2cd AK |
1674 | const char *name, |
1675 | MemoryRegion *orig, | |
a8170e5e | 1676 | hwaddr offset, |
093bc2cd AK |
1677 | uint64_t size) |
1678 | { | |
2c9b15ca | 1679 | memory_region_init(mr, owner, name, size); |
093bc2cd AK |
1680 | mr->alias = orig; |
1681 | mr->alias_offset = offset; | |
1682 | } | |
1683 | ||
b59821a9 PM |
1684 | void memory_region_init_rom_nomigrate(MemoryRegion *mr, |
1685 | struct Object *owner, | |
1686 | const char *name, | |
1687 | uint64_t size, | |
1688 | Error **errp) | |
a1777f7f | 1689 | { |
1cd3d492 | 1690 | Error *err = NULL; |
a1777f7f PM |
1691 | memory_region_init(mr, owner, name, size); |
1692 | mr->ram = true; | |
1693 | mr->readonly = true; | |
1694 | mr->terminates = true; | |
1695 | mr->destructor = memory_region_destructor_ram; | |
1cd3d492 | 1696 | mr->ram_block = qemu_ram_alloc(size, false, mr, &err); |
a1777f7f | 1697 | mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0; |
1cd3d492 IM |
1698 | if (err) { |
1699 | mr->size = int128_zero(); | |
1700 | object_unparent(OBJECT(mr)); | |
1701 | error_propagate(errp, err); | |
1702 | } | |
a1777f7f PM |
1703 | } |
1704 | ||
b59821a9 PM |
1705 | void memory_region_init_rom_device_nomigrate(MemoryRegion *mr, |
1706 | Object *owner, | |
1707 | const MemoryRegionOps *ops, | |
1708 | void *opaque, | |
1709 | const char *name, | |
1710 | uint64_t size, | |
1711 | Error **errp) | |
d0a9b5bc | 1712 | { |
1cd3d492 | 1713 | Error *err = NULL; |
39e0b03d | 1714 | assert(ops); |
2c9b15ca | 1715 | memory_region_init(mr, owner, name, size); |
7bc2b9cd | 1716 | mr->ops = ops; |
75f5941c | 1717 | mr->opaque = opaque; |
d0a9b5bc | 1718 | mr->terminates = true; |
75c578dc | 1719 | mr->rom_device = true; |
58268c8d | 1720 | mr->destructor = memory_region_destructor_ram; |
1cd3d492 IM |
1721 | mr->ram_block = qemu_ram_alloc(size, false, mr, &err); |
1722 | if (err) { | |
1723 | mr->size = int128_zero(); | |
1724 | object_unparent(OBJECT(mr)); | |
1725 | error_propagate(errp, err); | |
1726 | } | |
d0a9b5bc AK |
1727 | } |
1728 | ||
1221a474 AK |
1729 | void memory_region_init_iommu(void *_iommu_mr, |
1730 | size_t instance_size, | |
1731 | const char *mrtypename, | |
2c9b15ca | 1732 | Object *owner, |
30951157 AK |
1733 | const char *name, |
1734 | uint64_t size) | |
1735 | { | |
1221a474 | 1736 | struct IOMMUMemoryRegion *iommu_mr; |
3df9d748 AK |
1737 | struct MemoryRegion *mr; |
1738 | ||
1221a474 AK |
1739 | object_initialize(_iommu_mr, instance_size, mrtypename); |
1740 | mr = MEMORY_REGION(_iommu_mr); | |
3df9d748 AK |
1741 | memory_region_do_init(mr, owner, name, size); |
1742 | iommu_mr = IOMMU_MEMORY_REGION(mr); | |
30951157 | 1743 | mr->terminates = true; /* then re-forwards */ |
3df9d748 AK |
1744 | QLIST_INIT(&iommu_mr->iommu_notify); |
1745 | iommu_mr->iommu_notify_flags = IOMMU_NOTIFIER_NONE; | |
30951157 AK |
1746 | } |
1747 | ||
b4fefef9 | 1748 | static void memory_region_finalize(Object *obj) |
093bc2cd | 1749 | { |
b4fefef9 PC |
1750 | MemoryRegion *mr = MEMORY_REGION(obj); |
1751 | ||
2e2b8eb7 PB |
1752 | assert(!mr->container); |
1753 | ||
1754 | /* We know the region is not visible in any address space (it | |
1755 | * does not have a container and cannot be a root either because | |
1756 | * it has no references, so we can blindly clear mr->enabled. | |
1757 | * memory_region_set_enabled instead could trigger a transaction | |
1758 | * and cause an infinite loop. | |
1759 | */ | |
1760 | mr->enabled = false; | |
1761 | memory_region_transaction_begin(); | |
1762 | while (!QTAILQ_EMPTY(&mr->subregions)) { | |
1763 | MemoryRegion *subregion = QTAILQ_FIRST(&mr->subregions); | |
1764 | memory_region_del_subregion(mr, subregion); | |
1765 | } | |
1766 | memory_region_transaction_commit(); | |
1767 | ||
545e92e0 | 1768 | mr->destructor(mr); |
093bc2cd | 1769 | memory_region_clear_coalescing(mr); |
302fa283 | 1770 | g_free((char *)mr->name); |
7267c094 | 1771 | g_free(mr->ioeventfds); |
093bc2cd AK |
1772 | } |
1773 | ||
803c0816 PB |
1774 | Object *memory_region_owner(MemoryRegion *mr) |
1775 | { | |
22a893e4 PB |
1776 | Object *obj = OBJECT(mr); |
1777 | return obj->parent; | |
803c0816 PB |
1778 | } |
1779 | ||
46637be2 PB |
1780 | void memory_region_ref(MemoryRegion *mr) |
1781 | { | |
22a893e4 PB |
1782 | /* MMIO callbacks most likely will access data that belongs |
1783 | * to the owner, hence the need to ref/unref the owner whenever | |
1784 | * the memory region is in use. | |
1785 | * | |
1786 | * The memory region is a child of its owner. As long as the | |
1787 | * owner doesn't call unparent itself on the memory region, | |
1788 | * ref-ing the owner will also keep the memory region alive. | |
612263cf PB |
1789 | * Memory regions without an owner are supposed to never go away; |
1790 | * we do not ref/unref them because it slows down DMA sensibly. | |
22a893e4 | 1791 | */ |
612263cf PB |
1792 | if (mr && mr->owner) { |
1793 | object_ref(mr->owner); | |
46637be2 PB |
1794 | } |
1795 | } | |
1796 | ||
1797 | void memory_region_unref(MemoryRegion *mr) | |
1798 | { | |
612263cf PB |
1799 | if (mr && mr->owner) { |
1800 | object_unref(mr->owner); | |
46637be2 PB |
1801 | } |
1802 | } | |
1803 | ||
093bc2cd AK |
1804 | uint64_t memory_region_size(MemoryRegion *mr) |
1805 | { | |
08dafab4 AK |
1806 | if (int128_eq(mr->size, int128_2_64())) { |
1807 | return UINT64_MAX; | |
1808 | } | |
1809 | return int128_get64(mr->size); | |
093bc2cd AK |
1810 | } |
1811 | ||
5d546d4b | 1812 | const char *memory_region_name(const MemoryRegion *mr) |
8991c79b | 1813 | { |
d1dd32af PC |
1814 | if (!mr->name) { |
1815 | ((MemoryRegion *)mr)->name = | |
1816 | object_get_canonical_path_component(OBJECT(mr)); | |
1817 | } | |
302fa283 | 1818 | return mr->name; |
8991c79b AK |
1819 | } |
1820 | ||
21e00fa5 | 1821 | bool memory_region_is_ram_device(MemoryRegion *mr) |
e4dc3f59 | 1822 | { |
21e00fa5 | 1823 | return mr->ram_device; |
e4dc3f59 ND |
1824 | } |
1825 | ||
2d1a35be | 1826 | uint8_t memory_region_get_dirty_log_mask(MemoryRegion *mr) |
55043ba3 | 1827 | { |
6f6a5ef3 | 1828 | uint8_t mask = mr->dirty_log_mask; |
adaad61c | 1829 | if (global_dirty_log && mr->ram_block) { |
6f6a5ef3 PB |
1830 | mask |= (1 << DIRTY_MEMORY_MIGRATION); |
1831 | } | |
1832 | return mask; | |
55043ba3 AK |
1833 | } |
1834 | ||
2d1a35be PB |
1835 | bool memory_region_is_logging(MemoryRegion *mr, uint8_t client) |
1836 | { | |
1837 | return memory_region_get_dirty_log_mask(mr) & (1 << client); | |
1838 | } | |
1839 | ||
3df9d748 | 1840 | static void memory_region_update_iommu_notify_flags(IOMMUMemoryRegion *iommu_mr) |
5bf3d319 PX |
1841 | { |
1842 | IOMMUNotifierFlag flags = IOMMU_NOTIFIER_NONE; | |
1843 | IOMMUNotifier *iommu_notifier; | |
1221a474 | 1844 | IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr); |
5bf3d319 | 1845 | |
3df9d748 | 1846 | IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) { |
5bf3d319 PX |
1847 | flags |= iommu_notifier->notifier_flags; |
1848 | } | |
1849 | ||
1221a474 AK |
1850 | if (flags != iommu_mr->iommu_notify_flags && imrc->notify_flag_changed) { |
1851 | imrc->notify_flag_changed(iommu_mr, | |
1852 | iommu_mr->iommu_notify_flags, | |
1853 | flags); | |
5bf3d319 PX |
1854 | } |
1855 | ||
3df9d748 | 1856 | iommu_mr->iommu_notify_flags = flags; |
5bf3d319 PX |
1857 | } |
1858 | ||
cdb30812 PX |
1859 | void memory_region_register_iommu_notifier(MemoryRegion *mr, |
1860 | IOMMUNotifier *n) | |
06866575 | 1861 | { |
3df9d748 AK |
1862 | IOMMUMemoryRegion *iommu_mr; |
1863 | ||
efcd38c5 JW |
1864 | if (mr->alias) { |
1865 | memory_region_register_iommu_notifier(mr->alias, n); | |
1866 | return; | |
1867 | } | |
1868 | ||
cdb30812 | 1869 | /* We need to register for at least one bitfield */ |
3df9d748 | 1870 | iommu_mr = IOMMU_MEMORY_REGION(mr); |
cdb30812 | 1871 | assert(n->notifier_flags != IOMMU_NOTIFIER_NONE); |
698feb5e | 1872 | assert(n->start <= n->end); |
cb1efcf4 PM |
1873 | assert(n->iommu_idx >= 0 && |
1874 | n->iommu_idx < memory_region_iommu_num_indexes(iommu_mr)); | |
1875 | ||
3df9d748 AK |
1876 | QLIST_INSERT_HEAD(&iommu_mr->iommu_notify, n, node); |
1877 | memory_region_update_iommu_notify_flags(iommu_mr); | |
06866575 DG |
1878 | } |
1879 | ||
3df9d748 | 1880 | uint64_t memory_region_iommu_get_min_page_size(IOMMUMemoryRegion *iommu_mr) |
a788f227 | 1881 | { |
1221a474 AK |
1882 | IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr); |
1883 | ||
1884 | if (imrc->get_min_page_size) { | |
1885 | return imrc->get_min_page_size(iommu_mr); | |
f682e9c2 AK |
1886 | } |
1887 | return TARGET_PAGE_SIZE; | |
1888 | } | |
1889 | ||
3df9d748 | 1890 | void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n) |
f682e9c2 | 1891 | { |
3df9d748 | 1892 | MemoryRegion *mr = MEMORY_REGION(iommu_mr); |
1221a474 | 1893 | IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr); |
f682e9c2 | 1894 | hwaddr addr, granularity; |
a788f227 DG |
1895 | IOMMUTLBEntry iotlb; |
1896 | ||
faa362e3 | 1897 | /* If the IOMMU has its own replay callback, override */ |
1221a474 AK |
1898 | if (imrc->replay) { |
1899 | imrc->replay(iommu_mr, n); | |
faa362e3 PX |
1900 | return; |
1901 | } | |
1902 | ||
3df9d748 | 1903 | granularity = memory_region_iommu_get_min_page_size(iommu_mr); |
f682e9c2 | 1904 | |
a788f227 | 1905 | for (addr = 0; addr < memory_region_size(mr); addr += granularity) { |
2c91bcf2 | 1906 | iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE, n->iommu_idx); |
a788f227 DG |
1907 | if (iotlb.perm != IOMMU_NONE) { |
1908 | n->notify(n, &iotlb); | |
1909 | } | |
1910 | ||
1911 | /* if (2^64 - MR size) < granularity, it's possible to get an | |
1912 | * infinite loop here. This should catch such a wraparound */ | |
1913 | if ((addr + granularity) < addr) { | |
1914 | break; | |
1915 | } | |
1916 | } | |
1917 | } | |
1918 | ||
3df9d748 | 1919 | void memory_region_iommu_replay_all(IOMMUMemoryRegion *iommu_mr) |
de472e4a PX |
1920 | { |
1921 | IOMMUNotifier *notifier; | |
1922 | ||
3df9d748 AK |
1923 | IOMMU_NOTIFIER_FOREACH(notifier, iommu_mr) { |
1924 | memory_region_iommu_replay(iommu_mr, notifier); | |
de472e4a PX |
1925 | } |
1926 | } | |
1927 | ||
cdb30812 PX |
1928 | void memory_region_unregister_iommu_notifier(MemoryRegion *mr, |
1929 | IOMMUNotifier *n) | |
06866575 | 1930 | { |
3df9d748 AK |
1931 | IOMMUMemoryRegion *iommu_mr; |
1932 | ||
efcd38c5 JW |
1933 | if (mr->alias) { |
1934 | memory_region_unregister_iommu_notifier(mr->alias, n); | |
1935 | return; | |
1936 | } | |
cdb30812 | 1937 | QLIST_REMOVE(n, node); |
3df9d748 AK |
1938 | iommu_mr = IOMMU_MEMORY_REGION(mr); |
1939 | memory_region_update_iommu_notify_flags(iommu_mr); | |
06866575 DG |
1940 | } |
1941 | ||
bd2bfa4c PX |
1942 | void memory_region_notify_one(IOMMUNotifier *notifier, |
1943 | IOMMUTLBEntry *entry) | |
06866575 | 1944 | { |
cdb30812 PX |
1945 | IOMMUNotifierFlag request_flags; |
1946 | ||
bd2bfa4c PX |
1947 | /* |
1948 | * Skip the notification if the notification does not overlap | |
1949 | * with registered range. | |
1950 | */ | |
b021d1c0 | 1951 | if (notifier->start > entry->iova + entry->addr_mask || |
bd2bfa4c PX |
1952 | notifier->end < entry->iova) { |
1953 | return; | |
1954 | } | |
cdb30812 | 1955 | |
bd2bfa4c | 1956 | if (entry->perm & IOMMU_RW) { |
cdb30812 PX |
1957 | request_flags = IOMMU_NOTIFIER_MAP; |
1958 | } else { | |
1959 | request_flags = IOMMU_NOTIFIER_UNMAP; | |
1960 | } | |
1961 | ||
bd2bfa4c PX |
1962 | if (notifier->notifier_flags & request_flags) { |
1963 | notifier->notify(notifier, entry); | |
1964 | } | |
1965 | } | |
1966 | ||
3df9d748 | 1967 | void memory_region_notify_iommu(IOMMUMemoryRegion *iommu_mr, |
cb1efcf4 | 1968 | int iommu_idx, |
bd2bfa4c PX |
1969 | IOMMUTLBEntry entry) |
1970 | { | |
1971 | IOMMUNotifier *iommu_notifier; | |
1972 | ||
3df9d748 | 1973 | assert(memory_region_is_iommu(MEMORY_REGION(iommu_mr))); |
bd2bfa4c | 1974 | |
3df9d748 | 1975 | IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) { |
cb1efcf4 PM |
1976 | if (iommu_notifier->iommu_idx == iommu_idx) { |
1977 | memory_region_notify_one(iommu_notifier, &entry); | |
1978 | } | |
cdb30812 | 1979 | } |
06866575 DG |
1980 | } |
1981 | ||
f1334de6 AK |
1982 | int memory_region_iommu_get_attr(IOMMUMemoryRegion *iommu_mr, |
1983 | enum IOMMUMemoryRegionAttr attr, | |
1984 | void *data) | |
1985 | { | |
1986 | IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr); | |
1987 | ||
1988 | if (!imrc->get_attr) { | |
1989 | return -EINVAL; | |
1990 | } | |
1991 | ||
1992 | return imrc->get_attr(iommu_mr, attr, data); | |
1993 | } | |
1994 | ||
21f40209 PM |
1995 | int memory_region_iommu_attrs_to_index(IOMMUMemoryRegion *iommu_mr, |
1996 | MemTxAttrs attrs) | |
1997 | { | |
1998 | IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr); | |
1999 | ||
2000 | if (!imrc->attrs_to_index) { | |
2001 | return 0; | |
2002 | } | |
2003 | ||
2004 | return imrc->attrs_to_index(iommu_mr, attrs); | |
2005 | } | |
2006 | ||
2007 | int memory_region_iommu_num_indexes(IOMMUMemoryRegion *iommu_mr) | |
2008 | { | |
2009 | IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr); | |
2010 | ||
2011 | if (!imrc->num_indexes) { | |
2012 | return 1; | |
2013 | } | |
2014 | ||
2015 | return imrc->num_indexes(iommu_mr); | |
2016 | } | |
2017 | ||
093bc2cd AK |
2018 | void memory_region_set_log(MemoryRegion *mr, bool log, unsigned client) |
2019 | { | |
5a583347 | 2020 | uint8_t mask = 1 << client; |
deb809ed | 2021 | uint8_t old_logging; |
5a583347 | 2022 | |
dbddac6d | 2023 | assert(client == DIRTY_MEMORY_VGA); |
deb809ed PB |
2024 | old_logging = mr->vga_logging_count; |
2025 | mr->vga_logging_count += log ? 1 : -1; | |
2026 | if (!!old_logging == !!mr->vga_logging_count) { | |
2027 | return; | |
2028 | } | |
2029 | ||
59023ef4 | 2030 | memory_region_transaction_begin(); |
5a583347 | 2031 | mr->dirty_log_mask = (mr->dirty_log_mask & ~mask) | (log * mask); |
22bde714 | 2032 | memory_region_update_pending |= mr->enabled; |
59023ef4 | 2033 | memory_region_transaction_commit(); |
093bc2cd AK |
2034 | } |
2035 | ||
a8170e5e AK |
2036 | void memory_region_set_dirty(MemoryRegion *mr, hwaddr addr, |
2037 | hwaddr size) | |
093bc2cd | 2038 | { |
8e41fb63 FZ |
2039 | assert(mr->ram_block); |
2040 | cpu_physical_memory_set_dirty_range(memory_region_get_ram_addr(mr) + addr, | |
2041 | size, | |
58d2707e | 2042 | memory_region_get_dirty_log_mask(mr)); |
093bc2cd AK |
2043 | } |
2044 | ||
0fe1eca7 | 2045 | static void memory_region_sync_dirty_bitmap(MemoryRegion *mr) |
093bc2cd | 2046 | { |
0a752eee | 2047 | MemoryListener *listener; |
0d673e36 | 2048 | AddressSpace *as; |
0a752eee | 2049 | FlatView *view; |
5a583347 AK |
2050 | FlatRange *fr; |
2051 | ||
0a752eee PB |
2052 | /* If the same address space has multiple log_sync listeners, we |
2053 | * visit that address space's FlatView multiple times. But because | |
2054 | * log_sync listeners are rare, it's still cheaper than walking each | |
2055 | * address space once. | |
2056 | */ | |
2057 | QTAILQ_FOREACH(listener, &memory_listeners, link) { | |
2058 | if (!listener->log_sync) { | |
2059 | continue; | |
2060 | } | |
2061 | as = listener->address_space; | |
2062 | view = address_space_get_flatview(as); | |
99e86347 | 2063 | FOR_EACH_FLAT_RANGE(fr, view) { |
3ebb1817 | 2064 | if (fr->dirty_log_mask && (!mr || fr->mr == mr)) { |
16620684 | 2065 | MemoryRegionSection mrs = section_from_flat_range(fr, view); |
0a752eee | 2066 | listener->log_sync(listener, &mrs); |
0d673e36 | 2067 | } |
5a583347 | 2068 | } |
856d7245 | 2069 | flatview_unref(view); |
5a583347 | 2070 | } |
093bc2cd AK |
2071 | } |
2072 | ||
077874e0 PX |
2073 | void memory_region_clear_dirty_bitmap(MemoryRegion *mr, hwaddr start, |
2074 | hwaddr len) | |
2075 | { | |
2076 | MemoryRegionSection mrs; | |
2077 | MemoryListener *listener; | |
2078 | AddressSpace *as; | |
2079 | FlatView *view; | |
2080 | FlatRange *fr; | |
2081 | hwaddr sec_start, sec_end, sec_size; | |
2082 | ||
2083 | QTAILQ_FOREACH(listener, &memory_listeners, link) { | |
2084 | if (!listener->log_clear) { | |
2085 | continue; | |
2086 | } | |
2087 | as = listener->address_space; | |
2088 | view = address_space_get_flatview(as); | |
2089 | FOR_EACH_FLAT_RANGE(fr, view) { | |
2090 | if (!fr->dirty_log_mask || fr->mr != mr) { | |
2091 | /* | |
2092 | * Clear dirty bitmap operation only applies to those | |
2093 | * regions whose dirty logging is at least enabled | |
2094 | */ | |
2095 | continue; | |
2096 | } | |
2097 | ||
2098 | mrs = section_from_flat_range(fr, view); | |
2099 | ||
2100 | sec_start = MAX(mrs.offset_within_region, start); | |
2101 | sec_end = mrs.offset_within_region + int128_get64(mrs.size); | |
2102 | sec_end = MIN(sec_end, start + len); | |
2103 | ||
2104 | if (sec_start >= sec_end) { | |
2105 | /* | |
2106 | * If this memory region section has no intersection | |
2107 | * with the requested range, skip. | |
2108 | */ | |
2109 | continue; | |
2110 | } | |
2111 | ||
2112 | /* Valid case; shrink the section if needed */ | |
2113 | mrs.offset_within_address_space += | |
2114 | sec_start - mrs.offset_within_region; | |
2115 | mrs.offset_within_region = sec_start; | |
2116 | sec_size = sec_end - sec_start; | |
2117 | mrs.size = int128_make64(sec_size); | |
2118 | listener->log_clear(listener, &mrs); | |
2119 | } | |
2120 | flatview_unref(view); | |
2121 | } | |
2122 | } | |
2123 | ||
0fe1eca7 PB |
2124 | DirtyBitmapSnapshot *memory_region_snapshot_and_clear_dirty(MemoryRegion *mr, |
2125 | hwaddr addr, | |
2126 | hwaddr size, | |
2127 | unsigned client) | |
2128 | { | |
2129 | assert(mr->ram_block); | |
2130 | memory_region_sync_dirty_bitmap(mr); | |
5dea4079 | 2131 | return cpu_physical_memory_snapshot_and_clear_dirty(mr, addr, size, client); |
0fe1eca7 PB |
2132 | } |
2133 | ||
2134 | bool memory_region_snapshot_get_dirty(MemoryRegion *mr, DirtyBitmapSnapshot *snap, | |
2135 | hwaddr addr, hwaddr size) | |
2136 | { | |
2137 | assert(mr->ram_block); | |
2138 | return cpu_physical_memory_snapshot_get_dirty(snap, | |
2139 | memory_region_get_ram_addr(mr) + addr, size); | |
2140 | } | |
2141 | ||
093bc2cd AK |
2142 | void memory_region_set_readonly(MemoryRegion *mr, bool readonly) |
2143 | { | |
fb1cd6f9 | 2144 | if (mr->readonly != readonly) { |
59023ef4 | 2145 | memory_region_transaction_begin(); |
fb1cd6f9 | 2146 | mr->readonly = readonly; |
22bde714 | 2147 | memory_region_update_pending |= mr->enabled; |
59023ef4 | 2148 | memory_region_transaction_commit(); |
fb1cd6f9 | 2149 | } |
093bc2cd AK |
2150 | } |
2151 | ||
c26763f8 MAL |
2152 | void memory_region_set_nonvolatile(MemoryRegion *mr, bool nonvolatile) |
2153 | { | |
2154 | if (mr->nonvolatile != nonvolatile) { | |
2155 | memory_region_transaction_begin(); | |
2156 | mr->nonvolatile = nonvolatile; | |
2157 | memory_region_update_pending |= mr->enabled; | |
2158 | memory_region_transaction_commit(); | |
2159 | } | |
2160 | } | |
2161 | ||
5f9a5ea1 | 2162 | void memory_region_rom_device_set_romd(MemoryRegion *mr, bool romd_mode) |
d0a9b5bc | 2163 | { |
5f9a5ea1 | 2164 | if (mr->romd_mode != romd_mode) { |
59023ef4 | 2165 | memory_region_transaction_begin(); |
5f9a5ea1 | 2166 | mr->romd_mode = romd_mode; |
22bde714 | 2167 | memory_region_update_pending |= mr->enabled; |
59023ef4 | 2168 | memory_region_transaction_commit(); |
d0a9b5bc AK |
2169 | } |
2170 | } | |
2171 | ||
a8170e5e AK |
2172 | void memory_region_reset_dirty(MemoryRegion *mr, hwaddr addr, |
2173 | hwaddr size, unsigned client) | |
093bc2cd | 2174 | { |
8e41fb63 FZ |
2175 | assert(mr->ram_block); |
2176 | cpu_physical_memory_test_and_clear_dirty( | |
2177 | memory_region_get_ram_addr(mr) + addr, size, client); | |
093bc2cd AK |
2178 | } |
2179 | ||
a35ba7be PB |
2180 | int memory_region_get_fd(MemoryRegion *mr) |
2181 | { | |
4ff87573 PB |
2182 | int fd; |
2183 | ||
2184 | rcu_read_lock(); | |
2185 | while (mr->alias) { | |
2186 | mr = mr->alias; | |
a35ba7be | 2187 | } |
4ff87573 PB |
2188 | fd = mr->ram_block->fd; |
2189 | rcu_read_unlock(); | |
a35ba7be | 2190 | |
4ff87573 PB |
2191 | return fd; |
2192 | } | |
a35ba7be | 2193 | |
093bc2cd AK |
2194 | void *memory_region_get_ram_ptr(MemoryRegion *mr) |
2195 | { | |
49b24afc PB |
2196 | void *ptr; |
2197 | uint64_t offset = 0; | |
093bc2cd | 2198 | |
49b24afc PB |
2199 | rcu_read_lock(); |
2200 | while (mr->alias) { | |
2201 | offset += mr->alias_offset; | |
2202 | mr = mr->alias; | |
2203 | } | |
8e41fb63 | 2204 | assert(mr->ram_block); |
0878d0e1 | 2205 | ptr = qemu_map_ram_ptr(mr->ram_block, offset); |
49b24afc | 2206 | rcu_read_unlock(); |
093bc2cd | 2207 | |
0878d0e1 | 2208 | return ptr; |
093bc2cd AK |
2209 | } |
2210 | ||
07bdaa41 PB |
2211 | MemoryRegion *memory_region_from_host(void *ptr, ram_addr_t *offset) |
2212 | { | |
2213 | RAMBlock *block; | |
2214 | ||
2215 | block = qemu_ram_block_from_host(ptr, false, offset); | |
2216 | if (!block) { | |
2217 | return NULL; | |
2218 | } | |
2219 | ||
2220 | return block->mr; | |
2221 | } | |
2222 | ||
7ebb2745 FZ |
2223 | ram_addr_t memory_region_get_ram_addr(MemoryRegion *mr) |
2224 | { | |
2225 | return mr->ram_block ? mr->ram_block->offset : RAM_ADDR_INVALID; | |
2226 | } | |
2227 | ||
37d7c084 PB |
2228 | void memory_region_ram_resize(MemoryRegion *mr, ram_addr_t newsize, Error **errp) |
2229 | { | |
8e41fb63 | 2230 | assert(mr->ram_block); |
37d7c084 | 2231 | |
fa53a0e5 | 2232 | qemu_ram_resize(mr->ram_block, newsize, errp); |
37d7c084 PB |
2233 | } |
2234 | ||
0d673e36 | 2235 | static void memory_region_update_coalesced_range_as(MemoryRegion *mr, AddressSpace *as) |
093bc2cd | 2236 | { |
99e86347 | 2237 | FlatView *view; |
093bc2cd | 2238 | FlatRange *fr; |
093bc2cd | 2239 | |
856d7245 | 2240 | view = address_space_get_flatview(as); |
99e86347 | 2241 | FOR_EACH_FLAT_RANGE(fr, view) { |
093bc2cd | 2242 | if (fr->mr == mr) { |
909bf763 PB |
2243 | flat_range_coalesced_io_del(fr, as); |
2244 | flat_range_coalesced_io_add(fr, as); | |
093bc2cd AK |
2245 | } |
2246 | } | |
856d7245 | 2247 | flatview_unref(view); |
093bc2cd AK |
2248 | } |
2249 | ||
0d673e36 AK |
2250 | static void memory_region_update_coalesced_range(MemoryRegion *mr) |
2251 | { | |
2252 | AddressSpace *as; | |
2253 | ||
2254 | QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) { | |
2255 | memory_region_update_coalesced_range_as(mr, as); | |
2256 | } | |
2257 | } | |
2258 | ||
093bc2cd AK |
2259 | void memory_region_set_coalescing(MemoryRegion *mr) |
2260 | { | |
2261 | memory_region_clear_coalescing(mr); | |
08dafab4 | 2262 | memory_region_add_coalescing(mr, 0, int128_get64(mr->size)); |
093bc2cd AK |
2263 | } |
2264 | ||
2265 | void memory_region_add_coalescing(MemoryRegion *mr, | |
a8170e5e | 2266 | hwaddr offset, |
093bc2cd AK |
2267 | uint64_t size) |
2268 | { | |
7267c094 | 2269 | CoalescedMemoryRange *cmr = g_malloc(sizeof(*cmr)); |
093bc2cd | 2270 | |
08dafab4 | 2271 | cmr->addr = addrrange_make(int128_make64(offset), int128_make64(size)); |
093bc2cd AK |
2272 | QTAILQ_INSERT_TAIL(&mr->coalesced, cmr, link); |
2273 | memory_region_update_coalesced_range(mr); | |
d410515e | 2274 | memory_region_set_flush_coalesced(mr); |
093bc2cd AK |
2275 | } |
2276 | ||
2277 | void memory_region_clear_coalescing(MemoryRegion *mr) | |
2278 | { | |
2279 | CoalescedMemoryRange *cmr; | |
ab5b3db5 | 2280 | bool updated = false; |
093bc2cd | 2281 | |
d410515e JK |
2282 | qemu_flush_coalesced_mmio_buffer(); |
2283 | mr->flush_coalesced_mmio = false; | |
2284 | ||
093bc2cd AK |
2285 | while (!QTAILQ_EMPTY(&mr->coalesced)) { |
2286 | cmr = QTAILQ_FIRST(&mr->coalesced); | |
2287 | QTAILQ_REMOVE(&mr->coalesced, cmr, link); | |
7267c094 | 2288 | g_free(cmr); |
ab5b3db5 FZ |
2289 | updated = true; |
2290 | } | |
2291 | ||
2292 | if (updated) { | |
2293 | memory_region_update_coalesced_range(mr); | |
093bc2cd | 2294 | } |
093bc2cd AK |
2295 | } |
2296 | ||
d410515e JK |
2297 | void memory_region_set_flush_coalesced(MemoryRegion *mr) |
2298 | { | |
2299 | mr->flush_coalesced_mmio = true; | |
2300 | } | |
2301 | ||
2302 | void memory_region_clear_flush_coalesced(MemoryRegion *mr) | |
2303 | { | |
2304 | qemu_flush_coalesced_mmio_buffer(); | |
2305 | if (QTAILQ_EMPTY(&mr->coalesced)) { | |
2306 | mr->flush_coalesced_mmio = false; | |
2307 | } | |
2308 | } | |
2309 | ||
196ea131 JK |
2310 | void memory_region_clear_global_locking(MemoryRegion *mr) |
2311 | { | |
2312 | mr->global_locking = false; | |
2313 | } | |
2314 | ||
8c56c1a5 PF |
2315 | static bool userspace_eventfd_warning; |
2316 | ||
3e9d69e7 | 2317 | void memory_region_add_eventfd(MemoryRegion *mr, |
a8170e5e | 2318 | hwaddr addr, |
3e9d69e7 AK |
2319 | unsigned size, |
2320 | bool match_data, | |
2321 | uint64_t data, | |
753d5e14 | 2322 | EventNotifier *e) |
3e9d69e7 AK |
2323 | { |
2324 | MemoryRegionIoeventfd mrfd = { | |
08dafab4 AK |
2325 | .addr.start = int128_make64(addr), |
2326 | .addr.size = int128_make64(size), | |
3e9d69e7 AK |
2327 | .match_data = match_data, |
2328 | .data = data, | |
753d5e14 | 2329 | .e = e, |
3e9d69e7 AK |
2330 | }; |
2331 | unsigned i; | |
2332 | ||
8c56c1a5 PF |
2333 | if (kvm_enabled() && (!(kvm_eventfds_enabled() || |
2334 | userspace_eventfd_warning))) { | |
2335 | userspace_eventfd_warning = true; | |
2336 | error_report("Using eventfd without MMIO binding in KVM. " | |
2337 | "Suboptimal performance expected"); | |
2338 | } | |
2339 | ||
b8aecea2 JW |
2340 | if (size) { |
2341 | adjust_endianness(mr, &mrfd.data, size); | |
2342 | } | |
59023ef4 | 2343 | memory_region_transaction_begin(); |
3e9d69e7 | 2344 | for (i = 0; i < mr->ioeventfd_nb; ++i) { |
73bb753d | 2345 | if (memory_region_ioeventfd_before(&mrfd, &mr->ioeventfds[i])) { |
3e9d69e7 AK |
2346 | break; |
2347 | } | |
2348 | } | |
2349 | ++mr->ioeventfd_nb; | |
7267c094 | 2350 | mr->ioeventfds = g_realloc(mr->ioeventfds, |
3e9d69e7 AK |
2351 | sizeof(*mr->ioeventfds) * mr->ioeventfd_nb); |
2352 | memmove(&mr->ioeventfds[i+1], &mr->ioeventfds[i], | |
2353 | sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb-1 - i)); | |
2354 | mr->ioeventfds[i] = mrfd; | |
4dc56152 | 2355 | ioeventfd_update_pending |= mr->enabled; |
59023ef4 | 2356 | memory_region_transaction_commit(); |
3e9d69e7 AK |
2357 | } |
2358 | ||
2359 | void memory_region_del_eventfd(MemoryRegion *mr, | |
a8170e5e | 2360 | hwaddr addr, |
3e9d69e7 AK |
2361 | unsigned size, |
2362 | bool match_data, | |
2363 | uint64_t data, | |
753d5e14 | 2364 | EventNotifier *e) |
3e9d69e7 AK |
2365 | { |
2366 | MemoryRegionIoeventfd mrfd = { | |
08dafab4 AK |
2367 | .addr.start = int128_make64(addr), |
2368 | .addr.size = int128_make64(size), | |
3e9d69e7 AK |
2369 | .match_data = match_data, |
2370 | .data = data, | |
753d5e14 | 2371 | .e = e, |
3e9d69e7 AK |
2372 | }; |
2373 | unsigned i; | |
2374 | ||
b8aecea2 JW |
2375 | if (size) { |
2376 | adjust_endianness(mr, &mrfd.data, size); | |
2377 | } | |
59023ef4 | 2378 | memory_region_transaction_begin(); |
3e9d69e7 | 2379 | for (i = 0; i < mr->ioeventfd_nb; ++i) { |
73bb753d | 2380 | if (memory_region_ioeventfd_equal(&mrfd, &mr->ioeventfds[i])) { |
3e9d69e7 AK |
2381 | break; |
2382 | } | |
2383 | } | |
2384 | assert(i != mr->ioeventfd_nb); | |
2385 | memmove(&mr->ioeventfds[i], &mr->ioeventfds[i+1], | |
2386 | sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb - (i+1))); | |
2387 | --mr->ioeventfd_nb; | |
7267c094 | 2388 | mr->ioeventfds = g_realloc(mr->ioeventfds, |
3e9d69e7 | 2389 | sizeof(*mr->ioeventfds)*mr->ioeventfd_nb + 1); |
4dc56152 | 2390 | ioeventfd_update_pending |= mr->enabled; |
59023ef4 | 2391 | memory_region_transaction_commit(); |
3e9d69e7 AK |
2392 | } |
2393 | ||
feca4ac1 | 2394 | static void memory_region_update_container_subregions(MemoryRegion *subregion) |
093bc2cd | 2395 | { |
feca4ac1 | 2396 | MemoryRegion *mr = subregion->container; |
093bc2cd AK |
2397 | MemoryRegion *other; |
2398 | ||
59023ef4 JK |
2399 | memory_region_transaction_begin(); |
2400 | ||
dfde4e6e | 2401 | memory_region_ref(subregion); |
093bc2cd AK |
2402 | QTAILQ_FOREACH(other, &mr->subregions, subregions_link) { |
2403 | if (subregion->priority >= other->priority) { | |
2404 | QTAILQ_INSERT_BEFORE(other, subregion, subregions_link); | |
2405 | goto done; | |
2406 | } | |
2407 | } | |
2408 | QTAILQ_INSERT_TAIL(&mr->subregions, subregion, subregions_link); | |
2409 | done: | |
22bde714 | 2410 | memory_region_update_pending |= mr->enabled && subregion->enabled; |
59023ef4 | 2411 | memory_region_transaction_commit(); |
093bc2cd AK |
2412 | } |
2413 | ||
0598701a PC |
2414 | static void memory_region_add_subregion_common(MemoryRegion *mr, |
2415 | hwaddr offset, | |
2416 | MemoryRegion *subregion) | |
2417 | { | |
feca4ac1 PB |
2418 | assert(!subregion->container); |
2419 | subregion->container = mr; | |
0598701a | 2420 | subregion->addr = offset; |
feca4ac1 | 2421 | memory_region_update_container_subregions(subregion); |
0598701a | 2422 | } |
093bc2cd AK |
2423 | |
2424 | void memory_region_add_subregion(MemoryRegion *mr, | |
a8170e5e | 2425 | hwaddr offset, |
093bc2cd AK |
2426 | MemoryRegion *subregion) |
2427 | { | |
093bc2cd AK |
2428 | subregion->priority = 0; |
2429 | memory_region_add_subregion_common(mr, offset, subregion); | |
2430 | } | |
2431 | ||
2432 | void memory_region_add_subregion_overlap(MemoryRegion *mr, | |
a8170e5e | 2433 | hwaddr offset, |
093bc2cd | 2434 | MemoryRegion *subregion, |
a1ff8ae0 | 2435 | int priority) |
093bc2cd | 2436 | { |
093bc2cd AK |
2437 | subregion->priority = priority; |
2438 | memory_region_add_subregion_common(mr, offset, subregion); | |
2439 | } | |
2440 | ||
2441 | void memory_region_del_subregion(MemoryRegion *mr, | |
2442 | MemoryRegion *subregion) | |
2443 | { | |
59023ef4 | 2444 | memory_region_transaction_begin(); |
feca4ac1 PB |
2445 | assert(subregion->container == mr); |
2446 | subregion->container = NULL; | |
093bc2cd | 2447 | QTAILQ_REMOVE(&mr->subregions, subregion, subregions_link); |
dfde4e6e | 2448 | memory_region_unref(subregion); |
22bde714 | 2449 | memory_region_update_pending |= mr->enabled && subregion->enabled; |
59023ef4 | 2450 | memory_region_transaction_commit(); |
6bba19ba AK |
2451 | } |
2452 | ||
2453 | void memory_region_set_enabled(MemoryRegion *mr, bool enabled) | |
2454 | { | |
2455 | if (enabled == mr->enabled) { | |
2456 | return; | |
2457 | } | |
59023ef4 | 2458 | memory_region_transaction_begin(); |
6bba19ba | 2459 | mr->enabled = enabled; |
22bde714 | 2460 | memory_region_update_pending = true; |
59023ef4 | 2461 | memory_region_transaction_commit(); |
093bc2cd | 2462 | } |
1c0ffa58 | 2463 | |
e7af4c67 MT |
2464 | void memory_region_set_size(MemoryRegion *mr, uint64_t size) |
2465 | { | |
2466 | Int128 s = int128_make64(size); | |
2467 | ||
2468 | if (size == UINT64_MAX) { | |
2469 | s = int128_2_64(); | |
2470 | } | |
2471 | if (int128_eq(s, mr->size)) { | |
2472 | return; | |
2473 | } | |
2474 | memory_region_transaction_begin(); | |
2475 | mr->size = s; | |
2476 | memory_region_update_pending = true; | |
2477 | memory_region_transaction_commit(); | |
2478 | } | |
2479 | ||
67891b8a | 2480 | static void memory_region_readd_subregion(MemoryRegion *mr) |
2282e1af | 2481 | { |
feca4ac1 | 2482 | MemoryRegion *container = mr->container; |
2282e1af | 2483 | |
feca4ac1 | 2484 | if (container) { |
67891b8a PC |
2485 | memory_region_transaction_begin(); |
2486 | memory_region_ref(mr); | |
feca4ac1 PB |
2487 | memory_region_del_subregion(container, mr); |
2488 | mr->container = container; | |
2489 | memory_region_update_container_subregions(mr); | |
67891b8a PC |
2490 | memory_region_unref(mr); |
2491 | memory_region_transaction_commit(); | |
2282e1af | 2492 | } |
67891b8a | 2493 | } |
2282e1af | 2494 | |
67891b8a PC |
2495 | void memory_region_set_address(MemoryRegion *mr, hwaddr addr) |
2496 | { | |
2497 | if (addr != mr->addr) { | |
2498 | mr->addr = addr; | |
2499 | memory_region_readd_subregion(mr); | |
2500 | } | |
2282e1af AK |
2501 | } |
2502 | ||
a8170e5e | 2503 | void memory_region_set_alias_offset(MemoryRegion *mr, hwaddr offset) |
4703359e | 2504 | { |
4703359e | 2505 | assert(mr->alias); |
4703359e | 2506 | |
59023ef4 | 2507 | if (offset == mr->alias_offset) { |
4703359e AK |
2508 | return; |
2509 | } | |
2510 | ||
59023ef4 JK |
2511 | memory_region_transaction_begin(); |
2512 | mr->alias_offset = offset; | |
22bde714 | 2513 | memory_region_update_pending |= mr->enabled; |
59023ef4 | 2514 | memory_region_transaction_commit(); |
4703359e AK |
2515 | } |
2516 | ||
a2b257d6 IM |
2517 | uint64_t memory_region_get_alignment(const MemoryRegion *mr) |
2518 | { | |
2519 | return mr->align; | |
2520 | } | |
2521 | ||
e2177955 AK |
2522 | static int cmp_flatrange_addr(const void *addr_, const void *fr_) |
2523 | { | |
2524 | const AddrRange *addr = addr_; | |
2525 | const FlatRange *fr = fr_; | |
2526 | ||
2527 | if (int128_le(addrrange_end(*addr), fr->addr.start)) { | |
2528 | return -1; | |
2529 | } else if (int128_ge(addr->start, addrrange_end(fr->addr))) { | |
2530 | return 1; | |
2531 | } | |
2532 | return 0; | |
2533 | } | |
2534 | ||
99e86347 | 2535 | static FlatRange *flatview_lookup(FlatView *view, AddrRange addr) |
e2177955 | 2536 | { |
99e86347 | 2537 | return bsearch(&addr, view->ranges, view->nr, |
e2177955 AK |
2538 | sizeof(FlatRange), cmp_flatrange_addr); |
2539 | } | |
2540 | ||
eed2bacf IM |
2541 | bool memory_region_is_mapped(MemoryRegion *mr) |
2542 | { | |
2543 | return mr->container ? true : false; | |
2544 | } | |
2545 | ||
c6742b14 PB |
2546 | /* Same as memory_region_find, but it does not add a reference to the |
2547 | * returned region. It must be called from an RCU critical section. | |
2548 | */ | |
2549 | static MemoryRegionSection memory_region_find_rcu(MemoryRegion *mr, | |
2550 | hwaddr addr, uint64_t size) | |
e2177955 | 2551 | { |
052e87b0 | 2552 | MemoryRegionSection ret = { .mr = NULL }; |
73034e9e PB |
2553 | MemoryRegion *root; |
2554 | AddressSpace *as; | |
2555 | AddrRange range; | |
99e86347 | 2556 | FlatView *view; |
73034e9e PB |
2557 | FlatRange *fr; |
2558 | ||
2559 | addr += mr->addr; | |
feca4ac1 PB |
2560 | for (root = mr; root->container; ) { |
2561 | root = root->container; | |
73034e9e PB |
2562 | addr += root->addr; |
2563 | } | |
e2177955 | 2564 | |
73034e9e | 2565 | as = memory_region_to_address_space(root); |
eed2bacf IM |
2566 | if (!as) { |
2567 | return ret; | |
2568 | } | |
73034e9e | 2569 | range = addrrange_make(int128_make64(addr), int128_make64(size)); |
99e86347 | 2570 | |
16620684 | 2571 | view = address_space_to_flatview(as); |
99e86347 | 2572 | fr = flatview_lookup(view, range); |
e2177955 | 2573 | if (!fr) { |
c6742b14 | 2574 | return ret; |
e2177955 AK |
2575 | } |
2576 | ||
99e86347 | 2577 | while (fr > view->ranges && addrrange_intersects(fr[-1].addr, range)) { |
e2177955 AK |
2578 | --fr; |
2579 | } | |
2580 | ||
2581 | ret.mr = fr->mr; | |
16620684 | 2582 | ret.fv = view; |
e2177955 AK |
2583 | range = addrrange_intersection(range, fr->addr); |
2584 | ret.offset_within_region = fr->offset_in_region; | |
2585 | ret.offset_within_region += int128_get64(int128_sub(range.start, | |
2586 | fr->addr.start)); | |
052e87b0 | 2587 | ret.size = range.size; |
e2177955 | 2588 | ret.offset_within_address_space = int128_get64(range.start); |
7a8499e8 | 2589 | ret.readonly = fr->readonly; |
c26763f8 | 2590 | ret.nonvolatile = fr->nonvolatile; |
c6742b14 PB |
2591 | return ret; |
2592 | } | |
2593 | ||
2594 | MemoryRegionSection memory_region_find(MemoryRegion *mr, | |
2595 | hwaddr addr, uint64_t size) | |
2596 | { | |
2597 | MemoryRegionSection ret; | |
2598 | rcu_read_lock(); | |
2599 | ret = memory_region_find_rcu(mr, addr, size); | |
2600 | if (ret.mr) { | |
2601 | memory_region_ref(ret.mr); | |
2602 | } | |
2b647668 | 2603 | rcu_read_unlock(); |
e2177955 AK |
2604 | return ret; |
2605 | } | |
2606 | ||
c6742b14 PB |
2607 | bool memory_region_present(MemoryRegion *container, hwaddr addr) |
2608 | { | |
2609 | MemoryRegion *mr; | |
2610 | ||
2611 | rcu_read_lock(); | |
2612 | mr = memory_region_find_rcu(container, addr, 1).mr; | |
2613 | rcu_read_unlock(); | |
2614 | return mr && mr != container; | |
2615 | } | |
2616 | ||
9c1f8f44 | 2617 | void memory_global_dirty_log_sync(void) |
86e775c6 | 2618 | { |
3ebb1817 | 2619 | memory_region_sync_dirty_bitmap(NULL); |
7664e80c AK |
2620 | } |
2621 | ||
19310760 JZ |
2622 | static VMChangeStateEntry *vmstate_change; |
2623 | ||
7664e80c AK |
2624 | void memory_global_dirty_log_start(void) |
2625 | { | |
19310760 JZ |
2626 | if (vmstate_change) { |
2627 | qemu_del_vm_change_state_handler(vmstate_change); | |
2628 | vmstate_change = NULL; | |
2629 | } | |
2630 | ||
7664e80c | 2631 | global_dirty_log = true; |
6f6a5ef3 | 2632 | |
7376e582 | 2633 | MEMORY_LISTENER_CALL_GLOBAL(log_global_start, Forward); |
6f6a5ef3 | 2634 | |
39adb536 | 2635 | /* Refresh DIRTY_MEMORY_MIGRATION bit. */ |
6f6a5ef3 PB |
2636 | memory_region_transaction_begin(); |
2637 | memory_region_update_pending = true; | |
2638 | memory_region_transaction_commit(); | |
7664e80c AK |
2639 | } |
2640 | ||
19310760 | 2641 | static void memory_global_dirty_log_do_stop(void) |
7664e80c | 2642 | { |
7664e80c | 2643 | global_dirty_log = false; |
6f6a5ef3 | 2644 | |
39adb536 | 2645 | /* Refresh DIRTY_MEMORY_MIGRATION bit. */ |
6f6a5ef3 PB |
2646 | memory_region_transaction_begin(); |
2647 | memory_region_update_pending = true; | |
2648 | memory_region_transaction_commit(); | |
2649 | ||
7376e582 | 2650 | MEMORY_LISTENER_CALL_GLOBAL(log_global_stop, Reverse); |
7664e80c AK |
2651 | } |
2652 | ||
19310760 JZ |
2653 | static void memory_vm_change_state_handler(void *opaque, int running, |
2654 | RunState state) | |
2655 | { | |
2656 | if (running) { | |
2657 | memory_global_dirty_log_do_stop(); | |
2658 | ||
2659 | if (vmstate_change) { | |
2660 | qemu_del_vm_change_state_handler(vmstate_change); | |
2661 | vmstate_change = NULL; | |
2662 | } | |
2663 | } | |
2664 | } | |
2665 | ||
2666 | void memory_global_dirty_log_stop(void) | |
2667 | { | |
2668 | if (!runstate_is_running()) { | |
2669 | if (vmstate_change) { | |
2670 | return; | |
2671 | } | |
2672 | vmstate_change = qemu_add_vm_change_state_handler( | |
2673 | memory_vm_change_state_handler, NULL); | |
2674 | return; | |
2675 | } | |
2676 | ||
2677 | memory_global_dirty_log_do_stop(); | |
2678 | } | |
2679 | ||
7664e80c AK |
2680 | static void listener_add_address_space(MemoryListener *listener, |
2681 | AddressSpace *as) | |
2682 | { | |
99e86347 | 2683 | FlatView *view; |
7664e80c AK |
2684 | FlatRange *fr; |
2685 | ||
680a4783 PB |
2686 | if (listener->begin) { |
2687 | listener->begin(listener); | |
2688 | } | |
7664e80c | 2689 | if (global_dirty_log) { |
975aefe0 AK |
2690 | if (listener->log_global_start) { |
2691 | listener->log_global_start(listener); | |
2692 | } | |
7664e80c | 2693 | } |
975aefe0 | 2694 | |
856d7245 | 2695 | view = address_space_get_flatview(as); |
99e86347 | 2696 | FOR_EACH_FLAT_RANGE(fr, view) { |
279836f8 DH |
2697 | MemoryRegionSection section = section_from_flat_range(fr, view); |
2698 | ||
975aefe0 AK |
2699 | if (listener->region_add) { |
2700 | listener->region_add(listener, §ion); | |
2701 | } | |
ae990e6c DH |
2702 | if (fr->dirty_log_mask && listener->log_start) { |
2703 | listener->log_start(listener, §ion, 0, fr->dirty_log_mask); | |
2704 | } | |
7664e80c | 2705 | } |
680a4783 PB |
2706 | if (listener->commit) { |
2707 | listener->commit(listener); | |
2708 | } | |
856d7245 | 2709 | flatview_unref(view); |
7664e80c AK |
2710 | } |
2711 | ||
d25836ca PX |
2712 | static void listener_del_address_space(MemoryListener *listener, |
2713 | AddressSpace *as) | |
2714 | { | |
2715 | FlatView *view; | |
2716 | FlatRange *fr; | |
2717 | ||
2718 | if (listener->begin) { | |
2719 | listener->begin(listener); | |
2720 | } | |
2721 | view = address_space_get_flatview(as); | |
2722 | FOR_EACH_FLAT_RANGE(fr, view) { | |
2723 | MemoryRegionSection section = section_from_flat_range(fr, view); | |
2724 | ||
2725 | if (fr->dirty_log_mask && listener->log_stop) { | |
2726 | listener->log_stop(listener, §ion, fr->dirty_log_mask, 0); | |
2727 | } | |
2728 | if (listener->region_del) { | |
2729 | listener->region_del(listener, §ion); | |
2730 | } | |
2731 | } | |
2732 | if (listener->commit) { | |
2733 | listener->commit(listener); | |
2734 | } | |
2735 | flatview_unref(view); | |
2736 | } | |
2737 | ||
d45fa784 | 2738 | void memory_listener_register(MemoryListener *listener, AddressSpace *as) |
7664e80c | 2739 | { |
72e22d2f AK |
2740 | MemoryListener *other = NULL; |
2741 | ||
d45fa784 | 2742 | listener->address_space = as; |
72e22d2f | 2743 | if (QTAILQ_EMPTY(&memory_listeners) |
eae3eb3e | 2744 | || listener->priority >= QTAILQ_LAST(&memory_listeners)->priority) { |
72e22d2f AK |
2745 | QTAILQ_INSERT_TAIL(&memory_listeners, listener, link); |
2746 | } else { | |
2747 | QTAILQ_FOREACH(other, &memory_listeners, link) { | |
2748 | if (listener->priority < other->priority) { | |
2749 | break; | |
2750 | } | |
2751 | } | |
2752 | QTAILQ_INSERT_BEFORE(other, listener, link); | |
2753 | } | |
0d673e36 | 2754 | |
9a54635d | 2755 | if (QTAILQ_EMPTY(&as->listeners) |
eae3eb3e | 2756 | || listener->priority >= QTAILQ_LAST(&as->listeners)->priority) { |
9a54635d PB |
2757 | QTAILQ_INSERT_TAIL(&as->listeners, listener, link_as); |
2758 | } else { | |
2759 | QTAILQ_FOREACH(other, &as->listeners, link_as) { | |
2760 | if (listener->priority < other->priority) { | |
2761 | break; | |
2762 | } | |
2763 | } | |
2764 | QTAILQ_INSERT_BEFORE(other, listener, link_as); | |
2765 | } | |
2766 | ||
d45fa784 | 2767 | listener_add_address_space(listener, as); |
7664e80c AK |
2768 | } |
2769 | ||
2770 | void memory_listener_unregister(MemoryListener *listener) | |
2771 | { | |
1d8280c1 PB |
2772 | if (!listener->address_space) { |
2773 | return; | |
2774 | } | |
2775 | ||
d25836ca | 2776 | listener_del_address_space(listener, listener->address_space); |
72e22d2f | 2777 | QTAILQ_REMOVE(&memory_listeners, listener, link); |
9a54635d | 2778 | QTAILQ_REMOVE(&listener->address_space->listeners, listener, link_as); |
1d8280c1 | 2779 | listener->address_space = NULL; |
86e775c6 | 2780 | } |
e2177955 | 2781 | |
a2166410 GK |
2782 | void address_space_remove_listeners(AddressSpace *as) |
2783 | { | |
2784 | while (!QTAILQ_EMPTY(&as->listeners)) { | |
2785 | memory_listener_unregister(QTAILQ_FIRST(&as->listeners)); | |
2786 | } | |
2787 | } | |
2788 | ||
7dca8043 | 2789 | void address_space_init(AddressSpace *as, MemoryRegion *root, const char *name) |
1c0ffa58 | 2790 | { |
ac95190e | 2791 | memory_region_ref(root); |
8786db7c | 2792 | as->root = root; |
67ace39b | 2793 | as->current_map = NULL; |
4c19eb72 AK |
2794 | as->ioeventfd_nb = 0; |
2795 | as->ioeventfds = NULL; | |
9a54635d | 2796 | QTAILQ_INIT(&as->listeners); |
0d673e36 | 2797 | QTAILQ_INSERT_TAIL(&address_spaces, as, address_spaces_link); |
7dca8043 | 2798 | as->name = g_strdup(name ? name : "anonymous"); |
202fc01b AK |
2799 | address_space_update_topology(as); |
2800 | address_space_update_ioeventfds(as); | |
1c0ffa58 | 2801 | } |
658b2224 | 2802 | |
374f2981 | 2803 | static void do_address_space_destroy(AddressSpace *as) |
83f3c251 | 2804 | { |
9a54635d | 2805 | assert(QTAILQ_EMPTY(&as->listeners)); |
078c44f4 | 2806 | |
856d7245 | 2807 | flatview_unref(as->current_map); |
7dca8043 | 2808 | g_free(as->name); |
4c19eb72 | 2809 | g_free(as->ioeventfds); |
ac95190e | 2810 | memory_region_unref(as->root); |
83f3c251 AK |
2811 | } |
2812 | ||
374f2981 PB |
2813 | void address_space_destroy(AddressSpace *as) |
2814 | { | |
ac95190e PB |
2815 | MemoryRegion *root = as->root; |
2816 | ||
374f2981 PB |
2817 | /* Flush out anything from MemoryListeners listening in on this */ |
2818 | memory_region_transaction_begin(); | |
2819 | as->root = NULL; | |
2820 | memory_region_transaction_commit(); | |
2821 | QTAILQ_REMOVE(&address_spaces, as, address_spaces_link); | |
2822 | ||
2823 | /* At this point, as->dispatch and as->current_map are dummy | |
2824 | * entries that the guest should never use. Wait for the old | |
2825 | * values to expire before freeing the data. | |
2826 | */ | |
ac95190e | 2827 | as->root = root; |
374f2981 PB |
2828 | call_rcu(as, do_address_space_destroy, rcu); |
2829 | } | |
2830 | ||
4e831901 PX |
2831 | static const char *memory_region_type(MemoryRegion *mr) |
2832 | { | |
2833 | if (memory_region_is_ram_device(mr)) { | |
2834 | return "ramd"; | |
2835 | } else if (memory_region_is_romd(mr)) { | |
2836 | return "romd"; | |
2837 | } else if (memory_region_is_rom(mr)) { | |
2838 | return "rom"; | |
2839 | } else if (memory_region_is_ram(mr)) { | |
2840 | return "ram"; | |
2841 | } else { | |
2842 | return "i/o"; | |
2843 | } | |
2844 | } | |
2845 | ||
314e2987 BS |
2846 | typedef struct MemoryRegionList MemoryRegionList; |
2847 | ||
2848 | struct MemoryRegionList { | |
2849 | const MemoryRegion *mr; | |
a16878d2 | 2850 | QTAILQ_ENTRY(MemoryRegionList) mrqueue; |
314e2987 BS |
2851 | }; |
2852 | ||
b58deb34 | 2853 | typedef QTAILQ_HEAD(, MemoryRegionList) MemoryRegionListHead; |
314e2987 | 2854 | |
4e831901 PX |
2855 | #define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \ |
2856 | int128_sub((size), int128_one())) : 0) | |
2857 | #define MTREE_INDENT " " | |
2858 | ||
b6b71cb5 | 2859 | static void mtree_expand_owner(const char *label, Object *obj) |
fc051ae6 AK |
2860 | { |
2861 | DeviceState *dev = (DeviceState *) object_dynamic_cast(obj, TYPE_DEVICE); | |
2862 | ||
b6b71cb5 | 2863 | qemu_printf(" %s:{%s", label, dev ? "dev" : "obj"); |
fc051ae6 | 2864 | if (dev && dev->id) { |
b6b71cb5 | 2865 | qemu_printf(" id=%s", dev->id); |
fc051ae6 AK |
2866 | } else { |
2867 | gchar *canonical_path = object_get_canonical_path(obj); | |
2868 | if (canonical_path) { | |
b6b71cb5 | 2869 | qemu_printf(" path=%s", canonical_path); |
fc051ae6 AK |
2870 | g_free(canonical_path); |
2871 | } else { | |
b6b71cb5 | 2872 | qemu_printf(" type=%s", object_get_typename(obj)); |
fc051ae6 AK |
2873 | } |
2874 | } | |
b6b71cb5 | 2875 | qemu_printf("}"); |
fc051ae6 AK |
2876 | } |
2877 | ||
b6b71cb5 | 2878 | static void mtree_print_mr_owner(const MemoryRegion *mr) |
fc051ae6 AK |
2879 | { |
2880 | Object *owner = mr->owner; | |
2881 | Object *parent = memory_region_owner((MemoryRegion *)mr); | |
2882 | ||
2883 | if (!owner && !parent) { | |
b6b71cb5 | 2884 | qemu_printf(" orphan"); |
fc051ae6 AK |
2885 | return; |
2886 | } | |
2887 | if (owner) { | |
b6b71cb5 | 2888 | mtree_expand_owner("owner", owner); |
fc051ae6 AK |
2889 | } |
2890 | if (parent && parent != owner) { | |
b6b71cb5 | 2891 | mtree_expand_owner("parent", parent); |
fc051ae6 AK |
2892 | } |
2893 | } | |
2894 | ||
b6b71cb5 | 2895 | static void mtree_print_mr(const MemoryRegion *mr, unsigned int level, |
a8170e5e | 2896 | hwaddr base, |
fc051ae6 AK |
2897 | MemoryRegionListHead *alias_print_queue, |
2898 | bool owner) | |
314e2987 | 2899 | { |
9479c57a JK |
2900 | MemoryRegionList *new_ml, *ml, *next_ml; |
2901 | MemoryRegionListHead submr_print_queue; | |
314e2987 BS |
2902 | const MemoryRegion *submr; |
2903 | unsigned int i; | |
b31f8412 | 2904 | hwaddr cur_start, cur_end; |
314e2987 | 2905 | |
f8a9f720 | 2906 | if (!mr) { |
314e2987 BS |
2907 | return; |
2908 | } | |
2909 | ||
2910 | for (i = 0; i < level; i++) { | |
b6b71cb5 | 2911 | qemu_printf(MTREE_INDENT); |
314e2987 BS |
2912 | } |
2913 | ||
b31f8412 PX |
2914 | cur_start = base + mr->addr; |
2915 | cur_end = cur_start + MR_SIZE(mr->size); | |
2916 | ||
2917 | /* | |
2918 | * Try to detect overflow of memory region. This should never | |
2919 | * happen normally. When it happens, we dump something to warn the | |
2920 | * user who is observing this. | |
2921 | */ | |
2922 | if (cur_start < base || cur_end < cur_start) { | |
b6b71cb5 | 2923 | qemu_printf("[DETECTED OVERFLOW!] "); |
b31f8412 PX |
2924 | } |
2925 | ||
314e2987 BS |
2926 | if (mr->alias) { |
2927 | MemoryRegionList *ml; | |
2928 | bool found = false; | |
2929 | ||
2930 | /* check if the alias is already in the queue */ | |
a16878d2 | 2931 | QTAILQ_FOREACH(ml, alias_print_queue, mrqueue) { |
f54bb15f | 2932 | if (ml->mr == mr->alias) { |
314e2987 BS |
2933 | found = true; |
2934 | } | |
2935 | } | |
2936 | ||
2937 | if (!found) { | |
2938 | ml = g_new(MemoryRegionList, 1); | |
2939 | ml->mr = mr->alias; | |
a16878d2 | 2940 | QTAILQ_INSERT_TAIL(alias_print_queue, ml, mrqueue); |
314e2987 | 2941 | } |
b6b71cb5 MA |
2942 | qemu_printf(TARGET_FMT_plx "-" TARGET_FMT_plx |
2943 | " (prio %d, %s%s): alias %s @%s " TARGET_FMT_plx | |
2944 | "-" TARGET_FMT_plx "%s", | |
2945 | cur_start, cur_end, | |
2946 | mr->priority, | |
2947 | mr->nonvolatile ? "nv-" : "", | |
2948 | memory_region_type((MemoryRegion *)mr), | |
2949 | memory_region_name(mr), | |
2950 | memory_region_name(mr->alias), | |
2951 | mr->alias_offset, | |
2952 | mr->alias_offset + MR_SIZE(mr->size), | |
2953 | mr->enabled ? "" : " [disabled]"); | |
fc051ae6 | 2954 | if (owner) { |
b6b71cb5 | 2955 | mtree_print_mr_owner(mr); |
fc051ae6 | 2956 | } |
314e2987 | 2957 | } else { |
b6b71cb5 MA |
2958 | qemu_printf(TARGET_FMT_plx "-" TARGET_FMT_plx |
2959 | " (prio %d, %s%s): %s%s", | |
2960 | cur_start, cur_end, | |
2961 | mr->priority, | |
2962 | mr->nonvolatile ? "nv-" : "", | |
2963 | memory_region_type((MemoryRegion *)mr), | |
2964 | memory_region_name(mr), | |
2965 | mr->enabled ? "" : " [disabled]"); | |
fc051ae6 | 2966 | if (owner) { |
b6b71cb5 | 2967 | mtree_print_mr_owner(mr); |
fc051ae6 | 2968 | } |
314e2987 | 2969 | } |
b6b71cb5 | 2970 | qemu_printf("\n"); |
9479c57a JK |
2971 | |
2972 | QTAILQ_INIT(&submr_print_queue); | |
2973 | ||
314e2987 | 2974 | QTAILQ_FOREACH(submr, &mr->subregions, subregions_link) { |
9479c57a JK |
2975 | new_ml = g_new(MemoryRegionList, 1); |
2976 | new_ml->mr = submr; | |
a16878d2 | 2977 | QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) { |
9479c57a JK |
2978 | if (new_ml->mr->addr < ml->mr->addr || |
2979 | (new_ml->mr->addr == ml->mr->addr && | |
2980 | new_ml->mr->priority > ml->mr->priority)) { | |
a16878d2 | 2981 | QTAILQ_INSERT_BEFORE(ml, new_ml, mrqueue); |
9479c57a JK |
2982 | new_ml = NULL; |
2983 | break; | |
2984 | } | |
2985 | } | |
2986 | if (new_ml) { | |
a16878d2 | 2987 | QTAILQ_INSERT_TAIL(&submr_print_queue, new_ml, mrqueue); |
9479c57a JK |
2988 | } |
2989 | } | |
2990 | ||
a16878d2 | 2991 | QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) { |
b6b71cb5 | 2992 | mtree_print_mr(ml->mr, level + 1, cur_start, |
fc051ae6 | 2993 | alias_print_queue, owner); |
9479c57a JK |
2994 | } |
2995 | ||
a16878d2 | 2996 | QTAILQ_FOREACH_SAFE(ml, &submr_print_queue, mrqueue, next_ml) { |
9479c57a | 2997 | g_free(ml); |
314e2987 BS |
2998 | } |
2999 | } | |
3000 | ||
5e8fd947 | 3001 | struct FlatViewInfo { |
5e8fd947 AK |
3002 | int counter; |
3003 | bool dispatch_tree; | |
fc051ae6 | 3004 | bool owner; |
8072aae3 AK |
3005 | AccelClass *ac; |
3006 | const char *ac_name; | |
5e8fd947 AK |
3007 | }; |
3008 | ||
3009 | static void mtree_print_flatview(gpointer key, gpointer value, | |
3010 | gpointer user_data) | |
57bb40c9 | 3011 | { |
5e8fd947 AK |
3012 | FlatView *view = key; |
3013 | GArray *fv_address_spaces = value; | |
3014 | struct FlatViewInfo *fvi = user_data; | |
57bb40c9 PX |
3015 | FlatRange *range = &view->ranges[0]; |
3016 | MemoryRegion *mr; | |
3017 | int n = view->nr; | |
5e8fd947 AK |
3018 | int i; |
3019 | AddressSpace *as; | |
3020 | ||
b6b71cb5 | 3021 | qemu_printf("FlatView #%d\n", fvi->counter); |
5e8fd947 AK |
3022 | ++fvi->counter; |
3023 | ||
3024 | for (i = 0; i < fv_address_spaces->len; ++i) { | |
3025 | as = g_array_index(fv_address_spaces, AddressSpace*, i); | |
b6b71cb5 MA |
3026 | qemu_printf(" AS \"%s\", root: %s", |
3027 | as->name, memory_region_name(as->root)); | |
5e8fd947 | 3028 | if (as->root->alias) { |
b6b71cb5 | 3029 | qemu_printf(", alias %s", memory_region_name(as->root->alias)); |
5e8fd947 | 3030 | } |
b6b71cb5 | 3031 | qemu_printf("\n"); |
5e8fd947 AK |
3032 | } |
3033 | ||
b6b71cb5 | 3034 | qemu_printf(" Root memory region: %s\n", |
5e8fd947 | 3035 | view->root ? memory_region_name(view->root) : "(none)"); |
57bb40c9 PX |
3036 | |
3037 | if (n <= 0) { | |
b6b71cb5 | 3038 | qemu_printf(MTREE_INDENT "No rendered FlatView\n\n"); |
57bb40c9 PX |
3039 | return; |
3040 | } | |
3041 | ||
3042 | while (n--) { | |
3043 | mr = range->mr; | |
377a07aa | 3044 | if (range->offset_in_region) { |
b6b71cb5 MA |
3045 | qemu_printf(MTREE_INDENT TARGET_FMT_plx "-" TARGET_FMT_plx |
3046 | " (prio %d, %s%s): %s @" TARGET_FMT_plx, | |
3047 | int128_get64(range->addr.start), | |
3048 | int128_get64(range->addr.start) | |
3049 | + MR_SIZE(range->addr.size), | |
3050 | mr->priority, | |
3051 | range->nonvolatile ? "nv-" : "", | |
3052 | range->readonly ? "rom" : memory_region_type(mr), | |
3053 | memory_region_name(mr), | |
3054 | range->offset_in_region); | |
377a07aa | 3055 | } else { |
b6b71cb5 MA |
3056 | qemu_printf(MTREE_INDENT TARGET_FMT_plx "-" TARGET_FMT_plx |
3057 | " (prio %d, %s%s): %s", | |
3058 | int128_get64(range->addr.start), | |
3059 | int128_get64(range->addr.start) | |
3060 | + MR_SIZE(range->addr.size), | |
3061 | mr->priority, | |
3062 | range->nonvolatile ? "nv-" : "", | |
3063 | range->readonly ? "rom" : memory_region_type(mr), | |
3064 | memory_region_name(mr)); | |
377a07aa | 3065 | } |
fc051ae6 | 3066 | if (fvi->owner) { |
b6b71cb5 | 3067 | mtree_print_mr_owner(mr); |
fc051ae6 | 3068 | } |
8072aae3 AK |
3069 | |
3070 | if (fvi->ac) { | |
3071 | for (i = 0; i < fv_address_spaces->len; ++i) { | |
3072 | as = g_array_index(fv_address_spaces, AddressSpace*, i); | |
3073 | if (fvi->ac->has_memory(current_machine, as, | |
3074 | int128_get64(range->addr.start), | |
3075 | MR_SIZE(range->addr.size) + 1)) { | |
3076 | qemu_printf(" %s", fvi->ac_name); | |
3077 | } | |
3078 | } | |
3079 | } | |
b6b71cb5 | 3080 | qemu_printf("\n"); |
57bb40c9 PX |
3081 | range++; |
3082 | } | |
3083 | ||
5e8fd947 AK |
3084 | #if !defined(CONFIG_USER_ONLY) |
3085 | if (fvi->dispatch_tree && view->root) { | |
b6b71cb5 | 3086 | mtree_print_dispatch(view->dispatch, view->root); |
5e8fd947 AK |
3087 | } |
3088 | #endif | |
3089 | ||
b6b71cb5 | 3090 | qemu_printf("\n"); |
5e8fd947 AK |
3091 | } |
3092 | ||
3093 | static gboolean mtree_info_flatview_free(gpointer key, gpointer value, | |
3094 | gpointer user_data) | |
3095 | { | |
3096 | FlatView *view = key; | |
3097 | GArray *fv_address_spaces = value; | |
3098 | ||
3099 | g_array_unref(fv_address_spaces); | |
57bb40c9 | 3100 | flatview_unref(view); |
5e8fd947 AK |
3101 | |
3102 | return true; | |
57bb40c9 PX |
3103 | } |
3104 | ||
b6b71cb5 | 3105 | void mtree_info(bool flatview, bool dispatch_tree, bool owner) |
314e2987 BS |
3106 | { |
3107 | MemoryRegionListHead ml_head; | |
3108 | MemoryRegionList *ml, *ml2; | |
0d673e36 | 3109 | AddressSpace *as; |
314e2987 | 3110 | |
57bb40c9 | 3111 | if (flatview) { |
5e8fd947 AK |
3112 | FlatView *view; |
3113 | struct FlatViewInfo fvi = { | |
5e8fd947 | 3114 | .counter = 0, |
fc051ae6 AK |
3115 | .dispatch_tree = dispatch_tree, |
3116 | .owner = owner, | |
5e8fd947 AK |
3117 | }; |
3118 | GArray *fv_address_spaces; | |
3119 | GHashTable *views = g_hash_table_new(g_direct_hash, g_direct_equal); | |
8072aae3 AK |
3120 | AccelClass *ac = ACCEL_GET_CLASS(current_machine->accelerator); |
3121 | ||
3122 | if (ac->has_memory) { | |
3123 | fvi.ac = ac; | |
3124 | fvi.ac_name = current_machine->accel ? current_machine->accel : | |
3125 | object_class_get_name(OBJECT_CLASS(ac)); | |
3126 | } | |
5e8fd947 AK |
3127 | |
3128 | /* Gather all FVs in one table */ | |
57bb40c9 | 3129 | QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) { |
5e8fd947 AK |
3130 | view = address_space_get_flatview(as); |
3131 | ||
3132 | fv_address_spaces = g_hash_table_lookup(views, view); | |
3133 | if (!fv_address_spaces) { | |
3134 | fv_address_spaces = g_array_new(false, false, sizeof(as)); | |
3135 | g_hash_table_insert(views, view, fv_address_spaces); | |
3136 | } | |
3137 | ||
3138 | g_array_append_val(fv_address_spaces, as); | |
57bb40c9 | 3139 | } |
5e8fd947 AK |
3140 | |
3141 | /* Print */ | |
3142 | g_hash_table_foreach(views, mtree_print_flatview, &fvi); | |
3143 | ||
3144 | /* Free */ | |
3145 | g_hash_table_foreach_remove(views, mtree_info_flatview_free, 0); | |
3146 | g_hash_table_unref(views); | |
3147 | ||
57bb40c9 PX |
3148 | return; |
3149 | } | |
3150 | ||
314e2987 BS |
3151 | QTAILQ_INIT(&ml_head); |
3152 | ||
0d673e36 | 3153 | QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) { |
b6b71cb5 MA |
3154 | qemu_printf("address-space: %s\n", as->name); |
3155 | mtree_print_mr(as->root, 1, 0, &ml_head, owner); | |
3156 | qemu_printf("\n"); | |
b9f9be88 BS |
3157 | } |
3158 | ||
314e2987 | 3159 | /* print aliased regions */ |
a16878d2 | 3160 | QTAILQ_FOREACH(ml, &ml_head, mrqueue) { |
b6b71cb5 MA |
3161 | qemu_printf("memory-region: %s\n", memory_region_name(ml->mr)); |
3162 | mtree_print_mr(ml->mr, 1, 0, &ml_head, owner); | |
3163 | qemu_printf("\n"); | |
314e2987 BS |
3164 | } |
3165 | ||
a16878d2 | 3166 | QTAILQ_FOREACH_SAFE(ml, &ml_head, mrqueue, ml2) { |
88365e47 | 3167 | g_free(ml); |
314e2987 | 3168 | } |
314e2987 | 3169 | } |
b4fefef9 | 3170 | |
b08199c6 PM |
3171 | void memory_region_init_ram(MemoryRegion *mr, |
3172 | struct Object *owner, | |
3173 | const char *name, | |
3174 | uint64_t size, | |
3175 | Error **errp) | |
3176 | { | |
3177 | DeviceState *owner_dev; | |
3178 | Error *err = NULL; | |
3179 | ||
3180 | memory_region_init_ram_nomigrate(mr, owner, name, size, &err); | |
3181 | if (err) { | |
3182 | error_propagate(errp, err); | |
3183 | return; | |
3184 | } | |
3185 | /* This will assert if owner is neither NULL nor a DeviceState. | |
3186 | * We only want the owner here for the purposes of defining a | |
3187 | * unique name for migration. TODO: Ideally we should implement | |
3188 | * a naming scheme for Objects which are not DeviceStates, in | |
3189 | * which case we can relax this restriction. | |
3190 | */ | |
3191 | owner_dev = DEVICE(owner); | |
3192 | vmstate_register_ram(mr, owner_dev); | |
3193 | } | |
3194 | ||
3195 | void memory_region_init_rom(MemoryRegion *mr, | |
3196 | struct Object *owner, | |
3197 | const char *name, | |
3198 | uint64_t size, | |
3199 | Error **errp) | |
3200 | { | |
3201 | DeviceState *owner_dev; | |
3202 | Error *err = NULL; | |
3203 | ||
3204 | memory_region_init_rom_nomigrate(mr, owner, name, size, &err); | |
3205 | if (err) { | |
3206 | error_propagate(errp, err); | |
3207 | return; | |
3208 | } | |
3209 | /* This will assert if owner is neither NULL nor a DeviceState. | |
3210 | * We only want the owner here for the purposes of defining a | |
3211 | * unique name for migration. TODO: Ideally we should implement | |
3212 | * a naming scheme for Objects which are not DeviceStates, in | |
3213 | * which case we can relax this restriction. | |
3214 | */ | |
3215 | owner_dev = DEVICE(owner); | |
3216 | vmstate_register_ram(mr, owner_dev); | |
3217 | } | |
3218 | ||
3219 | void memory_region_init_rom_device(MemoryRegion *mr, | |
3220 | struct Object *owner, | |
3221 | const MemoryRegionOps *ops, | |
3222 | void *opaque, | |
3223 | const char *name, | |
3224 | uint64_t size, | |
3225 | Error **errp) | |
3226 | { | |
3227 | DeviceState *owner_dev; | |
3228 | Error *err = NULL; | |
3229 | ||
3230 | memory_region_init_rom_device_nomigrate(mr, owner, ops, opaque, | |
3231 | name, size, &err); | |
3232 | if (err) { | |
3233 | error_propagate(errp, err); | |
3234 | return; | |
3235 | } | |
3236 | /* This will assert if owner is neither NULL nor a DeviceState. | |
3237 | * We only want the owner here for the purposes of defining a | |
3238 | * unique name for migration. TODO: Ideally we should implement | |
3239 | * a naming scheme for Objects which are not DeviceStates, in | |
3240 | * which case we can relax this restriction. | |
3241 | */ | |
3242 | owner_dev = DEVICE(owner); | |
3243 | vmstate_register_ram(mr, owner_dev); | |
3244 | } | |
3245 | ||
b4fefef9 PC |
3246 | static const TypeInfo memory_region_info = { |
3247 | .parent = TYPE_OBJECT, | |
3248 | .name = TYPE_MEMORY_REGION, | |
1b53ecd9 | 3249 | .class_size = sizeof(MemoryRegionClass), |
b4fefef9 PC |
3250 | .instance_size = sizeof(MemoryRegion), |
3251 | .instance_init = memory_region_initfn, | |
3252 | .instance_finalize = memory_region_finalize, | |
3253 | }; | |
3254 | ||
3df9d748 AK |
3255 | static const TypeInfo iommu_memory_region_info = { |
3256 | .parent = TYPE_MEMORY_REGION, | |
3257 | .name = TYPE_IOMMU_MEMORY_REGION, | |
1221a474 | 3258 | .class_size = sizeof(IOMMUMemoryRegionClass), |
3df9d748 AK |
3259 | .instance_size = sizeof(IOMMUMemoryRegion), |
3260 | .instance_init = iommu_memory_region_initfn, | |
1221a474 | 3261 | .abstract = true, |
3df9d748 AK |
3262 | }; |
3263 | ||
b4fefef9 PC |
3264 | static void memory_register_types(void) |
3265 | { | |
3266 | type_register_static(&memory_region_info); | |
3df9d748 | 3267 | type_register_static(&iommu_memory_region_info); |
b4fefef9 PC |
3268 | } |
3269 | ||
3270 | type_init(memory_register_types) |