]>
Commit | Line | Data |
---|---|---|
093bc2cd AK |
1 | /* |
2 | * Physical memory management | |
3 | * | |
4 | * Copyright 2011 Red Hat, Inc. and/or its affiliates | |
5 | * | |
6 | * Authors: | |
7 | * Avi Kivity <[email protected]> | |
8 | * | |
9 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
10 | * the COPYING file in the top-level directory. | |
11 | * | |
12 | */ | |
13 | ||
14 | #include "memory.h" | |
1c0ffa58 | 15 | #include "exec-memory.h" |
658b2224 | 16 | #include "ioport.h" |
74901c3b | 17 | #include "bitops.h" |
3e9d69e7 | 18 | #include "kvm.h" |
093bc2cd AK |
19 | #include <assert.h> |
20 | ||
4ef4db86 AK |
21 | unsigned memory_region_transaction_depth = 0; |
22 | ||
093bc2cd AK |
23 | typedef struct AddrRange AddrRange; |
24 | ||
8417cebf AK |
25 | /* |
26 | * Note using signed integers limits us to physical addresses at most | |
27 | * 63 bits wide. They are needed for negative offsetting in aliases | |
28 | * (large MemoryRegion::alias_offset). | |
29 | */ | |
093bc2cd | 30 | struct AddrRange { |
08dafab4 AK |
31 | Int128 start; |
32 | Int128 size; | |
093bc2cd AK |
33 | }; |
34 | ||
08dafab4 | 35 | static AddrRange addrrange_make(Int128 start, Int128 size) |
093bc2cd AK |
36 | { |
37 | return (AddrRange) { start, size }; | |
38 | } | |
39 | ||
40 | static bool addrrange_equal(AddrRange r1, AddrRange r2) | |
41 | { | |
08dafab4 | 42 | return int128_eq(r1.start, r2.start) && int128_eq(r1.size, r2.size); |
093bc2cd AK |
43 | } |
44 | ||
08dafab4 | 45 | static Int128 addrrange_end(AddrRange r) |
093bc2cd | 46 | { |
08dafab4 | 47 | return int128_add(r.start, r.size); |
093bc2cd AK |
48 | } |
49 | ||
08dafab4 | 50 | static AddrRange addrrange_shift(AddrRange range, Int128 delta) |
093bc2cd | 51 | { |
08dafab4 | 52 | int128_addto(&range.start, delta); |
093bc2cd AK |
53 | return range; |
54 | } | |
55 | ||
08dafab4 AK |
56 | static bool addrrange_contains(AddrRange range, Int128 addr) |
57 | { | |
58 | return int128_ge(addr, range.start) | |
59 | && int128_lt(addr, addrrange_end(range)); | |
60 | } | |
61 | ||
093bc2cd AK |
62 | static bool addrrange_intersects(AddrRange r1, AddrRange r2) |
63 | { | |
08dafab4 AK |
64 | return addrrange_contains(r1, r2.start) |
65 | || addrrange_contains(r2, r1.start); | |
093bc2cd AK |
66 | } |
67 | ||
68 | static AddrRange addrrange_intersection(AddrRange r1, AddrRange r2) | |
69 | { | |
08dafab4 AK |
70 | Int128 start = int128_max(r1.start, r2.start); |
71 | Int128 end = int128_min(addrrange_end(r1), addrrange_end(r2)); | |
72 | return addrrange_make(start, int128_sub(end, start)); | |
093bc2cd AK |
73 | } |
74 | ||
75 | struct CoalescedMemoryRange { | |
76 | AddrRange addr; | |
77 | QTAILQ_ENTRY(CoalescedMemoryRange) link; | |
78 | }; | |
79 | ||
3e9d69e7 AK |
80 | struct MemoryRegionIoeventfd { |
81 | AddrRange addr; | |
82 | bool match_data; | |
83 | uint64_t data; | |
84 | int fd; | |
85 | }; | |
86 | ||
87 | static bool memory_region_ioeventfd_before(MemoryRegionIoeventfd a, | |
88 | MemoryRegionIoeventfd b) | |
89 | { | |
08dafab4 | 90 | if (int128_lt(a.addr.start, b.addr.start)) { |
3e9d69e7 | 91 | return true; |
08dafab4 | 92 | } else if (int128_gt(a.addr.start, b.addr.start)) { |
3e9d69e7 | 93 | return false; |
08dafab4 | 94 | } else if (int128_lt(a.addr.size, b.addr.size)) { |
3e9d69e7 | 95 | return true; |
08dafab4 | 96 | } else if (int128_gt(a.addr.size, b.addr.size)) { |
3e9d69e7 AK |
97 | return false; |
98 | } else if (a.match_data < b.match_data) { | |
99 | return true; | |
100 | } else if (a.match_data > b.match_data) { | |
101 | return false; | |
102 | } else if (a.match_data) { | |
103 | if (a.data < b.data) { | |
104 | return true; | |
105 | } else if (a.data > b.data) { | |
106 | return false; | |
107 | } | |
108 | } | |
109 | if (a.fd < b.fd) { | |
110 | return true; | |
111 | } else if (a.fd > b.fd) { | |
112 | return false; | |
113 | } | |
114 | return false; | |
115 | } | |
116 | ||
117 | static bool memory_region_ioeventfd_equal(MemoryRegionIoeventfd a, | |
118 | MemoryRegionIoeventfd b) | |
119 | { | |
120 | return !memory_region_ioeventfd_before(a, b) | |
121 | && !memory_region_ioeventfd_before(b, a); | |
122 | } | |
123 | ||
093bc2cd AK |
124 | typedef struct FlatRange FlatRange; |
125 | typedef struct FlatView FlatView; | |
126 | ||
127 | /* Range of memory in the global map. Addresses are absolute. */ | |
128 | struct FlatRange { | |
129 | MemoryRegion *mr; | |
130 | target_phys_addr_t offset_in_region; | |
131 | AddrRange addr; | |
5a583347 | 132 | uint8_t dirty_log_mask; |
d0a9b5bc | 133 | bool readable; |
fb1cd6f9 | 134 | bool readonly; |
093bc2cd AK |
135 | }; |
136 | ||
137 | /* Flattened global view of current active memory hierarchy. Kept in sorted | |
138 | * order. | |
139 | */ | |
140 | struct FlatView { | |
141 | FlatRange *ranges; | |
142 | unsigned nr; | |
143 | unsigned nr_allocated; | |
144 | }; | |
145 | ||
cc31e6e7 AK |
146 | typedef struct AddressSpace AddressSpace; |
147 | typedef struct AddressSpaceOps AddressSpaceOps; | |
148 | ||
149 | /* A system address space - I/O, memory, etc. */ | |
150 | struct AddressSpace { | |
151 | const AddressSpaceOps *ops; | |
152 | MemoryRegion *root; | |
153 | FlatView current_map; | |
3e9d69e7 AK |
154 | int ioeventfd_nb; |
155 | MemoryRegionIoeventfd *ioeventfds; | |
cc31e6e7 AK |
156 | }; |
157 | ||
158 | struct AddressSpaceOps { | |
159 | void (*range_add)(AddressSpace *as, FlatRange *fr); | |
160 | void (*range_del)(AddressSpace *as, FlatRange *fr); | |
161 | void (*log_start)(AddressSpace *as, FlatRange *fr); | |
162 | void (*log_stop)(AddressSpace *as, FlatRange *fr); | |
3e9d69e7 AK |
163 | void (*ioeventfd_add)(AddressSpace *as, MemoryRegionIoeventfd *fd); |
164 | void (*ioeventfd_del)(AddressSpace *as, MemoryRegionIoeventfd *fd); | |
cc31e6e7 AK |
165 | }; |
166 | ||
093bc2cd AK |
167 | #define FOR_EACH_FLAT_RANGE(var, view) \ |
168 | for (var = (view)->ranges; var < (view)->ranges + (view)->nr; ++var) | |
169 | ||
093bc2cd AK |
170 | static bool flatrange_equal(FlatRange *a, FlatRange *b) |
171 | { | |
172 | return a->mr == b->mr | |
173 | && addrrange_equal(a->addr, b->addr) | |
d0a9b5bc | 174 | && a->offset_in_region == b->offset_in_region |
fb1cd6f9 AK |
175 | && a->readable == b->readable |
176 | && a->readonly == b->readonly; | |
093bc2cd AK |
177 | } |
178 | ||
179 | static void flatview_init(FlatView *view) | |
180 | { | |
181 | view->ranges = NULL; | |
182 | view->nr = 0; | |
183 | view->nr_allocated = 0; | |
184 | } | |
185 | ||
186 | /* Insert a range into a given position. Caller is responsible for maintaining | |
187 | * sorting order. | |
188 | */ | |
189 | static void flatview_insert(FlatView *view, unsigned pos, FlatRange *range) | |
190 | { | |
191 | if (view->nr == view->nr_allocated) { | |
192 | view->nr_allocated = MAX(2 * view->nr, 10); | |
7267c094 | 193 | view->ranges = g_realloc(view->ranges, |
093bc2cd AK |
194 | view->nr_allocated * sizeof(*view->ranges)); |
195 | } | |
196 | memmove(view->ranges + pos + 1, view->ranges + pos, | |
197 | (view->nr - pos) * sizeof(FlatRange)); | |
198 | view->ranges[pos] = *range; | |
199 | ++view->nr; | |
200 | } | |
201 | ||
202 | static void flatview_destroy(FlatView *view) | |
203 | { | |
7267c094 | 204 | g_free(view->ranges); |
093bc2cd AK |
205 | } |
206 | ||
3d8e6bf9 AK |
207 | static bool can_merge(FlatRange *r1, FlatRange *r2) |
208 | { | |
08dafab4 | 209 | return int128_eq(addrrange_end(r1->addr), r2->addr.start) |
3d8e6bf9 | 210 | && r1->mr == r2->mr |
08dafab4 AK |
211 | && int128_eq(int128_add(int128_make64(r1->offset_in_region), |
212 | r1->addr.size), | |
213 | int128_make64(r2->offset_in_region)) | |
d0a9b5bc | 214 | && r1->dirty_log_mask == r2->dirty_log_mask |
fb1cd6f9 AK |
215 | && r1->readable == r2->readable |
216 | && r1->readonly == r2->readonly; | |
3d8e6bf9 AK |
217 | } |
218 | ||
219 | /* Attempt to simplify a view by merging ajacent ranges */ | |
220 | static void flatview_simplify(FlatView *view) | |
221 | { | |
222 | unsigned i, j; | |
223 | ||
224 | i = 0; | |
225 | while (i < view->nr) { | |
226 | j = i + 1; | |
227 | while (j < view->nr | |
228 | && can_merge(&view->ranges[j-1], &view->ranges[j])) { | |
08dafab4 | 229 | int128_addto(&view->ranges[i].addr.size, view->ranges[j].addr.size); |
3d8e6bf9 AK |
230 | ++j; |
231 | } | |
232 | ++i; | |
233 | memmove(&view->ranges[i], &view->ranges[j], | |
234 | (view->nr - j) * sizeof(view->ranges[j])); | |
235 | view->nr -= j - i; | |
236 | } | |
237 | } | |
238 | ||
164a4dcd AK |
239 | static void memory_region_read_accessor(void *opaque, |
240 | target_phys_addr_t addr, | |
241 | uint64_t *value, | |
242 | unsigned size, | |
243 | unsigned shift, | |
244 | uint64_t mask) | |
245 | { | |
246 | MemoryRegion *mr = opaque; | |
247 | uint64_t tmp; | |
248 | ||
249 | tmp = mr->ops->read(mr->opaque, addr, size); | |
250 | *value |= (tmp & mask) << shift; | |
251 | } | |
252 | ||
253 | static void memory_region_write_accessor(void *opaque, | |
254 | target_phys_addr_t addr, | |
255 | uint64_t *value, | |
256 | unsigned size, | |
257 | unsigned shift, | |
258 | uint64_t mask) | |
259 | { | |
260 | MemoryRegion *mr = opaque; | |
261 | uint64_t tmp; | |
262 | ||
263 | tmp = (*value >> shift) & mask; | |
264 | mr->ops->write(mr->opaque, addr, tmp, size); | |
265 | } | |
266 | ||
267 | static void access_with_adjusted_size(target_phys_addr_t addr, | |
268 | uint64_t *value, | |
269 | unsigned size, | |
270 | unsigned access_size_min, | |
271 | unsigned access_size_max, | |
272 | void (*access)(void *opaque, | |
273 | target_phys_addr_t addr, | |
274 | uint64_t *value, | |
275 | unsigned size, | |
276 | unsigned shift, | |
277 | uint64_t mask), | |
278 | void *opaque) | |
279 | { | |
280 | uint64_t access_mask; | |
281 | unsigned access_size; | |
282 | unsigned i; | |
283 | ||
284 | if (!access_size_min) { | |
285 | access_size_min = 1; | |
286 | } | |
287 | if (!access_size_max) { | |
288 | access_size_max = 4; | |
289 | } | |
290 | access_size = MAX(MIN(size, access_size_max), access_size_min); | |
291 | access_mask = -1ULL >> (64 - access_size * 8); | |
292 | for (i = 0; i < size; i += access_size) { | |
293 | /* FIXME: big-endian support */ | |
294 | access(opaque, addr + i, value, access_size, i * 8, access_mask); | |
295 | } | |
296 | } | |
297 | ||
16ef61c9 AK |
298 | static void memory_region_prepare_ram_addr(MemoryRegion *mr); |
299 | ||
cc31e6e7 AK |
300 | static void as_memory_range_add(AddressSpace *as, FlatRange *fr) |
301 | { | |
302 | ram_addr_t phys_offset, region_offset; | |
303 | ||
16ef61c9 AK |
304 | memory_region_prepare_ram_addr(fr->mr); |
305 | ||
cc31e6e7 AK |
306 | phys_offset = fr->mr->ram_addr; |
307 | region_offset = fr->offset_in_region; | |
308 | /* cpu_register_physical_memory_log() wants region_offset for | |
309 | * mmio, but prefers offseting phys_offset for RAM. Humour it. | |
310 | */ | |
311 | if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM) { | |
312 | phys_offset += region_offset; | |
313 | region_offset = 0; | |
314 | } | |
315 | ||
d0a9b5bc | 316 | if (!fr->readable) { |
b5fe14cc | 317 | phys_offset &= ~TARGET_PAGE_MASK & ~IO_MEM_ROMD; |
d0a9b5bc AK |
318 | } |
319 | ||
fb1cd6f9 AK |
320 | if (fr->readonly) { |
321 | phys_offset |= IO_MEM_ROM; | |
322 | } | |
323 | ||
08dafab4 AK |
324 | cpu_register_physical_memory_log(int128_get64(fr->addr.start), |
325 | int128_get64(fr->addr.size), | |
cc31e6e7 AK |
326 | phys_offset, |
327 | region_offset, | |
328 | fr->dirty_log_mask); | |
329 | } | |
330 | ||
331 | static void as_memory_range_del(AddressSpace *as, FlatRange *fr) | |
332 | { | |
39b796f2 | 333 | if (fr->dirty_log_mask) { |
08dafab4 AK |
334 | Int128 end = addrrange_end(fr->addr); |
335 | cpu_physical_sync_dirty_bitmap(int128_get64(fr->addr.start), | |
336 | int128_get64(end)); | |
39b796f2 | 337 | } |
08dafab4 AK |
338 | cpu_register_physical_memory(int128_get64(fr->addr.start), |
339 | int128_get64(fr->addr.size), | |
cc31e6e7 AK |
340 | IO_MEM_UNASSIGNED); |
341 | } | |
342 | ||
343 | static void as_memory_log_start(AddressSpace *as, FlatRange *fr) | |
344 | { | |
08dafab4 AK |
345 | cpu_physical_log_start(int128_get64(fr->addr.start), |
346 | int128_get64(fr->addr.size)); | |
cc31e6e7 AK |
347 | } |
348 | ||
349 | static void as_memory_log_stop(AddressSpace *as, FlatRange *fr) | |
350 | { | |
08dafab4 AK |
351 | cpu_physical_log_stop(int128_get64(fr->addr.start), |
352 | int128_get64(fr->addr.size)); | |
cc31e6e7 AK |
353 | } |
354 | ||
3e9d69e7 AK |
355 | static void as_memory_ioeventfd_add(AddressSpace *as, MemoryRegionIoeventfd *fd) |
356 | { | |
357 | int r; | |
358 | ||
08dafab4 | 359 | assert(fd->match_data && int128_get64(fd->addr.size) == 4); |
3e9d69e7 | 360 | |
08dafab4 AK |
361 | r = kvm_set_ioeventfd_mmio_long(fd->fd, int128_get64(fd->addr.start), |
362 | fd->data, true); | |
3e9d69e7 AK |
363 | if (r < 0) { |
364 | abort(); | |
365 | } | |
366 | } | |
367 | ||
368 | static void as_memory_ioeventfd_del(AddressSpace *as, MemoryRegionIoeventfd *fd) | |
369 | { | |
370 | int r; | |
371 | ||
08dafab4 AK |
372 | r = kvm_set_ioeventfd_mmio_long(fd->fd, int128_get64(fd->addr.start), |
373 | fd->data, false); | |
3e9d69e7 AK |
374 | if (r < 0) { |
375 | abort(); | |
376 | } | |
377 | } | |
378 | ||
cc31e6e7 AK |
379 | static const AddressSpaceOps address_space_ops_memory = { |
380 | .range_add = as_memory_range_add, | |
381 | .range_del = as_memory_range_del, | |
382 | .log_start = as_memory_log_start, | |
383 | .log_stop = as_memory_log_stop, | |
3e9d69e7 AK |
384 | .ioeventfd_add = as_memory_ioeventfd_add, |
385 | .ioeventfd_del = as_memory_ioeventfd_del, | |
cc31e6e7 AK |
386 | }; |
387 | ||
388 | static AddressSpace address_space_memory = { | |
389 | .ops = &address_space_ops_memory, | |
390 | }; | |
391 | ||
627a0e90 AK |
392 | static const MemoryRegionPortio *find_portio(MemoryRegion *mr, uint64_t offset, |
393 | unsigned width, bool write) | |
394 | { | |
395 | const MemoryRegionPortio *mrp; | |
396 | ||
397 | for (mrp = mr->ops->old_portio; mrp->size; ++mrp) { | |
398 | if (offset >= mrp->offset && offset < mrp->offset + mrp->len | |
399 | && width == mrp->size | |
400 | && (write ? (bool)mrp->write : (bool)mrp->read)) { | |
401 | return mrp; | |
402 | } | |
403 | } | |
404 | return NULL; | |
405 | } | |
406 | ||
658b2224 AK |
407 | static void memory_region_iorange_read(IORange *iorange, |
408 | uint64_t offset, | |
409 | unsigned width, | |
410 | uint64_t *data) | |
411 | { | |
412 | MemoryRegion *mr = container_of(iorange, MemoryRegion, iorange); | |
413 | ||
627a0e90 AK |
414 | if (mr->ops->old_portio) { |
415 | const MemoryRegionPortio *mrp = find_portio(mr, offset, width, false); | |
416 | ||
417 | *data = ((uint64_t)1 << (width * 8)) - 1; | |
418 | if (mrp) { | |
6bf9fd43 | 419 | *data = mrp->read(mr->opaque, offset + mr->offset); |
03808f58 JK |
420 | } else if (width == 2) { |
421 | mrp = find_portio(mr, offset, 1, false); | |
422 | assert(mrp); | |
423 | *data = mrp->read(mr->opaque, offset + mr->offset) | | |
424 | (mrp->read(mr->opaque, offset + mr->offset + 1) << 8); | |
627a0e90 AK |
425 | } |
426 | return; | |
427 | } | |
3a130f4e | 428 | *data = 0; |
6bf9fd43 | 429 | access_with_adjusted_size(offset + mr->offset, data, width, |
3a130f4e AK |
430 | mr->ops->impl.min_access_size, |
431 | mr->ops->impl.max_access_size, | |
432 | memory_region_read_accessor, mr); | |
658b2224 AK |
433 | } |
434 | ||
435 | static void memory_region_iorange_write(IORange *iorange, | |
436 | uint64_t offset, | |
437 | unsigned width, | |
438 | uint64_t data) | |
439 | { | |
440 | MemoryRegion *mr = container_of(iorange, MemoryRegion, iorange); | |
441 | ||
627a0e90 AK |
442 | if (mr->ops->old_portio) { |
443 | const MemoryRegionPortio *mrp = find_portio(mr, offset, width, true); | |
444 | ||
445 | if (mrp) { | |
6bf9fd43 | 446 | mrp->write(mr->opaque, offset + mr->offset, data); |
03808f58 JK |
447 | } else if (width == 2) { |
448 | mrp = find_portio(mr, offset, 1, false); | |
449 | assert(mrp); | |
450 | mrp->write(mr->opaque, offset + mr->offset, data & 0xff); | |
451 | mrp->write(mr->opaque, offset + mr->offset + 1, data >> 8); | |
627a0e90 AK |
452 | } |
453 | return; | |
454 | } | |
6bf9fd43 | 455 | access_with_adjusted_size(offset + mr->offset, &data, width, |
3a130f4e AK |
456 | mr->ops->impl.min_access_size, |
457 | mr->ops->impl.max_access_size, | |
458 | memory_region_write_accessor, mr); | |
658b2224 AK |
459 | } |
460 | ||
461 | static const IORangeOps memory_region_iorange_ops = { | |
462 | .read = memory_region_iorange_read, | |
463 | .write = memory_region_iorange_write, | |
464 | }; | |
465 | ||
466 | static void as_io_range_add(AddressSpace *as, FlatRange *fr) | |
467 | { | |
468 | iorange_init(&fr->mr->iorange, &memory_region_iorange_ops, | |
08dafab4 | 469 | int128_get64(fr->addr.start), int128_get64(fr->addr.size)); |
658b2224 AK |
470 | ioport_register(&fr->mr->iorange); |
471 | } | |
472 | ||
473 | static void as_io_range_del(AddressSpace *as, FlatRange *fr) | |
474 | { | |
08dafab4 AK |
475 | isa_unassign_ioport(int128_get64(fr->addr.start), |
476 | int128_get64(fr->addr.size)); | |
658b2224 AK |
477 | } |
478 | ||
3e9d69e7 AK |
479 | static void as_io_ioeventfd_add(AddressSpace *as, MemoryRegionIoeventfd *fd) |
480 | { | |
481 | int r; | |
482 | ||
08dafab4 | 483 | assert(fd->match_data && int128_get64(fd->addr.size) == 2); |
3e9d69e7 | 484 | |
08dafab4 AK |
485 | r = kvm_set_ioeventfd_pio_word(fd->fd, int128_get64(fd->addr.start), |
486 | fd->data, true); | |
3e9d69e7 AK |
487 | if (r < 0) { |
488 | abort(); | |
489 | } | |
490 | } | |
491 | ||
492 | static void as_io_ioeventfd_del(AddressSpace *as, MemoryRegionIoeventfd *fd) | |
493 | { | |
494 | int r; | |
495 | ||
08dafab4 AK |
496 | r = kvm_set_ioeventfd_pio_word(fd->fd, int128_get64(fd->addr.start), |
497 | fd->data, false); | |
3e9d69e7 AK |
498 | if (r < 0) { |
499 | abort(); | |
500 | } | |
501 | } | |
502 | ||
658b2224 AK |
503 | static const AddressSpaceOps address_space_ops_io = { |
504 | .range_add = as_io_range_add, | |
505 | .range_del = as_io_range_del, | |
3e9d69e7 AK |
506 | .ioeventfd_add = as_io_ioeventfd_add, |
507 | .ioeventfd_del = as_io_ioeventfd_del, | |
658b2224 AK |
508 | }; |
509 | ||
510 | static AddressSpace address_space_io = { | |
511 | .ops = &address_space_ops_io, | |
512 | }; | |
513 | ||
093bc2cd AK |
514 | /* Render a memory region into the global view. Ranges in @view obscure |
515 | * ranges in @mr. | |
516 | */ | |
517 | static void render_memory_region(FlatView *view, | |
518 | MemoryRegion *mr, | |
08dafab4 | 519 | Int128 base, |
fb1cd6f9 AK |
520 | AddrRange clip, |
521 | bool readonly) | |
093bc2cd AK |
522 | { |
523 | MemoryRegion *subregion; | |
524 | unsigned i; | |
525 | target_phys_addr_t offset_in_region; | |
08dafab4 AK |
526 | Int128 remain; |
527 | Int128 now; | |
093bc2cd AK |
528 | FlatRange fr; |
529 | AddrRange tmp; | |
530 | ||
6bba19ba AK |
531 | if (!mr->enabled) { |
532 | return; | |
533 | } | |
534 | ||
08dafab4 | 535 | int128_addto(&base, int128_make64(mr->addr)); |
fb1cd6f9 | 536 | readonly |= mr->readonly; |
093bc2cd AK |
537 | |
538 | tmp = addrrange_make(base, mr->size); | |
539 | ||
540 | if (!addrrange_intersects(tmp, clip)) { | |
541 | return; | |
542 | } | |
543 | ||
544 | clip = addrrange_intersection(tmp, clip); | |
545 | ||
546 | if (mr->alias) { | |
08dafab4 AK |
547 | int128_subfrom(&base, int128_make64(mr->alias->addr)); |
548 | int128_subfrom(&base, int128_make64(mr->alias_offset)); | |
fb1cd6f9 | 549 | render_memory_region(view, mr->alias, base, clip, readonly); |
093bc2cd AK |
550 | return; |
551 | } | |
552 | ||
553 | /* Render subregions in priority order. */ | |
554 | QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) { | |
fb1cd6f9 | 555 | render_memory_region(view, subregion, base, clip, readonly); |
093bc2cd AK |
556 | } |
557 | ||
14a3c10a | 558 | if (!mr->terminates) { |
093bc2cd AK |
559 | return; |
560 | } | |
561 | ||
08dafab4 | 562 | offset_in_region = int128_get64(int128_sub(clip.start, base)); |
093bc2cd AK |
563 | base = clip.start; |
564 | remain = clip.size; | |
565 | ||
566 | /* Render the region itself into any gaps left by the current view. */ | |
08dafab4 AK |
567 | for (i = 0; i < view->nr && int128_nz(remain); ++i) { |
568 | if (int128_ge(base, addrrange_end(view->ranges[i].addr))) { | |
093bc2cd AK |
569 | continue; |
570 | } | |
08dafab4 AK |
571 | if (int128_lt(base, view->ranges[i].addr.start)) { |
572 | now = int128_min(remain, | |
573 | int128_sub(view->ranges[i].addr.start, base)); | |
093bc2cd AK |
574 | fr.mr = mr; |
575 | fr.offset_in_region = offset_in_region; | |
576 | fr.addr = addrrange_make(base, now); | |
5a583347 | 577 | fr.dirty_log_mask = mr->dirty_log_mask; |
d0a9b5bc | 578 | fr.readable = mr->readable; |
fb1cd6f9 | 579 | fr.readonly = readonly; |
093bc2cd AK |
580 | flatview_insert(view, i, &fr); |
581 | ++i; | |
08dafab4 AK |
582 | int128_addto(&base, now); |
583 | offset_in_region += int128_get64(now); | |
584 | int128_subfrom(&remain, now); | |
093bc2cd | 585 | } |
08dafab4 AK |
586 | if (int128_eq(base, view->ranges[i].addr.start)) { |
587 | now = int128_min(remain, view->ranges[i].addr.size); | |
588 | int128_addto(&base, now); | |
589 | offset_in_region += int128_get64(now); | |
590 | int128_subfrom(&remain, now); | |
093bc2cd AK |
591 | } |
592 | } | |
08dafab4 | 593 | if (int128_nz(remain)) { |
093bc2cd AK |
594 | fr.mr = mr; |
595 | fr.offset_in_region = offset_in_region; | |
596 | fr.addr = addrrange_make(base, remain); | |
5a583347 | 597 | fr.dirty_log_mask = mr->dirty_log_mask; |
d0a9b5bc | 598 | fr.readable = mr->readable; |
fb1cd6f9 | 599 | fr.readonly = readonly; |
093bc2cd AK |
600 | flatview_insert(view, i, &fr); |
601 | } | |
602 | } | |
603 | ||
604 | /* Render a memory topology into a list of disjoint absolute ranges. */ | |
605 | static FlatView generate_memory_topology(MemoryRegion *mr) | |
606 | { | |
607 | FlatView view; | |
608 | ||
609 | flatview_init(&view); | |
610 | ||
08dafab4 AK |
611 | render_memory_region(&view, mr, int128_zero(), |
612 | addrrange_make(int128_zero(), int128_2_64()), false); | |
3d8e6bf9 | 613 | flatview_simplify(&view); |
093bc2cd AK |
614 | |
615 | return view; | |
616 | } | |
617 | ||
3e9d69e7 AK |
618 | static void address_space_add_del_ioeventfds(AddressSpace *as, |
619 | MemoryRegionIoeventfd *fds_new, | |
620 | unsigned fds_new_nb, | |
621 | MemoryRegionIoeventfd *fds_old, | |
622 | unsigned fds_old_nb) | |
623 | { | |
624 | unsigned iold, inew; | |
625 | ||
626 | /* Generate a symmetric difference of the old and new fd sets, adding | |
627 | * and deleting as necessary. | |
628 | */ | |
629 | ||
630 | iold = inew = 0; | |
631 | while (iold < fds_old_nb || inew < fds_new_nb) { | |
632 | if (iold < fds_old_nb | |
633 | && (inew == fds_new_nb | |
634 | || memory_region_ioeventfd_before(fds_old[iold], | |
635 | fds_new[inew]))) { | |
636 | as->ops->ioeventfd_del(as, &fds_old[iold]); | |
637 | ++iold; | |
638 | } else if (inew < fds_new_nb | |
639 | && (iold == fds_old_nb | |
640 | || memory_region_ioeventfd_before(fds_new[inew], | |
641 | fds_old[iold]))) { | |
642 | as->ops->ioeventfd_add(as, &fds_new[inew]); | |
643 | ++inew; | |
644 | } else { | |
645 | ++iold; | |
646 | ++inew; | |
647 | } | |
648 | } | |
649 | } | |
650 | ||
651 | static void address_space_update_ioeventfds(AddressSpace *as) | |
652 | { | |
653 | FlatRange *fr; | |
654 | unsigned ioeventfd_nb = 0; | |
655 | MemoryRegionIoeventfd *ioeventfds = NULL; | |
656 | AddrRange tmp; | |
657 | unsigned i; | |
658 | ||
659 | FOR_EACH_FLAT_RANGE(fr, &as->current_map) { | |
660 | for (i = 0; i < fr->mr->ioeventfd_nb; ++i) { | |
661 | tmp = addrrange_shift(fr->mr->ioeventfds[i].addr, | |
08dafab4 AK |
662 | int128_sub(fr->addr.start, |
663 | int128_make64(fr->offset_in_region))); | |
3e9d69e7 AK |
664 | if (addrrange_intersects(fr->addr, tmp)) { |
665 | ++ioeventfd_nb; | |
7267c094 | 666 | ioeventfds = g_realloc(ioeventfds, |
3e9d69e7 AK |
667 | ioeventfd_nb * sizeof(*ioeventfds)); |
668 | ioeventfds[ioeventfd_nb-1] = fr->mr->ioeventfds[i]; | |
669 | ioeventfds[ioeventfd_nb-1].addr = tmp; | |
670 | } | |
671 | } | |
672 | } | |
673 | ||
674 | address_space_add_del_ioeventfds(as, ioeventfds, ioeventfd_nb, | |
675 | as->ioeventfds, as->ioeventfd_nb); | |
676 | ||
7267c094 | 677 | g_free(as->ioeventfds); |
3e9d69e7 AK |
678 | as->ioeventfds = ioeventfds; |
679 | as->ioeventfd_nb = ioeventfd_nb; | |
680 | } | |
681 | ||
b8af1afb AK |
682 | static void address_space_update_topology_pass(AddressSpace *as, |
683 | FlatView old_view, | |
684 | FlatView new_view, | |
685 | bool adding) | |
093bc2cd | 686 | { |
093bc2cd AK |
687 | unsigned iold, inew; |
688 | FlatRange *frold, *frnew; | |
093bc2cd AK |
689 | |
690 | /* Generate a symmetric difference of the old and new memory maps. | |
691 | * Kill ranges in the old map, and instantiate ranges in the new map. | |
692 | */ | |
693 | iold = inew = 0; | |
694 | while (iold < old_view.nr || inew < new_view.nr) { | |
695 | if (iold < old_view.nr) { | |
696 | frold = &old_view.ranges[iold]; | |
697 | } else { | |
698 | frold = NULL; | |
699 | } | |
700 | if (inew < new_view.nr) { | |
701 | frnew = &new_view.ranges[inew]; | |
702 | } else { | |
703 | frnew = NULL; | |
704 | } | |
705 | ||
706 | if (frold | |
707 | && (!frnew | |
08dafab4 AK |
708 | || int128_lt(frold->addr.start, frnew->addr.start) |
709 | || (int128_eq(frold->addr.start, frnew->addr.start) | |
093bc2cd AK |
710 | && !flatrange_equal(frold, frnew)))) { |
711 | /* In old, but (not in new, or in new but attributes changed). */ | |
712 | ||
b8af1afb AK |
713 | if (!adding) { |
714 | as->ops->range_del(as, frold); | |
715 | } | |
716 | ||
093bc2cd AK |
717 | ++iold; |
718 | } else if (frold && frnew && flatrange_equal(frold, frnew)) { | |
719 | /* In both (logging may have changed) */ | |
720 | ||
b8af1afb AK |
721 | if (adding) { |
722 | if (frold->dirty_log_mask && !frnew->dirty_log_mask) { | |
723 | as->ops->log_stop(as, frnew); | |
724 | } else if (frnew->dirty_log_mask && !frold->dirty_log_mask) { | |
725 | as->ops->log_start(as, frnew); | |
726 | } | |
5a583347 AK |
727 | } |
728 | ||
093bc2cd AK |
729 | ++iold; |
730 | ++inew; | |
093bc2cd AK |
731 | } else { |
732 | /* In new */ | |
733 | ||
b8af1afb AK |
734 | if (adding) { |
735 | as->ops->range_add(as, frnew); | |
736 | } | |
737 | ||
093bc2cd AK |
738 | ++inew; |
739 | } | |
740 | } | |
b8af1afb AK |
741 | } |
742 | ||
743 | ||
744 | static void address_space_update_topology(AddressSpace *as) | |
745 | { | |
746 | FlatView old_view = as->current_map; | |
747 | FlatView new_view = generate_memory_topology(as->root); | |
748 | ||
749 | address_space_update_topology_pass(as, old_view, new_view, false); | |
750 | address_space_update_topology_pass(as, old_view, new_view, true); | |
751 | ||
cc31e6e7 | 752 | as->current_map = new_view; |
093bc2cd | 753 | flatview_destroy(&old_view); |
3e9d69e7 | 754 | address_space_update_ioeventfds(as); |
093bc2cd AK |
755 | } |
756 | ||
6bba19ba | 757 | static void memory_region_update_topology(MemoryRegion *mr) |
cc31e6e7 | 758 | { |
4ef4db86 AK |
759 | if (memory_region_transaction_depth) { |
760 | return; | |
761 | } | |
762 | ||
6bba19ba AK |
763 | if (mr && !mr->enabled) { |
764 | return; | |
765 | } | |
766 | ||
658b2224 AK |
767 | if (address_space_memory.root) { |
768 | address_space_update_topology(&address_space_memory); | |
769 | } | |
770 | if (address_space_io.root) { | |
771 | address_space_update_topology(&address_space_io); | |
772 | } | |
cc31e6e7 AK |
773 | } |
774 | ||
4ef4db86 AK |
775 | void memory_region_transaction_begin(void) |
776 | { | |
777 | ++memory_region_transaction_depth; | |
778 | } | |
779 | ||
780 | void memory_region_transaction_commit(void) | |
781 | { | |
782 | assert(memory_region_transaction_depth); | |
783 | --memory_region_transaction_depth; | |
6bba19ba | 784 | memory_region_update_topology(NULL); |
4ef4db86 AK |
785 | } |
786 | ||
545e92e0 AK |
787 | static void memory_region_destructor_none(MemoryRegion *mr) |
788 | { | |
789 | } | |
790 | ||
791 | static void memory_region_destructor_ram(MemoryRegion *mr) | |
792 | { | |
793 | qemu_ram_free(mr->ram_addr); | |
794 | } | |
795 | ||
796 | static void memory_region_destructor_ram_from_ptr(MemoryRegion *mr) | |
797 | { | |
798 | qemu_ram_free_from_ptr(mr->ram_addr); | |
799 | } | |
800 | ||
801 | static void memory_region_destructor_iomem(MemoryRegion *mr) | |
802 | { | |
803 | cpu_unregister_io_memory(mr->ram_addr); | |
804 | } | |
805 | ||
d0a9b5bc AK |
806 | static void memory_region_destructor_rom_device(MemoryRegion *mr) |
807 | { | |
808 | qemu_ram_free(mr->ram_addr & TARGET_PAGE_MASK); | |
809 | cpu_unregister_io_memory(mr->ram_addr & ~(TARGET_PAGE_MASK | IO_MEM_ROMD)); | |
810 | } | |
811 | ||
093bc2cd AK |
812 | void memory_region_init(MemoryRegion *mr, |
813 | const char *name, | |
814 | uint64_t size) | |
815 | { | |
816 | mr->ops = NULL; | |
817 | mr->parent = NULL; | |
08dafab4 AK |
818 | mr->size = int128_make64(size); |
819 | if (size == UINT64_MAX) { | |
820 | mr->size = int128_2_64(); | |
821 | } | |
093bc2cd AK |
822 | mr->addr = 0; |
823 | mr->offset = 0; | |
6bba19ba | 824 | mr->enabled = true; |
14a3c10a | 825 | mr->terminates = false; |
d0a9b5bc | 826 | mr->readable = true; |
fb1cd6f9 | 827 | mr->readonly = false; |
545e92e0 | 828 | mr->destructor = memory_region_destructor_none; |
093bc2cd AK |
829 | mr->priority = 0; |
830 | mr->may_overlap = false; | |
831 | mr->alias = NULL; | |
832 | QTAILQ_INIT(&mr->subregions); | |
833 | memset(&mr->subregions_link, 0, sizeof mr->subregions_link); | |
834 | QTAILQ_INIT(&mr->coalesced); | |
7267c094 | 835 | mr->name = g_strdup(name); |
5a583347 | 836 | mr->dirty_log_mask = 0; |
3e9d69e7 AK |
837 | mr->ioeventfd_nb = 0; |
838 | mr->ioeventfds = NULL; | |
093bc2cd AK |
839 | } |
840 | ||
841 | static bool memory_region_access_valid(MemoryRegion *mr, | |
842 | target_phys_addr_t addr, | |
897fa7cf AK |
843 | unsigned size, |
844 | bool is_write) | |
093bc2cd | 845 | { |
897fa7cf AK |
846 | if (mr->ops->valid.accepts |
847 | && !mr->ops->valid.accepts(mr->opaque, addr, size, is_write)) { | |
848 | return false; | |
849 | } | |
850 | ||
093bc2cd AK |
851 | if (!mr->ops->valid.unaligned && (addr & (size - 1))) { |
852 | return false; | |
853 | } | |
854 | ||
855 | /* Treat zero as compatibility all valid */ | |
856 | if (!mr->ops->valid.max_access_size) { | |
857 | return true; | |
858 | } | |
859 | ||
860 | if (size > mr->ops->valid.max_access_size | |
861 | || size < mr->ops->valid.min_access_size) { | |
862 | return false; | |
863 | } | |
864 | return true; | |
865 | } | |
866 | ||
867 | static uint32_t memory_region_read_thunk_n(void *_mr, | |
868 | target_phys_addr_t addr, | |
869 | unsigned size) | |
870 | { | |
871 | MemoryRegion *mr = _mr; | |
164a4dcd | 872 | uint64_t data = 0; |
093bc2cd | 873 | |
897fa7cf | 874 | if (!memory_region_access_valid(mr, addr, size, false)) { |
093bc2cd AK |
875 | return -1U; /* FIXME: better signalling */ |
876 | } | |
877 | ||
74901c3b AK |
878 | if (!mr->ops->read) { |
879 | return mr->ops->old_mmio.read[bitops_ffsl(size)](mr->opaque, addr); | |
880 | } | |
881 | ||
093bc2cd | 882 | /* FIXME: support unaligned access */ |
164a4dcd AK |
883 | access_with_adjusted_size(addr + mr->offset, &data, size, |
884 | mr->ops->impl.min_access_size, | |
885 | mr->ops->impl.max_access_size, | |
886 | memory_region_read_accessor, mr); | |
093bc2cd AK |
887 | |
888 | return data; | |
889 | } | |
890 | ||
891 | static void memory_region_write_thunk_n(void *_mr, | |
892 | target_phys_addr_t addr, | |
893 | unsigned size, | |
894 | uint64_t data) | |
895 | { | |
896 | MemoryRegion *mr = _mr; | |
093bc2cd | 897 | |
897fa7cf | 898 | if (!memory_region_access_valid(mr, addr, size, true)) { |
093bc2cd AK |
899 | return; /* FIXME: better signalling */ |
900 | } | |
901 | ||
74901c3b AK |
902 | if (!mr->ops->write) { |
903 | mr->ops->old_mmio.write[bitops_ffsl(size)](mr->opaque, addr, data); | |
904 | return; | |
905 | } | |
906 | ||
093bc2cd | 907 | /* FIXME: support unaligned access */ |
164a4dcd AK |
908 | access_with_adjusted_size(addr + mr->offset, &data, size, |
909 | mr->ops->impl.min_access_size, | |
910 | mr->ops->impl.max_access_size, | |
911 | memory_region_write_accessor, mr); | |
093bc2cd AK |
912 | } |
913 | ||
914 | static uint32_t memory_region_read_thunk_b(void *mr, target_phys_addr_t addr) | |
915 | { | |
916 | return memory_region_read_thunk_n(mr, addr, 1); | |
917 | } | |
918 | ||
919 | static uint32_t memory_region_read_thunk_w(void *mr, target_phys_addr_t addr) | |
920 | { | |
921 | return memory_region_read_thunk_n(mr, addr, 2); | |
922 | } | |
923 | ||
924 | static uint32_t memory_region_read_thunk_l(void *mr, target_phys_addr_t addr) | |
925 | { | |
926 | return memory_region_read_thunk_n(mr, addr, 4); | |
927 | } | |
928 | ||
929 | static void memory_region_write_thunk_b(void *mr, target_phys_addr_t addr, | |
930 | uint32_t data) | |
931 | { | |
932 | memory_region_write_thunk_n(mr, addr, 1, data); | |
933 | } | |
934 | ||
935 | static void memory_region_write_thunk_w(void *mr, target_phys_addr_t addr, | |
936 | uint32_t data) | |
937 | { | |
938 | memory_region_write_thunk_n(mr, addr, 2, data); | |
939 | } | |
940 | ||
941 | static void memory_region_write_thunk_l(void *mr, target_phys_addr_t addr, | |
942 | uint32_t data) | |
943 | { | |
944 | memory_region_write_thunk_n(mr, addr, 4, data); | |
945 | } | |
946 | ||
947 | static CPUReadMemoryFunc * const memory_region_read_thunk[] = { | |
948 | memory_region_read_thunk_b, | |
949 | memory_region_read_thunk_w, | |
950 | memory_region_read_thunk_l, | |
951 | }; | |
952 | ||
953 | static CPUWriteMemoryFunc * const memory_region_write_thunk[] = { | |
954 | memory_region_write_thunk_b, | |
955 | memory_region_write_thunk_w, | |
956 | memory_region_write_thunk_l, | |
957 | }; | |
958 | ||
16ef61c9 AK |
959 | static void memory_region_prepare_ram_addr(MemoryRegion *mr) |
960 | { | |
961 | if (mr->backend_registered) { | |
962 | return; | |
963 | } | |
964 | ||
545e92e0 | 965 | mr->destructor = memory_region_destructor_iomem; |
16ef61c9 AK |
966 | mr->ram_addr = cpu_register_io_memory(memory_region_read_thunk, |
967 | memory_region_write_thunk, | |
968 | mr, | |
969 | mr->ops->endianness); | |
970 | mr->backend_registered = true; | |
971 | } | |
972 | ||
093bc2cd AK |
973 | void memory_region_init_io(MemoryRegion *mr, |
974 | const MemoryRegionOps *ops, | |
975 | void *opaque, | |
976 | const char *name, | |
977 | uint64_t size) | |
978 | { | |
979 | memory_region_init(mr, name, size); | |
980 | mr->ops = ops; | |
981 | mr->opaque = opaque; | |
14a3c10a | 982 | mr->terminates = true; |
16ef61c9 | 983 | mr->backend_registered = false; |
093bc2cd AK |
984 | } |
985 | ||
986 | void memory_region_init_ram(MemoryRegion *mr, | |
987 | DeviceState *dev, | |
988 | const char *name, | |
989 | uint64_t size) | |
990 | { | |
991 | memory_region_init(mr, name, size); | |
14a3c10a | 992 | mr->terminates = true; |
545e92e0 | 993 | mr->destructor = memory_region_destructor_ram; |
093bc2cd | 994 | mr->ram_addr = qemu_ram_alloc(dev, name, size); |
16ef61c9 | 995 | mr->backend_registered = true; |
093bc2cd AK |
996 | } |
997 | ||
998 | void memory_region_init_ram_ptr(MemoryRegion *mr, | |
999 | DeviceState *dev, | |
1000 | const char *name, | |
1001 | uint64_t size, | |
1002 | void *ptr) | |
1003 | { | |
1004 | memory_region_init(mr, name, size); | |
14a3c10a | 1005 | mr->terminates = true; |
545e92e0 | 1006 | mr->destructor = memory_region_destructor_ram_from_ptr; |
093bc2cd | 1007 | mr->ram_addr = qemu_ram_alloc_from_ptr(dev, name, size, ptr); |
16ef61c9 | 1008 | mr->backend_registered = true; |
093bc2cd AK |
1009 | } |
1010 | ||
1011 | void memory_region_init_alias(MemoryRegion *mr, | |
1012 | const char *name, | |
1013 | MemoryRegion *orig, | |
1014 | target_phys_addr_t offset, | |
1015 | uint64_t size) | |
1016 | { | |
1017 | memory_region_init(mr, name, size); | |
1018 | mr->alias = orig; | |
1019 | mr->alias_offset = offset; | |
1020 | } | |
1021 | ||
d0a9b5bc AK |
1022 | void memory_region_init_rom_device(MemoryRegion *mr, |
1023 | const MemoryRegionOps *ops, | |
75f5941c | 1024 | void *opaque, |
d0a9b5bc AK |
1025 | DeviceState *dev, |
1026 | const char *name, | |
1027 | uint64_t size) | |
1028 | { | |
1029 | memory_region_init(mr, name, size); | |
7bc2b9cd | 1030 | mr->ops = ops; |
75f5941c | 1031 | mr->opaque = opaque; |
d0a9b5bc AK |
1032 | mr->terminates = true; |
1033 | mr->destructor = memory_region_destructor_rom_device; | |
1034 | mr->ram_addr = qemu_ram_alloc(dev, name, size); | |
1035 | mr->ram_addr |= cpu_register_io_memory(memory_region_read_thunk, | |
1036 | memory_region_write_thunk, | |
1037 | mr, | |
1038 | mr->ops->endianness); | |
1039 | mr->ram_addr |= IO_MEM_ROMD; | |
1040 | mr->backend_registered = true; | |
1041 | } | |
1042 | ||
093bc2cd AK |
1043 | void memory_region_destroy(MemoryRegion *mr) |
1044 | { | |
1045 | assert(QTAILQ_EMPTY(&mr->subregions)); | |
545e92e0 | 1046 | mr->destructor(mr); |
093bc2cd | 1047 | memory_region_clear_coalescing(mr); |
7267c094 AL |
1048 | g_free((char *)mr->name); |
1049 | g_free(mr->ioeventfds); | |
093bc2cd AK |
1050 | } |
1051 | ||
1052 | uint64_t memory_region_size(MemoryRegion *mr) | |
1053 | { | |
08dafab4 AK |
1054 | if (int128_eq(mr->size, int128_2_64())) { |
1055 | return UINT64_MAX; | |
1056 | } | |
1057 | return int128_get64(mr->size); | |
093bc2cd AK |
1058 | } |
1059 | ||
1060 | void memory_region_set_offset(MemoryRegion *mr, target_phys_addr_t offset) | |
1061 | { | |
1062 | mr->offset = offset; | |
1063 | } | |
1064 | ||
1065 | void memory_region_set_log(MemoryRegion *mr, bool log, unsigned client) | |
1066 | { | |
5a583347 AK |
1067 | uint8_t mask = 1 << client; |
1068 | ||
1069 | mr->dirty_log_mask = (mr->dirty_log_mask & ~mask) | (log * mask); | |
6bba19ba | 1070 | memory_region_update_topology(mr); |
093bc2cd AK |
1071 | } |
1072 | ||
1073 | bool memory_region_get_dirty(MemoryRegion *mr, target_phys_addr_t addr, | |
1074 | unsigned client) | |
1075 | { | |
14a3c10a | 1076 | assert(mr->terminates); |
5a583347 | 1077 | return cpu_physical_memory_get_dirty(mr->ram_addr + addr, 1 << client); |
093bc2cd AK |
1078 | } |
1079 | ||
1080 | void memory_region_set_dirty(MemoryRegion *mr, target_phys_addr_t addr) | |
1081 | { | |
14a3c10a | 1082 | assert(mr->terminates); |
5a583347 | 1083 | return cpu_physical_memory_set_dirty(mr->ram_addr + addr); |
093bc2cd AK |
1084 | } |
1085 | ||
1086 | void memory_region_sync_dirty_bitmap(MemoryRegion *mr) | |
1087 | { | |
5a583347 AK |
1088 | FlatRange *fr; |
1089 | ||
cc31e6e7 | 1090 | FOR_EACH_FLAT_RANGE(fr, &address_space_memory.current_map) { |
5a583347 | 1091 | if (fr->mr == mr) { |
08dafab4 AK |
1092 | cpu_physical_sync_dirty_bitmap(int128_get64(fr->addr.start), |
1093 | int128_get64(addrrange_end(fr->addr))); | |
5a583347 AK |
1094 | } |
1095 | } | |
093bc2cd AK |
1096 | } |
1097 | ||
1098 | void memory_region_set_readonly(MemoryRegion *mr, bool readonly) | |
1099 | { | |
fb1cd6f9 AK |
1100 | if (mr->readonly != readonly) { |
1101 | mr->readonly = readonly; | |
6bba19ba | 1102 | memory_region_update_topology(mr); |
fb1cd6f9 | 1103 | } |
093bc2cd AK |
1104 | } |
1105 | ||
d0a9b5bc AK |
1106 | void memory_region_rom_device_set_readable(MemoryRegion *mr, bool readable) |
1107 | { | |
1108 | if (mr->readable != readable) { | |
1109 | mr->readable = readable; | |
6bba19ba | 1110 | memory_region_update_topology(mr); |
d0a9b5bc AK |
1111 | } |
1112 | } | |
1113 | ||
093bc2cd AK |
1114 | void memory_region_reset_dirty(MemoryRegion *mr, target_phys_addr_t addr, |
1115 | target_phys_addr_t size, unsigned client) | |
1116 | { | |
14a3c10a | 1117 | assert(mr->terminates); |
5a583347 AK |
1118 | cpu_physical_memory_reset_dirty(mr->ram_addr + addr, |
1119 | mr->ram_addr + addr + size, | |
1120 | 1 << client); | |
093bc2cd AK |
1121 | } |
1122 | ||
1123 | void *memory_region_get_ram_ptr(MemoryRegion *mr) | |
1124 | { | |
1125 | if (mr->alias) { | |
1126 | return memory_region_get_ram_ptr(mr->alias) + mr->alias_offset; | |
1127 | } | |
1128 | ||
14a3c10a | 1129 | assert(mr->terminates); |
093bc2cd | 1130 | |
021d26d1 | 1131 | return qemu_get_ram_ptr(mr->ram_addr & TARGET_PAGE_MASK); |
093bc2cd AK |
1132 | } |
1133 | ||
1134 | static void memory_region_update_coalesced_range(MemoryRegion *mr) | |
1135 | { | |
1136 | FlatRange *fr; | |
1137 | CoalescedMemoryRange *cmr; | |
1138 | AddrRange tmp; | |
1139 | ||
cc31e6e7 | 1140 | FOR_EACH_FLAT_RANGE(fr, &address_space_memory.current_map) { |
093bc2cd | 1141 | if (fr->mr == mr) { |
08dafab4 AK |
1142 | qemu_unregister_coalesced_mmio(int128_get64(fr->addr.start), |
1143 | int128_get64(fr->addr.size)); | |
093bc2cd AK |
1144 | QTAILQ_FOREACH(cmr, &mr->coalesced, link) { |
1145 | tmp = addrrange_shift(cmr->addr, | |
08dafab4 AK |
1146 | int128_sub(fr->addr.start, |
1147 | int128_make64(fr->offset_in_region))); | |
093bc2cd AK |
1148 | if (!addrrange_intersects(tmp, fr->addr)) { |
1149 | continue; | |
1150 | } | |
1151 | tmp = addrrange_intersection(tmp, fr->addr); | |
08dafab4 AK |
1152 | qemu_register_coalesced_mmio(int128_get64(tmp.start), |
1153 | int128_get64(tmp.size)); | |
093bc2cd AK |
1154 | } |
1155 | } | |
1156 | } | |
1157 | } | |
1158 | ||
1159 | void memory_region_set_coalescing(MemoryRegion *mr) | |
1160 | { | |
1161 | memory_region_clear_coalescing(mr); | |
08dafab4 | 1162 | memory_region_add_coalescing(mr, 0, int128_get64(mr->size)); |
093bc2cd AK |
1163 | } |
1164 | ||
1165 | void memory_region_add_coalescing(MemoryRegion *mr, | |
1166 | target_phys_addr_t offset, | |
1167 | uint64_t size) | |
1168 | { | |
7267c094 | 1169 | CoalescedMemoryRange *cmr = g_malloc(sizeof(*cmr)); |
093bc2cd | 1170 | |
08dafab4 | 1171 | cmr->addr = addrrange_make(int128_make64(offset), int128_make64(size)); |
093bc2cd AK |
1172 | QTAILQ_INSERT_TAIL(&mr->coalesced, cmr, link); |
1173 | memory_region_update_coalesced_range(mr); | |
1174 | } | |
1175 | ||
1176 | void memory_region_clear_coalescing(MemoryRegion *mr) | |
1177 | { | |
1178 | CoalescedMemoryRange *cmr; | |
1179 | ||
1180 | while (!QTAILQ_EMPTY(&mr->coalesced)) { | |
1181 | cmr = QTAILQ_FIRST(&mr->coalesced); | |
1182 | QTAILQ_REMOVE(&mr->coalesced, cmr, link); | |
7267c094 | 1183 | g_free(cmr); |
093bc2cd AK |
1184 | } |
1185 | memory_region_update_coalesced_range(mr); | |
1186 | } | |
1187 | ||
3e9d69e7 AK |
1188 | void memory_region_add_eventfd(MemoryRegion *mr, |
1189 | target_phys_addr_t addr, | |
1190 | unsigned size, | |
1191 | bool match_data, | |
1192 | uint64_t data, | |
1193 | int fd) | |
1194 | { | |
1195 | MemoryRegionIoeventfd mrfd = { | |
08dafab4 AK |
1196 | .addr.start = int128_make64(addr), |
1197 | .addr.size = int128_make64(size), | |
3e9d69e7 AK |
1198 | .match_data = match_data, |
1199 | .data = data, | |
1200 | .fd = fd, | |
1201 | }; | |
1202 | unsigned i; | |
1203 | ||
1204 | for (i = 0; i < mr->ioeventfd_nb; ++i) { | |
1205 | if (memory_region_ioeventfd_before(mrfd, mr->ioeventfds[i])) { | |
1206 | break; | |
1207 | } | |
1208 | } | |
1209 | ++mr->ioeventfd_nb; | |
7267c094 | 1210 | mr->ioeventfds = g_realloc(mr->ioeventfds, |
3e9d69e7 AK |
1211 | sizeof(*mr->ioeventfds) * mr->ioeventfd_nb); |
1212 | memmove(&mr->ioeventfds[i+1], &mr->ioeventfds[i], | |
1213 | sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb-1 - i)); | |
1214 | mr->ioeventfds[i] = mrfd; | |
6bba19ba | 1215 | memory_region_update_topology(mr); |
3e9d69e7 AK |
1216 | } |
1217 | ||
1218 | void memory_region_del_eventfd(MemoryRegion *mr, | |
1219 | target_phys_addr_t addr, | |
1220 | unsigned size, | |
1221 | bool match_data, | |
1222 | uint64_t data, | |
1223 | int fd) | |
1224 | { | |
1225 | MemoryRegionIoeventfd mrfd = { | |
08dafab4 AK |
1226 | .addr.start = int128_make64(addr), |
1227 | .addr.size = int128_make64(size), | |
3e9d69e7 AK |
1228 | .match_data = match_data, |
1229 | .data = data, | |
1230 | .fd = fd, | |
1231 | }; | |
1232 | unsigned i; | |
1233 | ||
1234 | for (i = 0; i < mr->ioeventfd_nb; ++i) { | |
1235 | if (memory_region_ioeventfd_equal(mrfd, mr->ioeventfds[i])) { | |
1236 | break; | |
1237 | } | |
1238 | } | |
1239 | assert(i != mr->ioeventfd_nb); | |
1240 | memmove(&mr->ioeventfds[i], &mr->ioeventfds[i+1], | |
1241 | sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb - (i+1))); | |
1242 | --mr->ioeventfd_nb; | |
7267c094 | 1243 | mr->ioeventfds = g_realloc(mr->ioeventfds, |
3e9d69e7 | 1244 | sizeof(*mr->ioeventfds)*mr->ioeventfd_nb + 1); |
6bba19ba | 1245 | memory_region_update_topology(mr); |
3e9d69e7 AK |
1246 | } |
1247 | ||
093bc2cd AK |
1248 | static void memory_region_add_subregion_common(MemoryRegion *mr, |
1249 | target_phys_addr_t offset, | |
1250 | MemoryRegion *subregion) | |
1251 | { | |
1252 | MemoryRegion *other; | |
1253 | ||
1254 | assert(!subregion->parent); | |
1255 | subregion->parent = mr; | |
1256 | subregion->addr = offset; | |
1257 | QTAILQ_FOREACH(other, &mr->subregions, subregions_link) { | |
1258 | if (subregion->may_overlap || other->may_overlap) { | |
1259 | continue; | |
1260 | } | |
08dafab4 AK |
1261 | if (int128_gt(int128_make64(offset), |
1262 | int128_add(int128_make64(other->addr), other->size)) | |
1263 | || int128_le(int128_add(int128_make64(offset), subregion->size), | |
1264 | int128_make64(other->addr))) { | |
093bc2cd AK |
1265 | continue; |
1266 | } | |
a5e1cbc8 | 1267 | #if 0 |
860329b2 MW |
1268 | printf("warning: subregion collision %llx/%llx (%s) " |
1269 | "vs %llx/%llx (%s)\n", | |
093bc2cd | 1270 | (unsigned long long)offset, |
08dafab4 | 1271 | (unsigned long long)int128_get64(subregion->size), |
860329b2 MW |
1272 | subregion->name, |
1273 | (unsigned long long)other->addr, | |
08dafab4 | 1274 | (unsigned long long)int128_get64(other->size), |
860329b2 | 1275 | other->name); |
a5e1cbc8 | 1276 | #endif |
093bc2cd AK |
1277 | } |
1278 | QTAILQ_FOREACH(other, &mr->subregions, subregions_link) { | |
1279 | if (subregion->priority >= other->priority) { | |
1280 | QTAILQ_INSERT_BEFORE(other, subregion, subregions_link); | |
1281 | goto done; | |
1282 | } | |
1283 | } | |
1284 | QTAILQ_INSERT_TAIL(&mr->subregions, subregion, subregions_link); | |
1285 | done: | |
6bba19ba | 1286 | memory_region_update_topology(mr); |
093bc2cd AK |
1287 | } |
1288 | ||
1289 | ||
1290 | void memory_region_add_subregion(MemoryRegion *mr, | |
1291 | target_phys_addr_t offset, | |
1292 | MemoryRegion *subregion) | |
1293 | { | |
1294 | subregion->may_overlap = false; | |
1295 | subregion->priority = 0; | |
1296 | memory_region_add_subregion_common(mr, offset, subregion); | |
1297 | } | |
1298 | ||
1299 | void memory_region_add_subregion_overlap(MemoryRegion *mr, | |
1300 | target_phys_addr_t offset, | |
1301 | MemoryRegion *subregion, | |
1302 | unsigned priority) | |
1303 | { | |
1304 | subregion->may_overlap = true; | |
1305 | subregion->priority = priority; | |
1306 | memory_region_add_subregion_common(mr, offset, subregion); | |
1307 | } | |
1308 | ||
1309 | void memory_region_del_subregion(MemoryRegion *mr, | |
1310 | MemoryRegion *subregion) | |
1311 | { | |
1312 | assert(subregion->parent == mr); | |
1313 | subregion->parent = NULL; | |
1314 | QTAILQ_REMOVE(&mr->subregions, subregion, subregions_link); | |
6bba19ba AK |
1315 | memory_region_update_topology(mr); |
1316 | } | |
1317 | ||
1318 | void memory_region_set_enabled(MemoryRegion *mr, bool enabled) | |
1319 | { | |
1320 | if (enabled == mr->enabled) { | |
1321 | return; | |
1322 | } | |
1323 | mr->enabled = enabled; | |
1324 | memory_region_update_topology(NULL); | |
093bc2cd | 1325 | } |
1c0ffa58 AK |
1326 | |
1327 | void set_system_memory_map(MemoryRegion *mr) | |
1328 | { | |
cc31e6e7 | 1329 | address_space_memory.root = mr; |
6bba19ba | 1330 | memory_region_update_topology(NULL); |
1c0ffa58 | 1331 | } |
658b2224 AK |
1332 | |
1333 | void set_system_io_map(MemoryRegion *mr) | |
1334 | { | |
1335 | address_space_io.root = mr; | |
6bba19ba | 1336 | memory_region_update_topology(NULL); |
658b2224 | 1337 | } |
314e2987 BS |
1338 | |
1339 | typedef struct MemoryRegionList MemoryRegionList; | |
1340 | ||
1341 | struct MemoryRegionList { | |
1342 | const MemoryRegion *mr; | |
1343 | bool printed; | |
1344 | QTAILQ_ENTRY(MemoryRegionList) queue; | |
1345 | }; | |
1346 | ||
1347 | typedef QTAILQ_HEAD(queue, MemoryRegionList) MemoryRegionListHead; | |
1348 | ||
1349 | static void mtree_print_mr(fprintf_function mon_printf, void *f, | |
1350 | const MemoryRegion *mr, unsigned int level, | |
1351 | target_phys_addr_t base, | |
9479c57a | 1352 | MemoryRegionListHead *alias_print_queue) |
314e2987 | 1353 | { |
9479c57a JK |
1354 | MemoryRegionList *new_ml, *ml, *next_ml; |
1355 | MemoryRegionListHead submr_print_queue; | |
314e2987 BS |
1356 | const MemoryRegion *submr; |
1357 | unsigned int i; | |
1358 | ||
314e2987 BS |
1359 | if (!mr) { |
1360 | return; | |
1361 | } | |
1362 | ||
1363 | for (i = 0; i < level; i++) { | |
1364 | mon_printf(f, " "); | |
1365 | } | |
1366 | ||
1367 | if (mr->alias) { | |
1368 | MemoryRegionList *ml; | |
1369 | bool found = false; | |
1370 | ||
1371 | /* check if the alias is already in the queue */ | |
9479c57a | 1372 | QTAILQ_FOREACH(ml, alias_print_queue, queue) { |
314e2987 BS |
1373 | if (ml->mr == mr->alias && !ml->printed) { |
1374 | found = true; | |
1375 | } | |
1376 | } | |
1377 | ||
1378 | if (!found) { | |
1379 | ml = g_new(MemoryRegionList, 1); | |
1380 | ml->mr = mr->alias; | |
1381 | ml->printed = false; | |
9479c57a | 1382 | QTAILQ_INSERT_TAIL(alias_print_queue, ml, queue); |
314e2987 | 1383 | } |
4b474ba7 | 1384 | mon_printf(f, TARGET_FMT_plx "-" TARGET_FMT_plx " (prio %d): alias %s @%s " |
314e2987 BS |
1385 | TARGET_FMT_plx "-" TARGET_FMT_plx "\n", |
1386 | base + mr->addr, | |
08dafab4 AK |
1387 | base + mr->addr |
1388 | + (target_phys_addr_t)int128_get64(mr->size) - 1, | |
4b474ba7 | 1389 | mr->priority, |
314e2987 BS |
1390 | mr->name, |
1391 | mr->alias->name, | |
1392 | mr->alias_offset, | |
08dafab4 AK |
1393 | mr->alias_offset |
1394 | + (target_phys_addr_t)int128_get64(mr->size) - 1); | |
314e2987 | 1395 | } else { |
4b474ba7 | 1396 | mon_printf(f, TARGET_FMT_plx "-" TARGET_FMT_plx " (prio %d): %s\n", |
314e2987 | 1397 | base + mr->addr, |
08dafab4 AK |
1398 | base + mr->addr |
1399 | + (target_phys_addr_t)int128_get64(mr->size) - 1, | |
4b474ba7 | 1400 | mr->priority, |
314e2987 BS |
1401 | mr->name); |
1402 | } | |
9479c57a JK |
1403 | |
1404 | QTAILQ_INIT(&submr_print_queue); | |
1405 | ||
314e2987 | 1406 | QTAILQ_FOREACH(submr, &mr->subregions, subregions_link) { |
9479c57a JK |
1407 | new_ml = g_new(MemoryRegionList, 1); |
1408 | new_ml->mr = submr; | |
1409 | QTAILQ_FOREACH(ml, &submr_print_queue, queue) { | |
1410 | if (new_ml->mr->addr < ml->mr->addr || | |
1411 | (new_ml->mr->addr == ml->mr->addr && | |
1412 | new_ml->mr->priority > ml->mr->priority)) { | |
1413 | QTAILQ_INSERT_BEFORE(ml, new_ml, queue); | |
1414 | new_ml = NULL; | |
1415 | break; | |
1416 | } | |
1417 | } | |
1418 | if (new_ml) { | |
1419 | QTAILQ_INSERT_TAIL(&submr_print_queue, new_ml, queue); | |
1420 | } | |
1421 | } | |
1422 | ||
1423 | QTAILQ_FOREACH(ml, &submr_print_queue, queue) { | |
1424 | mtree_print_mr(mon_printf, f, ml->mr, level + 1, base + mr->addr, | |
1425 | alias_print_queue); | |
1426 | } | |
1427 | ||
88365e47 | 1428 | QTAILQ_FOREACH_SAFE(ml, &submr_print_queue, queue, next_ml) { |
9479c57a | 1429 | g_free(ml); |
314e2987 BS |
1430 | } |
1431 | } | |
1432 | ||
1433 | void mtree_info(fprintf_function mon_printf, void *f) | |
1434 | { | |
1435 | MemoryRegionListHead ml_head; | |
1436 | MemoryRegionList *ml, *ml2; | |
1437 | ||
1438 | QTAILQ_INIT(&ml_head); | |
1439 | ||
1440 | mon_printf(f, "memory\n"); | |
1441 | mtree_print_mr(mon_printf, f, address_space_memory.root, 0, 0, &ml_head); | |
1442 | ||
1443 | /* print aliased regions */ | |
1444 | QTAILQ_FOREACH(ml, &ml_head, queue) { | |
1445 | if (!ml->printed) { | |
1446 | mon_printf(f, "%s\n", ml->mr->name); | |
1447 | mtree_print_mr(mon_printf, f, ml->mr, 0, 0, &ml_head); | |
1448 | } | |
1449 | } | |
1450 | ||
1451 | QTAILQ_FOREACH_SAFE(ml, &ml_head, queue, ml2) { | |
88365e47 | 1452 | g_free(ml); |
314e2987 BS |
1453 | } |
1454 | ||
06631810 JK |
1455 | if (address_space_io.root && |
1456 | !QTAILQ_EMPTY(&address_space_io.root->subregions)) { | |
1457 | QTAILQ_INIT(&ml_head); | |
1458 | mon_printf(f, "I/O\n"); | |
1459 | mtree_print_mr(mon_printf, f, address_space_io.root, 0, 0, &ml_head); | |
1460 | } | |
314e2987 | 1461 | } |