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Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20190523' into...
[qemu.git] / hw / i386 / pc.c
CommitLineData
80cabfad
FB		 1/*
2 * QEMU PC System Emulator
5fafdf24 3 *
80cabfad 4 * Copyright (c) 2003-2004 Fabrice Bellard
5fafdf24 5 *
80cabfad
FB		 6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
e688df6b 24
b6a0aa05 25#include "qemu/osdep.h"
d471bf3e 26#include "qemu/units.h"
83c9f4ca 27#include "hw/hw.h"
0d09e41a
PB		 28#include "hw/i386/pc.h"
29#include "hw/char/serial.h"
bb3d5ea8 30#include "hw/char/parallel.h"
0d09e41a 31#include "hw/i386/apic.h"
54a40293 32#include "hw/i386/topology.h"
87abaa5d 33#include "hw/i386/fw_cfg.h"
54a40293 34#include "sysemu/cpus.h"
0d09e41a 35#include "hw/block/fdc.h"
83c9f4ca
PB		 36#include "hw/ide.h"
37#include "hw/pci/pci.h"
2118196b 38#include "hw/pci/pci_bus.h"
0d09e41a
PB		 39#include "hw/nvram/fw_cfg.h"
40#include "hw/timer/hpet.h"
a2eb5c0c 41#include "hw/firmware/smbios.h"
83c9f4ca 42#include "hw/loader.h"
ca20cf32 43#include "elf.h"
47b43a1f 44#include "multiboot.h"
0d09e41a 45#include "hw/timer/mc146818rtc.h"
55f613ac 46#include "hw/dma/i8257.h"
0d09e41a 47#include "hw/timer/i8254.h"
47973a2d 48#include "hw/input/i8042.h"
0d09e41a 49#include "hw/audio/pcspk.h"
83c9f4ca
PB		 50#include "hw/pci/msi.h"
51#include "hw/sysbus.h"
9c17d615 52#include "sysemu/sysemu.h"
e35704ba 53#include "sysemu/numa.h"
9c17d615 54#include "sysemu/kvm.h"
b1c12027 55#include "sysemu/qtest.h"
1d31f66b 56#include "kvm_i386.h"
0d09e41a 57#include "hw/xen/xen.h"
ab969087 58#include "hw/xen/start_info.h"
a19cbfb3 59#include "ui/qemu-spice.h"
022c62cb
PB		 60#include "exec/memory.h"
61#include "exec/address-spaces.h"
9c17d615 62#include "sysemu/arch_init.h"
1de7afc9 63#include "qemu/bitmap.h"
0c764a9d 64#include "qemu/config-file.h"
d49b6836 65#include "qemu/error-report.h"
922a01a0 66#include "qemu/option.h"
0445259b 67#include "hw/acpi/acpi.h"
5ff020b7 68#include "hw/acpi/cpu_hotplug.h"
c649983b 69#include "hw/boards.h"
72c194f7 70#include "acpi-build.h"
95bee274 71#include "hw/mem/pc-dimm.h"
e688df6b 72#include "qapi/error.h"
9af23989 73#include "qapi/qapi-visit-common.h"
bf1e8939 74#include "qapi/visitor.h"
15eafc2e 75#include "qom/cpu.h"
1255166b 76#include "hw/nmi.h"
a310e653 77#include "hw/usb.h"
60c5e104 78#include "hw/i386/intel_iommu.h"
489983d6 79#include "hw/net/ne2000-isa.h"
06e0259a 80#include "standard-headers/asm-x86/bootparam.h"
80cabfad 81
471fd342
BS		 82/* debug PC/ISA interrupts */
83//#define DEBUG_IRQ
84
85#ifdef DEBUG_IRQ
86#define DPRINTF(fmt, ...) \
87 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
88#else
89#define DPRINTF(fmt, ...)
90#endif
91
4c5b10b7
JS		 92#define E820_NR_ENTRIES 16
93
94struct e820_entry {
95 uint64_t address;
96 uint64_t length;
97 uint32_t type;
541dc0d4 98} QEMU_PACKED __attribute((__aligned__(4)));
4c5b10b7
JS		 99
100struct e820_table {
101 uint32_t count;
102 struct e820_entry entry[E820_NR_ENTRIES];
541dc0d4 103} QEMU_PACKED __attribute((__aligned__(4)));
4c5b10b7 104
7d67110f
GH		 105static struct e820_table e820_reserve;
106static struct e820_entry *e820_table;
107static unsigned e820_entries;
dd703b99 108struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
4c5b10b7 109
ab969087
LM		 110/* Physical Address of PVH entry point read from kernel ELF NOTE */
111static size_t pvh_start_addr;
112
9bf2650b
CH		 113GlobalProperty pc_compat_4_0[] = {};
114const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0);
115
abd93cc7 116GlobalProperty pc_compat_3_1[] = {
6c36bddf 117 { "intel-iommu", "dma-drain", "off" },
483c6ad4
BP		 118 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" },
119 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" },
9fe8b7be
VK		 120 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" },
121 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" },
483c6ad4 122 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" },
9fe8b7be
VK		 123 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" },
124 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" },
125 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" },
126 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" },
127 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" },
128 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" },
ecb85fe4
PB		 129 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
130 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
131 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
132 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
133 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
134 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
135 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
b0a19803 136 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" },
f24c3a79 137 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" },
abd93cc7
MAL		 138};
139const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1);
140
ddb3235d 141GlobalProperty pc_compat_3_0[] = {
6c36bddf
EH		 142 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" },
143 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" },
144 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" },
ddb3235d
MAL		 145};
146const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0);
147
0d47310b 148GlobalProperty pc_compat_2_12[] = {
6c36bddf
EH		 149 { TYPE_X86_CPU, "legacy-cache", "on" },
150 { TYPE_X86_CPU, "topoext", "off" },
151 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
152 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
0d47310b
MAL		 153};
154const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12);
155
43df70a9 156GlobalProperty pc_compat_2_11[] = {
6c36bddf
EH		 157 { TYPE_X86_CPU, "x-migrate-smi-count", "off" },
158 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" },
43df70a9
MAL		 159};
160const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11);
161
503224f4 162GlobalProperty pc_compat_2_10[] = {
6c36bddf
EH		 163 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" },
164 { "i440FX-pcihost", "x-pci-hole64-fix", "off" },
165 { "q35-pcihost", "x-pci-hole64-fix", "off" },
503224f4
MAL		 166};
167const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10);
168
3e803152 169GlobalProperty pc_compat_2_9[] = {
6c36bddf 170 { "mch", "extended-tseg-mbytes", "0" },
3e803152
MAL		 171};
172const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9);
173
edc24ccd 174GlobalProperty pc_compat_2_8[] = {
6c36bddf
EH		 175 { TYPE_X86_CPU, "tcg-cpuid", "off" },
176 { "kvmclock", "x-mach-use-reliable-get-clock", "off" },
177 { "ICH9-LPC", "x-smi-broadcast", "off" },
178 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" },
179 { "Haswell-" TYPE_X86_CPU, "stepping", "1" },
edc24ccd
MAL		 180};
181const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8);
182
5a995064 183GlobalProperty pc_compat_2_7[] = {
6c36bddf
EH		 184 { TYPE_X86_CPU, "l3-cache", "off" },
185 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" },
186 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" },
187 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" },
188 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" },
189 { "isa-pcspk", "migrate", "off" },
5a995064
MAL		 190};
191const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7);
192
ff8f261f 193GlobalProperty pc_compat_2_6[] = {
6c36bddf
EH		 194 { TYPE_X86_CPU, "cpuid-0xb", "off" },
195 { "vmxnet3", "romfile", "" },
196 { TYPE_X86_CPU, "fill-mtrr-mask", "off" },
197 { "apic-common", "legacy-instance-id", "on", }
ff8f261f
MAL		 198};
199const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6);
200
fe759610
MAL		 201GlobalProperty pc_compat_2_5[] = {};
202const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5);
203
2f99b9c2
MAL		 204GlobalProperty pc_compat_2_4[] = {
205 PC_CPU_MODEL_IDS("2.4.0")
6c36bddf
EH		 206 { "Haswell-" TYPE_X86_CPU, "abm", "off" },
207 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" },
208 { "Broadwell-" TYPE_X86_CPU, "abm", "off" },
209 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" },
210 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" },
211 { TYPE_X86_CPU, "check", "off" },
212 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" },
213 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" },
214 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" },
215 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" },
216 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" },
217 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" },
218 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" },
219 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", }
2f99b9c2
MAL		 220};
221const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4);
222
8995dd90
MAL		 223GlobalProperty pc_compat_2_3[] = {
224 PC_CPU_MODEL_IDS("2.3.0")
6c36bddf
EH		 225 { TYPE_X86_CPU, "arat", "off" },
226 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" },
227 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" },
228 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" },
229 { "n270" "-" TYPE_X86_CPU, "min-level", "5" },
230 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" },
231 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" },
232 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" },
233 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
234 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
235 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
236 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
237 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
238 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
239 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
240 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
241 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
242 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
243 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
244 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" },
8995dd90
MAL		 245};
246const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3);
247
1c30044e
MAL		 248GlobalProperty pc_compat_2_2[] = {
249 PC_CPU_MODEL_IDS("2.2.0")
6c36bddf
EH		 250 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" },
251 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" },
252 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" },
253 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" },
254 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" },
255 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" },
256 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" },
257 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" },
258 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" },
259 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" },
260 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" },
261 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" },
262 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" },
263 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" },
264 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" },
265 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" },
266 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" },
267 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" },
1c30044e
MAL		 268};
269const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2);
270
c4fc5695
MAL		 271GlobalProperty pc_compat_2_1[] = {
272 PC_CPU_MODEL_IDS("2.1.0")
6c36bddf
EH		 273 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" },
274 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" },
c4fc5695
MAL		 275};
276const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1);
277
a310e653
MAL		 278GlobalProperty pc_compat_2_0[] = {
279 PC_CPU_MODEL_IDS("2.0.0")
6c36bddf
EH		 280 { "virtio-scsi-pci", "any_layout", "off" },
281 { "PIIX4_PM", "memory-hotplug-support", "off" },
282 { "apic", "version", "0x11" },
283 { "nec-usb-xhci", "superspeed-ports-first", "off" },
284 { "nec-usb-xhci", "force-pcie-endcap", "on" },
285 { "pci-serial", "prog_if", "0" },
286 { "pci-serial-2x", "prog_if", "0" },
287 { "pci-serial-4x", "prog_if", "0" },
288 { "virtio-net-pci", "guest_announce", "off" },
289 { "ICH9-LPC", "memory-hotplug-support", "off" },
290 { "xio3130-downstream", COMPAT_PROP_PCP, "off" },
291 { "ioh3420", COMPAT_PROP_PCP, "off" },
a310e653
MAL		 292};
293const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0);
294
295GlobalProperty pc_compat_1_7[] = {
296 PC_CPU_MODEL_IDS("1.7.0")
6c36bddf
EH		 297 { TYPE_USB_DEVICE, "msos-desc", "no" },
298 { "PIIX4_PM", "acpi-pci-hotplug-with-bridge-support", "off" },
299 { "hpet", HPET_INTCAP, "4" },
a310e653
MAL		 300};
301const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7);
302
303GlobalProperty pc_compat_1_6[] = {
304 PC_CPU_MODEL_IDS("1.6.0")
6c36bddf
EH		 305 { "e1000", "mitigation", "off" },
306 { "qemu64-" TYPE_X86_CPU, "model", "2" },
307 { "qemu32-" TYPE_X86_CPU, "model", "3" },
308 { "i440FX-pcihost", "short_root_bus", "1" },
309 { "q35-pcihost", "short_root_bus", "1" },
a310e653
MAL		 310};
311const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6);
312
313GlobalProperty pc_compat_1_5[] = {
314 PC_CPU_MODEL_IDS("1.5.0")
6c36bddf
EH		 315 { "Conroe-" TYPE_X86_CPU, "model", "2" },
316 { "Conroe-" TYPE_X86_CPU, "min-level", "2" },
317 { "Penryn-" TYPE_X86_CPU, "model", "2" },
318 { "Penryn-" TYPE_X86_CPU, "min-level", "2" },
319 { "Nehalem-" TYPE_X86_CPU, "model", "2" },
320 { "Nehalem-" TYPE_X86_CPU, "min-level", "2" },
321 { "virtio-net-pci", "any_layout", "off" },
322 { TYPE_X86_CPU, "pmu", "on" },
323 { "i440FX-pcihost", "short_root_bus", "0" },
324 { "q35-pcihost", "short_root_bus", "0" },
a310e653
MAL		 325};
326const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5);
327
328GlobalProperty pc_compat_1_4[] = {
329 PC_CPU_MODEL_IDS("1.4.0")
6c36bddf
EH		 330 { "scsi-hd", "discard_granularity", "0" },
331 { "scsi-cd", "discard_granularity", "0" },
332 { "scsi-disk", "discard_granularity", "0" },
333 { "ide-hd", "discard_granularity", "0" },
334 { "ide-cd", "discard_granularity", "0" },
335 { "ide-drive", "discard_granularity", "0" },
336 { "virtio-blk-pci", "discard_granularity", "0" },
337 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */
338 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" },
339 { "virtio-net-pci", "ctrl_guest_offloads", "off" },
340 { "e1000", "romfile", "pxe-e1000.rom" },
341 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" },
342 { "pcnet", "romfile", "pxe-pcnet.rom" },
343 { "rtl8139", "romfile", "pxe-rtl8139.rom" },
344 { "virtio-net-pci", "romfile", "pxe-virtio.rom" },
345 { "486-" TYPE_X86_CPU, "model", "0" },
346 { "n270" "-" TYPE_X86_CPU, "movbe", "off" },
347 { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" },
a310e653
MAL		 348};
349const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4);
350
b881fbe9 351void gsi_handler(void *opaque, int n, int level)
1452411b 352{
b881fbe9 353 GSIState *s = opaque;
1452411b 354
b881fbe9
JK		 355 DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n);
356 if (n < ISA_NUM_IRQS) {
357 qemu_set_irq(s->i8259_irq[n], level);
1632dc6a 358 }
b881fbe9 359 qemu_set_irq(s->ioapic_irq[n], level);
2e9947d2 360}
1452411b 361
258711c6
JG		 362static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
363 unsigned size)
80cabfad
FB		 364{
365}
366
c02e1eac
JG		 367static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
368{
a6fc23e5 369 return 0xffffffffffffffffULL;
c02e1eac
JG		 370}
371
f929aad6 372/* MSDOS compatibility mode FPU exception support */
d537cf6c 373static qemu_irq ferr_irq;
8e78eb28
IY		 374
375void pc_register_ferr_irq(qemu_irq irq)
376{
377 ferr_irq = irq;
378}
379
f929aad6
FB		 380/* XXX: add IGNNE support */
381void cpu_set_ferr(CPUX86State *s)
382{
d537cf6c 383 qemu_irq_raise(ferr_irq);
f929aad6
FB		 384}
385
258711c6
JG		 386static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
387 unsigned size)
f929aad6 388{
d537cf6c 389 qemu_irq_lower(ferr_irq);
f929aad6
FB		 390}
391
c02e1eac
JG		 392static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
393{
a6fc23e5 394 return 0xffffffffffffffffULL;
c02e1eac
JG		 395}
396
28ab0e2e 397/* TSC handling */
28ab0e2e
FB		 398uint64_t cpu_get_tsc(CPUX86State *env)
399{
4a1418e0 400 return cpu_get_ticks();
28ab0e2e
FB		 401}
402
3de388f6 403/* IRQ handling */
4a8fa5dc 404int cpu_get_pic_interrupt(CPUX86State *env)
3de388f6 405{
02e51483 406 X86CPU *cpu = x86_env_get_cpu(env);
3de388f6
FB		 407 int intno;
408
bb93e099
WL		 409 if (!kvm_irqchip_in_kernel()) {
410 intno = apic_get_interrupt(cpu->apic_state);
411 if (intno >= 0) {
412 return intno;
413 }
414 /* read the irq from the PIC */
415 if (!apic_accept_pic_intr(cpu->apic_state)) {
416 return -1;
417 }
cf6d64bf 418 }
0e21e12b 419
3de388f6
FB		 420 intno = pic_read_irq(isa_pic);
421 return intno;
422}
423
d537cf6c 424static void pic_irq_request(void *opaque, int irq, int level)
3de388f6 425{
182735ef
AF		 426 CPUState *cs = first_cpu;
427 X86CPU *cpu = X86_CPU(cs);
a5b38b51 428
471fd342 429 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
bb93e099 430 if (cpu->apic_state && !kvm_irqchip_in_kernel()) {
bdc44640 431 CPU_FOREACH(cs) {
182735ef 432 cpu = X86_CPU(cs);
02e51483
CF		 433 if (apic_accept_pic_intr(cpu->apic_state)) {
434 apic_deliver_pic_intr(cpu->apic_state, level);
cf6d64bf 435 }
d5529471
AJ		 436 }
437 } else {
d8ed887b 438 if (level) {
c3affe56 439 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
d8ed887b
AF		 440 } else {
441 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
442 }
a5b38b51 443 }
3de388f6
FB		 444}
445
b0a21b53
FB		 446/* PC cmos mappings */
447
80cabfad
FB		 448#define REG_EQUIPMENT_BYTE 0x14
449
bda05509 450int cmos_get_fd_drive_type(FloppyDriveType fd0)
777428f2
FB		 451{
452 int val;
453
454 switch (fd0) {
2da44dd0 455 case FLOPPY_DRIVE_TYPE_144:
777428f2
FB		 456 /* 1.44 Mb 3"5 drive */
457 val = 4;
458 break;
2da44dd0 459 case FLOPPY_DRIVE_TYPE_288:
777428f2
FB		 460 /* 2.88 Mb 3"5 drive */
461 val = 5;
462 break;
2da44dd0 463 case FLOPPY_DRIVE_TYPE_120:
777428f2
FB		 464 /* 1.2 Mb 5"5 drive */
465 val = 2;
466 break;
2da44dd0 467 case FLOPPY_DRIVE_TYPE_NONE:
777428f2
FB		 468 default:
469 val = 0;
470 break;
471 }
472 return val;
473}
474
9139046c
MA		 475static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
476 int16_t cylinders, int8_t heads, int8_t sectors)
ba6c2377 477{
ba6c2377
FB		 478 rtc_set_memory(s, type_ofs, 47);
479 rtc_set_memory(s, info_ofs, cylinders);
480 rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
481 rtc_set_memory(s, info_ofs + 2, heads);
482 rtc_set_memory(s, info_ofs + 3, 0xff);
483 rtc_set_memory(s, info_ofs + 4, 0xff);
484 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
485 rtc_set_memory(s, info_ofs + 6, cylinders);
486 rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
487 rtc_set_memory(s, info_ofs + 8, sectors);
488}
489
6ac0e82d
AZ		 490/* convert boot_device letter to something recognizable by the bios */
491static int boot_device2nibble(char boot_device)
492{
493 switch(boot_device) {
494 case 'a':
495 case 'b':
496 return 0x01; /* floppy boot */
497 case 'c':
498 return 0x02; /* hard drive boot */
499 case 'd':
500 return 0x03; /* CD-ROM boot */
501 case 'n':
502 return 0x04; /* Network boot */
503 }
504 return 0;
505}
506
ddcd5531 507static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp)
0ecdffbb
AJ		 508{
509#define PC_MAX_BOOT_DEVICES 3
0ecdffbb
AJ		 510 int nbds, bds[3] = { 0, };
511 int i;
512
513 nbds = strlen(boot_device);
514 if (nbds > PC_MAX_BOOT_DEVICES) {
ddcd5531
GA		 515 error_setg(errp, "Too many boot devices for PC");
516 return;
0ecdffbb
AJ		 517 }
518 for (i = 0; i < nbds; i++) {
519 bds[i] = boot_device2nibble(boot_device[i]);
520 if (bds[i] == 0) {
ddcd5531
GA		 521 error_setg(errp, "Invalid boot device for PC: '%c'",
522 boot_device[i]);
523 return;
0ecdffbb
AJ		 524 }
525 }
526 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
d9346e81 527 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
0ecdffbb
AJ		 528}
529
ddcd5531 530static void pc_boot_set(void *opaque, const char *boot_device, Error **errp)
d9346e81 531{
ddcd5531 532 set_boot_dev(opaque, boot_device, errp);
d9346e81
MA		 533}
534
7444ca4e
LE		 535static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy)
536{
537 int val, nb, i;
2da44dd0
JS		 538 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE,
539 FLOPPY_DRIVE_TYPE_NONE };
7444ca4e
LE		 540
541 /* floppy type */
542 if (floppy) {
543 for (i = 0; i < 2; i++) {
544 fd_type[i] = isa_fdc_get_drive_type(floppy, i);
545 }
546 }
547 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
548 cmos_get_fd_drive_type(fd_type[1]);
549 rtc_set_memory(rtc_state, 0x10, val);
550
551 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE);
552 nb = 0;
2da44dd0 553 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) {
7444ca4e
LE		 554 nb++;
555 }
2da44dd0 556 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) {
7444ca4e
LE		 557 nb++;
558 }
559 switch (nb) {
560 case 0:
561 break;
562 case 1:
563 val |= 0x01; /* 1 drive, ready for boot */
564 break;
565 case 2:
566 val |= 0x41; /* 2 drives, ready for boot */
567 break;
568 }
569 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val);
570}
571
c0897e0c
MA		 572typedef struct pc_cmos_init_late_arg {
573 ISADevice *rtc_state;
9139046c 574 BusState *idebus[2];
c0897e0c
MA		 575} pc_cmos_init_late_arg;
576
b86f4613
LE		 577typedef struct check_fdc_state {
578 ISADevice *floppy;
579 bool multiple;
580} CheckFdcState;
581
582static int check_fdc(Object *obj, void *opaque)
583{
584 CheckFdcState *state = opaque;
585 Object *fdc;
586 uint32_t iobase;
587 Error *local_err = NULL;
588
589 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC);
590 if (!fdc) {
591 return 0;
592 }
593
1ea1572a 594 iobase = object_property_get_uint(obj, "iobase", &local_err);
b86f4613
LE		 595 if (local_err || iobase != 0x3f0) {
596 error_free(local_err);
597 return 0;
598 }
599
600 if (state->floppy) {
601 state->multiple = true;
602 } else {
603 state->floppy = ISA_DEVICE(obj);
604 }
605 return 0;
606}
607
608static const char * const fdc_container_path[] = {
609 "/unattached", "/peripheral", "/peripheral-anon"
610};
611
424e4a87
RK		 612/*
613 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
614 * and ACPI objects.
615 */
616ISADevice *pc_find_fdc0(void)
617{
618 int i;
619 Object *container;
620 CheckFdcState state = { 0 };
621
622 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) {
623 container = container_get(qdev_get_machine(), fdc_container_path[i]);
624 object_child_foreach(container, check_fdc, &state);
625 }
626
627 if (state.multiple) {
3dc6f869
AF		 628 warn_report("multiple floppy disk controllers with "
629 "iobase=0x3f0 have been found");
433672b0 630 error_printf("the one being picked for CMOS setup might not reflect "
9e5d2c52 631 "your intent");
424e4a87
RK		 632 }
633
634 return state.floppy;
635}
636
c0897e0c
MA		 637static void pc_cmos_init_late(void *opaque)
638{
639 pc_cmos_init_late_arg *arg = opaque;
640 ISADevice *s = arg->rtc_state;
9139046c
MA		 641 int16_t cylinders;
642 int8_t heads, sectors;
c0897e0c 643 int val;
2adc99b2 644 int i, trans;
c0897e0c 645
9139046c 646 val = 0;
272f0428
CP		 647 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0,
648 &cylinders, &heads, &sectors) >= 0) {
9139046c
MA		 649 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
650 val |= 0xf0;
651 }
272f0428
CP		 652 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1,
653 &cylinders, &heads, &sectors) >= 0) {
9139046c
MA		 654 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
655 val |= 0x0f;
656 }
657 rtc_set_memory(s, 0x12, val);
c0897e0c
MA		 658
659 val = 0;
660 for (i = 0; i < 4; i++) {
9139046c
MA		 661 /* NOTE: ide_get_geometry() returns the physical
662 geometry. It is always such that: 1 <= sects <= 63, 1
663 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
664 geometry can be different if a translation is done. */
272f0428
CP		 665 if (arg->idebus[i / 2] &&
666 ide_get_geometry(arg->idebus[i / 2], i % 2,
9139046c 667 &cylinders, &heads, &sectors) >= 0) {
2adc99b2
MA		 668 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
669 assert((trans & ~3) == 0);
670 val |= trans << (i * 2);
c0897e0c
MA		 671 }
672 }
673 rtc_set_memory(s, 0x39, val);
674
424e4a87 675 pc_cmos_init_floppy(s, pc_find_fdc0());
b86f4613 676
c0897e0c
MA		 677 qemu_unregister_reset(pc_cmos_init_late, opaque);
678}
679
23d30407 680void pc_cmos_init(PCMachineState *pcms,
220a8846 681 BusState *idebus0, BusState *idebus1,
63ffb564 682 ISADevice *s)
80cabfad 683{
7444ca4e 684 int val;
c0897e0c 685 static pc_cmos_init_late_arg arg;
b0a21b53 686
b0a21b53 687 /* various important CMOS locations needed by PC/Bochs bios */
80cabfad
FB		 688
689 /* memory size */
e89001f7 690 /* base memory (first MiB) */
d471bf3e 691 val = MIN(pcms->below_4g_mem_size / KiB, 640);
333190eb
FB		 692 rtc_set_memory(s, 0x15, val);
693 rtc_set_memory(s, 0x16, val >> 8);
e89001f7 694 /* extended memory (next 64MiB) */
d471bf3e
PB		 695 if (pcms->below_4g_mem_size > 1 * MiB) {
696 val = (pcms->below_4g_mem_size - 1 * MiB) / KiB;
e89001f7
MA		 697 } else {
698 val = 0;
699 }
80cabfad
FB		 700 if (val > 65535)
701 val = 65535;
b0a21b53
FB		 702 rtc_set_memory(s, 0x17, val);
703 rtc_set_memory(s, 0x18, val >> 8);
704 rtc_set_memory(s, 0x30, val);
705 rtc_set_memory(s, 0x31, val >> 8);
e89001f7 706 /* memory between 16MiB and 4GiB */
d471bf3e
PB		 707 if (pcms->below_4g_mem_size > 16 * MiB) {
708 val = (pcms->below_4g_mem_size - 16 * MiB) / (64 * KiB);
e89001f7 709 } else {
9da98861 710 val = 0;
e89001f7 711 }
80cabfad
FB		 712 if (val > 65535)
713 val = 65535;
b0a21b53
FB		 714 rtc_set_memory(s, 0x34, val);
715 rtc_set_memory(s, 0x35, val >> 8);
e89001f7 716 /* memory above 4GiB */
88076854 717 val = pcms->above_4g_mem_size / 65536;
e89001f7
MA		 718 rtc_set_memory(s, 0x5b, val);
719 rtc_set_memory(s, 0x5c, val >> 8);
720 rtc_set_memory(s, 0x5d, val >> 16);
3b46e624 721
23d30407 722 object_property_add_link(OBJECT(pcms), "rtc_state",
2d996150 723 TYPE_ISA_DEVICE,
ec68007a 724 (Object **)&pcms->rtc,
2d996150 725 object_property_allow_set_link,
265b578c 726 OBJ_PROP_LINK_STRONG, &error_abort);
23d30407 727 object_property_set_link(OBJECT(pcms), OBJECT(s),
2d996150 728 "rtc_state", &error_abort);
298e01b6 729
007b0657 730 set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal);
80cabfad 731
b0a21b53 732 val = 0;
b0a21b53
FB		 733 val |= 0x02; /* FPU is there */
734 val |= 0x04; /* PS/2 mouse installed */
735 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
736
b86f4613 737 /* hard drives and FDC */
c0897e0c 738 arg.rtc_state = s;
9139046c
MA		 739 arg.idebus[0] = idebus0;
740 arg.idebus[1] = idebus1;
c0897e0c 741 qemu_register_reset(pc_cmos_init_late, &arg);
80cabfad
FB		 742}
743
a0881c64
AF		 744#define TYPE_PORT92 "port92"
745#define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92)
746
4b78a802
BS		 747/* port 92 stuff: could be split off */
748typedef struct Port92State {
a0881c64
AF		 749 ISADevice parent_obj;
750
23af670e 751 MemoryRegion io;
4b78a802 752 uint8_t outport;
d812b3d6 753 qemu_irq a20_out;
4b78a802
BS		 754} Port92State;
755
93ef4192
AG		 756static void port92_write(void *opaque, hwaddr addr, uint64_t val,
757 unsigned size)
4b78a802
BS		 758{
759 Port92State *s = opaque;
4700a316 760 int oldval = s->outport;
4b78a802 761
c5539cb4 762 DPRINTF("port92: write 0x%02" PRIx64 "\n", val);
4b78a802 763 s->outport = val;
d812b3d6 764 qemu_set_irq(s->a20_out, (val >> 1) & 1);
4700a316 765 if ((val & 1) && !(oldval & 1)) {
cf83f140 766 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
4b78a802
BS		 767 }
768}
769
93ef4192
AG		 770static uint64_t port92_read(void *opaque, hwaddr addr,
771 unsigned size)
4b78a802
BS		 772{
773 Port92State *s = opaque;
774 uint32_t ret;
775
776 ret = s->outport;
777 DPRINTF("port92: read 0x%02x\n", ret);
778 return ret;
779}
780
d80fe99d 781static void port92_init(ISADevice *dev, qemu_irq a20_out)
4b78a802 782{
d80fe99d 783 qdev_connect_gpio_out_named(DEVICE(dev), PORT92_A20_LINE, 0, a20_out);
4b78a802
BS		 784}
785
786static const VMStateDescription vmstate_port92_isa = {
787 .name = "port92",
788 .version_id = 1,
789 .minimum_version_id = 1,
d49805ae 790 .fields = (VMStateField[]) {
4b78a802
BS		 791 VMSTATE_UINT8(outport, Port92State),
792 VMSTATE_END_OF_LIST()
793 }
794};
795
796static void port92_reset(DeviceState *d)
797{
a0881c64 798 Port92State *s = PORT92(d);
4b78a802
BS		 799
800 s->outport &= ~1;
801}
802
23af670e 803static const MemoryRegionOps port92_ops = {
93ef4192
AG		 804 .read = port92_read,
805 .write = port92_write,
806 .impl = {
807 .min_access_size = 1,
808 .max_access_size = 1,
809 },
810 .endianness = DEVICE_LITTLE_ENDIAN,
23af670e
RH		 811};
812
db895a1e 813static void port92_initfn(Object *obj)
4b78a802 814{
db895a1e 815 Port92State *s = PORT92(obj);
4b78a802 816
1437c94b 817 memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1);
23af670e 818
4b78a802 819 s->outport = 0;
d812b3d6
EV		 820
821 qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, PORT92_A20_LINE, 1);
db895a1e
AF		 822}
823
824static void port92_realizefn(DeviceState *dev, Error **errp)
825{
826 ISADevice *isadev = ISA_DEVICE(dev);
827 Port92State *s = PORT92(dev);
828
829 isa_register_ioport(isadev, &s->io, 0x92);
4b78a802
BS		 830}
831
8f04ee08
AL		 832static void port92_class_initfn(ObjectClass *klass, void *data)
833{
39bffca2 834 DeviceClass *dc = DEVICE_CLASS(klass);
db895a1e 835
db895a1e 836 dc->realize = port92_realizefn;
39bffca2
AL		 837 dc->reset = port92_reset;
838 dc->vmsd = &vmstate_port92_isa;
f3b17640
MA		 839 /*
840 * Reason: unlike ordinary ISA devices, this one needs additional
841 * wiring: its A20 output line needs to be wired up by
842 * port92_init().
843 */
e90f2a8c 844 dc->user_creatable = false;
8f04ee08
AL		 845}
846
8c43a6f0 847static const TypeInfo port92_info = {
a0881c64 848 .name = TYPE_PORT92,
39bffca2
AL		 849 .parent = TYPE_ISA_DEVICE,
850 .instance_size = sizeof(Port92State),
db895a1e 851 .instance_init = port92_initfn,
39bffca2 852 .class_init = port92_class_initfn,
4b78a802
BS		 853};
854
83f7d43a 855static void port92_register_types(void)
4b78a802 856{
39bffca2 857 type_register_static(&port92_info);
4b78a802 858}
83f7d43a
AF		 859
860type_init(port92_register_types)
4b78a802 861
956a3e6b 862static void handle_a20_line_change(void *opaque, int irq, int level)
59b8ad81 863{
cc36a7a2 864 X86CPU *cpu = opaque;
e1a23744 865
956a3e6b 866 /* XXX: send to all CPUs ? */
4b78a802 867 /* XXX: add logic to handle multiple A20 line sources */
cc36a7a2 868 x86_cpu_set_a20(cpu, level);
e1a23744
FB		 869}
870
4c5b10b7
JS		 871int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
872{
7d67110f 873 int index = le32_to_cpu(e820_reserve.count);
4c5b10b7
JS		 874 struct e820_entry *entry;
875
7d67110f
GH		 876 if (type != E820_RAM) {
877 /* old FW_CFG_E820_TABLE entry -- reservations only */
878 if (index >= E820_NR_ENTRIES) {
879 return -EBUSY;
880 }
881 entry = &e820_reserve.entry[index++];
882
883 entry->address = cpu_to_le64(address);
884 entry->length = cpu_to_le64(length);
885 entry->type = cpu_to_le32(type);
886
887 e820_reserve.count = cpu_to_le32(index);
888 }
4c5b10b7 889
7d67110f 890 /* new "etc/e820" file -- include ram too */
ab3ad07f 891 e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1);
7d67110f
GH		 892 e820_table[e820_entries].address = cpu_to_le64(address);
893 e820_table[e820_entries].length = cpu_to_le64(length);
894 e820_table[e820_entries].type = cpu_to_le32(type);
895 e820_entries++;
4c5b10b7 896
7d67110f 897 return e820_entries;
4c5b10b7
JS		 898}
899
7bf8ef19
GS		 900int e820_get_num_entries(void)
901{
902 return e820_entries;
903}
904
905bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length)
906{
907 if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) {
908 *address = le64_to_cpu(e820_table[idx].address);
909 *length = le64_to_cpu(e820_table[idx].length);
910 return true;
911 }
912 return false;
913}
914
54a40293
EH		 915/* Enables contiguous-apic-ID mode, for compatibility */
916static bool compat_apic_id_mode;
917
918void enable_compat_apic_id_mode(void)
919{
920 compat_apic_id_mode = true;
921}
922
923/* Calculates initial APIC ID for a specific CPU index
924 *
925 * Currently we need to be able to calculate the APIC ID from the CPU index
926 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
927 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
928 * all CPUs up to max_cpus.
929 */
930static uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
931{
932 uint32_t correct_id;
933 static bool warned;
934
935 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
936 if (compat_apic_id_mode) {
b1c12027 937 if (cpu_index != correct_id && !warned && !qtest_enabled()) {
54a40293
EH		 938 error_report("APIC IDs set in compatibility mode, "
939 "CPU topology won't match the configuration");
940 warned = true;
941 }
942 return cpu_index;
943 } else {
944 return correct_id;
945 }
946}
947
f2098f48 948static void pc_build_smbios(PCMachineState *pcms)
80cabfad 949{
c97294ec
GS		 950 uint8_t *smbios_tables, *smbios_anchor;
951 size_t smbios_tables_len, smbios_anchor_len;
89cc4a27
WH		 952 struct smbios_phys_mem_area *mem_array;
953 unsigned i, array_count;
38690a1c
IM		 954 MachineState *ms = MACHINE(pcms);
955 X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu);
f2098f48
IM		 956
957 /* tell smbios about cpuid version and features */
958 smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]);
5fd0a9d4
WH		 959
960 smbios_tables = smbios_get_table_legacy(&smbios_tables_len);
961 if (smbios_tables) {
f2098f48 962 fw_cfg_add_bytes(pcms->fw_cfg, FW_CFG_SMBIOS_ENTRIES,
5fd0a9d4
WH		 963 smbios_tables, smbios_tables_len);
964 }
965
89cc4a27
WH		 966 /* build the array of physical mem area from e820 table */
967 mem_array = g_malloc0(sizeof(*mem_array) * e820_get_num_entries());
968 for (i = 0, array_count = 0; i < e820_get_num_entries(); i++) {
969 uint64_t addr, len;
970
971 if (e820_get_entry(i, E820_RAM, &addr, &len)) {
972 mem_array[array_count].address = addr;
973 mem_array[array_count].length = len;
974 array_count++;
975 }
976 }
977 smbios_get_tables(mem_array, array_count,
978 &smbios_tables, &smbios_tables_len,
5fd0a9d4 979 &smbios_anchor, &smbios_anchor_len);
89cc4a27
WH		 980 g_free(mem_array);
981
5fd0a9d4 982 if (smbios_anchor) {
f2098f48 983 fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-tables",
5fd0a9d4 984 smbios_tables, smbios_tables_len);
f2098f48 985 fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-anchor",
5fd0a9d4
WH		 986 smbios_anchor, smbios_anchor_len);
987 }
988}
989
ebde2465 990static FWCfgState *bochs_bios_init(AddressSpace *as, PCMachineState *pcms)
5fd0a9d4
WH		 991{
992 FWCfgState *fw_cfg;
11c2fd3e 993 uint64_t *numa_fw_cfg;
ea265072
IM		 994 int i;
995 const CPUArchIdList *cpus;
996 MachineClass *mc = MACHINE_GET_CLASS(pcms);
3cce6243 997
305ae888 998 fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, as);
e3cadac0 999 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
c886fc4c 1000
1d934e89
EH		 1001 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86:
1002 *
a3abd0f2
IM		 1003 * For machine types prior to 1.8, SeaBIOS needs FW_CFG_MAX_CPUS for
1004 * building MPTable, ACPI MADT, ACPI CPU hotplug and ACPI SRAT table,
1005 * that tables are based on xAPIC ID and QEMU<->SeaBIOS interface
1006 * for CPU hotplug also uses APIC ID and not "CPU index".
1007 * This means that FW_CFG_MAX_CPUS is not the "maximum number of CPUs",
1008 * but the "limit to the APIC ID values SeaBIOS may see".
1d934e89 1009 *
a3abd0f2
IM		 1010 * So for compatibility reasons with old BIOSes we are stuck with
1011 * "etc/max-cpus" actually being apic_id_limit
1d934e89 1012 */
ebde2465 1013 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)pcms->apic_id_limit);
905fdcb5 1014 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
089da572
MA		 1015 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES,
1016 acpi_tables, acpi_tables_len);
9b5b76d4 1017 fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
b6f6e3d3 1018
089da572 1019 fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE,
7d67110f
GH		 1020 &e820_reserve, sizeof(e820_reserve));
1021 fw_cfg_add_file(fw_cfg, "etc/e820", e820_table,
1022 sizeof(struct e820_entry) * e820_entries);
11c2fd3e 1023
089da572 1024 fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg));
11c2fd3e
AL		 1025 /* allocate memory for the NUMA channel: one (64bit) word for the number
1026 * of nodes, one word for each VCPU->node and one word for each node to
1027 * hold the amount of memory.
1028 */
ebde2465 1029 numa_fw_cfg = g_new0(uint64_t, 1 + pcms->apic_id_limit + nb_numa_nodes);
11c2fd3e 1030 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
ea265072
IM		 1031 cpus = mc->possible_cpu_arch_ids(MACHINE(pcms));
1032 for (i = 0; i < cpus->len; i++) {
1033 unsigned int apic_id = cpus->cpus[i].arch_id;
ebde2465 1034 assert(apic_id < pcms->apic_id_limit);
d41f3e75 1035 numa_fw_cfg[apic_id + 1] = cpu_to_le64(cpus->cpus[i].props.node_id);
11c2fd3e
AL		 1036 }
1037 for (i = 0; i < nb_numa_nodes; i++) {
ebde2465
IM		 1038 numa_fw_cfg[pcms->apic_id_limit + 1 + i] =
1039 cpu_to_le64(numa_info[i].node_mem);
11c2fd3e 1040 }
089da572 1041 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg,
ebde2465 1042 (1 + pcms->apic_id_limit + nb_numa_nodes) *
1d934e89 1043 sizeof(*numa_fw_cfg));
bf483392
AG		 1044
1045 return fw_cfg;
80cabfad
FB		 1046}
1047
642a4f96
TS		 1048static long get_file_size(FILE *f)
1049{
1050 long where, size;
1051
1052 /* XXX: on Unix systems, using fstat() probably makes more sense */
1053
1054 where = ftell(f);
1055 fseek(f, 0, SEEK_END);
1056 size = ftell(f);
1057 fseek(f, where, SEEK_SET);
1058
1059 return size;
1060}
1061
3cbeb524
AB		 1062struct setup_data {
1063 uint64_t next;
1064 uint32_t type;
1065 uint32_t len;
1066 uint8_t data[0];
1067} __attribute__((packed));
1068
ab969087
LM		 1069
1070/*
1071 * The entry point into the kernel for PVH boot is different from
1072 * the native entry point. The PVH entry is defined by the x86/HVM
1073 * direct boot ABI and is available in an ELFNOTE in the kernel binary.
1074 *
1075 * This function is passed to load_elf() when it is called from
1076 * load_elfboot() which then additionally checks for an ELF Note of
1077 * type XEN_ELFNOTE_PHYS32_ENTRY and passes it to this function to
1078 * parse the PVH entry address from the ELF Note.
1079 *
1080 * Due to trickery in elf_opts.h, load_elf() is actually available as
1081 * load_elf32() or load_elf64() and this routine needs to be able
1082 * to deal with being called as 32 or 64 bit.
1083 *
1084 * The address of the PVH entry point is saved to the 'pvh_start_addr'
1085 * global variable. (although the entry point is 32-bit, the kernel
1086 * binary can be either 32-bit or 64-bit).
1087 */
1088static uint64_t read_pvh_start_addr(void *arg1, void *arg2, bool is64)
1089{
1090 size_t *elf_note_data_addr;
1091
1092 /* Check if ELF Note header passed in is valid */
1093 if (arg1 == NULL) {
1094 return 0;
1095 }
1096
1097 if (is64) {
1098 struct elf64_note *nhdr64 = (struct elf64_note *)arg1;
1099 uint64_t nhdr_size64 = sizeof(struct elf64_note);
1100 uint64_t phdr_align = *(uint64_t *)arg2;
1101 uint64_t nhdr_namesz = nhdr64->n_namesz;
1102
1103 elf_note_data_addr =
1104 ((void *)nhdr64) + nhdr_size64 +
1105 QEMU_ALIGN_UP(nhdr_namesz, phdr_align);
1106 } else {
1107 struct elf32_note *nhdr32 = (struct elf32_note *)arg1;
1108 uint32_t nhdr_size32 = sizeof(struct elf32_note);
1109 uint32_t phdr_align = *(uint32_t *)arg2;
1110 uint32_t nhdr_namesz = nhdr32->n_namesz;
1111
1112 elf_note_data_addr =
1113 ((void *)nhdr32) + nhdr_size32 +
1114 QEMU_ALIGN_UP(nhdr_namesz, phdr_align);
1115 }
1116
1117 pvh_start_addr = *elf_note_data_addr;
1118
1119 return pvh_start_addr;
1120}
1121
1122static bool load_elfboot(const char *kernel_filename,
1123 int kernel_file_size,
1124 uint8_t *header,
1125 size_t pvh_xen_start_addr,
1126 FWCfgState *fw_cfg)
1127{
1128 uint32_t flags = 0;
1129 uint32_t mh_load_addr = 0;
1130 uint32_t elf_kernel_size = 0;
1131 uint64_t elf_entry;
1132 uint64_t elf_low, elf_high;
1133 int kernel_size;
1134
1135 if (ldl_p(header) != 0x464c457f) {
1136 return false; /* no elfboot */
1137 }
1138
1139 bool elf_is64 = header[EI_CLASS] == ELFCLASS64;
1140 flags = elf_is64 ?
1141 ((Elf64_Ehdr *)header)->e_flags : ((Elf32_Ehdr *)header)->e_flags;
1142
1143 if (flags & 0x00010004) { /* LOAD_ELF_HEADER_HAS_ADDR */
1144 error_report("elfboot unsupported flags = %x", flags);
1145 exit(1);
1146 }
1147
1148 uint64_t elf_note_type = XEN_ELFNOTE_PHYS32_ENTRY;
1149 kernel_size = load_elf(kernel_filename, read_pvh_start_addr,
1150 NULL, &elf_note_type, &elf_entry,
1151 &elf_low, &elf_high, 0, I386_ELF_MACHINE,
1152 0, 0);
1153
1154 if (kernel_size < 0) {
1155 error_report("Error while loading elf kernel");
1156 exit(1);
1157 }
1158 mh_load_addr = elf_low;
1159 elf_kernel_size = elf_high - elf_low;
1160
1161 if (pvh_start_addr == 0) {
1162 error_report("Error loading uncompressed kernel without PVH ELF Note");
1163 exit(1);
1164 }
1165 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ENTRY, pvh_start_addr);
1166 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, mh_load_addr);
1167 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, elf_kernel_size);
1168
1169 return true;
1170}
1171
df1f79fd
EH		 1172static void load_linux(PCMachineState *pcms,
1173 FWCfgState *fw_cfg)
642a4f96
TS		 1174{
1175 uint16_t protocol;
f3839fda 1176 int setup_size, kernel_size, cmdline_size;
3cbeb524 1177 int dtb_size, setup_data_offset;
642a4f96 1178 uint32_t initrd_max;
c24323dd 1179 uint8_t header[8192], *setup, *kernel;
a8170e5e 1180 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
45a50b16 1181 FILE *f;
bf4e5d92 1182 char *vmode;
df1f79fd 1183 MachineState *machine = MACHINE(pcms);
cd4040ec 1184 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
3cbeb524 1185 struct setup_data *setup_data;
df1f79fd
EH		 1186 const char *kernel_filename = machine->kernel_filename;
1187 const char *initrd_filename = machine->initrd_filename;
3cbeb524 1188 const char *dtb_filename = machine->dtb;
df1f79fd 1189 const char *kernel_cmdline = machine->kernel_cmdline;
642a4f96
TS		 1190
1191 /* Align to 16 bytes as a paranoia measure */
1192 cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
1193
1194 /* load the kernel header */
1195 f = fopen(kernel_filename, "rb");
1196 if (!f || !(kernel_size = get_file_size(f)) ||
0f9d76e5
LG		 1197 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
1198 MIN(ARRAY_SIZE(header), kernel_size)) {
1199 fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
1200 kernel_filename, strerror(errno));
1201 exit(1);
642a4f96
TS		 1202 }
1203
1204 /* kernel protocol version */
bc4edd79 1205#if 0
642a4f96 1206 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
bc4edd79 1207#endif
0f9d76e5
LG		 1208 if (ldl_p(header+0x202) == 0x53726448) {
1209 protocol = lduw_p(header+0x206);
1210 } else {
5dc8ab36
SG		 1211 /*
1212 * This could be a multiboot kernel. If it is, let's stop treating it
1213 * like a Linux kernel.
1214 * Note: some multiboot images could be in the ELF format (the same of
1215 * PVH), so we try multiboot first since we check the multiboot magic
1216 * header before to load it.
1217 */
1218 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
1219 kernel_cmdline, kernel_size, header)) {
1220 return;
1221 }
ab969087
LM		 1222 /*
1223 * Check if the file is an uncompressed kernel file (ELF) and load it,
1224 * saving the PVH entry point used by the x86/HVM direct boot ABI.
1225 * If load_elfboot() is successful, populate the fw_cfg info.
1226 */
fda672b5
SG		 1227 if (pcmc->pvh_enabled &&
1228 load_elfboot(kernel_filename, kernel_size,
ab969087 1229 header, pvh_start_addr, fw_cfg)) {
ab969087
LM		 1230 fclose(f);
1231
1232 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
1233 strlen(kernel_cmdline) + 1);
1234 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
1235
ab969087
LM		 1236 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, sizeof(header));
1237 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA,
1238 header, sizeof(header));
1239
c5bf7847
SG		 1240 /* load initrd */
1241 if (initrd_filename) {
1242 gsize initrd_size;
1243 gchar *initrd_data;
1244 GError *gerr = NULL;
1245
1246 if (!g_file_get_contents(initrd_filename, &initrd_data,
1247 &initrd_size, &gerr)) {
1248 fprintf(stderr, "qemu: error reading initrd %s: %s\n",
1249 initrd_filename, gerr->message);
1250 exit(1);
1251 }
1252
1253 initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1;
1254 if (initrd_size >= initrd_max) {
1255 fprintf(stderr, "qemu: initrd is too large, cannot support."
1256 "(max: %"PRIu32", need %"PRId64")\n",
1257 initrd_max, (uint64_t)initrd_size);
1258 exit(1);
1259 }
1260
1261 initrd_addr = (initrd_max - initrd_size) & ~4095;
1262
1263 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
1264 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
1265 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data,
1266 initrd_size);
1267 }
1268
1fb0d709
SG		 1269 option_rom[nb_option_roms].bootindex = 0;
1270 option_rom[nb_option_roms].name = "pvh.bin";
1271 nb_option_roms++;
1272
ab969087
LM		 1273 return;
1274 }
0f9d76e5 1275 protocol = 0;
f16408df 1276 }
642a4f96
TS		 1277
1278 if (protocol < 0x200 || !(header[0x211] & 0x01)) {
0f9d76e5
LG		 1279 /* Low kernel */
1280 real_addr = 0x90000;
1281 cmdline_addr = 0x9a000 - cmdline_size;
1282 prot_addr = 0x10000;
642a4f96 1283 } else if (protocol < 0x202) {
0f9d76e5
LG		 1284 /* High but ancient kernel */
1285 real_addr = 0x90000;
1286 cmdline_addr = 0x9a000 - cmdline_size;
1287 prot_addr = 0x100000;
642a4f96 1288 } else {
0f9d76e5
LG		 1289 /* High and recent kernel */
1290 real_addr = 0x10000;
1291 cmdline_addr = 0x20000;
1292 prot_addr = 0x100000;
642a4f96
TS		 1293 }
1294
bc4edd79 1295#if 0
642a4f96 1296 fprintf(stderr,
0f9d76e5
LG		 1297 "qemu: real_addr = 0x" TARGET_FMT_plx "\n"
1298 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n"
1299 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n",
1300 real_addr,
1301 cmdline_addr,
1302 prot_addr);
bc4edd79 1303#endif
642a4f96
TS		 1304
1305 /* highest address for loading the initrd */
aab50e53
LZ		 1306 if (protocol >= 0x20c &&
1307 lduw_p(header+0x236) & XLF_CAN_BE_LOADED_ABOVE_4G) {
1308 /*
1309 * Linux has supported initrd up to 4 GB for a very long time (2007,
1310 * long before XLF_CAN_BE_LOADED_ABOVE_4G which was added in 2013),
1311 * though it only sets initrd_max to 2 GB to "work around bootloader
1312 * bugs". Luckily, QEMU firmware(which does something like bootloader)
1313 * has supported this.
1314 *
1315 * It's believed that if XLF_CAN_BE_LOADED_ABOVE_4G is set, initrd can
1316 * be loaded into any address.
1317 *
1318 * In addition, initrd_max is uint32_t simply because QEMU doesn't
1319 * support the 64-bit boot protocol (specifically the ext_ramdisk_image
1320 * field).
1321 *
1322 * Therefore here just limit initrd_max to UINT32_MAX simply as well.
1323 */
1324 initrd_max = UINT32_MAX;
1325 } else if (protocol >= 0x203) {
0f9d76e5
LG		 1326 initrd_max = ldl_p(header+0x22c);
1327 } else {
1328 initrd_max = 0x37ffffff;
1329 }
642a4f96 1330
cd4040ec
EH		 1331 if (initrd_max >= pcms->below_4g_mem_size - pcmc->acpi_data_size) {
1332 initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1;
927766c7 1333 }
642a4f96 1334
57a46d05
AG		 1335 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
1336 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
96f80586 1337 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
642a4f96
TS		 1338
1339 if (protocol >= 0x202) {
0f9d76e5 1340 stl_p(header+0x228, cmdline_addr);
642a4f96 1341 } else {
0f9d76e5
LG		 1342 stw_p(header+0x20, 0xA33F);
1343 stw_p(header+0x22, cmdline_addr-real_addr);
642a4f96
TS		 1344 }
1345
bf4e5d92
PT		 1346 /* handle vga= parameter */
1347 vmode = strstr(kernel_cmdline, "vga=");
1348 if (vmode) {
1349 unsigned int video_mode;
1350 /* skip "vga=" */
1351 vmode += 4;
1352 if (!strncmp(vmode, "normal", 6)) {
1353 video_mode = 0xffff;
1354 } else if (!strncmp(vmode, "ext", 3)) {
1355 video_mode = 0xfffe;
1356 } else if (!strncmp(vmode, "ask", 3)) {
1357 video_mode = 0xfffd;
1358 } else {
1359 video_mode = strtol(vmode, NULL, 0);
1360 }
1361 stw_p(header+0x1fa, video_mode);
1362 }
1363
642a4f96 1364 /* loader type */
5cbdb3a3 1365 /* High nybble = B reserved for QEMU; low nybble is revision number.
642a4f96
TS		 1366 If this code is substantially changed, you may want to consider
1367 incrementing the revision. */
0f9d76e5
LG		 1368 if (protocol >= 0x200) {
1369 header[0x210] = 0xB0;
1370 }
642a4f96
TS		 1371 /* heap */
1372 if (protocol >= 0x201) {
0f9d76e5
LG		 1373 header[0x211] |= 0x80; /* CAN_USE_HEAP */
1374 stw_p(header+0x224, cmdline_addr-real_addr-0x200);
642a4f96
TS		 1375 }
1376
1377 /* load initrd */
1378 if (initrd_filename) {
c24323dd
PM		 1379 gsize initrd_size;
1380 gchar *initrd_data;
1381 GError *gerr = NULL;
1382
0f9d76e5
LG		 1383 if (protocol < 0x200) {
1384 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
1385 exit(1);
1386 }
642a4f96 1387
c24323dd
PM		 1388 if (!g_file_get_contents(initrd_filename, &initrd_data,
1389 &initrd_size, &gerr)) {
7454e51d 1390 fprintf(stderr, "qemu: error reading initrd %s: %s\n",
c24323dd 1391 initrd_filename, gerr->message);
d6fa4b77 1392 exit(1);
c24323dd
PM		 1393 }
1394 if (initrd_size >= initrd_max) {
f3839fda 1395 fprintf(stderr, "qemu: initrd is too large, cannot support."
c24323dd
PM		 1396 "(max: %"PRIu32", need %"PRId64")\n",
1397 initrd_max, (uint64_t)initrd_size);
f3839fda 1398 exit(1);
d6fa4b77
MK		 1399 }
1400
45a50b16 1401 initrd_addr = (initrd_max-initrd_size) & ~4095;
57a46d05 1402
57a46d05
AG		 1403 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
1404 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
1405 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
642a4f96 1406
0f9d76e5
LG		 1407 stl_p(header+0x218, initrd_addr);
1408 stl_p(header+0x21c, initrd_size);
642a4f96
TS		 1409 }
1410
45a50b16 1411 /* load kernel and setup */
642a4f96 1412 setup_size = header[0x1f1];
0f9d76e5
LG		 1413 if (setup_size == 0) {
1414 setup_size = 4;
1415 }
642a4f96 1416 setup_size = (setup_size+1)*512;
ec5fd402
PB		 1417 if (setup_size > kernel_size) {
1418 fprintf(stderr, "qemu: invalid kernel header\n");
1419 exit(1);
1420 }
45a50b16 1421 kernel_size -= setup_size;
642a4f96 1422
7267c094
AL		 1423 setup = g_malloc(setup_size);
1424 kernel = g_malloc(kernel_size);
45a50b16 1425 fseek(f, 0, SEEK_SET);
5a41ecc5
KS		 1426 if (fread(setup, 1, setup_size, f) != setup_size) {
1427 fprintf(stderr, "fread() failed\n");
1428 exit(1);
1429 }
1430 if (fread(kernel, 1, kernel_size, f) != kernel_size) {
1431 fprintf(stderr, "fread() failed\n");
1432 exit(1);
1433 }
642a4f96 1434 fclose(f);
3cbeb524
AB		 1435
1436 /* append dtb to kernel */
1437 if (dtb_filename) {
1438 if (protocol < 0x209) {
1439 fprintf(stderr, "qemu: Linux kernel too old to load a dtb\n");
1440 exit(1);
1441 }
1442
1443 dtb_size = get_image_size(dtb_filename);
1444 if (dtb_size <= 0) {
1445 fprintf(stderr, "qemu: error reading dtb %s: %s\n",
1446 dtb_filename, strerror(errno));
1447 exit(1);
1448 }
1449
1450 setup_data_offset = QEMU_ALIGN_UP(kernel_size, 16);
1451 kernel_size = setup_data_offset + sizeof(struct setup_data) + dtb_size;
1452 kernel = g_realloc(kernel, kernel_size);
1453
1454 stq_p(header+0x250, prot_addr + setup_data_offset);
1455
1456 setup_data = (struct setup_data *)(kernel + setup_data_offset);
1457 setup_data->next = 0;
1458 setup_data->type = cpu_to_le32(SETUP_DTB);
1459 setup_data->len = cpu_to_le32(dtb_size);
1460
1461 load_image_size(dtb_filename, setup_data->data, dtb_size);
1462 }
1463
45a50b16 1464 memcpy(setup, header, MIN(sizeof(header), setup_size));
57a46d05
AG		 1465
1466 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
1467 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1468 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
1469
1470 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
1471 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
1472 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
1473
98e753a6
IM		 1474 option_rom[nb_option_roms].bootindex = 0;
1475 option_rom[nb_option_roms].name = "linuxboot.bin";
1476 if (pcmc->linuxboot_dma_enabled && fw_cfg_dma_enabled(fw_cfg)) {
b2a575a1 1477 option_rom[nb_option_roms].name = "linuxboot_dma.bin";
b2a575a1 1478 }
57a46d05 1479 nb_option_roms++;
642a4f96
TS		 1480}
1481
b41a2cd1
FB		 1482#define NE2000_NB_MAX 6
1483
675d6f82
BS		 1484static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
1485 0x280, 0x380 };
1486static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
b41a2cd1 1487
48a18b3c 1488void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
a41b2ff2
PB		 1489{
1490 static int nb_ne2k = 0;
1491
1492 if (nb_ne2k == NE2000_NB_MAX)
1493 return;
48a18b3c 1494 isa_ne2000_init(bus, ne2000_io[nb_ne2k],
9453c5bc 1495 ne2000_irq[nb_ne2k], nd);
a41b2ff2
PB		 1496 nb_ne2k++;
1497}
1498
92a16d7a 1499DeviceState *cpu_get_current_apic(void)
0e26b7b8 1500{
4917cf44
AF		 1501 if (current_cpu) {
1502 X86CPU *cpu = X86_CPU(current_cpu);
02e51483 1503 return cpu->apic_state;
0e26b7b8
BS		 1504 } else {
1505 return NULL;
1506 }
1507}
1508
845773ab 1509void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
53b67b30 1510{
c3affe56 1511 X86CPU *cpu = opaque;
53b67b30
BS		 1512
1513 if (level) {
c3affe56 1514 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
53b67b30
BS		 1515 }
1516}
1517
074281d6 1518static void pc_new_cpu(const char *typename, int64_t apic_id, Error **errp)
31050930 1519{
074281d6 1520 Object *cpu = NULL;
31050930
IM		 1521 Error *local_err = NULL;
1522
074281d6 1523 cpu = object_new(typename);
31050930 1524
c7b4efb4 1525 object_property_set_uint(cpu, apic_id, "apic-id", &local_err);
074281d6 1526 object_property_set_bool(cpu, true, "realized", &local_err);
31050930 1527
074281d6 1528 object_unref(cpu);
021c9d25 1529 error_propagate(errp, local_err);
31050930
IM		 1530}
1531
c649983b
IM		 1532void pc_hot_add_cpu(const int64_t id, Error **errp)
1533{
38690a1c 1534 MachineState *ms = MACHINE(qdev_get_machine());
c649983b 1535 int64_t apic_id = x86_cpu_apic_id_from_index(id);
0e3bd562 1536 Error *local_err = NULL;
c649983b 1537
8de433cb
IM		 1538 if (id < 0) {
1539 error_setg(errp, "Invalid CPU id: %" PRIi64, id);
1540 return;
1541 }
1542
5ff020b7
EH		 1543 if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) {
1544 error_setg(errp, "Unable to add CPU: %" PRIi64
1545 ", resulting APIC ID (%" PRIi64 ") is too large",
1546 id, apic_id);
1547 return;
1548 }
1549
311ca98d 1550 pc_new_cpu(ms->cpu_type, apic_id, &local_err);
0e3bd562
AF		 1551 if (local_err) {
1552 error_propagate(errp, local_err);
1553 return;
1554 }
c649983b
IM		 1555}
1556
4884b7bf 1557void pc_cpus_init(PCMachineState *pcms)
70166477
IY		 1558{
1559 int i;
c96a1c0b 1560 const CPUArchIdList *possible_cpus;
311ca98d 1561 MachineState *ms = MACHINE(pcms);
c96a1c0b 1562 MachineClass *mc = MACHINE_GET_CLASS(pcms);
70166477 1563
ebde2465
IM		 1564 /* Calculates the limit to CPU APIC ID values
1565 *
1566 * Limit for the APIC ID value, so that all
1567 * CPU APIC IDs are < pcms->apic_id_limit.
1568 *
1569 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init().
1570 */
1571 pcms->apic_id_limit = x86_cpu_apic_id_from_index(max_cpus - 1) + 1;
311ca98d 1572 possible_cpus = mc->possible_cpu_arch_ids(ms);
c96a1c0b 1573 for (i = 0; i < smp_cpus; i++) {
d342eb76
IM		 1574 pc_new_cpu(possible_cpus->cpus[i].type, possible_cpus->cpus[i].arch_id,
1575 &error_fatal);
70166477
IY		 1576 }
1577}
1578
217f1b4a
HZ		 1579static void pc_build_feature_control_file(PCMachineState *pcms)
1580{
38690a1c
IM		 1581 MachineState *ms = MACHINE(pcms);
1582 X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu);
217f1b4a
HZ		 1583 CPUX86State *env = &cpu->env;
1584 uint32_t unused, ecx, edx;
1585 uint64_t feature_control_bits = 0;
1586 uint64_t *val;
1587
1588 cpu_x86_cpuid(env, 1, 0, &unused, &unused, &ecx, &edx);
1589 if (ecx & CPUID_EXT_VMX) {
1590 feature_control_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1591 }
1592
1593 if ((edx & (CPUID_EXT2_MCE | CPUID_EXT2_MCA)) ==
1594 (CPUID_EXT2_MCE | CPUID_EXT2_MCA) &&
1595 (env->mcg_cap & MCG_LMCE_P)) {
1596 feature_control_bits |= FEATURE_CONTROL_LMCE;
1597 }
1598
1599 if (!feature_control_bits) {
1600 return;
1601 }
1602
1603 val = g_malloc(sizeof(*val));
1604 *val = cpu_to_le64(feature_control_bits | FEATURE_CONTROL_LOCKED);
1605 fw_cfg_add_file(pcms->fw_cfg, "etc/msr_feature_control", val, sizeof(*val));
1606}
1607
e3cadac0
IM		 1608static void rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count)
1609{
1610 if (cpus_count > 0xff) {
1611 /* If the number of CPUs can't be represented in 8 bits, the
1612 * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just
1613 * to make old BIOSes fail more predictably.
1614 */
1615 rtc_set_memory(rtc, 0x5f, 0);
1616 } else {
1617 rtc_set_memory(rtc, 0x5f, cpus_count - 1);
1618 }
1619}
1620
3459a625 1621static
9ebeed0c 1622void pc_machine_done(Notifier *notifier, void *data)
3459a625 1623{
9ebeed0c
EH		 1624 PCMachineState *pcms = container_of(notifier,
1625 PCMachineState, machine_done);
1626 PCIBus *bus = pcms->bus;
2118196b 1627
ba157b69 1628 /* set the number of CPUs */
e3cadac0 1629 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus);
ba157b69 1630
2118196b
MA		 1631 if (bus) {
1632 int extra_hosts = 0;
1633
1634 QLIST_FOREACH(bus, &bus->child, sibling) {
1635 /* look for expander root buses */
1636 if (pci_bus_is_root(bus)) {
1637 extra_hosts++;
1638 }
1639 }
f264d360 1640 if (extra_hosts && pcms->fw_cfg) {
2118196b
MA		 1641 uint64_t *val = g_malloc(sizeof(*val));
1642 *val = cpu_to_le64(extra_hosts);
f264d360 1643 fw_cfg_add_file(pcms->fw_cfg,
2118196b
MA		 1644 "etc/extra-pci-roots", val, sizeof(*val));
1645 }
1646 }
1647
bb292f5a 1648 acpi_setup();
6d42eefa 1649 if (pcms->fw_cfg) {
f2098f48 1650 pc_build_smbios(pcms);
217f1b4a 1651 pc_build_feature_control_file(pcms);
e3cadac0
IM		 1652 /* update FW_CFG_NB_CPUS to account for -device added CPUs */
1653 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
6d42eefa 1654 }
60c5e104 1655
1a26f466 1656 if (pcms->apic_id_limit > 255 && !xen_enabled()) {
60c5e104
IM		 1657 IntelIOMMUState *iommu = INTEL_IOMMU_DEVICE(x86_iommu_get_default());
1658
a924b3d8 1659 if (!iommu || !x86_iommu_ir_supported(X86_IOMMU_DEVICE(iommu)) ||
60c5e104
IM		 1660 iommu->intr_eim != ON_OFF_AUTO_ON) {
1661 error_report("current -smp configuration requires "
1662 "Extended Interrupt Mode enabled. "
1663 "You can add an IOMMU using: "
1664 "-device intel-iommu,intremap=on,eim=on");
1665 exit(EXIT_FAILURE);
1666 }
1667 }
3459a625
MT		 1668}
1669
e4e8ba04 1670void pc_guest_info_init(PCMachineState *pcms)
3459a625 1671{
1f3aba37 1672 int i;
b20c9bd5 1673
dd4c2f01
EH		 1674 pcms->apic_xrupt_override = kvm_allows_irq0_override();
1675 pcms->numa_nodes = nb_numa_nodes;
1676 pcms->node_mem = g_malloc0(pcms->numa_nodes *
1677 sizeof *pcms->node_mem);
8c85901e 1678 for (i = 0; i < nb_numa_nodes; i++) {
dd4c2f01 1679 pcms->node_mem[i] = numa_info[i].node_mem;
8c85901e
WG		 1680 }
1681
9ebeed0c
EH		 1682 pcms->machine_done.notify = pc_machine_done;
1683 qemu_add_machine_init_done_notifier(&pcms->machine_done);
3459a625
MT		 1684}
1685
83d08f26
MT		 1686/* setup pci memory address space mapping into system address space */
1687void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
1688 MemoryRegion *pci_address_space)
39848901 1689{
83d08f26
MT		 1690 /* Set to lower priority than RAM */
1691 memory_region_add_subregion_overlap(system_memory, 0x0,
1692 pci_address_space, -1);
39848901
IM		 1693}
1694
7bc35e0f 1695void xen_load_linux(PCMachineState *pcms)
b33a5bbf
CL		 1696{
1697 int i;
1698 FWCfgState *fw_cfg;
1699
df1f79fd 1700 assert(MACHINE(pcms)->kernel_filename != NULL);
b33a5bbf 1701
305ae888 1702 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE);
e3cadac0 1703 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
b33a5bbf
CL		 1704 rom_set_fw(fw_cfg);
1705
df1f79fd 1706 load_linux(pcms, fw_cfg);
b33a5bbf
CL		 1707 for (i = 0; i < nb_option_roms; i++) {
1708 assert(!strcmp(option_rom[i].name, "linuxboot.bin") ||
b2a575a1 1709 !strcmp(option_rom[i].name, "linuxboot_dma.bin") ||
1fb0d709 1710 !strcmp(option_rom[i].name, "pvh.bin") ||
b33a5bbf
CL		 1711 !strcmp(option_rom[i].name, "multiboot.bin"));
1712 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1713 }
f264d360 1714 pcms->fw_cfg = fw_cfg;
b33a5bbf
CL		 1715}
1716
5934e216
EH		 1717void pc_memory_init(PCMachineState *pcms,
1718 MemoryRegion *system_memory,
1719 MemoryRegion *rom_memory,
1720 MemoryRegion **ram_memory)
80cabfad 1721{
cbc5b5f3
JJ		 1722 int linux_boot, i;
1723 MemoryRegion *ram, *option_rom_mr;
00cb2a99 1724 MemoryRegion *ram_below_4g, *ram_above_4g;
a88b362c 1725 FWCfgState *fw_cfg;
62b160c0 1726 MachineState *machine = MACHINE(pcms);
16a9e8a5 1727 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
d592d303 1728
c8d163bc
EH		 1729 assert(machine->ram_size == pcms->below_4g_mem_size +
1730 pcms->above_4g_mem_size);
9521d42b
PB		 1731
1732 linux_boot = (machine->kernel_filename != NULL);
80cabfad 1733
00cb2a99 1734 /* Allocate RAM. We allocate it as a single memory region and use
66a0a2cb 1735 * aliases to address portions of it, mostly for backwards compatibility
00cb2a99
AK		 1736 * with older qemus that used qemu_ram_alloc().
1737 */
7267c094 1738 ram = g_malloc(sizeof(*ram));
9521d42b
PB		 1739 memory_region_allocate_system_memory(ram, NULL, "pc.ram",
1740 machine->ram_size);
ae0a5466 1741 *ram_memory = ram;
7267c094 1742 ram_below_4g = g_malloc(sizeof(*ram_below_4g));
2c9b15ca 1743 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram,
c8d163bc 1744 0, pcms->below_4g_mem_size);
00cb2a99 1745 memory_region_add_subregion(system_memory, 0, ram_below_4g);
c8d163bc
EH		 1746 e820_add_entry(0, pcms->below_4g_mem_size, E820_RAM);
1747 if (pcms->above_4g_mem_size > 0) {
7267c094 1748 ram_above_4g = g_malloc(sizeof(*ram_above_4g));
2c9b15ca 1749 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram,
c8d163bc
EH		 1750 pcms->below_4g_mem_size,
1751 pcms->above_4g_mem_size);
00cb2a99
AK		 1752 memory_region_add_subregion(system_memory, 0x100000000ULL,
1753 ram_above_4g);
c8d163bc 1754 e820_add_entry(0x100000000ULL, pcms->above_4g_mem_size, E820_RAM);
bbe80adf 1755 }
82b36dc3 1756
bb292f5a 1757 if (!pcmc->has_reserved_memory &&
ca8336f3 1758 (machine->ram_slots ||
9521d42b 1759 (machine->maxram_size > machine->ram_size))) {
ca8336f3
IM		 1760 MachineClass *mc = MACHINE_GET_CLASS(machine);
1761
1762 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
1763 mc->name);
1764 exit(EXIT_FAILURE);
1765 }
1766
b0c14ec4
DH		 1767 /* always allocate the device memory information */
1768 machine->device_memory = g_malloc0(sizeof(*machine->device_memory));
1769
f2ffbe2b 1770 /* initialize device memory address space */
bb292f5a 1771 if (pcmc->has_reserved_memory &&
9521d42b 1772 (machine->ram_size < machine->maxram_size)) {
f2ffbe2b 1773 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size;
619d11e4 1774
a0cc8856
IM		 1775 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
1776 error_report("unsupported amount of memory slots: %"PRIu64,
1777 machine->ram_slots);
1778 exit(EXIT_FAILURE);
1779 }
1780
f2c38522
PK		 1781 if (QEMU_ALIGN_UP(machine->maxram_size,
1782 TARGET_PAGE_SIZE) != machine->maxram_size) {
1783 error_report("maximum memory size must by aligned to multiple of "
1784 "%d bytes", TARGET_PAGE_SIZE);
1785 exit(EXIT_FAILURE);
1786 }
1787
b0c14ec4 1788 machine->device_memory->base =
d471bf3e 1789 ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, 1 * GiB);
619d11e4 1790
16a9e8a5 1791 if (pcmc->enforce_aligned_dimm) {
f2ffbe2b 1792 /* size device region assuming 1G page max alignment per slot */
d471bf3e 1793 device_mem_size += (1 * GiB) * machine->ram_slots;
085f8e88
IM		 1794 }
1795
f2ffbe2b
DH		 1796 if ((machine->device_memory->base + device_mem_size) <
1797 device_mem_size) {
619d11e4
IM		 1798 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT,
1799 machine->maxram_size);
1800 exit(EXIT_FAILURE);
1801 }
1802
b0c14ec4 1803 memory_region_init(&machine->device_memory->mr, OBJECT(pcms),
f2ffbe2b 1804 "device-memory", device_mem_size);
b0c14ec4
DH		 1805 memory_region_add_subregion(system_memory, machine->device_memory->base,
1806 &machine->device_memory->mr);
619d11e4 1807 }
cbc5b5f3
JJ		 1808
1809 /* Initialize PC system firmware */
5e640a9e 1810 pc_system_firmware_init(pcms, rom_memory);
00cb2a99 1811
7267c094 1812 option_rom_mr = g_malloc(sizeof(*option_rom_mr));
98a99ce0 1813 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE,
f8ed85ac 1814 &error_fatal);
208fa0e4
IM		 1815 if (pcmc->pci_enabled) {
1816 memory_region_set_readonly(option_rom_mr, true);
1817 }
4463aee6 1818 memory_region_add_subregion_overlap(rom_memory,
00cb2a99
AK		 1819 PC_ROM_MIN_VGA,
1820 option_rom_mr,
1821 1);
f753ff16 1822
ebde2465 1823 fw_cfg = bochs_bios_init(&address_space_memory, pcms);
c886fc4c 1824
8832cb80 1825 rom_set_fw(fw_cfg);
1d108d97 1826
b0c14ec4 1827 if (pcmc->has_reserved_memory && machine->device_memory->base) {
de268e13 1828 uint64_t *val = g_malloc(sizeof(*val));
2f8b5008 1829 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
b0c14ec4 1830 uint64_t res_mem_end = machine->device_memory->base;
2f8b5008
IM		 1831
1832 if (!pcmc->broken_reserved_end) {
b0c14ec4 1833 res_mem_end += memory_region_size(&machine->device_memory->mr);
2f8b5008 1834 }
d471bf3e 1835 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB));
de268e13
IM		 1836 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
1837 }
1838
f753ff16 1839 if (linux_boot) {
df1f79fd 1840 load_linux(pcms, fw_cfg);
f753ff16
PB		 1841 }
1842
1843 for (i = 0; i < nb_option_roms; i++) {
2e55e842 1844 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
406c8df3 1845 }
f264d360 1846 pcms->fw_cfg = fw_cfg;
cb135f59
PX		 1847
1848 /* Init default IOAPIC address space */
1849 pcms->ioapic_as = &address_space_memory;
3d53f5c3
IY		 1850}
1851
9fa99d25
MA		 1852/*
1853 * The 64bit pci hole starts after "above 4G RAM" and
1854 * potentially the space reserved for memory hotplug.
1855 */
1856uint64_t pc_pci_hole64_start(void)
1857{
1858 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
1859 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
b0c14ec4 1860 MachineState *ms = MACHINE(pcms);
9fa99d25
MA		 1861 uint64_t hole64_start = 0;
1862
b0c14ec4
DH		 1863 if (pcmc->has_reserved_memory && ms->device_memory->base) {
1864 hole64_start = ms->device_memory->base;
9fa99d25 1865 if (!pcmc->broken_reserved_end) {
b0c14ec4 1866 hole64_start += memory_region_size(&ms->device_memory->mr);
9fa99d25
MA		 1867 }
1868 } else {
1869 hole64_start = 0x100000000ULL + pcms->above_4g_mem_size;
1870 }
1871
d471bf3e 1872 return ROUND_UP(hole64_start, 1 * GiB);
9fa99d25
MA		 1873}
1874
0b0cc076 1875qemu_irq pc_allocate_cpu_irq(void)
845773ab 1876{
0b0cc076 1877 return qemu_allocate_irq(pic_irq_request, NULL, 0);
845773ab
IY		 1878}
1879
48a18b3c 1880DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
765d7908 1881{
ad6d45fa
AL		 1882 DeviceState *dev = NULL;
1883
bab47d9a 1884 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA);
16094b75
AJ		 1885 if (pci_bus) {
1886 PCIDevice *pcidev = pci_vga_init(pci_bus);
1887 dev = pcidev ? &pcidev->qdev : NULL;
1888 } else if (isa_bus) {
1889 ISADevice *isadev = isa_vga_init(isa_bus);
4a17cc4f 1890 dev = isadev ? DEVICE(isadev) : NULL;
765d7908 1891 }
bab47d9a 1892 rom_reset_order_override();
ad6d45fa 1893 return dev;
765d7908
IY		 1894}
1895
258711c6
JG		 1896static const MemoryRegionOps ioport80_io_ops = {
1897 .write = ioport80_write,
c02e1eac 1898 .read = ioport80_read,
258711c6
JG		 1899 .endianness = DEVICE_NATIVE_ENDIAN,
1900 .impl = {
1901 .min_access_size = 1,
1902 .max_access_size = 1,
1903 },
1904};
1905
1906static const MemoryRegionOps ioportF0_io_ops = {
1907 .write = ioportF0_write,
c02e1eac 1908 .read = ioportF0_read,
258711c6
JG		 1909 .endianness = DEVICE_NATIVE_ENDIAN,
1910 .impl = {
1911 .min_access_size = 1,
1912 .max_access_size = 1,
1913 },
1914};
1915
ac64273c
PMD		 1916static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport)
1917{
1918 int i;
1919 DriveInfo *fd[MAX_FD];
1920 qemu_irq *a20_line;
1921 ISADevice *i8042, *port92, *vmmouse;
1922
def337ff 1923 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS);
ac64273c
PMD		 1924 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
1925
1926 for (i = 0; i < MAX_FD; i++) {
1927 fd[i] = drive_get(IF_FLOPPY, 0, i);
1928 create_fdctrl |= !!fd[i];
1929 }
1930 if (create_fdctrl) {
1931 fdctrl_init_isa(isa_bus, fd);
1932 }
1933
1934 i8042 = isa_create_simple(isa_bus, "i8042");
1935 if (!no_vmport) {
1936 vmport_init(isa_bus);
1937 vmmouse = isa_try_create(isa_bus, "vmmouse");
1938 } else {
1939 vmmouse = NULL;
1940 }
1941 if (vmmouse) {
1942 DeviceState *dev = DEVICE(vmmouse);
1943 qdev_prop_set_ptr(dev, "ps2_mouse", i8042);
1944 qdev_init_nofail(dev);
1945 }
1946 port92 = isa_create_simple(isa_bus, "port92");
1947
1948 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1949 i8042_setup_a20_line(i8042, a20_line[0]);
1950 port92_init(port92, a20_line[1]);
1951 g_free(a20_line);
1952}
1953
48a18b3c 1954void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
1611977c 1955 ISADevice **rtc_state,
fd53c87c 1956 bool create_fdctrl,
7a10ef51 1957 bool no_vmport,
feddd2fd 1958 bool has_pit,
3a87d009 1959 uint32_t hpet_irqs)
ffe513da
IY		 1960{
1961 int i;
ce967e2f
JK		 1962 DeviceState *hpet = NULL;
1963 int pit_isa_irq = 0;
1964 qemu_irq pit_alt_irq = NULL;
7d932dfd 1965 qemu_irq rtc_irq = NULL;
ac64273c 1966 ISADevice *pit = NULL;
258711c6
JG		 1967 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1968 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
ffe513da 1969
2c9b15ca 1970 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
258711c6 1971 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
ffe513da 1972
2c9b15ca 1973 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
258711c6 1974 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
ffe513da 1975
5d17c0d2
JK		 1976 /*
1977 * Check if an HPET shall be created.
1978 *
1979 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1980 * when the HPET wants to take over. Thus we have to disable the latter.
1981 */
1982 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
7a10ef51 1983 /* In order to set property, here not using sysbus_try_create_simple */
51116102 1984 hpet = qdev_try_create(NULL, TYPE_HPET);
dd703b99 1985 if (hpet) {
7a10ef51
LPF		 1986 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7
1987 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23,
1988 * IRQ8 and IRQ2.
1989 */
5d7fb0f2 1990 uint8_t compat = object_property_get_uint(OBJECT(hpet),
7a10ef51
LPF		 1991 HPET_INTCAP, NULL);
1992 if (!compat) {
1993 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
1994 }
1995 qdev_init_nofail(hpet);
1996 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
1997
b881fbe9 1998 for (i = 0; i < GSI_NUM_PINS; i++) {
1356b98d 1999 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
dd703b99 2000 }
ce967e2f
JK		 2001 pit_isa_irq = -1;
2002 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
2003 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
822557eb 2004 }
ffe513da 2005 }
6c646a11 2006 *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq);
7d932dfd
JK		 2007
2008 qemu_register_boot_set(pc_boot_set, *rtc_state);
2009
feddd2fd 2010 if (!xen_enabled() && has_pit) {
15eafc2e 2011 if (kvm_pit_in_kernel()) {
c2d8d311
SS		 2012 pit = kvm_pit_init(isa_bus, 0x40);
2013 } else {
acf695ec 2014 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
c2d8d311
SS		 2015 }
2016 if (hpet) {
2017 /* connect PIT to output control line of the HPET */
4a17cc4f 2018 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
c2d8d311
SS		 2019 }
2020 pcspk_init(isa_bus, pit);
ce967e2f 2021 }
ffe513da 2022
55f613ac 2023 i8257_dma_init(isa_bus, 0);
ffe513da 2024
ac64273c
PMD		 2025 /* Super I/O */
2026 pc_superio_init(isa_bus, create_fdctrl, no_vmport);
ffe513da
IY		 2027}
2028
4b9c264b 2029void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus)
9011a1a7
IY		 2030{
2031 int i;
2032
bab47d9a 2033 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC);
9011a1a7
IY		 2034 for (i = 0; i < nb_nics; i++) {
2035 NICInfo *nd = &nd_table[i];
4b9c264b 2036 const char *model = nd->model ? nd->model : pcmc->default_nic_model;
9011a1a7 2037
4b9c264b 2038 if (g_str_equal(model, "ne2k_isa")) {
9011a1a7
IY		 2039 pc_init_ne2k_isa(isa_bus, nd);
2040 } else {
4b9c264b 2041 pci_nic_init_nofail(nd, pci_bus, model, NULL);
9011a1a7
IY		 2042 }
2043 }
bab47d9a 2044 rom_reset_order_override();
9011a1a7
IY		 2045}
2046
a39e3564
JB		 2047void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name)
2048{
2049 DeviceState *dev;
2050 SysBusDevice *d;
2051 unsigned int i;
2052
15eafc2e 2053 if (kvm_ioapic_in_kernel()) {
34bec7a8 2054 dev = qdev_create(NULL, TYPE_KVM_IOAPIC);
a39e3564 2055 } else {
34bec7a8 2056 dev = qdev_create(NULL, TYPE_IOAPIC);
a39e3564
JB		 2057 }
2058 if (parent_name) {
2059 object_property_add_child(object_resolve_path(parent_name, NULL),
2060 "ioapic", OBJECT(dev), NULL);
2061 }
2062 qdev_init_nofail(dev);
1356b98d 2063 d = SYS_BUS_DEVICE(dev);
3a4a4697 2064 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS);
a39e3564
JB		 2065
2066 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
2067 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i);
2068 }
2069}
d5747cac 2070
d468115b
DH		 2071static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2072 Error **errp)
2073{
2074 const PCMachineState *pcms = PC_MACHINE(hotplug_dev);
b0e62443 2075 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
f6a0d06b 2076 const MachineState *ms = MACHINE(hotplug_dev);
d468115b 2077 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
b0e62443 2078 const uint64_t legacy_align = TARGET_PAGE_SIZE;
ae909496 2079 Error *local_err = NULL;
d468115b
DH		 2080
2081 /*
2082 * When -no-acpi is used with Q35 machine type, no ACPI is built,
2083 * but pcms->acpi_dev is still created. Check !acpi_enabled in
2084 * addition to cover this case.
2085 */
2086 if (!pcms->acpi_dev || !acpi_enabled) {
2087 error_setg(errp,
2088 "memory hotplug is not enabled: missing acpi device or acpi disabled");
2089 return;
2090 }
2091
f6a0d06b 2092 if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
d468115b
DH		 2093 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'");
2094 return;
2095 }
8f1ffe5b 2096
ae909496
TH		 2097 hotplug_handler_pre_plug(pcms->acpi_dev, dev, &local_err);
2098 if (local_err) {
2099 error_propagate(errp, local_err);
2100 return;
2101 }
2102
fd3416f5 2103 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev),
b0e62443 2104 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp);
d468115b
DH		 2105}
2106
bb6e2f7a
DH		 2107static void pc_memory_plug(HotplugHandler *hotplug_dev,
2108 DeviceState *dev, Error **errp)
95bee274
IM		 2109{
2110 Error *local_err = NULL;
2111 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
f6a0d06b 2112 MachineState *ms = MACHINE(hotplug_dev);
7f3cf2d6 2113 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
95bee274 2114
fd3416f5 2115 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms), &local_err);
43bbb49e 2116 if (local_err) {
b8865591
IM		 2117 goto out;
2118 }
2119
7f3cf2d6 2120 if (is_nvdimm) {
f6a0d06b 2121 nvdimm_plug(ms->nvdimms_state);
c7f8d0f3
XG		 2122 }
2123
473ac567 2124 hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort);
95bee274
IM		 2125out:
2126 error_propagate(errp, local_err);
2127}
2128
bb6e2f7a
DH		 2129static void pc_memory_unplug_request(HotplugHandler *hotplug_dev,
2130 DeviceState *dev, Error **errp)
64fec58e 2131{
64fec58e
TC		 2132 Error *local_err = NULL;
2133 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
2134
8cd91ace
HZ		 2135 /*
2136 * When -no-acpi is used with Q35 machine type, no ACPI is built,
2137 * but pcms->acpi_dev is still created. Check !acpi_enabled in
2138 * addition to cover this case.
2139 */
2140 if (!pcms->acpi_dev || !acpi_enabled) {
64fec58e 2141 error_setg(&local_err,
8cd91ace 2142 "memory hotplug is not enabled: missing acpi device or acpi disabled");
64fec58e
TC		 2143 goto out;
2144 }
2145
b097cc52
XG		 2146 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
2147 error_setg(&local_err,
2148 "nvdimm device hot unplug is not supported yet.");
2149 goto out;
2150 }
2151
473ac567
DH		 2152 hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev,
2153 &local_err);
64fec58e
TC		 2154out:
2155 error_propagate(errp, local_err);
2156}
2157
bb6e2f7a
DH		 2158static void pc_memory_unplug(HotplugHandler *hotplug_dev,
2159 DeviceState *dev, Error **errp)
f7d3e29d
TC		 2160{
2161 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
f7d3e29d
TC		 2162 Error *local_err = NULL;
2163
473ac567 2164 hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
f7d3e29d
TC		 2165 if (local_err) {
2166 goto out;
2167 }
2168
fd3416f5 2169 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms));
07578b0a 2170 object_property_set_bool(OBJECT(dev), false, "realized", NULL);
f7d3e29d
TC		 2171 out:
2172 error_propagate(errp, local_err);
2173}
2174
3811ef14
IM		 2175static int pc_apic_cmp(const void *a, const void *b)
2176{
2177 CPUArchId *apic_a = (CPUArchId *)a;
2178 CPUArchId *apic_b = (CPUArchId *)b;
2179
2180 return apic_a->arch_id - apic_b->arch_id;
2181}
2182
7baef5cf 2183/* returns pointer to CPUArchId descriptor that matches CPU's apic_id
38690a1c 2184 * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no
b12227af 2185 * entry corresponding to CPU's apic_id returns NULL.
7baef5cf 2186 */
1ea69c0e 2187static CPUArchId *pc_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
7baef5cf 2188{
7baef5cf
IM		 2189 CPUArchId apic_id, *found_cpu;
2190
1ea69c0e 2191 apic_id.arch_id = id;
38690a1c
IM		 2192 found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus,
2193 ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus),
7baef5cf
IM		 2194 pc_apic_cmp);
2195 if (found_cpu && idx) {
38690a1c 2196 *idx = found_cpu - ms->possible_cpus->cpus;
7baef5cf
IM		 2197 }
2198 return found_cpu;
2199}
2200
5279569e
GZ		 2201static void pc_cpu_plug(HotplugHandler *hotplug_dev,
2202 DeviceState *dev, Error **errp)
2203{
7baef5cf 2204 CPUArchId *found_cpu;
5279569e 2205 Error *local_err = NULL;
1ea69c0e 2206 X86CPU *cpu = X86_CPU(dev);
5279569e
GZ		 2207 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
2208
a44a49db 2209 if (pcms->acpi_dev) {
473ac567 2210 hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
a44a49db
IM		 2211 if (local_err) {
2212 goto out;
2213 }
5279569e
GZ		 2214 }
2215
e3cadac0
IM		 2216 /* increment the number of CPUs */
2217 pcms->boot_cpus++;
26ef65be 2218 if (pcms->rtc) {
e3cadac0 2219 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus);
26ef65be
IM		 2220 }
2221 if (pcms->fw_cfg) {
e3cadac0 2222 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
2d996150
GZ		 2223 }
2224
1ea69c0e 2225 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL);
8aba3842 2226 found_cpu->cpu = OBJECT(dev);
5279569e
GZ		 2227out:
2228 error_propagate(errp, local_err);
2229}
8872c25a
IM		 2230static void pc_cpu_unplug_request_cb(HotplugHandler *hotplug_dev,
2231 DeviceState *dev, Error **errp)
2232{
73360e27 2233 int idx = -1;
8872c25a 2234 Error *local_err = NULL;
1ea69c0e 2235 X86CPU *cpu = X86_CPU(dev);
8872c25a
IM		 2236 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
2237
75ba2ddb
IM		 2238 if (!pcms->acpi_dev) {
2239 error_setg(&local_err, "CPU hot unplug not supported without ACPI");
2240 goto out;
2241 }
2242
1ea69c0e 2243 pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);
73360e27
IM		 2244 assert(idx != -1);
2245 if (idx == 0) {
2246 error_setg(&local_err, "Boot CPU is unpluggable");
2247 goto out;
2248 }
2249
473ac567
DH		 2250 hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev,
2251 &local_err);
8872c25a
IM		 2252 if (local_err) {
2253 goto out;
2254 }
2255
2256 out:
2257 error_propagate(errp, local_err);
2258
2259}
2260
2261static void pc_cpu_unplug_cb(HotplugHandler *hotplug_dev,
2262 DeviceState *dev, Error **errp)
2263{
8fe6374e 2264 CPUArchId *found_cpu;
8872c25a 2265 Error *local_err = NULL;
1ea69c0e 2266 X86CPU *cpu = X86_CPU(dev);
8872c25a
IM		 2267 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
2268
473ac567 2269 hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
8872c25a
IM		 2270 if (local_err) {
2271 goto out;
2272 }
2273
1ea69c0e 2274 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL);
8fe6374e 2275 found_cpu->cpu = NULL;
07578b0a 2276 object_property_set_bool(OBJECT(dev), false, "realized", NULL);
8872c25a 2277
e3cadac0
IM		 2278 /* decrement the number of CPUs */
2279 pcms->boot_cpus--;
2280 /* Update the number of CPUs in CMOS */
2281 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus);
2282 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
8872c25a
IM		 2283 out:
2284 error_propagate(errp, local_err);
2285}
5279569e 2286
4ec60c76
IM		 2287static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
2288 DeviceState *dev, Error **errp)
2289{
2290 int idx;
a15d2728 2291 CPUState *cs;
e8f7b83e 2292 CPUArchId *cpu_slot;
d89c2b8b 2293 X86CPUTopoInfo topo;
4ec60c76 2294 X86CPU *cpu = X86_CPU(dev);
6970c5ff 2295 MachineState *ms = MACHINE(hotplug_dev);
4ec60c76 2296 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
4ec60c76 2297
6970c5ff
IM		 2298 if(!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) {
2299 error_setg(errp, "Invalid CPU type, expected cpu type: '%s'",
2300 ms->cpu_type);
2301 return;
2302 }
2303
e8f7b83e
IM		 2304 /* if APIC ID is not set, set it based on socket/core/thread properties */
2305 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
2306 int max_socket = (max_cpus - 1) / smp_threads / smp_cores;
2307
2308 if (cpu->socket_id < 0) {
2309 error_setg(errp, "CPU socket-id is not set");
2310 return;
2311 } else if (cpu->socket_id > max_socket) {
2312 error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u",
2313 cpu->socket_id, max_socket);
2314 return;
2315 }
2316 if (cpu->core_id < 0) {
2317 error_setg(errp, "CPU core-id is not set");
2318 return;
2319 } else if (cpu->core_id > (smp_cores - 1)) {
2320 error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u",
2321 cpu->core_id, smp_cores - 1);
2322 return;
2323 }
2324 if (cpu->thread_id < 0) {
2325 error_setg(errp, "CPU thread-id is not set");
2326 return;
2327 } else if (cpu->thread_id > (smp_threads - 1)) {
2328 error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u",
2329 cpu->thread_id, smp_threads - 1);
2330 return;
2331 }
2332
2333 topo.pkg_id = cpu->socket_id;
2334 topo.core_id = cpu->core_id;
2335 topo.smt_id = cpu->thread_id;
2336 cpu->apic_id = apicid_from_topo_ids(smp_cores, smp_threads, &topo);
2337 }
2338
1ea69c0e 2339 cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);
4ec60c76 2340 if (!cpu_slot) {
38690a1c
IM		 2341 MachineState *ms = MACHINE(pcms);
2342
e8f7b83e
IM		 2343 x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo);
2344 error_setg(errp, "Invalid CPU [socket: %u, core: %u, thread: %u] with"
2345 " APIC ID %" PRIu32 ", valid index range 0:%d",
2346 topo.pkg_id, topo.core_id, topo.smt_id, cpu->apic_id,
38690a1c 2347 ms->possible_cpus->len - 1);
4ec60c76
IM		 2348 return;
2349 }
2350
2351 if (cpu_slot->cpu) {
2352 error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists",
2353 idx, cpu->apic_id);
2354 return;
2355 }
d89c2b8b
IM		 2356
2357 /* if 'address' properties socket-id/core-id/thread-id are not set, set them
c5514d0e 2358 * so that machine_query_hotpluggable_cpus would show correct values
d89c2b8b
IM		 2359 */
2360 /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn()
2361 * once -smp refactoring is complete and there will be CPU private
2362 * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */
2363 x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo);
2364 if (cpu->socket_id != -1 && cpu->socket_id != topo.pkg_id) {
2365 error_setg(errp, "property socket-id: %u doesn't match set apic-id:"
2366 " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo.pkg_id);
2367 return;
2368 }
2369 cpu->socket_id = topo.pkg_id;
2370
2371 if (cpu->core_id != -1 && cpu->core_id != topo.core_id) {
2372 error_setg(errp, "property core-id: %u doesn't match set apic-id:"
2373 " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo.core_id);
2374 return;
2375 }
2376 cpu->core_id = topo.core_id;
2377
2378 if (cpu->thread_id != -1 && cpu->thread_id != topo.smt_id) {
2379 error_setg(errp, "property thread-id: %u doesn't match set apic-id:"
2380 " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, topo.smt_id);
2381 return;
2382 }
2383 cpu->thread_id = topo.smt_id;
a15d2728 2384
e9688fab
RK		 2385 if (cpu->hyperv_vpindex && !kvm_hv_vpindex_settable()) {
2386 error_setg(errp, "kernel doesn't allow setting HyperV VP_INDEX");
2387 return;
2388 }
2389
a15d2728
IM		 2390 cs = CPU(cpu);
2391 cs->cpu_index = idx;
93b2a8cb 2392
a0ceb640 2393 numa_cpu_pre_plug(cpu_slot, dev, errp);
4ec60c76
IM		 2394}
2395
2396static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
2397 DeviceState *dev, Error **errp)
2398{
d468115b
DH		 2399 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2400 pc_memory_pre_plug(hotplug_dev, dev, errp);
2401 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
4ec60c76
IM		 2402 pc_cpu_pre_plug(hotplug_dev, dev, errp);
2403 }
2404}
2405
95bee274
IM		 2406static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev,
2407 DeviceState *dev, Error **errp)
2408{
2409 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
bb6e2f7a 2410 pc_memory_plug(hotplug_dev, dev, errp);
5279569e
GZ		 2411 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2412 pc_cpu_plug(hotplug_dev, dev, errp);
95bee274
IM		 2413 }
2414}
2415
d9c5c5b8
TC		 2416static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
2417 DeviceState *dev, Error **errp)
2418{
64fec58e 2419 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
bb6e2f7a 2420 pc_memory_unplug_request(hotplug_dev, dev, errp);
8872c25a
IM		 2421 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2422 pc_cpu_unplug_request_cb(hotplug_dev, dev, errp);
64fec58e
TC		 2423 } else {
2424 error_setg(errp, "acpi: device unplug request for not supported device"
2425 " type: %s", object_get_typename(OBJECT(dev)));
2426 }
d9c5c5b8
TC		 2427}
2428
232391c1
TC		 2429static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
2430 DeviceState *dev, Error **errp)
2431{
f7d3e29d 2432 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
bb6e2f7a 2433 pc_memory_unplug(hotplug_dev, dev, errp);
8872c25a
IM		 2434 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2435 pc_cpu_unplug_cb(hotplug_dev, dev, errp);
f7d3e29d
TC		 2436 } else {
2437 error_setg(errp, "acpi: device unplug for not supported device"
2438 " type: %s", object_get_typename(OBJECT(dev)));
2439 }
232391c1
TC		 2440}
2441
285816d7 2442static HotplugHandler *pc_get_hotplug_handler(MachineState *machine,
95bee274
IM		 2443 DeviceState *dev)
2444{
5279569e
GZ		 2445 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
2446 object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
95bee274
IM		 2447 return HOTPLUG_HANDLER(machine);
2448 }
2449
38aefb57 2450 return NULL;
95bee274
IM		 2451}
2452
bf1e8939 2453static void
f2ffbe2b
DH		 2454pc_machine_get_device_memory_region_size(Object *obj, Visitor *v,
2455 const char *name, void *opaque,
2456 Error **errp)
bf1e8939 2457{
b0c14ec4
DH		 2458 MachineState *ms = MACHINE(obj);
2459 int64_t value = memory_region_size(&ms->device_memory->mr);
bf1e8939 2460
51e72bc1 2461 visit_type_int(v, name, &value, errp);
bf1e8939
IM		 2462}
2463
c87b1520 2464static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v,
d7bce999
EB		 2465 const char *name, void *opaque,
2466 Error **errp)
c87b1520
DS		 2467{
2468 PCMachineState *pcms = PC_MACHINE(obj);
2469 uint64_t value = pcms->max_ram_below_4g;
2470
51e72bc1 2471 visit_type_size(v, name, &value, errp);
c87b1520
DS		 2472}
2473
2474static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v,
d7bce999
EB		 2475 const char *name, void *opaque,
2476 Error **errp)
c87b1520
DS		 2477{
2478 PCMachineState *pcms = PC_MACHINE(obj);
2479 Error *error = NULL;
2480 uint64_t value;
2481
51e72bc1 2482 visit_type_size(v, name, &value, &error);
c87b1520
DS		 2483 if (error) {
2484 error_propagate(errp, error);
2485 return;
2486 }
d471bf3e 2487 if (value > 4 * GiB) {
455b0fde
EB		 2488 error_setg(&error,
2489 "Machine option 'max-ram-below-4g=%"PRIu64
2490 "' expects size less than or equal to 4G", value);
c87b1520
DS		 2491 error_propagate(errp, error);
2492 return;
2493 }
2494
d471bf3e 2495 if (value < 1 * MiB) {
9e5d2c52
AF		 2496 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary,"
2497 "BIOS may not work with less than 1MiB", value);
c87b1520
DS		 2498 }
2499
2500 pcms->max_ram_below_4g = value;
2501}
2502
d7bce999
EB		 2503static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name,
2504 void *opaque, Error **errp)
9b23cfb7
DDAG		 2505{
2506 PCMachineState *pcms = PC_MACHINE(obj);
d1048bef 2507 OnOffAuto vmport = pcms->vmport;
9b23cfb7 2508
51e72bc1 2509 visit_type_OnOffAuto(v, name, &vmport, errp);
9b23cfb7
DDAG		 2510}
2511
d7bce999
EB		 2512static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name,
2513 void *opaque, Error **errp)
9b23cfb7
DDAG		 2514{
2515 PCMachineState *pcms = PC_MACHINE(obj);
2516
51e72bc1 2517 visit_type_OnOffAuto(v, name, &pcms->vmport, errp);
9b23cfb7
DDAG		 2518}
2519
355023f2
PB		 2520bool pc_machine_is_smm_enabled(PCMachineState *pcms)
2521{
2522 bool smm_available = false;
2523
2524 if (pcms->smm == ON_OFF_AUTO_OFF) {
2525 return false;
2526 }
2527
2528 if (tcg_enabled() || qtest_enabled()) {
2529 smm_available = true;
2530 } else if (kvm_enabled()) {
2531 smm_available = kvm_has_smm();
2532 }
2533
2534 if (smm_available) {
2535 return true;
2536 }
2537
2538 if (pcms->smm == ON_OFF_AUTO_ON) {
2539 error_report("System Management Mode not supported by this hypervisor.");
2540 exit(1);
2541 }
2542 return false;
2543}
2544
d7bce999
EB		 2545static void pc_machine_get_smm(Object *obj, Visitor *v, const char *name,
2546 void *opaque, Error **errp)
355023f2
PB		 2547{
2548 PCMachineState *pcms = PC_MACHINE(obj);
2549 OnOffAuto smm = pcms->smm;
2550
51e72bc1 2551 visit_type_OnOffAuto(v, name, &smm, errp);
355023f2
PB		 2552}
2553
d7bce999
EB		 2554static void pc_machine_set_smm(Object *obj, Visitor *v, const char *name,
2555 void *opaque, Error **errp)
355023f2
PB		 2556{
2557 PCMachineState *pcms = PC_MACHINE(obj);
2558
51e72bc1 2559 visit_type_OnOffAuto(v, name, &pcms->smm, errp);
355023f2
PB		 2560}
2561
be232eb0
CP		 2562static bool pc_machine_get_smbus(Object *obj, Error **errp)
2563{
2564 PCMachineState *pcms = PC_MACHINE(obj);
2565
f5878b03 2566 return pcms->smbus_enabled;
be232eb0
CP		 2567}
2568
2569static void pc_machine_set_smbus(Object *obj, bool value, Error **errp)
2570{
2571 PCMachineState *pcms = PC_MACHINE(obj);
2572
f5878b03 2573 pcms->smbus_enabled = value;
be232eb0
CP		 2574}
2575
272f0428
CP		 2576static bool pc_machine_get_sata(Object *obj, Error **errp)
2577{
2578 PCMachineState *pcms = PC_MACHINE(obj);
2579
f5878b03 2580 return pcms->sata_enabled;
272f0428
CP		 2581}
2582
2583static void pc_machine_set_sata(Object *obj, bool value, Error **errp)
2584{
2585 PCMachineState *pcms = PC_MACHINE(obj);
2586
f5878b03 2587 pcms->sata_enabled = value;
272f0428
CP		 2588}
2589
feddd2fd
CP		 2590static bool pc_machine_get_pit(Object *obj, Error **errp)
2591{
2592 PCMachineState *pcms = PC_MACHINE(obj);
2593
f5878b03 2594 return pcms->pit_enabled;
feddd2fd
CP		 2595}
2596
2597static void pc_machine_set_pit(Object *obj, bool value, Error **errp)
2598{
2599 PCMachineState *pcms = PC_MACHINE(obj);
2600
f5878b03 2601 pcms->pit_enabled = value;
feddd2fd
CP		 2602}
2603
bf1e8939
IM		 2604static void pc_machine_initfn(Object *obj)
2605{
c87b1520
DS		 2606 PCMachineState *pcms = PC_MACHINE(obj);
2607
5ec7d098 2608 pcms->max_ram_below_4g = 0; /* use default */
355023f2 2609 pcms->smm = ON_OFF_AUTO_AUTO;
d1048bef 2610 pcms->vmport = ON_OFF_AUTO_AUTO;
021746c1
WL		 2611 /* acpi build is enabled by default if machine supports it */
2612 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build;
f5878b03
CM		 2613 pcms->smbus_enabled = true;
2614 pcms->sata_enabled = true;
2615 pcms->pit_enabled = true;
ebc29e1b
MA		 2616
2617 pc_system_flash_create(pcms);
bf1e8939
IM		 2618}
2619
ae50c55a
ZG		 2620static void pc_machine_reset(void)
2621{
2622 CPUState *cs;
2623 X86CPU *cpu;
2624
2625 qemu_devices_reset();
2626
2627 /* Reset APIC after devices have been reset to cancel
2628 * any changes that qemu_devices_reset() might have done.
2629 */
2630 CPU_FOREACH(cs) {
2631 cpu = X86_CPU(cs);
2632
2633 if (cpu->apic_state) {
2634 device_reset(cpu->apic_state);
2635 }
2636 }
2637}
2638
ea089eeb
IM		 2639static CpuInstanceProperties
2640pc_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
fb43b73b 2641{
ea089eeb
IM		 2642 MachineClass *mc = MACHINE_GET_CLASS(ms);
2643 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
2644
2645 assert(cpu_index < possible_cpus->len);
2646 return possible_cpus->cpus[cpu_index].props;
fb43b73b
IM		 2647}
2648
79e07936
IM		 2649static int64_t pc_get_default_cpu_node_id(const MachineState *ms, int idx)
2650{
2651 X86CPUTopoInfo topo;
2652
2653 assert(idx < ms->possible_cpus->len);
2654 x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id,
2655 smp_cores, smp_threads, &topo);
2656 return topo.pkg_id % nb_numa_nodes;
2657}
2658
c96a1c0b 2659static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms)
3811ef14 2660{
c96a1c0b
IM		 2661 int i;
2662
2663 if (ms->possible_cpus) {
2664 /*
2665 * make sure that max_cpus hasn't changed since the first use, i.e.
2666 * -smp hasn't been parsed after it
2667 */
2668 assert(ms->possible_cpus->len == max_cpus);
2669 return ms->possible_cpus;
2670 }
2671
2672 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
2673 sizeof(CPUArchId) * max_cpus);
2674 ms->possible_cpus->len = max_cpus;
2675 for (i = 0; i < ms->possible_cpus->len; i++) {
c67ae933
IM		 2676 X86CPUTopoInfo topo;
2677
d342eb76 2678 ms->possible_cpus->cpus[i].type = ms->cpu_type;
f2d672c2 2679 ms->possible_cpus->cpus[i].vcpus_count = 1;
c96a1c0b 2680 ms->possible_cpus->cpus[i].arch_id = x86_cpu_apic_id_from_index(i);
c67ae933
IM		 2681 x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id,
2682 smp_cores, smp_threads, &topo);
2683 ms->possible_cpus->cpus[i].props.has_socket_id = true;
2684 ms->possible_cpus->cpus[i].props.socket_id = topo.pkg_id;
2685 ms->possible_cpus->cpus[i].props.has_core_id = true;
2686 ms->possible_cpus->cpus[i].props.core_id = topo.core_id;
2687 ms->possible_cpus->cpus[i].props.has_thread_id = true;
2688 ms->possible_cpus->cpus[i].props.thread_id = topo.smt_id;
c96a1c0b
IM		 2689 }
2690 return ms->possible_cpus;
3811ef14
IM		 2691}
2692
1255166b
BD		 2693static void x86_nmi(NMIState *n, int cpu_index, Error **errp)
2694{
2695 /* cpu index isn't used */
2696 CPUState *cs;
2697
2698 CPU_FOREACH(cs) {
2699 X86CPU *cpu = X86_CPU(cs);
2700
2701 if (!cpu->apic_state) {
2702 cpu_interrupt(cs, CPU_INTERRUPT_NMI);
2703 } else {
2704 apic_deliver_nmi(cpu->apic_state);
2705 }
2706 }
2707}
2708
95bee274
IM		 2709static void pc_machine_class_init(ObjectClass *oc, void *data)
2710{
2711 MachineClass *mc = MACHINE_CLASS(oc);
2712 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc);
2713 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
1255166b 2714 NMIClass *nc = NMI_CLASS(oc);
95bee274 2715
7102fa70
EH		 2716 pcmc->pci_enabled = true;
2717 pcmc->has_acpi_build = true;
2718 pcmc->rsdp_in_ram = true;
2719 pcmc->smbios_defaults = true;
2720 pcmc->smbios_uuid_encoded = true;
2721 pcmc->gigabyte_align = true;
2722 pcmc->has_reserved_memory = true;
2723 pcmc->kvmclock_enabled = true;
16a9e8a5 2724 pcmc->enforce_aligned_dimm = true;
cd4040ec
EH		 2725 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported
2726 * to be used at the moment, 32K should be enough for a while. */
2727 pcmc->acpi_data_size = 0x20000 + 0x8000;
36f96c4b 2728 pcmc->save_tsc_khz = true;
98e753a6 2729 pcmc->linuxboot_dma_enabled = true;
fda672b5 2730 pcmc->pvh_enabled = true;
debbdc00 2731 assert(!mc->get_hotplug_handler);
285816d7 2732 mc->get_hotplug_handler = pc_get_hotplug_handler;
ea089eeb 2733 mc->cpu_index_to_instance_props = pc_cpu_index_to_props;
79e07936 2734 mc->get_default_cpu_node_id = pc_get_default_cpu_node_id;
3811ef14 2735 mc->possible_cpu_arch_ids = pc_possible_cpu_arch_ids;
7b8be49d 2736 mc->auto_enable_numa_with_memhp = true;
c5514d0e 2737 mc->has_hotpluggable_cpus = true;
41742767 2738 mc->default_boot_order = "cad";
4458fb3a 2739 mc->hot_add_cpu = pc_hot_add_cpu;
2059839b 2740 mc->block_default_type = IF_IDE;
4458fb3a 2741 mc->max_cpus = 255;
ae50c55a 2742 mc->reset = pc_machine_reset;
4ec60c76 2743 hc->pre_plug = pc_machine_device_pre_plug_cb;
95bee274 2744 hc->plug = pc_machine_device_plug_cb;
d9c5c5b8 2745 hc->unplug_request = pc_machine_device_unplug_request_cb;
232391c1 2746 hc->unplug = pc_machine_device_unplug_cb;
1255166b 2747 nc->nmi_monitor_handler = x86_nmi;
311ca98d 2748 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
f6a0d06b 2749 mc->nvdimm_supported = true;
0efc257d 2750
f2ffbe2b
DH		 2751 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int",
2752 pc_machine_get_device_memory_region_size, NULL,
0efc257d
EH		 2753 NULL, NULL, &error_abort);
2754
2755 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size",
2756 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g,
2757 NULL, NULL, &error_abort);
2758
2759 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G,
2760 "Maximum ram below the 4G boundary (32bit boundary)", &error_abort);
2761
2762 object_class_property_add(oc, PC_MACHINE_SMM, "OnOffAuto",
2763 pc_machine_get_smm, pc_machine_set_smm,
2764 NULL, NULL, &error_abort);
2765 object_class_property_set_description(oc, PC_MACHINE_SMM,
2766 "Enable SMM (pc & q35)", &error_abort);
2767
2768 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto",
2769 pc_machine_get_vmport, pc_machine_set_vmport,
2770 NULL, NULL, &error_abort);
2771 object_class_property_set_description(oc, PC_MACHINE_VMPORT,
2772 "Enable vmport (pc & q35)", &error_abort);
2773
be232eb0
CP		 2774 object_class_property_add_bool(oc, PC_MACHINE_SMBUS,
2775 pc_machine_get_smbus, pc_machine_set_smbus, &error_abort);
272f0428
CP		 2776
2777 object_class_property_add_bool(oc, PC_MACHINE_SATA,
2778 pc_machine_get_sata, pc_machine_set_sata, &error_abort);
feddd2fd
CP		 2779
2780 object_class_property_add_bool(oc, PC_MACHINE_PIT,
2781 pc_machine_get_pit, pc_machine_set_pit, &error_abort);
95bee274
IM		 2782}
2783
d5747cac
IM		 2784static const TypeInfo pc_machine_info = {
2785 .name = TYPE_PC_MACHINE,
2786 .parent = TYPE_MACHINE,
2787 .abstract = true,
2788 .instance_size = sizeof(PCMachineState),
bf1e8939 2789 .instance_init = pc_machine_initfn,
d5747cac 2790 .class_size = sizeof(PCMachineClass),
95bee274
IM		 2791 .class_init = pc_machine_class_init,
2792 .interfaces = (InterfaceInfo[]) {
2793 { TYPE_HOTPLUG_HANDLER },
1255166b 2794 { TYPE_NMI },
95bee274
IM		 2795 { }
2796 },
d5747cac
IM		 2797};
2798
2799static void pc_machine_register_types(void)
2800{
2801 type_register_static(&pc_machine_info);
2802}
2803
2804type_init(pc_machine_register_types)
Empty description
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