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compat: replace PC_COMPAT_2_2 & HW_COMPAT_2_2 macros
[qemu.git] / hw / i386 / pc.c
CommitLineData
80cabfad
FB		 1/*
2 * QEMU PC System Emulator
5fafdf24 3 *
80cabfad 4 * Copyright (c) 2003-2004 Fabrice Bellard
5fafdf24 5 *
80cabfad
FB		 6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
e688df6b 24
b6a0aa05 25#include "qemu/osdep.h"
d471bf3e 26#include "qemu/units.h"
83c9f4ca 27#include "hw/hw.h"
0d09e41a
PB		 28#include "hw/i386/pc.h"
29#include "hw/char/serial.h"
bb3d5ea8 30#include "hw/char/parallel.h"
0d09e41a 31#include "hw/i386/apic.h"
54a40293
EH		 32#include "hw/i386/topology.h"
33#include "sysemu/cpus.h"
0d09e41a 34#include "hw/block/fdc.h"
83c9f4ca
PB		 35#include "hw/ide.h"
36#include "hw/pci/pci.h"
2118196b 37#include "hw/pci/pci_bus.h"
0d09e41a
PB		 38#include "hw/nvram/fw_cfg.h"
39#include "hw/timer/hpet.h"
a2eb5c0c 40#include "hw/firmware/smbios.h"
83c9f4ca 41#include "hw/loader.h"
ca20cf32 42#include "elf.h"
47b43a1f 43#include "multiboot.h"
0d09e41a 44#include "hw/timer/mc146818rtc.h"
55f613ac 45#include "hw/dma/i8257.h"
0d09e41a 46#include "hw/timer/i8254.h"
47973a2d 47#include "hw/input/i8042.h"
0d09e41a 48#include "hw/audio/pcspk.h"
83c9f4ca
PB		 49#include "hw/pci/msi.h"
50#include "hw/sysbus.h"
9c17d615 51#include "sysemu/sysemu.h"
e35704ba 52#include "sysemu/numa.h"
9c17d615 53#include "sysemu/kvm.h"
b1c12027 54#include "sysemu/qtest.h"
1d31f66b 55#include "kvm_i386.h"
0d09e41a 56#include "hw/xen/xen.h"
a19cbfb3 57#include "ui/qemu-spice.h"
022c62cb
PB		 58#include "exec/memory.h"
59#include "exec/address-spaces.h"
9c17d615 60#include "sysemu/arch_init.h"
1de7afc9 61#include "qemu/bitmap.h"
0c764a9d 62#include "qemu/config-file.h"
d49b6836 63#include "qemu/error-report.h"
922a01a0 64#include "qemu/option.h"
0445259b 65#include "hw/acpi/acpi.h"
5ff020b7 66#include "hw/acpi/cpu_hotplug.h"
c649983b 67#include "hw/boards.h"
72c194f7 68#include "acpi-build.h"
95bee274 69#include "hw/mem/pc-dimm.h"
e688df6b 70#include "qapi/error.h"
9af23989 71#include "qapi/qapi-visit-common.h"
bf1e8939 72#include "qapi/visitor.h"
15eafc2e 73#include "qom/cpu.h"
1255166b 74#include "hw/nmi.h"
60c5e104 75#include "hw/i386/intel_iommu.h"
489983d6 76#include "hw/net/ne2000-isa.h"
80cabfad 77
471fd342
BS		 78/* debug PC/ISA interrupts */
79//#define DEBUG_IRQ
80
81#ifdef DEBUG_IRQ
82#define DPRINTF(fmt, ...) \
83 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
84#else
85#define DPRINTF(fmt, ...)
86#endif
87
8a92ea2f 88#define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
b6f6e3d3 89#define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
6b35e7bf 90#define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
4c5b10b7 91#define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
40ac17cd 92#define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
80cabfad 93
4c5b10b7
JS		 94#define E820_NR_ENTRIES 16
95
96struct e820_entry {
97 uint64_t address;
98 uint64_t length;
99 uint32_t type;
541dc0d4 100} QEMU_PACKED __attribute((__aligned__(4)));
4c5b10b7
JS		 101
102struct e820_table {
103 uint32_t count;
104 struct e820_entry entry[E820_NR_ENTRIES];
541dc0d4 105} QEMU_PACKED __attribute((__aligned__(4)));
4c5b10b7 106
7d67110f
GH		 107static struct e820_table e820_reserve;
108static struct e820_entry *e820_table;
109static unsigned e820_entries;
dd703b99 110struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
4c5b10b7 111
abd93cc7
MAL		 112GlobalProperty pc_compat_3_1[] = {
113 {
114 .driver = "intel-iommu",
115 .property = "dma-drain",
116 .value = "off",
117 },
118};
119const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1);
120
ddb3235d
MAL		 121GlobalProperty pc_compat_3_0[] = {
122 {
123 .driver = TYPE_X86_CPU,
124 .property = "x-hv-synic-kvm-only",
125 .value = "on",
126 },{
127 .driver = "Skylake-Server" "-" TYPE_X86_CPU,
128 .property = "pku",
129 .value = "off",
130 },{
131 .driver = "Skylake-Server-IBRS" "-" TYPE_X86_CPU,
132 .property = "pku",
133 .value = "off",
134 },
135};
136const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0);
137
0d47310b
MAL		 138GlobalProperty pc_compat_2_12[] = {
139 {
140 .driver = TYPE_X86_CPU,
141 .property = "legacy-cache",
142 .value = "on",
143 },{
144 .driver = TYPE_X86_CPU,
145 .property = "topoext",
146 .value = "off",
147 },{
148 .driver = "EPYC-" TYPE_X86_CPU,
149 .property = "xlevel",
150 .value = stringify(0x8000000a),
151 },{
152 .driver = "EPYC-IBPB-" TYPE_X86_CPU,
153 .property = "xlevel",
154 .value = stringify(0x8000000a),
155 },
156};
157const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12);
158
43df70a9
MAL		 159GlobalProperty pc_compat_2_11[] = {
160 {
161 .driver = TYPE_X86_CPU,
162 .property = "x-migrate-smi-count",
163 .value = "off",
164 },{
165 .driver = "Skylake-Server" "-" TYPE_X86_CPU,
166 .property = "clflushopt",
167 .value = "off",
168 },
169};
170const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11);
171
503224f4
MAL		 172GlobalProperty pc_compat_2_10[] = {
173 {
174 .driver = TYPE_X86_CPU,
175 .property = "x-hv-max-vps",
176 .value = "0x40",
177 },{
178 .driver = "i440FX-pcihost",
179 .property = "x-pci-hole64-fix",
180 .value = "off",
181 },{
182 .driver = "q35-pcihost",
183 .property = "x-pci-hole64-fix",
184 .value = "off",
185 },
186};
187const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10);
188
3e803152
MAL		 189GlobalProperty pc_compat_2_9[] = {
190 {
191 .driver = "mch",
192 .property = "extended-tseg-mbytes",
193 .value = stringify(0),
194 },
195};
196const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9);
197
edc24ccd
MAL		 198GlobalProperty pc_compat_2_8[] = {
199 {
200 .driver = TYPE_X86_CPU,
201 .property = "tcg-cpuid",
202 .value = "off",
203 },
204 {
205 .driver = "kvmclock",
206 .property = "x-mach-use-reliable-get-clock",
207 .value = "off",
208 },
209 {
210 .driver = "ICH9-LPC",
211 .property = "x-smi-broadcast",
212 .value = "off",
213 },
214 {
215 .driver = TYPE_X86_CPU,
216 .property = "vmware-cpuid-freq",
217 .value = "off",
218 },
219 {
220 .driver = "Haswell-" TYPE_X86_CPU,
221 .property = "stepping",
222 .value = "1",
223 },
224};
225const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8);
226
5a995064
MAL		 227GlobalProperty pc_compat_2_7[] = {
228 {
229 .driver = TYPE_X86_CPU,
230 .property = "l3-cache",
231 .value = "off",
232 },
233 {
234 .driver = TYPE_X86_CPU,
235 .property = "full-cpuid-auto-level",
236 .value = "off",
237 },
238 {
239 .driver = "Opteron_G3" "-" TYPE_X86_CPU,
240 .property = "family",
241 .value = "15",
242 },
243 {
244 .driver = "Opteron_G3" "-" TYPE_X86_CPU,
245 .property = "model",
246 .value = "6",
247 },
248 {
249 .driver = "Opteron_G3" "-" TYPE_X86_CPU,
250 .property = "stepping",
251 .value = "1",
252 },
253 {
254 .driver = "isa-pcspk",
255 .property = "migrate",
256 .value = "off",
257 },
258};
259const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7);
260
ff8f261f
MAL		 261GlobalProperty pc_compat_2_6[] = {
262 {
263 .driver = TYPE_X86_CPU,
264 .property = "cpuid-0xb",
265 .value = "off",
266 },{
267 .driver = "vmxnet3",
268 .property = "romfile",
269 .value = "",
270 },
271 {
272 .driver = TYPE_X86_CPU,
273 .property = "fill-mtrr-mask",
274 .value = "off",
275 },
276 {
277 .driver = "apic-common",
278 .property = "legacy-instance-id",
279 .value = "on",
280 }
281};
282const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6);
283
fe759610
MAL		 284GlobalProperty pc_compat_2_5[] = {};
285const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5);
286
2f99b9c2
MAL		 287GlobalProperty pc_compat_2_4[] = {
288 PC_CPU_MODEL_IDS("2.4.0")
289 {
290 .driver = "Haswell-" TYPE_X86_CPU,
291 .property = "abm",
292 .value = "off",
293 },
294 {
295 .driver = "Haswell-noTSX-" TYPE_X86_CPU,
296 .property = "abm",
297 .value = "off",
298 },
299 {
300 .driver = "Broadwell-" TYPE_X86_CPU,
301 .property = "abm",
302 .value = "off",
303 },
304 {
305 .driver = "Broadwell-noTSX-" TYPE_X86_CPU,
306 .property = "abm",
307 .value = "off",
308 },
309 {
310 .driver = "host" "-" TYPE_X86_CPU,
311 .property = "host-cache-info",
312 .value = "on",
313 },
314 {
315 .driver = TYPE_X86_CPU,
316 .property = "check",
317 .value = "off",
318 },
319 {
320 .driver = "qemu64" "-" TYPE_X86_CPU,
321 .property = "sse4a",
322 .value = "on",
323 },
324 {
325 .driver = "qemu64" "-" TYPE_X86_CPU,
326 .property = "abm",
327 .value = "on",
328 },
329 {
330 .driver = "qemu64" "-" TYPE_X86_CPU,
331 .property = "popcnt",
332 .value = "on",
333 },
334 {
335 .driver = "qemu32" "-" TYPE_X86_CPU,
336 .property = "popcnt",
337 .value = "on",
338 },{
339 .driver = "Opteron_G2" "-" TYPE_X86_CPU,
340 .property = "rdtscp",
341 .value = "on",
342 },{
343 .driver = "Opteron_G3" "-" TYPE_X86_CPU,
344 .property = "rdtscp",
345 .value = "on",
346 },{
347 .driver = "Opteron_G4" "-" TYPE_X86_CPU,
348 .property = "rdtscp",
349 .value = "on",
350 },{
351 .driver = "Opteron_G5" "-" TYPE_X86_CPU,
352 .property = "rdtscp",
353 .value = "on",
354 }
355};
356const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4);
357
8995dd90
MAL		 358GlobalProperty pc_compat_2_3[] = {
359 PC_CPU_MODEL_IDS("2.3.0")
360 {
361 .driver = TYPE_X86_CPU,
362 .property = "arat",
363 .value = "off",
364 },{
365 .driver = "qemu64" "-" TYPE_X86_CPU,
366 .property = "min-level",
367 .value = stringify(4),
368 },{
369 .driver = "kvm64" "-" TYPE_X86_CPU,
370 .property = "min-level",
371 .value = stringify(5),
372 },{
373 .driver = "pentium3" "-" TYPE_X86_CPU,
374 .property = "min-level",
375 .value = stringify(2),
376 },{
377 .driver = "n270" "-" TYPE_X86_CPU,
378 .property = "min-level",
379 .value = stringify(5),
380 },{
381 .driver = "Conroe" "-" TYPE_X86_CPU,
382 .property = "min-level",
383 .value = stringify(4),
384 },{
385 .driver = "Penryn" "-" TYPE_X86_CPU,
386 .property = "min-level",
387 .value = stringify(4),
388 },{
389 .driver = "Nehalem" "-" TYPE_X86_CPU,
390 .property = "min-level",
391 .value = stringify(4),
392 },{
393 .driver = "n270" "-" TYPE_X86_CPU,
394 .property = "min-xlevel",
395 .value = stringify(0x8000000a),
396 },{
397 .driver = "Penryn" "-" TYPE_X86_CPU,
398 .property = "min-xlevel",
399 .value = stringify(0x8000000a),
400 },{
401 .driver = "Conroe" "-" TYPE_X86_CPU,
402 .property = "min-xlevel",
403 .value = stringify(0x8000000a),
404 },{
405 .driver = "Nehalem" "-" TYPE_X86_CPU,
406 .property = "min-xlevel",
407 .value = stringify(0x8000000a),
408 },{
409 .driver = "Westmere" "-" TYPE_X86_CPU,
410 .property = "min-xlevel",
411 .value = stringify(0x8000000a),
412 },{
413 .driver = "SandyBridge" "-" TYPE_X86_CPU,
414 .property = "min-xlevel",
415 .value = stringify(0x8000000a),
416 },{
417 .driver = "IvyBridge" "-" TYPE_X86_CPU,
418 .property = "min-xlevel",
419 .value = stringify(0x8000000a),
420 },{
421 .driver = "Haswell" "-" TYPE_X86_CPU,
422 .property = "min-xlevel",
423 .value = stringify(0x8000000a),
424 },{
425 .driver = "Haswell-noTSX" "-" TYPE_X86_CPU,
426 .property = "min-xlevel",
427 .value = stringify(0x8000000a),
428 },{
429 .driver = "Broadwell" "-" TYPE_X86_CPU,
430 .property = "min-xlevel",
431 .value = stringify(0x8000000a),
432 },{
433 .driver = "Broadwell-noTSX" "-" TYPE_X86_CPU,
434 .property = "min-xlevel",
435 .value = stringify(0x8000000a),
436 },{
437 .driver = TYPE_X86_CPU,
438 .property = "kvm-no-smi-migration",
439 .value = "on",
440 },
441};
442const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3);
443
1c30044e
MAL		 444GlobalProperty pc_compat_2_2[] = {
445 PC_CPU_MODEL_IDS("2.2.0")
446 {
447 .driver = "kvm64" "-" TYPE_X86_CPU,
448 .property = "vme",
449 .value = "off",
450 },
451 {
452 .driver = "kvm32" "-" TYPE_X86_CPU,
453 .property = "vme",
454 .value = "off",
455 },
456 {
457 .driver = "Conroe" "-" TYPE_X86_CPU,
458 .property = "vme",
459 .value = "off",
460 },
461 {
462 .driver = "Penryn" "-" TYPE_X86_CPU,
463 .property = "vme",
464 .value = "off",
465 },
466 {
467 .driver = "Nehalem" "-" TYPE_X86_CPU,
468 .property = "vme",
469 .value = "off",
470 },
471 {
472 .driver = "Westmere" "-" TYPE_X86_CPU,
473 .property = "vme",
474 .value = "off",
475 },
476 {
477 .driver = "SandyBridge" "-" TYPE_X86_CPU,
478 .property = "vme",
479 .value = "off",
480 },
481 {
482 .driver = "Haswell" "-" TYPE_X86_CPU,
483 .property = "vme",
484 .value = "off",
485 },
486 {
487 .driver = "Broadwell" "-" TYPE_X86_CPU,
488 .property = "vme",
489 .value = "off",
490 },
491 {
492 .driver = "Opteron_G1" "-" TYPE_X86_CPU,
493 .property = "vme",
494 .value = "off",
495 },
496 {
497 .driver = "Opteron_G2" "-" TYPE_X86_CPU,
498 .property = "vme",
499 .value = "off",
500 },
501 {
502 .driver = "Opteron_G3" "-" TYPE_X86_CPU,
503 .property = "vme",
504 .value = "off",
505 },
506 {
507 .driver = "Opteron_G4" "-" TYPE_X86_CPU,
508 .property = "vme",
509 .value = "off",
510 },
511 {
512 .driver = "Opteron_G5" "-" TYPE_X86_CPU,
513 .property = "vme",
514 .value = "off",
515 },
516 {
517 .driver = "Haswell" "-" TYPE_X86_CPU,
518 .property = "f16c",
519 .value = "off",
520 },
521 {
522 .driver = "Haswell" "-" TYPE_X86_CPU,
523 .property = "rdrand",
524 .value = "off",
525 },
526 {
527 .driver = "Broadwell" "-" TYPE_X86_CPU,
528 .property = "f16c",
529 .value = "off",
530 },
531 {
532 .driver = "Broadwell" "-" TYPE_X86_CPU,
533 .property = "rdrand",
534 .value = "off",
535 },
536};
537const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2);
538
b881fbe9 539void gsi_handler(void *opaque, int n, int level)
1452411b 540{
b881fbe9 541 GSIState *s = opaque;
1452411b 542
b881fbe9
JK		 543 DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n);
544 if (n < ISA_NUM_IRQS) {
545 qemu_set_irq(s->i8259_irq[n], level);
1632dc6a 546 }
b881fbe9 547 qemu_set_irq(s->ioapic_irq[n], level);
2e9947d2 548}
1452411b 549
258711c6
JG		 550static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
551 unsigned size)
80cabfad
FB		 552{
553}
554
c02e1eac
JG		 555static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
556{
a6fc23e5 557 return 0xffffffffffffffffULL;
c02e1eac
JG		 558}
559
f929aad6 560/* MSDOS compatibility mode FPU exception support */
d537cf6c 561static qemu_irq ferr_irq;
8e78eb28
IY		 562
563void pc_register_ferr_irq(qemu_irq irq)
564{
565 ferr_irq = irq;
566}
567
f929aad6
FB		 568/* XXX: add IGNNE support */
569void cpu_set_ferr(CPUX86State *s)
570{
d537cf6c 571 qemu_irq_raise(ferr_irq);
f929aad6
FB		 572}
573
258711c6
JG		 574static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
575 unsigned size)
f929aad6 576{
d537cf6c 577 qemu_irq_lower(ferr_irq);
f929aad6
FB		 578}
579
c02e1eac
JG		 580static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
581{
a6fc23e5 582 return 0xffffffffffffffffULL;
c02e1eac
JG		 583}
584
28ab0e2e 585/* TSC handling */
28ab0e2e
FB		 586uint64_t cpu_get_tsc(CPUX86State *env)
587{
4a1418e0 588 return cpu_get_ticks();
28ab0e2e
FB		 589}
590
3de388f6 591/* IRQ handling */
4a8fa5dc 592int cpu_get_pic_interrupt(CPUX86State *env)
3de388f6 593{
02e51483 594 X86CPU *cpu = x86_env_get_cpu(env);
3de388f6
FB		 595 int intno;
596
bb93e099
WL		 597 if (!kvm_irqchip_in_kernel()) {
598 intno = apic_get_interrupt(cpu->apic_state);
599 if (intno >= 0) {
600 return intno;
601 }
602 /* read the irq from the PIC */
603 if (!apic_accept_pic_intr(cpu->apic_state)) {
604 return -1;
605 }
cf6d64bf 606 }
0e21e12b 607
3de388f6
FB		 608 intno = pic_read_irq(isa_pic);
609 return intno;
610}
611
d537cf6c 612static void pic_irq_request(void *opaque, int irq, int level)
3de388f6 613{
182735ef
AF		 614 CPUState *cs = first_cpu;
615 X86CPU *cpu = X86_CPU(cs);
a5b38b51 616
471fd342 617 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
bb93e099 618 if (cpu->apic_state && !kvm_irqchip_in_kernel()) {
bdc44640 619 CPU_FOREACH(cs) {
182735ef 620 cpu = X86_CPU(cs);
02e51483
CF		 621 if (apic_accept_pic_intr(cpu->apic_state)) {
622 apic_deliver_pic_intr(cpu->apic_state, level);
cf6d64bf 623 }
d5529471
AJ		 624 }
625 } else {
d8ed887b 626 if (level) {
c3affe56 627 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
d8ed887b
AF		 628 } else {
629 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
630 }
a5b38b51 631 }
3de388f6
FB		 632}
633
b0a21b53
FB		 634/* PC cmos mappings */
635
80cabfad
FB		 636#define REG_EQUIPMENT_BYTE 0x14
637
bda05509 638int cmos_get_fd_drive_type(FloppyDriveType fd0)
777428f2
FB		 639{
640 int val;
641
642 switch (fd0) {
2da44dd0 643 case FLOPPY_DRIVE_TYPE_144:
777428f2
FB		 644 /* 1.44 Mb 3"5 drive */
645 val = 4;
646 break;
2da44dd0 647 case FLOPPY_DRIVE_TYPE_288:
777428f2
FB		 648 /* 2.88 Mb 3"5 drive */
649 val = 5;
650 break;
2da44dd0 651 case FLOPPY_DRIVE_TYPE_120:
777428f2
FB		 652 /* 1.2 Mb 5"5 drive */
653 val = 2;
654 break;
2da44dd0 655 case FLOPPY_DRIVE_TYPE_NONE:
777428f2
FB		 656 default:
657 val = 0;
658 break;
659 }
660 return val;
661}
662
9139046c
MA		 663static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
664 int16_t cylinders, int8_t heads, int8_t sectors)
ba6c2377 665{
ba6c2377
FB		 666 rtc_set_memory(s, type_ofs, 47);
667 rtc_set_memory(s, info_ofs, cylinders);
668 rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
669 rtc_set_memory(s, info_ofs + 2, heads);
670 rtc_set_memory(s, info_ofs + 3, 0xff);
671 rtc_set_memory(s, info_ofs + 4, 0xff);
672 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
673 rtc_set_memory(s, info_ofs + 6, cylinders);
674 rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
675 rtc_set_memory(s, info_ofs + 8, sectors);
676}
677
6ac0e82d
AZ		 678/* convert boot_device letter to something recognizable by the bios */
679static int boot_device2nibble(char boot_device)
680{
681 switch(boot_device) {
682 case 'a':
683 case 'b':
684 return 0x01; /* floppy boot */
685 case 'c':
686 return 0x02; /* hard drive boot */
687 case 'd':
688 return 0x03; /* CD-ROM boot */
689 case 'n':
690 return 0x04; /* Network boot */
691 }
692 return 0;
693}
694
ddcd5531 695static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp)
0ecdffbb
AJ		 696{
697#define PC_MAX_BOOT_DEVICES 3
0ecdffbb
AJ		 698 int nbds, bds[3] = { 0, };
699 int i;
700
701 nbds = strlen(boot_device);
702 if (nbds > PC_MAX_BOOT_DEVICES) {
ddcd5531
GA		 703 error_setg(errp, "Too many boot devices for PC");
704 return;
0ecdffbb
AJ		 705 }
706 for (i = 0; i < nbds; i++) {
707 bds[i] = boot_device2nibble(boot_device[i]);
708 if (bds[i] == 0) {
ddcd5531
GA		 709 error_setg(errp, "Invalid boot device for PC: '%c'",
710 boot_device[i]);
711 return;
0ecdffbb
AJ		 712 }
713 }
714 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
d9346e81 715 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
0ecdffbb
AJ		 716}
717
ddcd5531 718static void pc_boot_set(void *opaque, const char *boot_device, Error **errp)
d9346e81 719{
ddcd5531 720 set_boot_dev(opaque, boot_device, errp);
d9346e81
MA		 721}
722
7444ca4e
LE		 723static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy)
724{
725 int val, nb, i;
2da44dd0
JS		 726 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE,
727 FLOPPY_DRIVE_TYPE_NONE };
7444ca4e
LE		 728
729 /* floppy type */
730 if (floppy) {
731 for (i = 0; i < 2; i++) {
732 fd_type[i] = isa_fdc_get_drive_type(floppy, i);
733 }
734 }
735 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
736 cmos_get_fd_drive_type(fd_type[1]);
737 rtc_set_memory(rtc_state, 0x10, val);
738
739 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE);
740 nb = 0;
2da44dd0 741 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) {
7444ca4e
LE		 742 nb++;
743 }
2da44dd0 744 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) {
7444ca4e
LE		 745 nb++;
746 }
747 switch (nb) {
748 case 0:
749 break;
750 case 1:
751 val |= 0x01; /* 1 drive, ready for boot */
752 break;
753 case 2:
754 val |= 0x41; /* 2 drives, ready for boot */
755 break;
756 }
757 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val);
758}
759
c0897e0c
MA		 760typedef struct pc_cmos_init_late_arg {
761 ISADevice *rtc_state;
9139046c 762 BusState *idebus[2];
c0897e0c
MA		 763} pc_cmos_init_late_arg;
764
b86f4613
LE		 765typedef struct check_fdc_state {
766 ISADevice *floppy;
767 bool multiple;
768} CheckFdcState;
769
770static int check_fdc(Object *obj, void *opaque)
771{
772 CheckFdcState *state = opaque;
773 Object *fdc;
774 uint32_t iobase;
775 Error *local_err = NULL;
776
777 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC);
778 if (!fdc) {
779 return 0;
780 }
781
1ea1572a 782 iobase = object_property_get_uint(obj, "iobase", &local_err);
b86f4613
LE		 783 if (local_err || iobase != 0x3f0) {
784 error_free(local_err);
785 return 0;
786 }
787
788 if (state->floppy) {
789 state->multiple = true;
790 } else {
791 state->floppy = ISA_DEVICE(obj);
792 }
793 return 0;
794}
795
796static const char * const fdc_container_path[] = {
797 "/unattached", "/peripheral", "/peripheral-anon"
798};
799
424e4a87
RK		 800/*
801 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
802 * and ACPI objects.
803 */
804ISADevice *pc_find_fdc0(void)
805{
806 int i;
807 Object *container;
808 CheckFdcState state = { 0 };
809
810 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) {
811 container = container_get(qdev_get_machine(), fdc_container_path[i]);
812 object_child_foreach(container, check_fdc, &state);
813 }
814
815 if (state.multiple) {
3dc6f869
AF		 816 warn_report("multiple floppy disk controllers with "
817 "iobase=0x3f0 have been found");
433672b0 818 error_printf("the one being picked for CMOS setup might not reflect "
9e5d2c52 819 "your intent");
424e4a87
RK		 820 }
821
822 return state.floppy;
823}
824
c0897e0c
MA		 825static void pc_cmos_init_late(void *opaque)
826{
827 pc_cmos_init_late_arg *arg = opaque;
828 ISADevice *s = arg->rtc_state;
9139046c
MA		 829 int16_t cylinders;
830 int8_t heads, sectors;
c0897e0c 831 int val;
2adc99b2 832 int i, trans;
c0897e0c 833
9139046c 834 val = 0;
272f0428
CP		 835 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0,
836 &cylinders, &heads, &sectors) >= 0) {
9139046c
MA		 837 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
838 val |= 0xf0;
839 }
272f0428
CP		 840 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1,
841 &cylinders, &heads, &sectors) >= 0) {
9139046c
MA		 842 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
843 val |= 0x0f;
844 }
845 rtc_set_memory(s, 0x12, val);
c0897e0c
MA		 846
847 val = 0;
848 for (i = 0; i < 4; i++) {
9139046c
MA		 849 /* NOTE: ide_get_geometry() returns the physical
850 geometry. It is always such that: 1 <= sects <= 63, 1
851 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
852 geometry can be different if a translation is done. */
272f0428
CP		 853 if (arg->idebus[i / 2] &&
854 ide_get_geometry(arg->idebus[i / 2], i % 2,
9139046c 855 &cylinders, &heads, &sectors) >= 0) {
2adc99b2
MA		 856 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
857 assert((trans & ~3) == 0);
858 val |= trans << (i * 2);
c0897e0c
MA		 859 }
860 }
861 rtc_set_memory(s, 0x39, val);
862
424e4a87 863 pc_cmos_init_floppy(s, pc_find_fdc0());
b86f4613 864
c0897e0c
MA		 865 qemu_unregister_reset(pc_cmos_init_late, opaque);
866}
867
23d30407 868void pc_cmos_init(PCMachineState *pcms,
220a8846 869 BusState *idebus0, BusState *idebus1,
63ffb564 870 ISADevice *s)
80cabfad 871{
7444ca4e 872 int val;
c0897e0c 873 static pc_cmos_init_late_arg arg;
b0a21b53 874
b0a21b53 875 /* various important CMOS locations needed by PC/Bochs bios */
80cabfad
FB		 876
877 /* memory size */
e89001f7 878 /* base memory (first MiB) */
d471bf3e 879 val = MIN(pcms->below_4g_mem_size / KiB, 640);
333190eb
FB		 880 rtc_set_memory(s, 0x15, val);
881 rtc_set_memory(s, 0x16, val >> 8);
e89001f7 882 /* extended memory (next 64MiB) */
d471bf3e
PB		 883 if (pcms->below_4g_mem_size > 1 * MiB) {
884 val = (pcms->below_4g_mem_size - 1 * MiB) / KiB;
e89001f7
MA		 885 } else {
886 val = 0;
887 }
80cabfad
FB		 888 if (val > 65535)
889 val = 65535;
b0a21b53
FB		 890 rtc_set_memory(s, 0x17, val);
891 rtc_set_memory(s, 0x18, val >> 8);
892 rtc_set_memory(s, 0x30, val);
893 rtc_set_memory(s, 0x31, val >> 8);
e89001f7 894 /* memory between 16MiB and 4GiB */
d471bf3e
PB		 895 if (pcms->below_4g_mem_size > 16 * MiB) {
896 val = (pcms->below_4g_mem_size - 16 * MiB) / (64 * KiB);
e89001f7 897 } else {
9da98861 898 val = 0;
e89001f7 899 }
80cabfad
FB		 900 if (val > 65535)
901 val = 65535;
b0a21b53
FB		 902 rtc_set_memory(s, 0x34, val);
903 rtc_set_memory(s, 0x35, val >> 8);
e89001f7 904 /* memory above 4GiB */
88076854 905 val = pcms->above_4g_mem_size / 65536;
e89001f7
MA		 906 rtc_set_memory(s, 0x5b, val);
907 rtc_set_memory(s, 0x5c, val >> 8);
908 rtc_set_memory(s, 0x5d, val >> 16);
3b46e624 909
23d30407 910 object_property_add_link(OBJECT(pcms), "rtc_state",
2d996150 911 TYPE_ISA_DEVICE,
ec68007a 912 (Object **)&pcms->rtc,
2d996150 913 object_property_allow_set_link,
265b578c 914 OBJ_PROP_LINK_STRONG, &error_abort);
23d30407 915 object_property_set_link(OBJECT(pcms), OBJECT(s),
2d996150 916 "rtc_state", &error_abort);
298e01b6 917
007b0657 918 set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal);
80cabfad 919
b0a21b53 920 val = 0;
b0a21b53
FB		 921 val |= 0x02; /* FPU is there */
922 val |= 0x04; /* PS/2 mouse installed */
923 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
924
b86f4613 925 /* hard drives and FDC */
c0897e0c 926 arg.rtc_state = s;
9139046c
MA		 927 arg.idebus[0] = idebus0;
928 arg.idebus[1] = idebus1;
c0897e0c 929 qemu_register_reset(pc_cmos_init_late, &arg);
80cabfad
FB		 930}
931
a0881c64
AF		 932#define TYPE_PORT92 "port92"
933#define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92)
934
4b78a802
BS		 935/* port 92 stuff: could be split off */
936typedef struct Port92State {
a0881c64
AF		 937 ISADevice parent_obj;
938
23af670e 939 MemoryRegion io;
4b78a802 940 uint8_t outport;
d812b3d6 941 qemu_irq a20_out;
4b78a802
BS		 942} Port92State;
943
93ef4192
AG		 944static void port92_write(void *opaque, hwaddr addr, uint64_t val,
945 unsigned size)
4b78a802
BS		 946{
947 Port92State *s = opaque;
4700a316 948 int oldval = s->outport;
4b78a802 949
c5539cb4 950 DPRINTF("port92: write 0x%02" PRIx64 "\n", val);
4b78a802 951 s->outport = val;
d812b3d6 952 qemu_set_irq(s->a20_out, (val >> 1) & 1);
4700a316 953 if ((val & 1) && !(oldval & 1)) {
cf83f140 954 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
4b78a802
BS		 955 }
956}
957
93ef4192
AG		 958static uint64_t port92_read(void *opaque, hwaddr addr,
959 unsigned size)
4b78a802
BS		 960{
961 Port92State *s = opaque;
962 uint32_t ret;
963
964 ret = s->outport;
965 DPRINTF("port92: read 0x%02x\n", ret);
966 return ret;
967}
968
d80fe99d 969static void port92_init(ISADevice *dev, qemu_irq a20_out)
4b78a802 970{
d80fe99d 971 qdev_connect_gpio_out_named(DEVICE(dev), PORT92_A20_LINE, 0, a20_out);
4b78a802
BS		 972}
973
974static const VMStateDescription vmstate_port92_isa = {
975 .name = "port92",
976 .version_id = 1,
977 .minimum_version_id = 1,
d49805ae 978 .fields = (VMStateField[]) {
4b78a802
BS		 979 VMSTATE_UINT8(outport, Port92State),
980 VMSTATE_END_OF_LIST()
981 }
982};
983
984static void port92_reset(DeviceState *d)
985{
a0881c64 986 Port92State *s = PORT92(d);
4b78a802
BS		 987
988 s->outport &= ~1;
989}
990
23af670e 991static const MemoryRegionOps port92_ops = {
93ef4192
AG		 992 .read = port92_read,
993 .write = port92_write,
994 .impl = {
995 .min_access_size = 1,
996 .max_access_size = 1,
997 },
998 .endianness = DEVICE_LITTLE_ENDIAN,
23af670e
RH		 999};
1000
db895a1e 1001static void port92_initfn(Object *obj)
4b78a802 1002{
db895a1e 1003 Port92State *s = PORT92(obj);
4b78a802 1004
1437c94b 1005 memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1);
23af670e 1006
4b78a802 1007 s->outport = 0;
d812b3d6
EV		 1008
1009 qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, PORT92_A20_LINE, 1);
db895a1e
AF		 1010}
1011
1012static void port92_realizefn(DeviceState *dev, Error **errp)
1013{
1014 ISADevice *isadev = ISA_DEVICE(dev);
1015 Port92State *s = PORT92(dev);
1016
1017 isa_register_ioport(isadev, &s->io, 0x92);
4b78a802
BS		 1018}
1019
8f04ee08
AL		 1020static void port92_class_initfn(ObjectClass *klass, void *data)
1021{
39bffca2 1022 DeviceClass *dc = DEVICE_CLASS(klass);
db895a1e 1023
db895a1e 1024 dc->realize = port92_realizefn;
39bffca2
AL		 1025 dc->reset = port92_reset;
1026 dc->vmsd = &vmstate_port92_isa;
f3b17640
MA		 1027 /*
1028 * Reason: unlike ordinary ISA devices, this one needs additional
1029 * wiring: its A20 output line needs to be wired up by
1030 * port92_init().
1031 */
e90f2a8c 1032 dc->user_creatable = false;
8f04ee08
AL		 1033}
1034
8c43a6f0 1035static const TypeInfo port92_info = {
a0881c64 1036 .name = TYPE_PORT92,
39bffca2
AL		 1037 .parent = TYPE_ISA_DEVICE,
1038 .instance_size = sizeof(Port92State),
db895a1e 1039 .instance_init = port92_initfn,
39bffca2 1040 .class_init = port92_class_initfn,
4b78a802
BS		 1041};
1042
83f7d43a 1043static void port92_register_types(void)
4b78a802 1044{
39bffca2 1045 type_register_static(&port92_info);
4b78a802 1046}
83f7d43a
AF		 1047
1048type_init(port92_register_types)
4b78a802 1049
956a3e6b 1050static void handle_a20_line_change(void *opaque, int irq, int level)
59b8ad81 1051{
cc36a7a2 1052 X86CPU *cpu = opaque;
e1a23744 1053
956a3e6b 1054 /* XXX: send to all CPUs ? */
4b78a802 1055 /* XXX: add logic to handle multiple A20 line sources */
cc36a7a2 1056 x86_cpu_set_a20(cpu, level);
e1a23744
FB		 1057}
1058
4c5b10b7
JS		 1059int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
1060{
7d67110f 1061 int index = le32_to_cpu(e820_reserve.count);
4c5b10b7
JS		 1062 struct e820_entry *entry;
1063
7d67110f
GH		 1064 if (type != E820_RAM) {
1065 /* old FW_CFG_E820_TABLE entry -- reservations only */
1066 if (index >= E820_NR_ENTRIES) {
1067 return -EBUSY;
1068 }
1069 entry = &e820_reserve.entry[index++];
1070
1071 entry->address = cpu_to_le64(address);
1072 entry->length = cpu_to_le64(length);
1073 entry->type = cpu_to_le32(type);
1074
1075 e820_reserve.count = cpu_to_le32(index);
1076 }
4c5b10b7 1077
7d67110f 1078 /* new "etc/e820" file -- include ram too */
ab3ad07f 1079 e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1);
7d67110f
GH		 1080 e820_table[e820_entries].address = cpu_to_le64(address);
1081 e820_table[e820_entries].length = cpu_to_le64(length);
1082 e820_table[e820_entries].type = cpu_to_le32(type);
1083 e820_entries++;
4c5b10b7 1084
7d67110f 1085 return e820_entries;
4c5b10b7
JS		 1086}
1087
7bf8ef19
GS		 1088int e820_get_num_entries(void)
1089{
1090 return e820_entries;
1091}
1092
1093bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length)
1094{
1095 if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) {
1096 *address = le64_to_cpu(e820_table[idx].address);
1097 *length = le64_to_cpu(e820_table[idx].length);
1098 return true;
1099 }
1100 return false;
1101}
1102
54a40293
EH		 1103/* Enables contiguous-apic-ID mode, for compatibility */
1104static bool compat_apic_id_mode;
1105
1106void enable_compat_apic_id_mode(void)
1107{
1108 compat_apic_id_mode = true;
1109}
1110
1111/* Calculates initial APIC ID for a specific CPU index
1112 *
1113 * Currently we need to be able to calculate the APIC ID from the CPU index
1114 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
1115 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
1116 * all CPUs up to max_cpus.
1117 */
1118static uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
1119{
1120 uint32_t correct_id;
1121 static bool warned;
1122
1123 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
1124 if (compat_apic_id_mode) {
b1c12027 1125 if (cpu_index != correct_id && !warned && !qtest_enabled()) {
54a40293
EH		 1126 error_report("APIC IDs set in compatibility mode, "
1127 "CPU topology won't match the configuration");
1128 warned = true;
1129 }
1130 return cpu_index;
1131 } else {
1132 return correct_id;
1133 }
1134}
1135
f2098f48 1136static void pc_build_smbios(PCMachineState *pcms)
80cabfad 1137{
c97294ec
GS		 1138 uint8_t *smbios_tables, *smbios_anchor;
1139 size_t smbios_tables_len, smbios_anchor_len;
89cc4a27
WH		 1140 struct smbios_phys_mem_area *mem_array;
1141 unsigned i, array_count;
38690a1c
IM		 1142 MachineState *ms = MACHINE(pcms);
1143 X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu);
f2098f48
IM		 1144
1145 /* tell smbios about cpuid version and features */
1146 smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]);
5fd0a9d4
WH		 1147
1148 smbios_tables = smbios_get_table_legacy(&smbios_tables_len);
1149 if (smbios_tables) {
f2098f48 1150 fw_cfg_add_bytes(pcms->fw_cfg, FW_CFG_SMBIOS_ENTRIES,
5fd0a9d4
WH		 1151 smbios_tables, smbios_tables_len);
1152 }
1153
89cc4a27
WH		 1154 /* build the array of physical mem area from e820 table */
1155 mem_array = g_malloc0(sizeof(*mem_array) * e820_get_num_entries());
1156 for (i = 0, array_count = 0; i < e820_get_num_entries(); i++) {
1157 uint64_t addr, len;
1158
1159 if (e820_get_entry(i, E820_RAM, &addr, &len)) {
1160 mem_array[array_count].address = addr;
1161 mem_array[array_count].length = len;
1162 array_count++;
1163 }
1164 }
1165 smbios_get_tables(mem_array, array_count,
1166 &smbios_tables, &smbios_tables_len,
5fd0a9d4 1167 &smbios_anchor, &smbios_anchor_len);
89cc4a27
WH		 1168 g_free(mem_array);
1169
5fd0a9d4 1170 if (smbios_anchor) {
f2098f48 1171 fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-tables",
5fd0a9d4 1172 smbios_tables, smbios_tables_len);
f2098f48 1173 fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-anchor",
5fd0a9d4
WH		 1174 smbios_anchor, smbios_anchor_len);
1175 }
1176}
1177
ebde2465 1178static FWCfgState *bochs_bios_init(AddressSpace *as, PCMachineState *pcms)
5fd0a9d4
WH		 1179{
1180 FWCfgState *fw_cfg;
11c2fd3e 1181 uint64_t *numa_fw_cfg;
ea265072
IM		 1182 int i;
1183 const CPUArchIdList *cpus;
1184 MachineClass *mc = MACHINE_GET_CLASS(pcms);
3cce6243 1185
305ae888 1186 fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, as);
e3cadac0 1187 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
c886fc4c 1188
1d934e89
EH		 1189 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86:
1190 *
a3abd0f2
IM		 1191 * For machine types prior to 1.8, SeaBIOS needs FW_CFG_MAX_CPUS for
1192 * building MPTable, ACPI MADT, ACPI CPU hotplug and ACPI SRAT table,
1193 * that tables are based on xAPIC ID and QEMU<->SeaBIOS interface
1194 * for CPU hotplug also uses APIC ID and not "CPU index".
1195 * This means that FW_CFG_MAX_CPUS is not the "maximum number of CPUs",
1196 * but the "limit to the APIC ID values SeaBIOS may see".
1d934e89 1197 *
a3abd0f2
IM		 1198 * So for compatibility reasons with old BIOSes we are stuck with
1199 * "etc/max-cpus" actually being apic_id_limit
1d934e89 1200 */
ebde2465 1201 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)pcms->apic_id_limit);
905fdcb5 1202 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
089da572
MA		 1203 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES,
1204 acpi_tables, acpi_tables_len);
9b5b76d4 1205 fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
b6f6e3d3 1206
089da572 1207 fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE,
7d67110f
GH		 1208 &e820_reserve, sizeof(e820_reserve));
1209 fw_cfg_add_file(fw_cfg, "etc/e820", e820_table,
1210 sizeof(struct e820_entry) * e820_entries);
11c2fd3e 1211
089da572 1212 fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg));
11c2fd3e
AL		 1213 /* allocate memory for the NUMA channel: one (64bit) word for the number
1214 * of nodes, one word for each VCPU->node and one word for each node to
1215 * hold the amount of memory.
1216 */
ebde2465 1217 numa_fw_cfg = g_new0(uint64_t, 1 + pcms->apic_id_limit + nb_numa_nodes);
11c2fd3e 1218 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
ea265072
IM		 1219 cpus = mc->possible_cpu_arch_ids(MACHINE(pcms));
1220 for (i = 0; i < cpus->len; i++) {
1221 unsigned int apic_id = cpus->cpus[i].arch_id;
ebde2465 1222 assert(apic_id < pcms->apic_id_limit);
d41f3e75 1223 numa_fw_cfg[apic_id + 1] = cpu_to_le64(cpus->cpus[i].props.node_id);
11c2fd3e
AL		 1224 }
1225 for (i = 0; i < nb_numa_nodes; i++) {
ebde2465
IM		 1226 numa_fw_cfg[pcms->apic_id_limit + 1 + i] =
1227 cpu_to_le64(numa_info[i].node_mem);
11c2fd3e 1228 }
089da572 1229 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg,
ebde2465 1230 (1 + pcms->apic_id_limit + nb_numa_nodes) *
1d934e89 1231 sizeof(*numa_fw_cfg));
bf483392
AG		 1232
1233 return fw_cfg;
80cabfad
FB		 1234}
1235
642a4f96
TS		 1236static long get_file_size(FILE *f)
1237{
1238 long where, size;
1239
1240 /* XXX: on Unix systems, using fstat() probably makes more sense */
1241
1242 where = ftell(f);
1243 fseek(f, 0, SEEK_END);
1244 size = ftell(f);
1245 fseek(f, where, SEEK_SET);
1246
1247 return size;
1248}
1249
3cbeb524
AB		 1250/* setup_data types */
1251#define SETUP_NONE 0
1252#define SETUP_E820_EXT 1
1253#define SETUP_DTB 2
1254#define SETUP_PCI 3
1255#define SETUP_EFI 4
1256
1257struct setup_data {
1258 uint64_t next;
1259 uint32_t type;
1260 uint32_t len;
1261 uint8_t data[0];
1262} __attribute__((packed));
1263
df1f79fd
EH		 1264static void load_linux(PCMachineState *pcms,
1265 FWCfgState *fw_cfg)
642a4f96
TS		 1266{
1267 uint16_t protocol;
f3839fda 1268 int setup_size, kernel_size, cmdline_size;
3cbeb524 1269 int dtb_size, setup_data_offset;
642a4f96 1270 uint32_t initrd_max;
c24323dd 1271 uint8_t header[8192], *setup, *kernel;
a8170e5e 1272 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
45a50b16 1273 FILE *f;
bf4e5d92 1274 char *vmode;
df1f79fd 1275 MachineState *machine = MACHINE(pcms);
cd4040ec 1276 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
3cbeb524 1277 struct setup_data *setup_data;
df1f79fd
EH		 1278 const char *kernel_filename = machine->kernel_filename;
1279 const char *initrd_filename = machine->initrd_filename;
3cbeb524 1280 const char *dtb_filename = machine->dtb;
df1f79fd 1281 const char *kernel_cmdline = machine->kernel_cmdline;
642a4f96
TS		 1282
1283 /* Align to 16 bytes as a paranoia measure */
1284 cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
1285
1286 /* load the kernel header */
1287 f = fopen(kernel_filename, "rb");
1288 if (!f || !(kernel_size = get_file_size(f)) ||
0f9d76e5
LG		 1289 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
1290 MIN(ARRAY_SIZE(header), kernel_size)) {
1291 fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
1292 kernel_filename, strerror(errno));
1293 exit(1);
642a4f96
TS		 1294 }
1295
1296 /* kernel protocol version */
bc4edd79 1297#if 0
642a4f96 1298 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
bc4edd79 1299#endif
0f9d76e5
LG		 1300 if (ldl_p(header+0x202) == 0x53726448) {
1301 protocol = lduw_p(header+0x206);
1302 } else {
1303 /* This looks like a multiboot kernel. If it is, let's stop
1304 treating it like a Linux kernel. */
52001445 1305 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
0f9d76e5 1306 kernel_cmdline, kernel_size, header)) {
82663ee2 1307 return;
0f9d76e5
LG		 1308 }
1309 protocol = 0;
f16408df 1310 }
642a4f96
TS		 1311
1312 if (protocol < 0x200 || !(header[0x211] & 0x01)) {
0f9d76e5
LG		 1313 /* Low kernel */
1314 real_addr = 0x90000;
1315 cmdline_addr = 0x9a000 - cmdline_size;
1316 prot_addr = 0x10000;
642a4f96 1317 } else if (protocol < 0x202) {
0f9d76e5
LG		 1318 /* High but ancient kernel */
1319 real_addr = 0x90000;
1320 cmdline_addr = 0x9a000 - cmdline_size;
1321 prot_addr = 0x100000;
642a4f96 1322 } else {
0f9d76e5
LG		 1323 /* High and recent kernel */
1324 real_addr = 0x10000;
1325 cmdline_addr = 0x20000;
1326 prot_addr = 0x100000;
642a4f96
TS		 1327 }
1328
bc4edd79 1329#if 0
642a4f96 1330 fprintf(stderr,
0f9d76e5
LG		 1331 "qemu: real_addr = 0x" TARGET_FMT_plx "\n"
1332 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n"
1333 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n",
1334 real_addr,
1335 cmdline_addr,
1336 prot_addr);
bc4edd79 1337#endif
642a4f96
TS		 1338
1339 /* highest address for loading the initrd */
0f9d76e5
LG		 1340 if (protocol >= 0x203) {
1341 initrd_max = ldl_p(header+0x22c);
1342 } else {
1343 initrd_max = 0x37ffffff;
1344 }
642a4f96 1345
cd4040ec
EH		 1346 if (initrd_max >= pcms->below_4g_mem_size - pcmc->acpi_data_size) {
1347 initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1;
927766c7 1348 }
642a4f96 1349
57a46d05
AG		 1350 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
1351 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
96f80586 1352 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
642a4f96
TS		 1353
1354 if (protocol >= 0x202) {
0f9d76e5 1355 stl_p(header+0x228, cmdline_addr);
642a4f96 1356 } else {
0f9d76e5
LG		 1357 stw_p(header+0x20, 0xA33F);
1358 stw_p(header+0x22, cmdline_addr-real_addr);
642a4f96
TS		 1359 }
1360
bf4e5d92
PT		 1361 /* handle vga= parameter */
1362 vmode = strstr(kernel_cmdline, "vga=");
1363 if (vmode) {
1364 unsigned int video_mode;
1365 /* skip "vga=" */
1366 vmode += 4;
1367 if (!strncmp(vmode, "normal", 6)) {
1368 video_mode = 0xffff;
1369 } else if (!strncmp(vmode, "ext", 3)) {
1370 video_mode = 0xfffe;
1371 } else if (!strncmp(vmode, "ask", 3)) {
1372 video_mode = 0xfffd;
1373 } else {
1374 video_mode = strtol(vmode, NULL, 0);
1375 }
1376 stw_p(header+0x1fa, video_mode);
1377 }
1378
642a4f96 1379 /* loader type */
5cbdb3a3 1380 /* High nybble = B reserved for QEMU; low nybble is revision number.
642a4f96
TS		 1381 If this code is substantially changed, you may want to consider
1382 incrementing the revision. */
0f9d76e5
LG		 1383 if (protocol >= 0x200) {
1384 header[0x210] = 0xB0;
1385 }
642a4f96
TS		 1386 /* heap */
1387 if (protocol >= 0x201) {
0f9d76e5
LG		 1388 header[0x211] |= 0x80; /* CAN_USE_HEAP */
1389 stw_p(header+0x224, cmdline_addr-real_addr-0x200);
642a4f96
TS		 1390 }
1391
1392 /* load initrd */
1393 if (initrd_filename) {
c24323dd
PM		 1394 gsize initrd_size;
1395 gchar *initrd_data;
1396 GError *gerr = NULL;
1397
0f9d76e5
LG		 1398 if (protocol < 0x200) {
1399 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
1400 exit(1);
1401 }
642a4f96 1402
c24323dd
PM		 1403 if (!g_file_get_contents(initrd_filename, &initrd_data,
1404 &initrd_size, &gerr)) {
7454e51d 1405 fprintf(stderr, "qemu: error reading initrd %s: %s\n",
c24323dd 1406 initrd_filename, gerr->message);
d6fa4b77 1407 exit(1);
c24323dd
PM		 1408 }
1409 if (initrd_size >= initrd_max) {
f3839fda 1410 fprintf(stderr, "qemu: initrd is too large, cannot support."
c24323dd
PM		 1411 "(max: %"PRIu32", need %"PRId64")\n",
1412 initrd_max, (uint64_t)initrd_size);
f3839fda 1413 exit(1);
d6fa4b77
MK		 1414 }
1415
45a50b16 1416 initrd_addr = (initrd_max-initrd_size) & ~4095;
57a46d05 1417
57a46d05
AG		 1418 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
1419 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
1420 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
642a4f96 1421
0f9d76e5
LG		 1422 stl_p(header+0x218, initrd_addr);
1423 stl_p(header+0x21c, initrd_size);
642a4f96
TS		 1424 }
1425
45a50b16 1426 /* load kernel and setup */
642a4f96 1427 setup_size = header[0x1f1];
0f9d76e5
LG		 1428 if (setup_size == 0) {
1429 setup_size = 4;
1430 }
642a4f96 1431 setup_size = (setup_size+1)*512;
ec5fd402
PB		 1432 if (setup_size > kernel_size) {
1433 fprintf(stderr, "qemu: invalid kernel header\n");
1434 exit(1);
1435 }
45a50b16 1436 kernel_size -= setup_size;
642a4f96 1437
7267c094
AL		 1438 setup = g_malloc(setup_size);
1439 kernel = g_malloc(kernel_size);
45a50b16 1440 fseek(f, 0, SEEK_SET);
5a41ecc5
KS		 1441 if (fread(setup, 1, setup_size, f) != setup_size) {
1442 fprintf(stderr, "fread() failed\n");
1443 exit(1);
1444 }
1445 if (fread(kernel, 1, kernel_size, f) != kernel_size) {
1446 fprintf(stderr, "fread() failed\n");
1447 exit(1);
1448 }
642a4f96 1449 fclose(f);
3cbeb524
AB		 1450
1451 /* append dtb to kernel */
1452 if (dtb_filename) {
1453 if (protocol < 0x209) {
1454 fprintf(stderr, "qemu: Linux kernel too old to load a dtb\n");
1455 exit(1);
1456 }
1457
1458 dtb_size = get_image_size(dtb_filename);
1459 if (dtb_size <= 0) {
1460 fprintf(stderr, "qemu: error reading dtb %s: %s\n",
1461 dtb_filename, strerror(errno));
1462 exit(1);
1463 }
1464
1465 setup_data_offset = QEMU_ALIGN_UP(kernel_size, 16);
1466 kernel_size = setup_data_offset + sizeof(struct setup_data) + dtb_size;
1467 kernel = g_realloc(kernel, kernel_size);
1468
1469 stq_p(header+0x250, prot_addr + setup_data_offset);
1470
1471 setup_data = (struct setup_data *)(kernel + setup_data_offset);
1472 setup_data->next = 0;
1473 setup_data->type = cpu_to_le32(SETUP_DTB);
1474 setup_data->len = cpu_to_le32(dtb_size);
1475
1476 load_image_size(dtb_filename, setup_data->data, dtb_size);
1477 }
1478
45a50b16 1479 memcpy(setup, header, MIN(sizeof(header), setup_size));
57a46d05
AG		 1480
1481 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
1482 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1483 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
1484
1485 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
1486 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
1487 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
1488
98e753a6
IM		 1489 option_rom[nb_option_roms].bootindex = 0;
1490 option_rom[nb_option_roms].name = "linuxboot.bin";
1491 if (pcmc->linuxboot_dma_enabled && fw_cfg_dma_enabled(fw_cfg)) {
b2a575a1 1492 option_rom[nb_option_roms].name = "linuxboot_dma.bin";
b2a575a1 1493 }
57a46d05 1494 nb_option_roms++;
642a4f96
TS		 1495}
1496
b41a2cd1
FB		 1497#define NE2000_NB_MAX 6
1498
675d6f82
BS		 1499static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
1500 0x280, 0x380 };
1501static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
b41a2cd1 1502
48a18b3c 1503void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
a41b2ff2
PB		 1504{
1505 static int nb_ne2k = 0;
1506
1507 if (nb_ne2k == NE2000_NB_MAX)
1508 return;
48a18b3c 1509 isa_ne2000_init(bus, ne2000_io[nb_ne2k],
9453c5bc 1510 ne2000_irq[nb_ne2k], nd);
a41b2ff2
PB		 1511 nb_ne2k++;
1512}
1513
92a16d7a 1514DeviceState *cpu_get_current_apic(void)
0e26b7b8 1515{
4917cf44
AF		 1516 if (current_cpu) {
1517 X86CPU *cpu = X86_CPU(current_cpu);
02e51483 1518 return cpu->apic_state;
0e26b7b8
BS		 1519 } else {
1520 return NULL;
1521 }
1522}
1523
845773ab 1524void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
53b67b30 1525{
c3affe56 1526 X86CPU *cpu = opaque;
53b67b30
BS		 1527
1528 if (level) {
c3affe56 1529 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
53b67b30
BS		 1530 }
1531}
1532
074281d6 1533static void pc_new_cpu(const char *typename, int64_t apic_id, Error **errp)
31050930 1534{
074281d6 1535 Object *cpu = NULL;
31050930
IM		 1536 Error *local_err = NULL;
1537
074281d6 1538 cpu = object_new(typename);
31050930 1539
c7b4efb4 1540 object_property_set_uint(cpu, apic_id, "apic-id", &local_err);
074281d6 1541 object_property_set_bool(cpu, true, "realized", &local_err);
31050930 1542
074281d6 1543 object_unref(cpu);
021c9d25 1544 error_propagate(errp, local_err);
31050930
IM		 1545}
1546
c649983b
IM		 1547void pc_hot_add_cpu(const int64_t id, Error **errp)
1548{
38690a1c 1549 MachineState *ms = MACHINE(qdev_get_machine());
c649983b 1550 int64_t apic_id = x86_cpu_apic_id_from_index(id);
0e3bd562 1551 Error *local_err = NULL;
c649983b 1552
8de433cb
IM		 1553 if (id < 0) {
1554 error_setg(errp, "Invalid CPU id: %" PRIi64, id);
1555 return;
1556 }
1557
5ff020b7
EH		 1558 if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) {
1559 error_setg(errp, "Unable to add CPU: %" PRIi64
1560 ", resulting APIC ID (%" PRIi64 ") is too large",
1561 id, apic_id);
1562 return;
1563 }
1564
311ca98d 1565 pc_new_cpu(ms->cpu_type, apic_id, &local_err);
0e3bd562
AF		 1566 if (local_err) {
1567 error_propagate(errp, local_err);
1568 return;
1569 }
c649983b
IM		 1570}
1571
4884b7bf 1572void pc_cpus_init(PCMachineState *pcms)
70166477
IY		 1573{
1574 int i;
c96a1c0b 1575 const CPUArchIdList *possible_cpus;
311ca98d 1576 MachineState *ms = MACHINE(pcms);
c96a1c0b 1577 MachineClass *mc = MACHINE_GET_CLASS(pcms);
70166477 1578
ebde2465
IM		 1579 /* Calculates the limit to CPU APIC ID values
1580 *
1581 * Limit for the APIC ID value, so that all
1582 * CPU APIC IDs are < pcms->apic_id_limit.
1583 *
1584 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init().
1585 */
1586 pcms->apic_id_limit = x86_cpu_apic_id_from_index(max_cpus - 1) + 1;
311ca98d 1587 possible_cpus = mc->possible_cpu_arch_ids(ms);
c96a1c0b 1588 for (i = 0; i < smp_cpus; i++) {
d342eb76
IM		 1589 pc_new_cpu(possible_cpus->cpus[i].type, possible_cpus->cpus[i].arch_id,
1590 &error_fatal);
70166477
IY		 1591 }
1592}
1593
217f1b4a
HZ		 1594static void pc_build_feature_control_file(PCMachineState *pcms)
1595{
38690a1c
IM		 1596 MachineState *ms = MACHINE(pcms);
1597 X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu);
217f1b4a
HZ		 1598 CPUX86State *env = &cpu->env;
1599 uint32_t unused, ecx, edx;
1600 uint64_t feature_control_bits = 0;
1601 uint64_t *val;
1602
1603 cpu_x86_cpuid(env, 1, 0, &unused, &unused, &ecx, &edx);
1604 if (ecx & CPUID_EXT_VMX) {
1605 feature_control_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1606 }
1607
1608 if ((edx & (CPUID_EXT2_MCE | CPUID_EXT2_MCA)) ==
1609 (CPUID_EXT2_MCE | CPUID_EXT2_MCA) &&
1610 (env->mcg_cap & MCG_LMCE_P)) {
1611 feature_control_bits |= FEATURE_CONTROL_LMCE;
1612 }
1613
1614 if (!feature_control_bits) {
1615 return;
1616 }
1617
1618 val = g_malloc(sizeof(*val));
1619 *val = cpu_to_le64(feature_control_bits | FEATURE_CONTROL_LOCKED);
1620 fw_cfg_add_file(pcms->fw_cfg, "etc/msr_feature_control", val, sizeof(*val));
1621}
1622
e3cadac0
IM		 1623static void rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count)
1624{
1625 if (cpus_count > 0xff) {
1626 /* If the number of CPUs can't be represented in 8 bits, the
1627 * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just
1628 * to make old BIOSes fail more predictably.
1629 */
1630 rtc_set_memory(rtc, 0x5f, 0);
1631 } else {
1632 rtc_set_memory(rtc, 0x5f, cpus_count - 1);
1633 }
1634}
1635
3459a625 1636static
9ebeed0c 1637void pc_machine_done(Notifier *notifier, void *data)
3459a625 1638{
9ebeed0c
EH		 1639 PCMachineState *pcms = container_of(notifier,
1640 PCMachineState, machine_done);
1641 PCIBus *bus = pcms->bus;
2118196b 1642
ba157b69 1643 /* set the number of CPUs */
e3cadac0 1644 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus);
ba157b69 1645
2118196b
MA		 1646 if (bus) {
1647 int extra_hosts = 0;
1648
1649 QLIST_FOREACH(bus, &bus->child, sibling) {
1650 /* look for expander root buses */
1651 if (pci_bus_is_root(bus)) {
1652 extra_hosts++;
1653 }
1654 }
f264d360 1655 if (extra_hosts && pcms->fw_cfg) {
2118196b
MA		 1656 uint64_t *val = g_malloc(sizeof(*val));
1657 *val = cpu_to_le64(extra_hosts);
f264d360 1658 fw_cfg_add_file(pcms->fw_cfg,
2118196b
MA		 1659 "etc/extra-pci-roots", val, sizeof(*val));
1660 }
1661 }
1662
bb292f5a 1663 acpi_setup();
6d42eefa 1664 if (pcms->fw_cfg) {
f2098f48 1665 pc_build_smbios(pcms);
217f1b4a 1666 pc_build_feature_control_file(pcms);
e3cadac0
IM		 1667 /* update FW_CFG_NB_CPUS to account for -device added CPUs */
1668 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
6d42eefa 1669 }
60c5e104 1670
1a26f466 1671 if (pcms->apic_id_limit > 255 && !xen_enabled()) {
60c5e104
IM		 1672 IntelIOMMUState *iommu = INTEL_IOMMU_DEVICE(x86_iommu_get_default());
1673
a924b3d8 1674 if (!iommu || !x86_iommu_ir_supported(X86_IOMMU_DEVICE(iommu)) ||
60c5e104
IM		 1675 iommu->intr_eim != ON_OFF_AUTO_ON) {
1676 error_report("current -smp configuration requires "
1677 "Extended Interrupt Mode enabled. "
1678 "You can add an IOMMU using: "
1679 "-device intel-iommu,intremap=on,eim=on");
1680 exit(EXIT_FAILURE);
1681 }
1682 }
3459a625
MT		 1683}
1684
e4e8ba04 1685void pc_guest_info_init(PCMachineState *pcms)
3459a625 1686{
1f3aba37 1687 int i;
b20c9bd5 1688
dd4c2f01
EH		 1689 pcms->apic_xrupt_override = kvm_allows_irq0_override();
1690 pcms->numa_nodes = nb_numa_nodes;
1691 pcms->node_mem = g_malloc0(pcms->numa_nodes *
1692 sizeof *pcms->node_mem);
8c85901e 1693 for (i = 0; i < nb_numa_nodes; i++) {
dd4c2f01 1694 pcms->node_mem[i] = numa_info[i].node_mem;
8c85901e
WG		 1695 }
1696
9ebeed0c
EH		 1697 pcms->machine_done.notify = pc_machine_done;
1698 qemu_add_machine_init_done_notifier(&pcms->machine_done);
3459a625
MT		 1699}
1700
83d08f26
MT		 1701/* setup pci memory address space mapping into system address space */
1702void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
1703 MemoryRegion *pci_address_space)
39848901 1704{
83d08f26
MT		 1705 /* Set to lower priority than RAM */
1706 memory_region_add_subregion_overlap(system_memory, 0x0,
1707 pci_address_space, -1);
39848901
IM		 1708}
1709
f7e4dd6c
GH		 1710void pc_acpi_init(const char *default_dsdt)
1711{
c5a98cf3 1712 char *filename;
f7e4dd6c
GH		 1713
1714 if (acpi_tables != NULL) {
1715 /* manually set via -acpitable, leave it alone */
1716 return;
1717 }
1718
1719 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt);
1720 if (filename == NULL) {
2ab4b135 1721 warn_report("failed to find %s", default_dsdt);
c5a98cf3 1722 } else {
5bdb59a2
MA		 1723 QemuOpts *opts = qemu_opts_create(qemu_find_opts("acpi"), NULL, 0,
1724 &error_abort);
c5a98cf3 1725 Error *err = NULL;
f7e4dd6c 1726
5bdb59a2 1727 qemu_opt_set(opts, "file", filename, &error_abort);
0c764a9d 1728
1a4b2666 1729 acpi_table_add_builtin(opts, &err);
c5a98cf3 1730 if (err) {
88f83f35 1731 warn_reportf_err(err, "failed to load %s: ", filename);
c5a98cf3 1732 }
c5a98cf3 1733 g_free(filename);
f7e4dd6c 1734 }
f7e4dd6c
GH		 1735}
1736
7bc35e0f 1737void xen_load_linux(PCMachineState *pcms)
b33a5bbf
CL		 1738{
1739 int i;
1740 FWCfgState *fw_cfg;
1741
df1f79fd 1742 assert(MACHINE(pcms)->kernel_filename != NULL);
b33a5bbf 1743
305ae888 1744 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE);
e3cadac0 1745 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
b33a5bbf
CL		 1746 rom_set_fw(fw_cfg);
1747
df1f79fd 1748 load_linux(pcms, fw_cfg);
b33a5bbf
CL		 1749 for (i = 0; i < nb_option_roms; i++) {
1750 assert(!strcmp(option_rom[i].name, "linuxboot.bin") ||
b2a575a1 1751 !strcmp(option_rom[i].name, "linuxboot_dma.bin") ||
b33a5bbf
CL		 1752 !strcmp(option_rom[i].name, "multiboot.bin"));
1753 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1754 }
f264d360 1755 pcms->fw_cfg = fw_cfg;
b33a5bbf
CL		 1756}
1757
5934e216
EH		 1758void pc_memory_init(PCMachineState *pcms,
1759 MemoryRegion *system_memory,
1760 MemoryRegion *rom_memory,
1761 MemoryRegion **ram_memory)
80cabfad 1762{
cbc5b5f3
JJ		 1763 int linux_boot, i;
1764 MemoryRegion *ram, *option_rom_mr;
00cb2a99 1765 MemoryRegion *ram_below_4g, *ram_above_4g;
a88b362c 1766 FWCfgState *fw_cfg;
62b160c0 1767 MachineState *machine = MACHINE(pcms);
16a9e8a5 1768 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
d592d303 1769
c8d163bc
EH		 1770 assert(machine->ram_size == pcms->below_4g_mem_size +
1771 pcms->above_4g_mem_size);
9521d42b
PB		 1772
1773 linux_boot = (machine->kernel_filename != NULL);
80cabfad 1774
00cb2a99 1775 /* Allocate RAM. We allocate it as a single memory region and use
66a0a2cb 1776 * aliases to address portions of it, mostly for backwards compatibility
00cb2a99
AK		 1777 * with older qemus that used qemu_ram_alloc().
1778 */
7267c094 1779 ram = g_malloc(sizeof(*ram));
9521d42b
PB		 1780 memory_region_allocate_system_memory(ram, NULL, "pc.ram",
1781 machine->ram_size);
ae0a5466 1782 *ram_memory = ram;
7267c094 1783 ram_below_4g = g_malloc(sizeof(*ram_below_4g));
2c9b15ca 1784 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram,
c8d163bc 1785 0, pcms->below_4g_mem_size);
00cb2a99 1786 memory_region_add_subregion(system_memory, 0, ram_below_4g);
c8d163bc
EH		 1787 e820_add_entry(0, pcms->below_4g_mem_size, E820_RAM);
1788 if (pcms->above_4g_mem_size > 0) {
7267c094 1789 ram_above_4g = g_malloc(sizeof(*ram_above_4g));
2c9b15ca 1790 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram,
c8d163bc
EH		 1791 pcms->below_4g_mem_size,
1792 pcms->above_4g_mem_size);
00cb2a99
AK		 1793 memory_region_add_subregion(system_memory, 0x100000000ULL,
1794 ram_above_4g);
c8d163bc 1795 e820_add_entry(0x100000000ULL, pcms->above_4g_mem_size, E820_RAM);
bbe80adf 1796 }
82b36dc3 1797
bb292f5a 1798 if (!pcmc->has_reserved_memory &&
ca8336f3 1799 (machine->ram_slots ||
9521d42b 1800 (machine->maxram_size > machine->ram_size))) {
ca8336f3
IM		 1801 MachineClass *mc = MACHINE_GET_CLASS(machine);
1802
1803 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
1804 mc->name);
1805 exit(EXIT_FAILURE);
1806 }
1807
b0c14ec4
DH		 1808 /* always allocate the device memory information */
1809 machine->device_memory = g_malloc0(sizeof(*machine->device_memory));
1810
f2ffbe2b 1811 /* initialize device memory address space */
bb292f5a 1812 if (pcmc->has_reserved_memory &&
9521d42b 1813 (machine->ram_size < machine->maxram_size)) {
f2ffbe2b 1814 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size;
619d11e4 1815
a0cc8856
IM		 1816 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
1817 error_report("unsupported amount of memory slots: %"PRIu64,
1818 machine->ram_slots);
1819 exit(EXIT_FAILURE);
1820 }
1821
f2c38522
PK		 1822 if (QEMU_ALIGN_UP(machine->maxram_size,
1823 TARGET_PAGE_SIZE) != machine->maxram_size) {
1824 error_report("maximum memory size must by aligned to multiple of "
1825 "%d bytes", TARGET_PAGE_SIZE);
1826 exit(EXIT_FAILURE);
1827 }
1828
b0c14ec4 1829 machine->device_memory->base =
d471bf3e 1830 ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, 1 * GiB);
619d11e4 1831
16a9e8a5 1832 if (pcmc->enforce_aligned_dimm) {
f2ffbe2b 1833 /* size device region assuming 1G page max alignment per slot */
d471bf3e 1834 device_mem_size += (1 * GiB) * machine->ram_slots;
085f8e88
IM		 1835 }
1836
f2ffbe2b
DH		 1837 if ((machine->device_memory->base + device_mem_size) <
1838 device_mem_size) {
619d11e4
IM		 1839 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT,
1840 machine->maxram_size);
1841 exit(EXIT_FAILURE);
1842 }
1843
b0c14ec4 1844 memory_region_init(&machine->device_memory->mr, OBJECT(pcms),
f2ffbe2b 1845 "device-memory", device_mem_size);
b0c14ec4
DH		 1846 memory_region_add_subregion(system_memory, machine->device_memory->base,
1847 &machine->device_memory->mr);
619d11e4 1848 }
cbc5b5f3
JJ		 1849
1850 /* Initialize PC system firmware */
5db3f0de 1851 pc_system_firmware_init(rom_memory, !pcmc->pci_enabled);
00cb2a99 1852
7267c094 1853 option_rom_mr = g_malloc(sizeof(*option_rom_mr));
98a99ce0 1854 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE,
f8ed85ac 1855 &error_fatal);
208fa0e4
IM		 1856 if (pcmc->pci_enabled) {
1857 memory_region_set_readonly(option_rom_mr, true);
1858 }
4463aee6 1859 memory_region_add_subregion_overlap(rom_memory,
00cb2a99
AK		 1860 PC_ROM_MIN_VGA,
1861 option_rom_mr,
1862 1);
f753ff16 1863
ebde2465 1864 fw_cfg = bochs_bios_init(&address_space_memory, pcms);
c886fc4c 1865
8832cb80 1866 rom_set_fw(fw_cfg);
1d108d97 1867
b0c14ec4 1868 if (pcmc->has_reserved_memory && machine->device_memory->base) {
de268e13 1869 uint64_t *val = g_malloc(sizeof(*val));
2f8b5008 1870 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
b0c14ec4 1871 uint64_t res_mem_end = machine->device_memory->base;
2f8b5008
IM		 1872
1873 if (!pcmc->broken_reserved_end) {
b0c14ec4 1874 res_mem_end += memory_region_size(&machine->device_memory->mr);
2f8b5008 1875 }
d471bf3e 1876 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB));
de268e13
IM		 1877 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
1878 }
1879
f753ff16 1880 if (linux_boot) {
df1f79fd 1881 load_linux(pcms, fw_cfg);
f753ff16
PB		 1882 }
1883
1884 for (i = 0; i < nb_option_roms; i++) {
2e55e842 1885 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
406c8df3 1886 }
f264d360 1887 pcms->fw_cfg = fw_cfg;
cb135f59
PX		 1888
1889 /* Init default IOAPIC address space */
1890 pcms->ioapic_as = &address_space_memory;
3d53f5c3
IY		 1891}
1892
9fa99d25
MA		 1893/*
1894 * The 64bit pci hole starts after "above 4G RAM" and
1895 * potentially the space reserved for memory hotplug.
1896 */
1897uint64_t pc_pci_hole64_start(void)
1898{
1899 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
1900 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
b0c14ec4 1901 MachineState *ms = MACHINE(pcms);
9fa99d25
MA		 1902 uint64_t hole64_start = 0;
1903
b0c14ec4
DH		 1904 if (pcmc->has_reserved_memory && ms->device_memory->base) {
1905 hole64_start = ms->device_memory->base;
9fa99d25 1906 if (!pcmc->broken_reserved_end) {
b0c14ec4 1907 hole64_start += memory_region_size(&ms->device_memory->mr);
9fa99d25
MA		 1908 }
1909 } else {
1910 hole64_start = 0x100000000ULL + pcms->above_4g_mem_size;
1911 }
1912
d471bf3e 1913 return ROUND_UP(hole64_start, 1 * GiB);
9fa99d25
MA		 1914}
1915
0b0cc076 1916qemu_irq pc_allocate_cpu_irq(void)
845773ab 1917{
0b0cc076 1918 return qemu_allocate_irq(pic_irq_request, NULL, 0);
845773ab
IY		 1919}
1920
48a18b3c 1921DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
765d7908 1922{
ad6d45fa
AL		 1923 DeviceState *dev = NULL;
1924
bab47d9a 1925 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA);
16094b75
AJ		 1926 if (pci_bus) {
1927 PCIDevice *pcidev = pci_vga_init(pci_bus);
1928 dev = pcidev ? &pcidev->qdev : NULL;
1929 } else if (isa_bus) {
1930 ISADevice *isadev = isa_vga_init(isa_bus);
4a17cc4f 1931 dev = isadev ? DEVICE(isadev) : NULL;
765d7908 1932 }
bab47d9a 1933 rom_reset_order_override();
ad6d45fa 1934 return dev;
765d7908
IY		 1935}
1936
258711c6
JG		 1937static const MemoryRegionOps ioport80_io_ops = {
1938 .write = ioport80_write,
c02e1eac 1939 .read = ioport80_read,
258711c6
JG		 1940 .endianness = DEVICE_NATIVE_ENDIAN,
1941 .impl = {
1942 .min_access_size = 1,
1943 .max_access_size = 1,
1944 },
1945};
1946
1947static const MemoryRegionOps ioportF0_io_ops = {
1948 .write = ioportF0_write,
c02e1eac 1949 .read = ioportF0_read,
258711c6
JG		 1950 .endianness = DEVICE_NATIVE_ENDIAN,
1951 .impl = {
1952 .min_access_size = 1,
1953 .max_access_size = 1,
1954 },
1955};
1956
ac64273c
PMD		 1957static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport)
1958{
1959 int i;
1960 DriveInfo *fd[MAX_FD];
1961 qemu_irq *a20_line;
1962 ISADevice *i8042, *port92, *vmmouse;
1963
def337ff 1964 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS);
ac64273c
PMD		 1965 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
1966
1967 for (i = 0; i < MAX_FD; i++) {
1968 fd[i] = drive_get(IF_FLOPPY, 0, i);
1969 create_fdctrl |= !!fd[i];
1970 }
1971 if (create_fdctrl) {
1972 fdctrl_init_isa(isa_bus, fd);
1973 }
1974
1975 i8042 = isa_create_simple(isa_bus, "i8042");
1976 if (!no_vmport) {
1977 vmport_init(isa_bus);
1978 vmmouse = isa_try_create(isa_bus, "vmmouse");
1979 } else {
1980 vmmouse = NULL;
1981 }
1982 if (vmmouse) {
1983 DeviceState *dev = DEVICE(vmmouse);
1984 qdev_prop_set_ptr(dev, "ps2_mouse", i8042);
1985 qdev_init_nofail(dev);
1986 }
1987 port92 = isa_create_simple(isa_bus, "port92");
1988
1989 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1990 i8042_setup_a20_line(i8042, a20_line[0]);
1991 port92_init(port92, a20_line[1]);
1992 g_free(a20_line);
1993}
1994
48a18b3c 1995void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
1611977c 1996 ISADevice **rtc_state,
fd53c87c 1997 bool create_fdctrl,
7a10ef51 1998 bool no_vmport,
feddd2fd 1999 bool has_pit,
3a87d009 2000 uint32_t hpet_irqs)
ffe513da
IY		 2001{
2002 int i;
ce967e2f
JK		 2003 DeviceState *hpet = NULL;
2004 int pit_isa_irq = 0;
2005 qemu_irq pit_alt_irq = NULL;
7d932dfd 2006 qemu_irq rtc_irq = NULL;
ac64273c 2007 ISADevice *pit = NULL;
258711c6
JG		 2008 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
2009 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
ffe513da 2010
2c9b15ca 2011 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
258711c6 2012 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
ffe513da 2013
2c9b15ca 2014 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
258711c6 2015 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
ffe513da 2016
5d17c0d2
JK		 2017 /*
2018 * Check if an HPET shall be created.
2019 *
2020 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
2021 * when the HPET wants to take over. Thus we have to disable the latter.
2022 */
2023 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
7a10ef51 2024 /* In order to set property, here not using sysbus_try_create_simple */
51116102 2025 hpet = qdev_try_create(NULL, TYPE_HPET);
dd703b99 2026 if (hpet) {
7a10ef51
LPF		 2027 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7
2028 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23,
2029 * IRQ8 and IRQ2.
2030 */
5d7fb0f2 2031 uint8_t compat = object_property_get_uint(OBJECT(hpet),
7a10ef51
LPF		 2032 HPET_INTCAP, NULL);
2033 if (!compat) {
2034 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
2035 }
2036 qdev_init_nofail(hpet);
2037 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
2038
b881fbe9 2039 for (i = 0; i < GSI_NUM_PINS; i++) {
1356b98d 2040 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
dd703b99 2041 }
ce967e2f
JK		 2042 pit_isa_irq = -1;
2043 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
2044 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
822557eb 2045 }
ffe513da 2046 }
6c646a11 2047 *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq);
7d932dfd
JK		 2048
2049 qemu_register_boot_set(pc_boot_set, *rtc_state);
2050
feddd2fd 2051 if (!xen_enabled() && has_pit) {
15eafc2e 2052 if (kvm_pit_in_kernel()) {
c2d8d311
SS		 2053 pit = kvm_pit_init(isa_bus, 0x40);
2054 } else {
acf695ec 2055 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
c2d8d311
SS		 2056 }
2057 if (hpet) {
2058 /* connect PIT to output control line of the HPET */
4a17cc4f 2059 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
c2d8d311
SS		 2060 }
2061 pcspk_init(isa_bus, pit);
ce967e2f 2062 }
ffe513da 2063
55f613ac 2064 i8257_dma_init(isa_bus, 0);
ffe513da 2065
ac64273c
PMD		 2066 /* Super I/O */
2067 pc_superio_init(isa_bus, create_fdctrl, no_vmport);
ffe513da
IY		 2068}
2069
4b9c264b 2070void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus)
9011a1a7
IY		 2071{
2072 int i;
2073
bab47d9a 2074 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC);
9011a1a7
IY		 2075 for (i = 0; i < nb_nics; i++) {
2076 NICInfo *nd = &nd_table[i];
4b9c264b 2077 const char *model = nd->model ? nd->model : pcmc->default_nic_model;
9011a1a7 2078
4b9c264b 2079 if (g_str_equal(model, "ne2k_isa")) {
9011a1a7
IY		 2080 pc_init_ne2k_isa(isa_bus, nd);
2081 } else {
4b9c264b 2082 pci_nic_init_nofail(nd, pci_bus, model, NULL);
9011a1a7
IY		 2083 }
2084 }
bab47d9a 2085 rom_reset_order_override();
9011a1a7
IY		 2086}
2087
a39e3564
JB		 2088void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name)
2089{
2090 DeviceState *dev;
2091 SysBusDevice *d;
2092 unsigned int i;
2093
15eafc2e 2094 if (kvm_ioapic_in_kernel()) {
a39e3564
JB		 2095 dev = qdev_create(NULL, "kvm-ioapic");
2096 } else {
2097 dev = qdev_create(NULL, "ioapic");
2098 }
2099 if (parent_name) {
2100 object_property_add_child(object_resolve_path(parent_name, NULL),
2101 "ioapic", OBJECT(dev), NULL);
2102 }
2103 qdev_init_nofail(dev);
1356b98d 2104 d = SYS_BUS_DEVICE(dev);
3a4a4697 2105 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS);
a39e3564
JB		 2106
2107 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
2108 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i);
2109 }
2110}
d5747cac 2111
d468115b
DH		 2112static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2113 Error **errp)
2114{
2115 const PCMachineState *pcms = PC_MACHINE(hotplug_dev);
b0e62443 2116 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
d468115b 2117 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
b0e62443 2118 const uint64_t legacy_align = TARGET_PAGE_SIZE;
d468115b
DH		 2119
2120 /*
2121 * When -no-acpi is used with Q35 machine type, no ACPI is built,
2122 * but pcms->acpi_dev is still created. Check !acpi_enabled in
2123 * addition to cover this case.
2124 */
2125 if (!pcms->acpi_dev || !acpi_enabled) {
2126 error_setg(errp,
2127 "memory hotplug is not enabled: missing acpi device or acpi disabled");
2128 return;
2129 }
2130
2131 if (is_nvdimm && !pcms->acpi_nvdimm_state.is_enabled) {
2132 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'");
2133 return;
2134 }
8f1ffe5b 2135
fd3416f5 2136 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev),
b0e62443 2137 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp);
d468115b
DH		 2138}
2139
bb6e2f7a
DH		 2140static void pc_memory_plug(HotplugHandler *hotplug_dev,
2141 DeviceState *dev, Error **errp)
95bee274 2142{
3fbcdc27 2143 HotplugHandlerClass *hhc;
95bee274
IM		 2144 Error *local_err = NULL;
2145 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
7f3cf2d6 2146 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
95bee274 2147
fd3416f5 2148 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms), &local_err);
43bbb49e 2149 if (local_err) {
b8865591
IM		 2150 goto out;
2151 }
2152
7f3cf2d6 2153 if (is_nvdimm) {
284197e4 2154 nvdimm_plug(&pcms->acpi_nvdimm_state);
c7f8d0f3
XG		 2155 }
2156
3fbcdc27 2157 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
8e23184b 2158 hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort);
95bee274
IM		 2159out:
2160 error_propagate(errp, local_err);
2161}
2162
bb6e2f7a
DH		 2163static void pc_memory_unplug_request(HotplugHandler *hotplug_dev,
2164 DeviceState *dev, Error **errp)
64fec58e
TC		 2165{
2166 HotplugHandlerClass *hhc;
2167 Error *local_err = NULL;
2168 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
2169
8cd91ace
HZ		 2170 /*
2171 * When -no-acpi is used with Q35 machine type, no ACPI is built,
2172 * but pcms->acpi_dev is still created. Check !acpi_enabled in
2173 * addition to cover this case.
2174 */
2175 if (!pcms->acpi_dev || !acpi_enabled) {
64fec58e 2176 error_setg(&local_err,
8cd91ace 2177 "memory hotplug is not enabled: missing acpi device or acpi disabled");
64fec58e
TC		 2178 goto out;
2179 }
2180
b097cc52
XG		 2181 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
2182 error_setg(&local_err,
2183 "nvdimm device hot unplug is not supported yet.");
2184 goto out;
2185 }
2186
64fec58e
TC		 2187 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
2188 hhc->unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
2189
2190out:
2191 error_propagate(errp, local_err);
2192}
2193
bb6e2f7a
DH		 2194static void pc_memory_unplug(HotplugHandler *hotplug_dev,
2195 DeviceState *dev, Error **errp)
f7d3e29d
TC		 2196{
2197 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
f7d3e29d
TC		 2198 HotplugHandlerClass *hhc;
2199 Error *local_err = NULL;
2200
2201 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
2202 hhc->unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
2203
2204 if (local_err) {
2205 goto out;
2206 }
2207
fd3416f5 2208 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms));
f7d3e29d
TC		 2209 object_unparent(OBJECT(dev));
2210
2211 out:
2212 error_propagate(errp, local_err);
2213}
2214
3811ef14
IM		 2215static int pc_apic_cmp(const void *a, const void *b)
2216{
2217 CPUArchId *apic_a = (CPUArchId *)a;
2218 CPUArchId *apic_b = (CPUArchId *)b;
2219
2220 return apic_a->arch_id - apic_b->arch_id;
2221}
2222
7baef5cf 2223/* returns pointer to CPUArchId descriptor that matches CPU's apic_id
38690a1c 2224 * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no
b12227af 2225 * entry corresponding to CPU's apic_id returns NULL.
7baef5cf 2226 */
1ea69c0e 2227static CPUArchId *pc_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
7baef5cf 2228{
7baef5cf
IM		 2229 CPUArchId apic_id, *found_cpu;
2230
1ea69c0e 2231 apic_id.arch_id = id;
38690a1c
IM		 2232 found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus,
2233 ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus),
7baef5cf
IM		 2234 pc_apic_cmp);
2235 if (found_cpu && idx) {
38690a1c 2236 *idx = found_cpu - ms->possible_cpus->cpus;
7baef5cf
IM		 2237 }
2238 return found_cpu;
2239}
2240
5279569e
GZ		 2241static void pc_cpu_plug(HotplugHandler *hotplug_dev,
2242 DeviceState *dev, Error **errp)
2243{
7baef5cf 2244 CPUArchId *found_cpu;
5279569e
GZ		 2245 HotplugHandlerClass *hhc;
2246 Error *local_err = NULL;
1ea69c0e 2247 X86CPU *cpu = X86_CPU(dev);
5279569e
GZ		 2248 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
2249
a44a49db
IM		 2250 if (pcms->acpi_dev) {
2251 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
2252 hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
2253 if (local_err) {
2254 goto out;
2255 }
5279569e
GZ		 2256 }
2257
e3cadac0
IM		 2258 /* increment the number of CPUs */
2259 pcms->boot_cpus++;
26ef65be 2260 if (pcms->rtc) {
e3cadac0 2261 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus);
26ef65be
IM		 2262 }
2263 if (pcms->fw_cfg) {
e3cadac0 2264 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
2d996150
GZ		 2265 }
2266
1ea69c0e 2267 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL);
8aba3842 2268 found_cpu->cpu = OBJECT(dev);
5279569e
GZ		 2269out:
2270 error_propagate(errp, local_err);
2271}
8872c25a
IM		 2272static void pc_cpu_unplug_request_cb(HotplugHandler *hotplug_dev,
2273 DeviceState *dev, Error **errp)
2274{
73360e27 2275 int idx = -1;
8872c25a
IM		 2276 HotplugHandlerClass *hhc;
2277 Error *local_err = NULL;
1ea69c0e 2278 X86CPU *cpu = X86_CPU(dev);
8872c25a
IM		 2279 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
2280
75ba2ddb
IM		 2281 if (!pcms->acpi_dev) {
2282 error_setg(&local_err, "CPU hot unplug not supported without ACPI");
2283 goto out;
2284 }
2285
1ea69c0e 2286 pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);
73360e27
IM		 2287 assert(idx != -1);
2288 if (idx == 0) {
2289 error_setg(&local_err, "Boot CPU is unpluggable");
2290 goto out;
2291 }
2292
8872c25a
IM		 2293 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
2294 hhc->unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
2295
2296 if (local_err) {
2297 goto out;
2298 }
2299
2300 out:
2301 error_propagate(errp, local_err);
2302
2303}
2304
2305static void pc_cpu_unplug_cb(HotplugHandler *hotplug_dev,
2306 DeviceState *dev, Error **errp)
2307{
8fe6374e 2308 CPUArchId *found_cpu;
8872c25a
IM		 2309 HotplugHandlerClass *hhc;
2310 Error *local_err = NULL;
1ea69c0e 2311 X86CPU *cpu = X86_CPU(dev);
8872c25a
IM		 2312 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
2313
2314 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
2315 hhc->unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
2316
2317 if (local_err) {
2318 goto out;
2319 }
2320
1ea69c0e 2321 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL);
8fe6374e
IM		 2322 found_cpu->cpu = NULL;
2323 object_unparent(OBJECT(dev));
8872c25a 2324
e3cadac0
IM		 2325 /* decrement the number of CPUs */
2326 pcms->boot_cpus--;
2327 /* Update the number of CPUs in CMOS */
2328 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus);
2329 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
8872c25a
IM		 2330 out:
2331 error_propagate(errp, local_err);
2332}
5279569e 2333
4ec60c76
IM		 2334static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
2335 DeviceState *dev, Error **errp)
2336{
2337 int idx;
a15d2728 2338 CPUState *cs;
e8f7b83e 2339 CPUArchId *cpu_slot;
d89c2b8b 2340 X86CPUTopoInfo topo;
4ec60c76 2341 X86CPU *cpu = X86_CPU(dev);
6970c5ff 2342 MachineState *ms = MACHINE(hotplug_dev);
4ec60c76 2343 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
4ec60c76 2344
6970c5ff
IM		 2345 if(!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) {
2346 error_setg(errp, "Invalid CPU type, expected cpu type: '%s'",
2347 ms->cpu_type);
2348 return;
2349 }
2350
e8f7b83e
IM		 2351 /* if APIC ID is not set, set it based on socket/core/thread properties */
2352 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
2353 int max_socket = (max_cpus - 1) / smp_threads / smp_cores;
2354
2355 if (cpu->socket_id < 0) {
2356 error_setg(errp, "CPU socket-id is not set");
2357 return;
2358 } else if (cpu->socket_id > max_socket) {
2359 error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u",
2360 cpu->socket_id, max_socket);
2361 return;
2362 }
2363 if (cpu->core_id < 0) {
2364 error_setg(errp, "CPU core-id is not set");
2365 return;
2366 } else if (cpu->core_id > (smp_cores - 1)) {
2367 error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u",
2368 cpu->core_id, smp_cores - 1);
2369 return;
2370 }
2371 if (cpu->thread_id < 0) {
2372 error_setg(errp, "CPU thread-id is not set");
2373 return;
2374 } else if (cpu->thread_id > (smp_threads - 1)) {
2375 error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u",
2376 cpu->thread_id, smp_threads - 1);
2377 return;
2378 }
2379
2380 topo.pkg_id = cpu->socket_id;
2381 topo.core_id = cpu->core_id;
2382 topo.smt_id = cpu->thread_id;
2383 cpu->apic_id = apicid_from_topo_ids(smp_cores, smp_threads, &topo);
2384 }
2385
1ea69c0e 2386 cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);
4ec60c76 2387 if (!cpu_slot) {
38690a1c
IM		 2388 MachineState *ms = MACHINE(pcms);
2389
e8f7b83e
IM		 2390 x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo);
2391 error_setg(errp, "Invalid CPU [socket: %u, core: %u, thread: %u] with"
2392 " APIC ID %" PRIu32 ", valid index range 0:%d",
2393 topo.pkg_id, topo.core_id, topo.smt_id, cpu->apic_id,
38690a1c 2394 ms->possible_cpus->len - 1);
4ec60c76
IM		 2395 return;
2396 }
2397
2398 if (cpu_slot->cpu) {
2399 error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists",
2400 idx, cpu->apic_id);
2401 return;
2402 }
d89c2b8b
IM		 2403
2404 /* if 'address' properties socket-id/core-id/thread-id are not set, set them
c5514d0e 2405 * so that machine_query_hotpluggable_cpus would show correct values
d89c2b8b
IM		 2406 */
2407 /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn()
2408 * once -smp refactoring is complete and there will be CPU private
2409 * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */
2410 x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo);
2411 if (cpu->socket_id != -1 && cpu->socket_id != topo.pkg_id) {
2412 error_setg(errp, "property socket-id: %u doesn't match set apic-id:"
2413 " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo.pkg_id);
2414 return;
2415 }
2416 cpu->socket_id = topo.pkg_id;
2417
2418 if (cpu->core_id != -1 && cpu->core_id != topo.core_id) {
2419 error_setg(errp, "property core-id: %u doesn't match set apic-id:"
2420 " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo.core_id);
2421 return;
2422 }
2423 cpu->core_id = topo.core_id;
2424
2425 if (cpu->thread_id != -1 && cpu->thread_id != topo.smt_id) {
2426 error_setg(errp, "property thread-id: %u doesn't match set apic-id:"
2427 " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, topo.smt_id);
2428 return;
2429 }
2430 cpu->thread_id = topo.smt_id;
a15d2728 2431
e9688fab
RK		 2432 if (cpu->hyperv_vpindex && !kvm_hv_vpindex_settable()) {
2433 error_setg(errp, "kernel doesn't allow setting HyperV VP_INDEX");
2434 return;
2435 }
2436
a15d2728
IM		 2437 cs = CPU(cpu);
2438 cs->cpu_index = idx;
93b2a8cb 2439
a0ceb640 2440 numa_cpu_pre_plug(cpu_slot, dev, errp);
4ec60c76
IM		 2441}
2442
2443static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
2444 DeviceState *dev, Error **errp)
2445{
d468115b
DH		 2446 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2447 pc_memory_pre_plug(hotplug_dev, dev, errp);
2448 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
4ec60c76
IM		 2449 pc_cpu_pre_plug(hotplug_dev, dev, errp);
2450 }
2451}
2452
95bee274
IM		 2453static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev,
2454 DeviceState *dev, Error **errp)
2455{
2456 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
bb6e2f7a 2457 pc_memory_plug(hotplug_dev, dev, errp);
5279569e
GZ		 2458 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2459 pc_cpu_plug(hotplug_dev, dev, errp);
95bee274
IM		 2460 }
2461}
2462
d9c5c5b8
TC		 2463static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
2464 DeviceState *dev, Error **errp)
2465{
64fec58e 2466 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
bb6e2f7a 2467 pc_memory_unplug_request(hotplug_dev, dev, errp);
8872c25a
IM		 2468 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2469 pc_cpu_unplug_request_cb(hotplug_dev, dev, errp);
64fec58e
TC		 2470 } else {
2471 error_setg(errp, "acpi: device unplug request for not supported device"
2472 " type: %s", object_get_typename(OBJECT(dev)));
2473 }
d9c5c5b8
TC		 2474}
2475
232391c1
TC		 2476static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
2477 DeviceState *dev, Error **errp)
2478{
f7d3e29d 2479 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
bb6e2f7a 2480 pc_memory_unplug(hotplug_dev, dev, errp);
8872c25a
IM		 2481 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2482 pc_cpu_unplug_cb(hotplug_dev, dev, errp);
f7d3e29d
TC		 2483 } else {
2484 error_setg(errp, "acpi: device unplug for not supported device"
2485 " type: %s", object_get_typename(OBJECT(dev)));
2486 }
232391c1
TC		 2487}
2488
95bee274
IM		 2489static HotplugHandler *pc_get_hotpug_handler(MachineState *machine,
2490 DeviceState *dev)
2491{
5279569e
GZ		 2492 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
2493 object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
95bee274
IM		 2494 return HOTPLUG_HANDLER(machine);
2495 }
2496
38aefb57 2497 return NULL;
95bee274
IM		 2498}
2499
bf1e8939 2500static void
f2ffbe2b
DH		 2501pc_machine_get_device_memory_region_size(Object *obj, Visitor *v,
2502 const char *name, void *opaque,
2503 Error **errp)
bf1e8939 2504{
b0c14ec4
DH		 2505 MachineState *ms = MACHINE(obj);
2506 int64_t value = memory_region_size(&ms->device_memory->mr);
bf1e8939 2507
51e72bc1 2508 visit_type_int(v, name, &value, errp);
bf1e8939
IM		 2509}
2510
c87b1520 2511static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v,
d7bce999
EB		 2512 const char *name, void *opaque,
2513 Error **errp)
c87b1520
DS		 2514{
2515 PCMachineState *pcms = PC_MACHINE(obj);
2516 uint64_t value = pcms->max_ram_below_4g;
2517
51e72bc1 2518 visit_type_size(v, name, &value, errp);
c87b1520
DS		 2519}
2520
2521static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v,
d7bce999
EB		 2522 const char *name, void *opaque,
2523 Error **errp)
c87b1520
DS		 2524{
2525 PCMachineState *pcms = PC_MACHINE(obj);
2526 Error *error = NULL;
2527 uint64_t value;
2528
51e72bc1 2529 visit_type_size(v, name, &value, &error);
c87b1520
DS		 2530 if (error) {
2531 error_propagate(errp, error);
2532 return;
2533 }
d471bf3e 2534 if (value > 4 * GiB) {
455b0fde
EB		 2535 error_setg(&error,
2536 "Machine option 'max-ram-below-4g=%"PRIu64
2537 "' expects size less than or equal to 4G", value);
c87b1520
DS		 2538 error_propagate(errp, error);
2539 return;
2540 }
2541
d471bf3e 2542 if (value < 1 * MiB) {
9e5d2c52
AF		 2543 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary,"
2544 "BIOS may not work with less than 1MiB", value);
c87b1520
DS		 2545 }
2546
2547 pcms->max_ram_below_4g = value;
2548}
2549
d7bce999
EB		 2550static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name,
2551 void *opaque, Error **errp)
9b23cfb7
DDAG		 2552{
2553 PCMachineState *pcms = PC_MACHINE(obj);
d1048bef 2554 OnOffAuto vmport = pcms->vmport;
9b23cfb7 2555
51e72bc1 2556 visit_type_OnOffAuto(v, name, &vmport, errp);
9b23cfb7
DDAG		 2557}
2558
d7bce999
EB		 2559static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name,
2560 void *opaque, Error **errp)
9b23cfb7
DDAG		 2561{
2562 PCMachineState *pcms = PC_MACHINE(obj);
2563
51e72bc1 2564 visit_type_OnOffAuto(v, name, &pcms->vmport, errp);
9b23cfb7
DDAG		 2565}
2566
355023f2
PB		 2567bool pc_machine_is_smm_enabled(PCMachineState *pcms)
2568{
2569 bool smm_available = false;
2570
2571 if (pcms->smm == ON_OFF_AUTO_OFF) {
2572 return false;
2573 }
2574
2575 if (tcg_enabled() || qtest_enabled()) {
2576 smm_available = true;
2577 } else if (kvm_enabled()) {
2578 smm_available = kvm_has_smm();
2579 }
2580
2581 if (smm_available) {
2582 return true;
2583 }
2584
2585 if (pcms->smm == ON_OFF_AUTO_ON) {
2586 error_report("System Management Mode not supported by this hypervisor.");
2587 exit(1);
2588 }
2589 return false;
2590}
2591
d7bce999
EB		 2592static void pc_machine_get_smm(Object *obj, Visitor *v, const char *name,
2593 void *opaque, Error **errp)
355023f2
PB		 2594{
2595 PCMachineState *pcms = PC_MACHINE(obj);
2596 OnOffAuto smm = pcms->smm;
2597
51e72bc1 2598 visit_type_OnOffAuto(v, name, &smm, errp);
355023f2
PB		 2599}
2600
d7bce999
EB		 2601static void pc_machine_set_smm(Object *obj, Visitor *v, const char *name,
2602 void *opaque, Error **errp)
355023f2
PB		 2603{
2604 PCMachineState *pcms = PC_MACHINE(obj);
2605
51e72bc1 2606 visit_type_OnOffAuto(v, name, &pcms->smm, errp);
355023f2
PB		 2607}
2608
87252e1b
XG		 2609static bool pc_machine_get_nvdimm(Object *obj, Error **errp)
2610{
2611 PCMachineState *pcms = PC_MACHINE(obj);
2612
5fe79386 2613 return pcms->acpi_nvdimm_state.is_enabled;
87252e1b
XG		 2614}
2615
2616static void pc_machine_set_nvdimm(Object *obj, bool value, Error **errp)
2617{
2618 PCMachineState *pcms = PC_MACHINE(obj);
2619
5fe79386 2620 pcms->acpi_nvdimm_state.is_enabled = value;
87252e1b
XG		 2621}
2622
11c39b5c 2623static char *pc_machine_get_nvdimm_persistence(Object *obj, Error **errp)
9ab3aad2
RZ		 2624{
2625 PCMachineState *pcms = PC_MACHINE(obj);
9ab3aad2 2626
11c39b5c 2627 return g_strdup(pcms->acpi_nvdimm_state.persistence_string);
9ab3aad2
RZ		 2628}
2629
11c39b5c 2630static void pc_machine_set_nvdimm_persistence(Object *obj, const char *value,
9ab3aad2
RZ		 2631 Error **errp)
2632{
2633 PCMachineState *pcms = PC_MACHINE(obj);
11c39b5c
RZ		 2634 AcpiNVDIMMState *nvdimm_state = &pcms->acpi_nvdimm_state;
2635
2636 if (strcmp(value, "cpu") == 0)
2637 nvdimm_state->persistence = 3;
2638 else if (strcmp(value, "mem-ctrl") == 0)
2639 nvdimm_state->persistence = 2;
2640 else {
d319e05d
MA		 2641 error_setg(errp, "-machine nvdimm-persistence=%s: unsupported option",
2642 value);
2643 return;
9ab3aad2
RZ		 2644 }
2645
11c39b5c
RZ		 2646 g_free(nvdimm_state->persistence_string);
2647 nvdimm_state->persistence_string = g_strdup(value);
9ab3aad2
RZ		 2648}
2649
be232eb0
CP		 2650static bool pc_machine_get_smbus(Object *obj, Error **errp)
2651{
2652 PCMachineState *pcms = PC_MACHINE(obj);
2653
f5878b03 2654 return pcms->smbus_enabled;
be232eb0
CP		 2655}
2656
2657static void pc_machine_set_smbus(Object *obj, bool value, Error **errp)
2658{
2659 PCMachineState *pcms = PC_MACHINE(obj);
2660
f5878b03 2661 pcms->smbus_enabled = value;
be232eb0
CP		 2662}
2663
272f0428
CP		 2664static bool pc_machine_get_sata(Object *obj, Error **errp)
2665{
2666 PCMachineState *pcms = PC_MACHINE(obj);
2667
f5878b03 2668 return pcms->sata_enabled;
272f0428
CP		 2669}
2670
2671static void pc_machine_set_sata(Object *obj, bool value, Error **errp)
2672{
2673 PCMachineState *pcms = PC_MACHINE(obj);
2674
f5878b03 2675 pcms->sata_enabled = value;
272f0428
CP		 2676}
2677
feddd2fd
CP		 2678static bool pc_machine_get_pit(Object *obj, Error **errp)
2679{
2680 PCMachineState *pcms = PC_MACHINE(obj);
2681
f5878b03 2682 return pcms->pit_enabled;
feddd2fd
CP		 2683}
2684
2685static void pc_machine_set_pit(Object *obj, bool value, Error **errp)
2686{
2687 PCMachineState *pcms = PC_MACHINE(obj);
2688
f5878b03 2689 pcms->pit_enabled = value;
feddd2fd
CP		 2690}
2691
bf1e8939
IM		 2692static void pc_machine_initfn(Object *obj)
2693{
c87b1520
DS		 2694 PCMachineState *pcms = PC_MACHINE(obj);
2695
5ec7d098 2696 pcms->max_ram_below_4g = 0; /* use default */
355023f2 2697 pcms->smm = ON_OFF_AUTO_AUTO;
d1048bef 2698 pcms->vmport = ON_OFF_AUTO_AUTO;
87252e1b 2699 /* nvdimm is disabled on default. */
5fe79386 2700 pcms->acpi_nvdimm_state.is_enabled = false;
021746c1
WL		 2701 /* acpi build is enabled by default if machine supports it */
2702 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build;
f5878b03
CM		 2703 pcms->smbus_enabled = true;
2704 pcms->sata_enabled = true;
2705 pcms->pit_enabled = true;
bf1e8939
IM		 2706}
2707
ae50c55a
ZG		 2708static void pc_machine_reset(void)
2709{
2710 CPUState *cs;
2711 X86CPU *cpu;
2712
2713 qemu_devices_reset();
2714
2715 /* Reset APIC after devices have been reset to cancel
2716 * any changes that qemu_devices_reset() might have done.
2717 */
2718 CPU_FOREACH(cs) {
2719 cpu = X86_CPU(cs);
2720
2721 if (cpu->apic_state) {
2722 device_reset(cpu->apic_state);
2723 }
2724 }
2725}
2726
ea089eeb
IM		 2727static CpuInstanceProperties
2728pc_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
fb43b73b 2729{
ea089eeb
IM		 2730 MachineClass *mc = MACHINE_GET_CLASS(ms);
2731 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
2732
2733 assert(cpu_index < possible_cpus->len);
2734 return possible_cpus->cpus[cpu_index].props;
fb43b73b
IM		 2735}
2736
79e07936
IM		 2737static int64_t pc_get_default_cpu_node_id(const MachineState *ms, int idx)
2738{
2739 X86CPUTopoInfo topo;
2740
2741 assert(idx < ms->possible_cpus->len);
2742 x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id,
2743 smp_cores, smp_threads, &topo);
2744 return topo.pkg_id % nb_numa_nodes;
2745}
2746
c96a1c0b 2747static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms)
3811ef14 2748{
c96a1c0b
IM		 2749 int i;
2750
2751 if (ms->possible_cpus) {
2752 /*
2753 * make sure that max_cpus hasn't changed since the first use, i.e.
2754 * -smp hasn't been parsed after it
2755 */
2756 assert(ms->possible_cpus->len == max_cpus);
2757 return ms->possible_cpus;
2758 }
2759
2760 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
2761 sizeof(CPUArchId) * max_cpus);
2762 ms->possible_cpus->len = max_cpus;
2763 for (i = 0; i < ms->possible_cpus->len; i++) {
c67ae933
IM		 2764 X86CPUTopoInfo topo;
2765
d342eb76 2766 ms->possible_cpus->cpus[i].type = ms->cpu_type;
f2d672c2 2767 ms->possible_cpus->cpus[i].vcpus_count = 1;
c96a1c0b 2768 ms->possible_cpus->cpus[i].arch_id = x86_cpu_apic_id_from_index(i);
c67ae933
IM		 2769 x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id,
2770 smp_cores, smp_threads, &topo);
2771 ms->possible_cpus->cpus[i].props.has_socket_id = true;
2772 ms->possible_cpus->cpus[i].props.socket_id = topo.pkg_id;
2773 ms->possible_cpus->cpus[i].props.has_core_id = true;
2774 ms->possible_cpus->cpus[i].props.core_id = topo.core_id;
2775 ms->possible_cpus->cpus[i].props.has_thread_id = true;
2776 ms->possible_cpus->cpus[i].props.thread_id = topo.smt_id;
c96a1c0b
IM		 2777 }
2778 return ms->possible_cpus;
3811ef14
IM		 2779}
2780
1255166b
BD		 2781static void x86_nmi(NMIState *n, int cpu_index, Error **errp)
2782{
2783 /* cpu index isn't used */
2784 CPUState *cs;
2785
2786 CPU_FOREACH(cs) {
2787 X86CPU *cpu = X86_CPU(cs);
2788
2789 if (!cpu->apic_state) {
2790 cpu_interrupt(cs, CPU_INTERRUPT_NMI);
2791 } else {
2792 apic_deliver_nmi(cpu->apic_state);
2793 }
2794 }
2795}
2796
95bee274
IM		 2797static void pc_machine_class_init(ObjectClass *oc, void *data)
2798{
2799 MachineClass *mc = MACHINE_CLASS(oc);
2800 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc);
2801 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
1255166b 2802 NMIClass *nc = NMI_CLASS(oc);
95bee274 2803
7102fa70
EH		 2804 pcmc->pci_enabled = true;
2805 pcmc->has_acpi_build = true;
2806 pcmc->rsdp_in_ram = true;
2807 pcmc->smbios_defaults = true;
2808 pcmc->smbios_uuid_encoded = true;
2809 pcmc->gigabyte_align = true;
2810 pcmc->has_reserved_memory = true;
2811 pcmc->kvmclock_enabled = true;
16a9e8a5 2812 pcmc->enforce_aligned_dimm = true;
cd4040ec
EH		 2813 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported
2814 * to be used at the moment, 32K should be enough for a while. */
2815 pcmc->acpi_data_size = 0x20000 + 0x8000;
36f96c4b 2816 pcmc->save_tsc_khz = true;
98e753a6 2817 pcmc->linuxboot_dma_enabled = true;
debbdc00 2818 assert(!mc->get_hotplug_handler);
95bee274 2819 mc->get_hotplug_handler = pc_get_hotpug_handler;
ea089eeb 2820 mc->cpu_index_to_instance_props = pc_cpu_index_to_props;
79e07936 2821 mc->get_default_cpu_node_id = pc_get_default_cpu_node_id;
3811ef14 2822 mc->possible_cpu_arch_ids = pc_possible_cpu_arch_ids;
7b8be49d 2823 mc->auto_enable_numa_with_memhp = true;
c5514d0e 2824 mc->has_hotpluggable_cpus = true;
41742767 2825 mc->default_boot_order = "cad";
4458fb3a 2826 mc->hot_add_cpu = pc_hot_add_cpu;
2059839b 2827 mc->block_default_type = IF_IDE;
4458fb3a 2828 mc->max_cpus = 255;
ae50c55a 2829 mc->reset = pc_machine_reset;
4ec60c76 2830 hc->pre_plug = pc_machine_device_pre_plug_cb;
95bee274 2831 hc->plug = pc_machine_device_plug_cb;
d9c5c5b8 2832 hc->unplug_request = pc_machine_device_unplug_request_cb;
232391c1 2833 hc->unplug = pc_machine_device_unplug_cb;
1255166b 2834 nc->nmi_monitor_handler = x86_nmi;
311ca98d 2835 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
0efc257d 2836
f2ffbe2b
DH		 2837 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int",
2838 pc_machine_get_device_memory_region_size, NULL,
0efc257d
EH		 2839 NULL, NULL, &error_abort);
2840
2841 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size",
2842 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g,
2843 NULL, NULL, &error_abort);
2844
2845 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G,
2846 "Maximum ram below the 4G boundary (32bit boundary)", &error_abort);
2847
2848 object_class_property_add(oc, PC_MACHINE_SMM, "OnOffAuto",
2849 pc_machine_get_smm, pc_machine_set_smm,
2850 NULL, NULL, &error_abort);
2851 object_class_property_set_description(oc, PC_MACHINE_SMM,
2852 "Enable SMM (pc & q35)", &error_abort);
2853
2854 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto",
2855 pc_machine_get_vmport, pc_machine_set_vmport,
2856 NULL, NULL, &error_abort);
2857 object_class_property_set_description(oc, PC_MACHINE_VMPORT,
2858 "Enable vmport (pc & q35)", &error_abort);
2859
2860 object_class_property_add_bool(oc, PC_MACHINE_NVDIMM,
2861 pc_machine_get_nvdimm, pc_machine_set_nvdimm, &error_abort);
be232eb0 2862
11c39b5c
RZ		 2863 object_class_property_add_str(oc, PC_MACHINE_NVDIMM_PERSIST,
2864 pc_machine_get_nvdimm_persistence,
2865 pc_machine_set_nvdimm_persistence, &error_abort);
9ab3aad2 2866
be232eb0
CP		 2867 object_class_property_add_bool(oc, PC_MACHINE_SMBUS,
2868 pc_machine_get_smbus, pc_machine_set_smbus, &error_abort);
272f0428
CP		 2869
2870 object_class_property_add_bool(oc, PC_MACHINE_SATA,
2871 pc_machine_get_sata, pc_machine_set_sata, &error_abort);
feddd2fd
CP		 2872
2873 object_class_property_add_bool(oc, PC_MACHINE_PIT,
2874 pc_machine_get_pit, pc_machine_set_pit, &error_abort);
95bee274
IM		 2875}
2876
d5747cac
IM		 2877static const TypeInfo pc_machine_info = {
2878 .name = TYPE_PC_MACHINE,
2879 .parent = TYPE_MACHINE,
2880 .abstract = true,
2881 .instance_size = sizeof(PCMachineState),
bf1e8939 2882 .instance_init = pc_machine_initfn,
d5747cac 2883 .class_size = sizeof(PCMachineClass),
95bee274
IM		 2884 .class_init = pc_machine_class_init,
2885 .interfaces = (InterfaceInfo[]) {
2886 { TYPE_HOTPLUG_HANDLER },
1255166b 2887 { TYPE_NMI },
95bee274
IM		 2888 { }
2889 },
d5747cac
IM		 2890};
2891
2892static void pc_machine_register_types(void)
2893{
2894 type_register_static(&pc_machine_info);
2895}
2896
2897type_init(pc_machine_register_types)
Empty description
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