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Merge remote-tracking branch 'remotes/thibault/tags/samuel-thibault' into staging
[qemu.git] / hw / i386 / pc.c
CommitLineData
80cabfad
FB		 1/*
2 * QEMU PC System Emulator
5fafdf24 3 *
80cabfad 4 * Copyright (c) 2003-2004 Fabrice Bellard
5fafdf24 5 *
80cabfad
FB		 6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
e688df6b 24
b6a0aa05 25#include "qemu/osdep.h"
d471bf3e 26#include "qemu/units.h"
83c9f4ca 27#include "hw/hw.h"
0d09e41a
PB		 28#include "hw/i386/pc.h"
29#include "hw/char/serial.h"
bb3d5ea8 30#include "hw/char/parallel.h"
0d09e41a 31#include "hw/i386/apic.h"
54a40293
EH		 32#include "hw/i386/topology.h"
33#include "sysemu/cpus.h"
0d09e41a 34#include "hw/block/fdc.h"
83c9f4ca
PB		 35#include "hw/ide.h"
36#include "hw/pci/pci.h"
2118196b 37#include "hw/pci/pci_bus.h"
0d09e41a
PB		 38#include "hw/nvram/fw_cfg.h"
39#include "hw/timer/hpet.h"
a2eb5c0c 40#include "hw/firmware/smbios.h"
83c9f4ca 41#include "hw/loader.h"
ca20cf32 42#include "elf.h"
47b43a1f 43#include "multiboot.h"
0d09e41a 44#include "hw/timer/mc146818rtc.h"
55f613ac 45#include "hw/dma/i8257.h"
0d09e41a 46#include "hw/timer/i8254.h"
47973a2d 47#include "hw/input/i8042.h"
0d09e41a 48#include "hw/audio/pcspk.h"
83c9f4ca
PB		 49#include "hw/pci/msi.h"
50#include "hw/sysbus.h"
9c17d615 51#include "sysemu/sysemu.h"
e35704ba 52#include "sysemu/numa.h"
9c17d615 53#include "sysemu/kvm.h"
b1c12027 54#include "sysemu/qtest.h"
1d31f66b 55#include "kvm_i386.h"
0d09e41a 56#include "hw/xen/xen.h"
ab969087 57#include "hw/xen/start_info.h"
a19cbfb3 58#include "ui/qemu-spice.h"
022c62cb
PB		 59#include "exec/memory.h"
60#include "exec/address-spaces.h"
9c17d615 61#include "sysemu/arch_init.h"
1de7afc9 62#include "qemu/bitmap.h"
0c764a9d 63#include "qemu/config-file.h"
d49b6836 64#include "qemu/error-report.h"
922a01a0 65#include "qemu/option.h"
0445259b 66#include "hw/acpi/acpi.h"
5ff020b7 67#include "hw/acpi/cpu_hotplug.h"
c649983b 68#include "hw/boards.h"
72c194f7 69#include "acpi-build.h"
95bee274 70#include "hw/mem/pc-dimm.h"
e688df6b 71#include "qapi/error.h"
9af23989 72#include "qapi/qapi-visit-common.h"
bf1e8939 73#include "qapi/visitor.h"
15eafc2e 74#include "qom/cpu.h"
1255166b 75#include "hw/nmi.h"
a310e653 76#include "hw/usb.h"
60c5e104 77#include "hw/i386/intel_iommu.h"
489983d6 78#include "hw/net/ne2000-isa.h"
06e0259a 79#include "standard-headers/asm-x86/bootparam.h"
80cabfad 80
471fd342
BS		 81/* debug PC/ISA interrupts */
82//#define DEBUG_IRQ
83
84#ifdef DEBUG_IRQ
85#define DPRINTF(fmt, ...) \
86 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
87#else
88#define DPRINTF(fmt, ...)
89#endif
90
8a92ea2f 91#define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
b6f6e3d3 92#define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
6b35e7bf 93#define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
4c5b10b7 94#define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
40ac17cd 95#define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
80cabfad 96
4c5b10b7
JS		 97#define E820_NR_ENTRIES 16
98
99struct e820_entry {
100 uint64_t address;
101 uint64_t length;
102 uint32_t type;
541dc0d4 103} QEMU_PACKED __attribute((__aligned__(4)));
4c5b10b7
JS		 104
105struct e820_table {
106 uint32_t count;
107 struct e820_entry entry[E820_NR_ENTRIES];
541dc0d4 108} QEMU_PACKED __attribute((__aligned__(4)));
4c5b10b7 109
7d67110f
GH		 110static struct e820_table e820_reserve;
111static struct e820_entry *e820_table;
112static unsigned e820_entries;
dd703b99 113struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
4c5b10b7 114
ab969087
LM		 115/* Physical Address of PVH entry point read from kernel ELF NOTE */
116static size_t pvh_start_addr;
117
abd93cc7 118GlobalProperty pc_compat_3_1[] = {
6c36bddf 119 { "intel-iommu", "dma-drain", "off" },
483c6ad4
BP		 120 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" },
121 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" },
9fe8b7be
VK		 122 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" },
123 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" },
483c6ad4 124 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" },
9fe8b7be
VK		 125 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" },
126 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" },
127 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" },
128 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" },
129 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" },
130 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" },
ecb85fe4
PB		 131 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
132 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
133 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
134 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
135 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
136 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
137 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
b0a19803 138 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" },
f24c3a79 139 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" },
abd93cc7
MAL		 140};
141const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1);
142
ddb3235d 143GlobalProperty pc_compat_3_0[] = {
6c36bddf
EH		 144 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" },
145 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" },
146 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" },
ddb3235d
MAL		 147};
148const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0);
149
0d47310b 150GlobalProperty pc_compat_2_12[] = {
6c36bddf
EH		 151 { TYPE_X86_CPU, "legacy-cache", "on" },
152 { TYPE_X86_CPU, "topoext", "off" },
153 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
154 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
0d47310b
MAL		 155};
156const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12);
157
43df70a9 158GlobalProperty pc_compat_2_11[] = {
6c36bddf
EH		 159 { TYPE_X86_CPU, "x-migrate-smi-count", "off" },
160 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" },
43df70a9
MAL		 161};
162const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11);
163
503224f4 164GlobalProperty pc_compat_2_10[] = {
6c36bddf
EH		 165 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" },
166 { "i440FX-pcihost", "x-pci-hole64-fix", "off" },
167 { "q35-pcihost", "x-pci-hole64-fix", "off" },
503224f4
MAL		 168};
169const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10);
170
3e803152 171GlobalProperty pc_compat_2_9[] = {
6c36bddf 172 { "mch", "extended-tseg-mbytes", "0" },
3e803152
MAL		 173};
174const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9);
175
edc24ccd 176GlobalProperty pc_compat_2_8[] = {
6c36bddf
EH		 177 { TYPE_X86_CPU, "tcg-cpuid", "off" },
178 { "kvmclock", "x-mach-use-reliable-get-clock", "off" },
179 { "ICH9-LPC", "x-smi-broadcast", "off" },
180 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" },
181 { "Haswell-" TYPE_X86_CPU, "stepping", "1" },
edc24ccd
MAL		 182};
183const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8);
184
5a995064 185GlobalProperty pc_compat_2_7[] = {
6c36bddf
EH		 186 { TYPE_X86_CPU, "l3-cache", "off" },
187 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" },
188 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" },
189 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" },
190 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" },
191 { "isa-pcspk", "migrate", "off" },
5a995064
MAL		 192};
193const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7);
194
ff8f261f 195GlobalProperty pc_compat_2_6[] = {
6c36bddf
EH		 196 { TYPE_X86_CPU, "cpuid-0xb", "off" },
197 { "vmxnet3", "romfile", "" },
198 { TYPE_X86_CPU, "fill-mtrr-mask", "off" },
199 { "apic-common", "legacy-instance-id", "on", }
ff8f261f
MAL		 200};
201const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6);
202
fe759610
MAL		 203GlobalProperty pc_compat_2_5[] = {};
204const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5);
205
2f99b9c2
MAL		 206GlobalProperty pc_compat_2_4[] = {
207 PC_CPU_MODEL_IDS("2.4.0")
6c36bddf
EH		 208 { "Haswell-" TYPE_X86_CPU, "abm", "off" },
209 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" },
210 { "Broadwell-" TYPE_X86_CPU, "abm", "off" },
211 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" },
212 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" },
213 { TYPE_X86_CPU, "check", "off" },
214 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" },
215 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" },
216 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" },
217 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" },
218 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" },
219 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" },
220 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" },
221 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", }
2f99b9c2
MAL		 222};
223const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4);
224
8995dd90
MAL		 225GlobalProperty pc_compat_2_3[] = {
226 PC_CPU_MODEL_IDS("2.3.0")
6c36bddf
EH		 227 { TYPE_X86_CPU, "arat", "off" },
228 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" },
229 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" },
230 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" },
231 { "n270" "-" TYPE_X86_CPU, "min-level", "5" },
232 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" },
233 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" },
234 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" },
235 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
236 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
237 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
238 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
239 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
240 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
241 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
242 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
243 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
244 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
245 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
246 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" },
8995dd90
MAL		 247};
248const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3);
249
1c30044e
MAL		 250GlobalProperty pc_compat_2_2[] = {
251 PC_CPU_MODEL_IDS("2.2.0")
6c36bddf
EH		 252 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" },
253 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" },
254 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" },
255 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" },
256 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" },
257 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" },
258 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" },
259 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" },
260 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" },
261 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" },
262 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" },
263 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" },
264 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" },
265 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" },
266 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" },
267 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" },
268 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" },
269 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" },
1c30044e
MAL		 270};
271const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2);
272
c4fc5695
MAL		 273GlobalProperty pc_compat_2_1[] = {
274 PC_CPU_MODEL_IDS("2.1.0")
6c36bddf
EH		 275 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" },
276 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" },
c4fc5695
MAL		 277};
278const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1);
279
a310e653
MAL		 280GlobalProperty pc_compat_2_0[] = {
281 PC_CPU_MODEL_IDS("2.0.0")
6c36bddf
EH		 282 { "virtio-scsi-pci", "any_layout", "off" },
283 { "PIIX4_PM", "memory-hotplug-support", "off" },
284 { "apic", "version", "0x11" },
285 { "nec-usb-xhci", "superspeed-ports-first", "off" },
286 { "nec-usb-xhci", "force-pcie-endcap", "on" },
287 { "pci-serial", "prog_if", "0" },
288 { "pci-serial-2x", "prog_if", "0" },
289 { "pci-serial-4x", "prog_if", "0" },
290 { "virtio-net-pci", "guest_announce", "off" },
291 { "ICH9-LPC", "memory-hotplug-support", "off" },
292 { "xio3130-downstream", COMPAT_PROP_PCP, "off" },
293 { "ioh3420", COMPAT_PROP_PCP, "off" },
a310e653
MAL		 294};
295const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0);
296
297GlobalProperty pc_compat_1_7[] = {
298 PC_CPU_MODEL_IDS("1.7.0")
6c36bddf
EH		 299 { TYPE_USB_DEVICE, "msos-desc", "no" },
300 { "PIIX4_PM", "acpi-pci-hotplug-with-bridge-support", "off" },
301 { "hpet", HPET_INTCAP, "4" },
a310e653
MAL		 302};
303const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7);
304
305GlobalProperty pc_compat_1_6[] = {
306 PC_CPU_MODEL_IDS("1.6.0")
6c36bddf
EH		 307 { "e1000", "mitigation", "off" },
308 { "qemu64-" TYPE_X86_CPU, "model", "2" },
309 { "qemu32-" TYPE_X86_CPU, "model", "3" },
310 { "i440FX-pcihost", "short_root_bus", "1" },
311 { "q35-pcihost", "short_root_bus", "1" },
a310e653
MAL		 312};
313const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6);
314
315GlobalProperty pc_compat_1_5[] = {
316 PC_CPU_MODEL_IDS("1.5.0")
6c36bddf
EH		 317 { "Conroe-" TYPE_X86_CPU, "model", "2" },
318 { "Conroe-" TYPE_X86_CPU, "min-level", "2" },
319 { "Penryn-" TYPE_X86_CPU, "model", "2" },
320 { "Penryn-" TYPE_X86_CPU, "min-level", "2" },
321 { "Nehalem-" TYPE_X86_CPU, "model", "2" },
322 { "Nehalem-" TYPE_X86_CPU, "min-level", "2" },
323 { "virtio-net-pci", "any_layout", "off" },
324 { TYPE_X86_CPU, "pmu", "on" },
325 { "i440FX-pcihost", "short_root_bus", "0" },
326 { "q35-pcihost", "short_root_bus", "0" },
a310e653
MAL		 327};
328const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5);
329
330GlobalProperty pc_compat_1_4[] = {
331 PC_CPU_MODEL_IDS("1.4.0")
6c36bddf
EH		 332 { "scsi-hd", "discard_granularity", "0" },
333 { "scsi-cd", "discard_granularity", "0" },
334 { "scsi-disk", "discard_granularity", "0" },
335 { "ide-hd", "discard_granularity", "0" },
336 { "ide-cd", "discard_granularity", "0" },
337 { "ide-drive", "discard_granularity", "0" },
338 { "virtio-blk-pci", "discard_granularity", "0" },
339 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */
340 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" },
341 { "virtio-net-pci", "ctrl_guest_offloads", "off" },
342 { "e1000", "romfile", "pxe-e1000.rom" },
343 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" },
344 { "pcnet", "romfile", "pxe-pcnet.rom" },
345 { "rtl8139", "romfile", "pxe-rtl8139.rom" },
346 { "virtio-net-pci", "romfile", "pxe-virtio.rom" },
347 { "486-" TYPE_X86_CPU, "model", "0" },
348 { "n270" "-" TYPE_X86_CPU, "movbe", "off" },
349 { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" },
a310e653
MAL		 350};
351const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4);
352
b881fbe9 353void gsi_handler(void *opaque, int n, int level)
1452411b 354{
b881fbe9 355 GSIState *s = opaque;
1452411b 356
b881fbe9
JK		 357 DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n);
358 if (n < ISA_NUM_IRQS) {
359 qemu_set_irq(s->i8259_irq[n], level);
1632dc6a 360 }
b881fbe9 361 qemu_set_irq(s->ioapic_irq[n], level);
2e9947d2 362}
1452411b 363
258711c6
JG		 364static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
365 unsigned size)
80cabfad
FB		 366{
367}
368
c02e1eac
JG		 369static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
370{
a6fc23e5 371 return 0xffffffffffffffffULL;
c02e1eac
JG		 372}
373
f929aad6 374/* MSDOS compatibility mode FPU exception support */
d537cf6c 375static qemu_irq ferr_irq;
8e78eb28
IY		 376
377void pc_register_ferr_irq(qemu_irq irq)
378{
379 ferr_irq = irq;
380}
381
f929aad6
FB		 382/* XXX: add IGNNE support */
383void cpu_set_ferr(CPUX86State *s)
384{
d537cf6c 385 qemu_irq_raise(ferr_irq);
f929aad6
FB		 386}
387
258711c6
JG		 388static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
389 unsigned size)
f929aad6 390{
d537cf6c 391 qemu_irq_lower(ferr_irq);
f929aad6
FB		 392}
393
c02e1eac
JG		 394static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
395{
a6fc23e5 396 return 0xffffffffffffffffULL;
c02e1eac
JG		 397}
398
28ab0e2e 399/* TSC handling */
28ab0e2e
FB		 400uint64_t cpu_get_tsc(CPUX86State *env)
401{
4a1418e0 402 return cpu_get_ticks();
28ab0e2e
FB		 403}
404
3de388f6 405/* IRQ handling */
4a8fa5dc 406int cpu_get_pic_interrupt(CPUX86State *env)
3de388f6 407{
02e51483 408 X86CPU *cpu = x86_env_get_cpu(env);
3de388f6
FB		 409 int intno;
410
bb93e099
WL		 411 if (!kvm_irqchip_in_kernel()) {
412 intno = apic_get_interrupt(cpu->apic_state);
413 if (intno >= 0) {
414 return intno;
415 }
416 /* read the irq from the PIC */
417 if (!apic_accept_pic_intr(cpu->apic_state)) {
418 return -1;
419 }
cf6d64bf 420 }
0e21e12b 421
3de388f6
FB		 422 intno = pic_read_irq(isa_pic);
423 return intno;
424}
425
d537cf6c 426static void pic_irq_request(void *opaque, int irq, int level)
3de388f6 427{
182735ef
AF		 428 CPUState *cs = first_cpu;
429 X86CPU *cpu = X86_CPU(cs);
a5b38b51 430
471fd342 431 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
bb93e099 432 if (cpu->apic_state && !kvm_irqchip_in_kernel()) {
bdc44640 433 CPU_FOREACH(cs) {
182735ef 434 cpu = X86_CPU(cs);
02e51483
CF		 435 if (apic_accept_pic_intr(cpu->apic_state)) {
436 apic_deliver_pic_intr(cpu->apic_state, level);
cf6d64bf 437 }
d5529471
AJ		 438 }
439 } else {
d8ed887b 440 if (level) {
c3affe56 441 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
d8ed887b
AF		 442 } else {
443 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
444 }
a5b38b51 445 }
3de388f6
FB		 446}
447
b0a21b53
FB		 448/* PC cmos mappings */
449
80cabfad
FB		 450#define REG_EQUIPMENT_BYTE 0x14
451
bda05509 452int cmos_get_fd_drive_type(FloppyDriveType fd0)
777428f2
FB		 453{
454 int val;
455
456 switch (fd0) {
2da44dd0 457 case FLOPPY_DRIVE_TYPE_144:
777428f2
FB		 458 /* 1.44 Mb 3"5 drive */
459 val = 4;
460 break;
2da44dd0 461 case FLOPPY_DRIVE_TYPE_288:
777428f2
FB		 462 /* 2.88 Mb 3"5 drive */
463 val = 5;
464 break;
2da44dd0 465 case FLOPPY_DRIVE_TYPE_120:
777428f2
FB		 466 /* 1.2 Mb 5"5 drive */
467 val = 2;
468 break;
2da44dd0 469 case FLOPPY_DRIVE_TYPE_NONE:
777428f2
FB		 470 default:
471 val = 0;
472 break;
473 }
474 return val;
475}
476
9139046c
MA		 477static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
478 int16_t cylinders, int8_t heads, int8_t sectors)
ba6c2377 479{
ba6c2377
FB		 480 rtc_set_memory(s, type_ofs, 47);
481 rtc_set_memory(s, info_ofs, cylinders);
482 rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
483 rtc_set_memory(s, info_ofs + 2, heads);
484 rtc_set_memory(s, info_ofs + 3, 0xff);
485 rtc_set_memory(s, info_ofs + 4, 0xff);
486 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
487 rtc_set_memory(s, info_ofs + 6, cylinders);
488 rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
489 rtc_set_memory(s, info_ofs + 8, sectors);
490}
491
6ac0e82d
AZ		 492/* convert boot_device letter to something recognizable by the bios */
493static int boot_device2nibble(char boot_device)
494{
495 switch(boot_device) {
496 case 'a':
497 case 'b':
498 return 0x01; /* floppy boot */
499 case 'c':
500 return 0x02; /* hard drive boot */
501 case 'd':
502 return 0x03; /* CD-ROM boot */
503 case 'n':
504 return 0x04; /* Network boot */
505 }
506 return 0;
507}
508
ddcd5531 509static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp)
0ecdffbb
AJ		 510{
511#define PC_MAX_BOOT_DEVICES 3
0ecdffbb
AJ		 512 int nbds, bds[3] = { 0, };
513 int i;
514
515 nbds = strlen(boot_device);
516 if (nbds > PC_MAX_BOOT_DEVICES) {
ddcd5531
GA		 517 error_setg(errp, "Too many boot devices for PC");
518 return;
0ecdffbb
AJ		 519 }
520 for (i = 0; i < nbds; i++) {
521 bds[i] = boot_device2nibble(boot_device[i]);
522 if (bds[i] == 0) {
ddcd5531
GA		 523 error_setg(errp, "Invalid boot device for PC: '%c'",
524 boot_device[i]);
525 return;
0ecdffbb
AJ		 526 }
527 }
528 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
d9346e81 529 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
0ecdffbb
AJ		 530}
531
ddcd5531 532static void pc_boot_set(void *opaque, const char *boot_device, Error **errp)
d9346e81 533{
ddcd5531 534 set_boot_dev(opaque, boot_device, errp);
d9346e81
MA		 535}
536
7444ca4e
LE		 537static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy)
538{
539 int val, nb, i;
2da44dd0
JS		 540 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE,
541 FLOPPY_DRIVE_TYPE_NONE };
7444ca4e
LE		 542
543 /* floppy type */
544 if (floppy) {
545 for (i = 0; i < 2; i++) {
546 fd_type[i] = isa_fdc_get_drive_type(floppy, i);
547 }
548 }
549 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
550 cmos_get_fd_drive_type(fd_type[1]);
551 rtc_set_memory(rtc_state, 0x10, val);
552
553 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE);
554 nb = 0;
2da44dd0 555 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) {
7444ca4e
LE		 556 nb++;
557 }
2da44dd0 558 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) {
7444ca4e
LE		 559 nb++;
560 }
561 switch (nb) {
562 case 0:
563 break;
564 case 1:
565 val |= 0x01; /* 1 drive, ready for boot */
566 break;
567 case 2:
568 val |= 0x41; /* 2 drives, ready for boot */
569 break;
570 }
571 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val);
572}
573
c0897e0c
MA		 574typedef struct pc_cmos_init_late_arg {
575 ISADevice *rtc_state;
9139046c 576 BusState *idebus[2];
c0897e0c
MA		 577} pc_cmos_init_late_arg;
578
b86f4613
LE		 579typedef struct check_fdc_state {
580 ISADevice *floppy;
581 bool multiple;
582} CheckFdcState;
583
584static int check_fdc(Object *obj, void *opaque)
585{
586 CheckFdcState *state = opaque;
587 Object *fdc;
588 uint32_t iobase;
589 Error *local_err = NULL;
590
591 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC);
592 if (!fdc) {
593 return 0;
594 }
595
1ea1572a 596 iobase = object_property_get_uint(obj, "iobase", &local_err);
b86f4613
LE		 597 if (local_err || iobase != 0x3f0) {
598 error_free(local_err);
599 return 0;
600 }
601
602 if (state->floppy) {
603 state->multiple = true;
604 } else {
605 state->floppy = ISA_DEVICE(obj);
606 }
607 return 0;
608}
609
610static const char * const fdc_container_path[] = {
611 "/unattached", "/peripheral", "/peripheral-anon"
612};
613
424e4a87
RK		 614/*
615 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
616 * and ACPI objects.
617 */
618ISADevice *pc_find_fdc0(void)
619{
620 int i;
621 Object *container;
622 CheckFdcState state = { 0 };
623
624 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) {
625 container = container_get(qdev_get_machine(), fdc_container_path[i]);
626 object_child_foreach(container, check_fdc, &state);
627 }
628
629 if (state.multiple) {
3dc6f869
AF		 630 warn_report("multiple floppy disk controllers with "
631 "iobase=0x3f0 have been found");
433672b0 632 error_printf("the one being picked for CMOS setup might not reflect "
9e5d2c52 633 "your intent");
424e4a87
RK		 634 }
635
636 return state.floppy;
637}
638
c0897e0c
MA		 639static void pc_cmos_init_late(void *opaque)
640{
641 pc_cmos_init_late_arg *arg = opaque;
642 ISADevice *s = arg->rtc_state;
9139046c
MA		 643 int16_t cylinders;
644 int8_t heads, sectors;
c0897e0c 645 int val;
2adc99b2 646 int i, trans;
c0897e0c 647
9139046c 648 val = 0;
272f0428
CP		 649 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0,
650 &cylinders, &heads, &sectors) >= 0) {
9139046c
MA		 651 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
652 val |= 0xf0;
653 }
272f0428
CP		 654 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1,
655 &cylinders, &heads, &sectors) >= 0) {
9139046c
MA		 656 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
657 val |= 0x0f;
658 }
659 rtc_set_memory(s, 0x12, val);
c0897e0c
MA		 660
661 val = 0;
662 for (i = 0; i < 4; i++) {
9139046c
MA		 663 /* NOTE: ide_get_geometry() returns the physical
664 geometry. It is always such that: 1 <= sects <= 63, 1
665 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
666 geometry can be different if a translation is done. */
272f0428
CP		 667 if (arg->idebus[i / 2] &&
668 ide_get_geometry(arg->idebus[i / 2], i % 2,
9139046c 669 &cylinders, &heads, &sectors) >= 0) {
2adc99b2
MA		 670 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
671 assert((trans & ~3) == 0);
672 val |= trans << (i * 2);
c0897e0c
MA		 673 }
674 }
675 rtc_set_memory(s, 0x39, val);
676
424e4a87 677 pc_cmos_init_floppy(s, pc_find_fdc0());
b86f4613 678
c0897e0c
MA		 679 qemu_unregister_reset(pc_cmos_init_late, opaque);
680}
681
23d30407 682void pc_cmos_init(PCMachineState *pcms,
220a8846 683 BusState *idebus0, BusState *idebus1,
63ffb564 684 ISADevice *s)
80cabfad 685{
7444ca4e 686 int val;
c0897e0c 687 static pc_cmos_init_late_arg arg;
b0a21b53 688
b0a21b53 689 /* various important CMOS locations needed by PC/Bochs bios */
80cabfad
FB		 690
691 /* memory size */
e89001f7 692 /* base memory (first MiB) */
d471bf3e 693 val = MIN(pcms->below_4g_mem_size / KiB, 640);
333190eb
FB		 694 rtc_set_memory(s, 0x15, val);
695 rtc_set_memory(s, 0x16, val >> 8);
e89001f7 696 /* extended memory (next 64MiB) */
d471bf3e
PB		 697 if (pcms->below_4g_mem_size > 1 * MiB) {
698 val = (pcms->below_4g_mem_size - 1 * MiB) / KiB;
e89001f7
MA		 699 } else {
700 val = 0;
701 }
80cabfad
FB		 702 if (val > 65535)
703 val = 65535;
b0a21b53
FB		 704 rtc_set_memory(s, 0x17, val);
705 rtc_set_memory(s, 0x18, val >> 8);
706 rtc_set_memory(s, 0x30, val);
707 rtc_set_memory(s, 0x31, val >> 8);
e89001f7 708 /* memory between 16MiB and 4GiB */
d471bf3e
PB		 709 if (pcms->below_4g_mem_size > 16 * MiB) {
710 val = (pcms->below_4g_mem_size - 16 * MiB) / (64 * KiB);
e89001f7 711 } else {
9da98861 712 val = 0;
e89001f7 713 }
80cabfad
FB		 714 if (val > 65535)
715 val = 65535;
b0a21b53
FB		 716 rtc_set_memory(s, 0x34, val);
717 rtc_set_memory(s, 0x35, val >> 8);
e89001f7 718 /* memory above 4GiB */
88076854 719 val = pcms->above_4g_mem_size / 65536;
e89001f7
MA		 720 rtc_set_memory(s, 0x5b, val);
721 rtc_set_memory(s, 0x5c, val >> 8);
722 rtc_set_memory(s, 0x5d, val >> 16);
3b46e624 723
23d30407 724 object_property_add_link(OBJECT(pcms), "rtc_state",
2d996150 725 TYPE_ISA_DEVICE,
ec68007a 726 (Object **)&pcms->rtc,
2d996150 727 object_property_allow_set_link,
265b578c 728 OBJ_PROP_LINK_STRONG, &error_abort);
23d30407 729 object_property_set_link(OBJECT(pcms), OBJECT(s),
2d996150 730 "rtc_state", &error_abort);
298e01b6 731
007b0657 732 set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal);
80cabfad 733
b0a21b53 734 val = 0;
b0a21b53
FB		 735 val |= 0x02; /* FPU is there */
736 val |= 0x04; /* PS/2 mouse installed */
737 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
738
b86f4613 739 /* hard drives and FDC */
c0897e0c 740 arg.rtc_state = s;
9139046c
MA		 741 arg.idebus[0] = idebus0;
742 arg.idebus[1] = idebus1;
c0897e0c 743 qemu_register_reset(pc_cmos_init_late, &arg);
80cabfad
FB		 744}
745
a0881c64
AF		 746#define TYPE_PORT92 "port92"
747#define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92)
748
4b78a802
BS		 749/* port 92 stuff: could be split off */
750typedef struct Port92State {
a0881c64
AF		 751 ISADevice parent_obj;
752
23af670e 753 MemoryRegion io;
4b78a802 754 uint8_t outport;
d812b3d6 755 qemu_irq a20_out;
4b78a802
BS		 756} Port92State;
757
93ef4192
AG		 758static void port92_write(void *opaque, hwaddr addr, uint64_t val,
759 unsigned size)
4b78a802
BS		 760{
761 Port92State *s = opaque;
4700a316 762 int oldval = s->outport;
4b78a802 763
c5539cb4 764 DPRINTF("port92: write 0x%02" PRIx64 "\n", val);
4b78a802 765 s->outport = val;
d812b3d6 766 qemu_set_irq(s->a20_out, (val >> 1) & 1);
4700a316 767 if ((val & 1) && !(oldval & 1)) {
cf83f140 768 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
4b78a802
BS		 769 }
770}
771
93ef4192
AG		 772static uint64_t port92_read(void *opaque, hwaddr addr,
773 unsigned size)
4b78a802
BS		 774{
775 Port92State *s = opaque;
776 uint32_t ret;
777
778 ret = s->outport;
779 DPRINTF("port92: read 0x%02x\n", ret);
780 return ret;
781}
782
d80fe99d 783static void port92_init(ISADevice *dev, qemu_irq a20_out)
4b78a802 784{
d80fe99d 785 qdev_connect_gpio_out_named(DEVICE(dev), PORT92_A20_LINE, 0, a20_out);
4b78a802
BS		 786}
787
788static const VMStateDescription vmstate_port92_isa = {
789 .name = "port92",
790 .version_id = 1,
791 .minimum_version_id = 1,
d49805ae 792 .fields = (VMStateField[]) {
4b78a802
BS		 793 VMSTATE_UINT8(outport, Port92State),
794 VMSTATE_END_OF_LIST()
795 }
796};
797
798static void port92_reset(DeviceState *d)
799{
a0881c64 800 Port92State *s = PORT92(d);
4b78a802
BS		 801
802 s->outport &= ~1;
803}
804
23af670e 805static const MemoryRegionOps port92_ops = {
93ef4192
AG		 806 .read = port92_read,
807 .write = port92_write,
808 .impl = {
809 .min_access_size = 1,
810 .max_access_size = 1,
811 },
812 .endianness = DEVICE_LITTLE_ENDIAN,
23af670e
RH		 813};
814
db895a1e 815static void port92_initfn(Object *obj)
4b78a802 816{
db895a1e 817 Port92State *s = PORT92(obj);
4b78a802 818
1437c94b 819 memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1);
23af670e 820
4b78a802 821 s->outport = 0;
d812b3d6
EV		 822
823 qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, PORT92_A20_LINE, 1);
db895a1e
AF		 824}
825
826static void port92_realizefn(DeviceState *dev, Error **errp)
827{
828 ISADevice *isadev = ISA_DEVICE(dev);
829 Port92State *s = PORT92(dev);
830
831 isa_register_ioport(isadev, &s->io, 0x92);
4b78a802
BS		 832}
833
8f04ee08
AL		 834static void port92_class_initfn(ObjectClass *klass, void *data)
835{
39bffca2 836 DeviceClass *dc = DEVICE_CLASS(klass);
db895a1e 837
db895a1e 838 dc->realize = port92_realizefn;
39bffca2
AL		 839 dc->reset = port92_reset;
840 dc->vmsd = &vmstate_port92_isa;
f3b17640
MA		 841 /*
842 * Reason: unlike ordinary ISA devices, this one needs additional
843 * wiring: its A20 output line needs to be wired up by
844 * port92_init().
845 */
e90f2a8c 846 dc->user_creatable = false;
8f04ee08
AL		 847}
848
8c43a6f0 849static const TypeInfo port92_info = {
a0881c64 850 .name = TYPE_PORT92,
39bffca2
AL		 851 .parent = TYPE_ISA_DEVICE,
852 .instance_size = sizeof(Port92State),
db895a1e 853 .instance_init = port92_initfn,
39bffca2 854 .class_init = port92_class_initfn,
4b78a802
BS		 855};
856
83f7d43a 857static void port92_register_types(void)
4b78a802 858{
39bffca2 859 type_register_static(&port92_info);
4b78a802 860}
83f7d43a
AF		 861
862type_init(port92_register_types)
4b78a802 863
956a3e6b 864static void handle_a20_line_change(void *opaque, int irq, int level)
59b8ad81 865{
cc36a7a2 866 X86CPU *cpu = opaque;
e1a23744 867
956a3e6b 868 /* XXX: send to all CPUs ? */
4b78a802 869 /* XXX: add logic to handle multiple A20 line sources */
cc36a7a2 870 x86_cpu_set_a20(cpu, level);
e1a23744
FB		 871}
872
4c5b10b7
JS		 873int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
874{
7d67110f 875 int index = le32_to_cpu(e820_reserve.count);
4c5b10b7
JS		 876 struct e820_entry *entry;
877
7d67110f
GH		 878 if (type != E820_RAM) {
879 /* old FW_CFG_E820_TABLE entry -- reservations only */
880 if (index >= E820_NR_ENTRIES) {
881 return -EBUSY;
882 }
883 entry = &e820_reserve.entry[index++];
884
885 entry->address = cpu_to_le64(address);
886 entry->length = cpu_to_le64(length);
887 entry->type = cpu_to_le32(type);
888
889 e820_reserve.count = cpu_to_le32(index);
890 }
4c5b10b7 891
7d67110f 892 /* new "etc/e820" file -- include ram too */
ab3ad07f 893 e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1);
7d67110f
GH		 894 e820_table[e820_entries].address = cpu_to_le64(address);
895 e820_table[e820_entries].length = cpu_to_le64(length);
896 e820_table[e820_entries].type = cpu_to_le32(type);
897 e820_entries++;
4c5b10b7 898
7d67110f 899 return e820_entries;
4c5b10b7
JS		 900}
901
7bf8ef19
GS		 902int e820_get_num_entries(void)
903{
904 return e820_entries;
905}
906
907bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length)
908{
909 if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) {
910 *address = le64_to_cpu(e820_table[idx].address);
911 *length = le64_to_cpu(e820_table[idx].length);
912 return true;
913 }
914 return false;
915}
916
54a40293
EH		 917/* Enables contiguous-apic-ID mode, for compatibility */
918static bool compat_apic_id_mode;
919
920void enable_compat_apic_id_mode(void)
921{
922 compat_apic_id_mode = true;
923}
924
925/* Calculates initial APIC ID for a specific CPU index
926 *
927 * Currently we need to be able to calculate the APIC ID from the CPU index
928 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
929 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
930 * all CPUs up to max_cpus.
931 */
932static uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
933{
934 uint32_t correct_id;
935 static bool warned;
936
937 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
938 if (compat_apic_id_mode) {
b1c12027 939 if (cpu_index != correct_id && !warned && !qtest_enabled()) {
54a40293
EH		 940 error_report("APIC IDs set in compatibility mode, "
941 "CPU topology won't match the configuration");
942 warned = true;
943 }
944 return cpu_index;
945 } else {
946 return correct_id;
947 }
948}
949
f2098f48 950static void pc_build_smbios(PCMachineState *pcms)
80cabfad 951{
c97294ec
GS		 952 uint8_t *smbios_tables, *smbios_anchor;
953 size_t smbios_tables_len, smbios_anchor_len;
89cc4a27
WH		 954 struct smbios_phys_mem_area *mem_array;
955 unsigned i, array_count;
38690a1c
IM		 956 MachineState *ms = MACHINE(pcms);
957 X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu);
f2098f48
IM		 958
959 /* tell smbios about cpuid version and features */
960 smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]);
5fd0a9d4
WH		 961
962 smbios_tables = smbios_get_table_legacy(&smbios_tables_len);
963 if (smbios_tables) {
f2098f48 964 fw_cfg_add_bytes(pcms->fw_cfg, FW_CFG_SMBIOS_ENTRIES,
5fd0a9d4
WH		 965 smbios_tables, smbios_tables_len);
966 }
967
89cc4a27
WH		 968 /* build the array of physical mem area from e820 table */
969 mem_array = g_malloc0(sizeof(*mem_array) * e820_get_num_entries());
970 for (i = 0, array_count = 0; i < e820_get_num_entries(); i++) {
971 uint64_t addr, len;
972
973 if (e820_get_entry(i, E820_RAM, &addr, &len)) {
974 mem_array[array_count].address = addr;
975 mem_array[array_count].length = len;
976 array_count++;
977 }
978 }
979 smbios_get_tables(mem_array, array_count,
980 &smbios_tables, &smbios_tables_len,
5fd0a9d4 981 &smbios_anchor, &smbios_anchor_len);
89cc4a27
WH		 982 g_free(mem_array);
983
5fd0a9d4 984 if (smbios_anchor) {
f2098f48 985 fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-tables",
5fd0a9d4 986 smbios_tables, smbios_tables_len);
f2098f48 987 fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-anchor",
5fd0a9d4
WH		 988 smbios_anchor, smbios_anchor_len);
989 }
990}
991
ebde2465 992static FWCfgState *bochs_bios_init(AddressSpace *as, PCMachineState *pcms)
5fd0a9d4
WH		 993{
994 FWCfgState *fw_cfg;
11c2fd3e 995 uint64_t *numa_fw_cfg;
ea265072
IM		 996 int i;
997 const CPUArchIdList *cpus;
998 MachineClass *mc = MACHINE_GET_CLASS(pcms);
3cce6243 999
305ae888 1000 fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, as);
e3cadac0 1001 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
c886fc4c 1002
1d934e89
EH		 1003 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86:
1004 *
a3abd0f2
IM		 1005 * For machine types prior to 1.8, SeaBIOS needs FW_CFG_MAX_CPUS for
1006 * building MPTable, ACPI MADT, ACPI CPU hotplug and ACPI SRAT table,
1007 * that tables are based on xAPIC ID and QEMU<->SeaBIOS interface
1008 * for CPU hotplug also uses APIC ID and not "CPU index".
1009 * This means that FW_CFG_MAX_CPUS is not the "maximum number of CPUs",
1010 * but the "limit to the APIC ID values SeaBIOS may see".
1d934e89 1011 *
a3abd0f2
IM		 1012 * So for compatibility reasons with old BIOSes we are stuck with
1013 * "etc/max-cpus" actually being apic_id_limit
1d934e89 1014 */
ebde2465 1015 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)pcms->apic_id_limit);
905fdcb5 1016 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
089da572
MA		 1017 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES,
1018 acpi_tables, acpi_tables_len);
9b5b76d4 1019 fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
b6f6e3d3 1020
089da572 1021 fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE,
7d67110f
GH		 1022 &e820_reserve, sizeof(e820_reserve));
1023 fw_cfg_add_file(fw_cfg, "etc/e820", e820_table,
1024 sizeof(struct e820_entry) * e820_entries);
11c2fd3e 1025
089da572 1026 fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg));
11c2fd3e
AL		 1027 /* allocate memory for the NUMA channel: one (64bit) word for the number
1028 * of nodes, one word for each VCPU->node and one word for each node to
1029 * hold the amount of memory.
1030 */
ebde2465 1031 numa_fw_cfg = g_new0(uint64_t, 1 + pcms->apic_id_limit + nb_numa_nodes);
11c2fd3e 1032 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
ea265072
IM		 1033 cpus = mc->possible_cpu_arch_ids(MACHINE(pcms));
1034 for (i = 0; i < cpus->len; i++) {
1035 unsigned int apic_id = cpus->cpus[i].arch_id;
ebde2465 1036 assert(apic_id < pcms->apic_id_limit);
d41f3e75 1037 numa_fw_cfg[apic_id + 1] = cpu_to_le64(cpus->cpus[i].props.node_id);
11c2fd3e
AL		 1038 }
1039 for (i = 0; i < nb_numa_nodes; i++) {
ebde2465
IM		 1040 numa_fw_cfg[pcms->apic_id_limit + 1 + i] =
1041 cpu_to_le64(numa_info[i].node_mem);
11c2fd3e 1042 }
089da572 1043 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg,
ebde2465 1044 (1 + pcms->apic_id_limit + nb_numa_nodes) *
1d934e89 1045 sizeof(*numa_fw_cfg));
bf483392
AG		 1046
1047 return fw_cfg;
80cabfad
FB		 1048}
1049
642a4f96
TS		 1050static long get_file_size(FILE *f)
1051{
1052 long where, size;
1053
1054 /* XXX: on Unix systems, using fstat() probably makes more sense */
1055
1056 where = ftell(f);
1057 fseek(f, 0, SEEK_END);
1058 size = ftell(f);
1059 fseek(f, where, SEEK_SET);
1060
1061 return size;
1062}
1063
3cbeb524
AB		 1064struct setup_data {
1065 uint64_t next;
1066 uint32_t type;
1067 uint32_t len;
1068 uint8_t data[0];
1069} __attribute__((packed));
1070
ab969087
LM		 1071
1072/*
1073 * The entry point into the kernel for PVH boot is different from
1074 * the native entry point. The PVH entry is defined by the x86/HVM
1075 * direct boot ABI and is available in an ELFNOTE in the kernel binary.
1076 *
1077 * This function is passed to load_elf() when it is called from
1078 * load_elfboot() which then additionally checks for an ELF Note of
1079 * type XEN_ELFNOTE_PHYS32_ENTRY and passes it to this function to
1080 * parse the PVH entry address from the ELF Note.
1081 *
1082 * Due to trickery in elf_opts.h, load_elf() is actually available as
1083 * load_elf32() or load_elf64() and this routine needs to be able
1084 * to deal with being called as 32 or 64 bit.
1085 *
1086 * The address of the PVH entry point is saved to the 'pvh_start_addr'
1087 * global variable. (although the entry point is 32-bit, the kernel
1088 * binary can be either 32-bit or 64-bit).
1089 */
1090static uint64_t read_pvh_start_addr(void *arg1, void *arg2, bool is64)
1091{
1092 size_t *elf_note_data_addr;
1093
1094 /* Check if ELF Note header passed in is valid */
1095 if (arg1 == NULL) {
1096 return 0;
1097 }
1098
1099 if (is64) {
1100 struct elf64_note *nhdr64 = (struct elf64_note *)arg1;
1101 uint64_t nhdr_size64 = sizeof(struct elf64_note);
1102 uint64_t phdr_align = *(uint64_t *)arg2;
1103 uint64_t nhdr_namesz = nhdr64->n_namesz;
1104
1105 elf_note_data_addr =
1106 ((void *)nhdr64) + nhdr_size64 +
1107 QEMU_ALIGN_UP(nhdr_namesz, phdr_align);
1108 } else {
1109 struct elf32_note *nhdr32 = (struct elf32_note *)arg1;
1110 uint32_t nhdr_size32 = sizeof(struct elf32_note);
1111 uint32_t phdr_align = *(uint32_t *)arg2;
1112 uint32_t nhdr_namesz = nhdr32->n_namesz;
1113
1114 elf_note_data_addr =
1115 ((void *)nhdr32) + nhdr_size32 +
1116 QEMU_ALIGN_UP(nhdr_namesz, phdr_align);
1117 }
1118
1119 pvh_start_addr = *elf_note_data_addr;
1120
1121 return pvh_start_addr;
1122}
1123
1124static bool load_elfboot(const char *kernel_filename,
1125 int kernel_file_size,
1126 uint8_t *header,
1127 size_t pvh_xen_start_addr,
1128 FWCfgState *fw_cfg)
1129{
1130 uint32_t flags = 0;
1131 uint32_t mh_load_addr = 0;
1132 uint32_t elf_kernel_size = 0;
1133 uint64_t elf_entry;
1134 uint64_t elf_low, elf_high;
1135 int kernel_size;
1136
1137 if (ldl_p(header) != 0x464c457f) {
1138 return false; /* no elfboot */
1139 }
1140
1141 bool elf_is64 = header[EI_CLASS] == ELFCLASS64;
1142 flags = elf_is64 ?
1143 ((Elf64_Ehdr *)header)->e_flags : ((Elf32_Ehdr *)header)->e_flags;
1144
1145 if (flags & 0x00010004) { /* LOAD_ELF_HEADER_HAS_ADDR */
1146 error_report("elfboot unsupported flags = %x", flags);
1147 exit(1);
1148 }
1149
1150 uint64_t elf_note_type = XEN_ELFNOTE_PHYS32_ENTRY;
1151 kernel_size = load_elf(kernel_filename, read_pvh_start_addr,
1152 NULL, &elf_note_type, &elf_entry,
1153 &elf_low, &elf_high, 0, I386_ELF_MACHINE,
1154 0, 0);
1155
1156 if (kernel_size < 0) {
1157 error_report("Error while loading elf kernel");
1158 exit(1);
1159 }
1160 mh_load_addr = elf_low;
1161 elf_kernel_size = elf_high - elf_low;
1162
1163 if (pvh_start_addr == 0) {
1164 error_report("Error loading uncompressed kernel without PVH ELF Note");
1165 exit(1);
1166 }
1167 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ENTRY, pvh_start_addr);
1168 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, mh_load_addr);
1169 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, elf_kernel_size);
1170
1171 return true;
1172}
1173
df1f79fd
EH		 1174static void load_linux(PCMachineState *pcms,
1175 FWCfgState *fw_cfg)
642a4f96
TS		 1176{
1177 uint16_t protocol;
f3839fda 1178 int setup_size, kernel_size, cmdline_size;
3cbeb524 1179 int dtb_size, setup_data_offset;
642a4f96 1180 uint32_t initrd_max;
c24323dd 1181 uint8_t header[8192], *setup, *kernel;
a8170e5e 1182 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
45a50b16 1183 FILE *f;
bf4e5d92 1184 char *vmode;
df1f79fd 1185 MachineState *machine = MACHINE(pcms);
cd4040ec 1186 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
3cbeb524 1187 struct setup_data *setup_data;
df1f79fd
EH		 1188 const char *kernel_filename = machine->kernel_filename;
1189 const char *initrd_filename = machine->initrd_filename;
3cbeb524 1190 const char *dtb_filename = machine->dtb;
df1f79fd 1191 const char *kernel_cmdline = machine->kernel_cmdline;
642a4f96
TS		 1192
1193 /* Align to 16 bytes as a paranoia measure */
1194 cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
1195
1196 /* load the kernel header */
1197 f = fopen(kernel_filename, "rb");
1198 if (!f || !(kernel_size = get_file_size(f)) ||
0f9d76e5
LG		 1199 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
1200 MIN(ARRAY_SIZE(header), kernel_size)) {
1201 fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
1202 kernel_filename, strerror(errno));
1203 exit(1);
642a4f96
TS		 1204 }
1205
1206 /* kernel protocol version */
bc4edd79 1207#if 0
642a4f96 1208 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
bc4edd79 1209#endif
0f9d76e5
LG		 1210 if (ldl_p(header+0x202) == 0x53726448) {
1211 protocol = lduw_p(header+0x206);
1212 } else {
5dc8ab36
SG		 1213 /*
1214 * This could be a multiboot kernel. If it is, let's stop treating it
1215 * like a Linux kernel.
1216 * Note: some multiboot images could be in the ELF format (the same of
1217 * PVH), so we try multiboot first since we check the multiboot magic
1218 * header before to load it.
1219 */
1220 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
1221 kernel_cmdline, kernel_size, header)) {
1222 return;
1223 }
ab969087
LM		 1224 /*
1225 * Check if the file is an uncompressed kernel file (ELF) and load it,
1226 * saving the PVH entry point used by the x86/HVM direct boot ABI.
1227 * If load_elfboot() is successful, populate the fw_cfg info.
1228 */
fda672b5
SG		 1229 if (pcmc->pvh_enabled &&
1230 load_elfboot(kernel_filename, kernel_size,
ab969087 1231 header, pvh_start_addr, fw_cfg)) {
ab969087
LM		 1232 fclose(f);
1233
1234 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
1235 strlen(kernel_cmdline) + 1);
1236 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
1237
ab969087
LM		 1238 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, sizeof(header));
1239 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA,
1240 header, sizeof(header));
1241
c5bf7847
SG		 1242 /* load initrd */
1243 if (initrd_filename) {
1244 gsize initrd_size;
1245 gchar *initrd_data;
1246 GError *gerr = NULL;
1247
1248 if (!g_file_get_contents(initrd_filename, &initrd_data,
1249 &initrd_size, &gerr)) {
1250 fprintf(stderr, "qemu: error reading initrd %s: %s\n",
1251 initrd_filename, gerr->message);
1252 exit(1);
1253 }
1254
1255 initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1;
1256 if (initrd_size >= initrd_max) {
1257 fprintf(stderr, "qemu: initrd is too large, cannot support."
1258 "(max: %"PRIu32", need %"PRId64")\n",
1259 initrd_max, (uint64_t)initrd_size);
1260 exit(1);
1261 }
1262
1263 initrd_addr = (initrd_max - initrd_size) & ~4095;
1264
1265 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
1266 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
1267 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data,
1268 initrd_size);
1269 }
1270
1fb0d709
SG		 1271 option_rom[nb_option_roms].bootindex = 0;
1272 option_rom[nb_option_roms].name = "pvh.bin";
1273 nb_option_roms++;
1274
ab969087
LM		 1275 return;
1276 }
0f9d76e5 1277 protocol = 0;
f16408df 1278 }
642a4f96
TS		 1279
1280 if (protocol < 0x200 || !(header[0x211] & 0x01)) {
0f9d76e5
LG		 1281 /* Low kernel */
1282 real_addr = 0x90000;
1283 cmdline_addr = 0x9a000 - cmdline_size;
1284 prot_addr = 0x10000;
642a4f96 1285 } else if (protocol < 0x202) {
0f9d76e5
LG		 1286 /* High but ancient kernel */
1287 real_addr = 0x90000;
1288 cmdline_addr = 0x9a000 - cmdline_size;
1289 prot_addr = 0x100000;
642a4f96 1290 } else {
0f9d76e5
LG		 1291 /* High and recent kernel */
1292 real_addr = 0x10000;
1293 cmdline_addr = 0x20000;
1294 prot_addr = 0x100000;
642a4f96
TS		 1295 }
1296
bc4edd79 1297#if 0
642a4f96 1298 fprintf(stderr,
0f9d76e5
LG		 1299 "qemu: real_addr = 0x" TARGET_FMT_plx "\n"
1300 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n"
1301 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n",
1302 real_addr,
1303 cmdline_addr,
1304 prot_addr);
bc4edd79 1305#endif
642a4f96
TS		 1306
1307 /* highest address for loading the initrd */
aab50e53
LZ		 1308 if (protocol >= 0x20c &&
1309 lduw_p(header+0x236) & XLF_CAN_BE_LOADED_ABOVE_4G) {
1310 /*
1311 * Linux has supported initrd up to 4 GB for a very long time (2007,
1312 * long before XLF_CAN_BE_LOADED_ABOVE_4G which was added in 2013),
1313 * though it only sets initrd_max to 2 GB to "work around bootloader
1314 * bugs". Luckily, QEMU firmware(which does something like bootloader)
1315 * has supported this.
1316 *
1317 * It's believed that if XLF_CAN_BE_LOADED_ABOVE_4G is set, initrd can
1318 * be loaded into any address.
1319 *
1320 * In addition, initrd_max is uint32_t simply because QEMU doesn't
1321 * support the 64-bit boot protocol (specifically the ext_ramdisk_image
1322 * field).
1323 *
1324 * Therefore here just limit initrd_max to UINT32_MAX simply as well.
1325 */
1326 initrd_max = UINT32_MAX;
1327 } else if (protocol >= 0x203) {
0f9d76e5
LG		 1328 initrd_max = ldl_p(header+0x22c);
1329 } else {
1330 initrd_max = 0x37ffffff;
1331 }
642a4f96 1332
cd4040ec
EH		 1333 if (initrd_max >= pcms->below_4g_mem_size - pcmc->acpi_data_size) {
1334 initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1;
927766c7 1335 }
642a4f96 1336
57a46d05
AG		 1337 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
1338 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
96f80586 1339 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
642a4f96
TS		 1340
1341 if (protocol >= 0x202) {
0f9d76e5 1342 stl_p(header+0x228, cmdline_addr);
642a4f96 1343 } else {
0f9d76e5
LG		 1344 stw_p(header+0x20, 0xA33F);
1345 stw_p(header+0x22, cmdline_addr-real_addr);
642a4f96
TS		 1346 }
1347
bf4e5d92
PT		 1348 /* handle vga= parameter */
1349 vmode = strstr(kernel_cmdline, "vga=");
1350 if (vmode) {
1351 unsigned int video_mode;
1352 /* skip "vga=" */
1353 vmode += 4;
1354 if (!strncmp(vmode, "normal", 6)) {
1355 video_mode = 0xffff;
1356 } else if (!strncmp(vmode, "ext", 3)) {
1357 video_mode = 0xfffe;
1358 } else if (!strncmp(vmode, "ask", 3)) {
1359 video_mode = 0xfffd;
1360 } else {
1361 video_mode = strtol(vmode, NULL, 0);
1362 }
1363 stw_p(header+0x1fa, video_mode);
1364 }
1365
642a4f96 1366 /* loader type */
5cbdb3a3 1367 /* High nybble = B reserved for QEMU; low nybble is revision number.
642a4f96
TS		 1368 If this code is substantially changed, you may want to consider
1369 incrementing the revision. */
0f9d76e5
LG		 1370 if (protocol >= 0x200) {
1371 header[0x210] = 0xB0;
1372 }
642a4f96
TS		 1373 /* heap */
1374 if (protocol >= 0x201) {
0f9d76e5
LG		 1375 header[0x211] |= 0x80; /* CAN_USE_HEAP */
1376 stw_p(header+0x224, cmdline_addr-real_addr-0x200);
642a4f96
TS		 1377 }
1378
1379 /* load initrd */
1380 if (initrd_filename) {
c24323dd
PM		 1381 gsize initrd_size;
1382 gchar *initrd_data;
1383 GError *gerr = NULL;
1384
0f9d76e5
LG		 1385 if (protocol < 0x200) {
1386 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
1387 exit(1);
1388 }
642a4f96 1389
c24323dd
PM		 1390 if (!g_file_get_contents(initrd_filename, &initrd_data,
1391 &initrd_size, &gerr)) {
7454e51d 1392 fprintf(stderr, "qemu: error reading initrd %s: %s\n",
c24323dd 1393 initrd_filename, gerr->message);
d6fa4b77 1394 exit(1);
c24323dd
PM		 1395 }
1396 if (initrd_size >= initrd_max) {
f3839fda 1397 fprintf(stderr, "qemu: initrd is too large, cannot support."
c24323dd
PM		 1398 "(max: %"PRIu32", need %"PRId64")\n",
1399 initrd_max, (uint64_t)initrd_size);
f3839fda 1400 exit(1);
d6fa4b77
MK		 1401 }
1402
45a50b16 1403 initrd_addr = (initrd_max-initrd_size) & ~4095;
57a46d05 1404
57a46d05
AG		 1405 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
1406 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
1407 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
642a4f96 1408
0f9d76e5
LG		 1409 stl_p(header+0x218, initrd_addr);
1410 stl_p(header+0x21c, initrd_size);
642a4f96
TS		 1411 }
1412
45a50b16 1413 /* load kernel and setup */
642a4f96 1414 setup_size = header[0x1f1];
0f9d76e5
LG		 1415 if (setup_size == 0) {
1416 setup_size = 4;
1417 }
642a4f96 1418 setup_size = (setup_size+1)*512;
ec5fd402
PB		 1419 if (setup_size > kernel_size) {
1420 fprintf(stderr, "qemu: invalid kernel header\n");
1421 exit(1);
1422 }
45a50b16 1423 kernel_size -= setup_size;
642a4f96 1424
7267c094
AL		 1425 setup = g_malloc(setup_size);
1426 kernel = g_malloc(kernel_size);
45a50b16 1427 fseek(f, 0, SEEK_SET);
5a41ecc5
KS		 1428 if (fread(setup, 1, setup_size, f) != setup_size) {
1429 fprintf(stderr, "fread() failed\n");
1430 exit(1);
1431 }
1432 if (fread(kernel, 1, kernel_size, f) != kernel_size) {
1433 fprintf(stderr, "fread() failed\n");
1434 exit(1);
1435 }
642a4f96 1436 fclose(f);
3cbeb524
AB		 1437
1438 /* append dtb to kernel */
1439 if (dtb_filename) {
1440 if (protocol < 0x209) {
1441 fprintf(stderr, "qemu: Linux kernel too old to load a dtb\n");
1442 exit(1);
1443 }
1444
1445 dtb_size = get_image_size(dtb_filename);
1446 if (dtb_size <= 0) {
1447 fprintf(stderr, "qemu: error reading dtb %s: %s\n",
1448 dtb_filename, strerror(errno));
1449 exit(1);
1450 }
1451
1452 setup_data_offset = QEMU_ALIGN_UP(kernel_size, 16);
1453 kernel_size = setup_data_offset + sizeof(struct setup_data) + dtb_size;
1454 kernel = g_realloc(kernel, kernel_size);
1455
1456 stq_p(header+0x250, prot_addr + setup_data_offset);
1457
1458 setup_data = (struct setup_data *)(kernel + setup_data_offset);
1459 setup_data->next = 0;
1460 setup_data->type = cpu_to_le32(SETUP_DTB);
1461 setup_data->len = cpu_to_le32(dtb_size);
1462
1463 load_image_size(dtb_filename, setup_data->data, dtb_size);
1464 }
1465
45a50b16 1466 memcpy(setup, header, MIN(sizeof(header), setup_size));
57a46d05
AG		 1467
1468 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
1469 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1470 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
1471
1472 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
1473 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
1474 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
1475
98e753a6
IM		 1476 option_rom[nb_option_roms].bootindex = 0;
1477 option_rom[nb_option_roms].name = "linuxboot.bin";
1478 if (pcmc->linuxboot_dma_enabled && fw_cfg_dma_enabled(fw_cfg)) {
b2a575a1 1479 option_rom[nb_option_roms].name = "linuxboot_dma.bin";
b2a575a1 1480 }
57a46d05 1481 nb_option_roms++;
642a4f96
TS		 1482}
1483
b41a2cd1
FB		 1484#define NE2000_NB_MAX 6
1485
675d6f82
BS		 1486static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
1487 0x280, 0x380 };
1488static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
b41a2cd1 1489
48a18b3c 1490void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
a41b2ff2
PB		 1491{
1492 static int nb_ne2k = 0;
1493
1494 if (nb_ne2k == NE2000_NB_MAX)
1495 return;
48a18b3c 1496 isa_ne2000_init(bus, ne2000_io[nb_ne2k],
9453c5bc 1497 ne2000_irq[nb_ne2k], nd);
a41b2ff2
PB		 1498 nb_ne2k++;
1499}
1500
92a16d7a 1501DeviceState *cpu_get_current_apic(void)
0e26b7b8 1502{
4917cf44
AF		 1503 if (current_cpu) {
1504 X86CPU *cpu = X86_CPU(current_cpu);
02e51483 1505 return cpu->apic_state;
0e26b7b8
BS		 1506 } else {
1507 return NULL;
1508 }
1509}
1510
845773ab 1511void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
53b67b30 1512{
c3affe56 1513 X86CPU *cpu = opaque;
53b67b30
BS		 1514
1515 if (level) {
c3affe56 1516 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
53b67b30
BS		 1517 }
1518}
1519
074281d6 1520static void pc_new_cpu(const char *typename, int64_t apic_id, Error **errp)
31050930 1521{
074281d6 1522 Object *cpu = NULL;
31050930
IM		 1523 Error *local_err = NULL;
1524
074281d6 1525 cpu = object_new(typename);
31050930 1526
c7b4efb4 1527 object_property_set_uint(cpu, apic_id, "apic-id", &local_err);
074281d6 1528 object_property_set_bool(cpu, true, "realized", &local_err);
31050930 1529
074281d6 1530 object_unref(cpu);
021c9d25 1531 error_propagate(errp, local_err);
31050930
IM		 1532}
1533
c649983b
IM		 1534void pc_hot_add_cpu(const int64_t id, Error **errp)
1535{
38690a1c 1536 MachineState *ms = MACHINE(qdev_get_machine());
c649983b 1537 int64_t apic_id = x86_cpu_apic_id_from_index(id);
0e3bd562 1538 Error *local_err = NULL;
c649983b 1539
8de433cb
IM		 1540 if (id < 0) {
1541 error_setg(errp, "Invalid CPU id: %" PRIi64, id);
1542 return;
1543 }
1544
5ff020b7
EH		 1545 if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) {
1546 error_setg(errp, "Unable to add CPU: %" PRIi64
1547 ", resulting APIC ID (%" PRIi64 ") is too large",
1548 id, apic_id);
1549 return;
1550 }
1551
311ca98d 1552 pc_new_cpu(ms->cpu_type, apic_id, &local_err);
0e3bd562
AF		 1553 if (local_err) {
1554 error_propagate(errp, local_err);
1555 return;
1556 }
c649983b
IM		 1557}
1558
4884b7bf 1559void pc_cpus_init(PCMachineState *pcms)
70166477
IY		 1560{
1561 int i;
c96a1c0b 1562 const CPUArchIdList *possible_cpus;
311ca98d 1563 MachineState *ms = MACHINE(pcms);
c96a1c0b 1564 MachineClass *mc = MACHINE_GET_CLASS(pcms);
70166477 1565
ebde2465
IM		 1566 /* Calculates the limit to CPU APIC ID values
1567 *
1568 * Limit for the APIC ID value, so that all
1569 * CPU APIC IDs are < pcms->apic_id_limit.
1570 *
1571 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init().
1572 */
1573 pcms->apic_id_limit = x86_cpu_apic_id_from_index(max_cpus - 1) + 1;
311ca98d 1574 possible_cpus = mc->possible_cpu_arch_ids(ms);
c96a1c0b 1575 for (i = 0; i < smp_cpus; i++) {
d342eb76
IM		 1576 pc_new_cpu(possible_cpus->cpus[i].type, possible_cpus->cpus[i].arch_id,
1577 &error_fatal);
70166477
IY		 1578 }
1579}
1580
217f1b4a
HZ		 1581static void pc_build_feature_control_file(PCMachineState *pcms)
1582{
38690a1c
IM		 1583 MachineState *ms = MACHINE(pcms);
1584 X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu);
217f1b4a
HZ		 1585 CPUX86State *env = &cpu->env;
1586 uint32_t unused, ecx, edx;
1587 uint64_t feature_control_bits = 0;
1588 uint64_t *val;
1589
1590 cpu_x86_cpuid(env, 1, 0, &unused, &unused, &ecx, &edx);
1591 if (ecx & CPUID_EXT_VMX) {
1592 feature_control_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1593 }
1594
1595 if ((edx & (CPUID_EXT2_MCE | CPUID_EXT2_MCA)) ==
1596 (CPUID_EXT2_MCE | CPUID_EXT2_MCA) &&
1597 (env->mcg_cap & MCG_LMCE_P)) {
1598 feature_control_bits |= FEATURE_CONTROL_LMCE;
1599 }
1600
1601 if (!feature_control_bits) {
1602 return;
1603 }
1604
1605 val = g_malloc(sizeof(*val));
1606 *val = cpu_to_le64(feature_control_bits | FEATURE_CONTROL_LOCKED);
1607 fw_cfg_add_file(pcms->fw_cfg, "etc/msr_feature_control", val, sizeof(*val));
1608}
1609
e3cadac0
IM		 1610static void rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count)
1611{
1612 if (cpus_count > 0xff) {
1613 /* If the number of CPUs can't be represented in 8 bits, the
1614 * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just
1615 * to make old BIOSes fail more predictably.
1616 */
1617 rtc_set_memory(rtc, 0x5f, 0);
1618 } else {
1619 rtc_set_memory(rtc, 0x5f, cpus_count - 1);
1620 }
1621}
1622
3459a625 1623static
9ebeed0c 1624void pc_machine_done(Notifier *notifier, void *data)
3459a625 1625{
9ebeed0c
EH		 1626 PCMachineState *pcms = container_of(notifier,
1627 PCMachineState, machine_done);
1628 PCIBus *bus = pcms->bus;
2118196b 1629
ba157b69 1630 /* set the number of CPUs */
e3cadac0 1631 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus);
ba157b69 1632
2118196b
MA		 1633 if (bus) {
1634 int extra_hosts = 0;
1635
1636 QLIST_FOREACH(bus, &bus->child, sibling) {
1637 /* look for expander root buses */
1638 if (pci_bus_is_root(bus)) {
1639 extra_hosts++;
1640 }
1641 }
f264d360 1642 if (extra_hosts && pcms->fw_cfg) {
2118196b
MA		 1643 uint64_t *val = g_malloc(sizeof(*val));
1644 *val = cpu_to_le64(extra_hosts);
f264d360 1645 fw_cfg_add_file(pcms->fw_cfg,
2118196b
MA		 1646 "etc/extra-pci-roots", val, sizeof(*val));
1647 }
1648 }
1649
bb292f5a 1650 acpi_setup();
6d42eefa 1651 if (pcms->fw_cfg) {
f2098f48 1652 pc_build_smbios(pcms);
217f1b4a 1653 pc_build_feature_control_file(pcms);
e3cadac0
IM		 1654 /* update FW_CFG_NB_CPUS to account for -device added CPUs */
1655 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
6d42eefa 1656 }
60c5e104 1657
1a26f466 1658 if (pcms->apic_id_limit > 255 && !xen_enabled()) {
60c5e104
IM		 1659 IntelIOMMUState *iommu = INTEL_IOMMU_DEVICE(x86_iommu_get_default());
1660
a924b3d8 1661 if (!iommu || !x86_iommu_ir_supported(X86_IOMMU_DEVICE(iommu)) ||
60c5e104
IM		 1662 iommu->intr_eim != ON_OFF_AUTO_ON) {
1663 error_report("current -smp configuration requires "
1664 "Extended Interrupt Mode enabled. "
1665 "You can add an IOMMU using: "
1666 "-device intel-iommu,intremap=on,eim=on");
1667 exit(EXIT_FAILURE);
1668 }
1669 }
3459a625
MT		 1670}
1671
e4e8ba04 1672void pc_guest_info_init(PCMachineState *pcms)
3459a625 1673{
1f3aba37 1674 int i;
b20c9bd5 1675
dd4c2f01
EH		 1676 pcms->apic_xrupt_override = kvm_allows_irq0_override();
1677 pcms->numa_nodes = nb_numa_nodes;
1678 pcms->node_mem = g_malloc0(pcms->numa_nodes *
1679 sizeof *pcms->node_mem);
8c85901e 1680 for (i = 0; i < nb_numa_nodes; i++) {
dd4c2f01 1681 pcms->node_mem[i] = numa_info[i].node_mem;
8c85901e
WG		 1682 }
1683
9ebeed0c
EH		 1684 pcms->machine_done.notify = pc_machine_done;
1685 qemu_add_machine_init_done_notifier(&pcms->machine_done);
3459a625
MT		 1686}
1687
83d08f26
MT		 1688/* setup pci memory address space mapping into system address space */
1689void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
1690 MemoryRegion *pci_address_space)
39848901 1691{
83d08f26
MT		 1692 /* Set to lower priority than RAM */
1693 memory_region_add_subregion_overlap(system_memory, 0x0,
1694 pci_address_space, -1);
39848901
IM		 1695}
1696
7bc35e0f 1697void xen_load_linux(PCMachineState *pcms)
b33a5bbf
CL		 1698{
1699 int i;
1700 FWCfgState *fw_cfg;
1701
df1f79fd 1702 assert(MACHINE(pcms)->kernel_filename != NULL);
b33a5bbf 1703
305ae888 1704 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE);
e3cadac0 1705 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
b33a5bbf
CL		 1706 rom_set_fw(fw_cfg);
1707
df1f79fd 1708 load_linux(pcms, fw_cfg);
b33a5bbf
CL		 1709 for (i = 0; i < nb_option_roms; i++) {
1710 assert(!strcmp(option_rom[i].name, "linuxboot.bin") ||
b2a575a1 1711 !strcmp(option_rom[i].name, "linuxboot_dma.bin") ||
1fb0d709 1712 !strcmp(option_rom[i].name, "pvh.bin") ||
b33a5bbf
CL		 1713 !strcmp(option_rom[i].name, "multiboot.bin"));
1714 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1715 }
f264d360 1716 pcms->fw_cfg = fw_cfg;
b33a5bbf
CL		 1717}
1718
5934e216
EH		 1719void pc_memory_init(PCMachineState *pcms,
1720 MemoryRegion *system_memory,
1721 MemoryRegion *rom_memory,
1722 MemoryRegion **ram_memory)
80cabfad 1723{
cbc5b5f3
JJ		 1724 int linux_boot, i;
1725 MemoryRegion *ram, *option_rom_mr;
00cb2a99 1726 MemoryRegion *ram_below_4g, *ram_above_4g;
a88b362c 1727 FWCfgState *fw_cfg;
62b160c0 1728 MachineState *machine = MACHINE(pcms);
16a9e8a5 1729 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
d592d303 1730
c8d163bc
EH		 1731 assert(machine->ram_size == pcms->below_4g_mem_size +
1732 pcms->above_4g_mem_size);
9521d42b
PB		 1733
1734 linux_boot = (machine->kernel_filename != NULL);
80cabfad 1735
00cb2a99 1736 /* Allocate RAM. We allocate it as a single memory region and use
66a0a2cb 1737 * aliases to address portions of it, mostly for backwards compatibility
00cb2a99
AK		 1738 * with older qemus that used qemu_ram_alloc().
1739 */
7267c094 1740 ram = g_malloc(sizeof(*ram));
9521d42b
PB		 1741 memory_region_allocate_system_memory(ram, NULL, "pc.ram",
1742 machine->ram_size);
ae0a5466 1743 *ram_memory = ram;
7267c094 1744 ram_below_4g = g_malloc(sizeof(*ram_below_4g));
2c9b15ca 1745 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram,
c8d163bc 1746 0, pcms->below_4g_mem_size);
00cb2a99 1747 memory_region_add_subregion(system_memory, 0, ram_below_4g);
c8d163bc
EH		 1748 e820_add_entry(0, pcms->below_4g_mem_size, E820_RAM);
1749 if (pcms->above_4g_mem_size > 0) {
7267c094 1750 ram_above_4g = g_malloc(sizeof(*ram_above_4g));
2c9b15ca 1751 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram,
c8d163bc
EH		 1752 pcms->below_4g_mem_size,
1753 pcms->above_4g_mem_size);
00cb2a99
AK		 1754 memory_region_add_subregion(system_memory, 0x100000000ULL,
1755 ram_above_4g);
c8d163bc 1756 e820_add_entry(0x100000000ULL, pcms->above_4g_mem_size, E820_RAM);
bbe80adf 1757 }
82b36dc3 1758
bb292f5a 1759 if (!pcmc->has_reserved_memory &&
ca8336f3 1760 (machine->ram_slots ||
9521d42b 1761 (machine->maxram_size > machine->ram_size))) {
ca8336f3
IM		 1762 MachineClass *mc = MACHINE_GET_CLASS(machine);
1763
1764 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
1765 mc->name);
1766 exit(EXIT_FAILURE);
1767 }
1768
b0c14ec4
DH		 1769 /* always allocate the device memory information */
1770 machine->device_memory = g_malloc0(sizeof(*machine->device_memory));
1771
f2ffbe2b 1772 /* initialize device memory address space */
bb292f5a 1773 if (pcmc->has_reserved_memory &&
9521d42b 1774 (machine->ram_size < machine->maxram_size)) {
f2ffbe2b 1775 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size;
619d11e4 1776
a0cc8856
IM		 1777 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
1778 error_report("unsupported amount of memory slots: %"PRIu64,
1779 machine->ram_slots);
1780 exit(EXIT_FAILURE);
1781 }
1782
f2c38522
PK		 1783 if (QEMU_ALIGN_UP(machine->maxram_size,
1784 TARGET_PAGE_SIZE) != machine->maxram_size) {
1785 error_report("maximum memory size must by aligned to multiple of "
1786 "%d bytes", TARGET_PAGE_SIZE);
1787 exit(EXIT_FAILURE);
1788 }
1789
b0c14ec4 1790 machine->device_memory->base =
d471bf3e 1791 ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, 1 * GiB);
619d11e4 1792
16a9e8a5 1793 if (pcmc->enforce_aligned_dimm) {
f2ffbe2b 1794 /* size device region assuming 1G page max alignment per slot */
d471bf3e 1795 device_mem_size += (1 * GiB) * machine->ram_slots;
085f8e88
IM		 1796 }
1797
f2ffbe2b
DH		 1798 if ((machine->device_memory->base + device_mem_size) <
1799 device_mem_size) {
619d11e4
IM		 1800 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT,
1801 machine->maxram_size);
1802 exit(EXIT_FAILURE);
1803 }
1804
b0c14ec4 1805 memory_region_init(&machine->device_memory->mr, OBJECT(pcms),
f2ffbe2b 1806 "device-memory", device_mem_size);
b0c14ec4
DH		 1807 memory_region_add_subregion(system_memory, machine->device_memory->base,
1808 &machine->device_memory->mr);
619d11e4 1809 }
cbc5b5f3
JJ		 1810
1811 /* Initialize PC system firmware */
5e640a9e 1812 pc_system_firmware_init(pcms, rom_memory);
00cb2a99 1813
7267c094 1814 option_rom_mr = g_malloc(sizeof(*option_rom_mr));
98a99ce0 1815 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE,
f8ed85ac 1816 &error_fatal);
208fa0e4
IM		 1817 if (pcmc->pci_enabled) {
1818 memory_region_set_readonly(option_rom_mr, true);
1819 }
4463aee6 1820 memory_region_add_subregion_overlap(rom_memory,
00cb2a99
AK		 1821 PC_ROM_MIN_VGA,
1822 option_rom_mr,
1823 1);
f753ff16 1824
ebde2465 1825 fw_cfg = bochs_bios_init(&address_space_memory, pcms);
c886fc4c 1826
8832cb80 1827 rom_set_fw(fw_cfg);
1d108d97 1828
b0c14ec4 1829 if (pcmc->has_reserved_memory && machine->device_memory->base) {
de268e13 1830 uint64_t *val = g_malloc(sizeof(*val));
2f8b5008 1831 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
b0c14ec4 1832 uint64_t res_mem_end = machine->device_memory->base;
2f8b5008
IM		 1833
1834 if (!pcmc->broken_reserved_end) {
b0c14ec4 1835 res_mem_end += memory_region_size(&machine->device_memory->mr);
2f8b5008 1836 }
d471bf3e 1837 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB));
de268e13
IM		 1838 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
1839 }
1840
f753ff16 1841 if (linux_boot) {
df1f79fd 1842 load_linux(pcms, fw_cfg);
f753ff16
PB		 1843 }
1844
1845 for (i = 0; i < nb_option_roms; i++) {
2e55e842 1846 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
406c8df3 1847 }
f264d360 1848 pcms->fw_cfg = fw_cfg;
cb135f59
PX		 1849
1850 /* Init default IOAPIC address space */
1851 pcms->ioapic_as = &address_space_memory;
3d53f5c3
IY		 1852}
1853
9fa99d25
MA		 1854/*
1855 * The 64bit pci hole starts after "above 4G RAM" and
1856 * potentially the space reserved for memory hotplug.
1857 */
1858uint64_t pc_pci_hole64_start(void)
1859{
1860 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
1861 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
b0c14ec4 1862 MachineState *ms = MACHINE(pcms);
9fa99d25
MA		 1863 uint64_t hole64_start = 0;
1864
b0c14ec4
DH		 1865 if (pcmc->has_reserved_memory && ms->device_memory->base) {
1866 hole64_start = ms->device_memory->base;
9fa99d25 1867 if (!pcmc->broken_reserved_end) {
b0c14ec4 1868 hole64_start += memory_region_size(&ms->device_memory->mr);
9fa99d25
MA		 1869 }
1870 } else {
1871 hole64_start = 0x100000000ULL + pcms->above_4g_mem_size;
1872 }
1873
d471bf3e 1874 return ROUND_UP(hole64_start, 1 * GiB);
9fa99d25
MA		 1875}
1876
0b0cc076 1877qemu_irq pc_allocate_cpu_irq(void)
845773ab 1878{
0b0cc076 1879 return qemu_allocate_irq(pic_irq_request, NULL, 0);
845773ab
IY		 1880}
1881
48a18b3c 1882DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
765d7908 1883{
ad6d45fa
AL		 1884 DeviceState *dev = NULL;
1885
bab47d9a 1886 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA);
16094b75
AJ		 1887 if (pci_bus) {
1888 PCIDevice *pcidev = pci_vga_init(pci_bus);
1889 dev = pcidev ? &pcidev->qdev : NULL;
1890 } else if (isa_bus) {
1891 ISADevice *isadev = isa_vga_init(isa_bus);
4a17cc4f 1892 dev = isadev ? DEVICE(isadev) : NULL;
765d7908 1893 }
bab47d9a 1894 rom_reset_order_override();
ad6d45fa 1895 return dev;
765d7908
IY		 1896}
1897
258711c6
JG		 1898static const MemoryRegionOps ioport80_io_ops = {
1899 .write = ioport80_write,
c02e1eac 1900 .read = ioport80_read,
258711c6
JG		 1901 .endianness = DEVICE_NATIVE_ENDIAN,
1902 .impl = {
1903 .min_access_size = 1,
1904 .max_access_size = 1,
1905 },
1906};
1907
1908static const MemoryRegionOps ioportF0_io_ops = {
1909 .write = ioportF0_write,
c02e1eac 1910 .read = ioportF0_read,
258711c6
JG		 1911 .endianness = DEVICE_NATIVE_ENDIAN,
1912 .impl = {
1913 .min_access_size = 1,
1914 .max_access_size = 1,
1915 },
1916};
1917
ac64273c
PMD		 1918static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport)
1919{
1920 int i;
1921 DriveInfo *fd[MAX_FD];
1922 qemu_irq *a20_line;
1923 ISADevice *i8042, *port92, *vmmouse;
1924
def337ff 1925 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS);
ac64273c
PMD		 1926 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
1927
1928 for (i = 0; i < MAX_FD; i++) {
1929 fd[i] = drive_get(IF_FLOPPY, 0, i);
1930 create_fdctrl |= !!fd[i];
1931 }
1932 if (create_fdctrl) {
1933 fdctrl_init_isa(isa_bus, fd);
1934 }
1935
1936 i8042 = isa_create_simple(isa_bus, "i8042");
1937 if (!no_vmport) {
1938 vmport_init(isa_bus);
1939 vmmouse = isa_try_create(isa_bus, "vmmouse");
1940 } else {
1941 vmmouse = NULL;
1942 }
1943 if (vmmouse) {
1944 DeviceState *dev = DEVICE(vmmouse);
1945 qdev_prop_set_ptr(dev, "ps2_mouse", i8042);
1946 qdev_init_nofail(dev);
1947 }
1948 port92 = isa_create_simple(isa_bus, "port92");
1949
1950 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1951 i8042_setup_a20_line(i8042, a20_line[0]);
1952 port92_init(port92, a20_line[1]);
1953 g_free(a20_line);
1954}
1955
48a18b3c 1956void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
1611977c 1957 ISADevice **rtc_state,
fd53c87c 1958 bool create_fdctrl,
7a10ef51 1959 bool no_vmport,
feddd2fd 1960 bool has_pit,
3a87d009 1961 uint32_t hpet_irqs)
ffe513da
IY		 1962{
1963 int i;
ce967e2f
JK		 1964 DeviceState *hpet = NULL;
1965 int pit_isa_irq = 0;
1966 qemu_irq pit_alt_irq = NULL;
7d932dfd 1967 qemu_irq rtc_irq = NULL;
ac64273c 1968 ISADevice *pit = NULL;
258711c6
JG		 1969 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1970 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
ffe513da 1971
2c9b15ca 1972 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
258711c6 1973 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
ffe513da 1974
2c9b15ca 1975 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
258711c6 1976 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
ffe513da 1977
5d17c0d2
JK		 1978 /*
1979 * Check if an HPET shall be created.
1980 *
1981 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1982 * when the HPET wants to take over. Thus we have to disable the latter.
1983 */
1984 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
7a10ef51 1985 /* In order to set property, here not using sysbus_try_create_simple */
51116102 1986 hpet = qdev_try_create(NULL, TYPE_HPET);
dd703b99 1987 if (hpet) {
7a10ef51
LPF		 1988 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7
1989 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23,
1990 * IRQ8 and IRQ2.
1991 */
5d7fb0f2 1992 uint8_t compat = object_property_get_uint(OBJECT(hpet),
7a10ef51
LPF		 1993 HPET_INTCAP, NULL);
1994 if (!compat) {
1995 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
1996 }
1997 qdev_init_nofail(hpet);
1998 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
1999
b881fbe9 2000 for (i = 0; i < GSI_NUM_PINS; i++) {
1356b98d 2001 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
dd703b99 2002 }
ce967e2f
JK		 2003 pit_isa_irq = -1;
2004 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
2005 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
822557eb 2006 }
ffe513da 2007 }
6c646a11 2008 *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq);
7d932dfd
JK		 2009
2010 qemu_register_boot_set(pc_boot_set, *rtc_state);
2011
feddd2fd 2012 if (!xen_enabled() && has_pit) {
15eafc2e 2013 if (kvm_pit_in_kernel()) {
c2d8d311
SS		 2014 pit = kvm_pit_init(isa_bus, 0x40);
2015 } else {
acf695ec 2016 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
c2d8d311
SS		 2017 }
2018 if (hpet) {
2019 /* connect PIT to output control line of the HPET */
4a17cc4f 2020 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
c2d8d311
SS		 2021 }
2022 pcspk_init(isa_bus, pit);
ce967e2f 2023 }
ffe513da 2024
55f613ac 2025 i8257_dma_init(isa_bus, 0);
ffe513da 2026
ac64273c
PMD		 2027 /* Super I/O */
2028 pc_superio_init(isa_bus, create_fdctrl, no_vmport);
ffe513da
IY		 2029}
2030
4b9c264b 2031void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus)
9011a1a7
IY		 2032{
2033 int i;
2034
bab47d9a 2035 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC);
9011a1a7
IY		 2036 for (i = 0; i < nb_nics; i++) {
2037 NICInfo *nd = &nd_table[i];
4b9c264b 2038 const char *model = nd->model ? nd->model : pcmc->default_nic_model;
9011a1a7 2039
4b9c264b 2040 if (g_str_equal(model, "ne2k_isa")) {
9011a1a7
IY		 2041 pc_init_ne2k_isa(isa_bus, nd);
2042 } else {
4b9c264b 2043 pci_nic_init_nofail(nd, pci_bus, model, NULL);
9011a1a7
IY		 2044 }
2045 }
bab47d9a 2046 rom_reset_order_override();
9011a1a7
IY		 2047}
2048
a39e3564
JB		 2049void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name)
2050{
2051 DeviceState *dev;
2052 SysBusDevice *d;
2053 unsigned int i;
2054
15eafc2e 2055 if (kvm_ioapic_in_kernel()) {
34bec7a8 2056 dev = qdev_create(NULL, TYPE_KVM_IOAPIC);
a39e3564 2057 } else {
34bec7a8 2058 dev = qdev_create(NULL, TYPE_IOAPIC);
a39e3564
JB		 2059 }
2060 if (parent_name) {
2061 object_property_add_child(object_resolve_path(parent_name, NULL),
2062 "ioapic", OBJECT(dev), NULL);
2063 }
2064 qdev_init_nofail(dev);
1356b98d 2065 d = SYS_BUS_DEVICE(dev);
3a4a4697 2066 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS);
a39e3564
JB		 2067
2068 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
2069 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i);
2070 }
2071}
d5747cac 2072
d468115b
DH		 2073static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2074 Error **errp)
2075{
2076 const PCMachineState *pcms = PC_MACHINE(hotplug_dev);
b0e62443 2077 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
f6a0d06b 2078 const MachineState *ms = MACHINE(hotplug_dev);
d468115b 2079 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
b0e62443 2080 const uint64_t legacy_align = TARGET_PAGE_SIZE;
d468115b
DH		 2081
2082 /*
2083 * When -no-acpi is used with Q35 machine type, no ACPI is built,
2084 * but pcms->acpi_dev is still created. Check !acpi_enabled in
2085 * addition to cover this case.
2086 */
2087 if (!pcms->acpi_dev || !acpi_enabled) {
2088 error_setg(errp,
2089 "memory hotplug is not enabled: missing acpi device or acpi disabled");
2090 return;
2091 }
2092
9040e6df
WY		 2093 hotplug_handler_pre_plug(pcms->acpi_dev, dev, errp);
2094
f6a0d06b 2095 if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
d468115b
DH		 2096 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'");
2097 return;
2098 }
8f1ffe5b 2099
fd3416f5 2100 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev),
b0e62443 2101 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp);
d468115b
DH		 2102}
2103
bb6e2f7a
DH		 2104static void pc_memory_plug(HotplugHandler *hotplug_dev,
2105 DeviceState *dev, Error **errp)
95bee274
IM		 2106{
2107 Error *local_err = NULL;
2108 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
f6a0d06b 2109 MachineState *ms = MACHINE(hotplug_dev);
7f3cf2d6 2110 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
95bee274 2111
fd3416f5 2112 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms), &local_err);
43bbb49e 2113 if (local_err) {
b8865591
IM		 2114 goto out;
2115 }
2116
7f3cf2d6 2117 if (is_nvdimm) {
f6a0d06b 2118 nvdimm_plug(ms->nvdimms_state);
c7f8d0f3
XG		 2119 }
2120
473ac567 2121 hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort);
95bee274
IM		 2122out:
2123 error_propagate(errp, local_err);
2124}
2125
bb6e2f7a
DH		 2126static void pc_memory_unplug_request(HotplugHandler *hotplug_dev,
2127 DeviceState *dev, Error **errp)
64fec58e 2128{
64fec58e
TC		 2129 Error *local_err = NULL;
2130 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
2131
8cd91ace
HZ		 2132 /*
2133 * When -no-acpi is used with Q35 machine type, no ACPI is built,
2134 * but pcms->acpi_dev is still created. Check !acpi_enabled in
2135 * addition to cover this case.
2136 */
2137 if (!pcms->acpi_dev || !acpi_enabled) {
64fec58e 2138 error_setg(&local_err,
8cd91ace 2139 "memory hotplug is not enabled: missing acpi device or acpi disabled");
64fec58e
TC		 2140 goto out;
2141 }
2142
b097cc52
XG		 2143 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
2144 error_setg(&local_err,
2145 "nvdimm device hot unplug is not supported yet.");
2146 goto out;
2147 }
2148
473ac567
DH		 2149 hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev,
2150 &local_err);
64fec58e
TC		 2151out:
2152 error_propagate(errp, local_err);
2153}
2154
bb6e2f7a
DH		 2155static void pc_memory_unplug(HotplugHandler *hotplug_dev,
2156 DeviceState *dev, Error **errp)
f7d3e29d
TC		 2157{
2158 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
f7d3e29d
TC		 2159 Error *local_err = NULL;
2160
473ac567 2161 hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
f7d3e29d
TC		 2162 if (local_err) {
2163 goto out;
2164 }
2165
fd3416f5 2166 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms));
07578b0a 2167 object_property_set_bool(OBJECT(dev), false, "realized", NULL);
f7d3e29d
TC		 2168 out:
2169 error_propagate(errp, local_err);
2170}
2171
3811ef14
IM		 2172static int pc_apic_cmp(const void *a, const void *b)
2173{
2174 CPUArchId *apic_a = (CPUArchId *)a;
2175 CPUArchId *apic_b = (CPUArchId *)b;
2176
2177 return apic_a->arch_id - apic_b->arch_id;
2178}
2179
7baef5cf 2180/* returns pointer to CPUArchId descriptor that matches CPU's apic_id
38690a1c 2181 * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no
b12227af 2182 * entry corresponding to CPU's apic_id returns NULL.
7baef5cf 2183 */
1ea69c0e 2184static CPUArchId *pc_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
7baef5cf 2185{
7baef5cf
IM		 2186 CPUArchId apic_id, *found_cpu;
2187
1ea69c0e 2188 apic_id.arch_id = id;
38690a1c
IM		 2189 found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus,
2190 ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus),
7baef5cf
IM		 2191 pc_apic_cmp);
2192 if (found_cpu && idx) {
38690a1c 2193 *idx = found_cpu - ms->possible_cpus->cpus;
7baef5cf
IM		 2194 }
2195 return found_cpu;
2196}
2197
5279569e
GZ		 2198static void pc_cpu_plug(HotplugHandler *hotplug_dev,
2199 DeviceState *dev, Error **errp)
2200{
7baef5cf 2201 CPUArchId *found_cpu;
5279569e 2202 Error *local_err = NULL;
1ea69c0e 2203 X86CPU *cpu = X86_CPU(dev);
5279569e
GZ		 2204 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
2205
a44a49db 2206 if (pcms->acpi_dev) {
473ac567 2207 hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
a44a49db
IM		 2208 if (local_err) {
2209 goto out;
2210 }
5279569e
GZ		 2211 }
2212
e3cadac0
IM		 2213 /* increment the number of CPUs */
2214 pcms->boot_cpus++;
26ef65be 2215 if (pcms->rtc) {
e3cadac0 2216 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus);
26ef65be
IM		 2217 }
2218 if (pcms->fw_cfg) {
e3cadac0 2219 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
2d996150
GZ		 2220 }
2221
1ea69c0e 2222 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL);
8aba3842 2223 found_cpu->cpu = OBJECT(dev);
5279569e
GZ		 2224out:
2225 error_propagate(errp, local_err);
2226}
8872c25a
IM		 2227static void pc_cpu_unplug_request_cb(HotplugHandler *hotplug_dev,
2228 DeviceState *dev, Error **errp)
2229{
73360e27 2230 int idx = -1;
8872c25a 2231 Error *local_err = NULL;
1ea69c0e 2232 X86CPU *cpu = X86_CPU(dev);
8872c25a
IM		 2233 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
2234
75ba2ddb
IM		 2235 if (!pcms->acpi_dev) {
2236 error_setg(&local_err, "CPU hot unplug not supported without ACPI");
2237 goto out;
2238 }
2239
1ea69c0e 2240 pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);
73360e27
IM		 2241 assert(idx != -1);
2242 if (idx == 0) {
2243 error_setg(&local_err, "Boot CPU is unpluggable");
2244 goto out;
2245 }
2246
473ac567
DH		 2247 hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev,
2248 &local_err);
8872c25a
IM		 2249 if (local_err) {
2250 goto out;
2251 }
2252
2253 out:
2254 error_propagate(errp, local_err);
2255
2256}
2257
2258static void pc_cpu_unplug_cb(HotplugHandler *hotplug_dev,
2259 DeviceState *dev, Error **errp)
2260{
8fe6374e 2261 CPUArchId *found_cpu;
8872c25a 2262 Error *local_err = NULL;
1ea69c0e 2263 X86CPU *cpu = X86_CPU(dev);
8872c25a
IM		 2264 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
2265
473ac567 2266 hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
8872c25a
IM		 2267 if (local_err) {
2268 goto out;
2269 }
2270
1ea69c0e 2271 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL);
8fe6374e 2272 found_cpu->cpu = NULL;
07578b0a 2273 object_property_set_bool(OBJECT(dev), false, "realized", NULL);
8872c25a 2274
e3cadac0
IM		 2275 /* decrement the number of CPUs */
2276 pcms->boot_cpus--;
2277 /* Update the number of CPUs in CMOS */
2278 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus);
2279 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
8872c25a
IM		 2280 out:
2281 error_propagate(errp, local_err);
2282}
5279569e 2283
4ec60c76
IM		 2284static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
2285 DeviceState *dev, Error **errp)
2286{
2287 int idx;
a15d2728 2288 CPUState *cs;
e8f7b83e 2289 CPUArchId *cpu_slot;
d89c2b8b 2290 X86CPUTopoInfo topo;
4ec60c76 2291 X86CPU *cpu = X86_CPU(dev);
6970c5ff 2292 MachineState *ms = MACHINE(hotplug_dev);
4ec60c76 2293 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
4ec60c76 2294
6970c5ff
IM		 2295 if(!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) {
2296 error_setg(errp, "Invalid CPU type, expected cpu type: '%s'",
2297 ms->cpu_type);
2298 return;
2299 }
2300
e8f7b83e
IM		 2301 /* if APIC ID is not set, set it based on socket/core/thread properties */
2302 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
2303 int max_socket = (max_cpus - 1) / smp_threads / smp_cores;
2304
2305 if (cpu->socket_id < 0) {
2306 error_setg(errp, "CPU socket-id is not set");
2307 return;
2308 } else if (cpu->socket_id > max_socket) {
2309 error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u",
2310 cpu->socket_id, max_socket);
2311 return;
2312 }
2313 if (cpu->core_id < 0) {
2314 error_setg(errp, "CPU core-id is not set");
2315 return;
2316 } else if (cpu->core_id > (smp_cores - 1)) {
2317 error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u",
2318 cpu->core_id, smp_cores - 1);
2319 return;
2320 }
2321 if (cpu->thread_id < 0) {
2322 error_setg(errp, "CPU thread-id is not set");
2323 return;
2324 } else if (cpu->thread_id > (smp_threads - 1)) {
2325 error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u",
2326 cpu->thread_id, smp_threads - 1);
2327 return;
2328 }
2329
2330 topo.pkg_id = cpu->socket_id;
2331 topo.core_id = cpu->core_id;
2332 topo.smt_id = cpu->thread_id;
2333 cpu->apic_id = apicid_from_topo_ids(smp_cores, smp_threads, &topo);
2334 }
2335
1ea69c0e 2336 cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);
4ec60c76 2337 if (!cpu_slot) {
38690a1c
IM		 2338 MachineState *ms = MACHINE(pcms);
2339
e8f7b83e
IM		 2340 x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo);
2341 error_setg(errp, "Invalid CPU [socket: %u, core: %u, thread: %u] with"
2342 " APIC ID %" PRIu32 ", valid index range 0:%d",
2343 topo.pkg_id, topo.core_id, topo.smt_id, cpu->apic_id,
38690a1c 2344 ms->possible_cpus->len - 1);
4ec60c76
IM		 2345 return;
2346 }
2347
2348 if (cpu_slot->cpu) {
2349 error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists",
2350 idx, cpu->apic_id);
2351 return;
2352 }
d89c2b8b
IM		 2353
2354 /* if 'address' properties socket-id/core-id/thread-id are not set, set them
c5514d0e 2355 * so that machine_query_hotpluggable_cpus would show correct values
d89c2b8b
IM		 2356 */
2357 /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn()
2358 * once -smp refactoring is complete and there will be CPU private
2359 * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */
2360 x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo);
2361 if (cpu->socket_id != -1 && cpu->socket_id != topo.pkg_id) {
2362 error_setg(errp, "property socket-id: %u doesn't match set apic-id:"
2363 " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo.pkg_id);
2364 return;
2365 }
2366 cpu->socket_id = topo.pkg_id;
2367
2368 if (cpu->core_id != -1 && cpu->core_id != topo.core_id) {
2369 error_setg(errp, "property core-id: %u doesn't match set apic-id:"
2370 " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo.core_id);
2371 return;
2372 }
2373 cpu->core_id = topo.core_id;
2374
2375 if (cpu->thread_id != -1 && cpu->thread_id != topo.smt_id) {
2376 error_setg(errp, "property thread-id: %u doesn't match set apic-id:"
2377 " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, topo.smt_id);
2378 return;
2379 }
2380 cpu->thread_id = topo.smt_id;
a15d2728 2381
e9688fab
RK		 2382 if (cpu->hyperv_vpindex && !kvm_hv_vpindex_settable()) {
2383 error_setg(errp, "kernel doesn't allow setting HyperV VP_INDEX");
2384 return;
2385 }
2386
a15d2728
IM		 2387 cs = CPU(cpu);
2388 cs->cpu_index = idx;
93b2a8cb 2389
a0ceb640 2390 numa_cpu_pre_plug(cpu_slot, dev, errp);
4ec60c76
IM		 2391}
2392
2393static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
2394 DeviceState *dev, Error **errp)
2395{
d468115b
DH		 2396 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2397 pc_memory_pre_plug(hotplug_dev, dev, errp);
2398 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
4ec60c76
IM		 2399 pc_cpu_pre_plug(hotplug_dev, dev, errp);
2400 }
2401}
2402
95bee274
IM		 2403static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev,
2404 DeviceState *dev, Error **errp)
2405{
2406 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
bb6e2f7a 2407 pc_memory_plug(hotplug_dev, dev, errp);
5279569e
GZ		 2408 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2409 pc_cpu_plug(hotplug_dev, dev, errp);
95bee274
IM		 2410 }
2411}
2412
d9c5c5b8
TC		 2413static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
2414 DeviceState *dev, Error **errp)
2415{
64fec58e 2416 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
bb6e2f7a 2417 pc_memory_unplug_request(hotplug_dev, dev, errp);
8872c25a
IM		 2418 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2419 pc_cpu_unplug_request_cb(hotplug_dev, dev, errp);
64fec58e
TC		 2420 } else {
2421 error_setg(errp, "acpi: device unplug request for not supported device"
2422 " type: %s", object_get_typename(OBJECT(dev)));
2423 }
d9c5c5b8
TC		 2424}
2425
232391c1
TC		 2426static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
2427 DeviceState *dev, Error **errp)
2428{
f7d3e29d 2429 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
bb6e2f7a 2430 pc_memory_unplug(hotplug_dev, dev, errp);
8872c25a
IM		 2431 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2432 pc_cpu_unplug_cb(hotplug_dev, dev, errp);
f7d3e29d
TC		 2433 } else {
2434 error_setg(errp, "acpi: device unplug for not supported device"
2435 " type: %s", object_get_typename(OBJECT(dev)));
2436 }
232391c1
TC		 2437}
2438
285816d7 2439static HotplugHandler *pc_get_hotplug_handler(MachineState *machine,
95bee274
IM		 2440 DeviceState *dev)
2441{
5279569e
GZ		 2442 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
2443 object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
95bee274
IM		 2444 return HOTPLUG_HANDLER(machine);
2445 }
2446
38aefb57 2447 return NULL;
95bee274
IM		 2448}
2449
bf1e8939 2450static void
f2ffbe2b
DH		 2451pc_machine_get_device_memory_region_size(Object *obj, Visitor *v,
2452 const char *name, void *opaque,
2453 Error **errp)
bf1e8939 2454{
b0c14ec4
DH		 2455 MachineState *ms = MACHINE(obj);
2456 int64_t value = memory_region_size(&ms->device_memory->mr);
bf1e8939 2457
51e72bc1 2458 visit_type_int(v, name, &value, errp);
bf1e8939
IM		 2459}
2460
c87b1520 2461static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v,
d7bce999
EB		 2462 const char *name, void *opaque,
2463 Error **errp)
c87b1520
DS		 2464{
2465 PCMachineState *pcms = PC_MACHINE(obj);
2466 uint64_t value = pcms->max_ram_below_4g;
2467
51e72bc1 2468 visit_type_size(v, name, &value, errp);
c87b1520
DS		 2469}
2470
2471static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v,
d7bce999
EB		 2472 const char *name, void *opaque,
2473 Error **errp)
c87b1520
DS		 2474{
2475 PCMachineState *pcms = PC_MACHINE(obj);
2476 Error *error = NULL;
2477 uint64_t value;
2478
51e72bc1 2479 visit_type_size(v, name, &value, &error);
c87b1520
DS		 2480 if (error) {
2481 error_propagate(errp, error);
2482 return;
2483 }
d471bf3e 2484 if (value > 4 * GiB) {
455b0fde
EB		 2485 error_setg(&error,
2486 "Machine option 'max-ram-below-4g=%"PRIu64
2487 "' expects size less than or equal to 4G", value);
c87b1520
DS		 2488 error_propagate(errp, error);
2489 return;
2490 }
2491
d471bf3e 2492 if (value < 1 * MiB) {
9e5d2c52
AF		 2493 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary,"
2494 "BIOS may not work with less than 1MiB", value);
c87b1520
DS		 2495 }
2496
2497 pcms->max_ram_below_4g = value;
2498}
2499
d7bce999
EB		 2500static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name,
2501 void *opaque, Error **errp)
9b23cfb7
DDAG		 2502{
2503 PCMachineState *pcms = PC_MACHINE(obj);
d1048bef 2504 OnOffAuto vmport = pcms->vmport;
9b23cfb7 2505
51e72bc1 2506 visit_type_OnOffAuto(v, name, &vmport, errp);
9b23cfb7
DDAG		 2507}
2508
d7bce999
EB		 2509static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name,
2510 void *opaque, Error **errp)
9b23cfb7
DDAG		 2511{
2512 PCMachineState *pcms = PC_MACHINE(obj);
2513
51e72bc1 2514 visit_type_OnOffAuto(v, name, &pcms->vmport, errp);
9b23cfb7
DDAG		 2515}
2516
355023f2
PB		 2517bool pc_machine_is_smm_enabled(PCMachineState *pcms)
2518{
2519 bool smm_available = false;
2520
2521 if (pcms->smm == ON_OFF_AUTO_OFF) {
2522 return false;
2523 }
2524
2525 if (tcg_enabled() || qtest_enabled()) {
2526 smm_available = true;
2527 } else if (kvm_enabled()) {
2528 smm_available = kvm_has_smm();
2529 }
2530
2531 if (smm_available) {
2532 return true;
2533 }
2534
2535 if (pcms->smm == ON_OFF_AUTO_ON) {
2536 error_report("System Management Mode not supported by this hypervisor.");
2537 exit(1);
2538 }
2539 return false;
2540}
2541
d7bce999
EB		 2542static void pc_machine_get_smm(Object *obj, Visitor *v, const char *name,
2543 void *opaque, Error **errp)
355023f2
PB		 2544{
2545 PCMachineState *pcms = PC_MACHINE(obj);
2546 OnOffAuto smm = pcms->smm;
2547
51e72bc1 2548 visit_type_OnOffAuto(v, name, &smm, errp);
355023f2
PB		 2549}
2550
d7bce999
EB		 2551static void pc_machine_set_smm(Object *obj, Visitor *v, const char *name,
2552 void *opaque, Error **errp)
355023f2
PB		 2553{
2554 PCMachineState *pcms = PC_MACHINE(obj);
2555
51e72bc1 2556 visit_type_OnOffAuto(v, name, &pcms->smm, errp);
355023f2
PB		 2557}
2558
be232eb0
CP		 2559static bool pc_machine_get_smbus(Object *obj, Error **errp)
2560{
2561 PCMachineState *pcms = PC_MACHINE(obj);
2562
f5878b03 2563 return pcms->smbus_enabled;
be232eb0
CP		 2564}
2565
2566static void pc_machine_set_smbus(Object *obj, bool value, Error **errp)
2567{
2568 PCMachineState *pcms = PC_MACHINE(obj);
2569
f5878b03 2570 pcms->smbus_enabled = value;
be232eb0
CP		 2571}
2572
272f0428
CP		 2573static bool pc_machine_get_sata(Object *obj, Error **errp)
2574{
2575 PCMachineState *pcms = PC_MACHINE(obj);
2576
f5878b03 2577 return pcms->sata_enabled;
272f0428
CP		 2578}
2579
2580static void pc_machine_set_sata(Object *obj, bool value, Error **errp)
2581{
2582 PCMachineState *pcms = PC_MACHINE(obj);
2583
f5878b03 2584 pcms->sata_enabled = value;
272f0428
CP		 2585}
2586
feddd2fd
CP		 2587static bool pc_machine_get_pit(Object *obj, Error **errp)
2588{
2589 PCMachineState *pcms = PC_MACHINE(obj);
2590
f5878b03 2591 return pcms->pit_enabled;
feddd2fd
CP		 2592}
2593
2594static void pc_machine_set_pit(Object *obj, bool value, Error **errp)
2595{
2596 PCMachineState *pcms = PC_MACHINE(obj);
2597
f5878b03 2598 pcms->pit_enabled = value;
feddd2fd
CP		 2599}
2600
bf1e8939
IM		 2601static void pc_machine_initfn(Object *obj)
2602{
c87b1520
DS		 2603 PCMachineState *pcms = PC_MACHINE(obj);
2604
5ec7d098 2605 pcms->max_ram_below_4g = 0; /* use default */
355023f2 2606 pcms->smm = ON_OFF_AUTO_AUTO;
d1048bef 2607 pcms->vmport = ON_OFF_AUTO_AUTO;
021746c1
WL		 2608 /* acpi build is enabled by default if machine supports it */
2609 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build;
f5878b03
CM		 2610 pcms->smbus_enabled = true;
2611 pcms->sata_enabled = true;
2612 pcms->pit_enabled = true;
ebc29e1b
MA		 2613
2614 pc_system_flash_create(pcms);
bf1e8939
IM		 2615}
2616
ae50c55a
ZG		 2617static void pc_machine_reset(void)
2618{
2619 CPUState *cs;
2620 X86CPU *cpu;
2621
2622 qemu_devices_reset();
2623
2624 /* Reset APIC after devices have been reset to cancel
2625 * any changes that qemu_devices_reset() might have done.
2626 */
2627 CPU_FOREACH(cs) {
2628 cpu = X86_CPU(cs);
2629
2630 if (cpu->apic_state) {
2631 device_reset(cpu->apic_state);
2632 }
2633 }
2634}
2635
ea089eeb
IM		 2636static CpuInstanceProperties
2637pc_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
fb43b73b 2638{
ea089eeb
IM		 2639 MachineClass *mc = MACHINE_GET_CLASS(ms);
2640 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
2641
2642 assert(cpu_index < possible_cpus->len);
2643 return possible_cpus->cpus[cpu_index].props;
fb43b73b
IM		 2644}
2645
79e07936
IM		 2646static int64_t pc_get_default_cpu_node_id(const MachineState *ms, int idx)
2647{
2648 X86CPUTopoInfo topo;
2649
2650 assert(idx < ms->possible_cpus->len);
2651 x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id,
2652 smp_cores, smp_threads, &topo);
2653 return topo.pkg_id % nb_numa_nodes;
2654}
2655
c96a1c0b 2656static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms)
3811ef14 2657{
c96a1c0b
IM		 2658 int i;
2659
2660 if (ms->possible_cpus) {
2661 /*
2662 * make sure that max_cpus hasn't changed since the first use, i.e.
2663 * -smp hasn't been parsed after it
2664 */
2665 assert(ms->possible_cpus->len == max_cpus);
2666 return ms->possible_cpus;
2667 }
2668
2669 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
2670 sizeof(CPUArchId) * max_cpus);
2671 ms->possible_cpus->len = max_cpus;
2672 for (i = 0; i < ms->possible_cpus->len; i++) {
c67ae933
IM		 2673 X86CPUTopoInfo topo;
2674
d342eb76 2675 ms->possible_cpus->cpus[i].type = ms->cpu_type;
f2d672c2 2676 ms->possible_cpus->cpus[i].vcpus_count = 1;
c96a1c0b 2677 ms->possible_cpus->cpus[i].arch_id = x86_cpu_apic_id_from_index(i);
c67ae933
IM		 2678 x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id,
2679 smp_cores, smp_threads, &topo);
2680 ms->possible_cpus->cpus[i].props.has_socket_id = true;
2681 ms->possible_cpus->cpus[i].props.socket_id = topo.pkg_id;
2682 ms->possible_cpus->cpus[i].props.has_core_id = true;
2683 ms->possible_cpus->cpus[i].props.core_id = topo.core_id;
2684 ms->possible_cpus->cpus[i].props.has_thread_id = true;
2685 ms->possible_cpus->cpus[i].props.thread_id = topo.smt_id;
c96a1c0b
IM		 2686 }
2687 return ms->possible_cpus;
3811ef14
IM		 2688}
2689
1255166b
BD		 2690static void x86_nmi(NMIState *n, int cpu_index, Error **errp)
2691{
2692 /* cpu index isn't used */
2693 CPUState *cs;
2694
2695 CPU_FOREACH(cs) {
2696 X86CPU *cpu = X86_CPU(cs);
2697
2698 if (!cpu->apic_state) {
2699 cpu_interrupt(cs, CPU_INTERRUPT_NMI);
2700 } else {
2701 apic_deliver_nmi(cpu->apic_state);
2702 }
2703 }
2704}
2705
95bee274
IM		 2706static void pc_machine_class_init(ObjectClass *oc, void *data)
2707{
2708 MachineClass *mc = MACHINE_CLASS(oc);
2709 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc);
2710 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
1255166b 2711 NMIClass *nc = NMI_CLASS(oc);
95bee274 2712
7102fa70
EH		 2713 pcmc->pci_enabled = true;
2714 pcmc->has_acpi_build = true;
2715 pcmc->rsdp_in_ram = true;
2716 pcmc->smbios_defaults = true;
2717 pcmc->smbios_uuid_encoded = true;
2718 pcmc->gigabyte_align = true;
2719 pcmc->has_reserved_memory = true;
2720 pcmc->kvmclock_enabled = true;
16a9e8a5 2721 pcmc->enforce_aligned_dimm = true;
cd4040ec
EH		 2722 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported
2723 * to be used at the moment, 32K should be enough for a while. */
2724 pcmc->acpi_data_size = 0x20000 + 0x8000;
36f96c4b 2725 pcmc->save_tsc_khz = true;
98e753a6 2726 pcmc->linuxboot_dma_enabled = true;
fda672b5 2727 pcmc->pvh_enabled = true;
debbdc00 2728 assert(!mc->get_hotplug_handler);
285816d7 2729 mc->get_hotplug_handler = pc_get_hotplug_handler;
ea089eeb 2730 mc->cpu_index_to_instance_props = pc_cpu_index_to_props;
79e07936 2731 mc->get_default_cpu_node_id = pc_get_default_cpu_node_id;
3811ef14 2732 mc->possible_cpu_arch_ids = pc_possible_cpu_arch_ids;
7b8be49d 2733 mc->auto_enable_numa_with_memhp = true;
c5514d0e 2734 mc->has_hotpluggable_cpus = true;
41742767 2735 mc->default_boot_order = "cad";
4458fb3a 2736 mc->hot_add_cpu = pc_hot_add_cpu;
2059839b 2737 mc->block_default_type = IF_IDE;
4458fb3a 2738 mc->max_cpus = 255;
ae50c55a 2739 mc->reset = pc_machine_reset;
4ec60c76 2740 hc->pre_plug = pc_machine_device_pre_plug_cb;
95bee274 2741 hc->plug = pc_machine_device_plug_cb;
d9c5c5b8 2742 hc->unplug_request = pc_machine_device_unplug_request_cb;
232391c1 2743 hc->unplug = pc_machine_device_unplug_cb;
1255166b 2744 nc->nmi_monitor_handler = x86_nmi;
311ca98d 2745 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
f6a0d06b 2746 mc->nvdimm_supported = true;
0efc257d 2747
f2ffbe2b
DH		 2748 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int",
2749 pc_machine_get_device_memory_region_size, NULL,
0efc257d
EH		 2750 NULL, NULL, &error_abort);
2751
2752 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size",
2753 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g,
2754 NULL, NULL, &error_abort);
2755
2756 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G,
2757 "Maximum ram below the 4G boundary (32bit boundary)", &error_abort);
2758
2759 object_class_property_add(oc, PC_MACHINE_SMM, "OnOffAuto",
2760 pc_machine_get_smm, pc_machine_set_smm,
2761 NULL, NULL, &error_abort);
2762 object_class_property_set_description(oc, PC_MACHINE_SMM,
2763 "Enable SMM (pc & q35)", &error_abort);
2764
2765 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto",
2766 pc_machine_get_vmport, pc_machine_set_vmport,
2767 NULL, NULL, &error_abort);
2768 object_class_property_set_description(oc, PC_MACHINE_VMPORT,
2769 "Enable vmport (pc & q35)", &error_abort);
2770
be232eb0
CP		 2771 object_class_property_add_bool(oc, PC_MACHINE_SMBUS,
2772 pc_machine_get_smbus, pc_machine_set_smbus, &error_abort);
272f0428
CP		 2773
2774 object_class_property_add_bool(oc, PC_MACHINE_SATA,
2775 pc_machine_get_sata, pc_machine_set_sata, &error_abort);
feddd2fd
CP		 2776
2777 object_class_property_add_bool(oc, PC_MACHINE_PIT,
2778 pc_machine_get_pit, pc_machine_set_pit, &error_abort);
95bee274
IM		 2779}
2780
d5747cac
IM		 2781static const TypeInfo pc_machine_info = {
2782 .name = TYPE_PC_MACHINE,
2783 .parent = TYPE_MACHINE,
2784 .abstract = true,
2785 .instance_size = sizeof(PCMachineState),
bf1e8939 2786 .instance_init = pc_machine_initfn,
d5747cac 2787 .class_size = sizeof(PCMachineClass),
95bee274
IM		 2788 .class_init = pc_machine_class_init,
2789 .interfaces = (InterfaceInfo[]) {
2790 { TYPE_HOTPLUG_HANDLER },
1255166b 2791 { TYPE_NMI },
95bee274
IM		 2792 { }
2793 },
d5747cac
IM		 2794};
2795
2796static void pc_machine_register_types(void)
2797{
2798 type_register_static(&pc_machine_info);
2799}
2800
2801type_init(pc_machine_register_types)
Empty description
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