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Commit | Line | Data |
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093bc2cd AK |
1 | /* |
2 | * Physical memory management | |
3 | * | |
4 | * Copyright 2011 Red Hat, Inc. and/or its affiliates | |
5 | * | |
6 | * Authors: | |
7 | * Avi Kivity <[email protected]> | |
8 | * | |
9 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
10 | * the COPYING file in the top-level directory. | |
11 | * | |
6b620ca3 PB |
12 | * Contributions after 2012-01-13 are licensed under the terms of the |
13 | * GNU GPL, version 2 or (at your option) any later version. | |
093bc2cd AK |
14 | */ |
15 | ||
d38ea87a | 16 | #include "qemu/osdep.h" |
da34e65c | 17 | #include "qapi/error.h" |
33c11879 | 18 | #include "cpu.h" |
022c62cb PB |
19 | #include "exec/memory.h" |
20 | #include "exec/address-spaces.h" | |
409ddd01 | 21 | #include "qapi/visitor.h" |
1de7afc9 | 22 | #include "qemu/bitops.h" |
8c56c1a5 | 23 | #include "qemu/error-report.h" |
db725815 | 24 | #include "qemu/main-loop.h" |
b6b71cb5 | 25 | #include "qemu/qemu-print.h" |
2c9b15ca | 26 | #include "qom/object.h" |
0ab8ed18 | 27 | #include "trace-root.h" |
093bc2cd | 28 | |
022c62cb | 29 | #include "exec/memory-internal.h" |
220c3ebd | 30 | #include "exec/ram_addr.h" |
8c56c1a5 | 31 | #include "sysemu/kvm.h" |
54d31236 | 32 | #include "sysemu/runstate.h" |
14a48c1d | 33 | #include "sysemu/tcg.h" |
8072aae3 | 34 | #include "sysemu/accel.h" |
8072aae3 | 35 | #include "hw/boards.h" |
b08199c6 | 36 | #include "migration/vmstate.h" |
67d95c15 | 37 | |
d197063f PB |
38 | //#define DEBUG_UNASSIGNED |
39 | ||
22bde714 JK |
40 | static unsigned memory_region_transaction_depth; |
41 | static bool memory_region_update_pending; | |
4dc56152 | 42 | static bool ioeventfd_update_pending; |
ae7a2bca | 43 | bool global_dirty_log; |
7664e80c | 44 | |
eae3eb3e | 45 | static QTAILQ_HEAD(, MemoryListener) memory_listeners |
72e22d2f | 46 | = QTAILQ_HEAD_INITIALIZER(memory_listeners); |
4ef4db86 | 47 | |
0d673e36 AK |
48 | static QTAILQ_HEAD(, AddressSpace) address_spaces |
49 | = QTAILQ_HEAD_INITIALIZER(address_spaces); | |
50 | ||
967dc9b1 AK |
51 | static GHashTable *flat_views; |
52 | ||
093bc2cd AK |
53 | typedef struct AddrRange AddrRange; |
54 | ||
8417cebf | 55 | /* |
c9cdaa3a | 56 | * Note that signed integers are needed for negative offsetting in aliases |
8417cebf AK |
57 | * (large MemoryRegion::alias_offset). |
58 | */ | |
093bc2cd | 59 | struct AddrRange { |
08dafab4 AK |
60 | Int128 start; |
61 | Int128 size; | |
093bc2cd AK |
62 | }; |
63 | ||
08dafab4 | 64 | static AddrRange addrrange_make(Int128 start, Int128 size) |
093bc2cd AK |
65 | { |
66 | return (AddrRange) { start, size }; | |
67 | } | |
68 | ||
69 | static bool addrrange_equal(AddrRange r1, AddrRange r2) | |
70 | { | |
08dafab4 | 71 | return int128_eq(r1.start, r2.start) && int128_eq(r1.size, r2.size); |
093bc2cd AK |
72 | } |
73 | ||
08dafab4 | 74 | static Int128 addrrange_end(AddrRange r) |
093bc2cd | 75 | { |
08dafab4 | 76 | return int128_add(r.start, r.size); |
093bc2cd AK |
77 | } |
78 | ||
08dafab4 | 79 | static AddrRange addrrange_shift(AddrRange range, Int128 delta) |
093bc2cd | 80 | { |
08dafab4 | 81 | int128_addto(&range.start, delta); |
093bc2cd AK |
82 | return range; |
83 | } | |
84 | ||
08dafab4 AK |
85 | static bool addrrange_contains(AddrRange range, Int128 addr) |
86 | { | |
87 | return int128_ge(addr, range.start) | |
88 | && int128_lt(addr, addrrange_end(range)); | |
89 | } | |
90 | ||
093bc2cd AK |
91 | static bool addrrange_intersects(AddrRange r1, AddrRange r2) |
92 | { | |
08dafab4 AK |
93 | return addrrange_contains(r1, r2.start) |
94 | || addrrange_contains(r2, r1.start); | |
093bc2cd AK |
95 | } |
96 | ||
97 | static AddrRange addrrange_intersection(AddrRange r1, AddrRange r2) | |
98 | { | |
08dafab4 AK |
99 | Int128 start = int128_max(r1.start, r2.start); |
100 | Int128 end = int128_min(addrrange_end(r1), addrrange_end(r2)); | |
101 | return addrrange_make(start, int128_sub(end, start)); | |
093bc2cd AK |
102 | } |
103 | ||
0e0d36b4 AK |
104 | enum ListenerDirection { Forward, Reverse }; |
105 | ||
7376e582 | 106 | #define MEMORY_LISTENER_CALL_GLOBAL(_callback, _direction, _args...) \ |
0e0d36b4 AK |
107 | do { \ |
108 | MemoryListener *_listener; \ | |
109 | \ | |
110 | switch (_direction) { \ | |
111 | case Forward: \ | |
112 | QTAILQ_FOREACH(_listener, &memory_listeners, link) { \ | |
975aefe0 AK |
113 | if (_listener->_callback) { \ |
114 | _listener->_callback(_listener, ##_args); \ | |
115 | } \ | |
0e0d36b4 AK |
116 | } \ |
117 | break; \ | |
118 | case Reverse: \ | |
eae3eb3e | 119 | QTAILQ_FOREACH_REVERSE(_listener, &memory_listeners, link) { \ |
975aefe0 AK |
120 | if (_listener->_callback) { \ |
121 | _listener->_callback(_listener, ##_args); \ | |
122 | } \ | |
0e0d36b4 AK |
123 | } \ |
124 | break; \ | |
125 | default: \ | |
126 | abort(); \ | |
127 | } \ | |
128 | } while (0) | |
129 | ||
9a54635d | 130 | #define MEMORY_LISTENER_CALL(_as, _callback, _direction, _section, _args...) \ |
7376e582 AK |
131 | do { \ |
132 | MemoryListener *_listener; \ | |
133 | \ | |
134 | switch (_direction) { \ | |
135 | case Forward: \ | |
eae3eb3e | 136 | QTAILQ_FOREACH(_listener, &(_as)->listeners, link_as) { \ |
9a54635d | 137 | if (_listener->_callback) { \ |
7376e582 AK |
138 | _listener->_callback(_listener, _section, ##_args); \ |
139 | } \ | |
140 | } \ | |
141 | break; \ | |
142 | case Reverse: \ | |
eae3eb3e | 143 | QTAILQ_FOREACH_REVERSE(_listener, &(_as)->listeners, link_as) { \ |
9a54635d | 144 | if (_listener->_callback) { \ |
7376e582 AK |
145 | _listener->_callback(_listener, _section, ##_args); \ |
146 | } \ | |
147 | } \ | |
148 | break; \ | |
149 | default: \ | |
150 | abort(); \ | |
151 | } \ | |
152 | } while (0) | |
153 | ||
dfde4e6e | 154 | /* No need to ref/unref .mr, the FlatRange keeps it alive. */ |
b2dfd71c | 155 | #define MEMORY_LISTENER_UPDATE_REGION(fr, as, dir, callback, _args...) \ |
9c1f8f44 | 156 | do { \ |
16620684 AK |
157 | MemoryRegionSection mrs = section_from_flat_range(fr, \ |
158 | address_space_to_flatview(as)); \ | |
9a54635d | 159 | MEMORY_LISTENER_CALL(as, callback, dir, &mrs, ##_args); \ |
9c1f8f44 | 160 | } while(0) |
0e0d36b4 | 161 | |
093bc2cd AK |
162 | struct CoalescedMemoryRange { |
163 | AddrRange addr; | |
164 | QTAILQ_ENTRY(CoalescedMemoryRange) link; | |
165 | }; | |
166 | ||
3e9d69e7 AK |
167 | struct MemoryRegionIoeventfd { |
168 | AddrRange addr; | |
169 | bool match_data; | |
170 | uint64_t data; | |
753d5e14 | 171 | EventNotifier *e; |
3e9d69e7 AK |
172 | }; |
173 | ||
73bb753d TB |
174 | static bool memory_region_ioeventfd_before(MemoryRegionIoeventfd *a, |
175 | MemoryRegionIoeventfd *b) | |
3e9d69e7 | 176 | { |
73bb753d | 177 | if (int128_lt(a->addr.start, b->addr.start)) { |
3e9d69e7 | 178 | return true; |
73bb753d | 179 | } else if (int128_gt(a->addr.start, b->addr.start)) { |
3e9d69e7 | 180 | return false; |
73bb753d | 181 | } else if (int128_lt(a->addr.size, b->addr.size)) { |
3e9d69e7 | 182 | return true; |
73bb753d | 183 | } else if (int128_gt(a->addr.size, b->addr.size)) { |
3e9d69e7 | 184 | return false; |
73bb753d | 185 | } else if (a->match_data < b->match_data) { |
3e9d69e7 | 186 | return true; |
73bb753d | 187 | } else if (a->match_data > b->match_data) { |
3e9d69e7 | 188 | return false; |
73bb753d TB |
189 | } else if (a->match_data) { |
190 | if (a->data < b->data) { | |
3e9d69e7 | 191 | return true; |
73bb753d | 192 | } else if (a->data > b->data) { |
3e9d69e7 AK |
193 | return false; |
194 | } | |
195 | } | |
73bb753d | 196 | if (a->e < b->e) { |
3e9d69e7 | 197 | return true; |
73bb753d | 198 | } else if (a->e > b->e) { |
3e9d69e7 AK |
199 | return false; |
200 | } | |
201 | return false; | |
202 | } | |
203 | ||
73bb753d TB |
204 | static bool memory_region_ioeventfd_equal(MemoryRegionIoeventfd *a, |
205 | MemoryRegionIoeventfd *b) | |
3e9d69e7 AK |
206 | { |
207 | return !memory_region_ioeventfd_before(a, b) | |
208 | && !memory_region_ioeventfd_before(b, a); | |
209 | } | |
210 | ||
093bc2cd AK |
211 | /* Range of memory in the global map. Addresses are absolute. */ |
212 | struct FlatRange { | |
213 | MemoryRegion *mr; | |
a8170e5e | 214 | hwaddr offset_in_region; |
093bc2cd | 215 | AddrRange addr; |
5a583347 | 216 | uint8_t dirty_log_mask; |
b138e654 | 217 | bool romd_mode; |
fb1cd6f9 | 218 | bool readonly; |
c26763f8 | 219 | bool nonvolatile; |
3ac7d43a | 220 | int has_coalesced_range; |
093bc2cd AK |
221 | }; |
222 | ||
093bc2cd AK |
223 | #define FOR_EACH_FLAT_RANGE(var, view) \ |
224 | for (var = (view)->ranges; var < (view)->ranges + (view)->nr; ++var) | |
225 | ||
9c1f8f44 | 226 | static inline MemoryRegionSection |
16620684 | 227 | section_from_flat_range(FlatRange *fr, FlatView *fv) |
9c1f8f44 PB |
228 | { |
229 | return (MemoryRegionSection) { | |
230 | .mr = fr->mr, | |
16620684 | 231 | .fv = fv, |
9c1f8f44 PB |
232 | .offset_within_region = fr->offset_in_region, |
233 | .size = fr->addr.size, | |
234 | .offset_within_address_space = int128_get64(fr->addr.start), | |
235 | .readonly = fr->readonly, | |
c26763f8 | 236 | .nonvolatile = fr->nonvolatile, |
9c1f8f44 PB |
237 | }; |
238 | } | |
239 | ||
093bc2cd AK |
240 | static bool flatrange_equal(FlatRange *a, FlatRange *b) |
241 | { | |
242 | return a->mr == b->mr | |
243 | && addrrange_equal(a->addr, b->addr) | |
d0a9b5bc | 244 | && a->offset_in_region == b->offset_in_region |
b138e654 | 245 | && a->romd_mode == b->romd_mode |
c26763f8 MAL |
246 | && a->readonly == b->readonly |
247 | && a->nonvolatile == b->nonvolatile; | |
093bc2cd AK |
248 | } |
249 | ||
89c177bb | 250 | static FlatView *flatview_new(MemoryRegion *mr_root) |
093bc2cd | 251 | { |
cc94cd6d AK |
252 | FlatView *view; |
253 | ||
254 | view = g_new0(FlatView, 1); | |
856d7245 | 255 | view->ref = 1; |
89c177bb AK |
256 | view->root = mr_root; |
257 | memory_region_ref(mr_root); | |
02d9651d | 258 | trace_flatview_new(view, mr_root); |
cc94cd6d AK |
259 | |
260 | return view; | |
093bc2cd AK |
261 | } |
262 | ||
263 | /* Insert a range into a given position. Caller is responsible for maintaining | |
264 | * sorting order. | |
265 | */ | |
266 | static void flatview_insert(FlatView *view, unsigned pos, FlatRange *range) | |
267 | { | |
268 | if (view->nr == view->nr_allocated) { | |
269 | view->nr_allocated = MAX(2 * view->nr, 10); | |
7267c094 | 270 | view->ranges = g_realloc(view->ranges, |
093bc2cd AK |
271 | view->nr_allocated * sizeof(*view->ranges)); |
272 | } | |
273 | memmove(view->ranges + pos + 1, view->ranges + pos, | |
274 | (view->nr - pos) * sizeof(FlatRange)); | |
275 | view->ranges[pos] = *range; | |
dfde4e6e | 276 | memory_region_ref(range->mr); |
093bc2cd AK |
277 | ++view->nr; |
278 | } | |
279 | ||
280 | static void flatview_destroy(FlatView *view) | |
281 | { | |
dfde4e6e PB |
282 | int i; |
283 | ||
02d9651d | 284 | trace_flatview_destroy(view, view->root); |
66a6df1d AK |
285 | if (view->dispatch) { |
286 | address_space_dispatch_free(view->dispatch); | |
287 | } | |
dfde4e6e PB |
288 | for (i = 0; i < view->nr; i++) { |
289 | memory_region_unref(view->ranges[i].mr); | |
290 | } | |
7267c094 | 291 | g_free(view->ranges); |
89c177bb | 292 | memory_region_unref(view->root); |
a9a0c06d | 293 | g_free(view); |
093bc2cd AK |
294 | } |
295 | ||
447b0d0b | 296 | static bool flatview_ref(FlatView *view) |
856d7245 | 297 | { |
447b0d0b | 298 | return atomic_fetch_inc_nonzero(&view->ref) > 0; |
856d7245 PB |
299 | } |
300 | ||
48564041 | 301 | void flatview_unref(FlatView *view) |
856d7245 PB |
302 | { |
303 | if (atomic_fetch_dec(&view->ref) == 1) { | |
02d9651d | 304 | trace_flatview_destroy_rcu(view, view->root); |
092aa2fc | 305 | assert(view->root); |
66a6df1d | 306 | call_rcu(view, flatview_destroy, rcu); |
856d7245 PB |
307 | } |
308 | } | |
309 | ||
3d8e6bf9 AK |
310 | static bool can_merge(FlatRange *r1, FlatRange *r2) |
311 | { | |
08dafab4 | 312 | return int128_eq(addrrange_end(r1->addr), r2->addr.start) |
3d8e6bf9 | 313 | && r1->mr == r2->mr |
08dafab4 AK |
314 | && int128_eq(int128_add(int128_make64(r1->offset_in_region), |
315 | r1->addr.size), | |
316 | int128_make64(r2->offset_in_region)) | |
d0a9b5bc | 317 | && r1->dirty_log_mask == r2->dirty_log_mask |
b138e654 | 318 | && r1->romd_mode == r2->romd_mode |
c26763f8 MAL |
319 | && r1->readonly == r2->readonly |
320 | && r1->nonvolatile == r2->nonvolatile; | |
3d8e6bf9 AK |
321 | } |
322 | ||
8508e024 | 323 | /* Attempt to simplify a view by merging adjacent ranges */ |
3d8e6bf9 AK |
324 | static void flatview_simplify(FlatView *view) |
325 | { | |
838ec117 | 326 | unsigned i, j, k; |
3d8e6bf9 AK |
327 | |
328 | i = 0; | |
329 | while (i < view->nr) { | |
330 | j = i + 1; | |
331 | while (j < view->nr | |
332 | && can_merge(&view->ranges[j-1], &view->ranges[j])) { | |
08dafab4 | 333 | int128_addto(&view->ranges[i].addr.size, view->ranges[j].addr.size); |
3d8e6bf9 AK |
334 | ++j; |
335 | } | |
336 | ++i; | |
838ec117 KW |
337 | for (k = i; k < j; k++) { |
338 | memory_region_unref(view->ranges[k].mr); | |
339 | } | |
3d8e6bf9 AK |
340 | memmove(&view->ranges[i], &view->ranges[j], |
341 | (view->nr - j) * sizeof(view->ranges[j])); | |
342 | view->nr -= j - i; | |
343 | } | |
344 | } | |
345 | ||
e7342aa3 PB |
346 | static bool memory_region_big_endian(MemoryRegion *mr) |
347 | { | |
348 | #ifdef TARGET_WORDS_BIGENDIAN | |
349 | return mr->ops->endianness != DEVICE_LITTLE_ENDIAN; | |
350 | #else | |
351 | return mr->ops->endianness == DEVICE_BIG_ENDIAN; | |
352 | #endif | |
353 | } | |
354 | ||
e11ef3d1 PB |
355 | static bool memory_region_wrong_endianness(MemoryRegion *mr) |
356 | { | |
357 | #ifdef TARGET_WORDS_BIGENDIAN | |
358 | return mr->ops->endianness == DEVICE_LITTLE_ENDIAN; | |
359 | #else | |
360 | return mr->ops->endianness == DEVICE_BIG_ENDIAN; | |
361 | #endif | |
362 | } | |
363 | ||
364 | static void adjust_endianness(MemoryRegion *mr, uint64_t *data, unsigned size) | |
365 | { | |
366 | if (memory_region_wrong_endianness(mr)) { | |
367 | switch (size) { | |
368 | case 1: | |
369 | break; | |
370 | case 2: | |
371 | *data = bswap16(*data); | |
372 | break; | |
373 | case 4: | |
374 | *data = bswap32(*data); | |
375 | break; | |
376 | case 8: | |
377 | *data = bswap64(*data); | |
378 | break; | |
379 | default: | |
380 | abort(); | |
381 | } | |
382 | } | |
383 | } | |
384 | ||
3c754a93 | 385 | static inline void memory_region_shift_read_access(uint64_t *value, |
98f52cdb | 386 | signed shift, |
3c754a93 PMD |
387 | uint64_t mask, |
388 | uint64_t tmp) | |
389 | { | |
98f52cdb PMD |
390 | if (shift >= 0) { |
391 | *value |= (tmp & mask) << shift; | |
392 | } else { | |
393 | *value |= (tmp & mask) >> -shift; | |
394 | } | |
3c754a93 PMD |
395 | } |
396 | ||
397 | static inline uint64_t memory_region_shift_write_access(uint64_t *value, | |
98f52cdb | 398 | signed shift, |
3c754a93 PMD |
399 | uint64_t mask) |
400 | { | |
98f52cdb PMD |
401 | uint64_t tmp; |
402 | ||
403 | if (shift >= 0) { | |
404 | tmp = (*value >> shift) & mask; | |
405 | } else { | |
406 | tmp = (*value << -shift) & mask; | |
407 | } | |
408 | ||
409 | return tmp; | |
3c754a93 PMD |
410 | } |
411 | ||
4779dc1d HB |
412 | static hwaddr memory_region_to_absolute_addr(MemoryRegion *mr, hwaddr offset) |
413 | { | |
414 | MemoryRegion *root; | |
415 | hwaddr abs_addr = offset; | |
416 | ||
417 | abs_addr += mr->addr; | |
418 | for (root = mr; root->container; ) { | |
419 | root = root->container; | |
420 | abs_addr += root->addr; | |
421 | } | |
422 | ||
423 | return abs_addr; | |
424 | } | |
425 | ||
5a68be94 HB |
426 | static int get_cpu_index(void) |
427 | { | |
428 | if (current_cpu) { | |
429 | return current_cpu->cpu_index; | |
430 | } | |
431 | return -1; | |
432 | } | |
433 | ||
cc05c43a | 434 | static MemTxResult memory_region_read_accessor(MemoryRegion *mr, |
ce5d2f33 PB |
435 | hwaddr addr, |
436 | uint64_t *value, | |
437 | unsigned size, | |
98f52cdb | 438 | signed shift, |
cc05c43a PM |
439 | uint64_t mask, |
440 | MemTxAttrs attrs) | |
ce5d2f33 | 441 | { |
ce5d2f33 PB |
442 | uint64_t tmp; |
443 | ||
cc05c43a | 444 | tmp = mr->ops->read(mr->opaque, addr, size); |
23d92d68 | 445 | if (mr->subpage) { |
5a68be94 | 446 | trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size); |
f2d08942 HB |
447 | } else if (mr == &io_mem_notdirty) { |
448 | /* Accesses to code which has previously been translated into a TB show | |
449 | * up in the MMIO path, as accesses to the io_mem_notdirty | |
450 | * MemoryRegion. */ | |
451 | trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size); | |
4779dc1d HB |
452 | } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) { |
453 | hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr); | |
5a68be94 | 454 | trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size); |
23d92d68 | 455 | } |
3c754a93 | 456 | memory_region_shift_read_access(value, shift, mask, tmp); |
cc05c43a | 457 | return MEMTX_OK; |
ce5d2f33 PB |
458 | } |
459 | ||
cc05c43a PM |
460 | static MemTxResult memory_region_read_with_attrs_accessor(MemoryRegion *mr, |
461 | hwaddr addr, | |
462 | uint64_t *value, | |
463 | unsigned size, | |
98f52cdb | 464 | signed shift, |
cc05c43a PM |
465 | uint64_t mask, |
466 | MemTxAttrs attrs) | |
164a4dcd | 467 | { |
cc05c43a PM |
468 | uint64_t tmp = 0; |
469 | MemTxResult r; | |
164a4dcd | 470 | |
cc05c43a | 471 | r = mr->ops->read_with_attrs(mr->opaque, addr, &tmp, size, attrs); |
23d92d68 | 472 | if (mr->subpage) { |
5a68be94 | 473 | trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size); |
f2d08942 HB |
474 | } else if (mr == &io_mem_notdirty) { |
475 | /* Accesses to code which has previously been translated into a TB show | |
476 | * up in the MMIO path, as accesses to the io_mem_notdirty | |
477 | * MemoryRegion. */ | |
478 | trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size); | |
4779dc1d HB |
479 | } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) { |
480 | hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr); | |
5a68be94 | 481 | trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size); |
23d92d68 | 482 | } |
3c754a93 | 483 | memory_region_shift_read_access(value, shift, mask, tmp); |
cc05c43a | 484 | return r; |
164a4dcd AK |
485 | } |
486 | ||
cc05c43a PM |
487 | static MemTxResult memory_region_write_accessor(MemoryRegion *mr, |
488 | hwaddr addr, | |
489 | uint64_t *value, | |
490 | unsigned size, | |
98f52cdb | 491 | signed shift, |
cc05c43a PM |
492 | uint64_t mask, |
493 | MemTxAttrs attrs) | |
164a4dcd | 494 | { |
3c754a93 | 495 | uint64_t tmp = memory_region_shift_write_access(value, shift, mask); |
164a4dcd | 496 | |
23d92d68 | 497 | if (mr->subpage) { |
5a68be94 | 498 | trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size); |
f2d08942 HB |
499 | } else if (mr == &io_mem_notdirty) { |
500 | /* Accesses to code which has previously been translated into a TB show | |
501 | * up in the MMIO path, as accesses to the io_mem_notdirty | |
502 | * MemoryRegion. */ | |
503 | trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size); | |
4779dc1d HB |
504 | } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) { |
505 | hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr); | |
5a68be94 | 506 | trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size); |
23d92d68 | 507 | } |
164a4dcd | 508 | mr->ops->write(mr->opaque, addr, tmp, size); |
cc05c43a | 509 | return MEMTX_OK; |
164a4dcd AK |
510 | } |
511 | ||
cc05c43a PM |
512 | static MemTxResult memory_region_write_with_attrs_accessor(MemoryRegion *mr, |
513 | hwaddr addr, | |
514 | uint64_t *value, | |
515 | unsigned size, | |
98f52cdb | 516 | signed shift, |
cc05c43a PM |
517 | uint64_t mask, |
518 | MemTxAttrs attrs) | |
519 | { | |
3c754a93 | 520 | uint64_t tmp = memory_region_shift_write_access(value, shift, mask); |
cc05c43a | 521 | |
23d92d68 | 522 | if (mr->subpage) { |
5a68be94 | 523 | trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size); |
f2d08942 HB |
524 | } else if (mr == &io_mem_notdirty) { |
525 | /* Accesses to code which has previously been translated into a TB show | |
526 | * up in the MMIO path, as accesses to the io_mem_notdirty | |
527 | * MemoryRegion. */ | |
528 | trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size); | |
4779dc1d HB |
529 | } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) { |
530 | hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr); | |
5a68be94 | 531 | trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size); |
23d92d68 | 532 | } |
cc05c43a PM |
533 | return mr->ops->write_with_attrs(mr->opaque, addr, tmp, size, attrs); |
534 | } | |
535 | ||
536 | static MemTxResult access_with_adjusted_size(hwaddr addr, | |
164a4dcd AK |
537 | uint64_t *value, |
538 | unsigned size, | |
539 | unsigned access_size_min, | |
540 | unsigned access_size_max, | |
05e015f7 KF |
541 | MemTxResult (*access_fn) |
542 | (MemoryRegion *mr, | |
543 | hwaddr addr, | |
544 | uint64_t *value, | |
545 | unsigned size, | |
98f52cdb | 546 | signed shift, |
05e015f7 KF |
547 | uint64_t mask, |
548 | MemTxAttrs attrs), | |
cc05c43a PM |
549 | MemoryRegion *mr, |
550 | MemTxAttrs attrs) | |
164a4dcd AK |
551 | { |
552 | uint64_t access_mask; | |
553 | unsigned access_size; | |
554 | unsigned i; | |
cc05c43a | 555 | MemTxResult r = MEMTX_OK; |
164a4dcd AK |
556 | |
557 | if (!access_size_min) { | |
558 | access_size_min = 1; | |
559 | } | |
560 | if (!access_size_max) { | |
561 | access_size_max = 4; | |
562 | } | |
ce5d2f33 PB |
563 | |
564 | /* FIXME: support unaligned access? */ | |
164a4dcd | 565 | access_size = MAX(MIN(size, access_size_max), access_size_min); |
36960b4d | 566 | access_mask = MAKE_64BIT_MASK(0, access_size * 8); |
e7342aa3 PB |
567 | if (memory_region_big_endian(mr)) { |
568 | for (i = 0; i < size; i += access_size) { | |
05e015f7 | 569 | r |= access_fn(mr, addr + i, value, access_size, |
cc05c43a | 570 | (size - access_size - i) * 8, access_mask, attrs); |
e7342aa3 PB |
571 | } |
572 | } else { | |
573 | for (i = 0; i < size; i += access_size) { | |
05e015f7 | 574 | r |= access_fn(mr, addr + i, value, access_size, i * 8, |
cc05c43a | 575 | access_mask, attrs); |
e7342aa3 | 576 | } |
164a4dcd | 577 | } |
cc05c43a | 578 | return r; |
164a4dcd AK |
579 | } |
580 | ||
e2177955 AK |
581 | static AddressSpace *memory_region_to_address_space(MemoryRegion *mr) |
582 | { | |
0d673e36 AK |
583 | AddressSpace *as; |
584 | ||
feca4ac1 PB |
585 | while (mr->container) { |
586 | mr = mr->container; | |
e2177955 | 587 | } |
0d673e36 AK |
588 | QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) { |
589 | if (mr == as->root) { | |
590 | return as; | |
591 | } | |
e2177955 | 592 | } |
eed2bacf | 593 | return NULL; |
e2177955 AK |
594 | } |
595 | ||
093bc2cd AK |
596 | /* Render a memory region into the global view. Ranges in @view obscure |
597 | * ranges in @mr. | |
598 | */ | |
599 | static void render_memory_region(FlatView *view, | |
600 | MemoryRegion *mr, | |
08dafab4 | 601 | Int128 base, |
fb1cd6f9 | 602 | AddrRange clip, |
c26763f8 MAL |
603 | bool readonly, |
604 | bool nonvolatile) | |
093bc2cd AK |
605 | { |
606 | MemoryRegion *subregion; | |
607 | unsigned i; | |
a8170e5e | 608 | hwaddr offset_in_region; |
08dafab4 AK |
609 | Int128 remain; |
610 | Int128 now; | |
093bc2cd AK |
611 | FlatRange fr; |
612 | AddrRange tmp; | |
613 | ||
6bba19ba AK |
614 | if (!mr->enabled) { |
615 | return; | |
616 | } | |
617 | ||
08dafab4 | 618 | int128_addto(&base, int128_make64(mr->addr)); |
fb1cd6f9 | 619 | readonly |= mr->readonly; |
c26763f8 | 620 | nonvolatile |= mr->nonvolatile; |
093bc2cd AK |
621 | |
622 | tmp = addrrange_make(base, mr->size); | |
623 | ||
624 | if (!addrrange_intersects(tmp, clip)) { | |
625 | return; | |
626 | } | |
627 | ||
628 | clip = addrrange_intersection(tmp, clip); | |
629 | ||
630 | if (mr->alias) { | |
08dafab4 AK |
631 | int128_subfrom(&base, int128_make64(mr->alias->addr)); |
632 | int128_subfrom(&base, int128_make64(mr->alias_offset)); | |
c26763f8 MAL |
633 | render_memory_region(view, mr->alias, base, clip, |
634 | readonly, nonvolatile); | |
093bc2cd AK |
635 | return; |
636 | } | |
637 | ||
638 | /* Render subregions in priority order. */ | |
639 | QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) { | |
c26763f8 MAL |
640 | render_memory_region(view, subregion, base, clip, |
641 | readonly, nonvolatile); | |
093bc2cd AK |
642 | } |
643 | ||
14a3c10a | 644 | if (!mr->terminates) { |
093bc2cd AK |
645 | return; |
646 | } | |
647 | ||
08dafab4 | 648 | offset_in_region = int128_get64(int128_sub(clip.start, base)); |
093bc2cd AK |
649 | base = clip.start; |
650 | remain = clip.size; | |
651 | ||
2eb74e1a | 652 | fr.mr = mr; |
6f6a5ef3 | 653 | fr.dirty_log_mask = memory_region_get_dirty_log_mask(mr); |
b138e654 | 654 | fr.romd_mode = mr->romd_mode; |
2eb74e1a | 655 | fr.readonly = readonly; |
c26763f8 | 656 | fr.nonvolatile = nonvolatile; |
3ac7d43a | 657 | fr.has_coalesced_range = 0; |
2eb74e1a | 658 | |
093bc2cd | 659 | /* Render the region itself into any gaps left by the current view. */ |
08dafab4 AK |
660 | for (i = 0; i < view->nr && int128_nz(remain); ++i) { |
661 | if (int128_ge(base, addrrange_end(view->ranges[i].addr))) { | |
093bc2cd AK |
662 | continue; |
663 | } | |
08dafab4 AK |
664 | if (int128_lt(base, view->ranges[i].addr.start)) { |
665 | now = int128_min(remain, | |
666 | int128_sub(view->ranges[i].addr.start, base)); | |
093bc2cd AK |
667 | fr.offset_in_region = offset_in_region; |
668 | fr.addr = addrrange_make(base, now); | |
669 | flatview_insert(view, i, &fr); | |
670 | ++i; | |
08dafab4 AK |
671 | int128_addto(&base, now); |
672 | offset_in_region += int128_get64(now); | |
673 | int128_subfrom(&remain, now); | |
093bc2cd | 674 | } |
d26a8cae AK |
675 | now = int128_sub(int128_min(int128_add(base, remain), |
676 | addrrange_end(view->ranges[i].addr)), | |
677 | base); | |
678 | int128_addto(&base, now); | |
679 | offset_in_region += int128_get64(now); | |
680 | int128_subfrom(&remain, now); | |
093bc2cd | 681 | } |
08dafab4 | 682 | if (int128_nz(remain)) { |
093bc2cd AK |
683 | fr.offset_in_region = offset_in_region; |
684 | fr.addr = addrrange_make(base, remain); | |
685 | flatview_insert(view, i, &fr); | |
686 | } | |
687 | } | |
688 | ||
89c177bb AK |
689 | static MemoryRegion *memory_region_get_flatview_root(MemoryRegion *mr) |
690 | { | |
e673ba9a PB |
691 | while (mr->enabled) { |
692 | if (mr->alias) { | |
693 | if (!mr->alias_offset && int128_ge(mr->size, mr->alias->size)) { | |
694 | /* The alias is included in its entirety. Use it as | |
695 | * the "real" root, so that we can share more FlatViews. | |
696 | */ | |
697 | mr = mr->alias; | |
698 | continue; | |
699 | } | |
700 | } else if (!mr->terminates) { | |
701 | unsigned int found = 0; | |
702 | MemoryRegion *child, *next = NULL; | |
703 | QTAILQ_FOREACH(child, &mr->subregions, subregions_link) { | |
704 | if (child->enabled) { | |
705 | if (++found > 1) { | |
706 | next = NULL; | |
707 | break; | |
708 | } | |
709 | if (!child->addr && int128_ge(mr->size, child->size)) { | |
710 | /* A child is included in its entirety. If it's the only | |
711 | * enabled one, use it in the hope of finding an alias down the | |
712 | * way. This will also let us share FlatViews. | |
713 | */ | |
714 | next = child; | |
715 | } | |
716 | } | |
717 | } | |
092aa2fc AK |
718 | if (found == 0) { |
719 | return NULL; | |
720 | } | |
e673ba9a PB |
721 | if (next) { |
722 | mr = next; | |
723 | continue; | |
724 | } | |
725 | } | |
726 | ||
092aa2fc | 727 | return mr; |
89c177bb AK |
728 | } |
729 | ||
092aa2fc | 730 | return NULL; |
89c177bb AK |
731 | } |
732 | ||
093bc2cd | 733 | /* Render a memory topology into a list of disjoint absolute ranges. */ |
a9a0c06d | 734 | static FlatView *generate_memory_topology(MemoryRegion *mr) |
093bc2cd | 735 | { |
9bf561e3 | 736 | int i; |
a9a0c06d | 737 | FlatView *view; |
093bc2cd | 738 | |
89c177bb | 739 | view = flatview_new(mr); |
093bc2cd | 740 | |
83f3c251 | 741 | if (mr) { |
a9a0c06d | 742 | render_memory_region(view, mr, int128_zero(), |
c26763f8 MAL |
743 | addrrange_make(int128_zero(), int128_2_64()), |
744 | false, false); | |
83f3c251 | 745 | } |
a9a0c06d | 746 | flatview_simplify(view); |
093bc2cd | 747 | |
9bf561e3 AK |
748 | view->dispatch = address_space_dispatch_new(view); |
749 | for (i = 0; i < view->nr; i++) { | |
750 | MemoryRegionSection mrs = | |
751 | section_from_flat_range(&view->ranges[i], view); | |
752 | flatview_add_to_dispatch(view, &mrs); | |
753 | } | |
754 | address_space_dispatch_compact(view->dispatch); | |
967dc9b1 | 755 | g_hash_table_replace(flat_views, mr, view); |
9bf561e3 | 756 | |
093bc2cd AK |
757 | return view; |
758 | } | |
759 | ||
3e9d69e7 AK |
760 | static void address_space_add_del_ioeventfds(AddressSpace *as, |
761 | MemoryRegionIoeventfd *fds_new, | |
762 | unsigned fds_new_nb, | |
763 | MemoryRegionIoeventfd *fds_old, | |
764 | unsigned fds_old_nb) | |
765 | { | |
766 | unsigned iold, inew; | |
80a1ea37 AK |
767 | MemoryRegionIoeventfd *fd; |
768 | MemoryRegionSection section; | |
3e9d69e7 AK |
769 | |
770 | /* Generate a symmetric difference of the old and new fd sets, adding | |
771 | * and deleting as necessary. | |
772 | */ | |
773 | ||
774 | iold = inew = 0; | |
775 | while (iold < fds_old_nb || inew < fds_new_nb) { | |
776 | if (iold < fds_old_nb | |
777 | && (inew == fds_new_nb | |
73bb753d TB |
778 | || memory_region_ioeventfd_before(&fds_old[iold], |
779 | &fds_new[inew]))) { | |
80a1ea37 AK |
780 | fd = &fds_old[iold]; |
781 | section = (MemoryRegionSection) { | |
16620684 | 782 | .fv = address_space_to_flatview(as), |
80a1ea37 | 783 | .offset_within_address_space = int128_get64(fd->addr.start), |
052e87b0 | 784 | .size = fd->addr.size, |
80a1ea37 | 785 | }; |
9a54635d | 786 | MEMORY_LISTENER_CALL(as, eventfd_del, Forward, §ion, |
753d5e14 | 787 | fd->match_data, fd->data, fd->e); |
3e9d69e7 AK |
788 | ++iold; |
789 | } else if (inew < fds_new_nb | |
790 | && (iold == fds_old_nb | |
73bb753d TB |
791 | || memory_region_ioeventfd_before(&fds_new[inew], |
792 | &fds_old[iold]))) { | |
80a1ea37 AK |
793 | fd = &fds_new[inew]; |
794 | section = (MemoryRegionSection) { | |
16620684 | 795 | .fv = address_space_to_flatview(as), |
80a1ea37 | 796 | .offset_within_address_space = int128_get64(fd->addr.start), |
052e87b0 | 797 | .size = fd->addr.size, |
80a1ea37 | 798 | }; |
9a54635d | 799 | MEMORY_LISTENER_CALL(as, eventfd_add, Reverse, §ion, |
753d5e14 | 800 | fd->match_data, fd->data, fd->e); |
3e9d69e7 AK |
801 | ++inew; |
802 | } else { | |
803 | ++iold; | |
804 | ++inew; | |
805 | } | |
806 | } | |
807 | } | |
808 | ||
48564041 | 809 | FlatView *address_space_get_flatview(AddressSpace *as) |
856d7245 PB |
810 | { |
811 | FlatView *view; | |
812 | ||
374f2981 | 813 | rcu_read_lock(); |
447b0d0b | 814 | do { |
16620684 | 815 | view = address_space_to_flatview(as); |
447b0d0b PB |
816 | /* If somebody has replaced as->current_map concurrently, |
817 | * flatview_ref returns false. | |
818 | */ | |
819 | } while (!flatview_ref(view)); | |
374f2981 | 820 | rcu_read_unlock(); |
856d7245 PB |
821 | return view; |
822 | } | |
823 | ||
3e9d69e7 AK |
824 | static void address_space_update_ioeventfds(AddressSpace *as) |
825 | { | |
99e86347 | 826 | FlatView *view; |
3e9d69e7 AK |
827 | FlatRange *fr; |
828 | unsigned ioeventfd_nb = 0; | |
829 | MemoryRegionIoeventfd *ioeventfds = NULL; | |
830 | AddrRange tmp; | |
831 | unsigned i; | |
832 | ||
856d7245 | 833 | view = address_space_get_flatview(as); |
99e86347 | 834 | FOR_EACH_FLAT_RANGE(fr, view) { |
3e9d69e7 AK |
835 | for (i = 0; i < fr->mr->ioeventfd_nb; ++i) { |
836 | tmp = addrrange_shift(fr->mr->ioeventfds[i].addr, | |
08dafab4 AK |
837 | int128_sub(fr->addr.start, |
838 | int128_make64(fr->offset_in_region))); | |
3e9d69e7 AK |
839 | if (addrrange_intersects(fr->addr, tmp)) { |
840 | ++ioeventfd_nb; | |
7267c094 | 841 | ioeventfds = g_realloc(ioeventfds, |
3e9d69e7 AK |
842 | ioeventfd_nb * sizeof(*ioeventfds)); |
843 | ioeventfds[ioeventfd_nb-1] = fr->mr->ioeventfds[i]; | |
844 | ioeventfds[ioeventfd_nb-1].addr = tmp; | |
845 | } | |
846 | } | |
847 | } | |
848 | ||
849 | address_space_add_del_ioeventfds(as, ioeventfds, ioeventfd_nb, | |
850 | as->ioeventfds, as->ioeventfd_nb); | |
851 | ||
7267c094 | 852 | g_free(as->ioeventfds); |
3e9d69e7 AK |
853 | as->ioeventfds = ioeventfds; |
854 | as->ioeventfd_nb = ioeventfd_nb; | |
856d7245 | 855 | flatview_unref(view); |
3e9d69e7 AK |
856 | } |
857 | ||
909bf763 PB |
858 | static void flat_range_coalesced_io_del(FlatRange *fr, AddressSpace *as) |
859 | { | |
1f7af804 PB |
860 | if (!fr->has_coalesced_range) { |
861 | return; | |
862 | } | |
863 | ||
3ac7d43a PB |
864 | if (--fr->has_coalesced_range > 0) { |
865 | return; | |
866 | } | |
867 | ||
909bf763 PB |
868 | MEMORY_LISTENER_UPDATE_REGION(fr, as, Reverse, coalesced_io_del, |
869 | int128_get64(fr->addr.start), | |
870 | int128_get64(fr->addr.size)); | |
871 | } | |
872 | ||
873 | static void flat_range_coalesced_io_add(FlatRange *fr, AddressSpace *as) | |
874 | { | |
875 | MemoryRegion *mr = fr->mr; | |
876 | CoalescedMemoryRange *cmr; | |
877 | AddrRange tmp; | |
878 | ||
1f7af804 PB |
879 | if (QTAILQ_EMPTY(&mr->coalesced)) { |
880 | return; | |
881 | } | |
882 | ||
3ac7d43a PB |
883 | if (fr->has_coalesced_range++) { |
884 | return; | |
885 | } | |
886 | ||
909bf763 PB |
887 | QTAILQ_FOREACH(cmr, &mr->coalesced, link) { |
888 | tmp = addrrange_shift(cmr->addr, | |
889 | int128_sub(fr->addr.start, | |
890 | int128_make64(fr->offset_in_region))); | |
891 | if (!addrrange_intersects(tmp, fr->addr)) { | |
892 | continue; | |
893 | } | |
894 | tmp = addrrange_intersection(tmp, fr->addr); | |
895 | MEMORY_LISTENER_UPDATE_REGION(fr, as, Forward, coalesced_io_add, | |
896 | int128_get64(tmp.start), | |
897 | int128_get64(tmp.size)); | |
898 | } | |
899 | } | |
900 | ||
b8af1afb | 901 | static void address_space_update_topology_pass(AddressSpace *as, |
a9a0c06d PB |
902 | const FlatView *old_view, |
903 | const FlatView *new_view, | |
b8af1afb | 904 | bool adding) |
093bc2cd | 905 | { |
093bc2cd AK |
906 | unsigned iold, inew; |
907 | FlatRange *frold, *frnew; | |
093bc2cd AK |
908 | |
909 | /* Generate a symmetric difference of the old and new memory maps. | |
910 | * Kill ranges in the old map, and instantiate ranges in the new map. | |
911 | */ | |
912 | iold = inew = 0; | |
a9a0c06d PB |
913 | while (iold < old_view->nr || inew < new_view->nr) { |
914 | if (iold < old_view->nr) { | |
915 | frold = &old_view->ranges[iold]; | |
093bc2cd AK |
916 | } else { |
917 | frold = NULL; | |
918 | } | |
a9a0c06d PB |
919 | if (inew < new_view->nr) { |
920 | frnew = &new_view->ranges[inew]; | |
093bc2cd AK |
921 | } else { |
922 | frnew = NULL; | |
923 | } | |
924 | ||
925 | if (frold | |
926 | && (!frnew | |
08dafab4 AK |
927 | || int128_lt(frold->addr.start, frnew->addr.start) |
928 | || (int128_eq(frold->addr.start, frnew->addr.start) | |
093bc2cd | 929 | && !flatrange_equal(frold, frnew)))) { |
41a6e477 | 930 | /* In old but not in new, or in both but attributes changed. */ |
093bc2cd | 931 | |
b8af1afb | 932 | if (!adding) { |
3ac7d43a | 933 | flat_range_coalesced_io_del(frold, as); |
72e22d2f | 934 | MEMORY_LISTENER_UPDATE_REGION(frold, as, Reverse, region_del); |
b8af1afb AK |
935 | } |
936 | ||
093bc2cd AK |
937 | ++iold; |
938 | } else if (frold && frnew && flatrange_equal(frold, frnew)) { | |
41a6e477 | 939 | /* In both and unchanged (except logging may have changed) */ |
093bc2cd | 940 | |
4f826024 | 941 | if (adding) { |
50c1e149 | 942 | MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_nop); |
b2dfd71c PB |
943 | if (frnew->dirty_log_mask & ~frold->dirty_log_mask) { |
944 | MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, log_start, | |
945 | frold->dirty_log_mask, | |
946 | frnew->dirty_log_mask); | |
947 | } | |
948 | if (frold->dirty_log_mask & ~frnew->dirty_log_mask) { | |
949 | MEMORY_LISTENER_UPDATE_REGION(frnew, as, Reverse, log_stop, | |
950 | frold->dirty_log_mask, | |
951 | frnew->dirty_log_mask); | |
b8af1afb | 952 | } |
5a583347 AK |
953 | } |
954 | ||
093bc2cd AK |
955 | ++iold; |
956 | ++inew; | |
093bc2cd AK |
957 | } else { |
958 | /* In new */ | |
959 | ||
b8af1afb | 960 | if (adding) { |
72e22d2f | 961 | MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_add); |
3ac7d43a | 962 | flat_range_coalesced_io_add(frnew, as); |
b8af1afb AK |
963 | } |
964 | ||
093bc2cd AK |
965 | ++inew; |
966 | } | |
967 | } | |
b8af1afb AK |
968 | } |
969 | ||
967dc9b1 AK |
970 | static void flatviews_init(void) |
971 | { | |
092aa2fc AK |
972 | static FlatView *empty_view; |
973 | ||
967dc9b1 AK |
974 | if (flat_views) { |
975 | return; | |
976 | } | |
977 | ||
978 | flat_views = g_hash_table_new_full(g_direct_hash, g_direct_equal, NULL, | |
979 | (GDestroyNotify) flatview_unref); | |
092aa2fc AK |
980 | if (!empty_view) { |
981 | empty_view = generate_memory_topology(NULL); | |
982 | /* We keep it alive forever in the global variable. */ | |
983 | flatview_ref(empty_view); | |
984 | } else { | |
985 | g_hash_table_replace(flat_views, NULL, empty_view); | |
986 | flatview_ref(empty_view); | |
987 | } | |
967dc9b1 AK |
988 | } |
989 | ||
990 | static void flatviews_reset(void) | |
991 | { | |
992 | AddressSpace *as; | |
993 | ||
994 | if (flat_views) { | |
995 | g_hash_table_unref(flat_views); | |
996 | flat_views = NULL; | |
997 | } | |
998 | flatviews_init(); | |
999 | ||
1000 | /* Render unique FVs */ | |
1001 | QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) { | |
1002 | MemoryRegion *physmr = memory_region_get_flatview_root(as->root); | |
1003 | ||
1004 | if (g_hash_table_lookup(flat_views, physmr)) { | |
1005 | continue; | |
1006 | } | |
1007 | ||
1008 | generate_memory_topology(physmr); | |
1009 | } | |
1010 | } | |
1011 | ||
1012 | static void address_space_set_flatview(AddressSpace *as) | |
b8af1afb | 1013 | { |
67ace39b | 1014 | FlatView *old_view = address_space_to_flatview(as); |
967dc9b1 AK |
1015 | MemoryRegion *physmr = memory_region_get_flatview_root(as->root); |
1016 | FlatView *new_view = g_hash_table_lookup(flat_views, physmr); | |
1017 | ||
1018 | assert(new_view); | |
1019 | ||
67ace39b AK |
1020 | if (old_view == new_view) { |
1021 | return; | |
1022 | } | |
1023 | ||
1024 | if (old_view) { | |
1025 | flatview_ref(old_view); | |
1026 | } | |
1027 | ||
967dc9b1 | 1028 | flatview_ref(new_view); |
9a62e24f AK |
1029 | |
1030 | if (!QTAILQ_EMPTY(&as->listeners)) { | |
67ace39b AK |
1031 | FlatView tmpview = { .nr = 0 }, *old_view2 = old_view; |
1032 | ||
1033 | if (!old_view2) { | |
1034 | old_view2 = &tmpview; | |
1035 | } | |
1036 | address_space_update_topology_pass(as, old_view2, new_view, false); | |
1037 | address_space_update_topology_pass(as, old_view2, new_view, true); | |
9a62e24f | 1038 | } |
b8af1afb | 1039 | |
374f2981 PB |
1040 | /* Writes are protected by the BQL. */ |
1041 | atomic_rcu_set(&as->current_map, new_view); | |
67ace39b AK |
1042 | if (old_view) { |
1043 | flatview_unref(old_view); | |
1044 | } | |
856d7245 PB |
1045 | |
1046 | /* Note that all the old MemoryRegions are still alive up to this | |
1047 | * point. This relieves most MemoryListeners from the need to | |
1048 | * ref/unref the MemoryRegions they get---unless they use them | |
1049 | * outside the iothread mutex, in which case precise reference | |
1050 | * counting is necessary. | |
1051 | */ | |
67ace39b AK |
1052 | if (old_view) { |
1053 | flatview_unref(old_view); | |
1054 | } | |
093bc2cd AK |
1055 | } |
1056 | ||
202fc01b AK |
1057 | static void address_space_update_topology(AddressSpace *as) |
1058 | { | |
1059 | MemoryRegion *physmr = memory_region_get_flatview_root(as->root); | |
1060 | ||
1061 | flatviews_init(); | |
1062 | if (!g_hash_table_lookup(flat_views, physmr)) { | |
1063 | generate_memory_topology(physmr); | |
1064 | } | |
1065 | address_space_set_flatview(as); | |
1066 | } | |
1067 | ||
4ef4db86 AK |
1068 | void memory_region_transaction_begin(void) |
1069 | { | |
bb880ded | 1070 | qemu_flush_coalesced_mmio_buffer(); |
4ef4db86 AK |
1071 | ++memory_region_transaction_depth; |
1072 | } | |
1073 | ||
1074 | void memory_region_transaction_commit(void) | |
1075 | { | |
0d673e36 AK |
1076 | AddressSpace *as; |
1077 | ||
4ef4db86 | 1078 | assert(memory_region_transaction_depth); |
8d04fb55 JK |
1079 | assert(qemu_mutex_iothread_locked()); |
1080 | ||
4ef4db86 | 1081 | --memory_region_transaction_depth; |
4dc56152 GA |
1082 | if (!memory_region_transaction_depth) { |
1083 | if (memory_region_update_pending) { | |
967dc9b1 AK |
1084 | flatviews_reset(); |
1085 | ||
4dc56152 | 1086 | MEMORY_LISTENER_CALL_GLOBAL(begin, Forward); |
02e2b95f | 1087 | |
4dc56152 | 1088 | QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) { |
967dc9b1 | 1089 | address_space_set_flatview(as); |
02218487 | 1090 | address_space_update_ioeventfds(as); |
4dc56152 | 1091 | } |
ade9c1aa | 1092 | memory_region_update_pending = false; |
0b152095 | 1093 | ioeventfd_update_pending = false; |
4dc56152 GA |
1094 | MEMORY_LISTENER_CALL_GLOBAL(commit, Forward); |
1095 | } else if (ioeventfd_update_pending) { | |
1096 | QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) { | |
1097 | address_space_update_ioeventfds(as); | |
1098 | } | |
ade9c1aa | 1099 | ioeventfd_update_pending = false; |
4dc56152 | 1100 | } |
4dc56152 | 1101 | } |
4ef4db86 AK |
1102 | } |
1103 | ||
545e92e0 AK |
1104 | static void memory_region_destructor_none(MemoryRegion *mr) |
1105 | { | |
1106 | } | |
1107 | ||
1108 | static void memory_region_destructor_ram(MemoryRegion *mr) | |
1109 | { | |
f1060c55 | 1110 | qemu_ram_free(mr->ram_block); |
545e92e0 AK |
1111 | } |
1112 | ||
b4fefef9 PC |
1113 | static bool memory_region_need_escape(char c) |
1114 | { | |
1115 | return c == '/' || c == '[' || c == '\\' || c == ']'; | |
1116 | } | |
1117 | ||
1118 | static char *memory_region_escape_name(const char *name) | |
1119 | { | |
1120 | const char *p; | |
1121 | char *escaped, *q; | |
1122 | uint8_t c; | |
1123 | size_t bytes = 0; | |
1124 | ||
1125 | for (p = name; *p; p++) { | |
1126 | bytes += memory_region_need_escape(*p) ? 4 : 1; | |
1127 | } | |
1128 | if (bytes == p - name) { | |
1129 | return g_memdup(name, bytes + 1); | |
1130 | } | |
1131 | ||
1132 | escaped = g_malloc(bytes + 1); | |
1133 | for (p = name, q = escaped; *p; p++) { | |
1134 | c = *p; | |
1135 | if (unlikely(memory_region_need_escape(c))) { | |
1136 | *q++ = '\\'; | |
1137 | *q++ = 'x'; | |
1138 | *q++ = "0123456789abcdef"[c >> 4]; | |
1139 | c = "0123456789abcdef"[c & 15]; | |
1140 | } | |
1141 | *q++ = c; | |
1142 | } | |
1143 | *q = 0; | |
1144 | return escaped; | |
1145 | } | |
1146 | ||
3df9d748 AK |
1147 | static void memory_region_do_init(MemoryRegion *mr, |
1148 | Object *owner, | |
1149 | const char *name, | |
1150 | uint64_t size) | |
093bc2cd | 1151 | { |
08dafab4 AK |
1152 | mr->size = int128_make64(size); |
1153 | if (size == UINT64_MAX) { | |
1154 | mr->size = int128_2_64(); | |
1155 | } | |
302fa283 | 1156 | mr->name = g_strdup(name); |
612263cf | 1157 | mr->owner = owner; |
58eaa217 | 1158 | mr->ram_block = NULL; |
b4fefef9 PC |
1159 | |
1160 | if (name) { | |
843ef73a PC |
1161 | char *escaped_name = memory_region_escape_name(name); |
1162 | char *name_array = g_strdup_printf("%s[*]", escaped_name); | |
612263cf PB |
1163 | |
1164 | if (!owner) { | |
1165 | owner = container_get(qdev_get_machine(), "/unattached"); | |
1166 | } | |
1167 | ||
843ef73a | 1168 | object_property_add_child(owner, name_array, OBJECT(mr), &error_abort); |
b4fefef9 | 1169 | object_unref(OBJECT(mr)); |
843ef73a PC |
1170 | g_free(name_array); |
1171 | g_free(escaped_name); | |
b4fefef9 PC |
1172 | } |
1173 | } | |
1174 | ||
3df9d748 AK |
1175 | void memory_region_init(MemoryRegion *mr, |
1176 | Object *owner, | |
1177 | const char *name, | |
1178 | uint64_t size) | |
1179 | { | |
1180 | object_initialize(mr, sizeof(*mr), TYPE_MEMORY_REGION); | |
1181 | memory_region_do_init(mr, owner, name, size); | |
1182 | } | |
1183 | ||
d7bce999 EB |
1184 | static void memory_region_get_addr(Object *obj, Visitor *v, const char *name, |
1185 | void *opaque, Error **errp) | |
409ddd01 PC |
1186 | { |
1187 | MemoryRegion *mr = MEMORY_REGION(obj); | |
1188 | uint64_t value = mr->addr; | |
1189 | ||
51e72bc1 | 1190 | visit_type_uint64(v, name, &value, errp); |
409ddd01 PC |
1191 | } |
1192 | ||
d7bce999 EB |
1193 | static void memory_region_get_container(Object *obj, Visitor *v, |
1194 | const char *name, void *opaque, | |
1195 | Error **errp) | |
409ddd01 PC |
1196 | { |
1197 | MemoryRegion *mr = MEMORY_REGION(obj); | |
1198 | gchar *path = (gchar *)""; | |
1199 | ||
1200 | if (mr->container) { | |
1201 | path = object_get_canonical_path(OBJECT(mr->container)); | |
1202 | } | |
51e72bc1 | 1203 | visit_type_str(v, name, &path, errp); |
409ddd01 PC |
1204 | if (mr->container) { |
1205 | g_free(path); | |
1206 | } | |
1207 | } | |
1208 | ||
1209 | static Object *memory_region_resolve_container(Object *obj, void *opaque, | |
1210 | const char *part) | |
1211 | { | |
1212 | MemoryRegion *mr = MEMORY_REGION(obj); | |
1213 | ||
1214 | return OBJECT(mr->container); | |
1215 | } | |
1216 | ||
d7bce999 EB |
1217 | static void memory_region_get_priority(Object *obj, Visitor *v, |
1218 | const char *name, void *opaque, | |
1219 | Error **errp) | |
d33382da PC |
1220 | { |
1221 | MemoryRegion *mr = MEMORY_REGION(obj); | |
1222 | int32_t value = mr->priority; | |
1223 | ||
51e72bc1 | 1224 | visit_type_int32(v, name, &value, errp); |
d33382da PC |
1225 | } |
1226 | ||
d7bce999 EB |
1227 | static void memory_region_get_size(Object *obj, Visitor *v, const char *name, |
1228 | void *opaque, Error **errp) | |
52aef7bb PC |
1229 | { |
1230 | MemoryRegion *mr = MEMORY_REGION(obj); | |
1231 | uint64_t value = memory_region_size(mr); | |
1232 | ||
51e72bc1 | 1233 | visit_type_uint64(v, name, &value, errp); |
52aef7bb PC |
1234 | } |
1235 | ||
b4fefef9 PC |
1236 | static void memory_region_initfn(Object *obj) |
1237 | { | |
1238 | MemoryRegion *mr = MEMORY_REGION(obj); | |
409ddd01 | 1239 | ObjectProperty *op; |
b4fefef9 PC |
1240 | |
1241 | mr->ops = &unassigned_mem_ops; | |
6bba19ba | 1242 | mr->enabled = true; |
5f9a5ea1 | 1243 | mr->romd_mode = true; |
196ea131 | 1244 | mr->global_locking = true; |
545e92e0 | 1245 | mr->destructor = memory_region_destructor_none; |
093bc2cd | 1246 | QTAILQ_INIT(&mr->subregions); |
093bc2cd | 1247 | QTAILQ_INIT(&mr->coalesced); |
409ddd01 PC |
1248 | |
1249 | op = object_property_add(OBJECT(mr), "container", | |
1250 | "link<" TYPE_MEMORY_REGION ">", | |
1251 | memory_region_get_container, | |
1252 | NULL, /* memory_region_set_container */ | |
1253 | NULL, NULL, &error_abort); | |
1254 | op->resolve = memory_region_resolve_container; | |
1255 | ||
1256 | object_property_add(OBJECT(mr), "addr", "uint64", | |
1257 | memory_region_get_addr, | |
1258 | NULL, /* memory_region_set_addr */ | |
1259 | NULL, NULL, &error_abort); | |
d33382da PC |
1260 | object_property_add(OBJECT(mr), "priority", "uint32", |
1261 | memory_region_get_priority, | |
1262 | NULL, /* memory_region_set_priority */ | |
1263 | NULL, NULL, &error_abort); | |
52aef7bb PC |
1264 | object_property_add(OBJECT(mr), "size", "uint64", |
1265 | memory_region_get_size, | |
1266 | NULL, /* memory_region_set_size, */ | |
1267 | NULL, NULL, &error_abort); | |
093bc2cd AK |
1268 | } |
1269 | ||
3df9d748 AK |
1270 | static void iommu_memory_region_initfn(Object *obj) |
1271 | { | |
1272 | MemoryRegion *mr = MEMORY_REGION(obj); | |
1273 | ||
1274 | mr->is_iommu = true; | |
1275 | } | |
1276 | ||
b018ddf6 PB |
1277 | static uint64_t unassigned_mem_read(void *opaque, hwaddr addr, |
1278 | unsigned size) | |
1279 | { | |
1280 | #ifdef DEBUG_UNASSIGNED | |
1281 | printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); | |
1282 | #endif | |
4917cf44 | 1283 | if (current_cpu != NULL) { |
dbea78a4 PM |
1284 | bool is_exec = current_cpu->mem_io_access_type == MMU_INST_FETCH; |
1285 | cpu_unassigned_access(current_cpu, addr, false, is_exec, 0, size); | |
c658b94f | 1286 | } |
68a7439a | 1287 | return 0; |
b018ddf6 PB |
1288 | } |
1289 | ||
1290 | static void unassigned_mem_write(void *opaque, hwaddr addr, | |
1291 | uint64_t val, unsigned size) | |
1292 | { | |
1293 | #ifdef DEBUG_UNASSIGNED | |
1294 | printf("Unassigned mem write " TARGET_FMT_plx " = 0x%"PRIx64"\n", addr, val); | |
1295 | #endif | |
4917cf44 AF |
1296 | if (current_cpu != NULL) { |
1297 | cpu_unassigned_access(current_cpu, addr, true, false, 0, size); | |
c658b94f | 1298 | } |
b018ddf6 PB |
1299 | } |
1300 | ||
d197063f | 1301 | static bool unassigned_mem_accepts(void *opaque, hwaddr addr, |
8372d383 PM |
1302 | unsigned size, bool is_write, |
1303 | MemTxAttrs attrs) | |
d197063f PB |
1304 | { |
1305 | return false; | |
1306 | } | |
1307 | ||
1308 | const MemoryRegionOps unassigned_mem_ops = { | |
1309 | .valid.accepts = unassigned_mem_accepts, | |
1310 | .endianness = DEVICE_NATIVE_ENDIAN, | |
1311 | }; | |
1312 | ||
4a2e242b AW |
1313 | static uint64_t memory_region_ram_device_read(void *opaque, |
1314 | hwaddr addr, unsigned size) | |
1315 | { | |
1316 | MemoryRegion *mr = opaque; | |
1317 | uint64_t data = (uint64_t)~0; | |
1318 | ||
1319 | switch (size) { | |
1320 | case 1: | |
1321 | data = *(uint8_t *)(mr->ram_block->host + addr); | |
1322 | break; | |
1323 | case 2: | |
1324 | data = *(uint16_t *)(mr->ram_block->host + addr); | |
1325 | break; | |
1326 | case 4: | |
1327 | data = *(uint32_t *)(mr->ram_block->host + addr); | |
1328 | break; | |
1329 | case 8: | |
1330 | data = *(uint64_t *)(mr->ram_block->host + addr); | |
1331 | break; | |
1332 | } | |
1333 | ||
1334 | trace_memory_region_ram_device_read(get_cpu_index(), mr, addr, data, size); | |
1335 | ||
1336 | return data; | |
1337 | } | |
1338 | ||
1339 | static void memory_region_ram_device_write(void *opaque, hwaddr addr, | |
1340 | uint64_t data, unsigned size) | |
1341 | { | |
1342 | MemoryRegion *mr = opaque; | |
1343 | ||
1344 | trace_memory_region_ram_device_write(get_cpu_index(), mr, addr, data, size); | |
1345 | ||
1346 | switch (size) { | |
1347 | case 1: | |
1348 | *(uint8_t *)(mr->ram_block->host + addr) = (uint8_t)data; | |
1349 | break; | |
1350 | case 2: | |
1351 | *(uint16_t *)(mr->ram_block->host + addr) = (uint16_t)data; | |
1352 | break; | |
1353 | case 4: | |
1354 | *(uint32_t *)(mr->ram_block->host + addr) = (uint32_t)data; | |
1355 | break; | |
1356 | case 8: | |
1357 | *(uint64_t *)(mr->ram_block->host + addr) = data; | |
1358 | break; | |
1359 | } | |
1360 | } | |
1361 | ||
1362 | static const MemoryRegionOps ram_device_mem_ops = { | |
1363 | .read = memory_region_ram_device_read, | |
1364 | .write = memory_region_ram_device_write, | |
c99a29e7 | 1365 | .endianness = DEVICE_HOST_ENDIAN, |
4a2e242b AW |
1366 | .valid = { |
1367 | .min_access_size = 1, | |
1368 | .max_access_size = 8, | |
1369 | .unaligned = true, | |
1370 | }, | |
1371 | .impl = { | |
1372 | .min_access_size = 1, | |
1373 | .max_access_size = 8, | |
1374 | .unaligned = true, | |
1375 | }, | |
1376 | }; | |
1377 | ||
d2702032 PB |
1378 | bool memory_region_access_valid(MemoryRegion *mr, |
1379 | hwaddr addr, | |
1380 | unsigned size, | |
6d7b9a6c PM |
1381 | bool is_write, |
1382 | MemTxAttrs attrs) | |
093bc2cd | 1383 | { |
a014ed07 PB |
1384 | int access_size_min, access_size_max; |
1385 | int access_size, i; | |
897fa7cf | 1386 | |
093bc2cd AK |
1387 | if (!mr->ops->valid.unaligned && (addr & (size - 1))) { |
1388 | return false; | |
1389 | } | |
1390 | ||
a014ed07 | 1391 | if (!mr->ops->valid.accepts) { |
093bc2cd AK |
1392 | return true; |
1393 | } | |
1394 | ||
a014ed07 PB |
1395 | access_size_min = mr->ops->valid.min_access_size; |
1396 | if (!mr->ops->valid.min_access_size) { | |
1397 | access_size_min = 1; | |
1398 | } | |
1399 | ||
1400 | access_size_max = mr->ops->valid.max_access_size; | |
1401 | if (!mr->ops->valid.max_access_size) { | |
1402 | access_size_max = 4; | |
1403 | } | |
1404 | ||
1405 | access_size = MAX(MIN(size, access_size_max), access_size_min); | |
1406 | for (i = 0; i < size; i += access_size) { | |
1407 | if (!mr->ops->valid.accepts(mr->opaque, addr + i, access_size, | |
8372d383 | 1408 | is_write, attrs)) { |
a014ed07 PB |
1409 | return false; |
1410 | } | |
093bc2cd | 1411 | } |
a014ed07 | 1412 | |
093bc2cd AK |
1413 | return true; |
1414 | } | |
1415 | ||
cc05c43a PM |
1416 | static MemTxResult memory_region_dispatch_read1(MemoryRegion *mr, |
1417 | hwaddr addr, | |
1418 | uint64_t *pval, | |
1419 | unsigned size, | |
1420 | MemTxAttrs attrs) | |
093bc2cd | 1421 | { |
cc05c43a | 1422 | *pval = 0; |
093bc2cd | 1423 | |
ce5d2f33 | 1424 | if (mr->ops->read) { |
cc05c43a PM |
1425 | return access_with_adjusted_size(addr, pval, size, |
1426 | mr->ops->impl.min_access_size, | |
1427 | mr->ops->impl.max_access_size, | |
1428 | memory_region_read_accessor, | |
1429 | mr, attrs); | |
62a0db94 | 1430 | } else { |
cc05c43a PM |
1431 | return access_with_adjusted_size(addr, pval, size, |
1432 | mr->ops->impl.min_access_size, | |
1433 | mr->ops->impl.max_access_size, | |
1434 | memory_region_read_with_attrs_accessor, | |
1435 | mr, attrs); | |
74901c3b | 1436 | } |
093bc2cd AK |
1437 | } |
1438 | ||
3b643495 PM |
1439 | MemTxResult memory_region_dispatch_read(MemoryRegion *mr, |
1440 | hwaddr addr, | |
1441 | uint64_t *pval, | |
1442 | unsigned size, | |
1443 | MemTxAttrs attrs) | |
a621f38d | 1444 | { |
cc05c43a PM |
1445 | MemTxResult r; |
1446 | ||
6d7b9a6c | 1447 | if (!memory_region_access_valid(mr, addr, size, false, attrs)) { |
791af8c8 | 1448 | *pval = unassigned_mem_read(mr, addr, size); |
cc05c43a | 1449 | return MEMTX_DECODE_ERROR; |
791af8c8 | 1450 | } |
a621f38d | 1451 | |
cc05c43a | 1452 | r = memory_region_dispatch_read1(mr, addr, pval, size, attrs); |
791af8c8 | 1453 | adjust_endianness(mr, pval, size); |
cc05c43a | 1454 | return r; |
a621f38d | 1455 | } |
093bc2cd | 1456 | |
8c56c1a5 PF |
1457 | /* Return true if an eventfd was signalled */ |
1458 | static bool memory_region_dispatch_write_eventfds(MemoryRegion *mr, | |
1459 | hwaddr addr, | |
1460 | uint64_t data, | |
1461 | unsigned size, | |
1462 | MemTxAttrs attrs) | |
1463 | { | |
1464 | MemoryRegionIoeventfd ioeventfd = { | |
1465 | .addr = addrrange_make(int128_make64(addr), int128_make64(size)), | |
1466 | .data = data, | |
1467 | }; | |
1468 | unsigned i; | |
1469 | ||
1470 | for (i = 0; i < mr->ioeventfd_nb; i++) { | |
1471 | ioeventfd.match_data = mr->ioeventfds[i].match_data; | |
1472 | ioeventfd.e = mr->ioeventfds[i].e; | |
1473 | ||
73bb753d | 1474 | if (memory_region_ioeventfd_equal(&ioeventfd, &mr->ioeventfds[i])) { |
8c56c1a5 PF |
1475 | event_notifier_set(ioeventfd.e); |
1476 | return true; | |
1477 | } | |
1478 | } | |
1479 | ||
1480 | return false; | |
1481 | } | |
1482 | ||
3b643495 PM |
1483 | MemTxResult memory_region_dispatch_write(MemoryRegion *mr, |
1484 | hwaddr addr, | |
1485 | uint64_t data, | |
1486 | unsigned size, | |
1487 | MemTxAttrs attrs) | |
a621f38d | 1488 | { |
6d7b9a6c | 1489 | if (!memory_region_access_valid(mr, addr, size, true, attrs)) { |
b018ddf6 | 1490 | unassigned_mem_write(mr, addr, data, size); |
cc05c43a | 1491 | return MEMTX_DECODE_ERROR; |
093bc2cd AK |
1492 | } |
1493 | ||
a621f38d AK |
1494 | adjust_endianness(mr, &data, size); |
1495 | ||
8c56c1a5 PF |
1496 | if ((!kvm_eventfds_enabled()) && |
1497 | memory_region_dispatch_write_eventfds(mr, addr, data, size, attrs)) { | |
1498 | return MEMTX_OK; | |
1499 | } | |
1500 | ||
ce5d2f33 | 1501 | if (mr->ops->write) { |
cc05c43a PM |
1502 | return access_with_adjusted_size(addr, &data, size, |
1503 | mr->ops->impl.min_access_size, | |
1504 | mr->ops->impl.max_access_size, | |
1505 | memory_region_write_accessor, mr, | |
1506 | attrs); | |
62a0db94 | 1507 | } else { |
cc05c43a PM |
1508 | return |
1509 | access_with_adjusted_size(addr, &data, size, | |
1510 | mr->ops->impl.min_access_size, | |
1511 | mr->ops->impl.max_access_size, | |
1512 | memory_region_write_with_attrs_accessor, | |
1513 | mr, attrs); | |
74901c3b | 1514 | } |
093bc2cd AK |
1515 | } |
1516 | ||
093bc2cd | 1517 | void memory_region_init_io(MemoryRegion *mr, |
2c9b15ca | 1518 | Object *owner, |
093bc2cd AK |
1519 | const MemoryRegionOps *ops, |
1520 | void *opaque, | |
1521 | const char *name, | |
1522 | uint64_t size) | |
1523 | { | |
2c9b15ca | 1524 | memory_region_init(mr, owner, name, size); |
6d6d2abf | 1525 | mr->ops = ops ? ops : &unassigned_mem_ops; |
093bc2cd | 1526 | mr->opaque = opaque; |
14a3c10a | 1527 | mr->terminates = true; |
093bc2cd AK |
1528 | } |
1529 | ||
1cfe48c1 PM |
1530 | void memory_region_init_ram_nomigrate(MemoryRegion *mr, |
1531 | Object *owner, | |
1532 | const char *name, | |
1533 | uint64_t size, | |
1534 | Error **errp) | |
06329cce MA |
1535 | { |
1536 | memory_region_init_ram_shared_nomigrate(mr, owner, name, size, false, errp); | |
1537 | } | |
1538 | ||
1539 | void memory_region_init_ram_shared_nomigrate(MemoryRegion *mr, | |
1540 | Object *owner, | |
1541 | const char *name, | |
1542 | uint64_t size, | |
1543 | bool share, | |
1544 | Error **errp) | |
093bc2cd | 1545 | { |
1cd3d492 | 1546 | Error *err = NULL; |
2c9b15ca | 1547 | memory_region_init(mr, owner, name, size); |
8ea9252a | 1548 | mr->ram = true; |
14a3c10a | 1549 | mr->terminates = true; |
545e92e0 | 1550 | mr->destructor = memory_region_destructor_ram; |
1cd3d492 | 1551 | mr->ram_block = qemu_ram_alloc(size, share, mr, &err); |
677e7805 | 1552 | mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0; |
1cd3d492 IM |
1553 | if (err) { |
1554 | mr->size = int128_zero(); | |
1555 | object_unparent(OBJECT(mr)); | |
1556 | error_propagate(errp, err); | |
1557 | } | |
0b183fc8 PB |
1558 | } |
1559 | ||
60786ef3 MT |
1560 | void memory_region_init_resizeable_ram(MemoryRegion *mr, |
1561 | Object *owner, | |
1562 | const char *name, | |
1563 | uint64_t size, | |
1564 | uint64_t max_size, | |
1565 | void (*resized)(const char*, | |
1566 | uint64_t length, | |
1567 | void *host), | |
1568 | Error **errp) | |
1569 | { | |
1cd3d492 | 1570 | Error *err = NULL; |
60786ef3 MT |
1571 | memory_region_init(mr, owner, name, size); |
1572 | mr->ram = true; | |
1573 | mr->terminates = true; | |
1574 | mr->destructor = memory_region_destructor_ram; | |
8e41fb63 | 1575 | mr->ram_block = qemu_ram_alloc_resizeable(size, max_size, resized, |
1cd3d492 | 1576 | mr, &err); |
677e7805 | 1577 | mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0; |
1cd3d492 IM |
1578 | if (err) { |
1579 | mr->size = int128_zero(); | |
1580 | object_unparent(OBJECT(mr)); | |
1581 | error_propagate(errp, err); | |
1582 | } | |
60786ef3 MT |
1583 | } |
1584 | ||
d5dbde46 | 1585 | #ifdef CONFIG_POSIX |
0b183fc8 PB |
1586 | void memory_region_init_ram_from_file(MemoryRegion *mr, |
1587 | struct Object *owner, | |
1588 | const char *name, | |
1589 | uint64_t size, | |
98376843 | 1590 | uint64_t align, |
cbfc0171 | 1591 | uint32_t ram_flags, |
7f56e740 PB |
1592 | const char *path, |
1593 | Error **errp) | |
0b183fc8 | 1594 | { |
1cd3d492 | 1595 | Error *err = NULL; |
0b183fc8 PB |
1596 | memory_region_init(mr, owner, name, size); |
1597 | mr->ram = true; | |
1598 | mr->terminates = true; | |
1599 | mr->destructor = memory_region_destructor_ram; | |
98376843 | 1600 | mr->align = align; |
1cd3d492 | 1601 | mr->ram_block = qemu_ram_alloc_from_file(size, mr, ram_flags, path, &err); |
677e7805 | 1602 | mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0; |
1cd3d492 IM |
1603 | if (err) { |
1604 | mr->size = int128_zero(); | |
1605 | object_unparent(OBJECT(mr)); | |
1606 | error_propagate(errp, err); | |
1607 | } | |
093bc2cd | 1608 | } |
fea617c5 MAL |
1609 | |
1610 | void memory_region_init_ram_from_fd(MemoryRegion *mr, | |
1611 | struct Object *owner, | |
1612 | const char *name, | |
1613 | uint64_t size, | |
1614 | bool share, | |
1615 | int fd, | |
1616 | Error **errp) | |
1617 | { | |
1cd3d492 | 1618 | Error *err = NULL; |
fea617c5 MAL |
1619 | memory_region_init(mr, owner, name, size); |
1620 | mr->ram = true; | |
1621 | mr->terminates = true; | |
1622 | mr->destructor = memory_region_destructor_ram; | |
cbfc0171 JH |
1623 | mr->ram_block = qemu_ram_alloc_from_fd(size, mr, |
1624 | share ? RAM_SHARED : 0, | |
1cd3d492 | 1625 | fd, &err); |
fea617c5 | 1626 | mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0; |
1cd3d492 IM |
1627 | if (err) { |
1628 | mr->size = int128_zero(); | |
1629 | object_unparent(OBJECT(mr)); | |
1630 | error_propagate(errp, err); | |
1631 | } | |
fea617c5 | 1632 | } |
0b183fc8 | 1633 | #endif |
093bc2cd AK |
1634 | |
1635 | void memory_region_init_ram_ptr(MemoryRegion *mr, | |
2c9b15ca | 1636 | Object *owner, |
093bc2cd AK |
1637 | const char *name, |
1638 | uint64_t size, | |
1639 | void *ptr) | |
1640 | { | |
2c9b15ca | 1641 | memory_region_init(mr, owner, name, size); |
8ea9252a | 1642 | mr->ram = true; |
14a3c10a | 1643 | mr->terminates = true; |
fc3e7665 | 1644 | mr->destructor = memory_region_destructor_ram; |
677e7805 | 1645 | mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0; |
ef701d7b HT |
1646 | |
1647 | /* qemu_ram_alloc_from_ptr cannot fail with ptr != NULL. */ | |
1648 | assert(ptr != NULL); | |
8e41fb63 | 1649 | mr->ram_block = qemu_ram_alloc_from_ptr(size, ptr, mr, &error_fatal); |
093bc2cd AK |
1650 | } |
1651 | ||
21e00fa5 AW |
1652 | void memory_region_init_ram_device_ptr(MemoryRegion *mr, |
1653 | Object *owner, | |
1654 | const char *name, | |
1655 | uint64_t size, | |
1656 | void *ptr) | |
e4dc3f59 | 1657 | { |
2ddb89b0 BS |
1658 | memory_region_init(mr, owner, name, size); |
1659 | mr->ram = true; | |
1660 | mr->terminates = true; | |
21e00fa5 | 1661 | mr->ram_device = true; |
4a2e242b AW |
1662 | mr->ops = &ram_device_mem_ops; |
1663 | mr->opaque = mr; | |
2ddb89b0 BS |
1664 | mr->destructor = memory_region_destructor_ram; |
1665 | mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0; | |
1666 | /* qemu_ram_alloc_from_ptr cannot fail with ptr != NULL. */ | |
1667 | assert(ptr != NULL); | |
1668 | mr->ram_block = qemu_ram_alloc_from_ptr(size, ptr, mr, &error_fatal); | |
e4dc3f59 ND |
1669 | } |
1670 | ||
093bc2cd | 1671 | void memory_region_init_alias(MemoryRegion *mr, |
2c9b15ca | 1672 | Object *owner, |
093bc2cd AK |
1673 | const char *name, |
1674 | MemoryRegion *orig, | |
a8170e5e | 1675 | hwaddr offset, |
093bc2cd AK |
1676 | uint64_t size) |
1677 | { | |
2c9b15ca | 1678 | memory_region_init(mr, owner, name, size); |
093bc2cd AK |
1679 | mr->alias = orig; |
1680 | mr->alias_offset = offset; | |
1681 | } | |
1682 | ||
b59821a9 PM |
1683 | void memory_region_init_rom_nomigrate(MemoryRegion *mr, |
1684 | struct Object *owner, | |
1685 | const char *name, | |
1686 | uint64_t size, | |
1687 | Error **errp) | |
a1777f7f | 1688 | { |
1cd3d492 | 1689 | Error *err = NULL; |
a1777f7f PM |
1690 | memory_region_init(mr, owner, name, size); |
1691 | mr->ram = true; | |
1692 | mr->readonly = true; | |
1693 | mr->terminates = true; | |
1694 | mr->destructor = memory_region_destructor_ram; | |
1cd3d492 | 1695 | mr->ram_block = qemu_ram_alloc(size, false, mr, &err); |
a1777f7f | 1696 | mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0; |
1cd3d492 IM |
1697 | if (err) { |
1698 | mr->size = int128_zero(); | |
1699 | object_unparent(OBJECT(mr)); | |
1700 | error_propagate(errp, err); | |
1701 | } | |
a1777f7f PM |
1702 | } |
1703 | ||
b59821a9 PM |
1704 | void memory_region_init_rom_device_nomigrate(MemoryRegion *mr, |
1705 | Object *owner, | |
1706 | const MemoryRegionOps *ops, | |
1707 | void *opaque, | |
1708 | const char *name, | |
1709 | uint64_t size, | |
1710 | Error **errp) | |
d0a9b5bc | 1711 | { |
1cd3d492 | 1712 | Error *err = NULL; |
39e0b03d | 1713 | assert(ops); |
2c9b15ca | 1714 | memory_region_init(mr, owner, name, size); |
7bc2b9cd | 1715 | mr->ops = ops; |
75f5941c | 1716 | mr->opaque = opaque; |
d0a9b5bc | 1717 | mr->terminates = true; |
75c578dc | 1718 | mr->rom_device = true; |
58268c8d | 1719 | mr->destructor = memory_region_destructor_ram; |
1cd3d492 IM |
1720 | mr->ram_block = qemu_ram_alloc(size, false, mr, &err); |
1721 | if (err) { | |
1722 | mr->size = int128_zero(); | |
1723 | object_unparent(OBJECT(mr)); | |
1724 | error_propagate(errp, err); | |
1725 | } | |
d0a9b5bc AK |
1726 | } |
1727 | ||
1221a474 AK |
1728 | void memory_region_init_iommu(void *_iommu_mr, |
1729 | size_t instance_size, | |
1730 | const char *mrtypename, | |
2c9b15ca | 1731 | Object *owner, |
30951157 AK |
1732 | const char *name, |
1733 | uint64_t size) | |
1734 | { | |
1221a474 | 1735 | struct IOMMUMemoryRegion *iommu_mr; |
3df9d748 AK |
1736 | struct MemoryRegion *mr; |
1737 | ||
1221a474 AK |
1738 | object_initialize(_iommu_mr, instance_size, mrtypename); |
1739 | mr = MEMORY_REGION(_iommu_mr); | |
3df9d748 AK |
1740 | memory_region_do_init(mr, owner, name, size); |
1741 | iommu_mr = IOMMU_MEMORY_REGION(mr); | |
30951157 | 1742 | mr->terminates = true; /* then re-forwards */ |
3df9d748 AK |
1743 | QLIST_INIT(&iommu_mr->iommu_notify); |
1744 | iommu_mr->iommu_notify_flags = IOMMU_NOTIFIER_NONE; | |
30951157 AK |
1745 | } |
1746 | ||
b4fefef9 | 1747 | static void memory_region_finalize(Object *obj) |
093bc2cd | 1748 | { |
b4fefef9 PC |
1749 | MemoryRegion *mr = MEMORY_REGION(obj); |
1750 | ||
2e2b8eb7 PB |
1751 | assert(!mr->container); |
1752 | ||
1753 | /* We know the region is not visible in any address space (it | |
1754 | * does not have a container and cannot be a root either because | |
1755 | * it has no references, so we can blindly clear mr->enabled. | |
1756 | * memory_region_set_enabled instead could trigger a transaction | |
1757 | * and cause an infinite loop. | |
1758 | */ | |
1759 | mr->enabled = false; | |
1760 | memory_region_transaction_begin(); | |
1761 | while (!QTAILQ_EMPTY(&mr->subregions)) { | |
1762 | MemoryRegion *subregion = QTAILQ_FIRST(&mr->subregions); | |
1763 | memory_region_del_subregion(mr, subregion); | |
1764 | } | |
1765 | memory_region_transaction_commit(); | |
1766 | ||
545e92e0 | 1767 | mr->destructor(mr); |
093bc2cd | 1768 | memory_region_clear_coalescing(mr); |
302fa283 | 1769 | g_free((char *)mr->name); |
7267c094 | 1770 | g_free(mr->ioeventfds); |
093bc2cd AK |
1771 | } |
1772 | ||
803c0816 PB |
1773 | Object *memory_region_owner(MemoryRegion *mr) |
1774 | { | |
22a893e4 PB |
1775 | Object *obj = OBJECT(mr); |
1776 | return obj->parent; | |
803c0816 PB |
1777 | } |
1778 | ||
46637be2 PB |
1779 | void memory_region_ref(MemoryRegion *mr) |
1780 | { | |
22a893e4 PB |
1781 | /* MMIO callbacks most likely will access data that belongs |
1782 | * to the owner, hence the need to ref/unref the owner whenever | |
1783 | * the memory region is in use. | |
1784 | * | |
1785 | * The memory region is a child of its owner. As long as the | |
1786 | * owner doesn't call unparent itself on the memory region, | |
1787 | * ref-ing the owner will also keep the memory region alive. | |
612263cf PB |
1788 | * Memory regions without an owner are supposed to never go away; |
1789 | * we do not ref/unref them because it slows down DMA sensibly. | |
22a893e4 | 1790 | */ |
612263cf PB |
1791 | if (mr && mr->owner) { |
1792 | object_ref(mr->owner); | |
46637be2 PB |
1793 | } |
1794 | } | |
1795 | ||
1796 | void memory_region_unref(MemoryRegion *mr) | |
1797 | { | |
612263cf PB |
1798 | if (mr && mr->owner) { |
1799 | object_unref(mr->owner); | |
46637be2 PB |
1800 | } |
1801 | } | |
1802 | ||
093bc2cd AK |
1803 | uint64_t memory_region_size(MemoryRegion *mr) |
1804 | { | |
08dafab4 AK |
1805 | if (int128_eq(mr->size, int128_2_64())) { |
1806 | return UINT64_MAX; | |
1807 | } | |
1808 | return int128_get64(mr->size); | |
093bc2cd AK |
1809 | } |
1810 | ||
5d546d4b | 1811 | const char *memory_region_name(const MemoryRegion *mr) |
8991c79b | 1812 | { |
d1dd32af PC |
1813 | if (!mr->name) { |
1814 | ((MemoryRegion *)mr)->name = | |
1815 | object_get_canonical_path_component(OBJECT(mr)); | |
1816 | } | |
302fa283 | 1817 | return mr->name; |
8991c79b AK |
1818 | } |
1819 | ||
21e00fa5 | 1820 | bool memory_region_is_ram_device(MemoryRegion *mr) |
e4dc3f59 | 1821 | { |
21e00fa5 | 1822 | return mr->ram_device; |
e4dc3f59 ND |
1823 | } |
1824 | ||
2d1a35be | 1825 | uint8_t memory_region_get_dirty_log_mask(MemoryRegion *mr) |
55043ba3 | 1826 | { |
6f6a5ef3 | 1827 | uint8_t mask = mr->dirty_log_mask; |
adaad61c | 1828 | if (global_dirty_log && mr->ram_block) { |
6f6a5ef3 PB |
1829 | mask |= (1 << DIRTY_MEMORY_MIGRATION); |
1830 | } | |
1831 | return mask; | |
55043ba3 AK |
1832 | } |
1833 | ||
2d1a35be PB |
1834 | bool memory_region_is_logging(MemoryRegion *mr, uint8_t client) |
1835 | { | |
1836 | return memory_region_get_dirty_log_mask(mr) & (1 << client); | |
1837 | } | |
1838 | ||
3df9d748 | 1839 | static void memory_region_update_iommu_notify_flags(IOMMUMemoryRegion *iommu_mr) |
5bf3d319 PX |
1840 | { |
1841 | IOMMUNotifierFlag flags = IOMMU_NOTIFIER_NONE; | |
1842 | IOMMUNotifier *iommu_notifier; | |
1221a474 | 1843 | IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr); |
5bf3d319 | 1844 | |
3df9d748 | 1845 | IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) { |
5bf3d319 PX |
1846 | flags |= iommu_notifier->notifier_flags; |
1847 | } | |
1848 | ||
1221a474 AK |
1849 | if (flags != iommu_mr->iommu_notify_flags && imrc->notify_flag_changed) { |
1850 | imrc->notify_flag_changed(iommu_mr, | |
1851 | iommu_mr->iommu_notify_flags, | |
1852 | flags); | |
5bf3d319 PX |
1853 | } |
1854 | ||
3df9d748 | 1855 | iommu_mr->iommu_notify_flags = flags; |
5bf3d319 PX |
1856 | } |
1857 | ||
cdb30812 PX |
1858 | void memory_region_register_iommu_notifier(MemoryRegion *mr, |
1859 | IOMMUNotifier *n) | |
06866575 | 1860 | { |
3df9d748 AK |
1861 | IOMMUMemoryRegion *iommu_mr; |
1862 | ||
efcd38c5 JW |
1863 | if (mr->alias) { |
1864 | memory_region_register_iommu_notifier(mr->alias, n); | |
1865 | return; | |
1866 | } | |
1867 | ||
cdb30812 | 1868 | /* We need to register for at least one bitfield */ |
3df9d748 | 1869 | iommu_mr = IOMMU_MEMORY_REGION(mr); |
cdb30812 | 1870 | assert(n->notifier_flags != IOMMU_NOTIFIER_NONE); |
698feb5e | 1871 | assert(n->start <= n->end); |
cb1efcf4 PM |
1872 | assert(n->iommu_idx >= 0 && |
1873 | n->iommu_idx < memory_region_iommu_num_indexes(iommu_mr)); | |
1874 | ||
3df9d748 AK |
1875 | QLIST_INSERT_HEAD(&iommu_mr->iommu_notify, n, node); |
1876 | memory_region_update_iommu_notify_flags(iommu_mr); | |
06866575 DG |
1877 | } |
1878 | ||
3df9d748 | 1879 | uint64_t memory_region_iommu_get_min_page_size(IOMMUMemoryRegion *iommu_mr) |
a788f227 | 1880 | { |
1221a474 AK |
1881 | IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr); |
1882 | ||
1883 | if (imrc->get_min_page_size) { | |
1884 | return imrc->get_min_page_size(iommu_mr); | |
f682e9c2 AK |
1885 | } |
1886 | return TARGET_PAGE_SIZE; | |
1887 | } | |
1888 | ||
3df9d748 | 1889 | void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n) |
f682e9c2 | 1890 | { |
3df9d748 | 1891 | MemoryRegion *mr = MEMORY_REGION(iommu_mr); |
1221a474 | 1892 | IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr); |
f682e9c2 | 1893 | hwaddr addr, granularity; |
a788f227 DG |
1894 | IOMMUTLBEntry iotlb; |
1895 | ||
faa362e3 | 1896 | /* If the IOMMU has its own replay callback, override */ |
1221a474 AK |
1897 | if (imrc->replay) { |
1898 | imrc->replay(iommu_mr, n); | |
faa362e3 PX |
1899 | return; |
1900 | } | |
1901 | ||
3df9d748 | 1902 | granularity = memory_region_iommu_get_min_page_size(iommu_mr); |
f682e9c2 | 1903 | |
a788f227 | 1904 | for (addr = 0; addr < memory_region_size(mr); addr += granularity) { |
2c91bcf2 | 1905 | iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE, n->iommu_idx); |
a788f227 DG |
1906 | if (iotlb.perm != IOMMU_NONE) { |
1907 | n->notify(n, &iotlb); | |
1908 | } | |
1909 | ||
1910 | /* if (2^64 - MR size) < granularity, it's possible to get an | |
1911 | * infinite loop here. This should catch such a wraparound */ | |
1912 | if ((addr + granularity) < addr) { | |
1913 | break; | |
1914 | } | |
1915 | } | |
1916 | } | |
1917 | ||
3df9d748 | 1918 | void memory_region_iommu_replay_all(IOMMUMemoryRegion *iommu_mr) |
de472e4a PX |
1919 | { |
1920 | IOMMUNotifier *notifier; | |
1921 | ||
3df9d748 AK |
1922 | IOMMU_NOTIFIER_FOREACH(notifier, iommu_mr) { |
1923 | memory_region_iommu_replay(iommu_mr, notifier); | |
de472e4a PX |
1924 | } |
1925 | } | |
1926 | ||
cdb30812 PX |
1927 | void memory_region_unregister_iommu_notifier(MemoryRegion *mr, |
1928 | IOMMUNotifier *n) | |
06866575 | 1929 | { |
3df9d748 AK |
1930 | IOMMUMemoryRegion *iommu_mr; |
1931 | ||
efcd38c5 JW |
1932 | if (mr->alias) { |
1933 | memory_region_unregister_iommu_notifier(mr->alias, n); | |
1934 | return; | |
1935 | } | |
cdb30812 | 1936 | QLIST_REMOVE(n, node); |
3df9d748 AK |
1937 | iommu_mr = IOMMU_MEMORY_REGION(mr); |
1938 | memory_region_update_iommu_notify_flags(iommu_mr); | |
06866575 DG |
1939 | } |
1940 | ||
bd2bfa4c PX |
1941 | void memory_region_notify_one(IOMMUNotifier *notifier, |
1942 | IOMMUTLBEntry *entry) | |
06866575 | 1943 | { |
cdb30812 PX |
1944 | IOMMUNotifierFlag request_flags; |
1945 | ||
bd2bfa4c PX |
1946 | /* |
1947 | * Skip the notification if the notification does not overlap | |
1948 | * with registered range. | |
1949 | */ | |
b021d1c0 | 1950 | if (notifier->start > entry->iova + entry->addr_mask || |
bd2bfa4c PX |
1951 | notifier->end < entry->iova) { |
1952 | return; | |
1953 | } | |
cdb30812 | 1954 | |
bd2bfa4c | 1955 | if (entry->perm & IOMMU_RW) { |
cdb30812 PX |
1956 | request_flags = IOMMU_NOTIFIER_MAP; |
1957 | } else { | |
1958 | request_flags = IOMMU_NOTIFIER_UNMAP; | |
1959 | } | |
1960 | ||
bd2bfa4c PX |
1961 | if (notifier->notifier_flags & request_flags) { |
1962 | notifier->notify(notifier, entry); | |
1963 | } | |
1964 | } | |
1965 | ||
3df9d748 | 1966 | void memory_region_notify_iommu(IOMMUMemoryRegion *iommu_mr, |
cb1efcf4 | 1967 | int iommu_idx, |
bd2bfa4c PX |
1968 | IOMMUTLBEntry entry) |
1969 | { | |
1970 | IOMMUNotifier *iommu_notifier; | |
1971 | ||
3df9d748 | 1972 | assert(memory_region_is_iommu(MEMORY_REGION(iommu_mr))); |
bd2bfa4c | 1973 | |
3df9d748 | 1974 | IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) { |
cb1efcf4 PM |
1975 | if (iommu_notifier->iommu_idx == iommu_idx) { |
1976 | memory_region_notify_one(iommu_notifier, &entry); | |
1977 | } | |
cdb30812 | 1978 | } |
06866575 DG |
1979 | } |
1980 | ||
f1334de6 AK |
1981 | int memory_region_iommu_get_attr(IOMMUMemoryRegion *iommu_mr, |
1982 | enum IOMMUMemoryRegionAttr attr, | |
1983 | void *data) | |
1984 | { | |
1985 | IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr); | |
1986 | ||
1987 | if (!imrc->get_attr) { | |
1988 | return -EINVAL; | |
1989 | } | |
1990 | ||
1991 | return imrc->get_attr(iommu_mr, attr, data); | |
1992 | } | |
1993 | ||
21f40209 PM |
1994 | int memory_region_iommu_attrs_to_index(IOMMUMemoryRegion *iommu_mr, |
1995 | MemTxAttrs attrs) | |
1996 | { | |
1997 | IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr); | |
1998 | ||
1999 | if (!imrc->attrs_to_index) { | |
2000 | return 0; | |
2001 | } | |
2002 | ||
2003 | return imrc->attrs_to_index(iommu_mr, attrs); | |
2004 | } | |
2005 | ||
2006 | int memory_region_iommu_num_indexes(IOMMUMemoryRegion *iommu_mr) | |
2007 | { | |
2008 | IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr); | |
2009 | ||
2010 | if (!imrc->num_indexes) { | |
2011 | return 1; | |
2012 | } | |
2013 | ||
2014 | return imrc->num_indexes(iommu_mr); | |
2015 | } | |
2016 | ||
093bc2cd AK |
2017 | void memory_region_set_log(MemoryRegion *mr, bool log, unsigned client) |
2018 | { | |
5a583347 | 2019 | uint8_t mask = 1 << client; |
deb809ed | 2020 | uint8_t old_logging; |
5a583347 | 2021 | |
dbddac6d | 2022 | assert(client == DIRTY_MEMORY_VGA); |
deb809ed PB |
2023 | old_logging = mr->vga_logging_count; |
2024 | mr->vga_logging_count += log ? 1 : -1; | |
2025 | if (!!old_logging == !!mr->vga_logging_count) { | |
2026 | return; | |
2027 | } | |
2028 | ||
59023ef4 | 2029 | memory_region_transaction_begin(); |
5a583347 | 2030 | mr->dirty_log_mask = (mr->dirty_log_mask & ~mask) | (log * mask); |
22bde714 | 2031 | memory_region_update_pending |= mr->enabled; |
59023ef4 | 2032 | memory_region_transaction_commit(); |
093bc2cd AK |
2033 | } |
2034 | ||
a8170e5e AK |
2035 | void memory_region_set_dirty(MemoryRegion *mr, hwaddr addr, |
2036 | hwaddr size) | |
093bc2cd | 2037 | { |
8e41fb63 FZ |
2038 | assert(mr->ram_block); |
2039 | cpu_physical_memory_set_dirty_range(memory_region_get_ram_addr(mr) + addr, | |
2040 | size, | |
58d2707e | 2041 | memory_region_get_dirty_log_mask(mr)); |
093bc2cd AK |
2042 | } |
2043 | ||
0fe1eca7 | 2044 | static void memory_region_sync_dirty_bitmap(MemoryRegion *mr) |
093bc2cd | 2045 | { |
0a752eee | 2046 | MemoryListener *listener; |
0d673e36 | 2047 | AddressSpace *as; |
0a752eee | 2048 | FlatView *view; |
5a583347 AK |
2049 | FlatRange *fr; |
2050 | ||
0a752eee PB |
2051 | /* If the same address space has multiple log_sync listeners, we |
2052 | * visit that address space's FlatView multiple times. But because | |
2053 | * log_sync listeners are rare, it's still cheaper than walking each | |
2054 | * address space once. | |
2055 | */ | |
2056 | QTAILQ_FOREACH(listener, &memory_listeners, link) { | |
2057 | if (!listener->log_sync) { | |
2058 | continue; | |
2059 | } | |
2060 | as = listener->address_space; | |
2061 | view = address_space_get_flatview(as); | |
99e86347 | 2062 | FOR_EACH_FLAT_RANGE(fr, view) { |
3ebb1817 | 2063 | if (fr->dirty_log_mask && (!mr || fr->mr == mr)) { |
16620684 | 2064 | MemoryRegionSection mrs = section_from_flat_range(fr, view); |
0a752eee | 2065 | listener->log_sync(listener, &mrs); |
0d673e36 | 2066 | } |
5a583347 | 2067 | } |
856d7245 | 2068 | flatview_unref(view); |
5a583347 | 2069 | } |
093bc2cd AK |
2070 | } |
2071 | ||
077874e0 PX |
2072 | void memory_region_clear_dirty_bitmap(MemoryRegion *mr, hwaddr start, |
2073 | hwaddr len) | |
2074 | { | |
2075 | MemoryRegionSection mrs; | |
2076 | MemoryListener *listener; | |
2077 | AddressSpace *as; | |
2078 | FlatView *view; | |
2079 | FlatRange *fr; | |
2080 | hwaddr sec_start, sec_end, sec_size; | |
2081 | ||
2082 | QTAILQ_FOREACH(listener, &memory_listeners, link) { | |
2083 | if (!listener->log_clear) { | |
2084 | continue; | |
2085 | } | |
2086 | as = listener->address_space; | |
2087 | view = address_space_get_flatview(as); | |
2088 | FOR_EACH_FLAT_RANGE(fr, view) { | |
2089 | if (!fr->dirty_log_mask || fr->mr != mr) { | |
2090 | /* | |
2091 | * Clear dirty bitmap operation only applies to those | |
2092 | * regions whose dirty logging is at least enabled | |
2093 | */ | |
2094 | continue; | |
2095 | } | |
2096 | ||
2097 | mrs = section_from_flat_range(fr, view); | |
2098 | ||
2099 | sec_start = MAX(mrs.offset_within_region, start); | |
2100 | sec_end = mrs.offset_within_region + int128_get64(mrs.size); | |
2101 | sec_end = MIN(sec_end, start + len); | |
2102 | ||
2103 | if (sec_start >= sec_end) { | |
2104 | /* | |
2105 | * If this memory region section has no intersection | |
2106 | * with the requested range, skip. | |
2107 | */ | |
2108 | continue; | |
2109 | } | |
2110 | ||
2111 | /* Valid case; shrink the section if needed */ | |
2112 | mrs.offset_within_address_space += | |
2113 | sec_start - mrs.offset_within_region; | |
2114 | mrs.offset_within_region = sec_start; | |
2115 | sec_size = sec_end - sec_start; | |
2116 | mrs.size = int128_make64(sec_size); | |
2117 | listener->log_clear(listener, &mrs); | |
2118 | } | |
2119 | flatview_unref(view); | |
2120 | } | |
2121 | } | |
2122 | ||
0fe1eca7 PB |
2123 | DirtyBitmapSnapshot *memory_region_snapshot_and_clear_dirty(MemoryRegion *mr, |
2124 | hwaddr addr, | |
2125 | hwaddr size, | |
2126 | unsigned client) | |
2127 | { | |
2128 | assert(mr->ram_block); | |
2129 | memory_region_sync_dirty_bitmap(mr); | |
5dea4079 | 2130 | return cpu_physical_memory_snapshot_and_clear_dirty(mr, addr, size, client); |
0fe1eca7 PB |
2131 | } |
2132 | ||
2133 | bool memory_region_snapshot_get_dirty(MemoryRegion *mr, DirtyBitmapSnapshot *snap, | |
2134 | hwaddr addr, hwaddr size) | |
2135 | { | |
2136 | assert(mr->ram_block); | |
2137 | return cpu_physical_memory_snapshot_get_dirty(snap, | |
2138 | memory_region_get_ram_addr(mr) + addr, size); | |
2139 | } | |
2140 | ||
093bc2cd AK |
2141 | void memory_region_set_readonly(MemoryRegion *mr, bool readonly) |
2142 | { | |
fb1cd6f9 | 2143 | if (mr->readonly != readonly) { |
59023ef4 | 2144 | memory_region_transaction_begin(); |
fb1cd6f9 | 2145 | mr->readonly = readonly; |
22bde714 | 2146 | memory_region_update_pending |= mr->enabled; |
59023ef4 | 2147 | memory_region_transaction_commit(); |
fb1cd6f9 | 2148 | } |
093bc2cd AK |
2149 | } |
2150 | ||
c26763f8 MAL |
2151 | void memory_region_set_nonvolatile(MemoryRegion *mr, bool nonvolatile) |
2152 | { | |
2153 | if (mr->nonvolatile != nonvolatile) { | |
2154 | memory_region_transaction_begin(); | |
2155 | mr->nonvolatile = nonvolatile; | |
2156 | memory_region_update_pending |= mr->enabled; | |
2157 | memory_region_transaction_commit(); | |
2158 | } | |
2159 | } | |
2160 | ||
5f9a5ea1 | 2161 | void memory_region_rom_device_set_romd(MemoryRegion *mr, bool romd_mode) |
d0a9b5bc | 2162 | { |
5f9a5ea1 | 2163 | if (mr->romd_mode != romd_mode) { |
59023ef4 | 2164 | memory_region_transaction_begin(); |
5f9a5ea1 | 2165 | mr->romd_mode = romd_mode; |
22bde714 | 2166 | memory_region_update_pending |= mr->enabled; |
59023ef4 | 2167 | memory_region_transaction_commit(); |
d0a9b5bc AK |
2168 | } |
2169 | } | |
2170 | ||
a8170e5e AK |
2171 | void memory_region_reset_dirty(MemoryRegion *mr, hwaddr addr, |
2172 | hwaddr size, unsigned client) | |
093bc2cd | 2173 | { |
8e41fb63 FZ |
2174 | assert(mr->ram_block); |
2175 | cpu_physical_memory_test_and_clear_dirty( | |
2176 | memory_region_get_ram_addr(mr) + addr, size, client); | |
093bc2cd AK |
2177 | } |
2178 | ||
a35ba7be PB |
2179 | int memory_region_get_fd(MemoryRegion *mr) |
2180 | { | |
4ff87573 PB |
2181 | int fd; |
2182 | ||
2183 | rcu_read_lock(); | |
2184 | while (mr->alias) { | |
2185 | mr = mr->alias; | |
a35ba7be | 2186 | } |
4ff87573 PB |
2187 | fd = mr->ram_block->fd; |
2188 | rcu_read_unlock(); | |
a35ba7be | 2189 | |
4ff87573 PB |
2190 | return fd; |
2191 | } | |
a35ba7be | 2192 | |
093bc2cd AK |
2193 | void *memory_region_get_ram_ptr(MemoryRegion *mr) |
2194 | { | |
49b24afc PB |
2195 | void *ptr; |
2196 | uint64_t offset = 0; | |
093bc2cd | 2197 | |
49b24afc PB |
2198 | rcu_read_lock(); |
2199 | while (mr->alias) { | |
2200 | offset += mr->alias_offset; | |
2201 | mr = mr->alias; | |
2202 | } | |
8e41fb63 | 2203 | assert(mr->ram_block); |
0878d0e1 | 2204 | ptr = qemu_map_ram_ptr(mr->ram_block, offset); |
49b24afc | 2205 | rcu_read_unlock(); |
093bc2cd | 2206 | |
0878d0e1 | 2207 | return ptr; |
093bc2cd AK |
2208 | } |
2209 | ||
07bdaa41 PB |
2210 | MemoryRegion *memory_region_from_host(void *ptr, ram_addr_t *offset) |
2211 | { | |
2212 | RAMBlock *block; | |
2213 | ||
2214 | block = qemu_ram_block_from_host(ptr, false, offset); | |
2215 | if (!block) { | |
2216 | return NULL; | |
2217 | } | |
2218 | ||
2219 | return block->mr; | |
2220 | } | |
2221 | ||
7ebb2745 FZ |
2222 | ram_addr_t memory_region_get_ram_addr(MemoryRegion *mr) |
2223 | { | |
2224 | return mr->ram_block ? mr->ram_block->offset : RAM_ADDR_INVALID; | |
2225 | } | |
2226 | ||
37d7c084 PB |
2227 | void memory_region_ram_resize(MemoryRegion *mr, ram_addr_t newsize, Error **errp) |
2228 | { | |
8e41fb63 | 2229 | assert(mr->ram_block); |
37d7c084 | 2230 | |
fa53a0e5 | 2231 | qemu_ram_resize(mr->ram_block, newsize, errp); |
37d7c084 PB |
2232 | } |
2233 | ||
0d673e36 | 2234 | static void memory_region_update_coalesced_range_as(MemoryRegion *mr, AddressSpace *as) |
093bc2cd | 2235 | { |
99e86347 | 2236 | FlatView *view; |
093bc2cd | 2237 | FlatRange *fr; |
093bc2cd | 2238 | |
856d7245 | 2239 | view = address_space_get_flatview(as); |
99e86347 | 2240 | FOR_EACH_FLAT_RANGE(fr, view) { |
093bc2cd | 2241 | if (fr->mr == mr) { |
909bf763 PB |
2242 | flat_range_coalesced_io_del(fr, as); |
2243 | flat_range_coalesced_io_add(fr, as); | |
093bc2cd AK |
2244 | } |
2245 | } | |
856d7245 | 2246 | flatview_unref(view); |
093bc2cd AK |
2247 | } |
2248 | ||
0d673e36 AK |
2249 | static void memory_region_update_coalesced_range(MemoryRegion *mr) |
2250 | { | |
2251 | AddressSpace *as; | |
2252 | ||
2253 | QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) { | |
2254 | memory_region_update_coalesced_range_as(mr, as); | |
2255 | } | |
2256 | } | |
2257 | ||
093bc2cd AK |
2258 | void memory_region_set_coalescing(MemoryRegion *mr) |
2259 | { | |
2260 | memory_region_clear_coalescing(mr); | |
08dafab4 | 2261 | memory_region_add_coalescing(mr, 0, int128_get64(mr->size)); |
093bc2cd AK |
2262 | } |
2263 | ||
2264 | void memory_region_add_coalescing(MemoryRegion *mr, | |
a8170e5e | 2265 | hwaddr offset, |
093bc2cd AK |
2266 | uint64_t size) |
2267 | { | |
7267c094 | 2268 | CoalescedMemoryRange *cmr = g_malloc(sizeof(*cmr)); |
093bc2cd | 2269 | |
08dafab4 | 2270 | cmr->addr = addrrange_make(int128_make64(offset), int128_make64(size)); |
093bc2cd AK |
2271 | QTAILQ_INSERT_TAIL(&mr->coalesced, cmr, link); |
2272 | memory_region_update_coalesced_range(mr); | |
d410515e | 2273 | memory_region_set_flush_coalesced(mr); |
093bc2cd AK |
2274 | } |
2275 | ||
2276 | void memory_region_clear_coalescing(MemoryRegion *mr) | |
2277 | { | |
2278 | CoalescedMemoryRange *cmr; | |
ab5b3db5 | 2279 | bool updated = false; |
093bc2cd | 2280 | |
d410515e JK |
2281 | qemu_flush_coalesced_mmio_buffer(); |
2282 | mr->flush_coalesced_mmio = false; | |
2283 | ||
093bc2cd AK |
2284 | while (!QTAILQ_EMPTY(&mr->coalesced)) { |
2285 | cmr = QTAILQ_FIRST(&mr->coalesced); | |
2286 | QTAILQ_REMOVE(&mr->coalesced, cmr, link); | |
7267c094 | 2287 | g_free(cmr); |
ab5b3db5 FZ |
2288 | updated = true; |
2289 | } | |
2290 | ||
2291 | if (updated) { | |
2292 | memory_region_update_coalesced_range(mr); | |
093bc2cd | 2293 | } |
093bc2cd AK |
2294 | } |
2295 | ||
d410515e JK |
2296 | void memory_region_set_flush_coalesced(MemoryRegion *mr) |
2297 | { | |
2298 | mr->flush_coalesced_mmio = true; | |
2299 | } | |
2300 | ||
2301 | void memory_region_clear_flush_coalesced(MemoryRegion *mr) | |
2302 | { | |
2303 | qemu_flush_coalesced_mmio_buffer(); | |
2304 | if (QTAILQ_EMPTY(&mr->coalesced)) { | |
2305 | mr->flush_coalesced_mmio = false; | |
2306 | } | |
2307 | } | |
2308 | ||
196ea131 JK |
2309 | void memory_region_clear_global_locking(MemoryRegion *mr) |
2310 | { | |
2311 | mr->global_locking = false; | |
2312 | } | |
2313 | ||
8c56c1a5 PF |
2314 | static bool userspace_eventfd_warning; |
2315 | ||
3e9d69e7 | 2316 | void memory_region_add_eventfd(MemoryRegion *mr, |
a8170e5e | 2317 | hwaddr addr, |
3e9d69e7 AK |
2318 | unsigned size, |
2319 | bool match_data, | |
2320 | uint64_t data, | |
753d5e14 | 2321 | EventNotifier *e) |
3e9d69e7 AK |
2322 | { |
2323 | MemoryRegionIoeventfd mrfd = { | |
08dafab4 AK |
2324 | .addr.start = int128_make64(addr), |
2325 | .addr.size = int128_make64(size), | |
3e9d69e7 AK |
2326 | .match_data = match_data, |
2327 | .data = data, | |
753d5e14 | 2328 | .e = e, |
3e9d69e7 AK |
2329 | }; |
2330 | unsigned i; | |
2331 | ||
8c56c1a5 PF |
2332 | if (kvm_enabled() && (!(kvm_eventfds_enabled() || |
2333 | userspace_eventfd_warning))) { | |
2334 | userspace_eventfd_warning = true; | |
2335 | error_report("Using eventfd without MMIO binding in KVM. " | |
2336 | "Suboptimal performance expected"); | |
2337 | } | |
2338 | ||
b8aecea2 JW |
2339 | if (size) { |
2340 | adjust_endianness(mr, &mrfd.data, size); | |
2341 | } | |
59023ef4 | 2342 | memory_region_transaction_begin(); |
3e9d69e7 | 2343 | for (i = 0; i < mr->ioeventfd_nb; ++i) { |
73bb753d | 2344 | if (memory_region_ioeventfd_before(&mrfd, &mr->ioeventfds[i])) { |
3e9d69e7 AK |
2345 | break; |
2346 | } | |
2347 | } | |
2348 | ++mr->ioeventfd_nb; | |
7267c094 | 2349 | mr->ioeventfds = g_realloc(mr->ioeventfds, |
3e9d69e7 AK |
2350 | sizeof(*mr->ioeventfds) * mr->ioeventfd_nb); |
2351 | memmove(&mr->ioeventfds[i+1], &mr->ioeventfds[i], | |
2352 | sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb-1 - i)); | |
2353 | mr->ioeventfds[i] = mrfd; | |
4dc56152 | 2354 | ioeventfd_update_pending |= mr->enabled; |
59023ef4 | 2355 | memory_region_transaction_commit(); |
3e9d69e7 AK |
2356 | } |
2357 | ||
2358 | void memory_region_del_eventfd(MemoryRegion *mr, | |
a8170e5e | 2359 | hwaddr addr, |
3e9d69e7 AK |
2360 | unsigned size, |
2361 | bool match_data, | |
2362 | uint64_t data, | |
753d5e14 | 2363 | EventNotifier *e) |
3e9d69e7 AK |
2364 | { |
2365 | MemoryRegionIoeventfd mrfd = { | |
08dafab4 AK |
2366 | .addr.start = int128_make64(addr), |
2367 | .addr.size = int128_make64(size), | |
3e9d69e7 AK |
2368 | .match_data = match_data, |
2369 | .data = data, | |
753d5e14 | 2370 | .e = e, |
3e9d69e7 AK |
2371 | }; |
2372 | unsigned i; | |
2373 | ||
b8aecea2 JW |
2374 | if (size) { |
2375 | adjust_endianness(mr, &mrfd.data, size); | |
2376 | } | |
59023ef4 | 2377 | memory_region_transaction_begin(); |
3e9d69e7 | 2378 | for (i = 0; i < mr->ioeventfd_nb; ++i) { |
73bb753d | 2379 | if (memory_region_ioeventfd_equal(&mrfd, &mr->ioeventfds[i])) { |
3e9d69e7 AK |
2380 | break; |
2381 | } | |
2382 | } | |
2383 | assert(i != mr->ioeventfd_nb); | |
2384 | memmove(&mr->ioeventfds[i], &mr->ioeventfds[i+1], | |
2385 | sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb - (i+1))); | |
2386 | --mr->ioeventfd_nb; | |
7267c094 | 2387 | mr->ioeventfds = g_realloc(mr->ioeventfds, |
3e9d69e7 | 2388 | sizeof(*mr->ioeventfds)*mr->ioeventfd_nb + 1); |
4dc56152 | 2389 | ioeventfd_update_pending |= mr->enabled; |
59023ef4 | 2390 | memory_region_transaction_commit(); |
3e9d69e7 AK |
2391 | } |
2392 | ||
feca4ac1 | 2393 | static void memory_region_update_container_subregions(MemoryRegion *subregion) |
093bc2cd | 2394 | { |
feca4ac1 | 2395 | MemoryRegion *mr = subregion->container; |
093bc2cd AK |
2396 | MemoryRegion *other; |
2397 | ||
59023ef4 JK |
2398 | memory_region_transaction_begin(); |
2399 | ||
dfde4e6e | 2400 | memory_region_ref(subregion); |
093bc2cd AK |
2401 | QTAILQ_FOREACH(other, &mr->subregions, subregions_link) { |
2402 | if (subregion->priority >= other->priority) { | |
2403 | QTAILQ_INSERT_BEFORE(other, subregion, subregions_link); | |
2404 | goto done; | |
2405 | } | |
2406 | } | |
2407 | QTAILQ_INSERT_TAIL(&mr->subregions, subregion, subregions_link); | |
2408 | done: | |
22bde714 | 2409 | memory_region_update_pending |= mr->enabled && subregion->enabled; |
59023ef4 | 2410 | memory_region_transaction_commit(); |
093bc2cd AK |
2411 | } |
2412 | ||
0598701a PC |
2413 | static void memory_region_add_subregion_common(MemoryRegion *mr, |
2414 | hwaddr offset, | |
2415 | MemoryRegion *subregion) | |
2416 | { | |
feca4ac1 PB |
2417 | assert(!subregion->container); |
2418 | subregion->container = mr; | |
0598701a | 2419 | subregion->addr = offset; |
feca4ac1 | 2420 | memory_region_update_container_subregions(subregion); |
0598701a | 2421 | } |
093bc2cd AK |
2422 | |
2423 | void memory_region_add_subregion(MemoryRegion *mr, | |
a8170e5e | 2424 | hwaddr offset, |
093bc2cd AK |
2425 | MemoryRegion *subregion) |
2426 | { | |
093bc2cd AK |
2427 | subregion->priority = 0; |
2428 | memory_region_add_subregion_common(mr, offset, subregion); | |
2429 | } | |
2430 | ||
2431 | void memory_region_add_subregion_overlap(MemoryRegion *mr, | |
a8170e5e | 2432 | hwaddr offset, |
093bc2cd | 2433 | MemoryRegion *subregion, |
a1ff8ae0 | 2434 | int priority) |
093bc2cd | 2435 | { |
093bc2cd AK |
2436 | subregion->priority = priority; |
2437 | memory_region_add_subregion_common(mr, offset, subregion); | |
2438 | } | |
2439 | ||
2440 | void memory_region_del_subregion(MemoryRegion *mr, | |
2441 | MemoryRegion *subregion) | |
2442 | { | |
59023ef4 | 2443 | memory_region_transaction_begin(); |
feca4ac1 PB |
2444 | assert(subregion->container == mr); |
2445 | subregion->container = NULL; | |
093bc2cd | 2446 | QTAILQ_REMOVE(&mr->subregions, subregion, subregions_link); |
dfde4e6e | 2447 | memory_region_unref(subregion); |
22bde714 | 2448 | memory_region_update_pending |= mr->enabled && subregion->enabled; |
59023ef4 | 2449 | memory_region_transaction_commit(); |
6bba19ba AK |
2450 | } |
2451 | ||
2452 | void memory_region_set_enabled(MemoryRegion *mr, bool enabled) | |
2453 | { | |
2454 | if (enabled == mr->enabled) { | |
2455 | return; | |
2456 | } | |
59023ef4 | 2457 | memory_region_transaction_begin(); |
6bba19ba | 2458 | mr->enabled = enabled; |
22bde714 | 2459 | memory_region_update_pending = true; |
59023ef4 | 2460 | memory_region_transaction_commit(); |
093bc2cd | 2461 | } |
1c0ffa58 | 2462 | |
e7af4c67 MT |
2463 | void memory_region_set_size(MemoryRegion *mr, uint64_t size) |
2464 | { | |
2465 | Int128 s = int128_make64(size); | |
2466 | ||
2467 | if (size == UINT64_MAX) { | |
2468 | s = int128_2_64(); | |
2469 | } | |
2470 | if (int128_eq(s, mr->size)) { | |
2471 | return; | |
2472 | } | |
2473 | memory_region_transaction_begin(); | |
2474 | mr->size = s; | |
2475 | memory_region_update_pending = true; | |
2476 | memory_region_transaction_commit(); | |
2477 | } | |
2478 | ||
67891b8a | 2479 | static void memory_region_readd_subregion(MemoryRegion *mr) |
2282e1af | 2480 | { |
feca4ac1 | 2481 | MemoryRegion *container = mr->container; |
2282e1af | 2482 | |
feca4ac1 | 2483 | if (container) { |
67891b8a PC |
2484 | memory_region_transaction_begin(); |
2485 | memory_region_ref(mr); | |
feca4ac1 PB |
2486 | memory_region_del_subregion(container, mr); |
2487 | mr->container = container; | |
2488 | memory_region_update_container_subregions(mr); | |
67891b8a PC |
2489 | memory_region_unref(mr); |
2490 | memory_region_transaction_commit(); | |
2282e1af | 2491 | } |
67891b8a | 2492 | } |
2282e1af | 2493 | |
67891b8a PC |
2494 | void memory_region_set_address(MemoryRegion *mr, hwaddr addr) |
2495 | { | |
2496 | if (addr != mr->addr) { | |
2497 | mr->addr = addr; | |
2498 | memory_region_readd_subregion(mr); | |
2499 | } | |
2282e1af AK |
2500 | } |
2501 | ||
a8170e5e | 2502 | void memory_region_set_alias_offset(MemoryRegion *mr, hwaddr offset) |
4703359e | 2503 | { |
4703359e | 2504 | assert(mr->alias); |
4703359e | 2505 | |
59023ef4 | 2506 | if (offset == mr->alias_offset) { |
4703359e AK |
2507 | return; |
2508 | } | |
2509 | ||
59023ef4 JK |
2510 | memory_region_transaction_begin(); |
2511 | mr->alias_offset = offset; | |
22bde714 | 2512 | memory_region_update_pending |= mr->enabled; |
59023ef4 | 2513 | memory_region_transaction_commit(); |
4703359e AK |
2514 | } |
2515 | ||
a2b257d6 IM |
2516 | uint64_t memory_region_get_alignment(const MemoryRegion *mr) |
2517 | { | |
2518 | return mr->align; | |
2519 | } | |
2520 | ||
e2177955 AK |
2521 | static int cmp_flatrange_addr(const void *addr_, const void *fr_) |
2522 | { | |
2523 | const AddrRange *addr = addr_; | |
2524 | const FlatRange *fr = fr_; | |
2525 | ||
2526 | if (int128_le(addrrange_end(*addr), fr->addr.start)) { | |
2527 | return -1; | |
2528 | } else if (int128_ge(addr->start, addrrange_end(fr->addr))) { | |
2529 | return 1; | |
2530 | } | |
2531 | return 0; | |
2532 | } | |
2533 | ||
99e86347 | 2534 | static FlatRange *flatview_lookup(FlatView *view, AddrRange addr) |
e2177955 | 2535 | { |
99e86347 | 2536 | return bsearch(&addr, view->ranges, view->nr, |
e2177955 AK |
2537 | sizeof(FlatRange), cmp_flatrange_addr); |
2538 | } | |
2539 | ||
eed2bacf IM |
2540 | bool memory_region_is_mapped(MemoryRegion *mr) |
2541 | { | |
2542 | return mr->container ? true : false; | |
2543 | } | |
2544 | ||
c6742b14 PB |
2545 | /* Same as memory_region_find, but it does not add a reference to the |
2546 | * returned region. It must be called from an RCU critical section. | |
2547 | */ | |
2548 | static MemoryRegionSection memory_region_find_rcu(MemoryRegion *mr, | |
2549 | hwaddr addr, uint64_t size) | |
e2177955 | 2550 | { |
052e87b0 | 2551 | MemoryRegionSection ret = { .mr = NULL }; |
73034e9e PB |
2552 | MemoryRegion *root; |
2553 | AddressSpace *as; | |
2554 | AddrRange range; | |
99e86347 | 2555 | FlatView *view; |
73034e9e PB |
2556 | FlatRange *fr; |
2557 | ||
2558 | addr += mr->addr; | |
feca4ac1 PB |
2559 | for (root = mr; root->container; ) { |
2560 | root = root->container; | |
73034e9e PB |
2561 | addr += root->addr; |
2562 | } | |
e2177955 | 2563 | |
73034e9e | 2564 | as = memory_region_to_address_space(root); |
eed2bacf IM |
2565 | if (!as) { |
2566 | return ret; | |
2567 | } | |
73034e9e | 2568 | range = addrrange_make(int128_make64(addr), int128_make64(size)); |
99e86347 | 2569 | |
16620684 | 2570 | view = address_space_to_flatview(as); |
99e86347 | 2571 | fr = flatview_lookup(view, range); |
e2177955 | 2572 | if (!fr) { |
c6742b14 | 2573 | return ret; |
e2177955 AK |
2574 | } |
2575 | ||
99e86347 | 2576 | while (fr > view->ranges && addrrange_intersects(fr[-1].addr, range)) { |
e2177955 AK |
2577 | --fr; |
2578 | } | |
2579 | ||
2580 | ret.mr = fr->mr; | |
16620684 | 2581 | ret.fv = view; |
e2177955 AK |
2582 | range = addrrange_intersection(range, fr->addr); |
2583 | ret.offset_within_region = fr->offset_in_region; | |
2584 | ret.offset_within_region += int128_get64(int128_sub(range.start, | |
2585 | fr->addr.start)); | |
052e87b0 | 2586 | ret.size = range.size; |
e2177955 | 2587 | ret.offset_within_address_space = int128_get64(range.start); |
7a8499e8 | 2588 | ret.readonly = fr->readonly; |
c26763f8 | 2589 | ret.nonvolatile = fr->nonvolatile; |
c6742b14 PB |
2590 | return ret; |
2591 | } | |
2592 | ||
2593 | MemoryRegionSection memory_region_find(MemoryRegion *mr, | |
2594 | hwaddr addr, uint64_t size) | |
2595 | { | |
2596 | MemoryRegionSection ret; | |
2597 | rcu_read_lock(); | |
2598 | ret = memory_region_find_rcu(mr, addr, size); | |
2599 | if (ret.mr) { | |
2600 | memory_region_ref(ret.mr); | |
2601 | } | |
2b647668 | 2602 | rcu_read_unlock(); |
e2177955 AK |
2603 | return ret; |
2604 | } | |
2605 | ||
c6742b14 PB |
2606 | bool memory_region_present(MemoryRegion *container, hwaddr addr) |
2607 | { | |
2608 | MemoryRegion *mr; | |
2609 | ||
2610 | rcu_read_lock(); | |
2611 | mr = memory_region_find_rcu(container, addr, 1).mr; | |
2612 | rcu_read_unlock(); | |
2613 | return mr && mr != container; | |
2614 | } | |
2615 | ||
9c1f8f44 | 2616 | void memory_global_dirty_log_sync(void) |
86e775c6 | 2617 | { |
3ebb1817 | 2618 | memory_region_sync_dirty_bitmap(NULL); |
7664e80c AK |
2619 | } |
2620 | ||
19310760 JZ |
2621 | static VMChangeStateEntry *vmstate_change; |
2622 | ||
7664e80c AK |
2623 | void memory_global_dirty_log_start(void) |
2624 | { | |
19310760 JZ |
2625 | if (vmstate_change) { |
2626 | qemu_del_vm_change_state_handler(vmstate_change); | |
2627 | vmstate_change = NULL; | |
2628 | } | |
2629 | ||
7664e80c | 2630 | global_dirty_log = true; |
6f6a5ef3 | 2631 | |
7376e582 | 2632 | MEMORY_LISTENER_CALL_GLOBAL(log_global_start, Forward); |
6f6a5ef3 | 2633 | |
39adb536 | 2634 | /* Refresh DIRTY_MEMORY_MIGRATION bit. */ |
6f6a5ef3 PB |
2635 | memory_region_transaction_begin(); |
2636 | memory_region_update_pending = true; | |
2637 | memory_region_transaction_commit(); | |
7664e80c AK |
2638 | } |
2639 | ||
19310760 | 2640 | static void memory_global_dirty_log_do_stop(void) |
7664e80c | 2641 | { |
7664e80c | 2642 | global_dirty_log = false; |
6f6a5ef3 | 2643 | |
39adb536 | 2644 | /* Refresh DIRTY_MEMORY_MIGRATION bit. */ |
6f6a5ef3 PB |
2645 | memory_region_transaction_begin(); |
2646 | memory_region_update_pending = true; | |
2647 | memory_region_transaction_commit(); | |
2648 | ||
7376e582 | 2649 | MEMORY_LISTENER_CALL_GLOBAL(log_global_stop, Reverse); |
7664e80c AK |
2650 | } |
2651 | ||
19310760 JZ |
2652 | static void memory_vm_change_state_handler(void *opaque, int running, |
2653 | RunState state) | |
2654 | { | |
2655 | if (running) { | |
2656 | memory_global_dirty_log_do_stop(); | |
2657 | ||
2658 | if (vmstate_change) { | |
2659 | qemu_del_vm_change_state_handler(vmstate_change); | |
2660 | vmstate_change = NULL; | |
2661 | } | |
2662 | } | |
2663 | } | |
2664 | ||
2665 | void memory_global_dirty_log_stop(void) | |
2666 | { | |
2667 | if (!runstate_is_running()) { | |
2668 | if (vmstate_change) { | |
2669 | return; | |
2670 | } | |
2671 | vmstate_change = qemu_add_vm_change_state_handler( | |
2672 | memory_vm_change_state_handler, NULL); | |
2673 | return; | |
2674 | } | |
2675 | ||
2676 | memory_global_dirty_log_do_stop(); | |
2677 | } | |
2678 | ||
7664e80c AK |
2679 | static void listener_add_address_space(MemoryListener *listener, |
2680 | AddressSpace *as) | |
2681 | { | |
99e86347 | 2682 | FlatView *view; |
7664e80c AK |
2683 | FlatRange *fr; |
2684 | ||
680a4783 PB |
2685 | if (listener->begin) { |
2686 | listener->begin(listener); | |
2687 | } | |
7664e80c | 2688 | if (global_dirty_log) { |
975aefe0 AK |
2689 | if (listener->log_global_start) { |
2690 | listener->log_global_start(listener); | |
2691 | } | |
7664e80c | 2692 | } |
975aefe0 | 2693 | |
856d7245 | 2694 | view = address_space_get_flatview(as); |
99e86347 | 2695 | FOR_EACH_FLAT_RANGE(fr, view) { |
279836f8 DH |
2696 | MemoryRegionSection section = section_from_flat_range(fr, view); |
2697 | ||
975aefe0 AK |
2698 | if (listener->region_add) { |
2699 | listener->region_add(listener, §ion); | |
2700 | } | |
ae990e6c DH |
2701 | if (fr->dirty_log_mask && listener->log_start) { |
2702 | listener->log_start(listener, §ion, 0, fr->dirty_log_mask); | |
2703 | } | |
7664e80c | 2704 | } |
680a4783 PB |
2705 | if (listener->commit) { |
2706 | listener->commit(listener); | |
2707 | } | |
856d7245 | 2708 | flatview_unref(view); |
7664e80c AK |
2709 | } |
2710 | ||
d25836ca PX |
2711 | static void listener_del_address_space(MemoryListener *listener, |
2712 | AddressSpace *as) | |
2713 | { | |
2714 | FlatView *view; | |
2715 | FlatRange *fr; | |
2716 | ||
2717 | if (listener->begin) { | |
2718 | listener->begin(listener); | |
2719 | } | |
2720 | view = address_space_get_flatview(as); | |
2721 | FOR_EACH_FLAT_RANGE(fr, view) { | |
2722 | MemoryRegionSection section = section_from_flat_range(fr, view); | |
2723 | ||
2724 | if (fr->dirty_log_mask && listener->log_stop) { | |
2725 | listener->log_stop(listener, §ion, fr->dirty_log_mask, 0); | |
2726 | } | |
2727 | if (listener->region_del) { | |
2728 | listener->region_del(listener, §ion); | |
2729 | } | |
2730 | } | |
2731 | if (listener->commit) { | |
2732 | listener->commit(listener); | |
2733 | } | |
2734 | flatview_unref(view); | |
2735 | } | |
2736 | ||
d45fa784 | 2737 | void memory_listener_register(MemoryListener *listener, AddressSpace *as) |
7664e80c | 2738 | { |
72e22d2f AK |
2739 | MemoryListener *other = NULL; |
2740 | ||
d45fa784 | 2741 | listener->address_space = as; |
72e22d2f | 2742 | if (QTAILQ_EMPTY(&memory_listeners) |
eae3eb3e | 2743 | || listener->priority >= QTAILQ_LAST(&memory_listeners)->priority) { |
72e22d2f AK |
2744 | QTAILQ_INSERT_TAIL(&memory_listeners, listener, link); |
2745 | } else { | |
2746 | QTAILQ_FOREACH(other, &memory_listeners, link) { | |
2747 | if (listener->priority < other->priority) { | |
2748 | break; | |
2749 | } | |
2750 | } | |
2751 | QTAILQ_INSERT_BEFORE(other, listener, link); | |
2752 | } | |
0d673e36 | 2753 | |
9a54635d | 2754 | if (QTAILQ_EMPTY(&as->listeners) |
eae3eb3e | 2755 | || listener->priority >= QTAILQ_LAST(&as->listeners)->priority) { |
9a54635d PB |
2756 | QTAILQ_INSERT_TAIL(&as->listeners, listener, link_as); |
2757 | } else { | |
2758 | QTAILQ_FOREACH(other, &as->listeners, link_as) { | |
2759 | if (listener->priority < other->priority) { | |
2760 | break; | |
2761 | } | |
2762 | } | |
2763 | QTAILQ_INSERT_BEFORE(other, listener, link_as); | |
2764 | } | |
2765 | ||
d45fa784 | 2766 | listener_add_address_space(listener, as); |
7664e80c AK |
2767 | } |
2768 | ||
2769 | void memory_listener_unregister(MemoryListener *listener) | |
2770 | { | |
1d8280c1 PB |
2771 | if (!listener->address_space) { |
2772 | return; | |
2773 | } | |
2774 | ||
d25836ca | 2775 | listener_del_address_space(listener, listener->address_space); |
72e22d2f | 2776 | QTAILQ_REMOVE(&memory_listeners, listener, link); |
9a54635d | 2777 | QTAILQ_REMOVE(&listener->address_space->listeners, listener, link_as); |
1d8280c1 | 2778 | listener->address_space = NULL; |
86e775c6 | 2779 | } |
e2177955 | 2780 | |
a2166410 GK |
2781 | void address_space_remove_listeners(AddressSpace *as) |
2782 | { | |
2783 | while (!QTAILQ_EMPTY(&as->listeners)) { | |
2784 | memory_listener_unregister(QTAILQ_FIRST(&as->listeners)); | |
2785 | } | |
2786 | } | |
2787 | ||
7dca8043 | 2788 | void address_space_init(AddressSpace *as, MemoryRegion *root, const char *name) |
1c0ffa58 | 2789 | { |
ac95190e | 2790 | memory_region_ref(root); |
8786db7c | 2791 | as->root = root; |
67ace39b | 2792 | as->current_map = NULL; |
4c19eb72 AK |
2793 | as->ioeventfd_nb = 0; |
2794 | as->ioeventfds = NULL; | |
9a54635d | 2795 | QTAILQ_INIT(&as->listeners); |
0d673e36 | 2796 | QTAILQ_INSERT_TAIL(&address_spaces, as, address_spaces_link); |
7dca8043 | 2797 | as->name = g_strdup(name ? name : "anonymous"); |
202fc01b AK |
2798 | address_space_update_topology(as); |
2799 | address_space_update_ioeventfds(as); | |
1c0ffa58 | 2800 | } |
658b2224 | 2801 | |
374f2981 | 2802 | static void do_address_space_destroy(AddressSpace *as) |
83f3c251 | 2803 | { |
9a54635d | 2804 | assert(QTAILQ_EMPTY(&as->listeners)); |
078c44f4 | 2805 | |
856d7245 | 2806 | flatview_unref(as->current_map); |
7dca8043 | 2807 | g_free(as->name); |
4c19eb72 | 2808 | g_free(as->ioeventfds); |
ac95190e | 2809 | memory_region_unref(as->root); |
83f3c251 AK |
2810 | } |
2811 | ||
374f2981 PB |
2812 | void address_space_destroy(AddressSpace *as) |
2813 | { | |
ac95190e PB |
2814 | MemoryRegion *root = as->root; |
2815 | ||
374f2981 PB |
2816 | /* Flush out anything from MemoryListeners listening in on this */ |
2817 | memory_region_transaction_begin(); | |
2818 | as->root = NULL; | |
2819 | memory_region_transaction_commit(); | |
2820 | QTAILQ_REMOVE(&address_spaces, as, address_spaces_link); | |
2821 | ||
2822 | /* At this point, as->dispatch and as->current_map are dummy | |
2823 | * entries that the guest should never use. Wait for the old | |
2824 | * values to expire before freeing the data. | |
2825 | */ | |
ac95190e | 2826 | as->root = root; |
374f2981 PB |
2827 | call_rcu(as, do_address_space_destroy, rcu); |
2828 | } | |
2829 | ||
4e831901 PX |
2830 | static const char *memory_region_type(MemoryRegion *mr) |
2831 | { | |
2832 | if (memory_region_is_ram_device(mr)) { | |
2833 | return "ramd"; | |
2834 | } else if (memory_region_is_romd(mr)) { | |
2835 | return "romd"; | |
2836 | } else if (memory_region_is_rom(mr)) { | |
2837 | return "rom"; | |
2838 | } else if (memory_region_is_ram(mr)) { | |
2839 | return "ram"; | |
2840 | } else { | |
2841 | return "i/o"; | |
2842 | } | |
2843 | } | |
2844 | ||
314e2987 BS |
2845 | typedef struct MemoryRegionList MemoryRegionList; |
2846 | ||
2847 | struct MemoryRegionList { | |
2848 | const MemoryRegion *mr; | |
a16878d2 | 2849 | QTAILQ_ENTRY(MemoryRegionList) mrqueue; |
314e2987 BS |
2850 | }; |
2851 | ||
b58deb34 | 2852 | typedef QTAILQ_HEAD(, MemoryRegionList) MemoryRegionListHead; |
314e2987 | 2853 | |
4e831901 PX |
2854 | #define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \ |
2855 | int128_sub((size), int128_one())) : 0) | |
2856 | #define MTREE_INDENT " " | |
2857 | ||
b6b71cb5 | 2858 | static void mtree_expand_owner(const char *label, Object *obj) |
fc051ae6 AK |
2859 | { |
2860 | DeviceState *dev = (DeviceState *) object_dynamic_cast(obj, TYPE_DEVICE); | |
2861 | ||
b6b71cb5 | 2862 | qemu_printf(" %s:{%s", label, dev ? "dev" : "obj"); |
fc051ae6 | 2863 | if (dev && dev->id) { |
b6b71cb5 | 2864 | qemu_printf(" id=%s", dev->id); |
fc051ae6 AK |
2865 | } else { |
2866 | gchar *canonical_path = object_get_canonical_path(obj); | |
2867 | if (canonical_path) { | |
b6b71cb5 | 2868 | qemu_printf(" path=%s", canonical_path); |
fc051ae6 AK |
2869 | g_free(canonical_path); |
2870 | } else { | |
b6b71cb5 | 2871 | qemu_printf(" type=%s", object_get_typename(obj)); |
fc051ae6 AK |
2872 | } |
2873 | } | |
b6b71cb5 | 2874 | qemu_printf("}"); |
fc051ae6 AK |
2875 | } |
2876 | ||
b6b71cb5 | 2877 | static void mtree_print_mr_owner(const MemoryRegion *mr) |
fc051ae6 AK |
2878 | { |
2879 | Object *owner = mr->owner; | |
2880 | Object *parent = memory_region_owner((MemoryRegion *)mr); | |
2881 | ||
2882 | if (!owner && !parent) { | |
b6b71cb5 | 2883 | qemu_printf(" orphan"); |
fc051ae6 AK |
2884 | return; |
2885 | } | |
2886 | if (owner) { | |
b6b71cb5 | 2887 | mtree_expand_owner("owner", owner); |
fc051ae6 AK |
2888 | } |
2889 | if (parent && parent != owner) { | |
b6b71cb5 | 2890 | mtree_expand_owner("parent", parent); |
fc051ae6 AK |
2891 | } |
2892 | } | |
2893 | ||
b6b71cb5 | 2894 | static void mtree_print_mr(const MemoryRegion *mr, unsigned int level, |
a8170e5e | 2895 | hwaddr base, |
fc051ae6 AK |
2896 | MemoryRegionListHead *alias_print_queue, |
2897 | bool owner) | |
314e2987 | 2898 | { |
9479c57a JK |
2899 | MemoryRegionList *new_ml, *ml, *next_ml; |
2900 | MemoryRegionListHead submr_print_queue; | |
314e2987 BS |
2901 | const MemoryRegion *submr; |
2902 | unsigned int i; | |
b31f8412 | 2903 | hwaddr cur_start, cur_end; |
314e2987 | 2904 | |
f8a9f720 | 2905 | if (!mr) { |
314e2987 BS |
2906 | return; |
2907 | } | |
2908 | ||
2909 | for (i = 0; i < level; i++) { | |
b6b71cb5 | 2910 | qemu_printf(MTREE_INDENT); |
314e2987 BS |
2911 | } |
2912 | ||
b31f8412 PX |
2913 | cur_start = base + mr->addr; |
2914 | cur_end = cur_start + MR_SIZE(mr->size); | |
2915 | ||
2916 | /* | |
2917 | * Try to detect overflow of memory region. This should never | |
2918 | * happen normally. When it happens, we dump something to warn the | |
2919 | * user who is observing this. | |
2920 | */ | |
2921 | if (cur_start < base || cur_end < cur_start) { | |
b6b71cb5 | 2922 | qemu_printf("[DETECTED OVERFLOW!] "); |
b31f8412 PX |
2923 | } |
2924 | ||
314e2987 BS |
2925 | if (mr->alias) { |
2926 | MemoryRegionList *ml; | |
2927 | bool found = false; | |
2928 | ||
2929 | /* check if the alias is already in the queue */ | |
a16878d2 | 2930 | QTAILQ_FOREACH(ml, alias_print_queue, mrqueue) { |
f54bb15f | 2931 | if (ml->mr == mr->alias) { |
314e2987 BS |
2932 | found = true; |
2933 | } | |
2934 | } | |
2935 | ||
2936 | if (!found) { | |
2937 | ml = g_new(MemoryRegionList, 1); | |
2938 | ml->mr = mr->alias; | |
a16878d2 | 2939 | QTAILQ_INSERT_TAIL(alias_print_queue, ml, mrqueue); |
314e2987 | 2940 | } |
b6b71cb5 MA |
2941 | qemu_printf(TARGET_FMT_plx "-" TARGET_FMT_plx |
2942 | " (prio %d, %s%s): alias %s @%s " TARGET_FMT_plx | |
2943 | "-" TARGET_FMT_plx "%s", | |
2944 | cur_start, cur_end, | |
2945 | mr->priority, | |
2946 | mr->nonvolatile ? "nv-" : "", | |
2947 | memory_region_type((MemoryRegion *)mr), | |
2948 | memory_region_name(mr), | |
2949 | memory_region_name(mr->alias), | |
2950 | mr->alias_offset, | |
2951 | mr->alias_offset + MR_SIZE(mr->size), | |
2952 | mr->enabled ? "" : " [disabled]"); | |
fc051ae6 | 2953 | if (owner) { |
b6b71cb5 | 2954 | mtree_print_mr_owner(mr); |
fc051ae6 | 2955 | } |
314e2987 | 2956 | } else { |
b6b71cb5 MA |
2957 | qemu_printf(TARGET_FMT_plx "-" TARGET_FMT_plx |
2958 | " (prio %d, %s%s): %s%s", | |
2959 | cur_start, cur_end, | |
2960 | mr->priority, | |
2961 | mr->nonvolatile ? "nv-" : "", | |
2962 | memory_region_type((MemoryRegion *)mr), | |
2963 | memory_region_name(mr), | |
2964 | mr->enabled ? "" : " [disabled]"); | |
fc051ae6 | 2965 | if (owner) { |
b6b71cb5 | 2966 | mtree_print_mr_owner(mr); |
fc051ae6 | 2967 | } |
314e2987 | 2968 | } |
b6b71cb5 | 2969 | qemu_printf("\n"); |
9479c57a JK |
2970 | |
2971 | QTAILQ_INIT(&submr_print_queue); | |
2972 | ||
314e2987 | 2973 | QTAILQ_FOREACH(submr, &mr->subregions, subregions_link) { |
9479c57a JK |
2974 | new_ml = g_new(MemoryRegionList, 1); |
2975 | new_ml->mr = submr; | |
a16878d2 | 2976 | QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) { |
9479c57a JK |
2977 | if (new_ml->mr->addr < ml->mr->addr || |
2978 | (new_ml->mr->addr == ml->mr->addr && | |
2979 | new_ml->mr->priority > ml->mr->priority)) { | |
a16878d2 | 2980 | QTAILQ_INSERT_BEFORE(ml, new_ml, mrqueue); |
9479c57a JK |
2981 | new_ml = NULL; |
2982 | break; | |
2983 | } | |
2984 | } | |
2985 | if (new_ml) { | |
a16878d2 | 2986 | QTAILQ_INSERT_TAIL(&submr_print_queue, new_ml, mrqueue); |
9479c57a JK |
2987 | } |
2988 | } | |
2989 | ||
a16878d2 | 2990 | QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) { |
b6b71cb5 | 2991 | mtree_print_mr(ml->mr, level + 1, cur_start, |
fc051ae6 | 2992 | alias_print_queue, owner); |
9479c57a JK |
2993 | } |
2994 | ||
a16878d2 | 2995 | QTAILQ_FOREACH_SAFE(ml, &submr_print_queue, mrqueue, next_ml) { |
9479c57a | 2996 | g_free(ml); |
314e2987 BS |
2997 | } |
2998 | } | |
2999 | ||
5e8fd947 | 3000 | struct FlatViewInfo { |
5e8fd947 AK |
3001 | int counter; |
3002 | bool dispatch_tree; | |
fc051ae6 | 3003 | bool owner; |
8072aae3 AK |
3004 | AccelClass *ac; |
3005 | const char *ac_name; | |
5e8fd947 AK |
3006 | }; |
3007 | ||
3008 | static void mtree_print_flatview(gpointer key, gpointer value, | |
3009 | gpointer user_data) | |
57bb40c9 | 3010 | { |
5e8fd947 AK |
3011 | FlatView *view = key; |
3012 | GArray *fv_address_spaces = value; | |
3013 | struct FlatViewInfo *fvi = user_data; | |
57bb40c9 PX |
3014 | FlatRange *range = &view->ranges[0]; |
3015 | MemoryRegion *mr; | |
3016 | int n = view->nr; | |
5e8fd947 AK |
3017 | int i; |
3018 | AddressSpace *as; | |
3019 | ||
b6b71cb5 | 3020 | qemu_printf("FlatView #%d\n", fvi->counter); |
5e8fd947 AK |
3021 | ++fvi->counter; |
3022 | ||
3023 | for (i = 0; i < fv_address_spaces->len; ++i) { | |
3024 | as = g_array_index(fv_address_spaces, AddressSpace*, i); | |
b6b71cb5 MA |
3025 | qemu_printf(" AS \"%s\", root: %s", |
3026 | as->name, memory_region_name(as->root)); | |
5e8fd947 | 3027 | if (as->root->alias) { |
b6b71cb5 | 3028 | qemu_printf(", alias %s", memory_region_name(as->root->alias)); |
5e8fd947 | 3029 | } |
b6b71cb5 | 3030 | qemu_printf("\n"); |
5e8fd947 AK |
3031 | } |
3032 | ||
b6b71cb5 | 3033 | qemu_printf(" Root memory region: %s\n", |
5e8fd947 | 3034 | view->root ? memory_region_name(view->root) : "(none)"); |
57bb40c9 PX |
3035 | |
3036 | if (n <= 0) { | |
b6b71cb5 | 3037 | qemu_printf(MTREE_INDENT "No rendered FlatView\n\n"); |
57bb40c9 PX |
3038 | return; |
3039 | } | |
3040 | ||
3041 | while (n--) { | |
3042 | mr = range->mr; | |
377a07aa | 3043 | if (range->offset_in_region) { |
b6b71cb5 MA |
3044 | qemu_printf(MTREE_INDENT TARGET_FMT_plx "-" TARGET_FMT_plx |
3045 | " (prio %d, %s%s): %s @" TARGET_FMT_plx, | |
3046 | int128_get64(range->addr.start), | |
3047 | int128_get64(range->addr.start) | |
3048 | + MR_SIZE(range->addr.size), | |
3049 | mr->priority, | |
3050 | range->nonvolatile ? "nv-" : "", | |
3051 | range->readonly ? "rom" : memory_region_type(mr), | |
3052 | memory_region_name(mr), | |
3053 | range->offset_in_region); | |
377a07aa | 3054 | } else { |
b6b71cb5 MA |
3055 | qemu_printf(MTREE_INDENT TARGET_FMT_plx "-" TARGET_FMT_plx |
3056 | " (prio %d, %s%s): %s", | |
3057 | int128_get64(range->addr.start), | |
3058 | int128_get64(range->addr.start) | |
3059 | + MR_SIZE(range->addr.size), | |
3060 | mr->priority, | |
3061 | range->nonvolatile ? "nv-" : "", | |
3062 | range->readonly ? "rom" : memory_region_type(mr), | |
3063 | memory_region_name(mr)); | |
377a07aa | 3064 | } |
fc051ae6 | 3065 | if (fvi->owner) { |
b6b71cb5 | 3066 | mtree_print_mr_owner(mr); |
fc051ae6 | 3067 | } |
8072aae3 AK |
3068 | |
3069 | if (fvi->ac) { | |
3070 | for (i = 0; i < fv_address_spaces->len; ++i) { | |
3071 | as = g_array_index(fv_address_spaces, AddressSpace*, i); | |
3072 | if (fvi->ac->has_memory(current_machine, as, | |
3073 | int128_get64(range->addr.start), | |
3074 | MR_SIZE(range->addr.size) + 1)) { | |
3075 | qemu_printf(" %s", fvi->ac_name); | |
3076 | } | |
3077 | } | |
3078 | } | |
b6b71cb5 | 3079 | qemu_printf("\n"); |
57bb40c9 PX |
3080 | range++; |
3081 | } | |
3082 | ||
5e8fd947 AK |
3083 | #if !defined(CONFIG_USER_ONLY) |
3084 | if (fvi->dispatch_tree && view->root) { | |
b6b71cb5 | 3085 | mtree_print_dispatch(view->dispatch, view->root); |
5e8fd947 AK |
3086 | } |
3087 | #endif | |
3088 | ||
b6b71cb5 | 3089 | qemu_printf("\n"); |
5e8fd947 AK |
3090 | } |
3091 | ||
3092 | static gboolean mtree_info_flatview_free(gpointer key, gpointer value, | |
3093 | gpointer user_data) | |
3094 | { | |
3095 | FlatView *view = key; | |
3096 | GArray *fv_address_spaces = value; | |
3097 | ||
3098 | g_array_unref(fv_address_spaces); | |
57bb40c9 | 3099 | flatview_unref(view); |
5e8fd947 AK |
3100 | |
3101 | return true; | |
57bb40c9 PX |
3102 | } |
3103 | ||
b6b71cb5 | 3104 | void mtree_info(bool flatview, bool dispatch_tree, bool owner) |
314e2987 BS |
3105 | { |
3106 | MemoryRegionListHead ml_head; | |
3107 | MemoryRegionList *ml, *ml2; | |
0d673e36 | 3108 | AddressSpace *as; |
314e2987 | 3109 | |
57bb40c9 | 3110 | if (flatview) { |
5e8fd947 AK |
3111 | FlatView *view; |
3112 | struct FlatViewInfo fvi = { | |
5e8fd947 | 3113 | .counter = 0, |
fc051ae6 AK |
3114 | .dispatch_tree = dispatch_tree, |
3115 | .owner = owner, | |
5e8fd947 AK |
3116 | }; |
3117 | GArray *fv_address_spaces; | |
3118 | GHashTable *views = g_hash_table_new(g_direct_hash, g_direct_equal); | |
8072aae3 AK |
3119 | AccelClass *ac = ACCEL_GET_CLASS(current_machine->accelerator); |
3120 | ||
3121 | if (ac->has_memory) { | |
3122 | fvi.ac = ac; | |
3123 | fvi.ac_name = current_machine->accel ? current_machine->accel : | |
3124 | object_class_get_name(OBJECT_CLASS(ac)); | |
3125 | } | |
5e8fd947 AK |
3126 | |
3127 | /* Gather all FVs in one table */ | |
57bb40c9 | 3128 | QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) { |
5e8fd947 AK |
3129 | view = address_space_get_flatview(as); |
3130 | ||
3131 | fv_address_spaces = g_hash_table_lookup(views, view); | |
3132 | if (!fv_address_spaces) { | |
3133 | fv_address_spaces = g_array_new(false, false, sizeof(as)); | |
3134 | g_hash_table_insert(views, view, fv_address_spaces); | |
3135 | } | |
3136 | ||
3137 | g_array_append_val(fv_address_spaces, as); | |
57bb40c9 | 3138 | } |
5e8fd947 AK |
3139 | |
3140 | /* Print */ | |
3141 | g_hash_table_foreach(views, mtree_print_flatview, &fvi); | |
3142 | ||
3143 | /* Free */ | |
3144 | g_hash_table_foreach_remove(views, mtree_info_flatview_free, 0); | |
3145 | g_hash_table_unref(views); | |
3146 | ||
57bb40c9 PX |
3147 | return; |
3148 | } | |
3149 | ||
314e2987 BS |
3150 | QTAILQ_INIT(&ml_head); |
3151 | ||
0d673e36 | 3152 | QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) { |
b6b71cb5 MA |
3153 | qemu_printf("address-space: %s\n", as->name); |
3154 | mtree_print_mr(as->root, 1, 0, &ml_head, owner); | |
3155 | qemu_printf("\n"); | |
b9f9be88 BS |
3156 | } |
3157 | ||
314e2987 | 3158 | /* print aliased regions */ |
a16878d2 | 3159 | QTAILQ_FOREACH(ml, &ml_head, mrqueue) { |
b6b71cb5 MA |
3160 | qemu_printf("memory-region: %s\n", memory_region_name(ml->mr)); |
3161 | mtree_print_mr(ml->mr, 1, 0, &ml_head, owner); | |
3162 | qemu_printf("\n"); | |
314e2987 BS |
3163 | } |
3164 | ||
a16878d2 | 3165 | QTAILQ_FOREACH_SAFE(ml, &ml_head, mrqueue, ml2) { |
88365e47 | 3166 | g_free(ml); |
314e2987 | 3167 | } |
314e2987 | 3168 | } |
b4fefef9 | 3169 | |
b08199c6 PM |
3170 | void memory_region_init_ram(MemoryRegion *mr, |
3171 | struct Object *owner, | |
3172 | const char *name, | |
3173 | uint64_t size, | |
3174 | Error **errp) | |
3175 | { | |
3176 | DeviceState *owner_dev; | |
3177 | Error *err = NULL; | |
3178 | ||
3179 | memory_region_init_ram_nomigrate(mr, owner, name, size, &err); | |
3180 | if (err) { | |
3181 | error_propagate(errp, err); | |
3182 | return; | |
3183 | } | |
3184 | /* This will assert if owner is neither NULL nor a DeviceState. | |
3185 | * We only want the owner here for the purposes of defining a | |
3186 | * unique name for migration. TODO: Ideally we should implement | |
3187 | * a naming scheme for Objects which are not DeviceStates, in | |
3188 | * which case we can relax this restriction. | |
3189 | */ | |
3190 | owner_dev = DEVICE(owner); | |
3191 | vmstate_register_ram(mr, owner_dev); | |
3192 | } | |
3193 | ||
3194 | void memory_region_init_rom(MemoryRegion *mr, | |
3195 | struct Object *owner, | |
3196 | const char *name, | |
3197 | uint64_t size, | |
3198 | Error **errp) | |
3199 | { | |
3200 | DeviceState *owner_dev; | |
3201 | Error *err = NULL; | |
3202 | ||
3203 | memory_region_init_rom_nomigrate(mr, owner, name, size, &err); | |
3204 | if (err) { | |
3205 | error_propagate(errp, err); | |
3206 | return; | |
3207 | } | |
3208 | /* This will assert if owner is neither NULL nor a DeviceState. | |
3209 | * We only want the owner here for the purposes of defining a | |
3210 | * unique name for migration. TODO: Ideally we should implement | |
3211 | * a naming scheme for Objects which are not DeviceStates, in | |
3212 | * which case we can relax this restriction. | |
3213 | */ | |
3214 | owner_dev = DEVICE(owner); | |
3215 | vmstate_register_ram(mr, owner_dev); | |
3216 | } | |
3217 | ||
3218 | void memory_region_init_rom_device(MemoryRegion *mr, | |
3219 | struct Object *owner, | |
3220 | const MemoryRegionOps *ops, | |
3221 | void *opaque, | |
3222 | const char *name, | |
3223 | uint64_t size, | |
3224 | Error **errp) | |
3225 | { | |
3226 | DeviceState *owner_dev; | |
3227 | Error *err = NULL; | |
3228 | ||
3229 | memory_region_init_rom_device_nomigrate(mr, owner, ops, opaque, | |
3230 | name, size, &err); | |
3231 | if (err) { | |
3232 | error_propagate(errp, err); | |
3233 | return; | |
3234 | } | |
3235 | /* This will assert if owner is neither NULL nor a DeviceState. | |
3236 | * We only want the owner here for the purposes of defining a | |
3237 | * unique name for migration. TODO: Ideally we should implement | |
3238 | * a naming scheme for Objects which are not DeviceStates, in | |
3239 | * which case we can relax this restriction. | |
3240 | */ | |
3241 | owner_dev = DEVICE(owner); | |
3242 | vmstate_register_ram(mr, owner_dev); | |
3243 | } | |
3244 | ||
b4fefef9 PC |
3245 | static const TypeInfo memory_region_info = { |
3246 | .parent = TYPE_OBJECT, | |
3247 | .name = TYPE_MEMORY_REGION, | |
1b53ecd9 | 3248 | .class_size = sizeof(MemoryRegionClass), |
b4fefef9 PC |
3249 | .instance_size = sizeof(MemoryRegion), |
3250 | .instance_init = memory_region_initfn, | |
3251 | .instance_finalize = memory_region_finalize, | |
3252 | }; | |
3253 | ||
3df9d748 AK |
3254 | static const TypeInfo iommu_memory_region_info = { |
3255 | .parent = TYPE_MEMORY_REGION, | |
3256 | .name = TYPE_IOMMU_MEMORY_REGION, | |
1221a474 | 3257 | .class_size = sizeof(IOMMUMemoryRegionClass), |
3df9d748 AK |
3258 | .instance_size = sizeof(IOMMUMemoryRegion), |
3259 | .instance_init = iommu_memory_region_initfn, | |
1221a474 | 3260 | .abstract = true, |
3df9d748 AK |
3261 | }; |
3262 | ||
b4fefef9 PC |
3263 | static void memory_register_types(void) |
3264 | { | |
3265 | type_register_static(&memory_region_info); | |
3df9d748 | 3266 | type_register_static(&iommu_memory_region_info); |
b4fefef9 PC |
3267 | } |
3268 | ||
3269 | type_init(memory_register_types) |